[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / hisilicon / hns_mdio.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/acpi.h>
#include <linux/errno.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define MDIO_DRV_NAME "Hi-HNS_MDIO"
#define MDIO_BUS_NAME "Hisilicon MII Bus"

#define MDIO_TIMEOUT			1000000

struct hns_mdio_sc_reg {
	u16 mdio_clk_en;
	u16 mdio_clk_dis;
	u16 mdio_reset_req;
	u16 mdio_reset_dreq;
	u16 mdio_clk_st;
	u16 mdio_reset_st;
};

struct hns_mdio_device {
	void *vbase;		/* mdio reg base address */
	struct regmap *subctrl_vbase;
	struct hns_mdio_sc_reg sc_reg;
};

/* mdio reg */
#define MDIO_COMMAND_REG		0x0
#define MDIO_ADDR_REG			0x4
#define MDIO_WDATA_REG			0x8
#define MDIO_RDATA_REG			0xc
#define MDIO_STA_REG			0x10

/* cfg phy bit map */
#define MDIO_CMD_DEVAD_M	0x1f
#define MDIO_CMD_DEVAD_S	0
#define MDIO_CMD_PRTAD_M	0x1f
#define MDIO_CMD_PRTAD_S	5
#define MDIO_CMD_OP_S		10
#define MDIO_CMD_ST_S		12
#define MDIO_CMD_START_B	14

#define MDIO_ADDR_DATA_M	0xffff
#define MDIO_ADDR_DATA_S	0

#define MDIO_WDATA_DATA_M	0xffff
#define MDIO_WDATA_DATA_S	0

#define MDIO_RDATA_DATA_M	0xffff
#define MDIO_RDATA_DATA_S	0

#define MDIO_STATE_STA_B	0

enum mdio_st_clause {
	MDIO_ST_CLAUSE_45 = 0,
	MDIO_ST_CLAUSE_22
};

enum mdio_c22_op_seq {
	MDIO_C22_WRITE = 1,
	MDIO_C22_READ = 2
};

enum mdio_c45_op_seq {
	MDIO_C45_WRITE_ADDR = 0,
	MDIO_C45_WRITE_DATA,
	MDIO_C45_READ_INCREMENT,
	MDIO_C45_READ
};

/* peri subctrl reg */
#define MDIO_SC_CLK_EN		0x338
#define MDIO_SC_CLK_DIS		0x33C
#define MDIO_SC_RESET_REQ	0xA38
#define MDIO_SC_RESET_DREQ	0xA3C
#define MDIO_SC_CLK_ST		0x531C
#define MDIO_SC_RESET_ST	0x5A1C

static void mdio_write_reg(void *base, u32 reg, u32 value)
{
	u8 __iomem *reg_addr = (u8 __iomem *)base;

	writel_relaxed(value, reg_addr + reg);
}

#define MDIO_WRITE_REG(a, reg, value) \
	mdio_write_reg((a)->vbase, (reg), (value))

static u32 mdio_read_reg(void *base, u32 reg)
{
	u8 __iomem *reg_addr = (u8 __iomem *)base;

	return readl_relaxed(reg_addr + reg);
}

#define mdio_set_field(origin, mask, shift, val) \
	do { \
		(origin) &= (~((mask) << (shift))); \
		(origin) |= (((val) & (mask)) << (shift)); \
	} while (0)

#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))

static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
			       u32 val)
{
	u32 origin = mdio_read_reg(base, reg);

	mdio_set_field(origin, mask, shift, val);
	mdio_write_reg(base, reg, origin);
}

#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))

static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
{
	u32 origin;

	origin = mdio_read_reg(base, reg);
	return mdio_get_field(origin, mask, shift);
}

#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
		mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))

#define MDIO_GET_REG_BIT(dev, reg, bit) \
		mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))

#define MDIO_CHECK_SET_ST	1
#define MDIO_CHECK_CLR_ST	0

static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
				 u32 cfg_reg, u32 set_val,
				 u32 st_reg, u32 st_msk, u8 check_st)
{
	u32 time_cnt;
	u32 reg_value;

	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);

	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
		regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
		reg_value &= st_msk;
		if ((!!check_st) == (!!reg_value))
			break;
	}

	if ((!!check_st) != (!!reg_value))
		return -EBUSY;

	return 0;
}

static int hns_mdio_wait_ready(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = bus->priv;
	int i;
	u32 cmd_reg_value = 1;

	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	/* after that can do read or write*/
	for (i = 0; cmd_reg_value; i++) {
		cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
						 MDIO_COMMAND_REG,
						 MDIO_CMD_START_B);
		if (i == MDIO_TIMEOUT)
			return -ETIMEDOUT;
	}

	return 0;
}

static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
			       u8 is_c45, u8 op, u8 phy_id, u16 cmd)
{
	u32 cmd_reg_value;
	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;

	cmd_reg_value = st << MDIO_CMD_ST_S;
	cmd_reg_value |= op << MDIO_CMD_OP_S;
	cmd_reg_value |=
		(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	cmd_reg_value |= 1 << MDIO_CMD_START_B;

	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
}

/**
 * hns_mdio_write - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_write(struct mii_bus *bus,
			  int phy_id, int regnum, u16 data)
{
	int ret;
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	u8 op;
	u16 cmd_reg_cfg;

	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
		phy_id, is_c45, devad, reg, data);

	/* wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		cmd_reg_cfg = reg;
		op = MDIO_C22_WRITE;
	} else {
		/* config the cmd-reg to write addr*/
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		/* config the data needed writing */
		cmd_reg_cfg = devad;
		op = MDIO_C45_WRITE_ADDR;
	}

	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
			   MDIO_WDATA_DATA_S, data);

	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);

	return 0;
}

/**
 * hns_mdio_read - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return phy register value
 */
static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
{
	int ret;
	u16 reg_val = 0;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;

	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
		phy_id, is_c45, devad, reg);

	/* Step 1: wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C22_READ, phy_id, reg);
	} else {
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		/* Step 2; config the cmd-reg to write addr*/
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* Step 3: check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);
	}

	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
	/* check for read or write opt is finished */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
	if (reg_val) {
		dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
		return -EBUSY;
	}

	/* Step 6; get out data*/
	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
					  MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);

	return reg_val;
}

/**
 * hns_mdio_reset - reset mdio bus
 * @bus: mdio bus
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_reset(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	const struct hns_mdio_sc_reg *sc_reg;
	int ret;

	if (dev_of_node(bus->parent)) {
		if (!mdio_dev->subctrl_vbase) {
			dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
			return -ENODEV;
		}

		sc_reg = &mdio_dev->sc_reg;
		/* 1. reset req, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
					    0x1, sc_reg->mdio_reset_st, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO reset fail\n");
			return ret;
		}

		/* 2. dis clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
					    0x1, sc_reg->mdio_clk_st, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 3. reset dreq, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
					    0x1, sc_reg->mdio_reset_st, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 4. en clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
					    0x1, sc_reg->mdio_clk_st, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret)
			dev_err(&bus->dev, "MDIO en clk fail\n");
	} else if (is_acpi_node(bus->parent->fwnode)) {
		acpi_status s;

		s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
					 "_RST", NULL, NULL);
		if (ACPI_FAILURE(s)) {
			dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
			ret = -EBUSY;
		} else {
			ret = 0;
		}
	} else {
		dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}
	return ret;
}

/**
 * hns_mdio_probe - probe mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_probe(struct platform_device *pdev)
{
	struct hns_mdio_device *mdio_dev;
	struct mii_bus *new_bus;
	struct resource *res;
	int ret = -ENODEV;

	if (!pdev) {
		dev_err(NULL, "pdev is NULL!\r\n");
		return -ENODEV;
	}

	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	if (!mdio_dev)
		return -ENOMEM;

	new_bus = devm_mdiobus_alloc(&pdev->dev);
	if (!new_bus) {
		dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
		return -ENOMEM;
	}

	new_bus->name = MDIO_BUS_NAME;
	new_bus->read = hns_mdio_read;
	new_bus->write = hns_mdio_write;
	new_bus->reset = hns_mdio_reset;
	new_bus->priv = mdio_dev;
	new_bus->parent = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mdio_dev->vbase)) {
		ret = PTR_ERR(mdio_dev->vbase);
		return ret;
	}

	platform_set_drvdata(pdev, new_bus);
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
		 dev_name(&pdev->dev));
	if (dev_of_node(&pdev->dev)) {
		struct of_phandle_args reg_args;

		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
						       "subctrl-vbase",
						       4,
						       0,
						       &reg_args);
		if (!ret) {
			mdio_dev->subctrl_vbase =
				syscon_node_to_regmap(reg_args.np);
			if (IS_ERR(mdio_dev->subctrl_vbase)) {
				dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
				mdio_dev->subctrl_vbase = NULL;
			} else {
				if (reg_args.args_count == 4) {
					mdio_dev->sc_reg.mdio_clk_en =
						(u16)reg_args.args[0];
					mdio_dev->sc_reg.mdio_clk_dis =
						(u16)reg_args.args[0] + 4;
					mdio_dev->sc_reg.mdio_reset_req =
						(u16)reg_args.args[1];
					mdio_dev->sc_reg.mdio_reset_dreq =
						(u16)reg_args.args[1] + 4;
					mdio_dev->sc_reg.mdio_clk_st =
						(u16)reg_args.args[2];
					mdio_dev->sc_reg.mdio_reset_st =
						(u16)reg_args.args[3];
				} else {
					/* for compatible */
					mdio_dev->sc_reg.mdio_clk_en =
						MDIO_SC_CLK_EN;
					mdio_dev->sc_reg.mdio_clk_dis =
						MDIO_SC_CLK_DIS;
					mdio_dev->sc_reg.mdio_reset_req =
						MDIO_SC_RESET_REQ;
					mdio_dev->sc_reg.mdio_reset_dreq =
						MDIO_SC_RESET_DREQ;
					mdio_dev->sc_reg.mdio_clk_st =
						MDIO_SC_CLK_ST;
					mdio_dev->sc_reg.mdio_reset_st =
						MDIO_SC_RESET_ST;
				}
			}
		} else {
			dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
			mdio_dev->subctrl_vbase = NULL;
		}

		ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
	} else if (is_acpi_node(pdev->dev.fwnode)) {
		/* Clear all the IRQ properties */
		memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);

		/* Mask out all PHYs from auto probing. */
		new_bus->phy_mask = ~0;

		/* Register the MDIO bus */
		ret = mdiobus_register(new_bus);
	} else {
		dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}

	if (ret) {
		dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
		platform_set_drvdata(pdev, NULL);
		return ret;
	}

	return 0;
}

/**
 * hns_mdio_remove - remove mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_remove(struct platform_device *pdev)
{
	struct mii_bus *bus;

	bus = platform_get_drvdata(pdev);

	mdiobus_unregister(bus);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

static const struct of_device_id hns_mdio_match[] = {
	{.compatible = "hisilicon,mdio"},
	{.compatible = "hisilicon,hns-mdio"},
	{}
};
MODULE_DEVICE_TABLE(of, hns_mdio_match);

static const struct acpi_device_id hns_mdio_acpi_match[] = {
	{ "HISI0141", 0 },
	{ },
};
MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);

static struct platform_driver hns_mdio_driver = {
	.probe = hns_mdio_probe,
	.remove = hns_mdio_remove,
	.driver = {
		   .name = MDIO_DRV_NAME,
		   .of_match_table = hns_mdio_match,
		   .acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
		   },
};

module_platform_driver(hns_mdio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
MODULE_ALIAS("platform:" MDIO_DRV_NAME);
Commit	Line	Data
5b904d39	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
8a99ff5a	10	#include <linux/acpi.h>
5b904d39	11	#include <linux/errno.h>
	12	#include <linux/etherdevice.h>
	13	#include <linux/init.h>
	14	#include <linux/kernel.h>
c7fc9eb7	15	#include <linux/mfd/syscon.h>
5b904d39	16	#include <linux/module.h>
	17	#include <linux/mutex.h>
	18	#include <linux/netdevice.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of.h>
	21	#include <linux/of_mdio.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/phy.h>
	24	#include <linux/platform_device.h>
c7fc9eb7	25	#include <linux/regmap.h>
5b904d39	26
	27	#define MDIO_DRV_NAME "Hi-HNS_MDIO"
	28	#define MDIO_BUS_NAME "Hisilicon MII Bus"
5b904d39	29
	30	#define MDIO_TIMEOUT 1000000
	31
b15dc292 KY	32	struct hns_mdio_sc_reg {
	33	u16 mdio_clk_en;
	34	u16 mdio_clk_dis;
	35	u16 mdio_reset_req;
	36	u16 mdio_reset_dreq;
	37	u16 mdio_clk_st;
	38	u16 mdio_reset_st;
	39	};
	40
5b904d39	41	struct hns_mdio_device {
5b904d39	42	void vbase; / mdio reg base address */
c7fc9eb7	43	struct regmap *subctrl_vbase;
b15dc292	44	struct hns_mdio_sc_reg sc_reg;
5b904d39	45	};
	46
	47	/* mdio reg */
	48	#define MDIO_COMMAND_REG 0x0
	49	#define MDIO_ADDR_REG 0x4
	50	#define MDIO_WDATA_REG 0x8
	51	#define MDIO_RDATA_REG 0xc
	52	#define MDIO_STA_REG 0x10
	53
	54	/* cfg phy bit map */
	55	#define MDIO_CMD_DEVAD_M 0x1f
	56	#define MDIO_CMD_DEVAD_S 0
	57	#define MDIO_CMD_PRTAD_M 0x1f
	58	#define MDIO_CMD_PRTAD_S 5
5b904d39	59	#define MDIO_CMD_OP_S 10
5b904d39	60	#define MDIO_CMD_ST_S 12
	61	#define MDIO_CMD_START_B 14
	62
	63	#define MDIO_ADDR_DATA_M 0xffff
	64	#define MDIO_ADDR_DATA_S 0
	65
	66	#define MDIO_WDATA_DATA_M 0xffff
	67	#define MDIO_WDATA_DATA_S 0
	68
	69	#define MDIO_RDATA_DATA_M 0xffff
	70	#define MDIO_RDATA_DATA_S 0
	71
	72	#define MDIO_STATE_STA_B 0
	73
	74	enum mdio_st_clause {
	75	MDIO_ST_CLAUSE_45 = 0,
	76	MDIO_ST_CLAUSE_22
	77	};
	78
	79	enum mdio_c22_op_seq {
	80	MDIO_C22_WRITE = 1,
	81	MDIO_C22_READ = 2
	82	};
	83
	84	enum mdio_c45_op_seq {
	85	MDIO_C45_WRITE_ADDR = 0,
	86	MDIO_C45_WRITE_DATA,
	87	MDIO_C45_READ_INCREMENT,
	88	MDIO_C45_READ
	89	};
	90
	91	/* peri subctrl reg */
	92	#define MDIO_SC_CLK_EN 0x338
	93	#define MDIO_SC_CLK_DIS 0x33C
	94	#define MDIO_SC_RESET_REQ 0xA38
	95	#define MDIO_SC_RESET_DREQ 0xA3C
5b904d39	96	#define MDIO_SC_CLK_ST 0x531C
	97	#define MDIO_SC_RESET_ST 0x5A1C
	98
	99	static void mdio_write_reg(void *base, u32 reg, u32 value)
	100	{
	101	u8 __iomem reg_addr = (u8 __iomem )base;
	102
	103	writel_relaxed(value, reg_addr + reg);
	104	}
	105
	106	#define MDIO_WRITE_REG(a, reg, value) \
	107	mdio_write_reg((a)->vbase, (reg), (value))
	108
	109	static u32 mdio_read_reg(void *base, u32 reg)
	110	{
	111	u8 __iomem reg_addr = (u8 __iomem )base;
	112
	113	return readl_relaxed(reg_addr + reg);
	114	}
	115
	116	#define mdio_set_field(origin, mask, shift, val) \
	117	do { \
	118	(origin) &= (~((mask) << (shift))); \
	119	(origin) \|= (((val) & (mask)) << (shift)); \
	120	} while (0)
	121
	122	#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
	123
	124	static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
	125	u32 val)
	126	{
	127	u32 origin = mdio_read_reg(base, reg);
	128
	129	mdio_set_field(origin, mask, shift, val);
	130	mdio_write_reg(base, reg, origin);
	131	}
	132
	133	#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
	134	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
	135
	136	static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
	137	{
	138	u32 origin;
	139
	140	origin = mdio_read_reg(base, reg);
	141	return mdio_get_field(origin, mask, shift);
	142	}
	143
	144	#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
	145	mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
	146
	147	#define MDIO_GET_REG_BIT(dev, reg, bit) \
	148	mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
	149
	150	#define MDIO_CHECK_SET_ST 1
	151	#define MDIO_CHECK_CLR_ST 0
	152
	153	static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
	154	u32 cfg_reg, u32 set_val,
	155	u32 st_reg, u32 st_msk, u8 check_st)
	156	{
	157	u32 time_cnt;
	158	u32 reg_value;
	159
c7fc9eb7	160	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
5b904d39	161
5b904d39	162	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
c7fc9eb7	163	regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
5b904d39	164	reg_value &= st_msk;
	165	if ((!!check_st) == (!!reg_value))
	166	break;
	167	}
	168
	169	if ((!!check_st) != (!!reg_value))
	170	return -EBUSY;
	171
	172	return 0;
	173	}
	174
	175	static int hns_mdio_wait_ready(struct mii_bus *bus)
	176	{
	177	struct hns_mdio_device *mdio_dev = bus->priv;
	178	int i;
	179	u32 cmd_reg_value = 1;
	180
	181	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	182	/* after that can do read or write*/
	183	for (i = 0; cmd_reg_value; i++) {
	184	cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
	185	MDIO_COMMAND_REG,
	186	MDIO_CMD_START_B);
	187	if (i == MDIO_TIMEOUT)
	188	return -ETIMEDOUT;
	189	}
	190
	191	return 0;
	192	}
	193
	194	static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
	195	u8 is_c45, u8 op, u8 phy_id, u16 cmd)
	196	{
	197	u32 cmd_reg_value;
	198	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
	199
	200	cmd_reg_value = st << MDIO_CMD_ST_S;
	201	cmd_reg_value \|= op << MDIO_CMD_OP_S;
	202	cmd_reg_value \|=
	203	(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	204	cmd_reg_value \|= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	205	cmd_reg_value \|= 1 << MDIO_CMD_START_B;
	206
	207	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
	208	}
	209
	210	/**
	211	* hns_mdio_write - access phy register
	212	* @bus: mdio bus
	213	* @phy_id: phy id
	214	* @regnum: register num
	215	* @value: register value
	216	*
	217	* Return 0 on success, negative on failure
	218	*/
	219	static int hns_mdio_write(struct mii_bus *bus,
	220	int phy_id, int regnum, u16 data)
	221	{
	222	int ret;
	223	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
	224	u8 devad = ((regnum >> 16) & 0x1f);
	225	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	226	u16 reg = (u16)(regnum & 0xffff);
	227	u8 op;
228	u16 cmd_reg_cfg;
229
230	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
231	bus->id, mdio_dev->vbase);
232	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
233	phy_id, is_c45, devad, reg, data);
234
235	/* wait for ready */
236	ret = hns_mdio_wait_ready(bus);
237	if (ret) {
238	dev_err(&bus->dev, "MDIO bus is busy\n");
239	return ret;
240	}
241
242	if (!is_c45) {
243	cmd_reg_cfg = reg;
244	op = MDIO_C22_WRITE;
245	} else {
246	/* config the cmd-reg to write addr*/
247	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
248	MDIO_ADDR_DATA_S, reg);
249
250	hns_mdio_cmd_write(mdio_dev, is_c45,
251	MDIO_C45_WRITE_ADDR, phy_id, devad);
252
253	/* check for read or write opt is finished */
254	ret = hns_mdio_wait_ready(bus);
255	if (ret) {
256	dev_err(&bus->dev, "MDIO bus is busy\n");
257	return ret;
258	}
259
260	/* config the data needed writing */
261	cmd_reg_cfg = devad;
262	op = MDIO_C45_WRITE_ADDR;
263	}
264
265	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
266	MDIO_WDATA_DATA_S, data);
267
268	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
269
270	return 0;
271	}
272
273	/**
274	* hns_mdio_read - access phy register
275	* @bus: mdio bus
276	* @phy_id: phy id
277	* @regnum: register num
278	* @value: register value
279	*
280	* Return phy register value
281	*/
282	static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
283	{
284	int ret;
285	u16 reg_val = 0;
286	u8 devad = ((regnum >> 16) & 0x1f);
287	u8 is_c45 = !!(regnum & MII_ADDR_C45);
288	u16 reg = (u16)(regnum & 0xffff);
289	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
290
291	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
292	bus->id, mdio_dev->vbase);
293	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
294	phy_id, is_c45, devad, reg);
295
296	/* Step 1: wait for ready */
297	ret = hns_mdio_wait_ready(bus);
298	if (ret) {
299	dev_err(&bus->dev, "MDIO bus is busy\n");
300	return ret;
301	}
302
303	if (!is_c45) {
304	hns_mdio_cmd_write(mdio_dev, is_c45,
305	MDIO_C22_READ, phy_id, reg);
306	} else {
307	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
308	MDIO_ADDR_DATA_S, reg);
309
310	/* Step 2; config the cmd-reg to write addr*/
311	hns_mdio_cmd_write(mdio_dev, is_c45,
312	MDIO_C45_WRITE_ADDR, phy_id, devad);
313
314	/* Step 3: check for read or write opt is finished */
315	ret = hns_mdio_wait_ready(bus);
316	if (ret) {
317	dev_err(&bus->dev, "MDIO bus is busy\n");
318	return ret;
319	}
320
321	hns_mdio_cmd_write(mdio_dev, is_c45,
322	MDIO_C45_WRITE_ADDR, phy_id, devad);
323	}
324
325	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
326	/* check for read or write opt is finished */
327	ret = hns_mdio_wait_ready(bus);
328	if (ret) {
329	dev_err(&bus->dev, "MDIO bus is busy\n");
330	return ret;
331	}
332
333	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
334	if (reg_val) {
335	dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
336	return -EBUSY;
337	}
338
339	/* Step 6; get out data*/
340	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
341	MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
342
343	return reg_val;
344	}
345
346	/**
347	* hns_mdio_reset - reset mdio bus
348	* @bus: mdio bus
349	*
350	* Return 0 on success, negative on failure
351	*/
352	static int hns_mdio_reset(struct mii_bus *bus)
353	{
354	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
b15dc292	355	const struct hns_mdio_sc_reg *sc_reg;
5b904d39	356	int ret;
5b904d39	357
8a99ff5a KY	358	if (dev_of_node(bus->parent)) {
	359	if (!mdio_dev->subctrl_vbase) {
	360	dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
	361	return -ENODEV;
	362	}
16a9f361	363
b15dc292	364	sc_reg = &mdio_dev->sc_reg;
8a99ff5a	365	/* 1. reset req, and read reset st check */
b15dc292 KY	366	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
b15dc292 KY	367	0x1, sc_reg->mdio_reset_st, 0x1,
8a99ff5a KY	368	MDIO_CHECK_SET_ST);
	369	if (ret) {
	370	dev_err(&bus->dev, "MDIO reset fail\n");
	371	return ret;
	372	}
5b904d39	373
8a99ff5a	374	/* 2. dis clk, and read clk st check */
b15dc292 KY	375	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
b15dc292 KY	376	0x1, sc_reg->mdio_clk_st, 0x1,
8a99ff5a KY	377	MDIO_CHECK_CLR_ST);
	378	if (ret) {
	379	dev_err(&bus->dev, "MDIO dis clk fail\n");
	380	return ret;
	381	}
5b904d39	382
8a99ff5a	383	/* 3. reset dreq, and read reset st check */
b15dc292 KY	384	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
b15dc292 KY	385	0x1, sc_reg->mdio_reset_st, 0x1,
8a99ff5a KY	386	MDIO_CHECK_CLR_ST);
	387	if (ret) {
	388	dev_err(&bus->dev, "MDIO dis clk fail\n");
	389	return ret;
	390	}
5b904d39	391
8a99ff5a	392	/* 4. en clk, and read clk st check */
b15dc292 KY	393	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
b15dc292 KY	394	0x1, sc_reg->mdio_clk_st, 0x1,
8a99ff5a KY	395	MDIO_CHECK_SET_ST);
	396	if (ret)
	397	dev_err(&bus->dev, "MDIO en clk fail\n");
	398	} else if (is_acpi_node(bus->parent->fwnode)) {
	399	acpi_status s;
	400
	401	s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
	402	"_RST", NULL, NULL);
	403	if (ACPI_FAILURE(s)) {
	404	dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
	405	ret = -EBUSY;
	406	} else {
	407	ret = 0;
	408	}
	409	} else {
	410	dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
	411	ret = -ENXIO;
5b904d39	412	}
5b904d39	413	return ret;
	414	}
	415
5b904d39	416	/**
	417	* hns_mdio_probe - probe mdio device
	418	* @pdev: mdio platform device
	419	*
	420	* Return 0 on success, negative on failure
	421	*/
	422	static int hns_mdio_probe(struct platform_device *pdev)
	423	{
5b904d39	424	struct hns_mdio_device *mdio_dev;
	425	struct mii_bus *new_bus;
	426	struct resource *res;
16a9f361	427	int ret = -ENODEV;
5b904d39	428
	429	if (!pdev) {
	430	dev_err(NULL, "pdev is NULL!\r\n");
	431	return -ENODEV;
	432	}
16a9f361	433
5b904d39	434	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	435	if (!mdio_dev)
	436	return -ENOMEM;
	437
	438	new_bus = devm_mdiobus_alloc(&pdev->dev);
	439	if (!new_bus) {
	440	dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
	441	return -ENOMEM;
	442	}
	443
	444	new_bus->name = MDIO_BUS_NAME;
	445	new_bus->read = hns_mdio_read;
	446	new_bus->write = hns_mdio_write;
	447	new_bus->reset = hns_mdio_reset;
	448	new_bus->priv = mdio_dev;
16a9f361	449	new_bus->parent = &pdev->dev;
5b904d39	450
	451	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	452	mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
	453	if (IS_ERR(mdio_dev->vbase)) {
	454	ret = PTR_ERR(mdio_dev->vbase);
	455	return ret;
	456	}
	457
5b904d39	458	platform_set_drvdata(pdev, new_bus);
16a9f361 KY	459	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
	460	dev_name(&pdev->dev));
	461	if (dev_of_node(&pdev->dev)) {
b15dc292 KY	462	struct of_phandle_args reg_args;
	463
	464	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
	465	"subctrl-vbase",
	466	4,
	467	0,
	468	&reg_args);
	469	if (!ret) {
	470	mdio_dev->subctrl_vbase =
	471	syscon_node_to_regmap(reg_args.np);
	472	if (IS_ERR(mdio_dev->subctrl_vbase)) {
	473	dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
	474	mdio_dev->subctrl_vbase = NULL;
	475	} else {
	476	if (reg_args.args_count == 4) {
	477	mdio_dev->sc_reg.mdio_clk_en =
	478	(u16)reg_args.args[0];
	479	mdio_dev->sc_reg.mdio_clk_dis =
	480	(u16)reg_args.args[0] + 4;
	481	mdio_dev->sc_reg.mdio_reset_req =
	482	(u16)reg_args.args[1];
	483	mdio_dev->sc_reg.mdio_reset_dreq =
	484	(u16)reg_args.args[1] + 4;
	485	mdio_dev->sc_reg.mdio_clk_st =
	486	(u16)reg_args.args[2];
	487	mdio_dev->sc_reg.mdio_reset_st =
	488	(u16)reg_args.args[3];
	489	} else {
	490	/* for compatible */
	491	mdio_dev->sc_reg.mdio_clk_en =
	492	MDIO_SC_CLK_EN;
	493	mdio_dev->sc_reg.mdio_clk_dis =
	494	MDIO_SC_CLK_DIS;
	495	mdio_dev->sc_reg.mdio_reset_req =
	496	MDIO_SC_RESET_REQ;
	497	mdio_dev->sc_reg.mdio_reset_dreq =
	498	MDIO_SC_RESET_DREQ;
	499	mdio_dev->sc_reg.mdio_clk_st =
	500	MDIO_SC_CLK_ST;
	501	mdio_dev->sc_reg.mdio_reset_st =
	502	MDIO_SC_RESET_ST;
	503	}
	504	}
	505	} else {
	506	dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
16a9f361 KY	507	mdio_dev->subctrl_vbase = NULL;
16a9f361 KY	508	}
b15dc292	509
16a9f361	510	ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
8a99ff5a KY	511	} else if (is_acpi_node(pdev->dev.fwnode)) {
	512	/* Clear all the IRQ properties */
	513	memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);
	514
	515	/* Mask out all PHYs from auto probing. */
	516	new_bus->phy_mask = ~0;
	517
	518	/* Register the MDIO bus */
	519	ret = mdiobus_register(new_bus);
	520	} else {
	521	dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
	522	ret = -ENXIO;
16a9f361	523	}
5b904d39	524
5b904d39	525	if (ret) {
	526	dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
	527	platform_set_drvdata(pdev, NULL);
	528	return ret;
	529	}
	530
	531	return 0;
	532	}
	533
	534	/**
	535	* hns_mdio_remove - remove mdio device
	536	* @pdev: mdio platform device
	537	*
	538	* Return 0 on success, negative on failure
	539	*/
	540	static int hns_mdio_remove(struct platform_device *pdev)
	541	{
	542	struct mii_bus *bus;
	543
	544	bus = platform_get_drvdata(pdev);
	545
	546	mdiobus_unregister(bus);
	547	platform_set_drvdata(pdev, NULL);
	548	return 0;
	549	}
	550
	551	static const struct of_device_id hns_mdio_match[] = {
	552	{.compatible = "hisilicon,mdio"},
	553	{.compatible = "hisilicon,hns-mdio"},
	554	{}
	555	};
af40097e	556	MODULE_DEVICE_TABLE(of, hns_mdio_match);
5b904d39	557
8a99ff5a KY	558	static const struct acpi_device_id hns_mdio_acpi_match[] = {
	559	{ "HISI0141", 0 },
	560	{ },
	561	};
	562	MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);
	563
5b904d39	564	static struct platform_driver hns_mdio_driver = {
	565	.probe = hns_mdio_probe,
	566	.remove = hns_mdio_remove,
	567	.driver = {
	568	.name = MDIO_DRV_NAME,
	569	.of_match_table = hns_mdio_match,
8a99ff5a	570	.acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
5b904d39	571	},
	572	};
	573
	574	module_platform_driver(hns_mdio_driver);
	575
	576	MODULE_LICENSE("GPL");
	577	MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
	578	MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
	579	MODULE_ALIAS("platform:" MDIO_DRV_NAME);