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51ba902a AK |
1 | /* |
2 | * Huawei HiNIC PCI Express Linux driver | |
3 | * Copyright(c) 2017 Huawei Technologies Co., Ltd | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/pci.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/bitops.h> | |
22 | ||
23 | #include "hinic_hw_csr.h" | |
24 | #include "hinic_hw_if.h" | |
25 | ||
26 | #define PCIE_ATTR_ENTRY 0 | |
27 | ||
f00fe738 AK |
28 | #define VALID_MSIX_IDX(attr, msix_index) ((msix_index) < (attr)->num_irqs) |
29 | ||
30 | /** | |
31 | * hinic_msix_attr_set - set message attribute for msix entry | |
32 | * @hwif: the HW interface of a pci function device | |
33 | * @msix_index: msix_index | |
34 | * @pending_limit: the maximum pending interrupt events (unit 8) | |
35 | * @coalesc_timer: coalesc period for interrupt (unit 8 us) | |
36 | * @lli_timer: replenishing period for low latency credit (unit 8 us) | |
37 | * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) | |
38 | * @resend_timer: maximum wait for resending msix (unit coalesc period) | |
39 | * | |
40 | * Return 0 - Success, negative - Failure | |
41 | **/ | |
42 | int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, | |
43 | u8 pending_limit, u8 coalesc_timer, | |
44 | u8 lli_timer, u8 lli_credit_limit, | |
45 | u8 resend_timer) | |
46 | { | |
47 | u32 msix_ctrl, addr; | |
48 | ||
49 | if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) | |
50 | return -EINVAL; | |
51 | ||
52 | msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | | |
53 | HINIC_MSIX_ATTR_SET(coalesc_timer, COALESC_TIMER) | | |
54 | HINIC_MSIX_ATTR_SET(lli_timer, LLI_TIMER) | | |
55 | HINIC_MSIX_ATTR_SET(lli_credit_limit, LLI_CREDIT) | | |
56 | HINIC_MSIX_ATTR_SET(resend_timer, RESEND_TIMER); | |
57 | ||
58 | addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); | |
59 | ||
60 | hinic_hwif_write_reg(hwif, addr, msix_ctrl); | |
61 | return 0; | |
62 | } | |
63 | ||
64 | /** | |
65 | * hinic_msix_attr_get - get message attribute of msix entry | |
66 | * @hwif: the HW interface of a pci function device | |
67 | * @msix_index: msix_index | |
68 | * @pending_limit: the maximum pending interrupt events (unit 8) | |
69 | * @coalesc_timer: coalesc period for interrupt (unit 8 us) | |
70 | * @lli_timer: replenishing period for low latency credit (unit 8 us) | |
71 | * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) | |
72 | * @resend_timer: maximum wait for resending msix (unit coalesc period) | |
73 | * | |
74 | * Return 0 - Success, negative - Failure | |
75 | **/ | |
76 | int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, | |
77 | u8 *pending_limit, u8 *coalesc_timer, | |
78 | u8 *lli_timer, u8 *lli_credit_limit, | |
79 | u8 *resend_timer) | |
80 | { | |
81 | u32 addr, val; | |
82 | ||
83 | if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) | |
84 | return -EINVAL; | |
85 | ||
86 | addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); | |
87 | val = hinic_hwif_read_reg(hwif, addr); | |
88 | ||
89 | *pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT); | |
90 | *coalesc_timer = HINIC_MSIX_ATTR_GET(val, COALESC_TIMER); | |
91 | *lli_timer = HINIC_MSIX_ATTR_GET(val, LLI_TIMER); | |
92 | *lli_credit_limit = HINIC_MSIX_ATTR_GET(val, LLI_CREDIT); | |
93 | *resend_timer = HINIC_MSIX_ATTR_GET(val, RESEND_TIMER); | |
94 | return 0; | |
95 | } | |
96 | ||
97 | /** | |
98 | * hinic_msix_attr_cnt_clear - clear message attribute counters for msix entry | |
99 | * @hwif: the HW interface of a pci function device | |
100 | * @msix_index: msix_index | |
101 | * | |
102 | * Return 0 - Success, negative - Failure | |
103 | **/ | |
104 | int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index) | |
105 | { | |
106 | u32 msix_ctrl, addr; | |
107 | ||
108 | if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) | |
109 | return -EINVAL; | |
110 | ||
111 | msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); | |
112 | addr = HINIC_CSR_MSIX_CNT_ADDR(msix_index); | |
113 | ||
114 | hinic_hwif_write_reg(hwif, addr, msix_ctrl); | |
115 | return 0; | |
116 | } | |
117 | ||
c4d06d2d AK |
118 | /** |
119 | * hinic_set_pf_action - set action on pf channel | |
120 | * @hwif: the HW interface of a pci function device | |
121 | * @action: action on pf channel | |
122 | * | |
123 | * Return 0 - Success, negative - Failure | |
124 | **/ | |
125 | void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action) | |
126 | { | |
127 | u32 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR); | |
128 | ||
129 | attr5 = HINIC_FA5_CLEAR(attr5, PF_ACTION); | |
130 | attr5 |= HINIC_FA5_SET(action, PF_ACTION); | |
131 | ||
132 | hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, attr5); | |
133 | } | |
134 | ||
e2585ea7 AK |
135 | enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif) |
136 | { | |
137 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); | |
138 | ||
139 | return HINIC_FA4_GET(attr4, OUTBOUND_STATE); | |
140 | } | |
141 | ||
142 | void hinic_outbound_state_set(struct hinic_hwif *hwif, | |
143 | enum hinic_outbound_state outbound_state) | |
144 | { | |
145 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); | |
146 | ||
147 | attr4 = HINIC_FA4_CLEAR(attr4, OUTBOUND_STATE); | |
148 | attr4 |= HINIC_FA4_SET(outbound_state, OUTBOUND_STATE); | |
149 | ||
150 | hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); | |
151 | } | |
152 | ||
153 | enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif) | |
154 | { | |
155 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); | |
156 | ||
157 | return HINIC_FA4_GET(attr4, DB_STATE); | |
158 | } | |
159 | ||
160 | void hinic_db_state_set(struct hinic_hwif *hwif, | |
161 | enum hinic_db_state db_state) | |
162 | { | |
163 | u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); | |
164 | ||
165 | attr4 = HINIC_FA4_CLEAR(attr4, DB_STATE); | |
166 | attr4 |= HINIC_FA4_SET(db_state, DB_STATE); | |
167 | ||
168 | hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); | |
169 | } | |
170 | ||
6a044c3d XC |
171 | void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, |
172 | enum hinic_msix_state flag) | |
173 | { | |
174 | u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE + | |
175 | HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL; | |
176 | u32 mask_bits; | |
177 | ||
178 | mask_bits = readl(hwif->intr_regs_base + offset); | |
179 | mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
180 | ||
181 | if (flag) | |
182 | mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
183 | ||
184 | writel(mask_bits, hwif->intr_regs_base + offset); | |
185 | } | |
186 | ||
51ba902a AK |
187 | /** |
188 | * hwif_ready - test if the HW is ready for use | |
189 | * @hwif: the HW interface of a pci function device | |
190 | * | |
191 | * Return 0 - Success, negative - Failure | |
192 | **/ | |
193 | static int hwif_ready(struct hinic_hwif *hwif) | |
194 | { | |
195 | struct pci_dev *pdev = hwif->pdev; | |
196 | u32 addr, attr1; | |
197 | ||
198 | addr = HINIC_CSR_FUNC_ATTR1_ADDR; | |
199 | attr1 = hinic_hwif_read_reg(hwif, addr); | |
200 | ||
201 | if (!HINIC_FA1_GET(attr1, INIT_STATUS)) { | |
202 | dev_err(&pdev->dev, "hwif status is not ready\n"); | |
203 | return -EFAULT; | |
204 | } | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | /** | |
210 | * set_hwif_attr - set the attributes in the relevant members in hwif | |
211 | * @hwif: the HW interface of a pci function device | |
212 | * @attr0: the first attribute that was read from the hw | |
213 | * @attr1: the second attribute that was read from the hw | |
214 | **/ | |
215 | static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1) | |
216 | { | |
217 | hwif->attr.func_idx = HINIC_FA0_GET(attr0, FUNC_IDX); | |
218 | hwif->attr.pf_idx = HINIC_FA0_GET(attr0, PF_IDX); | |
219 | hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX); | |
220 | hwif->attr.func_type = HINIC_FA0_GET(attr0, FUNC_TYPE); | |
221 | ||
222 | hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC)); | |
223 | hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC)); | |
224 | hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC)); | |
225 | hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC)); | |
226 | } | |
227 | ||
228 | /** | |
229 | * read_hwif_attr - read the attributes and set members in hwif | |
230 | * @hwif: the HW interface of a pci function device | |
231 | **/ | |
232 | static void read_hwif_attr(struct hinic_hwif *hwif) | |
233 | { | |
234 | u32 addr, attr0, attr1; | |
235 | ||
236 | addr = HINIC_CSR_FUNC_ATTR0_ADDR; | |
237 | attr0 = hinic_hwif_read_reg(hwif, addr); | |
238 | ||
239 | addr = HINIC_CSR_FUNC_ATTR1_ADDR; | |
240 | attr1 = hinic_hwif_read_reg(hwif, addr); | |
241 | ||
242 | set_hwif_attr(hwif, attr0, attr1); | |
243 | } | |
244 | ||
245 | /** | |
246 | * set_ppf - try to set hwif as ppf and set the type of hwif in this case | |
247 | * @hwif: the HW interface of a pci function device | |
248 | **/ | |
249 | static void set_ppf(struct hinic_hwif *hwif) | |
250 | { | |
251 | struct hinic_func_attr *attr = &hwif->attr; | |
252 | u32 addr, val, ppf_election; | |
253 | ||
254 | /* Read Modify Write */ | |
255 | addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif)); | |
256 | ||
257 | val = hinic_hwif_read_reg(hwif, addr); | |
258 | val = HINIC_PPF_ELECTION_CLEAR(val, IDX); | |
259 | ||
260 | ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX); | |
261 | ||
262 | val |= ppf_election; | |
263 | hinic_hwif_write_reg(hwif, addr, val); | |
264 | ||
265 | /* check PPF */ | |
266 | val = hinic_hwif_read_reg(hwif, addr); | |
267 | ||
268 | attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); | |
269 | if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif)) | |
270 | attr->func_type = HINIC_PPF; | |
271 | } | |
272 | ||
273 | /** | |
274 | * set_dma_attr - set the dma attributes in the HW | |
275 | * @hwif: the HW interface of a pci function device | |
276 | * @entry_idx: the entry index in the dma table | |
277 | * @st: PCIE TLP steering tag | |
278 | * @at: PCIE TLP AT field | |
279 | * @ph: PCIE TLP Processing Hint field | |
280 | * @no_snooping: PCIE TLP No snooping | |
281 | * @tph_en: PCIE TLP Processing Hint Enable | |
282 | **/ | |
283 | static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx, | |
284 | u8 st, u8 at, u8 ph, | |
285 | enum hinic_pcie_nosnoop no_snooping, | |
286 | enum hinic_pcie_tph tph_en) | |
287 | { | |
288 | u32 addr, val, dma_attr_entry; | |
289 | ||
290 | /* Read Modify Write */ | |
291 | addr = HINIC_CSR_DMA_ATTR_ADDR(entry_idx); | |
292 | ||
293 | val = hinic_hwif_read_reg(hwif, addr); | |
294 | val = HINIC_DMA_ATTR_CLEAR(val, ST) & | |
295 | HINIC_DMA_ATTR_CLEAR(val, AT) & | |
296 | HINIC_DMA_ATTR_CLEAR(val, PH) & | |
297 | HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) & | |
298 | HINIC_DMA_ATTR_CLEAR(val, TPH_EN); | |
299 | ||
300 | dma_attr_entry = HINIC_DMA_ATTR_SET(st, ST) | | |
301 | HINIC_DMA_ATTR_SET(at, AT) | | |
302 | HINIC_DMA_ATTR_SET(ph, PH) | | |
303 | HINIC_DMA_ATTR_SET(no_snooping, NO_SNOOPING) | | |
304 | HINIC_DMA_ATTR_SET(tph_en, TPH_EN); | |
305 | ||
306 | val |= dma_attr_entry; | |
307 | hinic_hwif_write_reg(hwif, addr, val); | |
308 | } | |
309 | ||
310 | /** | |
311 | * dma_attr_table_init - initialize the the default dma attributes | |
312 | * @hwif: the HW interface of a pci function device | |
313 | **/ | |
314 | static void dma_attr_init(struct hinic_hwif *hwif) | |
315 | { | |
316 | set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE, | |
317 | HINIC_PCIE_AT_DISABLE, HINIC_PCIE_PH_DISABLE, | |
318 | HINIC_PCIE_SNOOP, HINIC_PCIE_TPH_DISABLE); | |
319 | } | |
320 | ||
321 | /** | |
322 | * hinic_init_hwif - initialize the hw interface | |
323 | * @hwif: the HW interface of a pci function device | |
324 | * @pdev: the pci device for acessing PCI resources | |
325 | * | |
326 | * Return 0 - Success, negative - Failure | |
327 | **/ | |
328 | int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev) | |
329 | { | |
330 | int err; | |
331 | ||
332 | hwif->pdev = pdev; | |
333 | ||
334 | hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR); | |
335 | if (!hwif->cfg_regs_bar) { | |
336 | dev_err(&pdev->dev, "Failed to map configuration regs\n"); | |
337 | return -ENOMEM; | |
338 | } | |
339 | ||
6a044c3d XC |
340 | hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR); |
341 | if (!hwif->intr_regs_base) { | |
342 | dev_err(&pdev->dev, "Failed to map configuration regs\n"); | |
343 | err = -ENOMEM; | |
344 | goto err_map_intr_bar; | |
345 | } | |
346 | ||
51ba902a AK |
347 | err = hwif_ready(hwif); |
348 | if (err) { | |
349 | dev_err(&pdev->dev, "HW interface is not ready\n"); | |
350 | goto err_hwif_ready; | |
351 | } | |
352 | ||
353 | read_hwif_attr(hwif); | |
354 | ||
355 | if (HINIC_IS_PF(hwif)) | |
356 | set_ppf(hwif); | |
357 | ||
358 | /* No transactionss before DMA is initialized */ | |
359 | dma_attr_init(hwif); | |
360 | return 0; | |
361 | ||
362 | err_hwif_ready: | |
6a044c3d XC |
363 | iounmap(hwif->intr_regs_base); |
364 | ||
365 | err_map_intr_bar: | |
51ba902a | 366 | iounmap(hwif->cfg_regs_bar); |
6a044c3d | 367 | |
51ba902a AK |
368 | return err; |
369 | } | |
370 | ||
371 | /** | |
372 | * hinic_free_hwif - free the HW interface | |
373 | * @hwif: the HW interface of a pci function device | |
374 | **/ | |
375 | void hinic_free_hwif(struct hinic_hwif *hwif) | |
376 | { | |
6a044c3d | 377 | iounmap(hwif->intr_regs_base); |
51ba902a AK |
378 | iounmap(hwif->cfg_regs_bar); |
379 | } |