[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / huawei / hinic / hinic_hw_if.h

/*
 * Huawei HiNIC PCI Express Linux driver
 * Copyright(c) 2017 Huawei Technologies Co., Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 */

#ifndef HINIC_HW_IF_H
#define HINIC_HW_IF_H

#include <linux/pci.h>
#include <linux/io.h>
#include <linux/types.h>
#include <asm/byteorder.h>

#define HINIC_DMA_ATTR_ST_SHIFT                                 0
#define HINIC_DMA_ATTR_AT_SHIFT                                 8
#define HINIC_DMA_ATTR_PH_SHIFT                                 10
#define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT                        12
#define HINIC_DMA_ATTR_TPH_EN_SHIFT                             13

#define HINIC_DMA_ATTR_ST_MASK                                  0xFF
#define HINIC_DMA_ATTR_AT_MASK                                  0x3
#define HINIC_DMA_ATTR_PH_MASK                                  0x3
#define HINIC_DMA_ATTR_NO_SNOOPING_MASK                         0x1
#define HINIC_DMA_ATTR_TPH_EN_MASK                              0x1

#define HINIC_DMA_ATTR_SET(val, member)                         \
	(((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) <<       \
	 HINIC_DMA_ATTR_##member##_SHIFT)

#define HINIC_DMA_ATTR_CLEAR(val, member)                       \
	((val) & (~(HINIC_DMA_ATTR_##member##_MASK              \
	 << HINIC_DMA_ATTR_##member##_SHIFT)))

#define HINIC_FA0_FUNC_IDX_SHIFT                                0
#define HINIC_FA0_PF_IDX_SHIFT                                  10
#define HINIC_FA0_PCI_INTF_IDX_SHIFT                            14
/* reserved members - off 16 */
#define HINIC_FA0_FUNC_TYPE_SHIFT                               24

#define HINIC_FA0_FUNC_IDX_MASK                                 0x3FF
#define HINIC_FA0_PF_IDX_MASK                                   0xF
#define HINIC_FA0_PCI_INTF_IDX_MASK                             0x3
#define HINIC_FA0_FUNC_TYPE_MASK                                0x1

#define HINIC_FA0_GET(val, member)                              \
	(((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)

#define HINIC_FA1_AEQS_PER_FUNC_SHIFT                           8
/* reserved members - off 10 */
#define HINIC_FA1_CEQS_PER_FUNC_SHIFT                           12
/* reserved members - off 15 */
#define HINIC_FA1_IRQS_PER_FUNC_SHIFT                           20
#define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT                       24
/* reserved members - off 27 */
#define HINIC_FA1_INIT_STATUS_SHIFT                             30

#define HINIC_FA1_AEQS_PER_FUNC_MASK                            0x3
#define HINIC_FA1_CEQS_PER_FUNC_MASK                            0x7
#define HINIC_FA1_IRQS_PER_FUNC_MASK                            0xF
#define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK                        0x7
#define HINIC_FA1_INIT_STATUS_MASK                              0x1

#define HINIC_FA1_GET(val, member)                              \
	(((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)

#define HINIC_FA4_OUTBOUND_STATE_SHIFT                          0
#define HINIC_FA4_DB_STATE_SHIFT                                1

#define HINIC_FA4_OUTBOUND_STATE_MASK                           0x1
#define HINIC_FA4_DB_STATE_MASK                                 0x1

#define HINIC_FA4_GET(val, member)                              \
	(((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK)

#define HINIC_FA4_SET(val, member)                              \
	((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT)

#define HINIC_FA4_CLEAR(val, member)                            \
	((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT)))

#define HINIC_FA5_PF_ACTION_SHIFT                               0
#define HINIC_FA5_PF_ACTION_MASK                                0xFFFF

#define HINIC_FA5_SET(val, member)                              \
	(((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)

#define HINIC_FA5_CLEAR(val, member)                            \
	((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))

#define HINIC_PPF_ELECTION_IDX_SHIFT                            0
#define HINIC_PPF_ELECTION_IDX_MASK                             0x1F

#define HINIC_PPF_ELECTION_SET(val, member)                     \
	(((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) <<   \
	 HINIC_PPF_ELECTION_##member##_SHIFT)

#define HINIC_PPF_ELECTION_GET(val, member)                     \
	(((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) &       \
	 HINIC_PPF_ELECTION_##member##_MASK)

#define HINIC_PPF_ELECTION_CLEAR(val, member)                   \
	((val) & (~(HINIC_PPF_ELECTION_##member##_MASK          \
	 << HINIC_PPF_ELECTION_##member##_SHIFT)))

#define HINIC_MSIX_PENDING_LIMIT_SHIFT                          0
#define HINIC_MSIX_COALESC_TIMER_SHIFT                          8
#define HINIC_MSIX_LLI_TIMER_SHIFT                              16
#define HINIC_MSIX_LLI_CREDIT_SHIFT                             24
#define HINIC_MSIX_RESEND_TIMER_SHIFT                           29

#define HINIC_MSIX_PENDING_LIMIT_MASK                           0xFF
#define HINIC_MSIX_COALESC_TIMER_MASK                           0xFF
#define HINIC_MSIX_LLI_TIMER_MASK                               0xFF
#define HINIC_MSIX_LLI_CREDIT_MASK                              0x1F
#define HINIC_MSIX_RESEND_TIMER_MASK                            0x7

#define HINIC_MSIX_ATTR_SET(val, member)                        \
	(((u32)(val) & HINIC_MSIX_##member##_MASK) <<           \
	 HINIC_MSIX_##member##_SHIFT)

#define HINIC_MSIX_ATTR_GET(val, member)                        \
	(((val) >> HINIC_MSIX_##member##_SHIFT) &               \
	 HINIC_MSIX_##member##_MASK)

#define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT                       29

#define HINIC_MSIX_CNT_RESEND_TIMER_MASK                        0x1

#define HINIC_MSIX_CNT_SET(val, member)                         \
	(((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) <<       \
	 HINIC_MSIX_CNT_##member##_SHIFT)

#define HINIC_HWIF_NUM_AEQS(hwif)       ((hwif)->attr.num_aeqs)
#define HINIC_HWIF_NUM_CEQS(hwif)       ((hwif)->attr.num_ceqs)
#define HINIC_HWIF_NUM_IRQS(hwif)       ((hwif)->attr.num_irqs)
#define HINIC_HWIF_FUNC_IDX(hwif)       ((hwif)->attr.func_idx)
#define HINIC_HWIF_PCI_INTF(hwif)       ((hwif)->attr.pci_intf_idx)
#define HINIC_HWIF_PF_IDX(hwif)         ((hwif)->attr.pf_idx)

#define HINIC_FUNC_TYPE(hwif)           ((hwif)->attr.func_type)
#define HINIC_IS_PF(hwif)               (HINIC_FUNC_TYPE(hwif) == HINIC_PF)
#define HINIC_IS_PPF(hwif)              (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)

#define HINIC_PCI_CFG_REGS_BAR          0
#define HINIC_PCI_INTR_REGS_BAR         2
#define HINIC_PCI_DB_BAR                4

#define HINIC_PCIE_ST_DISABLE           0
#define HINIC_PCIE_AT_DISABLE           0
#define HINIC_PCIE_PH_DISABLE           0

#define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT     0       /* Disabled */
#define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT     0xFF    /* max */
#define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT         0       /* Disabled */
#define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT  0       /* Disabled */
#define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT      7       /* max */

#define HINIC_PCI_MSIX_ENTRY_SIZE               16
#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL        12
#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT       1

enum hinic_pcie_nosnoop {
	HINIC_PCIE_SNOOP        = 0,
	HINIC_PCIE_NO_SNOOP     = 1,
};

enum hinic_pcie_tph {
	HINIC_PCIE_TPH_DISABLE  = 0,
	HINIC_PCIE_TPH_ENABLE   = 1,
};

enum hinic_func_type {
	HINIC_PF        = 0,
	HINIC_PPF       = 2,
};

enum hinic_mod_type {
	HINIC_MOD_COMM  = 0,    /* HW communication module */
	HINIC_MOD_L2NIC = 1,    /* L2NIC module */
	HINIC_MOD_CFGM  = 7,    /* Configuration module */

	HINIC_MOD_MAX   = 15
};

enum hinic_node_id {
	HINIC_NODE_ID_MGMT = 21,
};

enum hinic_pf_action {
	HINIC_PF_MGMT_INIT = 0x0,

	HINIC_PF_MGMT_ACTIVE = 0x11,
};

enum hinic_outbound_state {
	HINIC_OUTBOUND_ENABLE  = 0,
	HINIC_OUTBOUND_DISABLE = 1,
};

enum hinic_db_state {
	HINIC_DB_ENABLE  = 0,
	HINIC_DB_DISABLE = 1,
};

enum hinic_msix_state {
	HINIC_MSIX_ENABLE,
	HINIC_MSIX_DISABLE,
};

struct hinic_func_attr {
	u16                     func_idx;
	u8                      pf_idx;
	u8                      pci_intf_idx;

	enum hinic_func_type    func_type;

	u8                      ppf_idx;

	u16                     num_irqs;
	u8                      num_aeqs;
	u8                      num_ceqs;

	u8                      num_dma_attr;
};

struct hinic_hwif {
	struct pci_dev          *pdev;
	void __iomem            *cfg_regs_bar;
	void __iomem		*intr_regs_base;

	struct hinic_func_attr  attr;
};

static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
{
	return be32_to_cpu(readl(hwif->cfg_regs_bar + reg));
}

static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,
					u32 val)
{
	writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg);
}

int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
			u8 pending_limit, u8 coalesc_timer,
			u8 lli_timer_cfg, u8 lli_credit_limit,
			u8 resend_timer);

int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
			u8 *pending_limit, u8 *coalesc_timer_cfg,
			u8 *lli_timer, u8 *lli_credit_limit,
			u8 *resend_timer);

void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,
			  enum hinic_msix_state flag);

int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);

void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);

enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif);

void hinic_outbound_state_set(struct hinic_hwif *hwif,
			      enum hinic_outbound_state outbound_state);

enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif);

void hinic_db_state_set(struct hinic_hwif *hwif,
			enum hinic_db_state db_state);

int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev);

void hinic_free_hwif(struct hinic_hwif *hwif);

#endif
Commit	Line	Data
51ba902a AK	1	/*
	2	* Huawei HiNIC PCI Express Linux driver
	3	* Copyright(c) 2017 Huawei Technologies Co., Ltd
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	12	* for more details.
	13	*
	14	*/
	15
	16	#ifndef HINIC_HW_IF_H
	17	#define HINIC_HW_IF_H
	18
	19	#include <linux/pci.h>
	20	#include <linux/io.h>
	21	#include <linux/types.h>
	22	#include <asm/byteorder.h>
	23
	24	#define HINIC_DMA_ATTR_ST_SHIFT 0
	25	#define HINIC_DMA_ATTR_AT_SHIFT 8
	26	#define HINIC_DMA_ATTR_PH_SHIFT 10
	27	#define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT 12
	28	#define HINIC_DMA_ATTR_TPH_EN_SHIFT 13
	29
	30	#define HINIC_DMA_ATTR_ST_MASK 0xFF
	31	#define HINIC_DMA_ATTR_AT_MASK 0x3
	32	#define HINIC_DMA_ATTR_PH_MASK 0x3
	33	#define HINIC_DMA_ATTR_NO_SNOOPING_MASK 0x1
	34	#define HINIC_DMA_ATTR_TPH_EN_MASK 0x1
	35
	36	#define HINIC_DMA_ATTR_SET(val, member) \
	37	(((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \
	38	HINIC_DMA_ATTR_##member##_SHIFT)
	39
	40	#define HINIC_DMA_ATTR_CLEAR(val, member) \
	41	((val) & (~(HINIC_DMA_ATTR_##member##_MASK \
	42	<< HINIC_DMA_ATTR_##member##_SHIFT)))
	43
	44	#define HINIC_FA0_FUNC_IDX_SHIFT 0
	45	#define HINIC_FA0_PF_IDX_SHIFT 10
	46	#define HINIC_FA0_PCI_INTF_IDX_SHIFT 14
	47	/* reserved members - off 16 */
	48	#define HINIC_FA0_FUNC_TYPE_SHIFT 24
	49
	50	#define HINIC_FA0_FUNC_IDX_MASK 0x3FF
	51	#define HINIC_FA0_PF_IDX_MASK 0xF
	52	#define HINIC_FA0_PCI_INTF_IDX_MASK 0x3
	53	#define HINIC_FA0_FUNC_TYPE_MASK 0x1
	54
	55	#define HINIC_FA0_GET(val, member) \
	56	(((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)
	57
	58	#define HINIC_FA1_AEQS_PER_FUNC_SHIFT 8
	59	/* reserved members - off 10 */
	60	#define HINIC_FA1_CEQS_PER_FUNC_SHIFT 12
	61	/* reserved members - off 15 */
	62	#define HINIC_FA1_IRQS_PER_FUNC_SHIFT 20
	63	#define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT 24
	64	/* reserved members - off 27 */
65	#define HINIC_FA1_INIT_STATUS_SHIFT 30
66
67	#define HINIC_FA1_AEQS_PER_FUNC_MASK 0x3
68	#define HINIC_FA1_CEQS_PER_FUNC_MASK 0x7
69	#define HINIC_FA1_IRQS_PER_FUNC_MASK 0xF
70	#define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK 0x7
71	#define HINIC_FA1_INIT_STATUS_MASK 0x1
72
73	#define HINIC_FA1_GET(val, member) \
74	(((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)
75
e2585ea7 AK	76	#define HINIC_FA4_OUTBOUND_STATE_SHIFT 0
	77	#define HINIC_FA4_DB_STATE_SHIFT 1
	78
	79	#define HINIC_FA4_OUTBOUND_STATE_MASK 0x1
	80	#define HINIC_FA4_DB_STATE_MASK 0x1
	81
	82	#define HINIC_FA4_GET(val, member) \
	83	(((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK)
	84
	85	#define HINIC_FA4_SET(val, member) \
	86	((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT)
	87
	88	#define HINIC_FA4_CLEAR(val, member) \
	89	((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT)))
	90
c4d06d2d AK	91	#define HINIC_FA5_PF_ACTION_SHIFT 0
	92	#define HINIC_FA5_PF_ACTION_MASK 0xFFFF
	93
	94	#define HINIC_FA5_SET(val, member) \
	95	(((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)
	96
	97	#define HINIC_FA5_CLEAR(val, member) \
	98	((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))
	99
51ba902a AK	100	#define HINIC_PPF_ELECTION_IDX_SHIFT 0
	101	#define HINIC_PPF_ELECTION_IDX_MASK 0x1F
	102
	103	#define HINIC_PPF_ELECTION_SET(val, member) \
	104	(((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \
	105	HINIC_PPF_ELECTION_##member##_SHIFT)
	106
	107	#define HINIC_PPF_ELECTION_GET(val, member) \
	108	(((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
	109	HINIC_PPF_ELECTION_##member##_MASK)
	110
	111	#define HINIC_PPF_ELECTION_CLEAR(val, member) \
	112	((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
	113	<< HINIC_PPF_ELECTION_##member##_SHIFT)))
	114
f00fe738 AK	115	#define HINIC_MSIX_PENDING_LIMIT_SHIFT 0
	116	#define HINIC_MSIX_COALESC_TIMER_SHIFT 8
	117	#define HINIC_MSIX_LLI_TIMER_SHIFT 16
	118	#define HINIC_MSIX_LLI_CREDIT_SHIFT 24
	119	#define HINIC_MSIX_RESEND_TIMER_SHIFT 29
	120
	121	#define HINIC_MSIX_PENDING_LIMIT_MASK 0xFF
	122	#define HINIC_MSIX_COALESC_TIMER_MASK 0xFF
	123	#define HINIC_MSIX_LLI_TIMER_MASK 0xFF
	124	#define HINIC_MSIX_LLI_CREDIT_MASK 0x1F
	125	#define HINIC_MSIX_RESEND_TIMER_MASK 0x7
	126
	127	#define HINIC_MSIX_ATTR_SET(val, member) \
	128	(((u32)(val) & HINIC_MSIX_##member##_MASK) << \
	129	HINIC_MSIX_##member##_SHIFT)
	130
	131	#define HINIC_MSIX_ATTR_GET(val, member) \
	132	(((val) >> HINIC_MSIX_##member##_SHIFT) & \
	133	HINIC_MSIX_##member##_MASK)
	134
	135	#define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29
	136
	137	#define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x1
	138
	139	#define HINIC_MSIX_CNT_SET(val, member) \
	140	(((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \
	141	HINIC_MSIX_CNT_##member##_SHIFT)
	142
51ba902a AK	143	#define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs)
	144	#define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs)
	145	#define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs)
	146	#define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx)
	147	#define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx)
6dd8b682	148	#define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx)
51ba902a AK	149
	150	#define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type)
	151	#define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF)
	152	#define HINIC_IS_PPF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)
	153
	154	#define HINIC_PCI_CFG_REGS_BAR 0
6a044c3d	155	#define HINIC_PCI_INTR_REGS_BAR 2
f91090f7	156	#define HINIC_PCI_DB_BAR 4
51ba902a AK	157
	158	#define HINIC_PCIE_ST_DISABLE 0
	159	#define HINIC_PCIE_AT_DISABLE 0
	160	#define HINIC_PCIE_PH_DISABLE 0
	161
f00fe738 AK	162	#define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT 0 /* Disabled */
	163	#define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT 0xFF /* max */
	164	#define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT 0 /* Disabled */
	165	#define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT 0 /* Disabled */
	166	#define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT 7 /* max */
	167
6a044c3d XC	168	#define HINIC_PCI_MSIX_ENTRY_SIZE 16
	169	#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
	170	#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1
	171
51ba902a AK	172	enum hinic_pcie_nosnoop {
	173	HINIC_PCIE_SNOOP = 0,
	174	HINIC_PCIE_NO_SNOOP = 1,
	175	};
	176
	177	enum hinic_pcie_tph {
	178	HINIC_PCIE_TPH_DISABLE = 0,
	179	HINIC_PCIE_TPH_ENABLE = 1,
	180	};
	181
	182	enum hinic_func_type {
	183	HINIC_PF = 0,
	184	HINIC_PPF = 2,
	185	};
	186
a5564e7e AK	187	enum hinic_mod_type {
	188	HINIC_MOD_COMM = 0, /* HW communication module */
	189	HINIC_MOD_L2NIC = 1, /* L2NIC module */
	190	HINIC_MOD_CFGM = 7, /* Configuration module */
	191
	192	HINIC_MOD_MAX = 15
	193	};
	194
6dd8b682 AK	195	enum hinic_node_id {
	196	HINIC_NODE_ID_MGMT = 21,
	197	};
	198
c4d06d2d AK	199	enum hinic_pf_action {
	200	HINIC_PF_MGMT_INIT = 0x0,
	201
	202	HINIC_PF_MGMT_ACTIVE = 0x11,
	203	};
	204
e2585ea7 AK	205	enum hinic_outbound_state {
	206	HINIC_OUTBOUND_ENABLE = 0,
	207	HINIC_OUTBOUND_DISABLE = 1,
	208	};
	209
	210	enum hinic_db_state {
	211	HINIC_DB_ENABLE = 0,
	212	HINIC_DB_DISABLE = 1,
	213	};
	214
6a044c3d XC	215	enum hinic_msix_state {
	216	HINIC_MSIX_ENABLE,
	217	HINIC_MSIX_DISABLE,
	218	};
	219
51ba902a AK	220	struct hinic_func_attr {
	221	u16 func_idx;
	222	u8 pf_idx;
	223	u8 pci_intf_idx;
	224
	225	enum hinic_func_type func_type;
	226
	227	u8 ppf_idx;
	228
	229	u16 num_irqs;
	230	u8 num_aeqs;
	231	u8 num_ceqs;
	232
	233	u8 num_dma_attr;
	234	};
	235
	236	struct hinic_hwif {
	237	struct pci_dev *pdev;
	238	void __iomem *cfg_regs_bar;
6a044c3d	239	void __iomem *intr_regs_base;
51ba902a AK	240
	241	struct hinic_func_attr attr;
	242	};
	243
	244	static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
	245	{
	246	return be32_to_cpu(readl(hwif->cfg_regs_bar + reg));
	247	}
	248
	249	static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,
	250	u32 val)
	251	{
	252	writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg);
	253	}
	254
f00fe738 AK	255	int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
	256	u8 pending_limit, u8 coalesc_timer,
	257	u8 lli_timer_cfg, u8 lli_credit_limit,
	258	u8 resend_timer);
	259
	260	int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
	261	u8 pending_limit, u8 coalesc_timer_cfg,
	262	u8 lli_timer, u8 lli_credit_limit,
	263	u8 *resend_timer);
	264
6a044c3d XC	265	void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,
	266	enum hinic_msix_state flag);
	267
f00fe738 AK	268	int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);
f00fe738 AK	269
c4d06d2d AK	270	void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);
c4d06d2d AK	271
e2585ea7 AK	272	enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif);
	273
	274	void hinic_outbound_state_set(struct hinic_hwif *hwif,
	275	enum hinic_outbound_state outbound_state);
	276
	277	enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif);
	278
	279	void hinic_db_state_set(struct hinic_hwif *hwif,
	280	enum hinic_db_state db_state);
	281
51ba902a AK	282	int hinic_init_hwif(struct hinic_hwif hwif, struct pci_dev pdev);
	283
	284	void hinic_free_hwif(struct hinic_hwif *hwif);
	285
	286	#endif