[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / huawei / hinic / hinic_hw_qp.h

/*
 * Huawei HiNIC PCI Express Linux driver
 * Copyright(c) 2017 Huawei Technologies Co., Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 */

#ifndef HINIC_HW_QP_H
#define HINIC_HW_QP_H

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/sizes.h>
#include <linux/pci.h>
#include <linux/skbuff.h>

#include "hinic_common.h"
#include "hinic_hw_if.h"
#include "hinic_hw_wqe.h"
#include "hinic_hw_wq.h"
#include "hinic_hw_qp_ctxt.h"

#define HINIC_SQ_DB_INFO_PI_HI_SHIFT            0
#define HINIC_SQ_DB_INFO_QID_SHIFT              8
#define HINIC_SQ_DB_INFO_PATH_SHIFT             23
#define HINIC_SQ_DB_INFO_COS_SHIFT              24
#define HINIC_SQ_DB_INFO_TYPE_SHIFT             27

#define HINIC_SQ_DB_INFO_PI_HI_MASK             0xFF
#define HINIC_SQ_DB_INFO_QID_MASK               0x3FF
#define HINIC_SQ_DB_INFO_PATH_MASK              0x1
#define HINIC_SQ_DB_INFO_COS_MASK               0x7
#define HINIC_SQ_DB_INFO_TYPE_MASK              0x1F

#define HINIC_SQ_DB_INFO_SET(val, member)       \
		(((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \
		 << HINIC_SQ_DB_INFO_##member##_SHIFT)

#define HINIC_SQ_WQEBB_SIZE                     64
#define HINIC_RQ_WQEBB_SIZE                     32

#define HINIC_SQ_PAGE_SIZE                      SZ_4K
#define HINIC_RQ_PAGE_SIZE                      SZ_4K

#define HINIC_SQ_DEPTH                          SZ_4K
#define HINIC_RQ_DEPTH                          SZ_4K

/* In any change to HINIC_RX_BUF_SZ, HINIC_RX_BUF_SZ_IDX must be changed */
#define HINIC_RX_BUF_SZ                         2048
#define HINIC_RX_BUF_SZ_IDX			HINIC_RX_BUF_SZ_2048_IDX

#define HINIC_MIN_TX_WQE_SIZE(wq)               \
		ALIGN(HINIC_SQ_WQE_SIZE(1), (wq)->wqebb_size)

#define HINIC_MIN_TX_NUM_WQEBBS(sq)             \
		(HINIC_MIN_TX_WQE_SIZE((sq)->wq) / (sq)->wq->wqebb_size)

enum hinic_rx_buf_sz_idx {
	HINIC_RX_BUF_SZ_32_IDX,
	HINIC_RX_BUF_SZ_64_IDX,
	HINIC_RX_BUF_SZ_96_IDX,
	HINIC_RX_BUF_SZ_128_IDX,
	HINIC_RX_BUF_SZ_192_IDX,
	HINIC_RX_BUF_SZ_256_IDX,
	HINIC_RX_BUF_SZ_384_IDX,
	HINIC_RX_BUF_SZ_512_IDX,
	HINIC_RX_BUF_SZ_768_IDX,
	HINIC_RX_BUF_SZ_1024_IDX,
	HINIC_RX_BUF_SZ_1536_IDX,
	HINIC_RX_BUF_SZ_2048_IDX,
	HINIC_RX_BUF_SZ_3072_IDX,
	HINIC_RX_BUF_SZ_4096_IDX,
	HINIC_RX_BUF_SZ_8192_IDX,
	HINIC_RX_BUF_SZ_16384_IDX,
};

struct hinic_sq {
	struct hinic_hwif       *hwif;

	struct hinic_wq         *wq;

	u32                     irq;
	u16                     msix_entry;

	void                    *hw_ci_addr;
	dma_addr_t              hw_ci_dma_addr;

	void __iomem            *db_base;

	struct sk_buff          **saved_skb;
};

struct hinic_rq {
	struct hinic_hwif       *hwif;

	struct hinic_wq         *wq;

	u32                     irq;
	u16                     msix_entry;

	size_t                  buf_sz;

	struct sk_buff          **saved_skb;

	struct hinic_rq_cqe     **cqe;
	dma_addr_t              *cqe_dma;

	u16                     *pi_virt_addr;
	dma_addr_t              pi_dma_addr;
};

struct hinic_qp {
	struct hinic_sq         sq;
	struct hinic_rq         rq;

	u16     q_id;
};

void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
			     enum hinic_qp_ctxt_type ctxt_type,
			     u16 num_queues, u16 max_queues);

void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
			   struct hinic_sq *sq, u16 global_qid);

void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
			   struct hinic_rq *rq, u16 global_qid);

int hinic_init_sq(struct hinic_sq *sq, struct hinic_hwif *hwif,
		  struct hinic_wq *wq, struct msix_entry *entry, void *ci_addr,
		  dma_addr_t ci_dma_addr, void __iomem *db_base);

void hinic_clean_sq(struct hinic_sq *sq);

int hinic_init_rq(struct hinic_rq *rq, struct hinic_hwif *hwif,
		  struct hinic_wq *wq, struct msix_entry *entry);

void hinic_clean_rq(struct hinic_rq *rq);

int hinic_get_sq_free_wqebbs(struct hinic_sq *sq);

int hinic_get_rq_free_wqebbs(struct hinic_rq *rq);

void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len);

void hinic_task_set_outter_l3(struct hinic_sq_task *task,
			      enum hinic_l3_offload_type l3_type,
			      u32 network_len);

void hinic_task_set_inner_l3(struct hinic_sq_task *task,
			     enum hinic_l3_offload_type l3_type,
			     u32 network_len);

void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
			      enum hinic_l4_tunnel_type l4_type,
			      u32 tunnel_len);

void hinic_set_cs_inner_l4(struct hinic_sq_task *task,
			   u32 *queue_info,
			   enum hinic_l4_offload_type l4_offload,
			   u32 l4_len, u32 offset);

void hinic_set_tso_inner_l4(struct hinic_sq_task *task,
			    u32 *queue_info,
			    enum hinic_l4_offload_type l4_offload,
			    u32 l4_len,
			    u32 offset, u32 ip_ident, u32 mss);

void hinic_sq_prepare_wqe(struct hinic_sq *sq, u16 prod_idx,
			  struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
			  int nr_sges);

void hinic_sq_write_db(struct hinic_sq *sq, u16 prod_idx, unsigned int wqe_size,
		       unsigned int cos);

struct hinic_sq_wqe *hinic_sq_get_wqe(struct hinic_sq *sq,
				      unsigned int wqe_size, u16 *prod_idx);

void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size);

void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
			struct hinic_sq_wqe *wqe, struct sk_buff *skb,
			unsigned int wqe_size);

struct hinic_sq_wqe *hinic_sq_read_wqe(struct hinic_sq *sq,
				       struct sk_buff **skb,
				       unsigned int wqe_size, u16 *cons_idx);

struct hinic_sq_wqe *hinic_sq_read_wqebb(struct hinic_sq *sq,
					 struct sk_buff **skb,
					 unsigned int *wqe_size, u16 *cons_idx);

void hinic_sq_put_wqe(struct hinic_sq *sq, unsigned int wqe_size);

void hinic_sq_get_sges(struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
		       int nr_sges);

struct hinic_rq_wqe *hinic_rq_get_wqe(struct hinic_rq *rq,
				      unsigned int wqe_size, u16 *prod_idx);

void hinic_rq_write_wqe(struct hinic_rq *rq, u16 prod_idx,
			struct hinic_rq_wqe *wqe, struct sk_buff *skb);

struct hinic_rq_wqe *hinic_rq_read_wqe(struct hinic_rq *rq,
				       unsigned int wqe_size,
				       struct sk_buff **skb, u16 *cons_idx);

struct hinic_rq_wqe *hinic_rq_read_next_wqe(struct hinic_rq *rq,
					    unsigned int wqe_size,
					    struct sk_buff **skb,
					    u16 *cons_idx);

void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
		      unsigned int wqe_size);

void hinic_rq_get_sge(struct hinic_rq *rq, struct hinic_rq_wqe *wqe,
		      u16 cons_idx, struct hinic_sge *sge);

void hinic_rq_prepare_wqe(struct hinic_rq *rq, u16 prod_idx,
			  struct hinic_rq_wqe *wqe, struct hinic_sge *sge);

void hinic_rq_update(struct hinic_rq *rq, u16 prod_idx);

#endif
Commit	Line	Data
c3e79baf AK	1	/*
	2	* Huawei HiNIC PCI Express Linux driver
	3	* Copyright(c) 2017 Huawei Technologies Co., Ltd
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	12	* for more details.
	13	*
	14	*/
	15
	16	#ifndef HINIC_HW_QP_H
	17	#define HINIC_HW_QP_H
	18
00e57a6d	19	#include <linux/kernel.h>
b15a9f37 AK	20	#include <linux/types.h>
b15a9f37 AK	21	#include <linux/sizes.h>
f91090f7 AK	22	#include <linux/pci.h>
	23	#include <linux/skbuff.h>
	24
e2585ea7	25	#include "hinic_common.h"
f91090f7 AK	26	#include "hinic_hw_if.h"
	27	#include "hinic_hw_wqe.h"
	28	#include "hinic_hw_wq.h"
53e7d6fe	29	#include "hinic_hw_qp_ctxt.h"
b15a9f37	30
00e57a6d AK	31	#define HINIC_SQ_DB_INFO_PI_HI_SHIFT 0
	32	#define HINIC_SQ_DB_INFO_QID_SHIFT 8
	33	#define HINIC_SQ_DB_INFO_PATH_SHIFT 23
	34	#define HINIC_SQ_DB_INFO_COS_SHIFT 24
	35	#define HINIC_SQ_DB_INFO_TYPE_SHIFT 27
	36
	37	#define HINIC_SQ_DB_INFO_PI_HI_MASK 0xFF
	38	#define HINIC_SQ_DB_INFO_QID_MASK 0x3FF
	39	#define HINIC_SQ_DB_INFO_PATH_MASK 0x1
	40	#define HINIC_SQ_DB_INFO_COS_MASK 0x7
	41	#define HINIC_SQ_DB_INFO_TYPE_MASK 0x1F
	42
	43	#define HINIC_SQ_DB_INFO_SET(val, member) \
	44	(((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \
	45	<< HINIC_SQ_DB_INFO_##member##_SHIFT)
	46
b15a9f37 AK	47	#define HINIC_SQ_WQEBB_SIZE 64
	48	#define HINIC_RQ_WQEBB_SIZE 32
	49
	50	#define HINIC_SQ_PAGE_SIZE SZ_4K
	51	#define HINIC_RQ_PAGE_SIZE SZ_4K
	52
	53	#define HINIC_SQ_DEPTH SZ_4K
	54	#define HINIC_RQ_DEPTH SZ_4K
	55
cde66f24	56	/* In any change to HINIC_RX_BUF_SZ, HINIC_RX_BUF_SZ_IDX must be changed */
f91090f7	57	#define HINIC_RX_BUF_SZ 2048
cde66f24	58	#define HINIC_RX_BUF_SZ_IDX HINIC_RX_BUF_SZ_2048_IDX
f91090f7	59
00e57a6d AK	60	#define HINIC_MIN_TX_WQE_SIZE(wq) \
	61	ALIGN(HINIC_SQ_WQE_SIZE(1), (wq)->wqebb_size)
	62
	63	#define HINIC_MIN_TX_NUM_WQEBBS(sq) \
	64	(HINIC_MIN_TX_WQE_SIZE((sq)->wq) / (sq)->wq->wqebb_size)
	65
cde66f24 AK	66	enum hinic_rx_buf_sz_idx {
	67	HINIC_RX_BUF_SZ_32_IDX,
	68	HINIC_RX_BUF_SZ_64_IDX,
	69	HINIC_RX_BUF_SZ_96_IDX,
	70	HINIC_RX_BUF_SZ_128_IDX,
	71	HINIC_RX_BUF_SZ_192_IDX,
	72	HINIC_RX_BUF_SZ_256_IDX,
	73	HINIC_RX_BUF_SZ_384_IDX,
	74	HINIC_RX_BUF_SZ_512_IDX,
	75	HINIC_RX_BUF_SZ_768_IDX,
	76	HINIC_RX_BUF_SZ_1024_IDX,
	77	HINIC_RX_BUF_SZ_1536_IDX,
	78	HINIC_RX_BUF_SZ_2048_IDX,
	79	HINIC_RX_BUF_SZ_3072_IDX,
	80	HINIC_RX_BUF_SZ_4096_IDX,
	81	HINIC_RX_BUF_SZ_8192_IDX,
	82	HINIC_RX_BUF_SZ_16384_IDX,
	83	};
	84
c3e79baf	85	struct hinic_sq {
f91090f7 AK	86	struct hinic_hwif *hwif;
	87
	88	struct hinic_wq *wq;
	89
	90	u32 irq;
	91	u16 msix_entry;
	92
	93	void *hw_ci_addr;
	94	dma_addr_t hw_ci_dma_addr;
	95
	96	void __iomem *db_base;
	97
	98	struct sk_buff **saved_skb;
c3e79baf AK	99	};
	100
	101	struct hinic_rq {
f91090f7 AK	102	struct hinic_hwif *hwif;
	103
	104	struct hinic_wq *wq;
	105
	106	u32 irq;
	107	u16 msix_entry;
	108
	109	size_t buf_sz;
	110
	111	struct sk_buff **saved_skb;
	112
	113	struct hinic_rq_cqe **cqe;
	114	dma_addr_t *cqe_dma;
	115
	116	u16 *pi_virt_addr;
	117	dma_addr_t pi_dma_addr;
c3e79baf AK	118	};
	119
	120	struct hinic_qp {
	121	struct hinic_sq sq;
	122	struct hinic_rq rq;
b15a9f37 AK	123
b15a9f37 AK	124	u16 q_id;
c3e79baf AK	125	};
c3e79baf AK	126
53e7d6fe AK	127	void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
	128	enum hinic_qp_ctxt_type ctxt_type,
	129	u16 num_queues, u16 max_queues);
	130
	131	void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
	132	struct hinic_sq *sq, u16 global_qid);
	133
	134	void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
	135	struct hinic_rq *rq, u16 global_qid);
	136
f91090f7 AK	137	int hinic_init_sq(struct hinic_sq sq, struct hinic_hwif hwif,
	138	struct hinic_wq wq, struct msix_entry entry, void *ci_addr,
	139	dma_addr_t ci_dma_addr, void __iomem *db_base);
	140
	141	void hinic_clean_sq(struct hinic_sq *sq);
	142
	143	int hinic_init_rq(struct hinic_rq rq, struct hinic_hwif hwif,
	144	struct hinic_wq wq, struct msix_entry entry);
	145
	146	void hinic_clean_rq(struct hinic_rq *rq);
	147
00e57a6d AK	148	int hinic_get_sq_free_wqebbs(struct hinic_sq *sq);
00e57a6d AK	149
e2585ea7 AK	150	int hinic_get_rq_free_wqebbs(struct hinic_rq *rq);
e2585ea7 AK	151
cc18a754 ZC	152	void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len);
	153
	154	void hinic_task_set_outter_l3(struct hinic_sq_task *task,
	155	enum hinic_l3_offload_type l3_type,
	156	u32 network_len);
	157
	158	void hinic_task_set_inner_l3(struct hinic_sq_task *task,
	159	enum hinic_l3_offload_type l3_type,
	160	u32 network_len);
	161
	162	void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
6e29464b	163	enum hinic_l4_tunnel_type l4_type,
cc18a754 ZC	164	u32 tunnel_len);
	165
	166	void hinic_set_cs_inner_l4(struct hinic_sq_task *task,
	167	u32 *queue_info,
	168	enum hinic_l4_offload_type l4_offload,
	169	u32 l4_len, u32 offset);
	170
	171	void hinic_set_tso_inner_l4(struct hinic_sq_task *task,
	172	u32 *queue_info,
	173	enum hinic_l4_offload_type l4_offload,
	174	u32 l4_len,
	175	u32 offset, u32 ip_ident, u32 mss);
	176
00e57a6d AK	177	void hinic_sq_prepare_wqe(struct hinic_sq *sq, u16 prod_idx,
	178	struct hinic_sq_wqe wqe, struct hinic_sge sges,
	179	int nr_sges);
	180
	181	void hinic_sq_write_db(struct hinic_sq *sq, u16 prod_idx, unsigned int wqe_size,
	182	unsigned int cos);
	183
	184	struct hinic_sq_wqe hinic_sq_get_wqe(struct hinic_sq sq,
	185	unsigned int wqe_size, u16 *prod_idx);
	186
cc18a754 ZC	187	void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size);
cc18a754 ZC	188
00e57a6d AK	189	void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
	190	struct hinic_sq_wqe wqe, struct sk_buff skb,
	191	unsigned int wqe_size);
	192
	193	struct hinic_sq_wqe hinic_sq_read_wqe(struct hinic_sq sq,
	194	struct sk_buff **skb,
9c2956d2 ZC	195	unsigned int wqe_size, u16 *cons_idx);
	196
	197	struct hinic_sq_wqe hinic_sq_read_wqebb(struct hinic_sq sq,
	198	struct sk_buff **skb,
	199	unsigned int wqe_size, u16 cons_idx);
00e57a6d AK	200
	201	void hinic_sq_put_wqe(struct hinic_sq *sq, unsigned int wqe_size);
	202
	203	void hinic_sq_get_sges(struct hinic_sq_wqe wqe, struct hinic_sge sges,
	204	int nr_sges);
	205
e2585ea7 AK	206	struct hinic_rq_wqe hinic_rq_get_wqe(struct hinic_rq rq,
	207	unsigned int wqe_size, u16 *prod_idx);
	208
	209	void hinic_rq_write_wqe(struct hinic_rq *rq, u16 prod_idx,
	210	struct hinic_rq_wqe wqe, struct sk_buff skb);
	211
	212	struct hinic_rq_wqe hinic_rq_read_wqe(struct hinic_rq rq,
	213	unsigned int wqe_size,
	214	struct sk_buff *skb, u16 cons_idx);
	215
	216	struct hinic_rq_wqe hinic_rq_read_next_wqe(struct hinic_rq rq,
	217	unsigned int wqe_size,
	218	struct sk_buff **skb,
	219	u16 *cons_idx);
	220
	221	void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
	222	unsigned int wqe_size);
	223
	224	void hinic_rq_get_sge(struct hinic_rq rq, struct hinic_rq_wqe wqe,
	225	u16 cons_idx, struct hinic_sge *sge);
	226
	227	void hinic_rq_prepare_wqe(struct hinic_rq *rq, u16 prod_idx,
	228	struct hinic_rq_wqe wqe, struct hinic_sge sge);
	229
	230	void hinic_rq_update(struct hinic_rq *rq, u16 prod_idx);
	231
c3e79baf	232	#endif