[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / huawei / hinic / hinic_hw_qp.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Huawei HiNIC PCI Express Linux driver
 * Copyright(c) 2017 Huawei Technologies Co., Ltd
 */

#ifndef HINIC_HW_QP_H
#define HINIC_HW_QP_H

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/sizes.h>
#include <linux/pci.h>
#include <linux/skbuff.h>

#include "hinic_common.h"
#include "hinic_hw_if.h"
#include "hinic_hw_wqe.h"
#include "hinic_hw_wq.h"
#include "hinic_hw_qp_ctxt.h"

#define HINIC_SQ_DB_INFO_PI_HI_SHIFT            0
#define HINIC_SQ_DB_INFO_QID_SHIFT              8
#define HINIC_SQ_DB_INFO_PATH_SHIFT             23
#define HINIC_SQ_DB_INFO_COS_SHIFT              24
#define HINIC_SQ_DB_INFO_TYPE_SHIFT             27

#define HINIC_SQ_DB_INFO_PI_HI_MASK             0xFF
#define HINIC_SQ_DB_INFO_QID_MASK               0x3FF
#define HINIC_SQ_DB_INFO_PATH_MASK              0x1
#define HINIC_SQ_DB_INFO_COS_MASK               0x7
#define HINIC_SQ_DB_INFO_TYPE_MASK              0x1F

#define HINIC_SQ_DB_INFO_SET(val, member)       \
		(((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \
		 << HINIC_SQ_DB_INFO_##member##_SHIFT)

#define HINIC_SQ_WQEBB_SIZE                     64
#define HINIC_RQ_WQEBB_SIZE                     32

#define HINIC_SQ_PAGE_SIZE                      SZ_4K
#define HINIC_RQ_PAGE_SIZE                      SZ_4K

#define HINIC_SQ_DEPTH                          SZ_4K
#define HINIC_RQ_DEPTH                          SZ_4K

/* In any change to HINIC_RX_BUF_SZ, HINIC_RX_BUF_SZ_IDX must be changed */
#define HINIC_RX_BUF_SZ                         2048
#define HINIC_RX_BUF_SZ_IDX			HINIC_RX_BUF_SZ_2048_IDX

#define HINIC_MIN_TX_WQE_SIZE(wq)               \
		ALIGN(HINIC_SQ_WQE_SIZE(1), (wq)->wqebb_size)

#define HINIC_MIN_TX_NUM_WQEBBS(sq)             \
		(HINIC_MIN_TX_WQE_SIZE((sq)->wq) / (sq)->wq->wqebb_size)

enum hinic_rx_buf_sz_idx {
	HINIC_RX_BUF_SZ_32_IDX,
	HINIC_RX_BUF_SZ_64_IDX,
	HINIC_RX_BUF_SZ_96_IDX,
	HINIC_RX_BUF_SZ_128_IDX,
	HINIC_RX_BUF_SZ_192_IDX,
	HINIC_RX_BUF_SZ_256_IDX,
	HINIC_RX_BUF_SZ_384_IDX,
	HINIC_RX_BUF_SZ_512_IDX,
	HINIC_RX_BUF_SZ_768_IDX,
	HINIC_RX_BUF_SZ_1024_IDX,
	HINIC_RX_BUF_SZ_1536_IDX,
	HINIC_RX_BUF_SZ_2048_IDX,
	HINIC_RX_BUF_SZ_3072_IDX,
	HINIC_RX_BUF_SZ_4096_IDX,
	HINIC_RX_BUF_SZ_8192_IDX,
	HINIC_RX_BUF_SZ_16384_IDX,
};

struct hinic_sq {
	struct hinic_hwif       *hwif;

	struct hinic_wq         *wq;

	u32                     irq;
	u16                     msix_entry;

	void                    *hw_ci_addr;
	dma_addr_t              hw_ci_dma_addr;

	void __iomem            *db_base;

	struct sk_buff          **saved_skb;
};

struct hinic_rq {
	struct hinic_hwif       *hwif;

	struct hinic_wq         *wq;

	u32                     irq;
	u16                     msix_entry;

	size_t                  buf_sz;

	struct sk_buff          **saved_skb;

	struct hinic_rq_cqe     **cqe;
	dma_addr_t              *cqe_dma;

	u16                     *pi_virt_addr;
	dma_addr_t              pi_dma_addr;
};

struct hinic_qp {
	struct hinic_sq         sq;
	struct hinic_rq         rq;

	u16     q_id;
};

void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
			     enum hinic_qp_ctxt_type ctxt_type,
			     u16 num_queues, u16 max_queues);

void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
			   struct hinic_sq *sq, u16 global_qid);

void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
			   struct hinic_rq *rq, u16 global_qid);

int hinic_init_sq(struct hinic_sq *sq, struct hinic_hwif *hwif,
		  struct hinic_wq *wq, struct msix_entry *entry, void *ci_addr,
		  dma_addr_t ci_dma_addr, void __iomem *db_base);

void hinic_clean_sq(struct hinic_sq *sq);

int hinic_init_rq(struct hinic_rq *rq, struct hinic_hwif *hwif,
		  struct hinic_wq *wq, struct msix_entry *entry);

void hinic_clean_rq(struct hinic_rq *rq);

int hinic_get_sq_free_wqebbs(struct hinic_sq *sq);

int hinic_get_rq_free_wqebbs(struct hinic_rq *rq);

void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len);

void hinic_task_set_outter_l3(struct hinic_sq_task *task,
			      enum hinic_l3_offload_type l3_type,
			      u32 network_len);

void hinic_task_set_inner_l3(struct hinic_sq_task *task,
			     enum hinic_l3_offload_type l3_type,
			     u32 network_len);

void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
			      enum hinic_l4_tunnel_type l4_type,
			      u32 tunnel_len);

void hinic_set_cs_inner_l4(struct hinic_sq_task *task,
			   u32 *queue_info,
			   enum hinic_l4_offload_type l4_offload,
			   u32 l4_len, u32 offset);

void hinic_set_tso_inner_l4(struct hinic_sq_task *task,
			    u32 *queue_info,
			    enum hinic_l4_offload_type l4_offload,
			    u32 l4_len,
			    u32 offset, u32 ip_ident, u32 mss);

void hinic_sq_prepare_wqe(struct hinic_sq *sq, u16 prod_idx,
			  struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
			  int nr_sges);

void hinic_sq_write_db(struct hinic_sq *sq, u16 prod_idx, unsigned int wqe_size,
		       unsigned int cos);

struct hinic_sq_wqe *hinic_sq_get_wqe(struct hinic_sq *sq,
				      unsigned int wqe_size, u16 *prod_idx);

void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size);

void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
			struct hinic_sq_wqe *wqe, struct sk_buff *skb,
			unsigned int wqe_size);

struct hinic_sq_wqe *hinic_sq_read_wqe(struct hinic_sq *sq,
				       struct sk_buff **skb,
				       unsigned int wqe_size, u16 *cons_idx);

struct hinic_sq_wqe *hinic_sq_read_wqebb(struct hinic_sq *sq,
					 struct sk_buff **skb,
					 unsigned int *wqe_size, u16 *cons_idx);

void hinic_sq_put_wqe(struct hinic_sq *sq, unsigned int wqe_size);

void hinic_sq_get_sges(struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
		       int nr_sges);

struct hinic_rq_wqe *hinic_rq_get_wqe(struct hinic_rq *rq,
				      unsigned int wqe_size, u16 *prod_idx);

void hinic_rq_write_wqe(struct hinic_rq *rq, u16 prod_idx,
			struct hinic_rq_wqe *wqe, struct sk_buff *skb);

struct hinic_rq_wqe *hinic_rq_read_wqe(struct hinic_rq *rq,
				       unsigned int wqe_size,
				       struct sk_buff **skb, u16 *cons_idx);

struct hinic_rq_wqe *hinic_rq_read_next_wqe(struct hinic_rq *rq,
					    unsigned int wqe_size,
					    struct sk_buff **skb,
					    u16 *cons_idx);

void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
		      unsigned int wqe_size);

void hinic_rq_get_sge(struct hinic_rq *rq, struct hinic_rq_wqe *wqe,
		      u16 cons_idx, struct hinic_sge *sge);

void hinic_rq_prepare_wqe(struct hinic_rq *rq, u16 prod_idx,
			  struct hinic_rq_wqe *wqe, struct hinic_sge *sge);

void hinic_rq_update(struct hinic_rq *rq, u16 prod_idx);

#endif
Commit	Line	Data
2025cf9e	1	/* SPDX-License-Identifier: GPL-2.0-only */
c3e79baf AK	2	/*
	3	* Huawei HiNIC PCI Express Linux driver
	4	* Copyright(c) 2017 Huawei Technologies Co., Ltd
c3e79baf AK	5	*/
	6
	7	#ifndef HINIC_HW_QP_H
	8	#define HINIC_HW_QP_H
	9
00e57a6d	10	#include <linux/kernel.h>
b15a9f37 AK	11	#include <linux/types.h>
b15a9f37 AK	12	#include <linux/sizes.h>
f91090f7 AK	13	#include <linux/pci.h>
	14	#include <linux/skbuff.h>
	15
e2585ea7	16	#include "hinic_common.h"
f91090f7 AK	17	#include "hinic_hw_if.h"
	18	#include "hinic_hw_wqe.h"
	19	#include "hinic_hw_wq.h"
53e7d6fe	20	#include "hinic_hw_qp_ctxt.h"
b15a9f37	21
00e57a6d AK	22	#define HINIC_SQ_DB_INFO_PI_HI_SHIFT 0
	23	#define HINIC_SQ_DB_INFO_QID_SHIFT 8
	24	#define HINIC_SQ_DB_INFO_PATH_SHIFT 23
	25	#define HINIC_SQ_DB_INFO_COS_SHIFT 24
	26	#define HINIC_SQ_DB_INFO_TYPE_SHIFT 27
	27
	28	#define HINIC_SQ_DB_INFO_PI_HI_MASK 0xFF
	29	#define HINIC_SQ_DB_INFO_QID_MASK 0x3FF
	30	#define HINIC_SQ_DB_INFO_PATH_MASK 0x1
	31	#define HINIC_SQ_DB_INFO_COS_MASK 0x7
	32	#define HINIC_SQ_DB_INFO_TYPE_MASK 0x1F
	33
	34	#define HINIC_SQ_DB_INFO_SET(val, member) \
	35	(((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \
	36	<< HINIC_SQ_DB_INFO_##member##_SHIFT)
	37
b15a9f37 AK	38	#define HINIC_SQ_WQEBB_SIZE 64
	39	#define HINIC_RQ_WQEBB_SIZE 32
	40
	41	#define HINIC_SQ_PAGE_SIZE SZ_4K
	42	#define HINIC_RQ_PAGE_SIZE SZ_4K
	43
	44	#define HINIC_SQ_DEPTH SZ_4K
	45	#define HINIC_RQ_DEPTH SZ_4K
	46
cde66f24	47	/* In any change to HINIC_RX_BUF_SZ, HINIC_RX_BUF_SZ_IDX must be changed */
f91090f7	48	#define HINIC_RX_BUF_SZ 2048
cde66f24	49	#define HINIC_RX_BUF_SZ_IDX HINIC_RX_BUF_SZ_2048_IDX
f91090f7	50
00e57a6d AK	51	#define HINIC_MIN_TX_WQE_SIZE(wq) \
	52	ALIGN(HINIC_SQ_WQE_SIZE(1), (wq)->wqebb_size)
	53
	54	#define HINIC_MIN_TX_NUM_WQEBBS(sq) \
	55	(HINIC_MIN_TX_WQE_SIZE((sq)->wq) / (sq)->wq->wqebb_size)
	56
cde66f24 AK	57	enum hinic_rx_buf_sz_idx {
	58	HINIC_RX_BUF_SZ_32_IDX,
	59	HINIC_RX_BUF_SZ_64_IDX,
	60	HINIC_RX_BUF_SZ_96_IDX,
	61	HINIC_RX_BUF_SZ_128_IDX,
	62	HINIC_RX_BUF_SZ_192_IDX,
	63	HINIC_RX_BUF_SZ_256_IDX,
	64	HINIC_RX_BUF_SZ_384_IDX,
	65	HINIC_RX_BUF_SZ_512_IDX,
	66	HINIC_RX_BUF_SZ_768_IDX,
	67	HINIC_RX_BUF_SZ_1024_IDX,
	68	HINIC_RX_BUF_SZ_1536_IDX,
	69	HINIC_RX_BUF_SZ_2048_IDX,
	70	HINIC_RX_BUF_SZ_3072_IDX,
	71	HINIC_RX_BUF_SZ_4096_IDX,
	72	HINIC_RX_BUF_SZ_8192_IDX,
	73	HINIC_RX_BUF_SZ_16384_IDX,
	74	};
	75
c3e79baf	76	struct hinic_sq {
f91090f7 AK	77	struct hinic_hwif *hwif;
	78
	79	struct hinic_wq *wq;
	80
	81	u32 irq;
	82	u16 msix_entry;
	83
	84	void *hw_ci_addr;
	85	dma_addr_t hw_ci_dma_addr;
	86
	87	void __iomem *db_base;
	88
	89	struct sk_buff **saved_skb;
c3e79baf AK	90	};
	91
	92	struct hinic_rq {
f91090f7 AK	93	struct hinic_hwif *hwif;
	94
	95	struct hinic_wq *wq;
	96
	97	u32 irq;
	98	u16 msix_entry;
	99
	100	size_t buf_sz;
	101
	102	struct sk_buff **saved_skb;
	103
	104	struct hinic_rq_cqe **cqe;
	105	dma_addr_t *cqe_dma;
	106
	107	u16 *pi_virt_addr;
	108	dma_addr_t pi_dma_addr;
c3e79baf AK	109	};
	110
	111	struct hinic_qp {
	112	struct hinic_sq sq;
	113	struct hinic_rq rq;
b15a9f37 AK	114
b15a9f37 AK	115	u16 q_id;
c3e79baf AK	116	};
c3e79baf AK	117
53e7d6fe AK	118	void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
	119	enum hinic_qp_ctxt_type ctxt_type,
	120	u16 num_queues, u16 max_queues);
	121
	122	void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
	123	struct hinic_sq *sq, u16 global_qid);
	124
	125	void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
	126	struct hinic_rq *rq, u16 global_qid);
	127
f91090f7 AK	128	int hinic_init_sq(struct hinic_sq sq, struct hinic_hwif hwif,
	129	struct hinic_wq wq, struct msix_entry entry, void *ci_addr,
	130	dma_addr_t ci_dma_addr, void __iomem *db_base);
	131
	132	void hinic_clean_sq(struct hinic_sq *sq);
	133
	134	int hinic_init_rq(struct hinic_rq rq, struct hinic_hwif hwif,
	135	struct hinic_wq wq, struct msix_entry entry);
	136
	137	void hinic_clean_rq(struct hinic_rq *rq);
	138
00e57a6d AK	139	int hinic_get_sq_free_wqebbs(struct hinic_sq *sq);
00e57a6d AK	140
e2585ea7 AK	141	int hinic_get_rq_free_wqebbs(struct hinic_rq *rq);
e2585ea7 AK	142
cc18a754 ZC	143	void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len);
	144
	145	void hinic_task_set_outter_l3(struct hinic_sq_task *task,
	146	enum hinic_l3_offload_type l3_type,
	147	u32 network_len);
	148
	149	void hinic_task_set_inner_l3(struct hinic_sq_task *task,
	150	enum hinic_l3_offload_type l3_type,
	151	u32 network_len);
	152
	153	void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
6e29464b	154	enum hinic_l4_tunnel_type l4_type,
cc18a754 ZC	155	u32 tunnel_len);
	156
	157	void hinic_set_cs_inner_l4(struct hinic_sq_task *task,
	158	u32 *queue_info,
	159	enum hinic_l4_offload_type l4_offload,
	160	u32 l4_len, u32 offset);
	161
	162	void hinic_set_tso_inner_l4(struct hinic_sq_task *task,
	163	u32 *queue_info,
	164	enum hinic_l4_offload_type l4_offload,
	165	u32 l4_len,
	166	u32 offset, u32 ip_ident, u32 mss);
	167
00e57a6d AK	168	void hinic_sq_prepare_wqe(struct hinic_sq *sq, u16 prod_idx,
	169	struct hinic_sq_wqe wqe, struct hinic_sge sges,
	170	int nr_sges);
	171
	172	void hinic_sq_write_db(struct hinic_sq *sq, u16 prod_idx, unsigned int wqe_size,
	173	unsigned int cos);
	174
	175	struct hinic_sq_wqe hinic_sq_get_wqe(struct hinic_sq sq,
	176	unsigned int wqe_size, u16 *prod_idx);
	177
cc18a754 ZC	178	void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size);
cc18a754 ZC	179
00e57a6d AK	180	void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
	181	struct hinic_sq_wqe wqe, struct sk_buff skb,
	182	unsigned int wqe_size);
	183
	184	struct hinic_sq_wqe hinic_sq_read_wqe(struct hinic_sq sq,
	185	struct sk_buff **skb,
9c2956d2 ZC	186	unsigned int wqe_size, u16 *cons_idx);
	187
	188	struct hinic_sq_wqe hinic_sq_read_wqebb(struct hinic_sq sq,
	189	struct sk_buff **skb,
	190	unsigned int wqe_size, u16 cons_idx);
00e57a6d AK	191
	192	void hinic_sq_put_wqe(struct hinic_sq *sq, unsigned int wqe_size);
	193
	194	void hinic_sq_get_sges(struct hinic_sq_wqe wqe, struct hinic_sge sges,
	195	int nr_sges);
	196
e2585ea7 AK	197	struct hinic_rq_wqe hinic_rq_get_wqe(struct hinic_rq rq,
	198	unsigned int wqe_size, u16 *prod_idx);
	199
	200	void hinic_rq_write_wqe(struct hinic_rq *rq, u16 prod_idx,
	201	struct hinic_rq_wqe wqe, struct sk_buff skb);
	202
	203	struct hinic_rq_wqe hinic_rq_read_wqe(struct hinic_rq rq,
	204	unsigned int wqe_size,
	205	struct sk_buff *skb, u16 cons_idx);
	206
	207	struct hinic_rq_wqe hinic_rq_read_next_wqe(struct hinic_rq rq,
	208	unsigned int wqe_size,
	209	struct sk_buff **skb,
	210	u16 *cons_idx);
	211
	212	void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
	213	unsigned int wqe_size);
	214
	215	void hinic_rq_get_sge(struct hinic_rq rq, struct hinic_rq_wqe wqe,
	216	u16 cons_idx, struct hinic_sge *sge);
	217
	218	void hinic_rq_prepare_wqe(struct hinic_rq *rq, u16 prod_idx,
	219	struct hinic_rq_wqe wqe, struct hinic_sge sge);
	220
	221	void hinic_rq_update(struct hinic_rq *rq, u16 prod_idx);
	222
c3e79baf	223	#endif