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2025cf9e | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
25a3ba61 AK |
2 | /* |
3 | * Huawei HiNIC PCI Express Linux driver | |
4 | * Copyright(c) 2017 Huawei Technologies Co., Ltd | |
25a3ba61 AK |
5 | */ |
6 | ||
7 | #ifndef HINIC_PORT_H | |
8 | #define HINIC_PORT_H | |
9 | ||
10 | #include <linux/types.h> | |
11 | #include <linux/etherdevice.h> | |
c4d06d2d | 12 | #include <linux/bitops.h> |
25a3ba61 AK |
13 | |
14 | #include "hinic_dev.h" | |
15 | ||
c4d06d2d AK |
16 | enum hinic_rx_mode { |
17 | HINIC_RX_MODE_UC = BIT(0), | |
18 | HINIC_RX_MODE_MC = BIT(1), | |
19 | HINIC_RX_MODE_BC = BIT(2), | |
20 | HINIC_RX_MODE_MC_ALL = BIT(3), | |
21 | HINIC_RX_MODE_PROMISC = BIT(4), | |
22 | }; | |
23 | ||
24 | enum hinic_port_link_state { | |
25 | HINIC_LINK_STATE_DOWN, | |
26 | HINIC_LINK_STATE_UP, | |
27 | }; | |
28 | ||
29 | enum hinic_port_state { | |
30 | HINIC_PORT_DISABLE = 0, | |
31 | HINIC_PORT_ENABLE = 3, | |
32 | }; | |
33 | ||
e2585ea7 AK |
34 | enum hinic_func_port_state { |
35 | HINIC_FUNC_PORT_DISABLE = 0, | |
36 | HINIC_FUNC_PORT_ENABLE = 2, | |
37 | }; | |
38 | ||
edd384f6 AK |
39 | enum hinic_autoneg_cap { |
40 | HINIC_AUTONEG_UNSUPPORTED, | |
41 | HINIC_AUTONEG_SUPPORTED, | |
42 | }; | |
43 | ||
44 | enum hinic_autoneg_state { | |
45 | HINIC_AUTONEG_DISABLED, | |
46 | HINIC_AUTONEG_ACTIVE, | |
47 | }; | |
48 | ||
49 | enum hinic_duplex { | |
50 | HINIC_DUPLEX_HALF, | |
51 | HINIC_DUPLEX_FULL, | |
52 | }; | |
53 | ||
54 | enum hinic_speed { | |
55 | HINIC_SPEED_10MB_LINK = 0, | |
56 | HINIC_SPEED_100MB_LINK, | |
57 | HINIC_SPEED_1000MB_LINK, | |
58 | HINIC_SPEED_10GB_LINK, | |
59 | HINIC_SPEED_25GB_LINK, | |
60 | HINIC_SPEED_40GB_LINK, | |
61 | HINIC_SPEED_100GB_LINK, | |
62 | ||
63 | HINIC_SPEED_UNKNOWN = 0xFF, | |
64 | }; | |
65 | ||
cc18a754 ZC |
66 | enum hinic_tso_state { |
67 | HINIC_TSO_DISABLE = 0, | |
68 | HINIC_TSO_ENABLE = 1, | |
69 | }; | |
70 | ||
25a3ba61 AK |
71 | struct hinic_port_mac_cmd { |
72 | u8 status; | |
73 | u8 version; | |
74 | u8 rsvd0[6]; | |
75 | ||
76 | u16 func_idx; | |
77 | u16 vlan_id; | |
78 | u16 rsvd1; | |
79 | unsigned char mac[ETH_ALEN]; | |
80 | }; | |
81 | ||
82 | struct hinic_port_mtu_cmd { | |
83 | u8 status; | |
84 | u8 version; | |
85 | u8 rsvd0[6]; | |
86 | ||
87 | u16 func_idx; | |
88 | u16 rsvd1; | |
89 | u32 mtu; | |
90 | }; | |
91 | ||
92 | struct hinic_port_vlan_cmd { | |
93 | u8 status; | |
94 | u8 version; | |
95 | u8 rsvd0[6]; | |
96 | ||
97 | u16 func_idx; | |
98 | u16 vlan_id; | |
99 | }; | |
100 | ||
c4d06d2d AK |
101 | struct hinic_port_rx_mode_cmd { |
102 | u8 status; | |
103 | u8 version; | |
104 | u8 rsvd0[6]; | |
105 | ||
106 | u16 func_idx; | |
107 | u16 rsvd; | |
108 | u32 rx_mode; | |
109 | }; | |
110 | ||
111 | struct hinic_port_link_cmd { | |
112 | u8 status; | |
113 | u8 version; | |
114 | u8 rsvd0[6]; | |
115 | ||
116 | u16 func_idx; | |
117 | u8 state; | |
118 | u8 rsvd1; | |
119 | }; | |
120 | ||
121 | struct hinic_port_state_cmd { | |
122 | u8 status; | |
123 | u8 version; | |
124 | u8 rsvd0[6]; | |
125 | ||
126 | u8 state; | |
127 | u8 rsvd1[3]; | |
128 | }; | |
129 | ||
130 | struct hinic_port_link_status { | |
131 | u8 status; | |
132 | u8 version; | |
133 | u8 rsvd0[6]; | |
134 | ||
135 | u16 rsvd1; | |
136 | u8 link; | |
137 | u8 rsvd2; | |
138 | }; | |
139 | ||
e2585ea7 AK |
140 | struct hinic_port_func_state_cmd { |
141 | u8 status; | |
142 | u8 version; | |
143 | u8 rsvd0[6]; | |
144 | ||
145 | u16 func_idx; | |
146 | u16 rsvd1; | |
147 | u8 state; | |
148 | u8 rsvd2[3]; | |
149 | }; | |
150 | ||
edd384f6 AK |
151 | struct hinic_port_cap { |
152 | u8 status; | |
153 | u8 version; | |
154 | u8 rsvd0[6]; | |
155 | ||
156 | u16 func_idx; | |
157 | u16 rsvd1; | |
158 | u8 port_type; | |
159 | u8 autoneg_cap; | |
160 | u8 autoneg_state; | |
161 | u8 duplex; | |
162 | u8 speed; | |
163 | u8 rsvd2[3]; | |
164 | }; | |
165 | ||
cc18a754 ZC |
166 | struct hinic_tso_config { |
167 | u8 status; | |
168 | u8 version; | |
169 | u8 rsvd0[6]; | |
170 | ||
171 | u16 func_id; | |
172 | u16 rsvd1; | |
173 | u8 tso_en; | |
174 | u8 resv2[3]; | |
175 | }; | |
176 | ||
4a61abb1 XC |
177 | struct hinic_checksum_offload { |
178 | u8 status; | |
179 | u8 version; | |
180 | u8 rsvd0[6]; | |
181 | ||
182 | u16 func_id; | |
183 | u16 rsvd1; | |
184 | u32 rx_csum_offload; | |
185 | }; | |
25a3ba61 AK |
186 | int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr, |
187 | u16 vlan_id); | |
188 | ||
189 | int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr, | |
190 | u16 vlan_id); | |
191 | ||
192 | int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr); | |
193 | ||
194 | int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu); | |
195 | ||
196 | int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id); | |
197 | ||
198 | int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id); | |
199 | ||
c4d06d2d AK |
200 | int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode); |
201 | ||
202 | int hinic_port_link_state(struct hinic_dev *nic_dev, | |
203 | enum hinic_port_link_state *link_state); | |
204 | ||
205 | int hinic_port_set_state(struct hinic_dev *nic_dev, | |
206 | enum hinic_port_state state); | |
207 | ||
e2585ea7 AK |
208 | int hinic_port_set_func_state(struct hinic_dev *nic_dev, |
209 | enum hinic_func_port_state state); | |
210 | ||
edd384f6 AK |
211 | int hinic_port_get_cap(struct hinic_dev *nic_dev, |
212 | struct hinic_port_cap *port_cap); | |
213 | ||
cc18a754 ZC |
214 | int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state); |
215 | ||
4a61abb1 | 216 | int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en); |
25a3ba61 | 217 | #endif |