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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
f5e261e6 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
d9c76f99 | 55 | #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */ |
ff10e13c CW |
56 | #define E1000_BASE1000T_STATUS 10 |
57 | #define E1000_IDLE_ERROR_COUNT_MASK 0xFF | |
58 | #define E1000_RECEIVE_ERROR_COUNTER 21 | |
59 | #define E1000_RECEIVE_ERROR_MAX 0xFFFF | |
bc7f75fa | 60 | |
4662e82b BA |
61 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
62 | ||
bc7f75fa AK |
63 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
64 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
65 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 66 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
67 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
68 | u16 words, u16 *data); | |
69 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
70 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
71 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
72 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
caaddaf8 | 73 | static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
4662e82b BA |
74 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
75 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 76 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
17f208de | 77 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
1b98c2bb BA |
78 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); |
79 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); | |
80 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); | |
77996d1d BA |
81 | static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active); |
82 | static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active); | |
bc7f75fa AK |
83 | |
84 | /** | |
85 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
86 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
87 | **/ |
88 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
89 | { | |
90 | struct e1000_phy_info *phy = &hw->phy; | |
91 | s32 ret_val; | |
92 | ||
318a94d6 | 93 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
94 | phy->type = e1000_phy_none; |
95 | return 0; | |
96 | } | |
97 | ||
98 | phy->addr = 1; | |
99 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
100 | phy->reset_delay_us = 100; | |
101 | ||
17f208de BA |
102 | phy->ops.power_up = e1000_power_up_phy_copper; |
103 | phy->ops.power_down = e1000_power_down_phy_copper_82571; | |
104 | ||
bc7f75fa AK |
105 | switch (hw->mac.type) { |
106 | case e1000_82571: | |
107 | case e1000_82572: | |
108 | phy->type = e1000_phy_igp_2; | |
109 | break; | |
110 | case e1000_82573: | |
111 | phy->type = e1000_phy_m88; | |
112 | break; | |
4662e82b | 113 | case e1000_82574: |
8c81c9c3 | 114 | case e1000_82583: |
4662e82b | 115 | phy->type = e1000_phy_bm; |
1b98c2bb BA |
116 | phy->ops.acquire = e1000_get_hw_semaphore_82574; |
117 | phy->ops.release = e1000_put_hw_semaphore_82574; | |
77996d1d BA |
118 | phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; |
119 | phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; | |
4662e82b | 120 | break; |
bc7f75fa AK |
121 | default: |
122 | return -E1000_ERR_PHY; | |
123 | break; | |
124 | } | |
125 | ||
126 | /* This can only be done after all function pointers are setup. */ | |
127 | ret_val = e1000_get_phy_id_82571(hw); | |
dd93f95e BA |
128 | if (ret_val) { |
129 | e_dbg("Error getting PHY ID\n"); | |
130 | return ret_val; | |
131 | } | |
bc7f75fa AK |
132 | |
133 | /* Verify phy id */ | |
134 | switch (hw->mac.type) { | |
135 | case e1000_82571: | |
136 | case e1000_82572: | |
137 | if (phy->id != IGP01E1000_I_PHY_ID) | |
dd93f95e | 138 | ret_val = -E1000_ERR_PHY; |
bc7f75fa AK |
139 | break; |
140 | case e1000_82573: | |
141 | if (phy->id != M88E1111_I_PHY_ID) | |
dd93f95e | 142 | ret_val = -E1000_ERR_PHY; |
bc7f75fa | 143 | break; |
4662e82b | 144 | case e1000_82574: |
8c81c9c3 | 145 | case e1000_82583: |
4662e82b | 146 | if (phy->id != BME1000_E_PHY_ID_R2) |
dd93f95e | 147 | ret_val = -E1000_ERR_PHY; |
4662e82b | 148 | break; |
bc7f75fa | 149 | default: |
dd93f95e | 150 | ret_val = -E1000_ERR_PHY; |
bc7f75fa AK |
151 | break; |
152 | } | |
153 | ||
dd93f95e BA |
154 | if (ret_val) |
155 | e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); | |
156 | ||
157 | return ret_val; | |
bc7f75fa AK |
158 | } |
159 | ||
160 | /** | |
161 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
162 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
163 | **/ |
164 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
165 | { | |
166 | struct e1000_nvm_info *nvm = &hw->nvm; | |
167 | u32 eecd = er32(EECD); | |
168 | u16 size; | |
169 | ||
170 | nvm->opcode_bits = 8; | |
171 | nvm->delay_usec = 1; | |
172 | switch (nvm->override) { | |
173 | case e1000_nvm_override_spi_large: | |
174 | nvm->page_size = 32; | |
175 | nvm->address_bits = 16; | |
176 | break; | |
177 | case e1000_nvm_override_spi_small: | |
178 | nvm->page_size = 8; | |
179 | nvm->address_bits = 8; | |
180 | break; | |
181 | default: | |
182 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
183 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
184 | break; | |
185 | } | |
186 | ||
187 | switch (hw->mac.type) { | |
188 | case e1000_82573: | |
4662e82b | 189 | case e1000_82574: |
8c81c9c3 | 190 | case e1000_82583: |
bc7f75fa AK |
191 | if (((eecd >> 15) & 0x3) == 0x3) { |
192 | nvm->type = e1000_nvm_flash_hw; | |
193 | nvm->word_size = 2048; | |
ad68076e BA |
194 | /* |
195 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
196 | * to Flash update issue. |
197 | */ | |
198 | eecd &= ~E1000_EECD_AUPDEN; | |
199 | ew32(EECD, eecd); | |
200 | break; | |
201 | } | |
202 | /* Fall Through */ | |
203 | default: | |
ad68076e | 204 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
205 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
206 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
207 | /* |
208 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
209 | * for setting word_size. |
210 | */ | |
211 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
212 | |
213 | /* EEPROM access above 16k is unsupported */ | |
214 | if (size > 14) | |
215 | size = 14; | |
bc7f75fa AK |
216 | nvm->word_size = 1 << size; |
217 | break; | |
218 | } | |
219 | ||
1b98c2bb BA |
220 | /* Function Pointers */ |
221 | switch (hw->mac.type) { | |
222 | case e1000_82574: | |
223 | case e1000_82583: | |
224 | nvm->ops.acquire = e1000_get_hw_semaphore_82574; | |
225 | nvm->ops.release = e1000_put_hw_semaphore_82574; | |
226 | break; | |
227 | default: | |
228 | break; | |
229 | } | |
230 | ||
bc7f75fa AK |
231 | return 0; |
232 | } | |
233 | ||
234 | /** | |
235 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
236 | * @hw: pointer to the HW structure | |
bc7f75fa | 237 | **/ |
ec34c170 | 238 | static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) |
bc7f75fa | 239 | { |
bc7f75fa | 240 | struct e1000_mac_info *mac = &hw->mac; |
23a2d1b2 DG |
241 | u32 swsm = 0; |
242 | u32 swsm2 = 0; | |
243 | bool force_clear_smbi = false; | |
bc7f75fa | 244 | |
66092f59 | 245 | /* Set media type and media-dependent function pointers */ |
ec34c170 | 246 | switch (hw->adapter->pdev->device) { |
bc7f75fa AK |
247 | case E1000_DEV_ID_82571EB_FIBER: |
248 | case E1000_DEV_ID_82572EI_FIBER: | |
249 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 250 | hw->phy.media_type = e1000_media_type_fiber; |
66092f59 BA |
251 | mac->ops.setup_physical_interface = |
252 | e1000_setup_fiber_serdes_link_82571; | |
253 | mac->ops.check_for_link = e1000e_check_for_fiber_link; | |
254 | mac->ops.get_link_up_info = | |
255 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
256 | break; |
257 | case E1000_DEV_ID_82571EB_SERDES: | |
040babf9 AK |
258 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
259 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
66092f59 | 260 | case E1000_DEV_ID_82572EI_SERDES: |
318a94d6 | 261 | hw->phy.media_type = e1000_media_type_internal_serdes; |
66092f59 BA |
262 | mac->ops.setup_physical_interface = |
263 | e1000_setup_fiber_serdes_link_82571; | |
264 | mac->ops.check_for_link = e1000_check_for_serdes_link_82571; | |
265 | mac->ops.get_link_up_info = | |
266 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
267 | break; |
268 | default: | |
318a94d6 | 269 | hw->phy.media_type = e1000_media_type_copper; |
66092f59 BA |
270 | mac->ops.setup_physical_interface = |
271 | e1000_setup_copper_link_82571; | |
272 | mac->ops.check_for_link = e1000e_check_for_copper_link; | |
273 | mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
bc7f75fa AK |
274 | break; |
275 | } | |
276 | ||
277 | /* Set mta register count */ | |
278 | mac->mta_reg_count = 128; | |
279 | /* Set rar entry count */ | |
280 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
f464ba87 BA |
281 | /* Adaptive IFS supported */ |
282 | mac->adaptive_ifs = true; | |
bc7f75fa | 283 | |
66092f59 | 284 | /* MAC-specific function pointers */ |
4662e82b | 285 | switch (hw->mac.type) { |
f4d2dd4c | 286 | case e1000_82573: |
66092f59 BA |
287 | mac->ops.set_lan_id = e1000_set_lan_id_single_port; |
288 | mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; | |
289 | mac->ops.led_on = e1000e_led_on_generic; | |
290 | mac->ops.blink_led = e1000e_blink_led_generic; | |
a65a4a0d BA |
291 | |
292 | /* FWSM register */ | |
293 | mac->has_fwsm = true; | |
294 | /* | |
295 | * ARC supported; valid only if manageability features are | |
296 | * enabled. | |
297 | */ | |
298 | mac->arc_subsystem_valid = | |
299 | (er32(FWSM) & E1000_FWSM_MODE_MASK) | |
300 | ? true : false; | |
f4d2dd4c | 301 | break; |
4662e82b | 302 | case e1000_82574: |
8c81c9c3 | 303 | case e1000_82583: |
66092f59 BA |
304 | mac->ops.set_lan_id = e1000_set_lan_id_single_port; |
305 | mac->ops.check_mng_mode = e1000_check_mng_mode_82574; | |
306 | mac->ops.led_on = e1000_led_on_82574; | |
4662e82b BA |
307 | break; |
308 | default: | |
66092f59 BA |
309 | mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; |
310 | mac->ops.led_on = e1000e_led_on_generic; | |
311 | mac->ops.blink_led = e1000e_blink_led_generic; | |
a65a4a0d BA |
312 | |
313 | /* FWSM register */ | |
314 | mac->has_fwsm = true; | |
4662e82b BA |
315 | break; |
316 | } | |
317 | ||
23a2d1b2 DG |
318 | /* |
319 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
b595076a | 320 | * first NVM or PHY access. This should be done for single-port |
23a2d1b2 DG |
321 | * devices, and for one port only on dual-port devices so that |
322 | * for those devices we can still use the SMBI lock to synchronize | |
323 | * inter-port accesses to the PHY & NVM. | |
324 | */ | |
325 | switch (hw->mac.type) { | |
326 | case e1000_82571: | |
327 | case e1000_82572: | |
328 | swsm2 = er32(SWSM2); | |
329 | ||
330 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
331 | /* Only do this for the first interface on this card */ | |
66092f59 | 332 | ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK); |
23a2d1b2 | 333 | force_clear_smbi = true; |
66092f59 | 334 | } else { |
23a2d1b2 | 335 | force_clear_smbi = false; |
66092f59 | 336 | } |
23a2d1b2 DG |
337 | break; |
338 | default: | |
339 | force_clear_smbi = true; | |
340 | break; | |
341 | } | |
342 | ||
343 | if (force_clear_smbi) { | |
344 | /* Make sure SWSM.SMBI is clear */ | |
345 | swsm = er32(SWSM); | |
346 | if (swsm & E1000_SWSM_SMBI) { | |
347 | /* This bit should not be set on a first interface, and | |
348 | * indicates that the bootagent or EFI code has | |
349 | * improperly left this bit enabled | |
350 | */ | |
3bb99fe2 | 351 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
352 | } |
353 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
354 | } | |
355 | ||
356 | /* | |
2c73e1fe | 357 | * Initialize device specific counter of SMBI acquisition |
23a2d1b2 DG |
358 | * timeouts. |
359 | */ | |
360 | hw->dev_spec.e82571.smb_counter = 0; | |
361 | ||
bc7f75fa AK |
362 | return 0; |
363 | } | |
364 | ||
69e3fd8c | 365 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
366 | { |
367 | struct e1000_hw *hw = &adapter->hw; | |
368 | static int global_quad_port_a; /* global port a indication */ | |
369 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
370 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; |
371 | s32 rc; | |
372 | ||
ec34c170 | 373 | rc = e1000_init_mac_params_82571(hw); |
bc7f75fa AK |
374 | if (rc) |
375 | return rc; | |
376 | ||
377 | rc = e1000_init_nvm_params_82571(hw); | |
378 | if (rc) | |
379 | return rc; | |
380 | ||
381 | rc = e1000_init_phy_params_82571(hw); | |
382 | if (rc) | |
383 | return rc; | |
384 | ||
385 | /* tag quad port adapters first, it's used below */ | |
386 | switch (pdev->device) { | |
387 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
388 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
389 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 390 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
391 | adapter->flags |= FLAG_IS_QUAD_PORT; |
392 | /* mark the first port */ | |
393 | if (global_quad_port_a == 0) | |
394 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
395 | /* Reset for multiple quad port adapters */ | |
396 | global_quad_port_a++; | |
397 | if (global_quad_port_a == 4) | |
398 | global_quad_port_a = 0; | |
399 | break; | |
400 | default: | |
401 | break; | |
402 | } | |
403 | ||
404 | switch (adapter->hw.mac.type) { | |
405 | case e1000_82571: | |
406 | /* these dual ports don't have WoL on port B at all */ | |
407 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
408 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
409 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
410 | (is_port_b)) | |
411 | adapter->flags &= ~FLAG_HAS_WOL; | |
412 | /* quad ports only support WoL on port A */ | |
413 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 414 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 415 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
416 | /* Does not support WoL on any port */ |
417 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
418 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa | 419 | break; |
bc7f75fa AK |
420 | case e1000_82573: |
421 | if (pdev->device == E1000_DEV_ID_82573L) { | |
6f461f6c BA |
422 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; |
423 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
bc7f75fa AK |
424 | } |
425 | break; | |
426 | default: | |
427 | break; | |
428 | } | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | /** | |
434 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
435 | * @hw: pointer to the HW structure | |
436 | * | |
437 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
438 | * revision in the hardware structure. | |
439 | **/ | |
440 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
441 | { | |
442 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
443 | s32 ret_val; |
444 | u16 phy_id = 0; | |
bc7f75fa AK |
445 | |
446 | switch (hw->mac.type) { | |
447 | case e1000_82571: | |
448 | case e1000_82572: | |
ad68076e BA |
449 | /* |
450 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
451 | * In this case, we cannot access the PHY until the |
452 | * configuration is done. So we explicitly set the | |
ad68076e BA |
453 | * PHY ID. |
454 | */ | |
bc7f75fa AK |
455 | phy->id = IGP01E1000_I_PHY_ID; |
456 | break; | |
457 | case e1000_82573: | |
458 | return e1000e_get_phy_id(hw); | |
459 | break; | |
4662e82b | 460 | case e1000_82574: |
8c81c9c3 | 461 | case e1000_82583: |
4662e82b BA |
462 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
463 | if (ret_val) | |
464 | return ret_val; | |
465 | ||
466 | phy->id = (u32)(phy_id << 16); | |
467 | udelay(20); | |
468 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
469 | if (ret_val) | |
470 | return ret_val; | |
471 | ||
472 | phy->id |= (u32)(phy_id); | |
473 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
474 | break; | |
bc7f75fa AK |
475 | default: |
476 | return -E1000_ERR_PHY; | |
477 | break; | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | /** | |
484 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
485 | * @hw: pointer to the HW structure | |
486 | * | |
487 | * Acquire the HW semaphore to access the PHY or NVM | |
488 | **/ | |
489 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
490 | { | |
491 | u32 swsm; | |
23a2d1b2 DG |
492 | s32 sw_timeout = hw->nvm.word_size + 1; |
493 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
494 | s32 i = 0; |
495 | ||
23a2d1b2 DG |
496 | /* |
497 | * If we have timedout 3 times on trying to acquire | |
498 | * the inter-port SMBI semaphore, there is old code | |
499 | * operating on the other port, and it is not | |
500 | * releasing SMBI. Modify the number of times that | |
501 | * we try for the semaphore to interwork with this | |
502 | * older code. | |
503 | */ | |
504 | if (hw->dev_spec.e82571.smb_counter > 2) | |
505 | sw_timeout = 1; | |
506 | ||
507 | /* Get the SW semaphore */ | |
508 | while (i < sw_timeout) { | |
509 | swsm = er32(SWSM); | |
510 | if (!(swsm & E1000_SWSM_SMBI)) | |
511 | break; | |
512 | ||
513 | udelay(50); | |
514 | i++; | |
515 | } | |
516 | ||
517 | if (i == sw_timeout) { | |
3bb99fe2 | 518 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
519 | hw->dev_spec.e82571.smb_counter++; |
520 | } | |
bc7f75fa | 521 | /* Get the FW semaphore. */ |
23a2d1b2 | 522 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
523 | swsm = er32(SWSM); |
524 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
525 | ||
526 | /* Semaphore acquired if bit latched */ | |
527 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
528 | break; | |
529 | ||
530 | udelay(50); | |
531 | } | |
532 | ||
23a2d1b2 | 533 | if (i == fw_timeout) { |
bc7f75fa | 534 | /* Release semaphores */ |
23a2d1b2 | 535 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 536 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
537 | return -E1000_ERR_NVM; |
538 | } | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | /** | |
544 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
545 | * @hw: pointer to the HW structure | |
546 | * | |
547 | * Release hardware semaphore used to access the PHY or NVM | |
548 | **/ | |
549 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
550 | { | |
551 | u32 swsm; | |
552 | ||
553 | swsm = er32(SWSM); | |
23a2d1b2 | 554 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
555 | ew32(SWSM, swsm); |
556 | } | |
1b98c2bb BA |
557 | /** |
558 | * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore | |
559 | * @hw: pointer to the HW structure | |
560 | * | |
561 | * Acquire the HW semaphore during reset. | |
562 | * | |
563 | **/ | |
564 | static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) | |
565 | { | |
566 | u32 extcnf_ctrl; | |
1b98c2bb BA |
567 | s32 i = 0; |
568 | ||
569 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
570 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
571 | do { | |
572 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
573 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
574 | ||
575 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
576 | break; | |
577 | ||
578 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
579 | ||
1bba4386 | 580 | usleep_range(2000, 4000); |
1b98c2bb BA |
581 | i++; |
582 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
583 | ||
584 | if (i == MDIO_OWNERSHIP_TIMEOUT) { | |
585 | /* Release semaphores */ | |
586 | e1000_put_hw_semaphore_82573(hw); | |
587 | e_dbg("Driver can't access the PHY\n"); | |
5015e53a | 588 | return -E1000_ERR_PHY; |
1b98c2bb BA |
589 | } |
590 | ||
5015e53a | 591 | return 0; |
1b98c2bb BA |
592 | } |
593 | ||
594 | /** | |
595 | * e1000_put_hw_semaphore_82573 - Release hardware semaphore | |
596 | * @hw: pointer to the HW structure | |
597 | * | |
598 | * Release hardware semaphore used during reset. | |
599 | * | |
600 | **/ | |
601 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) | |
602 | { | |
603 | u32 extcnf_ctrl; | |
604 | ||
605 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
606 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
607 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
608 | } | |
609 | ||
610 | static DEFINE_MUTEX(swflag_mutex); | |
611 | ||
612 | /** | |
613 | * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore | |
614 | * @hw: pointer to the HW structure | |
615 | * | |
616 | * Acquire the HW semaphore to access the PHY or NVM. | |
617 | * | |
618 | **/ | |
619 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) | |
620 | { | |
621 | s32 ret_val; | |
622 | ||
623 | mutex_lock(&swflag_mutex); | |
624 | ret_val = e1000_get_hw_semaphore_82573(hw); | |
625 | if (ret_val) | |
626 | mutex_unlock(&swflag_mutex); | |
627 | return ret_val; | |
628 | } | |
629 | ||
630 | /** | |
631 | * e1000_put_hw_semaphore_82574 - Release hardware semaphore | |
632 | * @hw: pointer to the HW structure | |
633 | * | |
634 | * Release hardware semaphore used to access the PHY or NVM | |
635 | * | |
636 | **/ | |
637 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) | |
638 | { | |
639 | e1000_put_hw_semaphore_82573(hw); | |
640 | mutex_unlock(&swflag_mutex); | |
641 | } | |
bc7f75fa | 642 | |
77996d1d BA |
643 | /** |
644 | * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state | |
645 | * @hw: pointer to the HW structure | |
646 | * @active: true to enable LPLU, false to disable | |
647 | * | |
648 | * Sets the LPLU D0 state according to the active flag. | |
649 | * LPLU will not be activated unless the | |
650 | * device autonegotiation advertisement meets standards of | |
651 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
652 | * This is a function pointer entry point only called by | |
653 | * PHY setup routines. | |
654 | **/ | |
655 | static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) | |
656 | { | |
657 | u16 data = er32(POEMB); | |
658 | ||
659 | if (active) | |
660 | data |= E1000_PHY_CTRL_D0A_LPLU; | |
661 | else | |
662 | data &= ~E1000_PHY_CTRL_D0A_LPLU; | |
663 | ||
664 | ew32(POEMB, data); | |
665 | return 0; | |
666 | } | |
667 | ||
668 | /** | |
669 | * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 | |
670 | * @hw: pointer to the HW structure | |
671 | * @active: boolean used to enable/disable lplu | |
672 | * | |
673 | * The low power link up (lplu) state is set to the power management level D3 | |
674 | * when active is true, else clear lplu for D3. LPLU | |
675 | * is used during Dx states where the power conservation is most important. | |
676 | * During driver activity, SmartSpeed should be enabled so performance is | |
677 | * maintained. | |
678 | **/ | |
679 | static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) | |
680 | { | |
681 | u16 data = er32(POEMB); | |
682 | ||
683 | if (!active) { | |
684 | data &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
685 | } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
686 | (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || | |
687 | (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { | |
688 | data |= E1000_PHY_CTRL_NOND0A_LPLU; | |
689 | } | |
690 | ||
691 | ew32(POEMB, data); | |
692 | return 0; | |
693 | } | |
694 | ||
bc7f75fa AK |
695 | /** |
696 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
697 | * @hw: pointer to the HW structure | |
698 | * | |
699 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
700 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
701 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
702 | * hardware semaphore. | |
703 | **/ | |
704 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
705 | { | |
706 | s32 ret_val; | |
707 | ||
708 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
709 | if (ret_val) | |
710 | return ret_val; | |
711 | ||
8c81c9c3 AD |
712 | switch (hw->mac.type) { |
713 | case e1000_82573: | |
8c81c9c3 AD |
714 | break; |
715 | default: | |
bc7f75fa | 716 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
717 | break; |
718 | } | |
bc7f75fa AK |
719 | |
720 | if (ret_val) | |
721 | e1000_put_hw_semaphore_82571(hw); | |
722 | ||
723 | return ret_val; | |
724 | } | |
725 | ||
726 | /** | |
727 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
728 | * @hw: pointer to the HW structure | |
729 | * | |
730 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
731 | **/ | |
732 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
733 | { | |
734 | e1000e_release_nvm(hw); | |
735 | e1000_put_hw_semaphore_82571(hw); | |
736 | } | |
737 | ||
738 | /** | |
739 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
740 | * @hw: pointer to the HW structure | |
741 | * @offset: offset within the EEPROM to be written to | |
742 | * @words: number of words to write | |
743 | * @data: 16 bit word(s) to be written to the EEPROM | |
744 | * | |
745 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
746 | * | |
747 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 748 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
749 | **/ |
750 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
751 | u16 *data) | |
752 | { | |
753 | s32 ret_val; | |
754 | ||
755 | switch (hw->mac.type) { | |
756 | case e1000_82573: | |
4662e82b | 757 | case e1000_82574: |
8c81c9c3 | 758 | case e1000_82583: |
bc7f75fa AK |
759 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
760 | break; | |
761 | case e1000_82571: | |
762 | case e1000_82572: | |
763 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
764 | break; | |
765 | default: | |
766 | ret_val = -E1000_ERR_NVM; | |
767 | break; | |
768 | } | |
769 | ||
770 | return ret_val; | |
771 | } | |
772 | ||
773 | /** | |
774 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
775 | * @hw: pointer to the HW structure | |
776 | * | |
777 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
778 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
779 | * value to the EEPROM. | |
780 | **/ | |
781 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
782 | { | |
783 | u32 eecd; | |
784 | s32 ret_val; | |
785 | u16 i; | |
786 | ||
787 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
788 | if (ret_val) | |
789 | return ret_val; | |
790 | ||
ad68076e BA |
791 | /* |
792 | * If our nvm is an EEPROM, then we're done | |
793 | * otherwise, commit the checksum to the flash NVM. | |
794 | */ | |
bc7f75fa | 795 | if (hw->nvm.type != e1000_nvm_flash_hw) |
82607255 | 796 | return 0; |
bc7f75fa AK |
797 | |
798 | /* Check for pending operations. */ | |
799 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
1bba4386 | 800 | usleep_range(1000, 2000); |
bc7f75fa AK |
801 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) |
802 | break; | |
803 | } | |
804 | ||
805 | if (i == E1000_FLASH_UPDATES) | |
806 | return -E1000_ERR_NVM; | |
807 | ||
808 | /* Reset the firmware if using STM opcode. */ | |
809 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
810 | /* |
811 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
812 | * in two write cycles. |
813 | */ | |
814 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
815 | e1e_flush(); | |
816 | ew32(HICR, E1000_HICR_FW_RESET); | |
817 | } | |
818 | ||
819 | /* Commit the write to flash */ | |
820 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
821 | ew32(EECD, eecd); | |
822 | ||
823 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
1bba4386 | 824 | usleep_range(1000, 2000); |
bc7f75fa AK |
825 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) |
826 | break; | |
827 | } | |
828 | ||
829 | if (i == E1000_FLASH_UPDATES) | |
830 | return -E1000_ERR_NVM; | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
835 | /** | |
836 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
837 | * @hw: pointer to the HW structure | |
838 | * | |
839 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
840 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
841 | **/ | |
842 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
843 | { | |
844 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
845 | e1000_fix_nvm_checksum_82571(hw); | |
846 | ||
847 | return e1000e_validate_nvm_checksum_generic(hw); | |
848 | } | |
849 | ||
850 | /** | |
851 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
852 | * @hw: pointer to the HW structure | |
853 | * @offset: offset within the EEPROM to be written to | |
854 | * @words: number of words to write | |
855 | * @data: 16 bit word(s) to be written to the EEPROM | |
856 | * | |
857 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
858 | * command has completed before trying to write the next word. After write | |
859 | * poll for completion. | |
860 | * | |
861 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 862 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
863 | **/ |
864 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
865 | u16 words, u16 *data) | |
866 | { | |
867 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 868 | u32 i, eewr = 0; |
bc7f75fa AK |
869 | s32 ret_val = 0; |
870 | ||
ad68076e BA |
871 | /* |
872 | * A check for invalid values: offset too large, too many words, | |
873 | * and not enough words. | |
874 | */ | |
bc7f75fa AK |
875 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
876 | (words == 0)) { | |
3bb99fe2 | 877 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
878 | return -E1000_ERR_NVM; |
879 | } | |
880 | ||
881 | for (i = 0; i < words; i++) { | |
882 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
883 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
884 | E1000_NVM_RW_REG_START; | |
885 | ||
886 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
887 | if (ret_val) | |
888 | break; | |
889 | ||
890 | ew32(EEWR, eewr); | |
891 | ||
892 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
893 | if (ret_val) | |
894 | break; | |
895 | } | |
896 | ||
897 | return ret_val; | |
898 | } | |
899 | ||
900 | /** | |
901 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
902 | * @hw: pointer to the HW structure | |
903 | * | |
904 | * Reads the management control register for the config done bit to be set. | |
905 | **/ | |
906 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
907 | { | |
908 | s32 timeout = PHY_CFG_TIMEOUT; | |
909 | ||
910 | while (timeout) { | |
911 | if (er32(EEMNGCTL) & | |
912 | E1000_NVM_CFG_DONE_PORT_0) | |
913 | break; | |
1bba4386 | 914 | usleep_range(1000, 2000); |
bc7f75fa AK |
915 | timeout--; |
916 | } | |
917 | if (!timeout) { | |
3bb99fe2 | 918 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
919 | return -E1000_ERR_RESET; |
920 | } | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | /** | |
926 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
927 | * @hw: pointer to the HW structure | |
564ea9bb | 928 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
929 | * |
930 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
931 | * this function also disables smart speed and vice versa. LPLU will not be | |
932 | * activated unless the device autonegotiation advertisement meets standards | |
933 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
934 | * pointer entry point only called by PHY setup routines. | |
935 | **/ | |
936 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
937 | { | |
938 | struct e1000_phy_info *phy = &hw->phy; | |
939 | s32 ret_val; | |
940 | u16 data; | |
941 | ||
942 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
943 | if (ret_val) | |
944 | return ret_val; | |
945 | ||
946 | if (active) { | |
947 | data |= IGP02E1000_PM_D0_LPLU; | |
948 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
949 | if (ret_val) | |
950 | return ret_val; | |
951 | ||
952 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
953 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
954 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
955 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
956 | if (ret_val) | |
957 | return ret_val; | |
958 | } else { | |
959 | data &= ~IGP02E1000_PM_D0_LPLU; | |
960 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
961 | /* |
962 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
963 | * during Dx states where the power conservation is most |
964 | * important. During driver activity we should enable | |
ad68076e BA |
965 | * SmartSpeed, so performance is maintained. |
966 | */ | |
bc7f75fa AK |
967 | if (phy->smart_speed == e1000_smart_speed_on) { |
968 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 969 | &data); |
bc7f75fa AK |
970 | if (ret_val) |
971 | return ret_val; | |
972 | ||
973 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
974 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 975 | data); |
bc7f75fa AK |
976 | if (ret_val) |
977 | return ret_val; | |
978 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
979 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 980 | &data); |
bc7f75fa AK |
981 | if (ret_val) |
982 | return ret_val; | |
983 | ||
984 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
985 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 986 | data); |
bc7f75fa AK |
987 | if (ret_val) |
988 | return ret_val; | |
989 | } | |
990 | } | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
995 | /** | |
996 | * e1000_reset_hw_82571 - Reset hardware | |
997 | * @hw: pointer to the HW structure | |
998 | * | |
fe401674 | 999 | * This resets the hardware into a known state. |
bc7f75fa AK |
1000 | **/ |
1001 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
1002 | { | |
dd93f95e | 1003 | u32 ctrl, ctrl_ext; |
bc7f75fa | 1004 | s32 ret_val; |
bc7f75fa | 1005 | |
ad68076e BA |
1006 | /* |
1007 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
1008 | * on the last TLP read/write transaction when MAC is reset. |
1009 | */ | |
1010 | ret_val = e1000e_disable_pcie_master(hw); | |
1011 | if (ret_val) | |
3bb99fe2 | 1012 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 1013 | |
3bb99fe2 | 1014 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
1015 | ew32(IMC, 0xffffffff); |
1016 | ||
1017 | ew32(RCTL, 0); | |
1018 | ew32(TCTL, E1000_TCTL_PSP); | |
1019 | e1e_flush(); | |
1020 | ||
1bba4386 | 1021 | usleep_range(10000, 20000); |
bc7f75fa | 1022 | |
ad68076e BA |
1023 | /* |
1024 | * Must acquire the MDIO ownership before MAC reset. | |
1025 | * Ownership defaults to firmware after a reset. | |
1026 | */ | |
8c81c9c3 AD |
1027 | switch (hw->mac.type) { |
1028 | case e1000_82573: | |
1b98c2bb BA |
1029 | ret_val = e1000_get_hw_semaphore_82573(hw); |
1030 | break; | |
8c81c9c3 AD |
1031 | case e1000_82574: |
1032 | case e1000_82583: | |
1b98c2bb | 1033 | ret_val = e1000_get_hw_semaphore_82574(hw); |
8c81c9c3 AD |
1034 | break; |
1035 | default: | |
1036 | break; | |
bc7f75fa | 1037 | } |
1b98c2bb BA |
1038 | if (ret_val) |
1039 | e_dbg("Cannot acquire MDIO ownership\n"); | |
bc7f75fa AK |
1040 | |
1041 | ctrl = er32(CTRL); | |
1042 | ||
3bb99fe2 | 1043 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
1044 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
1045 | ||
1b98c2bb BA |
1046 | /* Must release MDIO ownership and mutex after MAC reset. */ |
1047 | switch (hw->mac.type) { | |
1048 | case e1000_82574: | |
1049 | case e1000_82583: | |
1050 | e1000_put_hw_semaphore_82574(hw); | |
1051 | break; | |
1052 | default: | |
1053 | break; | |
1054 | } | |
1055 | ||
bc7f75fa AK |
1056 | if (hw->nvm.type == e1000_nvm_flash_hw) { |
1057 | udelay(10); | |
1058 | ctrl_ext = er32(CTRL_EXT); | |
1059 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
1060 | ew32(CTRL_EXT, ctrl_ext); | |
1061 | e1e_flush(); | |
1062 | } | |
1063 | ||
1064 | ret_val = e1000e_get_auto_rd_done(hw); | |
1065 | if (ret_val) | |
1066 | /* We don't want to continue accessing MAC registers. */ | |
1067 | return ret_val; | |
1068 | ||
ad68076e BA |
1069 | /* |
1070 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
1071 | * Need to wait for Phy configuration completion before accessing |
1072 | * NVM and Phy. | |
1073 | */ | |
8c81c9c3 AD |
1074 | |
1075 | switch (hw->mac.type) { | |
1076 | case e1000_82573: | |
1077 | case e1000_82574: | |
1078 | case e1000_82583: | |
bc7f75fa | 1079 | msleep(25); |
8c81c9c3 AD |
1080 | break; |
1081 | default: | |
1082 | break; | |
1083 | } | |
bc7f75fa AK |
1084 | |
1085 | /* Clear any pending interrupt events. */ | |
1086 | ew32(IMC, 0xffffffff); | |
dd93f95e | 1087 | er32(ICR); |
bc7f75fa | 1088 | |
1aef70ef BA |
1089 | if (hw->mac.type == e1000_82571) { |
1090 | /* Install any alternate MAC address into RAR0 */ | |
1091 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1092 | if (ret_val) | |
1093 | return ret_val; | |
608f8a0d | 1094 | |
1aef70ef BA |
1095 | e1000e_set_laa_state_82571(hw, true); |
1096 | } | |
93ca1610 | 1097 | |
c9523379 | 1098 | /* Reinitialize the 82571 serdes link state machine */ |
1099 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
1100 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
1101 | ||
bc7f75fa AK |
1102 | return 0; |
1103 | } | |
1104 | ||
1105 | /** | |
1106 | * e1000_init_hw_82571 - Initialize hardware | |
1107 | * @hw: pointer to the HW structure | |
1108 | * | |
1109 | * This inits the hardware readying it for operation. | |
1110 | **/ | |
1111 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
1112 | { | |
1113 | struct e1000_mac_info *mac = &hw->mac; | |
1114 | u32 reg_data; | |
1115 | s32 ret_val; | |
a708dd88 | 1116 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
1117 | |
1118 | e1000_initialize_hw_bits_82571(hw); | |
1119 | ||
1120 | /* Initialize identification LED */ | |
d1964eb1 | 1121 | ret_val = mac->ops.id_led_init(hw); |
de39b752 | 1122 | if (ret_val) |
3bb99fe2 | 1123 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 1124 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
1125 | |
1126 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 1127 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 1128 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
1129 | |
1130 | /* Setup the receive address. */ | |
ad68076e BA |
1131 | /* |
1132 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
1133 | * 82571, we must reserve a RAR for it to work around an issue where |
1134 | * resetting one port will reload the MAC on the other port. | |
1135 | */ | |
1136 | if (e1000e_get_laa_state_82571(hw)) | |
1137 | rar_count--; | |
1138 | e1000e_init_rx_addrs(hw, rar_count); | |
1139 | ||
1140 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 1141 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
1142 | for (i = 0; i < mac->mta_reg_count; i++) |
1143 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
1144 | ||
1145 | /* Setup link and flow control */ | |
1146 | ret_val = e1000_setup_link_82571(hw); | |
1147 | ||
1148 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 1149 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
1150 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1151 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1152 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1153 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
1154 | |
1155 | /* ...for both queues. */ | |
8c81c9c3 AD |
1156 | switch (mac->type) { |
1157 | case e1000_82573: | |
a65a4a0d BA |
1158 | e1000e_enable_tx_pkt_filtering(hw); |
1159 | /* fall through */ | |
8c81c9c3 AD |
1160 | case e1000_82574: |
1161 | case e1000_82583: | |
8c81c9c3 AD |
1162 | reg_data = er32(GCR); |
1163 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1164 | ew32(GCR, reg_data); | |
1165 | break; | |
1166 | default: | |
e9ec2c0f | 1167 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
1168 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1169 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1170 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1171 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 1172 | break; |
bc7f75fa AK |
1173 | } |
1174 | ||
ad68076e BA |
1175 | /* |
1176 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1177 | * important that we do this after we have tried to establish link |
1178 | * because the symbol error count will increment wildly if there | |
1179 | * is no link. | |
1180 | */ | |
1181 | e1000_clear_hw_cntrs_82571(hw); | |
1182 | ||
1183 | return ret_val; | |
1184 | } | |
1185 | ||
1186 | /** | |
1187 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1188 | * @hw: pointer to the HW structure | |
1189 | * | |
1190 | * Initializes required hardware-dependent bits needed for normal operation. | |
1191 | **/ | |
1192 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1193 | { | |
1194 | u32 reg; | |
1195 | ||
1196 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1197 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1198 | reg |= (1 << 22); |
e9ec2c0f | 1199 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1200 | |
1201 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1202 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1203 | reg |= (1 << 22); |
e9ec2c0f | 1204 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1205 | |
1206 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1207 | reg = er32(TARC(0)); |
bc7f75fa AK |
1208 | reg &= ~(0xF << 27); /* 30:27 */ |
1209 | switch (hw->mac.type) { | |
1210 | case e1000_82571: | |
1211 | case e1000_82572: | |
1212 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1213 | break; | |
d6cb17d5 BA |
1214 | case e1000_82574: |
1215 | case e1000_82583: | |
1216 | reg |= (1 << 26); | |
1217 | break; | |
bc7f75fa AK |
1218 | default: |
1219 | break; | |
1220 | } | |
e9ec2c0f | 1221 | ew32(TARC(0), reg); |
bc7f75fa AK |
1222 | |
1223 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1224 | reg = er32(TARC(1)); |
bc7f75fa AK |
1225 | switch (hw->mac.type) { |
1226 | case e1000_82571: | |
1227 | case e1000_82572: | |
1228 | reg &= ~((1 << 29) | (1 << 30)); | |
1229 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1230 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1231 | reg &= ~(1 << 28); | |
1232 | else | |
1233 | reg |= (1 << 28); | |
e9ec2c0f | 1234 | ew32(TARC(1), reg); |
bc7f75fa AK |
1235 | break; |
1236 | default: | |
1237 | break; | |
1238 | } | |
1239 | ||
1240 | /* Device Control */ | |
8c81c9c3 AD |
1241 | switch (hw->mac.type) { |
1242 | case e1000_82573: | |
1243 | case e1000_82574: | |
1244 | case e1000_82583: | |
bc7f75fa AK |
1245 | reg = er32(CTRL); |
1246 | reg &= ~(1 << 29); | |
1247 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1248 | break; |
1249 | default: | |
1250 | break; | |
bc7f75fa AK |
1251 | } |
1252 | ||
1253 | /* Extended Device Control */ | |
8c81c9c3 AD |
1254 | switch (hw->mac.type) { |
1255 | case e1000_82573: | |
1256 | case e1000_82574: | |
1257 | case e1000_82583: | |
bc7f75fa AK |
1258 | reg = er32(CTRL_EXT); |
1259 | reg &= ~(1 << 23); | |
1260 | reg |= (1 << 22); | |
1261 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1262 | break; |
1263 | default: | |
1264 | break; | |
bc7f75fa | 1265 | } |
4662e82b | 1266 | |
6ea7ae1d AD |
1267 | if (hw->mac.type == e1000_82571) { |
1268 | reg = er32(PBA_ECC); | |
1269 | reg |= E1000_PBA_ECC_CORR_EN; | |
1270 | ew32(PBA_ECC, reg); | |
1271 | } | |
5df3f0ea | 1272 | /* |
1273 | * Workaround for hardware errata. | |
1274 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1275 | */ | |
1276 | ||
1277 | if ((hw->mac.type == e1000_82571) || | |
1278 | (hw->mac.type == e1000_82572)) { | |
1279 | reg = er32(CTRL_EXT); | |
1280 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1281 | ew32(CTRL_EXT, reg); | |
1282 | } | |
1283 | ||
6ea7ae1d | 1284 | |
78272bba | 1285 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1286 | switch (hw->mac.type) { |
1287 | case e1000_82574: | |
1288 | case e1000_82583: | |
4662e82b BA |
1289 | reg = er32(GCR); |
1290 | reg |= (1 << 22); | |
1291 | ew32(GCR, reg); | |
78272bba | 1292 | |
84efb7b9 BA |
1293 | /* |
1294 | * Workaround for hardware errata. | |
1295 | * apply workaround for hardware errata documented in errata | |
1296 | * docs Fixes issue where some error prone or unreliable PCIe | |
1297 | * completions are occurring, particularly with ASPM enabled. | |
af667a29 | 1298 | * Without fix, issue can cause Tx timeouts. |
84efb7b9 | 1299 | */ |
78272bba JB |
1300 | reg = er32(GCR2); |
1301 | reg |= 1; | |
1302 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1303 | break; |
1304 | default: | |
1305 | break; | |
4662e82b | 1306 | } |
bc7f75fa AK |
1307 | } |
1308 | ||
1309 | /** | |
caaddaf8 | 1310 | * e1000_clear_vfta_82571 - Clear VLAN filter table |
bc7f75fa AK |
1311 | * @hw: pointer to the HW structure |
1312 | * | |
1313 | * Clears the register array which contains the VLAN filter table by | |
1314 | * setting all the values to 0. | |
1315 | **/ | |
caaddaf8 | 1316 | static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
bc7f75fa AK |
1317 | { |
1318 | u32 offset; | |
1319 | u32 vfta_value = 0; | |
1320 | u32 vfta_offset = 0; | |
1321 | u32 vfta_bit_in_reg = 0; | |
1322 | ||
8c81c9c3 AD |
1323 | switch (hw->mac.type) { |
1324 | case e1000_82573: | |
1325 | case e1000_82574: | |
1326 | case e1000_82583: | |
bc7f75fa | 1327 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1328 | /* |
1329 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1330 | * a single VLAN ID. The following operations |
1331 | * determine which 32b entry (i.e. offset) into the | |
1332 | * array we want to set the VLAN ID (i.e. bit) of | |
1333 | * the manageability unit. | |
1334 | */ | |
1335 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1336 | E1000_VFTA_ENTRY_SHIFT) & | |
1337 | E1000_VFTA_ENTRY_MASK; | |
1338 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1339 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1340 | } | |
8c81c9c3 AD |
1341 | break; |
1342 | default: | |
1343 | break; | |
bc7f75fa AK |
1344 | } |
1345 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1346 | /* |
1347 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1348 | * manageability VLAN ID, then clear all bits except that of |
1349 | * the manageability unit. | |
1350 | */ | |
1351 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1352 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1353 | e1e_flush(); | |
1354 | } | |
1355 | } | |
1356 | ||
4662e82b BA |
1357 | /** |
1358 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1359 | * @hw: pointer to the HW structure | |
1360 | * | |
1361 | * Reads the NVM Initialization Control Word 2 and returns true | |
1362 | * (>0) if any manageability is enabled, else false (0). | |
1363 | **/ | |
1364 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1365 | { | |
1366 | u16 data; | |
1367 | ||
1368 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1369 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1370 | } | |
1371 | ||
1372 | /** | |
1373 | * e1000_led_on_82574 - Turn LED on | |
1374 | * @hw: pointer to the HW structure | |
1375 | * | |
1376 | * Turn LED on. | |
1377 | **/ | |
1378 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1379 | { | |
1380 | u32 ctrl; | |
1381 | u32 i; | |
1382 | ||
1383 | ctrl = hw->mac.ledctl_mode2; | |
1384 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1385 | /* | |
1386 | * If no link, then turn LED on by setting the invert bit | |
1387 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1388 | */ | |
1389 | for (i = 0; i < 4; i++) | |
1390 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1391 | E1000_LEDCTL_MODE_LED_ON) | |
1392 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1393 | } | |
1394 | ew32(LEDCTL, ctrl); | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
ff10e13c CW |
1399 | /** |
1400 | * e1000_check_phy_82574 - check 82574 phy hung state | |
1401 | * @hw: pointer to the HW structure | |
1402 | * | |
1403 | * Returns whether phy is hung or not | |
1404 | **/ | |
1405 | bool e1000_check_phy_82574(struct e1000_hw *hw) | |
1406 | { | |
1407 | u16 status_1kbt = 0; | |
1408 | u16 receive_errors = 0; | |
ff10e13c CW |
1409 | s32 ret_val = 0; |
1410 | ||
1411 | /* | |
1412 | * Read PHY Receive Error counter first, if its is max - all F's then | |
1413 | * read the Base1000T status register If both are max then PHY is hung. | |
1414 | */ | |
1415 | ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); | |
ff10e13c | 1416 | if (ret_val) |
5015e53a | 1417 | return false; |
ff10e13c CW |
1418 | if (receive_errors == E1000_RECEIVE_ERROR_MAX) { |
1419 | ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); | |
1420 | if (ret_val) | |
5015e53a | 1421 | return false; |
ff10e13c CW |
1422 | if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == |
1423 | E1000_IDLE_ERROR_COUNT_MASK) | |
5015e53a | 1424 | return true; |
ff10e13c | 1425 | } |
5015e53a BA |
1426 | |
1427 | return false; | |
ff10e13c CW |
1428 | } |
1429 | ||
bc7f75fa AK |
1430 | /** |
1431 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1432 | * @hw: pointer to the HW structure | |
1433 | * | |
1434 | * Determines which flow control settings to use, then configures flow | |
1435 | * control. Calls the appropriate media-specific link configuration | |
1436 | * function. Assuming the adapter has a valid link partner, a valid link | |
1437 | * should be established. Assumes the hardware has previously been reset | |
1438 | * and the transmitter and receiver are not enabled. | |
1439 | **/ | |
1440 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1441 | { | |
ad68076e BA |
1442 | /* |
1443 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1444 | * the default flow control setting, so we explicitly |
1445 | * set it to full. | |
1446 | */ | |
8c81c9c3 AD |
1447 | switch (hw->mac.type) { |
1448 | case e1000_82573: | |
1449 | case e1000_82574: | |
1450 | case e1000_82583: | |
1451 | if (hw->fc.requested_mode == e1000_fc_default) | |
1452 | hw->fc.requested_mode = e1000_fc_full; | |
1453 | break; | |
1454 | default: | |
1455 | break; | |
1456 | } | |
bc7f75fa AK |
1457 | |
1458 | return e1000e_setup_link(hw); | |
1459 | } | |
1460 | ||
1461 | /** | |
1462 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1463 | * @hw: pointer to the HW structure | |
1464 | * | |
1465 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1466 | * for link, once link is established calls to configure collision distance | |
1467 | * and flow control are called. | |
1468 | **/ | |
1469 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1470 | { | |
1471 | u32 ctrl; | |
bc7f75fa AK |
1472 | s32 ret_val; |
1473 | ||
1474 | ctrl = er32(CTRL); | |
1475 | ctrl |= E1000_CTRL_SLU; | |
1476 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1477 | ew32(CTRL, ctrl); | |
1478 | ||
1479 | switch (hw->phy.type) { | |
1480 | case e1000_phy_m88: | |
4662e82b | 1481 | case e1000_phy_bm: |
bc7f75fa AK |
1482 | ret_val = e1000e_copper_link_setup_m88(hw); |
1483 | break; | |
1484 | case e1000_phy_igp_2: | |
1485 | ret_val = e1000e_copper_link_setup_igp(hw); | |
bc7f75fa AK |
1486 | break; |
1487 | default: | |
1488 | return -E1000_ERR_PHY; | |
1489 | break; | |
1490 | } | |
1491 | ||
1492 | if (ret_val) | |
1493 | return ret_val; | |
1494 | ||
7eb61d81 | 1495 | return e1000e_setup_copper_link(hw); |
bc7f75fa AK |
1496 | } |
1497 | ||
1498 | /** | |
1499 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1500 | * @hw: pointer to the HW structure | |
1501 | * | |
1502 | * Configures collision distance and flow control for fiber and serdes links. | |
1503 | * Upon successful setup, poll for link. | |
1504 | **/ | |
1505 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1506 | { | |
1507 | switch (hw->mac.type) { | |
1508 | case e1000_82571: | |
1509 | case e1000_82572: | |
ad68076e BA |
1510 | /* |
1511 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1512 | * of reset to take the adapter out of that mode. So we |
1513 | * have to explicitly take the adapter out of loopback | |
489815ce | 1514 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1515 | * if another tool failed to take it out of loopback mode. |
1516 | */ | |
ad68076e | 1517 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1518 | break; |
1519 | default: | |
1520 | break; | |
1521 | } | |
1522 | ||
1523 | return e1000e_setup_fiber_serdes_link(hw); | |
1524 | } | |
1525 | ||
c9523379 | 1526 | /** |
1527 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1528 | * @hw: pointer to the HW structure | |
1529 | * | |
1a40d5c1 BA |
1530 | * Reports the link state as up or down. |
1531 | * | |
1532 | * If autonegotiation is supported by the link partner, the link state is | |
1533 | * determined by the result of autonegotiation. This is the most likely case. | |
1534 | * If autonegotiation is not supported by the link partner, and the link | |
1535 | * has a valid signal, force the link up. | |
1536 | * | |
1537 | * The link state is represented internally here by 4 states: | |
1538 | * | |
1539 | * 1) down | |
1540 | * 2) autoneg_progress | |
3ad2f3fb | 1541 | * 3) autoneg_complete (the link successfully autonegotiated) |
1a40d5c1 BA |
1542 | * 4) forced_up (the link has been forced up, it did not autonegotiate) |
1543 | * | |
c9523379 | 1544 | **/ |
f6370117 | 1545 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1546 | { |
1547 | struct e1000_mac_info *mac = &hw->mac; | |
1548 | u32 rxcw; | |
1549 | u32 ctrl; | |
1550 | u32 status; | |
d9c76f99 BA |
1551 | u32 txcw; |
1552 | u32 i; | |
c9523379 | 1553 | s32 ret_val = 0; |
1554 | ||
1555 | ctrl = er32(CTRL); | |
1556 | status = er32(STATUS); | |
1557 | rxcw = er32(RXCW); | |
1558 | ||
1559 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1560 | ||
1561 | /* Receiver is synchronized with no invalid bits. */ | |
1562 | switch (mac->serdes_link_state) { | |
1563 | case e1000_serdes_link_autoneg_complete: | |
1564 | if (!(status & E1000_STATUS_LU)) { | |
1565 | /* | |
1566 | * We have lost link, retry autoneg before | |
1567 | * reporting link failure | |
1568 | */ | |
1569 | mac->serdes_link_state = | |
1570 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1571 | mac->serdes_has_link = false; |
3bb99fe2 | 1572 | e_dbg("AN_UP -> AN_PROG\n"); |
a82a14f4 BA |
1573 | } else { |
1574 | mac->serdes_has_link = true; | |
c9523379 | 1575 | } |
a82a14f4 | 1576 | break; |
c9523379 | 1577 | |
1578 | case e1000_serdes_link_forced_up: | |
1579 | /* | |
1580 | * If we are receiving /C/ ordered sets, re-enable | |
1581 | * auto-negotiation in the TXCW register and disable | |
1582 | * forced link in the Device Control register in an | |
1583 | * attempt to auto-negotiate with our link partner. | |
d478eb44 BA |
1584 | * If the partner code word is null, stop forcing |
1585 | * and restart auto negotiation. | |
c9523379 | 1586 | */ |
d478eb44 | 1587 | if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { |
c9523379 | 1588 | /* Enable autoneg, and unforce link up */ |
1589 | ew32(TXCW, mac->txcw); | |
1a40d5c1 | 1590 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1591 | mac->serdes_link_state = |
1592 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1593 | mac->serdes_has_link = false; |
3bb99fe2 | 1594 | e_dbg("FORCED_UP -> AN_PROG\n"); |
a82a14f4 BA |
1595 | } else { |
1596 | mac->serdes_has_link = true; | |
c9523379 | 1597 | } |
1598 | break; | |
1599 | ||
1600 | case e1000_serdes_link_autoneg_progress: | |
1a40d5c1 BA |
1601 | if (rxcw & E1000_RXCW_C) { |
1602 | /* | |
1603 | * We received /C/ ordered sets, meaning the | |
1604 | * link partner has autonegotiated, and we can | |
1605 | * trust the Link Up (LU) status bit. | |
1606 | */ | |
1607 | if (status & E1000_STATUS_LU) { | |
1608 | mac->serdes_link_state = | |
1609 | e1000_serdes_link_autoneg_complete; | |
1610 | e_dbg("AN_PROG -> AN_UP\n"); | |
1611 | mac->serdes_has_link = true; | |
1612 | } else { | |
1613 | /* Autoneg completed, but failed. */ | |
1614 | mac->serdes_link_state = | |
1615 | e1000_serdes_link_down; | |
1616 | e_dbg("AN_PROG -> DOWN\n"); | |
1617 | } | |
c9523379 | 1618 | } else { |
1619 | /* | |
1a40d5c1 BA |
1620 | * The link partner did not autoneg. |
1621 | * Force link up and full duplex, and change | |
1622 | * state to forced. | |
c9523379 | 1623 | */ |
1a40d5c1 | 1624 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
c9523379 | 1625 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
1626 | ew32(CTRL, ctrl); | |
1627 | ||
1628 | /* Configure Flow Control after link up. */ | |
1a40d5c1 | 1629 | ret_val = e1000e_config_fc_after_link_up(hw); |
c9523379 | 1630 | if (ret_val) { |
3bb99fe2 | 1631 | e_dbg("Error config flow control\n"); |
c9523379 | 1632 | break; |
1633 | } | |
1634 | mac->serdes_link_state = | |
1635 | e1000_serdes_link_forced_up; | |
1a40d5c1 | 1636 | mac->serdes_has_link = true; |
3bb99fe2 | 1637 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1638 | } |
c9523379 | 1639 | break; |
1640 | ||
1641 | case e1000_serdes_link_down: | |
1642 | default: | |
1a40d5c1 BA |
1643 | /* |
1644 | * The link was down but the receiver has now gained | |
c9523379 | 1645 | * valid sync, so lets see if we can bring the link |
1a40d5c1 BA |
1646 | * up. |
1647 | */ | |
c9523379 | 1648 | ew32(TXCW, mac->txcw); |
1a40d5c1 | 1649 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1650 | mac->serdes_link_state = |
1651 | e1000_serdes_link_autoneg_progress; | |
a82a14f4 | 1652 | mac->serdes_has_link = false; |
3bb99fe2 | 1653 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1654 | break; |
1655 | } | |
1656 | } else { | |
1657 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1658 | mac->serdes_has_link = false; | |
1659 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1660 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1661 | } else { |
1662 | /* | |
d9c76f99 BA |
1663 | * Check several times, if Sync and Config |
1664 | * both are consistently 1 then simply ignore | |
1665 | * the Invalid bit and restart Autoneg | |
c9523379 | 1666 | */ |
d9c76f99 BA |
1667 | for (i = 0; i < AN_RETRY_COUNT; i++) { |
1668 | udelay(10); | |
1669 | rxcw = er32(RXCW); | |
1670 | if ((rxcw & E1000_RXCW_IV) && | |
1671 | !((rxcw & E1000_RXCW_SYNCH) && | |
1672 | (rxcw & E1000_RXCW_C))) { | |
1673 | mac->serdes_has_link = false; | |
1674 | mac->serdes_link_state = | |
1675 | e1000_serdes_link_down; | |
1676 | e_dbg("ANYSTATE -> DOWN\n"); | |
1677 | break; | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | if (i == AN_RETRY_COUNT) { | |
1682 | txcw = er32(TXCW); | |
1683 | txcw |= E1000_TXCW_ANE; | |
1684 | ew32(TXCW, txcw); | |
1685 | mac->serdes_link_state = | |
1686 | e1000_serdes_link_autoneg_progress; | |
c9523379 | 1687 | mac->serdes_has_link = false; |
d9c76f99 | 1688 | e_dbg("ANYSTATE -> AN_PROG\n"); |
c9523379 | 1689 | } |
1690 | } | |
1691 | } | |
1692 | ||
1693 | return ret_val; | |
1694 | } | |
1695 | ||
bc7f75fa AK |
1696 | /** |
1697 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1698 | * @hw: pointer to the HW structure | |
1699 | * @data: pointer to the NVM (EEPROM) | |
1700 | * | |
1701 | * Read the EEPROM for the current default LED configuration. If the | |
1702 | * LED configuration is not valid, set to a valid LED configuration. | |
1703 | **/ | |
1704 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1705 | { | |
1706 | s32 ret_val; | |
1707 | ||
1708 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1709 | if (ret_val) { | |
3bb99fe2 | 1710 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1711 | return ret_val; |
1712 | } | |
1713 | ||
8c81c9c3 AD |
1714 | switch (hw->mac.type) { |
1715 | case e1000_82573: | |
1716 | case e1000_82574: | |
1717 | case e1000_82583: | |
1718 | if (*data == ID_LED_RESERVED_F746) | |
1719 | *data = ID_LED_DEFAULT_82573; | |
1720 | break; | |
1721 | default: | |
1722 | if (*data == ID_LED_RESERVED_0000 || | |
1723 | *data == ID_LED_RESERVED_FFFF) | |
1724 | *data = ID_LED_DEFAULT; | |
1725 | break; | |
1726 | } | |
bc7f75fa AK |
1727 | |
1728 | return 0; | |
1729 | } | |
1730 | ||
1731 | /** | |
1732 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1733 | * @hw: pointer to the HW structure | |
1734 | * | |
489815ce | 1735 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1736 | **/ |
1737 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1738 | { | |
1739 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1740 | return false; |
bc7f75fa AK |
1741 | |
1742 | return hw->dev_spec.e82571.laa_is_present; | |
1743 | } | |
1744 | ||
1745 | /** | |
1746 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1747 | * @hw: pointer to the HW structure | |
1748 | * @state: enable/disable locally administered address | |
1749 | * | |
5ff5b664 | 1750 | * Enable/Disable the current locally administered address state. |
bc7f75fa AK |
1751 | **/ |
1752 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1753 | { | |
1754 | if (hw->mac.type != e1000_82571) | |
1755 | return; | |
1756 | ||
1757 | hw->dev_spec.e82571.laa_is_present = state; | |
1758 | ||
1759 | /* If workaround is activated... */ | |
1760 | if (state) | |
ad68076e BA |
1761 | /* |
1762 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1763 | * between the time RAR[0] gets clobbered and the time it |
1764 | * gets fixed, the actual LAA is in one of the RARs and no | |
1765 | * incoming packets directed to this port are dropped. | |
1766 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1767 | */ | |
1768 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1769 | } | |
1770 | ||
1771 | /** | |
1772 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1773 | * @hw: pointer to the HW structure | |
1774 | * | |
1775 | * Verifies that the EEPROM has completed the update. After updating the | |
1776 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1777 | * the checksum fix is not implemented, we need to set the bit and update | |
1778 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1779 | * we need to return bad checksum. | |
1780 | **/ | |
1781 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1782 | { | |
1783 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1784 | s32 ret_val; | |
1785 | u16 data; | |
1786 | ||
1787 | if (nvm->type != e1000_nvm_flash_hw) | |
1788 | return 0; | |
1789 | ||
ad68076e BA |
1790 | /* |
1791 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1792 | * 10h-12h. Checksum may need to be fixed. |
1793 | */ | |
1794 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1795 | if (ret_val) | |
1796 | return ret_val; | |
1797 | ||
1798 | if (!(data & 0x10)) { | |
ad68076e BA |
1799 | /* |
1800 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1801 | * when the checksum has already been fixed. If |
1802 | * the checksum is still wrong and this bit is a | |
1803 | * 1, we need to return bad checksum. Otherwise, | |
1804 | * we need to set this bit to a 1 and update the | |
1805 | * checksum. | |
1806 | */ | |
1807 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1808 | if (ret_val) | |
1809 | return ret_val; | |
1810 | ||
1811 | if (!(data & 0x8000)) { | |
1812 | data |= 0x8000; | |
1813 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1814 | if (ret_val) | |
1815 | return ret_val; | |
1816 | ret_val = e1000e_update_nvm_checksum(hw); | |
1817 | } | |
1818 | } | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
608f8a0d BA |
1823 | /** |
1824 | * e1000_read_mac_addr_82571 - Read device MAC address | |
1825 | * @hw: pointer to the HW structure | |
1826 | **/ | |
1827 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | |
1828 | { | |
1aef70ef | 1829 | if (hw->mac.type == e1000_82571) { |
5015e53a BA |
1830 | s32 ret_val = 0; |
1831 | ||
1aef70ef BA |
1832 | /* |
1833 | * If there's an alternate MAC address place it in RAR0 | |
1834 | * so that it will override the Si installed default perm | |
1835 | * address. | |
1836 | */ | |
1837 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1838 | if (ret_val) | |
5015e53a | 1839 | return ret_val; |
1aef70ef | 1840 | } |
608f8a0d | 1841 | |
5015e53a | 1842 | return e1000_read_mac_addr_generic(hw); |
608f8a0d BA |
1843 | } |
1844 | ||
17f208de BA |
1845 | /** |
1846 | * e1000_power_down_phy_copper_82571 - Remove link during PHY power down | |
1847 | * @hw: pointer to the HW structure | |
1848 | * | |
1849 | * In the case of a PHY power down to save power, or to turn off link during a | |
1850 | * driver unload, or wake on lan is not enabled, remove the link. | |
1851 | **/ | |
1852 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) | |
1853 | { | |
1854 | struct e1000_phy_info *phy = &hw->phy; | |
1855 | struct e1000_mac_info *mac = &hw->mac; | |
1856 | ||
668018d7 | 1857 | if (!phy->ops.check_reset_block) |
17f208de BA |
1858 | return; |
1859 | ||
1860 | /* If the management interface is not enabled, then power down */ | |
1861 | if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) | |
1862 | e1000_power_down_phy_copper(hw); | |
17f208de BA |
1863 | } |
1864 | ||
bc7f75fa AK |
1865 | /** |
1866 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1867 | * @hw: pointer to the HW structure | |
1868 | * | |
1869 | * Clears the hardware counters by reading the counter registers. | |
1870 | **/ | |
1871 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1872 | { | |
bc7f75fa AK |
1873 | e1000e_clear_hw_cntrs_base(hw); |
1874 | ||
99673d9b BA |
1875 | er32(PRC64); |
1876 | er32(PRC127); | |
1877 | er32(PRC255); | |
1878 | er32(PRC511); | |
1879 | er32(PRC1023); | |
1880 | er32(PRC1522); | |
1881 | er32(PTC64); | |
1882 | er32(PTC127); | |
1883 | er32(PTC255); | |
1884 | er32(PTC511); | |
1885 | er32(PTC1023); | |
1886 | er32(PTC1522); | |
1887 | ||
1888 | er32(ALGNERRC); | |
1889 | er32(RXERRC); | |
1890 | er32(TNCRS); | |
1891 | er32(CEXTERR); | |
1892 | er32(TSCTC); | |
1893 | er32(TSCTFC); | |
1894 | ||
1895 | er32(MGTPRC); | |
1896 | er32(MGTPDC); | |
1897 | er32(MGTPTC); | |
1898 | ||
1899 | er32(IAC); | |
1900 | er32(ICRXOC); | |
1901 | ||
1902 | er32(ICRXPTC); | |
1903 | er32(ICRXATC); | |
1904 | er32(ICTXPTC); | |
1905 | er32(ICTXATC); | |
1906 | er32(ICTXQEC); | |
1907 | er32(ICTXQMTC); | |
1908 | er32(ICRXDMTC); | |
bc7f75fa AK |
1909 | } |
1910 | ||
8ce9d6c7 | 1911 | static const struct e1000_mac_operations e82571_mac_ops = { |
4662e82b | 1912 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1913 | /* .check_for_link: media type dependent */ |
d1964eb1 | 1914 | .id_led_init = e1000e_id_led_init_generic, |
bc7f75fa AK |
1915 | .cleanup_led = e1000e_cleanup_led_generic, |
1916 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1917 | .get_bus_info = e1000e_get_bus_info_pcie, | |
f4d2dd4c | 1918 | .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
bc7f75fa | 1919 | /* .get_link_up_info: media type dependent */ |
4662e82b | 1920 | /* .led_on: mac type dependent */ |
bc7f75fa | 1921 | .led_off = e1000e_led_off_generic, |
ab8932f3 | 1922 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1923 | .write_vfta = e1000_write_vfta_generic, |
1924 | .clear_vfta = e1000_clear_vfta_82571, | |
bc7f75fa AK |
1925 | .reset_hw = e1000_reset_hw_82571, |
1926 | .init_hw = e1000_init_hw_82571, | |
1927 | .setup_link = e1000_setup_link_82571, | |
1928 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1929 | .setup_led = e1000e_setup_led_generic, |
608f8a0d | 1930 | .read_mac_addr = e1000_read_mac_addr_82571, |
bc7f75fa AK |
1931 | }; |
1932 | ||
8ce9d6c7 | 1933 | static const struct e1000_phy_operations e82_phy_ops_igp = { |
94d8186a | 1934 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1935 | .check_polarity = e1000_check_polarity_igp, |
bc7f75fa | 1936 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1937 | .commit = NULL, |
bc7f75fa AK |
1938 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1939 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1940 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1941 | .get_info = e1000e_get_phy_info_igp, |
1942 | .read_reg = e1000e_read_phy_reg_igp, | |
1943 | .release = e1000_put_hw_semaphore_82571, | |
1944 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1945 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1946 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1947 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1948 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1949 | }; |
1950 | ||
8ce9d6c7 | 1951 | static const struct e1000_phy_operations e82_phy_ops_m88 = { |
94d8186a | 1952 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1953 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1954 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1955 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1956 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1957 | .get_cfg_done = e1000e_get_cfg_done, | |
1958 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1959 | .get_info = e1000e_get_phy_info_m88, |
1960 | .read_reg = e1000e_read_phy_reg_m88, | |
1961 | .release = e1000_put_hw_semaphore_82571, | |
1962 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1963 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1964 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1965 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1966 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1967 | }; |
1968 | ||
8ce9d6c7 | 1969 | static const struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1970 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1971 | .check_polarity = e1000_check_polarity_m88, |
4662e82b | 1972 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1973 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1974 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1975 | .get_cfg_done = e1000e_get_cfg_done, | |
1976 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1977 | .get_info = e1000e_get_phy_info_m88, |
1978 | .read_reg = e1000e_read_phy_reg_bm2, | |
1979 | .release = e1000_put_hw_semaphore_82571, | |
1980 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1981 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1982 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1983 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1984 | .cfg_on_link_up = NULL, |
4662e82b BA |
1985 | }; |
1986 | ||
8ce9d6c7 | 1987 | static const struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1988 | .acquire = e1000_acquire_nvm_82571, |
1989 | .read = e1000e_read_nvm_eerd, | |
1990 | .release = e1000_release_nvm_82571, | |
1991 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1992 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1993 | .validate = e1000_validate_nvm_checksum_82571, |
1994 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1995 | }; |
1996 | ||
8ce9d6c7 | 1997 | const struct e1000_info e1000_82571_info = { |
bc7f75fa AK |
1998 | .mac = e1000_82571, |
1999 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2000 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
2001 | | FLAG_HAS_WOL |
2002 | | FLAG_APME_IN_CTRL3 | |
bc7f75fa | 2003 | | FLAG_HAS_CTRLEXT_ON_LOAD |
bc7f75fa AK |
2004 | | FLAG_HAS_SMART_POWER_DOWN |
2005 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
2006 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
2007 | | FLAG_APME_CHECK_PORT_B, | |
3a3b7586 JB |
2008 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
2009 | | FLAG2_DMA_BURST, | |
bc7f75fa | 2010 | .pba = 38, |
2adc55c9 | 2011 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 2012 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
2013 | .mac_ops = &e82571_mac_ops, |
2014 | .phy_ops = &e82_phy_ops_igp, | |
2015 | .nvm_ops = &e82571_nvm_ops, | |
2016 | }; | |
2017 | ||
8ce9d6c7 | 2018 | const struct e1000_info e1000_82572_info = { |
bc7f75fa AK |
2019 | .mac = e1000_82572, |
2020 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2021 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
2022 | | FLAG_HAS_WOL |
2023 | | FLAG_APME_IN_CTRL3 | |
bc7f75fa | 2024 | | FLAG_HAS_CTRLEXT_ON_LOAD |
bc7f75fa | 2025 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
3a3b7586 JB |
2026 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
2027 | | FLAG2_DMA_BURST, | |
bc7f75fa | 2028 | .pba = 38, |
2adc55c9 | 2029 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 2030 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
2031 | .mac_ops = &e82571_mac_ops, |
2032 | .phy_ops = &e82_phy_ops_igp, | |
2033 | .nvm_ops = &e82571_nvm_ops, | |
2034 | }; | |
2035 | ||
8ce9d6c7 | 2036 | const struct e1000_info e1000_82573_info = { |
bc7f75fa AK |
2037 | .mac = e1000_82573, |
2038 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
bc7f75fa AK |
2039 | | FLAG_HAS_WOL |
2040 | | FLAG_APME_IN_CTRL3 | |
bc7f75fa AK |
2041 | | FLAG_HAS_SMART_POWER_DOWN |
2042 | | FLAG_HAS_AMT | |
bc7f75fa | 2043 | | FLAG_HAS_SWSM_ON_LOAD, |
78cd29d5 BA |
2044 | .flags2 = FLAG2_DISABLE_ASPM_L1 |
2045 | | FLAG2_DISABLE_ASPM_L0S, | |
bc7f75fa | 2046 | .pba = 20, |
2adc55c9 | 2047 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 2048 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
2049 | .mac_ops = &e82571_mac_ops, |
2050 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 2051 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
2052 | }; |
2053 | ||
8ce9d6c7 | 2054 | const struct e1000_info e1000_82574_info = { |
4662e82b BA |
2055 | .mac = e1000_82574, |
2056 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2057 | | FLAG_HAS_MSIX | |
2058 | | FLAG_HAS_JUMBO_FRAMES | |
2059 | | FLAG_HAS_WOL | |
2060 | | FLAG_APME_IN_CTRL3 | |
4662e82b BA |
2061 | | FLAG_HAS_SMART_POWER_DOWN |
2062 | | FLAG_HAS_AMT | |
2063 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
78cd29d5 | 2064 | .flags2 = FLAG2_CHECK_PHY_HANG |
7f99ae63 BA |
2065 | | FLAG2_DISABLE_ASPM_L0S |
2066 | | FLAG2_NO_DISABLE_RX, | |
ed5c2b0b | 2067 | .pba = 32, |
a825e00c | 2068 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
2069 | .get_variants = e1000_get_variants_82571, |
2070 | .mac_ops = &e82571_mac_ops, | |
2071 | .phy_ops = &e82_phy_ops_bm, | |
2072 | .nvm_ops = &e82571_nvm_ops, | |
2073 | }; | |
2074 | ||
8ce9d6c7 | 2075 | const struct e1000_info e1000_82583_info = { |
8c81c9c3 AD |
2076 | .mac = e1000_82583, |
2077 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2078 | | FLAG_HAS_WOL | |
2079 | | FLAG_APME_IN_CTRL3 | |
8c81c9c3 AD |
2080 | | FLAG_HAS_SMART_POWER_DOWN |
2081 | | FLAG_HAS_AMT | |
a3d72d5d | 2082 | | FLAG_HAS_JUMBO_FRAMES |
8c81c9c3 | 2083 | | FLAG_HAS_CTRLEXT_ON_LOAD, |
7f99ae63 BA |
2084 | .flags2 = FLAG2_DISABLE_ASPM_L0S |
2085 | | FLAG2_NO_DISABLE_RX, | |
ed5c2b0b | 2086 | .pba = 32, |
a3d72d5d | 2087 | .max_hw_frame_size = DEFAULT_JUMBO, |
8c81c9c3 AD |
2088 | .get_variants = e1000_get_variants_82571, |
2089 | .mac_ops = &e82571_mac_ops, | |
2090 | .phy_ops = &e82_phy_ops_bm, | |
2091 | .nvm_ops = &e82571_nvm_ops, | |
2092 | }; | |
2093 |