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e78b80b1 | 1 | /* Intel PRO/1000 Linux driver |
529498cd | 2 | * Copyright(c) 1999 - 2015 Intel Corporation. |
e78b80b1 DE |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * Linux NICS <linux.nics@intel.com> | |
18 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
20 | */ | |
bc7f75fa AK |
21 | |
22 | #ifndef _E1000_DEFINES_H_ | |
23 | #define _E1000_DEFINES_H_ | |
24 | ||
bc7f75fa AK |
25 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ |
26 | #define REQ_TX_DESCRIPTOR_MULTIPLE 8 | |
27 | #define REQ_RX_DESCRIPTOR_MULTIPLE 8 | |
28 | ||
29 | /* Definitions for power management and wakeup registers */ | |
30 | /* Wake Up Control */ | |
74f350ee DE |
31 | #define E1000_WUC_APME 0x00000001 /* APM Enable */ |
32 | #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ | |
33 | #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ | |
34 | #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ | |
35 | #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ | |
bc7f75fa AK |
36 | |
37 | /* Wake Up Filter Control */ | |
38 | #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | |
39 | #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | |
40 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | |
41 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ | |
42 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | |
efb90e43 | 43 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
bc7f75fa | 44 | |
a4f58f54 BA |
45 | /* Wake Up Status */ |
46 | #define E1000_WUS_LNKC E1000_WUFC_LNKC | |
47 | #define E1000_WUS_MAG E1000_WUFC_MAG | |
48 | #define E1000_WUS_EX E1000_WUFC_EX | |
49 | #define E1000_WUS_MC E1000_WUFC_MC | |
50 | #define E1000_WUS_BC E1000_WUFC_BC | |
51 | ||
bc7f75fa | 52 | /* Extended Device Control */ |
2fbe4526 | 53 | #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ |
93a23f48 | 54 | #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ |
ba9e186f | 55 | #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ |
bc7f75fa | 56 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ |
1d5846b9 | 57 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ |
bc7f75fa | 58 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
5df3f0ea | 59 | #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ |
bc7f75fa AK |
60 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
61 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 | |
4662e82b | 62 | #define E1000_CTRL_EXT_EIAME 0x01000000 |
bc7f75fa | 63 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ |
c29c3ba5 | 64 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ |
4662e82b | 65 | #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ |
23e4f061 | 66 | #define E1000_CTRL_EXT_LSECCK 0x00001000 |
a4f58f54 | 67 | #define E1000_CTRL_EXT_PHYPDEN 0x00100000 |
bc7f75fa | 68 | |
489815ce | 69 | /* Receive Descriptor bit definitions */ |
bc7f75fa AK |
70 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
71 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | |
72 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | |
73 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | |
489815ce | 74 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
bc7f75fa AK |
75 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
76 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | |
77 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | |
78 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | |
79 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ | |
80 | #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ | |
2e1706f2 | 81 | #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ |
bc7f75fa AK |
82 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ |
83 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | |
84 | ||
b67e1913 | 85 | #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ |
bc7f75fa AK |
86 | #define E1000_RXDEXT_STATERR_CE 0x01000000 |
87 | #define E1000_RXDEXT_STATERR_SE 0x02000000 | |
88 | #define E1000_RXDEXT_STATERR_SEQ 0x04000000 | |
89 | #define E1000_RXDEXT_STATERR_CXE 0x10000000 | |
90 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 | |
91 | ||
92 | /* mask to determine if packets should be dropped due to frame errors */ | |
93 | #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ | |
55c5f55e BA |
94 | E1000_RXD_ERR_CE | \ |
95 | E1000_RXD_ERR_SE | \ | |
96 | E1000_RXD_ERR_SEQ | \ | |
97 | E1000_RXD_ERR_CXE | \ | |
98 | E1000_RXD_ERR_RXE) | |
bc7f75fa AK |
99 | |
100 | /* Same mask, but for extended and packet split descriptors */ | |
101 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ | |
55c5f55e BA |
102 | E1000_RXDEXT_STATERR_CE | \ |
103 | E1000_RXDEXT_STATERR_SE | \ | |
104 | E1000_RXDEXT_STATERR_SEQ | \ | |
105 | E1000_RXDEXT_STATERR_CXE | \ | |
106 | E1000_RXDEXT_STATERR_RXE) | |
bc7f75fa | 107 | |
70495a50 BA |
108 | #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 |
109 | #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 | |
110 | #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 | |
111 | #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 | |
112 | #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 | |
113 | #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 | |
114 | ||
bc7f75fa AK |
115 | #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 |
116 | ||
117 | /* Management Control */ | |
118 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | |
119 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | |
120 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | |
121 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | |
122 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | |
ad68076e BA |
123 | /* Enable MAC address filtering */ |
124 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 | |
125 | /* Enable MNG packets to host memory */ | |
126 | #define E1000_MANC_EN_MNG2HOST 0x00200000 | |
bc7f75fa | 127 | |
cd791618 BA |
128 | #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ |
129 | #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ | |
130 | #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ | |
131 | #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ | |
132 | ||
bc7f75fa AK |
133 | /* Receive Control */ |
134 | #define E1000_RCTL_EN 0x00000002 /* enable */ | |
135 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ | |
136 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ | |
137 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ | |
138 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | |
139 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | |
140 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | |
141 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | |
142 | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | |
ad68076e | 143 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ |
79849ebc | 144 | #define E1000_RCTL_RDMTS_HEX 0x00010000 |
bc7f75fa | 145 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ |
a4f58f54 | 146 | #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ |
bc7f75fa AK |
147 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ |
148 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | |
ad68076e BA |
149 | #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ |
150 | #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ | |
151 | #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ | |
152 | #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ | |
bc7f75fa | 153 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ |
ad68076e BA |
154 | #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ |
155 | #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ | |
156 | #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ | |
bc7f75fa AK |
157 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ |
158 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ | |
159 | #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ | |
cf955e6c | 160 | #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ |
a4f58f54 | 161 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ |
bc7f75fa AK |
162 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ |
163 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ | |
164 | ||
e921eb1a | 165 | /* Use byte values for the following shift parameters |
bc7f75fa AK |
166 | * Usage: |
167 | * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & | |
168 | * E1000_PSRCTL_BSIZE0_MASK) | | |
169 | * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & | |
170 | * E1000_PSRCTL_BSIZE1_MASK) | | |
171 | * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & | |
172 | * E1000_PSRCTL_BSIZE2_MASK) | | |
173 | * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; | |
174 | * E1000_PSRCTL_BSIZE3_MASK)) | |
175 | * where value0 = [128..16256], default=256 | |
176 | * value1 = [1024..64512], default=4096 | |
177 | * value2 = [0..64512], default=4096 | |
178 | * value3 = [0..64512], default=0 | |
179 | */ | |
180 | ||
181 | #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F | |
182 | #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 | |
183 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 | |
184 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 | |
185 | ||
186 | #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ | |
187 | #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ | |
188 | #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ | |
189 | #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ | |
190 | ||
191 | /* SWFW_SYNC Definitions */ | |
192 | #define E1000_SWFW_EEP_SM 0x1 | |
193 | #define E1000_SWFW_PHY0_SM 0x2 | |
194 | #define E1000_SWFW_PHY1_SM 0x4 | |
2d9498f3 | 195 | #define E1000_SWFW_CSR_SM 0x8 |
bc7f75fa AK |
196 | |
197 | /* Device Control */ | |
198 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | |
199 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | |
200 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | |
201 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | |
202 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | |
203 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | |
204 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ | |
205 | #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ | |
206 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ | |
207 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | |
208 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | |
209 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | |
6dfaa769 BA |
210 | #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ |
211 | #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ | |
94fb848b | 212 | #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ |
bc7f75fa AK |
213 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
214 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | |
3ffcf2cb BA |
215 | #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ |
216 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ | |
bc7f75fa AK |
217 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
218 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ | |
219 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | |
220 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | |
221 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ | |
222 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ | |
223 | ||
1241f29f BA |
224 | #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 |
225 | ||
226 | #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 | |
bc7f75fa AK |
227 | |
228 | /* Device Status */ | |
229 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ | |
230 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | |
231 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | |
232 | #define E1000_STATUS_FUNC_SHIFT 2 | |
233 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | |
234 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | |
772d05c5 | 235 | #define E1000_STATUS_SPEED_MASK 0x000000C0 |
bc7f75fa AK |
236 | #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ |
237 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | |
238 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | |
239 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ | |
fc0c7760 | 240 | #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ |
c29c3ba5 | 241 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master Req status */ |
bc7f75fa | 242 | |
bc7f75fa AK |
243 | #define HALF_DUPLEX 1 |
244 | #define FULL_DUPLEX 2 | |
245 | ||
bc7f75fa AK |
246 | #define ADVERTISE_10_HALF 0x0001 |
247 | #define ADVERTISE_10_FULL 0x0002 | |
248 | #define ADVERTISE_100_HALF 0x0004 | |
249 | #define ADVERTISE_100_FULL 0x0008 | |
250 | #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ | |
251 | #define ADVERTISE_1000_FULL 0x0020 | |
252 | ||
253 | /* 1000/H is not supported, nor spec-compliant. */ | |
55c5f55e BA |
254 | #define E1000_ALL_SPEED_DUPLEX ( \ |
255 | ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ | |
256 | ADVERTISE_100_FULL | ADVERTISE_1000_FULL) | |
257 | #define E1000_ALL_NOT_GIG ( \ | |
258 | ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ | |
259 | ADVERTISE_100_FULL) | |
260 | #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) | |
261 | #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) | |
262 | #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) | |
bc7f75fa AK |
263 | |
264 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX | |
265 | ||
266 | /* LED Control */ | |
a4f58f54 BA |
267 | #define E1000_PHY_LED0_MODE_MASK 0x00000007 |
268 | #define E1000_PHY_LED0_IVRT 0x00000008 | |
269 | #define E1000_PHY_LED0_MASK 0x0000001F | |
270 | ||
bc7f75fa AK |
271 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F |
272 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 | |
273 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 | |
274 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 | |
275 | ||
a4f58f54 | 276 | #define E1000_LEDCTL_MODE_LINK_UP 0x2 |
bc7f75fa AK |
277 | #define E1000_LEDCTL_MODE_LED_ON 0xE |
278 | #define E1000_LEDCTL_MODE_LED_OFF 0xF | |
279 | ||
280 | /* Transmit Descriptor bit definitions */ | |
281 | #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ | |
282 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | |
283 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | |
284 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | |
285 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
286 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | |
287 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | |
288 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ | |
289 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | |
290 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | |
291 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ | |
292 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | |
293 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ | |
294 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ | |
295 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ | |
296 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ | |
297 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ | |
298 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ | |
299 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ | |
b67e1913 | 300 | #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ |
bc7f75fa AK |
301 | |
302 | /* Transmit Control */ | |
ad68076e | 303 | #define E1000_TCTL_EN 0x00000002 /* enable Tx */ |
bc7f75fa AK |
304 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ |
305 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ | |
306 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ | |
307 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | |
308 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ | |
309 | ||
bc7f75fa AK |
310 | /* SerDes Control */ |
311 | #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 | |
3ffcf2cb | 312 | #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 |
bc7f75fa AK |
313 | |
314 | /* Receive Checksum Control */ | |
315 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ | |
316 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | |
70495a50 | 317 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ |
bc7f75fa AK |
318 | |
319 | /* Header split receive */ | |
a80483d3 JB |
320 | #define E1000_RFCTL_NFSW_DIS 0x00000040 |
321 | #define E1000_RFCTL_NFSR_DIS 0x00000080 | |
4662e82b | 322 | #define E1000_RFCTL_ACK_DIS 0x00001000 |
bc7f75fa AK |
323 | #define E1000_RFCTL_EXTEN 0x00008000 |
324 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 | |
325 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | |
326 | ||
327 | /* Collision related configuration parameters */ | |
328 | #define E1000_COLLISION_THRESHOLD 15 | |
329 | #define E1000_CT_SHIFT 4 | |
330 | #define E1000_COLLISION_DISTANCE 63 | |
331 | #define E1000_COLD_SHIFT 12 | |
332 | ||
333 | /* Default values for the transmit IPG register */ | |
334 | #define DEFAULT_82543_TIPG_IPGT_COPPER 8 | |
335 | ||
336 | #define E1000_TIPG_IPGT_MASK 0x000003FF | |
337 | ||
338 | #define DEFAULT_82543_TIPG_IPGR1 8 | |
339 | #define E1000_TIPG_IPGR1_SHIFT 10 | |
340 | ||
341 | #define DEFAULT_82543_TIPG_IPGR2 6 | |
342 | #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 | |
343 | #define E1000_TIPG_IPGR2_SHIFT 20 | |
344 | ||
345 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 | |
493004d0 | 346 | #define E1000_TX_PTR_GAP 0x1F |
bc7f75fa AK |
347 | |
348 | /* Extended Configuration Control and Size */ | |
349 | #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 | |
350 | #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 | |
f523d211 | 351 | #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 |
bc7f75fa | 352 | #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 |
d3738bb8 | 353 | #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 |
bc7f75fa AK |
354 | #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 |
355 | #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 | |
356 | #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 | |
357 | #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 | |
358 | ||
359 | #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 | |
360 | #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 | |
361 | #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 | |
362 | #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 | |
363 | ||
364 | #define E1000_KABGTXD_BGSQLBIAS 0x00050000 | |
365 | ||
203e4151 BA |
366 | /* Low Power IDLE Control */ |
367 | #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ | |
368 | ||
bc7f75fa | 369 | /* PBA constants */ |
ad68076e BA |
370 | #define E1000_PBA_8K 0x0008 /* 8KB */ |
371 | #define E1000_PBA_16K 0x0010 /* 16KB */ | |
bc7f75fa | 372 | |
3e35d991 BA |
373 | #define E1000_PBA_RXA_MASK 0xFFFF |
374 | ||
bc7f75fa AK |
375 | #define E1000_PBS_16K E1000_PBA_16K |
376 | ||
94fb848b BA |
377 | /* Uncorrectable/correctable ECC Error counts and enable bits */ |
378 | #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF | |
379 | #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 | |
380 | #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 | |
381 | #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 | |
382 | ||
bc7f75fa AK |
383 | #define IFS_MAX 80 |
384 | #define IFS_MIN 40 | |
385 | #define IFS_RATIO 4 | |
386 | #define IFS_STEP 10 | |
387 | #define MIN_NUM_XMITS 1000 | |
388 | ||
389 | /* SW Semaphore Register */ | |
390 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | |
391 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | |
392 | #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ | |
23a2d1b2 DG |
393 | |
394 | #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ | |
bc7f75fa AK |
395 | |
396 | /* Interrupt Cause Read */ | |
397 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | |
398 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ | |
ad68076e BA |
399 | #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ |
400 | #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ | |
4aea7a5c | 401 | #define E1000_ICR_RXO 0x00000040 /* Receiver Overrun */ |
ad68076e | 402 | #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ |
116f4a64 BP |
403 | #define E1000_ICR_MDAC 0x00000200 /* MDIO Access Complete */ |
404 | #define E1000_ICR_SRPD 0x00010000 /* Small Receive Packet Detected */ | |
405 | #define E1000_ICR_ACK 0x00020000 /* Receive ACK Frame Detected */ | |
406 | #define E1000_ICR_MNG 0x00040000 /* Manageability Event Detected */ | |
94fb848b | 407 | #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ |
c29c3ba5 BA |
408 | /* If this bit asserted, the driver should claim the interrupt */ |
409 | #define E1000_ICR_INT_ASSERTED 0x80000000 | |
4662e82b BA |
410 | #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ |
411 | #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ | |
412 | #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ | |
413 | #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ | |
116f4a64 | 414 | #define E1000_ICR_OTHER 0x01000000 /* Other Interrupt */ |
bc7f75fa | 415 | |
6ea7ae1d AD |
416 | /* PBA ECC Register */ |
417 | #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ | |
418 | #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ | |
419 | #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ | |
420 | #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ | |
421 | #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ | |
422 | ||
e921eb1a | 423 | /* This defines the bits that are set in the Interrupt Mask |
bc7f75fa AK |
424 | * Set/Read Register. Each bit is documented below: |
425 | * o RXT0 = Receiver Timer Interrupt (ring 0) | |
426 | * o TXDW = Transmit Descriptor Written Back | |
427 | * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) | |
428 | * o RXSEQ = Receive Sequence Error | |
429 | * o LSC = Link Status Change | |
430 | */ | |
431 | #define IMS_ENABLE_MASK ( \ | |
55c5f55e BA |
432 | E1000_IMS_RXT0 | \ |
433 | E1000_IMS_TXDW | \ | |
434 | E1000_IMS_RXDMT0 | \ | |
435 | E1000_IMS_RXSEQ | \ | |
436 | E1000_IMS_LSC) | |
bc7f75fa | 437 | |
116f4a64 BP |
438 | /* These are all of the events related to the OTHER interrupt. |
439 | */ | |
440 | #define IMS_OTHER_MASK ( \ | |
441 | E1000_IMS_LSC | \ | |
442 | E1000_IMS_RXO | \ | |
443 | E1000_IMS_MDAC | \ | |
444 | E1000_IMS_SRPD | \ | |
445 | E1000_IMS_ACK | \ | |
446 | E1000_IMS_MNG) | |
447 | ||
bc7f75fa AK |
448 | /* Interrupt Mask Set */ |
449 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | |
450 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ | |
ad68076e BA |
451 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ |
452 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ | |
116f4a64 | 453 | #define E1000_IMS_RXO E1000_ICR_RXO /* Receiver Overrun */ |
ad68076e | 454 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ |
116f4a64 BP |
455 | #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO Access Complete */ |
456 | #define E1000_IMS_SRPD E1000_ICR_SRPD /* Small Receive Packet */ | |
457 | #define E1000_IMS_ACK E1000_ICR_ACK /* Receive ACK Frame Detected */ | |
458 | #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability Event */ | |
94fb848b | 459 | #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ |
4662e82b BA |
460 | #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ |
461 | #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ | |
462 | #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ | |
463 | #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ | |
a61cfe4f | 464 | #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupt */ |
bc7f75fa AK |
465 | |
466 | /* Interrupt Cause Set */ | |
467 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | |
f8d59f78 | 468 | #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ |
ad68076e | 469 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ |
a61cfe4f | 470 | #define E1000_ICS_OTHER E1000_ICR_OTHER /* Other Interrupt */ |
bc7f75fa AK |
471 | |
472 | /* Transmit Descriptor Control */ | |
473 | #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ | |
3a3b7586 | 474 | #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ |
bc7f75fa | 475 | #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ |
3a3b7586 | 476 | #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ |
bc7f75fa AK |
477 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ |
478 | #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ | |
ad68076e BA |
479 | /* Enable the counting of desc. still to be processed. */ |
480 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 | |
bc7f75fa AK |
481 | |
482 | /* Flow Control Constants */ | |
483 | #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 | |
484 | #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 | |
485 | #define FLOW_CONTROL_TYPE 0x8808 | |
486 | ||
487 | /* 802.1q VLAN Packet Size */ | |
488 | #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ | |
489 | ||
e921eb1a | 490 | /* Receive Address |
ad68076e | 491 | * Number of high/low register pairs in the RAR. The RAR (Receive Address |
bc7f75fa AK |
492 | * Registers) holds the directed and multicast addresses that we monitor. |
493 | * Technically, we have 16 spots. However, we reserve one of these spots | |
494 | * (RAR[15]) for our directed address used by controllers with | |
495 | * manageability enabled, allowing us room for 15 multicast addresses. | |
496 | */ | |
497 | #define E1000_RAR_ENTRIES 15 | |
498 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | |
608f8a0d BA |
499 | #define E1000_RAL_MAC_ADDR_LEN 4 |
500 | #define E1000_RAH_MAC_ADDR_LEN 2 | |
bc7f75fa AK |
501 | |
502 | /* Error Codes */ | |
503 | #define E1000_ERR_NVM 1 | |
504 | #define E1000_ERR_PHY 2 | |
505 | #define E1000_ERR_CONFIG 3 | |
506 | #define E1000_ERR_PARAM 4 | |
507 | #define E1000_ERR_MAC_INIT 5 | |
508 | #define E1000_ERR_PHY_TYPE 6 | |
509 | #define E1000_ERR_RESET 9 | |
510 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 | |
511 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 | |
512 | #define E1000_BLK_PHY_RESET 12 | |
513 | #define E1000_ERR_SWFW_SYNC 13 | |
514 | #define E1000_NOT_IMPLEMENTED 14 | |
073287c0 BA |
515 | #define E1000_ERR_INVALID_ARGUMENT 16 |
516 | #define E1000_ERR_NO_SPACE 17 | |
517 | #define E1000_ERR_NVM_PBA_SECTION 18 | |
bc7f75fa AK |
518 | |
519 | /* Loop limit on how long we wait for auto-negotiation to complete */ | |
520 | #define FIBER_LINK_UP_LIMIT 50 | |
521 | #define COPPER_LINK_UP_LIMIT 10 | |
522 | #define PHY_AUTO_NEG_LIMIT 45 | |
523 | #define PHY_FORCE_LIMIT 20 | |
524 | /* Number of 100 microseconds we wait for PCI Express master disable */ | |
525 | #define MASTER_DISABLE_TIMEOUT 800 | |
526 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ | |
527 | #define PHY_CFG_TIMEOUT 100 | |
528 | /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ | |
529 | #define MDIO_OWNERSHIP_TIMEOUT 10 | |
530 | /* Number of milliseconds for NVM auto read done after MAC reset. */ | |
531 | #define AUTO_READ_DONE_TIMEOUT 10 | |
532 | ||
533 | /* Flow Control */ | |
3ec2a2b8 BA |
534 | #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ |
535 | #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ | |
bc7f75fa AK |
536 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
537 | ||
538 | /* Transmit Configuration Word */ | |
539 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ | |
540 | #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ | |
541 | #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ | |
542 | #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ | |
543 | #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ | |
544 | ||
545 | /* Receive Configuration Word */ | |
d478eb44 | 546 | #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ |
bc7f75fa AK |
547 | #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ |
548 | #define E1000_RXCW_C 0x20000000 /* Receive config */ | |
549 | #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ | |
550 | ||
01d7ada5 CH |
551 | /* HH Time Sync */ |
552 | #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ | |
553 | #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ | |
554 | #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ | |
555 | ||
b67e1913 | 556 | #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ |
b67e1913 BA |
557 | #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ |
558 | ||
559 | #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ | |
560 | #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ | |
d89777bf BA |
561 | #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 |
562 | #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 | |
563 | #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 | |
564 | #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 | |
565 | #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A | |
b67e1913 BA |
566 | #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ |
567 | #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ | |
568 | ||
d89777bf BA |
569 | #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 |
570 | #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 | |
571 | ||
572 | #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 | |
573 | #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 | |
574 | ||
b67e1913 BA |
575 | #define E1000_TIMINCA_INCPERIOD_SHIFT 24 |
576 | #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF | |
577 | ||
bc7f75fa AK |
578 | /* PCI Express Control */ |
579 | #define E1000_GCR_RXD_NO_SNOOP 0x00000001 | |
580 | #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 | |
581 | #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 | |
582 | #define E1000_GCR_TXD_NO_SNOOP 0x00000008 | |
583 | #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 | |
584 | #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 | |
585 | ||
586 | #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ | |
587 | E1000_GCR_RXDSCW_NO_SNOOP | \ | |
588 | E1000_GCR_RXDSCR_NO_SNOOP | \ | |
589 | E1000_GCR_TXD_NO_SNOOP | \ | |
590 | E1000_GCR_TXDSCW_NO_SNOOP | \ | |
591 | E1000_GCR_TXDSCR_NO_SNOOP) | |
592 | ||
bc7f75fa AK |
593 | /* NVM Control */ |
594 | #define E1000_EECD_SK 0x00000001 /* NVM Clock */ | |
595 | #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ | |
596 | #define E1000_EECD_DI 0x00000004 /* NVM Data In */ | |
597 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ | |
598 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ | |
599 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ | |
f4187b56 | 600 | #define E1000_EECD_PRES 0x00000100 /* NVM Present */ |
bc7f75fa | 601 | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ |
ad68076e BA |
602 | /* NVM Addressing bits based on type (0-small, 1-large) */ |
603 | #define E1000_EECD_ADDR_BITS 0x00000400 | |
bc7f75fa AK |
604 | #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ |
605 | #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ | |
606 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ | |
607 | #define E1000_EECD_SIZE_EX_SHIFT 11 | |
608 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | |
609 | #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ | |
610 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | |
e243455d | 611 | #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) |
bc7f75fa | 612 | |
c29c3ba5 BA |
613 | #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM r/w regs */ |
614 | #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ | |
615 | #define E1000_NVM_RW_REG_START 1 /* Start operation */ | |
616 | #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | |
617 | #define E1000_NVM_POLL_WRITE 1 /* Flag for polling write complete */ | |
618 | #define E1000_NVM_POLL_READ 0 /* Flag for polling read complete */ | |
619 | #define E1000_FLASH_UPDATES 2000 | |
bc7f75fa AK |
620 | |
621 | /* NVM Word Offsets */ | |
1aef70ef | 622 | #define NVM_COMPAT 0x0003 |
bc7f75fa | 623 | #define NVM_ID_LED_SETTINGS 0x0004 |
1cc7a3a1 BA |
624 | #define NVM_FUTURE_INIT_WORD1 0x0019 |
625 | #define NVM_COMPAT_VALID_CSUM 0x0001 | |
626 | #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 | |
627 | ||
bc7f75fa AK |
628 | #define NVM_INIT_CONTROL2_REG 0x000F |
629 | #define NVM_INIT_CONTROL3_PORT_B 0x0014 | |
630 | #define NVM_INIT_3GIO_3 0x001A | |
631 | #define NVM_INIT_CONTROL3_PORT_A 0x0024 | |
632 | #define NVM_CFG 0x0012 | |
93ca1610 | 633 | #define NVM_ALT_MAC_ADDR_PTR 0x0037 |
bc7f75fa AK |
634 | #define NVM_CHECKSUM_REG 0x003F |
635 | ||
636 | #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ | |
637 | #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ | |
638 | ||
639 | /* Mask bits for fields in Word 0x0f of the NVM */ | |
640 | #define NVM_WORD0F_PAUSE_MASK 0x3000 | |
641 | #define NVM_WORD0F_PAUSE 0x1000 | |
642 | #define NVM_WORD0F_ASM_DIR 0x2000 | |
643 | ||
644 | /* Mask bits for fields in Word 0x1a of the NVM */ | |
645 | #define NVM_WORD1A_ASPM_MASK 0x000C | |
646 | ||
1aef70ef BA |
647 | /* Mask bits for fields in Word 0x03 of the EEPROM */ |
648 | #define NVM_COMPAT_LOM 0x0800 | |
649 | ||
073287c0 BA |
650 | /* length of string needed to store PBA number */ |
651 | #define E1000_PBANUM_LENGTH 11 | |
652 | ||
bc7f75fa AK |
653 | /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ |
654 | #define NVM_SUM 0xBABA | |
655 | ||
656 | /* PBA (printed board assembly) number words */ | |
657 | #define NVM_PBA_OFFSET_0 8 | |
658 | #define NVM_PBA_OFFSET_1 9 | |
073287c0 | 659 | #define NVM_PBA_PTR_GUARD 0xFAFA |
bc7f75fa AK |
660 | #define NVM_WORD_SIZE_BASE_SHIFT 6 |
661 | ||
662 | /* NVM Commands - SPI */ | |
663 | #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ | |
664 | #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ | |
665 | #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ | |
666 | #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ | |
667 | #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ | |
668 | #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ | |
669 | ||
670 | /* SPI NVM Status Register */ | |
671 | #define NVM_STATUS_RDY_SPI 0x01 | |
672 | ||
673 | /* Word definitions for ID LED Settings */ | |
674 | #define ID_LED_RESERVED_0000 0x0000 | |
675 | #define ID_LED_RESERVED_FFFF 0xFFFF | |
676 | #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ | |
677 | (ID_LED_OFF1_OFF2 << 8) | \ | |
678 | (ID_LED_DEF1_DEF2 << 4) | \ | |
679 | (ID_LED_DEF1_DEF2)) | |
680 | #define ID_LED_DEF1_DEF2 0x1 | |
681 | #define ID_LED_DEF1_ON2 0x2 | |
682 | #define ID_LED_DEF1_OFF2 0x3 | |
683 | #define ID_LED_ON1_DEF2 0x4 | |
684 | #define ID_LED_ON1_ON2 0x5 | |
685 | #define ID_LED_ON1_OFF2 0x6 | |
686 | #define ID_LED_OFF1_DEF2 0x7 | |
687 | #define ID_LED_OFF1_ON2 0x8 | |
688 | #define ID_LED_OFF1_OFF2 0x9 | |
689 | ||
690 | #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF | |
691 | #define IGP_ACTIVITY_LED_ENABLE 0x0300 | |
692 | #define IGP_LED3_MODE 0x07000000 | |
693 | ||
694 | /* PCI/PCI-X/PCI-EX Config space */ | |
695 | #define PCI_HEADER_TYPE_REGISTER 0x0E | |
696 | #define PCIE_LINK_STATUS 0x12 | |
697 | ||
698 | #define PCI_HEADER_TYPE_MULTIFUNC 0x80 | |
699 | #define PCIE_LINK_WIDTH_MASK 0x3F0 | |
700 | #define PCIE_LINK_WIDTH_SHIFT 4 | |
701 | ||
702 | #define PHY_REVISION_MASK 0xFFFFFFF0 | |
703 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ | |
704 | #define MAX_PHY_MULTI_PAGE_REG 0xF | |
705 | ||
e921eb1a | 706 | /* Bit definitions for valid PHY IDs. |
ad68076e | 707 | * I = Integrated |
bc7f75fa AK |
708 | * E = External |
709 | */ | |
710 | #define M88E1000_E_PHY_ID 0x01410C50 | |
711 | #define M88E1000_I_PHY_ID 0x01410C30 | |
712 | #define M88E1011_I_PHY_ID 0x01410C20 | |
713 | #define IGP01E1000_I_PHY_ID 0x02A80380 | |
714 | #define M88E1111_I_PHY_ID 0x01410CC0 | |
715 | #define GG82563_E_PHY_ID 0x01410CA0 | |
716 | #define IGP03E1000_E_PHY_ID 0x02A80390 | |
717 | #define IFE_E_PHY_ID 0x02A80330 | |
718 | #define IFE_PLUS_E_PHY_ID 0x02A80320 | |
719 | #define IFE_C_E_PHY_ID 0x02A80310 | |
97ac8cae BA |
720 | #define BME1000_E_PHY_ID 0x01410CB0 |
721 | #define BME1000_E_PHY_ID_R2 0x01410CB1 | |
a4f58f54 BA |
722 | #define I82577_E_PHY_ID 0x01540050 |
723 | #define I82578_E_PHY_ID 0x004DD040 | |
d3738bb8 | 724 | #define I82579_E_PHY_ID 0x01540090 |
2fbe4526 | 725 | #define I217_E_PHY_ID 0x015400A0 |
bc7f75fa AK |
726 | |
727 | /* M88E1000 Specific Registers */ | |
728 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ | |
729 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ | |
730 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ | |
731 | ||
732 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ | |
733 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ | |
734 | ||
735 | /* M88E1000 PHY Specific Control Register */ | |
736 | #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ | |
737 | #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ | |
738 | /* Manual MDI configuration */ | |
739 | #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ | |
ad68076e BA |
740 | /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ |
741 | #define M88E1000_PSCR_AUTO_X_1000T 0x0040 | |
742 | /* Auto crossover enabled all speeds */ | |
743 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 | |
ad68076e | 744 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |
bc7f75fa AK |
745 | |
746 | /* M88E1000 PHY Specific Status Register */ | |
747 | #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ | |
748 | #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ | |
749 | #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ | |
ad68076e BA |
750 | /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ |
751 | #define M88E1000_PSSR_CABLE_LENGTH 0x0380 | |
bc7f75fa AK |
752 | #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
753 | #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | |
754 | ||
755 | #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 | |
756 | ||
e921eb1a | 757 | /* Number of times we will attempt to autonegotiate before downshifting if we |
ad68076e BA |
758 | * are the master |
759 | */ | |
bc7f75fa AK |
760 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 |
761 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 | |
e921eb1a | 762 | /* Number of times we will attempt to autonegotiate before downshifting if we |
ad68076e BA |
763 | * are the slave |
764 | */ | |
bc7f75fa AK |
765 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 |
766 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 | |
767 | #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ | |
768 | ||
769 | /* M88EC018 Rev 2 specific DownShift settings */ | |
770 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 | |
771 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 | |
772 | ||
a4f58f54 BA |
773 | #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 |
774 | #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C | |
775 | ||
97ac8cae BA |
776 | /* BME1000 PHY Specific Control Register */ |
777 | #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ | |
778 | ||
e921eb1a | 779 | /* Bits... |
bc7f75fa AK |
780 | * 15-5: page |
781 | * 4-0: register offset | |
782 | */ | |
783 | #define GG82563_PAGE_SHIFT 5 | |
784 | #define GG82563_REG(page, reg) \ | |
785 | (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) | |
786 | #define GG82563_MIN_ALT_REG 30 | |
787 | ||
788 | /* GG82563 Specific Registers */ | |
789 | #define GG82563_PHY_SPEC_CTRL \ | |
790 | GG82563_REG(0, 16) /* PHY Specific Control */ | |
791 | #define GG82563_PHY_PAGE_SELECT \ | |
792 | GG82563_REG(0, 22) /* Page Select */ | |
793 | #define GG82563_PHY_SPEC_CTRL_2 \ | |
794 | GG82563_REG(0, 26) /* PHY Specific Control 2 */ | |
795 | #define GG82563_PHY_PAGE_SELECT_ALT \ | |
796 | GG82563_REG(0, 29) /* Alternate Page Select */ | |
797 | ||
798 | #define GG82563_PHY_MAC_SPEC_CTRL \ | |
799 | GG82563_REG(2, 21) /* MAC Specific Control Register */ | |
800 | ||
801 | #define GG82563_PHY_DSP_DISTANCE \ | |
802 | GG82563_REG(5, 26) /* DSP Distance */ | |
803 | ||
804 | /* Page 193 - Port Control Registers */ | |
805 | #define GG82563_PHY_KMRN_MODE_CTRL \ | |
806 | GG82563_REG(193, 16) /* Kumeran Mode Control */ | |
807 | #define GG82563_PHY_PWR_MGMT_CTRL \ | |
808 | GG82563_REG(193, 20) /* Power Management Control */ | |
809 | ||
810 | /* Page 194 - KMRN Registers */ | |
811 | #define GG82563_PHY_INBAND_CTRL \ | |
812 | GG82563_REG(194, 18) /* Inband Control */ | |
813 | ||
814 | /* MDI Control */ | |
bb034512 | 815 | #define E1000_MDIC_REG_MASK 0x001F0000 |
bc7f75fa AK |
816 | #define E1000_MDIC_REG_SHIFT 16 |
817 | #define E1000_MDIC_PHY_SHIFT 21 | |
818 | #define E1000_MDIC_OP_WRITE 0x04000000 | |
819 | #define E1000_MDIC_OP_READ 0x08000000 | |
820 | #define E1000_MDIC_READY 0x10000000 | |
821 | #define E1000_MDIC_ERROR 0x40000000 | |
822 | ||
823 | /* SerDes Control */ | |
824 | #define E1000_GEN_POLL_TIMEOUT 640 | |
825 | ||
826 | #endif /* _E1000_DEFINES_H_ */ |