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e1000e: 82579 potential system hang on stress when ME enabled
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / e1000e / hw.h
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bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
32#include <linux/types.h>
33
34struct e1000_hw;
35struct e1000_adapter;
36
37#include "defines.h"
38
bc7f75fa
AK		 39enum e1e_registers {
40 E1000_CTRL = 0x00000, /* Device Control - RW */
41 E1000_STATUS = 0x00008, /* Device Status - RO */
42 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
43 E1000_EERD = 0x00014, /* EEPROM Read - RW */
44 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
45 E1000_FLA = 0x0001C, /* Flash Access - RW */
46 E1000_MDIC = 0x00020, /* MDI Control - RW */
47 E1000_SCTL = 0x00024, /* SerDes Control - RW */
48 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
49 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
831bd2e6 50 E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
bc7f75fa
AK		 51 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
52 E1000_FCT = 0x00030, /* Flow Control Type - RW */
53 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
54 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
55 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
56 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
57 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
58 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
4662e82b 59 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
bc7f75fa 60 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
4662e82b
BA		 61 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
62 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
63#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
ad68076e 64 E1000_RCTL = 0x00100, /* Rx Control - RW */
bc7f75fa 65 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
ad68076e
BA		 66 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
67 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
68 E1000_TCTL = 0x00400, /* Tx Control - RW */
69 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
70 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
71 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
bc7f75fa
AK		 72 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
73 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
74 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
75 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
77996d1d 76#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
bc7f75fa
AK		 77 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
78 E1000_PBS = 0x01008, /* Packet Buffer Size */
79 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
80 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
81 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
6ea7ae1d 82 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
bc7f75fa
AK		 83 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
84 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
85 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
86 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
1e36052e
BA		 87/*
88 * Convenience macros
bc7f75fa
AK		 89 *
90 * Note: "_n" is the queue number of the register to be written to.
91 *
92 * Example usage:
1e36052e 93 * E1000_RDBAL(current_rx_queue)
bc7f75fa 94 */
1e36052e
BA		 95 E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
96#define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
97 E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
98#define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
99 E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
100#define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
101 E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
102#define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
103 E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
104#define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
105 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
106 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
107#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
108 E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
109
bc7f75fa 110 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
1e36052e
BA		 111 E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
112#define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
113 E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
114#define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
115 E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
116#define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
117 E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
118#define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
119 E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
120#define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
ad68076e 121 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
e9ec2c0f
JK		 122 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
123#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
ad68076e 124 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
e9ec2c0f
JK		 125 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
126#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
bc7f75fa
AK		 127 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
128 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
129 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
130 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
131 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
132 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
133 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
134 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
135 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
136 E1000_COLC = 0x04028, /* Collision Count - R/clr */
137 E1000_DC = 0x04030, /* Defer Count - R/clr */
ad68076e 138 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
bc7f75fa
AK		 139 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
140 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
141 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
ad68076e
BA		 142 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
143 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
144 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
145 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
146 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
147 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
148 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
149 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
150 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
151 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
152 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
153 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
154 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
155 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
156 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
157 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
158 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
159 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
160 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
161 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
162 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
163 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
164 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
165 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
166 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
bc7f75fa 167 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
ad68076e
BA		 168 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
169 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
170 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
171 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
172 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
173 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
174 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
175 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
176 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
177 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
178 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
179 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
180 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
181 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
182 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
183 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
184 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
bc7f75fa
AK		 185 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
186 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
187 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
188 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
189 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
190 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
191 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
192 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
193 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
ad68076e 194 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
489815ce 195 E1000_RFCTL = 0x05008, /* Receive Filter Control */
bc7f75fa 196 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
a4f58f54
BA		 197 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
198#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
199#define E1000_RA (E1000_RAL(0))
200 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
201#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
bc7f75fa
AK		 202 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
203 E1000_WUC = 0x05800, /* Wakeup Control - RW */
204 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
205 E1000_WUS = 0x05810, /* Wakeup Status - RO */
70495a50 206 E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
bc7f75fa
AK		 207 E1000_MANC = 0x05820, /* Management Control - RW */
208 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
209 E1000_HOST_IF = 0x08800, /* Host Interface */
210
211 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
212 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
cd791618
BA		 213 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
214#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
bc7f75fa
AK		 215 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
216 E1000_GCR = 0x05B00, /* PCI-Ex Control */
78272bba 217 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
bc7f75fa
AK		 218 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
219 E1000_SWSM = 0x05B50, /* SW Semaphore */
220 E1000_FWSM = 0x05B54, /* FW Semaphore */
23a2d1b2 221 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
70495a50
BA		 222 E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
223#define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
224 E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
225#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
d3738bb8
BA		 226 E1000_FFLT_DBG = 0x05F04, /* Debug Register */
227 E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
228#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
229#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
489815ce 230 E1000_HICR = 0x08F00, /* Host Interface Control */
bc7f75fa
AK		 231};
232
5eb6f3c7 233#define E1000_MAX_PHY_ADDR 4
bc7f75fa
AK		 234
235/* IGP01E1000 Specific Registers */
236#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
237#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
238#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
239#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
240#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
241#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
97ac8cae
BA		 242#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
243#define IGP_PAGE_SHIFT 5
244#define PHY_REG_MASK 0x1F
245
246#define BM_WUC_PAGE 800
247#define BM_WUC_ADDRESS_OPCODE 0x11
248#define BM_WUC_DATA_OPCODE 0x12
249#define BM_WUC_ENABLE_PAGE 769
250#define BM_WUC_ENABLE_REG 17
251#define BM_WUC_ENABLE_BIT (1 << 2)
252#define BM_WUC_HOST_WU_BIT (1 << 4)
2b6b168d 253#define BM_WUC_ME_WU_BIT (1 << 5)
97ac8cae
BA		 254
255#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
256#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
257#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
bc7f75fa
AK		 258
259#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
260#define IGP01E1000_PHY_POLARITY_MASK 0x0078
261
262#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
263#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
264
265#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
266
267#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
268#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
269#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
270
271#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
272
273#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
cbe7a81a 274#define IGP01E1000_PSSR_MDIX 0x0800
bc7f75fa
AK		 275#define IGP01E1000_PSSR_SPEED_MASK 0xC000
276#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
277
278#define IGP02E1000_PHY_CHANNEL_NUM 4
279#define IGP02E1000_PHY_AGC_A 0x11B1
280#define IGP02E1000_PHY_AGC_B 0x12B1
281#define IGP02E1000_PHY_AGC_C 0x14B1
282#define IGP02E1000_PHY_AGC_D 0x18B1
283
284#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
285#define IGP02E1000_AGC_LENGTH_MASK 0x7F
286#define IGP02E1000_AGC_RANGE 15
287
288/* manage.c */
289#define E1000_VFTA_ENTRY_SHIFT 5
290#define E1000_VFTA_ENTRY_MASK 0x7F
291#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
292
293#define E1000_HICR_EN 0x01 /* Enable bit - RO */
ad68076e
BA		 294/* Driver sets this bit when done to put command in RAM */
295#define E1000_HICR_C 0x02
bc7f75fa
AK		 296#define E1000_HICR_FW_RESET_ENABLE 0x40
297#define E1000_HICR_FW_RESET 0x80
298
299#define E1000_FWSM_MODE_MASK 0xE
300#define E1000_FWSM_MODE_SHIFT 1
301
302#define E1000_MNG_IAMT_MODE 0x3
303#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
304#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
305#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
306#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
307#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
308#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
309
310/* nvm.c */
311#define E1000_STM_OPCODE 0xDB00
312
313#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
314#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
315#define E1000_KMRNCTRLSTA_REN 0x00200000
d3738bb8 316#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
bc7f75fa 317#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
07818950
BA		 318#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
319#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
d9b24135 320#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
bc7f75fa 321#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
7d3cabbc 322#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
ff847ac2 323#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
96f2bd13 324#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
bc7f75fa
AK		 325
326#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
327#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
328#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
329#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
330
331/* IFE PHY Extended Status Control */
332#define IFE_PESC_POLARITY_REVERSED 0x0100
333
334/* IFE PHY Special Control */
335#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
336#define IFE_PSC_FORCE_POLARITY 0x0020
337
338/* IFE PHY Special Control and LED Control */
339#define IFE_PSCL_PROBE_MODE 0x0020
340#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
341#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
342
343/* IFE PHY MDIX Control */
344#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
345#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
346#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
347
348#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
349
350#define E1000_DEV_ID_82571EB_COPPER 0x105E
351#define E1000_DEV_ID_82571EB_FIBER 0x105F
352#define E1000_DEV_ID_82571EB_SERDES 0x1060
353#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
040babf9 354#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
bc7f75fa
AK		 355#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
356#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
040babf9
AK		 357#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
358#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
bc7f75fa
AK		 359#define E1000_DEV_ID_82572EI_COPPER 0x107D
360#define E1000_DEV_ID_82572EI_FIBER 0x107E
361#define E1000_DEV_ID_82572EI_SERDES 0x107F
362#define E1000_DEV_ID_82572EI 0x10B9
363#define E1000_DEV_ID_82573E 0x108B
364#define E1000_DEV_ID_82573E_IAMT 0x108C
365#define E1000_DEV_ID_82573L 0x109A
4662e82b 366#define E1000_DEV_ID_82574L 0x10D3
bef28b11 367#define E1000_DEV_ID_82574LA 0x10F6
8c81c9c3 368#define E1000_DEV_ID_82583V 0x150C
bc7f75fa
AK		 369
370#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
371#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
372#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
373#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
374
9e135a2e 375#define E1000_DEV_ID_ICH8_82567V_3 0x1501
bc7f75fa
AK		 376#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
377#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
378#define E1000_DEV_ID_ICH8_IGP_C 0x104B
379#define E1000_DEV_ID_ICH8_IFE 0x104C
380#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
381#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
382#define E1000_DEV_ID_ICH8_IGP_M 0x104D
383#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
2f15f9d6 384#define E1000_DEV_ID_ICH9_BM 0x10E5
97ac8cae
BA		 385#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
386#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
387#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
bc7f75fa
AK		 388#define E1000_DEV_ID_ICH9_IGP_C 0x294C
389#define E1000_DEV_ID_ICH9_IFE 0x10C0
390#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
391#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
97ac8cae
BA		 392#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
393#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
394#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
f4187b56
BA		 395#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
396#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
10df0b91 397#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
a4f58f54
BA		 398#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
399#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
400#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
401#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
d3738bb8
BA		 402#define E1000_DEV_ID_PCH2_LV_LM 0x1502
403#define E1000_DEV_ID_PCH2_LV_V 0x1503
bc7f75fa 404
4662e82b
BA		 405#define E1000_REVISION_4 4
406
bc7f75fa
AK		 407#define E1000_FUNC_1 1
408
608f8a0d
BA		 409#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
410#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
411
bc7f75fa
AK		 412enum e1000_mac_type {
413 e1000_82571,
414 e1000_82572,
415 e1000_82573,
4662e82b 416 e1000_82574,
8c81c9c3 417 e1000_82583,
bc7f75fa
AK		 418 e1000_80003es2lan,
419 e1000_ich8lan,
420 e1000_ich9lan,
f4187b56 421 e1000_ich10lan,
a4f58f54 422 e1000_pchlan,
d3738bb8 423 e1000_pch2lan,
bc7f75fa
AK		 424};
425
426enum e1000_media_type {
427 e1000_media_type_unknown = 0,
428 e1000_media_type_copper = 1,
429 e1000_media_type_fiber = 2,
430 e1000_media_type_internal_serdes = 3,
431 e1000_num_media_types
432};
433
434enum e1000_nvm_type {
435 e1000_nvm_unknown = 0,
436 e1000_nvm_none,
437 e1000_nvm_eeprom_spi,
438 e1000_nvm_flash_hw,
439 e1000_nvm_flash_sw
440};
441
442enum e1000_nvm_override {
443 e1000_nvm_override_none = 0,
444 e1000_nvm_override_spi_small,
445 e1000_nvm_override_spi_large
446};
447
448enum e1000_phy_type {
449 e1000_phy_unknown = 0,
450 e1000_phy_none,
451 e1000_phy_m88,
452 e1000_phy_igp,
453 e1000_phy_igp_2,
454 e1000_phy_gg82563,
455 e1000_phy_igp_3,
456 e1000_phy_ife,
97ac8cae 457 e1000_phy_bm,
a4f58f54
BA		 458 e1000_phy_82578,
459 e1000_phy_82577,
d3738bb8 460 e1000_phy_82579,
bc7f75fa
AK		 461};
462
463enum e1000_bus_width {
464 e1000_bus_width_unknown = 0,
465 e1000_bus_width_pcie_x1,
466 e1000_bus_width_pcie_x2,
467 e1000_bus_width_pcie_x4 = 4,
468 e1000_bus_width_32,
469 e1000_bus_width_64,
470 e1000_bus_width_reserved
471};
472
473enum e1000_1000t_rx_status {
474 e1000_1000t_rx_status_not_ok = 0,
475 e1000_1000t_rx_status_ok,
476 e1000_1000t_rx_status_undefined = 0xFF
477};
478
479enum e1000_rev_polarity{
480 e1000_rev_polarity_normal = 0,
481 e1000_rev_polarity_reversed,
482 e1000_rev_polarity_undefined = 0xFF
483};
484
5c48ef3e 485enum e1000_fc_mode {
bc7f75fa
AK		 486 e1000_fc_none = 0,
487 e1000_fc_rx_pause,
488 e1000_fc_tx_pause,
489 e1000_fc_full,
490 e1000_fc_default = 0xFF
491};
492
493enum e1000_ms_type {
494 e1000_ms_hw_default = 0,
495 e1000_ms_force_master,
496 e1000_ms_force_slave,
497 e1000_ms_auto
498};
499
500enum e1000_smart_speed {
501 e1000_smart_speed_default = 0,
502 e1000_smart_speed_on,
503 e1000_smart_speed_off
504};
505
c9523379 506enum e1000_serdes_link_state {
507 e1000_serdes_link_down = 0,
508 e1000_serdes_link_autoneg_progress,
509 e1000_serdes_link_autoneg_complete,
510 e1000_serdes_link_forced_up
511};
512
bc7f75fa
AK		 513/* Receive Descriptor */
514struct e1000_rx_desc {
a39fe742
AV		 515 __le64 buffer_addr; /* Address of the descriptor's data buffer */
516 __le16 length; /* Length of data DMAed into data buffer */
517 __le16 csum; /* Packet checksum */
bc7f75fa
AK		 518 u8 status; /* Descriptor status */
519 u8 errors; /* Descriptor Errors */
a39fe742 520 __le16 special;
bc7f75fa
AK		 521};
522
523/* Receive Descriptor - Extended */
524union e1000_rx_desc_extended {
525 struct {
a39fe742
AV		 526 __le64 buffer_addr;
527 __le64 reserved;
bc7f75fa
AK		 528 } read;
529 struct {
530 struct {
a39fe742 531 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 532 union {
a39fe742 533 __le32 rss; /* RSS Hash */
bc7f75fa 534 struct {
a39fe742
AV		 535 __le16 ip_id; /* IP id */
536 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 537 } csum_ip;
538 } hi_dword;
539 } lower;
540 struct {
a39fe742
AV		 541 __le32 status_error; /* ext status/error */
542 __le16 length;
543 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 544 } upper;
545 } wb; /* writeback */
546};
547
548#define MAX_PS_BUFFERS 4
549/* Receive Descriptor - Packet Split */
550union e1000_rx_desc_packet_split {
551 struct {
552 /* one buffer for protocol header(s), three data buffers */
a39fe742 553 __le64 buffer_addr[MAX_PS_BUFFERS];
bc7f75fa
AK		 554 } read;
555 struct {
556 struct {
a39fe742 557 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 558 union {
a39fe742 559 __le32 rss; /* RSS Hash */
bc7f75fa 560 struct {
a39fe742
AV		 561 __le16 ip_id; /* IP id */
562 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 563 } csum_ip;
564 } hi_dword;
565 } lower;
566 struct {
a39fe742
AV		 567 __le32 status_error; /* ext status/error */
568 __le16 length0; /* length of buffer 0 */
569 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 570 } middle;
571 struct {
a39fe742
AV		 572 __le16 header_status;
573 __le16 length[3]; /* length of buffers 1-3 */
bc7f75fa 574 } upper;
a39fe742 575 __le64 reserved;
bc7f75fa
AK		 576 } wb; /* writeback */
577};
578
579/* Transmit Descriptor */
580struct e1000_tx_desc {
a39fe742 581 __le64 buffer_addr; /* Address of the descriptor's data buffer */
bc7f75fa 582 union {
a39fe742 583 __le32 data;
bc7f75fa 584 struct {
a39fe742 585 __le16 length; /* Data buffer length */
bc7f75fa
AK		 586 u8 cso; /* Checksum offset */
587 u8 cmd; /* Descriptor control */
588 } flags;
589 } lower;
590 union {
a39fe742 591 __le32 data;
bc7f75fa
AK		 592 struct {
593 u8 status; /* Descriptor status */
594 u8 css; /* Checksum start */
a39fe742 595 __le16 special;
bc7f75fa
AK		 596 } fields;
597 } upper;
598};
599
600/* Offload Context Descriptor */
601struct e1000_context_desc {
602 union {
a39fe742 603 __le32 ip_config;
bc7f75fa
AK		 604 struct {
605 u8 ipcss; /* IP checksum start */
606 u8 ipcso; /* IP checksum offset */
a39fe742 607 __le16 ipcse; /* IP checksum end */
bc7f75fa
AK		 608 } ip_fields;
609 } lower_setup;
610 union {
a39fe742 611 __le32 tcp_config;
bc7f75fa
AK		 612 struct {
613 u8 tucss; /* TCP checksum start */
614 u8 tucso; /* TCP checksum offset */
a39fe742 615 __le16 tucse; /* TCP checksum end */
bc7f75fa
AK		 616 } tcp_fields;
617 } upper_setup;
a39fe742 618 __le32 cmd_and_length;
bc7f75fa 619 union {
a39fe742 620 __le32 data;
bc7f75fa
AK		 621 struct {
622 u8 status; /* Descriptor status */
623 u8 hdr_len; /* Header length */
a39fe742 624 __le16 mss; /* Maximum segment size */
bc7f75fa
AK		 625 } fields;
626 } tcp_seg_setup;
627};
628
629/* Offload data descriptor */
630struct e1000_data_desc {
a39fe742 631 __le64 buffer_addr; /* Address of the descriptor's buffer address */
bc7f75fa 632 union {
a39fe742 633 __le32 data;
bc7f75fa 634 struct {
a39fe742 635 __le16 length; /* Data buffer length */
bc7f75fa
AK		 636 u8 typ_len_ext;
637 u8 cmd;
638 } flags;
639 } lower;
640 union {
a39fe742 641 __le32 data;
bc7f75fa
AK		 642 struct {
643 u8 status; /* Descriptor status */
644 u8 popts; /* Packet Options */
a39fe742 645 __le16 special; /* */
bc7f75fa
AK		 646 } fields;
647 } upper;
648};
649
650/* Statistics counters collected by the MAC */
651struct e1000_hw_stats {
652 u64 crcerrs;
653 u64 algnerrc;
654 u64 symerrs;
655 u64 rxerrc;
656 u64 mpc;
657 u64 scc;
658 u64 ecol;
659 u64 mcc;
660 u64 latecol;
661 u64 colc;
662 u64 dc;
663 u64 tncrs;
664 u64 sec;
665 u64 cexterr;
666 u64 rlec;
667 u64 xonrxc;
668 u64 xontxc;
669 u64 xoffrxc;
670 u64 xofftxc;
671 u64 fcruc;
672 u64 prc64;
673 u64 prc127;
674 u64 prc255;
675 u64 prc511;
676 u64 prc1023;
677 u64 prc1522;
678 u64 gprc;
679 u64 bprc;
680 u64 mprc;
681 u64 gptc;
7c25769f
BA		 682 u64 gorc;
683 u64 gotc;
bc7f75fa
AK		 684 u64 rnbc;
685 u64 ruc;
686 u64 rfc;
687 u64 roc;
688 u64 rjc;
689 u64 mgprc;
690 u64 mgpdc;
691 u64 mgptc;
7c25769f
BA		 692 u64 tor;
693 u64 tot;
bc7f75fa
AK		 694 u64 tpr;
695 u64 tpt;
696 u64 ptc64;
697 u64 ptc127;
698 u64 ptc255;
699 u64 ptc511;
700 u64 ptc1023;
701 u64 ptc1522;
702 u64 mptc;
703 u64 bptc;
704 u64 tsctc;
705 u64 tsctfc;
706 u64 iac;
707 u64 icrxptc;
708 u64 icrxatc;
709 u64 ictxptc;
710 u64 ictxatc;
711 u64 ictxqec;
712 u64 ictxqmtc;
713 u64 icrxdmtc;
714 u64 icrxoc;
715};
716
717struct e1000_phy_stats {
718 u32 idle_errors;
719 u32 receive_errors;
720};
721
722struct e1000_host_mng_dhcp_cookie {
723 u32 signature;
724 u8 status;
725 u8 reserved0;
726 u16 vlan_id;
727 u32 reserved1;
728 u16 reserved2;
729 u8 reserved3;
730 u8 checksum;
731};
732
733/* Host Interface "Rev 1" */
734struct e1000_host_command_header {
735 u8 command_id;
736 u8 command_length;
737 u8 command_options;
738 u8 checksum;
739};
740
741#define E1000_HI_MAX_DATA_LENGTH 252
742struct e1000_host_command_info {
743 struct e1000_host_command_header command_header;
744 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
745};
746
747/* Host Interface "Rev 2" */
748struct e1000_host_mng_command_header {
749 u8 command_id;
750 u8 checksum;
751 u16 reserved1;
752 u16 reserved2;
753 u16 command_length;
754};
755
756#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
757struct e1000_host_mng_command_info {
758 struct e1000_host_mng_command_header command_header;
759 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
760};
761
762/* Function pointers and static data for the MAC. */
763struct e1000_mac_operations {
a4f58f54 764 s32 (*id_led_init)(struct e1000_hw *);
dbf80dcb 765 s32 (*blink_led)(struct e1000_hw *);
4662e82b 766 bool (*check_mng_mode)(struct e1000_hw *);
bc7f75fa
AK		 767 s32 (*check_for_link)(struct e1000_hw *);
768 s32 (*cleanup_led)(struct e1000_hw *);
769 void (*clear_hw_cntrs)(struct e1000_hw *);
caaddaf8 770 void (*clear_vfta)(struct e1000_hw *);
bc7f75fa 771 s32 (*get_bus_info)(struct e1000_hw *);
f4d2dd4c 772 void (*set_lan_id)(struct e1000_hw *);
bc7f75fa
AK		 773 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
774 s32 (*led_on)(struct e1000_hw *);
775 s32 (*led_off)(struct e1000_hw *);
ab8932f3 776 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
bc7f75fa
AK		 777 s32 (*reset_hw)(struct e1000_hw *);
778 s32 (*init_hw)(struct e1000_hw *);
779 s32 (*setup_link)(struct e1000_hw *);
780 s32 (*setup_physical_interface)(struct e1000_hw *);
a4f58f54 781 s32 (*setup_led)(struct e1000_hw *);
caaddaf8 782 void (*write_vfta)(struct e1000_hw *, u32, u32);
57cde763 783 void (*config_collision_dist)(struct e1000_hw *);
608f8a0d 784 s32 (*read_mac_addr)(struct e1000_hw *);
bc7f75fa
AK		 785};
786
2b6b168d
BA		 787/*
788 * When to use various PHY register access functions:
789 *
790 * Func Caller
791 * Function Does Does When to use
792 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
793 * X_reg L,P,A n/a for simple PHY reg accesses
794 * X_reg_locked P,A L for multiple accesses of different regs
795 * on different pages
796 * X_reg_page A L,P for multiple accesses of different regs
797 * on the same page
798 *
799 * Where X=[read|write], L=locking, P=sets page, A=register access
800 *
801 */
bc7f75fa 802struct e1000_phy_operations {
94d8186a
BA		 803 s32 (*acquire)(struct e1000_hw *);
804 s32 (*cfg_on_link_up)(struct e1000_hw *);
a4f58f54 805 s32 (*check_polarity)(struct e1000_hw *);
bc7f75fa 806 s32 (*check_reset_block)(struct e1000_hw *);
94d8186a 807 s32 (*commit)(struct e1000_hw *);
bc7f75fa
AK		 808 s32 (*force_speed_duplex)(struct e1000_hw *);
809 s32 (*get_cfg_done)(struct e1000_hw *hw);
810 s32 (*get_cable_length)(struct e1000_hw *);
94d8186a 811 s32 (*get_info)(struct e1000_hw *);
2b6b168d 812 s32 (*set_page)(struct e1000_hw *, u16);
94d8186a
BA		 813 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
814 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
2b6b168d 815 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
94d8186a
BA		 816 void (*release)(struct e1000_hw *);
817 s32 (*reset)(struct e1000_hw *);
bc7f75fa
AK		 818 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
819 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
94d8186a
BA		 820 s32 (*write_reg)(struct e1000_hw *, u32, u16);
821 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
2b6b168d 822 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
17f208de
BA		 823 void (*power_up)(struct e1000_hw *);
824 void (*power_down)(struct e1000_hw *);
bc7f75fa
AK		 825};
826
827/* Function pointers for the NVM. */
828struct e1000_nvm_operations {
94d8186a
BA		 829 s32 (*acquire)(struct e1000_hw *);
830 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
831 void (*release)(struct e1000_hw *);
e85e3639 832 void (*reload)(struct e1000_hw *);
94d8186a 833 s32 (*update)(struct e1000_hw *);
bc7f75fa 834 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
94d8186a
BA		 835 s32 (*validate)(struct e1000_hw *);
836 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
bc7f75fa
AK		 837};
838
839struct e1000_mac_info {
840 struct e1000_mac_operations ops;
d8d5f8ae
BA		 841 u8 addr[ETH_ALEN];
842 u8 perm_addr[ETH_ALEN];
bc7f75fa
AK		 843
844 enum e1000_mac_type type;
bc7f75fa
AK		 845
846 u32 collision_delta;
847 u32 ledctl_default;
848 u32 ledctl_mode1;
849 u32 ledctl_mode2;
bc7f75fa 850 u32 mc_filter_type;
bc7f75fa
AK		 851 u32 tx_packet_delta;
852 u32 txcw;
853
854 u16 current_ifs_val;
855 u16 ifs_max_val;
856 u16 ifs_min_val;
857 u16 ifs_ratio;
858 u16 ifs_step_size;
859 u16 mta_reg_count;
ab8932f3
BA		 860
861 /* Maximum size of the MTA register table in all supported adapters */
862 #define MAX_MTA_REG 128
863 u32 mta_shadow[MAX_MTA_REG];
bc7f75fa 864 u16 rar_entry_count;
bc7f75fa
AK		 865
866 u8 forced_speed_duplex;
867
f464ba87 868 bool adaptive_ifs;
a65a4a0d 869 bool has_fwsm;
bc7f75fa
AK		 870 bool arc_subsystem_valid;
871 bool autoneg;
872 bool autoneg_failed;
873 bool get_link_status;
874 bool in_ifs_mode;
875 bool serdes_has_link;
876 bool tx_pkt_filtering;
c9523379 877 enum e1000_serdes_link_state serdes_link_state;
bc7f75fa
AK		 878};
879
880struct e1000_phy_info {
881 struct e1000_phy_operations ops;
882
883 enum e1000_phy_type type;
884
885 enum e1000_1000t_rx_status local_rx;
886 enum e1000_1000t_rx_status remote_rx;
887 enum e1000_ms_type ms_type;
888 enum e1000_ms_type original_ms_type;
889 enum e1000_rev_polarity cable_polarity;
890 enum e1000_smart_speed smart_speed;
891
892 u32 addr;
893 u32 id;
894 u32 reset_delay_us; /* in usec */
895 u32 revision;
896
318a94d6
JK		 897 enum e1000_media_type media_type;
898
bc7f75fa
AK		 899 u16 autoneg_advertised;
900 u16 autoneg_mask;
901 u16 cable_length;
902 u16 max_cable_length;
903 u16 min_cable_length;
904
905 u8 mdix;
906
907 bool disable_polarity_correction;
908 bool is_mdix;
909 bool polarity_correction;
910 bool speed_downgraded;
318a94d6 911 bool autoneg_wait_to_complete;
bc7f75fa
AK		 912};
913
914struct e1000_nvm_info {
915 struct e1000_nvm_operations ops;
916
917 enum e1000_nvm_type type;
918 enum e1000_nvm_override override;
919
920 u32 flash_bank_size;
921 u32 flash_base_addr;
922
923 u16 word_size;
924 u16 delay_usec;
925 u16 address_bits;
926 u16 opcode_bits;
927 u16 page_size;
928};
929
930struct e1000_bus_info {
931 enum e1000_bus_width width;
932
933 u16 func;
934};
935
318a94d6
JK		 936struct e1000_fc_info {
937 u32 high_water; /* Flow control high-water mark */
938 u32 low_water; /* Flow control low-water mark */
939 u16 pause_time; /* Flow control pause timer */
a305595b 940 u16 refresh_time; /* Flow control refresh timer */
318a94d6
JK		 941 bool send_xon; /* Flow control send XON */
942 bool strict_ieee; /* Strict IEEE mode */
5c48ef3e
BA		 943 enum e1000_fc_mode current_mode; /* FC mode in effect */
944 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
318a94d6
JK		 945};
946
bc7f75fa
AK		 947struct e1000_dev_spec_82571 {
948 bool laa_is_present;
23a2d1b2 949 u32 smb_counter;
bc7f75fa
AK		 950};
951
3421eecd
BA		 952struct e1000_dev_spec_80003es2lan {
953 bool mdic_wa_enable;
954};
955
bc7f75fa
AK		 956struct e1000_shadow_ram {
957 u16 value;
958 bool modified;
959};
960
961#define E1000_ICH8_SHADOW_RAM_WORDS 2048
962
963struct e1000_dev_spec_ich8lan {
964 bool kmrn_lock_loss_workaround_enabled;
965 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
1d5846b9 966 bool nvm_k1_enabled;
e52997f9 967 bool eee_disable;
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AK		 968};
969
970struct e1000_hw {
971 struct e1000_adapter *adapter;
972
c5083cf6
BA		 973 void __iomem *hw_addr;
974 void __iomem *flash_address;
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AK		 975
976 struct e1000_mac_info mac;
318a94d6 977 struct e1000_fc_info fc;
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AK		 978 struct e1000_phy_info phy;
979 struct e1000_nvm_info nvm;
980 struct e1000_bus_info bus;
981 struct e1000_host_mng_dhcp_cookie mng_cookie;
982
983 union {
984 struct e1000_dev_spec_82571 e82571;
3421eecd 985 struct e1000_dev_spec_80003es2lan e80003es2lan;
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AK		 986 struct e1000_dev_spec_ich8lan ich8lan;
987 } dev_spec;
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AK		 988};
989
bc7f75fa 990#endif
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