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e1000e: use true/false for bool autoneg_false
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
1605927f 30 * 82562G 10/100 Network Connection
bc7f75fa
AK		 31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
97ac8cae
BA		 42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
1605927f 44 * 82567V Gigabit Network Connection
97ac8cae
BA		 45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
2f15f9d6 50 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
d3738bb8
BA		 55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
bc7f75fa
AK		 57 */
58
bc7f75fa
AK		 59#include "e1000.h"
60
61#define ICH_FLASH_GFPREG 0x0000
62#define ICH_FLASH_HSFSTS 0x0004
63#define ICH_FLASH_HSFCTL 0x0006
64#define ICH_FLASH_FADDR 0x0008
65#define ICH_FLASH_FDATA0 0x0010
4a770358 66#define ICH_FLASH_PR0 0x0074
bc7f75fa
AK		 67
68#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74#define ICH_CYCLE_READ 0
75#define ICH_CYCLE_WRITE 2
76#define ICH_CYCLE_ERASE 3
77
78#define FLASH_GFPREG_BASE_MASK 0x1FFF
79#define FLASH_SECTOR_ADDR_SHIFT 12
80
81#define ICH_FLASH_SEG_SIZE_256 256
82#define ICH_FLASH_SEG_SIZE_4K 4096
83#define ICH_FLASH_SEG_SIZE_8K 8192
84#define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
6dfaa769
BA		 88/* FW established a valid mode */
89#define E1000_ICH_FWSM_FW_VALID 0x00008000
bc7f75fa
AK		 90
91#define E1000_ICH_MNG_IAMT_MODE 0x2
92
93#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98#define E1000_ICH_NVM_SIG_WORD 0x13
99#define E1000_ICH_NVM_SIG_MASK 0xC000
e243455d
BA		 100#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101#define E1000_ICH_NVM_SIG_VALUE 0x80
bc7f75fa
AK		 102
103#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105#define E1000_FEXTNVM_SW_CONFIG 1
106#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
831bd2e6
BA		 108#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
111
bc7f75fa
AK		 112#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
113
114#define E1000_ICH_RAR_ENTRIES 7
115
116#define PHY_PAGE_SHIFT 5
117#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
121
122#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
125
a4f58f54
BA		 126#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
127
53ac5a88
BA		 128#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
129
f523d211
BA		 130/* SMBus Address Phy Register */
131#define HV_SMB_ADDR PHY_REG(768, 26)
8395ae83 132#define HV_SMB_ADDR_MASK 0x007F
f523d211
BA		 133#define HV_SMB_ADDR_PEC_EN 0x0200
134#define HV_SMB_ADDR_VALID 0x0080
135
d3738bb8
BA		 136/* PHY Power Management Control */
137#define HV_PM_CTRL PHY_REG(770, 17)
138
e52997f9 139/* PHY Low Power Idle Control */
0ed013e2
BA		 140#define I82579_LPI_CTRL PHY_REG(772, 20)
141#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
142#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
e52997f9 143
1effb45c
BA		 144/* EMI Registers */
145#define I82579_EMI_ADDR 0x10
146#define I82579_EMI_DATA 0x11
147#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
4d24136c
BA		 148#define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */
149#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
1effb45c 150
f523d211
BA		 151/* Strapping Option Register - RO */
152#define E1000_STRAP 0x0000C
153#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
154#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
155
fa2ce13c
BA		 156/* OEM Bits Phy Register */
157#define HV_OEM_BITS PHY_REG(768, 25)
158#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
f523d211 159#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
fa2ce13c
BA		 160#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
161
1d5846b9
BA		 162#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
163#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
164
fddaa1af
BA		 165/* KMRN Mode Control */
166#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
167#define HV_KMRN_MDIO_SLOW 0x0400
168
1d2101a7
BA		 169/* KMRN FIFO Control and Status */
170#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
171#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
172#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
173
bc7f75fa
AK		 174/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
175/* Offset 04h HSFSTS */
176union ich8_hws_flash_status {
177 struct ich8_hsfsts {
178 u16 flcdone :1; /* bit 0 Flash Cycle Done */
179 u16 flcerr :1; /* bit 1 Flash Cycle Error */
180 u16 dael :1; /* bit 2 Direct Access error Log */
181 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
182 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
183 u16 reserved1 :2; /* bit 13:6 Reserved */
184 u16 reserved2 :6; /* bit 13:6 Reserved */
185 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
186 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
187 } hsf_status;
188 u16 regval;
189};
190
191/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
192/* Offset 06h FLCTL */
193union ich8_hws_flash_ctrl {
194 struct ich8_hsflctl {
195 u16 flcgo :1; /* 0 Flash Cycle Go */
196 u16 flcycle :2; /* 2:1 Flash Cycle */
197 u16 reserved :5; /* 7:3 Reserved */
198 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
199 u16 flockdn :6; /* 15:10 Reserved */
200 } hsf_ctrl;
201 u16 regval;
202};
203
204/* ICH Flash Region Access Permissions */
205union ich8_hws_flash_regacc {
206 struct ich8_flracc {
207 u32 grra :8; /* 0:7 GbE region Read Access */
208 u32 grwa :8; /* 8:15 GbE region Write Access */
209 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
210 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
211 } hsf_flregacc;
212 u16 regval;
213};
214
4a770358
BA		 215/* ICH Flash Protected Region */
216union ich8_flash_protected_range {
217 struct ich8_pr {
218 u32 base:13; /* 0:12 Protected Range Base */
219 u32 reserved1:2; /* 13:14 Reserved */
220 u32 rpe:1; /* 15 Read Protection Enable */
221 u32 limit:13; /* 16:28 Protected Range Limit */
222 u32 reserved2:2; /* 29:30 Reserved */
223 u32 wpe:1; /* 31 Write Protection Enable */
224 } range;
225 u32 regval;
226};
227
bc7f75fa
AK		 228static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
229static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
230static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 231static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
232static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
233 u32 offset, u8 byte);
f4187b56
BA		 234static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
235 u8 *data);
bc7f75fa
AK		 236static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
237 u16 *data);
238static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
239 u8 size, u16 *data);
240static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
241static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
f4187b56 242static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 243static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
244static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
245static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
246static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
247static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
248static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
249static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
250static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 251static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 252static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 253static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1d5846b9 254static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 255static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 256static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
257static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
831bd2e6 258static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
605c82ba 259static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
bc7f75fa
AK		 260
261static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
262{
263 return readw(hw->flash_address + reg);
264}
265
266static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
267{
268 return readl(hw->flash_address + reg);
269}
270
271static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
272{
273 writew(val, hw->flash_address + reg);
274}
275
276static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
277{
278 writel(val, hw->flash_address + reg);
279}
280
281#define er16flash(reg) __er16flash(hw, (reg))
282#define er32flash(reg) __er32flash(hw, (reg))
0e15df49
BA		 283#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
284#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
bc7f75fa 285
99730e4c
BA		 286static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
287{
288 u32 ctrl;
289
290 ctrl = er32(CTRL);
291 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
292 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
293 ew32(CTRL, ctrl);
945a5151 294 e1e_flush();
99730e4c
BA		 295 udelay(10);
296 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
297 ew32(CTRL, ctrl);
298}
299
a4f58f54
BA		 300/**
301 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
302 * @hw: pointer to the HW structure
303 *
304 * Initialize family-specific PHY parameters and function pointers.
305 **/
306static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
307{
308 struct e1000_phy_info *phy = &hw->phy;
309 s32 ret_val = 0;
310
311 phy->addr = 1;
312 phy->reset_delay_us = 100;
313
2b6b168d 314 phy->ops.set_page = e1000_set_page_igp;
94d8186a
BA		 315 phy->ops.read_reg = e1000_read_phy_reg_hv;
316 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
2b6b168d 317 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
fa2ce13c
BA		 318 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
319 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 320 phy->ops.write_reg = e1000_write_phy_reg_hv;
321 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
2b6b168d 322 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
17f208de
BA		 323 phy->ops.power_up = e1000_power_up_phy_copper;
324 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
a4f58f54
BA		 325 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
326
90b82984
BA		 327 if (!e1000_check_reset_block(hw)) {
328 u32 fwsm = er32(FWSM);
329
330 /*
331 * The MAC-PHY interconnect may still be in SMBus mode after
332 * Sx->S0. If resetting the PHY is not blocked, toggle the
333 * LANPHYPC Value bit to force the interconnect to PCIe mode.
334 */
99730e4c 335 e1000_toggle_lanphypc_value_ich8lan(hw);
6dfaa769 336 msleep(50);
605c82ba
BA		 337
338 /*
339 * Gate automatic PHY configuration by hardware on
340 * non-managed 82579
341 */
90b82984
BA		 342 if ((hw->mac.type == e1000_pch2lan) &&
343 !(fwsm & E1000_ICH_FWSM_FW_VALID))
605c82ba 344 e1000_gate_hw_phy_config_ich8lan(hw, true);
6dfaa769 345
90b82984
BA		 346 /*
347 * Reset the PHY before any access to it. Doing so, ensures
348 * that the PHY is in a known good state before we read/write
349 * PHY registers. The generic reset is sufficient here,
350 * because we haven't determined the PHY type yet.
351 */
352 ret_val = e1000e_phy_hw_reset_generic(hw);
353 if (ret_val)
354 goto out;
627c8a04 355
90b82984
BA		 356 /* Ungate automatic PHY configuration on non-managed 82579 */
357 if ((hw->mac.type == e1000_pch2lan) &&
358 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
359 usleep_range(10000, 20000);
360 e1000_gate_hw_phy_config_ich8lan(hw, false);
361 }
605c82ba
BA		 362 }
363
a4f58f54 364 phy->id = e1000_phy_unknown;
664dc878
BA		 365 switch (hw->mac.type) {
366 default:
367 ret_val = e1000e_get_phy_id(hw);
368 if (ret_val)
369 goto out;
370 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
371 break;
372 /* fall-through */
373 case e1000_pch2lan:
fddaa1af 374 /*
664dc878 375 * In case the PHY needs to be in mdio slow mode,
fddaa1af
BA		 376 * set slow mode and try to get the PHY id again.
377 */
378 ret_val = e1000_set_mdio_slow_mode_hv(hw);
379 if (ret_val)
380 goto out;
381 ret_val = e1000e_get_phy_id(hw);
382 if (ret_val)
383 goto out;
664dc878 384 break;
fddaa1af 385 }
a4f58f54
BA		 386 phy->type = e1000e_get_phy_type_from_id(phy->id);
387
0be84010
BA		 388 switch (phy->type) {
389 case e1000_phy_82577:
d3738bb8 390 case e1000_phy_82579:
a4f58f54
BA		 391 phy->ops.check_polarity = e1000_check_polarity_82577;
392 phy->ops.force_speed_duplex =
6cc7aaed 393 e1000_phy_force_speed_duplex_82577;
0be84010 394 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 395 phy->ops.get_info = e1000_get_phy_info_82577;
396 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 397 break;
0be84010
BA		 398 case e1000_phy_82578:
399 phy->ops.check_polarity = e1000_check_polarity_m88;
400 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
401 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
402 phy->ops.get_info = e1000e_get_phy_info_m88;
403 break;
404 default:
405 ret_val = -E1000_ERR_PHY;
406 break;
a4f58f54
BA		 407 }
408
fddaa1af 409out:
a4f58f54
BA		 410 return ret_val;
411}
412
bc7f75fa
AK		 413/**
414 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
415 * @hw: pointer to the HW structure
416 *
417 * Initialize family-specific PHY parameters and function pointers.
418 **/
419static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
420{
421 struct e1000_phy_info *phy = &hw->phy;
422 s32 ret_val;
423 u16 i = 0;
424
425 phy->addr = 1;
426 phy->reset_delay_us = 100;
427
17f208de
BA		 428 phy->ops.power_up = e1000_power_up_phy_copper;
429 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
430
97ac8cae
BA		 431 /*
432 * We may need to do this twice - once for IGP and if that fails,
433 * we'll set BM func pointers and try again
434 */
435 ret_val = e1000e_determine_phy_address(hw);
436 if (ret_val) {
94d8186a
BA		 437 phy->ops.write_reg = e1000e_write_phy_reg_bm;
438 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 439 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 440 if (ret_val) {
441 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 442 return ret_val;
9b71b419 443 }
97ac8cae
BA		 444 }
445
bc7f75fa
AK		 446 phy->id = 0;
447 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
448 (i++ < 100)) {
1bba4386 449 usleep_range(1000, 2000);
bc7f75fa
AK		 450 ret_val = e1000e_get_phy_id(hw);
451 if (ret_val)
452 return ret_val;
453 }
454
455 /* Verify phy id */
456 switch (phy->id) {
457 case IGP03E1000_E_PHY_ID:
458 phy->type = e1000_phy_igp_3;
459 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 460 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
461 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 462 phy->ops.get_info = e1000e_get_phy_info_igp;
463 phy->ops.check_polarity = e1000_check_polarity_igp;
464 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 465 break;
466 case IFE_E_PHY_ID:
467 case IFE_PLUS_E_PHY_ID:
468 case IFE_C_E_PHY_ID:
469 phy->type = e1000_phy_ife;
470 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 471 phy->ops.get_info = e1000_get_phy_info_ife;
472 phy->ops.check_polarity = e1000_check_polarity_ife;
473 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 474 break;
97ac8cae
BA		 475 case BME1000_E_PHY_ID:
476 phy->type = e1000_phy_bm;
477 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 478 phy->ops.read_reg = e1000e_read_phy_reg_bm;
479 phy->ops.write_reg = e1000e_write_phy_reg_bm;
480 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 481 phy->ops.get_info = e1000e_get_phy_info_m88;
482 phy->ops.check_polarity = e1000_check_polarity_m88;
483 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 484 break;
bc7f75fa
AK		 485 default:
486 return -E1000_ERR_PHY;
487 break;
488 }
489
490 return 0;
491}
492
493/**
494 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
495 * @hw: pointer to the HW structure
496 *
497 * Initialize family-specific NVM parameters and function
498 * pointers.
499 **/
500static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
501{
502 struct e1000_nvm_info *nvm = &hw->nvm;
503 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 504 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 505 u16 i;
506
ad68076e 507 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 508 if (!hw->flash_address) {
3bb99fe2 509 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 510 return -E1000_ERR_CONFIG;
511 }
512
513 nvm->type = e1000_nvm_flash_sw;
514
515 gfpreg = er32flash(ICH_FLASH_GFPREG);
516
ad68076e
BA		 517 /*
518 * sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 519 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 520 * the overall size.
521 */
bc7f75fa
AK		 522 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
523 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
524
525 /* flash_base_addr is byte-aligned */
526 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
527
ad68076e
BA		 528 /*
529 * find total size of the NVM, then cut in half since the total
530 * size represents two separate NVM banks.
531 */
bc7f75fa
AK		 532 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
533 << FLASH_SECTOR_ADDR_SHIFT;
534 nvm->flash_bank_size /= 2;
535 /* Adjust to word count */
536 nvm->flash_bank_size /= sizeof(u16);
537
538 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
539
540 /* Clear shadow ram */
541 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 542 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 543 dev_spec->shadow_ram[i].value = 0xFFFF;
544 }
545
546 return 0;
547}
548
549/**
550 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
551 * @hw: pointer to the HW structure
552 *
553 * Initialize family-specific MAC parameters and function
554 * pointers.
555 **/
556static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
557{
558 struct e1000_hw *hw = &adapter->hw;
559 struct e1000_mac_info *mac = &hw->mac;
560
561 /* Set media type function pointer */
318a94d6 562 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 563
564 /* Set mta register count */
565 mac->mta_reg_count = 32;
566 /* Set rar entry count */
567 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
568 if (mac->type == e1000_ich8lan)
569 mac->rar_entry_count--;
a65a4a0d
BA		 570 /* FWSM register */
571 mac->has_fwsm = true;
572 /* ARC subsystem not supported */
573 mac->arc_subsystem_valid = false;
f464ba87
BA		 574 /* Adaptive IFS supported */
575 mac->adaptive_ifs = true;
bc7f75fa 576
a4f58f54
BA		 577 /* LED operations */
578 switch (mac->type) {
579 case e1000_ich8lan:
580 case e1000_ich9lan:
581 case e1000_ich10lan:
eb7700dc
BA		 582 /* check management mode */
583 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54
BA		 584 /* ID LED init */
585 mac->ops.id_led_init = e1000e_id_led_init;
dbf80dcb
BA		 586 /* blink LED */
587 mac->ops.blink_led = e1000e_blink_led_generic;
a4f58f54
BA		 588 /* setup LED */
589 mac->ops.setup_led = e1000e_setup_led_generic;
590 /* cleanup LED */
591 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
592 /* turn on/off LED */
593 mac->ops.led_on = e1000_led_on_ich8lan;
594 mac->ops.led_off = e1000_led_off_ich8lan;
595 break;
596 case e1000_pchlan:
d3738bb8 597 case e1000_pch2lan:
eb7700dc
BA		 598 /* check management mode */
599 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 600 /* ID LED init */
601 mac->ops.id_led_init = e1000_id_led_init_pchlan;
602 /* setup LED */
603 mac->ops.setup_led = e1000_setup_led_pchlan;
604 /* cleanup LED */
605 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
606 /* turn on/off LED */
607 mac->ops.led_on = e1000_led_on_pchlan;
608 mac->ops.led_off = e1000_led_off_pchlan;
609 break;
610 default:
611 break;
612 }
613
bc7f75fa
AK		 614 /* Enable PCS Lock-loss workaround for ICH8 */
615 if (mac->type == e1000_ich8lan)
564ea9bb 616 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa 617
605c82ba
BA		 618 /* Gate automatic PHY configuration by hardware on managed 82579 */
619 if ((mac->type == e1000_pch2lan) &&
620 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
621 e1000_gate_hw_phy_config_ich8lan(hw, true);
d3738bb8 622
bc7f75fa
AK		 623 return 0;
624}
625
e52997f9
BA		 626/**
627 * e1000_set_eee_pchlan - Enable/disable EEE support
628 * @hw: pointer to the HW structure
629 *
630 * Enable/disable EEE based on setting in dev_spec structure. The bits in
631 * the LPI Control register will remain set only if/when link is up.
632 **/
633static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
634{
635 s32 ret_val = 0;
636 u16 phy_reg;
637
638 if (hw->phy.type != e1000_phy_82579)
639 goto out;
640
641 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
642 if (ret_val)
643 goto out;
644
645 if (hw->dev_spec.ich8lan.eee_disable)
646 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
647 else
648 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
649
650 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
651out:
652 return ret_val;
653}
654
7d3cabbc
BA		 655/**
656 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
657 * @hw: pointer to the HW structure
658 *
659 * Checks to see of the link status of the hardware has changed. If a
660 * change in link status has been detected, then we read the PHY registers
661 * to get the current speed/duplex if link exists.
662 **/
663static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
664{
665 struct e1000_mac_info *mac = &hw->mac;
666 s32 ret_val;
667 bool link;
1d2101a7 668 u16 phy_reg;
7d3cabbc
BA		 669
670 /*
671 * We only want to go out to the PHY registers to see if Auto-Neg
672 * has completed and/or if our link status has changed. The
673 * get_link_status flag is set upon receiving a Link Status
674 * Change or Rx Sequence Error interrupt.
675 */
676 if (!mac->get_link_status) {
677 ret_val = 0;
678 goto out;
679 }
680
7d3cabbc
BA		 681 /*
682 * First we want to see if the MII Status Register reports
683 * link. If so, then we want to get the current speed/duplex
684 * of the PHY.
685 */
686 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
687 if (ret_val)
688 goto out;
689
1d5846b9
BA		 690 if (hw->mac.type == e1000_pchlan) {
691 ret_val = e1000_k1_gig_workaround_hv(hw, link);
692 if (ret_val)
693 goto out;
694 }
695
7d3cabbc
BA		 696 if (!link)
697 goto out; /* No link detected */
698
699 mac->get_link_status = false;
700
1d2101a7
BA		 701 switch (hw->mac.type) {
702 case e1000_pch2lan:
831bd2e6
BA		 703 ret_val = e1000_k1_workaround_lv(hw);
704 if (ret_val)
705 goto out;
1d2101a7
BA		 706 /* fall-thru */
707 case e1000_pchlan:
708 if (hw->phy.type == e1000_phy_82578) {
709 ret_val = e1000_link_stall_workaround_hv(hw);
710 if (ret_val)
711 goto out;
712 }
713
714 /*
715 * Workaround for PCHx parts in half-duplex:
716 * Set the number of preambles removed from the packet
717 * when it is passed from the PHY to the MAC to prevent
718 * the MAC from misinterpreting the packet type.
719 */
720 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
721 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
722
723 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
724 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
725
726 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
727 break;
728 default:
729 break;
831bd2e6
BA		 730 }
731
7d3cabbc
BA		 732 /*
733 * Check if there was DownShift, must be checked
734 * immediately after link-up
735 */
736 e1000e_check_downshift(hw);
737
e52997f9
BA		 738 /* Enable/Disable EEE after link up */
739 ret_val = e1000_set_eee_pchlan(hw);
740 if (ret_val)
741 goto out;
742
7d3cabbc
BA		 743 /*
744 * If we are forcing speed/duplex, then we simply return since
745 * we have already determined whether we have link or not.
746 */
747 if (!mac->autoneg) {
748 ret_val = -E1000_ERR_CONFIG;
749 goto out;
750 }
751
752 /*
753 * Auto-Neg is enabled. Auto Speed Detection takes care
754 * of MAC speed/duplex configuration. So we only need to
755 * configure Collision Distance in the MAC.
756 */
757 e1000e_config_collision_dist(hw);
758
759 /*
760 * Configure Flow Control now that Auto-Neg has completed.
761 * First, we need to restore the desired flow control
762 * settings because we may have had to re-autoneg with a
763 * different link partner.
764 */
765 ret_val = e1000e_config_fc_after_link_up(hw);
766 if (ret_val)
3bb99fe2 767 e_dbg("Error configuring flow control\n");
7d3cabbc
BA		 768
769out:
770 return ret_val;
771}
772
69e3fd8c 773static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 774{
775 struct e1000_hw *hw = &adapter->hw;
776 s32 rc;
777
778 rc = e1000_init_mac_params_ich8lan(adapter);
779 if (rc)
780 return rc;
781
782 rc = e1000_init_nvm_params_ich8lan(hw);
783 if (rc)
784 return rc;
785
d3738bb8
BA		 786 switch (hw->mac.type) {
787 case e1000_ich8lan:
788 case e1000_ich9lan:
789 case e1000_ich10lan:
a4f58f54 790 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 791 break;
792 case e1000_pchlan:
793 case e1000_pch2lan:
794 rc = e1000_init_phy_params_pchlan(hw);
795 break;
796 default:
797 break;
798 }
bc7f75fa
AK		 799 if (rc)
800 return rc;
801
23e4f061
BA		 802 /*
803 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
804 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
805 */
806 if ((adapter->hw.phy.type == e1000_phy_ife) ||
807 ((adapter->hw.mac.type >= e1000_pch2lan) &&
808 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
2adc55c9
BA		 809 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
810 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
dbf80dcb
BA		 811
812 hw->mac.ops.blink_led = NULL;
2adc55c9
BA		 813 }
814
bc7f75fa 815 if ((adapter->hw.mac.type == e1000_ich8lan) &&
462d5994 816 (adapter->hw.phy.type != e1000_phy_ife))
bc7f75fa
AK		 817 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
818
c6e7f51e
BA		 819 /* Enable workaround for 82579 w/ ME enabled */
820 if ((adapter->hw.mac.type == e1000_pch2lan) &&
821 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
822 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
823
5a86f28f
BA		 824 /* Disable EEE by default until IEEE802.3az spec is finalized */
825 if (adapter->flags2 & FLAG2_HAS_EEE)
826 adapter->hw.dev_spec.ich8lan.eee_disable = true;
827
bc7f75fa
AK		 828 return 0;
829}
830
717d438d 831static DEFINE_MUTEX(nvm_mutex);
717d438d 832
ca15df58
BA		 833/**
834 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
835 * @hw: pointer to the HW structure
836 *
837 * Acquires the mutex for performing NVM operations.
838 **/
839static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
840{
841 mutex_lock(&nvm_mutex);
842
843 return 0;
844}
845
846/**
847 * e1000_release_nvm_ich8lan - Release NVM mutex
848 * @hw: pointer to the HW structure
849 *
850 * Releases the mutex used while performing NVM operations.
851 **/
852static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
853{
854 mutex_unlock(&nvm_mutex);
ca15df58
BA		 855}
856
bc7f75fa
AK		 857/**
858 * e1000_acquire_swflag_ich8lan - Acquire software control flag
859 * @hw: pointer to the HW structure
860 *
ca15df58
BA		 861 * Acquires the software control flag for performing PHY and select
862 * MAC CSR accesses.
bc7f75fa
AK		 863 **/
864static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
865{
373a88d7
BA		 866 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
867 s32 ret_val = 0;
bc7f75fa 868
a90b412c
BA		 869 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
870 &hw->adapter->state)) {
34c9ef8b 871 e_dbg("contention for Phy access\n");
a90b412c
BA		 872 return -E1000_ERR_PHY;
873 }
717d438d 874
bc7f75fa
AK		 875 while (timeout) {
876 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 877 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
878 break;
bc7f75fa 879
373a88d7
BA		 880 mdelay(1);
881 timeout--;
882 }
883
884 if (!timeout) {
a90b412c 885 e_dbg("SW has already locked the resource.\n");
373a88d7
BA		 886 ret_val = -E1000_ERR_CONFIG;
887 goto out;
888 }
889
53ac5a88 890 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 891
892 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
893 ew32(EXTCNF_CTRL, extcnf_ctrl);
894
895 while (timeout) {
896 extcnf_ctrl = er32(EXTCNF_CTRL);
897 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
898 break;
a4f58f54 899
bc7f75fa
AK		 900 mdelay(1);
901 timeout--;
902 }
903
904 if (!timeout) {
434f1392 905 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
a90b412c 906 er32(FWSM), extcnf_ctrl);
2e2e8d53
BA		 907 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
908 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 909 ret_val = -E1000_ERR_CONFIG;
910 goto out;
bc7f75fa
AK		 911 }
912
373a88d7
BA		 913out:
914 if (ret_val)
a90b412c 915 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
373a88d7
BA		 916
917 return ret_val;
bc7f75fa
AK		 918}
919
920/**
921 * e1000_release_swflag_ich8lan - Release software control flag
922 * @hw: pointer to the HW structure
923 *
ca15df58
BA		 924 * Releases the software control flag for performing PHY and select
925 * MAC CSR accesses.
bc7f75fa
AK		 926 **/
927static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
928{
929 u32 extcnf_ctrl;
930
931 extcnf_ctrl = er32(EXTCNF_CTRL);
c5caf482
BA		 932
933 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
934 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
935 ew32(EXTCNF_CTRL, extcnf_ctrl);
936 } else {
937 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
938 }
717d438d 939
a90b412c 940 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
bc7f75fa
AK		 941}
942
4662e82b
BA		 943/**
944 * e1000_check_mng_mode_ich8lan - Checks management mode
945 * @hw: pointer to the HW structure
946 *
eb7700dc 947 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 948 * This is a function pointer entry point only called by read/write
949 * routines for the PHY and NVM parts.
950 **/
951static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
952{
a708dd88
BA		 953 u32 fwsm;
954
955 fwsm = er32(FWSM);
eb7700dc
BA		 956 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
957 ((fwsm & E1000_FWSM_MODE_MASK) ==
958 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
959}
4662e82b 960
eb7700dc
BA		 961/**
962 * e1000_check_mng_mode_pchlan - Checks management mode
963 * @hw: pointer to the HW structure
964 *
965 * This checks if the adapter has iAMT enabled.
966 * This is a function pointer entry point only called by read/write
967 * routines for the PHY and NVM parts.
968 **/
969static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
970{
971 u32 fwsm;
972
973 fwsm = er32(FWSM);
974 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
975 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 976}
977
bc7f75fa
AK		 978/**
979 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
980 * @hw: pointer to the HW structure
981 *
982 * Checks if firmware is blocking the reset of the PHY.
983 * This is a function pointer entry point only called by
984 * reset routines.
985 **/
986static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
987{
988 u32 fwsm;
989
990 fwsm = er32(FWSM);
991
992 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
993}
994
8395ae83
BA		 995/**
996 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
997 * @hw: pointer to the HW structure
998 *
999 * Assumes semaphore already acquired.
1000 *
1001 **/
1002static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1003{
1004 u16 phy_data;
1005 u32 strap = er32(STRAP);
1006 s32 ret_val = 0;
1007
1008 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1009
1010 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1011 if (ret_val)
1012 goto out;
1013
1014 phy_data &= ~HV_SMB_ADDR_MASK;
1015 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1016 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1017 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1018
1019out:
1020 return ret_val;
1021}
1022
f523d211
BA		 1023/**
1024 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1025 * @hw: pointer to the HW structure
1026 *
1027 * SW should configure the LCD from the NVM extended configuration region
1028 * as a workaround for certain parts.
1029 **/
1030static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1031{
1032 struct e1000_phy_info *phy = &hw->phy;
1033 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 1034 s32 ret_val = 0;
f523d211
BA		 1035 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1036
f523d211
BA		 1037 /*
1038 * Initialize the PHY from the NVM on ICH platforms. This
1039 * is needed due to an issue where the NVM configuration is
1040 * not properly autoloaded after power transitions.
1041 * Therefore, after each PHY reset, we will load the
1042 * configuration data out of the NVM manually.
1043 */
3f0c16e8
BA		 1044 switch (hw->mac.type) {
1045 case e1000_ich8lan:
1046 if (phy->type != e1000_phy_igp_3)
1047 return ret_val;
1048
5f3eed6f
BA		 1049 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1050 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
3f0c16e8
BA		 1051 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1052 break;
1053 }
1054 /* Fall-thru */
1055 case e1000_pchlan:
d3738bb8 1056 case e1000_pch2lan:
8b802a7e 1057 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 1058 break;
1059 default:
1060 return ret_val;
1061 }
1062
1063 ret_val = hw->phy.ops.acquire(hw);
1064 if (ret_val)
1065 return ret_val;
8b802a7e
BA		 1066
1067 data = er32(FEXTNVM);
1068 if (!(data & sw_cfg_mask))
1069 goto out;
f523d211 1070
8b802a7e
BA		 1071 /*
1072 * Make sure HW does not configure LCD from PHY
1073 * extended configuration before SW configuration
1074 */
1075 data = er32(EXTCNF_CTRL);
d3738bb8
BA		 1076 if (!(hw->mac.type == e1000_pch2lan)) {
1077 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1078 goto out;
1079 }
8b802a7e
BA		 1080
1081 cnf_size = er32(EXTCNF_SIZE);
1082 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1083 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1084 if (!cnf_size)
1085 goto out;
1086
1087 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1088 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1089
87fb7410
BA		 1090 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1091 (hw->mac.type == e1000_pchlan)) ||
1092 (hw->mac.type == e1000_pch2lan)) {
f523d211 1093 /*
8b802a7e
BA		 1094 * HW configures the SMBus address and LEDs when the
1095 * OEM and LCD Write Enable bits are set in the NVM.
1096 * When both NVM bits are cleared, SW will configure
1097 * them instead.
f523d211 1098 */
8395ae83 1099 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 1100 if (ret_val)
f523d211
BA		 1101 goto out;
1102
8b802a7e
BA		 1103 data = er32(LEDCTL);
1104 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1105 (u16)data);
1106 if (ret_val)
f523d211 1107 goto out;
8b802a7e 1108 }
f523d211 1109
8b802a7e
BA		 1110 /* Configure LCD from extended configuration region. */
1111
1112 /* cnf_base_addr is in DWORD */
1113 word_addr = (u16)(cnf_base_addr << 1);
1114
1115 for (i = 0; i < cnf_size; i++) {
1116 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1117 &reg_data);
1118 if (ret_val)
1119 goto out;
1120
1121 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1122 1, &reg_addr);
1123 if (ret_val)
1124 goto out;
1125
1126 /* Save off the PHY page for future writes. */
1127 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1128 phy_page = reg_data;
1129 continue;
f523d211 1130 }
8b802a7e
BA		 1131
1132 reg_addr &= PHY_REG_MASK;
1133 reg_addr |= phy_page;
1134
1135 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1136 reg_data);
1137 if (ret_val)
1138 goto out;
f523d211
BA		 1139 }
1140
1141out:
94d8186a 1142 hw->phy.ops.release(hw);
f523d211
BA		 1143 return ret_val;
1144}
1145
1d5846b9
BA		 1146/**
1147 * e1000_k1_gig_workaround_hv - K1 Si workaround
1148 * @hw: pointer to the HW structure
1149 * @link: link up bool flag
1150 *
1151 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1152 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1153 * If link is down, the function will restore the default K1 setting located
1154 * in the NVM.
1155 **/
1156static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1157{
1158 s32 ret_val = 0;
1159 u16 status_reg = 0;
1160 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1161
1162 if (hw->mac.type != e1000_pchlan)
1163 goto out;
1164
1165 /* Wrap the whole flow with the sw flag */
94d8186a 1166 ret_val = hw->phy.ops.acquire(hw);
1d5846b9
BA		 1167 if (ret_val)
1168 goto out;
1169
1170 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1171 if (link) {
1172 if (hw->phy.type == e1000_phy_82578) {
94d8186a 1173 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1d5846b9
BA		 1174 &status_reg);
1175 if (ret_val)
1176 goto release;
1177
1178 status_reg &= BM_CS_STATUS_LINK_UP |
1179 BM_CS_STATUS_RESOLVED |
1180 BM_CS_STATUS_SPEED_MASK;
1181
1182 if (status_reg == (BM_CS_STATUS_LINK_UP |
1183 BM_CS_STATUS_RESOLVED |
1184 BM_CS_STATUS_SPEED_1000))
1185 k1_enable = false;
1186 }
1187
1188 if (hw->phy.type == e1000_phy_82577) {
94d8186a 1189 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1d5846b9
BA		 1190 &status_reg);
1191 if (ret_val)
1192 goto release;
1193
1194 status_reg &= HV_M_STATUS_LINK_UP |
1195 HV_M_STATUS_AUTONEG_COMPLETE |
1196 HV_M_STATUS_SPEED_MASK;
1197
1198 if (status_reg == (HV_M_STATUS_LINK_UP |
1199 HV_M_STATUS_AUTONEG_COMPLETE |
1200 HV_M_STATUS_SPEED_1000))
1201 k1_enable = false;
1202 }
1203
1204 /* Link stall fix for link up */
94d8186a 1205 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1206 0x0100);
1207 if (ret_val)
1208 goto release;
1209
1210 } else {
1211 /* Link stall fix for link down */
94d8186a 1212 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1213 0x4100);
1214 if (ret_val)
1215 goto release;
1216 }
1217
1218 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1219
1220release:
94d8186a 1221 hw->phy.ops.release(hw);
1d5846b9
BA		 1222out:
1223 return ret_val;
1224}
1225
1226/**
1227 * e1000_configure_k1_ich8lan - Configure K1 power state
1228 * @hw: pointer to the HW structure
1229 * @enable: K1 state to configure
1230 *
1231 * Configure the K1 power state based on the provided parameter.
1232 * Assumes semaphore already acquired.
1233 *
1234 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1235 **/
bb436b20 1236s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9
BA		 1237{
1238 s32 ret_val = 0;
1239 u32 ctrl_reg = 0;
1240 u32 ctrl_ext = 0;
1241 u32 reg = 0;
1242 u16 kmrn_reg = 0;
1243
1244 ret_val = e1000e_read_kmrn_reg_locked(hw,
1245 E1000_KMRNCTRLSTA_K1_CONFIG,
1246 &kmrn_reg);
1247 if (ret_val)
1248 goto out;
1249
1250 if (k1_enable)
1251 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1252 else
1253 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1254
1255 ret_val = e1000e_write_kmrn_reg_locked(hw,
1256 E1000_KMRNCTRLSTA_K1_CONFIG,
1257 kmrn_reg);
1258 if (ret_val)
1259 goto out;
1260
1261 udelay(20);
1262 ctrl_ext = er32(CTRL_EXT);
1263 ctrl_reg = er32(CTRL);
1264
1265 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1266 reg |= E1000_CTRL_FRCSPD;
1267 ew32(CTRL, reg);
1268
1269 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
945a5151 1270 e1e_flush();
1d5846b9
BA		 1271 udelay(20);
1272 ew32(CTRL, ctrl_reg);
1273 ew32(CTRL_EXT, ctrl_ext);
945a5151 1274 e1e_flush();
1d5846b9
BA		 1275 udelay(20);
1276
1277out:
1278 return ret_val;
1279}
1280
f523d211
BA		 1281/**
1282 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1283 * @hw: pointer to the HW structure
1284 * @d0_state: boolean if entering d0 or d3 device state
1285 *
1286 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1287 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1288 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1289 **/
1290static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1291{
1292 s32 ret_val = 0;
1293 u32 mac_reg;
1294 u16 oem_reg;
1295
d3738bb8 1296 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
f523d211
BA		 1297 return ret_val;
1298
94d8186a 1299 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1300 if (ret_val)
1301 return ret_val;
1302
d3738bb8
BA		 1303 if (!(hw->mac.type == e1000_pch2lan)) {
1304 mac_reg = er32(EXTCNF_CTRL);
1305 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1306 goto out;
1307 }
f523d211
BA		 1308
1309 mac_reg = er32(FEXTNVM);
1310 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1311 goto out;
1312
1313 mac_reg = er32(PHY_CTRL);
1314
94d8186a 1315 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211
BA		 1316 if (ret_val)
1317 goto out;
1318
1319 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1320
1321 if (d0_state) {
1322 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1323 oem_reg |= HV_OEM_BITS_GBE_DIS;
1324
1325 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1326 oem_reg |= HV_OEM_BITS_LPLU;
03299e46
BA		 1327
1328 /* Set Restart auto-neg to activate the bits */
1329 if (!e1000_check_reset_block(hw))
1330 oem_reg |= HV_OEM_BITS_RESTART_AN;
f523d211 1331 } else {
03299e46
BA		 1332 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1333 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
f523d211
BA		 1334 oem_reg |= HV_OEM_BITS_GBE_DIS;
1335
03299e46
BA		 1336 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1337 E1000_PHY_CTRL_NOND0A_LPLU))
f523d211
BA		 1338 oem_reg |= HV_OEM_BITS_LPLU;
1339 }
03299e46 1340
94d8186a 1341 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
f523d211
BA		 1342
1343out:
94d8186a 1344 hw->phy.ops.release(hw);
f523d211
BA		 1345
1346 return ret_val;
1347}
1348
1349
fddaa1af
BA		 1350/**
1351 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1352 * @hw: pointer to the HW structure
1353 **/
1354static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1355{
1356 s32 ret_val;
1357 u16 data;
1358
1359 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1360 if (ret_val)
1361 return ret_val;
1362
1363 data |= HV_KMRN_MDIO_SLOW;
1364
1365 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1366
1367 return ret_val;
1368}
1369
a4f58f54
BA		 1370/**
1371 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1372 * done after every PHY reset.
1373 **/
1374static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1375{
1376 s32 ret_val = 0;
baf86c9d 1377 u16 phy_data;
a4f58f54
BA		 1378
1379 if (hw->mac.type != e1000_pchlan)
1380 return ret_val;
1381
fddaa1af
BA		 1382 /* Set MDIO slow mode before any other MDIO access */
1383 if (hw->phy.type == e1000_phy_82577) {
1384 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1385 if (ret_val)
1386 goto out;
1387 }
1388
a4f58f54
BA		 1389 if (((hw->phy.type == e1000_phy_82577) &&
1390 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1391 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1392 /* Disable generation of early preamble */
1393 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1394 if (ret_val)
1395 return ret_val;
1396
1397 /* Preamble tuning for SSC */
1d2101a7 1398 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
a4f58f54
BA		 1399 if (ret_val)
1400 return ret_val;
1401 }
1402
1403 if (hw->phy.type == e1000_phy_82578) {
1404 /*
1405 * Return registers to default by doing a soft reset then
1406 * writing 0x3140 to the control register.
1407 */
1408 if (hw->phy.revision < 2) {
1409 e1000e_phy_sw_reset(hw);
1410 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1411 }
1412 }
1413
1414 /* Select page 0 */
94d8186a 1415 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1416 if (ret_val)
1417 return ret_val;
1d5846b9 1418
a4f58f54 1419 hw->phy.addr = 1;
1d5846b9 1420 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1421 hw->phy.ops.release(hw);
1d5846b9
BA		 1422 if (ret_val)
1423 goto out;
a4f58f54 1424
1d5846b9
BA		 1425 /*
1426 * Configure the K1 Si workaround during phy reset assuming there is
1427 * link so that it disables K1 if link is in 1Gbps.
1428 */
1429 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d
BA		 1430 if (ret_val)
1431 goto out;
1d5846b9 1432
baf86c9d
BA		 1433 /* Workaround for link disconnects on a busy hub in half duplex */
1434 ret_val = hw->phy.ops.acquire(hw);
1435 if (ret_val)
1436 goto out;
3ebfc7c9 1437 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
baf86c9d
BA		 1438 if (ret_val)
1439 goto release;
3ebfc7c9
BA		 1440 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1441 phy_data & 0x00FF);
baf86c9d
BA		 1442release:
1443 hw->phy.ops.release(hw);
1d5846b9 1444out:
a4f58f54
BA		 1445 return ret_val;
1446}
1447
d3738bb8
BA		 1448/**
1449 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1450 * @hw: pointer to the HW structure
1451 **/
1452void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1453{
1454 u32 mac_reg;
2b6b168d
BA		 1455 u16 i, phy_reg = 0;
1456 s32 ret_val;
1457
1458 ret_val = hw->phy.ops.acquire(hw);
1459 if (ret_val)
1460 return;
1461 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1462 if (ret_val)
1463 goto release;
d3738bb8
BA		 1464
1465 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1466 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1467 mac_reg = er32(RAL(i));
2b6b168d
BA		 1468 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1469 (u16)(mac_reg & 0xFFFF));
1470 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1471 (u16)((mac_reg >> 16) & 0xFFFF));
1472
d3738bb8 1473 mac_reg = er32(RAH(i));
2b6b168d
BA		 1474 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1475 (u16)(mac_reg & 0xFFFF));
1476 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1477 (u16)((mac_reg & E1000_RAH_AV)
1478 >> 16));
d3738bb8 1479 }
2b6b168d
BA		 1480
1481 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1482
1483release:
1484 hw->phy.ops.release(hw);
d3738bb8
BA		 1485}
1486
d3738bb8
BA		 1487/**
1488 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1489 * with 82579 PHY
1490 * @hw: pointer to the HW structure
1491 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1492 **/
1493s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1494{
1495 s32 ret_val = 0;
1496 u16 phy_reg, data;
1497 u32 mac_reg;
1498 u16 i;
1499
1500 if (hw->mac.type != e1000_pch2lan)
1501 goto out;
1502
1503 /* disable Rx path while enabling/disabling workaround */
1504 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1505 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1506 if (ret_val)
1507 goto out;
1508
1509 if (enable) {
1510 /*
1511 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1512 * SHRAL/H) and initial CRC values to the MAC
1513 */
1514 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1515 u8 mac_addr[ETH_ALEN] = {0};
1516 u32 addr_high, addr_low;
1517
1518 addr_high = er32(RAH(i));
1519 if (!(addr_high & E1000_RAH_AV))
1520 continue;
1521 addr_low = er32(RAL(i));
1522 mac_addr[0] = (addr_low & 0xFF);
1523 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1524 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1525 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1526 mac_addr[4] = (addr_high & 0xFF);
1527 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1528
fe46f58f 1529 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
d3738bb8
BA		 1530 }
1531
1532 /* Write Rx addresses to the PHY */
1533 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1534
1535 /* Enable jumbo frame workaround in the MAC */
1536 mac_reg = er32(FFLT_DBG);
1537 mac_reg &= ~(1 << 14);
1538 mac_reg |= (7 << 15);
1539 ew32(FFLT_DBG, mac_reg);
1540
1541 mac_reg = er32(RCTL);
1542 mac_reg |= E1000_RCTL_SECRC;
1543 ew32(RCTL, mac_reg);
1544
1545 ret_val = e1000e_read_kmrn_reg(hw,
1546 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1547 &data);
1548 if (ret_val)
1549 goto out;
1550 ret_val = e1000e_write_kmrn_reg(hw,
1551 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1552 data | (1 << 0));
1553 if (ret_val)
1554 goto out;
1555 ret_val = e1000e_read_kmrn_reg(hw,
1556 E1000_KMRNCTRLSTA_HD_CTRL,
1557 &data);
1558 if (ret_val)
1559 goto out;
1560 data &= ~(0xF << 8);
1561 data |= (0xB << 8);
1562 ret_val = e1000e_write_kmrn_reg(hw,
1563 E1000_KMRNCTRLSTA_HD_CTRL,
1564 data);
1565 if (ret_val)
1566 goto out;
1567
1568 /* Enable jumbo frame workaround in the PHY */
d3738bb8
BA		 1569 e1e_rphy(hw, PHY_REG(769, 23), &data);
1570 data &= ~(0x7F << 5);
1571 data |= (0x37 << 5);
1572 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1573 if (ret_val)
1574 goto out;
1575 e1e_rphy(hw, PHY_REG(769, 16), &data);
1576 data &= ~(1 << 13);
d3738bb8
BA		 1577 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1578 if (ret_val)
1579 goto out;
1580 e1e_rphy(hw, PHY_REG(776, 20), &data);
1581 data &= ~(0x3FF << 2);
1582 data |= (0x1A << 2);
1583 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1584 if (ret_val)
1585 goto out;
b64e9dd5 1586 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
d3738bb8
BA		 1587 if (ret_val)
1588 goto out;
1589 e1e_rphy(hw, HV_PM_CTRL, &data);
1590 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1591 if (ret_val)
1592 goto out;
1593 } else {
1594 /* Write MAC register values back to h/w defaults */
1595 mac_reg = er32(FFLT_DBG);
1596 mac_reg &= ~(0xF << 14);
1597 ew32(FFLT_DBG, mac_reg);
1598
1599 mac_reg = er32(RCTL);
1600 mac_reg &= ~E1000_RCTL_SECRC;
a1ce6473 1601 ew32(RCTL, mac_reg);
d3738bb8
BA		 1602
1603 ret_val = e1000e_read_kmrn_reg(hw,
1604 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1605 &data);
1606 if (ret_val)
1607 goto out;
1608 ret_val = e1000e_write_kmrn_reg(hw,
1609 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1610 data & ~(1 << 0));
1611 if (ret_val)
1612 goto out;
1613 ret_val = e1000e_read_kmrn_reg(hw,
1614 E1000_KMRNCTRLSTA_HD_CTRL,
1615 &data);
1616 if (ret_val)
1617 goto out;
1618 data &= ~(0xF << 8);
1619 data |= (0xB << 8);
1620 ret_val = e1000e_write_kmrn_reg(hw,
1621 E1000_KMRNCTRLSTA_HD_CTRL,
1622 data);
1623 if (ret_val)
1624 goto out;
1625
1626 /* Write PHY register values back to h/w defaults */
d3738bb8
BA		 1627 e1e_rphy(hw, PHY_REG(769, 23), &data);
1628 data &= ~(0x7F << 5);
1629 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1630 if (ret_val)
1631 goto out;
1632 e1e_rphy(hw, PHY_REG(769, 16), &data);
d3738bb8
BA		 1633 data |= (1 << 13);
1634 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1635 if (ret_val)
1636 goto out;
1637 e1e_rphy(hw, PHY_REG(776, 20), &data);
1638 data &= ~(0x3FF << 2);
1639 data |= (0x8 << 2);
1640 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1641 if (ret_val)
1642 goto out;
1643 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1644 if (ret_val)
1645 goto out;
1646 e1e_rphy(hw, HV_PM_CTRL, &data);
1647 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1648 if (ret_val)
1649 goto out;
1650 }
1651
1652 /* re-enable Rx path after enabling/disabling workaround */
1653 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1654
1655out:
1656 return ret_val;
1657}
1658
1659/**
1660 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1661 * done after every PHY reset.
1662 **/
1663static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1664{
1665 s32 ret_val = 0;
1666
1667 if (hw->mac.type != e1000_pch2lan)
1668 goto out;
1669
1670 /* Set MDIO slow mode before any other MDIO access */
1671 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1672
4d24136c
BA		 1673 ret_val = hw->phy.ops.acquire(hw);
1674 if (ret_val)
1675 goto out;
1676 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1677 I82579_MSE_THRESHOLD);
1678 if (ret_val)
1679 goto release;
1680 /* set MSE higher to enable link to stay up when noise is high */
1681 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034);
1682 if (ret_val)
1683 goto release;
1684 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1685 I82579_MSE_LINK_DOWN);
1686 if (ret_val)
1687 goto release;
1688 /* drop link after 5 times MSE threshold was reached */
1689 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005);
1690release:
1691 hw->phy.ops.release(hw);
1692
d3738bb8
BA		 1693out:
1694 return ret_val;
1695}
1696
831bd2e6
BA		 1697/**
1698 * e1000_k1_gig_workaround_lv - K1 Si workaround
1699 * @hw: pointer to the HW structure
1700 *
1701 * Workaround to set the K1 beacon duration for 82579 parts
1702 **/
1703static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1704{
1705 s32 ret_val = 0;
1706 u16 status_reg = 0;
1707 u32 mac_reg;
0ed013e2 1708 u16 phy_reg;
831bd2e6
BA		 1709
1710 if (hw->mac.type != e1000_pch2lan)
1711 goto out;
1712
1713 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1714 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1715 if (ret_val)
1716 goto out;
1717
1718 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1719 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1720 mac_reg = er32(FEXTNVM4);
1721 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1722
0ed013e2
BA		 1723 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1724 if (ret_val)
1725 goto out;
1726
1727 if (status_reg & HV_M_STATUS_SPEED_1000) {
831bd2e6 1728 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
0ed013e2
BA		 1729 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1730 } else {
831bd2e6 1731 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
0ed013e2
BA		 1732 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1733 }
831bd2e6 1734 ew32(FEXTNVM4, mac_reg);
0ed013e2 1735 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
831bd2e6
BA		 1736 }
1737
1738out:
1739 return ret_val;
1740}
1741
605c82ba
BA		 1742/**
1743 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1744 * @hw: pointer to the HW structure
1745 * @gate: boolean set to true to gate, false to ungate
1746 *
1747 * Gate/ungate the automatic PHY configuration via hardware; perform
1748 * the configuration via software instead.
1749 **/
1750static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1751{
1752 u32 extcnf_ctrl;
1753
1754 if (hw->mac.type != e1000_pch2lan)
1755 return;
1756
1757 extcnf_ctrl = er32(EXTCNF_CTRL);
1758
1759 if (gate)
1760 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1761 else
1762 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1763
1764 ew32(EXTCNF_CTRL, extcnf_ctrl);
605c82ba
BA		 1765}
1766
fc0c7760
BA		 1767/**
1768 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1769 * @hw: pointer to the HW structure
1770 *
1771 * Check the appropriate indication the MAC has finished configuring the
1772 * PHY after a software reset.
1773 **/
1774static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1775{
1776 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1777
1778 /* Wait for basic configuration completes before proceeding */
1779 do {
1780 data = er32(STATUS);
1781 data &= E1000_STATUS_LAN_INIT_DONE;
1782 udelay(100);
1783 } while ((!data) && --loop);
1784
1785 /*
1786 * If basic configuration is incomplete before the above loop
1787 * count reaches 0, loading the configuration from NVM will
1788 * leave the PHY in a bad state possibly resulting in no link.
1789 */
1790 if (loop == 0)
3bb99fe2 1791 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 1792
1793 /* Clear the Init Done bit for the next init event */
1794 data = er32(STATUS);
1795 data &= ~E1000_STATUS_LAN_INIT_DONE;
1796 ew32(STATUS, data);
1797}
1798
bc7f75fa 1799/**
e98cac44 1800 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 1801 * @hw: pointer to the HW structure
bc7f75fa 1802 **/
e98cac44 1803static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 1804{
f523d211
BA		 1805 s32 ret_val = 0;
1806 u16 reg;
bc7f75fa 1807
e98cac44
BA		 1808 if (e1000_check_reset_block(hw))
1809 goto out;
fc0c7760 1810
5f3eed6f 1811 /* Allow time for h/w to get to quiescent state after reset */
1bba4386 1812 usleep_range(10000, 20000);
5f3eed6f 1813
fddaa1af 1814 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 1815 switch (hw->mac.type) {
1816 case e1000_pchlan:
a4f58f54
BA		 1817 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1818 if (ret_val)
e98cac44
BA		 1819 goto out;
1820 break;
d3738bb8
BA		 1821 case e1000_pch2lan:
1822 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1823 if (ret_val)
1824 goto out;
1825 break;
e98cac44
BA		 1826 default:
1827 break;
a4f58f54
BA		 1828 }
1829
3ebfc7c9
BA		 1830 /* Clear the host wakeup bit after lcd reset */
1831 if (hw->mac.type >= e1000_pchlan) {
1832 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1833 reg &= ~BM_WUC_HOST_WU_BIT;
1834 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1835 }
db2932ec 1836
f523d211
BA		 1837 /* Configure the LCD with the extended configuration region in NVM */
1838 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1839 if (ret_val)
1840 goto out;
bc7f75fa 1841
f523d211 1842 /* Configure the LCD with the OEM bits in NVM */
e98cac44 1843 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 1844
1effb45c
BA		 1845 if (hw->mac.type == e1000_pch2lan) {
1846 /* Ungate automatic PHY configuration on non-managed 82579 */
1847 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1bba4386 1848 usleep_range(10000, 20000);
1effb45c
BA		 1849 e1000_gate_hw_phy_config_ich8lan(hw, false);
1850 }
1851
1852 /* Set EEE LPI Update Timer to 200usec */
1853 ret_val = hw->phy.ops.acquire(hw);
1854 if (ret_val)
1855 goto out;
1856 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1857 I82579_LPI_UPDATE_TIMER);
1858 if (ret_val)
1859 goto release;
1860 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1861 0x1387);
1862release:
1863 hw->phy.ops.release(hw);
605c82ba
BA		 1864 }
1865
f523d211 1866out:
e98cac44
BA		 1867 return ret_val;
1868}
1869
1870/**
1871 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1872 * @hw: pointer to the HW structure
1873 *
1874 * Resets the PHY
1875 * This is a function pointer entry point called by drivers
1876 * or other shared routines.
1877 **/
1878static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1879{
1880 s32 ret_val = 0;
1881
605c82ba
BA		 1882 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1883 if ((hw->mac.type == e1000_pch2lan) &&
1884 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1885 e1000_gate_hw_phy_config_ich8lan(hw, true);
1886
e98cac44
BA		 1887 ret_val = e1000e_phy_hw_reset_generic(hw);
1888 if (ret_val)
1889 goto out;
1890
1891 ret_val = e1000_post_phy_reset_ich8lan(hw);
1892
1893out:
1894 return ret_val;
bc7f75fa
AK		 1895}
1896
fa2ce13c
BA		 1897/**
1898 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1899 * @hw: pointer to the HW structure
1900 * @active: true to enable LPLU, false to disable
1901 *
1902 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1903 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1904 * the phy speed. This function will manually set the LPLU bit and restart
1905 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1906 * since it configures the same bit.
1907 **/
1908static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1909{
1910 s32 ret_val = 0;
1911 u16 oem_reg;
1912
1913 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1914 if (ret_val)
1915 goto out;
1916
1917 if (active)
1918 oem_reg |= HV_OEM_BITS_LPLU;
1919 else
1920 oem_reg &= ~HV_OEM_BITS_LPLU;
1921
464c85e3
BA		 1922 if (!e1000_check_reset_block(hw))
1923 oem_reg |= HV_OEM_BITS_RESTART_AN;
1924
fa2ce13c
BA		 1925 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1926
1927out:
1928 return ret_val;
1929}
1930
bc7f75fa
AK		 1931/**
1932 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1933 * @hw: pointer to the HW structure
564ea9bb 1934 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1935 *
1936 * Sets the LPLU D0 state according to the active flag. When
1937 * activating LPLU this function also disables smart speed
1938 * and vice versa. LPLU will not be activated unless the
1939 * device autonegotiation advertisement meets standards of
1940 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1941 * This is a function pointer entry point only called by
1942 * PHY setup routines.
1943 **/
1944static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1945{
1946 struct e1000_phy_info *phy = &hw->phy;
1947 u32 phy_ctrl;
1948 s32 ret_val = 0;
1949 u16 data;
1950
97ac8cae 1951 if (phy->type == e1000_phy_ife)
bc7f75fa
AK		 1952 return ret_val;
1953
1954 phy_ctrl = er32(PHY_CTRL);
1955
1956 if (active) {
1957 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1958 ew32(PHY_CTRL, phy_ctrl);
1959
60f1292f
BA		 1960 if (phy->type != e1000_phy_igp_3)
1961 return 0;
1962
ad68076e
BA		 1963 /*
1964 * Call gig speed drop workaround on LPLU before accessing
1965 * any PHY registers
1966 */
60f1292f 1967 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1968 e1000e_gig_downshift_workaround_ich8lan(hw);
1969
1970 /* When LPLU is enabled, we should disable SmartSpeed */
1971 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1972 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1973 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1974 if (ret_val)
1975 return ret_val;
1976 } else {
1977 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1978 ew32(PHY_CTRL, phy_ctrl);
1979
60f1292f
BA		 1980 if (phy->type != e1000_phy_igp_3)
1981 return 0;
1982
ad68076e
BA		 1983 /*
1984 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1985 * during Dx states where the power conservation is most
1986 * important. During driver activity we should enable
ad68076e
BA		 1987 * SmartSpeed, so performance is maintained.
1988 */
bc7f75fa
AK		 1989 if (phy->smart_speed == e1000_smart_speed_on) {
1990 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1991 &data);
bc7f75fa
AK		 1992 if (ret_val)
1993 return ret_val;
1994
1995 data |= IGP01E1000_PSCFR_SMART_SPEED;
1996 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1997 data);
bc7f75fa
AK		 1998 if (ret_val)
1999 return ret_val;
2000 } else if (phy->smart_speed == e1000_smart_speed_off) {
2001 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2002 &data);
bc7f75fa
AK		 2003 if (ret_val)
2004 return ret_val;
2005
2006 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2007 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2008 data);
bc7f75fa
AK		 2009 if (ret_val)
2010 return ret_val;
2011 }
2012 }
2013
2014 return 0;
2015}
2016
2017/**
2018 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2019 * @hw: pointer to the HW structure
564ea9bb 2020 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2021 *
2022 * Sets the LPLU D3 state according to the active flag. When
2023 * activating LPLU this function also disables smart speed
2024 * and vice versa. LPLU will not be activated unless the
2025 * device autonegotiation advertisement meets standards of
2026 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2027 * This is a function pointer entry point only called by
2028 * PHY setup routines.
2029 **/
2030static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2031{
2032 struct e1000_phy_info *phy = &hw->phy;
2033 u32 phy_ctrl;
2034 s32 ret_val;
2035 u16 data;
2036
2037 phy_ctrl = er32(PHY_CTRL);
2038
2039 if (!active) {
2040 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2041 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 2042
2043 if (phy->type != e1000_phy_igp_3)
2044 return 0;
2045
ad68076e
BA		 2046 /*
2047 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 2048 * during Dx states where the power conservation is most
2049 * important. During driver activity we should enable
ad68076e
BA		 2050 * SmartSpeed, so performance is maintained.
2051 */
bc7f75fa 2052 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 2053 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2054 &data);
bc7f75fa
AK		 2055 if (ret_val)
2056 return ret_val;
2057
2058 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2059 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2060 data);
bc7f75fa
AK		 2061 if (ret_val)
2062 return ret_val;
2063 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 2064 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2065 &data);
bc7f75fa
AK		 2066 if (ret_val)
2067 return ret_val;
2068
2069 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2070 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2071 data);
bc7f75fa
AK		 2072 if (ret_val)
2073 return ret_val;
2074 }
2075 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2076 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2077 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2078 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2079 ew32(PHY_CTRL, phy_ctrl);
2080
60f1292f
BA		 2081 if (phy->type != e1000_phy_igp_3)
2082 return 0;
2083
ad68076e
BA		 2084 /*
2085 * Call gig speed drop workaround on LPLU before accessing
2086 * any PHY registers
2087 */
60f1292f 2088 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 2089 e1000e_gig_downshift_workaround_ich8lan(hw);
2090
2091 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 2092 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 2093 if (ret_val)
2094 return ret_val;
2095
2096 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 2097 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 2098 }
2099
2100 return 0;
2101}
2102
f4187b56
BA		 2103/**
2104 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2105 * @hw: pointer to the HW structure
2106 * @bank: pointer to the variable that returns the active bank
2107 *
2108 * Reads signature byte from the NVM using the flash access registers.
e243455d 2109 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 2110 **/
2111static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2112{
e243455d 2113 u32 eecd;
f4187b56 2114 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 2115 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2116 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d
BA		 2117 u8 sig_byte = 0;
2118 s32 ret_val = 0;
f4187b56 2119
e243455d
BA		 2120 switch (hw->mac.type) {
2121 case e1000_ich8lan:
2122 case e1000_ich9lan:
2123 eecd = er32(EECD);
2124 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2125 E1000_EECD_SEC1VAL_VALID_MASK) {
2126 if (eecd & E1000_EECD_SEC1VAL)
2127 *bank = 1;
2128 else
2129 *bank = 0;
2130
2131 return 0;
2132 }
434f1392 2133 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
e243455d
BA		 2134 /* fall-thru */
2135 default:
2136 /* set bank to 0 in case flash read fails */
2137 *bank = 0;
2138
2139 /* Check bank 0 */
2140 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2141 &sig_byte);
2142 if (ret_val)
2143 return ret_val;
2144 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2145 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 2146 *bank = 0;
e243455d
BA		 2147 return 0;
2148 }
f4187b56 2149
e243455d
BA		 2150 /* Check bank 1 */
2151 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2152 bank1_offset,
2153 &sig_byte);
2154 if (ret_val)
2155 return ret_val;
2156 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2157 E1000_ICH_NVM_SIG_VALUE) {
2158 *bank = 1;
2159 return 0;
f4187b56 2160 }
e243455d 2161
3bb99fe2 2162 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 2163 return -E1000_ERR_NVM;
f4187b56
BA		 2164 }
2165
2166 return 0;
2167}
2168
bc7f75fa
AK		 2169/**
2170 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2171 * @hw: pointer to the HW structure
2172 * @offset: The offset (in bytes) of the word(s) to read.
2173 * @words: Size of data to read in words
2174 * @data: Pointer to the word(s) to read at offset.
2175 *
2176 * Reads a word(s) from the NVM using the flash access registers.
2177 **/
2178static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2179 u16 *data)
2180{
2181 struct e1000_nvm_info *nvm = &hw->nvm;
2182 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2183 u32 act_offset;
148675a7 2184 s32 ret_val = 0;
f4187b56 2185 u32 bank = 0;
bc7f75fa
AK		 2186 u16 i, word;
2187
2188 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2189 (words == 0)) {
3bb99fe2 2190 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 2191 ret_val = -E1000_ERR_NVM;
2192 goto out;
bc7f75fa
AK		 2193 }
2194
94d8186a 2195 nvm->ops.acquire(hw);
bc7f75fa 2196
f4187b56 2197 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 2198 if (ret_val) {
3bb99fe2 2199 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 2200 bank = 0;
2201 }
f4187b56
BA		 2202
2203 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 2204 act_offset += offset;
2205
148675a7 2206 ret_val = 0;
bc7f75fa 2207 for (i = 0; i < words; i++) {
b9e06f70 2208 if (dev_spec->shadow_ram[offset+i].modified) {
bc7f75fa
AK		 2209 data[i] = dev_spec->shadow_ram[offset+i].value;
2210 } else {
2211 ret_val = e1000_read_flash_word_ich8lan(hw,
2212 act_offset + i,
2213 &word);
2214 if (ret_val)
2215 break;
2216 data[i] = word;
2217 }
2218 }
2219
94d8186a 2220 nvm->ops.release(hw);
bc7f75fa 2221
e243455d
BA		 2222out:
2223 if (ret_val)
3bb99fe2 2224 e_dbg("NVM read error: %d\n", ret_val);
e243455d 2225
bc7f75fa
AK		 2226 return ret_val;
2227}
2228
2229/**
2230 * e1000_flash_cycle_init_ich8lan - Initialize flash
2231 * @hw: pointer to the HW structure
2232 *
2233 * This function does initial flash setup so that a new read/write/erase cycle
2234 * can be started.
2235 **/
2236static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2237{
2238 union ich8_hws_flash_status hsfsts;
2239 s32 ret_val = -E1000_ERR_NVM;
bc7f75fa
AK		 2240
2241 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2242
2243 /* Check if the flash descriptor is valid */
2244 if (hsfsts.hsf_status.fldesvalid == 0) {
434f1392 2245 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
bc7f75fa
AK		 2246 return -E1000_ERR_NVM;
2247 }
2248
2249 /* Clear FCERR and DAEL in hw status by writing 1 */
2250 hsfsts.hsf_status.flcerr = 1;
2251 hsfsts.hsf_status.dael = 1;
2252
2253 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2254
ad68076e
BA		 2255 /*
2256 * Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 2257 * bit to check against, in order to start a new cycle or
2258 * FDONE bit should be changed in the hardware so that it
489815ce 2259 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 2260 * indication whether a cycle is in progress or has been
2261 * completed.
2262 */
2263
2264 if (hsfsts.hsf_status.flcinprog == 0) {
ad68076e
BA		 2265 /*
2266 * There is no cycle running at present,
5ff5b664 2267 * so we can start a cycle.
ad68076e
BA		 2268 * Begin by setting Flash Cycle Done.
2269 */
bc7f75fa
AK		 2270 hsfsts.hsf_status.flcdone = 1;
2271 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2272 ret_val = 0;
2273 } else {
90da0669
BA		 2274 s32 i = 0;
2275
ad68076e 2276 /*
5ff5b664 2277 * Otherwise poll for sometime so the current
ad68076e
BA		 2278 * cycle has a chance to end before giving up.
2279 */
bc7f75fa 2280 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
c8243ee0 2281 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
bc7f75fa
AK		 2282 if (hsfsts.hsf_status.flcinprog == 0) {
2283 ret_val = 0;
2284 break;
2285 }
2286 udelay(1);
2287 }
9e2d7657 2288 if (!ret_val) {
ad68076e
BA		 2289 /*
2290 * Successful in waiting for previous cycle to timeout,
2291 * now set the Flash Cycle Done.
2292 */
bc7f75fa
AK		 2293 hsfsts.hsf_status.flcdone = 1;
2294 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2295 } else {
2c73e1fe 2296 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 2297 }
2298 }
2299
2300 return ret_val;
2301}
2302
2303/**
2304 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2305 * @hw: pointer to the HW structure
2306 * @timeout: maximum time to wait for completion
2307 *
2308 * This function starts a flash cycle and waits for its completion.
2309 **/
2310static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2311{
2312 union ich8_hws_flash_ctrl hsflctl;
2313 union ich8_hws_flash_status hsfsts;
2314 s32 ret_val = -E1000_ERR_NVM;
2315 u32 i = 0;
2316
2317 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2318 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2319 hsflctl.hsf_ctrl.flcgo = 1;
2320 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2321
2322 /* wait till FDONE bit is set to 1 */
2323 do {
2324 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2325 if (hsfsts.hsf_status.flcdone == 1)
2326 break;
2327 udelay(1);
2328 } while (i++ < timeout);
2329
2330 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2331 return 0;
2332
2333 return ret_val;
2334}
2335
2336/**
2337 * e1000_read_flash_word_ich8lan - Read word from flash
2338 * @hw: pointer to the HW structure
2339 * @offset: offset to data location
2340 * @data: pointer to the location for storing the data
2341 *
2342 * Reads the flash word at offset into data. Offset is converted
2343 * to bytes before read.
2344 **/
2345static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2346 u16 *data)
2347{
2348 /* Must convert offset into bytes. */
2349 offset <<= 1;
2350
2351 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2352}
2353
f4187b56
BA		 2354/**
2355 * e1000_read_flash_byte_ich8lan - Read byte from flash
2356 * @hw: pointer to the HW structure
2357 * @offset: The offset of the byte to read.
2358 * @data: Pointer to a byte to store the value read.
2359 *
2360 * Reads a single byte from the NVM using the flash access registers.
2361 **/
2362static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2363 u8 *data)
2364{
2365 s32 ret_val;
2366 u16 word = 0;
2367
2368 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2369 if (ret_val)
2370 return ret_val;
2371
2372 *data = (u8)word;
2373
2374 return 0;
2375}
2376
bc7f75fa
AK		 2377/**
2378 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2379 * @hw: pointer to the HW structure
2380 * @offset: The offset (in bytes) of the byte or word to read.
2381 * @size: Size of data to read, 1=byte 2=word
2382 * @data: Pointer to the word to store the value read.
2383 *
2384 * Reads a byte or word from the NVM using the flash access registers.
2385 **/
2386static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2387 u8 size, u16 *data)
2388{
2389 union ich8_hws_flash_status hsfsts;
2390 union ich8_hws_flash_ctrl hsflctl;
2391 u32 flash_linear_addr;
2392 u32 flash_data = 0;
2393 s32 ret_val = -E1000_ERR_NVM;
2394 u8 count = 0;
2395
2396 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2397 return -E1000_ERR_NVM;
2398
2399 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2400 hw->nvm.flash_base_addr;
2401
2402 do {
2403 udelay(1);
2404 /* Steps */
2405 ret_val = e1000_flash_cycle_init_ich8lan(hw);
9e2d7657 2406 if (ret_val)
bc7f75fa
AK		 2407 break;
2408
2409 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2410 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2411 hsflctl.hsf_ctrl.fldbcount = size - 1;
2412 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2413 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2414
2415 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2416
2417 ret_val = e1000_flash_cycle_ich8lan(hw,
2418 ICH_FLASH_READ_COMMAND_TIMEOUT);
2419
ad68076e
BA		 2420 /*
2421 * Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 2422 * and try the whole sequence a few more times, else
2423 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 2424 * least significant byte first msb to lsb
2425 */
9e2d7657 2426 if (!ret_val) {
bc7f75fa 2427 flash_data = er32flash(ICH_FLASH_FDATA0);
b1cdfead 2428 if (size == 1)
bc7f75fa 2429 *data = (u8)(flash_data & 0x000000FF);
b1cdfead 2430 else if (size == 2)
bc7f75fa 2431 *data = (u16)(flash_data & 0x0000FFFF);
bc7f75fa
AK		 2432 break;
2433 } else {
ad68076e
BA		 2434 /*
2435 * If we've gotten here, then things are probably
bc7f75fa
AK		 2436 * completely hosed, but if the error condition is
2437 * detected, it won't hurt to give it another try...
2438 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2439 */
2440 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2441 if (hsfsts.hsf_status.flcerr == 1) {
2442 /* Repeat for some time before giving up. */
2443 continue;
2444 } else if (hsfsts.hsf_status.flcdone == 0) {
434f1392 2445 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 2446 break;
2447 }
2448 }
2449 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2450
2451 return ret_val;
2452}
2453
2454/**
2455 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2456 * @hw: pointer to the HW structure
2457 * @offset: The offset (in bytes) of the word(s) to write.
2458 * @words: Size of data to write in words
2459 * @data: Pointer to the word(s) to write at offset.
2460 *
2461 * Writes a byte or word to the NVM using the flash access registers.
2462 **/
2463static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2464 u16 *data)
2465{
2466 struct e1000_nvm_info *nvm = &hw->nvm;
2467 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 2468 u16 i;
2469
2470 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2471 (words == 0)) {
3bb99fe2 2472 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 2473 return -E1000_ERR_NVM;
2474 }
2475
94d8186a 2476 nvm->ops.acquire(hw);
ca15df58 2477
bc7f75fa 2478 for (i = 0; i < words; i++) {
564ea9bb 2479 dev_spec->shadow_ram[offset+i].modified = true;
bc7f75fa
AK		 2480 dev_spec->shadow_ram[offset+i].value = data[i];
2481 }
2482
94d8186a 2483 nvm->ops.release(hw);
ca15df58 2484
bc7f75fa
AK		 2485 return 0;
2486}
2487
2488/**
2489 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2490 * @hw: pointer to the HW structure
2491 *
2492 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2493 * which writes the checksum to the shadow ram. The changes in the shadow
2494 * ram are then committed to the EEPROM by processing each bank at a time
2495 * checking for the modified bit and writing only the pending changes.
489815ce 2496 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 2497 * future writes.
2498 **/
2499static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2500{
2501 struct e1000_nvm_info *nvm = &hw->nvm;
2502 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 2503 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 2504 s32 ret_val;
2505 u16 data;
2506
2507 ret_val = e1000e_update_nvm_checksum_generic(hw);
2508 if (ret_val)
e243455d 2509 goto out;
bc7f75fa
AK		 2510
2511 if (nvm->type != e1000_nvm_flash_sw)
e243455d 2512 goto out;
bc7f75fa 2513
94d8186a 2514 nvm->ops.acquire(hw);
bc7f75fa 2515
ad68076e
BA		 2516 /*
2517 * We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 2518 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 2519 * is going to be written
2520 */
f4187b56 2521 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 2522 if (ret_val) {
3bb99fe2 2523 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 2524 bank = 0;
e243455d 2525 }
f4187b56
BA		 2526
2527 if (bank == 0) {
bc7f75fa
AK		 2528 new_bank_offset = nvm->flash_bank_size;
2529 old_bank_offset = 0;
e243455d 2530 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 2531 if (ret_val)
2532 goto release;
bc7f75fa
AK		 2533 } else {
2534 old_bank_offset = nvm->flash_bank_size;
2535 new_bank_offset = 0;
e243455d 2536 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 2537 if (ret_val)
2538 goto release;
bc7f75fa
AK		 2539 }
2540
2541 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
ad68076e
BA		 2542 /*
2543 * Determine whether to write the value stored
bc7f75fa 2544 * in the other NVM bank or a modified value stored
ad68076e
BA		 2545 * in the shadow RAM
2546 */
bc7f75fa
AK		 2547 if (dev_spec->shadow_ram[i].modified) {
2548 data = dev_spec->shadow_ram[i].value;
2549 } else {
e243455d
BA		 2550 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2551 old_bank_offset,
2552 &data);
2553 if (ret_val)
2554 break;
bc7f75fa
AK		 2555 }
2556
ad68076e
BA		 2557 /*
2558 * If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 2559 * (15:14) are 11b until the commit has completed.
2560 * This will allow us to write 10b which indicates the
2561 * signature is valid. We want to do this after the write
2562 * has completed so that we don't mark the segment valid
ad68076e
BA		 2563 * while the write is still in progress
2564 */
bc7f75fa
AK		 2565 if (i == E1000_ICH_NVM_SIG_WORD)
2566 data |= E1000_ICH_NVM_SIG_MASK;
2567
2568 /* Convert offset to bytes. */
2569 act_offset = (i + new_bank_offset) << 1;
2570
2571 udelay(100);
2572 /* Write the bytes to the new bank. */
2573 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2574 act_offset,
2575 (u8)data);
2576 if (ret_val)
2577 break;
2578
2579 udelay(100);
2580 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2581 act_offset + 1,
2582 (u8)(data >> 8));
2583 if (ret_val)
2584 break;
2585 }
2586
ad68076e
BA		 2587 /*
2588 * Don't bother writing the segment valid bits if sector
2589 * programming failed.
2590 */
bc7f75fa 2591 if (ret_val) {
4a770358 2592 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 2593 e_dbg("Flash commit failed.\n");
9c5e209d 2594 goto release;
bc7f75fa
AK		 2595 }
2596
ad68076e
BA		 2597 /*
2598 * Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 2599 * to 10b in word 0x13 , this can be done without an
2600 * erase as well since these bits are 11 to start with
ad68076e
BA		 2601 * and we need to change bit 14 to 0b
2602 */
bc7f75fa 2603 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 2604 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 2605 if (ret_val)
2606 goto release;
2607
bc7f75fa
AK		 2608 data &= 0xBFFF;
2609 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2610 act_offset * 2 + 1,
2611 (u8)(data >> 8));
9c5e209d
BA		 2612 if (ret_val)
2613 goto release;
bc7f75fa 2614
ad68076e
BA		 2615 /*
2616 * And invalidate the previously valid segment by setting
bc7f75fa
AK		 2617 * its signature word (0x13) high_byte to 0b. This can be
2618 * done without an erase because flash erase sets all bits
ad68076e
BA		 2619 * to 1's. We can write 1's to 0's without an erase
2620 */
bc7f75fa
AK		 2621 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2622 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 2623 if (ret_val)
2624 goto release;
bc7f75fa
AK		 2625
2626 /* Great! Everything worked, we can now clear the cached entries. */
2627 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2628 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2629 dev_spec->shadow_ram[i].value = 0xFFFF;
2630 }
2631
9c5e209d 2632release:
94d8186a 2633 nvm->ops.release(hw);
bc7f75fa 2634
ad68076e
BA		 2635 /*
2636 * Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2637 * until after the next adapter reset.
2638 */
9c5e209d
BA		 2639 if (!ret_val) {
2640 e1000e_reload_nvm(hw);
1bba4386 2641 usleep_range(10000, 20000);
9c5e209d 2642 }
bc7f75fa 2643
e243455d
BA		 2644out:
2645 if (ret_val)
3bb99fe2 2646 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2647
bc7f75fa
AK		 2648 return ret_val;
2649}
2650
2651/**
2652 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2653 * @hw: pointer to the HW structure
2654 *
2655 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2656 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2657 * calculated, in which case we need to calculate the checksum and set bit 6.
2658 **/
2659static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2660{
2661 s32 ret_val;
2662 u16 data;
2663
ad68076e
BA		 2664 /*
2665 * Read 0x19 and check bit 6. If this bit is 0, the checksum
bc7f75fa
AK		 2666 * needs to be fixed. This bit is an indication that the NVM
2667 * was prepared by OEM software and did not calculate the
2668 * checksum...a likely scenario.
2669 */
2670 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2671 if (ret_val)
2672 return ret_val;
2673
2674 if ((data & 0x40) == 0) {
2675 data |= 0x40;
2676 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2677 if (ret_val)
2678 return ret_val;
2679 ret_val = e1000e_update_nvm_checksum(hw);
2680 if (ret_val)
2681 return ret_val;
2682 }
2683
2684 return e1000e_validate_nvm_checksum_generic(hw);
2685}
2686
4a770358
BA		 2687/**
2688 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2689 * @hw: pointer to the HW structure
2690 *
2691 * To prevent malicious write/erase of the NVM, set it to be read-only
2692 * so that the hardware ignores all write/erase cycles of the NVM via
2693 * the flash control registers. The shadow-ram copy of the NVM will
2694 * still be updated, however any updates to this copy will not stick
2695 * across driver reloads.
2696 **/
2697void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2698{
ca15df58 2699 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2700 union ich8_flash_protected_range pr0;
2701 union ich8_hws_flash_status hsfsts;
2702 u32 gfpreg;
4a770358 2703
94d8186a 2704 nvm->ops.acquire(hw);
4a770358
BA		 2705
2706 gfpreg = er32flash(ICH_FLASH_GFPREG);
2707
2708 /* Write-protect GbE Sector of NVM */
2709 pr0.regval = er32flash(ICH_FLASH_PR0);
2710 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2711 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2712 pr0.range.wpe = true;
2713 ew32flash(ICH_FLASH_PR0, pr0.regval);
2714
2715 /*
2716 * Lock down a subset of GbE Flash Control Registers, e.g.
2717 * PR0 to prevent the write-protection from being lifted.
2718 * Once FLOCKDN is set, the registers protected by it cannot
2719 * be written until FLOCKDN is cleared by a hardware reset.
2720 */
2721 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2722 hsfsts.hsf_status.flockdn = true;
2723 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2724
94d8186a 2725 nvm->ops.release(hw);
4a770358
BA		 2726}
2727
bc7f75fa
AK		 2728/**
2729 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2730 * @hw: pointer to the HW structure
2731 * @offset: The offset (in bytes) of the byte/word to read.
2732 * @size: Size of data to read, 1=byte 2=word
2733 * @data: The byte(s) to write to the NVM.
2734 *
2735 * Writes one/two bytes to the NVM using the flash access registers.
2736 **/
2737static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2738 u8 size, u16 data)
2739{
2740 union ich8_hws_flash_status hsfsts;
2741 union ich8_hws_flash_ctrl hsflctl;
2742 u32 flash_linear_addr;
2743 u32 flash_data = 0;
2744 s32 ret_val;
2745 u8 count = 0;
2746
2747 if (size < 1 || size > 2 || data > size * 0xff ||
2748 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2749 return -E1000_ERR_NVM;
2750
2751 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2752 hw->nvm.flash_base_addr;
2753
2754 do {
2755 udelay(1);
2756 /* Steps */
2757 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2758 if (ret_val)
2759 break;
2760
2761 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2762 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2763 hsflctl.hsf_ctrl.fldbcount = size -1;
2764 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2765 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2766
2767 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2768
2769 if (size == 1)
2770 flash_data = (u32)data & 0x00FF;
2771 else
2772 flash_data = (u32)data;
2773
2774 ew32flash(ICH_FLASH_FDATA0, flash_data);
2775
ad68076e
BA		 2776 /*
2777 * check if FCERR is set to 1 , if set to 1, clear it
2778 * and try the whole sequence a few more times else done
2779 */
bc7f75fa
AK		 2780 ret_val = e1000_flash_cycle_ich8lan(hw,
2781 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2782 if (!ret_val)
2783 break;
2784
ad68076e
BA		 2785 /*
2786 * If we're here, then things are most likely
bc7f75fa
AK		 2787 * completely hosed, but if the error condition
2788 * is detected, it won't hurt to give it another
2789 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2790 */
2791 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2792 if (hsfsts.hsf_status.flcerr == 1)
2793 /* Repeat for some time before giving up. */
2794 continue;
2795 if (hsfsts.hsf_status.flcdone == 0) {
434f1392 2796 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 2797 break;
2798 }
2799 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2800
2801 return ret_val;
2802}
2803
2804/**
2805 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2806 * @hw: pointer to the HW structure
2807 * @offset: The index of the byte to read.
2808 * @data: The byte to write to the NVM.
2809 *
2810 * Writes a single byte to the NVM using the flash access registers.
2811 **/
2812static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2813 u8 data)
2814{
2815 u16 word = (u16)data;
2816
2817 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2818}
2819
2820/**
2821 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2822 * @hw: pointer to the HW structure
2823 * @offset: The offset of the byte to write.
2824 * @byte: The byte to write to the NVM.
2825 *
2826 * Writes a single byte to the NVM using the flash access registers.
2827 * Goes through a retry algorithm before giving up.
2828 **/
2829static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2830 u32 offset, u8 byte)
2831{
2832 s32 ret_val;
2833 u16 program_retries;
2834
2835 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2836 if (!ret_val)
2837 return ret_val;
2838
2839 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 2840 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 2841 udelay(100);
2842 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2843 if (!ret_val)
2844 break;
2845 }
2846 if (program_retries == 100)
2847 return -E1000_ERR_NVM;
2848
2849 return 0;
2850}
2851
2852/**
2853 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2854 * @hw: pointer to the HW structure
2855 * @bank: 0 for first bank, 1 for second bank, etc.
2856 *
2857 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2858 * bank N is 4096 * N + flash_reg_addr.
2859 **/
2860static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2861{
2862 struct e1000_nvm_info *nvm = &hw->nvm;
2863 union ich8_hws_flash_status hsfsts;
2864 union ich8_hws_flash_ctrl hsflctl;
2865 u32 flash_linear_addr;
2866 /* bank size is in 16bit words - adjust to bytes */
2867 u32 flash_bank_size = nvm->flash_bank_size * 2;
2868 s32 ret_val;
2869 s32 count = 0;
a708dd88 2870 s32 j, iteration, sector_size;
bc7f75fa
AK		 2871
2872 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2873
ad68076e
BA		 2874 /*
2875 * Determine HW Sector size: Read BERASE bits of hw flash status
2876 * register
2877 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 2878 * consecutive sectors. The start index for the nth Hw sector
2879 * can be calculated as = bank * 4096 + n * 256
2880 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2881 * The start index for the nth Hw sector can be calculated
2882 * as = bank * 4096
2883 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2884 * (ich9 only, otherwise error condition)
2885 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2886 */
2887 switch (hsfsts.hsf_status.berasesz) {
2888 case 0:
2889 /* Hw sector size 256 */
2890 sector_size = ICH_FLASH_SEG_SIZE_256;
2891 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2892 break;
2893 case 1:
2894 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 2895 iteration = 1;
bc7f75fa
AK		 2896 break;
2897 case 2:
148675a7
BA		 2898 sector_size = ICH_FLASH_SEG_SIZE_8K;
2899 iteration = 1;
bc7f75fa
AK		 2900 break;
2901 case 3:
2902 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 2903 iteration = 1;
bc7f75fa
AK		 2904 break;
2905 default:
2906 return -E1000_ERR_NVM;
2907 }
2908
2909 /* Start with the base address, then add the sector offset. */
2910 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 2911 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa
AK		 2912
2913 for (j = 0; j < iteration ; j++) {
2914 do {
2915 /* Steps */
2916 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2917 if (ret_val)
2918 return ret_val;
2919
ad68076e
BA		 2920 /*
2921 * Write a value 11 (block Erase) in Flash
2922 * Cycle field in hw flash control
2923 */
bc7f75fa
AK		 2924 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2925 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2926 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2927
ad68076e
BA		 2928 /*
2929 * Write the last 24 bits of an index within the
bc7f75fa
AK		 2930 * block into Flash Linear address field in Flash
2931 * Address.
2932 */
2933 flash_linear_addr += (j * sector_size);
2934 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2935
2936 ret_val = e1000_flash_cycle_ich8lan(hw,
2937 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
9e2d7657 2938 if (!ret_val)
bc7f75fa
AK		 2939 break;
2940
ad68076e
BA		 2941 /*
2942 * Check if FCERR is set to 1. If 1,
bc7f75fa 2943 * clear it and try the whole sequence
ad68076e
BA		 2944 * a few more times else Done
2945 */
bc7f75fa
AK		 2946 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2947 if (hsfsts.hsf_status.flcerr == 1)
ad68076e 2948 /* repeat for some time before giving up */
bc7f75fa
AK		 2949 continue;
2950 else if (hsfsts.hsf_status.flcdone == 0)
2951 return ret_val;
2952 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2953 }
2954
2955 return 0;
2956}
2957
2958/**
2959 * e1000_valid_led_default_ich8lan - Set the default LED settings
2960 * @hw: pointer to the HW structure
2961 * @data: Pointer to the LED settings
2962 *
2963 * Reads the LED default settings from the NVM to data. If the NVM LED
2964 * settings is all 0's or F's, set the LED default to a valid LED default
2965 * setting.
2966 **/
2967static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2968{
2969 s32 ret_val;
2970
2971 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2972 if (ret_val) {
3bb99fe2 2973 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 2974 return ret_val;
2975 }
2976
2977 if (*data == ID_LED_RESERVED_0000 ||
2978 *data == ID_LED_RESERVED_FFFF)
2979 *data = ID_LED_DEFAULT_ICH8LAN;
2980
2981 return 0;
2982}
2983
a4f58f54
BA		 2984/**
2985 * e1000_id_led_init_pchlan - store LED configurations
2986 * @hw: pointer to the HW structure
2987 *
2988 * PCH does not control LEDs via the LEDCTL register, rather it uses
2989 * the PHY LED configuration register.
2990 *
2991 * PCH also does not have an "always on" or "always off" mode which
2992 * complicates the ID feature. Instead of using the "on" mode to indicate
2993 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2994 * use "link_up" mode. The LEDs will still ID on request if there is no
2995 * link based on logic in e1000_led_[on|off]_pchlan().
2996 **/
2997static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2998{
2999 struct e1000_mac_info *mac = &hw->mac;
3000 s32 ret_val;
3001 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3002 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3003 u16 data, i, temp, shift;
3004
3005 /* Get default ID LED modes */
3006 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3007 if (ret_val)
3008 goto out;
3009
3010 mac->ledctl_default = er32(LEDCTL);
3011 mac->ledctl_mode1 = mac->ledctl_default;
3012 mac->ledctl_mode2 = mac->ledctl_default;
3013
3014 for (i = 0; i < 4; i++) {
3015 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3016 shift = (i * 5);
3017 switch (temp) {
3018 case ID_LED_ON1_DEF2:
3019 case ID_LED_ON1_ON2:
3020 case ID_LED_ON1_OFF2:
3021 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3022 mac->ledctl_mode1 |= (ledctl_on << shift);
3023 break;
3024 case ID_LED_OFF1_DEF2:
3025 case ID_LED_OFF1_ON2:
3026 case ID_LED_OFF1_OFF2:
3027 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3028 mac->ledctl_mode1 |= (ledctl_off << shift);
3029 break;
3030 default:
3031 /* Do nothing */
3032 break;
3033 }
3034 switch (temp) {
3035 case ID_LED_DEF1_ON2:
3036 case ID_LED_ON1_ON2:
3037 case ID_LED_OFF1_ON2:
3038 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3039 mac->ledctl_mode2 |= (ledctl_on << shift);
3040 break;
3041 case ID_LED_DEF1_OFF2:
3042 case ID_LED_ON1_OFF2:
3043 case ID_LED_OFF1_OFF2:
3044 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3045 mac->ledctl_mode2 |= (ledctl_off << shift);
3046 break;
3047 default:
3048 /* Do nothing */
3049 break;
3050 }
3051 }
3052
3053out:
3054 return ret_val;
3055}
3056
bc7f75fa
AK		 3057/**
3058 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3059 * @hw: pointer to the HW structure
3060 *
3061 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3062 * register, so the the bus width is hard coded.
3063 **/
3064static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3065{
3066 struct e1000_bus_info *bus = &hw->bus;
3067 s32 ret_val;
3068
3069 ret_val = e1000e_get_bus_info_pcie(hw);
3070
ad68076e
BA		 3071 /*
3072 * ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 3073 * a configuration space, but do not contain
3074 * PCI Express Capability registers, so bus width
3075 * must be hardcoded.
3076 */
3077 if (bus->width == e1000_bus_width_unknown)
3078 bus->width = e1000_bus_width_pcie_x1;
3079
3080 return ret_val;
3081}
3082
3083/**
3084 * e1000_reset_hw_ich8lan - Reset the hardware
3085 * @hw: pointer to the HW structure
3086 *
3087 * Does a full reset of the hardware which includes a reset of the PHY and
3088 * MAC.
3089 **/
3090static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3091{
1d5846b9 3092 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
db2932ec 3093 u16 reg;
dd93f95e 3094 u32 ctrl, kab;
bc7f75fa
AK		 3095 s32 ret_val;
3096
ad68076e
BA		 3097 /*
3098 * Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 3099 * on the last TLP read/write transaction when MAC is reset.
3100 */
3101 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 3102 if (ret_val)
3bb99fe2 3103 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 3104
3bb99fe2 3105 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 3106 ew32(IMC, 0xffffffff);
3107
ad68076e
BA		 3108 /*
3109 * Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 3110 * any pending transactions to complete before we hit the MAC
3111 * with the global reset.
3112 */
3113 ew32(RCTL, 0);
3114 ew32(TCTL, E1000_TCTL_PSP);
3115 e1e_flush();
3116
1bba4386 3117 usleep_range(10000, 20000);
bc7f75fa
AK		 3118
3119 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3120 if (hw->mac.type == e1000_ich8lan) {
3121 /* Set Tx and Rx buffer allocation to 8k apiece. */
3122 ew32(PBA, E1000_PBA_8K);
3123 /* Set Packet Buffer Size to 16k. */
3124 ew32(PBS, E1000_PBS_16K);
3125 }
3126
1d5846b9
BA		 3127 if (hw->mac.type == e1000_pchlan) {
3128 /* Save the NVM K1 bit setting*/
3129 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3130 if (ret_val)
3131 return ret_val;
3132
3133 if (reg & E1000_NVM_K1_ENABLE)
3134 dev_spec->nvm_k1_enabled = true;
3135 else
3136 dev_spec->nvm_k1_enabled = false;
3137 }
3138
bc7f75fa
AK		 3139 ctrl = er32(CTRL);
3140
3141 if (!e1000_check_reset_block(hw)) {
ad68076e 3142 /*
e98cac44 3143 * Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 3144 * time to make sure the interface between MAC and the
3145 * external PHY is reset.
3146 */
3147 ctrl |= E1000_CTRL_PHY_RST;
605c82ba
BA		 3148
3149 /*
3150 * Gate automatic PHY configuration by hardware on
3151 * non-managed 82579
3152 */
3153 if ((hw->mac.type == e1000_pch2lan) &&
3154 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3155 e1000_gate_hw_phy_config_ich8lan(hw, true);
bc7f75fa
AK		 3156 }
3157 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 3158 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa 3159 ew32(CTRL, (ctrl | E1000_CTRL_RST));
945a5151 3160 /* cannot issue a flush here because it hangs the hardware */
bc7f75fa
AK		 3161 msleep(20);
3162
fc0c7760 3163 if (!ret_val)
a90b412c 3164 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
37f40239 3165
e98cac44 3166 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 3167 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44
BA		 3168 if (ret_val)
3169 goto out;
fc0c7760 3170
e98cac44 3171 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211
BA		 3172 if (ret_val)
3173 goto out;
3174 }
e98cac44 3175
7d3cabbc
BA		 3176 /*
3177 * For PCH, this write will make sure that any noise
3178 * will be detected as a CRC error and be dropped rather than show up
3179 * as a bad packet to the DMA engine.
3180 */
3181 if (hw->mac.type == e1000_pchlan)
3182 ew32(CRC_OFFSET, 0x65656565);
3183
bc7f75fa 3184 ew32(IMC, 0xffffffff);
dd93f95e 3185 er32(ICR);
bc7f75fa
AK		 3186
3187 kab = er32(KABGTXD);
3188 kab |= E1000_KABGTXD_BGSQLBIAS;
3189 ew32(KABGTXD, kab);
3190
f523d211 3191out:
bc7f75fa
AK		 3192 return ret_val;
3193}
3194
3195/**
3196 * e1000_init_hw_ich8lan - Initialize the hardware
3197 * @hw: pointer to the HW structure
3198 *
3199 * Prepares the hardware for transmit and receive by doing the following:
3200 * - initialize hardware bits
3201 * - initialize LED identification
3202 * - setup receive address registers
3203 * - setup flow control
489815ce 3204 * - setup transmit descriptors
bc7f75fa
AK		 3205 * - clear statistics
3206 **/
3207static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3208{
3209 struct e1000_mac_info *mac = &hw->mac;
3210 u32 ctrl_ext, txdctl, snoop;
3211 s32 ret_val;
3212 u16 i;
3213
3214 e1000_initialize_hw_bits_ich8lan(hw);
3215
3216 /* Initialize identification LED */
a4f58f54 3217 ret_val = mac->ops.id_led_init(hw);
de39b752 3218 if (ret_val)
3bb99fe2 3219 e_dbg("Error initializing identification LED\n");
de39b752 3220 /* This is not fatal and we should not stop init due to this */
bc7f75fa
AK		 3221
3222 /* Setup the receive address. */
3223 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3224
3225 /* Zero out the Multicast HASH table */
3bb99fe2 3226 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 3227 for (i = 0; i < mac->mta_reg_count; i++)
3228 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3229
fc0c7760
BA		 3230 /*
3231 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3ebfc7c9 3232 * the ME. Disable wakeup by clearing the host wakeup bit.
fc0c7760
BA		 3233 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3234 */
3235 if (hw->phy.type == e1000_phy_82578) {
3ebfc7c9
BA		 3236 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3237 i &= ~BM_WUC_HOST_WU_BIT;
3238 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
fc0c7760
BA		 3239 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3240 if (ret_val)
3241 return ret_val;
3242 }
3243
bc7f75fa
AK		 3244 /* Setup link and flow control */
3245 ret_val = e1000_setup_link_ich8lan(hw);
3246
3247 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 3248 txdctl = er32(TXDCTL(0));
bc7f75fa
AK		 3249 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3250 E1000_TXDCTL_FULL_TX_DESC_WB;
3251 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3252 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f
JK		 3253 ew32(TXDCTL(0), txdctl);
3254 txdctl = er32(TXDCTL(1));
bc7f75fa
AK		 3255 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3256 E1000_TXDCTL_FULL_TX_DESC_WB;
3257 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3258 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f 3259 ew32(TXDCTL(1), txdctl);
bc7f75fa 3260
ad68076e
BA		 3261 /*
3262 * ICH8 has opposite polarity of no_snoop bits.
3263 * By default, we should use snoop behavior.
3264 */
bc7f75fa
AK		 3265 if (mac->type == e1000_ich8lan)
3266 snoop = PCIE_ICH8_SNOOP_ALL;
3267 else
3268 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3269 e1000e_set_pcie_no_snoop(hw, snoop);
3270
3271 ctrl_ext = er32(CTRL_EXT);
3272 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3273 ew32(CTRL_EXT, ctrl_ext);
3274
ad68076e
BA		 3275 /*
3276 * Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 3277 * important that we do this after we have tried to establish link
3278 * because the symbol error count will increment wildly if there
3279 * is no link.
3280 */
3281 e1000_clear_hw_cntrs_ich8lan(hw);
3282
3283 return 0;
3284}
3285/**
3286 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3287 * @hw: pointer to the HW structure
3288 *
3289 * Sets/Clears required hardware bits necessary for correctly setting up the
3290 * hardware for transmit and receive.
3291 **/
3292static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3293{
3294 u32 reg;
3295
3296 /* Extended Device Control */
3297 reg = er32(CTRL_EXT);
3298 reg |= (1 << 22);
a4f58f54
BA		 3299 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3300 if (hw->mac.type >= e1000_pchlan)
3301 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 3302 ew32(CTRL_EXT, reg);
3303
3304 /* Transmit Descriptor Control 0 */
e9ec2c0f 3305 reg = er32(TXDCTL(0));
bc7f75fa 3306 reg |= (1 << 22);
e9ec2c0f 3307 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 3308
3309 /* Transmit Descriptor Control 1 */
e9ec2c0f 3310 reg = er32(TXDCTL(1));
bc7f75fa 3311 reg |= (1 << 22);
e9ec2c0f 3312 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 3313
3314 /* Transmit Arbitration Control 0 */
e9ec2c0f 3315 reg = er32(TARC(0));
bc7f75fa
AK		 3316 if (hw->mac.type == e1000_ich8lan)
3317 reg |= (1 << 28) | (1 << 29);
3318 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 3319 ew32(TARC(0), reg);
bc7f75fa
AK		 3320
3321 /* Transmit Arbitration Control 1 */
e9ec2c0f 3322 reg = er32(TARC(1));
bc7f75fa
AK		 3323 if (er32(TCTL) & E1000_TCTL_MULR)
3324 reg &= ~(1 << 28);
3325 else
3326 reg |= (1 << 28);
3327 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 3328 ew32(TARC(1), reg);
bc7f75fa
AK		 3329
3330 /* Device Status */
3331 if (hw->mac.type == e1000_ich8lan) {
3332 reg = er32(STATUS);
3333 reg &= ~(1 << 31);
3334 ew32(STATUS, reg);
3335 }
a80483d3
JB		 3336
3337 /*
3338 * work-around descriptor data corruption issue during nfs v2 udp
3339 * traffic, just disable the nfs filtering capability
3340 */
3341 reg = er32(RFCTL);
3342 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3343 ew32(RFCTL, reg);
bc7f75fa
AK		 3344}
3345
3346/**
3347 * e1000_setup_link_ich8lan - Setup flow control and link settings
3348 * @hw: pointer to the HW structure
3349 *
3350 * Determines which flow control settings to use, then configures flow
3351 * control. Calls the appropriate media-specific link configuration
3352 * function. Assuming the adapter has a valid link partner, a valid link
3353 * should be established. Assumes the hardware has previously been reset
3354 * and the transmitter and receiver are not enabled.
3355 **/
3356static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3357{
bc7f75fa
AK		 3358 s32 ret_val;
3359
3360 if (e1000_check_reset_block(hw))
3361 return 0;
3362
ad68076e
BA		 3363 /*
3364 * ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 3365 * the default flow control setting, so we explicitly
3366 * set it to full.
3367 */
37289d9c
BA		 3368 if (hw->fc.requested_mode == e1000_fc_default) {
3369 /* Workaround h/w hang when Tx flow control enabled */
3370 if (hw->mac.type == e1000_pchlan)
3371 hw->fc.requested_mode = e1000_fc_rx_pause;
3372 else
3373 hw->fc.requested_mode = e1000_fc_full;
3374 }
bc7f75fa 3375
5c48ef3e
BA		 3376 /*
3377 * Save off the requested flow control mode for use later. Depending
3378 * on the link partner's capabilities, we may or may not use this mode.
3379 */
3380 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 3381
3bb99fe2 3382 e_dbg("After fix-ups FlowControl is now = %x\n",
5c48ef3e 3383 hw->fc.current_mode);
bc7f75fa
AK		 3384
3385 /* Continue to configure the copper link. */
3386 ret_val = e1000_setup_copper_link_ich8lan(hw);
3387 if (ret_val)
3388 return ret_val;
3389
318a94d6 3390 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 3391 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3392 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 3393 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 3394 ew32(FCRTV_PCH, hw->fc.refresh_time);
3395
482fed85
BA		 3396 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3397 hw->fc.pause_time);
a4f58f54
BA		 3398 if (ret_val)
3399 return ret_val;
3400 }
bc7f75fa
AK		 3401
3402 return e1000e_set_fc_watermarks(hw);
3403}
3404
3405/**
3406 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3407 * @hw: pointer to the HW structure
3408 *
3409 * Configures the kumeran interface to the PHY to wait the appropriate time
3410 * when polling the PHY, then call the generic setup_copper_link to finish
3411 * configuring the copper link.
3412 **/
3413static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3414{
3415 u32 ctrl;
3416 s32 ret_val;
3417 u16 reg_data;
3418
3419 ctrl = er32(CTRL);
3420 ctrl |= E1000_CTRL_SLU;
3421 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3422 ew32(CTRL, ctrl);
3423
ad68076e
BA		 3424 /*
3425 * Set the mac to wait the maximum time between each iteration
bc7f75fa 3426 * and increase the max iterations when polling the phy;
ad68076e
BA		 3427 * this fixes erroneous timeouts at 10Mbps.
3428 */
07818950 3429 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 3430 if (ret_val)
3431 return ret_val;
07818950
BA		 3432 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3433 &reg_data);
bc7f75fa
AK		 3434 if (ret_val)
3435 return ret_val;
3436 reg_data |= 0x3F;
07818950
BA		 3437 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3438 reg_data);
bc7f75fa
AK		 3439 if (ret_val)
3440 return ret_val;
3441
a4f58f54
BA		 3442 switch (hw->phy.type) {
3443 case e1000_phy_igp_3:
bc7f75fa
AK		 3444 ret_val = e1000e_copper_link_setup_igp(hw);
3445 if (ret_val)
3446 return ret_val;
a4f58f54
BA		 3447 break;
3448 case e1000_phy_bm:
3449 case e1000_phy_82578:
97ac8cae
BA		 3450 ret_val = e1000e_copper_link_setup_m88(hw);
3451 if (ret_val)
3452 return ret_val;
a4f58f54
BA		 3453 break;
3454 case e1000_phy_82577:
d3738bb8 3455 case e1000_phy_82579:
a4f58f54
BA		 3456 ret_val = e1000_copper_link_setup_82577(hw);
3457 if (ret_val)
3458 return ret_val;
3459 break;
3460 case e1000_phy_ife:
482fed85 3461 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
97ac8cae
BA		 3462 if (ret_val)
3463 return ret_val;
3464
3465 reg_data &= ~IFE_PMC_AUTO_MDIX;
3466
3467 switch (hw->phy.mdix) {
3468 case 1:
3469 reg_data &= ~IFE_PMC_FORCE_MDIX;
3470 break;
3471 case 2:
3472 reg_data |= IFE_PMC_FORCE_MDIX;
3473 break;
3474 case 0:
3475 default:
3476 reg_data |= IFE_PMC_AUTO_MDIX;
3477 break;
3478 }
482fed85 3479 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
97ac8cae
BA		 3480 if (ret_val)
3481 return ret_val;
a4f58f54
BA		 3482 break;
3483 default:
3484 break;
97ac8cae 3485 }
bc7f75fa
AK		 3486 return e1000e_setup_copper_link(hw);
3487}
3488
3489/**
3490 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3491 * @hw: pointer to the HW structure
3492 * @speed: pointer to store current link speed
3493 * @duplex: pointer to store the current link duplex
3494 *
ad68076e 3495 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 3496 * information and then calls the Kumeran lock loss workaround for links at
3497 * gigabit speeds.
3498 **/
3499static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3500 u16 *duplex)
3501{
3502 s32 ret_val;
3503
3504 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3505 if (ret_val)
3506 return ret_val;
3507
3508 if ((hw->mac.type == e1000_ich8lan) &&
3509 (hw->phy.type == e1000_phy_igp_3) &&
3510 (*speed == SPEED_1000)) {
3511 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3512 }
3513
3514 return ret_val;
3515}
3516
3517/**
3518 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3519 * @hw: pointer to the HW structure
3520 *
3521 * Work-around for 82566 Kumeran PCS lock loss:
3522 * On link status change (i.e. PCI reset, speed change) and link is up and
3523 * speed is gigabit-
3524 * 0) if workaround is optionally disabled do nothing
3525 * 1) wait 1ms for Kumeran link to come up
3526 * 2) check Kumeran Diagnostic register PCS lock loss bit
3527 * 3) if not set the link is locked (all is good), otherwise...
3528 * 4) reset the PHY
3529 * 5) repeat up to 10 times
3530 * Note: this is only called for IGP3 copper when speed is 1gb.
3531 **/
3532static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3533{
3534 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3535 u32 phy_ctrl;
3536 s32 ret_val;
3537 u16 i, data;
3538 bool link;
3539
3540 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3541 return 0;
3542
ad68076e
BA		 3543 /*
3544 * Make sure link is up before proceeding. If not just return.
bc7f75fa 3545 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 3546 * stability
3547 */
bc7f75fa
AK		 3548 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3549 if (!link)
3550 return 0;
3551
3552 for (i = 0; i < 10; i++) {
3553 /* read once to clear */
3554 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3555 if (ret_val)
3556 return ret_val;
3557 /* and again to get new status */
3558 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3559 if (ret_val)
3560 return ret_val;
3561
3562 /* check for PCS lock */
3563 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3564 return 0;
3565
3566 /* Issue PHY reset */
3567 e1000_phy_hw_reset(hw);
3568 mdelay(5);
3569 }
3570 /* Disable GigE link negotiation */
3571 phy_ctrl = er32(PHY_CTRL);
3572 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3573 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3574 ew32(PHY_CTRL, phy_ctrl);
3575
ad68076e
BA		 3576 /*
3577 * Call gig speed drop workaround on Gig disable before accessing
3578 * any PHY registers
3579 */
bc7f75fa
AK		 3580 e1000e_gig_downshift_workaround_ich8lan(hw);
3581
3582 /* unable to acquire PCS lock */
3583 return -E1000_ERR_PHY;
3584}
3585
3586/**
ad68076e 3587 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 3588 * @hw: pointer to the HW structure
489815ce 3589 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 3590 *
564ea9bb
BA		 3591 * If ICH8, set the current Kumeran workaround state (enabled - true
3592 * /disabled - false).
bc7f75fa
AK		 3593 **/
3594void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3595 bool state)
3596{
3597 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3598
3599 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3600 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3601 return;
3602 }
3603
3604 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3605}
3606
3607/**
3608 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3609 * @hw: pointer to the HW structure
3610 *
3611 * Workaround for 82566 power-down on D3 entry:
3612 * 1) disable gigabit link
3613 * 2) write VR power-down enable
3614 * 3) read it back
3615 * Continue if successful, else issue LCD reset and repeat
3616 **/
3617void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3618{
3619 u32 reg;
3620 u16 data;
3621 u8 retry = 0;
3622
3623 if (hw->phy.type != e1000_phy_igp_3)
3624 return;
3625
3626 /* Try the workaround twice (if needed) */
3627 do {
3628 /* Disable link */
3629 reg = er32(PHY_CTRL);
3630 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3631 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3632 ew32(PHY_CTRL, reg);
3633
ad68076e
BA		 3634 /*
3635 * Call gig speed drop workaround on Gig disable before
3636 * accessing any PHY registers
3637 */
bc7f75fa
AK		 3638 if (hw->mac.type == e1000_ich8lan)
3639 e1000e_gig_downshift_workaround_ich8lan(hw);
3640
3641 /* Write VR power-down enable */
3642 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3643 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3644 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3645
3646 /* Read it back and test */
3647 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3648 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3649 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3650 break;
3651
3652 /* Issue PHY reset and repeat at most one more time */
3653 reg = er32(CTRL);
3654 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3655 retry++;
3656 } while (retry);
3657}
3658
3659/**
3660 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3661 * @hw: pointer to the HW structure
3662 *
3663 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3664 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3665 * 1) Set Kumeran Near-end loopback
3666 * 2) Clear Kumeran Near-end loopback
462d5994 3667 * Should only be called for ICH8[m] devices with any 1G Phy.
bc7f75fa
AK		 3668 **/
3669void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3670{
3671 s32 ret_val;
3672 u16 reg_data;
3673
462d5994 3674 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
bc7f75fa
AK		 3675 return;
3676
3677 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3678 &reg_data);
3679 if (ret_val)
3680 return;
3681 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3682 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3683 reg_data);
3684 if (ret_val)
3685 return;
3686 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3687 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3688 reg_data);
3689}
3690
97ac8cae 3691/**
99730e4c 3692 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
97ac8cae
BA		 3693 * @hw: pointer to the HW structure
3694 *
3695 * During S0 to Sx transition, it is possible the link remains at gig
3696 * instead of negotiating to a lower speed. Before going to Sx, set
c077a906
BA		 3697 * 'Gig Disable' to force link speed negotiation to a lower speed based on
3698 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
3699 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3700 * needs to be written.
97ac8cae 3701 **/
99730e4c 3702void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
97ac8cae
BA		 3703{
3704 u32 phy_ctrl;
8395ae83 3705 s32 ret_val;
97ac8cae 3706
17f085df 3707 phy_ctrl = er32(PHY_CTRL);
c077a906 3708 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
17f085df 3709 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 3710
462d5994
BA		 3711 if (hw->mac.type == e1000_ich8lan)
3712 e1000e_gig_downshift_workaround_ich8lan(hw);
3713
8395ae83 3714 if (hw->mac.type >= e1000_pchlan) {
ce54afd1 3715 e1000_oem_bits_config_ich8lan(hw, false);
03299e46 3716 e1000_phy_hw_reset_ich8lan(hw);
8395ae83
BA		 3717 ret_val = hw->phy.ops.acquire(hw);
3718 if (ret_val)
3719 return;
3720 e1000_write_smbus_addr(hw);
3721 hw->phy.ops.release(hw);
3722 }
97ac8cae
BA		 3723}
3724
99730e4c
BA		 3725/**
3726 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3727 * @hw: pointer to the HW structure
3728 *
3729 * During Sx to S0 transitions on non-managed devices or managed devices
3730 * on which PHY resets are not blocked, if the PHY registers cannot be
3731 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
3732 * the PHY.
3733 **/
3734void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3735{
90b82984
BA		 3736 u16 phy_id1, phy_id2;
3737 s32 ret_val;
99730e4c 3738
90b82984 3739 if ((hw->mac.type != e1000_pch2lan) || e1000_check_reset_block(hw))
99730e4c
BA		 3740 return;
3741
90b82984
BA		 3742 ret_val = hw->phy.ops.acquire(hw);
3743 if (ret_val) {
3744 e_dbg("Failed to acquire PHY semaphore in resume\n");
3745 return;
3746 }
99730e4c 3747
90b82984
BA		 3748 /* Test access to the PHY registers by reading the ID regs */
3749 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3750 if (ret_val)
3751 goto release;
3752 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3753 if (ret_val)
3754 goto release;
99730e4c 3755
90b82984
BA		 3756 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3757 (u32)(phy_id2 & PHY_REVISION_MASK)))
3758 goto release;
99730e4c 3759
90b82984 3760 e1000_toggle_lanphypc_value_ich8lan(hw);
99730e4c 3761
90b82984
BA		 3762 hw->phy.ops.release(hw);
3763 msleep(50);
3764 e1000_phy_hw_reset(hw);
3765 msleep(50);
3766 return;
99730e4c
BA		 3767
3768release:
3769 hw->phy.ops.release(hw);
99730e4c
BA		 3770}
3771
bc7f75fa
AK		 3772/**
3773 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3774 * @hw: pointer to the HW structure
3775 *
3776 * Return the LED back to the default configuration.
3777 **/
3778static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3779{
3780 if (hw->phy.type == e1000_phy_ife)
3781 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3782
3783 ew32(LEDCTL, hw->mac.ledctl_default);
3784 return 0;
3785}
3786
3787/**
489815ce 3788 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 3789 * @hw: pointer to the HW structure
3790 *
489815ce 3791 * Turn on the LEDs.
bc7f75fa
AK		 3792 **/
3793static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3794{
3795 if (hw->phy.type == e1000_phy_ife)
3796 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3797 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3798
3799 ew32(LEDCTL, hw->mac.ledctl_mode2);
3800 return 0;
3801}
3802
3803/**
489815ce 3804 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 3805 * @hw: pointer to the HW structure
3806 *
489815ce 3807 * Turn off the LEDs.
bc7f75fa
AK		 3808 **/
3809static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3810{
3811 if (hw->phy.type == e1000_phy_ife)
3812 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
482fed85
BA		 3813 (IFE_PSCL_PROBE_MODE |
3814 IFE_PSCL_PROBE_LEDS_OFF));
bc7f75fa
AK		 3815
3816 ew32(LEDCTL, hw->mac.ledctl_mode1);
3817 return 0;
3818}
3819
a4f58f54
BA		 3820/**
3821 * e1000_setup_led_pchlan - Configures SW controllable LED
3822 * @hw: pointer to the HW structure
3823 *
3824 * This prepares the SW controllable LED for use.
3825 **/
3826static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3827{
482fed85 3828 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
a4f58f54
BA		 3829}
3830
3831/**
3832 * e1000_cleanup_led_pchlan - Restore the default LED operation
3833 * @hw: pointer to the HW structure
3834 *
3835 * Return the LED back to the default configuration.
3836 **/
3837static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3838{
482fed85 3839 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
a4f58f54
BA		 3840}
3841
3842/**
3843 * e1000_led_on_pchlan - Turn LEDs on
3844 * @hw: pointer to the HW structure
3845 *
3846 * Turn on the LEDs.
3847 **/
3848static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3849{
3850 u16 data = (u16)hw->mac.ledctl_mode2;
3851 u32 i, led;
3852
3853 /*
3854 * If no link, then turn LED on by setting the invert bit
3855 * for each LED that's mode is "link_up" in ledctl_mode2.
3856 */
3857 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3858 for (i = 0; i < 3; i++) {
3859 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3860 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3861 E1000_LEDCTL_MODE_LINK_UP)
3862 continue;
3863 if (led & E1000_PHY_LED0_IVRT)
3864 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3865 else
3866 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3867 }
3868 }
3869
482fed85 3870 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3871}
3872
3873/**
3874 * e1000_led_off_pchlan - Turn LEDs off
3875 * @hw: pointer to the HW structure
3876 *
3877 * Turn off the LEDs.
3878 **/
3879static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3880{
3881 u16 data = (u16)hw->mac.ledctl_mode1;
3882 u32 i, led;
3883
3884 /*
3885 * If no link, then turn LED off by clearing the invert bit
3886 * for each LED that's mode is "link_up" in ledctl_mode1.
3887 */
3888 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3889 for (i = 0; i < 3; i++) {
3890 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3891 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3892 E1000_LEDCTL_MODE_LINK_UP)
3893 continue;
3894 if (led & E1000_PHY_LED0_IVRT)
3895 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3896 else
3897 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3898 }
3899 }
3900
482fed85 3901 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3902}
3903
f4187b56 3904/**
e98cac44 3905 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 3906 * @hw: pointer to the HW structure
3907 *
e98cac44
BA		 3908 * Read appropriate register for the config done bit for completion status
3909 * and configure the PHY through s/w for EEPROM-less parts.
3910 *
3911 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3912 * config done bit, so only an error is logged and continues. If we were
3913 * to return with error, EEPROM-less silicon would not be able to be reset
3914 * or change link.
f4187b56
BA		 3915 **/
3916static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3917{
e98cac44 3918 s32 ret_val = 0;
f4187b56 3919 u32 bank = 0;
e98cac44 3920 u32 status;
f4187b56 3921
e98cac44 3922 e1000e_get_cfg_done(hw);
fc0c7760 3923
e98cac44
BA		 3924 /* Wait for indication from h/w that it has completed basic config */
3925 if (hw->mac.type >= e1000_ich10lan) {
3926 e1000_lan_init_done_ich8lan(hw);
3927 } else {
3928 ret_val = e1000e_get_auto_rd_done(hw);
3929 if (ret_val) {
3930 /*
3931 * When auto config read does not complete, do not
3932 * return with an error. This can happen in situations
3933 * where there is no eeprom and prevents getting link.
3934 */
3935 e_dbg("Auto Read Done did not complete\n");
3936 ret_val = 0;
3937 }
fc0c7760
BA		 3938 }
3939
e98cac44
BA		 3940 /* Clear PHY Reset Asserted bit */
3941 status = er32(STATUS);
3942 if (status & E1000_STATUS_PHYRA)
3943 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3944 else
3945 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 3946
3947 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 3948 if (hw->mac.type <= e1000_ich9lan) {
f4187b56
BA		 3949 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3950 (hw->phy.type == e1000_phy_igp_3)) {
3951 e1000e_phy_init_script_igp3(hw);
3952 }
3953 } else {
3954 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3955 /* Maybe we should do a basic PHY config */
3bb99fe2 3956 e_dbg("EEPROM not present\n");
e98cac44 3957 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 3958 }
3959 }
3960
e98cac44 3961 return ret_val;
f4187b56
BA		 3962}
3963
17f208de
BA		 3964/**
3965 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3966 * @hw: pointer to the HW structure
3967 *
3968 * In the case of a PHY power down to save power, or to turn off link during a
3969 * driver unload, or wake on lan is not enabled, remove the link.
3970 **/
3971static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3972{
3973 /* If the management interface is not enabled, then power down */
3974 if (!(hw->mac.ops.check_mng_mode(hw) ||
3975 hw->phy.ops.check_reset_block(hw)))
3976 e1000_power_down_phy_copper(hw);
17f208de
BA		 3977}
3978
bc7f75fa
AK		 3979/**
3980 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3981 * @hw: pointer to the HW structure
3982 *
3983 * Clears hardware counters specific to the silicon family and calls
3984 * clear_hw_cntrs_generic to clear all general purpose counters.
3985 **/
3986static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3987{
a4f58f54 3988 u16 phy_data;
2b6b168d 3989 s32 ret_val;
bc7f75fa
AK		 3990
3991 e1000e_clear_hw_cntrs_base(hw);
3992
99673d9b
BA		 3993 er32(ALGNERRC);
3994 er32(RXERRC);
3995 er32(TNCRS);
3996 er32(CEXTERR);
3997 er32(TSCTC);
3998 er32(TSCTFC);
bc7f75fa 3999
99673d9b
BA		 4000 er32(MGTPRC);
4001 er32(MGTPDC);
4002 er32(MGTPTC);
bc7f75fa 4003
99673d9b
BA		 4004 er32(IAC);
4005 er32(ICRXOC);
bc7f75fa 4006
a4f58f54
BA		 4007 /* Clear PHY statistics registers */
4008 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 4009 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 4010 (hw->phy.type == e1000_phy_82577)) {
2b6b168d
BA		 4011 ret_val = hw->phy.ops.acquire(hw);
4012 if (ret_val)
4013 return;
4014 ret_val = hw->phy.ops.set_page(hw,
4015 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4016 if (ret_val)
4017 goto release;
4018 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4019 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4020 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4021 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4022 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4023 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4024 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4025 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4026 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4027 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4028 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4029 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4030 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4031 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4032release:
4033 hw->phy.ops.release(hw);
a4f58f54 4034 }
bc7f75fa
AK		 4035}
4036
8ce9d6c7 4037static const struct e1000_mac_operations ich8_mac_ops = {
a4f58f54 4038 .id_led_init = e1000e_id_led_init,
eb7700dc 4039 /* check_mng_mode dependent on mac type */
7d3cabbc 4040 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 4041 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 4042 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4043 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 4044 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 4045 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 4046 /* led_on dependent on mac type */
4047 /* led_off dependent on mac type */
e2de3eb6 4048 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 4049 .reset_hw = e1000_reset_hw_ich8lan,
4050 .init_hw = e1000_init_hw_ich8lan,
4051 .setup_link = e1000_setup_link_ich8lan,
4052 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
a4f58f54 4053 /* id_led_init dependent on mac type */
bc7f75fa
AK		 4054};
4055
8ce9d6c7 4056static const struct e1000_phy_operations ich8_phy_ops = {
94d8186a 4057 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 4058 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 4059 .commit = NULL,
f4187b56 4060 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 4061 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 4062 .read_reg = e1000e_read_phy_reg_igp,
4063 .release = e1000_release_swflag_ich8lan,
4064 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 4065 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4066 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 4067 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 4068};
4069
8ce9d6c7 4070static const struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a
BA		 4071 .acquire = e1000_acquire_nvm_ich8lan,
4072 .read = e1000_read_nvm_ich8lan,
4073 .release = e1000_release_nvm_ich8lan,
4074 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 4075 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 4076 .validate = e1000_validate_nvm_checksum_ich8lan,
4077 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 4078};
4079
8ce9d6c7 4080const struct e1000_info e1000_ich8_info = {
bc7f75fa
AK		 4081 .mac = e1000_ich8lan,
4082 .flags = FLAG_HAS_WOL
97ac8cae 4083 | FLAG_IS_ICH
bc7f75fa
AK		 4084 | FLAG_HAS_CTRLEXT_ON_LOAD
4085 | FLAG_HAS_AMT
4086 | FLAG_HAS_FLASH
4087 | FLAG_APME_IN_WUC,
4088 .pba = 8,
2adc55c9 4089 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 4090 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 4091 .mac_ops = &ich8_mac_ops,
4092 .phy_ops = &ich8_phy_ops,
4093 .nvm_ops = &ich8_nvm_ops,
4094};
4095
8ce9d6c7 4096const struct e1000_info e1000_ich9_info = {
bc7f75fa
AK		 4097 .mac = e1000_ich9lan,
4098 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 4099 | FLAG_IS_ICH
bc7f75fa 4100 | FLAG_HAS_WOL
bc7f75fa
AK		 4101 | FLAG_HAS_CTRLEXT_ON_LOAD
4102 | FLAG_HAS_AMT
bc7f75fa
AK		 4103 | FLAG_HAS_FLASH
4104 | FLAG_APME_IN_WUC,
7f1557e1 4105 .pba = 18,
2adc55c9 4106 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 4107 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 4108 .mac_ops = &ich8_mac_ops,
4109 .phy_ops = &ich8_phy_ops,
4110 .nvm_ops = &ich8_nvm_ops,
4111};
4112
8ce9d6c7 4113const struct e1000_info e1000_ich10_info = {
f4187b56
BA		 4114 .mac = e1000_ich10lan,
4115 .flags = FLAG_HAS_JUMBO_FRAMES
4116 | FLAG_IS_ICH
4117 | FLAG_HAS_WOL
f4187b56
BA		 4118 | FLAG_HAS_CTRLEXT_ON_LOAD
4119 | FLAG_HAS_AMT
f4187b56
BA		 4120 | FLAG_HAS_FLASH
4121 | FLAG_APME_IN_WUC,
7f1557e1 4122 .pba = 18,
2adc55c9 4123 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 4124 .get_variants = e1000_get_variants_ich8lan,
4125 .mac_ops = &ich8_mac_ops,
4126 .phy_ops = &ich8_phy_ops,
4127 .nvm_ops = &ich8_nvm_ops,
4128};
a4f58f54 4129
8ce9d6c7 4130const struct e1000_info e1000_pch_info = {
a4f58f54
BA		 4131 .mac = e1000_pchlan,
4132 .flags = FLAG_IS_ICH
4133 | FLAG_HAS_WOL
a4f58f54
BA		 4134 | FLAG_HAS_CTRLEXT_ON_LOAD
4135 | FLAG_HAS_AMT
4136 | FLAG_HAS_FLASH
4137 | FLAG_HAS_JUMBO_FRAMES
38eb394e 4138 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 4139 | FLAG_APME_IN_WUC,
8c7bbb92 4140 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 4141 .pba = 26,
4142 .max_hw_frame_size = 4096,
4143 .get_variants = e1000_get_variants_ich8lan,
4144 .mac_ops = &ich8_mac_ops,
4145 .phy_ops = &ich8_phy_ops,
4146 .nvm_ops = &ich8_nvm_ops,
4147};
d3738bb8 4148
8ce9d6c7 4149const struct e1000_info e1000_pch2_info = {
d3738bb8
BA		 4150 .mac = e1000_pch2lan,
4151 .flags = FLAG_IS_ICH
4152 | FLAG_HAS_WOL
d3738bb8
BA		 4153 | FLAG_HAS_CTRLEXT_ON_LOAD
4154 | FLAG_HAS_AMT
4155 | FLAG_HAS_FLASH
4156 | FLAG_HAS_JUMBO_FRAMES
4157 | FLAG_APME_IN_WUC,
e52997f9
BA		 4158 .flags2 = FLAG2_HAS_PHY_STATS
4159 | FLAG2_HAS_EEE,
828bac87 4160 .pba = 26,
d3738bb8
BA		 4161 .max_hw_frame_size = DEFAULT_JUMBO,
4162 .get_variants = e1000_get_variants_ich8lan,
4163 .mac_ops = &ich8_mac_ops,
4164 .phy_ops = &ich8_phy_ops,
4165 .nvm_ops = &ich8_nvm_ops,
4166};
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