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e1000e: Fix the max snoop/no-snoop latency for 10M
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
CommitLineData
ae06c70b 1// SPDX-License-Identifier: GPL-2.0
51dce24b 2/* Copyright(c) 1999 - 2018 Intel Corporation. */
bc7f75fa 3
e921eb1a 4/* 82562G 10/100 Network Connection
bc7f75fa
AK		 5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
97ac8cae
BA		 16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
1605927f 18 * 82567V Gigabit Network Connection
97ac8cae
BA		 19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
2f15f9d6 24 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
d3738bb8
BA		 29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
3b70d4f8
DE		 31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
bc7f75fa
AK		 39 */
40
bc7f75fa
AK		 41#include "e1000.h"
42
bc7f75fa
AK		 43/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44/* Offset 04h HSFSTS */
45union ich8_hws_flash_status {
46 struct ich8_hsfsts {
362e20ca
BA		 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
bc7f75fa
AK		 56 } hsf_status;
57 u16 regval;
58};
59
60/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61/* Offset 06h FLCTL */
62union ich8_hws_flash_ctrl {
63 struct ich8_hsflctl {
362e20ca
BA		 64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
bc7f75fa
AK		 69 } hsf_ctrl;
70 u16 regval;
71};
72
73/* ICH Flash Region Access Permissions */
74union ich8_hws_flash_regacc {
75 struct ich8_flracc {
362e20ca
BA		 76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
bc7f75fa
AK		 80 } hsf_flregacc;
81 u16 regval;
82};
83
4a770358
BA		 84/* ICH Flash Protected Region */
85union ich8_flash_protected_range {
86 struct ich8_pr {
e80bd1d1
BA		 87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
4a770358
BA		 93 } range;
94 u32 regval;
95};
96
bc7f75fa
AK		 97static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 99static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
f4187b56
BA		 102static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 u8 *data);
bc7f75fa
AK		 104static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 u16 *data);
106static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 u8 size, u16 *data);
79849ebc
DE		 108static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 u32 *data);
110static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
bc7f75fa 116static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 117static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 125static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 126static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 127static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1f96012d 128static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 129static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 130static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
b3e5bf1f
DE		 132static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
831bd2e6 135static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
605c82ba 136static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
74f350ee 137static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
ea8179a7 138static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
74f350ee 139static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
bc7f75fa
AK		 140
141static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142{
143 return readw(hw->flash_address + reg);
144}
145
146static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147{
148 return readl(hw->flash_address + reg);
149}
150
151static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152{
153 writew(val, hw->flash_address + reg);
154}
155
156static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157{
158 writel(val, hw->flash_address + reg);
159}
160
161#define er16flash(reg) __er16flash(hw, (reg))
162#define er32flash(reg) __er32flash(hw, (reg))
0e15df49
BA		 163#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
bc7f75fa 165
cb17aab9
BA		 166/**
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
169 *
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
173 *
174 * Assumes the sw/fw/hw semaphore is already acquired.
175 **/
176static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
99730e4c 177{
a52359b5
BA		 178 u16 phy_reg = 0;
179 u32 phy_id = 0;
2c982624 180 s32 ret_val = 0;
a52359b5 181 u16 retry_count;
16b095a4 182 u32 mac_reg = 0;
a52359b5
BA		 183
184 for (retry_count = 0; retry_count < 2; retry_count++) {
c2ade1a4 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
a52359b5
BA		 186 if (ret_val || (phy_reg == 0xFFFF))
187 continue;
188 phy_id = (u32)(phy_reg << 16);
189
c2ade1a4 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
a52359b5
BA		 191 if (ret_val || (phy_reg == 0xFFFF)) {
192 phy_id = 0;
193 continue;
194 }
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 break;
197 }
cb17aab9
BA		 198
199 if (hw->phy.id) {
200 if (hw->phy.id == phy_id)
16b095a4 201 goto out;
a52359b5
BA		 202 } else if (phy_id) {
203 hw->phy.id = phy_id;
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
16b095a4 205 goto out;
cb17aab9
BA		 206 }
207
e921eb1a 208 /* In case the PHY needs to be in mdio slow mode,
a52359b5
BA		 209 * set slow mode and try to get the PHY id again.
210 */
2c982624
DE		 211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
217 }
a52359b5 218
16b095a4
BA		 219 if (ret_val)
220 return false;
221out:
c8744f44 222 if (hw->mac.type >= e1000_pch_lpt) {
beee8072
YL		 223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
16b095a4 229
beee8072
YL		 230 /* Unforce SMBus mode in MAC */
231 mac_reg = er32(CTRL_EXT);
232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 ew32(CTRL_EXT, mac_reg);
234 }
16b095a4
BA		 235 }
236
237 return true;
cb17aab9
BA		 238}
239
74f350ee
DE		 240/**
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
243 *
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
246 **/
247static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248{
249 u32 mac_reg;
250
251 /* Set Phy Config Counter to 50msec */
252 mac_reg = er32(FEXTNVM3);
253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 ew32(FEXTNVM3, mac_reg);
256
257 /* Toggle LANPHYPC Value bit */
258 mac_reg = er32(CTRL);
259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261 ew32(CTRL, mac_reg);
262 e1e_flush();
263 usleep_range(10, 20);
264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267
268 if (hw->mac.type < e1000_pch_lpt) {
269 msleep(50);
270 } else {
271 u16 count = 20;
272
273 do {
ab6973ae 274 usleep_range(5000, 6000);
74f350ee
DE		 275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276
277 msleep(30);
278 }
279}
280
cb17aab9
BA		 281/**
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
284 *
285 * Workarounds/flow necessary for PHY initialization during driver load
286 * and resume paths.
287 **/
288static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289{
f7235ef6 290 struct e1000_adapter *adapter = hw->adapter;
cb17aab9
BA		 291 u32 mac_reg, fwsm = er32(FWSM);
292 s32 ret_val;
293
6e928b72
BA		 294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
296 */
297 e1000_gate_hw_phy_config_ich8lan(hw, true);
298
74f350ee
DE		 299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
301 */
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
0c80cdbf 303 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
1050242f 304 if (ret_val)
0c80cdbf 305 e_warn("Failed to disable ULP\n");
74f350ee 306
cb17aab9
BA		 307 ret_val = hw->phy.ops.acquire(hw);
308 if (ret_val) {
309 e_dbg("Failed to initialize PHY flow\n");
6e928b72 310 goto out;
cb17aab9
BA		 311 }
312
e921eb1a 313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
cb17aab9
BA		 314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
316 */
317 switch (hw->mac.type) {
2fbe4526 318 case e1000_pch_lpt:
79849ebc 319 case e1000_pch_spt:
c8744f44 320 case e1000_pch_cnp:
fb776f5d 321 case e1000_pch_tgp:
59e46688 322 case e1000_pch_adp:
cc23f4f0 323 case e1000_pch_mtp:
2fbe4526
BA		 324 if (e1000_phy_is_accessible_pchlan(hw))
325 break;
326
e921eb1a 327 /* Before toggling LANPHYPC, see if PHY is accessible by
2fbe4526
BA		 328 * forcing MAC to SMBus mode first.
329 */
330 mac_reg = er32(CTRL_EXT);
331 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
332 ew32(CTRL_EXT, mac_reg);
333
16b095a4
BA		 334 /* Wait 50 milliseconds for MAC to finish any retries
335 * that it might be trying to perform from previous
336 * attempts to acknowledge any phy read requests.
337 */
338 msleep(50);
339
5463fce6 340 fallthrough;
cb17aab9 341 case e1000_pch2lan:
16b095a4 342 if (e1000_phy_is_accessible_pchlan(hw))
cb17aab9
BA		 343 break;
344
5463fce6 345 fallthrough;
cb17aab9
BA		 346 case e1000_pchlan:
347 if ((hw->mac.type == e1000_pchlan) &&
348 (fwsm & E1000_ICH_FWSM_FW_VALID))
349 break;
350
351 if (hw->phy.ops.check_reset_block(hw)) {
352 e_dbg("Required LANPHYPC toggle blocked by ME\n");
16b095a4 353 ret_val = -E1000_ERR_PHY;
cb17aab9
BA		 354 break;
355 }
356
cb17aab9 357 /* Toggle LANPHYPC Value bit */
74f350ee
DE		 358 e1000_toggle_lanphypc_pch_lpt(hw);
359 if (hw->mac.type >= e1000_pch_lpt) {
16b095a4
BA		 360 if (e1000_phy_is_accessible_pchlan(hw))
361 break;
362
363 /* Toggling LANPHYPC brings the PHY out of SMBus mode
364 * so ensure that the MAC is also out of SMBus mode
365 */
366 mac_reg = er32(CTRL_EXT);
367 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
368 ew32(CTRL_EXT, mac_reg);
369
370 if (e1000_phy_is_accessible_pchlan(hw))
371 break;
372
373 ret_val = -E1000_ERR_PHY;
2fbe4526 374 }
cb17aab9
BA		 375 break;
376 default:
377 break;
378 }
379
380 hw->phy.ops.release(hw);
16b095a4 381 if (!ret_val) {
f7235ef6
DE		 382
383 /* Check to see if able to reset PHY. Print error if not */
384 if (hw->phy.ops.check_reset_block(hw)) {
385 e_err("Reset blocked by ME\n");
386 goto out;
387 }
388
16b095a4
BA		 389 /* Reset the PHY before any access to it. Doing so, ensures
390 * that the PHY is in a known good state before we read/write
391 * PHY registers. The generic reset is sufficient here,
392 * because we haven't determined the PHY type yet.
393 */
394 ret_val = e1000e_phy_hw_reset_generic(hw);
f7235ef6
DE		 395 if (ret_val)
396 goto out;
397
398 /* On a successful reset, possibly need to wait for the PHY
399 * to quiesce to an accessible state before returning control
400 * to the calling function. If the PHY does not quiesce, then
401 * return E1000E_BLK_PHY_RESET, as this is the condition that
402 * the PHY is in.
403 */
404 ret_val = hw->phy.ops.check_reset_block(hw);
405 if (ret_val)
406 e_err("ME blocked access to PHY after reset\n");
16b095a4 407 }
cb17aab9 408
6e928b72 409out:
cb17aab9
BA		 410 /* Ungate automatic PHY configuration on non-managed 82579 */
411 if ((hw->mac.type == e1000_pch2lan) &&
412 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
ab6973ae 413 usleep_range(10000, 11000);
cb17aab9
BA		 414 e1000_gate_hw_phy_config_ich8lan(hw, false);
415 }
416
417 return ret_val;
99730e4c
BA		 418}
419
a4f58f54
BA		 420/**
421 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
422 * @hw: pointer to the HW structure
423 *
424 * Initialize family-specific PHY parameters and function pointers.
425 **/
426static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
427{
428 struct e1000_phy_info *phy = &hw->phy;
70806a7f 429 s32 ret_val;
a4f58f54 430
e80bd1d1
BA		 431 phy->addr = 1;
432 phy->reset_delay_us = 100;
433
434 phy->ops.set_page = e1000_set_page_igp;
435 phy->ops.read_reg = e1000_read_phy_reg_hv;
436 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
437 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
438 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
439 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
440 phy->ops.write_reg = e1000_write_phy_reg_hv;
441 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
442 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
443 phy->ops.power_up = e1000_power_up_phy_copper;
444 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
445 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
a4f58f54 446
cb17aab9 447 phy->id = e1000_phy_unknown;
627c8a04 448
cb17aab9
BA		 449 ret_val = e1000_init_phy_workarounds_pchlan(hw);
450 if (ret_val)
451 return ret_val;
605c82ba 452
cb17aab9
BA		 453 if (phy->id == e1000_phy_unknown)
454 switch (hw->mac.type) {
455 default:
456 ret_val = e1000e_get_phy_id(hw);
457 if (ret_val)
458 return ret_val;
459 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
460 break;
5463fce6 461 fallthrough;
cb17aab9 462 case e1000_pch2lan:
2fbe4526 463 case e1000_pch_lpt:
79849ebc 464 case e1000_pch_spt:
c8744f44 465 case e1000_pch_cnp:
fb776f5d 466 case e1000_pch_tgp:
59e46688 467 case e1000_pch_adp:
cc23f4f0 468 case e1000_pch_mtp:
e921eb1a 469 /* In case the PHY needs to be in mdio slow mode,
cb17aab9
BA		 470 * set slow mode and try to get the PHY id again.
471 */
472 ret_val = e1000_set_mdio_slow_mode_hv(hw);
473 if (ret_val)
474 return ret_val;
475 ret_val = e1000e_get_phy_id(hw);
476 if (ret_val)
477 return ret_val;
664dc878 478 break;
cb17aab9 479 }
a4f58f54
BA		 480 phy->type = e1000e_get_phy_type_from_id(phy->id);
481
0be84010
BA		 482 switch (phy->type) {
483 case e1000_phy_82577:
d3738bb8 484 case e1000_phy_82579:
2fbe4526 485 case e1000_phy_i217:
a4f58f54
BA		 486 phy->ops.check_polarity = e1000_check_polarity_82577;
487 phy->ops.force_speed_duplex =
6cc7aaed 488 e1000_phy_force_speed_duplex_82577;
0be84010 489 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 490 phy->ops.get_info = e1000_get_phy_info_82577;
491 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 492 break;
0be84010
BA		 493 case e1000_phy_82578:
494 phy->ops.check_polarity = e1000_check_polarity_m88;
495 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
496 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
497 phy->ops.get_info = e1000e_get_phy_info_m88;
498 break;
499 default:
500 ret_val = -E1000_ERR_PHY;
501 break;
a4f58f54
BA		 502 }
503
504 return ret_val;
505}
506
bc7f75fa
AK		 507/**
508 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
509 * @hw: pointer to the HW structure
510 *
511 * Initialize family-specific PHY parameters and function pointers.
512 **/
513static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
514{
515 struct e1000_phy_info *phy = &hw->phy;
516 s32 ret_val;
517 u16 i = 0;
518
e80bd1d1
BA		 519 phy->addr = 1;
520 phy->reset_delay_us = 100;
bc7f75fa 521
e80bd1d1
BA		 522 phy->ops.power_up = e1000_power_up_phy_copper;
523 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
17f208de 524
e921eb1a 525 /* We may need to do this twice - once for IGP and if that fails,
97ac8cae
BA		 526 * we'll set BM func pointers and try again
527 */
528 ret_val = e1000e_determine_phy_address(hw);
529 if (ret_val) {
94d8186a 530 phy->ops.write_reg = e1000e_write_phy_reg_bm;
e80bd1d1 531 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 532 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 533 if (ret_val) {
534 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 535 return ret_val;
9b71b419 536 }
97ac8cae
BA		 537 }
538
bc7f75fa
AK		 539 phy->id = 0;
540 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
541 (i++ < 100)) {
ab6973ae 542 usleep_range(1000, 1100);
bc7f75fa
AK		 543 ret_val = e1000e_get_phy_id(hw);
544 if (ret_val)
545 return ret_val;
546 }
547
548 /* Verify phy id */
549 switch (phy->id) {
550 case IGP03E1000_E_PHY_ID:
551 phy->type = e1000_phy_igp_3;
552 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 553 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
554 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 555 phy->ops.get_info = e1000e_get_phy_info_igp;
556 phy->ops.check_polarity = e1000_check_polarity_igp;
557 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 558 break;
559 case IFE_E_PHY_ID:
560 case IFE_PLUS_E_PHY_ID:
561 case IFE_C_E_PHY_ID:
562 phy->type = e1000_phy_ife;
563 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 564 phy->ops.get_info = e1000_get_phy_info_ife;
565 phy->ops.check_polarity = e1000_check_polarity_ife;
566 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 567 break;
97ac8cae
BA		 568 case BME1000_E_PHY_ID:
569 phy->type = e1000_phy_bm;
570 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 571 phy->ops.read_reg = e1000e_read_phy_reg_bm;
572 phy->ops.write_reg = e1000e_write_phy_reg_bm;
573 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 574 phy->ops.get_info = e1000e_get_phy_info_m88;
575 phy->ops.check_polarity = e1000_check_polarity_m88;
576 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 577 break;
bc7f75fa
AK		 578 default:
579 return -E1000_ERR_PHY;
bc7f75fa
AK		 580 }
581
582 return 0;
583}
584
585/**
586 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
587 * @hw: pointer to the HW structure
588 *
589 * Initialize family-specific NVM parameters and function
590 * pointers.
591 **/
592static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
593{
594 struct e1000_nvm_info *nvm = &hw->nvm;
595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 596 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa 597 u16 i;
79849ebc 598 u32 nvm_size;
bc7f75fa 599
bc7f75fa 600 nvm->type = e1000_nvm_flash_sw;
9d17ce49 601
c8744f44 602 if (hw->mac.type >= e1000_pch_spt) {
9d17ce49
YL		 603 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
604 * STRAP register. This is because in SPT the GbE Flash region
605 * is no longer accessed through the flash registers. Instead,
606 * the mechanism has changed, and the Flash region access
607 * registers are now implemented in GbE memory space.
608 */
79849ebc
DE		 609 nvm->flash_base_addr = 0;
610 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
611 * NVM_SIZE_MULTIPLIER;
612 nvm->flash_bank_size = nvm_size / 2;
613 /* Adjust to word count */
614 nvm->flash_bank_size /= sizeof(u16);
615 /* Set the base address for flash register access */
616 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
617 } else {
9d17ce49 618 /* Can't read flash registers if register set isn't mapped. */
79849ebc
DE		 619 if (!hw->flash_address) {
620 e_dbg("ERROR: Flash registers not mapped\n");
621 return -E1000_ERR_CONFIG;
622 }
bc7f75fa 623
79849ebc 624 gfpreg = er32flash(ICH_FLASH_GFPREG);
bc7f75fa 625
79849ebc
DE		 626 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
627 * Add 1 to sector_end_addr since this sector is included in
628 * the overall size.
629 */
630 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
631 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
bc7f75fa 632
79849ebc
DE		 633 /* flash_base_addr is byte-aligned */
634 nvm->flash_base_addr = sector_base_addr
635 << FLASH_SECTOR_ADDR_SHIFT;
bc7f75fa 636
79849ebc
DE		 637 /* find total size of the NVM, then cut in half since the total
638 * size represents two separate NVM banks.
639 */
640 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
641 << FLASH_SECTOR_ADDR_SHIFT);
642 nvm->flash_bank_size /= 2;
643 /* Adjust to word count */
644 nvm->flash_bank_size /= sizeof(u16);
645 }
bc7f75fa
AK		 646
647 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
648
649 /* Clear shadow ram */
650 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 651 dev_spec->shadow_ram[i].modified = false;
e80bd1d1 652 dev_spec->shadow_ram[i].value = 0xFFFF;
bc7f75fa
AK		 653 }
654
655 return 0;
656}
657
658/**
659 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
660 * @hw: pointer to the HW structure
661 *
662 * Initialize family-specific MAC parameters and function
663 * pointers.
664 **/
ec34c170 665static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
bc7f75fa 666{
bc7f75fa
AK		 667 struct e1000_mac_info *mac = &hw->mac;
668
669 /* Set media type function pointer */
318a94d6 670 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 671
672 /* Set mta register count */
673 mac->mta_reg_count = 32;
674 /* Set rar entry count */
675 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
676 if (mac->type == e1000_ich8lan)
677 mac->rar_entry_count--;
a65a4a0d
BA		 678 /* FWSM register */
679 mac->has_fwsm = true;
680 /* ARC subsystem not supported */
681 mac->arc_subsystem_valid = false;
f464ba87
BA		 682 /* Adaptive IFS supported */
683 mac->adaptive_ifs = true;
bc7f75fa 684
2fbe4526 685 /* LED and other operations */
a4f58f54
BA		 686 switch (mac->type) {
687 case e1000_ich8lan:
688 case e1000_ich9lan:
689 case e1000_ich10lan:
eb7700dc
BA		 690 /* check management mode */
691 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54 692 /* ID LED init */
d1964eb1 693 mac->ops.id_led_init = e1000e_id_led_init_generic;
dbf80dcb
BA		 694 /* blink LED */
695 mac->ops.blink_led = e1000e_blink_led_generic;
a4f58f54
BA		 696 /* setup LED */
697 mac->ops.setup_led = e1000e_setup_led_generic;
698 /* cleanup LED */
699 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
700 /* turn on/off LED */
701 mac->ops.led_on = e1000_led_on_ich8lan;
702 mac->ops.led_off = e1000_led_off_ich8lan;
703 break;
d3738bb8 704 case e1000_pch2lan:
69e1e019
BA		 705 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
706 mac->ops.rar_set = e1000_rar_set_pch2lan;
5463fce6 707 fallthrough;
2fbe4526 708 case e1000_pch_lpt:
79849ebc 709 case e1000_pch_spt:
c8744f44 710 case e1000_pch_cnp:
fb776f5d 711 case e1000_pch_tgp:
59e46688 712 case e1000_pch_adp:
cc23f4f0 713 case e1000_pch_mtp:
69e1e019 714 case e1000_pchlan:
eb7700dc
BA		 715 /* check management mode */
716 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 717 /* ID LED init */
718 mac->ops.id_led_init = e1000_id_led_init_pchlan;
719 /* setup LED */
720 mac->ops.setup_led = e1000_setup_led_pchlan;
721 /* cleanup LED */
722 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
723 /* turn on/off LED */
724 mac->ops.led_on = e1000_led_on_pchlan;
725 mac->ops.led_off = e1000_led_off_pchlan;
726 break;
727 default:
728 break;
729 }
730
c8744f44 731 if (mac->type >= e1000_pch_lpt) {
2fbe4526
BA		 732 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
733 mac->ops.rar_set = e1000_rar_set_pch_lpt;
ea8179a7
BA		 734 mac->ops.setup_physical_interface =
735 e1000_setup_copper_link_pch_lpt;
b3e5bf1f 736 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
2fbe4526
BA		 737 }
738
bc7f75fa
AK		 739 /* Enable PCS Lock-loss workaround for ICH8 */
740 if (mac->type == e1000_ich8lan)
564ea9bb 741 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa
AK		 742
743 return 0;
744}
745
4ddc48a9
BA		 746/**
747 * __e1000_access_emi_reg_locked - Read/write EMI register
748 * @hw: pointer to the HW structure
b50f7bca 749 * @address: EMI address to program
4ddc48a9
BA		 750 * @data: pointer to value to read/write from/to the EMI address
751 * @read: boolean flag to indicate read or write
752 *
753 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
754 **/
755static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
756 u16 *data, bool read)
757{
70806a7f 758 s32 ret_val;
4ddc48a9
BA		 759
760 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
761 if (ret_val)
762 return ret_val;
763
764 if (read)
765 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
766 else
767 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
768
769 return ret_val;
770}
771
772/**
773 * e1000_read_emi_reg_locked - Read Extended Management Interface register
774 * @hw: pointer to the HW structure
775 * @addr: EMI address to program
776 * @data: value to be read from the EMI address
777 *
778 * Assumes the SW/FW/HW Semaphore is already acquired.
779 **/
203e4151 780s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
4ddc48a9
BA		 781{
782 return __e1000_access_emi_reg_locked(hw, addr, data, true);
783}
784
785/**
786 * e1000_write_emi_reg_locked - Write Extended Management Interface register
787 * @hw: pointer to the HW structure
788 * @addr: EMI address to program
789 * @data: value to be written to the EMI address
790 *
791 * Assumes the SW/FW/HW Semaphore is already acquired.
792 **/
d495bcb8 793s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
4ddc48a9
BA		 794{
795 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
796}
797
e52997f9
BA		 798/**
799 * e1000_set_eee_pchlan - Enable/disable EEE support
800 * @hw: pointer to the HW structure
801 *
3d4d5755
BA		 802 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
803 * the link and the EEE capabilities of the link partner. The LPI Control
804 * register bits will remain set only if/when link is up.
a03206ed
DE		 805 *
806 * EEE LPI must not be asserted earlier than one second after link is up.
807 * On 82579, EEE LPI should not be enabled until such time otherwise there
808 * can be link issues with some switches. Other devices can have EEE LPI
809 * enabled immediately upon link up since they have a timer in hardware which
810 * prevents LPI from being asserted too early.
e52997f9 811 **/
a03206ed 812s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
e52997f9 813{
2fbe4526 814 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3d4d5755 815 s32 ret_val;
d495bcb8 816 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
e52997f9 817
d495bcb8
BA		 818 switch (hw->phy.type) {
819 case e1000_phy_82579:
820 lpa = I82579_EEE_LP_ABILITY;
821 pcs_status = I82579_EEE_PCS_STATUS;
822 adv_addr = I82579_EEE_ADVERTISEMENT;
823 break;
824 case e1000_phy_i217:
825 lpa = I217_EEE_LP_ABILITY;
826 pcs_status = I217_EEE_PCS_STATUS;
827 adv_addr = I217_EEE_ADVERTISEMENT;
828 break;
829 default:
5015e53a 830 return 0;
d495bcb8 831 }
e52997f9 832
3d4d5755 833 ret_val = hw->phy.ops.acquire(hw);
e52997f9 834 if (ret_val)
5015e53a 835 return ret_val;
e52997f9 836
3d4d5755 837 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
2fbe4526 838 if (ret_val)
3d4d5755
BA		 839 goto release;
840
841 /* Clear bits that enable EEE in various speeds */
842 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
843
844 /* Enable EEE if not disabled by user */
845 if (!dev_spec->eee_disable) {
2fbe4526 846 /* Save off link partner's EEE ability */
3d4d5755 847 ret_val = e1000_read_emi_reg_locked(hw, lpa,
4ddc48a9 848 &dev_spec->eee_lp_ability);
2fbe4526
BA		 849 if (ret_val)
850 goto release;
2fbe4526 851
d495bcb8
BA		 852 /* Read EEE advertisement */
853 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
854 if (ret_val)
855 goto release;
856
3d4d5755 857 /* Enable EEE only for speeds in which the link partner is
d495bcb8 858 * EEE capable and for which we advertise EEE.
2fbe4526 859 */
d495bcb8 860 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
3d4d5755
BA		 861 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
862
d495bcb8 863 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
c2ade1a4
BA		 864 e1e_rphy_locked(hw, MII_LPA, &data);
865 if (data & LPA_100FULL)
3d4d5755
BA		 866 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
867 else
868 /* EEE is not supported in 100Half, so ignore
869 * partner's EEE in 100 ability if full-duplex
870 * is not advertised.
871 */
872 dev_spec->eee_lp_ability &=
873 ~I82579_EEE_100_SUPPORTED;
874 }
2fbe4526
BA		 875 }
876
7142a55c
DE		 877 if (hw->phy.type == e1000_phy_82579) {
878 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
879 &data);
880 if (ret_val)
881 goto release;
882
883 data &= ~I82579_LPI_100_PLL_SHUT;
884 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
885 data);
886 }
887
d495bcb8
BA		 888 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
889 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
890 if (ret_val)
891 goto release;
892
3d4d5755
BA		 893 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
894release:
895 hw->phy.ops.release(hw);
896
897 return ret_val;
e52997f9
BA		 898}
899
e08f626b
BA		 900/**
901 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
902 * @hw: pointer to the HW structure
903 * @link: link up bool flag
904 *
905 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
906 * preventing further DMA write requests. Workaround the issue by disabling
907 * the de-assertion of the clock request when in 1Gpbs mode.
e0236ad9
BA		 908 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
909 * speeds in order to avoid Tx hangs.
e08f626b
BA		 910 **/
911static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
912{
913 u32 fextnvm6 = er32(FEXTNVM6);
e0236ad9 914 u32 status = er32(STATUS);
e08f626b 915 s32 ret_val = 0;
e0236ad9 916 u16 reg;
e08f626b 917
e0236ad9 918 if (link && (status & E1000_STATUS_SPEED_1000)) {
e08f626b
BA		 919 ret_val = hw->phy.ops.acquire(hw);
920 if (ret_val)
921 return ret_val;
922
923 ret_val =
924 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 925 &reg);
e08f626b
BA		 926 if (ret_val)
927 goto release;
928
929 ret_val =
930 e1000e_write_kmrn_reg_locked(hw,
931 E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 932 reg &
e08f626b
BA		 933 ~E1000_KMRNCTRLSTA_K1_ENABLE);
934 if (ret_val)
935 goto release;
936
937 usleep_range(10, 20);
938
939 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
940
941 ret_val =
942 e1000e_write_kmrn_reg_locked(hw,
943 E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 944 reg);
e08f626b
BA		 945release:
946 hw->phy.ops.release(hw);
947 } else {
948 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
e0236ad9
BA		 949 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
950
79849ebc
DE		 951 if ((hw->phy.revision > 5) || !link ||
952 ((status & E1000_STATUS_SPEED_100) &&
953 (status & E1000_STATUS_FD)))
e0236ad9
BA		 954 goto update_fextnvm6;
955
956 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
957 if (ret_val)
958 return ret_val;
959
960 /* Clear link status transmit timeout */
961 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
962
963 if (status & E1000_STATUS_SPEED_100) {
964 /* Set inband Tx timeout to 5x10us for 100Half */
965 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
966
967 /* Do not extend the K1 entry latency for 100Half */
968 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
969 } else {
970 /* Set inband Tx timeout to 50x10us for 10Full/Half */
971 reg |= 50 <<
972 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
973
974 /* Extend the K1 entry latency for 10 Mbps */
975 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
976 }
977
978 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
979 if (ret_val)
980 return ret_val;
981
982update_fextnvm6:
983 ew32(FEXTNVM6, fextnvm6);
e08f626b
BA		 984 }
985
986 return ret_val;
987}
988
cf8fb73c
BA		 989/**
990 * e1000_platform_pm_pch_lpt - Set platform power management values
991 * @hw: pointer to the HW structure
992 * @link: bool indicating link status
993 *
994 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
995 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
996 * when link is up (which must not exceed the maximum latency supported
997 * by the platform), otherwise specify there is no LTR requirement.
998 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
999 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1000 * Capability register set, on this device LTR is set by writing the
1001 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1002 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1003 * message to the PMC.
1004 **/
1005static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1006{
1007 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1008 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
eb486ba6
SN		 1009 u16 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1010 u16 lat_enc_d = 0; /* latency decoded */
cf8fb73c
BA		 1011 u16 lat_enc = 0; /* latency encoded */
1012
1013 if (link) {
1014 u16 speed, duplex, scale = 0;
1015 u16 max_snoop, max_nosnoop;
1016 u16 max_ltr_enc; /* max LTR latency encoded */
30544af5 1017 u64 value;
cf8fb73c
BA		 1018 u32 rxa;
1019
1020 if (!hw->adapter->max_frame_size) {
1021 e_dbg("max_frame_size not set.\n");
1022 return -E1000_ERR_CONFIG;
1023 }
1024
1025 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1026 if (!speed) {
1027 e_dbg("Speed not set.\n");
1028 return -E1000_ERR_CONFIG;
1029 }
1030
1031 /* Rx Packet Buffer Allocation size (KB) */
1032 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1033
1034 /* Determine the maximum latency tolerated by the device.
1035 *
1036 * Per the PCIe spec, the tolerated latencies are encoded as
1037 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1038 * a 10-bit value (0-1023) to provide a range from 1 ns to
1039 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1040 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1041 */
bfc9473b
YL		 1042 rxa *= 512;
1043 value = (rxa > hw->adapter->max_frame_size) ?
1044 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1045 0;
cf8fb73c 1046
cf8fb73c
BA		 1047 while (value > PCI_LTR_VALUE_MASK) {
1048 scale++;
18dd2392 1049 value = DIV_ROUND_UP(value, BIT(5));
cf8fb73c
BA		 1050 }
1051 if (scale > E1000_LTRV_SCALE_MAX) {
1052 e_dbg("Invalid LTR latency scale %d\n", scale);
1053 return -E1000_ERR_CONFIG;
1054 }
1055 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1056
1057 /* Determine the maximum latency tolerated by the platform */
1058 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1059 &max_snoop);
1060 pci_read_config_word(hw->adapter->pdev,
1061 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1062 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1063
eb486ba6
SN		 1064 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1065 (1U << (E1000_LTRV_SCALE_FACTOR *
1066 ((lat_enc & E1000_LTRV_SCALE_MASK)
1067 >> E1000_LTRV_SCALE_SHIFT)));
1068
1069 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1070 (1U << (E1000_LTRV_SCALE_FACTOR *
1071 ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1072 >> E1000_LTRV_SCALE_SHIFT)));
1073
1074 if (lat_enc_d > max_ltr_enc_d)
cf8fb73c
BA		 1075 lat_enc = max_ltr_enc;
1076 }
1077
1078 /* Set Snoop and No-Snoop latencies the same */
1079 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1080 ew32(LTRV, reg);
1081
1082 return 0;
1083}
1084
74f350ee
DE		 1085/**
1086 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1087 * @hw: pointer to the HW structure
1088 * @to_sx: boolean indicating a system power state transition to Sx
1089 *
1090 * When link is down, configure ULP mode to significantly reduce the power
1091 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1092 * ME firmware to start the ULP configuration. If not on an ME enabled
1093 * system, configure the ULP mode by software.
1094 */
1095s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1096{
1097 u32 mac_reg;
1098 s32 ret_val = 0;
1099 u16 phy_reg;
6607c99e 1100 u16 oem_reg = 0;
74f350ee
DE		 1101
1102 if ((hw->mac.type < e1000_pch_lpt) ||
1103 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1104 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1105 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1106 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1107 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1108 return 0;
1109
1110 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1111 /* Request ME configure ULP mode in the PHY */
1112 mac_reg = er32(H2ME);
1113 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1114 ew32(H2ME, mac_reg);
1115
1116 goto out;
1117 }
1118
1119 if (!to_sx) {
1120 int i = 0;
1121
1122 /* Poll up to 5 seconds for Cable Disconnected indication */
1123 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1124 /* Bail if link is re-acquired */
1125 if (er32(STATUS) & E1000_STATUS_LU)
1126 return -E1000_ERR_PHY;
1127
1128 if (i++ == 100)
1129 break;
1130
1131 msleep(50);
1132 }
1133 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1134 (er32(FEXT) &
1135 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1136 }
1137
1138 ret_val = hw->phy.ops.acquire(hw);
1139 if (ret_val)
1140 goto out;
1141
6607c99e
YL		 1142 /* Force SMBus mode in PHY */
1143 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1144 if (ret_val)
1145 goto release;
1146 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1147 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1148
1149 /* Force SMBus mode in MAC */
1150 mac_reg = er32(CTRL_EXT);
1151 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1152 ew32(CTRL_EXT, mac_reg);
1153
79849ebc
DE		 1154 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1155 * LPLU and disable Gig speed when entering ULP
1156 */
1157 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1158 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
6607c99e 1159 &oem_reg);
79849ebc
DE		 1160 if (ret_val)
1161 goto release;
6607c99e
YL		 1162
1163 phy_reg = oem_reg;
79849ebc 1164 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
6607c99e 1165
79849ebc
DE		 1166 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1167 phy_reg);
6607c99e 1168
79849ebc
DE		 1169 if (ret_val)
1170 goto release;
1171 }
1172
74f350ee
DE		 1173 /* Set Inband ULP Exit, Reset to SMBus mode and
1174 * Disable SMBus Release on PERST# in PHY
1175 */
1176 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1177 if (ret_val)
1178 goto release;
1179 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1180 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1181 if (to_sx) {
1182 if (er32(WUFC) & E1000_WUFC_LNKC)
1183 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
6607c99e
YL		 1184 else
1185 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
74f350ee
DE		 1186
1187 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
6607c99e 1188 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
74f350ee
DE		 1189 } else {
1190 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
6607c99e
YL		 1191 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1192 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
74f350ee
DE		 1193 }
1194 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1195
1196 /* Set Disable SMBus Release on PERST# in MAC */
1197 mac_reg = er32(FEXTNVM7);
1198 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1199 ew32(FEXTNVM7, mac_reg);
1200
1201 /* Commit ULP changes in PHY by starting auto ULP configuration */
1202 phy_reg |= I218_ULP_CONFIG1_START;
1203 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
6607c99e
YL		 1204
1205 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1206 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1207 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1208 oem_reg);
1209 if (ret_val)
1210 goto release;
1211 }
1212
74f350ee
DE		 1213release:
1214 hw->phy.ops.release(hw);
1215out:
1216 if (ret_val)
1217 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1218 else
1219 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1220
1221 return ret_val;
1222}
1223
1224/**
1225 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1226 * @hw: pointer to the HW structure
1227 * @force: boolean indicating whether or not to force disabling ULP
1228 *
1229 * Un-configure ULP mode when link is up, the system is transitioned from
1230 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1231 * system, poll for an indication from ME that ULP has been un-configured.
1232 * If not on an ME enabled system, un-configure the ULP mode by software.
1233 *
1234 * During nominal operation, this function is called when link is acquired
1235 * to disable ULP mode (force=false); otherwise, for example when unloading
1236 * the driver or during Sx->S0 transitions, this is called with force=true
1237 * to forcibly disable ULP.
1238 */
1239static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1240{
1241 s32 ret_val = 0;
1242 u32 mac_reg;
1243 u16 phy_reg;
1244 int i = 0;
1245
1246 if ((hw->mac.type < e1000_pch_lpt) ||
1247 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1248 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1249 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1250 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1251 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1252 return 0;
1253
1254 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
3cf31b1a
ML		 1255 struct e1000_adapter *adapter = hw->adapter;
1256 bool firmware_bug = false;
1257
74f350ee
DE		 1258 if (force) {
1259 /* Request ME un-configure ULP mode in the PHY */
1260 mac_reg = er32(H2ME);
1261 mac_reg &= ~E1000_H2ME_ULP;
1262 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1263 ew32(H2ME, mac_reg);
1264 }
1265
3cf31b1a
ML		 1266 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1267 * If this takes more than 1 second, show a warning indicating a
1268 * firmware bug
1269 */
74f350ee 1270 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
3cf31b1a 1271 if (i++ == 250) {
74f350ee
DE		 1272 ret_val = -E1000_ERR_PHY;
1273 goto out;
1274 }
3cf31b1a
ML		 1275 if (i > 100 && !firmware_bug)
1276 firmware_bug = true;
74f350ee 1277
ab6973ae 1278 usleep_range(10000, 11000);
74f350ee 1279 }
3cf31b1a
ML		 1280 if (firmware_bug)
1281 e_warn("ULP_CONFIG_DONE took %dmsec. This is a firmware bug\n", i * 10);
1282 else
1283 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
74f350ee
DE		 1284
1285 if (force) {
1286 mac_reg = er32(H2ME);
1287 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1288 ew32(H2ME, mac_reg);
1289 } else {
1290 /* Clear H2ME.ULP after ME ULP configuration */
1291 mac_reg = er32(H2ME);
1292 mac_reg &= ~E1000_H2ME_ULP;
1293 ew32(H2ME, mac_reg);
1294 }
1295
1296 goto out;
1297 }
1298
1299 ret_val = hw->phy.ops.acquire(hw);
1300 if (ret_val)
1301 goto out;
1302
1303 if (force)
1304 /* Toggle LANPHYPC Value bit */
1305 e1000_toggle_lanphypc_pch_lpt(hw);
1306
1307 /* Unforce SMBus mode in PHY */
1308 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1309 if (ret_val) {
1310 /* The MAC might be in PCIe mode, so temporarily force to
1311 * SMBus mode in order to access the PHY.
1312 */
1313 mac_reg = er32(CTRL_EXT);
1314 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1315 ew32(CTRL_EXT, mac_reg);
1316
1317 msleep(50);
1318
1319 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1320 &phy_reg);
1321 if (ret_val)
1322 goto release;
1323 }
1324 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1325 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1326
1327 /* Unforce SMBus mode in MAC */
1328 mac_reg = er32(CTRL_EXT);
1329 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1330 ew32(CTRL_EXT, mac_reg);
1331
1332 /* When ULP mode was previously entered, K1 was disabled by the
1333 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1334 */
1335 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1336 if (ret_val)
1337 goto release;
1338 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1339 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1340
1341 /* Clear ULP enabled configuration */
1342 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1343 if (ret_val)
1344 goto release;
1345 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1346 I218_ULP_CONFIG1_STICKY_ULP |
1347 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1348 I218_ULP_CONFIG1_WOL_HOST |
1349 I218_ULP_CONFIG1_INBAND_EXIT |
c5c6d077
RA		 1350 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1351 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
74f350ee
DE		 1352 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1353 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1354
1355 /* Commit ULP changes by starting auto ULP configuration */
1356 phy_reg |= I218_ULP_CONFIG1_START;
1357 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1358
1359 /* Clear Disable SMBus Release on PERST# in MAC */
1360 mac_reg = er32(FEXTNVM7);
1361 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1362 ew32(FEXTNVM7, mac_reg);
1363
1364release:
1365 hw->phy.ops.release(hw);
1366 if (force) {
1367 e1000_phy_hw_reset(hw);
1368 msleep(50);
1369 }
1370out:
1371 if (ret_val)
1372 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1373 else
1374 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1375
1376 return ret_val;
1377}
1378
7d3cabbc
BA		 1379/**
1380 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1381 * @hw: pointer to the HW structure
1382 *
1383 * Checks to see of the link status of the hardware has changed. If a
1384 * change in link status has been detected, then we read the PHY registers
1385 * to get the current speed/duplex if link exists.
1386 **/
1387static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1388{
1389 struct e1000_mac_info *mac = &hw->mac;
79849ebc
DE		 1390 s32 ret_val, tipg_reg = 0;
1391 u16 emi_addr, emi_val = 0;
7d3cabbc 1392 bool link;
1d2101a7 1393 u16 phy_reg;
7d3cabbc 1394
e921eb1a 1395 /* We only want to go out to the PHY registers to see if Auto-Neg
7d3cabbc
BA		 1396 * has completed and/or if our link status has changed. The
1397 * get_link_status flag is set upon receiving a Link Status
1398 * Change or Rx Sequence Error interrupt.
1399 */
5015e53a 1400 if (!mac->get_link_status)
3016e0a0 1401 return 0;
e2710dbf 1402 mac->get_link_status = false;
7d3cabbc 1403
e921eb1a 1404 /* First we want to see if the MII Status Register reports
7d3cabbc
BA		 1405 * link. If so, then we want to get the current speed/duplex
1406 * of the PHY.
1407 */
1408 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1409 if (ret_val)
e2710dbf 1410 goto out;
7d3cabbc 1411
1d5846b9
BA		 1412 if (hw->mac.type == e1000_pchlan) {
1413 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1414 if (ret_val)
e2710dbf 1415 goto out;
1d5846b9
BA		 1416 }
1417
fbb9ab10 1418 /* When connected at 10Mbps half-duplex, some parts are excessively
772d05c5
BA		 1419 * aggressive resulting in many collisions. To avoid this, increase
1420 * the IPG and reduce Rx latency in the PHY.
1421 */
c8744f44 1422 if ((hw->mac.type >= e1000_pch2lan) && link) {
69cfbc95 1423 u16 speed, duplex;
6cf08d1c 1424
69cfbc95 1425 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
79849ebc
DE		 1426 tipg_reg = er32(TIPG);
1427 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1428
69cfbc95 1429 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
79849ebc
DE		 1430 tipg_reg |= 0xFF;
1431 /* Reduce Rx latency in analog PHY */
1432 emi_val = 0;
c8744f44 1433 } else if (hw->mac.type >= e1000_pch_spt &&
69cfbc95
YL		 1434 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1435 tipg_reg |= 0xC;
1436 emi_val = 1;
79849ebc 1437 } else {
fbb9ab10 1438
79849ebc
DE		 1439 /* Roll back the default values */
1440 tipg_reg |= 0x08;
1441 emi_val = 1;
1442 }
772d05c5 1443
79849ebc 1444 ew32(TIPG, tipg_reg);
772d05c5 1445
79849ebc
DE		 1446 ret_val = hw->phy.ops.acquire(hw);
1447 if (ret_val)
e2710dbf 1448 goto out;
fbb9ab10 1449
79849ebc
DE		 1450 if (hw->mac.type == e1000_pch2lan)
1451 emi_addr = I82579_RX_CONFIG;
1452 else
1453 emi_addr = I217_RX_CONFIG;
1454 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
772d05c5 1455
c8744f44 1456 if (hw->mac.type >= e1000_pch_lpt) {
74f31299
RA		 1457 u16 phy_reg;
1458
1459 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1460 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1461 if (speed == SPEED_100 || speed == SPEED_10)
1462 phy_reg |= 0x3E8;
1463 else
1464 phy_reg |= 0xFA;
1465 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
e5e9a2ec
KHF		 1466
1467 if (speed == SPEED_1000) {
1468 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1469 &phy_reg);
1470
1471 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1472
1473 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1474 phy_reg);
1475 }
74f31299 1476 }
79849ebc 1477 hw->phy.ops.release(hw);
772d05c5 1478
79849ebc 1479 if (ret_val)
e2710dbf 1480 goto out;
93cbfc70 1481
c8744f44 1482 if (hw->mac.type >= e1000_pch_spt) {
93cbfc70
YL		 1483 u16 data;
1484 u16 ptr_gap;
1485
1486 if (speed == SPEED_1000) {
1487 ret_val = hw->phy.ops.acquire(hw);
1488 if (ret_val)
e2710dbf 1489 goto out;
93cbfc70
YL		 1490
1491 ret_val = e1e_rphy_locked(hw,
1492 PHY_REG(776, 20),
1493 &data);
1494 if (ret_val) {
1495 hw->phy.ops.release(hw);
e2710dbf 1496 goto out;
93cbfc70
YL		 1497 }
1498
1499 ptr_gap = (data & (0x3FF << 2)) >> 2;
1500 if (ptr_gap < 0x18) {
1501 data &= ~(0x3FF << 2);
1502 data |= (0x18 << 2);
1503 ret_val =
1504 e1e_wphy_locked(hw,
1505 PHY_REG(776, 20),
1506 data);
1507 }
1508 hw->phy.ops.release(hw);
1509 if (ret_val)
e2710dbf 1510 goto out;
c26f40da
RA		 1511 } else {
1512 ret_val = hw->phy.ops.acquire(hw);
1513 if (ret_val)
e2710dbf 1514 goto out;
c26f40da
RA		 1515
1516 ret_val = e1e_wphy_locked(hw,
1517 PHY_REG(776, 20),
1518 0xC023);
1519 hw->phy.ops.release(hw);
1520 if (ret_val)
e2710dbf 1521 goto out;
c26f40da 1522
93cbfc70
YL		 1523 }
1524 }
1525 }
1526
1527 /* I217 Packet Loss issue:
1528 * ensure that FEXTNVM4 Beacon Duration is set correctly
1529 * on power up.
1530 * Set the Beacon Duration for I217 to 8 usec
1531 */
c8744f44 1532 if (hw->mac.type >= e1000_pch_lpt) {
93cbfc70
YL		 1533 u32 mac_reg;
1534
1535 mac_reg = er32(FEXTNVM4);
1536 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1537 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1538 ew32(FEXTNVM4, mac_reg);
772d05c5
BA		 1539 }
1540
e08f626b
BA		 1541 /* Work-around I218 hang issue */
1542 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
91a3d82f
BA		 1543 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1544 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
352f8ead 1545 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
e08f626b
BA		 1546 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1547 if (ret_val)
e2710dbf 1548 goto out;
e08f626b 1549 }
c8744f44 1550 if (hw->mac.type >= e1000_pch_lpt) {
cf8fb73c
BA		 1551 /* Set platform power management values for
1552 * Latency Tolerance Reporting (LTR)
1553 */
1554 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1555 if (ret_val)
e2710dbf 1556 goto out;
cf8fb73c
BA		 1557 }
1558
2fbe4526
BA		 1559 /* Clear link partner's EEE ability */
1560 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1561
c8744f44 1562 if (hw->mac.type >= e1000_pch_lpt) {
79849ebc
DE		 1563 u32 fextnvm6 = er32(FEXTNVM6);
1564
c8744f44
SN		 1565 if (hw->mac.type == e1000_pch_spt) {
1566 /* FEXTNVM6 K1-off workaround - for SPT only */
1567 u32 pcieanacfg = er32(PCIEANACFG);
1568
1569 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1570 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1571 else
1572 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1573 }
79849ebc 1574
43932382
KHF		 1575 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1576 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1577
79849ebc
DE		 1578 ew32(FEXTNVM6, fextnvm6);
1579 }
1580
7d3cabbc 1581 if (!link)
e2710dbf 1582 goto out;
7d3cabbc 1583
1d2101a7
BA		 1584 switch (hw->mac.type) {
1585 case e1000_pch2lan:
831bd2e6
BA		 1586 ret_val = e1000_k1_workaround_lv(hw);
1587 if (ret_val)
5015e53a 1588 return ret_val;
5463fce6 1589 fallthrough;
1d2101a7
BA		 1590 case e1000_pchlan:
1591 if (hw->phy.type == e1000_phy_82578) {
1592 ret_val = e1000_link_stall_workaround_hv(hw);
1593 if (ret_val)
5015e53a 1594 return ret_val;
1d2101a7
BA		 1595 }
1596
e921eb1a 1597 /* Workaround for PCHx parts in half-duplex:
1d2101a7
BA		 1598 * Set the number of preambles removed from the packet
1599 * when it is passed from the PHY to the MAC to prevent
1600 * the MAC from misinterpreting the packet type.
1601 */
1602 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1603 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1604
1605 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
18dd2392 1606 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1d2101a7
BA		 1607
1608 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1609 break;
1610 default:
1611 break;
831bd2e6
BA		 1612 }
1613
e921eb1a 1614 /* Check if there was DownShift, must be checked
7d3cabbc
BA		 1615 * immediately after link-up
1616 */
1617 e1000e_check_downshift(hw);
1618
e52997f9 1619 /* Enable/Disable EEE after link up */
a03206ed
DE		 1620 if (hw->phy.type > e1000_phy_82579) {
1621 ret_val = e1000_set_eee_pchlan(hw);
1622 if (ret_val)
1623 return ret_val;
1624 }
e52997f9 1625
e921eb1a 1626 /* If we are forcing speed/duplex, then we simply return since
7d3cabbc
BA		 1627 * we have already determined whether we have link or not.
1628 */
5015e53a 1629 if (!mac->autoneg)
3016e0a0 1630 return -E1000_ERR_CONFIG;
7d3cabbc 1631
e921eb1a 1632 /* Auto-Neg is enabled. Auto Speed Detection takes care
7d3cabbc
BA		 1633 * of MAC speed/duplex configuration. So we only need to
1634 * configure Collision Distance in the MAC.
1635 */
57cde763 1636 mac->ops.config_collision_dist(hw);
7d3cabbc 1637
e921eb1a 1638 /* Configure Flow Control now that Auto-Neg has completed.
7d3cabbc
BA		 1639 * First, we need to restore the desired flow control
1640 * settings because we may have had to re-autoneg with a
1641 * different link partner.
1642 */
1643 ret_val = e1000e_config_fc_after_link_up(hw);
3016e0a0 1644 if (ret_val)
3bb99fe2 1645 e_dbg("Error configuring flow control\n");
7d3cabbc 1646
3016e0a0 1647 return ret_val;
e2710dbf
BP		 1648
1649out:
1650 mac->get_link_status = true;
1651 return ret_val;
7d3cabbc
BA		 1652}
1653
69e3fd8c 1654static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 1655{
1656 struct e1000_hw *hw = &adapter->hw;
1657 s32 rc;
1658
ec34c170 1659 rc = e1000_init_mac_params_ich8lan(hw);
bc7f75fa
AK		 1660 if (rc)
1661 return rc;
1662
1663 rc = e1000_init_nvm_params_ich8lan(hw);
1664 if (rc)
1665 return rc;
1666
d3738bb8
BA		 1667 switch (hw->mac.type) {
1668 case e1000_ich8lan:
1669 case e1000_ich9lan:
1670 case e1000_ich10lan:
a4f58f54 1671 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 1672 break;
1673 case e1000_pchlan:
1674 case e1000_pch2lan:
2fbe4526 1675 case e1000_pch_lpt:
79849ebc 1676 case e1000_pch_spt:
c8744f44 1677 case e1000_pch_cnp:
fb776f5d 1678 case e1000_pch_tgp:
59e46688 1679 case e1000_pch_adp:
cc23f4f0 1680 case e1000_pch_mtp:
d3738bb8
BA		 1681 rc = e1000_init_phy_params_pchlan(hw);
1682 break;
1683 default:
1684 break;
1685 }
bc7f75fa
AK		 1686 if (rc)
1687 return rc;
1688
e921eb1a 1689 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
23e4f061
BA		 1690 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1691 */
1692 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1693 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1694 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
2adc55c9 1695 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
8084b86d 1696 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
dbf80dcb
BA		 1697
1698 hw->mac.ops.blink_led = NULL;
2adc55c9
BA		 1699 }
1700
bc7f75fa 1701 if ((adapter->hw.mac.type == e1000_ich8lan) &&
462d5994 1702 (adapter->hw.phy.type != e1000_phy_ife))
bc7f75fa
AK		 1703 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1704
c6e7f51e
BA		 1705 /* Enable workaround for 82579 w/ ME enabled */
1706 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1707 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1708 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1709
bc7f75fa
AK		 1710 return 0;
1711}
1712
717d438d 1713static DEFINE_MUTEX(nvm_mutex);
717d438d 1714
ca15df58
BA		 1715/**
1716 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1717 * @hw: pointer to the HW structure
1718 *
1719 * Acquires the mutex for performing NVM operations.
1720 **/
8bb62869 1721static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 1722{
1723 mutex_lock(&nvm_mutex);
1724
1725 return 0;
1726}
1727
1728/**
1729 * e1000_release_nvm_ich8lan - Release NVM mutex
1730 * @hw: pointer to the HW structure
1731 *
1732 * Releases the mutex used while performing NVM operations.
1733 **/
8bb62869 1734static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 1735{
1736 mutex_unlock(&nvm_mutex);
ca15df58
BA		 1737}
1738
bc7f75fa
AK		 1739/**
1740 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1741 * @hw: pointer to the HW structure
1742 *
ca15df58
BA		 1743 * Acquires the software control flag for performing PHY and select
1744 * MAC CSR accesses.
bc7f75fa
AK		 1745 **/
1746static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1747{
373a88d7
BA		 1748 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1749 s32 ret_val = 0;
bc7f75fa 1750
a90b412c
BA		 1751 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1752 &hw->adapter->state)) {
34c9ef8b 1753 e_dbg("contention for Phy access\n");
a90b412c
BA		 1754 return -E1000_ERR_PHY;
1755 }
717d438d 1756
bc7f75fa
AK		 1757 while (timeout) {
1758 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 1759 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1760 break;
bc7f75fa 1761
373a88d7
BA		 1762 mdelay(1);
1763 timeout--;
1764 }
1765
1766 if (!timeout) {
a90b412c 1767 e_dbg("SW has already locked the resource.\n");
373a88d7
BA		 1768 ret_val = -E1000_ERR_CONFIG;
1769 goto out;
1770 }
1771
53ac5a88 1772 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 1773
1774 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1775 ew32(EXTCNF_CTRL, extcnf_ctrl);
1776
1777 while (timeout) {
1778 extcnf_ctrl = er32(EXTCNF_CTRL);
1779 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1780 break;
a4f58f54 1781
bc7f75fa
AK		 1782 mdelay(1);
1783 timeout--;
1784 }
1785
1786 if (!timeout) {
434f1392 1787 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
a90b412c 1788 er32(FWSM), extcnf_ctrl);
2e2e8d53
BA		 1789 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1790 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 1791 ret_val = -E1000_ERR_CONFIG;
1792 goto out;
bc7f75fa
AK		 1793 }
1794
373a88d7
BA		 1795out:
1796 if (ret_val)
a90b412c 1797 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
373a88d7
BA		 1798
1799 return ret_val;
bc7f75fa
AK		 1800}
1801
1802/**
1803 * e1000_release_swflag_ich8lan - Release software control flag
1804 * @hw: pointer to the HW structure
1805 *
ca15df58
BA		 1806 * Releases the software control flag for performing PHY and select
1807 * MAC CSR accesses.
bc7f75fa
AK		 1808 **/
1809static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1810{
1811 u32 extcnf_ctrl;
1812
1813 extcnf_ctrl = er32(EXTCNF_CTRL);
c5caf482
BA		 1814
1815 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1816 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1817 ew32(EXTCNF_CTRL, extcnf_ctrl);
1818 } else {
1819 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1820 }
717d438d 1821
a90b412c 1822 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
bc7f75fa
AK		 1823}
1824
4662e82b
BA		 1825/**
1826 * e1000_check_mng_mode_ich8lan - Checks management mode
1827 * @hw: pointer to the HW structure
1828 *
eb7700dc 1829 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 1830 * This is a function pointer entry point only called by read/write
1831 * routines for the PHY and NVM parts.
1832 **/
1833static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1834{
a708dd88
BA		 1835 u32 fwsm;
1836
1837 fwsm = er32(FWSM);
261a7d12 1838 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
f0ff4398 1839 ((fwsm & E1000_FWSM_MODE_MASK) ==
261a7d12 1840 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
eb7700dc 1841}
4662e82b 1842
eb7700dc
BA		 1843/**
1844 * e1000_check_mng_mode_pchlan - Checks management mode
1845 * @hw: pointer to the HW structure
1846 *
1847 * This checks if the adapter has iAMT enabled.
1848 * This is a function pointer entry point only called by read/write
1849 * routines for the PHY and NVM parts.
1850 **/
1851static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1852{
1853 u32 fwsm;
1854
1855 fwsm = er32(FWSM);
1856 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
f0ff4398 1857 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 1858}
1859
69e1e019
BA		 1860/**
1861 * e1000_rar_set_pch2lan - Set receive address register
1862 * @hw: pointer to the HW structure
1863 * @addr: pointer to the receive address
1864 * @index: receive address array register
1865 *
1866 * Sets the receive address array register at index to the address passed
1867 * in by addr. For 82579, RAR[0] is the base address register that is to
1868 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1869 * Use SHRA[0-3] in place of those reserved for ME.
1870 **/
b3e5bf1f 1871static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
69e1e019
BA		 1872{
1873 u32 rar_low, rar_high;
1874
e921eb1a 1875 /* HW expects these in little endian so we reverse the byte order
69e1e019
BA		 1876 * from network order (big endian) to little endian
1877 */
1878 rar_low = ((u32)addr[0] |
1879 ((u32)addr[1] << 8) |
1880 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1881
1882 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1883
1884 /* If MAC address zero, no need to set the AV bit */
1885 if (rar_low || rar_high)
1886 rar_high |= E1000_RAH_AV;
1887
1888 if (index == 0) {
1889 ew32(RAL(index), rar_low);
1890 e1e_flush();
1891 ew32(RAH(index), rar_high);
1892 e1e_flush();
b3e5bf1f 1893 return 0;
69e1e019
BA		 1894 }
1895
c3a0dce3
DE		 1896 /* RAR[1-6] are owned by manageability. Skip those and program the
1897 * next address into the SHRA register array.
1898 */
96dee024 1899 if (index < (u32)(hw->mac.rar_entry_count)) {
69e1e019
BA		 1900 s32 ret_val;
1901
1902 ret_val = e1000_acquire_swflag_ich8lan(hw);
1903 if (ret_val)
1904 goto out;
1905
1906 ew32(SHRAL(index - 1), rar_low);
1907 e1e_flush();
1908 ew32(SHRAH(index - 1), rar_high);
1909 e1e_flush();
1910
1911 e1000_release_swflag_ich8lan(hw);
1912
1913 /* verify the register updates */
1914 if ((er32(SHRAL(index - 1)) == rar_low) &&
1915 (er32(SHRAH(index - 1)) == rar_high))
b3e5bf1f 1916 return 0;
69e1e019
BA		 1917
1918 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1919 (index - 1), er32(FWSM));
1920 }
1921
1922out:
1923 e_dbg("Failed to write receive address at index %d\n", index);
b3e5bf1f
DE		 1924 return -E1000_ERR_CONFIG;
1925}
1926
1927/**
1928 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1929 * @hw: pointer to the HW structure
1930 *
1931 * Get the number of available receive registers that the Host can
1932 * program. SHRA[0-10] are the shared receive address registers
1933 * that are shared between the Host and manageability engine (ME).
1934 * ME can reserve any number of addresses and the host needs to be
1935 * able to tell how many available registers it has access to.
1936 **/
1937static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1938{
1939 u32 wlock_mac;
1940 u32 num_entries;
1941
1942 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1943 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1944
1945 switch (wlock_mac) {
1946 case 0:
1947 /* All SHRA[0..10] and RAR[0] available */
1948 num_entries = hw->mac.rar_entry_count;
1949 break;
1950 case 1:
1951 /* Only RAR[0] available */
1952 num_entries = 1;
1953 break;
1954 default:
1955 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1956 num_entries = wlock_mac + 1;
1957 break;
1958 }
1959
1960 return num_entries;
69e1e019
BA		 1961}
1962
2fbe4526
BA		 1963/**
1964 * e1000_rar_set_pch_lpt - Set receive address registers
1965 * @hw: pointer to the HW structure
1966 * @addr: pointer to the receive address
1967 * @index: receive address array register
1968 *
1969 * Sets the receive address register array at index to the address passed
1970 * in by addr. For LPT, RAR[0] is the base address register that is to
1971 * contain the MAC address. SHRA[0-10] are the shared receive address
1972 * registers that are shared between the Host and manageability engine (ME).
1973 **/
b3e5bf1f 1974static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2fbe4526
BA		 1975{
1976 u32 rar_low, rar_high;
1977 u32 wlock_mac;
1978
e921eb1a 1979 /* HW expects these in little endian so we reverse the byte order
2fbe4526
BA		 1980 * from network order (big endian) to little endian
1981 */
1982 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1983 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1984
1985 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1986
1987 /* If MAC address zero, no need to set the AV bit */
1988 if (rar_low || rar_high)
1989 rar_high |= E1000_RAH_AV;
1990
1991 if (index == 0) {
1992 ew32(RAL(index), rar_low);
1993 e1e_flush();
1994 ew32(RAH(index), rar_high);
1995 e1e_flush();
b3e5bf1f 1996 return 0;
2fbe4526
BA		 1997 }
1998
e921eb1a 1999 /* The manageability engine (ME) can lock certain SHRAR registers that
2fbe4526
BA		 2000 * it is using - those registers are unavailable for use.
2001 */
2002 if (index < hw->mac.rar_entry_count) {
2003 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2004 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2005
2006 /* Check if all SHRAR registers are locked */
2007 if (wlock_mac == 1)
2008 goto out;
2009
2010 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2011 s32 ret_val;
2012
2013 ret_val = e1000_acquire_swflag_ich8lan(hw);
2014
2015 if (ret_val)
2016 goto out;
2017
2018 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2019 e1e_flush();
2020 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2021 e1e_flush();
2022
2023 e1000_release_swflag_ich8lan(hw);
2024
2025 /* verify the register updates */
2026 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2027 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
b3e5bf1f 2028 return 0;
2fbe4526
BA		 2029 }
2030 }
2031
2032out:
2033 e_dbg("Failed to write receive address at index %d\n", index);
b3e5bf1f 2034 return -E1000_ERR_CONFIG;
2fbe4526
BA		 2035}
2036
bc7f75fa
AK		 2037/**
2038 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2039 * @hw: pointer to the HW structure
2040 *
2041 * Checks if firmware is blocking the reset of the PHY.
2042 * This is a function pointer entry point only called by
2043 * reset routines.
2044 **/
2045static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2046{
f7235ef6
DE		 2047 bool blocked = false;
2048 int i = 0;
bc7f75fa 2049
f7235ef6 2050 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
d17c7868 2051 (i++ < 30))
ab6973ae 2052 usleep_range(10000, 11000);
f7235ef6 2053 return blocked ? E1000_BLK_PHY_RESET : 0;
bc7f75fa
AK		 2054}
2055
8395ae83
BA		 2056/**
2057 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2058 * @hw: pointer to the HW structure
2059 *
2060 * Assumes semaphore already acquired.
2061 *
2062 **/
2063static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2064{
2065 u16 phy_data;
2066 u32 strap = er32(STRAP);
2fbe4526
BA		 2067 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2068 E1000_STRAP_SMT_FREQ_SHIFT;
70806a7f 2069 s32 ret_val;
8395ae83
BA		 2070
2071 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2072
2073 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2074 if (ret_val)
5015e53a 2075 return ret_val;
8395ae83
BA		 2076
2077 phy_data &= ~HV_SMB_ADDR_MASK;
2078 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2079 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
8395ae83 2080
2fbe4526
BA		 2081 if (hw->phy.type == e1000_phy_i217) {
2082 /* Restore SMBus frequency */
2083 if (freq--) {
2084 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
18dd2392 2085 phy_data |= (freq & BIT(0)) <<
2fbe4526 2086 HV_SMB_ADDR_FREQ_LOW_SHIFT;
18dd2392 2087 phy_data |= (freq & BIT(1)) <<
2fbe4526
BA		 2088 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2089 } else {
2090 e_dbg("Unsupported SMB frequency in PHY\n");
2091 }
2092 }
2093
5015e53a 2094 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
8395ae83
BA		 2095}
2096
f523d211
BA		 2097/**
2098 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2099 * @hw: pointer to the HW structure
2100 *
2101 * SW should configure the LCD from the NVM extended configuration region
2102 * as a workaround for certain parts.
2103 **/
2104static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2105{
2106 struct e1000_phy_info *phy = &hw->phy;
2107 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 2108 s32 ret_val = 0;
f523d211
BA		 2109 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2110
e921eb1a 2111 /* Initialize the PHY from the NVM on ICH platforms. This
f523d211
BA		 2112 * is needed due to an issue where the NVM configuration is
2113 * not properly autoloaded after power transitions.
2114 * Therefore, after each PHY reset, we will load the
2115 * configuration data out of the NVM manually.
2116 */
3f0c16e8
BA		 2117 switch (hw->mac.type) {
2118 case e1000_ich8lan:
2119 if (phy->type != e1000_phy_igp_3)
2120 return ret_val;
2121
5f3eed6f
BA		 2122 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2123 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
3f0c16e8
BA		 2124 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2125 break;
2126 }
5463fce6 2127 fallthrough;
3f0c16e8 2128 case e1000_pchlan:
d3738bb8 2129 case e1000_pch2lan:
2fbe4526 2130 case e1000_pch_lpt:
79849ebc 2131 case e1000_pch_spt:
c8744f44 2132 case e1000_pch_cnp:
fb776f5d 2133 case e1000_pch_tgp:
59e46688 2134 case e1000_pch_adp:
cc23f4f0 2135 case e1000_pch_mtp:
8b802a7e 2136 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 2137 break;
2138 default:
2139 return ret_val;
2140 }
2141
2142 ret_val = hw->phy.ops.acquire(hw);
2143 if (ret_val)
2144 return ret_val;
8b802a7e
BA		 2145
2146 data = er32(FEXTNVM);
2147 if (!(data & sw_cfg_mask))
75ce1532 2148 goto release;
f523d211 2149
e921eb1a 2150 /* Make sure HW does not configure LCD from PHY
8b802a7e
BA		 2151 * extended configuration before SW configuration
2152 */
2153 data = er32(EXTCNF_CTRL);
2fbe4526
BA		 2154 if ((hw->mac.type < e1000_pch2lan) &&
2155 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2156 goto release;
8b802a7e
BA		 2157
2158 cnf_size = er32(EXTCNF_SIZE);
2159 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2160 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2161 if (!cnf_size)
75ce1532 2162 goto release;
8b802a7e
BA		 2163
2164 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2165 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2166
2fbe4526
BA		 2167 if (((hw->mac.type == e1000_pchlan) &&
2168 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2169 (hw->mac.type > e1000_pchlan)) {
e921eb1a 2170 /* HW configures the SMBus address and LEDs when the
8b802a7e
BA		 2171 * OEM and LCD Write Enable bits are set in the NVM.
2172 * When both NVM bits are cleared, SW will configure
2173 * them instead.
f523d211 2174 */
8395ae83 2175 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 2176 if (ret_val)
75ce1532 2177 goto release;
f523d211 2178
8b802a7e
BA		 2179 data = er32(LEDCTL);
2180 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2181 (u16)data);
2182 if (ret_val)
75ce1532 2183 goto release;
8b802a7e 2184 }
f523d211 2185
8b802a7e
BA		 2186 /* Configure LCD from extended configuration region. */
2187
2188 /* cnf_base_addr is in DWORD */
2189 word_addr = (u16)(cnf_base_addr << 1);
2190
2191 for (i = 0; i < cnf_size; i++) {
e5fe2541 2192 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
8b802a7e 2193 if (ret_val)
75ce1532 2194 goto release;
8b802a7e
BA		 2195
2196 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2197 1, &reg_addr);
2198 if (ret_val)
75ce1532 2199 goto release;
8b802a7e
BA		 2200
2201 /* Save off the PHY page for future writes. */
2202 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2203 phy_page = reg_data;
2204 continue;
f523d211 2205 }
8b802a7e
BA		 2206
2207 reg_addr &= PHY_REG_MASK;
2208 reg_addr |= phy_page;
2209
f1430d69 2210 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
8b802a7e 2211 if (ret_val)
75ce1532 2212 goto release;
f523d211
BA		 2213 }
2214
75ce1532 2215release:
94d8186a 2216 hw->phy.ops.release(hw);
f523d211
BA		 2217 return ret_val;
2218}
2219
1d5846b9
BA		 2220/**
2221 * e1000_k1_gig_workaround_hv - K1 Si workaround
2222 * @hw: pointer to the HW structure
2223 * @link: link up bool flag
2224 *
2225 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2226 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2227 * If link is down, the function will restore the default K1 setting located
2228 * in the NVM.
2229 **/
2230static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2231{
2232 s32 ret_val = 0;
2233 u16 status_reg = 0;
2234 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2235
2236 if (hw->mac.type != e1000_pchlan)
5015e53a 2237 return 0;
1d5846b9
BA		 2238
2239 /* Wrap the whole flow with the sw flag */
94d8186a 2240 ret_val = hw->phy.ops.acquire(hw);
1d5846b9 2241 if (ret_val)
5015e53a 2242 return ret_val;
1d5846b9
BA		 2243
2244 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2245 if (link) {
2246 if (hw->phy.type == e1000_phy_82578) {
f1430d69
BA		 2247 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2248 &status_reg);
1d5846b9
BA		 2249 if (ret_val)
2250 goto release;
2251
f0ff4398
BA		 2252 status_reg &= (BM_CS_STATUS_LINK_UP |
2253 BM_CS_STATUS_RESOLVED |
2254 BM_CS_STATUS_SPEED_MASK);
1d5846b9
BA		 2255
2256 if (status_reg == (BM_CS_STATUS_LINK_UP |
f0ff4398
BA		 2257 BM_CS_STATUS_RESOLVED |
2258 BM_CS_STATUS_SPEED_1000))
1d5846b9
BA		 2259 k1_enable = false;
2260 }
2261
2262 if (hw->phy.type == e1000_phy_82577) {
f1430d69 2263 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1d5846b9
BA		 2264 if (ret_val)
2265 goto release;
2266
f0ff4398
BA		 2267 status_reg &= (HV_M_STATUS_LINK_UP |
2268 HV_M_STATUS_AUTONEG_COMPLETE |
2269 HV_M_STATUS_SPEED_MASK);
1d5846b9
BA		 2270
2271 if (status_reg == (HV_M_STATUS_LINK_UP |
f0ff4398
BA		 2272 HV_M_STATUS_AUTONEG_COMPLETE |
2273 HV_M_STATUS_SPEED_1000))
1d5846b9
BA		 2274 k1_enable = false;
2275 }
2276
2277 /* Link stall fix for link up */
f1430d69 2278 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1d5846b9
BA		 2279 if (ret_val)
2280 goto release;
2281
2282 } else {
2283 /* Link stall fix for link down */
f1430d69 2284 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1d5846b9
BA		 2285 if (ret_val)
2286 goto release;
2287 }
2288
2289 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2290
2291release:
94d8186a 2292 hw->phy.ops.release(hw);
5015e53a 2293
1d5846b9
BA		 2294 return ret_val;
2295}
2296
2297/**
2298 * e1000_configure_k1_ich8lan - Configure K1 power state
2299 * @hw: pointer to the HW structure
b50f7bca 2300 * @k1_enable: K1 state to configure
1d5846b9
BA		 2301 *
2302 * Configure the K1 power state based on the provided parameter.
2303 * Assumes semaphore already acquired.
2304 *
2305 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2306 **/
bb436b20 2307s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9 2308{
70806a7f 2309 s32 ret_val;
1d5846b9
BA		 2310 u32 ctrl_reg = 0;
2311 u32 ctrl_ext = 0;
2312 u32 reg = 0;
2313 u16 kmrn_reg = 0;
2314
3d3a1676
BA		 2315 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2316 &kmrn_reg);
1d5846b9 2317 if (ret_val)
5015e53a 2318 return ret_val;
1d5846b9
BA		 2319
2320 if (k1_enable)
2321 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2322 else
2323 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2324
3d3a1676
BA		 2325 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2326 kmrn_reg);
1d5846b9 2327 if (ret_val)
5015e53a 2328 return ret_val;
1d5846b9 2329
ce43a216 2330 usleep_range(20, 40);
1d5846b9
BA		 2331 ctrl_ext = er32(CTRL_EXT);
2332 ctrl_reg = er32(CTRL);
2333
2334 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2335 reg |= E1000_CTRL_FRCSPD;
2336 ew32(CTRL, reg);
2337
2338 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
945a5151 2339 e1e_flush();
ce43a216 2340 usleep_range(20, 40);
1d5846b9
BA		 2341 ew32(CTRL, ctrl_reg);
2342 ew32(CTRL_EXT, ctrl_ext);
945a5151 2343 e1e_flush();
ce43a216 2344 usleep_range(20, 40);
1d5846b9 2345
5015e53a 2346 return 0;
1d5846b9
BA		 2347}
2348
f523d211
BA		 2349/**
2350 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2351 * @hw: pointer to the HW structure
2352 * @d0_state: boolean if entering d0 or d3 device state
2353 *
2354 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2355 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2356 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2357 **/
2358static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2359{
2360 s32 ret_val = 0;
2361 u32 mac_reg;
2362 u16 oem_reg;
2363
2fbe4526 2364 if (hw->mac.type < e1000_pchlan)
f523d211
BA		 2365 return ret_val;
2366
94d8186a 2367 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 2368 if (ret_val)
2369 return ret_val;
2370
2fbe4526 2371 if (hw->mac.type == e1000_pchlan) {
d3738bb8
BA		 2372 mac_reg = er32(EXTCNF_CTRL);
2373 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
75ce1532 2374 goto release;
d3738bb8 2375 }
f523d211
BA		 2376
2377 mac_reg = er32(FEXTNVM);
2378 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
75ce1532 2379 goto release;
f523d211
BA		 2380
2381 mac_reg = er32(PHY_CTRL);
2382
f1430d69 2383 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211 2384 if (ret_val)
75ce1532 2385 goto release;
f523d211
BA		 2386
2387 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2388
2389 if (d0_state) {
2390 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2391 oem_reg |= HV_OEM_BITS_GBE_DIS;
2392
2393 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2394 oem_reg |= HV_OEM_BITS_LPLU;
2395 } else {
03299e46
BA		 2396 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2397 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
f523d211
BA		 2398 oem_reg |= HV_OEM_BITS_GBE_DIS;
2399
03299e46
BA		 2400 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2401 E1000_PHY_CTRL_NOND0A_LPLU))
f523d211
BA		 2402 oem_reg |= HV_OEM_BITS_LPLU;
2403 }
03299e46 2404
92fe1733
BA		 2405 /* Set Restart auto-neg to activate the bits */
2406 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2407 !hw->phy.ops.check_reset_block(hw))
2408 oem_reg |= HV_OEM_BITS_RESTART_AN;
2409
f1430d69 2410 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
f523d211 2411
75ce1532 2412release:
94d8186a 2413 hw->phy.ops.release(hw);
f523d211
BA		 2414
2415 return ret_val;
2416}
2417
fddaa1af
BA		 2418/**
2419 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2420 * @hw: pointer to the HW structure
2421 **/
2422static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2423{
2424 s32 ret_val;
2425 u16 data;
2426
2427 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2428 if (ret_val)
2429 return ret_val;
2430
2431 data |= HV_KMRN_MDIO_SLOW;
2432
2433 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2434
2435 return ret_val;
2436}
2437
a4f58f54 2438/**
b50f7bca
JB		 2439 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2440 * @hw: pointer to the HW structure
2441 *
2442 * A series of PHY workarounds to be done after every PHY reset.
a4f58f54
BA		 2443 **/
2444static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2445{
2446 s32 ret_val = 0;
baf86c9d 2447 u16 phy_data;
a4f58f54
BA		 2448
2449 if (hw->mac.type != e1000_pchlan)
5015e53a 2450 return 0;
a4f58f54 2451
fddaa1af
BA		 2452 /* Set MDIO slow mode before any other MDIO access */
2453 if (hw->phy.type == e1000_phy_82577) {
2454 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2455 if (ret_val)
5015e53a 2456 return ret_val;
fddaa1af
BA		 2457 }
2458
a4f58f54
BA		 2459 if (((hw->phy.type == e1000_phy_82577) &&
2460 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2461 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2462 /* Disable generation of early preamble */
2463 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2464 if (ret_val)
2465 return ret_val;
2466
2467 /* Preamble tuning for SSC */
1d2101a7 2468 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
a4f58f54
BA		 2469 if (ret_val)
2470 return ret_val;
2471 }
2472
2473 if (hw->phy.type == e1000_phy_82578) {
e921eb1a 2474 /* Return registers to default by doing a soft reset then
a4f58f54
BA		 2475 * writing 0x3140 to the control register.
2476 */
2477 if (hw->phy.revision < 2) {
2478 e1000e_phy_sw_reset(hw);
c2ade1a4 2479 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
d75372a2
GS		 2480 if (ret_val)
2481 return ret_val;
a4f58f54
BA		 2482 }
2483 }
2484
2485 /* Select page 0 */
94d8186a 2486 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 2487 if (ret_val)
2488 return ret_val;
1d5846b9 2489
a4f58f54 2490 hw->phy.addr = 1;
1d5846b9 2491 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 2492 hw->phy.ops.release(hw);
1d5846b9 2493 if (ret_val)
5015e53a 2494 return ret_val;
a4f58f54 2495
e921eb1a 2496 /* Configure the K1 Si workaround during phy reset assuming there is
1d5846b9
BA		 2497 * link so that it disables K1 if link is in 1Gbps.
2498 */
2499 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d 2500 if (ret_val)
5015e53a 2501 return ret_val;
1d5846b9 2502
baf86c9d
BA		 2503 /* Workaround for link disconnects on a busy hub in half duplex */
2504 ret_val = hw->phy.ops.acquire(hw);
2505 if (ret_val)
5015e53a 2506 return ret_val;
f1430d69 2507 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
baf86c9d
BA		 2508 if (ret_val)
2509 goto release;
f1430d69 2510 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
651fb102
BA		 2511 if (ret_val)
2512 goto release;
2513
2514 /* set MSE higher to enable link to stay up when noise is high */
2515 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
baf86c9d
BA		 2516release:
2517 hw->phy.ops.release(hw);
5015e53a 2518
a4f58f54
BA		 2519 return ret_val;
2520}
2521
d3738bb8
BA		 2522/**
2523 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2524 * @hw: pointer to the HW structure
2525 **/
2526void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2527{
2528 u32 mac_reg;
2b6b168d
BA		 2529 u16 i, phy_reg = 0;
2530 s32 ret_val;
2531
2532 ret_val = hw->phy.ops.acquire(hw);
2533 if (ret_val)
2534 return;
2535 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2536 if (ret_val)
2537 goto release;
d3738bb8 2538
c3a0dce3
DE		 2539 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2540 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
d3738bb8 2541 mac_reg = er32(RAL(i));
2b6b168d
BA		 2542 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2543 (u16)(mac_reg & 0xFFFF));
2544 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2545 (u16)((mac_reg >> 16) & 0xFFFF));
2546
d3738bb8 2547 mac_reg = er32(RAH(i));
2b6b168d
BA		 2548 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2549 (u16)(mac_reg & 0xFFFF));
2550 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2551 (u16)((mac_reg & E1000_RAH_AV)
2552 >> 16));
d3738bb8 2553 }
2b6b168d
BA		 2554
2555 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2556
2557release:
2558 hw->phy.ops.release(hw);
d3738bb8
BA		 2559}
2560
d3738bb8
BA		 2561/**
2562 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2563 * with 82579 PHY
2564 * @hw: pointer to the HW structure
2565 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2566 **/
2567s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2568{
2569 s32 ret_val = 0;
2570 u16 phy_reg, data;
2571 u32 mac_reg;
2572 u16 i;
2573
2fbe4526 2574 if (hw->mac.type < e1000_pch2lan)
5015e53a 2575 return 0;
d3738bb8
BA		 2576
2577 /* disable Rx path while enabling/disabling workaround */
2578 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
18dd2392 2579 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
d3738bb8 2580 if (ret_val)
5015e53a 2581 return ret_val;
d3738bb8
BA		 2582
2583 if (enable) {
c3a0dce3 2584 /* Write Rx addresses (rar_entry_count for RAL/H, and
d3738bb8
BA		 2585 * SHRAL/H) and initial CRC values to the MAC
2586 */
c3a0dce3 2587 for (i = 0; i < hw->mac.rar_entry_count; i++) {
362e20ca 2588 u8 mac_addr[ETH_ALEN] = { 0 };
d3738bb8
BA		 2589 u32 addr_high, addr_low;
2590
2591 addr_high = er32(RAH(i));
2592 if (!(addr_high & E1000_RAH_AV))
2593 continue;
2594 addr_low = er32(RAL(i));
2595 mac_addr[0] = (addr_low & 0xFF);
2596 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2597 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2598 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2599 mac_addr[4] = (addr_high & 0xFF);
2600 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2601
fe46f58f 2602 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
d3738bb8
BA		 2603 }
2604
2605 /* Write Rx addresses to the PHY */
2606 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2607
2608 /* Enable jumbo frame workaround in the MAC */
2609 mac_reg = er32(FFLT_DBG);
18dd2392 2610 mac_reg &= ~BIT(14);
d3738bb8
BA		 2611 mac_reg |= (7 << 15);
2612 ew32(FFLT_DBG, mac_reg);
2613
2614 mac_reg = er32(RCTL);
2615 mac_reg |= E1000_RCTL_SECRC;
2616 ew32(RCTL, mac_reg);
2617
2618 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2619 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2620 &data);
d3738bb8 2621 if (ret_val)
5015e53a 2622 return ret_val;
d3738bb8
BA		 2623 ret_val = e1000e_write_kmrn_reg(hw,
2624 E1000_KMRNCTRLSTA_CTRL_OFFSET,
18dd2392 2625 data | BIT(0));
d3738bb8 2626 if (ret_val)
5015e53a 2627 return ret_val;
d3738bb8 2628 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2629 E1000_KMRNCTRLSTA_HD_CTRL,
2630 &data);
d3738bb8 2631 if (ret_val)
5015e53a 2632 return ret_val;
d3738bb8
BA		 2633 data &= ~(0xF << 8);
2634 data |= (0xB << 8);
2635 ret_val = e1000e_write_kmrn_reg(hw,
2636 E1000_KMRNCTRLSTA_HD_CTRL,
2637 data);
2638 if (ret_val)
5015e53a 2639 return ret_val;
d3738bb8
BA		 2640
2641 /* Enable jumbo frame workaround in the PHY */
d3738bb8
BA		 2642 e1e_rphy(hw, PHY_REG(769, 23), &data);
2643 data &= ~(0x7F << 5);
2644 data |= (0x37 << 5);
2645 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2646 if (ret_val)
5015e53a 2647 return ret_val;
d3738bb8 2648 e1e_rphy(hw, PHY_REG(769, 16), &data);
18dd2392 2649 data &= ~BIT(13);
d3738bb8
BA		 2650 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2651 if (ret_val)
5015e53a 2652 return ret_val;
d3738bb8
BA		 2653 e1e_rphy(hw, PHY_REG(776, 20), &data);
2654 data &= ~(0x3FF << 2);
493004d0 2655 data |= (E1000_TX_PTR_GAP << 2);
d3738bb8
BA		 2656 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2657 if (ret_val)
5015e53a 2658 return ret_val;
b64e9dd5 2659 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
d3738bb8 2660 if (ret_val)
5015e53a 2661 return ret_val;
d3738bb8 2662 e1e_rphy(hw, HV_PM_CTRL, &data);
18dd2392 2663 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
d3738bb8 2664 if (ret_val)
5015e53a 2665 return ret_val;
d3738bb8
BA		 2666 } else {
2667 /* Write MAC register values back to h/w defaults */
2668 mac_reg = er32(FFLT_DBG);
2669 mac_reg &= ~(0xF << 14);
2670 ew32(FFLT_DBG, mac_reg);
2671
2672 mac_reg = er32(RCTL);
2673 mac_reg &= ~E1000_RCTL_SECRC;
a1ce6473 2674 ew32(RCTL, mac_reg);
d3738bb8
BA		 2675
2676 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2677 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2678 &data);
d3738bb8 2679 if (ret_val)
5015e53a 2680 return ret_val;
d3738bb8
BA		 2681 ret_val = e1000e_write_kmrn_reg(hw,
2682 E1000_KMRNCTRLSTA_CTRL_OFFSET,
18dd2392 2683 data & ~BIT(0));
d3738bb8 2684 if (ret_val)
5015e53a 2685 return ret_val;
d3738bb8 2686 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2687 E1000_KMRNCTRLSTA_HD_CTRL,
2688 &data);
d3738bb8 2689 if (ret_val)
5015e53a 2690 return ret_val;
d3738bb8
BA		 2691 data &= ~(0xF << 8);
2692 data |= (0xB << 8);
2693 ret_val = e1000e_write_kmrn_reg(hw,
2694 E1000_KMRNCTRLSTA_HD_CTRL,
2695 data);
2696 if (ret_val)
5015e53a 2697 return ret_val;
d3738bb8
BA		 2698
2699 /* Write PHY register values back to h/w defaults */
d3738bb8
BA		 2700 e1e_rphy(hw, PHY_REG(769, 23), &data);
2701 data &= ~(0x7F << 5);
2702 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2703 if (ret_val)
5015e53a 2704 return ret_val;
d3738bb8 2705 e1e_rphy(hw, PHY_REG(769, 16), &data);
18dd2392 2706 data |= BIT(13);
d3738bb8
BA		 2707 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2708 if (ret_val)
5015e53a 2709 return ret_val;
d3738bb8
BA		 2710 e1e_rphy(hw, PHY_REG(776, 20), &data);
2711 data &= ~(0x3FF << 2);
2712 data |= (0x8 << 2);
2713 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2714 if (ret_val)
5015e53a 2715 return ret_val;
d3738bb8
BA		 2716 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2717 if (ret_val)
5015e53a 2718 return ret_val;
d3738bb8 2719 e1e_rphy(hw, HV_PM_CTRL, &data);
18dd2392 2720 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
d3738bb8 2721 if (ret_val)
5015e53a 2722 return ret_val;
d3738bb8
BA		 2723 }
2724
2725 /* re-enable Rx path after enabling/disabling workaround */
18dd2392 2726 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
d3738bb8
BA		 2727}
2728
2729/**
b50f7bca
JB		 2730 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2731 * @hw: pointer to the HW structure
2732 *
2733 * A series of PHY workarounds to be done after every PHY reset.
d3738bb8
BA		 2734 **/
2735static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2736{
2737 s32 ret_val = 0;
2738
2739 if (hw->mac.type != e1000_pch2lan)
5015e53a 2740 return 0;
d3738bb8
BA		 2741
2742 /* Set MDIO slow mode before any other MDIO access */
2743 ret_val = e1000_set_mdio_slow_mode_hv(hw);
8e5ab42d
BA		 2744 if (ret_val)
2745 return ret_val;
d3738bb8 2746
4d24136c
BA		 2747 ret_val = hw->phy.ops.acquire(hw);
2748 if (ret_val)
5015e53a 2749 return ret_val;
4d24136c 2750 /* set MSE higher to enable link to stay up when noise is high */
4ddc48a9 2751 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
4d24136c
BA		 2752 if (ret_val)
2753 goto release;
2754 /* drop link after 5 times MSE threshold was reached */
4ddc48a9 2755 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
4d24136c
BA		 2756release:
2757 hw->phy.ops.release(hw);
2758
d3738bb8
BA		 2759 return ret_val;
2760}
2761
831bd2e6
BA		 2762/**
2763 * e1000_k1_gig_workaround_lv - K1 Si workaround
2764 * @hw: pointer to the HW structure
2765 *
77e61146
DE		 2766 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2767 * Disable K1 in 1000Mbps and 100Mbps
831bd2e6
BA		 2768 **/
2769static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2770{
2771 s32 ret_val = 0;
2772 u16 status_reg = 0;
831bd2e6
BA		 2773
2774 if (hw->mac.type != e1000_pch2lan)
5015e53a 2775 return 0;
831bd2e6 2776
77e61146 2777 /* Set K1 beacon duration based on 10Mbs speed */
831bd2e6
BA		 2778 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2779 if (ret_val)
5015e53a 2780 return ret_val;
831bd2e6
BA		 2781
2782 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2783 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
77e61146
DE		 2784 if (status_reg &
2785 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
36ceeb43
BA		 2786 u16 pm_phy_reg;
2787
77e61146 2788 /* LV 1G/100 Packet drop issue wa */
36ceeb43
BA		 2789 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2790 if (ret_val)
2791 return ret_val;
77e61146 2792 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
36ceeb43
BA		 2793 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2794 if (ret_val)
2795 return ret_val;
0ed013e2 2796 } else {
77e61146
DE		 2797 u32 mac_reg;
2798
2799 mac_reg = er32(FEXTNVM4);
2800 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
831bd2e6 2801 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
77e61146 2802 ew32(FEXTNVM4, mac_reg);
0ed013e2 2803 }
831bd2e6
BA		 2804 }
2805
831bd2e6
BA		 2806 return ret_val;
2807}
2808
605c82ba
BA		 2809/**
2810 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2811 * @hw: pointer to the HW structure
2812 * @gate: boolean set to true to gate, false to ungate
2813 *
2814 * Gate/ungate the automatic PHY configuration via hardware; perform
2815 * the configuration via software instead.
2816 **/
2817static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2818{
2819 u32 extcnf_ctrl;
2820
2fbe4526 2821 if (hw->mac.type < e1000_pch2lan)
605c82ba
BA		 2822 return;
2823
2824 extcnf_ctrl = er32(EXTCNF_CTRL);
2825
2826 if (gate)
2827 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2828 else
2829 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2830
2831 ew32(EXTCNF_CTRL, extcnf_ctrl);
605c82ba
BA		 2832}
2833
fc0c7760
BA		 2834/**
2835 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2836 * @hw: pointer to the HW structure
2837 *
2838 * Check the appropriate indication the MAC has finished configuring the
2839 * PHY after a software reset.
2840 **/
2841static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2842{
2843 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2844
2845 /* Wait for basic configuration completes before proceeding */
2846 do {
2847 data = er32(STATUS);
2848 data &= E1000_STATUS_LAN_INIT_DONE;
ce43a216 2849 usleep_range(100, 200);
fc0c7760
BA		 2850 } while ((!data) && --loop);
2851
e921eb1a 2852 /* If basic configuration is incomplete before the above loop
fc0c7760
BA		 2853 * count reaches 0, loading the configuration from NVM will
2854 * leave the PHY in a bad state possibly resulting in no link.
2855 */
2856 if (loop == 0)
3bb99fe2 2857 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 2858
2859 /* Clear the Init Done bit for the next init event */
2860 data = er32(STATUS);
2861 data &= ~E1000_STATUS_LAN_INIT_DONE;
2862 ew32(STATUS, data);
2863}
2864
bc7f75fa 2865/**
e98cac44 2866 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 2867 * @hw: pointer to the HW structure
bc7f75fa 2868 **/
e98cac44 2869static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 2870{
f523d211
BA		 2871 s32 ret_val = 0;
2872 u16 reg;
bc7f75fa 2873
44abd5c1 2874 if (hw->phy.ops.check_reset_block(hw))
5015e53a 2875 return 0;
fc0c7760 2876
5f3eed6f 2877 /* Allow time for h/w to get to quiescent state after reset */
ab6973ae 2878 usleep_range(10000, 11000);
5f3eed6f 2879
fddaa1af 2880 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 2881 switch (hw->mac.type) {
2882 case e1000_pchlan:
a4f58f54
BA		 2883 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2884 if (ret_val)
5015e53a 2885 return ret_val;
e98cac44 2886 break;
d3738bb8
BA		 2887 case e1000_pch2lan:
2888 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2889 if (ret_val)
5015e53a 2890 return ret_val;
d3738bb8 2891 break;
e98cac44
BA		 2892 default:
2893 break;
a4f58f54
BA		 2894 }
2895
3ebfc7c9
BA		 2896 /* Clear the host wakeup bit after lcd reset */
2897 if (hw->mac.type >= e1000_pchlan) {
2898 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2899 reg &= ~BM_WUC_HOST_WU_BIT;
2900 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2901 }
db2932ec 2902
f523d211
BA		 2903 /* Configure the LCD with the extended configuration region in NVM */
2904 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2905 if (ret_val)
5015e53a 2906 return ret_val;
bc7f75fa 2907
f523d211 2908 /* Configure the LCD with the OEM bits in NVM */
e98cac44 2909 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 2910
1effb45c
BA		 2911 if (hw->mac.type == e1000_pch2lan) {
2912 /* Ungate automatic PHY configuration on non-managed 82579 */
2913 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
ab6973ae 2914 usleep_range(10000, 11000);
1effb45c
BA		 2915 e1000_gate_hw_phy_config_ich8lan(hw, false);
2916 }
2917
2918 /* Set EEE LPI Update Timer to 200usec */
2919 ret_val = hw->phy.ops.acquire(hw);
2920 if (ret_val)
5015e53a 2921 return ret_val;
4ddc48a9
BA		 2922 ret_val = e1000_write_emi_reg_locked(hw,
2923 I82579_LPI_UPDATE_TIMER,
2924 0x1387);
1effb45c 2925 hw->phy.ops.release(hw);
605c82ba
BA		 2926 }
2927
e98cac44
BA		 2928 return ret_val;
2929}
2930
2931/**
2932 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2933 * @hw: pointer to the HW structure
2934 *
2935 * Resets the PHY
2936 * This is a function pointer entry point called by drivers
2937 * or other shared routines.
2938 **/
2939static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2940{
2941 s32 ret_val = 0;
2942
605c82ba
BA		 2943 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2944 if ((hw->mac.type == e1000_pch2lan) &&
2945 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2946 e1000_gate_hw_phy_config_ich8lan(hw, true);
2947
e98cac44
BA		 2948 ret_val = e1000e_phy_hw_reset_generic(hw);
2949 if (ret_val)
5015e53a 2950 return ret_val;
e98cac44 2951
5015e53a 2952 return e1000_post_phy_reset_ich8lan(hw);
bc7f75fa
AK		 2953}
2954
fa2ce13c
BA		 2955/**
2956 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2957 * @hw: pointer to the HW structure
2958 * @active: true to enable LPLU, false to disable
2959 *
2960 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2961 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2962 * the phy speed. This function will manually set the LPLU bit and restart
2963 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2964 * since it configures the same bit.
2965 **/
2966static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2967{
70806a7f 2968 s32 ret_val;
fa2ce13c
BA		 2969 u16 oem_reg;
2970
2971 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2972 if (ret_val)
5015e53a 2973 return ret_val;
fa2ce13c
BA		 2974
2975 if (active)
2976 oem_reg |= HV_OEM_BITS_LPLU;
2977 else
2978 oem_reg &= ~HV_OEM_BITS_LPLU;
2979
44abd5c1 2980 if (!hw->phy.ops.check_reset_block(hw))
464c85e3
BA		 2981 oem_reg |= HV_OEM_BITS_RESTART_AN;
2982
5015e53a 2983 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
fa2ce13c
BA		 2984}
2985
bc7f75fa
AK		 2986/**
2987 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2988 * @hw: pointer to the HW structure
564ea9bb 2989 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2990 *
2991 * Sets the LPLU D0 state according to the active flag. When
2992 * activating LPLU this function also disables smart speed
2993 * and vice versa. LPLU will not be activated unless the
2994 * device autonegotiation advertisement meets standards of
2995 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2996 * This is a function pointer entry point only called by
2997 * PHY setup routines.
2998 **/
2999static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3000{
3001 struct e1000_phy_info *phy = &hw->phy;
3002 u32 phy_ctrl;
3003 s32 ret_val = 0;
3004 u16 data;
3005
97ac8cae 3006 if (phy->type == e1000_phy_ife)
82607255 3007 return 0;
bc7f75fa
AK		 3008
3009 phy_ctrl = er32(PHY_CTRL);
3010
3011 if (active) {
3012 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3013 ew32(PHY_CTRL, phy_ctrl);
3014
60f1292f
BA		 3015 if (phy->type != e1000_phy_igp_3)
3016 return 0;
3017
e921eb1a 3018 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 3019 * any PHY registers
3020 */
60f1292f 3021 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 3022 e1000e_gig_downshift_workaround_ich8lan(hw);
3023
3024 /* When LPLU is enabled, we should disable SmartSpeed */
3025 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
7dbbe5d5
BA		 3026 if (ret_val)
3027 return ret_val;
bc7f75fa
AK		 3028 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3029 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3030 if (ret_val)
3031 return ret_val;
3032 } else {
3033 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3034 ew32(PHY_CTRL, phy_ctrl);
3035
60f1292f
BA		 3036 if (phy->type != e1000_phy_igp_3)
3037 return 0;
3038
e921eb1a 3039 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 3040 * during Dx states where the power conservation is most
3041 * important. During driver activity we should enable
ad68076e
BA		 3042 * SmartSpeed, so performance is maintained.
3043 */
bc7f75fa
AK		 3044 if (phy->smart_speed == e1000_smart_speed_on) {
3045 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 3046 &data);
bc7f75fa
AK		 3047 if (ret_val)
3048 return ret_val;
3049
3050 data |= IGP01E1000_PSCFR_SMART_SPEED;
3051 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 3052 data);
bc7f75fa
AK		 3053 if (ret_val)
3054 return ret_val;
3055 } else if (phy->smart_speed == e1000_smart_speed_off) {
3056 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 3057 &data);
bc7f75fa
AK		 3058 if (ret_val)
3059 return ret_val;
3060
3061 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3062 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 3063 data);
bc7f75fa
AK		 3064 if (ret_val)
3065 return ret_val;
3066 }
3067 }
3068
3069 return 0;
3070}
3071
3072/**
3073 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3074 * @hw: pointer to the HW structure
564ea9bb 3075 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 3076 *
3077 * Sets the LPLU D3 state according to the active flag. When
3078 * activating LPLU this function also disables smart speed
3079 * and vice versa. LPLU will not be activated unless the
3080 * device autonegotiation advertisement meets standards of
3081 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3082 * This is a function pointer entry point only called by
3083 * PHY setup routines.
3084 **/
3085static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3086{
3087 struct e1000_phy_info *phy = &hw->phy;
3088 u32 phy_ctrl;
d7eb3384 3089 s32 ret_val = 0;
bc7f75fa
AK		 3090 u16 data;
3091
3092 phy_ctrl = er32(PHY_CTRL);
3093
3094 if (!active) {
3095 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3096 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 3097
3098 if (phy->type != e1000_phy_igp_3)
3099 return 0;
3100
e921eb1a 3101 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 3102 * during Dx states where the power conservation is most
3103 * important. During driver activity we should enable
ad68076e
BA		 3104 * SmartSpeed, so performance is maintained.
3105 */
bc7f75fa 3106 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 3107 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3108 &data);
bc7f75fa
AK		 3109 if (ret_val)
3110 return ret_val;
3111
3112 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 3113 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3114 data);
bc7f75fa
AK		 3115 if (ret_val)
3116 return ret_val;
3117 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 3118 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3119 &data);
bc7f75fa
AK		 3120 if (ret_val)
3121 return ret_val;
3122
3123 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 3124 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3125 data);
bc7f75fa
AK		 3126 if (ret_val)
3127 return ret_val;
3128 }
3129 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3130 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3131 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3132 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3133 ew32(PHY_CTRL, phy_ctrl);
3134
60f1292f
BA		 3135 if (phy->type != e1000_phy_igp_3)
3136 return 0;
3137
e921eb1a 3138 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 3139 * any PHY registers
3140 */
60f1292f 3141 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 3142 e1000e_gig_downshift_workaround_ich8lan(hw);
3143
3144 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 3145 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 3146 if (ret_val)
3147 return ret_val;
3148
3149 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 3150 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 3151 }
3152
d7eb3384 3153 return ret_val;
bc7f75fa
AK		 3154}
3155
f4187b56
BA		 3156/**
3157 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3158 * @hw: pointer to the HW structure
3159 * @bank: pointer to the variable that returns the active bank
3160 *
3161 * Reads signature byte from the NVM using the flash access registers.
e243455d 3162 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 3163 **/
3164static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3165{
e243455d 3166 u32 eecd;
f4187b56 3167 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 3168 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3169 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
f3ed935d 3170 u32 nvm_dword = 0;
e243455d 3171 u8 sig_byte = 0;
f71dde6a 3172 s32 ret_val;
f4187b56 3173
e243455d 3174 switch (hw->mac.type) {
79849ebc 3175 case e1000_pch_spt:
c8744f44 3176 case e1000_pch_cnp:
fb776f5d 3177 case e1000_pch_tgp:
59e46688 3178 case e1000_pch_adp:
cc23f4f0 3179 case e1000_pch_mtp:
f3ed935d
RA		 3180 bank1_offset = nvm->flash_bank_size;
3181 act_offset = E1000_ICH_NVM_SIG_WORD;
3182
3183 /* set bank to 0 in case flash read fails */
3184 *bank = 0;
3185
3186 /* Check bank 0 */
3187 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3188 &nvm_dword);
3189 if (ret_val)
3190 return ret_val;
3191 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3192 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3193 E1000_ICH_NVM_SIG_VALUE) {
3194 *bank = 0;
79849ebc
DE		 3195 return 0;
3196 }
f3ed935d
RA		 3197
3198 /* Check bank 1 */
3199 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3200 bank1_offset,
3201 &nvm_dword);
3202 if (ret_val)
3203 return ret_val;
3204 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3205 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3206 E1000_ICH_NVM_SIG_VALUE) {
3207 *bank = 1;
3208 return 0;
3209 }
3210
3211 e_dbg("ERROR: No valid NVM bank present\n");
3212 return -E1000_ERR_NVM;
e243455d
BA		 3213 case e1000_ich8lan:
3214 case e1000_ich9lan:
3215 eecd = er32(EECD);
3216 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3217 E1000_EECD_SEC1VAL_VALID_MASK) {
3218 if (eecd & E1000_EECD_SEC1VAL)
3219 *bank = 1;
3220 else
3221 *bank = 0;
3222
3223 return 0;
3224 }
434f1392 3225 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
5463fce6 3226 fallthrough;
e243455d
BA		 3227 default:
3228 /* set bank to 0 in case flash read fails */
3229 *bank = 0;
3230
3231 /* Check bank 0 */
3232 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
f0ff4398 3233 &sig_byte);
e243455d
BA		 3234 if (ret_val)
3235 return ret_val;
3236 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3237 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 3238 *bank = 0;
e243455d
BA		 3239 return 0;
3240 }
f4187b56 3241
e243455d
BA		 3242 /* Check bank 1 */
3243 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
f0ff4398
BA		 3244 bank1_offset,
3245 &sig_byte);
e243455d
BA		 3246 if (ret_val)
3247 return ret_val;
3248 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3249 E1000_ICH_NVM_SIG_VALUE) {
3250 *bank = 1;
3251 return 0;
f4187b56 3252 }
e243455d 3253
3bb99fe2 3254 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 3255 return -E1000_ERR_NVM;
f4187b56 3256 }
f4187b56
BA		 3257}
3258
79849ebc
DE		 3259/**
3260 * e1000_read_nvm_spt - NVM access for SPT
3261 * @hw: pointer to the HW structure
3262 * @offset: The offset (in bytes) of the word(s) to read.
3263 * @words: Size of data to read in words.
3264 * @data: pointer to the word(s) to read at offset.
3265 *
3266 * Reads a word(s) from the NVM
3267 **/
3268static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3269 u16 *data)
3270{
3271 struct e1000_nvm_info *nvm = &hw->nvm;
3272 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3273 u32 act_offset;
3274 s32 ret_val = 0;
3275 u32 bank = 0;
3276 u32 dword = 0;
3277 u16 offset_to_read;
3278 u16 i;
3279
3280 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3281 (words == 0)) {
3282 e_dbg("nvm parameter(s) out of bounds\n");
3283 ret_val = -E1000_ERR_NVM;
3284 goto out;
3285 }
3286
3287 nvm->ops.acquire(hw);
3288
3289 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3290 if (ret_val) {
3291 e_dbg("Could not detect valid bank, assuming bank 0\n");
3292 bank = 0;
3293 }
3294
3295 act_offset = (bank) ? nvm->flash_bank_size : 0;
3296 act_offset += offset;
3297
3298 ret_val = 0;
3299
3300 for (i = 0; i < words; i += 2) {
3301 if (words - i == 1) {
3302 if (dev_spec->shadow_ram[offset + i].modified) {
3303 data[i] =
3304 dev_spec->shadow_ram[offset + i].value;
3305 } else {
3306 offset_to_read = act_offset + i -
3307 ((act_offset + i) % 2);
3308 ret_val =
3309 e1000_read_flash_dword_ich8lan(hw,
3310 offset_to_read,
3311 &dword);
3312 if (ret_val)
3313 break;
3314 if ((act_offset + i) % 2 == 0)
3315 data[i] = (u16)(dword & 0xFFFF);
3316 else
3317 data[i] = (u16)((dword >> 16) & 0xFFFF);
3318 }
3319 } else {
3320 offset_to_read = act_offset + i;
3321 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3322 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3323 ret_val =
3324 e1000_read_flash_dword_ich8lan(hw,
3325 offset_to_read,
3326 &dword);
3327 if (ret_val)
3328 break;
3329 }
3330 if (dev_spec->shadow_ram[offset + i].modified)
3331 data[i] =
3332 dev_spec->shadow_ram[offset + i].value;
3333 else
3334 data[i] = (u16)(dword & 0xFFFF);
3335 if (dev_spec->shadow_ram[offset + i].modified)
3336 data[i + 1] =
3337 dev_spec->shadow_ram[offset + i + 1].value;
3338 else
3339 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3340 }
3341 }
3342
3343 nvm->ops.release(hw);
3344
3345out:
3346 if (ret_val)
3347 e_dbg("NVM read error: %d\n", ret_val);
3348
3349 return ret_val;
3350}
3351
bc7f75fa
AK		 3352/**
3353 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3354 * @hw: pointer to the HW structure
3355 * @offset: The offset (in bytes) of the word(s) to read.
3356 * @words: Size of data to read in words
3357 * @data: Pointer to the word(s) to read at offset.
3358 *
3359 * Reads a word(s) from the NVM using the flash access registers.
3360 **/
3361static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3362 u16 *data)
3363{
3364 struct e1000_nvm_info *nvm = &hw->nvm;
3365 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3366 u32 act_offset;
148675a7 3367 s32 ret_val = 0;
f4187b56 3368 u32 bank = 0;
bc7f75fa
AK		 3369 u16 i, word;
3370
3371 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3372 (words == 0)) {
3bb99fe2 3373 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 3374 ret_val = -E1000_ERR_NVM;
3375 goto out;
bc7f75fa
AK		 3376 }
3377
94d8186a 3378 nvm->ops.acquire(hw);
bc7f75fa 3379
f4187b56 3380 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 3381 if (ret_val) {
3bb99fe2 3382 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 3383 bank = 0;
3384 }
f4187b56
BA		 3385
3386 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 3387 act_offset += offset;
3388
148675a7 3389 ret_val = 0;
bc7f75fa 3390 for (i = 0; i < words; i++) {
362e20ca
BA		 3391 if (dev_spec->shadow_ram[offset + i].modified) {
3392 data[i] = dev_spec->shadow_ram[offset + i].value;
bc7f75fa
AK		 3393 } else {
3394 ret_val = e1000_read_flash_word_ich8lan(hw,
3395 act_offset + i,
3396 &word);
3397 if (ret_val)
3398 break;
3399 data[i] = word;
3400 }
3401 }
3402
94d8186a 3403 nvm->ops.release(hw);
bc7f75fa 3404
e243455d
BA		 3405out:
3406 if (ret_val)
3bb99fe2 3407 e_dbg("NVM read error: %d\n", ret_val);
e243455d 3408
bc7f75fa
AK		 3409 return ret_val;
3410}
3411
3412/**
3413 * e1000_flash_cycle_init_ich8lan - Initialize flash
3414 * @hw: pointer to the HW structure
3415 *
3416 * This function does initial flash setup so that a new read/write/erase cycle
3417 * can be started.
3418 **/
3419static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3420{
3421 union ich8_hws_flash_status hsfsts;
3422 s32 ret_val = -E1000_ERR_NVM;
bc7f75fa
AK		 3423
3424 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3425
3426 /* Check if the flash descriptor is valid */
04499ec4 3427 if (!hsfsts.hsf_status.fldesvalid) {
434f1392 3428 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
bc7f75fa
AK		 3429 return -E1000_ERR_NVM;
3430 }
3431
3432 /* Clear FCERR and DAEL in hw status by writing 1 */
3433 hsfsts.hsf_status.flcerr = 1;
3434 hsfsts.hsf_status.dael = 1;
c8744f44 3435 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 3436 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3437 else
3438 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
bc7f75fa 3439
e921eb1a 3440 /* Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 3441 * bit to check against, in order to start a new cycle or
3442 * FDONE bit should be changed in the hardware so that it
489815ce 3443 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 3444 * indication whether a cycle is in progress or has been
3445 * completed.
3446 */
3447
04499ec4 3448 if (!hsfsts.hsf_status.flcinprog) {
e921eb1a 3449 /* There is no cycle running at present,
5ff5b664 3450 * so we can start a cycle.
ad68076e
BA		 3451 * Begin by setting Flash Cycle Done.
3452 */
bc7f75fa 3453 hsfsts.hsf_status.flcdone = 1;
c8744f44 3454 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 3455 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3456 else
3457 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
bc7f75fa
AK		 3458 ret_val = 0;
3459 } else {
f71dde6a 3460 s32 i;
90da0669 3461
e921eb1a 3462 /* Otherwise poll for sometime so the current
ad68076e
BA		 3463 * cycle has a chance to end before giving up.
3464 */
bc7f75fa 3465 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
c8243ee0 3466 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3467 if (!hsfsts.hsf_status.flcinprog) {
bc7f75fa
AK		 3468 ret_val = 0;
3469 break;
3470 }
3471 udelay(1);
3472 }
9e2d7657 3473 if (!ret_val) {
e921eb1a 3474 /* Successful in waiting for previous cycle to timeout,
ad68076e
BA		 3475 * now set the Flash Cycle Done.
3476 */
bc7f75fa 3477 hsfsts.hsf_status.flcdone = 1;
c8744f44 3478 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 3479 ew32flash(ICH_FLASH_HSFSTS,
3480 hsfsts.regval & 0xFFFF);
3481 else
3482 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
bc7f75fa 3483 } else {
2c73e1fe 3484 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 3485 }
3486 }
3487
3488 return ret_val;
3489}
3490
3491/**
3492 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3493 * @hw: pointer to the HW structure
3494 * @timeout: maximum time to wait for completion
3495 *
3496 * This function starts a flash cycle and waits for its completion.
3497 **/
3498static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3499{
3500 union ich8_hws_flash_ctrl hsflctl;
3501 union ich8_hws_flash_status hsfsts;
bc7f75fa
AK		 3502 u32 i = 0;
3503
3504 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
c8744f44 3505 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 3506 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3507 else
3508 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
bc7f75fa 3509 hsflctl.hsf_ctrl.flcgo = 1;
79849ebc 3510
c8744f44 3511 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 3512 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3513 else
3514 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
bc7f75fa
AK		 3515
3516 /* wait till FDONE bit is set to 1 */
3517 do {
3518 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3519 if (hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 3520 break;
3521 udelay(1);
3522 } while (i++ < timeout);
3523
04499ec4 3524 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 3525 return 0;
3526
55920b5e 3527 return -E1000_ERR_NVM;
bc7f75fa
AK		 3528}
3529
79849ebc
DE		 3530/**
3531 * e1000_read_flash_dword_ich8lan - Read dword from flash
3532 * @hw: pointer to the HW structure
3533 * @offset: offset to data location
3534 * @data: pointer to the location for storing the data
3535 *
3536 * Reads the flash dword at offset into data. Offset is converted
3537 * to bytes before read.
3538 **/
3539static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3540 u32 *data)
3541{
3542 /* Must convert word offset into bytes. */
3543 offset <<= 1;
3544 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3545}
3546
bc7f75fa
AK		 3547/**
3548 * e1000_read_flash_word_ich8lan - Read word from flash
3549 * @hw: pointer to the HW structure
3550 * @offset: offset to data location
3551 * @data: pointer to the location for storing the data
3552 *
3553 * Reads the flash word at offset into data. Offset is converted
3554 * to bytes before read.
3555 **/
3556static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3557 u16 *data)
3558{
3559 /* Must convert offset into bytes. */
3560 offset <<= 1;
3561
3562 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3563}
3564
f4187b56
BA		 3565/**
3566 * e1000_read_flash_byte_ich8lan - Read byte from flash
3567 * @hw: pointer to the HW structure
3568 * @offset: The offset of the byte to read.
3569 * @data: Pointer to a byte to store the value read.
3570 *
3571 * Reads a single byte from the NVM using the flash access registers.
3572 **/
3573static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3574 u8 *data)
3575{
3576 s32 ret_val;
3577 u16 word = 0;
3578
79849ebc
DE		 3579 /* In SPT, only 32 bits access is supported,
3580 * so this function should not be called.
3581 */
c8744f44 3582 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 3583 return -E1000_ERR_NVM;
3584 else
3585 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3586
f4187b56
BA		 3587 if (ret_val)
3588 return ret_val;
3589
3590 *data = (u8)word;
3591
3592 return 0;
3593}
3594
bc7f75fa
AK		 3595/**
3596 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3597 * @hw: pointer to the HW structure
3598 * @offset: The offset (in bytes) of the byte or word to read.
3599 * @size: Size of data to read, 1=byte 2=word
3600 * @data: Pointer to the word to store the value read.
3601 *
3602 * Reads a byte or word from the NVM using the flash access registers.
3603 **/
3604static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3605 u8 size, u16 *data)
3606{
3607 union ich8_hws_flash_status hsfsts;
3608 union ich8_hws_flash_ctrl hsflctl;
3609 u32 flash_linear_addr;
3610 u32 flash_data = 0;
3611 s32 ret_val = -E1000_ERR_NVM;
3612 u8 count = 0;
3613
e80bd1d1 3614 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
bc7f75fa
AK		 3615 return -E1000_ERR_NVM;
3616
f0ff4398
BA		 3617 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3618 hw->nvm.flash_base_addr);
bc7f75fa
AK		 3619
3620 do {
3621 udelay(1);
3622 /* Steps */
3623 ret_val = e1000_flash_cycle_init_ich8lan(hw);
9e2d7657 3624 if (ret_val)
bc7f75fa
AK		 3625 break;
3626
3627 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3628 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3629 hsflctl.hsf_ctrl.fldbcount = size - 1;
3630 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3631 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3632
3633 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3634
17e813ec
BA		 3635 ret_val =
3636 e1000_flash_cycle_ich8lan(hw,
3637 ICH_FLASH_READ_COMMAND_TIMEOUT);
bc7f75fa 3638
e921eb1a 3639 /* Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 3640 * and try the whole sequence a few more times, else
3641 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 3642 * least significant byte first msb to lsb
3643 */
9e2d7657 3644 if (!ret_val) {
bc7f75fa 3645 flash_data = er32flash(ICH_FLASH_FDATA0);
b1cdfead 3646 if (size == 1)
bc7f75fa 3647 *data = (u8)(flash_data & 0x000000FF);
b1cdfead 3648 else if (size == 2)
bc7f75fa 3649 *data = (u16)(flash_data & 0x0000FFFF);
bc7f75fa
AK		 3650 break;
3651 } else {
e921eb1a 3652 /* If we've gotten here, then things are probably
bc7f75fa
AK		 3653 * completely hosed, but if the error condition is
3654 * detected, it won't hurt to give it another try...
3655 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3656 */
3657 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3658 if (hsfsts.hsf_status.flcerr) {
bc7f75fa
AK		 3659 /* Repeat for some time before giving up. */
3660 continue;
04499ec4 3661 } else if (!hsfsts.hsf_status.flcdone) {
434f1392 3662 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 3663 break;
3664 }
3665 }
3666 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3667
3668 return ret_val;
3669}
3670
79849ebc
DE		 3671/**
3672 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3673 * @hw: pointer to the HW structure
3674 * @offset: The offset (in bytes) of the dword to read.
3675 * @data: Pointer to the dword to store the value read.
3676 *
3677 * Reads a byte or word from the NVM using the flash access registers.
3678 **/
3679
3680static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3681 u32 *data)
3682{
3683 union ich8_hws_flash_status hsfsts;
3684 union ich8_hws_flash_ctrl hsflctl;
3685 u32 flash_linear_addr;
3686 s32 ret_val = -E1000_ERR_NVM;
3687 u8 count = 0;
3688
c8744f44 3689 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
79849ebc
DE		 3690 return -E1000_ERR_NVM;
3691 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3692 hw->nvm.flash_base_addr);
3693
3694 do {
3695 udelay(1);
3696 /* Steps */
3697 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3698 if (ret_val)
3699 break;
3700 /* In SPT, This register is in Lan memory space, not flash.
3701 * Therefore, only 32 bit access is supported
3702 */
3703 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3704
3705 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3706 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3707 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3708 /* In SPT, This register is in Lan memory space, not flash.
3709 * Therefore, only 32 bit access is supported
3710 */
3711 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3712 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3713
3714 ret_val =
3715 e1000_flash_cycle_ich8lan(hw,
3716 ICH_FLASH_READ_COMMAND_TIMEOUT);
3717
3718 /* Check if FCERR is set to 1, if set to 1, clear it
3719 * and try the whole sequence a few more times, else
3720 * read in (shift in) the Flash Data0, the order is
3721 * least significant byte first msb to lsb
3722 */
3723 if (!ret_val) {
3724 *data = er32flash(ICH_FLASH_FDATA0);
3725 break;
3726 } else {
3727 /* If we've gotten here, then things are probably
3728 * completely hosed, but if the error condition is
3729 * detected, it won't hurt to give it another try...
3730 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3731 */
3732 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3733 if (hsfsts.hsf_status.flcerr) {
3734 /* Repeat for some time before giving up. */
3735 continue;
3736 } else if (!hsfsts.hsf_status.flcdone) {
3737 e_dbg("Timeout error - flash cycle did not complete.\n");
3738 break;
3739 }
3740 }
3741 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3742
3743 return ret_val;
3744}
3745
bc7f75fa
AK		 3746/**
3747 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3748 * @hw: pointer to the HW structure
3749 * @offset: The offset (in bytes) of the word(s) to write.
3750 * @words: Size of data to write in words
3751 * @data: Pointer to the word(s) to write at offset.
3752 *
3753 * Writes a byte or word to the NVM using the flash access registers.
3754 **/
3755static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3756 u16 *data)
3757{
3758 struct e1000_nvm_info *nvm = &hw->nvm;
3759 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 3760 u16 i;
3761
3762 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3763 (words == 0)) {
3bb99fe2 3764 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 3765 return -E1000_ERR_NVM;
3766 }
3767
94d8186a 3768 nvm->ops.acquire(hw);
ca15df58 3769
bc7f75fa 3770 for (i = 0; i < words; i++) {
362e20ca
BA		 3771 dev_spec->shadow_ram[offset + i].modified = true;
3772 dev_spec->shadow_ram[offset + i].value = data[i];
bc7f75fa
AK		 3773 }
3774
94d8186a 3775 nvm->ops.release(hw);
ca15df58 3776
bc7f75fa
AK		 3777 return 0;
3778}
3779
3780/**
79849ebc 3781 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
bc7f75fa
AK		 3782 * @hw: pointer to the HW structure
3783 *
3784 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3785 * which writes the checksum to the shadow ram. The changes in the shadow
3786 * ram are then committed to the EEPROM by processing each bank at a time
3787 * checking for the modified bit and writing only the pending changes.
489815ce 3788 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 3789 * future writes.
3790 **/
79849ebc 3791static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
bc7f75fa
AK		 3792{
3793 struct e1000_nvm_info *nvm = &hw->nvm;
3794 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 3795 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa 3796 s32 ret_val;
79849ebc 3797 u32 dword = 0;
bc7f75fa
AK		 3798
3799 ret_val = e1000e_update_nvm_checksum_generic(hw);
3800 if (ret_val)
e243455d 3801 goto out;
bc7f75fa
AK		 3802
3803 if (nvm->type != e1000_nvm_flash_sw)
e243455d 3804 goto out;
bc7f75fa 3805
94d8186a 3806 nvm->ops.acquire(hw);
bc7f75fa 3807
e921eb1a 3808 /* We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 3809 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 3810 * is going to be written
3811 */
e80bd1d1 3812 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 3813 if (ret_val) {
3bb99fe2 3814 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 3815 bank = 0;
e243455d 3816 }
f4187b56
BA		 3817
3818 if (bank == 0) {
bc7f75fa
AK		 3819 new_bank_offset = nvm->flash_bank_size;
3820 old_bank_offset = 0;
e243455d 3821 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 3822 if (ret_val)
3823 goto release;
bc7f75fa
AK		 3824 } else {
3825 old_bank_offset = nvm->flash_bank_size;
3826 new_bank_offset = 0;
e243455d 3827 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 3828 if (ret_val)
3829 goto release;
bc7f75fa 3830 }
79849ebc 3831 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
e921eb1a 3832 /* Determine whether to write the value stored
bc7f75fa 3833 * in the other NVM bank or a modified value stored
ad68076e
BA		 3834 * in the shadow RAM
3835 */
79849ebc
DE		 3836 ret_val = e1000_read_flash_dword_ich8lan(hw,
3837 i + old_bank_offset,
3838 &dword);
3839
3840 if (dev_spec->shadow_ram[i].modified) {
3841 dword &= 0xffff0000;
3842 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3843 }
3844 if (dev_spec->shadow_ram[i + 1].modified) {
3845 dword &= 0x0000ffff;
3846 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3847 << 16);
3848 }
3849 if (ret_val)
3850 break;
3851
3852 /* If the word is 0x13, then make sure the signature bits
3853 * (15:14) are 11b until the commit has completed.
3854 * This will allow us to write 10b which indicates the
3855 * signature is valid. We want to do this after the write
3856 * has completed so that we don't mark the segment valid
3857 * while the write is still in progress
3858 */
3859 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3860 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3861
3862 /* Convert offset to bytes. */
3863 act_offset = (i + new_bank_offset) << 1;
3864
3865 usleep_range(100, 200);
3866
3867 /* Write the data to the new bank. Offset in words */
3868 act_offset = i + new_bank_offset;
3869 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3870 dword);
3871 if (ret_val)
3872 break;
3873 }
3874
3875 /* Don't bother writing the segment valid bits if sector
3876 * programming failed.
3877 */
3878 if (ret_val) {
3879 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3880 e_dbg("Flash commit failed.\n");
3881 goto release;
3882 }
3883
3884 /* Finally validate the new segment by setting bit 15:14
3885 * to 10b in word 0x13 , this can be done without an
3886 * erase as well since these bits are 11 to start with
3887 * and we need to change bit 14 to 0b
3888 */
3889 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3890
3891 /*offset in words but we read dword */
3892 --act_offset;
3893 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3894
3895 if (ret_val)
3896 goto release;
3897
3898 dword &= 0xBFFFFFFF;
3899 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3900
3901 if (ret_val)
3902 goto release;
3903
3904 /* And invalidate the previously valid segment by setting
3905 * its signature word (0x13) high_byte to 0b. This can be
3906 * done without an erase because flash erase sets all bits
3907 * to 1's. We can write 1's to 0's without an erase
3908 */
3909 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3910
3911 /* offset in words but we read dword */
3912 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3913 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3914
3915 if (ret_val)
3916 goto release;
3917
3918 dword &= 0x00FFFFFF;
3919 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3920
3921 if (ret_val)
3922 goto release;
3923
3924 /* Great! Everything worked, we can now clear the cached entries. */
3925 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3926 dev_spec->shadow_ram[i].modified = false;
3927 dev_spec->shadow_ram[i].value = 0xFFFF;
3928 }
3929
3930release:
3931 nvm->ops.release(hw);
3932
3933 /* Reload the EEPROM, or else modifications will not appear
3934 * until after the next adapter reset.
3935 */
3936 if (!ret_val) {
3937 nvm->ops.reload(hw);
ab6973ae 3938 usleep_range(10000, 11000);
79849ebc
DE		 3939 }
3940
3941out:
3942 if (ret_val)
3943 e_dbg("NVM update error: %d\n", ret_val);
3944
3945 return ret_val;
3946}
3947
3948/**
3949 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3950 * @hw: pointer to the HW structure
3951 *
3952 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3953 * which writes the checksum to the shadow ram. The changes in the shadow
3954 * ram are then committed to the EEPROM by processing each bank at a time
3955 * checking for the modified bit and writing only the pending changes.
3956 * After a successful commit, the shadow ram is cleared and is ready for
3957 * future writes.
3958 **/
3959static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3960{
3961 struct e1000_nvm_info *nvm = &hw->nvm;
3962 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3963 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3964 s32 ret_val;
3965 u16 data = 0;
3966
3967 ret_val = e1000e_update_nvm_checksum_generic(hw);
3968 if (ret_val)
3969 goto out;
3970
3971 if (nvm->type != e1000_nvm_flash_sw)
3972 goto out;
3973
3974 nvm->ops.acquire(hw);
3975
3976 /* We're writing to the opposite bank so if we're on bank 1,
3977 * write to bank 0 etc. We also need to erase the segment that
3978 * is going to be written
3979 */
3980 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3981 if (ret_val) {
3982 e_dbg("Could not detect valid bank, assuming bank 0\n");
3983 bank = 0;
3984 }
3985
3986 if (bank == 0) {
3987 new_bank_offset = nvm->flash_bank_size;
3988 old_bank_offset = 0;
3989 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3990 if (ret_val)
3991 goto release;
3992 } else {
3993 old_bank_offset = nvm->flash_bank_size;
3994 new_bank_offset = 0;
3995 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3996 if (ret_val)
3997 goto release;
3998 }
3999 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
bc7f75fa
AK		 4000 if (dev_spec->shadow_ram[i].modified) {
4001 data = dev_spec->shadow_ram[i].value;
4002 } else {
e243455d 4003 ret_val = e1000_read_flash_word_ich8lan(hw, i +
f0ff4398
BA		 4004 old_bank_offset,
4005 &data);
e243455d
BA		 4006 if (ret_val)
4007 break;
bc7f75fa
AK		 4008 }
4009
e921eb1a 4010 /* If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 4011 * (15:14) are 11b until the commit has completed.
4012 * This will allow us to write 10b which indicates the
4013 * signature is valid. We want to do this after the write
4014 * has completed so that we don't mark the segment valid
ad68076e
BA		 4015 * while the write is still in progress
4016 */
bc7f75fa
AK		 4017 if (i == E1000_ICH_NVM_SIG_WORD)
4018 data |= E1000_ICH_NVM_SIG_MASK;
4019
4020 /* Convert offset to bytes. */
4021 act_offset = (i + new_bank_offset) << 1;
4022
ce43a216 4023 usleep_range(100, 200);
bc7f75fa
AK		 4024 /* Write the bytes to the new bank. */
4025 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4026 act_offset,
4027 (u8)data);
4028 if (ret_val)
4029 break;
4030
ce43a216 4031 usleep_range(100, 200);
bc7f75fa 4032 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
f0ff4398
BA		 4033 act_offset + 1,
4034 (u8)(data >> 8));
bc7f75fa
AK		 4035 if (ret_val)
4036 break;
4037 }
4038
e921eb1a 4039 /* Don't bother writing the segment valid bits if sector
ad68076e
BA		 4040 * programming failed.
4041 */
bc7f75fa 4042 if (ret_val) {
4a770358 4043 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 4044 e_dbg("Flash commit failed.\n");
9c5e209d 4045 goto release;
bc7f75fa
AK		 4046 }
4047
e921eb1a 4048 /* Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 4049 * to 10b in word 0x13 , this can be done without an
4050 * erase as well since these bits are 11 to start with
ad68076e
BA		 4051 * and we need to change bit 14 to 0b
4052 */
bc7f75fa 4053 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 4054 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 4055 if (ret_val)
4056 goto release;
4057
bc7f75fa
AK		 4058 data &= 0xBFFF;
4059 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4060 act_offset * 2 + 1,
4061 (u8)(data >> 8));
9c5e209d
BA		 4062 if (ret_val)
4063 goto release;
bc7f75fa 4064
e921eb1a 4065 /* And invalidate the previously valid segment by setting
bc7f75fa
AK		 4066 * its signature word (0x13) high_byte to 0b. This can be
4067 * done without an erase because flash erase sets all bits
ad68076e
BA		 4068 * to 1's. We can write 1's to 0's without an erase
4069 */
bc7f75fa
AK		 4070 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4071 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 4072 if (ret_val)
4073 goto release;
bc7f75fa
AK		 4074
4075 /* Great! Everything worked, we can now clear the cached entries. */
4076 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 4077 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 4078 dev_spec->shadow_ram[i].value = 0xFFFF;
4079 }
4080
9c5e209d 4081release:
94d8186a 4082 nvm->ops.release(hw);
bc7f75fa 4083
e921eb1a 4084 /* Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 4085 * until after the next adapter reset.
4086 */
9c5e209d 4087 if (!ret_val) {
e85e3639 4088 nvm->ops.reload(hw);
ab6973ae 4089 usleep_range(10000, 11000);
9c5e209d 4090 }
bc7f75fa 4091
e243455d
BA		 4092out:
4093 if (ret_val)
3bb99fe2 4094 e_dbg("NVM update error: %d\n", ret_val);
e243455d 4095
bc7f75fa
AK		 4096 return ret_val;
4097}
4098
4099/**
4100 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4101 * @hw: pointer to the HW structure
4102 *
4103 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4104 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4105 * calculated, in which case we need to calculate the checksum and set bit 6.
4106 **/
4107static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4108{
4109 s32 ret_val;
4110 u16 data;
1cc7a3a1
BA		 4111 u16 word;
4112 u16 valid_csum_mask;
bc7f75fa 4113
1cc7a3a1
BA		 4114 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4115 * the checksum needs to be fixed. This bit is an indication that
4116 * the NVM was prepared by OEM software and did not calculate
4117 * the checksum...a likely scenario.
bc7f75fa 4118 */
1cc7a3a1
BA		 4119 switch (hw->mac.type) {
4120 case e1000_pch_lpt:
79849ebc 4121 case e1000_pch_spt:
c8744f44 4122 case e1000_pch_cnp:
fb776f5d 4123 case e1000_pch_tgp:
59e46688 4124 case e1000_pch_adp:
cc23f4f0 4125 case e1000_pch_mtp:
1cc7a3a1
BA		 4126 word = NVM_COMPAT;
4127 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4128 break;
4129 default:
4130 word = NVM_FUTURE_INIT_WORD1;
4131 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4132 break;
4133 }
4134
4135 ret_val = e1000_read_nvm(hw, word, 1, &data);
bc7f75fa
AK		 4136 if (ret_val)
4137 return ret_val;
4138
1cc7a3a1 4139 if (!(data & valid_csum_mask)) {
de79f442
SN		 4140 e_dbg("NVM Checksum Invalid\n");
4141
4142 if (hw->mac.type < e1000_pch_cnp) {
4143 data |= valid_csum_mask;
4144 ret_val = e1000_write_nvm(hw, word, 1, &data);
4145 if (ret_val)
4146 return ret_val;
4147 ret_val = e1000e_update_nvm_checksum(hw);
4148 if (ret_val)
4149 return ret_val;
4150 }
bc7f75fa
AK		 4151 }
4152
4153 return e1000e_validate_nvm_checksum_generic(hw);
4154}
4155
4a770358
BA		 4156/**
4157 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4158 * @hw: pointer to the HW structure
4159 *
4160 * To prevent malicious write/erase of the NVM, set it to be read-only
4161 * so that the hardware ignores all write/erase cycles of the NVM via
4162 * the flash control registers. The shadow-ram copy of the NVM will
4163 * still be updated, however any updates to this copy will not stick
4164 * across driver reloads.
4165 **/
4166void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4167{
ca15df58 4168 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 4169 union ich8_flash_protected_range pr0;
4170 union ich8_hws_flash_status hsfsts;
4171 u32 gfpreg;
4a770358 4172
94d8186a 4173 nvm->ops.acquire(hw);
4a770358
BA		 4174
4175 gfpreg = er32flash(ICH_FLASH_GFPREG);
4176
4177 /* Write-protect GbE Sector of NVM */
4178 pr0.regval = er32flash(ICH_FLASH_PR0);
4179 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4180 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4181 pr0.range.wpe = true;
4182 ew32flash(ICH_FLASH_PR0, pr0.regval);
4183
e921eb1a 4184 /* Lock down a subset of GbE Flash Control Registers, e.g.
4a770358
BA		 4185 * PR0 to prevent the write-protection from being lifted.
4186 * Once FLOCKDN is set, the registers protected by it cannot
4187 * be written until FLOCKDN is cleared by a hardware reset.
4188 */
4189 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4190 hsfsts.hsf_status.flockdn = true;
4191 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4192
94d8186a 4193 nvm->ops.release(hw);
4a770358
BA		 4194}
4195
bc7f75fa
AK		 4196/**
4197 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4198 * @hw: pointer to the HW structure
4199 * @offset: The offset (in bytes) of the byte/word to read.
4200 * @size: Size of data to read, 1=byte 2=word
4201 * @data: The byte(s) to write to the NVM.
4202 *
4203 * Writes one/two bytes to the NVM using the flash access registers.
4204 **/
4205static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4206 u8 size, u16 data)
4207{
4208 union ich8_hws_flash_status hsfsts;
4209 union ich8_hws_flash_ctrl hsflctl;
4210 u32 flash_linear_addr;
4211 u32 flash_data = 0;
4212 s32 ret_val;
4213 u8 count = 0;
4214
c8744f44 4215 if (hw->mac.type >= e1000_pch_spt) {
79849ebc
DE		 4216 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4217 return -E1000_ERR_NVM;
4218 } else {
4219 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4220 return -E1000_ERR_NVM;
4221 }
bc7f75fa 4222
f0ff4398
BA		 4223 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4224 hw->nvm.flash_base_addr);
bc7f75fa
AK		 4225
4226 do {
4227 udelay(1);
4228 /* Steps */
4229 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4230 if (ret_val)
4231 break;
79849ebc
DE		 4232 /* In SPT, This register is in Lan memory space, not
4233 * flash. Therefore, only 32 bit access is supported
4234 */
c8744f44 4235 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 4236 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4237 else
4238 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
bc7f75fa 4239
bc7f75fa 4240 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
362e20ca 4241 hsflctl.hsf_ctrl.fldbcount = size - 1;
bc7f75fa 4242 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
79849ebc
DE		 4243 /* In SPT, This register is in Lan memory space,
4244 * not flash. Therefore, only 32 bit access is
4245 * supported
4246 */
c8744f44 4247 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 4248 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4249 else
4250 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
bc7f75fa
AK		 4251
4252 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4253
4254 if (size == 1)
4255 flash_data = (u32)data & 0x00FF;
4256 else
4257 flash_data = (u32)data;
4258
4259 ew32flash(ICH_FLASH_FDATA0, flash_data);
4260
e921eb1a 4261 /* check if FCERR is set to 1 , if set to 1, clear it
ad68076e
BA		 4262 * and try the whole sequence a few more times else done
4263 */
17e813ec
BA		 4264 ret_val =
4265 e1000_flash_cycle_ich8lan(hw,
4266 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
bc7f75fa
AK		 4267 if (!ret_val)
4268 break;
4269
e921eb1a 4270 /* If we're here, then things are most likely
bc7f75fa
AK		 4271 * completely hosed, but if the error condition
4272 * is detected, it won't hurt to give it another
4273 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4274 */
4275 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 4276 if (hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 4277 /* Repeat for some time before giving up. */
4278 continue;
04499ec4 4279 if (!hsfsts.hsf_status.flcdone) {
434f1392 4280 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 4281 break;
4282 }
4283 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4284
4285 return ret_val;
4286}
4287
79849ebc
DE		 4288/**
4289* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4290* @hw: pointer to the HW structure
4291* @offset: The offset (in bytes) of the dwords to read.
4292* @data: The 4 bytes to write to the NVM.
4293*
4294* Writes one/two/four bytes to the NVM using the flash access registers.
4295**/
4296static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4297 u32 data)
4298{
4299 union ich8_hws_flash_status hsfsts;
4300 union ich8_hws_flash_ctrl hsflctl;
4301 u32 flash_linear_addr;
4302 s32 ret_val;
4303 u8 count = 0;
4304
c8744f44 4305 if (hw->mac.type >= e1000_pch_spt) {
79849ebc
DE		 4306 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4307 return -E1000_ERR_NVM;
4308 }
4309 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4310 hw->nvm.flash_base_addr);
4311 do {
4312 udelay(1);
4313 /* Steps */
4314 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4315 if (ret_val)
4316 break;
4317
4318 /* In SPT, This register is in Lan memory space, not
4319 * flash. Therefore, only 32 bit access is supported
4320 */
c8744f44 4321 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 4322 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4323 >> 16;
4324 else
4325 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4326
4327 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4328 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4329
4330 /* In SPT, This register is in Lan memory space,
4331 * not flash. Therefore, only 32 bit access is
4332 * supported
4333 */
c8744f44 4334 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 4335 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4336 else
4337 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4338
4339 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4340
4341 ew32flash(ICH_FLASH_FDATA0, data);
4342
4343 /* check if FCERR is set to 1 , if set to 1, clear it
4344 * and try the whole sequence a few more times else done
4345 */
4346 ret_val =
4347 e1000_flash_cycle_ich8lan(hw,
4348 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4349
4350 if (!ret_val)
4351 break;
4352
4353 /* If we're here, then things are most likely
4354 * completely hosed, but if the error condition
4355 * is detected, it won't hurt to give it another
4356 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4357 */
4358 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4359
4360 if (hsfsts.hsf_status.flcerr)
4361 /* Repeat for some time before giving up. */
4362 continue;
4363 if (!hsfsts.hsf_status.flcdone) {
4364 e_dbg("Timeout error - flash cycle did not complete.\n");
4365 break;
4366 }
4367 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4368
4369 return ret_val;
4370}
4371
bc7f75fa
AK		 4372/**
4373 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4374 * @hw: pointer to the HW structure
4375 * @offset: The index of the byte to read.
4376 * @data: The byte to write to the NVM.
4377 *
4378 * Writes a single byte to the NVM using the flash access registers.
4379 **/
4380static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4381 u8 data)
4382{
4383 u16 word = (u16)data;
4384
4385 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4386}
4387
79849ebc
DE		 4388/**
4389* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4390* @hw: pointer to the HW structure
4391* @offset: The offset of the word to write.
4392* @dword: The dword to write to the NVM.
4393*
4394* Writes a single dword to the NVM using the flash access registers.
4395* Goes through a retry algorithm before giving up.
4396**/
4397static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4398 u32 offset, u32 dword)
4399{
4400 s32 ret_val;
4401 u16 program_retries;
4402
4403 /* Must convert word offset into bytes. */
4404 offset <<= 1;
4405 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4406
4407 if (!ret_val)
4408 return ret_val;
4409 for (program_retries = 0; program_retries < 100; program_retries++) {
4410 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4411 usleep_range(100, 200);
4412 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4413 if (!ret_val)
4414 break;
4415 }
4416 if (program_retries == 100)
4417 return -E1000_ERR_NVM;
4418
4419 return 0;
4420}
4421
bc7f75fa
AK		 4422/**
4423 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4424 * @hw: pointer to the HW structure
4425 * @offset: The offset of the byte to write.
4426 * @byte: The byte to write to the NVM.
4427 *
4428 * Writes a single byte to the NVM using the flash access registers.
4429 * Goes through a retry algorithm before giving up.
4430 **/
4431static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4432 u32 offset, u8 byte)
4433{
4434 s32 ret_val;
4435 u16 program_retries;
4436
4437 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4438 if (!ret_val)
4439 return ret_val;
4440
4441 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 4442 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
ce43a216 4443 usleep_range(100, 200);
bc7f75fa
AK		 4444 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4445 if (!ret_val)
4446 break;
4447 }
4448 if (program_retries == 100)
4449 return -E1000_ERR_NVM;
4450
4451 return 0;
4452}
4453
4454/**
4455 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4456 * @hw: pointer to the HW structure
4457 * @bank: 0 for first bank, 1 for second bank, etc.
4458 *
4459 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4460 * bank N is 4096 * N + flash_reg_addr.
4461 **/
4462static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4463{
4464 struct e1000_nvm_info *nvm = &hw->nvm;
4465 union ich8_hws_flash_status hsfsts;
4466 union ich8_hws_flash_ctrl hsflctl;
4467 u32 flash_linear_addr;
4468 /* bank size is in 16bit words - adjust to bytes */
4469 u32 flash_bank_size = nvm->flash_bank_size * 2;
4470 s32 ret_val;
4471 s32 count = 0;
a708dd88 4472 s32 j, iteration, sector_size;
bc7f75fa
AK		 4473
4474 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4475
e921eb1a 4476 /* Determine HW Sector size: Read BERASE bits of hw flash status
ad68076e
BA		 4477 * register
4478 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 4479 * consecutive sectors. The start index for the nth Hw sector
4480 * can be calculated as = bank * 4096 + n * 256
4481 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4482 * The start index for the nth Hw sector can be calculated
4483 * as = bank * 4096
4484 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4485 * (ich9 only, otherwise error condition)
4486 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4487 */
4488 switch (hsfsts.hsf_status.berasesz) {
4489 case 0:
4490 /* Hw sector size 256 */
4491 sector_size = ICH_FLASH_SEG_SIZE_256;
4492 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4493 break;
4494 case 1:
4495 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 4496 iteration = 1;
bc7f75fa
AK		 4497 break;
4498 case 2:
148675a7
BA		 4499 sector_size = ICH_FLASH_SEG_SIZE_8K;
4500 iteration = 1;
bc7f75fa
AK		 4501 break;
4502 case 3:
4503 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 4504 iteration = 1;
bc7f75fa
AK		 4505 break;
4506 default:
4507 return -E1000_ERR_NVM;
4508 }
4509
4510 /* Start with the base address, then add the sector offset. */
4511 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 4512 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa 4513
53aa82da 4514 for (j = 0; j < iteration; j++) {
bc7f75fa 4515 do {
17e813ec
BA		 4516 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4517
bc7f75fa
AK		 4518 /* Steps */
4519 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4520 if (ret_val)
4521 return ret_val;
4522
e921eb1a 4523 /* Write a value 11 (block Erase) in Flash
ad68076e
BA		 4524 * Cycle field in hw flash control
4525 */
c8744f44 4526 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 4527 hsflctl.regval =
4528 er32flash(ICH_FLASH_HSFSTS) >> 16;
4529 else
4530 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4531
bc7f75fa 4532 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
c8744f44 4533 if (hw->mac.type >= e1000_pch_spt)
79849ebc
DE		 4534 ew32flash(ICH_FLASH_HSFSTS,
4535 hsflctl.regval << 16);
4536 else
4537 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
bc7f75fa 4538
e921eb1a 4539 /* Write the last 24 bits of an index within the
bc7f75fa
AK		 4540 * block into Flash Linear address field in Flash
4541 * Address.
4542 */
4543 flash_linear_addr += (j * sector_size);
4544 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4545
17e813ec 4546 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
9e2d7657 4547 if (!ret_val)
bc7f75fa
AK		 4548 break;
4549
e921eb1a 4550 /* Check if FCERR is set to 1. If 1,
bc7f75fa 4551 * clear it and try the whole sequence
ad68076e
BA		 4552 * a few more times else Done
4553 */
bc7f75fa 4554 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 4555 if (hsfsts.hsf_status.flcerr)
ad68076e 4556 /* repeat for some time before giving up */
bc7f75fa 4557 continue;
04499ec4 4558 else if (!hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 4559 return ret_val;
4560 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4561 }
4562
4563 return 0;
4564}
4565
4566/**
4567 * e1000_valid_led_default_ich8lan - Set the default LED settings
4568 * @hw: pointer to the HW structure
4569 * @data: Pointer to the LED settings
4570 *
4571 * Reads the LED default settings from the NVM to data. If the NVM LED
4572 * settings is all 0's or F's, set the LED default to a valid LED default
4573 * setting.
4574 **/
4575static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4576{
4577 s32 ret_val;
4578
4579 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4580 if (ret_val) {
3bb99fe2 4581 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 4582 return ret_val;
4583 }
4584
e5fe2541 4585 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
bc7f75fa
AK		 4586 *data = ID_LED_DEFAULT_ICH8LAN;
4587
4588 return 0;
4589}
4590
a4f58f54
BA		 4591/**
4592 * e1000_id_led_init_pchlan - store LED configurations
4593 * @hw: pointer to the HW structure
4594 *
4595 * PCH does not control LEDs via the LEDCTL register, rather it uses
4596 * the PHY LED configuration register.
4597 *
4598 * PCH also does not have an "always on" or "always off" mode which
4599 * complicates the ID feature. Instead of using the "on" mode to indicate
d1964eb1 4600 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
a4f58f54
BA		 4601 * use "link_up" mode. The LEDs will still ID on request if there is no
4602 * link based on logic in e1000_led_[on|off]_pchlan().
4603 **/
4604static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4605{
4606 struct e1000_mac_info *mac = &hw->mac;
4607 s32 ret_val;
4608 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4609 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4610 u16 data, i, temp, shift;
4611
4612 /* Get default ID LED modes */
4613 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4614 if (ret_val)
5015e53a 4615 return ret_val;
a4f58f54
BA		 4616
4617 mac->ledctl_default = er32(LEDCTL);
4618 mac->ledctl_mode1 = mac->ledctl_default;
4619 mac->ledctl_mode2 = mac->ledctl_default;
4620
4621 for (i = 0; i < 4; i++) {
4622 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4623 shift = (i * 5);
4624 switch (temp) {
4625 case ID_LED_ON1_DEF2:
4626 case ID_LED_ON1_ON2:
4627 case ID_LED_ON1_OFF2:
4628 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4629 mac->ledctl_mode1 |= (ledctl_on << shift);
4630 break;
4631 case ID_LED_OFF1_DEF2:
4632 case ID_LED_OFF1_ON2:
4633 case ID_LED_OFF1_OFF2:
4634 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4635 mac->ledctl_mode1 |= (ledctl_off << shift);
4636 break;
4637 default:
4638 /* Do nothing */
4639 break;
4640 }
4641 switch (temp) {
4642 case ID_LED_DEF1_ON2:
4643 case ID_LED_ON1_ON2:
4644 case ID_LED_OFF1_ON2:
4645 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4646 mac->ledctl_mode2 |= (ledctl_on << shift);
4647 break;
4648 case ID_LED_DEF1_OFF2:
4649 case ID_LED_ON1_OFF2:
4650 case ID_LED_OFF1_OFF2:
4651 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4652 mac->ledctl_mode2 |= (ledctl_off << shift);
4653 break;
4654 default:
4655 /* Do nothing */
4656 break;
4657 }
4658 }
4659
5015e53a 4660 return 0;
a4f58f54
BA		 4661}
4662
bc7f75fa
AK		 4663/**
4664 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4665 * @hw: pointer to the HW structure
4666 *
4667 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4668 * register, so the the bus width is hard coded.
4669 **/
4670static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4671{
4672 struct e1000_bus_info *bus = &hw->bus;
4673 s32 ret_val;
4674
4675 ret_val = e1000e_get_bus_info_pcie(hw);
4676
e921eb1a 4677 /* ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 4678 * a configuration space, but do not contain
4679 * PCI Express Capability registers, so bus width
4680 * must be hardcoded.
4681 */
4682 if (bus->width == e1000_bus_width_unknown)
4683 bus->width = e1000_bus_width_pcie_x1;
4684
4685 return ret_val;
4686}
4687
4688/**
4689 * e1000_reset_hw_ich8lan - Reset the hardware
4690 * @hw: pointer to the HW structure
4691 *
4692 * Does a full reset of the hardware which includes a reset of the PHY and
4693 * MAC.
4694 **/
4695static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4696{
1d5846b9 4697 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
62bc813e
BA		 4698 u16 kum_cfg;
4699 u32 ctrl, reg;
bc7f75fa
AK		 4700 s32 ret_val;
4701
e921eb1a 4702 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 4703 * on the last TLP read/write transaction when MAC is reset.
4704 */
4705 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 4706 if (ret_val)
3bb99fe2 4707 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 4708
3bb99fe2 4709 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 4710 ew32(IMC, 0xffffffff);
4711
e921eb1a 4712 /* Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 4713 * any pending transactions to complete before we hit the MAC
4714 * with the global reset.
4715 */
4716 ew32(RCTL, 0);
4717 ew32(TCTL, E1000_TCTL_PSP);
4718 e1e_flush();
4719
ab6973ae 4720 usleep_range(10000, 11000);
bc7f75fa
AK		 4721
4722 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4723 if (hw->mac.type == e1000_ich8lan) {
4724 /* Set Tx and Rx buffer allocation to 8k apiece. */
4725 ew32(PBA, E1000_PBA_8K);
4726 /* Set Packet Buffer Size to 16k. */
4727 ew32(PBS, E1000_PBS_16K);
4728 }
4729
1d5846b9 4730 if (hw->mac.type == e1000_pchlan) {
62bc813e
BA		 4731 /* Save the NVM K1 bit setting */
4732 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
1d5846b9
BA		 4733 if (ret_val)
4734 return ret_val;
4735
62bc813e 4736 if (kum_cfg & E1000_NVM_K1_ENABLE)
1d5846b9
BA		 4737 dev_spec->nvm_k1_enabled = true;
4738 else
4739 dev_spec->nvm_k1_enabled = false;
4740 }
4741
bc7f75fa
AK		 4742 ctrl = er32(CTRL);
4743
44abd5c1 4744 if (!hw->phy.ops.check_reset_block(hw)) {
e921eb1a 4745 /* Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 4746 * time to make sure the interface between MAC and the
4747 * external PHY is reset.
4748 */
4749 ctrl |= E1000_CTRL_PHY_RST;
605c82ba 4750
e921eb1a 4751 /* Gate automatic PHY configuration by hardware on
605c82ba
BA		 4752 * non-managed 82579
4753 */
4754 if ((hw->mac.type == e1000_pch2lan) &&
4755 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4756 e1000_gate_hw_phy_config_ich8lan(hw, true);
bc7f75fa
AK		 4757 }
4758 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 4759 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa 4760 ew32(CTRL, (ctrl | E1000_CTRL_RST));
945a5151 4761 /* cannot issue a flush here because it hangs the hardware */
bc7f75fa
AK		 4762 msleep(20);
4763
62bc813e
BA		 4764 /* Set Phy Config Counter to 50msec */
4765 if (hw->mac.type == e1000_pch2lan) {
4766 reg = er32(FEXTNVM3);
4767 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4768 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4769 ew32(FEXTNVM3, reg);
4770 }
4771
fc0c7760 4772 if (!ret_val)
a90b412c 4773 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
37f40239 4774
e98cac44 4775 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 4776 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44 4777 if (ret_val)
5015e53a 4778 return ret_val;
fc0c7760 4779
e98cac44 4780 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211 4781 if (ret_val)
5015e53a 4782 return ret_val;
f523d211 4783 }
e98cac44 4784
e921eb1a 4785 /* For PCH, this write will make sure that any noise
7d3cabbc
BA		 4786 * will be detected as a CRC error and be dropped rather than show up
4787 * as a bad packet to the DMA engine.
4788 */
4789 if (hw->mac.type == e1000_pchlan)
4790 ew32(CRC_OFFSET, 0x65656565);
4791
bc7f75fa 4792 ew32(IMC, 0xffffffff);
dd93f95e 4793 er32(ICR);
bc7f75fa 4794
62bc813e
BA		 4795 reg = er32(KABGTXD);
4796 reg |= E1000_KABGTXD_BGSQLBIAS;
4797 ew32(KABGTXD, reg);
bc7f75fa 4798
5015e53a 4799 return 0;
bc7f75fa
AK		 4800}
4801
4802/**
4803 * e1000_init_hw_ich8lan - Initialize the hardware
4804 * @hw: pointer to the HW structure
4805 *
4806 * Prepares the hardware for transmit and receive by doing the following:
4807 * - initialize hardware bits
4808 * - initialize LED identification
4809 * - setup receive address registers
4810 * - setup flow control
489815ce 4811 * - setup transmit descriptors
bc7f75fa
AK		 4812 * - clear statistics
4813 **/
4814static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4815{
4816 struct e1000_mac_info *mac = &hw->mac;
4817 u32 ctrl_ext, txdctl, snoop;
4818 s32 ret_val;
4819 u16 i;
4820
4821 e1000_initialize_hw_bits_ich8lan(hw);
4822
4823 /* Initialize identification LED */
a4f58f54 4824 ret_val = mac->ops.id_led_init(hw);
33550cec 4825 /* An error is not fatal and we should not stop init due to this */
de39b752 4826 if (ret_val)
3bb99fe2 4827 e_dbg("Error initializing identification LED\n");
bc7f75fa
AK		 4828
4829 /* Setup the receive address. */
4830 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4831
4832 /* Zero out the Multicast HASH table */
3bb99fe2 4833 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 4834 for (i = 0; i < mac->mta_reg_count; i++)
4835 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4836
e921eb1a 4837 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3ebfc7c9 4838 * the ME. Disable wakeup by clearing the host wakeup bit.
fc0c7760
BA		 4839 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4840 */
4841 if (hw->phy.type == e1000_phy_82578) {
3ebfc7c9
BA		 4842 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4843 i &= ~BM_WUC_HOST_WU_BIT;
4844 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
fc0c7760
BA		 4845 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4846 if (ret_val)
4847 return ret_val;
4848 }
4849
bc7f75fa 4850 /* Setup link and flow control */
1a46b40f 4851 ret_val = mac->ops.setup_link(hw);
bc7f75fa
AK		 4852
4853 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 4854 txdctl = er32(TXDCTL(0));
f0ff4398
BA		 4855 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4856 E1000_TXDCTL_FULL_TX_DESC_WB);
4857 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4858 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f
JK		 4859 ew32(TXDCTL(0), txdctl);
4860 txdctl = er32(TXDCTL(1));
f0ff4398
BA		 4861 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4862 E1000_TXDCTL_FULL_TX_DESC_WB);
4863 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4864 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f 4865 ew32(TXDCTL(1), txdctl);
bc7f75fa 4866
e921eb1a 4867 /* ICH8 has opposite polarity of no_snoop bits.
ad68076e
BA		 4868 * By default, we should use snoop behavior.
4869 */
bc7f75fa
AK		 4870 if (mac->type == e1000_ich8lan)
4871 snoop = PCIE_ICH8_SNOOP_ALL;
4872 else
53aa82da 4873 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
bc7f75fa
AK		 4874 e1000e_set_pcie_no_snoop(hw, snoop);
4875
4876 ctrl_ext = er32(CTRL_EXT);
4877 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4878 ew32(CTRL_EXT, ctrl_ext);
4879
e921eb1a 4880 /* Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 4881 * important that we do this after we have tried to establish link
4882 * because the symbol error count will increment wildly if there
4883 * is no link.
4884 */
4885 e1000_clear_hw_cntrs_ich8lan(hw);
4886
e561a705 4887 return ret_val;
bc7f75fa 4888}
fc830b78 4889
bc7f75fa
AK		 4890/**
4891 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4892 * @hw: pointer to the HW structure
4893 *
4894 * Sets/Clears required hardware bits necessary for correctly setting up the
4895 * hardware for transmit and receive.
4896 **/
4897static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4898{
4899 u32 reg;
4900
4901 /* Extended Device Control */
4902 reg = er32(CTRL_EXT);
18dd2392 4903 reg |= BIT(22);
a4f58f54
BA		 4904 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4905 if (hw->mac.type >= e1000_pchlan)
4906 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 4907 ew32(CTRL_EXT, reg);
4908
4909 /* Transmit Descriptor Control 0 */
e9ec2c0f 4910 reg = er32(TXDCTL(0));
18dd2392 4911 reg |= BIT(22);
e9ec2c0f 4912 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 4913
4914 /* Transmit Descriptor Control 1 */
e9ec2c0f 4915 reg = er32(TXDCTL(1));
18dd2392 4916 reg |= BIT(22);
e9ec2c0f 4917 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 4918
4919 /* Transmit Arbitration Control 0 */
e9ec2c0f 4920 reg = er32(TARC(0));
bc7f75fa 4921 if (hw->mac.type == e1000_ich8lan)
18dd2392
JK		 4922 reg |= BIT(28) | BIT(29);
4923 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
e9ec2c0f 4924 ew32(TARC(0), reg);
bc7f75fa
AK		 4925
4926 /* Transmit Arbitration Control 1 */
e9ec2c0f 4927 reg = er32(TARC(1));
bc7f75fa 4928 if (er32(TCTL) & E1000_TCTL_MULR)
18dd2392 4929 reg &= ~BIT(28);
bc7f75fa 4930 else
18dd2392
JK		 4931 reg |= BIT(28);
4932 reg |= BIT(24) | BIT(26) | BIT(30);
e9ec2c0f 4933 ew32(TARC(1), reg);
bc7f75fa
AK		 4934
4935 /* Device Status */
4936 if (hw->mac.type == e1000_ich8lan) {
4937 reg = er32(STATUS);
18dd2392 4938 reg &= ~BIT(31);
bc7f75fa
AK		 4939 ew32(STATUS, reg);
4940 }
a80483d3 4941
e921eb1a 4942 /* work-around descriptor data corruption issue during nfs v2 udp
a80483d3
JB		 4943 * traffic, just disable the nfs filtering capability
4944 */
4945 reg = er32(RFCTL);
4946 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
f6bd5577 4947
e921eb1a 4948 /* Disable IPv6 extension header parsing because some malformed
f6bd5577
MV		 4949 * IPv6 headers can hang the Rx.
4950 */
4951 if (hw->mac.type == e1000_ich8lan)
4952 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
a80483d3 4953 ew32(RFCTL, reg);
94fb848b
BA		 4954
4955 /* Enable ECC on Lynxpoint */
c8744f44 4956 if (hw->mac.type >= e1000_pch_lpt) {
94fb848b
BA		 4957 reg = er32(PBECCSTS);
4958 reg |= E1000_PBECCSTS_ECC_ENABLE;
4959 ew32(PBECCSTS, reg);
4960
4961 reg = er32(CTRL);
4962 reg |= E1000_CTRL_MEHE;
4963 ew32(CTRL, reg);
4964 }
bc7f75fa
AK		 4965}
4966
4967/**
4968 * e1000_setup_link_ich8lan - Setup flow control and link settings
4969 * @hw: pointer to the HW structure
4970 *
4971 * Determines which flow control settings to use, then configures flow
4972 * control. Calls the appropriate media-specific link configuration
4973 * function. Assuming the adapter has a valid link partner, a valid link
4974 * should be established. Assumes the hardware has previously been reset
4975 * and the transmitter and receiver are not enabled.
4976 **/
4977static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4978{
bc7f75fa
AK		 4979 s32 ret_val;
4980
44abd5c1 4981 if (hw->phy.ops.check_reset_block(hw))
bc7f75fa
AK		 4982 return 0;
4983
e921eb1a 4984 /* ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 4985 * the default flow control setting, so we explicitly
4986 * set it to full.
4987 */
37289d9c
BA		 4988 if (hw->fc.requested_mode == e1000_fc_default) {
4989 /* Workaround h/w hang when Tx flow control enabled */
4990 if (hw->mac.type == e1000_pchlan)
4991 hw->fc.requested_mode = e1000_fc_rx_pause;
4992 else
4993 hw->fc.requested_mode = e1000_fc_full;
4994 }
bc7f75fa 4995
e921eb1a 4996 /* Save off the requested flow control mode for use later. Depending
5c48ef3e
BA		 4997 * on the link partner's capabilities, we may or may not use this mode.
4998 */
4999 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 5000
17e813ec 5001 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
bc7f75fa
AK		 5002
5003 /* Continue to configure the copper link. */
944ce011 5004 ret_val = hw->mac.ops.setup_physical_interface(hw);
bc7f75fa
AK		 5005 if (ret_val)
5006 return ret_val;
5007
318a94d6 5008 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 5009 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 5010 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 5011 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 5012 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 5013 ew32(FCRTV_PCH, hw->fc.refresh_time);
5014
482fed85
BA		 5015 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5016 hw->fc.pause_time);
a4f58f54
BA		 5017 if (ret_val)
5018 return ret_val;
5019 }
bc7f75fa
AK		 5020
5021 return e1000e_set_fc_watermarks(hw);
5022}
5023
5024/**
5025 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5026 * @hw: pointer to the HW structure
5027 *
5028 * Configures the kumeran interface to the PHY to wait the appropriate time
5029 * when polling the PHY, then call the generic setup_copper_link to finish
5030 * configuring the copper link.
5031 **/
5032static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5033{
5034 u32 ctrl;
5035 s32 ret_val;
5036 u16 reg_data;
5037
5038 ctrl = er32(CTRL);
5039 ctrl |= E1000_CTRL_SLU;
5040 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5041 ew32(CTRL, ctrl);
5042
e921eb1a 5043 /* Set the mac to wait the maximum time between each iteration
bc7f75fa 5044 * and increase the max iterations when polling the phy;
ad68076e
BA		 5045 * this fixes erroneous timeouts at 10Mbps.
5046 */
07818950 5047 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 5048 if (ret_val)
5049 return ret_val;
07818950 5050 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 5051 &reg_data);
bc7f75fa
AK		 5052 if (ret_val)
5053 return ret_val;
5054 reg_data |= 0x3F;
07818950 5055 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 5056 reg_data);
bc7f75fa
AK		 5057 if (ret_val)
5058 return ret_val;
5059
a4f58f54
BA		 5060 switch (hw->phy.type) {
5061 case e1000_phy_igp_3:
bc7f75fa
AK		 5062 ret_val = e1000e_copper_link_setup_igp(hw);
5063 if (ret_val)
5064 return ret_val;
a4f58f54
BA		 5065 break;
5066 case e1000_phy_bm:
5067 case e1000_phy_82578:
97ac8cae
BA		 5068 ret_val = e1000e_copper_link_setup_m88(hw);
5069 if (ret_val)
5070 return ret_val;
a4f58f54
BA		 5071 break;
5072 case e1000_phy_82577:
d3738bb8 5073 case e1000_phy_82579:
a4f58f54
BA		 5074 ret_val = e1000_copper_link_setup_82577(hw);
5075 if (ret_val)
5076 return ret_val;
5077 break;
5078 case e1000_phy_ife:
482fed85 5079 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
97ac8cae
BA		 5080 if (ret_val)
5081 return ret_val;
5082
5083 reg_data &= ~IFE_PMC_AUTO_MDIX;
5084
5085 switch (hw->phy.mdix) {
5086 case 1:
5087 reg_data &= ~IFE_PMC_FORCE_MDIX;
5088 break;
5089 case 2:
5090 reg_data |= IFE_PMC_FORCE_MDIX;
5091 break;
5092 case 0:
5093 default:
5094 reg_data |= IFE_PMC_AUTO_MDIX;
5095 break;
5096 }
482fed85 5097 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
97ac8cae
BA		 5098 if (ret_val)
5099 return ret_val;
a4f58f54
BA		 5100 break;
5101 default:
5102 break;
97ac8cae 5103 }
3fa82936 5104
bc7f75fa
AK		 5105 return e1000e_setup_copper_link(hw);
5106}
5107
ea8179a7
BA		 5108/**
5109 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5110 * @hw: pointer to the HW structure
5111 *
5112 * Calls the PHY specific link setup function and then calls the
5113 * generic setup_copper_link to finish configuring the link for
5114 * Lynxpoint PCH devices
5115 **/
5116static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5117{
5118 u32 ctrl;
5119 s32 ret_val;
5120
5121 ctrl = er32(CTRL);
5122 ctrl |= E1000_CTRL_SLU;
5123 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5124 ew32(CTRL, ctrl);
5125
5126 ret_val = e1000_copper_link_setup_82577(hw);
5127 if (ret_val)
5128 return ret_val;
5129
5130 return e1000e_setup_copper_link(hw);
5131}
5132
bc7f75fa
AK		 5133/**
5134 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5135 * @hw: pointer to the HW structure
5136 * @speed: pointer to store current link speed
5137 * @duplex: pointer to store the current link duplex
5138 *
ad68076e 5139 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 5140 * information and then calls the Kumeran lock loss workaround for links at
5141 * gigabit speeds.
5142 **/
5143static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5144 u16 *duplex)
5145{
5146 s32 ret_val;
5147
5148 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5149 if (ret_val)
5150 return ret_val;
5151
5152 if ((hw->mac.type == e1000_ich8lan) &&
e5fe2541 5153 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
bc7f75fa
AK		 5154 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5155 }
5156
5157 return ret_val;
5158}
5159
5160/**
5161 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5162 * @hw: pointer to the HW structure
5163 *
5164 * Work-around for 82566 Kumeran PCS lock loss:
5165 * On link status change (i.e. PCI reset, speed change) and link is up and
5166 * speed is gigabit-
5167 * 0) if workaround is optionally disabled do nothing
5168 * 1) wait 1ms for Kumeran link to come up
5169 * 2) check Kumeran Diagnostic register PCS lock loss bit
5170 * 3) if not set the link is locked (all is good), otherwise...
5171 * 4) reset the PHY
5172 * 5) repeat up to 10 times
5173 * Note: this is only called for IGP3 copper when speed is 1gb.
5174 **/
5175static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5176{
5177 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5178 u32 phy_ctrl;
5179 s32 ret_val;
5180 u16 i, data;
5181 bool link;
5182
5183 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5184 return 0;
5185
e921eb1a 5186 /* Make sure link is up before proceeding. If not just return.
bc7f75fa 5187 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 5188 * stability
5189 */
bc7f75fa
AK		 5190 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5191 if (!link)
5192 return 0;
5193
5194 for (i = 0; i < 10; i++) {
5195 /* read once to clear */
5196 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5197 if (ret_val)
5198 return ret_val;
5199 /* and again to get new status */
5200 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5201 if (ret_val)
5202 return ret_val;
5203
5204 /* check for PCS lock */
5205 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5206 return 0;
5207
5208 /* Issue PHY reset */
5209 e1000_phy_hw_reset(hw);
5210 mdelay(5);
5211 }
5212 /* Disable GigE link negotiation */
5213 phy_ctrl = er32(PHY_CTRL);
5214 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5215 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5216 ew32(PHY_CTRL, phy_ctrl);
5217
e921eb1a 5218 /* Call gig speed drop workaround on Gig disable before accessing
ad68076e
BA		 5219 * any PHY registers
5220 */
bc7f75fa
AK		 5221 e1000e_gig_downshift_workaround_ich8lan(hw);
5222
5223 /* unable to acquire PCS lock */
5224 return -E1000_ERR_PHY;
5225}
5226
5227/**
6e3c8075 5228 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 5229 * @hw: pointer to the HW structure
489815ce 5230 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 5231 *
564ea9bb
BA		 5232 * If ICH8, set the current Kumeran workaround state (enabled - true
5233 * /disabled - false).
bc7f75fa
AK		 5234 **/
5235void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
17e813ec 5236 bool state)
bc7f75fa
AK		 5237{
5238 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5239
5240 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 5241 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 5242 return;
5243 }
5244
5245 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5246}
5247
5248/**
5249 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5250 * @hw: pointer to the HW structure
5251 *
5252 * Workaround for 82566 power-down on D3 entry:
5253 * 1) disable gigabit link
5254 * 2) write VR power-down enable
5255 * 3) read it back
5256 * Continue if successful, else issue LCD reset and repeat
5257 **/
5258void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5259{
5260 u32 reg;
5261 u16 data;
e80bd1d1 5262 u8 retry = 0;
bc7f75fa
AK		 5263
5264 if (hw->phy.type != e1000_phy_igp_3)
5265 return;
5266
5267 /* Try the workaround twice (if needed) */
5268 do {
5269 /* Disable link */
5270 reg = er32(PHY_CTRL);
5271 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5272 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5273 ew32(PHY_CTRL, reg);
5274
e921eb1a 5275 /* Call gig speed drop workaround on Gig disable before
ad68076e
BA		 5276 * accessing any PHY registers
5277 */
bc7f75fa
AK		 5278 if (hw->mac.type == e1000_ich8lan)
5279 e1000e_gig_downshift_workaround_ich8lan(hw);
5280
5281 /* Write VR power-down enable */
5282 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5283 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5284 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5285
5286 /* Read it back and test */
5287 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5288 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5289 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5290 break;
5291
5292 /* Issue PHY reset and repeat at most one more time */
5293 reg = er32(CTRL);
5294 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5295 retry++;
5296 } while (retry);
5297}
5298
5299/**
5300 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5301 * @hw: pointer to the HW structure
5302 *
5303 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 5304 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 5305 * 1) Set Kumeran Near-end loopback
5306 * 2) Clear Kumeran Near-end loopback
462d5994 5307 * Should only be called for ICH8[m] devices with any 1G Phy.
bc7f75fa
AK		 5308 **/
5309void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5310{
5311 s32 ret_val;
5312 u16 reg_data;
5313
462d5994 5314 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
bc7f75fa
AK		 5315 return;
5316
5317 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 5318 &reg_data);
bc7f75fa
AK		 5319 if (ret_val)
5320 return;
5321 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5322 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 5323 reg_data);
bc7f75fa
AK		 5324 if (ret_val)
5325 return;
5326 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
7dbbe5d5 5327 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
bc7f75fa
AK		 5328}
5329
97ac8cae 5330/**
99730e4c 5331 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
97ac8cae
BA		 5332 * @hw: pointer to the HW structure
5333 *
5334 * During S0 to Sx transition, it is possible the link remains at gig
5335 * instead of negotiating to a lower speed. Before going to Sx, set
c077a906
BA		 5336 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5337 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5338 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5339 * needs to be written.
2fbe4526
BA		 5340 * Parts that support (and are linked to a partner which support) EEE in
5341 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5342 * than 10Mbps w/o EEE.
97ac8cae 5343 **/
99730e4c 5344void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
97ac8cae 5345{
2fbe4526 5346 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
97ac8cae 5347 u32 phy_ctrl;
8395ae83 5348 s32 ret_val;
97ac8cae 5349
17f085df 5350 phy_ctrl = er32(PHY_CTRL);
c077a906 5351 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
e08f626b 5352
2fbe4526 5353 if (hw->phy.type == e1000_phy_i217) {
e08f626b
BA		 5354 u16 phy_reg, device_id = hw->adapter->pdev->device;
5355
5356 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
91a3d82f
BA		 5357 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5358 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
79849ebc 5359 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
c8744f44 5360 (hw->mac.type >= e1000_pch_spt)) {
e08f626b
BA		 5361 u32 fextnvm6 = er32(FEXTNVM6);
5362
5363 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5364 }
2fbe4526
BA		 5365
5366 ret_val = hw->phy.ops.acquire(hw);
5367 if (ret_val)
5368 goto out;
5369
5370 if (!dev_spec->eee_disable) {
5371 u16 eee_advert;
5372
4ddc48a9
BA		 5373 ret_val =
5374 e1000_read_emi_reg_locked(hw,
5375 I217_EEE_ADVERTISEMENT,
5376 &eee_advert);
2fbe4526
BA		 5377 if (ret_val)
5378 goto release;
2fbe4526 5379
e921eb1a 5380 /* Disable LPLU if both link partners support 100BaseT
2fbe4526 5381 * EEE and 100Full is advertised on both ends of the
b4c1e6bf
DE		 5382 * link, and enable Auto Enable LPI since there will
5383 * be no driver to enable LPI while in Sx.
2fbe4526 5384 */
3d4d5755 5385 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
2fbe4526 5386 (dev_spec->eee_lp_ability &
3d4d5755 5387 I82579_EEE_100_SUPPORTED) &&
b4c1e6bf 5388 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
2fbe4526
BA		 5389 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5390 E1000_PHY_CTRL_NOND0A_LPLU);
b4c1e6bf
DE		 5391
5392 /* Set Auto Enable LPI after link up */
5393 e1e_rphy_locked(hw,
5394 I217_LPI_GPIO_CTRL, &phy_reg);
5395 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5396 e1e_wphy_locked(hw,
5397 I217_LPI_GPIO_CTRL, phy_reg);
5398 }
2fbe4526
BA		 5399 }
5400
e921eb1a 5401 /* For i217 Intel Rapid Start Technology support,
2fbe4526
BA		 5402 * when the system is going into Sx and no manageability engine
5403 * is present, the driver must configure proxy to reset only on
5404 * power good. LPI (Low Power Idle) state must also reset only
5405 * on power good, as well as the MTA (Multicast table array).
5406 * The SMBus release must also be disabled on LCD reset.
5407 */
5408 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2fbe4526
BA		 5409 /* Enable proxy to reset only on power good. */
5410 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5411 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5412 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5413
e921eb1a 5414 /* Set bit enable LPI (EEE) to reset only on
2fbe4526
BA		 5415 * power good.
5416 */
5417 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
6d7407bf 5418 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
2fbe4526
BA		 5419 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5420
5421 /* Disable the SMB release on LCD reset. */
5422 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
6d7407bf 5423 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 5424 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5425 }
5426
e921eb1a 5427 /* Enable MTA to reset for Intel Rapid Start Technology
2fbe4526
BA		 5428 * Support
5429 */
5430 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
6d7407bf 5431 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 5432 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5433
5434release:
5435 hw->phy.ops.release(hw);
5436 }
5437out:
17f085df 5438 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 5439
462d5994
BA		 5440 if (hw->mac.type == e1000_ich8lan)
5441 e1000e_gig_downshift_workaround_ich8lan(hw);
5442
8395ae83 5443 if (hw->mac.type >= e1000_pchlan) {
ce54afd1 5444 e1000_oem_bits_config_ich8lan(hw, false);
92fe1733
BA		 5445
5446 /* Reset PHY to activate OEM bits on 82577/8 */
5447 if (hw->mac.type == e1000_pchlan)
5448 e1000e_phy_hw_reset_generic(hw);
5449
8395ae83
BA		 5450 ret_val = hw->phy.ops.acquire(hw);
5451 if (ret_val)
5452 return;
5453 e1000_write_smbus_addr(hw);
5454 hw->phy.ops.release(hw);
5455 }
97ac8cae
BA		 5456}
5457
99730e4c
BA		 5458/**
5459 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5460 * @hw: pointer to the HW structure
5461 *
5462 * During Sx to S0 transitions on non-managed devices or managed devices
5463 * on which PHY resets are not blocked, if the PHY registers cannot be
5464 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5465 * the PHY.
2fbe4526 5466 * On i217, setup Intel Rapid Start Technology.
99730e4c
BA		 5467 **/
5468void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5469{
90b82984 5470 s32 ret_val;
99730e4c 5471
cb17aab9 5472 if (hw->mac.type < e1000_pch2lan)
99730e4c
BA		 5473 return;
5474
cb17aab9 5475 ret_val = e1000_init_phy_workarounds_pchlan(hw);
90b82984 5476 if (ret_val) {
cb17aab9 5477 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
90b82984
BA		 5478 return;
5479 }
2fbe4526 5480
e921eb1a 5481 /* For i217 Intel Rapid Start Technology support when the system
2fbe4526
BA		 5482 * is transitioning from Sx and no manageability engine is present
5483 * configure SMBus to restore on reset, disable proxy, and enable
5484 * the reset on MTA (Multicast table array).
5485 */
5486 if (hw->phy.type == e1000_phy_i217) {
5487 u16 phy_reg;
5488
5489 ret_val = hw->phy.ops.acquire(hw);
5490 if (ret_val) {
5491 e_dbg("Failed to setup iRST\n");
5492 return;
5493 }
5494
b4c1e6bf
DE		 5495 /* Clear Auto Enable LPI after link up */
5496 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5497 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5498 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5499
2fbe4526 5500 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
e921eb1a 5501 /* Restore clear on SMB if no manageability engine
2fbe4526
BA		 5502 * is present
5503 */
5504 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5505 if (ret_val)
5506 goto release;
6d7407bf 5507 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 5508 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5509
5510 /* Disable Proxy */
5511 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5512 }
5513 /* Enable reset on MTA */
5514 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5515 if (ret_val)
5516 goto release;
6d7407bf 5517 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 5518 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5519release:
5520 if (ret_val)
5521 e_dbg("Error %d in resume workarounds\n", ret_val);
5522 hw->phy.ops.release(hw);
5523 }
99730e4c
BA		 5524}
5525
bc7f75fa
AK		 5526/**
5527 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5528 * @hw: pointer to the HW structure
5529 *
5530 * Return the LED back to the default configuration.
5531 **/
5532static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5533{
5534 if (hw->phy.type == e1000_phy_ife)
5535 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5536
5537 ew32(LEDCTL, hw->mac.ledctl_default);
5538 return 0;
5539}
5540
5541/**
489815ce 5542 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 5543 * @hw: pointer to the HW structure
5544 *
489815ce 5545 * Turn on the LEDs.
bc7f75fa
AK		 5546 **/
5547static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5548{
5549 if (hw->phy.type == e1000_phy_ife)
5550 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5551 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5552
5553 ew32(LEDCTL, hw->mac.ledctl_mode2);
5554 return 0;
5555}
5556
5557/**
489815ce 5558 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 5559 * @hw: pointer to the HW structure
5560 *
489815ce 5561 * Turn off the LEDs.
bc7f75fa
AK		 5562 **/
5563static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5564{
5565 if (hw->phy.type == e1000_phy_ife)
5566 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
482fed85
BA		 5567 (IFE_PSCL_PROBE_MODE |
5568 IFE_PSCL_PROBE_LEDS_OFF));
bc7f75fa
AK		 5569
5570 ew32(LEDCTL, hw->mac.ledctl_mode1);
5571 return 0;
5572}
5573
a4f58f54
BA		 5574/**
5575 * e1000_setup_led_pchlan - Configures SW controllable LED
5576 * @hw: pointer to the HW structure
5577 *
5578 * This prepares the SW controllable LED for use.
5579 **/
5580static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5581{
482fed85 5582 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
a4f58f54
BA		 5583}
5584
5585/**
5586 * e1000_cleanup_led_pchlan - Restore the default LED operation
5587 * @hw: pointer to the HW structure
5588 *
5589 * Return the LED back to the default configuration.
5590 **/
5591static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5592{
482fed85 5593 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
a4f58f54
BA		 5594}
5595
5596/**
5597 * e1000_led_on_pchlan - Turn LEDs on
5598 * @hw: pointer to the HW structure
5599 *
5600 * Turn on the LEDs.
5601 **/
5602static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5603{
5604 u16 data = (u16)hw->mac.ledctl_mode2;
5605 u32 i, led;
5606
e921eb1a 5607 /* If no link, then turn LED on by setting the invert bit
a4f58f54
BA		 5608 * for each LED that's mode is "link_up" in ledctl_mode2.
5609 */
5610 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5611 for (i = 0; i < 3; i++) {
5612 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5613 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5614 E1000_LEDCTL_MODE_LINK_UP)
5615 continue;
5616 if (led & E1000_PHY_LED0_IVRT)
5617 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5618 else
5619 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5620 }
5621 }
5622
482fed85 5623 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 5624}
5625
5626/**
5627 * e1000_led_off_pchlan - Turn LEDs off
5628 * @hw: pointer to the HW structure
5629 *
5630 * Turn off the LEDs.
5631 **/
5632static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5633{
5634 u16 data = (u16)hw->mac.ledctl_mode1;
5635 u32 i, led;
5636
e921eb1a 5637 /* If no link, then turn LED off by clearing the invert bit
a4f58f54
BA		 5638 * for each LED that's mode is "link_up" in ledctl_mode1.
5639 */
5640 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5641 for (i = 0; i < 3; i++) {
5642 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5643 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5644 E1000_LEDCTL_MODE_LINK_UP)
5645 continue;
5646 if (led & E1000_PHY_LED0_IVRT)
5647 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5648 else
5649 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5650 }
5651 }
5652
482fed85 5653 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 5654}
5655
f4187b56 5656/**
e98cac44 5657 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 5658 * @hw: pointer to the HW structure
5659 *
e98cac44
BA		 5660 * Read appropriate register for the config done bit for completion status
5661 * and configure the PHY through s/w for EEPROM-less parts.
5662 *
5663 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5664 * config done bit, so only an error is logged and continues. If we were
5665 * to return with error, EEPROM-less silicon would not be able to be reset
5666 * or change link.
f4187b56
BA		 5667 **/
5668static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5669{
e98cac44 5670 s32 ret_val = 0;
f4187b56 5671 u32 bank = 0;
e98cac44 5672 u32 status;
f4187b56 5673
fe90849f 5674 e1000e_get_cfg_done_generic(hw);
fc0c7760 5675
e98cac44
BA		 5676 /* Wait for indication from h/w that it has completed basic config */
5677 if (hw->mac.type >= e1000_ich10lan) {
5678 e1000_lan_init_done_ich8lan(hw);
5679 } else {
5680 ret_val = e1000e_get_auto_rd_done(hw);
5681 if (ret_val) {
e921eb1a 5682 /* When auto config read does not complete, do not
e98cac44
BA		 5683 * return with an error. This can happen in situations
5684 * where there is no eeprom and prevents getting link.
5685 */
5686 e_dbg("Auto Read Done did not complete\n");
5687 ret_val = 0;
5688 }
fc0c7760
BA		 5689 }
5690
e98cac44
BA		 5691 /* Clear PHY Reset Asserted bit */
5692 status = er32(STATUS);
5693 if (status & E1000_STATUS_PHYRA)
5694 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5695 else
5696 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 5697
5698 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 5699 if (hw->mac.type <= e1000_ich9lan) {
04499ec4 5700 if (!(er32(EECD) & E1000_EECD_PRES) &&
f4187b56
BA		 5701 (hw->phy.type == e1000_phy_igp_3)) {
5702 e1000e_phy_init_script_igp3(hw);
5703 }
5704 } else {
5705 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5706 /* Maybe we should do a basic PHY config */
3bb99fe2 5707 e_dbg("EEPROM not present\n");
e98cac44 5708 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 5709 }
5710 }
5711
e98cac44 5712 return ret_val;
f4187b56
BA		 5713}
5714
17f208de
BA		 5715/**
5716 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5717 * @hw: pointer to the HW structure
5718 *
5719 * In the case of a PHY power down to save power, or to turn off link during a
5720 * driver unload, or wake on lan is not enabled, remove the link.
5721 **/
5722static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5723{
5724 /* If the management interface is not enabled, then power down */
5725 if (!(hw->mac.ops.check_mng_mode(hw) ||
5726 hw->phy.ops.check_reset_block(hw)))
5727 e1000_power_down_phy_copper(hw);
17f208de
BA		 5728}
5729
bc7f75fa
AK		 5730/**
5731 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5732 * @hw: pointer to the HW structure
5733 *
5734 * Clears hardware counters specific to the silicon family and calls
5735 * clear_hw_cntrs_generic to clear all general purpose counters.
5736 **/
5737static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5738{
a4f58f54 5739 u16 phy_data;
2b6b168d 5740 s32 ret_val;
bc7f75fa
AK		 5741
5742 e1000e_clear_hw_cntrs_base(hw);
5743
99673d9b
BA		 5744 er32(ALGNERRC);
5745 er32(RXERRC);
5746 er32(TNCRS);
5747 er32(CEXTERR);
5748 er32(TSCTC);
5749 er32(TSCTFC);
bc7f75fa 5750
99673d9b
BA		 5751 er32(MGTPRC);
5752 er32(MGTPDC);
5753 er32(MGTPTC);
bc7f75fa 5754
99673d9b
BA		 5755 er32(IAC);
5756 er32(ICRXOC);
bc7f75fa 5757
a4f58f54
BA		 5758 /* Clear PHY statistics registers */
5759 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 5760 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 5761 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 5762 (hw->phy.type == e1000_phy_82577)) {
2b6b168d
BA		 5763 ret_val = hw->phy.ops.acquire(hw);
5764 if (ret_val)
5765 return;
5766 ret_val = hw->phy.ops.set_page(hw,
5767 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5768 if (ret_val)
5769 goto release;
5770 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5771 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5772 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5773 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5774 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5775 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5776 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5777 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5778 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5779 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5780 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5781 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5782 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5783 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5784release:
5785 hw->phy.ops.release(hw);
a4f58f54 5786 }
bc7f75fa
AK		 5787}
5788
8ce9d6c7 5789static const struct e1000_mac_operations ich8_mac_ops = {
eb7700dc 5790 /* check_mng_mode dependent on mac type */
7d3cabbc 5791 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 5792 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 5793 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5794 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 5795 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 5796 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 5797 /* led_on dependent on mac type */
5798 /* led_off dependent on mac type */
e2de3eb6 5799 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 5800 .reset_hw = e1000_reset_hw_ich8lan,
5801 .init_hw = e1000_init_hw_ich8lan,
5802 .setup_link = e1000_setup_link_ich8lan,
55c5f55e 5803 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
a4f58f54 5804 /* id_led_init dependent on mac type */
57cde763 5805 .config_collision_dist = e1000e_config_collision_dist_generic,
69e1e019 5806 .rar_set = e1000e_rar_set_generic,
b3e5bf1f 5807 .rar_get_count = e1000e_rar_get_count_generic,
bc7f75fa
AK		 5808};
5809
8ce9d6c7 5810static const struct e1000_phy_operations ich8_phy_ops = {
94d8186a 5811 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 5812 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 5813 .commit = NULL,
f4187b56 5814 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 5815 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 5816 .read_reg = e1000e_read_phy_reg_igp,
5817 .release = e1000_release_swflag_ich8lan,
5818 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 5819 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5820 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 5821 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 5822};
5823
8ce9d6c7 5824static const struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a 5825 .acquire = e1000_acquire_nvm_ich8lan,
55c5f55e 5826 .read = e1000_read_nvm_ich8lan,
94d8186a 5827 .release = e1000_release_nvm_ich8lan,
e85e3639 5828 .reload = e1000e_reload_nvm_generic,
94d8186a 5829 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 5830 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 5831 .validate = e1000_validate_nvm_checksum_ich8lan,
5832 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 5833};
5834
79849ebc
DE		 5835static const struct e1000_nvm_operations spt_nvm_ops = {
5836 .acquire = e1000_acquire_nvm_ich8lan,
5837 .release = e1000_release_nvm_ich8lan,
5838 .read = e1000_read_nvm_spt,
5839 .update = e1000_update_nvm_checksum_spt,
5840 .reload = e1000e_reload_nvm_generic,
5841 .valid_led_default = e1000_valid_led_default_ich8lan,
5842 .validate = e1000_validate_nvm_checksum_ich8lan,
5843 .write = e1000_write_nvm_ich8lan,
5844};
5845
8ce9d6c7 5846const struct e1000_info e1000_ich8_info = {
bc7f75fa
AK		 5847 .mac = e1000_ich8lan,
5848 .flags = FLAG_HAS_WOL
97ac8cae 5849 | FLAG_IS_ICH
bc7f75fa
AK		 5850 | FLAG_HAS_CTRLEXT_ON_LOAD
5851 | FLAG_HAS_AMT
5852 | FLAG_HAS_FLASH
5853 | FLAG_APME_IN_WUC,
5854 .pba = 8,
8084b86d 5855 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 5856 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 5857 .mac_ops = &ich8_mac_ops,
5858 .phy_ops = &ich8_phy_ops,
5859 .nvm_ops = &ich8_nvm_ops,
5860};
5861
8ce9d6c7 5862const struct e1000_info e1000_ich9_info = {
bc7f75fa
AK		 5863 .mac = e1000_ich9lan,
5864 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 5865 | FLAG_IS_ICH
bc7f75fa 5866 | FLAG_HAS_WOL
bc7f75fa
AK		 5867 | FLAG_HAS_CTRLEXT_ON_LOAD
5868 | FLAG_HAS_AMT
bc7f75fa
AK		 5869 | FLAG_HAS_FLASH
5870 | FLAG_APME_IN_WUC,
7f1557e1 5871 .pba = 18,
2adc55c9 5872 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 5873 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 5874 .mac_ops = &ich8_mac_ops,
5875 .phy_ops = &ich8_phy_ops,
5876 .nvm_ops = &ich8_nvm_ops,
5877};
5878
8ce9d6c7 5879const struct e1000_info e1000_ich10_info = {
f4187b56
BA		 5880 .mac = e1000_ich10lan,
5881 .flags = FLAG_HAS_JUMBO_FRAMES
5882 | FLAG_IS_ICH
5883 | FLAG_HAS_WOL
f4187b56
BA		 5884 | FLAG_HAS_CTRLEXT_ON_LOAD
5885 | FLAG_HAS_AMT
f4187b56
BA		 5886 | FLAG_HAS_FLASH
5887 | FLAG_APME_IN_WUC,
7f1557e1 5888 .pba = 18,
2adc55c9 5889 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 5890 .get_variants = e1000_get_variants_ich8lan,
5891 .mac_ops = &ich8_mac_ops,
5892 .phy_ops = &ich8_phy_ops,
5893 .nvm_ops = &ich8_nvm_ops,
5894};
a4f58f54 5895
8ce9d6c7 5896const struct e1000_info e1000_pch_info = {
a4f58f54
BA		 5897 .mac = e1000_pchlan,
5898 .flags = FLAG_IS_ICH
5899 | FLAG_HAS_WOL
a4f58f54
BA		 5900 | FLAG_HAS_CTRLEXT_ON_LOAD
5901 | FLAG_HAS_AMT
5902 | FLAG_HAS_FLASH
5903 | FLAG_HAS_JUMBO_FRAMES
38eb394e 5904 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 5905 | FLAG_APME_IN_WUC,
8c7bbb92 5906 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 5907 .pba = 26,
5908 .max_hw_frame_size = 4096,
5909 .get_variants = e1000_get_variants_ich8lan,
5910 .mac_ops = &ich8_mac_ops,
5911 .phy_ops = &ich8_phy_ops,
5912 .nvm_ops = &ich8_nvm_ops,
5913};
d3738bb8 5914
8ce9d6c7 5915const struct e1000_info e1000_pch2_info = {
d3738bb8
BA		 5916 .mac = e1000_pch2lan,
5917 .flags = FLAG_IS_ICH
5918 | FLAG_HAS_WOL
b67e1913 5919 | FLAG_HAS_HW_TIMESTAMP
d3738bb8
BA		 5920 | FLAG_HAS_CTRLEXT_ON_LOAD
5921 | FLAG_HAS_AMT
5922 | FLAG_HAS_FLASH
5923 | FLAG_HAS_JUMBO_FRAMES
5924 | FLAG_APME_IN_WUC,
e52997f9 5925 .flags2 = FLAG2_HAS_PHY_STATS
10ed1e0b
JW		 5926 | FLAG2_HAS_EEE
5927 | FLAG2_CHECK_SYSTIM_OVERFLOW,
828bac87 5928 .pba = 26,
8084b86d 5929 .max_hw_frame_size = 9022,
d3738bb8
BA		 5930 .get_variants = e1000_get_variants_ich8lan,
5931 .mac_ops = &ich8_mac_ops,
5932 .phy_ops = &ich8_phy_ops,
5933 .nvm_ops = &ich8_nvm_ops,
5934};
2fbe4526
BA		 5935
5936const struct e1000_info e1000_pch_lpt_info = {
5937 .mac = e1000_pch_lpt,
5938 .flags = FLAG_IS_ICH
5939 | FLAG_HAS_WOL
b67e1913 5940 | FLAG_HAS_HW_TIMESTAMP
2fbe4526
BA		 5941 | FLAG_HAS_CTRLEXT_ON_LOAD
5942 | FLAG_HAS_AMT
5943 | FLAG_HAS_FLASH
5944 | FLAG_HAS_JUMBO_FRAMES
5945 | FLAG_APME_IN_WUC,
5946 .flags2 = FLAG2_HAS_PHY_STATS
8037dd60
JW		 5947 | FLAG2_HAS_EEE
5948 | FLAG2_CHECK_SYSTIM_OVERFLOW,
2fbe4526 5949 .pba = 26,
8084b86d 5950 .max_hw_frame_size = 9022,
2fbe4526
BA		 5951 .get_variants = e1000_get_variants_ich8lan,
5952 .mac_ops = &ich8_mac_ops,
5953 .phy_ops = &ich8_phy_ops,
5954 .nvm_ops = &ich8_nvm_ops,
5955};
79849ebc
DE		 5956
5957const struct e1000_info e1000_pch_spt_info = {
5958 .mac = e1000_pch_spt,
5959 .flags = FLAG_IS_ICH
5960 | FLAG_HAS_WOL
5961 | FLAG_HAS_HW_TIMESTAMP
5962 | FLAG_HAS_CTRLEXT_ON_LOAD
5963 | FLAG_HAS_AMT
5964 | FLAG_HAS_FLASH
5965 | FLAG_HAS_JUMBO_FRAMES
5966 | FLAG_APME_IN_WUC,
5967 .flags2 = FLAG2_HAS_PHY_STATS
5968 | FLAG2_HAS_EEE,
5969 .pba = 26,
8084b86d 5970 .max_hw_frame_size = 9022,
79849ebc
DE		 5971 .get_variants = e1000_get_variants_ich8lan,
5972 .mac_ops = &ich8_mac_ops,
5973 .phy_ops = &ich8_phy_ops,
5974 .nvm_ops = &spt_nvm_ops,
5975};
3a3173b9
SN		 5976
5977const struct e1000_info e1000_pch_cnp_info = {
5978 .mac = e1000_pch_cnp,
5979 .flags = FLAG_IS_ICH
5980 | FLAG_HAS_WOL
5981 | FLAG_HAS_HW_TIMESTAMP
5982 | FLAG_HAS_CTRLEXT_ON_LOAD
5983 | FLAG_HAS_AMT
5984 | FLAG_HAS_FLASH
5985 | FLAG_HAS_JUMBO_FRAMES
5986 | FLAG_APME_IN_WUC,
5987 .flags2 = FLAG2_HAS_PHY_STATS
5988 | FLAG2_HAS_EEE,
5989 .pba = 26,
5990 .max_hw_frame_size = 9022,
5991 .get_variants = e1000_get_variants_ich8lan,
5992 .mac_ops = &ich8_mac_ops,
5993 .phy_ops = &ich8_phy_ops,
5994 .nvm_ops = &spt_nvm_ops,
5995};
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