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drivers/net: fix up function prototypes after __dev* removals
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
076d8070 59#define DRV_VERSION "2.1.4" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 82 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 83};
84
84f4ee90
TI		 85struct e1000_reg_info {
86 u32 ofs;
87 char *name;
88};
89
af667a29
BA		 90#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
91#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
92#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
93#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
94#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
95
96#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
97#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
98#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
99#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
100#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 101
102static const struct e1000_reg_info e1000_reg_info_tbl[] = {
103
104 /* General Registers */
105 {E1000_CTRL, "CTRL"},
106 {E1000_STATUS, "STATUS"},
107 {E1000_CTRL_EXT, "CTRL_EXT"},
108
109 /* Interrupt Registers */
110 {E1000_ICR, "ICR"},
111
af667a29 112 /* Rx Registers */
84f4ee90 113 {E1000_RCTL, "RCTL"},
1e36052e
BA		 114 {E1000_RDLEN(0), "RDLEN"},
115 {E1000_RDH(0), "RDH"},
116 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 117 {E1000_RDTR, "RDTR"},
118 {E1000_RXDCTL(0), "RXDCTL"},
119 {E1000_ERT, "ERT"},
1e36052e
BA		 120 {E1000_RDBAL(0), "RDBAL"},
121 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 122 {E1000_RDFH, "RDFH"},
123 {E1000_RDFT, "RDFT"},
124 {E1000_RDFHS, "RDFHS"},
125 {E1000_RDFTS, "RDFTS"},
126 {E1000_RDFPC, "RDFPC"},
127
af667a29 128 /* Tx Registers */
84f4ee90 129 {E1000_TCTL, "TCTL"},
1e36052e
BA		 130 {E1000_TDBAL(0), "TDBAL"},
131 {E1000_TDBAH(0), "TDBAH"},
132 {E1000_TDLEN(0), "TDLEN"},
133 {E1000_TDH(0), "TDH"},
134 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 135 {E1000_TIDV, "TIDV"},
136 {E1000_TXDCTL(0), "TXDCTL"},
137 {E1000_TADV, "TADV"},
138 {E1000_TARC(0), "TARC"},
139 {E1000_TDFH, "TDFH"},
140 {E1000_TDFT, "TDFT"},
141 {E1000_TDFHS, "TDFHS"},
142 {E1000_TDFTS, "TDFTS"},
143 {E1000_TDFPC, "TDFPC"},
144
145 /* List Terminator */
f36bb6ca 146 {0, NULL}
84f4ee90
TI		 147};
148
e921eb1a 149/**
84f4ee90 150 * e1000_regdump - register printout routine
e921eb1a
BA		 151 * @hw: pointer to the HW structure
152 * @reginfo: pointer to the register info table
153 **/
84f4ee90
TI		 154static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
155{
156 int n = 0;
157 char rname[16];
158 u32 regs[8];
159
160 switch (reginfo->ofs) {
161 case E1000_RXDCTL(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_RXDCTL(n));
164 break;
165 case E1000_TXDCTL(0):
166 for (n = 0; n < 2; n++)
167 regs[n] = __er32(hw, E1000_TXDCTL(n));
168 break;
169 case E1000_TARC(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_TARC(n));
172 break;
173 default:
ef456f85
JK		 174 pr_info("%-15s %08x\n",
175 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 176 return;
177 }
178
179 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 180 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 181}
182
f0c5dadf
ET		 183static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
184 struct e1000_buffer *bi)
185{
186 int i;
187 struct e1000_ps_page *ps_page;
188
189 for (i = 0; i < adapter->rx_ps_pages; i++) {
190 ps_page = &bi->ps_pages[i];
191
192 if (ps_page->page) {
193 pr_info("packet dump for ps_page %d:\n", i);
194 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
195 16, 1, page_address(ps_page->page),
196 PAGE_SIZE, true);
197 }
198 }
199}
200
e921eb1a 201/**
af667a29 202 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 203 * @adapter: board private structure
204 **/
84f4ee90
TI		 205static void e1000e_dump(struct e1000_adapter *adapter)
206{
207 struct net_device *netdev = adapter->netdev;
208 struct e1000_hw *hw = &adapter->hw;
209 struct e1000_reg_info *reginfo;
210 struct e1000_ring *tx_ring = adapter->tx_ring;
211 struct e1000_tx_desc *tx_desc;
af667a29 212 struct my_u0 {
e885d762
BA		 213 __le64 a;
214 __le64 b;
af667a29 215 } *u0;
84f4ee90
TI		 216 struct e1000_buffer *buffer_info;
217 struct e1000_ring *rx_ring = adapter->rx_ring;
218 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 219 union e1000_rx_desc_extended *rx_desc;
af667a29 220 struct my_u1 {
e885d762
BA		 221 __le64 a;
222 __le64 b;
223 __le64 c;
224 __le64 d;
af667a29 225 } *u1;
84f4ee90
TI		 226 u32 staterr;
227 int i = 0;
228
229 if (!netif_msg_hw(adapter))
230 return;
231
232 /* Print netdevice Info */
233 if (netdev) {
234 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 235 pr_info("Device Name state trans_start last_rx\n");
236 pr_info("%-15s %016lX %016lX %016lX\n",
237 netdev->name, netdev->state, netdev->trans_start,
238 netdev->last_rx);
84f4ee90
TI		 239 }
240
241 /* Print Registers */
242 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 243 pr_info(" Register Name Value\n");
84f4ee90
TI		 244 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
245 reginfo->name; reginfo++) {
246 e1000_regdump(hw, reginfo);
247 }
248
af667a29 249 /* Print Tx Ring Summary */
84f4ee90 250 if (!netdev || !netif_running(netdev))
fe1e980f 251 return;
84f4ee90 252
af667a29 253 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 254 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 255 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 256 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
257 0, tx_ring->next_to_use, tx_ring->next_to_clean,
258 (unsigned long long)buffer_info->dma,
259 buffer_info->length,
260 buffer_info->next_to_watch,
261 (unsigned long long)buffer_info->time_stamp);
84f4ee90 262
af667a29 263 /* Print Tx Ring */
84f4ee90
TI		 264 if (!netif_msg_tx_done(adapter))
265 goto rx_ring_summary;
266
af667a29 267 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 268
269 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
270 *
271 * Legacy Transmit Descriptor
272 * +--------------------------------------------------------------+
273 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
274 * +--------------------------------------------------------------+
275 * 8 | Special | CSS | Status | CMD | CSO | Length |
276 * +--------------------------------------------------------------+
277 * 63 48 47 36 35 32 31 24 23 16 15 0
278 *
279 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
280 * 63 48 47 40 39 32 31 16 15 8 7 0
281 * +----------------------------------------------------------------+
282 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
283 * +----------------------------------------------------------------+
284 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
285 * +----------------------------------------------------------------+
286 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
287 *
288 * Extended Data Descriptor (DTYP=0x1)
289 * +----------------------------------------------------------------+
290 * 0 | Buffer Address [63:0] |
291 * +----------------------------------------------------------------+
292 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
293 * +----------------------------------------------------------------+
294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
295 */
ef456f85
JK		 296 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
297 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
298 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 299 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 300 const char *next_desc;
84f4ee90
TI		 301 tx_desc = E1000_TX_DESC(*tx_ring, i);
302 buffer_info = &tx_ring->buffer_info[i];
303 u0 = (struct my_u0 *)tx_desc;
84f4ee90 304 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 305 next_desc = " NTC/U";
84f4ee90 306 else if (i == tx_ring->next_to_use)
ef456f85 307 next_desc = " NTU";
84f4ee90 308 else if (i == tx_ring->next_to_clean)
ef456f85 309 next_desc = " NTC";
84f4ee90 310 else
ef456f85
JK		 311 next_desc = "";
312 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
313 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
314 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
315 i,
316 (unsigned long long)le64_to_cpu(u0->a),
317 (unsigned long long)le64_to_cpu(u0->b),
318 (unsigned long long)buffer_info->dma,
319 buffer_info->length, buffer_info->next_to_watch,
320 (unsigned long long)buffer_info->time_stamp,
321 buffer_info->skb, next_desc);
84f4ee90 322
f0c5dadf 323 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 324 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 325 16, 1, buffer_info->skb->data,
326 buffer_info->skb->len, true);
84f4ee90
TI		 327 }
328
af667a29 329 /* Print Rx Ring Summary */
84f4ee90 330rx_ring_summary:
af667a29 331 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 332 pr_info("Queue [NTU] [NTC]\n");
333 pr_info(" %5d %5X %5X\n",
334 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 335
af667a29 336 /* Print Rx Ring */
84f4ee90 337 if (!netif_msg_rx_status(adapter))
fe1e980f 338 return;
84f4ee90 339
af667a29 340 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 341 switch (adapter->rx_ps_pages) {
342 case 1:
343 case 2:
344 case 3:
345 /* [Extended] Packet Split Receive Descriptor Format
346 *
347 * +-----------------------------------------------------+
348 * 0 | Buffer Address 0 [63:0] |
349 * +-----------------------------------------------------+
350 * 8 | Buffer Address 1 [63:0] |
351 * +-----------------------------------------------------+
352 * 16 | Buffer Address 2 [63:0] |
353 * +-----------------------------------------------------+
354 * 24 | Buffer Address 3 [63:0] |
355 * +-----------------------------------------------------+
356 */
ef456f85 357 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 358 /* [Extended] Receive Descriptor (Write-Back) Format
359 *
360 * 63 48 47 32 31 13 12 8 7 4 3 0
361 * +------------------------------------------------------+
362 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
363 * | Checksum | Ident | | Queue | | Type |
364 * +------------------------------------------------------+
365 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
366 * +------------------------------------------------------+
367 * 63 48 47 32 31 20 19 0
368 */
ef456f85 369 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 370 for (i = 0; i < rx_ring->count; i++) {
ef456f85 371 const char *next_desc;
84f4ee90
TI		 372 buffer_info = &rx_ring->buffer_info[i];
373 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
374 u1 = (struct my_u1 *)rx_desc_ps;
375 staterr =
af667a29 376 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 377
378 if (i == rx_ring->next_to_use)
379 next_desc = " NTU";
380 else if (i == rx_ring->next_to_clean)
381 next_desc = " NTC";
382 else
383 next_desc = "";
384
84f4ee90
TI		 385 if (staterr & E1000_RXD_STAT_DD) {
386 /* Descriptor Done */
ef456f85
JK		 387 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
388 "RWB", i,
389 (unsigned long long)le64_to_cpu(u1->a),
390 (unsigned long long)le64_to_cpu(u1->b),
391 (unsigned long long)le64_to_cpu(u1->c),
392 (unsigned long long)le64_to_cpu(u1->d),
393 buffer_info->skb, next_desc);
84f4ee90 394 } else {
ef456f85
JK		 395 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
396 "R ", i,
397 (unsigned long long)le64_to_cpu(u1->a),
398 (unsigned long long)le64_to_cpu(u1->b),
399 (unsigned long long)le64_to_cpu(u1->c),
400 (unsigned long long)le64_to_cpu(u1->d),
401 (unsigned long long)buffer_info->dma,
402 buffer_info->skb, next_desc);
84f4ee90
TI		 403
404 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 405 e1000e_dump_ps_pages(adapter,
406 buffer_info);
84f4ee90 407 }
84f4ee90
TI		 408 }
409 break;
410 default:
411 case 0:
5f450212 412 /* Extended Receive Descriptor (Read) Format
84f4ee90 413 *
5f450212
BA		 414 * +-----------------------------------------------------+
415 * 0 | Buffer Address [63:0] |
416 * +-----------------------------------------------------+
417 * 8 | Reserved |
418 * +-----------------------------------------------------+
84f4ee90 419 */
ef456f85 420 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 421 /* Extended Receive Descriptor (Write-Back) Format
422 *
423 * 63 48 47 32 31 24 23 4 3 0
424 * +------------------------------------------------------+
425 * | RSS Hash | | | |
426 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
427 * | Packet | IP | | | Type |
428 * | Checksum | Ident | | | |
429 * +------------------------------------------------------+
430 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
431 * +------------------------------------------------------+
432 * 63 48 47 32 31 20 19 0
433 */
ef456f85 434 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 435
436 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 437 const char *next_desc;
438
84f4ee90 439 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 440 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
441 u1 = (struct my_u1 *)rx_desc;
442 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 443
444 if (i == rx_ring->next_to_use)
445 next_desc = " NTU";
446 else if (i == rx_ring->next_to_clean)
447 next_desc = " NTC";
448 else
449 next_desc = "";
450
5f450212
BA		 451 if (staterr & E1000_RXD_STAT_DD) {
452 /* Descriptor Done */
ef456f85
JK		 453 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
454 "RWB", i,
455 (unsigned long long)le64_to_cpu(u1->a),
456 (unsigned long long)le64_to_cpu(u1->b),
457 buffer_info->skb, next_desc);
5f450212 458 } else {
ef456f85
JK		 459 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
460 "R ", i,
461 (unsigned long long)le64_to_cpu(u1->a),
462 (unsigned long long)le64_to_cpu(u1->b),
463 (unsigned long long)buffer_info->dma,
464 buffer_info->skb, next_desc);
5f450212 465
f0c5dadf
ET		 466 if (netif_msg_pktdata(adapter) &&
467 buffer_info->skb)
5f450212
BA		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS, 16,
470 1,
f0c5dadf 471 buffer_info->skb->data,
5f450212
BA		 472 adapter->rx_buffer_len,
473 true);
474 }
84f4ee90
TI		 475 }
476 }
84f4ee90
TI		 477}
478
bc7f75fa
AK		 479/**
480 * e1000_desc_unused - calculate if we have unused descriptors
481 **/
482static int e1000_desc_unused(struct e1000_ring *ring)
483{
484 if (ring->next_to_clean > ring->next_to_use)
485 return ring->next_to_clean - ring->next_to_use - 1;
486
487 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
488}
489
490/**
ad68076e 491 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 492 * @adapter: board private structure
493 * @status: descriptor status field as written by hardware
494 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
495 * @skb: pointer to sk_buff to be indicated to stack
496 **/
497static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 498 struct net_device *netdev, struct sk_buff *skb,
a39fe742 499 u8 status, __le16 vlan)
bc7f75fa 500{
86d70e53 501 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 502 skb->protocol = eth_type_trans(skb, netdev);
503
86d70e53
JK		 504 if (status & E1000_RXD_STAT_VP)
505 __vlan_hwaccel_put_tag(skb, tag);
506
507 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 508}
509
510/**
af667a29 511 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 512 * @adapter: board private structure
513 * @status_err: receive descriptor status and error fields
514 * @csum: receive descriptor csum field
515 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 516 **/
517static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 518 struct sk_buff *skb)
bc7f75fa
AK		 519{
520 u16 status = (u16)status_err;
521 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 522
523 skb_checksum_none_assert(skb);
bc7f75fa 524
afd12939
BA		 525 /* Rx checksum disabled */
526 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
527 return;
528
bc7f75fa
AK		 529 /* Ignore Checksum bit is set */
530 if (status & E1000_RXD_STAT_IXSM)
531 return;
afd12939 532
2e1706f2
BA		 533 /* TCP/UDP checksum error bit or IP checksum error bit is set */
534 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 535 /* let the stack verify checksum errors */
536 adapter->hw_csum_err++;
537 return;
538 }
539
540 /* TCP/UDP Checksum has not been calculated */
541 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
542 return;
543
544 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 545 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 546 adapter->hw_csum_good++;
547}
548
55aa6985 549static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 550{
55aa6985 551 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 552 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 553 s32 ret_val = __ew32_prepare(hw);
554
555 writel(i, rx_ring->tail);
c6e7f51e 556
bdc125f7 557 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 558 u32 rctl = er32(RCTL);
559 ew32(RCTL, rctl & ~E1000_RCTL_EN);
560 e_err("ME firmware caused invalid RDT - resetting\n");
561 schedule_work(&adapter->reset_task);
562 }
563}
564
55aa6985 565static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 566{
55aa6985 567 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 568 struct e1000_hw *hw = &adapter->hw;
bdc125f7 569 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 570
bdc125f7
BA		 571 writel(i, tx_ring->tail);
572
573 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 574 u32 tctl = er32(TCTL);
575 ew32(TCTL, tctl & ~E1000_TCTL_EN);
576 e_err("ME firmware caused invalid TDT - resetting\n");
577 schedule_work(&adapter->reset_task);
578 }
579}
580
bc7f75fa 581/**
5f450212 582 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 583 * @rx_ring: Rx descriptor ring
bc7f75fa 584 **/
55aa6985 585static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 586 int cleaned_count, gfp_t gfp)
bc7f75fa 587{
55aa6985 588 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 589 struct net_device *netdev = adapter->netdev;
590 struct pci_dev *pdev = adapter->pdev;
5f450212 591 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 592 struct e1000_buffer *buffer_info;
593 struct sk_buff *skb;
594 unsigned int i;
89d71a66 595 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 596
597 i = rx_ring->next_to_use;
598 buffer_info = &rx_ring->buffer_info[i];
599
600 while (cleaned_count--) {
601 skb = buffer_info->skb;
602 if (skb) {
603 skb_trim(skb, 0);
604 goto map_skb;
605 }
606
c2fed996 607 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 608 if (!skb) {
609 /* Better luck next round */
610 adapter->alloc_rx_buff_failed++;
611 break;
612 }
613
bc7f75fa
AK		 614 buffer_info->skb = skb;
615map_skb:
0be3f55f 616 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 617 adapter->rx_buffer_len,
0be3f55f
NN		 618 DMA_FROM_DEVICE);
619 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 620 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 621 adapter->rx_dma_failed++;
622 break;
623 }
624
5f450212
BA		 625 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
626 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 627
50849d79 628 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 629 /* Force memory writes to complete before letting h/w
50849d79
TH		 630 * know there are new descriptors to fetch. (Only
631 * applicable for weak-ordered memory model archs,
632 * such as IA-64).
633 */
634 wmb();
c6e7f51e 635 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 636 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 637 else
c5083cf6 638 writel(i, rx_ring->tail);
50849d79 639 }
bc7f75fa
AK		 640 i++;
641 if (i == rx_ring->count)
642 i = 0;
643 buffer_info = &rx_ring->buffer_info[i];
644 }
645
50849d79 646 rx_ring->next_to_use = i;
bc7f75fa
AK		 647}
648
649/**
650 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 651 * @rx_ring: Rx descriptor ring
bc7f75fa 652 **/
55aa6985 653static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 654 int cleaned_count, gfp_t gfp)
bc7f75fa 655{
55aa6985 656 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 657 struct net_device *netdev = adapter->netdev;
658 struct pci_dev *pdev = adapter->pdev;
659 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 660 struct e1000_buffer *buffer_info;
661 struct e1000_ps_page *ps_page;
662 struct sk_buff *skb;
663 unsigned int i, j;
664
665 i = rx_ring->next_to_use;
666 buffer_info = &rx_ring->buffer_info[i];
667
668 while (cleaned_count--) {
669 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
670
671 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 672 ps_page = &buffer_info->ps_pages[j];
673 if (j >= adapter->rx_ps_pages) {
674 /* all unused desc entries get hw null ptr */
af667a29
BA		 675 rx_desc->read.buffer_addr[j + 1] =
676 ~cpu_to_le64(0);
47f44e40
AK		 677 continue;
678 }
679 if (!ps_page->page) {
c2fed996 680 ps_page->page = alloc_page(gfp);
bc7f75fa 681 if (!ps_page->page) {
47f44e40
AK		 682 adapter->alloc_rx_buff_failed++;
683 goto no_buffers;
684 }
0be3f55f
NN		 685 ps_page->dma = dma_map_page(&pdev->dev,
686 ps_page->page,
687 0, PAGE_SIZE,
688 DMA_FROM_DEVICE);
689 if (dma_mapping_error(&pdev->dev,
690 ps_page->dma)) {
47f44e40 691 dev_err(&adapter->pdev->dev,
af667a29 692 "Rx DMA page map failed\n");
47f44e40
AK		 693 adapter->rx_dma_failed++;
694 goto no_buffers;
bc7f75fa 695 }
bc7f75fa 696 }
e921eb1a 697 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 698 * didn't change because each write-back
699 * erases this info.
700 */
af667a29
BA		 701 rx_desc->read.buffer_addr[j + 1] =
702 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 703 }
704
c2fed996
JK		 705 skb = __netdev_alloc_skb_ip_align(netdev,
706 adapter->rx_ps_bsize0,
707 gfp);
bc7f75fa
AK		 708
709 if (!skb) {
710 adapter->alloc_rx_buff_failed++;
711 break;
712 }
713
bc7f75fa 714 buffer_info->skb = skb;
0be3f55f 715 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 716 adapter->rx_ps_bsize0,
0be3f55f
NN		 717 DMA_FROM_DEVICE);
718 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 719 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 720 adapter->rx_dma_failed++;
721 /* cleanup skb */
722 dev_kfree_skb_any(skb);
723 buffer_info->skb = NULL;
724 break;
725 }
726
727 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
728
50849d79 729 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 730 /* Force memory writes to complete before letting h/w
50849d79
TH		 731 * know there are new descriptors to fetch. (Only
732 * applicable for weak-ordered memory model archs,
733 * such as IA-64).
734 */
735 wmb();
c6e7f51e 736 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 737 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 738 else
c5083cf6 739 writel(i << 1, rx_ring->tail);
50849d79
TH		 740 }
741
bc7f75fa
AK		 742 i++;
743 if (i == rx_ring->count)
744 i = 0;
745 buffer_info = &rx_ring->buffer_info[i];
746 }
747
748no_buffers:
50849d79 749 rx_ring->next_to_use = i;
bc7f75fa
AK		 750}
751
97ac8cae
BA		 752/**
753 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 754 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 755 * @cleaned_count: number of buffers to allocate this pass
756 **/
757
55aa6985 758static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 759 int cleaned_count, gfp_t gfp)
97ac8cae 760{
55aa6985 761 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 762 struct net_device *netdev = adapter->netdev;
763 struct pci_dev *pdev = adapter->pdev;
5f450212 764 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 765 struct e1000_buffer *buffer_info;
766 struct sk_buff *skb;
767 unsigned int i;
89d71a66 768 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 769
770 i = rx_ring->next_to_use;
771 buffer_info = &rx_ring->buffer_info[i];
772
773 while (cleaned_count--) {
774 skb = buffer_info->skb;
775 if (skb) {
776 skb_trim(skb, 0);
777 goto check_page;
778 }
779
c2fed996 780 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 781 if (unlikely(!skb)) {
782 /* Better luck next round */
783 adapter->alloc_rx_buff_failed++;
784 break;
785 }
786
97ac8cae
BA		 787 buffer_info->skb = skb;
788check_page:
789 /* allocate a new page if necessary */
790 if (!buffer_info->page) {
c2fed996 791 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 792 if (unlikely(!buffer_info->page)) {
793 adapter->alloc_rx_buff_failed++;
794 break;
795 }
796 }
797
798 if (!buffer_info->dma)
0be3f55f 799 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 800 buffer_info->page, 0,
801 PAGE_SIZE,
0be3f55f 802 DMA_FROM_DEVICE);
97ac8cae 803
5f450212
BA		 804 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
805 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 806
807 if (unlikely(++i == rx_ring->count))
808 i = 0;
809 buffer_info = &rx_ring->buffer_info[i];
810 }
811
812 if (likely(rx_ring->next_to_use != i)) {
813 rx_ring->next_to_use = i;
814 if (unlikely(i-- == 0))
815 i = (rx_ring->count - 1);
816
817 /* Force memory writes to complete before letting h/w
818 * know there are new descriptors to fetch. (Only
819 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 820 * such as IA-64).
821 */
97ac8cae 822 wmb();
c6e7f51e 823 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 824 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 825 else
c5083cf6 826 writel(i, rx_ring->tail);
97ac8cae
BA		 827 }
828}
829
70495a50
BA		 830static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
831 struct sk_buff *skb)
832{
833 if (netdev->features & NETIF_F_RXHASH)
834 skb->rxhash = le32_to_cpu(rss);
835}
836
bc7f75fa 837/**
55aa6985
BA		 838 * e1000_clean_rx_irq - Send received data up the network stack
839 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 840 *
841 * the return value indicates whether actual cleaning was done, there
842 * is no guarantee that everything was cleaned
843 **/
55aa6985
BA		 844static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
845 int work_to_do)
bc7f75fa 846{
55aa6985 847 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 848 struct net_device *netdev = adapter->netdev;
849 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 850 struct e1000_hw *hw = &adapter->hw;
5f450212 851 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 852 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 853 u32 length, staterr;
bc7f75fa
AK		 854 unsigned int i;
855 int cleaned_count = 0;
3db1cd5c 856 bool cleaned = false;
bc7f75fa
AK		 857 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
858
859 i = rx_ring->next_to_clean;
5f450212
BA		 860 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
861 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 862 buffer_info = &rx_ring->buffer_info[i];
863
5f450212 864 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 865 struct sk_buff *skb;
bc7f75fa
AK		 866
867 if (*work_done >= work_to_do)
868 break;
869 (*work_done)++;
2d0bb1c1 870 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 871
bc7f75fa
AK		 872 skb = buffer_info->skb;
873 buffer_info->skb = NULL;
874
875 prefetch(skb->data - NET_IP_ALIGN);
876
877 i++;
878 if (i == rx_ring->count)
879 i = 0;
5f450212 880 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 881 prefetch(next_rxd);
882
883 next_buffer = &rx_ring->buffer_info[i];
884
3db1cd5c 885 cleaned = true;
bc7f75fa 886 cleaned_count++;
0be3f55f 887 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 888 buffer_info->dma,
889 adapter->rx_buffer_len,
0be3f55f 890 DMA_FROM_DEVICE);
bc7f75fa
AK		 891 buffer_info->dma = 0;
892
5f450212 893 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 894
e921eb1a 895 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 896 * packet, if that's the case we need to toss it. In fact, we
897 * need to toss every packet with the EOP bit clear and the
898 * next frame that _does_ have the EOP bit set, as it is by
899 * definition only a frame fragment
900 */
5f450212 901 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 902 adapter->flags2 |= FLAG2_IS_DISCARDING;
903
904 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 905 /* All receives must fit into a single buffer */
3bb99fe2 906 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 907 /* recycle */
908 buffer_info->skb = skb;
5f450212 909 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 910 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 911 goto next_desc;
912 }
913
cf955e6c
BG		 914 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
915 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 916 /* recycle */
917 buffer_info->skb = skb;
918 goto next_desc;
919 }
920
eb7c3adb 921 /* adjust length to remove Ethernet CRC */
0184039a
BG		 922 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
923 /* If configured to store CRC, don't subtract FCS,
924 * but keep the FCS bytes out of the total_rx_bytes
925 * counter
926 */
927 if (netdev->features & NETIF_F_RXFCS)
928 total_rx_bytes -= 4;
929 else
930 length -= 4;
931 }
eb7c3adb 932
bc7f75fa
AK		 933 total_rx_bytes += length;
934 total_rx_packets++;
935
e921eb1a 936 /* code added for copybreak, this should improve
bc7f75fa 937 * performance for small packets with large amounts
ad68076e
BA		 938 * of reassembly being done in the stack
939 */
bc7f75fa
AK		 940 if (length < copybreak) {
941 struct sk_buff *new_skb =
89d71a66 942 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 943 if (new_skb) {
808ff676
BA		 944 skb_copy_to_linear_data_offset(new_skb,
945 -NET_IP_ALIGN,
946 (skb->data -
947 NET_IP_ALIGN),
948 (length +
949 NET_IP_ALIGN));
bc7f75fa
AK		 950 /* save the skb in buffer_info as good */
951 buffer_info->skb = skb;
952 skb = new_skb;
953 }
954 /* else just continue with the old one */
955 }
956 /* end copybreak code */
957 skb_put(skb, length);
958
959 /* Receive Checksum Offload */
2e1706f2 960 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 961
70495a50
BA		 962 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
963
5f450212
BA		 964 e1000_receive_skb(adapter, netdev, skb, staterr,
965 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 966
967next_desc:
5f450212 968 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 969
970 /* return some buffers to hardware, one at a time is too slow */
971 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 972 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 973 GFP_ATOMIC);
bc7f75fa
AK		 974 cleaned_count = 0;
975 }
976
977 /* use prefetched values */
978 rx_desc = next_rxd;
979 buffer_info = next_buffer;
5f450212
BA		 980
981 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 982 }
983 rx_ring->next_to_clean = i;
984
985 cleaned_count = e1000_desc_unused(rx_ring);
986 if (cleaned_count)
55aa6985 987 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 988
bc7f75fa 989 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 990 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 991 return cleaned;
992}
993
55aa6985
BA		 994static void e1000_put_txbuf(struct e1000_ring *tx_ring,
995 struct e1000_buffer *buffer_info)
bc7f75fa 996{
55aa6985
BA		 997 struct e1000_adapter *adapter = tx_ring->adapter;
998
03b1320d
AD		 999 if (buffer_info->dma) {
1000 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1001 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1002 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1003 else
0be3f55f
NN		 1004 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1005 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1006 buffer_info->dma = 0;
1007 }
bc7f75fa
AK		 1008 if (buffer_info->skb) {
1009 dev_kfree_skb_any(buffer_info->skb);
1010 buffer_info->skb = NULL;
1011 }
1b7719c4 1012 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1013}
1014
41cec6f1 1015static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1016{
41cec6f1
BA		 1017 struct e1000_adapter *adapter = container_of(work,
1018 struct e1000_adapter,
1019 print_hang_task);
09357b00 1020 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1021 struct e1000_ring *tx_ring = adapter->tx_ring;
1022 unsigned int i = tx_ring->next_to_clean;
1023 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1024 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1025 struct e1000_hw *hw = &adapter->hw;
1026 u16 phy_status, phy_1000t_status, phy_ext_status;
1027 u16 pci_status;
1028
615b32af
JB		 1029 if (test_bit(__E1000_DOWN, &adapter->state))
1030 return;
1031
09357b00
JK		 1032 if (!adapter->tx_hang_recheck &&
1033 (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1034 /* May be block on write-back, flush and detect again
09357b00
JK		 1035 * flush pending descriptor writebacks to memory
1036 */
1037 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1038 /* execute the writes immediately */
1039 e1e_flush();
e921eb1a 1040 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1041 * the write is successful
1042 */
1043 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1044 /* execute the writes immediately */
1045 e1e_flush();
09357b00
JK		 1046 adapter->tx_hang_recheck = true;
1047 return;
1048 }
1049 /* Real hang detected */
1050 adapter->tx_hang_recheck = false;
1051 netif_stop_queue(netdev);
1052
41cec6f1
BA		 1053 e1e_rphy(hw, PHY_STATUS, &phy_status);
1054 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1055 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1056
41cec6f1
BA		 1057 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1058
1059 /* detected Hardware unit hang */
1060 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1061 " TDH <%x>\n"
1062 " TDT <%x>\n"
1063 " next_to_use <%x>\n"
1064 " next_to_clean <%x>\n"
1065 "buffer_info[next_to_clean]:\n"
1066 " time_stamp <%lx>\n"
1067 " next_to_watch <%x>\n"
1068 " jiffies <%lx>\n"
41cec6f1
BA		 1069 " next_to_watch.status <%x>\n"
1070 "MAC Status <%x>\n"
1071 "PHY Status <%x>\n"
1072 "PHY 1000BASE-T Status <%x>\n"
1073 "PHY Extended Status <%x>\n"
1074 "PCI Status <%x>\n",
c5083cf6
BA		 1075 readl(tx_ring->head),
1076 readl(tx_ring->tail),
44defeb3
JK		 1077 tx_ring->next_to_use,
1078 tx_ring->next_to_clean,
1079 tx_ring->buffer_info[eop].time_stamp,
1080 eop,
1081 jiffies,
41cec6f1
BA		 1082 eop_desc->upper.fields.status,
1083 er32(STATUS),
1084 phy_status,
1085 phy_1000t_status,
1086 phy_ext_status,
1087 pci_status);
7c0427ee
BA		 1088
1089 /* Suggest workaround for known h/w issue */
1090 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1091 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1092}
1093
1094/**
1095 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1096 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1097 *
1098 * the return value indicates whether actual cleaning was done, there
1099 * is no guarantee that everything was cleaned
1100 **/
55aa6985 1101static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1102{
55aa6985 1103 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1104 struct net_device *netdev = adapter->netdev;
1105 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1106 struct e1000_tx_desc *tx_desc, *eop_desc;
1107 struct e1000_buffer *buffer_info;
1108 unsigned int i, eop;
1109 unsigned int count = 0;
bc7f75fa 1110 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1111 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1112
1113 i = tx_ring->next_to_clean;
1114 eop = tx_ring->buffer_info[i].next_to_watch;
1115 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1116
12d04a3c
AD		 1117 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1118 (count < tx_ring->count)) {
a86043c2 1119 bool cleaned = false;
2d0bb1c1 1120 rmb(); /* read buffer_info after eop_desc */
a86043c2 1121 for (; !cleaned; count++) {
bc7f75fa
AK		 1122 tx_desc = E1000_TX_DESC(*tx_ring, i);
1123 buffer_info = &tx_ring->buffer_info[i];
1124 cleaned = (i == eop);
1125
1126 if (cleaned) {
9ed318d5
TH		 1127 total_tx_packets += buffer_info->segs;
1128 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1129 if (buffer_info->skb) {
1130 bytes_compl += buffer_info->skb->len;
1131 pkts_compl++;
1132 }
bc7f75fa
AK		 1133 }
1134
55aa6985 1135 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1136 tx_desc->upper.data = 0;
1137
1138 i++;
1139 if (i == tx_ring->count)
1140 i = 0;
1141 }
1142
dac87619
TL		 1143 if (i == tx_ring->next_to_use)
1144 break;
bc7f75fa
AK		 1145 eop = tx_ring->buffer_info[i].next_to_watch;
1146 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1147 }
1148
1149 tx_ring->next_to_clean = i;
1150
3f0cfa3b
TH		 1151 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1152
bc7f75fa 1153#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1154 if (count && netif_carrier_ok(netdev) &&
1155 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1156 /* Make sure that anybody stopping the queue after this
1157 * sees the new next_to_clean.
1158 */
1159 smp_mb();
1160
1161 if (netif_queue_stopped(netdev) &&
1162 !(test_bit(__E1000_DOWN, &adapter->state))) {
1163 netif_wake_queue(netdev);
1164 ++adapter->restart_queue;
1165 }
1166 }
1167
1168 if (adapter->detect_tx_hung) {
e921eb1a 1169 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1170 * check with the clearing of time_stamp and movement of i
1171 */
3db1cd5c 1172 adapter->detect_tx_hung = false;
12d04a3c
AD		 1173 if (tx_ring->buffer_info[i].time_stamp &&
1174 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1175 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1176 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1177 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1178 else
1179 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1180 }
1181 adapter->total_tx_bytes += total_tx_bytes;
1182 adapter->total_tx_packets += total_tx_packets;
807540ba 1183 return count < tx_ring->count;
bc7f75fa
AK		 1184}
1185
bc7f75fa
AK		 1186/**
1187 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1188 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1189 *
1190 * the return value indicates whether actual cleaning was done, there
1191 * is no guarantee that everything was cleaned
1192 **/
55aa6985
BA		 1193static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1194 int work_to_do)
bc7f75fa 1195{
55aa6985 1196 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1197 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1198 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1199 struct net_device *netdev = adapter->netdev;
1200 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1201 struct e1000_buffer *buffer_info, *next_buffer;
1202 struct e1000_ps_page *ps_page;
1203 struct sk_buff *skb;
1204 unsigned int i, j;
1205 u32 length, staterr;
1206 int cleaned_count = 0;
3db1cd5c 1207 bool cleaned = false;
bc7f75fa
AK		 1208 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1209
1210 i = rx_ring->next_to_clean;
1211 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1212 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1213 buffer_info = &rx_ring->buffer_info[i];
1214
1215 while (staterr & E1000_RXD_STAT_DD) {
1216 if (*work_done >= work_to_do)
1217 break;
1218 (*work_done)++;
1219 skb = buffer_info->skb;
2d0bb1c1 1220 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1221
1222 /* in the packet split case this is header only */
1223 prefetch(skb->data - NET_IP_ALIGN);
1224
1225 i++;
1226 if (i == rx_ring->count)
1227 i = 0;
1228 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1229 prefetch(next_rxd);
1230
1231 next_buffer = &rx_ring->buffer_info[i];
1232
3db1cd5c 1233 cleaned = true;
bc7f75fa 1234 cleaned_count++;
0be3f55f 1235 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1236 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1237 buffer_info->dma = 0;
1238
af667a29 1239 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1240 if (!(staterr & E1000_RXD_STAT_EOP))
1241 adapter->flags2 |= FLAG2_IS_DISCARDING;
1242
1243 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1244 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1245 dev_kfree_skb_irq(skb);
b94b5028
JB		 1246 if (staterr & E1000_RXD_STAT_EOP)
1247 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1248 goto next_desc;
1249 }
1250
cf955e6c
BG		 1251 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1252 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1253 dev_kfree_skb_irq(skb);
1254 goto next_desc;
1255 }
1256
1257 length = le16_to_cpu(rx_desc->wb.middle.length0);
1258
1259 if (!length) {
ef456f85 1260 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1261 dev_kfree_skb_irq(skb);
1262 goto next_desc;
1263 }
1264
1265 /* Good Receive */
1266 skb_put(skb, length);
1267
1268 {
e921eb1a 1269 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1270 * it more efficient than reusing j
1271 */
1272 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1273
e921eb1a 1274 /* page alloc/put takes too long and effects small
0e15df49
BA		 1275 * packet throughput, so unsplit small packets and
1276 * save the alloc/put only valid in softirq (napi)
1277 * context to call kmap_*
ad68076e 1278 */
0e15df49
BA		 1279 if (l1 && (l1 <= copybreak) &&
1280 ((length + l1) <= adapter->rx_ps_bsize0)) {
1281 u8 *vaddr;
1282
1283 ps_page = &buffer_info->ps_pages[0];
1284
e921eb1a 1285 /* there is no documentation about how to call
0e15df49
BA		 1286 * kmap_atomic, so we can't hold the mapping
1287 * very long
1288 */
1289 dma_sync_single_for_cpu(&pdev->dev,
1290 ps_page->dma,
1291 PAGE_SIZE,
1292 DMA_FROM_DEVICE);
9f393834 1293 vaddr = kmap_atomic(ps_page->page);
0e15df49 1294 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1295 kunmap_atomic(vaddr);
0e15df49
BA		 1296 dma_sync_single_for_device(&pdev->dev,
1297 ps_page->dma,
1298 PAGE_SIZE,
1299 DMA_FROM_DEVICE);
1300
1301 /* remove the CRC */
0184039a
BG		 1302 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1303 if (!(netdev->features & NETIF_F_RXFCS))
1304 l1 -= 4;
1305 }
0e15df49
BA		 1306
1307 skb_put(skb, l1);
1308 goto copydone;
1309 } /* if */
bc7f75fa
AK		 1310 }
1311
1312 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1313 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1314 if (!length)
1315 break;
1316
47f44e40 1317 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1318 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1319 DMA_FROM_DEVICE);
bc7f75fa
AK		 1320 ps_page->dma = 0;
1321 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1322 ps_page->page = NULL;
1323 skb->len += length;
1324 skb->data_len += length;
98a045d7 1325 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1326 }
1327
eb7c3adb
JK		 1328 /* strip the ethernet crc, problem is we're using pages now so
1329 * this whole operation can get a little cpu intensive
1330 */
0184039a
BG		 1331 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1332 if (!(netdev->features & NETIF_F_RXFCS))
1333 pskb_trim(skb, skb->len - 4);
1334 }
eb7c3adb 1335
bc7f75fa
AK		 1336copydone:
1337 total_rx_bytes += skb->len;
1338 total_rx_packets++;
1339
2e1706f2 1340 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1341
70495a50
BA		 1342 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1343
bc7f75fa
AK		 1344 if (rx_desc->wb.upper.header_status &
1345 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1346 adapter->rx_hdr_split++;
1347
1348 e1000_receive_skb(adapter, netdev, skb,
1349 staterr, rx_desc->wb.middle.vlan);
1350
1351next_desc:
1352 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1353 buffer_info->skb = NULL;
1354
1355 /* return some buffers to hardware, one at a time is too slow */
1356 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1357 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1358 GFP_ATOMIC);
bc7f75fa
AK		 1359 cleaned_count = 0;
1360 }
1361
1362 /* use prefetched values */
1363 rx_desc = next_rxd;
1364 buffer_info = next_buffer;
1365
1366 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1367 }
1368 rx_ring->next_to_clean = i;
1369
1370 cleaned_count = e1000_desc_unused(rx_ring);
1371 if (cleaned_count)
55aa6985 1372 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1373
bc7f75fa 1374 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1375 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1376 return cleaned;
1377}
1378
97ac8cae
BA		 1379/**
1380 * e1000_consume_page - helper function
1381 **/
1382static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1383 u16 length)
1384{
1385 bi->page = NULL;
1386 skb->len += length;
1387 skb->data_len += length;
98a045d7 1388 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1389}
1390
1391/**
1392 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1393 * @adapter: board private structure
1394 *
1395 * the return value indicates whether actual cleaning was done, there
1396 * is no guarantee that everything was cleaned
1397 **/
55aa6985
BA		 1398static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1399 int work_to_do)
97ac8cae 1400{
55aa6985 1401 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1402 struct net_device *netdev = adapter->netdev;
1403 struct pci_dev *pdev = adapter->pdev;
5f450212 1404 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1405 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1406 u32 length, staterr;
97ac8cae
BA		 1407 unsigned int i;
1408 int cleaned_count = 0;
1409 bool cleaned = false;
1410 unsigned int total_rx_bytes=0, total_rx_packets=0;
1411
1412 i = rx_ring->next_to_clean;
5f450212
BA		 1413 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1414 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1415 buffer_info = &rx_ring->buffer_info[i];
1416
5f450212 1417 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1418 struct sk_buff *skb;
97ac8cae
BA		 1419
1420 if (*work_done >= work_to_do)
1421 break;
1422 (*work_done)++;
2d0bb1c1 1423 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1424
97ac8cae
BA		 1425 skb = buffer_info->skb;
1426 buffer_info->skb = NULL;
1427
1428 ++i;
1429 if (i == rx_ring->count)
1430 i = 0;
5f450212 1431 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1432 prefetch(next_rxd);
1433
1434 next_buffer = &rx_ring->buffer_info[i];
1435
1436 cleaned = true;
1437 cleaned_count++;
0be3f55f
NN		 1438 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1439 DMA_FROM_DEVICE);
97ac8cae
BA		 1440 buffer_info->dma = 0;
1441
5f450212 1442 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1443
1444 /* errors is only valid for DD + EOP descriptors */
5f450212 1445 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1446 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1447 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1448 /* recycle both page and skb */
1449 buffer_info->skb = skb;
1450 /* an error means any chain goes out the window too */
1451 if (rx_ring->rx_skb_top)
1452 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1453 rx_ring->rx_skb_top = NULL;
1454 goto next_desc;
97ac8cae
BA		 1455 }
1456
f0f1a172 1457#define rxtop (rx_ring->rx_skb_top)
5f450212 1458 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1459 /* this descriptor is only the beginning (or middle) */
1460 if (!rxtop) {
1461 /* this is the beginning of a chain */
1462 rxtop = skb;
1463 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1464 0, length);
1465 } else {
1466 /* this is the middle of a chain */
1467 skb_fill_page_desc(rxtop,
1468 skb_shinfo(rxtop)->nr_frags,
1469 buffer_info->page, 0, length);
1470 /* re-use the skb, only consumed the page */
1471 buffer_info->skb = skb;
1472 }
1473 e1000_consume_page(buffer_info, rxtop, length);
1474 goto next_desc;
1475 } else {
1476 if (rxtop) {
1477 /* end of the chain */
1478 skb_fill_page_desc(rxtop,
1479 skb_shinfo(rxtop)->nr_frags,
1480 buffer_info->page, 0, length);
1481 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1482 * page
1483 */
97ac8cae
BA		 1484 buffer_info->skb = skb;
1485 skb = rxtop;
1486 rxtop = NULL;
1487 e1000_consume_page(buffer_info, skb, length);
1488 } else {
1489 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1490 * copybreak to save the put_page/alloc_page
1491 */
97ac8cae
BA		 1492 if (length <= copybreak &&
1493 skb_tailroom(skb) >= length) {
1494 u8 *vaddr;
4679026d 1495 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1496 memcpy(skb_tail_pointer(skb), vaddr,
1497 length);
4679026d 1498 kunmap_atomic(vaddr);
97ac8cae 1499 /* re-use the page, so don't erase
e921eb1a
BA		 1500 * buffer_info->page
1501 */
97ac8cae
BA		 1502 skb_put(skb, length);
1503 } else {
1504 skb_fill_page_desc(skb, 0,
1505 buffer_info->page, 0,
1506 length);
1507 e1000_consume_page(buffer_info, skb,
1508 length);
1509 }
1510 }
1511 }
1512
2e1706f2
BA		 1513 /* Receive Checksum Offload */
1514 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1515
70495a50
BA		 1516 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1517
97ac8cae
BA		 1518 /* probably a little skewed due to removing CRC */
1519 total_rx_bytes += skb->len;
1520 total_rx_packets++;
1521
1522 /* eth type trans needs skb->data to point to something */
1523 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1524 e_err("pskb_may_pull failed.\n");
ef5ab89c 1525 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1526 goto next_desc;
1527 }
1528
5f450212
BA		 1529 e1000_receive_skb(adapter, netdev, skb, staterr,
1530 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1531
1532next_desc:
5f450212 1533 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1534
1535 /* return some buffers to hardware, one at a time is too slow */
1536 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1537 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1538 GFP_ATOMIC);
97ac8cae
BA		 1539 cleaned_count = 0;
1540 }
1541
1542 /* use prefetched values */
1543 rx_desc = next_rxd;
1544 buffer_info = next_buffer;
5f450212
BA		 1545
1546 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1547 }
1548 rx_ring->next_to_clean = i;
1549
1550 cleaned_count = e1000_desc_unused(rx_ring);
1551 if (cleaned_count)
55aa6985 1552 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1553
1554 adapter->total_rx_bytes += total_rx_bytes;
1555 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1556 return cleaned;
1557}
1558
bc7f75fa
AK		 1559/**
1560 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1561 * @rx_ring: Rx descriptor ring
bc7f75fa 1562 **/
55aa6985 1563static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1564{
55aa6985 1565 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1566 struct e1000_buffer *buffer_info;
1567 struct e1000_ps_page *ps_page;
1568 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1569 unsigned int i, j;
1570
1571 /* Free all the Rx ring sk_buffs */
1572 for (i = 0; i < rx_ring->count; i++) {
1573 buffer_info = &rx_ring->buffer_info[i];
1574 if (buffer_info->dma) {
1575 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1576 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1577 adapter->rx_buffer_len,
0be3f55f 1578 DMA_FROM_DEVICE);
97ac8cae 1579 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1580 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1581 PAGE_SIZE,
0be3f55f 1582 DMA_FROM_DEVICE);
bc7f75fa 1583 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1584 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1585 adapter->rx_ps_bsize0,
0be3f55f 1586 DMA_FROM_DEVICE);
bc7f75fa
AK		 1587 buffer_info->dma = 0;
1588 }
1589
97ac8cae
BA		 1590 if (buffer_info->page) {
1591 put_page(buffer_info->page);
1592 buffer_info->page = NULL;
1593 }
1594
bc7f75fa
AK		 1595 if (buffer_info->skb) {
1596 dev_kfree_skb(buffer_info->skb);
1597 buffer_info->skb = NULL;
1598 }
1599
1600 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1601 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1602 if (!ps_page->page)
1603 break;
0be3f55f
NN		 1604 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1605 DMA_FROM_DEVICE);
bc7f75fa
AK		 1606 ps_page->dma = 0;
1607 put_page(ps_page->page);
1608 ps_page->page = NULL;
1609 }
1610 }
1611
1612 /* there also may be some cached data from a chained receive */
1613 if (rx_ring->rx_skb_top) {
1614 dev_kfree_skb(rx_ring->rx_skb_top);
1615 rx_ring->rx_skb_top = NULL;
1616 }
1617
bc7f75fa
AK		 1618 /* Zero out the descriptor ring */
1619 memset(rx_ring->desc, 0, rx_ring->size);
1620
1621 rx_ring->next_to_clean = 0;
1622 rx_ring->next_to_use = 0;
b94b5028 1623 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1624
c5083cf6 1625 writel(0, rx_ring->head);
bdc125f7
BA		 1626 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1627 e1000e_update_rdt_wa(rx_ring, 0);
1628 else
1629 writel(0, rx_ring->tail);
bc7f75fa
AK		 1630}
1631
a8f88ff5
JB		 1632static void e1000e_downshift_workaround(struct work_struct *work)
1633{
1634 struct e1000_adapter *adapter = container_of(work,
1635 struct e1000_adapter, downshift_task);
1636
615b32af
JB		 1637 if (test_bit(__E1000_DOWN, &adapter->state))
1638 return;
1639
a8f88ff5
JB		 1640 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1641}
1642
bc7f75fa
AK		 1643/**
1644 * e1000_intr_msi - Interrupt Handler
1645 * @irq: interrupt number
1646 * @data: pointer to a network interface device structure
1647 **/
1648static irqreturn_t e1000_intr_msi(int irq, void *data)
1649{
1650 struct net_device *netdev = data;
1651 struct e1000_adapter *adapter = netdev_priv(netdev);
1652 struct e1000_hw *hw = &adapter->hw;
1653 u32 icr = er32(ICR);
1654
e921eb1a 1655 /* read ICR disables interrupts using IAM */
573cca8c 1656 if (icr & E1000_ICR_LSC) {
f92518dd 1657 hw->mac.get_link_status = true;
e921eb1a 1658 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1659 * disconnect (LSC) before accessing any PHY registers
1660 */
bc7f75fa
AK		 1661 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1662 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1663 schedule_work(&adapter->downshift_task);
bc7f75fa 1664
e921eb1a 1665 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1666 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1667 * adapter in watchdog
1668 */
bc7f75fa
AK		 1669 if (netif_carrier_ok(netdev) &&
1670 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1671 /* disable receives */
1672 u32 rctl = er32(RCTL);
1673 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1674 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1675 }
1676 /* guard against interrupt when we're going down */
1677 if (!test_bit(__E1000_DOWN, &adapter->state))
1678 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1679 }
1680
288379f0 1681 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1682 adapter->total_tx_bytes = 0;
1683 adapter->total_tx_packets = 0;
1684 adapter->total_rx_bytes = 0;
1685 adapter->total_rx_packets = 0;
288379f0 1686 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1687 }
1688
1689 return IRQ_HANDLED;
1690}
1691
1692/**
1693 * e1000_intr - Interrupt Handler
1694 * @irq: interrupt number
1695 * @data: pointer to a network interface device structure
1696 **/
1697static irqreturn_t e1000_intr(int irq, void *data)
1698{
1699 struct net_device *netdev = data;
1700 struct e1000_adapter *adapter = netdev_priv(netdev);
1701 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1702 u32 rctl, icr = er32(ICR);
4662e82b 1703
a68ea775 1704 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1705 return IRQ_NONE; /* Not our interrupt */
1706
e921eb1a 1707 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1708 * not set, then the adapter didn't send an interrupt
1709 */
bc7f75fa
AK		 1710 if (!(icr & E1000_ICR_INT_ASSERTED))
1711 return IRQ_NONE;
1712
e921eb1a 1713 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1714 * interrupts are masked. No need for the
1715 * IMC write
1716 */
bc7f75fa 1717
573cca8c 1718 if (icr & E1000_ICR_LSC) {
f92518dd 1719 hw->mac.get_link_status = true;
e921eb1a 1720 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1721 * disconnect (LSC) before accessing any PHY registers
1722 */
bc7f75fa
AK		 1723 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1724 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1725 schedule_work(&adapter->downshift_task);
bc7f75fa 1726
e921eb1a 1727 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1728 * For packet buffer work-around on link down event;
1729 * disable receives here in the ISR and
1730 * reset adapter in watchdog
1731 */
1732 if (netif_carrier_ok(netdev) &&
1733 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1734 /* disable receives */
1735 rctl = er32(RCTL);
1736 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1737 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1738 }
1739 /* guard against interrupt when we're going down */
1740 if (!test_bit(__E1000_DOWN, &adapter->state))
1741 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1742 }
1743
288379f0 1744 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1745 adapter->total_tx_bytes = 0;
1746 adapter->total_tx_packets = 0;
1747 adapter->total_rx_bytes = 0;
1748 adapter->total_rx_packets = 0;
288379f0 1749 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1750 }
1751
1752 return IRQ_HANDLED;
1753}
1754
4662e82b
BA		 1755static irqreturn_t e1000_msix_other(int irq, void *data)
1756{
1757 struct net_device *netdev = data;
1758 struct e1000_adapter *adapter = netdev_priv(netdev);
1759 struct e1000_hw *hw = &adapter->hw;
1760 u32 icr = er32(ICR);
1761
1762 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1763 if (!test_bit(__E1000_DOWN, &adapter->state))
1764 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1765 return IRQ_NONE;
1766 }
1767
1768 if (icr & adapter->eiac_mask)
1769 ew32(ICS, (icr & adapter->eiac_mask));
1770
1771 if (icr & E1000_ICR_OTHER) {
1772 if (!(icr & E1000_ICR_LSC))
1773 goto no_link_interrupt;
f92518dd 1774 hw->mac.get_link_status = true;
4662e82b
BA		 1775 /* guard against interrupt when we're going down */
1776 if (!test_bit(__E1000_DOWN, &adapter->state))
1777 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1778 }
1779
1780no_link_interrupt:
a3c69fef
JB		 1781 if (!test_bit(__E1000_DOWN, &adapter->state))
1782 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1783
1784 return IRQ_HANDLED;
1785}
1786
1787
1788static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1789{
1790 struct net_device *netdev = data;
1791 struct e1000_adapter *adapter = netdev_priv(netdev);
1792 struct e1000_hw *hw = &adapter->hw;
1793 struct e1000_ring *tx_ring = adapter->tx_ring;
1794
1795
1796 adapter->total_tx_bytes = 0;
1797 adapter->total_tx_packets = 0;
1798
55aa6985 1799 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1800 /* Ring was not completely cleaned, so fire another interrupt */
1801 ew32(ICS, tx_ring->ims_val);
1802
1803 return IRQ_HANDLED;
1804}
1805
1806static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1807{
1808 struct net_device *netdev = data;
1809 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1810 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1811
1812 /* Write the ITR value calculated at the end of the
1813 * previous interrupt.
1814 */
55aa6985
BA		 1815 if (rx_ring->set_itr) {
1816 writel(1000000000 / (rx_ring->itr_val * 256),
1817 rx_ring->itr_register);
1818 rx_ring->set_itr = 0;
4662e82b
BA		 1819 }
1820
288379f0 1821 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1822 adapter->total_rx_bytes = 0;
1823 adapter->total_rx_packets = 0;
288379f0 1824 __napi_schedule(&adapter->napi);
4662e82b
BA		 1825 }
1826 return IRQ_HANDLED;
1827}
1828
1829/**
1830 * e1000_configure_msix - Configure MSI-X hardware
1831 *
1832 * e1000_configure_msix sets up the hardware to properly
1833 * generate MSI-X interrupts.
1834 **/
1835static void e1000_configure_msix(struct e1000_adapter *adapter)
1836{
1837 struct e1000_hw *hw = &adapter->hw;
1838 struct e1000_ring *rx_ring = adapter->rx_ring;
1839 struct e1000_ring *tx_ring = adapter->tx_ring;
1840 int vector = 0;
1841 u32 ctrl_ext, ivar = 0;
1842
1843 adapter->eiac_mask = 0;
1844
1845 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1846 if (hw->mac.type == e1000_82574) {
1847 u32 rfctl = er32(RFCTL);
1848 rfctl |= E1000_RFCTL_ACK_DIS;
1849 ew32(RFCTL, rfctl);
1850 }
1851
1852#define E1000_IVAR_INT_ALLOC_VALID 0x8
1853 /* Configure Rx vector */
1854 rx_ring->ims_val = E1000_IMS_RXQ0;
1855 adapter->eiac_mask |= rx_ring->ims_val;
1856 if (rx_ring->itr_val)
1857 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1858 rx_ring->itr_register);
4662e82b 1859 else
c5083cf6 1860 writel(1, rx_ring->itr_register);
4662e82b
BA		 1861 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1862
1863 /* Configure Tx vector */
1864 tx_ring->ims_val = E1000_IMS_TXQ0;
1865 vector++;
1866 if (tx_ring->itr_val)
1867 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1868 tx_ring->itr_register);
4662e82b 1869 else
c5083cf6 1870 writel(1, tx_ring->itr_register);
4662e82b
BA		 1871 adapter->eiac_mask |= tx_ring->ims_val;
1872 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1873
1874 /* set vector for Other Causes, e.g. link changes */
1875 vector++;
1876 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1877 if (rx_ring->itr_val)
1878 writel(1000000000 / (rx_ring->itr_val * 256),
1879 hw->hw_addr + E1000_EITR_82574(vector));
1880 else
1881 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1882
1883 /* Cause Tx interrupts on every write back */
1884 ivar |= (1 << 31);
1885
1886 ew32(IVAR, ivar);
1887
1888 /* enable MSI-X PBA support */
1889 ctrl_ext = er32(CTRL_EXT);
1890 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1891
1892 /* Auto-Mask Other interrupts upon ICR read */
1893#define E1000_EIAC_MASK_82574 0x01F00000
1894 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1895 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1896 ew32(CTRL_EXT, ctrl_ext);
1897 e1e_flush();
1898}
1899
1900void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1901{
1902 if (adapter->msix_entries) {
1903 pci_disable_msix(adapter->pdev);
1904 kfree(adapter->msix_entries);
1905 adapter->msix_entries = NULL;
1906 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1907 pci_disable_msi(adapter->pdev);
1908 adapter->flags &= ~FLAG_MSI_ENABLED;
1909 }
4662e82b
BA		 1910}
1911
1912/**
1913 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1914 *
1915 * Attempt to configure interrupts using the best available
1916 * capabilities of the hardware and kernel.
1917 **/
1918void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1919{
1920 int err;
8e86acd7 1921 int i;
4662e82b
BA		 1922
1923 switch (adapter->int_mode) {
1924 case E1000E_INT_MODE_MSIX:
1925 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1926 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1927 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1928 sizeof(struct msix_entry),
1929 GFP_KERNEL);
1930 if (adapter->msix_entries) {
8e86acd7 1931 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1932 adapter->msix_entries[i].entry = i;
1933
1934 err = pci_enable_msix(adapter->pdev,
1935 adapter->msix_entries,
8e86acd7 1936 adapter->num_vectors);
b1cdfead 1937 if (err == 0)
4662e82b
BA		 1938 return;
1939 }
1940 /* MSI-X failed, so fall through and try MSI */
ef456f85 1941 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1942 e1000e_reset_interrupt_capability(adapter);
1943 }
1944 adapter->int_mode = E1000E_INT_MODE_MSI;
1945 /* Fall through */
1946 case E1000E_INT_MODE_MSI:
1947 if (!pci_enable_msi(adapter->pdev)) {
1948 adapter->flags |= FLAG_MSI_ENABLED;
1949 } else {
1950 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1951 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1952 }
1953 /* Fall through */
1954 case E1000E_INT_MODE_LEGACY:
1955 /* Don't do anything; this is the system default */
1956 break;
1957 }
8e86acd7
JK		 1958
1959 /* store the number of vectors being used */
1960 adapter->num_vectors = 1;
4662e82b
BA		 1961}
1962
1963/**
1964 * e1000_request_msix - Initialize MSI-X interrupts
1965 *
1966 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1967 * kernel.
1968 **/
1969static int e1000_request_msix(struct e1000_adapter *adapter)
1970{
1971 struct net_device *netdev = adapter->netdev;
1972 int err = 0, vector = 0;
1973
1974 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1975 snprintf(adapter->rx_ring->name,
1976 sizeof(adapter->rx_ring->name) - 1,
1977 "%s-rx-0", netdev->name);
4662e82b
BA		 1978 else
1979 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1980 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1981 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1982 netdev);
1983 if (err)
5015e53a 1984 return err;
c5083cf6
BA		 1985 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
1986 E1000_EITR_82574(vector);
4662e82b
BA		 1987 adapter->rx_ring->itr_val = adapter->itr;
1988 vector++;
1989
1990 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1991 snprintf(adapter->tx_ring->name,
1992 sizeof(adapter->tx_ring->name) - 1,
1993 "%s-tx-0", netdev->name);
4662e82b
BA		 1994 else
1995 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1996 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1997 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 1998 netdev);
1999 if (err)
5015e53a 2000 return err;
c5083cf6
BA		 2001 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2002 E1000_EITR_82574(vector);
4662e82b
BA		 2003 adapter->tx_ring->itr_val = adapter->itr;
2004 vector++;
2005
2006 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2007 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2008 if (err)
5015e53a 2009 return err;
4662e82b
BA		 2010
2011 e1000_configure_msix(adapter);
5015e53a 2012
4662e82b 2013 return 0;
4662e82b
BA		 2014}
2015
f8d59f78
BA		 2016/**
2017 * e1000_request_irq - initialize interrupts
2018 *
2019 * Attempts to configure interrupts using the best available
2020 * capabilities of the hardware and kernel.
2021 **/
bc7f75fa
AK		 2022static int e1000_request_irq(struct e1000_adapter *adapter)
2023{
2024 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2025 int err;
2026
4662e82b
BA		 2027 if (adapter->msix_entries) {
2028 err = e1000_request_msix(adapter);
2029 if (!err)
2030 return err;
2031 /* fall back to MSI */
2032 e1000e_reset_interrupt_capability(adapter);
2033 adapter->int_mode = E1000E_INT_MODE_MSI;
2034 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2035 }
4662e82b 2036 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2037 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2038 netdev->name, netdev);
2039 if (!err)
2040 return err;
bc7f75fa 2041
4662e82b
BA		 2042 /* fall back to legacy interrupt */
2043 e1000e_reset_interrupt_capability(adapter);
2044 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2045 }
2046
a0607fd3 2047 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2048 netdev->name, netdev);
2049 if (err)
2050 e_err("Unable to allocate interrupt, Error: %d\n", err);
2051
bc7f75fa
AK		 2052 return err;
2053}
2054
2055static void e1000_free_irq(struct e1000_adapter *adapter)
2056{
2057 struct net_device *netdev = adapter->netdev;
2058
4662e82b
BA		 2059 if (adapter->msix_entries) {
2060 int vector = 0;
2061
2062 free_irq(adapter->msix_entries[vector].vector, netdev);
2063 vector++;
2064
2065 free_irq(adapter->msix_entries[vector].vector, netdev);
2066 vector++;
2067
2068 /* Other Causes interrupt vector */
2069 free_irq(adapter->msix_entries[vector].vector, netdev);
2070 return;
bc7f75fa 2071 }
4662e82b
BA		 2072
2073 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2074}
2075
2076/**
2077 * e1000_irq_disable - Mask off interrupt generation on the NIC
2078 **/
2079static void e1000_irq_disable(struct e1000_adapter *adapter)
2080{
2081 struct e1000_hw *hw = &adapter->hw;
2082
bc7f75fa 2083 ew32(IMC, ~0);
4662e82b
BA		 2084 if (adapter->msix_entries)
2085 ew32(EIAC_82574, 0);
bc7f75fa 2086 e1e_flush();
8e86acd7
JK		 2087
2088 if (adapter->msix_entries) {
2089 int i;
2090 for (i = 0; i < adapter->num_vectors; i++)
2091 synchronize_irq(adapter->msix_entries[i].vector);
2092 } else {
2093 synchronize_irq(adapter->pdev->irq);
2094 }
bc7f75fa
AK		 2095}
2096
2097/**
2098 * e1000_irq_enable - Enable default interrupt generation settings
2099 **/
2100static void e1000_irq_enable(struct e1000_adapter *adapter)
2101{
2102 struct e1000_hw *hw = &adapter->hw;
2103
4662e82b
BA		 2104 if (adapter->msix_entries) {
2105 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2106 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2107 } else {
2108 ew32(IMS, IMS_ENABLE_MASK);
2109 }
74ef9c39 2110 e1e_flush();
bc7f75fa
AK		 2111}
2112
2113/**
31dbe5b4 2114 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2115 * @adapter: address of board private structure
2116 *
31dbe5b4 2117 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2118 * For ASF and Pass Through versions of f/w this means that
2119 * the driver is loaded. For AMT version (only with 82573)
2120 * of the f/w this means that the network i/f is open.
2121 **/
31dbe5b4 2122void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2123{
2124 struct e1000_hw *hw = &adapter->hw;
2125 u32 ctrl_ext;
2126 u32 swsm;
2127
2128 /* Let firmware know the driver has taken over */
2129 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2130 swsm = er32(SWSM);
2131 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2132 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2133 ctrl_ext = er32(CTRL_EXT);
ad68076e 2134 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2135 }
2136}
2137
2138/**
31dbe5b4 2139 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2140 * @adapter: address of board private structure
2141 *
31dbe5b4 2142 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2143 * For ASF and Pass Through versions of f/w this means that the
2144 * driver is no longer loaded. For AMT version (only with 82573) i
2145 * of the f/w this means that the network i/f is closed.
2146 *
2147 **/
31dbe5b4 2148void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2149{
2150 struct e1000_hw *hw = &adapter->hw;
2151 u32 ctrl_ext;
2152 u32 swsm;
2153
2154 /* Let firmware taken over control of h/w */
2155 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2156 swsm = er32(SWSM);
2157 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2158 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2159 ctrl_ext = er32(CTRL_EXT);
ad68076e 2160 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2161 }
2162}
2163
bc7f75fa 2164/**
49ce9c2c 2165 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2166 **/
2167static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2168 struct e1000_ring *ring)
2169{
2170 struct pci_dev *pdev = adapter->pdev;
2171
2172 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2173 GFP_KERNEL);
2174 if (!ring->desc)
2175 return -ENOMEM;
2176
2177 return 0;
2178}
2179
2180/**
2181 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2182 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2183 *
2184 * Return 0 on success, negative on failure
2185 **/
55aa6985 2186int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2187{
55aa6985 2188 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2189 int err = -ENOMEM, size;
2190
2191 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2192 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2193 if (!tx_ring->buffer_info)
2194 goto err;
bc7f75fa
AK		 2195
2196 /* round up to nearest 4K */
2197 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2198 tx_ring->size = ALIGN(tx_ring->size, 4096);
2199
2200 err = e1000_alloc_ring_dma(adapter, tx_ring);
2201 if (err)
2202 goto err;
2203
2204 tx_ring->next_to_use = 0;
2205 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2206
2207 return 0;
2208err:
2209 vfree(tx_ring->buffer_info);
44defeb3 2210 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2211 return err;
2212}
2213
2214/**
2215 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2216 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2217 *
2218 * Returns 0 on success, negative on failure
2219 **/
55aa6985 2220int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2221{
55aa6985 2222 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2223 struct e1000_buffer *buffer_info;
2224 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2225
2226 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2227 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2228 if (!rx_ring->buffer_info)
2229 goto err;
bc7f75fa 2230
47f44e40
AK		 2231 for (i = 0; i < rx_ring->count; i++) {
2232 buffer_info = &rx_ring->buffer_info[i];
2233 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2234 sizeof(struct e1000_ps_page),
2235 GFP_KERNEL);
2236 if (!buffer_info->ps_pages)
2237 goto err_pages;
2238 }
bc7f75fa
AK		 2239
2240 desc_len = sizeof(union e1000_rx_desc_packet_split);
2241
2242 /* Round up to nearest 4K */
2243 rx_ring->size = rx_ring->count * desc_len;
2244 rx_ring->size = ALIGN(rx_ring->size, 4096);
2245
2246 err = e1000_alloc_ring_dma(adapter, rx_ring);
2247 if (err)
47f44e40 2248 goto err_pages;
bc7f75fa
AK		 2249
2250 rx_ring->next_to_clean = 0;
2251 rx_ring->next_to_use = 0;
2252 rx_ring->rx_skb_top = NULL;
2253
2254 return 0;
47f44e40
AK		 2255
2256err_pages:
2257 for (i = 0; i < rx_ring->count; i++) {
2258 buffer_info = &rx_ring->buffer_info[i];
2259 kfree(buffer_info->ps_pages);
2260 }
bc7f75fa
AK		 2261err:
2262 vfree(rx_ring->buffer_info);
e9262447 2263 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2264 return err;
2265}
2266
2267/**
2268 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2269 * @tx_ring: Tx descriptor ring
bc7f75fa 2270 **/
55aa6985 2271static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2272{
55aa6985 2273 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2274 struct e1000_buffer *buffer_info;
2275 unsigned long size;
2276 unsigned int i;
2277
2278 for (i = 0; i < tx_ring->count; i++) {
2279 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2280 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2281 }
2282
3f0cfa3b 2283 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2284 size = sizeof(struct e1000_buffer) * tx_ring->count;
2285 memset(tx_ring->buffer_info, 0, size);
2286
2287 memset(tx_ring->desc, 0, tx_ring->size);
2288
2289 tx_ring->next_to_use = 0;
2290 tx_ring->next_to_clean = 0;
2291
c5083cf6 2292 writel(0, tx_ring->head);
bdc125f7
BA		 2293 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2294 e1000e_update_tdt_wa(tx_ring, 0);
2295 else
2296 writel(0, tx_ring->tail);
bc7f75fa
AK		 2297}
2298
2299/**
2300 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2301 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2302 *
2303 * Free all transmit software resources
2304 **/
55aa6985 2305void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2306{
55aa6985 2307 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2308 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2309
55aa6985 2310 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2311
2312 vfree(tx_ring->buffer_info);
2313 tx_ring->buffer_info = NULL;
2314
2315 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2316 tx_ring->dma);
2317 tx_ring->desc = NULL;
2318}
2319
2320/**
2321 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2322 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2323 *
2324 * Free all receive software resources
2325 **/
55aa6985 2326void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2327{
55aa6985 2328 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2329 struct pci_dev *pdev = adapter->pdev;
47f44e40 2330 int i;
bc7f75fa 2331
55aa6985 2332 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2333
b1cdfead 2334 for (i = 0; i < rx_ring->count; i++)
47f44e40 2335 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2336
bc7f75fa
AK		 2337 vfree(rx_ring->buffer_info);
2338 rx_ring->buffer_info = NULL;
2339
bc7f75fa
AK		 2340 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2341 rx_ring->dma);
2342 rx_ring->desc = NULL;
2343}
2344
2345/**
2346 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2347 * @adapter: pointer to adapter
2348 * @itr_setting: current adapter->itr
2349 * @packets: the number of packets during this measurement interval
2350 * @bytes: the number of bytes during this measurement interval
2351 *
bc7f75fa
AK		 2352 * Stores a new ITR value based on packets and byte
2353 * counts during the last interrupt. The advantage of per interrupt
2354 * computation is faster updates and more accurate ITR for the current
2355 * traffic pattern. Constants in this function were computed
2356 * based on theoretical maximum wire speed and thresholds were set based
2357 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2358 * while increasing bulk throughput. This functionality is controlled
2359 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2360 **/
2361static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2362 u16 itr_setting, int packets,
2363 int bytes)
2364{
2365 unsigned int retval = itr_setting;
2366
2367 if (packets == 0)
5015e53a 2368 return itr_setting;
bc7f75fa
AK		 2369
2370 switch (itr_setting) {
2371 case lowest_latency:
2372 /* handle TSO and jumbo frames */
2373 if (bytes/packets > 8000)
2374 retval = bulk_latency;
b1cdfead 2375 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2376 retval = low_latency;
bc7f75fa
AK		 2377 break;
2378 case low_latency: /* 50 usec aka 20000 ints/s */
2379 if (bytes > 10000) {
2380 /* this if handles the TSO accounting */
b1cdfead 2381 if (bytes/packets > 8000)
bc7f75fa 2382 retval = bulk_latency;
b1cdfead 2383 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2384 retval = bulk_latency;
b1cdfead 2385 else if ((packets > 35))
bc7f75fa 2386 retval = lowest_latency;
bc7f75fa
AK		 2387 } else if (bytes/packets > 2000) {
2388 retval = bulk_latency;
2389 } else if (packets <= 2 && bytes < 512) {
2390 retval = lowest_latency;
2391 }
2392 break;
2393 case bulk_latency: /* 250 usec aka 4000 ints/s */
2394 if (bytes > 25000) {
b1cdfead 2395 if (packets > 35)
bc7f75fa 2396 retval = low_latency;
bc7f75fa
AK		 2397 } else if (bytes < 6000) {
2398 retval = low_latency;
2399 }
2400 break;
2401 }
2402
bc7f75fa
AK		 2403 return retval;
2404}
2405
2406static void e1000_set_itr(struct e1000_adapter *adapter)
2407{
2408 struct e1000_hw *hw = &adapter->hw;
2409 u16 current_itr;
2410 u32 new_itr = adapter->itr;
2411
2412 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2413 if (adapter->link_speed != SPEED_1000) {
2414 current_itr = 0;
2415 new_itr = 4000;
2416 goto set_itr_now;
2417 }
2418
828bac87
BA		 2419 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2420 new_itr = 0;
2421 goto set_itr_now;
2422 }
2423
bc7f75fa
AK		 2424 adapter->tx_itr = e1000_update_itr(adapter,
2425 adapter->tx_itr,
2426 adapter->total_tx_packets,
2427 adapter->total_tx_bytes);
2428 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2429 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2430 adapter->tx_itr = low_latency;
2431
2432 adapter->rx_itr = e1000_update_itr(adapter,
2433 adapter->rx_itr,
2434 adapter->total_rx_packets,
2435 adapter->total_rx_bytes);
2436 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2437 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2438 adapter->rx_itr = low_latency;
2439
2440 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2441
2442 switch (current_itr) {
2443 /* counts and packets in update_itr are dependent on these numbers */
2444 case lowest_latency:
2445 new_itr = 70000;
2446 break;
2447 case low_latency:
2448 new_itr = 20000; /* aka hwitr = ~200 */
2449 break;
2450 case bulk_latency:
2451 new_itr = 4000;
2452 break;
2453 default:
2454 break;
2455 }
2456
2457set_itr_now:
2458 if (new_itr != adapter->itr) {
e921eb1a 2459 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2460 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2461 * increasing
2462 */
bc7f75fa
AK		 2463 new_itr = new_itr > adapter->itr ?
2464 min(adapter->itr + (new_itr >> 2), new_itr) :
2465 new_itr;
2466 adapter->itr = new_itr;
4662e82b
BA		 2467 adapter->rx_ring->itr_val = new_itr;
2468 if (adapter->msix_entries)
2469 adapter->rx_ring->set_itr = 1;
2470 else
828bac87
BA		 2471 if (new_itr)
2472 ew32(ITR, 1000000000 / (new_itr * 256));
2473 else
2474 ew32(ITR, 0);
bc7f75fa
AK		 2475 }
2476}
2477
22a4cca2
MV		 2478/**
2479 * e1000e_write_itr - write the ITR value to the appropriate registers
2480 * @adapter: address of board private structure
2481 * @itr: new ITR value to program
2482 *
2483 * e1000e_write_itr determines if the adapter is in MSI-X mode
2484 * and, if so, writes the EITR registers with the ITR value.
2485 * Otherwise, it writes the ITR value into the ITR register.
2486 **/
2487void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2488{
2489 struct e1000_hw *hw = &adapter->hw;
2490 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2491
2492 if (adapter->msix_entries) {
2493 int vector;
2494
2495 for (vector = 0; vector < adapter->num_vectors; vector++)
2496 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2497 } else {
2498 ew32(ITR, new_itr);
2499 }
2500}
2501
4662e82b
BA		 2502/**
2503 * e1000_alloc_queues - Allocate memory for all rings
2504 * @adapter: board private structure to initialize
2505 **/
9f9a12f8 2506static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2507{
55aa6985
BA		 2508 int size = sizeof(struct e1000_ring);
2509
2510 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2511 if (!adapter->tx_ring)
2512 goto err;
55aa6985
BA		 2513 adapter->tx_ring->count = adapter->tx_ring_count;
2514 adapter->tx_ring->adapter = adapter;
4662e82b 2515
55aa6985 2516 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2517 if (!adapter->rx_ring)
2518 goto err;
55aa6985
BA		 2519 adapter->rx_ring->count = adapter->rx_ring_count;
2520 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2521
2522 return 0;
2523err:
2524 e_err("Unable to allocate memory for queues\n");
2525 kfree(adapter->rx_ring);
2526 kfree(adapter->tx_ring);
2527 return -ENOMEM;
2528}
2529
bc7f75fa 2530/**
c58c8a78 2531 * e1000e_poll - NAPI Rx polling callback
ad68076e 2532 * @napi: struct associated with this polling callback
c58c8a78 2533 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2534 **/
c58c8a78 2535static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2536{
c58c8a78
BA		 2537 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2538 napi);
4662e82b 2539 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2540 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2541 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2542
4cf1653a 2543 adapter = netdev_priv(poll_dev);
bc7f75fa 2544
c58c8a78
BA		 2545 if (!adapter->msix_entries ||
2546 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2547 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2548
c58c8a78 2549 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2550
12d04a3c 2551 if (!tx_cleaned)
c58c8a78 2552 work_done = weight;
bc7f75fa 2553
c58c8a78
BA		 2554 /* If weight not fully consumed, exit the polling mode */
2555 if (work_done < weight) {
bc7f75fa
AK		 2556 if (adapter->itr_setting & 3)
2557 e1000_set_itr(adapter);
288379f0 2558 napi_complete(napi);
a3c69fef
JB		 2559 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2560 if (adapter->msix_entries)
2561 ew32(IMS, adapter->rx_ring->ims_val);
2562 else
2563 e1000_irq_enable(adapter);
2564 }
bc7f75fa
AK		 2565 }
2566
2567 return work_done;
2568}
2569
8e586137 2570static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2571{
2572 struct e1000_adapter *adapter = netdev_priv(netdev);
2573 struct e1000_hw *hw = &adapter->hw;
2574 u32 vfta, index;
2575
2576 /* don't update vlan cookie if already programmed */
2577 if ((adapter->hw.mng_cookie.status &
2578 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2579 (vid == adapter->mng_vlan_id))
8e586137 2580 return 0;
caaddaf8 2581
bc7f75fa 2582 /* add VID to filter table */
caaddaf8
BA		 2583 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2584 index = (vid >> 5) & 0x7F;
2585 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2586 vfta |= (1 << (vid & 0x1F));
2587 hw->mac.ops.write_vfta(hw, index, vfta);
2588 }
86d70e53
JK		 2589
2590 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2591
2592 return 0;
bc7f75fa
AK		 2593}
2594
8e586137 2595static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2596{
2597 struct e1000_adapter *adapter = netdev_priv(netdev);
2598 struct e1000_hw *hw = &adapter->hw;
2599 u32 vfta, index;
2600
bc7f75fa
AK		 2601 if ((adapter->hw.mng_cookie.status &
2602 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2603 (vid == adapter->mng_vlan_id)) {
2604 /* release control to f/w */
31dbe5b4 2605 e1000e_release_hw_control(adapter);
8e586137 2606 return 0;
bc7f75fa
AK		 2607 }
2608
2609 /* remove VID from filter table */
caaddaf8
BA		 2610 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2611 index = (vid >> 5) & 0x7F;
2612 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2613 vfta &= ~(1 << (vid & 0x1F));
2614 hw->mac.ops.write_vfta(hw, index, vfta);
2615 }
86d70e53
JK		 2616
2617 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2618
2619 return 0;
bc7f75fa
AK		 2620}
2621
86d70e53
JK		 2622/**
2623 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2624 * @adapter: board private structure to initialize
2625 **/
2626static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2627{
2628 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2629 struct e1000_hw *hw = &adapter->hw;
2630 u32 rctl;
bc7f75fa 2631
86d70e53
JK		 2632 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2633 /* disable VLAN receive filtering */
2634 rctl = er32(RCTL);
2635 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2636 ew32(RCTL, rctl);
2637
2638 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2639 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2640 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2641 }
bc7f75fa
AK		 2642 }
2643}
2644
86d70e53
JK		 2645/**
2646 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2647 * @adapter: board private structure to initialize
2648 **/
2649static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2650{
2651 struct e1000_hw *hw = &adapter->hw;
2652 u32 rctl;
2653
2654 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2655 /* enable VLAN receive filtering */
2656 rctl = er32(RCTL);
2657 rctl |= E1000_RCTL_VFE;
2658 rctl &= ~E1000_RCTL_CFIEN;
2659 ew32(RCTL, rctl);
2660 }
2661}
bc7f75fa 2662
86d70e53
JK		 2663/**
2664 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2665 * @adapter: board private structure to initialize
2666 **/
2667static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2668{
bc7f75fa 2669 struct e1000_hw *hw = &adapter->hw;
86d70e53 2670 u32 ctrl;
bc7f75fa 2671
86d70e53
JK		 2672 /* disable VLAN tag insert/strip */
2673 ctrl = er32(CTRL);
2674 ctrl &= ~E1000_CTRL_VME;
2675 ew32(CTRL, ctrl);
2676}
bc7f75fa 2677
86d70e53
JK		 2678/**
2679 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2680 * @adapter: board private structure to initialize
2681 **/
2682static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2683{
2684 struct e1000_hw *hw = &adapter->hw;
2685 u32 ctrl;
bc7f75fa 2686
86d70e53
JK		 2687 /* enable VLAN tag insert/strip */
2688 ctrl = er32(CTRL);
2689 ctrl |= E1000_CTRL_VME;
2690 ew32(CTRL, ctrl);
2691}
bc7f75fa 2692
86d70e53
JK		 2693static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2694{
2695 struct net_device *netdev = adapter->netdev;
2696 u16 vid = adapter->hw.mng_cookie.vlan_id;
2697 u16 old_vid = adapter->mng_vlan_id;
2698
2699 if (adapter->hw.mng_cookie.status &
2700 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2701 e1000_vlan_rx_add_vid(netdev, vid);
2702 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2703 }
2704
86d70e53
JK		 2705 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2706 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2707}
2708
2709static void e1000_restore_vlan(struct e1000_adapter *adapter)
2710{
2711 u16 vid;
2712
86d70e53 2713 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2714
86d70e53 2715 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2716 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2717}
2718
cd791618 2719static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2720{
2721 struct e1000_hw *hw = &adapter->hw;
cd791618 2722 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2723
2724 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2725 return;
2726
2727 manc = er32(MANC);
2728
e921eb1a 2729 /* enable receiving management packets to the host. this will probably
bc7f75fa 2730 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2731 * the packets will be handled on SMBUS
2732 */
bc7f75fa
AK		 2733 manc |= E1000_MANC_EN_MNG2HOST;
2734 manc2h = er32(MANC2H);
cd791618
BA		 2735
2736 switch (hw->mac.type) {
2737 default:
2738 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2739 break;
2740 case e1000_82574:
2741 case e1000_82583:
e921eb1a 2742 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2743 * if so, enable it.
2744 */
2745 for (i = 0, j = 0; i < 8; i++) {
2746 mdef = er32(MDEF(i));
2747
2748 /* Ignore filters with anything other than IPMI ports */
3b21b508 2749 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2750 continue;
2751
2752 /* Enable this decision filter in MANC2H */
2753 if (mdef)
2754 manc2h |= (1 << i);
2755
2756 j |= mdef;
2757 }
2758
2759 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2760 break;
2761
2762 /* Create new decision filter in an empty filter */
2763 for (i = 0, j = 0; i < 8; i++)
2764 if (er32(MDEF(i)) == 0) {
2765 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2766 E1000_MDEF_PORT_664));
2767 manc2h |= (1 << 1);
2768 j++;
2769 break;
2770 }
2771
2772 if (!j)
2773 e_warn("Unable to create IPMI pass-through filter\n");
2774 break;
2775 }
2776
bc7f75fa
AK		 2777 ew32(MANC2H, manc2h);
2778 ew32(MANC, manc);
2779}
2780
2781/**
af667a29 2782 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2783 * @adapter: board private structure
2784 *
2785 * Configure the Tx unit of the MAC after a reset.
2786 **/
2787static void e1000_configure_tx(struct e1000_adapter *adapter)
2788{
2789 struct e1000_hw *hw = &adapter->hw;
2790 struct e1000_ring *tx_ring = adapter->tx_ring;
2791 u64 tdba;
c550b121 2792 u32 tdlen, tarc;
bc7f75fa
AK		 2793
2794 /* Setup the HW Tx Head and Tail descriptor pointers */
2795 tdba = tx_ring->dma;
2796 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2797 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2798 ew32(TDBAH(0), (tdba >> 32));
2799 ew32(TDLEN(0), tdlen);
2800 ew32(TDH(0), 0);
2801 ew32(TDT(0), 0);
2802 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2803 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2804
bc7f75fa
AK		 2805 /* Set the Tx Interrupt Delay register */
2806 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2807 /* Tx irq moderation */
bc7f75fa
AK		 2808 ew32(TADV, adapter->tx_abs_int_delay);
2809
3a3b7586
JB		 2810 if (adapter->flags2 & FLAG2_DMA_BURST) {
2811 u32 txdctl = er32(TXDCTL(0));
2812 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2813 E1000_TXDCTL_WTHRESH);
e921eb1a 2814 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2815 * hardware to use the bus more efficiently in bursts, depends
2816 * on the tx_int_delay to be enabled,
8edc0e62 2817 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2818 * hthresh = 1 ==> prefetch when one or more available
2819 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2820 * BEWARE: this seems to work but should be considered first if
af667a29 2821 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2822 */
2823 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2824 ew32(TXDCTL(0), txdctl);
3a3b7586 2825 }
56032be7
BA		 2826 /* erratum work around: set txdctl the same for both queues */
2827 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2828
bc7f75fa 2829 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2830 tarc = er32(TARC(0));
e921eb1a 2831 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2832 * gigabit link later
2833 */
bc7f75fa
AK		 2834#define SPEED_MODE_BIT (1 << 21)
2835 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2836 ew32(TARC(0), tarc);
bc7f75fa
AK		 2837 }
2838
2839 /* errata: program both queues to unweighted RR */
2840 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2841 tarc = er32(TARC(0));
bc7f75fa 2842 tarc |= 1;
e9ec2c0f
JK		 2843 ew32(TARC(0), tarc);
2844 tarc = er32(TARC(1));
bc7f75fa 2845 tarc |= 1;
e9ec2c0f 2846 ew32(TARC(1), tarc);
bc7f75fa
AK		 2847 }
2848
bc7f75fa
AK		 2849 /* Setup Transmit Descriptor Settings for eop descriptor */
2850 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2851
2852 /* only set IDE if we are delaying interrupts using the timers */
2853 if (adapter->tx_int_delay)
2854 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2855
2856 /* enable Report Status bit */
2857 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2858
57cde763 2859 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2860}
2861
2862/**
2863 * e1000_setup_rctl - configure the receive control registers
2864 * @adapter: Board private structure
2865 **/
2866#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2867 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2868static void e1000_setup_rctl(struct e1000_adapter *adapter)
2869{
2870 struct e1000_hw *hw = &adapter->hw;
2871 u32 rctl, rfctl;
bc7f75fa
AK		 2872 u32 pages = 0;
2873
2fbe4526
BA		 2874 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2875 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2876 s32 ret_val;
2877
2878 if (adapter->netdev->mtu > ETH_DATA_LEN)
2879 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2880 else
2881 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2882
2883 if (ret_val)
2884 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2885 }
2886
bc7f75fa
AK		 2887 /* Program MC offset vector base */
2888 rctl = er32(RCTL);
2889 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2890 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2891 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2892 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2893
2894 /* Do not Store bad packets */
2895 rctl &= ~E1000_RCTL_SBP;
2896
2897 /* Enable Long Packet receive */
2898 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2899 rctl &= ~E1000_RCTL_LPE;
2900 else
2901 rctl |= E1000_RCTL_LPE;
2902
eb7c3adb
JK		 2903 /* Some systems expect that the CRC is included in SMBUS traffic. The
2904 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2905 * host memory when this is enabled
2906 */
2907 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2908 rctl |= E1000_RCTL_SECRC;
5918bd88 2909
a4f58f54
BA		 2910 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2911 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2912 u16 phy_data;
2913
2914 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2915 phy_data &= 0xfff8;
2916 phy_data |= (1 << 2);
2917 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2918
2919 e1e_rphy(hw, 22, &phy_data);
2920 phy_data &= 0x0fff;
2921 phy_data |= (1 << 14);
2922 e1e_wphy(hw, 0x10, 0x2823);
2923 e1e_wphy(hw, 0x11, 0x0003);
2924 e1e_wphy(hw, 22, phy_data);
2925 }
2926
bc7f75fa
AK		 2927 /* Setup buffer sizes */
2928 rctl &= ~E1000_RCTL_SZ_4096;
2929 rctl |= E1000_RCTL_BSEX;
2930 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2931 case 2048:
2932 default:
2933 rctl |= E1000_RCTL_SZ_2048;
2934 rctl &= ~E1000_RCTL_BSEX;
2935 break;
2936 case 4096:
2937 rctl |= E1000_RCTL_SZ_4096;
2938 break;
2939 case 8192:
2940 rctl |= E1000_RCTL_SZ_8192;
2941 break;
2942 case 16384:
2943 rctl |= E1000_RCTL_SZ_16384;
2944 break;
2945 }
2946
5f450212
BA		 2947 /* Enable Extended Status in all Receive Descriptors */
2948 rfctl = er32(RFCTL);
2949 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 2950 ew32(RFCTL, rfctl);
5f450212 2951
e921eb1a 2952 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 2953 * header is placed in skb->data and the packet data is
2954 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2955 * In the case of a non-split, skb->data is linearly filled,
2956 * followed by the page buffers. Therefore, skb->data is
2957 * sized to hold the largest protocol header.
2958 *
2959 * allocations using alloc_page take too long for regular MTU
2960 * so only enable packet split for jumbo frames
2961 *
2962 * Using pages when the page size is greater than 16k wastes
2963 * a lot of memory, since we allocate 3 pages at all times
2964 * per packet.
2965 */
bc7f75fa 2966 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2967 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2968 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2969 else
2970 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2971
2972 if (adapter->rx_ps_pages) {
90da0669
BA		 2973 u32 psrctl = 0;
2974
140a7480
AK		 2975 /* Enable Packet split descriptors */
2976 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2977
2978 psrctl |= adapter->rx_ps_bsize0 >>
2979 E1000_PSRCTL_BSIZE0_SHIFT;
2980
2981 switch (adapter->rx_ps_pages) {
2982 case 3:
2983 psrctl |= PAGE_SIZE <<
2984 E1000_PSRCTL_BSIZE3_SHIFT;
2985 case 2:
2986 psrctl |= PAGE_SIZE <<
2987 E1000_PSRCTL_BSIZE2_SHIFT;
2988 case 1:
2989 psrctl |= PAGE_SIZE >>
2990 E1000_PSRCTL_BSIZE1_SHIFT;
2991 break;
2992 }
2993
2994 ew32(PSRCTL, psrctl);
2995 }
2996
cf955e6c
BG		 2997 /* This is useful for sniffing bad packets. */
2998 if (adapter->netdev->features & NETIF_F_RXALL) {
2999 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3000 * in e1000e_set_rx_mode
3001 */
cf955e6c
BG		 3002 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3003 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3004 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3005
3006 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3007 E1000_RCTL_DPF | /* Allow filtered pause */
3008 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3009 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3010 * and that breaks VLANs.
3011 */
3012 }
3013
bc7f75fa 3014 ew32(RCTL, rctl);
318a94d6
JK		 3015 /* just started the receive unit, no need to restart */
3016 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3017}
3018
3019/**
3020 * e1000_configure_rx - Configure Receive Unit after Reset
3021 * @adapter: board private structure
3022 *
3023 * Configure the Rx unit of the MAC after a reset.
3024 **/
3025static void e1000_configure_rx(struct e1000_adapter *adapter)
3026{
3027 struct e1000_hw *hw = &adapter->hw;
3028 struct e1000_ring *rx_ring = adapter->rx_ring;
3029 u64 rdba;
3030 u32 rdlen, rctl, rxcsum, ctrl_ext;
3031
3032 if (adapter->rx_ps_pages) {
3033 /* this is a 32 byte descriptor */
3034 rdlen = rx_ring->count *
af667a29 3035 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3036 adapter->clean_rx = e1000_clean_rx_irq_ps;
3037 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3038 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3039 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3040 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3041 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3042 } else {
5f450212 3043 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3044 adapter->clean_rx = e1000_clean_rx_irq;
3045 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3046 }
3047
3048 /* disable receives while setting up the descriptors */
3049 rctl = er32(RCTL);
7f99ae63
BA		 3050 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3051 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3052 e1e_flush();
1bba4386 3053 usleep_range(10000, 20000);
bc7f75fa 3054
3a3b7586 3055 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3056 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3057 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3058 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3059 * granularity = 01
3060 * wthresh = 04,
3061 * hthresh = 04,
3062 * pthresh = 0x20
3063 */
3064 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3065 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3066
e921eb1a 3067 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3068 * the value was not set by the user via module options
3069 */
3070 if (adapter->rx_int_delay == DEFAULT_RDTR)
3071 adapter->rx_int_delay = BURST_RDTR;
3072 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3073 adapter->rx_abs_int_delay = BURST_RADV;
3074 }
3075
bc7f75fa
AK		 3076 /* set the Receive Delay Timer Register */
3077 ew32(RDTR, adapter->rx_int_delay);
3078
3079 /* irq moderation */
3080 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3081 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3082 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3083
3084 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3085 /* Auto-Mask interrupts upon ICR access */
3086 ctrl_ext |= E1000_CTRL_EXT_IAME;
3087 ew32(IAM, 0xffffffff);
3088 ew32(CTRL_EXT, ctrl_ext);
3089 e1e_flush();
3090
e921eb1a 3091 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3092 * the Base and Length of the Rx Descriptor Ring
3093 */
bc7f75fa 3094 rdba = rx_ring->dma;
1e36052e
BA		 3095 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3096 ew32(RDBAH(0), (rdba >> 32));
3097 ew32(RDLEN(0), rdlen);
3098 ew32(RDH(0), 0);
3099 ew32(RDT(0), 0);
3100 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3101 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3102
3103 /* Enable Receive Checksum Offload for TCP and UDP */
3104 rxcsum = er32(RXCSUM);
2e1706f2 3105 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3106 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3107 else
bc7f75fa 3108 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3109 ew32(RXCSUM, rxcsum);
3110
79d4e908 3111 if (adapter->hw.mac.type == e1000_pch2lan) {
e921eb1a 3112 /* With jumbo frames, excessive C-state transition
79d4e908
BA		 3113 * latencies result in dropped transactions.
3114 */
53ec5498
BA		 3115 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3116 u32 rxdctl = er32(RXDCTL(0));
3117 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3118 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3119 } else {
af667a29
BA		 3120 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3121 PM_QOS_DEFAULT_VALUE);
53ec5498 3122 }
97ac8cae 3123 }
bc7f75fa
AK		 3124
3125 /* Enable Receives */
3126 ew32(RCTL, rctl);
3127}
3128
3129/**
ef9b965a
JB		 3130 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3131 * @netdev: network interface device structure
bc7f75fa 3132 *
ef9b965a
JB		 3133 * Writes multicast address list to the MTA hash table.
3134 * Returns: -ENOMEM on failure
3135 * 0 on no addresses written
3136 * X on writing X addresses to MTA
3137 */
3138static int e1000e_write_mc_addr_list(struct net_device *netdev)
3139{
3140 struct e1000_adapter *adapter = netdev_priv(netdev);
3141 struct e1000_hw *hw = &adapter->hw;
3142 struct netdev_hw_addr *ha;
3143 u8 *mta_list;
3144 int i;
3145
3146 if (netdev_mc_empty(netdev)) {
3147 /* nothing to program, so clear mc list */
3148 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3149 return 0;
3150 }
3151
3152 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3153 if (!mta_list)
3154 return -ENOMEM;
3155
3156 /* update_mc_addr_list expects a packed array of only addresses. */
3157 i = 0;
3158 netdev_for_each_mc_addr(ha, netdev)
3159 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3160
3161 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3162 kfree(mta_list);
3163
3164 return netdev_mc_count(netdev);
3165}
3166
3167/**
3168 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3169 * @netdev: network interface device structure
bc7f75fa 3170 *
ef9b965a
JB		 3171 * Writes unicast address list to the RAR table.
3172 * Returns: -ENOMEM on failure/insufficient address space
3173 * 0 on no addresses written
3174 * X on writing X addresses to the RAR table
bc7f75fa 3175 **/
ef9b965a 3176static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3177{
ef9b965a
JB		 3178 struct e1000_adapter *adapter = netdev_priv(netdev);
3179 struct e1000_hw *hw = &adapter->hw;
3180 unsigned int rar_entries = hw->mac.rar_entry_count;
3181 int count = 0;
3182
3183 /* save a rar entry for our hardware address */
3184 rar_entries--;
3185
3186 /* save a rar entry for the LAA workaround */
3187 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3188 rar_entries--;
3189
3190 /* return ENOMEM indicating insufficient memory for addresses */
3191 if (netdev_uc_count(netdev) > rar_entries)
3192 return -ENOMEM;
3193
3194 if (!netdev_uc_empty(netdev) && rar_entries) {
3195 struct netdev_hw_addr *ha;
3196
e921eb1a 3197 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3198 * combining
3199 */
3200 netdev_for_each_uc_addr(ha, netdev) {
3201 if (!rar_entries)
3202 break;
69e1e019 3203 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3204 count++;
3205 }
3206 }
3207
3208 /* zero out the remaining RAR entries not used above */
3209 for (; rar_entries > 0; rar_entries--) {
3210 ew32(RAH(rar_entries), 0);
3211 ew32(RAL(rar_entries), 0);
3212 }
3213 e1e_flush();
3214
3215 return count;
bc7f75fa
AK		 3216}
3217
3218/**
ef9b965a 3219 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3220 * @netdev: network interface device structure
3221 *
ef9b965a
JB		 3222 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3223 * address list or the network interface flags are updated. This routine is
3224 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3225 * promiscuous mode, and all-multi behavior.
3226 **/
ef9b965a 3227static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3228{
3229 struct e1000_adapter *adapter = netdev_priv(netdev);
3230 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3231 u32 rctl;
bc7f75fa
AK		 3232
3233 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3234 rctl = er32(RCTL);
3235
ef9b965a
JB		 3236 /* clear the affected bits */
3237 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3238
bc7f75fa
AK		 3239 if (netdev->flags & IFF_PROMISC) {
3240 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3241 /* Do not hardware filter VLANs in promisc mode */
3242 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3243 } else {
ef9b965a 3244 int count;
3d3a1676 3245
746b9f02
PM		 3246 if (netdev->flags & IFF_ALLMULTI) {
3247 rctl |= E1000_RCTL_MPE;
746b9f02 3248 } else {
e921eb1a 3249 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3250 * then we should just turn on promiscuous mode so
3251 * that we can at least receive multicast traffic
3252 */
3253 count = e1000e_write_mc_addr_list(netdev);
3254 if (count < 0)
3255 rctl |= E1000_RCTL_MPE;
746b9f02 3256 }
86d70e53 3257 e1000e_vlan_filter_enable(adapter);
e921eb1a 3258 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3259 * sufficient space to store all the addresses then enable
3260 * unicast promiscuous mode
bc7f75fa 3261 */
ef9b965a
JB		 3262 count = e1000e_write_uc_addr_list(netdev);
3263 if (count < 0)
3264 rctl |= E1000_RCTL_UPE;
bc7f75fa 3265 }
86d70e53 3266
ef9b965a
JB		 3267 ew32(RCTL, rctl);
3268
86d70e53
JK		 3269 if (netdev->features & NETIF_F_HW_VLAN_RX)
3270 e1000e_vlan_strip_enable(adapter);
3271 else
3272 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3273}
3274
70495a50
BA		 3275static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3276{
3277 struct e1000_hw *hw = &adapter->hw;
3278 u32 mrqc, rxcsum;
3279 int i;
3280 static const u32 rsskey[10] = {
3281 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3282 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3283 };
3284
3285 /* Fill out hash function seed */
3286 for (i = 0; i < 10; i++)
3287 ew32(RSSRK(i), rsskey[i]);
3288
3289 /* Direct all traffic to queue 0 */
3290 for (i = 0; i < 32; i++)
3291 ew32(RETA(i), 0);
3292
e921eb1a 3293 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3294 * descriptor on writeback.
3295 */
3296 rxcsum = er32(RXCSUM);
3297 rxcsum |= E1000_RXCSUM_PCSD;
3298
3299 ew32(RXCSUM, rxcsum);
3300
3301 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3302 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3303 E1000_MRQC_RSS_FIELD_IPV6 |
3304 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3305 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3306
3307 ew32(MRQC, mrqc);
3308}
3309
bc7f75fa 3310/**
ad68076e 3311 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3312 * @adapter: private board structure
3313 **/
3314static void e1000_configure(struct e1000_adapter *adapter)
3315{
55aa6985
BA		 3316 struct e1000_ring *rx_ring = adapter->rx_ring;
3317
ef9b965a 3318 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3319
3320 e1000_restore_vlan(adapter);
cd791618 3321 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3322
3323 e1000_configure_tx(adapter);
70495a50
BA		 3324
3325 if (adapter->netdev->features & NETIF_F_RXHASH)
3326 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3327 e1000_setup_rctl(adapter);
3328 e1000_configure_rx(adapter);
55aa6985 3329 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3330}
3331
3332/**
3333 * e1000e_power_up_phy - restore link in case the phy was powered down
3334 * @adapter: address of board private structure
3335 *
3336 * The phy may be powered down to save power and turn off link when the
3337 * driver is unloaded and wake on lan is not enabled (among others)
3338 * *** this routine MUST be followed by a call to e1000e_reset ***
3339 **/
3340void e1000e_power_up_phy(struct e1000_adapter *adapter)
3341{
17f208de
BA		 3342 if (adapter->hw.phy.ops.power_up)
3343 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3344
3345 adapter->hw.mac.ops.setup_link(&adapter->hw);
3346}
3347
3348/**
3349 * e1000_power_down_phy - Power down the PHY
3350 *
17f208de
BA		 3351 * Power down the PHY so no link is implied when interface is down.
3352 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3353 */
3354static void e1000_power_down_phy(struct e1000_adapter *adapter)
3355{
bc7f75fa 3356 /* WoL is enabled */
23b66e2b 3357 if (adapter->wol)
bc7f75fa
AK		 3358 return;
3359
17f208de
BA		 3360 if (adapter->hw.phy.ops.power_down)
3361 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3362}
3363
3364/**
3365 * e1000e_reset - bring the hardware into a known good state
3366 *
3367 * This function boots the hardware and enables some settings that
3368 * require a configuration cycle of the hardware - those cannot be
3369 * set/changed during runtime. After reset the device needs to be
ad68076e 3370 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3371 */
3372void e1000e_reset(struct e1000_adapter *adapter)
3373{
3374 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3375 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3376 struct e1000_hw *hw = &adapter->hw;
3377 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3378 u32 pba = adapter->pba;
bc7f75fa
AK		 3379 u16 hwm;
3380
ad68076e 3381 /* reset Packet Buffer Allocation to default */
318a94d6 3382 ew32(PBA, pba);
df762464 3383
318a94d6 3384 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3385 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3386 * large enough to accommodate two full transmit packets,
3387 * rounded up to the next 1KB and expressed in KB. Likewise,
3388 * the Rx FIFO should be large enough to accommodate at least
3389 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3390 * expressed in KB.
3391 */
df762464 3392 pba = er32(PBA);
bc7f75fa 3393 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3394 tx_space = pba >> 16;
bc7f75fa 3395 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3396 pba &= 0xffff;
e921eb1a 3397 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3398 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3399 */
3400 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3401 sizeof(struct e1000_tx_desc) -
3402 ETH_FCS_LEN) * 2;
3403 min_tx_space = ALIGN(min_tx_space, 1024);
3404 min_tx_space >>= 10;
3405 /* software strips receive CRC, so leave room for it */
318a94d6 3406 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3407 min_rx_space = ALIGN(min_rx_space, 1024);
3408 min_rx_space >>= 10;
3409
e921eb1a 3410 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3411 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3412 * allocation, take space away from current Rx allocation
3413 */
df762464
AK		 3414 if ((tx_space < min_tx_space) &&
3415 ((min_tx_space - tx_space) < pba)) {
3416 pba -= min_tx_space - tx_space;
bc7f75fa 3417
e921eb1a 3418 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3419 * adjustment
ad68076e 3420 */
79d4e908 3421 if (pba < min_rx_space)
df762464 3422 pba = min_rx_space;
bc7f75fa 3423 }
df762464
AK		 3424
3425 ew32(PBA, pba);
bc7f75fa
AK		 3426 }
3427
e921eb1a 3428 /* flow control settings
ad68076e 3429 *
38eb394e 3430 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3431 * (or the size used for early receive) above it in the Rx FIFO.
3432 * Set it to the lower of:
3433 * - 90% of the Rx FIFO size, and
38eb394e 3434 * - the full Rx FIFO size minus one full frame
ad68076e 3435 */
d3738bb8
BA		 3436 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3437 fc->pause_time = 0xFFFF;
3438 else
3439 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3440 fc->send_xon = true;
d3738bb8
BA		 3441 fc->current_mode = fc->requested_mode;
3442
3443 switch (hw->mac.type) {
79d4e908
BA		 3444 case e1000_ich9lan:
3445 case e1000_ich10lan:
3446 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3447 pba = 14;
3448 ew32(PBA, pba);
3449 fc->high_water = 0x2800;
3450 fc->low_water = fc->high_water - 8;
3451 break;
3452 }
3453 /* fall-through */
d3738bb8 3454 default:
79d4e908
BA		 3455 hwm = min(((pba << 10) * 9 / 10),
3456 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3457
3458 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3459 fc->low_water = fc->high_water - 8;
3460 break;
3461 case e1000_pchlan:
e921eb1a 3462 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3463 * loads. If hangs persist, try disabling Tx flow control.
3464 */
3465 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3466 fc->high_water = 0x3500;
3467 fc->low_water = 0x1500;
3468 } else {
3469 fc->high_water = 0x5000;
3470 fc->low_water = 0x3000;
3471 }
a305595b 3472 fc->refresh_time = 0x1000;
d3738bb8
BA		 3473 break;
3474 case e1000_pch2lan:
2fbe4526 3475 case e1000_pch_lpt:
d3738bb8
BA		 3476 fc->high_water = 0x05C20;
3477 fc->low_water = 0x05048;
3478 fc->pause_time = 0x0650;
3479 fc->refresh_time = 0x0400;
828bac87
BA		 3480 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3481 pba = 14;
3482 ew32(PBA, pba);
3483 }
d3738bb8 3484 break;
38eb394e 3485 }
bc7f75fa 3486
e921eb1a 3487 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3488 * maximum size per Tx descriptor limited only to the transmit
3489 * allocation of the packet buffer minus 96 bytes with an upper
3490 * limit of 24KB due to receive synchronization limitations.
3491 */
3492 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3493 24 << 10);
3494
e921eb1a 3495 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3496 * fit in receive buffer.
828bac87
BA		 3497 */
3498 if (adapter->itr_setting & 0x3) {
79d4e908 3499 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3500 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3501 dev_info(&adapter->pdev->dev,
3502 "Interrupt Throttle Rate turned off\n");
3503 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3504 e1000e_write_itr(adapter, 0);
828bac87
BA		 3505 }
3506 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3507 dev_info(&adapter->pdev->dev,
3508 "Interrupt Throttle Rate turned on\n");
3509 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3510 adapter->itr = 20000;
22a4cca2 3511 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3512 }
3513 }
3514
bc7f75fa
AK		 3515 /* Allow time for pending master requests to run */
3516 mac->ops.reset_hw(hw);
97ac8cae 3517
e921eb1a 3518 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3519 * that the network interface is in control
3520 */
c43bc57e 3521 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3522 e1000e_get_hw_control(adapter);
97ac8cae 3523
bc7f75fa
AK		 3524 ew32(WUC, 0);
3525
3526 if (mac->ops.init_hw(hw))
44defeb3 3527 e_err("Hardware Error\n");
bc7f75fa
AK		 3528
3529 e1000_update_mng_vlan(adapter);
3530
3531 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3532 ew32(VET, ETH_P_8021Q);
3533
3534 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3535
3536 if (!netif_running(adapter->netdev) &&
3537 !test_bit(__E1000_TESTING, &adapter->state)) {
3538 e1000_power_down_phy(adapter);
3539 return;
3540 }
3541
bc7f75fa
AK		 3542 e1000_get_phy_info(hw);
3543
918d7197
BA		 3544 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3545 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3546 u16 phy_data = 0;
e921eb1a 3547 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3548 * the return value of this function because there is nothing
ad68076e
BA		 3549 * different we would do if it failed
3550 */
bc7f75fa
AK		 3551 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3552 phy_data &= ~IGP02E1000_PM_SPD;
3553 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3554 }
bc7f75fa
AK		 3555}
3556
3557int e1000e_up(struct e1000_adapter *adapter)
3558{
3559 struct e1000_hw *hw = &adapter->hw;
3560
3561 /* hardware has been reset, we need to reload some things */
3562 e1000_configure(adapter);
3563
3564 clear_bit(__E1000_DOWN, &adapter->state);
3565
4662e82b
BA		 3566 if (adapter->msix_entries)
3567 e1000_configure_msix(adapter);
bc7f75fa
AK		 3568 e1000_irq_enable(adapter);
3569
400484fa 3570 netif_start_queue(adapter->netdev);
4cb9be7a 3571
bc7f75fa 3572 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3573 if (adapter->msix_entries)
3574 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3575 else
3576 ew32(ICS, E1000_ICS_LSC);
3577
bc7f75fa
AK		 3578 return 0;
3579}
3580
713b3c9e
JB		 3581static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3582{
3583 struct e1000_hw *hw = &adapter->hw;
3584
3585 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3586 return;
3587
3588 /* flush pending descriptor writebacks to memory */
3589 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3590 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3591
3592 /* execute the writes immediately */
3593 e1e_flush();
bf03085f 3594
e921eb1a 3595 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3596 * write is successful
3597 */
3598 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3599 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3600
3601 /* execute the writes immediately */
3602 e1e_flush();
3603}
3604
67fd4fcb
JK		 3605static void e1000e_update_stats(struct e1000_adapter *adapter);
3606
bc7f75fa
AK		 3607void e1000e_down(struct e1000_adapter *adapter)
3608{
3609 struct net_device *netdev = adapter->netdev;
3610 struct e1000_hw *hw = &adapter->hw;
3611 u32 tctl, rctl;
3612
e921eb1a 3613 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3614 * reschedule our watchdog timer
3615 */
bc7f75fa
AK		 3616 set_bit(__E1000_DOWN, &adapter->state);
3617
3618 /* disable receives in the hardware */
3619 rctl = er32(RCTL);
7f99ae63
BA		 3620 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3621 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3622 /* flush and sleep below */
3623
4cb9be7a 3624 netif_stop_queue(netdev);
bc7f75fa
AK		 3625
3626 /* disable transmits in the hardware */
3627 tctl = er32(TCTL);
3628 tctl &= ~E1000_TCTL_EN;
3629 ew32(TCTL, tctl);
7f99ae63 3630
bc7f75fa
AK		 3631 /* flush both disables and wait for them to finish */
3632 e1e_flush();
1bba4386 3633 usleep_range(10000, 20000);
bc7f75fa 3634
bc7f75fa
AK		 3635 e1000_irq_disable(adapter);
3636
3637 del_timer_sync(&adapter->watchdog_timer);
3638 del_timer_sync(&adapter->phy_info_timer);
3639
bc7f75fa 3640 netif_carrier_off(netdev);
67fd4fcb
JK		 3641
3642 spin_lock(&adapter->stats64_lock);
3643 e1000e_update_stats(adapter);
3644 spin_unlock(&adapter->stats64_lock);
3645
400484fa 3646 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3647 e1000_clean_tx_ring(adapter->tx_ring);
3648 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3649
bc7f75fa
AK		 3650 adapter->link_speed = 0;
3651 adapter->link_duplex = 0;
3652
52cc3086
JK		 3653 if (!pci_channel_offline(adapter->pdev))
3654 e1000e_reset(adapter);
713b3c9e 3655
e921eb1a 3656 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 3657 * pci_disable_device here.
3658 */
3659}
3660
3661void e1000e_reinit_locked(struct e1000_adapter *adapter)
3662{
3663 might_sleep();
3664 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3665 usleep_range(1000, 2000);
bc7f75fa
AK		 3666 e1000e_down(adapter);
3667 e1000e_up(adapter);
3668 clear_bit(__E1000_RESETTING, &adapter->state);
3669}
3670
3671/**
3672 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3673 * @adapter: board private structure to initialize
3674 *
3675 * e1000_sw_init initializes the Adapter private data structure.
3676 * Fields are initialized based on PCI device information and
3677 * OS network device settings (MTU size).
3678 **/
9f9a12f8 3679static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 3680{
bc7f75fa
AK		 3681 struct net_device *netdev = adapter->netdev;
3682
3683 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3684 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3685 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3686 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3687 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3688 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3689
67fd4fcb
JK		 3690 spin_lock_init(&adapter->stats64_lock);
3691
4662e82b 3692 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3693
4662e82b
BA		 3694 if (e1000_alloc_queues(adapter))
3695 return -ENOMEM;
bc7f75fa 3696
bc7f75fa 3697 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3698 e1000_irq_disable(adapter);
3699
bc7f75fa
AK		 3700 set_bit(__E1000_DOWN, &adapter->state);
3701 return 0;
bc7f75fa
AK		 3702}
3703
f8d59f78
BA		 3704/**
3705 * e1000_intr_msi_test - Interrupt Handler
3706 * @irq: interrupt number
3707 * @data: pointer to a network interface device structure
3708 **/
3709static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3710{
3711 struct net_device *netdev = data;
3712 struct e1000_adapter *adapter = netdev_priv(netdev);
3713 struct e1000_hw *hw = &adapter->hw;
3714 u32 icr = er32(ICR);
3715
3bb99fe2 3716 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3717 if (icr & E1000_ICR_RXSEQ) {
3718 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 3719 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 3720 * interrupt is handled.
3721 */
f8d59f78
BA		 3722 wmb();
3723 }
3724
3725 return IRQ_HANDLED;
3726}
3727
3728/**
3729 * e1000_test_msi_interrupt - Returns 0 for successful test
3730 * @adapter: board private struct
3731 *
3732 * code flow taken from tg3.c
3733 **/
3734static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3735{
3736 struct net_device *netdev = adapter->netdev;
3737 struct e1000_hw *hw = &adapter->hw;
3738 int err;
3739
3740 /* poll_enable hasn't been called yet, so don't need disable */
3741 /* clear any pending events */
3742 er32(ICR);
3743
3744 /* free the real vector and request a test handler */
3745 e1000_free_irq(adapter);
4662e82b 3746 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3747
3748 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 3749 * MSI irq handler will unset this flag
3750 */
f8d59f78
BA		 3751 adapter->flags |= FLAG_MSI_TEST_FAILED;
3752
3753 err = pci_enable_msi(adapter->pdev);
3754 if (err)
3755 goto msi_test_failed;
3756
a0607fd3 3757 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3758 netdev->name, netdev);
3759 if (err) {
3760 pci_disable_msi(adapter->pdev);
3761 goto msi_test_failed;
3762 }
3763
e921eb1a 3764 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 3765 * interrupt.
3766 */
f8d59f78
BA		 3767 wmb();
3768
3769 e1000_irq_enable(adapter);
3770
3771 /* fire an unusual interrupt on the test handler */
3772 ew32(ICS, E1000_ICS_RXSEQ);
3773 e1e_flush();
569a3aff 3774 msleep(100);
f8d59f78
BA		 3775
3776 e1000_irq_disable(adapter);
3777
bc76329d 3778 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 3779
3780 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3781 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3782 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3783 } else {
068e8a30 3784 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3785 }
f8d59f78
BA		 3786
3787 free_irq(adapter->pdev->irq, netdev);
3788 pci_disable_msi(adapter->pdev);
3789
f8d59f78 3790msi_test_failed:
4662e82b 3791 e1000e_set_interrupt_capability(adapter);
068e8a30 3792 return e1000_request_irq(adapter);
f8d59f78
BA		 3793}
3794
3795/**
3796 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3797 * @adapter: board private struct
3798 *
3799 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3800 **/
3801static int e1000_test_msi(struct e1000_adapter *adapter)
3802{
3803 int err;
3804 u16 pci_cmd;
3805
3806 if (!(adapter->flags & FLAG_MSI_ENABLED))
3807 return 0;
3808
3809 /* disable SERR in case the MSI write causes a master abort */
3810 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3811 if (pci_cmd & PCI_COMMAND_SERR)
3812 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3813 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3814
3815 err = e1000_test_msi_interrupt(adapter);
3816
36f2407f
DN		 3817 /* re-enable SERR */
3818 if (pci_cmd & PCI_COMMAND_SERR) {
3819 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3820 pci_cmd |= PCI_COMMAND_SERR;
3821 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3822 }
f8d59f78 3823
f8d59f78
BA		 3824 return err;
3825}
3826
bc7f75fa
AK		 3827/**
3828 * e1000_open - Called when a network interface is made active
3829 * @netdev: network interface device structure
3830 *
3831 * Returns 0 on success, negative value on failure
3832 *
3833 * The open entry point is called when a network interface is made
3834 * active by the system (IFF_UP). At this point all resources needed
3835 * for transmit and receive operations are allocated, the interrupt
3836 * handler is registered with the OS, the watchdog timer is started,
3837 * and the stack is notified that the interface is ready.
3838 **/
3839static int e1000_open(struct net_device *netdev)
3840{
3841 struct e1000_adapter *adapter = netdev_priv(netdev);
3842 struct e1000_hw *hw = &adapter->hw;
23606cf5 3843 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3844 int err;
3845
3846 /* disallow open during test */
3847 if (test_bit(__E1000_TESTING, &adapter->state))
3848 return -EBUSY;
3849
23606cf5
RW		 3850 pm_runtime_get_sync(&pdev->dev);
3851
9c563d20
JB		 3852 netif_carrier_off(netdev);
3853
bc7f75fa 3854 /* allocate transmit descriptors */
55aa6985 3855 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3856 if (err)
3857 goto err_setup_tx;
3858
3859 /* allocate receive descriptors */
55aa6985 3860 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3861 if (err)
3862 goto err_setup_rx;
3863
e921eb1a 3864 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 3865 * interface is now open and reset the part to a known state.
3866 */
3867 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3868 e1000e_get_hw_control(adapter);
11b08be8
BA		 3869 e1000e_reset(adapter);
3870 }
3871
bc7f75fa
AK		 3872 e1000e_power_up_phy(adapter);
3873
3874 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3875 if ((adapter->hw.mng_cookie.status &
3876 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3877 e1000_update_mng_vlan(adapter);
3878
79d4e908
BA		 3879 /* DMA latency requirement to workaround jumbo issue */
3880 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3881 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3882 PM_QOS_CPU_DMA_LATENCY,
3883 PM_QOS_DEFAULT_VALUE);
c128ec29 3884
e921eb1a 3885 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3886 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3887 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3888 * clean_rx handler before we do so.
3889 */
bc7f75fa
AK		 3890 e1000_configure(adapter);
3891
3892 err = e1000_request_irq(adapter);
3893 if (err)
3894 goto err_req_irq;
3895
e921eb1a 3896 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 3897 * ignore e1000e MSI messages, which means we need to test our MSI
3898 * interrupt now
3899 */
4662e82b 3900 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3901 err = e1000_test_msi(adapter);
3902 if (err) {
3903 e_err("Interrupt allocation failed\n");
3904 goto err_req_irq;
3905 }
3906 }
3907
bc7f75fa
AK		 3908 /* From here on the code is the same as e1000e_up() */
3909 clear_bit(__E1000_DOWN, &adapter->state);
3910
3911 napi_enable(&adapter->napi);
3912
3913 e1000_irq_enable(adapter);
3914
09357b00 3915 adapter->tx_hang_recheck = false;
4cb9be7a 3916 netif_start_queue(netdev);
d55b53ff 3917
23606cf5
RW		 3918 adapter->idle_check = true;
3919 pm_runtime_put(&pdev->dev);
3920
bc7f75fa 3921 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3922 if (adapter->msix_entries)
3923 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3924 else
3925 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3926
3927 return 0;
3928
3929err_req_irq:
31dbe5b4 3930 e1000e_release_hw_control(adapter);
bc7f75fa 3931 e1000_power_down_phy(adapter);
55aa6985 3932 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3933err_setup_rx:
55aa6985 3934 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3935err_setup_tx:
3936 e1000e_reset(adapter);
23606cf5 3937 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3938
3939 return err;
3940}
3941
3942/**
3943 * e1000_close - Disables a network interface
3944 * @netdev: network interface device structure
3945 *
3946 * Returns 0, this is not allowed to fail
3947 *
3948 * The close entry point is called when an interface is de-activated
3949 * by the OS. The hardware is still under the drivers control, but
3950 * needs to be disabled. A global MAC reset is issued to stop the
3951 * hardware, and all transmit and receive resources are freed.
3952 **/
3953static int e1000_close(struct net_device *netdev)
3954{
3955 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3956 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 3957 int count = E1000_CHECK_RESET_COUNT;
3958
3959 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
3960 usleep_range(10000, 20000);
bc7f75fa
AK		 3961
3962 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3963
3964 pm_runtime_get_sync(&pdev->dev);
3965
5f4a780d
BA		 3966 napi_disable(&adapter->napi);
3967
23606cf5
RW		 3968 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3969 e1000e_down(adapter);
3970 e1000_free_irq(adapter);
3971 }
bc7f75fa 3972 e1000_power_down_phy(adapter);
bc7f75fa 3973
55aa6985
BA		 3974 e1000e_free_tx_resources(adapter->tx_ring);
3975 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3976
e921eb1a 3977 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 3978 * the same ID is registered on the host OS (let 8021q kill it)
3979 */
86d70e53
JK		 3980 if (adapter->hw.mng_cookie.status &
3981 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3982 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3983
e921eb1a 3984 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 3985 * interface is now closed
3986 */
31dbe5b4
BA		 3987 if ((adapter->flags & FLAG_HAS_AMT) &&
3988 !test_bit(__E1000_TESTING, &adapter->state))
3989 e1000e_release_hw_control(adapter);
bc7f75fa 3990
79d4e908 3991 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 3992 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 3993
23606cf5
RW		 3994 pm_runtime_put_sync(&pdev->dev);
3995
bc7f75fa
AK		 3996 return 0;
3997}
3998/**
3999 * e1000_set_mac - Change the Ethernet Address of the NIC
4000 * @netdev: network interface device structure
4001 * @p: pointer to an address structure
4002 *
4003 * Returns 0 on success, negative on failure
4004 **/
4005static int e1000_set_mac(struct net_device *netdev, void *p)
4006{
4007 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4008 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4009 struct sockaddr *addr = p;
4010
4011 if (!is_valid_ether_addr(addr->sa_data))
4012 return -EADDRNOTAVAIL;
4013
4014 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4015 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4016
69e1e019 4017 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4018
4019 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4020 /* activate the work around */
4021 e1000e_set_laa_state_82571(&adapter->hw, 1);
4022
e921eb1a 4023 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4024 * between the time RAR[0] gets clobbered and the time it
4025 * gets fixed (in e1000_watchdog), the actual LAA is in one
4026 * of the RARs and no incoming packets directed to this port
4027 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4028 * RAR[14]
4029 */
69e1e019
BA		 4030 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4031 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4032 }
4033
4034 return 0;
4035}
4036
a8f88ff5
JB		 4037/**
4038 * e1000e_update_phy_task - work thread to update phy
4039 * @work: pointer to our work struct
4040 *
4041 * this worker thread exists because we must acquire a
4042 * semaphore to read the phy, which we could msleep while
4043 * waiting for it, and we can't msleep in a timer.
4044 **/
4045static void e1000e_update_phy_task(struct work_struct *work)
4046{
4047 struct e1000_adapter *adapter = container_of(work,
4048 struct e1000_adapter, update_phy_task);
615b32af
JB		 4049
4050 if (test_bit(__E1000_DOWN, &adapter->state))
4051 return;
4052
a8f88ff5
JB		 4053 e1000_get_phy_info(&adapter->hw);
4054}
4055
e921eb1a
BA		 4056/**
4057 * e1000_update_phy_info - timre call-back to update PHY info
4058 * @data: pointer to adapter cast into an unsigned long
4059 *
ad68076e
BA		 4060 * Need to wait a few seconds after link up to get diagnostic information from
4061 * the phy
e921eb1a 4062 **/
bc7f75fa
AK		 4063static void e1000_update_phy_info(unsigned long data)
4064{
4065 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4066
4067 if (test_bit(__E1000_DOWN, &adapter->state))
4068 return;
4069
a8f88ff5 4070 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4071}
4072
8c7bbb92
BA		 4073/**
4074 * e1000e_update_phy_stats - Update the PHY statistics counters
4075 * @adapter: board private structure
2b6b168d
BA		 4076 *
4077 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4078 **/
4079static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4080{
4081 struct e1000_hw *hw = &adapter->hw;
4082 s32 ret_val;
4083 u16 phy_data;
4084
4085 ret_val = hw->phy.ops.acquire(hw);
4086 if (ret_val)
4087 return;
4088
e921eb1a 4089 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4090 * If not, set to the page with the PHY status registers.
4091 */
2b6b168d 4092 hw->phy.addr = 1;
8c7bbb92
BA		 4093 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4094 &phy_data);
4095 if (ret_val)
4096 goto release;
2b6b168d
BA		 4097 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4098 ret_val = hw->phy.ops.set_page(hw,
4099 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4100 if (ret_val)
4101 goto release;
4102 }
4103
8c7bbb92 4104 /* Single Collision Count */
2b6b168d
BA		 4105 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4106 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4107 if (!ret_val)
4108 adapter->stats.scc += phy_data;
4109
4110 /* Excessive Collision Count */
2b6b168d
BA		 4111 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4112 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4113 if (!ret_val)
4114 adapter->stats.ecol += phy_data;
4115
4116 /* Multiple Collision Count */
2b6b168d
BA		 4117 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4118 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4119 if (!ret_val)
4120 adapter->stats.mcc += phy_data;
4121
4122 /* Late Collision Count */
2b6b168d
BA		 4123 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4124 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4125 if (!ret_val)
4126 adapter->stats.latecol += phy_data;
4127
4128 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4129 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4130 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4131 if (!ret_val)
4132 hw->mac.collision_delta = phy_data;
4133
4134 /* Defer Count */
2b6b168d
BA		 4135 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4136 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4137 if (!ret_val)
4138 adapter->stats.dc += phy_data;
4139
4140 /* Transmit with no CRS */
2b6b168d
BA		 4141 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4142 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4143 if (!ret_val)
4144 adapter->stats.tncrs += phy_data;
4145
4146release:
4147 hw->phy.ops.release(hw);
4148}
4149
bc7f75fa
AK		 4150/**
4151 * e1000e_update_stats - Update the board statistics counters
4152 * @adapter: board private structure
4153 **/
67fd4fcb 4154static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4155{
7274c20f 4156 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4157 struct e1000_hw *hw = &adapter->hw;
4158 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4159
e921eb1a 4160 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4161 * connection is down.
4162 */
4163 if (adapter->link_speed == 0)
4164 return;
4165 if (pci_channel_offline(pdev))
4166 return;
4167
bc7f75fa
AK		 4168 adapter->stats.crcerrs += er32(CRCERRS);
4169 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4170 adapter->stats.gorc += er32(GORCL);
4171 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4172 adapter->stats.bprc += er32(BPRC);
4173 adapter->stats.mprc += er32(MPRC);
4174 adapter->stats.roc += er32(ROC);
4175
bc7f75fa 4176 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4177
4178 /* Half-duplex statistics */
4179 if (adapter->link_duplex == HALF_DUPLEX) {
4180 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4181 e1000e_update_phy_stats(adapter);
4182 } else {
4183 adapter->stats.scc += er32(SCC);
4184 adapter->stats.ecol += er32(ECOL);
4185 adapter->stats.mcc += er32(MCC);
4186 adapter->stats.latecol += er32(LATECOL);
4187 adapter->stats.dc += er32(DC);
4188
4189 hw->mac.collision_delta = er32(COLC);
4190
4191 if ((hw->mac.type != e1000_82574) &&
4192 (hw->mac.type != e1000_82583))
4193 adapter->stats.tncrs += er32(TNCRS);
4194 }
4195 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4196 }
8c7bbb92 4197
bc7f75fa
AK		 4198 adapter->stats.xonrxc += er32(XONRXC);
4199 adapter->stats.xontxc += er32(XONTXC);
4200 adapter->stats.xoffrxc += er32(XOFFRXC);
4201 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4202 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4203 adapter->stats.gotc += er32(GOTCL);
4204 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4205 adapter->stats.rnbc += er32(RNBC);
4206 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4207
4208 adapter->stats.mptc += er32(MPTC);
4209 adapter->stats.bptc += er32(BPTC);
4210
4211 /* used for adaptive IFS */
4212
4213 hw->mac.tx_packet_delta = er32(TPT);
4214 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4215
4216 adapter->stats.algnerrc += er32(ALGNERRC);
4217 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4218 adapter->stats.cexterr += er32(CEXTERR);
4219 adapter->stats.tsctc += er32(TSCTC);
4220 adapter->stats.tsctfc += er32(TSCTFC);
4221
bc7f75fa 4222 /* Fill out the OS statistics structure */
7274c20f
AK		 4223 netdev->stats.multicast = adapter->stats.mprc;
4224 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4225
4226 /* Rx Errors */
4227
e921eb1a 4228 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4229 * our own version based on RUC and ROC
4230 */
7274c20f 4231 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4232 adapter->stats.crcerrs + adapter->stats.algnerrc +
4233 adapter->stats.ruc + adapter->stats.roc +
4234 adapter->stats.cexterr;
7274c20f 4235 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4236 adapter->stats.roc;
7274c20f
AK		 4237 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4238 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4239 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4240
4241 /* Tx Errors */
7274c20f 4242 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4243 adapter->stats.latecol;
7274c20f
AK		 4244 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4245 netdev->stats.tx_window_errors = adapter->stats.latecol;
4246 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4247
4248 /* Tx Dropped needs to be maintained elsewhere */
4249
bc7f75fa
AK		 4250 /* Management Stats */
4251 adapter->stats.mgptc += er32(MGTPTC);
4252 adapter->stats.mgprc += er32(MGTPRC);
4253 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4254}
4255
7c25769f
BA		 4256/**
4257 * e1000_phy_read_status - Update the PHY register status snapshot
4258 * @adapter: board private structure
4259 **/
4260static void e1000_phy_read_status(struct e1000_adapter *adapter)
4261{
4262 struct e1000_hw *hw = &adapter->hw;
4263 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4264
4265 if ((er32(STATUS) & E1000_STATUS_LU) &&
4266 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4267 int ret_val;
4268
7c25769f
BA		 4269 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4270 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4271 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4272 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4273 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4274 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4275 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4276 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4277 if (ret_val)
44defeb3 4278 e_warn("Error reading PHY register\n");
7c25769f 4279 } else {
e921eb1a 4280 /* Do not read PHY registers if link is not up
7c25769f
BA		 4281 * Set values to typical power-on defaults
4282 */
4283 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4284 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4285 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4286 BMSR_ERCAP);
4287 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4288 ADVERTISE_ALL | ADVERTISE_CSMA);
4289 phy->lpa = 0;
4290 phy->expansion = EXPANSION_ENABLENPAGE;
4291 phy->ctrl1000 = ADVERTISE_1000FULL;
4292 phy->stat1000 = 0;
4293 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4294 }
7c25769f
BA		 4295}
4296
bc7f75fa
AK		 4297static void e1000_print_link_info(struct e1000_adapter *adapter)
4298{
bc7f75fa
AK		 4299 struct e1000_hw *hw = &adapter->hw;
4300 u32 ctrl = er32(CTRL);
4301
8f12fe86 4302 /* Link status message must follow this format for user tools */
ef456f85
JK		 4303 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4304 adapter->netdev->name,
4305 adapter->link_speed,
4306 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4307 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4308 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4309 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4310}
4311
0c6bdb30 4312static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4313{
4314 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4315 bool link_active = false;
318a94d6
JK		 4316 s32 ret_val = 0;
4317
e921eb1a 4318 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4319 * Rx sequence error interrupt. get_link_status will stay
4320 * false until the check_for_link establishes link
4321 * for copper adapters ONLY
4322 */
4323 switch (hw->phy.media_type) {
4324 case e1000_media_type_copper:
4325 if (hw->mac.get_link_status) {
4326 ret_val = hw->mac.ops.check_for_link(hw);
4327 link_active = !hw->mac.get_link_status;
4328 } else {
3db1cd5c 4329 link_active = true;
318a94d6
JK		 4330 }
4331 break;
4332 case e1000_media_type_fiber:
4333 ret_val = hw->mac.ops.check_for_link(hw);
4334 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4335 break;
4336 case e1000_media_type_internal_serdes:
4337 ret_val = hw->mac.ops.check_for_link(hw);
4338 link_active = adapter->hw.mac.serdes_has_link;
4339 break;
4340 default:
4341 case e1000_media_type_unknown:
4342 break;
4343 }
4344
4345 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4346 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4347 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4348 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4349 }
4350
4351 return link_active;
4352}
4353
4354static void e1000e_enable_receives(struct e1000_adapter *adapter)
4355{
4356 /* make sure the receive unit is started */
4357 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4358 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4359 struct e1000_hw *hw = &adapter->hw;
4360 u32 rctl = er32(RCTL);
4361 ew32(RCTL, rctl | E1000_RCTL_EN);
4362 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4363 }
4364}
4365
ff10e13c
CW		 4366static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4367{
4368 struct e1000_hw *hw = &adapter->hw;
4369
e921eb1a 4370 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4371 * for hung state and reset, if two calls return true
4372 */
4373 if (e1000_check_phy_82574(hw))
4374 adapter->phy_hang_count++;
4375 else
4376 adapter->phy_hang_count = 0;
4377
4378 if (adapter->phy_hang_count > 1) {
4379 adapter->phy_hang_count = 0;
4380 schedule_work(&adapter->reset_task);
4381 }
4382}
4383
bc7f75fa
AK		 4384/**
4385 * e1000_watchdog - Timer Call-back
4386 * @data: pointer to adapter cast into an unsigned long
4387 **/
4388static void e1000_watchdog(unsigned long data)
4389{
4390 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4391
4392 /* Do the rest outside of interrupt context */
4393 schedule_work(&adapter->watchdog_task);
4394
4395 /* TODO: make this use queue_delayed_work() */
4396}
4397
4398static void e1000_watchdog_task(struct work_struct *work)
4399{
4400 struct e1000_adapter *adapter = container_of(work,
4401 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4402 struct net_device *netdev = adapter->netdev;
4403 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4404 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4405 struct e1000_ring *tx_ring = adapter->tx_ring;
4406 struct e1000_hw *hw = &adapter->hw;
4407 u32 link, tctl;
bc7f75fa 4408
615b32af
JB		 4409 if (test_bit(__E1000_DOWN, &adapter->state))
4410 return;
4411
b405e8df 4412 link = e1000e_has_link(adapter);
318a94d6 4413 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4414 /* Cancel scheduled suspend requests. */
4415 pm_runtime_resume(netdev->dev.parent);
4416
318a94d6 4417 e1000e_enable_receives(adapter);
bc7f75fa 4418 goto link_up;
bc7f75fa
AK		 4419 }
4420
4421 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4422 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4423 e1000_update_mng_vlan(adapter);
4424
bc7f75fa
AK		 4425 if (link) {
4426 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4427 bool txb2b = true;
23606cf5
RW		 4428
4429 /* Cancel scheduled suspend requests. */
4430 pm_runtime_resume(netdev->dev.parent);
4431
318a94d6 4432 /* update snapshot of PHY registers on LSC */
7c25769f 4433 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4434 mac->ops.get_link_up_info(&adapter->hw,
4435 &adapter->link_speed,
4436 &adapter->link_duplex);
4437 e1000_print_link_info(adapter);
e921eb1a 4438 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4439 * if link has autonegotiated at 10/100 half
4440 */
4441 if ((hw->phy.type == e1000_phy_igp_3 ||
4442 hw->phy.type == e1000_phy_bm) &&
4443 (hw->mac.autoneg == true) &&
4444 (adapter->link_speed == SPEED_10 ||
4445 adapter->link_speed == SPEED_100) &&
4446 (adapter->link_duplex == HALF_DUPLEX)) {
4447 u16 autoneg_exp;
4448
4449 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4450
4451 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4452 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4453 }
4454
f49c57e1 4455 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4456 adapter->tx_timeout_factor = 1;
4457 switch (adapter->link_speed) {
4458 case SPEED_10:
3db1cd5c 4459 txb2b = false;
10f1b492 4460 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4461 break;
4462 case SPEED_100:
3db1cd5c 4463 txb2b = false;
4c86e0b9 4464 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4465 break;
4466 }
4467
e921eb1a 4468 /* workaround: re-program speed mode bit after
ad68076e
BA		 4469 * link-up event
4470 */
bc7f75fa
AK		 4471 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4472 !txb2b) {
4473 u32 tarc0;
e9ec2c0f 4474 tarc0 = er32(TARC(0));
bc7f75fa 4475 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4476 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4477 }
4478
e921eb1a 4479 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4480 * some hardware issues
4481 */
bc7f75fa
AK		 4482 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4483 switch (adapter->link_speed) {
4484 case SPEED_10:
4485 case SPEED_100:
44defeb3 4486 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4487 netdev->features &= ~NETIF_F_TSO;
4488 netdev->features &= ~NETIF_F_TSO6;
4489 break;
4490 case SPEED_1000:
4491 netdev->features |= NETIF_F_TSO;
4492 netdev->features |= NETIF_F_TSO6;
4493 break;
4494 default:
4495 /* oops */
4496 break;
4497 }
4498 }
4499
e921eb1a 4500 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4501 * after setting TARC(0)
4502 */
bc7f75fa
AK		 4503 tctl = er32(TCTL);
4504 tctl |= E1000_TCTL_EN;
4505 ew32(TCTL, tctl);
4506
e921eb1a 4507 /* Perform any post-link-up configuration before
75eb0fad
BA		 4508 * reporting link up.
4509 */
4510 if (phy->ops.cfg_on_link_up)
4511 phy->ops.cfg_on_link_up(hw);
4512
bc7f75fa 4513 netif_carrier_on(netdev);
bc7f75fa
AK		 4514
4515 if (!test_bit(__E1000_DOWN, &adapter->state))
4516 mod_timer(&adapter->phy_info_timer,
4517 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4518 }
4519 } else {
4520 if (netif_carrier_ok(netdev)) {
4521 adapter->link_speed = 0;
4522 adapter->link_duplex = 0;
8f12fe86
BA		 4523 /* Link status message must follow this format */
4524 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4525 adapter->netdev->name);
bc7f75fa 4526 netif_carrier_off(netdev);
bc7f75fa
AK		 4527 if (!test_bit(__E1000_DOWN, &adapter->state))
4528 mod_timer(&adapter->phy_info_timer,
4529 round_jiffies(jiffies + 2 * HZ));
4530
4531 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4532 schedule_work(&adapter->reset_task);
23606cf5
RW		 4533 else
4534 pm_schedule_suspend(netdev->dev.parent,
4535 LINK_TIMEOUT);
bc7f75fa
AK		 4536 }
4537 }
4538
4539link_up:
67fd4fcb 4540 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4541 e1000e_update_stats(adapter);
4542
4543 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4544 adapter->tpt_old = adapter->stats.tpt;
4545 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4546 adapter->colc_old = adapter->stats.colc;
4547
7c25769f
BA		 4548 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4549 adapter->gorc_old = adapter->stats.gorc;
4550 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4551 adapter->gotc_old = adapter->stats.gotc;
2084b114 4552 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4553
4554 e1000e_update_adaptive(&adapter->hw);
4555
90da0669
BA		 4556 if (!netif_carrier_ok(netdev) &&
4557 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
e921eb1a 4558 /* We've lost link, so the controller stops DMA,
90da0669
BA		 4559 * but we've got queued Tx work that's never going
4560 * to get done, so reset controller to flush Tx.
4561 * (Do the reset outside of interrupt context).
4562 */
90da0669
BA		 4563 schedule_work(&adapter->reset_task);
4564 /* return immediately since reset is imminent */
4565 return;
bc7f75fa
AK		 4566 }
4567
eab2abf5
JB		 4568 /* Simple mode for Interrupt Throttle Rate (ITR) */
4569 if (adapter->itr_setting == 4) {
e921eb1a 4570 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4571 * Total asymmetrical Tx or Rx gets ITR=8000;
4572 * everyone else is between 2000-8000.
4573 */
4574 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4575 u32 dif = (adapter->gotc > adapter->gorc ?
4576 adapter->gotc - adapter->gorc :
4577 adapter->gorc - adapter->gotc) / 10000;
4578 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4579
22a4cca2 4580 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 4581 }
4582
ad68076e 4583 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4584 if (adapter->msix_entries)
4585 ew32(ICS, adapter->rx_ring->ims_val);
4586 else
4587 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4588
713b3c9e
JB		 4589 /* flush pending descriptors to memory before detecting Tx hang */
4590 e1000e_flush_descriptors(adapter);
4591
bc7f75fa 4592 /* Force detection of hung controller every watchdog period */
3db1cd5c 4593 adapter->detect_tx_hung = true;
bc7f75fa 4594
e921eb1a 4595 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 4596 * reset from the other port. Set the appropriate LAA in RAR[0]
4597 */
bc7f75fa 4598 if (e1000e_get_laa_state_82571(hw))
69e1e019 4599 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 4600
ff10e13c
CW		 4601 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4602 e1000e_check_82574_phy_workaround(adapter);
4603
bc7f75fa
AK		 4604 /* Reset the timer */
4605 if (!test_bit(__E1000_DOWN, &adapter->state))
4606 mod_timer(&adapter->watchdog_timer,
4607 round_jiffies(jiffies + 2 * HZ));
4608}
4609
4610#define E1000_TX_FLAGS_CSUM 0x00000001
4611#define E1000_TX_FLAGS_VLAN 0x00000002
4612#define E1000_TX_FLAGS_TSO 0x00000004
4613#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4614#define E1000_TX_FLAGS_NO_FCS 0x00000010
bc7f75fa
AK		 4615#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4616#define E1000_TX_FLAGS_VLAN_SHIFT 16
4617
55aa6985 4618static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4619{
bc7f75fa
AK		 4620 struct e1000_context_desc *context_desc;
4621 struct e1000_buffer *buffer_info;
4622 unsigned int i;
4623 u32 cmd_length = 0;
70443ae9 4624 u16 ipcse = 0, mss;
bc7f75fa 4625 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4626
3d5e33c9
BA		 4627 if (!skb_is_gso(skb))
4628 return 0;
bc7f75fa 4629
3d5e33c9 4630 if (skb_header_cloned(skb)) {
90da0669
BA		 4631 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4632
3d5e33c9
BA		 4633 if (err)
4634 return err;
bc7f75fa
AK		 4635 }
4636
3d5e33c9
BA		 4637 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4638 mss = skb_shinfo(skb)->gso_size;
4639 if (skb->protocol == htons(ETH_P_IP)) {
4640 struct iphdr *iph = ip_hdr(skb);
4641 iph->tot_len = 0;
4642 iph->check = 0;
4643 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4644 0, IPPROTO_TCP, 0);
4645 cmd_length = E1000_TXD_CMD_IP;
4646 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4647 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4648 ipv6_hdr(skb)->payload_len = 0;
4649 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4650 &ipv6_hdr(skb)->daddr,
4651 0, IPPROTO_TCP, 0);
4652 ipcse = 0;
4653 }
4654 ipcss = skb_network_offset(skb);
4655 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4656 tucss = skb_transport_offset(skb);
4657 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 4658
4659 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4660 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4661
4662 i = tx_ring->next_to_use;
4663 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4664 buffer_info = &tx_ring->buffer_info[i];
4665
4666 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4667 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4668 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4669 context_desc->upper_setup.tcp_fields.tucss = tucss;
4670 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 4671 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 4672 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4673 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4674 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4675
4676 buffer_info->time_stamp = jiffies;
4677 buffer_info->next_to_watch = i;
4678
4679 i++;
4680 if (i == tx_ring->count)
4681 i = 0;
4682 tx_ring->next_to_use = i;
4683
4684 return 1;
bc7f75fa
AK		 4685}
4686
55aa6985 4687static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4688{
55aa6985 4689 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4690 struct e1000_context_desc *context_desc;
4691 struct e1000_buffer *buffer_info;
4692 unsigned int i;
4693 u8 css;
af807c82 4694 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4695 __be16 protocol;
bc7f75fa 4696
af807c82
DG		 4697 if (skb->ip_summed != CHECKSUM_PARTIAL)
4698 return 0;
bc7f75fa 4699
5f66f208
AJ		 4700 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4701 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4702 else
4703 protocol = skb->protocol;
4704
3f518390 4705 switch (protocol) {
09640e63 4706 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4707 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4708 cmd_len |= E1000_TXD_CMD_TCP;
4709 break;
09640e63 4710 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4711 /* XXX not handling all IPV6 headers */
4712 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4713 cmd_len |= E1000_TXD_CMD_TCP;
4714 break;
4715 default:
4716 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4717 e_warn("checksum_partial proto=%x!\n",
4718 be16_to_cpu(protocol));
af807c82 4719 break;
bc7f75fa
AK		 4720 }
4721
0d0b1672 4722 css = skb_checksum_start_offset(skb);
af807c82
DG		 4723
4724 i = tx_ring->next_to_use;
4725 buffer_info = &tx_ring->buffer_info[i];
4726 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4727
4728 context_desc->lower_setup.ip_config = 0;
4729 context_desc->upper_setup.tcp_fields.tucss = css;
4730 context_desc->upper_setup.tcp_fields.tucso =
4731 css + skb->csum_offset;
4732 context_desc->upper_setup.tcp_fields.tucse = 0;
4733 context_desc->tcp_seg_setup.data = 0;
4734 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4735
4736 buffer_info->time_stamp = jiffies;
4737 buffer_info->next_to_watch = i;
4738
4739 i++;
4740 if (i == tx_ring->count)
4741 i = 0;
4742 tx_ring->next_to_use = i;
4743
4744 return 1;
bc7f75fa
AK		 4745}
4746
55aa6985
BA		 4747static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4748 unsigned int first, unsigned int max_per_txd,
d821a4c4 4749 unsigned int nr_frags)
bc7f75fa 4750{
55aa6985 4751 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4752 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4753 struct e1000_buffer *buffer_info;
8ddc951c 4754 unsigned int len = skb_headlen(skb);
03b1320d 4755 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4756 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4757
4758 i = tx_ring->next_to_use;
4759
4760 while (len) {
1b7719c4 4761 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4762 size = min(len, max_per_txd);
4763
bc7f75fa 4764 buffer_info->length = size;
bc7f75fa 4765 buffer_info->time_stamp = jiffies;
bc7f75fa 4766 buffer_info->next_to_watch = i;
0be3f55f
NN		 4767 buffer_info->dma = dma_map_single(&pdev->dev,
4768 skb->data + offset,
af667a29 4769 size, DMA_TO_DEVICE);
03b1320d 4770 buffer_info->mapped_as_page = false;
0be3f55f 4771 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4772 goto dma_error;
bc7f75fa
AK		 4773
4774 len -= size;
4775 offset += size;
03b1320d 4776 count++;
1b7719c4
AD		 4777
4778 if (len) {
4779 i++;
4780 if (i == tx_ring->count)
4781 i = 0;
4782 }
bc7f75fa
AK		 4783 }
4784
4785 for (f = 0; f < nr_frags; f++) {
9e903e08 4786 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4787
4788 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4789 len = skb_frag_size(frag);
877749bf 4790 offset = 0;
bc7f75fa
AK		 4791
4792 while (len) {
1b7719c4
AD		 4793 i++;
4794 if (i == tx_ring->count)
4795 i = 0;
4796
bc7f75fa
AK		 4797 buffer_info = &tx_ring->buffer_info[i];
4798 size = min(len, max_per_txd);
bc7f75fa
AK		 4799
4800 buffer_info->length = size;
4801 buffer_info->time_stamp = jiffies;
bc7f75fa 4802 buffer_info->next_to_watch = i;
877749bf
IC		 4803 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4804 offset, size, DMA_TO_DEVICE);
03b1320d 4805 buffer_info->mapped_as_page = true;
0be3f55f 4806 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4807 goto dma_error;
bc7f75fa
AK		 4808
4809 len -= size;
4810 offset += size;
4811 count++;
bc7f75fa
AK		 4812 }
4813 }
4814
af667a29 4815 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4816 /* multiply data chunks by size of headers */
4817 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4818
bc7f75fa 4819 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4820 tx_ring->buffer_info[i].segs = segs;
4821 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4822 tx_ring->buffer_info[first].next_to_watch = i;
4823
4824 return count;
03b1320d
AD		 4825
4826dma_error:
af667a29 4827 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4828 buffer_info->dma = 0;
c1fa347f 4829 if (count)
03b1320d 4830 count--;
c1fa347f
RK		 4831
4832 while (count--) {
af667a29 4833 if (i == 0)
03b1320d 4834 i += tx_ring->count;
c1fa347f 4835 i--;
03b1320d 4836 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4837 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4838 }
4839
4840 return 0;
bc7f75fa
AK		 4841}
4842
55aa6985 4843static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4844{
55aa6985 4845 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4846 struct e1000_tx_desc *tx_desc = NULL;
4847 struct e1000_buffer *buffer_info;
4848 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4849 unsigned int i;
4850
4851 if (tx_flags & E1000_TX_FLAGS_TSO) {
4852 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4853 E1000_TXD_CMD_TSE;
4854 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4855
4856 if (tx_flags & E1000_TX_FLAGS_IPV4)
4857 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4858 }
4859
4860 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4861 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4862 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4863 }
4864
4865 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4866 txd_lower |= E1000_TXD_CMD_VLE;
4867 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4868 }
4869
943146de
BG		 4870 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4871 txd_lower &= ~(E1000_TXD_CMD_IFCS);
4872
bc7f75fa
AK		 4873 i = tx_ring->next_to_use;
4874
36b973df 4875 do {
bc7f75fa
AK		 4876 buffer_info = &tx_ring->buffer_info[i];
4877 tx_desc = E1000_TX_DESC(*tx_ring, i);
4878 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4879 tx_desc->lower.data =
4880 cpu_to_le32(txd_lower | buffer_info->length);
4881 tx_desc->upper.data = cpu_to_le32(txd_upper);
4882
4883 i++;
4884 if (i == tx_ring->count)
4885 i = 0;
36b973df 4886 } while (--count > 0);
bc7f75fa
AK		 4887
4888 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4889
943146de
BG		 4890 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4891 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4892 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4893
e921eb1a 4894 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 4895 * know there are new descriptors to fetch. (Only
4896 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4897 * such as IA-64).
4898 */
bc7f75fa
AK		 4899 wmb();
4900
4901 tx_ring->next_to_use = i;
c6e7f51e
BA		 4902
4903 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4904 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4905 else
c5083cf6 4906 writel(i, tx_ring->tail);
c6e7f51e 4907
e921eb1a 4908 /* we need this if more than one processor can write to our tail
ad68076e
BA		 4909 * at a time, it synchronizes IO on IA64/Altix systems
4910 */
bc7f75fa
AK		 4911 mmiowb();
4912}
4913
4914#define MINIMUM_DHCP_PACKET_SIZE 282
4915static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4916 struct sk_buff *skb)
4917{
4918 struct e1000_hw *hw = &adapter->hw;
4919 u16 length, offset;
4920
4921 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4922 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4923 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4924 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4925 return 0;
4926 }
4927
4928 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4929 return 0;
4930
4931 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4932 return 0;
4933
4934 {
4935 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4936 struct udphdr *udp;
4937
4938 if (ip->protocol != IPPROTO_UDP)
4939 return 0;
4940
4941 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4942 if (ntohs(udp->dest) != 67)
4943 return 0;
4944
4945 offset = (u8 *)udp + 8 - skb->data;
4946 length = skb->len - offset;
4947 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4948 }
4949
4950 return 0;
4951}
4952
55aa6985 4953static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4954{
55aa6985 4955 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4956
55aa6985 4957 netif_stop_queue(adapter->netdev);
e921eb1a 4958 /* Herbert's original patch had:
bc7f75fa 4959 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4960 * but since that doesn't exist yet, just open code it.
4961 */
bc7f75fa
AK		 4962 smp_mb();
4963
e921eb1a 4964 /* We need to check again in a case another CPU has just
ad68076e
BA		 4965 * made room available.
4966 */
55aa6985 4967 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 4968 return -EBUSY;
4969
4970 /* A reprieve! */
55aa6985 4971 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 4972 ++adapter->restart_queue;
4973 return 0;
4974}
4975
55aa6985 4976static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4977{
d821a4c4
BA		 4978 BUG_ON(size > tx_ring->count);
4979
55aa6985 4980 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 4981 return 0;
55aa6985 4982 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 4983}
4984
3b29a56d
SH		 4985static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
4986 struct net_device *netdev)
bc7f75fa
AK		 4987{
4988 struct e1000_adapter *adapter = netdev_priv(netdev);
4989 struct e1000_ring *tx_ring = adapter->tx_ring;
4990 unsigned int first;
bc7f75fa 4991 unsigned int tx_flags = 0;
e743d313 4992 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 4993 unsigned int nr_frags;
4994 unsigned int mss;
bc7f75fa
AK		 4995 int count = 0;
4996 int tso;
4997 unsigned int f;
bc7f75fa
AK		 4998
4999 if (test_bit(__E1000_DOWN, &adapter->state)) {
5000 dev_kfree_skb_any(skb);
5001 return NETDEV_TX_OK;
5002 }
5003
5004 if (skb->len <= 0) {
5005 dev_kfree_skb_any(skb);
5006 return NETDEV_TX_OK;
5007 }
5008
e921eb1a 5009 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5010 * pad skb in order to meet this minimum size requirement
5011 */
5012 if (unlikely(skb->len < 17)) {
5013 if (skb_pad(skb, 17 - skb->len))
5014 return NETDEV_TX_OK;
5015 skb->len = 17;
5016 skb_set_tail_pointer(skb, 17);
5017 }
5018
bc7f75fa 5019 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5020 if (mss) {
5021 u8 hdr_len;
bc7f75fa 5022
e921eb1a 5023 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5024 * points to just header, pull a few bytes of payload from
5025 * frags into skb->data
5026 */
bc7f75fa 5027 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5028 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5029 * avoiding it could save a lot of cycles
5030 */
4e6c709c 5031 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5032 unsigned int pull_size;
5033
a2a5b323 5034 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5035 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5036 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5037 dev_kfree_skb_any(skb);
5038 return NETDEV_TX_OK;
5039 }
e743d313 5040 len = skb_headlen(skb);
bc7f75fa
AK		 5041 }
5042 }
5043
5044 /* reserve a descriptor for the offload context */
5045 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5046 count++;
5047 count++;
5048
d821a4c4 5049 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5050
5051 nr_frags = skb_shinfo(skb)->nr_frags;
5052 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5053 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5054 adapter->tx_fifo_limit);
bc7f75fa
AK		 5055
5056 if (adapter->hw.mac.tx_pkt_filtering)
5057 e1000_transfer_dhcp_info(adapter, skb);
5058
e921eb1a 5059 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5060 * head, otherwise try next time
5061 */
55aa6985 5062 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5063 return NETDEV_TX_BUSY;
bc7f75fa 5064
eab6d18d 5065 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5066 tx_flags |= E1000_TX_FLAGS_VLAN;
5067 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5068 }
5069
5070 first = tx_ring->next_to_use;
5071
55aa6985 5072 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5073 if (tso < 0) {
5074 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5075 return NETDEV_TX_OK;
5076 }
5077
5078 if (tso)
5079 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5080 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5081 tx_flags |= E1000_TX_FLAGS_CSUM;
5082
e921eb1a 5083 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5084 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5085 * no longer assume, we must.
5086 */
bc7f75fa
AK		 5087 if (skb->protocol == htons(ETH_P_IP))
5088 tx_flags |= E1000_TX_FLAGS_IPV4;
5089
943146de
BG		 5090 if (unlikely(skb->no_fcs))
5091 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5092
25985edc 5093 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5094 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5095 nr_frags);
1b7719c4 5096 if (count) {
80be3129
WB		 5097 skb_tx_timestamp(skb);
5098
3f0cfa3b 5099 netdev_sent_queue(netdev, skb->len);
55aa6985 5100 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5101 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5102 e1000_maybe_stop_tx(tx_ring,
5103 (MAX_SKB_FRAGS *
5104 DIV_ROUND_UP(PAGE_SIZE,
5105 adapter->tx_fifo_limit) + 2));
1b7719c4 5106 } else {
bc7f75fa 5107 dev_kfree_skb_any(skb);
1b7719c4
AD		 5108 tx_ring->buffer_info[first].time_stamp = 0;
5109 tx_ring->next_to_use = first;
bc7f75fa
AK		 5110 }
5111
bc7f75fa
AK		 5112 return NETDEV_TX_OK;
5113}
5114
5115/**
5116 * e1000_tx_timeout - Respond to a Tx Hang
5117 * @netdev: network interface device structure
5118 **/
5119static void e1000_tx_timeout(struct net_device *netdev)
5120{
5121 struct e1000_adapter *adapter = netdev_priv(netdev);
5122
5123 /* Do the reset outside of interrupt context */
5124 adapter->tx_timeout_count++;
5125 schedule_work(&adapter->reset_task);
5126}
5127
5128static void e1000_reset_task(struct work_struct *work)
5129{
5130 struct e1000_adapter *adapter;
5131 adapter = container_of(work, struct e1000_adapter, reset_task);
5132
615b32af
JB		 5133 /* don't run the task if already down */
5134 if (test_bit(__E1000_DOWN, &adapter->state))
5135 return;
5136
affa9dfb
CW		 5137 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5138 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5139 e1000e_dump(adapter);
5140 e_err("Reset adapter\n");
5141 }
bc7f75fa
AK		 5142 e1000e_reinit_locked(adapter);
5143}
5144
5145/**
67fd4fcb 5146 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5147 * @netdev: network interface device structure
67fd4fcb 5148 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5149 *
5150 * Returns the address of the device statistics structure.
bc7f75fa 5151 **/
67fd4fcb
JK		 5152struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5153 struct rtnl_link_stats64 *stats)
bc7f75fa 5154{
67fd4fcb
JK		 5155 struct e1000_adapter *adapter = netdev_priv(netdev);
5156
5157 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5158 spin_lock(&adapter->stats64_lock);
5159 e1000e_update_stats(adapter);
5160 /* Fill out the OS statistics structure */
5161 stats->rx_bytes = adapter->stats.gorc;
5162 stats->rx_packets = adapter->stats.gprc;
5163 stats->tx_bytes = adapter->stats.gotc;
5164 stats->tx_packets = adapter->stats.gptc;
5165 stats->multicast = adapter->stats.mprc;
5166 stats->collisions = adapter->stats.colc;
5167
5168 /* Rx Errors */
5169
e921eb1a 5170 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5171 * our own version based on RUC and ROC
5172 */
5173 stats->rx_errors = adapter->stats.rxerrc +
5174 adapter->stats.crcerrs + adapter->stats.algnerrc +
5175 adapter->stats.ruc + adapter->stats.roc +
5176 adapter->stats.cexterr;
5177 stats->rx_length_errors = adapter->stats.ruc +
5178 adapter->stats.roc;
5179 stats->rx_crc_errors = adapter->stats.crcerrs;
5180 stats->rx_frame_errors = adapter->stats.algnerrc;
5181 stats->rx_missed_errors = adapter->stats.mpc;
5182
5183 /* Tx Errors */
5184 stats->tx_errors = adapter->stats.ecol +
5185 adapter->stats.latecol;
5186 stats->tx_aborted_errors = adapter->stats.ecol;
5187 stats->tx_window_errors = adapter->stats.latecol;
5188 stats->tx_carrier_errors = adapter->stats.tncrs;
5189
5190 /* Tx Dropped needs to be maintained elsewhere */
5191
5192 spin_unlock(&adapter->stats64_lock);
5193 return stats;
bc7f75fa
AK		 5194}
5195
5196/**
5197 * e1000_change_mtu - Change the Maximum Transfer Unit
5198 * @netdev: network interface device structure
5199 * @new_mtu: new value for maximum frame size
5200 *
5201 * Returns 0 on success, negative on failure
5202 **/
5203static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5204{
5205 struct e1000_adapter *adapter = netdev_priv(netdev);
5206 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5207
2adc55c9 5208 /* Jumbo frame support */
2e1706f2
BA		 5209 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5210 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5211 e_err("Jumbo Frames not supported.\n");
5212 return -EINVAL;
bc7f75fa
AK		 5213 }
5214
2adc55c9
BA		 5215 /* Supported frame sizes */
5216 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5217 (max_frame > adapter->max_hw_frame_size)) {
5218 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5219 return -EINVAL;
5220 }
5221
2fbe4526
BA		 5222 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5223 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5224 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5225 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5226 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5227 return -EINVAL;
5228 }
5229
bc7f75fa 5230 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5231 usleep_range(1000, 2000);
610c9928 5232 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5233 adapter->max_frame_size = max_frame;
610c9928
BA		 5234 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5235 netdev->mtu = new_mtu;
bc7f75fa
AK		 5236 if (netif_running(netdev))
5237 e1000e_down(adapter);
5238
e921eb1a 5239 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5240 * means we reserve 2 more, this pushes us to allocate from the next
5241 * larger slab size.
ad68076e 5242 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5243 * However with the new *_jumbo_rx* routines, jumbo receives will use
5244 * fragmented skbs
ad68076e 5245 */
bc7f75fa 5246
9926146b 5247 if (max_frame <= 2048)
bc7f75fa
AK		 5248 adapter->rx_buffer_len = 2048;
5249 else
5250 adapter->rx_buffer_len = 4096;
5251
5252 /* adjust allocation if LPE protects us, and we aren't using SBP */
5253 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5254 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5255 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5256 + ETH_FCS_LEN;
bc7f75fa 5257
bc7f75fa
AK		 5258 if (netif_running(netdev))
5259 e1000e_up(adapter);
5260 else
5261 e1000e_reset(adapter);
5262
5263 clear_bit(__E1000_RESETTING, &adapter->state);
5264
5265 return 0;
5266}
5267
5268static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5269 int cmd)
5270{
5271 struct e1000_adapter *adapter = netdev_priv(netdev);
5272 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5273
318a94d6 5274 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5275 return -EOPNOTSUPP;
5276
5277 switch (cmd) {
5278 case SIOCGMIIPHY:
5279 data->phy_id = adapter->hw.phy.addr;
5280 break;
5281 case SIOCGMIIREG:
b16a002e
BA		 5282 e1000_phy_read_status(adapter);
5283
7c25769f
BA		 5284 switch (data->reg_num & 0x1F) {
5285 case MII_BMCR:
5286 data->val_out = adapter->phy_regs.bmcr;
5287 break;
5288 case MII_BMSR:
5289 data->val_out = adapter->phy_regs.bmsr;
5290 break;
5291 case MII_PHYSID1:
5292 data->val_out = (adapter->hw.phy.id >> 16);
5293 break;
5294 case MII_PHYSID2:
5295 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5296 break;
5297 case MII_ADVERTISE:
5298 data->val_out = adapter->phy_regs.advertise;
5299 break;
5300 case MII_LPA:
5301 data->val_out = adapter->phy_regs.lpa;
5302 break;
5303 case MII_EXPANSION:
5304 data->val_out = adapter->phy_regs.expansion;
5305 break;
5306 case MII_CTRL1000:
5307 data->val_out = adapter->phy_regs.ctrl1000;
5308 break;
5309 case MII_STAT1000:
5310 data->val_out = adapter->phy_regs.stat1000;
5311 break;
5312 case MII_ESTATUS:
5313 data->val_out = adapter->phy_regs.estatus;
5314 break;
5315 default:
bc7f75fa
AK		 5316 return -EIO;
5317 }
bc7f75fa
AK		 5318 break;
5319 case SIOCSMIIREG:
5320 default:
5321 return -EOPNOTSUPP;
5322 }
5323 return 0;
5324}
5325
5326static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5327{
5328 switch (cmd) {
5329 case SIOCGMIIPHY:
5330 case SIOCGMIIREG:
5331 case SIOCSMIIREG:
5332 return e1000_mii_ioctl(netdev, ifr, cmd);
5333 default:
5334 return -EOPNOTSUPP;
5335 }
5336}
5337
a4f58f54
BA		 5338static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5339{
5340 struct e1000_hw *hw = &adapter->hw;
5341 u32 i, mac_reg;
2b6b168d 5342 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5343 int retval = 0;
5344
5345 /* copy MAC RARs to PHY RARs */
d3738bb8 5346 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5347
2b6b168d
BA		 5348 retval = hw->phy.ops.acquire(hw);
5349 if (retval) {
5350 e_err("Could not acquire PHY\n");
5351 return retval;
5352 }
5353
5354 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5355 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5356 if (retval)
75ce1532 5357 goto release;
2b6b168d
BA		 5358
5359 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5360 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5361 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5362 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5363 (u16)(mac_reg & 0xFFFF));
5364 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5365 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5366 }
5367
5368 /* configure PHY Rx Control register */
2b6b168d 5369 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5370 mac_reg = er32(RCTL);
5371 if (mac_reg & E1000_RCTL_UPE)
5372 phy_reg |= BM_RCTL_UPE;
5373 if (mac_reg & E1000_RCTL_MPE)
5374 phy_reg |= BM_RCTL_MPE;
5375 phy_reg &= ~(BM_RCTL_MO_MASK);
5376 if (mac_reg & E1000_RCTL_MO_3)
5377 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5378 << BM_RCTL_MO_SHIFT);
5379 if (mac_reg & E1000_RCTL_BAM)
5380 phy_reg |= BM_RCTL_BAM;
5381 if (mac_reg & E1000_RCTL_PMCF)
5382 phy_reg |= BM_RCTL_PMCF;
5383 mac_reg = er32(CTRL);
5384 if (mac_reg & E1000_CTRL_RFCE)
5385 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5386 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5387
5388 /* enable PHY wakeup in MAC register */
5389 ew32(WUFC, wufc);
5390 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5391
5392 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5393 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5394 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5395
5396 /* activate PHY wakeup */
2b6b168d
BA		 5397 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5398 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5399 if (retval)
5400 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5401release:
94d8186a 5402 hw->phy.ops.release(hw);
a4f58f54
BA		 5403
5404 return retval;
5405}
5406
23606cf5
RW		 5407static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5408 bool runtime)
bc7f75fa
AK		 5409{
5410 struct net_device *netdev = pci_get_drvdata(pdev);
5411 struct e1000_adapter *adapter = netdev_priv(netdev);
5412 struct e1000_hw *hw = &adapter->hw;
5413 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5414 /* Runtime suspend should only enable wakeup for link changes */
5415 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5416 int retval = 0;
5417
5418 netif_device_detach(netdev);
5419
5420 if (netif_running(netdev)) {
bb9e44d0
BA		 5421 int count = E1000_CHECK_RESET_COUNT;
5422
5423 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5424 usleep_range(10000, 20000);
5425
bc7f75fa
AK		 5426 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5427 e1000e_down(adapter);
5428 e1000_free_irq(adapter);
5429 }
4662e82b 5430 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5431
5432 retval = pci_save_state(pdev);
5433 if (retval)
5434 return retval;
5435
5436 status = er32(STATUS);
5437 if (status & E1000_STATUS_LU)
5438 wufc &= ~E1000_WUFC_LNKC;
5439
5440 if (wufc) {
5441 e1000_setup_rctl(adapter);
ef9b965a 5442 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5443
5444 /* turn on all-multi mode if wake on multicast is enabled */
5445 if (wufc & E1000_WUFC_MC) {
5446 rctl = er32(RCTL);
5447 rctl |= E1000_RCTL_MPE;
5448 ew32(RCTL, rctl);
5449 }
5450
5451 ctrl = er32(CTRL);
5452 /* advertise wake from D3Cold */
5453 #define E1000_CTRL_ADVD3WUC 0x00100000
5454 /* phy power management enable */
5455 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5456 ctrl |= E1000_CTRL_ADVD3WUC;
5457 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5458 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5459 ew32(CTRL, ctrl);
5460
318a94d6
JK		 5461 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5462 adapter->hw.phy.media_type ==
5463 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5464 /* keep the laser running in D3 */
5465 ctrl_ext = er32(CTRL_EXT);
93a23f48 5466 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5467 ew32(CTRL_EXT, ctrl_ext);
5468 }
5469
97ac8cae 5470 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5471 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5472
bc7f75fa
AK		 5473 /* Allow time for pending master requests to run */
5474 e1000e_disable_pcie_master(&adapter->hw);
5475
82776a4b 5476 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5477 /* enable wakeup by the PHY */
5478 retval = e1000_init_phy_wakeup(adapter, wufc);
5479 if (retval)
5480 return retval;
5481 } else {
5482 /* enable wakeup by the MAC */
5483 ew32(WUFC, wufc);
5484 ew32(WUC, E1000_WUC_PME_EN);
5485 }
bc7f75fa
AK		 5486 } else {
5487 ew32(WUC, 0);
5488 ew32(WUFC, 0);
bc7f75fa
AK		 5489 }
5490
4f9de721
RW		 5491 *enable_wake = !!wufc;
5492
bc7f75fa 5493 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5494 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5495 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5496 *enable_wake = true;
bc7f75fa
AK		 5497
5498 if (adapter->hw.phy.type == e1000_phy_igp_3)
5499 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5500
e921eb1a 5501 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5502 * would have already happened in close and is redundant.
5503 */
31dbe5b4 5504 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5505
5506 pci_disable_device(pdev);
5507
4f9de721
RW		 5508 return 0;
5509}
5510
5511static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5512{
5513 if (sleep && wake) {
5514 pci_prepare_to_sleep(pdev);
5515 return;
5516 }
5517
5518 pci_wake_from_d3(pdev, wake);
5519 pci_set_power_state(pdev, PCI_D3hot);
5520}
5521
5522static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5523 bool wake)
5524{
5525 struct net_device *netdev = pci_get_drvdata(pdev);
5526 struct e1000_adapter *adapter = netdev_priv(netdev);
5527
e921eb1a 5528 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 5529 * correctable error when the MAC transitions from D0 to D3. To
5530 * prevent this we need to mask off the correctable errors on the
5531 * downstream port of the pci-e switch.
5532 */
5533 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5534 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 5535 u16 devctl;
5536
f8c0fcac
JL		 5537 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
5538 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
5539 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 5540
4f9de721 5541 e1000_power_off(pdev, sleep, wake);
005cbdfc 5542
f8c0fcac 5543 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 5544 } else {
4f9de721 5545 e1000_power_off(pdev, sleep, wake);
005cbdfc 5546 }
bc7f75fa
AK		 5547}
5548
6f461f6c
BA		 5549#ifdef CONFIG_PCIEASPM
5550static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5551{
9f728f53 5552 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5553}
5554#else
5555static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 5556{
e921eb1a 5557 /* Both device and parent should have the same ASPM setting.
6f461f6c 5558 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5559 */
f8c0fcac 5560 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
0c75ba22 5561
f8c0fcac
JL		 5562 if (pdev->bus->self)
5563 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
5564 state);
6f461f6c
BA		 5565}
5566#endif
78cd29d5 5567static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5568{
5569 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5570 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5571 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5572
5573 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5574}
5575
aa338601 5576#ifdef CONFIG_PM
23606cf5 5577static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5578{
23606cf5 5579 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5580}
5581
23606cf5 5582static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5583{
5584 struct net_device *netdev = pci_get_drvdata(pdev);
5585 struct e1000_adapter *adapter = netdev_priv(netdev);
5586 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5587 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5588 u32 err;
5589
78cd29d5
BA		 5590 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5591 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5592 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5593 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5594 if (aspm_disable_flag)
5595 e1000e_disable_aspm(pdev, aspm_disable_flag);
5596
bc7f75fa
AK		 5597 pci_set_power_state(pdev, PCI_D0);
5598 pci_restore_state(pdev);
28b8f04a 5599 pci_save_state(pdev);
6e4f6f6b 5600
4662e82b 5601 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5602 if (netif_running(netdev)) {
5603 err = e1000_request_irq(adapter);
5604 if (err)
5605 return err;
5606 }
5607
2fbe4526 5608 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 5609 e1000_resume_workarounds_pchlan(&adapter->hw);
5610
bc7f75fa 5611 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5612
5613 /* report the system wakeup cause from S3/S4 */
5614 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5615 u16 phy_data;
5616
5617 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5618 if (phy_data) {
5619 e_info("PHY Wakeup cause - %s\n",
5620 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5621 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5622 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5623 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5624 phy_data & E1000_WUS_LNKC ?
5625 "Link Status Change" : "other");
a4f58f54
BA		 5626 }
5627 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5628 } else {
5629 u32 wus = er32(WUS);
5630 if (wus) {
5631 e_info("MAC Wakeup cause - %s\n",
5632 wus & E1000_WUS_EX ? "Unicast Packet" :
5633 wus & E1000_WUS_MC ? "Multicast Packet" :
5634 wus & E1000_WUS_BC ? "Broadcast Packet" :
5635 wus & E1000_WUS_MAG ? "Magic Packet" :
5636 wus & E1000_WUS_LNKC ? "Link Status Change" :
5637 "other");
5638 }
5639 ew32(WUS, ~0);
5640 }
5641
bc7f75fa 5642 e1000e_reset(adapter);
bc7f75fa 5643
cd791618 5644 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5645
5646 if (netif_running(netdev))
5647 e1000e_up(adapter);
5648
5649 netif_device_attach(netdev);
5650
e921eb1a 5651 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5652 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5653 * under the control of the driver.
5654 */
c43bc57e 5655 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5656 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5657
5658 return 0;
5659}
23606cf5 5660
a0340162
RW		 5661#ifdef CONFIG_PM_SLEEP
5662static int e1000_suspend(struct device *dev)
5663{
5664 struct pci_dev *pdev = to_pci_dev(dev);
5665 int retval;
5666 bool wake;
5667
5668 retval = __e1000_shutdown(pdev, &wake, false);
5669 if (!retval)
5670 e1000_complete_shutdown(pdev, true, wake);
5671
5672 return retval;
5673}
5674
23606cf5
RW		 5675static int e1000_resume(struct device *dev)
5676{
5677 struct pci_dev *pdev = to_pci_dev(dev);
5678 struct net_device *netdev = pci_get_drvdata(pdev);
5679 struct e1000_adapter *adapter = netdev_priv(netdev);
5680
5681 if (e1000e_pm_ready(adapter))
5682 adapter->idle_check = true;
5683
5684 return __e1000_resume(pdev);
5685}
a0340162
RW		 5686#endif /* CONFIG_PM_SLEEP */
5687
5688#ifdef CONFIG_PM_RUNTIME
5689static int e1000_runtime_suspend(struct device *dev)
5690{
5691 struct pci_dev *pdev = to_pci_dev(dev);
5692 struct net_device *netdev = pci_get_drvdata(pdev);
5693 struct e1000_adapter *adapter = netdev_priv(netdev);
5694
5695 if (e1000e_pm_ready(adapter)) {
5696 bool wake;
5697
5698 __e1000_shutdown(pdev, &wake, true);
5699 }
5700
5701 return 0;
5702}
5703
5704static int e1000_idle(struct device *dev)
5705{
5706 struct pci_dev *pdev = to_pci_dev(dev);
5707 struct net_device *netdev = pci_get_drvdata(pdev);
5708 struct e1000_adapter *adapter = netdev_priv(netdev);
5709
5710 if (!e1000e_pm_ready(adapter))
5711 return 0;
5712
5713 if (adapter->idle_check) {
5714 adapter->idle_check = false;
5715 if (!e1000e_has_link(adapter))
5716 pm_schedule_suspend(dev, MSEC_PER_SEC);
5717 }
5718
5719 return -EBUSY;
5720}
23606cf5
RW		 5721
5722static int e1000_runtime_resume(struct device *dev)
5723{
5724 struct pci_dev *pdev = to_pci_dev(dev);
5725 struct net_device *netdev = pci_get_drvdata(pdev);
5726 struct e1000_adapter *adapter = netdev_priv(netdev);
5727
5728 if (!e1000e_pm_ready(adapter))
5729 return 0;
5730
5731 adapter->idle_check = !dev->power.runtime_auto;
5732 return __e1000_resume(pdev);
5733}
a0340162 5734#endif /* CONFIG_PM_RUNTIME */
aa338601 5735#endif /* CONFIG_PM */
bc7f75fa
AK		 5736
5737static void e1000_shutdown(struct pci_dev *pdev)
5738{
4f9de721
RW		 5739 bool wake = false;
5740
23606cf5 5741 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5742
5743 if (system_state == SYSTEM_POWER_OFF)
5744 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5745}
5746
5747#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5748
5749static irqreturn_t e1000_intr_msix(int irq, void *data)
5750{
5751 struct net_device *netdev = data;
5752 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5753
5754 if (adapter->msix_entries) {
90da0669
BA		 5755 int vector, msix_irq;
5756
147b2c8c
DD		 5757 vector = 0;
5758 msix_irq = adapter->msix_entries[vector].vector;
5759 disable_irq(msix_irq);
5760 e1000_intr_msix_rx(msix_irq, netdev);
5761 enable_irq(msix_irq);
5762
5763 vector++;
5764 msix_irq = adapter->msix_entries[vector].vector;
5765 disable_irq(msix_irq);
5766 e1000_intr_msix_tx(msix_irq, netdev);
5767 enable_irq(msix_irq);
5768
5769 vector++;
5770 msix_irq = adapter->msix_entries[vector].vector;
5771 disable_irq(msix_irq);
5772 e1000_msix_other(msix_irq, netdev);
5773 enable_irq(msix_irq);
5774 }
5775
5776 return IRQ_HANDLED;
5777}
5778
e921eb1a
BA		 5779/**
5780 * e1000_netpoll
5781 * @netdev: network interface device structure
5782 *
bc7f75fa
AK		 5783 * Polling 'interrupt' - used by things like netconsole to send skbs
5784 * without having to re-enable interrupts. It's not called while
5785 * the interrupt routine is executing.
5786 */
5787static void e1000_netpoll(struct net_device *netdev)
5788{
5789 struct e1000_adapter *adapter = netdev_priv(netdev);
5790
147b2c8c
DD		 5791 switch (adapter->int_mode) {
5792 case E1000E_INT_MODE_MSIX:
5793 e1000_intr_msix(adapter->pdev->irq, netdev);
5794 break;
5795 case E1000E_INT_MODE_MSI:
5796 disable_irq(adapter->pdev->irq);
5797 e1000_intr_msi(adapter->pdev->irq, netdev);
5798 enable_irq(adapter->pdev->irq);
5799 break;
5800 default: /* E1000E_INT_MODE_LEGACY */
5801 disable_irq(adapter->pdev->irq);
5802 e1000_intr(adapter->pdev->irq, netdev);
5803 enable_irq(adapter->pdev->irq);
5804 break;
5805 }
bc7f75fa
AK		 5806}
5807#endif
5808
5809/**
5810 * e1000_io_error_detected - called when PCI error is detected
5811 * @pdev: Pointer to PCI device
5812 * @state: The current pci connection state
5813 *
5814 * This function is called after a PCI bus error affecting
5815 * this device has been detected.
5816 */
5817static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5818 pci_channel_state_t state)
5819{
5820 struct net_device *netdev = pci_get_drvdata(pdev);
5821 struct e1000_adapter *adapter = netdev_priv(netdev);
5822
5823 netif_device_detach(netdev);
5824
c93b5a76
MM		 5825 if (state == pci_channel_io_perm_failure)
5826 return PCI_ERS_RESULT_DISCONNECT;
5827
bc7f75fa
AK		 5828 if (netif_running(netdev))
5829 e1000e_down(adapter);
5830 pci_disable_device(pdev);
5831
5832 /* Request a slot slot reset. */
5833 return PCI_ERS_RESULT_NEED_RESET;
5834}
5835
5836/**
5837 * e1000_io_slot_reset - called after the pci bus has been reset.
5838 * @pdev: Pointer to PCI device
5839 *
5840 * Restart the card from scratch, as if from a cold-boot. Implementation
5841 * resembles the first-half of the e1000_resume routine.
5842 */
5843static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5844{
5845 struct net_device *netdev = pci_get_drvdata(pdev);
5846 struct e1000_adapter *adapter = netdev_priv(netdev);
5847 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5848 u16 aspm_disable_flag = 0;
6e4f6f6b 5849 int err;
111b9dc5 5850 pci_ers_result_t result;
bc7f75fa 5851
78cd29d5
BA		 5852 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5853 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5854 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5855 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5856 if (aspm_disable_flag)
5857 e1000e_disable_aspm(pdev, aspm_disable_flag);
5858
f0f422e5 5859 err = pci_enable_device_mem(pdev);
6e4f6f6b 5860 if (err) {
bc7f75fa
AK		 5861 dev_err(&pdev->dev,
5862 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5863 result = PCI_ERS_RESULT_DISCONNECT;
5864 } else {
5865 pci_set_master(pdev);
23606cf5 5866 pdev->state_saved = true;
111b9dc5 5867 pci_restore_state(pdev);
bc7f75fa 5868
111b9dc5
JB		 5869 pci_enable_wake(pdev, PCI_D3hot, 0);
5870 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5871
111b9dc5
JB		 5872 e1000e_reset(adapter);
5873 ew32(WUS, ~0);
5874 result = PCI_ERS_RESULT_RECOVERED;
5875 }
bc7f75fa 5876
111b9dc5
JB		 5877 pci_cleanup_aer_uncorrect_error_status(pdev);
5878
5879 return result;
bc7f75fa
AK		 5880}
5881
5882/**
5883 * e1000_io_resume - called when traffic can start flowing again.
5884 * @pdev: Pointer to PCI device
5885 *
5886 * This callback is called when the error recovery driver tells us that
5887 * its OK to resume normal operation. Implementation resembles the
5888 * second-half of the e1000_resume routine.
5889 */
5890static void e1000_io_resume(struct pci_dev *pdev)
5891{
5892 struct net_device *netdev = pci_get_drvdata(pdev);
5893 struct e1000_adapter *adapter = netdev_priv(netdev);
5894
cd791618 5895 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5896
5897 if (netif_running(netdev)) {
5898 if (e1000e_up(adapter)) {
5899 dev_err(&pdev->dev,
5900 "can't bring device back up after reset\n");
5901 return;
5902 }
5903 }
5904
5905 netif_device_attach(netdev);
5906
e921eb1a 5907 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5908 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5909 * under the control of the driver.
5910 */
c43bc57e 5911 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5912 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5913
5914}
5915
5916static void e1000_print_device_info(struct e1000_adapter *adapter)
5917{
5918 struct e1000_hw *hw = &adapter->hw;
5919 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5920 u32 ret_val;
5921 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5922
5923 /* print bus type/speed/width info */
a5cc7642 5924 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5925 /* bus width */
5926 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5927 "Width x1"),
5928 /* MAC address */
7c510e4b 5929 netdev->dev_addr);
44defeb3
JK		 5930 e_info("Intel(R) PRO/%s Network Connection\n",
5931 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5932 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5933 E1000_PBANUM_LENGTH);
5934 if (ret_val)
f2315bf1 5935 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 5936 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5937 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5938}
5939
10aa4c04
AK		 5940static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5941{
5942 struct e1000_hw *hw = &adapter->hw;
5943 int ret_val;
5944 u16 buf = 0;
5945
5946 if (hw->mac.type != e1000_82573)
5947 return;
5948
5949 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 5950 le16_to_cpus(&buf);
5951 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 5952 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 5953 dev_warn(&adapter->pdev->dev,
5954 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 5955 }
10aa4c04
AK		 5956}
5957
c8f44aff 5958static int e1000_set_features(struct net_device *netdev,
70495a50 5959 netdev_features_t features)
dc221294
BA		 5960{
5961 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 5962 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 5963
5964 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
5965 adapter->flags |= FLAG_TSO_FORCE;
5966
5967 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 5968 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
5969 NETIF_F_RXALL)))
dc221294
BA		 5970 return 0;
5971
0184039a
BG		 5972 if (changed & NETIF_F_RXFCS) {
5973 if (features & NETIF_F_RXFCS) {
5974 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
5975 } else {
5976 /* We need to take it back to defaults, which might mean
5977 * stripping is still disabled at the adapter level.
5978 */
5979 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
5980 adapter->flags2 |= FLAG2_CRC_STRIPPING;
5981 else
5982 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
5983 }
5984 }
5985
70495a50
BA		 5986 netdev->features = features;
5987
dc221294
BA		 5988 if (netif_running(netdev))
5989 e1000e_reinit_locked(adapter);
5990 else
5991 e1000e_reset(adapter);
5992
5993 return 0;
5994}
5995
651c2466
SH		 5996static const struct net_device_ops e1000e_netdev_ops = {
5997 .ndo_open = e1000_open,
5998 .ndo_stop = e1000_close,
00829823 5999 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6000 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6001 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6002 .ndo_set_mac_address = e1000_set_mac,
6003 .ndo_change_mtu = e1000_change_mtu,
6004 .ndo_do_ioctl = e1000_ioctl,
6005 .ndo_tx_timeout = e1000_tx_timeout,
6006 .ndo_validate_addr = eth_validate_addr,
6007
651c2466
SH		 6008 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6009 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6010#ifdef CONFIG_NET_POLL_CONTROLLER
6011 .ndo_poll_controller = e1000_netpoll,
6012#endif
dc221294 6013 .ndo_set_features = e1000_set_features,
651c2466
SH		 6014};
6015
bc7f75fa
AK		 6016/**
6017 * e1000_probe - Device Initialization Routine
6018 * @pdev: PCI device information struct
6019 * @ent: entry in e1000_pci_tbl
6020 *
6021 * Returns 0 on success, negative on failure
6022 *
6023 * e1000_probe initializes an adapter identified by a pci_dev structure.
6024 * The OS initialization, configuring of the adapter private structure,
6025 * and a hardware reset occur.
6026 **/
1dd06ae8 6027static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6028{
6029 struct net_device *netdev;
6030 struct e1000_adapter *adapter;
6031 struct e1000_hw *hw;
6032 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6033 resource_size_t mmio_start, mmio_len;
6034 resource_size_t flash_start, flash_len;
bc7f75fa 6035 static int cards_found;
78cd29d5 6036 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6037 int i, err, pci_using_dac;
6038 u16 eeprom_data = 0;
6039 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6040
78cd29d5
BA		 6041 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6042 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6043 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6044 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6045 if (aspm_disable_flag)
6046 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6047
f0f422e5 6048 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6049 if (err)
6050 return err;
6051
6052 pci_using_dac = 0;
0be3f55f 6053 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6054 if (!err) {
0be3f55f 6055 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6056 if (!err)
6057 pci_using_dac = 1;
6058 } else {
0be3f55f 6059 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6060 if (err) {
0be3f55f
NN		 6061 err = dma_set_coherent_mask(&pdev->dev,
6062 DMA_BIT_MASK(32));
bc7f75fa 6063 if (err) {
ef456f85 6064 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6065 goto err_dma;
6066 }
6067 }
6068 }
6069
e8de1481 6070 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6071 pci_select_bars(pdev, IORESOURCE_MEM),
6072 e1000e_driver_name);
bc7f75fa
AK		 6073 if (err)
6074 goto err_pci_reg;
6075
68eac460 6076 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6077 pci_enable_pcie_error_reporting(pdev);
68eac460 6078
bc7f75fa 6079 pci_set_master(pdev);
438b365a
BA		 6080 /* PCI config space info */
6081 err = pci_save_state(pdev);
6082 if (err)
6083 goto err_alloc_etherdev;
bc7f75fa
AK		 6084
6085 err = -ENOMEM;
6086 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6087 if (!netdev)
6088 goto err_alloc_etherdev;
6089
bc7f75fa
AK		 6090 SET_NETDEV_DEV(netdev, &pdev->dev);
6091
f85e4dfa
TH		 6092 netdev->irq = pdev->irq;
6093
bc7f75fa
AK		 6094 pci_set_drvdata(pdev, netdev);
6095 adapter = netdev_priv(netdev);
6096 hw = &adapter->hw;
6097 adapter->netdev = netdev;
6098 adapter->pdev = pdev;
6099 adapter->ei = ei;
6100 adapter->pba = ei->pba;
6101 adapter->flags = ei->flags;
eb7c3adb 6102 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6103 adapter->hw.adapter = adapter;
6104 adapter->hw.mac.type = ei->mac;
2adc55c9 6105 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6106 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6107
6108 mmio_start = pci_resource_start(pdev, 0);
6109 mmio_len = pci_resource_len(pdev, 0);
6110
6111 err = -EIO;
6112 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6113 if (!adapter->hw.hw_addr)
6114 goto err_ioremap;
6115
6116 if ((adapter->flags & FLAG_HAS_FLASH) &&
6117 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6118 flash_start = pci_resource_start(pdev, 1);
6119 flash_len = pci_resource_len(pdev, 1);
6120 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6121 if (!adapter->hw.flash_address)
6122 goto err_flashmap;
6123 }
6124
6125 /* construct the net_device struct */
651c2466 6126 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6127 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6128 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6129 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6130 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6131
6132 netdev->mem_start = mmio_start;
6133 netdev->mem_end = mmio_start + mmio_len;
6134
6135 adapter->bd_number = cards_found++;
6136
4662e82b
BA		 6137 e1000e_check_options(adapter);
6138
bc7f75fa
AK		 6139 /* setup adapter struct */
6140 err = e1000_sw_init(adapter);
6141 if (err)
6142 goto err_sw_init;
6143
bc7f75fa
AK		 6144 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6145 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6146 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6147
69e3fd8c 6148 err = ei->get_variants(adapter);
bc7f75fa
AK		 6149 if (err)
6150 goto err_hw_init;
6151
4a770358
BA		 6152 if ((adapter->flags & FLAG_IS_ICH) &&
6153 (adapter->flags & FLAG_READ_ONLY_NVM))
6154 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6155
bc7f75fa
AK		 6156 hw->mac.ops.get_bus_info(&adapter->hw);
6157
318a94d6 6158 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6159
6160 /* Copper options */
318a94d6 6161 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6162 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6163 adapter->hw.phy.disable_polarity_correction = 0;
6164 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6165 }
6166
470a5420 6167 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6168 dev_info(&pdev->dev,
6169 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6170
dc221294
BA		 6171 /* Set initial default active device features */
6172 netdev->features = (NETIF_F_SG |
6173 NETIF_F_HW_VLAN_RX |
6174 NETIF_F_HW_VLAN_TX |
6175 NETIF_F_TSO |
6176 NETIF_F_TSO6 |
70495a50 6177 NETIF_F_RXHASH |
dc221294
BA		 6178 NETIF_F_RXCSUM |
6179 NETIF_F_HW_CSUM);
6180
6181 /* Set user-changeable features (subset of all device features) */
6182 netdev->hw_features = netdev->features;
0184039a 6183 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6184 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6185 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6186
6187 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6188 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6189
dc221294
BA		 6190 netdev->vlan_features |= (NETIF_F_SG |
6191 NETIF_F_TSO |
6192 NETIF_F_TSO6 |
6193 NETIF_F_HW_CSUM);
a5136e23 6194
ef9b965a
JB		 6195 netdev->priv_flags |= IFF_UNICAST_FLT;
6196
7b872a55 6197 if (pci_using_dac) {
bc7f75fa 6198 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6199 netdev->vlan_features |= NETIF_F_HIGHDMA;
6200 }
bc7f75fa 6201
bc7f75fa
AK		 6202 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6203 adapter->flags |= FLAG_MNG_PT_ENABLED;
6204
e921eb1a 6205 /* before reading the NVM, reset the controller to
ad68076e
BA		 6206 * put the device in a known good starting state
6207 */
bc7f75fa
AK		 6208 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6209
e921eb1a 6210 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6211 * attempt. Let's give it a few tries
6212 */
6213 for (i = 0;; i++) {
6214 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6215 break;
6216 if (i == 2) {
185095fb 6217 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6218 err = -EIO;
6219 goto err_eeprom;
6220 }
6221 }
6222
10aa4c04
AK		 6223 e1000_eeprom_checks(adapter);
6224
608f8a0d 6225 /* copy the MAC address */
bc7f75fa 6226 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6227 dev_err(&pdev->dev,
6228 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6229
6230 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6231 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6232
6233 if (!is_valid_ether_addr(netdev->perm_addr)) {
185095fb
BA		 6234 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
6235 netdev->perm_addr);
bc7f75fa
AK		 6236 err = -EIO;
6237 goto err_eeprom;
6238 }
6239
6240 init_timer(&adapter->watchdog_timer);
c061b18d 6241 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6242 adapter->watchdog_timer.data = (unsigned long) adapter;
6243
6244 init_timer(&adapter->phy_info_timer);
c061b18d 6245 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6246 adapter->phy_info_timer.data = (unsigned long) adapter;
6247
6248 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6249 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6250 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6251 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6252 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6253
bc7f75fa
AK		 6254 /* Initialize link parameters. User can change them with ethtool */
6255 adapter->hw.mac.autoneg = 1;
3db1cd5c 6256 adapter->fc_autoneg = true;
5c48ef3e
BA		 6257 adapter->hw.fc.requested_mode = e1000_fc_default;
6258 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6259 adapter->hw.phy.autoneg_advertised = 0x2f;
6260
6261 /* ring size defaults */
d821a4c4
BA		 6262 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6263 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6264
e921eb1a 6265 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6266 * the EEPROM, enable the ACPI Magic Packet filter
6267 */
6268 if (adapter->flags & FLAG_APME_IN_WUC) {
6269 /* APME bit in EEPROM is mapped to WUC.APME */
6270 eeprom_data = er32(WUC);
6271 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6272 if ((hw->mac.type > e1000_ich10lan) &&
6273 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6274 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6275 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6276 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6277 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6278 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6279 1, &eeprom_data);
bc7f75fa 6280 else
3d3a1676
BA		 6281 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6282 1, &eeprom_data);
bc7f75fa
AK		 6283 }
6284
6285 /* fetch WoL from EEPROM */
6286 if (eeprom_data & eeprom_apme_mask)
6287 adapter->eeprom_wol |= E1000_WUFC_MAG;
6288
e921eb1a 6289 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6290 * where the eeprom may be wrong or the board simply won't support
6291 * wake on lan on a particular port
6292 */
6293 if (!(adapter->flags & FLAG_HAS_WOL))
6294 adapter->eeprom_wol = 0;
6295
6296 /* initialize the wol settings based on the eeprom settings */
6297 adapter->wol = adapter->eeprom_wol;
6ff68026 6298 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6299
84527590
BA		 6300 /* save off EEPROM version number */
6301 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6302
bc7f75fa
AK		 6303 /* reset the hardware with the new settings */
6304 e1000e_reset(adapter);
6305
e921eb1a 6306 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6307 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6308 * under the control of the driver.
6309 */
c43bc57e 6310 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6311 e1000e_get_hw_control(adapter);
bc7f75fa 6312
f2315bf1 6313 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6314 err = register_netdev(netdev);
6315 if (err)
6316 goto err_register;
6317
9c563d20
JB		 6318 /* carrier off reporting is important to ethtool even BEFORE open */
6319 netif_carrier_off(netdev);
6320
bc7f75fa
AK		 6321 e1000_print_device_info(adapter);
6322
f3ec4f87
AS		 6323 if (pci_dev_run_wake(pdev))
6324 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6325
bc7f75fa
AK		 6326 return 0;
6327
6328err_register:
c43bc57e 6329 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6330 e1000e_release_hw_control(adapter);
bc7f75fa 6331err_eeprom:
470a5420 6332 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6333 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6334err_hw_init:
bc7f75fa
AK		 6335 kfree(adapter->tx_ring);
6336 kfree(adapter->rx_ring);
6337err_sw_init:
c43bc57e
JB		 6338 if (adapter->hw.flash_address)
6339 iounmap(adapter->hw.flash_address);
e82f54ba 6340 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6341err_flashmap:
bc7f75fa
AK		 6342 iounmap(adapter->hw.hw_addr);
6343err_ioremap:
6344 free_netdev(netdev);
6345err_alloc_etherdev:
f0f422e5
BA		 6346 pci_release_selected_regions(pdev,
6347 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6348err_pci_reg:
6349err_dma:
6350 pci_disable_device(pdev);
6351 return err;
6352}
6353
6354/**
6355 * e1000_remove - Device Removal Routine
6356 * @pdev: PCI device information struct
6357 *
6358 * e1000_remove is called by the PCI subsystem to alert the driver
6359 * that it should release a PCI device. The could be caused by a
6360 * Hot-Plug event, or because the driver is going to be removed from
6361 * memory.
6362 **/
9f9a12f8 6363static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6364{
6365 struct net_device *netdev = pci_get_drvdata(pdev);
6366 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6367 bool down = test_bit(__E1000_DOWN, &adapter->state);
6368
e921eb1a 6369 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6370 * from being rescheduled.
ad68076e 6371 */
23606cf5
RW		 6372 if (!down)
6373 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6374 del_timer_sync(&adapter->watchdog_timer);
6375 del_timer_sync(&adapter->phy_info_timer);
6376
41cec6f1
BA		 6377 cancel_work_sync(&adapter->reset_task);
6378 cancel_work_sync(&adapter->watchdog_task);
6379 cancel_work_sync(&adapter->downshift_task);
6380 cancel_work_sync(&adapter->update_phy_task);
6381 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6382
17f208de
BA		 6383 if (!(netdev->flags & IFF_UP))
6384 e1000_power_down_phy(adapter);
6385
23606cf5
RW		 6386 /* Don't lie to e1000_close() down the road. */
6387 if (!down)
6388 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6389 unregister_netdev(netdev);
6390
f3ec4f87
AS		 6391 if (pci_dev_run_wake(pdev))
6392 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6393
e921eb1a 6394 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6395 * would have already happened in close and is redundant.
6396 */
31dbe5b4 6397 e1000e_release_hw_control(adapter);
bc7f75fa 6398
4662e82b 6399 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6400 kfree(adapter->tx_ring);
6401 kfree(adapter->rx_ring);
6402
6403 iounmap(adapter->hw.hw_addr);
6404 if (adapter->hw.flash_address)
6405 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6406 pci_release_selected_regions(pdev,
6407 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6408
6409 free_netdev(netdev);
6410
111b9dc5 6411 /* AER disable */
19d5afd4 6412 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6413
bc7f75fa
AK		 6414 pci_disable_device(pdev);
6415}
6416
6417/* PCI Error Recovery (ERS) */
3646f0e5 6418static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6419 .error_detected = e1000_io_error_detected,
6420 .slot_reset = e1000_io_slot_reset,
6421 .resume = e1000_io_resume,
6422};
6423
a3aa1884 6424static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6427 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6428 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6429 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6430 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6431 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6432 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6433 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6434
bc7f75fa
AK		 6435 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6436 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6437 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6439
bc7f75fa
AK		 6440 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6442 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6443
4662e82b 6444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6447
bc7f75fa
AK		 6448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6449 board_80003es2lan },
6450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6451 board_80003es2lan },
6452 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6453 board_80003es2lan },
6454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6455 board_80003es2lan },
ad68076e 6456
bc7f75fa
AK		 6457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6458 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6459 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6462 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6464 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6465
bc7f75fa
AK		 6466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6468 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6472 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6475
6476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6479
f4187b56
BA		 6480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6483
a4f58f54
BA		 6484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6488
d3738bb8
BA		 6489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6491
2fbe4526
BA		 6492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 6494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 6496
f36bb6ca 6497 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6498};
6499MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6500
aa338601 6501#ifdef CONFIG_PM
23606cf5 6502static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6503 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6504 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6505 e1000_runtime_resume, e1000_idle)
23606cf5 6506};
e50208a0 6507#endif
23606cf5 6508
bc7f75fa
AK		 6509/* PCI Device API Driver */
6510static struct pci_driver e1000_driver = {
6511 .name = e1000e_driver_name,
6512 .id_table = e1000_pci_tbl,
6513 .probe = e1000_probe,
9f9a12f8 6514 .remove = e1000_remove,
aa338601 6515#ifdef CONFIG_PM
f36bb6ca
BA		 6516 .driver = {
6517 .pm = &e1000_pm_ops,
6518 },
bc7f75fa
AK		 6519#endif
6520 .shutdown = e1000_shutdown,
6521 .err_handler = &e1000_err_handler
6522};
6523
6524/**
6525 * e1000_init_module - Driver Registration Routine
6526 *
6527 * e1000_init_module is the first routine called when the driver is
6528 * loaded. All it does is register with the PCI subsystem.
6529 **/
6530static int __init e1000_init_module(void)
6531{
6532 int ret;
8544b9f7
BA		 6533 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6534 e1000e_driver_version);
f5e261e6 6535 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6536 ret = pci_register_driver(&e1000_driver);
53ec5498 6537
bc7f75fa
AK		 6538 return ret;
6539}
6540module_init(e1000_init_module);
6541
6542/**
6543 * e1000_exit_module - Driver Exit Cleanup Routine
6544 *
6545 * e1000_exit_module is called just before the driver is removed
6546 * from memory.
6547 **/
6548static void __exit e1000_exit_module(void)
6549{
6550 pci_unregister_driver(&e1000_driver);
6551}
6552module_exit(e1000_exit_module);
6553
6554
6555MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6556MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6557MODULE_LICENSE("GPL");
6558MODULE_VERSION(DRV_VERSION);
6559
06c24b91 6560/* netdev.c */
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