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PCI: Make pci_error_handlers const
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
a61d3d14 59#define DRV_VERSION "2.0.0" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 82 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 83};
84
84f4ee90
TI		 85struct e1000_reg_info {
86 u32 ofs;
87 char *name;
88};
89
af667a29
BA		 90#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
91#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
92#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
93#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
94#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
95
96#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
97#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
98#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
99#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
100#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 101
102static const struct e1000_reg_info e1000_reg_info_tbl[] = {
103
104 /* General Registers */
105 {E1000_CTRL, "CTRL"},
106 {E1000_STATUS, "STATUS"},
107 {E1000_CTRL_EXT, "CTRL_EXT"},
108
109 /* Interrupt Registers */
110 {E1000_ICR, "ICR"},
111
af667a29 112 /* Rx Registers */
84f4ee90 113 {E1000_RCTL, "RCTL"},
1e36052e
BA		 114 {E1000_RDLEN(0), "RDLEN"},
115 {E1000_RDH(0), "RDH"},
116 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 117 {E1000_RDTR, "RDTR"},
118 {E1000_RXDCTL(0), "RXDCTL"},
119 {E1000_ERT, "ERT"},
1e36052e
BA		 120 {E1000_RDBAL(0), "RDBAL"},
121 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 122 {E1000_RDFH, "RDFH"},
123 {E1000_RDFT, "RDFT"},
124 {E1000_RDFHS, "RDFHS"},
125 {E1000_RDFTS, "RDFTS"},
126 {E1000_RDFPC, "RDFPC"},
127
af667a29 128 /* Tx Registers */
84f4ee90 129 {E1000_TCTL, "TCTL"},
1e36052e
BA		 130 {E1000_TDBAL(0), "TDBAL"},
131 {E1000_TDBAH(0), "TDBAH"},
132 {E1000_TDLEN(0), "TDLEN"},
133 {E1000_TDH(0), "TDH"},
134 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 135 {E1000_TIDV, "TIDV"},
136 {E1000_TXDCTL(0), "TXDCTL"},
137 {E1000_TADV, "TADV"},
138 {E1000_TARC(0), "TARC"},
139 {E1000_TDFH, "TDFH"},
140 {E1000_TDFT, "TDFT"},
141 {E1000_TDFHS, "TDFHS"},
142 {E1000_TDFTS, "TDFTS"},
143 {E1000_TDFPC, "TDFPC"},
144
145 /* List Terminator */
f36bb6ca 146 {0, NULL}
84f4ee90
TI		 147};
148
149/*
150 * e1000_regdump - register printout routine
151 */
152static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
153{
154 int n = 0;
155 char rname[16];
156 u32 regs[8];
157
158 switch (reginfo->ofs) {
159 case E1000_RXDCTL(0):
160 for (n = 0; n < 2; n++)
161 regs[n] = __er32(hw, E1000_RXDCTL(n));
162 break;
163 case E1000_TXDCTL(0):
164 for (n = 0; n < 2; n++)
165 regs[n] = __er32(hw, E1000_TXDCTL(n));
166 break;
167 case E1000_TARC(0):
168 for (n = 0; n < 2; n++)
169 regs[n] = __er32(hw, E1000_TARC(n));
170 break;
171 default:
ef456f85
JK		 172 pr_info("%-15s %08x\n",
173 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 174 return;
175 }
176
177 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 178 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 179}
180
84f4ee90 181/*
af667a29 182 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 183 */
184static void e1000e_dump(struct e1000_adapter *adapter)
185{
186 struct net_device *netdev = adapter->netdev;
187 struct e1000_hw *hw = &adapter->hw;
188 struct e1000_reg_info *reginfo;
189 struct e1000_ring *tx_ring = adapter->tx_ring;
190 struct e1000_tx_desc *tx_desc;
af667a29 191 struct my_u0 {
e885d762
BA		 192 __le64 a;
193 __le64 b;
af667a29 194 } *u0;
84f4ee90
TI		 195 struct e1000_buffer *buffer_info;
196 struct e1000_ring *rx_ring = adapter->rx_ring;
197 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 198 union e1000_rx_desc_extended *rx_desc;
af667a29 199 struct my_u1 {
e885d762
BA		 200 __le64 a;
201 __le64 b;
202 __le64 c;
203 __le64 d;
af667a29 204 } *u1;
84f4ee90
TI		 205 u32 staterr;
206 int i = 0;
207
208 if (!netif_msg_hw(adapter))
209 return;
210
211 /* Print netdevice Info */
212 if (netdev) {
213 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 214 pr_info("Device Name state trans_start last_rx\n");
215 pr_info("%-15s %016lX %016lX %016lX\n",
216 netdev->name, netdev->state, netdev->trans_start,
217 netdev->last_rx);
84f4ee90
TI		 218 }
219
220 /* Print Registers */
221 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 222 pr_info(" Register Name Value\n");
84f4ee90
TI		 223 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
224 reginfo->name; reginfo++) {
225 e1000_regdump(hw, reginfo);
226 }
227
af667a29 228 /* Print Tx Ring Summary */
84f4ee90 229 if (!netdev || !netif_running(netdev))
fe1e980f 230 return;
84f4ee90 231
af667a29 232 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 233 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 234 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 235 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
236 0, tx_ring->next_to_use, tx_ring->next_to_clean,
237 (unsigned long long)buffer_info->dma,
238 buffer_info->length,
239 buffer_info->next_to_watch,
240 (unsigned long long)buffer_info->time_stamp);
84f4ee90 241
af667a29 242 /* Print Tx Ring */
84f4ee90
TI		 243 if (!netif_msg_tx_done(adapter))
244 goto rx_ring_summary;
245
af667a29 246 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 247
248 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
249 *
250 * Legacy Transmit Descriptor
251 * +--------------------------------------------------------------+
252 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
253 * +--------------------------------------------------------------+
254 * 8 | Special | CSS | Status | CMD | CSO | Length |
255 * +--------------------------------------------------------------+
256 * 63 48 47 36 35 32 31 24 23 16 15 0
257 *
258 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
259 * 63 48 47 40 39 32 31 16 15 8 7 0
260 * +----------------------------------------------------------------+
261 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
262 * +----------------------------------------------------------------+
263 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
264 * +----------------------------------------------------------------+
265 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
266 *
267 * Extended Data Descriptor (DTYP=0x1)
268 * +----------------------------------------------------------------+
269 * 0 | Buffer Address [63:0] |
270 * +----------------------------------------------------------------+
271 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
272 * +----------------------------------------------------------------+
273 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
274 */
ef456f85
JK		 275 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
276 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
277 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 278 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 279 const char *next_desc;
84f4ee90
TI		 280 tx_desc = E1000_TX_DESC(*tx_ring, i);
281 buffer_info = &tx_ring->buffer_info[i];
282 u0 = (struct my_u0 *)tx_desc;
84f4ee90 283 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 284 next_desc = " NTC/U";
84f4ee90 285 else if (i == tx_ring->next_to_use)
ef456f85 286 next_desc = " NTU";
84f4ee90 287 else if (i == tx_ring->next_to_clean)
ef456f85 288 next_desc = " NTC";
84f4ee90 289 else
ef456f85
JK		 290 next_desc = "";
291 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
292 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
293 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
294 i,
295 (unsigned long long)le64_to_cpu(u0->a),
296 (unsigned long long)le64_to_cpu(u0->b),
297 (unsigned long long)buffer_info->dma,
298 buffer_info->length, buffer_info->next_to_watch,
299 (unsigned long long)buffer_info->time_stamp,
300 buffer_info->skb, next_desc);
84f4ee90
TI		 301
302 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
303 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 304 16, 1, phys_to_virt(buffer_info->dma),
305 buffer_info->length, true);
84f4ee90
TI		 306 }
307
af667a29 308 /* Print Rx Ring Summary */
84f4ee90 309rx_ring_summary:
af667a29 310 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 311 pr_info("Queue [NTU] [NTC]\n");
312 pr_info(" %5d %5X %5X\n",
313 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 314
af667a29 315 /* Print Rx Ring */
84f4ee90 316 if (!netif_msg_rx_status(adapter))
fe1e980f 317 return;
84f4ee90 318
af667a29 319 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 320 switch (adapter->rx_ps_pages) {
321 case 1:
322 case 2:
323 case 3:
324 /* [Extended] Packet Split Receive Descriptor Format
325 *
326 * +-----------------------------------------------------+
327 * 0 | Buffer Address 0 [63:0] |
328 * +-----------------------------------------------------+
329 * 8 | Buffer Address 1 [63:0] |
330 * +-----------------------------------------------------+
331 * 16 | Buffer Address 2 [63:0] |
332 * +-----------------------------------------------------+
333 * 24 | Buffer Address 3 [63:0] |
334 * +-----------------------------------------------------+
335 */
ef456f85 336 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 337 /* [Extended] Receive Descriptor (Write-Back) Format
338 *
339 * 63 48 47 32 31 13 12 8 7 4 3 0
340 * +------------------------------------------------------+
341 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
342 * | Checksum | Ident | | Queue | | Type |
343 * +------------------------------------------------------+
344 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
345 * +------------------------------------------------------+
346 * 63 48 47 32 31 20 19 0
347 */
ef456f85 348 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 349 for (i = 0; i < rx_ring->count; i++) {
ef456f85 350 const char *next_desc;
84f4ee90
TI		 351 buffer_info = &rx_ring->buffer_info[i];
352 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
353 u1 = (struct my_u1 *)rx_desc_ps;
354 staterr =
af667a29 355 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 356
357 if (i == rx_ring->next_to_use)
358 next_desc = " NTU";
359 else if (i == rx_ring->next_to_clean)
360 next_desc = " NTC";
361 else
362 next_desc = "";
363
84f4ee90
TI		 364 if (staterr & E1000_RXD_STAT_DD) {
365 /* Descriptor Done */
ef456f85
JK		 366 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
367 "RWB", i,
368 (unsigned long long)le64_to_cpu(u1->a),
369 (unsigned long long)le64_to_cpu(u1->b),
370 (unsigned long long)le64_to_cpu(u1->c),
371 (unsigned long long)le64_to_cpu(u1->d),
372 buffer_info->skb, next_desc);
84f4ee90 373 } else {
ef456f85
JK		 374 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
375 "R ", i,
376 (unsigned long long)le64_to_cpu(u1->a),
377 (unsigned long long)le64_to_cpu(u1->b),
378 (unsigned long long)le64_to_cpu(u1->c),
379 (unsigned long long)le64_to_cpu(u1->d),
380 (unsigned long long)buffer_info->dma,
381 buffer_info->skb, next_desc);
84f4ee90
TI		 382
383 if (netif_msg_pktdata(adapter))
384 print_hex_dump(KERN_INFO, "",
385 DUMP_PREFIX_ADDRESS, 16, 1,
386 phys_to_virt(buffer_info->dma),
387 adapter->rx_ps_bsize0, true);
388 }
84f4ee90
TI		 389 }
390 break;
391 default:
392 case 0:
5f450212 393 /* Extended Receive Descriptor (Read) Format
84f4ee90 394 *
5f450212
BA		 395 * +-----------------------------------------------------+
396 * 0 | Buffer Address [63:0] |
397 * +-----------------------------------------------------+
398 * 8 | Reserved |
399 * +-----------------------------------------------------+
84f4ee90 400 */
ef456f85 401 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 402 /* Extended Receive Descriptor (Write-Back) Format
403 *
404 * 63 48 47 32 31 24 23 4 3 0
405 * +------------------------------------------------------+
406 * | RSS Hash | | | |
407 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
408 * | Packet | IP | | | Type |
409 * | Checksum | Ident | | | |
410 * +------------------------------------------------------+
411 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
412 * +------------------------------------------------------+
413 * 63 48 47 32 31 20 19 0
414 */
ef456f85 415 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 416
417 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 418 const char *next_desc;
419
84f4ee90 420 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 421 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
422 u1 = (struct my_u1 *)rx_desc;
423 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 424
425 if (i == rx_ring->next_to_use)
426 next_desc = " NTU";
427 else if (i == rx_ring->next_to_clean)
428 next_desc = " NTC";
429 else
430 next_desc = "";
431
5f450212
BA		 432 if (staterr & E1000_RXD_STAT_DD) {
433 /* Descriptor Done */
ef456f85
JK		 434 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
435 "RWB", i,
436 (unsigned long long)le64_to_cpu(u1->a),
437 (unsigned long long)le64_to_cpu(u1->b),
438 buffer_info->skb, next_desc);
5f450212 439 } else {
ef456f85
JK		 440 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
441 "R ", i,
442 (unsigned long long)le64_to_cpu(u1->a),
443 (unsigned long long)le64_to_cpu(u1->b),
444 (unsigned long long)buffer_info->dma,
445 buffer_info->skb, next_desc);
5f450212
BA		 446
447 if (netif_msg_pktdata(adapter))
448 print_hex_dump(KERN_INFO, "",
449 DUMP_PREFIX_ADDRESS, 16,
450 1,
451 phys_to_virt
452 (buffer_info->dma),
453 adapter->rx_buffer_len,
454 true);
455 }
84f4ee90
TI		 456 }
457 }
84f4ee90
TI		 458}
459
bc7f75fa
AK		 460/**
461 * e1000_desc_unused - calculate if we have unused descriptors
462 **/
463static int e1000_desc_unused(struct e1000_ring *ring)
464{
465 if (ring->next_to_clean > ring->next_to_use)
466 return ring->next_to_clean - ring->next_to_use - 1;
467
468 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
469}
470
471/**
ad68076e 472 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 473 * @adapter: board private structure
474 * @status: descriptor status field as written by hardware
475 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
476 * @skb: pointer to sk_buff to be indicated to stack
477 **/
478static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 479 struct net_device *netdev, struct sk_buff *skb,
a39fe742 480 u8 status, __le16 vlan)
bc7f75fa 481{
86d70e53 482 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 483 skb->protocol = eth_type_trans(skb, netdev);
484
86d70e53
JK		 485 if (status & E1000_RXD_STAT_VP)
486 __vlan_hwaccel_put_tag(skb, tag);
487
488 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 489}
490
491/**
af667a29 492 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 493 * @adapter: board private structure
494 * @status_err: receive descriptor status and error fields
495 * @csum: receive descriptor csum field
496 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 497 **/
498static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 499 struct sk_buff *skb)
bc7f75fa
AK		 500{
501 u16 status = (u16)status_err;
502 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 503
504 skb_checksum_none_assert(skb);
bc7f75fa 505
afd12939
BA		 506 /* Rx checksum disabled */
507 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
508 return;
509
bc7f75fa
AK		 510 /* Ignore Checksum bit is set */
511 if (status & E1000_RXD_STAT_IXSM)
512 return;
afd12939 513
2e1706f2
BA		 514 /* TCP/UDP checksum error bit or IP checksum error bit is set */
515 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 516 /* let the stack verify checksum errors */
517 adapter->hw_csum_err++;
518 return;
519 }
520
521 /* TCP/UDP Checksum has not been calculated */
522 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
523 return;
524
525 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 526 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 527 adapter->hw_csum_good++;
528}
529
55aa6985 530static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 531{
55aa6985 532 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 533 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 534 s32 ret_val = __ew32_prepare(hw);
535
536 writel(i, rx_ring->tail);
c6e7f51e 537
bdc125f7 538 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 539 u32 rctl = er32(RCTL);
540 ew32(RCTL, rctl & ~E1000_RCTL_EN);
541 e_err("ME firmware caused invalid RDT - resetting\n");
542 schedule_work(&adapter->reset_task);
543 }
544}
545
55aa6985 546static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 547{
55aa6985 548 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 549 struct e1000_hw *hw = &adapter->hw;
bdc125f7 550 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 551
bdc125f7
BA		 552 writel(i, tx_ring->tail);
553
554 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 555 u32 tctl = er32(TCTL);
556 ew32(TCTL, tctl & ~E1000_TCTL_EN);
557 e_err("ME firmware caused invalid TDT - resetting\n");
558 schedule_work(&adapter->reset_task);
559 }
560}
561
bc7f75fa 562/**
5f450212 563 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 564 * @rx_ring: Rx descriptor ring
bc7f75fa 565 **/
55aa6985 566static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 567 int cleaned_count, gfp_t gfp)
bc7f75fa 568{
55aa6985 569 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 570 struct net_device *netdev = adapter->netdev;
571 struct pci_dev *pdev = adapter->pdev;
5f450212 572 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 573 struct e1000_buffer *buffer_info;
574 struct sk_buff *skb;
575 unsigned int i;
89d71a66 576 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 577
578 i = rx_ring->next_to_use;
579 buffer_info = &rx_ring->buffer_info[i];
580
581 while (cleaned_count--) {
582 skb = buffer_info->skb;
583 if (skb) {
584 skb_trim(skb, 0);
585 goto map_skb;
586 }
587
c2fed996 588 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 589 if (!skb) {
590 /* Better luck next round */
591 adapter->alloc_rx_buff_failed++;
592 break;
593 }
594
bc7f75fa
AK		 595 buffer_info->skb = skb;
596map_skb:
0be3f55f 597 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 598 adapter->rx_buffer_len,
0be3f55f
NN		 599 DMA_FROM_DEVICE);
600 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 601 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 602 adapter->rx_dma_failed++;
603 break;
604 }
605
5f450212
BA		 606 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
607 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 608
50849d79
TH		 609 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
610 /*
611 * Force memory writes to complete before letting h/w
612 * know there are new descriptors to fetch. (Only
613 * applicable for weak-ordered memory model archs,
614 * such as IA-64).
615 */
616 wmb();
c6e7f51e 617 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 618 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 619 else
c5083cf6 620 writel(i, rx_ring->tail);
50849d79 621 }
bc7f75fa
AK		 622 i++;
623 if (i == rx_ring->count)
624 i = 0;
625 buffer_info = &rx_ring->buffer_info[i];
626 }
627
50849d79 628 rx_ring->next_to_use = i;
bc7f75fa
AK		 629}
630
631/**
632 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 633 * @rx_ring: Rx descriptor ring
bc7f75fa 634 **/
55aa6985 635static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 636 int cleaned_count, gfp_t gfp)
bc7f75fa 637{
55aa6985 638 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 639 struct net_device *netdev = adapter->netdev;
640 struct pci_dev *pdev = adapter->pdev;
641 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 642 struct e1000_buffer *buffer_info;
643 struct e1000_ps_page *ps_page;
644 struct sk_buff *skb;
645 unsigned int i, j;
646
647 i = rx_ring->next_to_use;
648 buffer_info = &rx_ring->buffer_info[i];
649
650 while (cleaned_count--) {
651 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
652
653 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 654 ps_page = &buffer_info->ps_pages[j];
655 if (j >= adapter->rx_ps_pages) {
656 /* all unused desc entries get hw null ptr */
af667a29
BA		 657 rx_desc->read.buffer_addr[j + 1] =
658 ~cpu_to_le64(0);
47f44e40
AK		 659 continue;
660 }
661 if (!ps_page->page) {
c2fed996 662 ps_page->page = alloc_page(gfp);
bc7f75fa 663 if (!ps_page->page) {
47f44e40
AK		 664 adapter->alloc_rx_buff_failed++;
665 goto no_buffers;
666 }
0be3f55f
NN		 667 ps_page->dma = dma_map_page(&pdev->dev,
668 ps_page->page,
669 0, PAGE_SIZE,
670 DMA_FROM_DEVICE);
671 if (dma_mapping_error(&pdev->dev,
672 ps_page->dma)) {
47f44e40 673 dev_err(&adapter->pdev->dev,
af667a29 674 "Rx DMA page map failed\n");
47f44e40
AK		 675 adapter->rx_dma_failed++;
676 goto no_buffers;
bc7f75fa 677 }
bc7f75fa 678 }
47f44e40
AK		 679 /*
680 * Refresh the desc even if buffer_addrs
681 * didn't change because each write-back
682 * erases this info.
683 */
af667a29
BA		 684 rx_desc->read.buffer_addr[j + 1] =
685 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 686 }
687
c2fed996
JK		 688 skb = __netdev_alloc_skb_ip_align(netdev,
689 adapter->rx_ps_bsize0,
690 gfp);
bc7f75fa
AK		 691
692 if (!skb) {
693 adapter->alloc_rx_buff_failed++;
694 break;
695 }
696
bc7f75fa 697 buffer_info->skb = skb;
0be3f55f 698 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 699 adapter->rx_ps_bsize0,
0be3f55f
NN		 700 DMA_FROM_DEVICE);
701 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 702 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 703 adapter->rx_dma_failed++;
704 /* cleanup skb */
705 dev_kfree_skb_any(skb);
706 buffer_info->skb = NULL;
707 break;
708 }
709
710 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
711
50849d79
TH		 712 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
713 /*
714 * Force memory writes to complete before letting h/w
715 * know there are new descriptors to fetch. (Only
716 * applicable for weak-ordered memory model archs,
717 * such as IA-64).
718 */
719 wmb();
c6e7f51e 720 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 721 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 722 else
c5083cf6 723 writel(i << 1, rx_ring->tail);
50849d79
TH		 724 }
725
bc7f75fa
AK		 726 i++;
727 if (i == rx_ring->count)
728 i = 0;
729 buffer_info = &rx_ring->buffer_info[i];
730 }
731
732no_buffers:
50849d79 733 rx_ring->next_to_use = i;
bc7f75fa
AK		 734}
735
97ac8cae
BA		 736/**
737 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 738 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 739 * @cleaned_count: number of buffers to allocate this pass
740 **/
741
55aa6985 742static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 743 int cleaned_count, gfp_t gfp)
97ac8cae 744{
55aa6985 745 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 746 struct net_device *netdev = adapter->netdev;
747 struct pci_dev *pdev = adapter->pdev;
5f450212 748 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 749 struct e1000_buffer *buffer_info;
750 struct sk_buff *skb;
751 unsigned int i;
89d71a66 752 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 753
754 i = rx_ring->next_to_use;
755 buffer_info = &rx_ring->buffer_info[i];
756
757 while (cleaned_count--) {
758 skb = buffer_info->skb;
759 if (skb) {
760 skb_trim(skb, 0);
761 goto check_page;
762 }
763
c2fed996 764 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 765 if (unlikely(!skb)) {
766 /* Better luck next round */
767 adapter->alloc_rx_buff_failed++;
768 break;
769 }
770
97ac8cae
BA		 771 buffer_info->skb = skb;
772check_page:
773 /* allocate a new page if necessary */
774 if (!buffer_info->page) {
c2fed996 775 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 776 if (unlikely(!buffer_info->page)) {
777 adapter->alloc_rx_buff_failed++;
778 break;
779 }
780 }
781
782 if (!buffer_info->dma)
0be3f55f 783 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 784 buffer_info->page, 0,
785 PAGE_SIZE,
0be3f55f 786 DMA_FROM_DEVICE);
97ac8cae 787
5f450212
BA		 788 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
789 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 790
791 if (unlikely(++i == rx_ring->count))
792 i = 0;
793 buffer_info = &rx_ring->buffer_info[i];
794 }
795
796 if (likely(rx_ring->next_to_use != i)) {
797 rx_ring->next_to_use = i;
798 if (unlikely(i-- == 0))
799 i = (rx_ring->count - 1);
800
801 /* Force memory writes to complete before letting h/w
802 * know there are new descriptors to fetch. (Only
803 * applicable for weak-ordered memory model archs,
804 * such as IA-64). */
805 wmb();
c6e7f51e 806 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 807 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 808 else
c5083cf6 809 writel(i, rx_ring->tail);
97ac8cae
BA		 810 }
811}
812
70495a50
BA		 813static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
814 struct sk_buff *skb)
815{
816 if (netdev->features & NETIF_F_RXHASH)
817 skb->rxhash = le32_to_cpu(rss);
818}
819
bc7f75fa 820/**
55aa6985
BA		 821 * e1000_clean_rx_irq - Send received data up the network stack
822 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 823 *
824 * the return value indicates whether actual cleaning was done, there
825 * is no guarantee that everything was cleaned
826 **/
55aa6985
BA		 827static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
828 int work_to_do)
bc7f75fa 829{
55aa6985 830 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 831 struct net_device *netdev = adapter->netdev;
832 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 833 struct e1000_hw *hw = &adapter->hw;
5f450212 834 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 835 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 836 u32 length, staterr;
bc7f75fa
AK		 837 unsigned int i;
838 int cleaned_count = 0;
3db1cd5c 839 bool cleaned = false;
bc7f75fa
AK		 840 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
841
842 i = rx_ring->next_to_clean;
5f450212
BA		 843 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
844 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 845 buffer_info = &rx_ring->buffer_info[i];
846
5f450212 847 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 848 struct sk_buff *skb;
bc7f75fa
AK		 849
850 if (*work_done >= work_to_do)
851 break;
852 (*work_done)++;
2d0bb1c1 853 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 854
bc7f75fa
AK		 855 skb = buffer_info->skb;
856 buffer_info->skb = NULL;
857
858 prefetch(skb->data - NET_IP_ALIGN);
859
860 i++;
861 if (i == rx_ring->count)
862 i = 0;
5f450212 863 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 864 prefetch(next_rxd);
865
866 next_buffer = &rx_ring->buffer_info[i];
867
3db1cd5c 868 cleaned = true;
bc7f75fa 869 cleaned_count++;
0be3f55f 870 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 871 buffer_info->dma,
872 adapter->rx_buffer_len,
0be3f55f 873 DMA_FROM_DEVICE);
bc7f75fa
AK		 874 buffer_info->dma = 0;
875
5f450212 876 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 877
b94b5028
JB		 878 /*
879 * !EOP means multiple descriptors were used to store a single
880 * packet, if that's the case we need to toss it. In fact, we
881 * need to toss every packet with the EOP bit clear and the
882 * next frame that _does_ have the EOP bit set, as it is by
883 * definition only a frame fragment
884 */
5f450212 885 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 886 adapter->flags2 |= FLAG2_IS_DISCARDING;
887
888 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 889 /* All receives must fit into a single buffer */
3bb99fe2 890 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 891 /* recycle */
892 buffer_info->skb = skb;
5f450212 893 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 894 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 895 goto next_desc;
896 }
897
cf955e6c
BG		 898 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
899 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 900 /* recycle */
901 buffer_info->skb = skb;
902 goto next_desc;
903 }
904
eb7c3adb 905 /* adjust length to remove Ethernet CRC */
0184039a
BG		 906 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
907 /* If configured to store CRC, don't subtract FCS,
908 * but keep the FCS bytes out of the total_rx_bytes
909 * counter
910 */
911 if (netdev->features & NETIF_F_RXFCS)
912 total_rx_bytes -= 4;
913 else
914 length -= 4;
915 }
eb7c3adb 916
bc7f75fa
AK		 917 total_rx_bytes += length;
918 total_rx_packets++;
919
ad68076e
BA		 920 /*
921 * code added for copybreak, this should improve
bc7f75fa 922 * performance for small packets with large amounts
ad68076e
BA		 923 * of reassembly being done in the stack
924 */
bc7f75fa
AK		 925 if (length < copybreak) {
926 struct sk_buff *new_skb =
89d71a66 927 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 928 if (new_skb) {
808ff676
BA		 929 skb_copy_to_linear_data_offset(new_skb,
930 -NET_IP_ALIGN,
931 (skb->data -
932 NET_IP_ALIGN),
933 (length +
934 NET_IP_ALIGN));
bc7f75fa
AK		 935 /* save the skb in buffer_info as good */
936 buffer_info->skb = skb;
937 skb = new_skb;
938 }
939 /* else just continue with the old one */
940 }
941 /* end copybreak code */
942 skb_put(skb, length);
943
944 /* Receive Checksum Offload */
2e1706f2 945 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 946
70495a50
BA		 947 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
948
5f450212
BA		 949 e1000_receive_skb(adapter, netdev, skb, staterr,
950 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 951
952next_desc:
5f450212 953 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 954
955 /* return some buffers to hardware, one at a time is too slow */
956 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 957 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 958 GFP_ATOMIC);
bc7f75fa
AK		 959 cleaned_count = 0;
960 }
961
962 /* use prefetched values */
963 rx_desc = next_rxd;
964 buffer_info = next_buffer;
5f450212
BA		 965
966 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 967 }
968 rx_ring->next_to_clean = i;
969
970 cleaned_count = e1000_desc_unused(rx_ring);
971 if (cleaned_count)
55aa6985 972 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 973
bc7f75fa 974 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 975 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 976 return cleaned;
977}
978
55aa6985
BA		 979static void e1000_put_txbuf(struct e1000_ring *tx_ring,
980 struct e1000_buffer *buffer_info)
bc7f75fa 981{
55aa6985
BA		 982 struct e1000_adapter *adapter = tx_ring->adapter;
983
03b1320d
AD		 984 if (buffer_info->dma) {
985 if (buffer_info->mapped_as_page)
0be3f55f
NN		 986 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
987 buffer_info->length, DMA_TO_DEVICE);
03b1320d 988 else
0be3f55f
NN		 989 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
990 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 991 buffer_info->dma = 0;
992 }
bc7f75fa
AK		 993 if (buffer_info->skb) {
994 dev_kfree_skb_any(buffer_info->skb);
995 buffer_info->skb = NULL;
996 }
1b7719c4 997 buffer_info->time_stamp = 0;
bc7f75fa
AK		 998}
999
41cec6f1 1000static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1001{
41cec6f1
BA		 1002 struct e1000_adapter *adapter = container_of(work,
1003 struct e1000_adapter,
1004 print_hang_task);
09357b00 1005 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1006 struct e1000_ring *tx_ring = adapter->tx_ring;
1007 unsigned int i = tx_ring->next_to_clean;
1008 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1009 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1010 struct e1000_hw *hw = &adapter->hw;
1011 u16 phy_status, phy_1000t_status, phy_ext_status;
1012 u16 pci_status;
1013
615b32af
JB		 1014 if (test_bit(__E1000_DOWN, &adapter->state))
1015 return;
1016
09357b00
JK		 1017 if (!adapter->tx_hang_recheck &&
1018 (adapter->flags2 & FLAG2_DMA_BURST)) {
397c020a
MV		 1019 /*
1020 * May be block on write-back, flush and detect again
09357b00
JK		 1021 * flush pending descriptor writebacks to memory
1022 */
1023 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1024 /* execute the writes immediately */
1025 e1e_flush();
bf03085f
MV		 1026 /*
1027 * Due to rare timing issues, write to TIDV again to ensure
1028 * the write is successful
1029 */
1030 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1031 /* execute the writes immediately */
1032 e1e_flush();
09357b00
JK		 1033 adapter->tx_hang_recheck = true;
1034 return;
1035 }
1036 /* Real hang detected */
1037 adapter->tx_hang_recheck = false;
1038 netif_stop_queue(netdev);
1039
41cec6f1
BA		 1040 e1e_rphy(hw, PHY_STATUS, &phy_status);
1041 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1042 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1043
41cec6f1
BA		 1044 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1045
1046 /* detected Hardware unit hang */
1047 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1048 " TDH <%x>\n"
1049 " TDT <%x>\n"
1050 " next_to_use <%x>\n"
1051 " next_to_clean <%x>\n"
1052 "buffer_info[next_to_clean]:\n"
1053 " time_stamp <%lx>\n"
1054 " next_to_watch <%x>\n"
1055 " jiffies <%lx>\n"
41cec6f1
BA		 1056 " next_to_watch.status <%x>\n"
1057 "MAC Status <%x>\n"
1058 "PHY Status <%x>\n"
1059 "PHY 1000BASE-T Status <%x>\n"
1060 "PHY Extended Status <%x>\n"
1061 "PCI Status <%x>\n",
c5083cf6
BA		 1062 readl(tx_ring->head),
1063 readl(tx_ring->tail),
44defeb3
JK		 1064 tx_ring->next_to_use,
1065 tx_ring->next_to_clean,
1066 tx_ring->buffer_info[eop].time_stamp,
1067 eop,
1068 jiffies,
41cec6f1
BA		 1069 eop_desc->upper.fields.status,
1070 er32(STATUS),
1071 phy_status,
1072 phy_1000t_status,
1073 phy_ext_status,
1074 pci_status);
7c0427ee
BA		 1075
1076 /* Suggest workaround for known h/w issue */
1077 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1078 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1079}
1080
1081/**
1082 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1083 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1084 *
1085 * the return value indicates whether actual cleaning was done, there
1086 * is no guarantee that everything was cleaned
1087 **/
55aa6985 1088static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1089{
55aa6985 1090 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1091 struct net_device *netdev = adapter->netdev;
1092 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1093 struct e1000_tx_desc *tx_desc, *eop_desc;
1094 struct e1000_buffer *buffer_info;
1095 unsigned int i, eop;
1096 unsigned int count = 0;
bc7f75fa 1097 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1098 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1099
1100 i = tx_ring->next_to_clean;
1101 eop = tx_ring->buffer_info[i].next_to_watch;
1102 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1103
12d04a3c
AD		 1104 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1105 (count < tx_ring->count)) {
a86043c2 1106 bool cleaned = false;
2d0bb1c1 1107 rmb(); /* read buffer_info after eop_desc */
a86043c2 1108 for (; !cleaned; count++) {
bc7f75fa
AK		 1109 tx_desc = E1000_TX_DESC(*tx_ring, i);
1110 buffer_info = &tx_ring->buffer_info[i];
1111 cleaned = (i == eop);
1112
1113 if (cleaned) {
9ed318d5
TH		 1114 total_tx_packets += buffer_info->segs;
1115 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1116 if (buffer_info->skb) {
1117 bytes_compl += buffer_info->skb->len;
1118 pkts_compl++;
1119 }
bc7f75fa
AK		 1120 }
1121
55aa6985 1122 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1123 tx_desc->upper.data = 0;
1124
1125 i++;
1126 if (i == tx_ring->count)
1127 i = 0;
1128 }
1129
dac87619
TL		 1130 if (i == tx_ring->next_to_use)
1131 break;
bc7f75fa
AK		 1132 eop = tx_ring->buffer_info[i].next_to_watch;
1133 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1134 }
1135
1136 tx_ring->next_to_clean = i;
1137
3f0cfa3b
TH		 1138 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1139
bc7f75fa 1140#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1141 if (count && netif_carrier_ok(netdev) &&
1142 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1143 /* Make sure that anybody stopping the queue after this
1144 * sees the new next_to_clean.
1145 */
1146 smp_mb();
1147
1148 if (netif_queue_stopped(netdev) &&
1149 !(test_bit(__E1000_DOWN, &adapter->state))) {
1150 netif_wake_queue(netdev);
1151 ++adapter->restart_queue;
1152 }
1153 }
1154
1155 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1156 /*
1157 * Detect a transmit hang in hardware, this serializes the
1158 * check with the clearing of time_stamp and movement of i
1159 */
3db1cd5c 1160 adapter->detect_tx_hung = false;
12d04a3c
AD		 1161 if (tx_ring->buffer_info[i].time_stamp &&
1162 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1163 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1164 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1165 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1166 else
1167 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1168 }
1169 adapter->total_tx_bytes += total_tx_bytes;
1170 adapter->total_tx_packets += total_tx_packets;
807540ba 1171 return count < tx_ring->count;
bc7f75fa
AK		 1172}
1173
bc7f75fa
AK		 1174/**
1175 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1176 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1177 *
1178 * the return value indicates whether actual cleaning was done, there
1179 * is no guarantee that everything was cleaned
1180 **/
55aa6985
BA		 1181static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1182 int work_to_do)
bc7f75fa 1183{
55aa6985 1184 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1185 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1186 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1187 struct net_device *netdev = adapter->netdev;
1188 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1189 struct e1000_buffer *buffer_info, *next_buffer;
1190 struct e1000_ps_page *ps_page;
1191 struct sk_buff *skb;
1192 unsigned int i, j;
1193 u32 length, staterr;
1194 int cleaned_count = 0;
3db1cd5c 1195 bool cleaned = false;
bc7f75fa
AK		 1196 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1197
1198 i = rx_ring->next_to_clean;
1199 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1200 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1201 buffer_info = &rx_ring->buffer_info[i];
1202
1203 while (staterr & E1000_RXD_STAT_DD) {
1204 if (*work_done >= work_to_do)
1205 break;
1206 (*work_done)++;
1207 skb = buffer_info->skb;
2d0bb1c1 1208 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1209
1210 /* in the packet split case this is header only */
1211 prefetch(skb->data - NET_IP_ALIGN);
1212
1213 i++;
1214 if (i == rx_ring->count)
1215 i = 0;
1216 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1217 prefetch(next_rxd);
1218
1219 next_buffer = &rx_ring->buffer_info[i];
1220
3db1cd5c 1221 cleaned = true;
bc7f75fa 1222 cleaned_count++;
0be3f55f 1223 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1224 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1225 buffer_info->dma = 0;
1226
af667a29 1227 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1228 if (!(staterr & E1000_RXD_STAT_EOP))
1229 adapter->flags2 |= FLAG2_IS_DISCARDING;
1230
1231 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1232 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1233 dev_kfree_skb_irq(skb);
b94b5028
JB		 1234 if (staterr & E1000_RXD_STAT_EOP)
1235 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1236 goto next_desc;
1237 }
1238
cf955e6c
BG		 1239 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1240 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1241 dev_kfree_skb_irq(skb);
1242 goto next_desc;
1243 }
1244
1245 length = le16_to_cpu(rx_desc->wb.middle.length0);
1246
1247 if (!length) {
ef456f85 1248 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1249 dev_kfree_skb_irq(skb);
1250 goto next_desc;
1251 }
1252
1253 /* Good Receive */
1254 skb_put(skb, length);
1255
1256 {
0e15df49
BA		 1257 /*
1258 * this looks ugly, but it seems compiler issues make
1259 * it more efficient than reusing j
1260 */
1261 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1262
ad68076e 1263 /*
0e15df49
BA		 1264 * page alloc/put takes too long and effects small
1265 * packet throughput, so unsplit small packets and
1266 * save the alloc/put only valid in softirq (napi)
1267 * context to call kmap_*
ad68076e 1268 */
0e15df49
BA		 1269 if (l1 && (l1 <= copybreak) &&
1270 ((length + l1) <= adapter->rx_ps_bsize0)) {
1271 u8 *vaddr;
1272
1273 ps_page = &buffer_info->ps_pages[0];
1274
1275 /*
1276 * there is no documentation about how to call
1277 * kmap_atomic, so we can't hold the mapping
1278 * very long
1279 */
1280 dma_sync_single_for_cpu(&pdev->dev,
1281 ps_page->dma,
1282 PAGE_SIZE,
1283 DMA_FROM_DEVICE);
9f393834 1284 vaddr = kmap_atomic(ps_page->page);
0e15df49 1285 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1286 kunmap_atomic(vaddr);
0e15df49
BA		 1287 dma_sync_single_for_device(&pdev->dev,
1288 ps_page->dma,
1289 PAGE_SIZE,
1290 DMA_FROM_DEVICE);
1291
1292 /* remove the CRC */
0184039a
BG		 1293 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1294 if (!(netdev->features & NETIF_F_RXFCS))
1295 l1 -= 4;
1296 }
0e15df49
BA		 1297
1298 skb_put(skb, l1);
1299 goto copydone;
1300 } /* if */
bc7f75fa
AK		 1301 }
1302
1303 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1304 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1305 if (!length)
1306 break;
1307
47f44e40 1308 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1309 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1310 DMA_FROM_DEVICE);
bc7f75fa
AK		 1311 ps_page->dma = 0;
1312 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1313 ps_page->page = NULL;
1314 skb->len += length;
1315 skb->data_len += length;
98a045d7 1316 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1317 }
1318
eb7c3adb
JK		 1319 /* strip the ethernet crc, problem is we're using pages now so
1320 * this whole operation can get a little cpu intensive
1321 */
0184039a
BG		 1322 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1323 if (!(netdev->features & NETIF_F_RXFCS))
1324 pskb_trim(skb, skb->len - 4);
1325 }
eb7c3adb 1326
bc7f75fa
AK		 1327copydone:
1328 total_rx_bytes += skb->len;
1329 total_rx_packets++;
1330
2e1706f2 1331 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1332
70495a50
BA		 1333 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1334
bc7f75fa
AK		 1335 if (rx_desc->wb.upper.header_status &
1336 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1337 adapter->rx_hdr_split++;
1338
1339 e1000_receive_skb(adapter, netdev, skb,
1340 staterr, rx_desc->wb.middle.vlan);
1341
1342next_desc:
1343 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1344 buffer_info->skb = NULL;
1345
1346 /* return some buffers to hardware, one at a time is too slow */
1347 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1348 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1349 GFP_ATOMIC);
bc7f75fa
AK		 1350 cleaned_count = 0;
1351 }
1352
1353 /* use prefetched values */
1354 rx_desc = next_rxd;
1355 buffer_info = next_buffer;
1356
1357 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1358 }
1359 rx_ring->next_to_clean = i;
1360
1361 cleaned_count = e1000_desc_unused(rx_ring);
1362 if (cleaned_count)
55aa6985 1363 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1364
bc7f75fa 1365 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1366 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1367 return cleaned;
1368}
1369
97ac8cae
BA		 1370/**
1371 * e1000_consume_page - helper function
1372 **/
1373static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1374 u16 length)
1375{
1376 bi->page = NULL;
1377 skb->len += length;
1378 skb->data_len += length;
98a045d7 1379 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1380}
1381
1382/**
1383 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1384 * @adapter: board private structure
1385 *
1386 * the return value indicates whether actual cleaning was done, there
1387 * is no guarantee that everything was cleaned
1388 **/
55aa6985
BA		 1389static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1390 int work_to_do)
97ac8cae 1391{
55aa6985 1392 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1393 struct net_device *netdev = adapter->netdev;
1394 struct pci_dev *pdev = adapter->pdev;
5f450212 1395 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1396 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1397 u32 length, staterr;
97ac8cae
BA		 1398 unsigned int i;
1399 int cleaned_count = 0;
1400 bool cleaned = false;
1401 unsigned int total_rx_bytes=0, total_rx_packets=0;
1402
1403 i = rx_ring->next_to_clean;
5f450212
BA		 1404 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1405 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1406 buffer_info = &rx_ring->buffer_info[i];
1407
5f450212 1408 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1409 struct sk_buff *skb;
97ac8cae
BA		 1410
1411 if (*work_done >= work_to_do)
1412 break;
1413 (*work_done)++;
2d0bb1c1 1414 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1415
97ac8cae
BA		 1416 skb = buffer_info->skb;
1417 buffer_info->skb = NULL;
1418
1419 ++i;
1420 if (i == rx_ring->count)
1421 i = 0;
5f450212 1422 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1423 prefetch(next_rxd);
1424
1425 next_buffer = &rx_ring->buffer_info[i];
1426
1427 cleaned = true;
1428 cleaned_count++;
0be3f55f
NN		 1429 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1430 DMA_FROM_DEVICE);
97ac8cae
BA		 1431 buffer_info->dma = 0;
1432
5f450212 1433 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1434
1435 /* errors is only valid for DD + EOP descriptors */
5f450212 1436 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1437 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1438 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1439 /* recycle both page and skb */
1440 buffer_info->skb = skb;
1441 /* an error means any chain goes out the window too */
1442 if (rx_ring->rx_skb_top)
1443 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1444 rx_ring->rx_skb_top = NULL;
1445 goto next_desc;
97ac8cae
BA		 1446 }
1447
f0f1a172 1448#define rxtop (rx_ring->rx_skb_top)
5f450212 1449 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1450 /* this descriptor is only the beginning (or middle) */
1451 if (!rxtop) {
1452 /* this is the beginning of a chain */
1453 rxtop = skb;
1454 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1455 0, length);
1456 } else {
1457 /* this is the middle of a chain */
1458 skb_fill_page_desc(rxtop,
1459 skb_shinfo(rxtop)->nr_frags,
1460 buffer_info->page, 0, length);
1461 /* re-use the skb, only consumed the page */
1462 buffer_info->skb = skb;
1463 }
1464 e1000_consume_page(buffer_info, rxtop, length);
1465 goto next_desc;
1466 } else {
1467 if (rxtop) {
1468 /* end of the chain */
1469 skb_fill_page_desc(rxtop,
1470 skb_shinfo(rxtop)->nr_frags,
1471 buffer_info->page, 0, length);
1472 /* re-use the current skb, we only consumed the
1473 * page */
1474 buffer_info->skb = skb;
1475 skb = rxtop;
1476 rxtop = NULL;
1477 e1000_consume_page(buffer_info, skb, length);
1478 } else {
1479 /* no chain, got EOP, this buf is the packet
1480 * copybreak to save the put_page/alloc_page */
1481 if (length <= copybreak &&
1482 skb_tailroom(skb) >= length) {
1483 u8 *vaddr;
4679026d 1484 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1485 memcpy(skb_tail_pointer(skb), vaddr,
1486 length);
4679026d 1487 kunmap_atomic(vaddr);
97ac8cae
BA		 1488 /* re-use the page, so don't erase
1489 * buffer_info->page */
1490 skb_put(skb, length);
1491 } else {
1492 skb_fill_page_desc(skb, 0,
1493 buffer_info->page, 0,
1494 length);
1495 e1000_consume_page(buffer_info, skb,
1496 length);
1497 }
1498 }
1499 }
1500
2e1706f2
BA		 1501 /* Receive Checksum Offload */
1502 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1503
70495a50
BA		 1504 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1505
97ac8cae
BA		 1506 /* probably a little skewed due to removing CRC */
1507 total_rx_bytes += skb->len;
1508 total_rx_packets++;
1509
1510 /* eth type trans needs skb->data to point to something */
1511 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1512 e_err("pskb_may_pull failed.\n");
ef5ab89c 1513 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1514 goto next_desc;
1515 }
1516
5f450212
BA		 1517 e1000_receive_skb(adapter, netdev, skb, staterr,
1518 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1519
1520next_desc:
5f450212 1521 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1522
1523 /* return some buffers to hardware, one at a time is too slow */
1524 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1525 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1526 GFP_ATOMIC);
97ac8cae
BA		 1527 cleaned_count = 0;
1528 }
1529
1530 /* use prefetched values */
1531 rx_desc = next_rxd;
1532 buffer_info = next_buffer;
5f450212
BA		 1533
1534 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1535 }
1536 rx_ring->next_to_clean = i;
1537
1538 cleaned_count = e1000_desc_unused(rx_ring);
1539 if (cleaned_count)
55aa6985 1540 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1541
1542 adapter->total_rx_bytes += total_rx_bytes;
1543 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1544 return cleaned;
1545}
1546
bc7f75fa
AK		 1547/**
1548 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1549 * @rx_ring: Rx descriptor ring
bc7f75fa 1550 **/
55aa6985 1551static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1552{
55aa6985 1553 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1554 struct e1000_buffer *buffer_info;
1555 struct e1000_ps_page *ps_page;
1556 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1557 unsigned int i, j;
1558
1559 /* Free all the Rx ring sk_buffs */
1560 for (i = 0; i < rx_ring->count; i++) {
1561 buffer_info = &rx_ring->buffer_info[i];
1562 if (buffer_info->dma) {
1563 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1564 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1565 adapter->rx_buffer_len,
0be3f55f 1566 DMA_FROM_DEVICE);
97ac8cae 1567 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1568 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1569 PAGE_SIZE,
0be3f55f 1570 DMA_FROM_DEVICE);
bc7f75fa 1571 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1572 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1573 adapter->rx_ps_bsize0,
0be3f55f 1574 DMA_FROM_DEVICE);
bc7f75fa
AK		 1575 buffer_info->dma = 0;
1576 }
1577
97ac8cae
BA		 1578 if (buffer_info->page) {
1579 put_page(buffer_info->page);
1580 buffer_info->page = NULL;
1581 }
1582
bc7f75fa
AK		 1583 if (buffer_info->skb) {
1584 dev_kfree_skb(buffer_info->skb);
1585 buffer_info->skb = NULL;
1586 }
1587
1588 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1589 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1590 if (!ps_page->page)
1591 break;
0be3f55f
NN		 1592 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1593 DMA_FROM_DEVICE);
bc7f75fa
AK		 1594 ps_page->dma = 0;
1595 put_page(ps_page->page);
1596 ps_page->page = NULL;
1597 }
1598 }
1599
1600 /* there also may be some cached data from a chained receive */
1601 if (rx_ring->rx_skb_top) {
1602 dev_kfree_skb(rx_ring->rx_skb_top);
1603 rx_ring->rx_skb_top = NULL;
1604 }
1605
bc7f75fa
AK		 1606 /* Zero out the descriptor ring */
1607 memset(rx_ring->desc, 0, rx_ring->size);
1608
1609 rx_ring->next_to_clean = 0;
1610 rx_ring->next_to_use = 0;
b94b5028 1611 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1612
c5083cf6 1613 writel(0, rx_ring->head);
bdc125f7
BA		 1614 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1615 e1000e_update_rdt_wa(rx_ring, 0);
1616 else
1617 writel(0, rx_ring->tail);
bc7f75fa
AK		 1618}
1619
a8f88ff5
JB		 1620static void e1000e_downshift_workaround(struct work_struct *work)
1621{
1622 struct e1000_adapter *adapter = container_of(work,
1623 struct e1000_adapter, downshift_task);
1624
615b32af
JB		 1625 if (test_bit(__E1000_DOWN, &adapter->state))
1626 return;
1627
a8f88ff5
JB		 1628 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1629}
1630
bc7f75fa
AK		 1631/**
1632 * e1000_intr_msi - Interrupt Handler
1633 * @irq: interrupt number
1634 * @data: pointer to a network interface device structure
1635 **/
1636static irqreturn_t e1000_intr_msi(int irq, void *data)
1637{
1638 struct net_device *netdev = data;
1639 struct e1000_adapter *adapter = netdev_priv(netdev);
1640 struct e1000_hw *hw = &adapter->hw;
1641 u32 icr = er32(ICR);
1642
ad68076e
BA		 1643 /*
1644 * read ICR disables interrupts using IAM
1645 */
bc7f75fa 1646
573cca8c 1647 if (icr & E1000_ICR_LSC) {
f92518dd 1648 hw->mac.get_link_status = true;
ad68076e
BA		 1649 /*
1650 * ICH8 workaround-- Call gig speed drop workaround on cable
1651 * disconnect (LSC) before accessing any PHY registers
1652 */
bc7f75fa
AK		 1653 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1654 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1655 schedule_work(&adapter->downshift_task);
bc7f75fa 1656
ad68076e
BA		 1657 /*
1658 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1659 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1660 * adapter in watchdog
1661 */
bc7f75fa
AK		 1662 if (netif_carrier_ok(netdev) &&
1663 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1664 /* disable receives */
1665 u32 rctl = er32(RCTL);
1666 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1667 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1668 }
1669 /* guard against interrupt when we're going down */
1670 if (!test_bit(__E1000_DOWN, &adapter->state))
1671 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1672 }
1673
288379f0 1674 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1675 adapter->total_tx_bytes = 0;
1676 adapter->total_tx_packets = 0;
1677 adapter->total_rx_bytes = 0;
1678 adapter->total_rx_packets = 0;
288379f0 1679 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1680 }
1681
1682 return IRQ_HANDLED;
1683}
1684
1685/**
1686 * e1000_intr - Interrupt Handler
1687 * @irq: interrupt number
1688 * @data: pointer to a network interface device structure
1689 **/
1690static irqreturn_t e1000_intr(int irq, void *data)
1691{
1692 struct net_device *netdev = data;
1693 struct e1000_adapter *adapter = netdev_priv(netdev);
1694 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1695 u32 rctl, icr = er32(ICR);
4662e82b 1696
a68ea775 1697 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1698 return IRQ_NONE; /* Not our interrupt */
1699
ad68076e
BA		 1700 /*
1701 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1702 * not set, then the adapter didn't send an interrupt
1703 */
bc7f75fa
AK		 1704 if (!(icr & E1000_ICR_INT_ASSERTED))
1705 return IRQ_NONE;
1706
ad68076e
BA		 1707 /*
1708 * Interrupt Auto-Mask...upon reading ICR,
1709 * interrupts are masked. No need for the
1710 * IMC write
1711 */
bc7f75fa 1712
573cca8c 1713 if (icr & E1000_ICR_LSC) {
f92518dd 1714 hw->mac.get_link_status = true;
ad68076e
BA		 1715 /*
1716 * ICH8 workaround-- Call gig speed drop workaround on cable
1717 * disconnect (LSC) before accessing any PHY registers
1718 */
bc7f75fa
AK		 1719 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1720 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1721 schedule_work(&adapter->downshift_task);
bc7f75fa 1722
ad68076e
BA		 1723 /*
1724 * 80003ES2LAN workaround--
bc7f75fa
AK		 1725 * For packet buffer work-around on link down event;
1726 * disable receives here in the ISR and
1727 * reset adapter in watchdog
1728 */
1729 if (netif_carrier_ok(netdev) &&
1730 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1731 /* disable receives */
1732 rctl = er32(RCTL);
1733 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1734 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1735 }
1736 /* guard against interrupt when we're going down */
1737 if (!test_bit(__E1000_DOWN, &adapter->state))
1738 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1739 }
1740
288379f0 1741 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1742 adapter->total_tx_bytes = 0;
1743 adapter->total_tx_packets = 0;
1744 adapter->total_rx_bytes = 0;
1745 adapter->total_rx_packets = 0;
288379f0 1746 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1747 }
1748
1749 return IRQ_HANDLED;
1750}
1751
4662e82b
BA		 1752static irqreturn_t e1000_msix_other(int irq, void *data)
1753{
1754 struct net_device *netdev = data;
1755 struct e1000_adapter *adapter = netdev_priv(netdev);
1756 struct e1000_hw *hw = &adapter->hw;
1757 u32 icr = er32(ICR);
1758
1759 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1760 if (!test_bit(__E1000_DOWN, &adapter->state))
1761 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1762 return IRQ_NONE;
1763 }
1764
1765 if (icr & adapter->eiac_mask)
1766 ew32(ICS, (icr & adapter->eiac_mask));
1767
1768 if (icr & E1000_ICR_OTHER) {
1769 if (!(icr & E1000_ICR_LSC))
1770 goto no_link_interrupt;
f92518dd 1771 hw->mac.get_link_status = true;
4662e82b
BA		 1772 /* guard against interrupt when we're going down */
1773 if (!test_bit(__E1000_DOWN, &adapter->state))
1774 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1775 }
1776
1777no_link_interrupt:
a3c69fef
JB		 1778 if (!test_bit(__E1000_DOWN, &adapter->state))
1779 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1780
1781 return IRQ_HANDLED;
1782}
1783
1784
1785static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1786{
1787 struct net_device *netdev = data;
1788 struct e1000_adapter *adapter = netdev_priv(netdev);
1789 struct e1000_hw *hw = &adapter->hw;
1790 struct e1000_ring *tx_ring = adapter->tx_ring;
1791
1792
1793 adapter->total_tx_bytes = 0;
1794 adapter->total_tx_packets = 0;
1795
55aa6985 1796 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1797 /* Ring was not completely cleaned, so fire another interrupt */
1798 ew32(ICS, tx_ring->ims_val);
1799
1800 return IRQ_HANDLED;
1801}
1802
1803static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1804{
1805 struct net_device *netdev = data;
1806 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1807 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1808
1809 /* Write the ITR value calculated at the end of the
1810 * previous interrupt.
1811 */
55aa6985
BA		 1812 if (rx_ring->set_itr) {
1813 writel(1000000000 / (rx_ring->itr_val * 256),
1814 rx_ring->itr_register);
1815 rx_ring->set_itr = 0;
4662e82b
BA		 1816 }
1817
288379f0 1818 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1819 adapter->total_rx_bytes = 0;
1820 adapter->total_rx_packets = 0;
288379f0 1821 __napi_schedule(&adapter->napi);
4662e82b
BA		 1822 }
1823 return IRQ_HANDLED;
1824}
1825
1826/**
1827 * e1000_configure_msix - Configure MSI-X hardware
1828 *
1829 * e1000_configure_msix sets up the hardware to properly
1830 * generate MSI-X interrupts.
1831 **/
1832static void e1000_configure_msix(struct e1000_adapter *adapter)
1833{
1834 struct e1000_hw *hw = &adapter->hw;
1835 struct e1000_ring *rx_ring = adapter->rx_ring;
1836 struct e1000_ring *tx_ring = adapter->tx_ring;
1837 int vector = 0;
1838 u32 ctrl_ext, ivar = 0;
1839
1840 adapter->eiac_mask = 0;
1841
1842 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1843 if (hw->mac.type == e1000_82574) {
1844 u32 rfctl = er32(RFCTL);
1845 rfctl |= E1000_RFCTL_ACK_DIS;
1846 ew32(RFCTL, rfctl);
1847 }
1848
1849#define E1000_IVAR_INT_ALLOC_VALID 0x8
1850 /* Configure Rx vector */
1851 rx_ring->ims_val = E1000_IMS_RXQ0;
1852 adapter->eiac_mask |= rx_ring->ims_val;
1853 if (rx_ring->itr_val)
1854 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1855 rx_ring->itr_register);
4662e82b 1856 else
c5083cf6 1857 writel(1, rx_ring->itr_register);
4662e82b
BA		 1858 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1859
1860 /* Configure Tx vector */
1861 tx_ring->ims_val = E1000_IMS_TXQ0;
1862 vector++;
1863 if (tx_ring->itr_val)
1864 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1865 tx_ring->itr_register);
4662e82b 1866 else
c5083cf6 1867 writel(1, tx_ring->itr_register);
4662e82b
BA		 1868 adapter->eiac_mask |= tx_ring->ims_val;
1869 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1870
1871 /* set vector for Other Causes, e.g. link changes */
1872 vector++;
1873 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1874 if (rx_ring->itr_val)
1875 writel(1000000000 / (rx_ring->itr_val * 256),
1876 hw->hw_addr + E1000_EITR_82574(vector));
1877 else
1878 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1879
1880 /* Cause Tx interrupts on every write back */
1881 ivar |= (1 << 31);
1882
1883 ew32(IVAR, ivar);
1884
1885 /* enable MSI-X PBA support */
1886 ctrl_ext = er32(CTRL_EXT);
1887 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1888
1889 /* Auto-Mask Other interrupts upon ICR read */
1890#define E1000_EIAC_MASK_82574 0x01F00000
1891 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1892 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1893 ew32(CTRL_EXT, ctrl_ext);
1894 e1e_flush();
1895}
1896
1897void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1898{
1899 if (adapter->msix_entries) {
1900 pci_disable_msix(adapter->pdev);
1901 kfree(adapter->msix_entries);
1902 adapter->msix_entries = NULL;
1903 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1904 pci_disable_msi(adapter->pdev);
1905 adapter->flags &= ~FLAG_MSI_ENABLED;
1906 }
4662e82b
BA		 1907}
1908
1909/**
1910 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1911 *
1912 * Attempt to configure interrupts using the best available
1913 * capabilities of the hardware and kernel.
1914 **/
1915void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1916{
1917 int err;
8e86acd7 1918 int i;
4662e82b
BA		 1919
1920 switch (adapter->int_mode) {
1921 case E1000E_INT_MODE_MSIX:
1922 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1923 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1924 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1925 sizeof(struct msix_entry),
1926 GFP_KERNEL);
1927 if (adapter->msix_entries) {
8e86acd7 1928 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1929 adapter->msix_entries[i].entry = i;
1930
1931 err = pci_enable_msix(adapter->pdev,
1932 adapter->msix_entries,
8e86acd7 1933 adapter->num_vectors);
b1cdfead 1934 if (err == 0)
4662e82b
BA		 1935 return;
1936 }
1937 /* MSI-X failed, so fall through and try MSI */
ef456f85 1938 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1939 e1000e_reset_interrupt_capability(adapter);
1940 }
1941 adapter->int_mode = E1000E_INT_MODE_MSI;
1942 /* Fall through */
1943 case E1000E_INT_MODE_MSI:
1944 if (!pci_enable_msi(adapter->pdev)) {
1945 adapter->flags |= FLAG_MSI_ENABLED;
1946 } else {
1947 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1948 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1949 }
1950 /* Fall through */
1951 case E1000E_INT_MODE_LEGACY:
1952 /* Don't do anything; this is the system default */
1953 break;
1954 }
8e86acd7
JK		 1955
1956 /* store the number of vectors being used */
1957 adapter->num_vectors = 1;
4662e82b
BA		 1958}
1959
1960/**
1961 * e1000_request_msix - Initialize MSI-X interrupts
1962 *
1963 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1964 * kernel.
1965 **/
1966static int e1000_request_msix(struct e1000_adapter *adapter)
1967{
1968 struct net_device *netdev = adapter->netdev;
1969 int err = 0, vector = 0;
1970
1971 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1972 snprintf(adapter->rx_ring->name,
1973 sizeof(adapter->rx_ring->name) - 1,
1974 "%s-rx-0", netdev->name);
4662e82b
BA		 1975 else
1976 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1977 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1978 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1979 netdev);
1980 if (err)
5015e53a 1981 return err;
c5083cf6
BA		 1982 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
1983 E1000_EITR_82574(vector);
4662e82b
BA		 1984 adapter->rx_ring->itr_val = adapter->itr;
1985 vector++;
1986
1987 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1988 snprintf(adapter->tx_ring->name,
1989 sizeof(adapter->tx_ring->name) - 1,
1990 "%s-tx-0", netdev->name);
4662e82b
BA		 1991 else
1992 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1993 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1994 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 1995 netdev);
1996 if (err)
5015e53a 1997 return err;
c5083cf6
BA		 1998 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
1999 E1000_EITR_82574(vector);
4662e82b
BA		 2000 adapter->tx_ring->itr_val = adapter->itr;
2001 vector++;
2002
2003 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2004 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2005 if (err)
5015e53a 2006 return err;
4662e82b
BA		 2007
2008 e1000_configure_msix(adapter);
5015e53a 2009
4662e82b 2010 return 0;
4662e82b
BA		 2011}
2012
f8d59f78
BA		 2013/**
2014 * e1000_request_irq - initialize interrupts
2015 *
2016 * Attempts to configure interrupts using the best available
2017 * capabilities of the hardware and kernel.
2018 **/
bc7f75fa
AK		 2019static int e1000_request_irq(struct e1000_adapter *adapter)
2020{
2021 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2022 int err;
2023
4662e82b
BA		 2024 if (adapter->msix_entries) {
2025 err = e1000_request_msix(adapter);
2026 if (!err)
2027 return err;
2028 /* fall back to MSI */
2029 e1000e_reset_interrupt_capability(adapter);
2030 adapter->int_mode = E1000E_INT_MODE_MSI;
2031 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2032 }
4662e82b 2033 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2034 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2035 netdev->name, netdev);
2036 if (!err)
2037 return err;
bc7f75fa 2038
4662e82b
BA		 2039 /* fall back to legacy interrupt */
2040 e1000e_reset_interrupt_capability(adapter);
2041 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2042 }
2043
a0607fd3 2044 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2045 netdev->name, netdev);
2046 if (err)
2047 e_err("Unable to allocate interrupt, Error: %d\n", err);
2048
bc7f75fa
AK		 2049 return err;
2050}
2051
2052static void e1000_free_irq(struct e1000_adapter *adapter)
2053{
2054 struct net_device *netdev = adapter->netdev;
2055
4662e82b
BA		 2056 if (adapter->msix_entries) {
2057 int vector = 0;
2058
2059 free_irq(adapter->msix_entries[vector].vector, netdev);
2060 vector++;
2061
2062 free_irq(adapter->msix_entries[vector].vector, netdev);
2063 vector++;
2064
2065 /* Other Causes interrupt vector */
2066 free_irq(adapter->msix_entries[vector].vector, netdev);
2067 return;
bc7f75fa 2068 }
4662e82b
BA		 2069
2070 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2071}
2072
2073/**
2074 * e1000_irq_disable - Mask off interrupt generation on the NIC
2075 **/
2076static void e1000_irq_disable(struct e1000_adapter *adapter)
2077{
2078 struct e1000_hw *hw = &adapter->hw;
2079
bc7f75fa 2080 ew32(IMC, ~0);
4662e82b
BA		 2081 if (adapter->msix_entries)
2082 ew32(EIAC_82574, 0);
bc7f75fa 2083 e1e_flush();
8e86acd7
JK		 2084
2085 if (adapter->msix_entries) {
2086 int i;
2087 for (i = 0; i < adapter->num_vectors; i++)
2088 synchronize_irq(adapter->msix_entries[i].vector);
2089 } else {
2090 synchronize_irq(adapter->pdev->irq);
2091 }
bc7f75fa
AK		 2092}
2093
2094/**
2095 * e1000_irq_enable - Enable default interrupt generation settings
2096 **/
2097static void e1000_irq_enable(struct e1000_adapter *adapter)
2098{
2099 struct e1000_hw *hw = &adapter->hw;
2100
4662e82b
BA		 2101 if (adapter->msix_entries) {
2102 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2103 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2104 } else {
2105 ew32(IMS, IMS_ENABLE_MASK);
2106 }
74ef9c39 2107 e1e_flush();
bc7f75fa
AK		 2108}
2109
2110/**
31dbe5b4 2111 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2112 * @adapter: address of board private structure
2113 *
31dbe5b4 2114 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2115 * For ASF and Pass Through versions of f/w this means that
2116 * the driver is loaded. For AMT version (only with 82573)
2117 * of the f/w this means that the network i/f is open.
2118 **/
31dbe5b4 2119void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2120{
2121 struct e1000_hw *hw = &adapter->hw;
2122 u32 ctrl_ext;
2123 u32 swsm;
2124
2125 /* Let firmware know the driver has taken over */
2126 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2127 swsm = er32(SWSM);
2128 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2129 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2130 ctrl_ext = er32(CTRL_EXT);
ad68076e 2131 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2132 }
2133}
2134
2135/**
31dbe5b4 2136 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2137 * @adapter: address of board private structure
2138 *
31dbe5b4 2139 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2140 * For ASF and Pass Through versions of f/w this means that the
2141 * driver is no longer loaded. For AMT version (only with 82573) i
2142 * of the f/w this means that the network i/f is closed.
2143 *
2144 **/
31dbe5b4 2145void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2146{
2147 struct e1000_hw *hw = &adapter->hw;
2148 u32 ctrl_ext;
2149 u32 swsm;
2150
2151 /* Let firmware taken over control of h/w */
2152 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2153 swsm = er32(SWSM);
2154 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2155 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2156 ctrl_ext = er32(CTRL_EXT);
ad68076e 2157 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2158 }
2159}
2160
bc7f75fa 2161/**
49ce9c2c 2162 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2163 **/
2164static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2165 struct e1000_ring *ring)
2166{
2167 struct pci_dev *pdev = adapter->pdev;
2168
2169 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2170 GFP_KERNEL);
2171 if (!ring->desc)
2172 return -ENOMEM;
2173
2174 return 0;
2175}
2176
2177/**
2178 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2179 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2180 *
2181 * Return 0 on success, negative on failure
2182 **/
55aa6985 2183int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2184{
55aa6985 2185 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2186 int err = -ENOMEM, size;
2187
2188 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2189 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2190 if (!tx_ring->buffer_info)
2191 goto err;
bc7f75fa
AK		 2192
2193 /* round up to nearest 4K */
2194 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2195 tx_ring->size = ALIGN(tx_ring->size, 4096);
2196
2197 err = e1000_alloc_ring_dma(adapter, tx_ring);
2198 if (err)
2199 goto err;
2200
2201 tx_ring->next_to_use = 0;
2202 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2203
2204 return 0;
2205err:
2206 vfree(tx_ring->buffer_info);
44defeb3 2207 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2208 return err;
2209}
2210
2211/**
2212 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2213 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2214 *
2215 * Returns 0 on success, negative on failure
2216 **/
55aa6985 2217int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2218{
55aa6985 2219 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2220 struct e1000_buffer *buffer_info;
2221 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2222
2223 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2224 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2225 if (!rx_ring->buffer_info)
2226 goto err;
bc7f75fa 2227
47f44e40
AK		 2228 for (i = 0; i < rx_ring->count; i++) {
2229 buffer_info = &rx_ring->buffer_info[i];
2230 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2231 sizeof(struct e1000_ps_page),
2232 GFP_KERNEL);
2233 if (!buffer_info->ps_pages)
2234 goto err_pages;
2235 }
bc7f75fa
AK		 2236
2237 desc_len = sizeof(union e1000_rx_desc_packet_split);
2238
2239 /* Round up to nearest 4K */
2240 rx_ring->size = rx_ring->count * desc_len;
2241 rx_ring->size = ALIGN(rx_ring->size, 4096);
2242
2243 err = e1000_alloc_ring_dma(adapter, rx_ring);
2244 if (err)
47f44e40 2245 goto err_pages;
bc7f75fa
AK		 2246
2247 rx_ring->next_to_clean = 0;
2248 rx_ring->next_to_use = 0;
2249 rx_ring->rx_skb_top = NULL;
2250
2251 return 0;
47f44e40
AK		 2252
2253err_pages:
2254 for (i = 0; i < rx_ring->count; i++) {
2255 buffer_info = &rx_ring->buffer_info[i];
2256 kfree(buffer_info->ps_pages);
2257 }
bc7f75fa
AK		 2258err:
2259 vfree(rx_ring->buffer_info);
e9262447 2260 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2261 return err;
2262}
2263
2264/**
2265 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2266 * @tx_ring: Tx descriptor ring
bc7f75fa 2267 **/
55aa6985 2268static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2269{
55aa6985 2270 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2271 struct e1000_buffer *buffer_info;
2272 unsigned long size;
2273 unsigned int i;
2274
2275 for (i = 0; i < tx_ring->count; i++) {
2276 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2277 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2278 }
2279
3f0cfa3b 2280 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2281 size = sizeof(struct e1000_buffer) * tx_ring->count;
2282 memset(tx_ring->buffer_info, 0, size);
2283
2284 memset(tx_ring->desc, 0, tx_ring->size);
2285
2286 tx_ring->next_to_use = 0;
2287 tx_ring->next_to_clean = 0;
2288
c5083cf6 2289 writel(0, tx_ring->head);
bdc125f7
BA		 2290 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2291 e1000e_update_tdt_wa(tx_ring, 0);
2292 else
2293 writel(0, tx_ring->tail);
bc7f75fa
AK		 2294}
2295
2296/**
2297 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2298 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2299 *
2300 * Free all transmit software resources
2301 **/
55aa6985 2302void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2303{
55aa6985 2304 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2305 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2306
55aa6985 2307 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2308
2309 vfree(tx_ring->buffer_info);
2310 tx_ring->buffer_info = NULL;
2311
2312 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2313 tx_ring->dma);
2314 tx_ring->desc = NULL;
2315}
2316
2317/**
2318 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2319 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2320 *
2321 * Free all receive software resources
2322 **/
55aa6985 2323void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2324{
55aa6985 2325 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2326 struct pci_dev *pdev = adapter->pdev;
47f44e40 2327 int i;
bc7f75fa 2328
55aa6985 2329 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2330
b1cdfead 2331 for (i = 0; i < rx_ring->count; i++)
47f44e40 2332 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2333
bc7f75fa
AK		 2334 vfree(rx_ring->buffer_info);
2335 rx_ring->buffer_info = NULL;
2336
bc7f75fa
AK		 2337 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2338 rx_ring->dma);
2339 rx_ring->desc = NULL;
2340}
2341
2342/**
2343 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2344 * @adapter: pointer to adapter
2345 * @itr_setting: current adapter->itr
2346 * @packets: the number of packets during this measurement interval
2347 * @bytes: the number of bytes during this measurement interval
2348 *
bc7f75fa
AK		 2349 * Stores a new ITR value based on packets and byte
2350 * counts during the last interrupt. The advantage of per interrupt
2351 * computation is faster updates and more accurate ITR for the current
2352 * traffic pattern. Constants in this function were computed
2353 * based on theoretical maximum wire speed and thresholds were set based
2354 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2355 * while increasing bulk throughput. This functionality is controlled
2356 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2357 **/
2358static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2359 u16 itr_setting, int packets,
2360 int bytes)
2361{
2362 unsigned int retval = itr_setting;
2363
2364 if (packets == 0)
5015e53a 2365 return itr_setting;
bc7f75fa
AK		 2366
2367 switch (itr_setting) {
2368 case lowest_latency:
2369 /* handle TSO and jumbo frames */
2370 if (bytes/packets > 8000)
2371 retval = bulk_latency;
b1cdfead 2372 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2373 retval = low_latency;
bc7f75fa
AK		 2374 break;
2375 case low_latency: /* 50 usec aka 20000 ints/s */
2376 if (bytes > 10000) {
2377 /* this if handles the TSO accounting */
b1cdfead 2378 if (bytes/packets > 8000)
bc7f75fa 2379 retval = bulk_latency;
b1cdfead 2380 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2381 retval = bulk_latency;
b1cdfead 2382 else if ((packets > 35))
bc7f75fa 2383 retval = lowest_latency;
bc7f75fa
AK		 2384 } else if (bytes/packets > 2000) {
2385 retval = bulk_latency;
2386 } else if (packets <= 2 && bytes < 512) {
2387 retval = lowest_latency;
2388 }
2389 break;
2390 case bulk_latency: /* 250 usec aka 4000 ints/s */
2391 if (bytes > 25000) {
b1cdfead 2392 if (packets > 35)
bc7f75fa 2393 retval = low_latency;
bc7f75fa
AK		 2394 } else if (bytes < 6000) {
2395 retval = low_latency;
2396 }
2397 break;
2398 }
2399
bc7f75fa
AK		 2400 return retval;
2401}
2402
2403static void e1000_set_itr(struct e1000_adapter *adapter)
2404{
2405 struct e1000_hw *hw = &adapter->hw;
2406 u16 current_itr;
2407 u32 new_itr = adapter->itr;
2408
2409 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2410 if (adapter->link_speed != SPEED_1000) {
2411 current_itr = 0;
2412 new_itr = 4000;
2413 goto set_itr_now;
2414 }
2415
828bac87
BA		 2416 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2417 new_itr = 0;
2418 goto set_itr_now;
2419 }
2420
bc7f75fa
AK		 2421 adapter->tx_itr = e1000_update_itr(adapter,
2422 adapter->tx_itr,
2423 adapter->total_tx_packets,
2424 adapter->total_tx_bytes);
2425 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2426 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2427 adapter->tx_itr = low_latency;
2428
2429 adapter->rx_itr = e1000_update_itr(adapter,
2430 adapter->rx_itr,
2431 adapter->total_rx_packets,
2432 adapter->total_rx_bytes);
2433 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2434 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2435 adapter->rx_itr = low_latency;
2436
2437 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2438
2439 switch (current_itr) {
2440 /* counts and packets in update_itr are dependent on these numbers */
2441 case lowest_latency:
2442 new_itr = 70000;
2443 break;
2444 case low_latency:
2445 new_itr = 20000; /* aka hwitr = ~200 */
2446 break;
2447 case bulk_latency:
2448 new_itr = 4000;
2449 break;
2450 default:
2451 break;
2452 }
2453
2454set_itr_now:
2455 if (new_itr != adapter->itr) {
ad68076e
BA		 2456 /*
2457 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2458 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2459 * increasing
2460 */
bc7f75fa
AK		 2461 new_itr = new_itr > adapter->itr ?
2462 min(adapter->itr + (new_itr >> 2), new_itr) :
2463 new_itr;
2464 adapter->itr = new_itr;
4662e82b
BA		 2465 adapter->rx_ring->itr_val = new_itr;
2466 if (adapter->msix_entries)
2467 adapter->rx_ring->set_itr = 1;
2468 else
828bac87
BA		 2469 if (new_itr)
2470 ew32(ITR, 1000000000 / (new_itr * 256));
2471 else
2472 ew32(ITR, 0);
bc7f75fa
AK		 2473 }
2474}
2475
22a4cca2
MV		 2476/**
2477 * e1000e_write_itr - write the ITR value to the appropriate registers
2478 * @adapter: address of board private structure
2479 * @itr: new ITR value to program
2480 *
2481 * e1000e_write_itr determines if the adapter is in MSI-X mode
2482 * and, if so, writes the EITR registers with the ITR value.
2483 * Otherwise, it writes the ITR value into the ITR register.
2484 **/
2485void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2486{
2487 struct e1000_hw *hw = &adapter->hw;
2488 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2489
2490 if (adapter->msix_entries) {
2491 int vector;
2492
2493 for (vector = 0; vector < adapter->num_vectors; vector++)
2494 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2495 } else {
2496 ew32(ITR, new_itr);
2497 }
2498}
2499
4662e82b
BA		 2500/**
2501 * e1000_alloc_queues - Allocate memory for all rings
2502 * @adapter: board private structure to initialize
2503 **/
2504static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2505{
55aa6985
BA		 2506 int size = sizeof(struct e1000_ring);
2507
2508 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2509 if (!adapter->tx_ring)
2510 goto err;
55aa6985
BA		 2511 adapter->tx_ring->count = adapter->tx_ring_count;
2512 adapter->tx_ring->adapter = adapter;
4662e82b 2513
55aa6985 2514 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2515 if (!adapter->rx_ring)
2516 goto err;
55aa6985
BA		 2517 adapter->rx_ring->count = adapter->rx_ring_count;
2518 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2519
2520 return 0;
2521err:
2522 e_err("Unable to allocate memory for queues\n");
2523 kfree(adapter->rx_ring);
2524 kfree(adapter->tx_ring);
2525 return -ENOMEM;
2526}
2527
bc7f75fa 2528/**
c58c8a78 2529 * e1000e_poll - NAPI Rx polling callback
ad68076e 2530 * @napi: struct associated with this polling callback
c58c8a78 2531 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2532 **/
c58c8a78 2533static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2534{
c58c8a78
BA		 2535 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2536 napi);
4662e82b 2537 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2538 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2539 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2540
4cf1653a 2541 adapter = netdev_priv(poll_dev);
bc7f75fa 2542
c58c8a78
BA		 2543 if (!adapter->msix_entries ||
2544 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2545 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2546
c58c8a78 2547 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2548
12d04a3c 2549 if (!tx_cleaned)
c58c8a78 2550 work_done = weight;
bc7f75fa 2551
c58c8a78
BA		 2552 /* If weight not fully consumed, exit the polling mode */
2553 if (work_done < weight) {
bc7f75fa
AK		 2554 if (adapter->itr_setting & 3)
2555 e1000_set_itr(adapter);
288379f0 2556 napi_complete(napi);
a3c69fef
JB		 2557 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2558 if (adapter->msix_entries)
2559 ew32(IMS, adapter->rx_ring->ims_val);
2560 else
2561 e1000_irq_enable(adapter);
2562 }
bc7f75fa
AK		 2563 }
2564
2565 return work_done;
2566}
2567
8e586137 2568static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2569{
2570 struct e1000_adapter *adapter = netdev_priv(netdev);
2571 struct e1000_hw *hw = &adapter->hw;
2572 u32 vfta, index;
2573
2574 /* don't update vlan cookie if already programmed */
2575 if ((adapter->hw.mng_cookie.status &
2576 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2577 (vid == adapter->mng_vlan_id))
8e586137 2578 return 0;
caaddaf8 2579
bc7f75fa 2580 /* add VID to filter table */
caaddaf8
BA		 2581 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2582 index = (vid >> 5) & 0x7F;
2583 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2584 vfta |= (1 << (vid & 0x1F));
2585 hw->mac.ops.write_vfta(hw, index, vfta);
2586 }
86d70e53
JK		 2587
2588 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2589
2590 return 0;
bc7f75fa
AK		 2591}
2592
8e586137 2593static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2594{
2595 struct e1000_adapter *adapter = netdev_priv(netdev);
2596 struct e1000_hw *hw = &adapter->hw;
2597 u32 vfta, index;
2598
bc7f75fa
AK		 2599 if ((adapter->hw.mng_cookie.status &
2600 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2601 (vid == adapter->mng_vlan_id)) {
2602 /* release control to f/w */
31dbe5b4 2603 e1000e_release_hw_control(adapter);
8e586137 2604 return 0;
bc7f75fa
AK		 2605 }
2606
2607 /* remove VID from filter table */
caaddaf8
BA		 2608 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2609 index = (vid >> 5) & 0x7F;
2610 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2611 vfta &= ~(1 << (vid & 0x1F));
2612 hw->mac.ops.write_vfta(hw, index, vfta);
2613 }
86d70e53
JK		 2614
2615 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2616
2617 return 0;
bc7f75fa
AK		 2618}
2619
86d70e53
JK		 2620/**
2621 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2622 * @adapter: board private structure to initialize
2623 **/
2624static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2625{
2626 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2627 struct e1000_hw *hw = &adapter->hw;
2628 u32 rctl;
bc7f75fa 2629
86d70e53
JK		 2630 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2631 /* disable VLAN receive filtering */
2632 rctl = er32(RCTL);
2633 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2634 ew32(RCTL, rctl);
2635
2636 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2637 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2638 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2639 }
bc7f75fa
AK		 2640 }
2641}
2642
86d70e53
JK		 2643/**
2644 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2645 * @adapter: board private structure to initialize
2646 **/
2647static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2648{
2649 struct e1000_hw *hw = &adapter->hw;
2650 u32 rctl;
2651
2652 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2653 /* enable VLAN receive filtering */
2654 rctl = er32(RCTL);
2655 rctl |= E1000_RCTL_VFE;
2656 rctl &= ~E1000_RCTL_CFIEN;
2657 ew32(RCTL, rctl);
2658 }
2659}
bc7f75fa 2660
86d70e53
JK		 2661/**
2662 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2663 * @adapter: board private structure to initialize
2664 **/
2665static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2666{
bc7f75fa 2667 struct e1000_hw *hw = &adapter->hw;
86d70e53 2668 u32 ctrl;
bc7f75fa 2669
86d70e53
JK		 2670 /* disable VLAN tag insert/strip */
2671 ctrl = er32(CTRL);
2672 ctrl &= ~E1000_CTRL_VME;
2673 ew32(CTRL, ctrl);
2674}
bc7f75fa 2675
86d70e53
JK		 2676/**
2677 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2678 * @adapter: board private structure to initialize
2679 **/
2680static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2681{
2682 struct e1000_hw *hw = &adapter->hw;
2683 u32 ctrl;
bc7f75fa 2684
86d70e53
JK		 2685 /* enable VLAN tag insert/strip */
2686 ctrl = er32(CTRL);
2687 ctrl |= E1000_CTRL_VME;
2688 ew32(CTRL, ctrl);
2689}
bc7f75fa 2690
86d70e53
JK		 2691static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2692{
2693 struct net_device *netdev = adapter->netdev;
2694 u16 vid = adapter->hw.mng_cookie.vlan_id;
2695 u16 old_vid = adapter->mng_vlan_id;
2696
2697 if (adapter->hw.mng_cookie.status &
2698 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2699 e1000_vlan_rx_add_vid(netdev, vid);
2700 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2701 }
2702
86d70e53
JK		 2703 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2704 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2705}
2706
2707static void e1000_restore_vlan(struct e1000_adapter *adapter)
2708{
2709 u16 vid;
2710
86d70e53 2711 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2712
86d70e53 2713 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2714 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2715}
2716
cd791618 2717static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2718{
2719 struct e1000_hw *hw = &adapter->hw;
cd791618 2720 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2721
2722 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2723 return;
2724
2725 manc = er32(MANC);
2726
ad68076e
BA		 2727 /*
2728 * enable receiving management packets to the host. this will probably
bc7f75fa 2729 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2730 * the packets will be handled on SMBUS
2731 */
bc7f75fa
AK		 2732 manc |= E1000_MANC_EN_MNG2HOST;
2733 manc2h = er32(MANC2H);
cd791618
BA		 2734
2735 switch (hw->mac.type) {
2736 default:
2737 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2738 break;
2739 case e1000_82574:
2740 case e1000_82583:
2741 /*
2742 * Check if IPMI pass-through decision filter already exists;
2743 * if so, enable it.
2744 */
2745 for (i = 0, j = 0; i < 8; i++) {
2746 mdef = er32(MDEF(i));
2747
2748 /* Ignore filters with anything other than IPMI ports */
3b21b508 2749 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2750 continue;
2751
2752 /* Enable this decision filter in MANC2H */
2753 if (mdef)
2754 manc2h |= (1 << i);
2755
2756 j |= mdef;
2757 }
2758
2759 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2760 break;
2761
2762 /* Create new decision filter in an empty filter */
2763 for (i = 0, j = 0; i < 8; i++)
2764 if (er32(MDEF(i)) == 0) {
2765 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2766 E1000_MDEF_PORT_664));
2767 manc2h |= (1 << 1);
2768 j++;
2769 break;
2770 }
2771
2772 if (!j)
2773 e_warn("Unable to create IPMI pass-through filter\n");
2774 break;
2775 }
2776
bc7f75fa
AK		 2777 ew32(MANC2H, manc2h);
2778 ew32(MANC, manc);
2779}
2780
2781/**
af667a29 2782 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2783 * @adapter: board private structure
2784 *
2785 * Configure the Tx unit of the MAC after a reset.
2786 **/
2787static void e1000_configure_tx(struct e1000_adapter *adapter)
2788{
2789 struct e1000_hw *hw = &adapter->hw;
2790 struct e1000_ring *tx_ring = adapter->tx_ring;
2791 u64 tdba;
c550b121 2792 u32 tdlen, tarc;
bc7f75fa
AK		 2793
2794 /* Setup the HW Tx Head and Tail descriptor pointers */
2795 tdba = tx_ring->dma;
2796 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2797 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2798 ew32(TDBAH(0), (tdba >> 32));
2799 ew32(TDLEN(0), tdlen);
2800 ew32(TDH(0), 0);
2801 ew32(TDT(0), 0);
2802 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2803 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2804
bc7f75fa
AK		 2805 /* Set the Tx Interrupt Delay register */
2806 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2807 /* Tx irq moderation */
bc7f75fa
AK		 2808 ew32(TADV, adapter->tx_abs_int_delay);
2809
3a3b7586
JB		 2810 if (adapter->flags2 & FLAG2_DMA_BURST) {
2811 u32 txdctl = er32(TXDCTL(0));
2812 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2813 E1000_TXDCTL_WTHRESH);
2814 /*
2815 * set up some performance related parameters to encourage the
2816 * hardware to use the bus more efficiently in bursts, depends
2817 * on the tx_int_delay to be enabled,
2818 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2819 * hthresh = 1 ==> prefetch when one or more available
2820 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2821 * BEWARE: this seems to work but should be considered first if
af667a29 2822 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2823 */
2824 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2825 ew32(TXDCTL(0), txdctl);
3a3b7586 2826 }
56032be7
BA		 2827 /* erratum work around: set txdctl the same for both queues */
2828 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2829
bc7f75fa 2830 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2831 tarc = er32(TARC(0));
ad68076e
BA		 2832 /*
2833 * set the speed mode bit, we'll clear it if we're not at
2834 * gigabit link later
2835 */
bc7f75fa
AK		 2836#define SPEED_MODE_BIT (1 << 21)
2837 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2838 ew32(TARC(0), tarc);
bc7f75fa
AK		 2839 }
2840
2841 /* errata: program both queues to unweighted RR */
2842 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2843 tarc = er32(TARC(0));
bc7f75fa 2844 tarc |= 1;
e9ec2c0f
JK		 2845 ew32(TARC(0), tarc);
2846 tarc = er32(TARC(1));
bc7f75fa 2847 tarc |= 1;
e9ec2c0f 2848 ew32(TARC(1), tarc);
bc7f75fa
AK		 2849 }
2850
bc7f75fa
AK		 2851 /* Setup Transmit Descriptor Settings for eop descriptor */
2852 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2853
2854 /* only set IDE if we are delaying interrupts using the timers */
2855 if (adapter->tx_int_delay)
2856 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2857
2858 /* enable Report Status bit */
2859 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2860
57cde763 2861 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2862}
2863
2864/**
2865 * e1000_setup_rctl - configure the receive control registers
2866 * @adapter: Board private structure
2867 **/
2868#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2869 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2870static void e1000_setup_rctl(struct e1000_adapter *adapter)
2871{
2872 struct e1000_hw *hw = &adapter->hw;
2873 u32 rctl, rfctl;
bc7f75fa
AK		 2874 u32 pages = 0;
2875
2fbe4526
BA		 2876 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2877 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2878 s32 ret_val;
2879
2880 if (adapter->netdev->mtu > ETH_DATA_LEN)
2881 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2882 else
2883 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2884
2885 if (ret_val)
2886 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2887 }
2888
bc7f75fa
AK		 2889 /* Program MC offset vector base */
2890 rctl = er32(RCTL);
2891 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2892 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2893 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2894 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2895
2896 /* Do not Store bad packets */
2897 rctl &= ~E1000_RCTL_SBP;
2898
2899 /* Enable Long Packet receive */
2900 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2901 rctl &= ~E1000_RCTL_LPE;
2902 else
2903 rctl |= E1000_RCTL_LPE;
2904
eb7c3adb
JK		 2905 /* Some systems expect that the CRC is included in SMBUS traffic. The
2906 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2907 * host memory when this is enabled
2908 */
2909 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2910 rctl |= E1000_RCTL_SECRC;
5918bd88 2911
a4f58f54
BA		 2912 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2913 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2914 u16 phy_data;
2915
2916 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2917 phy_data &= 0xfff8;
2918 phy_data |= (1 << 2);
2919 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2920
2921 e1e_rphy(hw, 22, &phy_data);
2922 phy_data &= 0x0fff;
2923 phy_data |= (1 << 14);
2924 e1e_wphy(hw, 0x10, 0x2823);
2925 e1e_wphy(hw, 0x11, 0x0003);
2926 e1e_wphy(hw, 22, phy_data);
2927 }
2928
bc7f75fa
AK		 2929 /* Setup buffer sizes */
2930 rctl &= ~E1000_RCTL_SZ_4096;
2931 rctl |= E1000_RCTL_BSEX;
2932 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2933 case 2048:
2934 default:
2935 rctl |= E1000_RCTL_SZ_2048;
2936 rctl &= ~E1000_RCTL_BSEX;
2937 break;
2938 case 4096:
2939 rctl |= E1000_RCTL_SZ_4096;
2940 break;
2941 case 8192:
2942 rctl |= E1000_RCTL_SZ_8192;
2943 break;
2944 case 16384:
2945 rctl |= E1000_RCTL_SZ_16384;
2946 break;
2947 }
2948
5f450212
BA		 2949 /* Enable Extended Status in all Receive Descriptors */
2950 rfctl = er32(RFCTL);
2951 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 2952 ew32(RFCTL, rfctl);
5f450212 2953
bc7f75fa
AK		 2954 /*
2955 * 82571 and greater support packet-split where the protocol
2956 * header is placed in skb->data and the packet data is
2957 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2958 * In the case of a non-split, skb->data is linearly filled,
2959 * followed by the page buffers. Therefore, skb->data is
2960 * sized to hold the largest protocol header.
2961 *
2962 * allocations using alloc_page take too long for regular MTU
2963 * so only enable packet split for jumbo frames
2964 *
2965 * Using pages when the page size is greater than 16k wastes
2966 * a lot of memory, since we allocate 3 pages at all times
2967 * per packet.
2968 */
bc7f75fa 2969 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2970 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2971 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2972 else
2973 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2974
2975 if (adapter->rx_ps_pages) {
90da0669
BA		 2976 u32 psrctl = 0;
2977
140a7480
AK		 2978 /* Enable Packet split descriptors */
2979 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2980
2981 psrctl |= adapter->rx_ps_bsize0 >>
2982 E1000_PSRCTL_BSIZE0_SHIFT;
2983
2984 switch (adapter->rx_ps_pages) {
2985 case 3:
2986 psrctl |= PAGE_SIZE <<
2987 E1000_PSRCTL_BSIZE3_SHIFT;
2988 case 2:
2989 psrctl |= PAGE_SIZE <<
2990 E1000_PSRCTL_BSIZE2_SHIFT;
2991 case 1:
2992 psrctl |= PAGE_SIZE >>
2993 E1000_PSRCTL_BSIZE1_SHIFT;
2994 break;
2995 }
2996
2997 ew32(PSRCTL, psrctl);
2998 }
2999
cf955e6c
BG		 3000 /* This is useful for sniffing bad packets. */
3001 if (adapter->netdev->features & NETIF_F_RXALL) {
3002 /* UPE and MPE will be handled by normal PROMISC logic
3003 * in e1000e_set_rx_mode */
3004 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3005 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3006 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3007
3008 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3009 E1000_RCTL_DPF | /* Allow filtered pause */
3010 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3011 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3012 * and that breaks VLANs.
3013 */
3014 }
3015
bc7f75fa 3016 ew32(RCTL, rctl);
318a94d6
JK		 3017 /* just started the receive unit, no need to restart */
3018 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3019}
3020
3021/**
3022 * e1000_configure_rx - Configure Receive Unit after Reset
3023 * @adapter: board private structure
3024 *
3025 * Configure the Rx unit of the MAC after a reset.
3026 **/
3027static void e1000_configure_rx(struct e1000_adapter *adapter)
3028{
3029 struct e1000_hw *hw = &adapter->hw;
3030 struct e1000_ring *rx_ring = adapter->rx_ring;
3031 u64 rdba;
3032 u32 rdlen, rctl, rxcsum, ctrl_ext;
3033
3034 if (adapter->rx_ps_pages) {
3035 /* this is a 32 byte descriptor */
3036 rdlen = rx_ring->count *
af667a29 3037 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3038 adapter->clean_rx = e1000_clean_rx_irq_ps;
3039 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3040 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3041 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3042 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3043 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3044 } else {
5f450212 3045 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3046 adapter->clean_rx = e1000_clean_rx_irq;
3047 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3048 }
3049
3050 /* disable receives while setting up the descriptors */
3051 rctl = er32(RCTL);
7f99ae63
BA		 3052 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3053 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3054 e1e_flush();
1bba4386 3055 usleep_range(10000, 20000);
bc7f75fa 3056
3a3b7586
JB		 3057 if (adapter->flags2 & FLAG2_DMA_BURST) {
3058 /*
3059 * set the writeback threshold (only takes effect if the RDTR
3060 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3061 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3062 * granularity = 01
3063 * wthresh = 04,
3064 * hthresh = 04,
3065 * pthresh = 0x20
3066 */
3067 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3068 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3069
3070 /*
3071 * override the delay timers for enabling bursting, only if
3072 * the value was not set by the user via module options
3073 */
3074 if (adapter->rx_int_delay == DEFAULT_RDTR)
3075 adapter->rx_int_delay = BURST_RDTR;
3076 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3077 adapter->rx_abs_int_delay = BURST_RADV;
3078 }
3079
bc7f75fa
AK		 3080 /* set the Receive Delay Timer Register */
3081 ew32(RDTR, adapter->rx_int_delay);
3082
3083 /* irq moderation */
3084 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3085 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3086 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3087
3088 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3089 /* Auto-Mask interrupts upon ICR access */
3090 ctrl_ext |= E1000_CTRL_EXT_IAME;
3091 ew32(IAM, 0xffffffff);
3092 ew32(CTRL_EXT, ctrl_ext);
3093 e1e_flush();
3094
ad68076e
BA		 3095 /*
3096 * Setup the HW Rx Head and Tail Descriptor Pointers and
3097 * the Base and Length of the Rx Descriptor Ring
3098 */
bc7f75fa 3099 rdba = rx_ring->dma;
1e36052e
BA		 3100 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3101 ew32(RDBAH(0), (rdba >> 32));
3102 ew32(RDLEN(0), rdlen);
3103 ew32(RDH(0), 0);
3104 ew32(RDT(0), 0);
3105 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3106 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3107
3108 /* Enable Receive Checksum Offload for TCP and UDP */
3109 rxcsum = er32(RXCSUM);
2e1706f2 3110 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3111 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3112 else
bc7f75fa 3113 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3114 ew32(RXCSUM, rxcsum);
3115
79d4e908
BA		 3116 if (adapter->hw.mac.type == e1000_pch2lan) {
3117 /*
3118 * With jumbo frames, excessive C-state transition
3119 * latencies result in dropped transactions.
3120 */
53ec5498
BA		 3121 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3122 u32 rxdctl = er32(RXDCTL(0));
3123 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3124 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3125 } else {
af667a29
BA		 3126 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3127 PM_QOS_DEFAULT_VALUE);
53ec5498 3128 }
97ac8cae 3129 }
bc7f75fa
AK		 3130
3131 /* Enable Receives */
3132 ew32(RCTL, rctl);
3133}
3134
3135/**
ef9b965a
JB		 3136 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3137 * @netdev: network interface device structure
bc7f75fa 3138 *
ef9b965a
JB		 3139 * Writes multicast address list to the MTA hash table.
3140 * Returns: -ENOMEM on failure
3141 * 0 on no addresses written
3142 * X on writing X addresses to MTA
3143 */
3144static int e1000e_write_mc_addr_list(struct net_device *netdev)
3145{
3146 struct e1000_adapter *adapter = netdev_priv(netdev);
3147 struct e1000_hw *hw = &adapter->hw;
3148 struct netdev_hw_addr *ha;
3149 u8 *mta_list;
3150 int i;
3151
3152 if (netdev_mc_empty(netdev)) {
3153 /* nothing to program, so clear mc list */
3154 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3155 return 0;
3156 }
3157
3158 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3159 if (!mta_list)
3160 return -ENOMEM;
3161
3162 /* update_mc_addr_list expects a packed array of only addresses. */
3163 i = 0;
3164 netdev_for_each_mc_addr(ha, netdev)
3165 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3166
3167 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3168 kfree(mta_list);
3169
3170 return netdev_mc_count(netdev);
3171}
3172
3173/**
3174 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3175 * @netdev: network interface device structure
bc7f75fa 3176 *
ef9b965a
JB		 3177 * Writes unicast address list to the RAR table.
3178 * Returns: -ENOMEM on failure/insufficient address space
3179 * 0 on no addresses written
3180 * X on writing X addresses to the RAR table
bc7f75fa 3181 **/
ef9b965a 3182static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3183{
ef9b965a
JB		 3184 struct e1000_adapter *adapter = netdev_priv(netdev);
3185 struct e1000_hw *hw = &adapter->hw;
3186 unsigned int rar_entries = hw->mac.rar_entry_count;
3187 int count = 0;
3188
3189 /* save a rar entry for our hardware address */
3190 rar_entries--;
3191
3192 /* save a rar entry for the LAA workaround */
3193 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3194 rar_entries--;
3195
3196 /* return ENOMEM indicating insufficient memory for addresses */
3197 if (netdev_uc_count(netdev) > rar_entries)
3198 return -ENOMEM;
3199
3200 if (!netdev_uc_empty(netdev) && rar_entries) {
3201 struct netdev_hw_addr *ha;
3202
3203 /*
3204 * write the addresses in reverse order to avoid write
3205 * combining
3206 */
3207 netdev_for_each_uc_addr(ha, netdev) {
3208 if (!rar_entries)
3209 break;
69e1e019 3210 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3211 count++;
3212 }
3213 }
3214
3215 /* zero out the remaining RAR entries not used above */
3216 for (; rar_entries > 0; rar_entries--) {
3217 ew32(RAH(rar_entries), 0);
3218 ew32(RAL(rar_entries), 0);
3219 }
3220 e1e_flush();
3221
3222 return count;
bc7f75fa
AK		 3223}
3224
3225/**
ef9b965a 3226 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3227 * @netdev: network interface device structure
3228 *
ef9b965a
JB		 3229 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3230 * address list or the network interface flags are updated. This routine is
3231 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3232 * promiscuous mode, and all-multi behavior.
3233 **/
ef9b965a 3234static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3235{
3236 struct e1000_adapter *adapter = netdev_priv(netdev);
3237 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3238 u32 rctl;
bc7f75fa
AK		 3239
3240 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3241 rctl = er32(RCTL);
3242
ef9b965a
JB		 3243 /* clear the affected bits */
3244 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3245
bc7f75fa
AK		 3246 if (netdev->flags & IFF_PROMISC) {
3247 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3248 /* Do not hardware filter VLANs in promisc mode */
3249 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3250 } else {
ef9b965a 3251 int count;
3d3a1676 3252
746b9f02
PM		 3253 if (netdev->flags & IFF_ALLMULTI) {
3254 rctl |= E1000_RCTL_MPE;
746b9f02 3255 } else {
ef9b965a
JB		 3256 /*
3257 * Write addresses to the MTA, if the attempt fails
3258 * then we should just turn on promiscuous mode so
3259 * that we can at least receive multicast traffic
3260 */
3261 count = e1000e_write_mc_addr_list(netdev);
3262 if (count < 0)
3263 rctl |= E1000_RCTL_MPE;
746b9f02 3264 }
86d70e53 3265 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3266 /*
ef9b965a
JB		 3267 * Write addresses to available RAR registers, if there is not
3268 * sufficient space to store all the addresses then enable
3269 * unicast promiscuous mode
bc7f75fa 3270 */
ef9b965a
JB		 3271 count = e1000e_write_uc_addr_list(netdev);
3272 if (count < 0)
3273 rctl |= E1000_RCTL_UPE;
bc7f75fa 3274 }
86d70e53 3275
ef9b965a
JB		 3276 ew32(RCTL, rctl);
3277
86d70e53
JK		 3278 if (netdev->features & NETIF_F_HW_VLAN_RX)
3279 e1000e_vlan_strip_enable(adapter);
3280 else
3281 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3282}
3283
70495a50
BA		 3284static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3285{
3286 struct e1000_hw *hw = &adapter->hw;
3287 u32 mrqc, rxcsum;
3288 int i;
3289 static const u32 rsskey[10] = {
3290 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3291 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3292 };
3293
3294 /* Fill out hash function seed */
3295 for (i = 0; i < 10; i++)
3296 ew32(RSSRK(i), rsskey[i]);
3297
3298 /* Direct all traffic to queue 0 */
3299 for (i = 0; i < 32; i++)
3300 ew32(RETA(i), 0);
3301
3302 /*
3303 * Disable raw packet checksumming so that RSS hash is placed in
3304 * descriptor on writeback.
3305 */
3306 rxcsum = er32(RXCSUM);
3307 rxcsum |= E1000_RXCSUM_PCSD;
3308
3309 ew32(RXCSUM, rxcsum);
3310
3311 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3312 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3313 E1000_MRQC_RSS_FIELD_IPV6 |
3314 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3315 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3316
3317 ew32(MRQC, mrqc);
3318}
3319
bc7f75fa 3320/**
ad68076e 3321 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3322 * @adapter: private board structure
3323 **/
3324static void e1000_configure(struct e1000_adapter *adapter)
3325{
55aa6985
BA		 3326 struct e1000_ring *rx_ring = adapter->rx_ring;
3327
ef9b965a 3328 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3329
3330 e1000_restore_vlan(adapter);
cd791618 3331 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3332
3333 e1000_configure_tx(adapter);
70495a50
BA		 3334
3335 if (adapter->netdev->features & NETIF_F_RXHASH)
3336 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3337 e1000_setup_rctl(adapter);
3338 e1000_configure_rx(adapter);
55aa6985 3339 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3340}
3341
3342/**
3343 * e1000e_power_up_phy - restore link in case the phy was powered down
3344 * @adapter: address of board private structure
3345 *
3346 * The phy may be powered down to save power and turn off link when the
3347 * driver is unloaded and wake on lan is not enabled (among others)
3348 * *** this routine MUST be followed by a call to e1000e_reset ***
3349 **/
3350void e1000e_power_up_phy(struct e1000_adapter *adapter)
3351{
17f208de
BA		 3352 if (adapter->hw.phy.ops.power_up)
3353 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3354
3355 adapter->hw.mac.ops.setup_link(&adapter->hw);
3356}
3357
3358/**
3359 * e1000_power_down_phy - Power down the PHY
3360 *
17f208de
BA		 3361 * Power down the PHY so no link is implied when interface is down.
3362 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3363 */
3364static void e1000_power_down_phy(struct e1000_adapter *adapter)
3365{
bc7f75fa 3366 /* WoL is enabled */
23b66e2b 3367 if (adapter->wol)
bc7f75fa
AK		 3368 return;
3369
17f208de
BA		 3370 if (adapter->hw.phy.ops.power_down)
3371 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3372}
3373
3374/**
3375 * e1000e_reset - bring the hardware into a known good state
3376 *
3377 * This function boots the hardware and enables some settings that
3378 * require a configuration cycle of the hardware - those cannot be
3379 * set/changed during runtime. After reset the device needs to be
ad68076e 3380 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3381 */
3382void e1000e_reset(struct e1000_adapter *adapter)
3383{
3384 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3385 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3386 struct e1000_hw *hw = &adapter->hw;
3387 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3388 u32 pba = adapter->pba;
bc7f75fa
AK		 3389 u16 hwm;
3390
ad68076e 3391 /* reset Packet Buffer Allocation to default */
318a94d6 3392 ew32(PBA, pba);
df762464 3393
318a94d6 3394 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3395 /*
3396 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3397 * large enough to accommodate two full transmit packets,
3398 * rounded up to the next 1KB and expressed in KB. Likewise,
3399 * the Rx FIFO should be large enough to accommodate at least
3400 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3401 * expressed in KB.
3402 */
df762464 3403 pba = er32(PBA);
bc7f75fa 3404 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3405 tx_space = pba >> 16;
bc7f75fa 3406 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3407 pba &= 0xffff;
ad68076e 3408 /*
af667a29 3409 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3410 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3411 */
3412 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3413 sizeof(struct e1000_tx_desc) -
3414 ETH_FCS_LEN) * 2;
3415 min_tx_space = ALIGN(min_tx_space, 1024);
3416 min_tx_space >>= 10;
3417 /* software strips receive CRC, so leave room for it */
318a94d6 3418 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3419 min_rx_space = ALIGN(min_rx_space, 1024);
3420 min_rx_space >>= 10;
3421
ad68076e
BA		 3422 /*
3423 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3424 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3425 * allocation, take space away from current Rx allocation
3426 */
df762464
AK		 3427 if ((tx_space < min_tx_space) &&
3428 ((min_tx_space - tx_space) < pba)) {
3429 pba -= min_tx_space - tx_space;
bc7f75fa 3430
ad68076e 3431 /*
af667a29 3432 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3433 * adjustment or use Early Receive if available
3434 */
79d4e908 3435 if (pba < min_rx_space)
df762464 3436 pba = min_rx_space;
bc7f75fa 3437 }
df762464
AK		 3438
3439 ew32(PBA, pba);
bc7f75fa
AK		 3440 }
3441
ad68076e
BA		 3442 /*
3443 * flow control settings
3444 *
38eb394e 3445 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3446 * (or the size used for early receive) above it in the Rx FIFO.
3447 * Set it to the lower of:
3448 * - 90% of the Rx FIFO size, and
38eb394e 3449 * - the full Rx FIFO size minus one full frame
ad68076e 3450 */
d3738bb8
BA		 3451 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3452 fc->pause_time = 0xFFFF;
3453 else
3454 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3455 fc->send_xon = true;
d3738bb8
BA		 3456 fc->current_mode = fc->requested_mode;
3457
3458 switch (hw->mac.type) {
79d4e908
BA		 3459 case e1000_ich9lan:
3460 case e1000_ich10lan:
3461 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3462 pba = 14;
3463 ew32(PBA, pba);
3464 fc->high_water = 0x2800;
3465 fc->low_water = fc->high_water - 8;
3466 break;
3467 }
3468 /* fall-through */
d3738bb8 3469 default:
79d4e908
BA		 3470 hwm = min(((pba << 10) * 9 / 10),
3471 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3472
3473 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3474 fc->low_water = fc->high_water - 8;
3475 break;
3476 case e1000_pchlan:
38eb394e
BA		 3477 /*
3478 * Workaround PCH LOM adapter hangs with certain network
3479 * loads. If hangs persist, try disabling Tx flow control.
3480 */
3481 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3482 fc->high_water = 0x3500;
3483 fc->low_water = 0x1500;
3484 } else {
3485 fc->high_water = 0x5000;
3486 fc->low_water = 0x3000;
3487 }
a305595b 3488 fc->refresh_time = 0x1000;
d3738bb8
BA		 3489 break;
3490 case e1000_pch2lan:
2fbe4526 3491 case e1000_pch_lpt:
d3738bb8
BA		 3492 fc->high_water = 0x05C20;
3493 fc->low_water = 0x05048;
3494 fc->pause_time = 0x0650;
3495 fc->refresh_time = 0x0400;
828bac87
BA		 3496 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3497 pba = 14;
3498 ew32(PBA, pba);
3499 }
d3738bb8 3500 break;
38eb394e 3501 }
bc7f75fa 3502
828bac87
BA		 3503 /*
3504 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3505 * fit in receive buffer.
828bac87
BA		 3506 */
3507 if (adapter->itr_setting & 0x3) {
79d4e908 3508 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3509 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3510 dev_info(&adapter->pdev->dev,
3511 "Interrupt Throttle Rate turned off\n");
3512 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3513 e1000e_write_itr(adapter, 0);
828bac87
BA		 3514 }
3515 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3516 dev_info(&adapter->pdev->dev,
3517 "Interrupt Throttle Rate turned on\n");
3518 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3519 adapter->itr = 20000;
22a4cca2 3520 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3521 }
3522 }
3523
bc7f75fa
AK		 3524 /* Allow time for pending master requests to run */
3525 mac->ops.reset_hw(hw);
97ac8cae
BA		 3526
3527 /*
3528 * For parts with AMT enabled, let the firmware know
3529 * that the network interface is in control
3530 */
c43bc57e 3531 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3532 e1000e_get_hw_control(adapter);
97ac8cae 3533
bc7f75fa
AK		 3534 ew32(WUC, 0);
3535
3536 if (mac->ops.init_hw(hw))
44defeb3 3537 e_err("Hardware Error\n");
bc7f75fa
AK		 3538
3539 e1000_update_mng_vlan(adapter);
3540
3541 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3542 ew32(VET, ETH_P_8021Q);
3543
3544 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3545
3546 if (!netif_running(adapter->netdev) &&
3547 !test_bit(__E1000_TESTING, &adapter->state)) {
3548 e1000_power_down_phy(adapter);
3549 return;
3550 }
3551
bc7f75fa
AK		 3552 e1000_get_phy_info(hw);
3553
918d7197
BA		 3554 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3555 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3556 u16 phy_data = 0;
ad68076e
BA		 3557 /*
3558 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3559 * the return value of this function because there is nothing
ad68076e
BA		 3560 * different we would do if it failed
3561 */
bc7f75fa
AK		 3562 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3563 phy_data &= ~IGP02E1000_PM_SPD;
3564 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3565 }
bc7f75fa
AK		 3566}
3567
3568int e1000e_up(struct e1000_adapter *adapter)
3569{
3570 struct e1000_hw *hw = &adapter->hw;
3571
3572 /* hardware has been reset, we need to reload some things */
3573 e1000_configure(adapter);
3574
3575 clear_bit(__E1000_DOWN, &adapter->state);
3576
4662e82b
BA		 3577 if (adapter->msix_entries)
3578 e1000_configure_msix(adapter);
bc7f75fa
AK		 3579 e1000_irq_enable(adapter);
3580
400484fa 3581 netif_start_queue(adapter->netdev);
4cb9be7a 3582
bc7f75fa 3583 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3584 if (adapter->msix_entries)
3585 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3586 else
3587 ew32(ICS, E1000_ICS_LSC);
3588
bc7f75fa
AK		 3589 return 0;
3590}
3591
713b3c9e
JB		 3592static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3593{
3594 struct e1000_hw *hw = &adapter->hw;
3595
3596 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3597 return;
3598
3599 /* flush pending descriptor writebacks to memory */
3600 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3601 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3602
3603 /* execute the writes immediately */
3604 e1e_flush();
bf03085f
MV		 3605
3606 /*
3607 * due to rare timing issues, write to TIDV/RDTR again to ensure the
3608 * write is successful
3609 */
3610 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3611 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3612
3613 /* execute the writes immediately */
3614 e1e_flush();
3615}
3616
67fd4fcb
JK		 3617static void e1000e_update_stats(struct e1000_adapter *adapter);
3618
bc7f75fa
AK		 3619void e1000e_down(struct e1000_adapter *adapter)
3620{
3621 struct net_device *netdev = adapter->netdev;
3622 struct e1000_hw *hw = &adapter->hw;
3623 u32 tctl, rctl;
3624
ad68076e
BA		 3625 /*
3626 * signal that we're down so the interrupt handler does not
3627 * reschedule our watchdog timer
3628 */
bc7f75fa
AK		 3629 set_bit(__E1000_DOWN, &adapter->state);
3630
3631 /* disable receives in the hardware */
3632 rctl = er32(RCTL);
7f99ae63
BA		 3633 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3634 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3635 /* flush and sleep below */
3636
4cb9be7a 3637 netif_stop_queue(netdev);
bc7f75fa
AK		 3638
3639 /* disable transmits in the hardware */
3640 tctl = er32(TCTL);
3641 tctl &= ~E1000_TCTL_EN;
3642 ew32(TCTL, tctl);
7f99ae63 3643
bc7f75fa
AK		 3644 /* flush both disables and wait for them to finish */
3645 e1e_flush();
1bba4386 3646 usleep_range(10000, 20000);
bc7f75fa 3647
bc7f75fa
AK		 3648 e1000_irq_disable(adapter);
3649
3650 del_timer_sync(&adapter->watchdog_timer);
3651 del_timer_sync(&adapter->phy_info_timer);
3652
bc7f75fa 3653 netif_carrier_off(netdev);
67fd4fcb
JK		 3654
3655 spin_lock(&adapter->stats64_lock);
3656 e1000e_update_stats(adapter);
3657 spin_unlock(&adapter->stats64_lock);
3658
400484fa 3659 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3660 e1000_clean_tx_ring(adapter->tx_ring);
3661 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3662
bc7f75fa
AK		 3663 adapter->link_speed = 0;
3664 adapter->link_duplex = 0;
3665
52cc3086
JK		 3666 if (!pci_channel_offline(adapter->pdev))
3667 e1000e_reset(adapter);
713b3c9e 3668
bc7f75fa
AK		 3669 /*
3670 * TODO: for power management, we could drop the link and
3671 * pci_disable_device here.
3672 */
3673}
3674
3675void e1000e_reinit_locked(struct e1000_adapter *adapter)
3676{
3677 might_sleep();
3678 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3679 usleep_range(1000, 2000);
bc7f75fa
AK		 3680 e1000e_down(adapter);
3681 e1000e_up(adapter);
3682 clear_bit(__E1000_RESETTING, &adapter->state);
3683}
3684
3685/**
3686 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3687 * @adapter: board private structure to initialize
3688 *
3689 * e1000_sw_init initializes the Adapter private data structure.
3690 * Fields are initialized based on PCI device information and
3691 * OS network device settings (MTU size).
3692 **/
3693static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3694{
bc7f75fa
AK		 3695 struct net_device *netdev = adapter->netdev;
3696
3697 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3698 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3699 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3700 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3701 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3702 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3703
67fd4fcb
JK		 3704 spin_lock_init(&adapter->stats64_lock);
3705
4662e82b 3706 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3707
4662e82b
BA		 3708 if (e1000_alloc_queues(adapter))
3709 return -ENOMEM;
bc7f75fa 3710
bc7f75fa 3711 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3712 e1000_irq_disable(adapter);
3713
bc7f75fa
AK		 3714 set_bit(__E1000_DOWN, &adapter->state);
3715 return 0;
bc7f75fa
AK		 3716}
3717
f8d59f78
BA		 3718/**
3719 * e1000_intr_msi_test - Interrupt Handler
3720 * @irq: interrupt number
3721 * @data: pointer to a network interface device structure
3722 **/
3723static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3724{
3725 struct net_device *netdev = data;
3726 struct e1000_adapter *adapter = netdev_priv(netdev);
3727 struct e1000_hw *hw = &adapter->hw;
3728 u32 icr = er32(ICR);
3729
3bb99fe2 3730 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3731 if (icr & E1000_ICR_RXSEQ) {
3732 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3733 wmb();
3734 }
3735
3736 return IRQ_HANDLED;
3737}
3738
3739/**
3740 * e1000_test_msi_interrupt - Returns 0 for successful test
3741 * @adapter: board private struct
3742 *
3743 * code flow taken from tg3.c
3744 **/
3745static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3746{
3747 struct net_device *netdev = adapter->netdev;
3748 struct e1000_hw *hw = &adapter->hw;
3749 int err;
3750
3751 /* poll_enable hasn't been called yet, so don't need disable */
3752 /* clear any pending events */
3753 er32(ICR);
3754
3755 /* free the real vector and request a test handler */
3756 e1000_free_irq(adapter);
4662e82b 3757 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3758
3759 /* Assume that the test fails, if it succeeds then the test
3760 * MSI irq handler will unset this flag */
3761 adapter->flags |= FLAG_MSI_TEST_FAILED;
3762
3763 err = pci_enable_msi(adapter->pdev);
3764 if (err)
3765 goto msi_test_failed;
3766
a0607fd3 3767 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3768 netdev->name, netdev);
3769 if (err) {
3770 pci_disable_msi(adapter->pdev);
3771 goto msi_test_failed;
3772 }
3773
3774 wmb();
3775
3776 e1000_irq_enable(adapter);
3777
3778 /* fire an unusual interrupt on the test handler */
3779 ew32(ICS, E1000_ICS_RXSEQ);
3780 e1e_flush();
569a3aff 3781 msleep(100);
f8d59f78
BA		 3782
3783 e1000_irq_disable(adapter);
3784
3785 rmb();
3786
3787 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3788 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3789 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3790 } else {
068e8a30 3791 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3792 }
f8d59f78
BA		 3793
3794 free_irq(adapter->pdev->irq, netdev);
3795 pci_disable_msi(adapter->pdev);
3796
f8d59f78 3797msi_test_failed:
4662e82b 3798 e1000e_set_interrupt_capability(adapter);
068e8a30 3799 return e1000_request_irq(adapter);
f8d59f78
BA		 3800}
3801
3802/**
3803 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3804 * @adapter: board private struct
3805 *
3806 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3807 **/
3808static int e1000_test_msi(struct e1000_adapter *adapter)
3809{
3810 int err;
3811 u16 pci_cmd;
3812
3813 if (!(adapter->flags & FLAG_MSI_ENABLED))
3814 return 0;
3815
3816 /* disable SERR in case the MSI write causes a master abort */
3817 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3818 if (pci_cmd & PCI_COMMAND_SERR)
3819 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3820 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3821
3822 err = e1000_test_msi_interrupt(adapter);
3823
36f2407f
DN		 3824 /* re-enable SERR */
3825 if (pci_cmd & PCI_COMMAND_SERR) {
3826 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3827 pci_cmd |= PCI_COMMAND_SERR;
3828 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3829 }
f8d59f78 3830
f8d59f78
BA		 3831 return err;
3832}
3833
bc7f75fa
AK		 3834/**
3835 * e1000_open - Called when a network interface is made active
3836 * @netdev: network interface device structure
3837 *
3838 * Returns 0 on success, negative value on failure
3839 *
3840 * The open entry point is called when a network interface is made
3841 * active by the system (IFF_UP). At this point all resources needed
3842 * for transmit and receive operations are allocated, the interrupt
3843 * handler is registered with the OS, the watchdog timer is started,
3844 * and the stack is notified that the interface is ready.
3845 **/
3846static int e1000_open(struct net_device *netdev)
3847{
3848 struct e1000_adapter *adapter = netdev_priv(netdev);
3849 struct e1000_hw *hw = &adapter->hw;
23606cf5 3850 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3851 int err;
3852
3853 /* disallow open during test */
3854 if (test_bit(__E1000_TESTING, &adapter->state))
3855 return -EBUSY;
3856
23606cf5
RW		 3857 pm_runtime_get_sync(&pdev->dev);
3858
9c563d20
JB		 3859 netif_carrier_off(netdev);
3860
bc7f75fa 3861 /* allocate transmit descriptors */
55aa6985 3862 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3863 if (err)
3864 goto err_setup_tx;
3865
3866 /* allocate receive descriptors */
55aa6985 3867 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3868 if (err)
3869 goto err_setup_rx;
3870
11b08be8
BA		 3871 /*
3872 * If AMT is enabled, let the firmware know that the network
3873 * interface is now open and reset the part to a known state.
3874 */
3875 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3876 e1000e_get_hw_control(adapter);
11b08be8
BA		 3877 e1000e_reset(adapter);
3878 }
3879
bc7f75fa
AK		 3880 e1000e_power_up_phy(adapter);
3881
3882 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3883 if ((adapter->hw.mng_cookie.status &
3884 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3885 e1000_update_mng_vlan(adapter);
3886
79d4e908
BA		 3887 /* DMA latency requirement to workaround jumbo issue */
3888 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3889 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3890 PM_QOS_CPU_DMA_LATENCY,
3891 PM_QOS_DEFAULT_VALUE);
c128ec29 3892
ad68076e
BA		 3893 /*
3894 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3895 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3896 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3897 * clean_rx handler before we do so.
3898 */
bc7f75fa
AK		 3899 e1000_configure(adapter);
3900
3901 err = e1000_request_irq(adapter);
3902 if (err)
3903 goto err_req_irq;
3904
f8d59f78
BA		 3905 /*
3906 * Work around PCIe errata with MSI interrupts causing some chipsets to
3907 * ignore e1000e MSI messages, which means we need to test our MSI
3908 * interrupt now
3909 */
4662e82b 3910 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3911 err = e1000_test_msi(adapter);
3912 if (err) {
3913 e_err("Interrupt allocation failed\n");
3914 goto err_req_irq;
3915 }
3916 }
3917
bc7f75fa
AK		 3918 /* From here on the code is the same as e1000e_up() */
3919 clear_bit(__E1000_DOWN, &adapter->state);
3920
3921 napi_enable(&adapter->napi);
3922
3923 e1000_irq_enable(adapter);
3924
09357b00 3925 adapter->tx_hang_recheck = false;
4cb9be7a 3926 netif_start_queue(netdev);
d55b53ff 3927
23606cf5
RW		 3928 adapter->idle_check = true;
3929 pm_runtime_put(&pdev->dev);
3930
bc7f75fa 3931 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3932 if (adapter->msix_entries)
3933 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3934 else
3935 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3936
3937 return 0;
3938
3939err_req_irq:
31dbe5b4 3940 e1000e_release_hw_control(adapter);
bc7f75fa 3941 e1000_power_down_phy(adapter);
55aa6985 3942 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3943err_setup_rx:
55aa6985 3944 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3945err_setup_tx:
3946 e1000e_reset(adapter);
23606cf5 3947 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3948
3949 return err;
3950}
3951
3952/**
3953 * e1000_close - Disables a network interface
3954 * @netdev: network interface device structure
3955 *
3956 * Returns 0, this is not allowed to fail
3957 *
3958 * The close entry point is called when an interface is de-activated
3959 * by the OS. The hardware is still under the drivers control, but
3960 * needs to be disabled. A global MAC reset is issued to stop the
3961 * hardware, and all transmit and receive resources are freed.
3962 **/
3963static int e1000_close(struct net_device *netdev)
3964{
3965 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3966 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 3967 int count = E1000_CHECK_RESET_COUNT;
3968
3969 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
3970 usleep_range(10000, 20000);
bc7f75fa
AK		 3971
3972 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3973
3974 pm_runtime_get_sync(&pdev->dev);
3975
5f4a780d
BA		 3976 napi_disable(&adapter->napi);
3977
23606cf5
RW		 3978 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3979 e1000e_down(adapter);
3980 e1000_free_irq(adapter);
3981 }
bc7f75fa 3982 e1000_power_down_phy(adapter);
bc7f75fa 3983
55aa6985
BA		 3984 e1000e_free_tx_resources(adapter->tx_ring);
3985 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3986
ad68076e
BA		 3987 /*
3988 * kill manageability vlan ID if supported, but not if a vlan with
3989 * the same ID is registered on the host OS (let 8021q kill it)
3990 */
86d70e53
JK		 3991 if (adapter->hw.mng_cookie.status &
3992 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3993 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3994
ad68076e
BA		 3995 /*
3996 * If AMT is enabled, let the firmware know that the network
3997 * interface is now closed
3998 */
31dbe5b4
BA		 3999 if ((adapter->flags & FLAG_HAS_AMT) &&
4000 !test_bit(__E1000_TESTING, &adapter->state))
4001 e1000e_release_hw_control(adapter);
bc7f75fa 4002
79d4e908 4003 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 4004 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4005
23606cf5
RW		 4006 pm_runtime_put_sync(&pdev->dev);
4007
bc7f75fa
AK		 4008 return 0;
4009}
4010/**
4011 * e1000_set_mac - Change the Ethernet Address of the NIC
4012 * @netdev: network interface device structure
4013 * @p: pointer to an address structure
4014 *
4015 * Returns 0 on success, negative on failure
4016 **/
4017static int e1000_set_mac(struct net_device *netdev, void *p)
4018{
4019 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4020 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4021 struct sockaddr *addr = p;
4022
4023 if (!is_valid_ether_addr(addr->sa_data))
4024 return -EADDRNOTAVAIL;
4025
4026 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4027 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4028
69e1e019 4029 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4030
4031 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4032 /* activate the work around */
4033 e1000e_set_laa_state_82571(&adapter->hw, 1);
4034
ad68076e
BA		 4035 /*
4036 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4037 * between the time RAR[0] gets clobbered and the time it
4038 * gets fixed (in e1000_watchdog), the actual LAA is in one
4039 * of the RARs and no incoming packets directed to this port
4040 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4041 * RAR[14]
4042 */
69e1e019
BA		 4043 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4044 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4045 }
4046
4047 return 0;
4048}
4049
a8f88ff5
JB		 4050/**
4051 * e1000e_update_phy_task - work thread to update phy
4052 * @work: pointer to our work struct
4053 *
4054 * this worker thread exists because we must acquire a
4055 * semaphore to read the phy, which we could msleep while
4056 * waiting for it, and we can't msleep in a timer.
4057 **/
4058static void e1000e_update_phy_task(struct work_struct *work)
4059{
4060 struct e1000_adapter *adapter = container_of(work,
4061 struct e1000_adapter, update_phy_task);
615b32af
JB		 4062
4063 if (test_bit(__E1000_DOWN, &adapter->state))
4064 return;
4065
a8f88ff5
JB		 4066 e1000_get_phy_info(&adapter->hw);
4067}
4068
ad68076e
BA		 4069/*
4070 * Need to wait a few seconds after link up to get diagnostic information from
4071 * the phy
4072 */
bc7f75fa
AK		 4073static void e1000_update_phy_info(unsigned long data)
4074{
4075 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4076
4077 if (test_bit(__E1000_DOWN, &adapter->state))
4078 return;
4079
a8f88ff5 4080 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4081}
4082
8c7bbb92
BA		 4083/**
4084 * e1000e_update_phy_stats - Update the PHY statistics counters
4085 * @adapter: board private structure
2b6b168d
BA		 4086 *
4087 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4088 **/
4089static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4090{
4091 struct e1000_hw *hw = &adapter->hw;
4092 s32 ret_val;
4093 u16 phy_data;
4094
4095 ret_val = hw->phy.ops.acquire(hw);
4096 if (ret_val)
4097 return;
4098
8c7bbb92
BA		 4099 /*
4100 * A page set is expensive so check if already on desired page.
4101 * If not, set to the page with the PHY status registers.
4102 */
2b6b168d 4103 hw->phy.addr = 1;
8c7bbb92
BA		 4104 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4105 &phy_data);
4106 if (ret_val)
4107 goto release;
2b6b168d
BA		 4108 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4109 ret_val = hw->phy.ops.set_page(hw,
4110 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4111 if (ret_val)
4112 goto release;
4113 }
4114
8c7bbb92 4115 /* Single Collision Count */
2b6b168d
BA		 4116 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4117 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4118 if (!ret_val)
4119 adapter->stats.scc += phy_data;
4120
4121 /* Excessive Collision Count */
2b6b168d
BA		 4122 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4123 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4124 if (!ret_val)
4125 adapter->stats.ecol += phy_data;
4126
4127 /* Multiple Collision Count */
2b6b168d
BA		 4128 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4129 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4130 if (!ret_val)
4131 adapter->stats.mcc += phy_data;
4132
4133 /* Late Collision Count */
2b6b168d
BA		 4134 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4135 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4136 if (!ret_val)
4137 adapter->stats.latecol += phy_data;
4138
4139 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4140 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4141 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4142 if (!ret_val)
4143 hw->mac.collision_delta = phy_data;
4144
4145 /* Defer Count */
2b6b168d
BA		 4146 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4147 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4148 if (!ret_val)
4149 adapter->stats.dc += phy_data;
4150
4151 /* Transmit with no CRS */
2b6b168d
BA		 4152 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4153 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4154 if (!ret_val)
4155 adapter->stats.tncrs += phy_data;
4156
4157release:
4158 hw->phy.ops.release(hw);
4159}
4160
bc7f75fa
AK		 4161/**
4162 * e1000e_update_stats - Update the board statistics counters
4163 * @adapter: board private structure
4164 **/
67fd4fcb 4165static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4166{
7274c20f 4167 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4168 struct e1000_hw *hw = &adapter->hw;
4169 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4170
4171 /*
4172 * Prevent stats update while adapter is being reset, or if the pci
4173 * connection is down.
4174 */
4175 if (adapter->link_speed == 0)
4176 return;
4177 if (pci_channel_offline(pdev))
4178 return;
4179
bc7f75fa
AK		 4180 adapter->stats.crcerrs += er32(CRCERRS);
4181 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4182 adapter->stats.gorc += er32(GORCL);
4183 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4184 adapter->stats.bprc += er32(BPRC);
4185 adapter->stats.mprc += er32(MPRC);
4186 adapter->stats.roc += er32(ROC);
4187
bc7f75fa 4188 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4189
4190 /* Half-duplex statistics */
4191 if (adapter->link_duplex == HALF_DUPLEX) {
4192 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4193 e1000e_update_phy_stats(adapter);
4194 } else {
4195 adapter->stats.scc += er32(SCC);
4196 adapter->stats.ecol += er32(ECOL);
4197 adapter->stats.mcc += er32(MCC);
4198 adapter->stats.latecol += er32(LATECOL);
4199 adapter->stats.dc += er32(DC);
4200
4201 hw->mac.collision_delta = er32(COLC);
4202
4203 if ((hw->mac.type != e1000_82574) &&
4204 (hw->mac.type != e1000_82583))
4205 adapter->stats.tncrs += er32(TNCRS);
4206 }
4207 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4208 }
8c7bbb92 4209
bc7f75fa
AK		 4210 adapter->stats.xonrxc += er32(XONRXC);
4211 adapter->stats.xontxc += er32(XONTXC);
4212 adapter->stats.xoffrxc += er32(XOFFRXC);
4213 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4214 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4215 adapter->stats.gotc += er32(GOTCL);
4216 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4217 adapter->stats.rnbc += er32(RNBC);
4218 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4219
4220 adapter->stats.mptc += er32(MPTC);
4221 adapter->stats.bptc += er32(BPTC);
4222
4223 /* used for adaptive IFS */
4224
4225 hw->mac.tx_packet_delta = er32(TPT);
4226 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4227
4228 adapter->stats.algnerrc += er32(ALGNERRC);
4229 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4230 adapter->stats.cexterr += er32(CEXTERR);
4231 adapter->stats.tsctc += er32(TSCTC);
4232 adapter->stats.tsctfc += er32(TSCTFC);
4233
bc7f75fa 4234 /* Fill out the OS statistics structure */
7274c20f
AK		 4235 netdev->stats.multicast = adapter->stats.mprc;
4236 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4237
4238 /* Rx Errors */
4239
ad68076e
BA		 4240 /*
4241 * RLEC on some newer hardware can be incorrect so build
4242 * our own version based on RUC and ROC
4243 */
7274c20f 4244 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4245 adapter->stats.crcerrs + adapter->stats.algnerrc +
4246 adapter->stats.ruc + adapter->stats.roc +
4247 adapter->stats.cexterr;
7274c20f 4248 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4249 adapter->stats.roc;
7274c20f
AK		 4250 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4251 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4252 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4253
4254 /* Tx Errors */
7274c20f 4255 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4256 adapter->stats.latecol;
7274c20f
AK		 4257 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4258 netdev->stats.tx_window_errors = adapter->stats.latecol;
4259 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4260
4261 /* Tx Dropped needs to be maintained elsewhere */
4262
bc7f75fa
AK		 4263 /* Management Stats */
4264 adapter->stats.mgptc += er32(MGTPTC);
4265 adapter->stats.mgprc += er32(MGTPRC);
4266 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4267}
4268
7c25769f
BA		 4269/**
4270 * e1000_phy_read_status - Update the PHY register status snapshot
4271 * @adapter: board private structure
4272 **/
4273static void e1000_phy_read_status(struct e1000_adapter *adapter)
4274{
4275 struct e1000_hw *hw = &adapter->hw;
4276 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4277
4278 if ((er32(STATUS) & E1000_STATUS_LU) &&
4279 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4280 int ret_val;
4281
7c25769f
BA		 4282 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4283 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4284 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4285 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4286 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4287 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4288 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4289 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4290 if (ret_val)
44defeb3 4291 e_warn("Error reading PHY register\n");
7c25769f
BA		 4292 } else {
4293 /*
4294 * Do not read PHY registers if link is not up
4295 * Set values to typical power-on defaults
4296 */
4297 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4298 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4299 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4300 BMSR_ERCAP);
4301 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4302 ADVERTISE_ALL | ADVERTISE_CSMA);
4303 phy->lpa = 0;
4304 phy->expansion = EXPANSION_ENABLENPAGE;
4305 phy->ctrl1000 = ADVERTISE_1000FULL;
4306 phy->stat1000 = 0;
4307 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4308 }
7c25769f
BA		 4309}
4310
bc7f75fa
AK		 4311static void e1000_print_link_info(struct e1000_adapter *adapter)
4312{
bc7f75fa
AK		 4313 struct e1000_hw *hw = &adapter->hw;
4314 u32 ctrl = er32(CTRL);
4315
8f12fe86 4316 /* Link status message must follow this format for user tools */
ef456f85
JK		 4317 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4318 adapter->netdev->name,
4319 adapter->link_speed,
4320 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4321 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4322 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4323 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4324}
4325
0c6bdb30 4326static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4327{
4328 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4329 bool link_active = false;
318a94d6
JK		 4330 s32 ret_val = 0;
4331
4332 /*
4333 * get_link_status is set on LSC (link status) interrupt or
4334 * Rx sequence error interrupt. get_link_status will stay
4335 * false until the check_for_link establishes link
4336 * for copper adapters ONLY
4337 */
4338 switch (hw->phy.media_type) {
4339 case e1000_media_type_copper:
4340 if (hw->mac.get_link_status) {
4341 ret_val = hw->mac.ops.check_for_link(hw);
4342 link_active = !hw->mac.get_link_status;
4343 } else {
3db1cd5c 4344 link_active = true;
318a94d6
JK		 4345 }
4346 break;
4347 case e1000_media_type_fiber:
4348 ret_val = hw->mac.ops.check_for_link(hw);
4349 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4350 break;
4351 case e1000_media_type_internal_serdes:
4352 ret_val = hw->mac.ops.check_for_link(hw);
4353 link_active = adapter->hw.mac.serdes_has_link;
4354 break;
4355 default:
4356 case e1000_media_type_unknown:
4357 break;
4358 }
4359
4360 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4361 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4362 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4363 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4364 }
4365
4366 return link_active;
4367}
4368
4369static void e1000e_enable_receives(struct e1000_adapter *adapter)
4370{
4371 /* make sure the receive unit is started */
4372 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4373 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4374 struct e1000_hw *hw = &adapter->hw;
4375 u32 rctl = er32(RCTL);
4376 ew32(RCTL, rctl | E1000_RCTL_EN);
4377 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4378 }
4379}
4380
ff10e13c
CW		 4381static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4382{
4383 struct e1000_hw *hw = &adapter->hw;
4384
4385 /*
4386 * With 82574 controllers, PHY needs to be checked periodically
4387 * for hung state and reset, if two calls return true
4388 */
4389 if (e1000_check_phy_82574(hw))
4390 adapter->phy_hang_count++;
4391 else
4392 adapter->phy_hang_count = 0;
4393
4394 if (adapter->phy_hang_count > 1) {
4395 adapter->phy_hang_count = 0;
4396 schedule_work(&adapter->reset_task);
4397 }
4398}
4399
bc7f75fa
AK		 4400/**
4401 * e1000_watchdog - Timer Call-back
4402 * @data: pointer to adapter cast into an unsigned long
4403 **/
4404static void e1000_watchdog(unsigned long data)
4405{
4406 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4407
4408 /* Do the rest outside of interrupt context */
4409 schedule_work(&adapter->watchdog_task);
4410
4411 /* TODO: make this use queue_delayed_work() */
4412}
4413
4414static void e1000_watchdog_task(struct work_struct *work)
4415{
4416 struct e1000_adapter *adapter = container_of(work,
4417 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4418 struct net_device *netdev = adapter->netdev;
4419 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4420 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4421 struct e1000_ring *tx_ring = adapter->tx_ring;
4422 struct e1000_hw *hw = &adapter->hw;
4423 u32 link, tctl;
bc7f75fa 4424
615b32af
JB		 4425 if (test_bit(__E1000_DOWN, &adapter->state))
4426 return;
4427
b405e8df 4428 link = e1000e_has_link(adapter);
318a94d6 4429 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4430 /* Cancel scheduled suspend requests. */
4431 pm_runtime_resume(netdev->dev.parent);
4432
318a94d6 4433 e1000e_enable_receives(adapter);
bc7f75fa 4434 goto link_up;
bc7f75fa
AK		 4435 }
4436
4437 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4438 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4439 e1000_update_mng_vlan(adapter);
4440
bc7f75fa
AK		 4441 if (link) {
4442 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4443 bool txb2b = true;
23606cf5
RW		 4444
4445 /* Cancel scheduled suspend requests. */
4446 pm_runtime_resume(netdev->dev.parent);
4447
318a94d6 4448 /* update snapshot of PHY registers on LSC */
7c25769f 4449 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4450 mac->ops.get_link_up_info(&adapter->hw,
4451 &adapter->link_speed,
4452 &adapter->link_duplex);
4453 e1000_print_link_info(adapter);
f4187b56
BA		 4454 /*
4455 * On supported PHYs, check for duplex mismatch only
4456 * if link has autonegotiated at 10/100 half
4457 */
4458 if ((hw->phy.type == e1000_phy_igp_3 ||
4459 hw->phy.type == e1000_phy_bm) &&
4460 (hw->mac.autoneg == true) &&
4461 (adapter->link_speed == SPEED_10 ||
4462 adapter->link_speed == SPEED_100) &&
4463 (adapter->link_duplex == HALF_DUPLEX)) {
4464 u16 autoneg_exp;
4465
4466 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4467
4468 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4469 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4470 }
4471
f49c57e1 4472 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4473 adapter->tx_timeout_factor = 1;
4474 switch (adapter->link_speed) {
4475 case SPEED_10:
3db1cd5c 4476 txb2b = false;
10f1b492 4477 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4478 break;
4479 case SPEED_100:
3db1cd5c 4480 txb2b = false;
4c86e0b9 4481 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4482 break;
4483 }
4484
ad68076e
BA		 4485 /*
4486 * workaround: re-program speed mode bit after
4487 * link-up event
4488 */
bc7f75fa
AK		 4489 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4490 !txb2b) {
4491 u32 tarc0;
e9ec2c0f 4492 tarc0 = er32(TARC(0));
bc7f75fa 4493 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4494 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4495 }
4496
ad68076e
BA		 4497 /*
4498 * disable TSO for pcie and 10/100 speeds, to avoid
4499 * some hardware issues
4500 */
bc7f75fa
AK		 4501 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4502 switch (adapter->link_speed) {
4503 case SPEED_10:
4504 case SPEED_100:
44defeb3 4505 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4506 netdev->features &= ~NETIF_F_TSO;
4507 netdev->features &= ~NETIF_F_TSO6;
4508 break;
4509 case SPEED_1000:
4510 netdev->features |= NETIF_F_TSO;
4511 netdev->features |= NETIF_F_TSO6;
4512 break;
4513 default:
4514 /* oops */
4515 break;
4516 }
4517 }
4518
ad68076e
BA		 4519 /*
4520 * enable transmits in the hardware, need to do this
4521 * after setting TARC(0)
4522 */
bc7f75fa
AK		 4523 tctl = er32(TCTL);
4524 tctl |= E1000_TCTL_EN;
4525 ew32(TCTL, tctl);
4526
75eb0fad
BA		 4527 /*
4528 * Perform any post-link-up configuration before
4529 * reporting link up.
4530 */
4531 if (phy->ops.cfg_on_link_up)
4532 phy->ops.cfg_on_link_up(hw);
4533
bc7f75fa 4534 netif_carrier_on(netdev);
bc7f75fa
AK		 4535
4536 if (!test_bit(__E1000_DOWN, &adapter->state))
4537 mod_timer(&adapter->phy_info_timer,
4538 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4539 }
4540 } else {
4541 if (netif_carrier_ok(netdev)) {
4542 adapter->link_speed = 0;
4543 adapter->link_duplex = 0;
8f12fe86
BA		 4544 /* Link status message must follow this format */
4545 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4546 adapter->netdev->name);
bc7f75fa 4547 netif_carrier_off(netdev);
bc7f75fa
AK		 4548 if (!test_bit(__E1000_DOWN, &adapter->state))
4549 mod_timer(&adapter->phy_info_timer,
4550 round_jiffies(jiffies + 2 * HZ));
4551
4552 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4553 schedule_work(&adapter->reset_task);
23606cf5
RW		 4554 else
4555 pm_schedule_suspend(netdev->dev.parent,
4556 LINK_TIMEOUT);
bc7f75fa
AK		 4557 }
4558 }
4559
4560link_up:
67fd4fcb 4561 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4562 e1000e_update_stats(adapter);
4563
4564 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4565 adapter->tpt_old = adapter->stats.tpt;
4566 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4567 adapter->colc_old = adapter->stats.colc;
4568
7c25769f
BA		 4569 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4570 adapter->gorc_old = adapter->stats.gorc;
4571 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4572 adapter->gotc_old = adapter->stats.gotc;
2084b114 4573 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4574
4575 e1000e_update_adaptive(&adapter->hw);
4576
90da0669
BA		 4577 if (!netif_carrier_ok(netdev) &&
4578 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4579 /*
4580 * We've lost link, so the controller stops DMA,
4581 * but we've got queued Tx work that's never going
4582 * to get done, so reset controller to flush Tx.
4583 * (Do the reset outside of interrupt context).
4584 */
90da0669
BA		 4585 schedule_work(&adapter->reset_task);
4586 /* return immediately since reset is imminent */
4587 return;
bc7f75fa
AK		 4588 }
4589
eab2abf5
JB		 4590 /* Simple mode for Interrupt Throttle Rate (ITR) */
4591 if (adapter->itr_setting == 4) {
4592 /*
4593 * Symmetric Tx/Rx gets a reduced ITR=2000;
4594 * Total asymmetrical Tx or Rx gets ITR=8000;
4595 * everyone else is between 2000-8000.
4596 */
4597 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4598 u32 dif = (adapter->gotc > adapter->gorc ?
4599 adapter->gotc - adapter->gorc :
4600 adapter->gorc - adapter->gotc) / 10000;
4601 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4602
22a4cca2 4603 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 4604 }
4605
ad68076e 4606 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4607 if (adapter->msix_entries)
4608 ew32(ICS, adapter->rx_ring->ims_val);
4609 else
4610 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4611
713b3c9e
JB		 4612 /* flush pending descriptors to memory before detecting Tx hang */
4613 e1000e_flush_descriptors(adapter);
4614
bc7f75fa 4615 /* Force detection of hung controller every watchdog period */
3db1cd5c 4616 adapter->detect_tx_hung = true;
bc7f75fa 4617
ad68076e
BA		 4618 /*
4619 * With 82571 controllers, LAA may be overwritten due to controller
4620 * reset from the other port. Set the appropriate LAA in RAR[0]
4621 */
bc7f75fa 4622 if (e1000e_get_laa_state_82571(hw))
69e1e019 4623 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 4624
ff10e13c
CW		 4625 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4626 e1000e_check_82574_phy_workaround(adapter);
4627
bc7f75fa
AK		 4628 /* Reset the timer */
4629 if (!test_bit(__E1000_DOWN, &adapter->state))
4630 mod_timer(&adapter->watchdog_timer,
4631 round_jiffies(jiffies + 2 * HZ));
4632}
4633
4634#define E1000_TX_FLAGS_CSUM 0x00000001
4635#define E1000_TX_FLAGS_VLAN 0x00000002
4636#define E1000_TX_FLAGS_TSO 0x00000004
4637#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4638#define E1000_TX_FLAGS_NO_FCS 0x00000010
bc7f75fa
AK		 4639#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4640#define E1000_TX_FLAGS_VLAN_SHIFT 16
4641
55aa6985 4642static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4643{
bc7f75fa
AK		 4644 struct e1000_context_desc *context_desc;
4645 struct e1000_buffer *buffer_info;
4646 unsigned int i;
4647 u32 cmd_length = 0;
4648 u16 ipcse = 0, tucse, mss;
4649 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4650
3d5e33c9
BA		 4651 if (!skb_is_gso(skb))
4652 return 0;
bc7f75fa 4653
3d5e33c9 4654 if (skb_header_cloned(skb)) {
90da0669
BA		 4655 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4656
3d5e33c9
BA		 4657 if (err)
4658 return err;
bc7f75fa
AK		 4659 }
4660
3d5e33c9
BA		 4661 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4662 mss = skb_shinfo(skb)->gso_size;
4663 if (skb->protocol == htons(ETH_P_IP)) {
4664 struct iphdr *iph = ip_hdr(skb);
4665 iph->tot_len = 0;
4666 iph->check = 0;
4667 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4668 0, IPPROTO_TCP, 0);
4669 cmd_length = E1000_TXD_CMD_IP;
4670 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4671 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4672 ipv6_hdr(skb)->payload_len = 0;
4673 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4674 &ipv6_hdr(skb)->daddr,
4675 0, IPPROTO_TCP, 0);
4676 ipcse = 0;
4677 }
4678 ipcss = skb_network_offset(skb);
4679 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4680 tucss = skb_transport_offset(skb);
4681 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4682 tucse = 0;
4683
4684 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4685 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4686
4687 i = tx_ring->next_to_use;
4688 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4689 buffer_info = &tx_ring->buffer_info[i];
4690
4691 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4692 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4693 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4694 context_desc->upper_setup.tcp_fields.tucss = tucss;
4695 context_desc->upper_setup.tcp_fields.tucso = tucso;
4696 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4697 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4698 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4699 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4700
4701 buffer_info->time_stamp = jiffies;
4702 buffer_info->next_to_watch = i;
4703
4704 i++;
4705 if (i == tx_ring->count)
4706 i = 0;
4707 tx_ring->next_to_use = i;
4708
4709 return 1;
bc7f75fa
AK		 4710}
4711
55aa6985 4712static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4713{
55aa6985 4714 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4715 struct e1000_context_desc *context_desc;
4716 struct e1000_buffer *buffer_info;
4717 unsigned int i;
4718 u8 css;
af807c82 4719 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4720 __be16 protocol;
bc7f75fa 4721
af807c82
DG		 4722 if (skb->ip_summed != CHECKSUM_PARTIAL)
4723 return 0;
bc7f75fa 4724
5f66f208
AJ		 4725 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4726 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4727 else
4728 protocol = skb->protocol;
4729
3f518390 4730 switch (protocol) {
09640e63 4731 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4732 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4733 cmd_len |= E1000_TXD_CMD_TCP;
4734 break;
09640e63 4735 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4736 /* XXX not handling all IPV6 headers */
4737 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4738 cmd_len |= E1000_TXD_CMD_TCP;
4739 break;
4740 default:
4741 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4742 e_warn("checksum_partial proto=%x!\n",
4743 be16_to_cpu(protocol));
af807c82 4744 break;
bc7f75fa
AK		 4745 }
4746
0d0b1672 4747 css = skb_checksum_start_offset(skb);
af807c82
DG		 4748
4749 i = tx_ring->next_to_use;
4750 buffer_info = &tx_ring->buffer_info[i];
4751 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4752
4753 context_desc->lower_setup.ip_config = 0;
4754 context_desc->upper_setup.tcp_fields.tucss = css;
4755 context_desc->upper_setup.tcp_fields.tucso =
4756 css + skb->csum_offset;
4757 context_desc->upper_setup.tcp_fields.tucse = 0;
4758 context_desc->tcp_seg_setup.data = 0;
4759 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4760
4761 buffer_info->time_stamp = jiffies;
4762 buffer_info->next_to_watch = i;
4763
4764 i++;
4765 if (i == tx_ring->count)
4766 i = 0;
4767 tx_ring->next_to_use = i;
4768
4769 return 1;
bc7f75fa
AK		 4770}
4771
4772#define E1000_MAX_PER_TXD 8192
4773#define E1000_MAX_TXD_PWR 12
4774
55aa6985
BA		 4775static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4776 unsigned int first, unsigned int max_per_txd,
4777 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4778{
55aa6985 4779 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4780 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4781 struct e1000_buffer *buffer_info;
8ddc951c 4782 unsigned int len = skb_headlen(skb);
03b1320d 4783 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4784 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4785
4786 i = tx_ring->next_to_use;
4787
4788 while (len) {
1b7719c4 4789 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4790 size = min(len, max_per_txd);
4791
bc7f75fa 4792 buffer_info->length = size;
bc7f75fa 4793 buffer_info->time_stamp = jiffies;
bc7f75fa 4794 buffer_info->next_to_watch = i;
0be3f55f
NN		 4795 buffer_info->dma = dma_map_single(&pdev->dev,
4796 skb->data + offset,
af667a29 4797 size, DMA_TO_DEVICE);
03b1320d 4798 buffer_info->mapped_as_page = false;
0be3f55f 4799 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4800 goto dma_error;
bc7f75fa
AK		 4801
4802 len -= size;
4803 offset += size;
03b1320d 4804 count++;
1b7719c4
AD		 4805
4806 if (len) {
4807 i++;
4808 if (i == tx_ring->count)
4809 i = 0;
4810 }
bc7f75fa
AK		 4811 }
4812
4813 for (f = 0; f < nr_frags; f++) {
9e903e08 4814 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4815
4816 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4817 len = skb_frag_size(frag);
877749bf 4818 offset = 0;
bc7f75fa
AK		 4819
4820 while (len) {
1b7719c4
AD		 4821 i++;
4822 if (i == tx_ring->count)
4823 i = 0;
4824
bc7f75fa
AK		 4825 buffer_info = &tx_ring->buffer_info[i];
4826 size = min(len, max_per_txd);
bc7f75fa
AK		 4827
4828 buffer_info->length = size;
4829 buffer_info->time_stamp = jiffies;
bc7f75fa 4830 buffer_info->next_to_watch = i;
877749bf
IC		 4831 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4832 offset, size, DMA_TO_DEVICE);
03b1320d 4833 buffer_info->mapped_as_page = true;
0be3f55f 4834 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4835 goto dma_error;
bc7f75fa
AK		 4836
4837 len -= size;
4838 offset += size;
4839 count++;
bc7f75fa
AK		 4840 }
4841 }
4842
af667a29 4843 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4844 /* multiply data chunks by size of headers */
4845 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4846
bc7f75fa 4847 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4848 tx_ring->buffer_info[i].segs = segs;
4849 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4850 tx_ring->buffer_info[first].next_to_watch = i;
4851
4852 return count;
03b1320d
AD		 4853
4854dma_error:
af667a29 4855 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4856 buffer_info->dma = 0;
c1fa347f 4857 if (count)
03b1320d 4858 count--;
c1fa347f
RK		 4859
4860 while (count--) {
af667a29 4861 if (i == 0)
03b1320d 4862 i += tx_ring->count;
c1fa347f 4863 i--;
03b1320d 4864 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4865 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4866 }
4867
4868 return 0;
bc7f75fa
AK		 4869}
4870
55aa6985 4871static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4872{
55aa6985 4873 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4874 struct e1000_tx_desc *tx_desc = NULL;
4875 struct e1000_buffer *buffer_info;
4876 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4877 unsigned int i;
4878
4879 if (tx_flags & E1000_TX_FLAGS_TSO) {
4880 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4881 E1000_TXD_CMD_TSE;
4882 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4883
4884 if (tx_flags & E1000_TX_FLAGS_IPV4)
4885 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4886 }
4887
4888 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4889 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4890 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4891 }
4892
4893 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4894 txd_lower |= E1000_TXD_CMD_VLE;
4895 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4896 }
4897
943146de
BG		 4898 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4899 txd_lower &= ~(E1000_TXD_CMD_IFCS);
4900
bc7f75fa
AK		 4901 i = tx_ring->next_to_use;
4902
36b973df 4903 do {
bc7f75fa
AK		 4904 buffer_info = &tx_ring->buffer_info[i];
4905 tx_desc = E1000_TX_DESC(*tx_ring, i);
4906 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4907 tx_desc->lower.data =
4908 cpu_to_le32(txd_lower | buffer_info->length);
4909 tx_desc->upper.data = cpu_to_le32(txd_upper);
4910
4911 i++;
4912 if (i == tx_ring->count)
4913 i = 0;
36b973df 4914 } while (--count > 0);
bc7f75fa
AK		 4915
4916 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4917
943146de
BG		 4918 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4919 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4920 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4921
ad68076e
BA		 4922 /*
4923 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4924 * know there are new descriptors to fetch. (Only
4925 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4926 * such as IA-64).
4927 */
bc7f75fa
AK		 4928 wmb();
4929
4930 tx_ring->next_to_use = i;
c6e7f51e
BA		 4931
4932 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4933 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4934 else
c5083cf6 4935 writel(i, tx_ring->tail);
c6e7f51e 4936
ad68076e
BA		 4937 /*
4938 * we need this if more than one processor can write to our tail
4939 * at a time, it synchronizes IO on IA64/Altix systems
4940 */
bc7f75fa
AK		 4941 mmiowb();
4942}
4943
4944#define MINIMUM_DHCP_PACKET_SIZE 282
4945static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4946 struct sk_buff *skb)
4947{
4948 struct e1000_hw *hw = &adapter->hw;
4949 u16 length, offset;
4950
4951 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4952 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4953 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4954 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4955 return 0;
4956 }
4957
4958 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4959 return 0;
4960
4961 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4962 return 0;
4963
4964 {
4965 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4966 struct udphdr *udp;
4967
4968 if (ip->protocol != IPPROTO_UDP)
4969 return 0;
4970
4971 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4972 if (ntohs(udp->dest) != 67)
4973 return 0;
4974
4975 offset = (u8 *)udp + 8 - skb->data;
4976 length = skb->len - offset;
4977 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4978 }
4979
4980 return 0;
4981}
4982
55aa6985 4983static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4984{
55aa6985 4985 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4986
55aa6985 4987 netif_stop_queue(adapter->netdev);
ad68076e
BA		 4988 /*
4989 * Herbert's original patch had:
bc7f75fa 4990 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4991 * but since that doesn't exist yet, just open code it.
4992 */
bc7f75fa
AK		 4993 smp_mb();
4994
ad68076e
BA		 4995 /*
4996 * We need to check again in a case another CPU has just
4997 * made room available.
4998 */
55aa6985 4999 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5000 return -EBUSY;
5001
5002 /* A reprieve! */
55aa6985 5003 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5004 ++adapter->restart_queue;
5005 return 0;
5006}
5007
55aa6985 5008static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5009{
55aa6985 5010 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5011 return 0;
55aa6985 5012 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5013}
5014
0e15df49 5015#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
3b29a56d
SH		 5016static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5017 struct net_device *netdev)
bc7f75fa
AK		 5018{
5019 struct e1000_adapter *adapter = netdev_priv(netdev);
5020 struct e1000_ring *tx_ring = adapter->tx_ring;
5021 unsigned int first;
5022 unsigned int max_per_txd = E1000_MAX_PER_TXD;
5023 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
5024 unsigned int tx_flags = 0;
e743d313 5025 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5026 unsigned int nr_frags;
5027 unsigned int mss;
bc7f75fa
AK		 5028 int count = 0;
5029 int tso;
5030 unsigned int f;
bc7f75fa
AK		 5031
5032 if (test_bit(__E1000_DOWN, &adapter->state)) {
5033 dev_kfree_skb_any(skb);
5034 return NETDEV_TX_OK;
5035 }
5036
5037 if (skb->len <= 0) {
5038 dev_kfree_skb_any(skb);
5039 return NETDEV_TX_OK;
5040 }
5041
5042 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5043 /*
5044 * The controller does a simple calculation to
bc7f75fa
AK		 5045 * make sure there is enough room in the FIFO before
5046 * initiating the DMA for each buffer. The calc is:
5047 * 4 = ceil(buffer len/mss). To make sure we don't
5048 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5049 * drops.
5050 */
bc7f75fa
AK		 5051 if (mss) {
5052 u8 hdr_len;
5053 max_per_txd = min(mss << 2, max_per_txd);
5054 max_txd_pwr = fls(max_per_txd) - 1;
5055
ad68076e
BA		 5056 /*
5057 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5058 * points to just header, pull a few bytes of payload from
5059 * frags into skb->data
5060 */
bc7f75fa 5061 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5062 /*
5063 * we do this workaround for ES2LAN, but it is un-necessary,
5064 * avoiding it could save a lot of cycles
5065 */
4e6c709c 5066 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5067 unsigned int pull_size;
5068
a2a5b323 5069 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5070 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5071 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5072 dev_kfree_skb_any(skb);
5073 return NETDEV_TX_OK;
5074 }
e743d313 5075 len = skb_headlen(skb);
bc7f75fa
AK		 5076 }
5077 }
5078
5079 /* reserve a descriptor for the offload context */
5080 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5081 count++;
5082 count++;
5083
5084 count += TXD_USE_COUNT(len, max_txd_pwr);
5085
5086 nr_frags = skb_shinfo(skb)->nr_frags;
5087 for (f = 0; f < nr_frags; f++)
9e903e08 5088 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5089 max_txd_pwr);
5090
5091 if (adapter->hw.mac.tx_pkt_filtering)
5092 e1000_transfer_dhcp_info(adapter, skb);
5093
ad68076e
BA		 5094 /*
5095 * need: count + 2 desc gap to keep tail from touching
5096 * head, otherwise try next time
5097 */
55aa6985 5098 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5099 return NETDEV_TX_BUSY;
bc7f75fa 5100
eab6d18d 5101 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5102 tx_flags |= E1000_TX_FLAGS_VLAN;
5103 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5104 }
5105
5106 first = tx_ring->next_to_use;
5107
55aa6985 5108 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5109 if (tso < 0) {
5110 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5111 return NETDEV_TX_OK;
5112 }
5113
5114 if (tso)
5115 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5116 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5117 tx_flags |= E1000_TX_FLAGS_CSUM;
5118
ad68076e
BA		 5119 /*
5120 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5121 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5122 * no longer assume, we must.
5123 */
bc7f75fa
AK		 5124 if (skb->protocol == htons(ETH_P_IP))
5125 tx_flags |= E1000_TX_FLAGS_IPV4;
5126
943146de
BG		 5127 if (unlikely(skb->no_fcs))
5128 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5129
25985edc 5130 /* if count is 0 then mapping error has occurred */
55aa6985 5131 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5132 if (count) {
80be3129
WB		 5133 skb_tx_timestamp(skb);
5134
3f0cfa3b 5135 netdev_sent_queue(netdev, skb->len);
55aa6985 5136 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5137 /* Make sure there is space in the ring for the next send. */
55aa6985 5138 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5139
5140 } else {
bc7f75fa 5141 dev_kfree_skb_any(skb);
1b7719c4
AD		 5142 tx_ring->buffer_info[first].time_stamp = 0;
5143 tx_ring->next_to_use = first;
bc7f75fa
AK		 5144 }
5145
bc7f75fa
AK		 5146 return NETDEV_TX_OK;
5147}
5148
5149/**
5150 * e1000_tx_timeout - Respond to a Tx Hang
5151 * @netdev: network interface device structure
5152 **/
5153static void e1000_tx_timeout(struct net_device *netdev)
5154{
5155 struct e1000_adapter *adapter = netdev_priv(netdev);
5156
5157 /* Do the reset outside of interrupt context */
5158 adapter->tx_timeout_count++;
5159 schedule_work(&adapter->reset_task);
5160}
5161
5162static void e1000_reset_task(struct work_struct *work)
5163{
5164 struct e1000_adapter *adapter;
5165 adapter = container_of(work, struct e1000_adapter, reset_task);
5166
615b32af
JB		 5167 /* don't run the task if already down */
5168 if (test_bit(__E1000_DOWN, &adapter->state))
5169 return;
5170
affa9dfb
CW		 5171 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5172 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5173 e1000e_dump(adapter);
5174 e_err("Reset adapter\n");
5175 }
bc7f75fa
AK		 5176 e1000e_reinit_locked(adapter);
5177}
5178
5179/**
67fd4fcb 5180 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5181 * @netdev: network interface device structure
67fd4fcb 5182 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5183 *
5184 * Returns the address of the device statistics structure.
bc7f75fa 5185 **/
67fd4fcb
JK		 5186struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5187 struct rtnl_link_stats64 *stats)
bc7f75fa 5188{
67fd4fcb
JK		 5189 struct e1000_adapter *adapter = netdev_priv(netdev);
5190
5191 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5192 spin_lock(&adapter->stats64_lock);
5193 e1000e_update_stats(adapter);
5194 /* Fill out the OS statistics structure */
5195 stats->rx_bytes = adapter->stats.gorc;
5196 stats->rx_packets = adapter->stats.gprc;
5197 stats->tx_bytes = adapter->stats.gotc;
5198 stats->tx_packets = adapter->stats.gptc;
5199 stats->multicast = adapter->stats.mprc;
5200 stats->collisions = adapter->stats.colc;
5201
5202 /* Rx Errors */
5203
5204 /*
5205 * RLEC on some newer hardware can be incorrect so build
5206 * our own version based on RUC and ROC
5207 */
5208 stats->rx_errors = adapter->stats.rxerrc +
5209 adapter->stats.crcerrs + adapter->stats.algnerrc +
5210 adapter->stats.ruc + adapter->stats.roc +
5211 adapter->stats.cexterr;
5212 stats->rx_length_errors = adapter->stats.ruc +
5213 adapter->stats.roc;
5214 stats->rx_crc_errors = adapter->stats.crcerrs;
5215 stats->rx_frame_errors = adapter->stats.algnerrc;
5216 stats->rx_missed_errors = adapter->stats.mpc;
5217
5218 /* Tx Errors */
5219 stats->tx_errors = adapter->stats.ecol +
5220 adapter->stats.latecol;
5221 stats->tx_aborted_errors = adapter->stats.ecol;
5222 stats->tx_window_errors = adapter->stats.latecol;
5223 stats->tx_carrier_errors = adapter->stats.tncrs;
5224
5225 /* Tx Dropped needs to be maintained elsewhere */
5226
5227 spin_unlock(&adapter->stats64_lock);
5228 return stats;
bc7f75fa
AK		 5229}
5230
5231/**
5232 * e1000_change_mtu - Change the Maximum Transfer Unit
5233 * @netdev: network interface device structure
5234 * @new_mtu: new value for maximum frame size
5235 *
5236 * Returns 0 on success, negative on failure
5237 **/
5238static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5239{
5240 struct e1000_adapter *adapter = netdev_priv(netdev);
5241 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5242
2adc55c9 5243 /* Jumbo frame support */
2e1706f2
BA		 5244 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5245 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5246 e_err("Jumbo Frames not supported.\n");
5247 return -EINVAL;
bc7f75fa
AK		 5248 }
5249
2adc55c9
BA		 5250 /* Supported frame sizes */
5251 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5252 (max_frame > adapter->max_hw_frame_size)) {
5253 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5254 return -EINVAL;
5255 }
5256
2fbe4526
BA		 5257 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5258 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5259 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5260 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5261 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5262 return -EINVAL;
5263 }
5264
bc7f75fa 5265 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5266 usleep_range(1000, 2000);
610c9928 5267 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5268 adapter->max_frame_size = max_frame;
610c9928
BA		 5269 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5270 netdev->mtu = new_mtu;
bc7f75fa
AK		 5271 if (netif_running(netdev))
5272 e1000e_down(adapter);
5273
ad68076e
BA		 5274 /*
5275 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5276 * means we reserve 2 more, this pushes us to allocate from the next
5277 * larger slab size.
ad68076e 5278 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5279 * However with the new *_jumbo_rx* routines, jumbo receives will use
5280 * fragmented skbs
ad68076e 5281 */
bc7f75fa 5282
9926146b 5283 if (max_frame <= 2048)
bc7f75fa
AK		 5284 adapter->rx_buffer_len = 2048;
5285 else
5286 adapter->rx_buffer_len = 4096;
5287
5288 /* adjust allocation if LPE protects us, and we aren't using SBP */
5289 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5290 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5291 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5292 + ETH_FCS_LEN;
bc7f75fa 5293
bc7f75fa
AK		 5294 if (netif_running(netdev))
5295 e1000e_up(adapter);
5296 else
5297 e1000e_reset(adapter);
5298
5299 clear_bit(__E1000_RESETTING, &adapter->state);
5300
5301 return 0;
5302}
5303
5304static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5305 int cmd)
5306{
5307 struct e1000_adapter *adapter = netdev_priv(netdev);
5308 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5309
318a94d6 5310 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5311 return -EOPNOTSUPP;
5312
5313 switch (cmd) {
5314 case SIOCGMIIPHY:
5315 data->phy_id = adapter->hw.phy.addr;
5316 break;
5317 case SIOCGMIIREG:
b16a002e
BA		 5318 e1000_phy_read_status(adapter);
5319
7c25769f
BA		 5320 switch (data->reg_num & 0x1F) {
5321 case MII_BMCR:
5322 data->val_out = adapter->phy_regs.bmcr;
5323 break;
5324 case MII_BMSR:
5325 data->val_out = adapter->phy_regs.bmsr;
5326 break;
5327 case MII_PHYSID1:
5328 data->val_out = (adapter->hw.phy.id >> 16);
5329 break;
5330 case MII_PHYSID2:
5331 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5332 break;
5333 case MII_ADVERTISE:
5334 data->val_out = adapter->phy_regs.advertise;
5335 break;
5336 case MII_LPA:
5337 data->val_out = adapter->phy_regs.lpa;
5338 break;
5339 case MII_EXPANSION:
5340 data->val_out = adapter->phy_regs.expansion;
5341 break;
5342 case MII_CTRL1000:
5343 data->val_out = adapter->phy_regs.ctrl1000;
5344 break;
5345 case MII_STAT1000:
5346 data->val_out = adapter->phy_regs.stat1000;
5347 break;
5348 case MII_ESTATUS:
5349 data->val_out = adapter->phy_regs.estatus;
5350 break;
5351 default:
bc7f75fa
AK		 5352 return -EIO;
5353 }
bc7f75fa
AK		 5354 break;
5355 case SIOCSMIIREG:
5356 default:
5357 return -EOPNOTSUPP;
5358 }
5359 return 0;
5360}
5361
5362static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5363{
5364 switch (cmd) {
5365 case SIOCGMIIPHY:
5366 case SIOCGMIIREG:
5367 case SIOCSMIIREG:
5368 return e1000_mii_ioctl(netdev, ifr, cmd);
5369 default:
5370 return -EOPNOTSUPP;
5371 }
5372}
5373
a4f58f54
BA		 5374static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5375{
5376 struct e1000_hw *hw = &adapter->hw;
5377 u32 i, mac_reg;
2b6b168d 5378 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5379 int retval = 0;
5380
5381 /* copy MAC RARs to PHY RARs */
d3738bb8 5382 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5383
2b6b168d
BA		 5384 retval = hw->phy.ops.acquire(hw);
5385 if (retval) {
5386 e_err("Could not acquire PHY\n");
5387 return retval;
5388 }
5389
5390 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5391 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5392 if (retval)
75ce1532 5393 goto release;
2b6b168d
BA		 5394
5395 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5396 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5397 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5398 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5399 (u16)(mac_reg & 0xFFFF));
5400 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5401 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5402 }
5403
5404 /* configure PHY Rx Control register */
2b6b168d 5405 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5406 mac_reg = er32(RCTL);
5407 if (mac_reg & E1000_RCTL_UPE)
5408 phy_reg |= BM_RCTL_UPE;
5409 if (mac_reg & E1000_RCTL_MPE)
5410 phy_reg |= BM_RCTL_MPE;
5411 phy_reg &= ~(BM_RCTL_MO_MASK);
5412 if (mac_reg & E1000_RCTL_MO_3)
5413 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5414 << BM_RCTL_MO_SHIFT);
5415 if (mac_reg & E1000_RCTL_BAM)
5416 phy_reg |= BM_RCTL_BAM;
5417 if (mac_reg & E1000_RCTL_PMCF)
5418 phy_reg |= BM_RCTL_PMCF;
5419 mac_reg = er32(CTRL);
5420 if (mac_reg & E1000_CTRL_RFCE)
5421 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5422 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5423
5424 /* enable PHY wakeup in MAC register */
5425 ew32(WUFC, wufc);
5426 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5427
5428 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5429 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5430 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5431
5432 /* activate PHY wakeup */
2b6b168d
BA		 5433 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5434 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5435 if (retval)
5436 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5437release:
94d8186a 5438 hw->phy.ops.release(hw);
a4f58f54
BA		 5439
5440 return retval;
5441}
5442
23606cf5
RW		 5443static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5444 bool runtime)
bc7f75fa
AK		 5445{
5446 struct net_device *netdev = pci_get_drvdata(pdev);
5447 struct e1000_adapter *adapter = netdev_priv(netdev);
5448 struct e1000_hw *hw = &adapter->hw;
5449 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5450 /* Runtime suspend should only enable wakeup for link changes */
5451 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5452 int retval = 0;
5453
5454 netif_device_detach(netdev);
5455
5456 if (netif_running(netdev)) {
bb9e44d0
BA		 5457 int count = E1000_CHECK_RESET_COUNT;
5458
5459 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5460 usleep_range(10000, 20000);
5461
bc7f75fa
AK		 5462 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5463 e1000e_down(adapter);
5464 e1000_free_irq(adapter);
5465 }
4662e82b 5466 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5467
5468 retval = pci_save_state(pdev);
5469 if (retval)
5470 return retval;
5471
5472 status = er32(STATUS);
5473 if (status & E1000_STATUS_LU)
5474 wufc &= ~E1000_WUFC_LNKC;
5475
5476 if (wufc) {
5477 e1000_setup_rctl(adapter);
ef9b965a 5478 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5479
5480 /* turn on all-multi mode if wake on multicast is enabled */
5481 if (wufc & E1000_WUFC_MC) {
5482 rctl = er32(RCTL);
5483 rctl |= E1000_RCTL_MPE;
5484 ew32(RCTL, rctl);
5485 }
5486
5487 ctrl = er32(CTRL);
5488 /* advertise wake from D3Cold */
5489 #define E1000_CTRL_ADVD3WUC 0x00100000
5490 /* phy power management enable */
5491 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5492 ctrl |= E1000_CTRL_ADVD3WUC;
5493 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5494 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5495 ew32(CTRL, ctrl);
5496
318a94d6
JK		 5497 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5498 adapter->hw.phy.media_type ==
5499 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5500 /* keep the laser running in D3 */
5501 ctrl_ext = er32(CTRL_EXT);
93a23f48 5502 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5503 ew32(CTRL_EXT, ctrl_ext);
5504 }
5505
97ac8cae 5506 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5507 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5508
bc7f75fa
AK		 5509 /* Allow time for pending master requests to run */
5510 e1000e_disable_pcie_master(&adapter->hw);
5511
82776a4b 5512 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5513 /* enable wakeup by the PHY */
5514 retval = e1000_init_phy_wakeup(adapter, wufc);
5515 if (retval)
5516 return retval;
5517 } else {
5518 /* enable wakeup by the MAC */
5519 ew32(WUFC, wufc);
5520 ew32(WUC, E1000_WUC_PME_EN);
5521 }
bc7f75fa
AK		 5522 } else {
5523 ew32(WUC, 0);
5524 ew32(WUFC, 0);
bc7f75fa
AK		 5525 }
5526
4f9de721
RW		 5527 *enable_wake = !!wufc;
5528
bc7f75fa 5529 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5530 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5531 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5532 *enable_wake = true;
bc7f75fa
AK		 5533
5534 if (adapter->hw.phy.type == e1000_phy_igp_3)
5535 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5536
ad68076e
BA		 5537 /*
5538 * Release control of h/w to f/w. If f/w is AMT enabled, this
5539 * would have already happened in close and is redundant.
5540 */
31dbe5b4 5541 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5542
5543 pci_disable_device(pdev);
5544
4f9de721
RW		 5545 return 0;
5546}
5547
5548static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5549{
5550 if (sleep && wake) {
5551 pci_prepare_to_sleep(pdev);
5552 return;
5553 }
5554
5555 pci_wake_from_d3(pdev, wake);
5556 pci_set_power_state(pdev, PCI_D3hot);
5557}
5558
5559static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5560 bool wake)
5561{
5562 struct net_device *netdev = pci_get_drvdata(pdev);
5563 struct e1000_adapter *adapter = netdev_priv(netdev);
5564
005cbdfc
AD		 5565 /*
5566 * The pci-e switch on some quad port adapters will report a
5567 * correctable error when the MAC transitions from D0 to D3. To
5568 * prevent this we need to mask off the correctable errors on the
5569 * downstream port of the pci-e switch.
5570 */
5571 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5572 struct pci_dev *us_dev = pdev->bus->self;
353064de 5573 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5574 u16 devctl;
5575
5576 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5577 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5578 (devctl & ~PCI_EXP_DEVCTL_CERE));
5579
4f9de721 5580 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5581
5582 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5583 } else {
4f9de721 5584 e1000_power_off(pdev, sleep, wake);
005cbdfc 5585 }
bc7f75fa
AK		 5586}
5587
6f461f6c
BA		 5588#ifdef CONFIG_PCIEASPM
5589static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5590{
9f728f53 5591 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5592}
5593#else
5594static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5595{
5596 int pos;
6f461f6c 5597 u16 reg16;
1eae4eb2
AK		 5598
5599 /*
6f461f6c
BA		 5600 * Both device and parent should have the same ASPM setting.
5601 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5602 */
6f461f6c
BA		 5603 pos = pci_pcie_cap(pdev);
5604 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5605 reg16 &= ~state;
5606 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5607
0c75ba22
AB		 5608 if (!pdev->bus->self)
5609 return;
5610
6f461f6c
BA		 5611 pos = pci_pcie_cap(pdev->bus->self);
5612 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5613 reg16 &= ~state;
5614 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5615}
5616#endif
78cd29d5 5617static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5618{
5619 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5620 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5621 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5622
5623 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5624}
5625
aa338601 5626#ifdef CONFIG_PM
23606cf5 5627static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5628{
23606cf5 5629 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5630}
5631
23606cf5 5632static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5633{
5634 struct net_device *netdev = pci_get_drvdata(pdev);
5635 struct e1000_adapter *adapter = netdev_priv(netdev);
5636 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5637 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5638 u32 err;
5639
78cd29d5
BA		 5640 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5641 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5642 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5643 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5644 if (aspm_disable_flag)
5645 e1000e_disable_aspm(pdev, aspm_disable_flag);
5646
bc7f75fa
AK		 5647 pci_set_power_state(pdev, PCI_D0);
5648 pci_restore_state(pdev);
28b8f04a 5649 pci_save_state(pdev);
6e4f6f6b 5650
4662e82b 5651 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5652 if (netif_running(netdev)) {
5653 err = e1000_request_irq(adapter);
5654 if (err)
5655 return err;
5656 }
5657
2fbe4526 5658 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 5659 e1000_resume_workarounds_pchlan(&adapter->hw);
5660
bc7f75fa 5661 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5662
5663 /* report the system wakeup cause from S3/S4 */
5664 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5665 u16 phy_data;
5666
5667 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5668 if (phy_data) {
5669 e_info("PHY Wakeup cause - %s\n",
5670 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5671 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5672 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5673 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5674 phy_data & E1000_WUS_LNKC ?
5675 "Link Status Change" : "other");
a4f58f54
BA		 5676 }
5677 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5678 } else {
5679 u32 wus = er32(WUS);
5680 if (wus) {
5681 e_info("MAC Wakeup cause - %s\n",
5682 wus & E1000_WUS_EX ? "Unicast Packet" :
5683 wus & E1000_WUS_MC ? "Multicast Packet" :
5684 wus & E1000_WUS_BC ? "Broadcast Packet" :
5685 wus & E1000_WUS_MAG ? "Magic Packet" :
5686 wus & E1000_WUS_LNKC ? "Link Status Change" :
5687 "other");
5688 }
5689 ew32(WUS, ~0);
5690 }
5691
bc7f75fa 5692 e1000e_reset(adapter);
bc7f75fa 5693
cd791618 5694 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5695
5696 if (netif_running(netdev))
5697 e1000e_up(adapter);
5698
5699 netif_device_attach(netdev);
5700
ad68076e
BA		 5701 /*
5702 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5703 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5704 * under the control of the driver.
5705 */
c43bc57e 5706 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5707 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5708
5709 return 0;
5710}
23606cf5 5711
a0340162
RW		 5712#ifdef CONFIG_PM_SLEEP
5713static int e1000_suspend(struct device *dev)
5714{
5715 struct pci_dev *pdev = to_pci_dev(dev);
5716 int retval;
5717 bool wake;
5718
5719 retval = __e1000_shutdown(pdev, &wake, false);
5720 if (!retval)
5721 e1000_complete_shutdown(pdev, true, wake);
5722
5723 return retval;
5724}
5725
23606cf5
RW		 5726static int e1000_resume(struct device *dev)
5727{
5728 struct pci_dev *pdev = to_pci_dev(dev);
5729 struct net_device *netdev = pci_get_drvdata(pdev);
5730 struct e1000_adapter *adapter = netdev_priv(netdev);
5731
5732 if (e1000e_pm_ready(adapter))
5733 adapter->idle_check = true;
5734
5735 return __e1000_resume(pdev);
5736}
a0340162
RW		 5737#endif /* CONFIG_PM_SLEEP */
5738
5739#ifdef CONFIG_PM_RUNTIME
5740static int e1000_runtime_suspend(struct device *dev)
5741{
5742 struct pci_dev *pdev = to_pci_dev(dev);
5743 struct net_device *netdev = pci_get_drvdata(pdev);
5744 struct e1000_adapter *adapter = netdev_priv(netdev);
5745
5746 if (e1000e_pm_ready(adapter)) {
5747 bool wake;
5748
5749 __e1000_shutdown(pdev, &wake, true);
5750 }
5751
5752 return 0;
5753}
5754
5755static int e1000_idle(struct device *dev)
5756{
5757 struct pci_dev *pdev = to_pci_dev(dev);
5758 struct net_device *netdev = pci_get_drvdata(pdev);
5759 struct e1000_adapter *adapter = netdev_priv(netdev);
5760
5761 if (!e1000e_pm_ready(adapter))
5762 return 0;
5763
5764 if (adapter->idle_check) {
5765 adapter->idle_check = false;
5766 if (!e1000e_has_link(adapter))
5767 pm_schedule_suspend(dev, MSEC_PER_SEC);
5768 }
5769
5770 return -EBUSY;
5771}
23606cf5
RW		 5772
5773static int e1000_runtime_resume(struct device *dev)
5774{
5775 struct pci_dev *pdev = to_pci_dev(dev);
5776 struct net_device *netdev = pci_get_drvdata(pdev);
5777 struct e1000_adapter *adapter = netdev_priv(netdev);
5778
5779 if (!e1000e_pm_ready(adapter))
5780 return 0;
5781
5782 adapter->idle_check = !dev->power.runtime_auto;
5783 return __e1000_resume(pdev);
5784}
a0340162 5785#endif /* CONFIG_PM_RUNTIME */
aa338601 5786#endif /* CONFIG_PM */
bc7f75fa
AK		 5787
5788static void e1000_shutdown(struct pci_dev *pdev)
5789{
4f9de721
RW		 5790 bool wake = false;
5791
23606cf5 5792 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5793
5794 if (system_state == SYSTEM_POWER_OFF)
5795 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5796}
5797
5798#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5799
5800static irqreturn_t e1000_intr_msix(int irq, void *data)
5801{
5802 struct net_device *netdev = data;
5803 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5804
5805 if (adapter->msix_entries) {
90da0669
BA		 5806 int vector, msix_irq;
5807
147b2c8c
DD		 5808 vector = 0;
5809 msix_irq = adapter->msix_entries[vector].vector;
5810 disable_irq(msix_irq);
5811 e1000_intr_msix_rx(msix_irq, netdev);
5812 enable_irq(msix_irq);
5813
5814 vector++;
5815 msix_irq = adapter->msix_entries[vector].vector;
5816 disable_irq(msix_irq);
5817 e1000_intr_msix_tx(msix_irq, netdev);
5818 enable_irq(msix_irq);
5819
5820 vector++;
5821 msix_irq = adapter->msix_entries[vector].vector;
5822 disable_irq(msix_irq);
5823 e1000_msix_other(msix_irq, netdev);
5824 enable_irq(msix_irq);
5825 }
5826
5827 return IRQ_HANDLED;
5828}
5829
bc7f75fa
AK		 5830/*
5831 * Polling 'interrupt' - used by things like netconsole to send skbs
5832 * without having to re-enable interrupts. It's not called while
5833 * the interrupt routine is executing.
5834 */
5835static void e1000_netpoll(struct net_device *netdev)
5836{
5837 struct e1000_adapter *adapter = netdev_priv(netdev);
5838
147b2c8c
DD		 5839 switch (adapter->int_mode) {
5840 case E1000E_INT_MODE_MSIX:
5841 e1000_intr_msix(adapter->pdev->irq, netdev);
5842 break;
5843 case E1000E_INT_MODE_MSI:
5844 disable_irq(adapter->pdev->irq);
5845 e1000_intr_msi(adapter->pdev->irq, netdev);
5846 enable_irq(adapter->pdev->irq);
5847 break;
5848 default: /* E1000E_INT_MODE_LEGACY */
5849 disable_irq(adapter->pdev->irq);
5850 e1000_intr(adapter->pdev->irq, netdev);
5851 enable_irq(adapter->pdev->irq);
5852 break;
5853 }
bc7f75fa
AK		 5854}
5855#endif
5856
5857/**
5858 * e1000_io_error_detected - called when PCI error is detected
5859 * @pdev: Pointer to PCI device
5860 * @state: The current pci connection state
5861 *
5862 * This function is called after a PCI bus error affecting
5863 * this device has been detected.
5864 */
5865static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5866 pci_channel_state_t state)
5867{
5868 struct net_device *netdev = pci_get_drvdata(pdev);
5869 struct e1000_adapter *adapter = netdev_priv(netdev);
5870
5871 netif_device_detach(netdev);
5872
c93b5a76
MM		 5873 if (state == pci_channel_io_perm_failure)
5874 return PCI_ERS_RESULT_DISCONNECT;
5875
bc7f75fa
AK		 5876 if (netif_running(netdev))
5877 e1000e_down(adapter);
5878 pci_disable_device(pdev);
5879
5880 /* Request a slot slot reset. */
5881 return PCI_ERS_RESULT_NEED_RESET;
5882}
5883
5884/**
5885 * e1000_io_slot_reset - called after the pci bus has been reset.
5886 * @pdev: Pointer to PCI device
5887 *
5888 * Restart the card from scratch, as if from a cold-boot. Implementation
5889 * resembles the first-half of the e1000_resume routine.
5890 */
5891static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5892{
5893 struct net_device *netdev = pci_get_drvdata(pdev);
5894 struct e1000_adapter *adapter = netdev_priv(netdev);
5895 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5896 u16 aspm_disable_flag = 0;
6e4f6f6b 5897 int err;
111b9dc5 5898 pci_ers_result_t result;
bc7f75fa 5899
78cd29d5
BA		 5900 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5901 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5902 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5903 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5904 if (aspm_disable_flag)
5905 e1000e_disable_aspm(pdev, aspm_disable_flag);
5906
f0f422e5 5907 err = pci_enable_device_mem(pdev);
6e4f6f6b 5908 if (err) {
bc7f75fa
AK		 5909 dev_err(&pdev->dev,
5910 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5911 result = PCI_ERS_RESULT_DISCONNECT;
5912 } else {
5913 pci_set_master(pdev);
23606cf5 5914 pdev->state_saved = true;
111b9dc5 5915 pci_restore_state(pdev);
bc7f75fa 5916
111b9dc5
JB		 5917 pci_enable_wake(pdev, PCI_D3hot, 0);
5918 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5919
111b9dc5
JB		 5920 e1000e_reset(adapter);
5921 ew32(WUS, ~0);
5922 result = PCI_ERS_RESULT_RECOVERED;
5923 }
bc7f75fa 5924
111b9dc5
JB		 5925 pci_cleanup_aer_uncorrect_error_status(pdev);
5926
5927 return result;
bc7f75fa
AK		 5928}
5929
5930/**
5931 * e1000_io_resume - called when traffic can start flowing again.
5932 * @pdev: Pointer to PCI device
5933 *
5934 * This callback is called when the error recovery driver tells us that
5935 * its OK to resume normal operation. Implementation resembles the
5936 * second-half of the e1000_resume routine.
5937 */
5938static void e1000_io_resume(struct pci_dev *pdev)
5939{
5940 struct net_device *netdev = pci_get_drvdata(pdev);
5941 struct e1000_adapter *adapter = netdev_priv(netdev);
5942
cd791618 5943 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5944
5945 if (netif_running(netdev)) {
5946 if (e1000e_up(adapter)) {
5947 dev_err(&pdev->dev,
5948 "can't bring device back up after reset\n");
5949 return;
5950 }
5951 }
5952
5953 netif_device_attach(netdev);
5954
ad68076e
BA		 5955 /*
5956 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5957 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5958 * under the control of the driver.
5959 */
c43bc57e 5960 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5961 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5962
5963}
5964
5965static void e1000_print_device_info(struct e1000_adapter *adapter)
5966{
5967 struct e1000_hw *hw = &adapter->hw;
5968 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5969 u32 ret_val;
5970 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5971
5972 /* print bus type/speed/width info */
a5cc7642 5973 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5974 /* bus width */
5975 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5976 "Width x1"),
5977 /* MAC address */
7c510e4b 5978 netdev->dev_addr);
44defeb3
JK		 5979 e_info("Intel(R) PRO/%s Network Connection\n",
5980 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5981 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5982 E1000_PBANUM_LENGTH);
5983 if (ret_val)
f2315bf1 5984 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 5985 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5986 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5987}
5988
10aa4c04
AK		 5989static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5990{
5991 struct e1000_hw *hw = &adapter->hw;
5992 int ret_val;
5993 u16 buf = 0;
5994
5995 if (hw->mac.type != e1000_82573)
5996 return;
5997
5998 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 5999 le16_to_cpus(&buf);
6000 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6001 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6002 dev_warn(&adapter->pdev->dev,
6003 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6004 }
10aa4c04
AK		 6005}
6006
c8f44aff 6007static int e1000_set_features(struct net_device *netdev,
70495a50 6008 netdev_features_t features)
dc221294
BA		 6009{
6010 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6011 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6012
6013 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6014 adapter->flags |= FLAG_TSO_FORCE;
6015
6016 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6017 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6018 NETIF_F_RXALL)))
dc221294
BA		 6019 return 0;
6020
0184039a
BG		 6021 if (changed & NETIF_F_RXFCS) {
6022 if (features & NETIF_F_RXFCS) {
6023 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6024 } else {
6025 /* We need to take it back to defaults, which might mean
6026 * stripping is still disabled at the adapter level.
6027 */
6028 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6029 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6030 else
6031 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6032 }
6033 }
6034
70495a50
BA		 6035 netdev->features = features;
6036
dc221294
BA		 6037 if (netif_running(netdev))
6038 e1000e_reinit_locked(adapter);
6039 else
6040 e1000e_reset(adapter);
6041
6042 return 0;
6043}
6044
651c2466
SH		 6045static const struct net_device_ops e1000e_netdev_ops = {
6046 .ndo_open = e1000_open,
6047 .ndo_stop = e1000_close,
00829823 6048 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6049 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6050 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6051 .ndo_set_mac_address = e1000_set_mac,
6052 .ndo_change_mtu = e1000_change_mtu,
6053 .ndo_do_ioctl = e1000_ioctl,
6054 .ndo_tx_timeout = e1000_tx_timeout,
6055 .ndo_validate_addr = eth_validate_addr,
6056
651c2466
SH		 6057 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6058 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6059#ifdef CONFIG_NET_POLL_CONTROLLER
6060 .ndo_poll_controller = e1000_netpoll,
6061#endif
dc221294 6062 .ndo_set_features = e1000_set_features,
651c2466
SH		 6063};
6064
bc7f75fa
AK		 6065/**
6066 * e1000_probe - Device Initialization Routine
6067 * @pdev: PCI device information struct
6068 * @ent: entry in e1000_pci_tbl
6069 *
6070 * Returns 0 on success, negative on failure
6071 *
6072 * e1000_probe initializes an adapter identified by a pci_dev structure.
6073 * The OS initialization, configuring of the adapter private structure,
6074 * and a hardware reset occur.
6075 **/
6076static int __devinit e1000_probe(struct pci_dev *pdev,
6077 const struct pci_device_id *ent)
6078{
6079 struct net_device *netdev;
6080 struct e1000_adapter *adapter;
6081 struct e1000_hw *hw;
6082 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6083 resource_size_t mmio_start, mmio_len;
6084 resource_size_t flash_start, flash_len;
bc7f75fa 6085 static int cards_found;
78cd29d5 6086 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6087 int i, err, pci_using_dac;
6088 u16 eeprom_data = 0;
6089 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6090
78cd29d5
BA		 6091 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6092 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6093 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6094 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6095 if (aspm_disable_flag)
6096 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6097
f0f422e5 6098 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6099 if (err)
6100 return err;
6101
6102 pci_using_dac = 0;
0be3f55f 6103 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6104 if (!err) {
0be3f55f 6105 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6106 if (!err)
6107 pci_using_dac = 1;
6108 } else {
0be3f55f 6109 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6110 if (err) {
0be3f55f
NN		 6111 err = dma_set_coherent_mask(&pdev->dev,
6112 DMA_BIT_MASK(32));
bc7f75fa 6113 if (err) {
ef456f85 6114 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6115 goto err_dma;
6116 }
6117 }
6118 }
6119
e8de1481 6120 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6121 pci_select_bars(pdev, IORESOURCE_MEM),
6122 e1000e_driver_name);
bc7f75fa
AK		 6123 if (err)
6124 goto err_pci_reg;
6125
68eac460 6126 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6127 pci_enable_pcie_error_reporting(pdev);
68eac460 6128
bc7f75fa 6129 pci_set_master(pdev);
438b365a
BA		 6130 /* PCI config space info */
6131 err = pci_save_state(pdev);
6132 if (err)
6133 goto err_alloc_etherdev;
bc7f75fa
AK		 6134
6135 err = -ENOMEM;
6136 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6137 if (!netdev)
6138 goto err_alloc_etherdev;
6139
bc7f75fa
AK		 6140 SET_NETDEV_DEV(netdev, &pdev->dev);
6141
f85e4dfa
TH		 6142 netdev->irq = pdev->irq;
6143
bc7f75fa
AK		 6144 pci_set_drvdata(pdev, netdev);
6145 adapter = netdev_priv(netdev);
6146 hw = &adapter->hw;
6147 adapter->netdev = netdev;
6148 adapter->pdev = pdev;
6149 adapter->ei = ei;
6150 adapter->pba = ei->pba;
6151 adapter->flags = ei->flags;
eb7c3adb 6152 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6153 adapter->hw.adapter = adapter;
6154 adapter->hw.mac.type = ei->mac;
2adc55c9 6155 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6156 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6157
6158 mmio_start = pci_resource_start(pdev, 0);
6159 mmio_len = pci_resource_len(pdev, 0);
6160
6161 err = -EIO;
6162 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6163 if (!adapter->hw.hw_addr)
6164 goto err_ioremap;
6165
6166 if ((adapter->flags & FLAG_HAS_FLASH) &&
6167 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6168 flash_start = pci_resource_start(pdev, 1);
6169 flash_len = pci_resource_len(pdev, 1);
6170 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6171 if (!adapter->hw.flash_address)
6172 goto err_flashmap;
6173 }
6174
6175 /* construct the net_device struct */
651c2466 6176 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6177 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6178 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6179 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6180 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6181
6182 netdev->mem_start = mmio_start;
6183 netdev->mem_end = mmio_start + mmio_len;
6184
6185 adapter->bd_number = cards_found++;
6186
4662e82b
BA		 6187 e1000e_check_options(adapter);
6188
bc7f75fa
AK		 6189 /* setup adapter struct */
6190 err = e1000_sw_init(adapter);
6191 if (err)
6192 goto err_sw_init;
6193
bc7f75fa
AK		 6194 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6195 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6196 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6197
69e3fd8c 6198 err = ei->get_variants(adapter);
bc7f75fa
AK		 6199 if (err)
6200 goto err_hw_init;
6201
4a770358
BA		 6202 if ((adapter->flags & FLAG_IS_ICH) &&
6203 (adapter->flags & FLAG_READ_ONLY_NVM))
6204 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6205
bc7f75fa
AK		 6206 hw->mac.ops.get_bus_info(&adapter->hw);
6207
318a94d6 6208 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6209
6210 /* Copper options */
318a94d6 6211 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6212 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6213 adapter->hw.phy.disable_polarity_correction = 0;
6214 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6215 }
6216
470a5420 6217 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6218 dev_info(&pdev->dev,
6219 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6220
dc221294
BA		 6221 /* Set initial default active device features */
6222 netdev->features = (NETIF_F_SG |
6223 NETIF_F_HW_VLAN_RX |
6224 NETIF_F_HW_VLAN_TX |
6225 NETIF_F_TSO |
6226 NETIF_F_TSO6 |
70495a50 6227 NETIF_F_RXHASH |
dc221294
BA		 6228 NETIF_F_RXCSUM |
6229 NETIF_F_HW_CSUM);
6230
6231 /* Set user-changeable features (subset of all device features) */
6232 netdev->hw_features = netdev->features;
0184039a 6233 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6234 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6235 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6236
6237 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6238 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6239
dc221294
BA		 6240 netdev->vlan_features |= (NETIF_F_SG |
6241 NETIF_F_TSO |
6242 NETIF_F_TSO6 |
6243 NETIF_F_HW_CSUM);
a5136e23 6244
ef9b965a
JB		 6245 netdev->priv_flags |= IFF_UNICAST_FLT;
6246
7b872a55 6247 if (pci_using_dac) {
bc7f75fa 6248 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6249 netdev->vlan_features |= NETIF_F_HIGHDMA;
6250 }
bc7f75fa 6251
bc7f75fa
AK		 6252 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6253 adapter->flags |= FLAG_MNG_PT_ENABLED;
6254
ad68076e
BA		 6255 /*
6256 * before reading the NVM, reset the controller to
6257 * put the device in a known good starting state
6258 */
bc7f75fa
AK		 6259 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6260
6261 /*
6262 * systems with ASPM and others may see the checksum fail on the first
6263 * attempt. Let's give it a few tries
6264 */
6265 for (i = 0;; i++) {
6266 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6267 break;
6268 if (i == 2) {
185095fb 6269 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6270 err = -EIO;
6271 goto err_eeprom;
6272 }
6273 }
6274
10aa4c04
AK		 6275 e1000_eeprom_checks(adapter);
6276
608f8a0d 6277 /* copy the MAC address */
bc7f75fa 6278 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6279 dev_err(&pdev->dev,
6280 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6281
6282 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6283 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6284
6285 if (!is_valid_ether_addr(netdev->perm_addr)) {
185095fb
BA		 6286 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
6287 netdev->perm_addr);
bc7f75fa
AK		 6288 err = -EIO;
6289 goto err_eeprom;
6290 }
6291
6292 init_timer(&adapter->watchdog_timer);
c061b18d 6293 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6294 adapter->watchdog_timer.data = (unsigned long) adapter;
6295
6296 init_timer(&adapter->phy_info_timer);
c061b18d 6297 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6298 adapter->phy_info_timer.data = (unsigned long) adapter;
6299
6300 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6301 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6302 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6303 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6304 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6305
bc7f75fa
AK		 6306 /* Initialize link parameters. User can change them with ethtool */
6307 adapter->hw.mac.autoneg = 1;
3db1cd5c 6308 adapter->fc_autoneg = true;
5c48ef3e
BA		 6309 adapter->hw.fc.requested_mode = e1000_fc_default;
6310 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6311 adapter->hw.phy.autoneg_advertised = 0x2f;
6312
6313 /* ring size defaults */
6314 adapter->rx_ring->count = 256;
6315 adapter->tx_ring->count = 256;
6316
6317 /*
6318 * Initial Wake on LAN setting - If APM wake is enabled in
6319 * the EEPROM, enable the ACPI Magic Packet filter
6320 */
6321 if (adapter->flags & FLAG_APME_IN_WUC) {
6322 /* APME bit in EEPROM is mapped to WUC.APME */
6323 eeprom_data = er32(WUC);
6324 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6325 if ((hw->mac.type > e1000_ich10lan) &&
6326 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6327 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6328 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6329 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6330 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6331 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6332 1, &eeprom_data);
bc7f75fa 6333 else
3d3a1676
BA		 6334 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6335 1, &eeprom_data);
bc7f75fa
AK		 6336 }
6337
6338 /* fetch WoL from EEPROM */
6339 if (eeprom_data & eeprom_apme_mask)
6340 adapter->eeprom_wol |= E1000_WUFC_MAG;
6341
6342 /*
6343 * now that we have the eeprom settings, apply the special cases
6344 * where the eeprom may be wrong or the board simply won't support
6345 * wake on lan on a particular port
6346 */
6347 if (!(adapter->flags & FLAG_HAS_WOL))
6348 adapter->eeprom_wol = 0;
6349
6350 /* initialize the wol settings based on the eeprom settings */
6351 adapter->wol = adapter->eeprom_wol;
6ff68026 6352 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6353
84527590
BA		 6354 /* save off EEPROM version number */
6355 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6356
bc7f75fa
AK		 6357 /* reset the hardware with the new settings */
6358 e1000e_reset(adapter);
6359
ad68076e
BA		 6360 /*
6361 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6362 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6363 * under the control of the driver.
6364 */
c43bc57e 6365 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6366 e1000e_get_hw_control(adapter);
bc7f75fa 6367
f2315bf1 6368 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6369 err = register_netdev(netdev);
6370 if (err)
6371 goto err_register;
6372
9c563d20
JB		 6373 /* carrier off reporting is important to ethtool even BEFORE open */
6374 netif_carrier_off(netdev);
6375
bc7f75fa
AK		 6376 e1000_print_device_info(adapter);
6377
f3ec4f87
AS		 6378 if (pci_dev_run_wake(pdev))
6379 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6380
bc7f75fa
AK		 6381 return 0;
6382
6383err_register:
c43bc57e 6384 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6385 e1000e_release_hw_control(adapter);
bc7f75fa 6386err_eeprom:
470a5420 6387 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6388 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6389err_hw_init:
bc7f75fa
AK		 6390 kfree(adapter->tx_ring);
6391 kfree(adapter->rx_ring);
6392err_sw_init:
c43bc57e
JB		 6393 if (adapter->hw.flash_address)
6394 iounmap(adapter->hw.flash_address);
e82f54ba 6395 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6396err_flashmap:
bc7f75fa
AK		 6397 iounmap(adapter->hw.hw_addr);
6398err_ioremap:
6399 free_netdev(netdev);
6400err_alloc_etherdev:
f0f422e5
BA		 6401 pci_release_selected_regions(pdev,
6402 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6403err_pci_reg:
6404err_dma:
6405 pci_disable_device(pdev);
6406 return err;
6407}
6408
6409/**
6410 * e1000_remove - Device Removal Routine
6411 * @pdev: PCI device information struct
6412 *
6413 * e1000_remove is called by the PCI subsystem to alert the driver
6414 * that it should release a PCI device. The could be caused by a
6415 * Hot-Plug event, or because the driver is going to be removed from
6416 * memory.
6417 **/
6418static void __devexit e1000_remove(struct pci_dev *pdev)
6419{
6420 struct net_device *netdev = pci_get_drvdata(pdev);
6421 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6422 bool down = test_bit(__E1000_DOWN, &adapter->state);
6423
ad68076e 6424 /*
23f333a2
TH		 6425 * The timers may be rescheduled, so explicitly disable them
6426 * from being rescheduled.
ad68076e 6427 */
23606cf5
RW		 6428 if (!down)
6429 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6430 del_timer_sync(&adapter->watchdog_timer);
6431 del_timer_sync(&adapter->phy_info_timer);
6432
41cec6f1
BA		 6433 cancel_work_sync(&adapter->reset_task);
6434 cancel_work_sync(&adapter->watchdog_task);
6435 cancel_work_sync(&adapter->downshift_task);
6436 cancel_work_sync(&adapter->update_phy_task);
6437 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6438
17f208de
BA		 6439 if (!(netdev->flags & IFF_UP))
6440 e1000_power_down_phy(adapter);
6441
23606cf5
RW		 6442 /* Don't lie to e1000_close() down the road. */
6443 if (!down)
6444 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6445 unregister_netdev(netdev);
6446
f3ec4f87
AS		 6447 if (pci_dev_run_wake(pdev))
6448 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6449
ad68076e
BA		 6450 /*
6451 * Release control of h/w to f/w. If f/w is AMT enabled, this
6452 * would have already happened in close and is redundant.
6453 */
31dbe5b4 6454 e1000e_release_hw_control(adapter);
bc7f75fa 6455
4662e82b 6456 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6457 kfree(adapter->tx_ring);
6458 kfree(adapter->rx_ring);
6459
6460 iounmap(adapter->hw.hw_addr);
6461 if (adapter->hw.flash_address)
6462 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6463 pci_release_selected_regions(pdev,
6464 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6465
6466 free_netdev(netdev);
6467
111b9dc5 6468 /* AER disable */
19d5afd4 6469 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6470
bc7f75fa
AK		 6471 pci_disable_device(pdev);
6472}
6473
6474/* PCI Error Recovery (ERS) */
6475static struct pci_error_handlers e1000_err_handler = {
6476 .error_detected = e1000_io_error_detected,
6477 .slot_reset = e1000_io_slot_reset,
6478 .resume = e1000_io_resume,
6479};
6480
a3aa1884 6481static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6491
bc7f75fa
AK		 6492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6496
bc7f75fa
AK		 6497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6500
4662e82b 6501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6504
bc7f75fa
AK		 6505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6506 board_80003es2lan },
6507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6508 board_80003es2lan },
6509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6510 board_80003es2lan },
6511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6512 board_80003es2lan },
ad68076e 6513
bc7f75fa
AK		 6514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6522
bc7f75fa
AK		 6523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6525 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6529 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6532
6533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6534 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6535 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6536
f4187b56
BA		 6537 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6540
a4f58f54
BA		 6541 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6542 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6545
d3738bb8
BA		 6546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6548
2fbe4526
BA		 6549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
6551
f36bb6ca 6552 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6553};
6554MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6555
aa338601 6556#ifdef CONFIG_PM
23606cf5 6557static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6558 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6559 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6560 e1000_runtime_resume, e1000_idle)
23606cf5 6561};
e50208a0 6562#endif
23606cf5 6563
bc7f75fa
AK		 6564/* PCI Device API Driver */
6565static struct pci_driver e1000_driver = {
6566 .name = e1000e_driver_name,
6567 .id_table = e1000_pci_tbl,
6568 .probe = e1000_probe,
6569 .remove = __devexit_p(e1000_remove),
aa338601 6570#ifdef CONFIG_PM
f36bb6ca
BA		 6571 .driver = {
6572 .pm = &e1000_pm_ops,
6573 },
bc7f75fa
AK		 6574#endif
6575 .shutdown = e1000_shutdown,
6576 .err_handler = &e1000_err_handler
6577};
6578
6579/**
6580 * e1000_init_module - Driver Registration Routine
6581 *
6582 * e1000_init_module is the first routine called when the driver is
6583 * loaded. All it does is register with the PCI subsystem.
6584 **/
6585static int __init e1000_init_module(void)
6586{
6587 int ret;
8544b9f7
BA		 6588 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6589 e1000e_driver_version);
f5e261e6 6590 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6591 ret = pci_register_driver(&e1000_driver);
53ec5498 6592
bc7f75fa
AK		 6593 return ret;
6594}
6595module_init(e1000_init_module);
6596
6597/**
6598 * e1000_exit_module - Driver Exit Cleanup Routine
6599 *
6600 * e1000_exit_module is called just before the driver is removed
6601 * from memory.
6602 **/
6603static void __exit e1000_exit_module(void)
6604{
6605 pci_unregister_driver(&e1000_driver);
6606}
6607module_exit(e1000_exit_module);
6608
6609
6610MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6611MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6612MODULE_LICENSE("GPL");
6613MODULE_VERSION(DRV_VERSION);
6614
06c24b91 6615/* netdev.c */
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