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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
bf67044b | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
8544b9f7 BA |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
bc7f75fa AK |
31 | #include <linux/module.h> |
32 | #include <linux/types.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/vmalloc.h> | |
36 | #include <linux/pagemap.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/netdevice.h> | |
9fb7a5f7 | 39 | #include <linux/interrupt.h> |
bc7f75fa AK |
40 | #include <linux/tcp.h> |
41 | #include <linux/ipv6.h> | |
5a0e3ad6 | 42 | #include <linux/slab.h> |
bc7f75fa AK |
43 | #include <net/checksum.h> |
44 | #include <net/ip6_checksum.h> | |
bc7f75fa AK |
45 | #include <linux/ethtool.h> |
46 | #include <linux/if_vlan.h> | |
47 | #include <linux/cpu.h> | |
48 | #include <linux/smp.h> | |
e8db0be1 | 49 | #include <linux/pm_qos.h> |
23606cf5 | 50 | #include <linux/pm_runtime.h> |
111b9dc5 | 51 | #include <linux/aer.h> |
70c71606 | 52 | #include <linux/prefetch.h> |
bc7f75fa AK |
53 | |
54 | #include "e1000.h" | |
55 | ||
b3ccf267 | 56 | #define DRV_EXTRAVERSION "-k" |
c14c643b | 57 | |
8defe713 | 58 | #define DRV_VERSION "2.3.2" DRV_EXTRAVERSION |
bc7f75fa AK |
59 | char e1000e_driver_name[] = "e1000e"; |
60 | const char e1000e_driver_version[] = DRV_VERSION; | |
61 | ||
b3f4d599 | 62 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
63 | static int debug = -1; | |
64 | module_param(debug, int, 0); | |
65 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
66 | ||
bc7f75fa AK |
67 | static const struct e1000_info *e1000_info_tbl[] = { |
68 | [board_82571] = &e1000_82571_info, | |
69 | [board_82572] = &e1000_82572_info, | |
70 | [board_82573] = &e1000_82573_info, | |
4662e82b | 71 | [board_82574] = &e1000_82574_info, |
8c81c9c3 | 72 | [board_82583] = &e1000_82583_info, |
bc7f75fa AK |
73 | [board_80003es2lan] = &e1000_es2_info, |
74 | [board_ich8lan] = &e1000_ich8_info, | |
75 | [board_ich9lan] = &e1000_ich9_info, | |
f4187b56 | 76 | [board_ich10lan] = &e1000_ich10_info, |
a4f58f54 | 77 | [board_pchlan] = &e1000_pch_info, |
d3738bb8 | 78 | [board_pch2lan] = &e1000_pch2_info, |
2fbe4526 | 79 | [board_pch_lpt] = &e1000_pch_lpt_info, |
bc7f75fa AK |
80 | }; |
81 | ||
84f4ee90 TI |
82 | struct e1000_reg_info { |
83 | u32 ofs; | |
84 | char *name; | |
85 | }; | |
86 | ||
84f4ee90 | 87 | static const struct e1000_reg_info e1000_reg_info_tbl[] = { |
84f4ee90 TI |
88 | /* General Registers */ |
89 | {E1000_CTRL, "CTRL"}, | |
90 | {E1000_STATUS, "STATUS"}, | |
91 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
92 | ||
93 | /* Interrupt Registers */ | |
94 | {E1000_ICR, "ICR"}, | |
95 | ||
af667a29 | 96 | /* Rx Registers */ |
84f4ee90 | 97 | {E1000_RCTL, "RCTL"}, |
1e36052e BA |
98 | {E1000_RDLEN(0), "RDLEN"}, |
99 | {E1000_RDH(0), "RDH"}, | |
100 | {E1000_RDT(0), "RDT"}, | |
84f4ee90 TI |
101 | {E1000_RDTR, "RDTR"}, |
102 | {E1000_RXDCTL(0), "RXDCTL"}, | |
103 | {E1000_ERT, "ERT"}, | |
1e36052e BA |
104 | {E1000_RDBAL(0), "RDBAL"}, |
105 | {E1000_RDBAH(0), "RDBAH"}, | |
84f4ee90 TI |
106 | {E1000_RDFH, "RDFH"}, |
107 | {E1000_RDFT, "RDFT"}, | |
108 | {E1000_RDFHS, "RDFHS"}, | |
109 | {E1000_RDFTS, "RDFTS"}, | |
110 | {E1000_RDFPC, "RDFPC"}, | |
111 | ||
af667a29 | 112 | /* Tx Registers */ |
84f4ee90 | 113 | {E1000_TCTL, "TCTL"}, |
1e36052e BA |
114 | {E1000_TDBAL(0), "TDBAL"}, |
115 | {E1000_TDBAH(0), "TDBAH"}, | |
116 | {E1000_TDLEN(0), "TDLEN"}, | |
117 | {E1000_TDH(0), "TDH"}, | |
118 | {E1000_TDT(0), "TDT"}, | |
84f4ee90 TI |
119 | {E1000_TIDV, "TIDV"}, |
120 | {E1000_TXDCTL(0), "TXDCTL"}, | |
121 | {E1000_TADV, "TADV"}, | |
122 | {E1000_TARC(0), "TARC"}, | |
123 | {E1000_TDFH, "TDFH"}, | |
124 | {E1000_TDFT, "TDFT"}, | |
125 | {E1000_TDFHS, "TDFHS"}, | |
126 | {E1000_TDFTS, "TDFTS"}, | |
127 | {E1000_TDFPC, "TDFPC"}, | |
128 | ||
129 | /* List Terminator */ | |
f36bb6ca | 130 | {0, NULL} |
84f4ee90 TI |
131 | }; |
132 | ||
e921eb1a | 133 | /** |
84f4ee90 | 134 | * e1000_regdump - register printout routine |
e921eb1a BA |
135 | * @hw: pointer to the HW structure |
136 | * @reginfo: pointer to the register info table | |
137 | **/ | |
84f4ee90 TI |
138 | static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) |
139 | { | |
140 | int n = 0; | |
141 | char rname[16]; | |
142 | u32 regs[8]; | |
143 | ||
144 | switch (reginfo->ofs) { | |
145 | case E1000_RXDCTL(0): | |
146 | for (n = 0; n < 2; n++) | |
147 | regs[n] = __er32(hw, E1000_RXDCTL(n)); | |
148 | break; | |
149 | case E1000_TXDCTL(0): | |
150 | for (n = 0; n < 2; n++) | |
151 | regs[n] = __er32(hw, E1000_TXDCTL(n)); | |
152 | break; | |
153 | case E1000_TARC(0): | |
154 | for (n = 0; n < 2; n++) | |
155 | regs[n] = __er32(hw, E1000_TARC(n)); | |
156 | break; | |
157 | default: | |
ef456f85 JK |
158 | pr_info("%-15s %08x\n", |
159 | reginfo->name, __er32(hw, reginfo->ofs)); | |
84f4ee90 TI |
160 | return; |
161 | } | |
162 | ||
163 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); | |
ef456f85 | 164 | pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); |
84f4ee90 TI |
165 | } |
166 | ||
f0c5dadf ET |
167 | static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, |
168 | struct e1000_buffer *bi) | |
169 | { | |
170 | int i; | |
171 | struct e1000_ps_page *ps_page; | |
172 | ||
173 | for (i = 0; i < adapter->rx_ps_pages; i++) { | |
174 | ps_page = &bi->ps_pages[i]; | |
175 | ||
176 | if (ps_page->page) { | |
177 | pr_info("packet dump for ps_page %d:\n", i); | |
178 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, | |
179 | 16, 1, page_address(ps_page->page), | |
180 | PAGE_SIZE, true); | |
181 | } | |
182 | } | |
183 | } | |
184 | ||
e921eb1a | 185 | /** |
af667a29 | 186 | * e1000e_dump - Print registers, Tx-ring and Rx-ring |
e921eb1a BA |
187 | * @adapter: board private structure |
188 | **/ | |
84f4ee90 TI |
189 | static void e1000e_dump(struct e1000_adapter *adapter) |
190 | { | |
191 | struct net_device *netdev = adapter->netdev; | |
192 | struct e1000_hw *hw = &adapter->hw; | |
193 | struct e1000_reg_info *reginfo; | |
194 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
195 | struct e1000_tx_desc *tx_desc; | |
af667a29 | 196 | struct my_u0 { |
e885d762 BA |
197 | __le64 a; |
198 | __le64 b; | |
af667a29 | 199 | } *u0; |
84f4ee90 TI |
200 | struct e1000_buffer *buffer_info; |
201 | struct e1000_ring *rx_ring = adapter->rx_ring; | |
202 | union e1000_rx_desc_packet_split *rx_desc_ps; | |
5f450212 | 203 | union e1000_rx_desc_extended *rx_desc; |
af667a29 | 204 | struct my_u1 { |
e885d762 BA |
205 | __le64 a; |
206 | __le64 b; | |
207 | __le64 c; | |
208 | __le64 d; | |
af667a29 | 209 | } *u1; |
84f4ee90 TI |
210 | u32 staterr; |
211 | int i = 0; | |
212 | ||
213 | if (!netif_msg_hw(adapter)) | |
214 | return; | |
215 | ||
216 | /* Print netdevice Info */ | |
217 | if (netdev) { | |
218 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
ef456f85 | 219 | pr_info("Device Name state trans_start last_rx\n"); |
e5fe2541 BA |
220 | pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, |
221 | netdev->state, netdev->trans_start, netdev->last_rx); | |
84f4ee90 TI |
222 | } |
223 | ||
224 | /* Print Registers */ | |
225 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
ef456f85 | 226 | pr_info(" Register Name Value\n"); |
84f4ee90 TI |
227 | for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; |
228 | reginfo->name; reginfo++) { | |
229 | e1000_regdump(hw, reginfo); | |
230 | } | |
231 | ||
af667a29 | 232 | /* Print Tx Ring Summary */ |
84f4ee90 | 233 | if (!netdev || !netif_running(netdev)) |
fe1e980f | 234 | return; |
84f4ee90 | 235 | |
af667a29 | 236 | dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); |
ef456f85 | 237 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
84f4ee90 | 238 | buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; |
ef456f85 JK |
239 | pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", |
240 | 0, tx_ring->next_to_use, tx_ring->next_to_clean, | |
241 | (unsigned long long)buffer_info->dma, | |
242 | buffer_info->length, | |
243 | buffer_info->next_to_watch, | |
244 | (unsigned long long)buffer_info->time_stamp); | |
84f4ee90 | 245 | |
af667a29 | 246 | /* Print Tx Ring */ |
84f4ee90 TI |
247 | if (!netif_msg_tx_done(adapter)) |
248 | goto rx_ring_summary; | |
249 | ||
af667a29 | 250 | dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); |
84f4ee90 TI |
251 | |
252 | /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) | |
253 | * | |
254 | * Legacy Transmit Descriptor | |
255 | * +--------------------------------------------------------------+ | |
256 | * 0 | Buffer Address [63:0] (Reserved on Write Back) | | |
257 | * +--------------------------------------------------------------+ | |
258 | * 8 | Special | CSS | Status | CMD | CSO | Length | | |
259 | * +--------------------------------------------------------------+ | |
260 | * 63 48 47 36 35 32 31 24 23 16 15 0 | |
261 | * | |
262 | * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload | |
263 | * 63 48 47 40 39 32 31 16 15 8 7 0 | |
264 | * +----------------------------------------------------------------+ | |
265 | * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | | |
266 | * +----------------------------------------------------------------+ | |
267 | * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | | |
268 | * +----------------------------------------------------------------+ | |
269 | * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 | |
270 | * | |
271 | * Extended Data Descriptor (DTYP=0x1) | |
272 | * +----------------------------------------------------------------+ | |
273 | * 0 | Buffer Address [63:0] | | |
274 | * +----------------------------------------------------------------+ | |
275 | * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | | |
276 | * +----------------------------------------------------------------+ | |
277 | * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 | |
278 | */ | |
ef456f85 JK |
279 | pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); |
280 | pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); | |
281 | pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); | |
84f4ee90 | 282 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { |
ef456f85 | 283 | const char *next_desc; |
84f4ee90 TI |
284 | tx_desc = E1000_TX_DESC(*tx_ring, i); |
285 | buffer_info = &tx_ring->buffer_info[i]; | |
286 | u0 = (struct my_u0 *)tx_desc; | |
84f4ee90 | 287 | if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) |
ef456f85 | 288 | next_desc = " NTC/U"; |
84f4ee90 | 289 | else if (i == tx_ring->next_to_use) |
ef456f85 | 290 | next_desc = " NTU"; |
84f4ee90 | 291 | else if (i == tx_ring->next_to_clean) |
ef456f85 | 292 | next_desc = " NTC"; |
84f4ee90 | 293 | else |
ef456f85 JK |
294 | next_desc = ""; |
295 | pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", | |
296 | (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' : | |
297 | ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')), | |
298 | i, | |
299 | (unsigned long long)le64_to_cpu(u0->a), | |
300 | (unsigned long long)le64_to_cpu(u0->b), | |
301 | (unsigned long long)buffer_info->dma, | |
302 | buffer_info->length, buffer_info->next_to_watch, | |
303 | (unsigned long long)buffer_info->time_stamp, | |
304 | buffer_info->skb, next_desc); | |
84f4ee90 | 305 | |
f0c5dadf | 306 | if (netif_msg_pktdata(adapter) && buffer_info->skb) |
84f4ee90 | 307 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, |
f0c5dadf ET |
308 | 16, 1, buffer_info->skb->data, |
309 | buffer_info->skb->len, true); | |
84f4ee90 TI |
310 | } |
311 | ||
af667a29 | 312 | /* Print Rx Ring Summary */ |
84f4ee90 | 313 | rx_ring_summary: |
af667a29 | 314 | dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); |
ef456f85 JK |
315 | pr_info("Queue [NTU] [NTC]\n"); |
316 | pr_info(" %5d %5X %5X\n", | |
317 | 0, rx_ring->next_to_use, rx_ring->next_to_clean); | |
84f4ee90 | 318 | |
af667a29 | 319 | /* Print Rx Ring */ |
84f4ee90 | 320 | if (!netif_msg_rx_status(adapter)) |
fe1e980f | 321 | return; |
84f4ee90 | 322 | |
af667a29 | 323 | dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); |
84f4ee90 TI |
324 | switch (adapter->rx_ps_pages) { |
325 | case 1: | |
326 | case 2: | |
327 | case 3: | |
328 | /* [Extended] Packet Split Receive Descriptor Format | |
329 | * | |
330 | * +-----------------------------------------------------+ | |
331 | * 0 | Buffer Address 0 [63:0] | | |
332 | * +-----------------------------------------------------+ | |
333 | * 8 | Buffer Address 1 [63:0] | | |
334 | * +-----------------------------------------------------+ | |
335 | * 16 | Buffer Address 2 [63:0] | | |
336 | * +-----------------------------------------------------+ | |
337 | * 24 | Buffer Address 3 [63:0] | | |
338 | * +-----------------------------------------------------+ | |
339 | */ | |
ef456f85 | 340 | pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); |
84f4ee90 TI |
341 | /* [Extended] Receive Descriptor (Write-Back) Format |
342 | * | |
343 | * 63 48 47 32 31 13 12 8 7 4 3 0 | |
344 | * +------------------------------------------------------+ | |
345 | * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | | |
346 | * | Checksum | Ident | | Queue | | Type | | |
347 | * +------------------------------------------------------+ | |
348 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
349 | * +------------------------------------------------------+ | |
350 | * 63 48 47 32 31 20 19 0 | |
351 | */ | |
ef456f85 | 352 | pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); |
84f4ee90 | 353 | for (i = 0; i < rx_ring->count; i++) { |
ef456f85 | 354 | const char *next_desc; |
84f4ee90 TI |
355 | buffer_info = &rx_ring->buffer_info[i]; |
356 | rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); | |
357 | u1 = (struct my_u1 *)rx_desc_ps; | |
358 | staterr = | |
af667a29 | 359 | le32_to_cpu(rx_desc_ps->wb.middle.status_error); |
ef456f85 JK |
360 | |
361 | if (i == rx_ring->next_to_use) | |
362 | next_desc = " NTU"; | |
363 | else if (i == rx_ring->next_to_clean) | |
364 | next_desc = " NTC"; | |
365 | else | |
366 | next_desc = ""; | |
367 | ||
84f4ee90 TI |
368 | if (staterr & E1000_RXD_STAT_DD) { |
369 | /* Descriptor Done */ | |
ef456f85 JK |
370 | pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", |
371 | "RWB", i, | |
372 | (unsigned long long)le64_to_cpu(u1->a), | |
373 | (unsigned long long)le64_to_cpu(u1->b), | |
374 | (unsigned long long)le64_to_cpu(u1->c), | |
375 | (unsigned long long)le64_to_cpu(u1->d), | |
376 | buffer_info->skb, next_desc); | |
84f4ee90 | 377 | } else { |
ef456f85 JK |
378 | pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", |
379 | "R ", i, | |
380 | (unsigned long long)le64_to_cpu(u1->a), | |
381 | (unsigned long long)le64_to_cpu(u1->b), | |
382 | (unsigned long long)le64_to_cpu(u1->c), | |
383 | (unsigned long long)le64_to_cpu(u1->d), | |
384 | (unsigned long long)buffer_info->dma, | |
385 | buffer_info->skb, next_desc); | |
84f4ee90 TI |
386 | |
387 | if (netif_msg_pktdata(adapter)) | |
f0c5dadf ET |
388 | e1000e_dump_ps_pages(adapter, |
389 | buffer_info); | |
84f4ee90 | 390 | } |
84f4ee90 TI |
391 | } |
392 | break; | |
393 | default: | |
394 | case 0: | |
5f450212 | 395 | /* Extended Receive Descriptor (Read) Format |
84f4ee90 | 396 | * |
5f450212 BA |
397 | * +-----------------------------------------------------+ |
398 | * 0 | Buffer Address [63:0] | | |
399 | * +-----------------------------------------------------+ | |
400 | * 8 | Reserved | | |
401 | * +-----------------------------------------------------+ | |
84f4ee90 | 402 | */ |
ef456f85 | 403 | pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); |
5f450212 BA |
404 | /* Extended Receive Descriptor (Write-Back) Format |
405 | * | |
406 | * 63 48 47 32 31 24 23 4 3 0 | |
407 | * +------------------------------------------------------+ | |
408 | * | RSS Hash | | | | | |
409 | * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | | |
410 | * | Packet | IP | | | Type | | |
411 | * | Checksum | Ident | | | | | |
412 | * +------------------------------------------------------+ | |
413 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
414 | * +------------------------------------------------------+ | |
415 | * 63 48 47 32 31 20 19 0 | |
416 | */ | |
ef456f85 | 417 | pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); |
5f450212 BA |
418 | |
419 | for (i = 0; i < rx_ring->count; i++) { | |
ef456f85 JK |
420 | const char *next_desc; |
421 | ||
84f4ee90 | 422 | buffer_info = &rx_ring->buffer_info[i]; |
5f450212 BA |
423 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
424 | u1 = (struct my_u1 *)rx_desc; | |
425 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
ef456f85 JK |
426 | |
427 | if (i == rx_ring->next_to_use) | |
428 | next_desc = " NTU"; | |
429 | else if (i == rx_ring->next_to_clean) | |
430 | next_desc = " NTC"; | |
431 | else | |
432 | next_desc = ""; | |
433 | ||
5f450212 BA |
434 | if (staterr & E1000_RXD_STAT_DD) { |
435 | /* Descriptor Done */ | |
ef456f85 JK |
436 | pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", |
437 | "RWB", i, | |
438 | (unsigned long long)le64_to_cpu(u1->a), | |
439 | (unsigned long long)le64_to_cpu(u1->b), | |
440 | buffer_info->skb, next_desc); | |
5f450212 | 441 | } else { |
ef456f85 JK |
442 | pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", |
443 | "R ", i, | |
444 | (unsigned long long)le64_to_cpu(u1->a), | |
445 | (unsigned long long)le64_to_cpu(u1->b), | |
446 | (unsigned long long)buffer_info->dma, | |
447 | buffer_info->skb, next_desc); | |
5f450212 | 448 | |
f0c5dadf ET |
449 | if (netif_msg_pktdata(adapter) && |
450 | buffer_info->skb) | |
5f450212 BA |
451 | print_hex_dump(KERN_INFO, "", |
452 | DUMP_PREFIX_ADDRESS, 16, | |
453 | 1, | |
f0c5dadf | 454 | buffer_info->skb->data, |
5f450212 BA |
455 | adapter->rx_buffer_len, |
456 | true); | |
457 | } | |
84f4ee90 TI |
458 | } |
459 | } | |
84f4ee90 TI |
460 | } |
461 | ||
bc7f75fa AK |
462 | /** |
463 | * e1000_desc_unused - calculate if we have unused descriptors | |
464 | **/ | |
465 | static int e1000_desc_unused(struct e1000_ring *ring) | |
466 | { | |
467 | if (ring->next_to_clean > ring->next_to_use) | |
468 | return ring->next_to_clean - ring->next_to_use - 1; | |
469 | ||
470 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | |
471 | } | |
472 | ||
b67e1913 BA |
473 | /** |
474 | * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp | |
475 | * @adapter: board private structure | |
476 | * @hwtstamps: time stamp structure to update | |
477 | * @systim: unsigned 64bit system time value. | |
478 | * | |
479 | * Convert the system time value stored in the RX/TXSTMP registers into a | |
480 | * hwtstamp which can be used by the upper level time stamping functions. | |
481 | * | |
482 | * The 'systim_lock' spinlock is used to protect the consistency of the | |
483 | * system time value. This is needed because reading the 64 bit time | |
484 | * value involves reading two 32 bit registers. The first read latches the | |
485 | * value. | |
486 | **/ | |
487 | static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, | |
488 | struct skb_shared_hwtstamps *hwtstamps, | |
489 | u64 systim) | |
490 | { | |
491 | u64 ns; | |
492 | unsigned long flags; | |
493 | ||
494 | spin_lock_irqsave(&adapter->systim_lock, flags); | |
495 | ns = timecounter_cyc2time(&adapter->tc, systim); | |
496 | spin_unlock_irqrestore(&adapter->systim_lock, flags); | |
497 | ||
498 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
499 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
500 | } | |
501 | ||
502 | /** | |
503 | * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp | |
504 | * @adapter: board private structure | |
505 | * @status: descriptor extended error and status field | |
506 | * @skb: particular skb to include time stamp | |
507 | * | |
508 | * If the time stamp is valid, convert it into the timecounter ns value | |
509 | * and store that result into the shhwtstamps structure which is passed | |
510 | * up the network stack. | |
511 | **/ | |
512 | static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, | |
513 | struct sk_buff *skb) | |
514 | { | |
515 | struct e1000_hw *hw = &adapter->hw; | |
516 | u64 rxstmp; | |
517 | ||
518 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || | |
519 | !(status & E1000_RXDEXT_STATERR_TST) || | |
520 | !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) | |
521 | return; | |
522 | ||
523 | /* The Rx time stamp registers contain the time stamp. No other | |
524 | * received packet will be time stamped until the Rx time stamp | |
525 | * registers are read. Because only one packet can be time stamped | |
526 | * at a time, the register values must belong to this packet and | |
527 | * therefore none of the other additional attributes need to be | |
528 | * compared. | |
529 | */ | |
530 | rxstmp = (u64)er32(RXSTMPL); | |
531 | rxstmp |= (u64)er32(RXSTMPH) << 32; | |
532 | e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); | |
533 | ||
534 | adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; | |
535 | } | |
536 | ||
bc7f75fa | 537 | /** |
ad68076e | 538 | * e1000_receive_skb - helper function to handle Rx indications |
bc7f75fa | 539 | * @adapter: board private structure |
b67e1913 | 540 | * @staterr: descriptor extended error and status field as written by hardware |
bc7f75fa AK |
541 | * @vlan: descriptor vlan field as written by hardware (no le/be conversion) |
542 | * @skb: pointer to sk_buff to be indicated to stack | |
543 | **/ | |
544 | static void e1000_receive_skb(struct e1000_adapter *adapter, | |
af667a29 | 545 | struct net_device *netdev, struct sk_buff *skb, |
b67e1913 | 546 | u32 staterr, __le16 vlan) |
bc7f75fa | 547 | { |
86d70e53 | 548 | u16 tag = le16_to_cpu(vlan); |
b67e1913 BA |
549 | |
550 | e1000e_rx_hwtstamp(adapter, staterr, skb); | |
551 | ||
bc7f75fa AK |
552 | skb->protocol = eth_type_trans(skb, netdev); |
553 | ||
b67e1913 | 554 | if (staterr & E1000_RXD_STAT_VP) |
86a9bad3 | 555 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); |
86d70e53 JK |
556 | |
557 | napi_gro_receive(&adapter->napi, skb); | |
bc7f75fa AK |
558 | } |
559 | ||
560 | /** | |
af667a29 | 561 | * e1000_rx_checksum - Receive Checksum Offload |
afd12939 BA |
562 | * @adapter: board private structure |
563 | * @status_err: receive descriptor status and error fields | |
564 | * @csum: receive descriptor csum field | |
565 | * @sk_buff: socket buffer with received data | |
bc7f75fa AK |
566 | **/ |
567 | static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, | |
2e1706f2 | 568 | struct sk_buff *skb) |
bc7f75fa AK |
569 | { |
570 | u16 status = (u16)status_err; | |
571 | u8 errors = (u8)(status_err >> 24); | |
bc8acf2c ED |
572 | |
573 | skb_checksum_none_assert(skb); | |
bc7f75fa | 574 | |
afd12939 BA |
575 | /* Rx checksum disabled */ |
576 | if (!(adapter->netdev->features & NETIF_F_RXCSUM)) | |
577 | return; | |
578 | ||
bc7f75fa AK |
579 | /* Ignore Checksum bit is set */ |
580 | if (status & E1000_RXD_STAT_IXSM) | |
581 | return; | |
afd12939 | 582 | |
2e1706f2 BA |
583 | /* TCP/UDP checksum error bit or IP checksum error bit is set */ |
584 | if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { | |
bc7f75fa AK |
585 | /* let the stack verify checksum errors */ |
586 | adapter->hw_csum_err++; | |
587 | return; | |
588 | } | |
589 | ||
590 | /* TCP/UDP Checksum has not been calculated */ | |
591 | if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) | |
592 | return; | |
593 | ||
594 | /* It must be a TCP or UDP packet with a valid checksum */ | |
2e1706f2 | 595 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
bc7f75fa AK |
596 | adapter->hw_csum_good++; |
597 | } | |
598 | ||
55aa6985 | 599 | static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) |
c6e7f51e | 600 | { |
55aa6985 | 601 | struct e1000_adapter *adapter = rx_ring->adapter; |
c6e7f51e | 602 | struct e1000_hw *hw = &adapter->hw; |
bdc125f7 BA |
603 | s32 ret_val = __ew32_prepare(hw); |
604 | ||
605 | writel(i, rx_ring->tail); | |
c6e7f51e | 606 | |
bdc125f7 | 607 | if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { |
c6e7f51e BA |
608 | u32 rctl = er32(RCTL); |
609 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
610 | e_err("ME firmware caused invalid RDT - resetting\n"); | |
611 | schedule_work(&adapter->reset_task); | |
612 | } | |
613 | } | |
614 | ||
55aa6985 | 615 | static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) |
c6e7f51e | 616 | { |
55aa6985 | 617 | struct e1000_adapter *adapter = tx_ring->adapter; |
c6e7f51e | 618 | struct e1000_hw *hw = &adapter->hw; |
bdc125f7 | 619 | s32 ret_val = __ew32_prepare(hw); |
c6e7f51e | 620 | |
bdc125f7 BA |
621 | writel(i, tx_ring->tail); |
622 | ||
623 | if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { | |
c6e7f51e BA |
624 | u32 tctl = er32(TCTL); |
625 | ew32(TCTL, tctl & ~E1000_TCTL_EN); | |
626 | e_err("ME firmware caused invalid TDT - resetting\n"); | |
627 | schedule_work(&adapter->reset_task); | |
628 | } | |
629 | } | |
630 | ||
bc7f75fa | 631 | /** |
5f450212 | 632 | * e1000_alloc_rx_buffers - Replace used receive buffers |
55aa6985 | 633 | * @rx_ring: Rx descriptor ring |
bc7f75fa | 634 | **/ |
55aa6985 | 635 | static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, |
c2fed996 | 636 | int cleaned_count, gfp_t gfp) |
bc7f75fa | 637 | { |
55aa6985 | 638 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
639 | struct net_device *netdev = adapter->netdev; |
640 | struct pci_dev *pdev = adapter->pdev; | |
5f450212 | 641 | union e1000_rx_desc_extended *rx_desc; |
bc7f75fa AK |
642 | struct e1000_buffer *buffer_info; |
643 | struct sk_buff *skb; | |
644 | unsigned int i; | |
89d71a66 | 645 | unsigned int bufsz = adapter->rx_buffer_len; |
bc7f75fa AK |
646 | |
647 | i = rx_ring->next_to_use; | |
648 | buffer_info = &rx_ring->buffer_info[i]; | |
649 | ||
650 | while (cleaned_count--) { | |
651 | skb = buffer_info->skb; | |
652 | if (skb) { | |
653 | skb_trim(skb, 0); | |
654 | goto map_skb; | |
655 | } | |
656 | ||
c2fed996 | 657 | skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); |
bc7f75fa AK |
658 | if (!skb) { |
659 | /* Better luck next round */ | |
660 | adapter->alloc_rx_buff_failed++; | |
661 | break; | |
662 | } | |
663 | ||
bc7f75fa AK |
664 | buffer_info->skb = skb; |
665 | map_skb: | |
0be3f55f | 666 | buffer_info->dma = dma_map_single(&pdev->dev, skb->data, |
bc7f75fa | 667 | adapter->rx_buffer_len, |
0be3f55f NN |
668 | DMA_FROM_DEVICE); |
669 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { | |
af667a29 | 670 | dev_err(&pdev->dev, "Rx DMA map failed\n"); |
bc7f75fa AK |
671 | adapter->rx_dma_failed++; |
672 | break; | |
673 | } | |
674 | ||
5f450212 BA |
675 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
676 | rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
bc7f75fa | 677 | |
50849d79 | 678 | if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { |
e921eb1a | 679 | /* Force memory writes to complete before letting h/w |
50849d79 TH |
680 | * know there are new descriptors to fetch. (Only |
681 | * applicable for weak-ordered memory model archs, | |
682 | * such as IA-64). | |
683 | */ | |
684 | wmb(); | |
c6e7f51e | 685 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
55aa6985 | 686 | e1000e_update_rdt_wa(rx_ring, i); |
c6e7f51e | 687 | else |
c5083cf6 | 688 | writel(i, rx_ring->tail); |
50849d79 | 689 | } |
bc7f75fa AK |
690 | i++; |
691 | if (i == rx_ring->count) | |
692 | i = 0; | |
693 | buffer_info = &rx_ring->buffer_info[i]; | |
694 | } | |
695 | ||
50849d79 | 696 | rx_ring->next_to_use = i; |
bc7f75fa AK |
697 | } |
698 | ||
699 | /** | |
700 | * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split | |
55aa6985 | 701 | * @rx_ring: Rx descriptor ring |
bc7f75fa | 702 | **/ |
55aa6985 | 703 | static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, |
c2fed996 | 704 | int cleaned_count, gfp_t gfp) |
bc7f75fa | 705 | { |
55aa6985 | 706 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
707 | struct net_device *netdev = adapter->netdev; |
708 | struct pci_dev *pdev = adapter->pdev; | |
709 | union e1000_rx_desc_packet_split *rx_desc; | |
bc7f75fa AK |
710 | struct e1000_buffer *buffer_info; |
711 | struct e1000_ps_page *ps_page; | |
712 | struct sk_buff *skb; | |
713 | unsigned int i, j; | |
714 | ||
715 | i = rx_ring->next_to_use; | |
716 | buffer_info = &rx_ring->buffer_info[i]; | |
717 | ||
718 | while (cleaned_count--) { | |
719 | rx_desc = E1000_RX_DESC_PS(*rx_ring, i); | |
720 | ||
721 | for (j = 0; j < PS_PAGE_BUFFERS; j++) { | |
47f44e40 AK |
722 | ps_page = &buffer_info->ps_pages[j]; |
723 | if (j >= adapter->rx_ps_pages) { | |
724 | /* all unused desc entries get hw null ptr */ | |
af667a29 BA |
725 | rx_desc->read.buffer_addr[j + 1] = |
726 | ~cpu_to_le64(0); | |
47f44e40 AK |
727 | continue; |
728 | } | |
729 | if (!ps_page->page) { | |
c2fed996 | 730 | ps_page->page = alloc_page(gfp); |
bc7f75fa | 731 | if (!ps_page->page) { |
47f44e40 AK |
732 | adapter->alloc_rx_buff_failed++; |
733 | goto no_buffers; | |
734 | } | |
0be3f55f NN |
735 | ps_page->dma = dma_map_page(&pdev->dev, |
736 | ps_page->page, | |
737 | 0, PAGE_SIZE, | |
738 | DMA_FROM_DEVICE); | |
739 | if (dma_mapping_error(&pdev->dev, | |
740 | ps_page->dma)) { | |
47f44e40 | 741 | dev_err(&adapter->pdev->dev, |
af667a29 | 742 | "Rx DMA page map failed\n"); |
47f44e40 AK |
743 | adapter->rx_dma_failed++; |
744 | goto no_buffers; | |
bc7f75fa | 745 | } |
bc7f75fa | 746 | } |
e921eb1a | 747 | /* Refresh the desc even if buffer_addrs |
47f44e40 AK |
748 | * didn't change because each write-back |
749 | * erases this info. | |
750 | */ | |
af667a29 BA |
751 | rx_desc->read.buffer_addr[j + 1] = |
752 | cpu_to_le64(ps_page->dma); | |
bc7f75fa AK |
753 | } |
754 | ||
e5fe2541 | 755 | skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, |
c2fed996 | 756 | gfp); |
bc7f75fa AK |
757 | |
758 | if (!skb) { | |
759 | adapter->alloc_rx_buff_failed++; | |
760 | break; | |
761 | } | |
762 | ||
bc7f75fa | 763 | buffer_info->skb = skb; |
0be3f55f | 764 | buffer_info->dma = dma_map_single(&pdev->dev, skb->data, |
bc7f75fa | 765 | adapter->rx_ps_bsize0, |
0be3f55f NN |
766 | DMA_FROM_DEVICE); |
767 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { | |
af667a29 | 768 | dev_err(&pdev->dev, "Rx DMA map failed\n"); |
bc7f75fa AK |
769 | adapter->rx_dma_failed++; |
770 | /* cleanup skb */ | |
771 | dev_kfree_skb_any(skb); | |
772 | buffer_info->skb = NULL; | |
773 | break; | |
774 | } | |
775 | ||
776 | rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); | |
777 | ||
50849d79 | 778 | if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { |
e921eb1a | 779 | /* Force memory writes to complete before letting h/w |
50849d79 TH |
780 | * know there are new descriptors to fetch. (Only |
781 | * applicable for weak-ordered memory model archs, | |
782 | * such as IA-64). | |
783 | */ | |
784 | wmb(); | |
c6e7f51e | 785 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
55aa6985 | 786 | e1000e_update_rdt_wa(rx_ring, i << 1); |
c6e7f51e | 787 | else |
c5083cf6 | 788 | writel(i << 1, rx_ring->tail); |
50849d79 TH |
789 | } |
790 | ||
bc7f75fa AK |
791 | i++; |
792 | if (i == rx_ring->count) | |
793 | i = 0; | |
794 | buffer_info = &rx_ring->buffer_info[i]; | |
795 | } | |
796 | ||
797 | no_buffers: | |
50849d79 | 798 | rx_ring->next_to_use = i; |
bc7f75fa AK |
799 | } |
800 | ||
97ac8cae BA |
801 | /** |
802 | * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers | |
55aa6985 | 803 | * @rx_ring: Rx descriptor ring |
97ac8cae BA |
804 | * @cleaned_count: number of buffers to allocate this pass |
805 | **/ | |
806 | ||
55aa6985 | 807 | static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, |
c2fed996 | 808 | int cleaned_count, gfp_t gfp) |
97ac8cae | 809 | { |
55aa6985 | 810 | struct e1000_adapter *adapter = rx_ring->adapter; |
97ac8cae BA |
811 | struct net_device *netdev = adapter->netdev; |
812 | struct pci_dev *pdev = adapter->pdev; | |
5f450212 | 813 | union e1000_rx_desc_extended *rx_desc; |
97ac8cae BA |
814 | struct e1000_buffer *buffer_info; |
815 | struct sk_buff *skb; | |
816 | unsigned int i; | |
2a2293b9 | 817 | unsigned int bufsz = 256 - 16; /* for skb_reserve */ |
97ac8cae BA |
818 | |
819 | i = rx_ring->next_to_use; | |
820 | buffer_info = &rx_ring->buffer_info[i]; | |
821 | ||
822 | while (cleaned_count--) { | |
823 | skb = buffer_info->skb; | |
824 | if (skb) { | |
825 | skb_trim(skb, 0); | |
826 | goto check_page; | |
827 | } | |
828 | ||
c2fed996 | 829 | skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); |
97ac8cae BA |
830 | if (unlikely(!skb)) { |
831 | /* Better luck next round */ | |
832 | adapter->alloc_rx_buff_failed++; | |
833 | break; | |
834 | } | |
835 | ||
97ac8cae BA |
836 | buffer_info->skb = skb; |
837 | check_page: | |
838 | /* allocate a new page if necessary */ | |
839 | if (!buffer_info->page) { | |
c2fed996 | 840 | buffer_info->page = alloc_page(gfp); |
97ac8cae BA |
841 | if (unlikely(!buffer_info->page)) { |
842 | adapter->alloc_rx_buff_failed++; | |
843 | break; | |
844 | } | |
845 | } | |
846 | ||
37287fae | 847 | if (!buffer_info->dma) { |
0be3f55f | 848 | buffer_info->dma = dma_map_page(&pdev->dev, |
f0ff4398 BA |
849 | buffer_info->page, 0, |
850 | PAGE_SIZE, | |
0be3f55f | 851 | DMA_FROM_DEVICE); |
37287fae CP |
852 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { |
853 | adapter->alloc_rx_buff_failed++; | |
854 | break; | |
855 | } | |
856 | } | |
97ac8cae | 857 | |
5f450212 BA |
858 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
859 | rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
97ac8cae BA |
860 | |
861 | if (unlikely(++i == rx_ring->count)) | |
862 | i = 0; | |
863 | buffer_info = &rx_ring->buffer_info[i]; | |
864 | } | |
865 | ||
866 | if (likely(rx_ring->next_to_use != i)) { | |
867 | rx_ring->next_to_use = i; | |
868 | if (unlikely(i-- == 0)) | |
869 | i = (rx_ring->count - 1); | |
870 | ||
871 | /* Force memory writes to complete before letting h/w | |
872 | * know there are new descriptors to fetch. (Only | |
873 | * applicable for weak-ordered memory model archs, | |
e921eb1a BA |
874 | * such as IA-64). |
875 | */ | |
97ac8cae | 876 | wmb(); |
c6e7f51e | 877 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
55aa6985 | 878 | e1000e_update_rdt_wa(rx_ring, i); |
c6e7f51e | 879 | else |
c5083cf6 | 880 | writel(i, rx_ring->tail); |
97ac8cae BA |
881 | } |
882 | } | |
883 | ||
70495a50 BA |
884 | static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, |
885 | struct sk_buff *skb) | |
886 | { | |
887 | if (netdev->features & NETIF_F_RXHASH) | |
888 | skb->rxhash = le32_to_cpu(rss); | |
889 | } | |
890 | ||
bc7f75fa | 891 | /** |
55aa6985 BA |
892 | * e1000_clean_rx_irq - Send received data up the network stack |
893 | * @rx_ring: Rx descriptor ring | |
bc7f75fa AK |
894 | * |
895 | * the return value indicates whether actual cleaning was done, there | |
896 | * is no guarantee that everything was cleaned | |
897 | **/ | |
55aa6985 BA |
898 | static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, |
899 | int work_to_do) | |
bc7f75fa | 900 | { |
55aa6985 | 901 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
902 | struct net_device *netdev = adapter->netdev; |
903 | struct pci_dev *pdev = adapter->pdev; | |
3bb99fe2 | 904 | struct e1000_hw *hw = &adapter->hw; |
5f450212 | 905 | union e1000_rx_desc_extended *rx_desc, *next_rxd; |
bc7f75fa | 906 | struct e1000_buffer *buffer_info, *next_buffer; |
5f450212 | 907 | u32 length, staterr; |
bc7f75fa AK |
908 | unsigned int i; |
909 | int cleaned_count = 0; | |
3db1cd5c | 910 | bool cleaned = false; |
bc7f75fa AK |
911 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
912 | ||
913 | i = rx_ring->next_to_clean; | |
5f450212 BA |
914 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
915 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
bc7f75fa AK |
916 | buffer_info = &rx_ring->buffer_info[i]; |
917 | ||
5f450212 | 918 | while (staterr & E1000_RXD_STAT_DD) { |
bc7f75fa | 919 | struct sk_buff *skb; |
bc7f75fa AK |
920 | |
921 | if (*work_done >= work_to_do) | |
922 | break; | |
923 | (*work_done)++; | |
2d0bb1c1 | 924 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
bc7f75fa | 925 | |
bc7f75fa AK |
926 | skb = buffer_info->skb; |
927 | buffer_info->skb = NULL; | |
928 | ||
929 | prefetch(skb->data - NET_IP_ALIGN); | |
930 | ||
931 | i++; | |
932 | if (i == rx_ring->count) | |
933 | i = 0; | |
5f450212 | 934 | next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); |
bc7f75fa AK |
935 | prefetch(next_rxd); |
936 | ||
937 | next_buffer = &rx_ring->buffer_info[i]; | |
938 | ||
3db1cd5c | 939 | cleaned = true; |
bc7f75fa | 940 | cleaned_count++; |
e5fe2541 BA |
941 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
942 | adapter->rx_buffer_len, DMA_FROM_DEVICE); | |
bc7f75fa AK |
943 | buffer_info->dma = 0; |
944 | ||
5f450212 | 945 | length = le16_to_cpu(rx_desc->wb.upper.length); |
bc7f75fa | 946 | |
e921eb1a | 947 | /* !EOP means multiple descriptors were used to store a single |
b94b5028 JB |
948 | * packet, if that's the case we need to toss it. In fact, we |
949 | * need to toss every packet with the EOP bit clear and the | |
950 | * next frame that _does_ have the EOP bit set, as it is by | |
951 | * definition only a frame fragment | |
952 | */ | |
5f450212 | 953 | if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) |
b94b5028 JB |
954 | adapter->flags2 |= FLAG2_IS_DISCARDING; |
955 | ||
956 | if (adapter->flags2 & FLAG2_IS_DISCARDING) { | |
bc7f75fa | 957 | /* All receives must fit into a single buffer */ |
3bb99fe2 | 958 | e_dbg("Receive packet consumed multiple buffers\n"); |
bc7f75fa AK |
959 | /* recycle */ |
960 | buffer_info->skb = skb; | |
5f450212 | 961 | if (staterr & E1000_RXD_STAT_EOP) |
b94b5028 | 962 | adapter->flags2 &= ~FLAG2_IS_DISCARDING; |
bc7f75fa AK |
963 | goto next_desc; |
964 | } | |
965 | ||
cf955e6c BG |
966 | if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && |
967 | !(netdev->features & NETIF_F_RXALL))) { | |
bc7f75fa AK |
968 | /* recycle */ |
969 | buffer_info->skb = skb; | |
970 | goto next_desc; | |
971 | } | |
972 | ||
eb7c3adb | 973 | /* adjust length to remove Ethernet CRC */ |
0184039a BG |
974 | if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { |
975 | /* If configured to store CRC, don't subtract FCS, | |
976 | * but keep the FCS bytes out of the total_rx_bytes | |
977 | * counter | |
978 | */ | |
979 | if (netdev->features & NETIF_F_RXFCS) | |
980 | total_rx_bytes -= 4; | |
981 | else | |
982 | length -= 4; | |
983 | } | |
eb7c3adb | 984 | |
bc7f75fa AK |
985 | total_rx_bytes += length; |
986 | total_rx_packets++; | |
987 | ||
e921eb1a | 988 | /* code added for copybreak, this should improve |
bc7f75fa | 989 | * performance for small packets with large amounts |
ad68076e BA |
990 | * of reassembly being done in the stack |
991 | */ | |
bc7f75fa AK |
992 | if (length < copybreak) { |
993 | struct sk_buff *new_skb = | |
89d71a66 | 994 | netdev_alloc_skb_ip_align(netdev, length); |
bc7f75fa | 995 | if (new_skb) { |
808ff676 BA |
996 | skb_copy_to_linear_data_offset(new_skb, |
997 | -NET_IP_ALIGN, | |
998 | (skb->data - | |
999 | NET_IP_ALIGN), | |
1000 | (length + | |
1001 | NET_IP_ALIGN)); | |
bc7f75fa AK |
1002 | /* save the skb in buffer_info as good */ |
1003 | buffer_info->skb = skb; | |
1004 | skb = new_skb; | |
1005 | } | |
1006 | /* else just continue with the old one */ | |
1007 | } | |
1008 | /* end copybreak code */ | |
1009 | skb_put(skb, length); | |
1010 | ||
1011 | /* Receive Checksum Offload */ | |
2e1706f2 | 1012 | e1000_rx_checksum(adapter, staterr, skb); |
bc7f75fa | 1013 | |
70495a50 BA |
1014 | e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); |
1015 | ||
5f450212 BA |
1016 | e1000_receive_skb(adapter, netdev, skb, staterr, |
1017 | rx_desc->wb.upper.vlan); | |
bc7f75fa AK |
1018 | |
1019 | next_desc: | |
5f450212 | 1020 | rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); |
bc7f75fa AK |
1021 | |
1022 | /* return some buffers to hardware, one at a time is too slow */ | |
1023 | if (cleaned_count >= E1000_RX_BUFFER_WRITE) { | |
55aa6985 | 1024 | adapter->alloc_rx_buf(rx_ring, cleaned_count, |
c2fed996 | 1025 | GFP_ATOMIC); |
bc7f75fa AK |
1026 | cleaned_count = 0; |
1027 | } | |
1028 | ||
1029 | /* use prefetched values */ | |
1030 | rx_desc = next_rxd; | |
1031 | buffer_info = next_buffer; | |
5f450212 BA |
1032 | |
1033 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
bc7f75fa AK |
1034 | } |
1035 | rx_ring->next_to_clean = i; | |
1036 | ||
1037 | cleaned_count = e1000_desc_unused(rx_ring); | |
1038 | if (cleaned_count) | |
55aa6985 | 1039 | adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); |
bc7f75fa | 1040 | |
bc7f75fa | 1041 | adapter->total_rx_bytes += total_rx_bytes; |
7c25769f | 1042 | adapter->total_rx_packets += total_rx_packets; |
bc7f75fa AK |
1043 | return cleaned; |
1044 | } | |
1045 | ||
55aa6985 BA |
1046 | static void e1000_put_txbuf(struct e1000_ring *tx_ring, |
1047 | struct e1000_buffer *buffer_info) | |
bc7f75fa | 1048 | { |
55aa6985 BA |
1049 | struct e1000_adapter *adapter = tx_ring->adapter; |
1050 | ||
03b1320d AD |
1051 | if (buffer_info->dma) { |
1052 | if (buffer_info->mapped_as_page) | |
0be3f55f NN |
1053 | dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, |
1054 | buffer_info->length, DMA_TO_DEVICE); | |
03b1320d | 1055 | else |
0be3f55f NN |
1056 | dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, |
1057 | buffer_info->length, DMA_TO_DEVICE); | |
03b1320d AD |
1058 | buffer_info->dma = 0; |
1059 | } | |
bc7f75fa AK |
1060 | if (buffer_info->skb) { |
1061 | dev_kfree_skb_any(buffer_info->skb); | |
1062 | buffer_info->skb = NULL; | |
1063 | } | |
1b7719c4 | 1064 | buffer_info->time_stamp = 0; |
bc7f75fa AK |
1065 | } |
1066 | ||
41cec6f1 | 1067 | static void e1000_print_hw_hang(struct work_struct *work) |
bc7f75fa | 1068 | { |
41cec6f1 | 1069 | struct e1000_adapter *adapter = container_of(work, |
f0ff4398 BA |
1070 | struct e1000_adapter, |
1071 | print_hang_task); | |
09357b00 | 1072 | struct net_device *netdev = adapter->netdev; |
bc7f75fa AK |
1073 | struct e1000_ring *tx_ring = adapter->tx_ring; |
1074 | unsigned int i = tx_ring->next_to_clean; | |
1075 | unsigned int eop = tx_ring->buffer_info[i].next_to_watch; | |
1076 | struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); | |
41cec6f1 BA |
1077 | struct e1000_hw *hw = &adapter->hw; |
1078 | u16 phy_status, phy_1000t_status, phy_ext_status; | |
1079 | u16 pci_status; | |
1080 | ||
615b32af JB |
1081 | if (test_bit(__E1000_DOWN, &adapter->state)) |
1082 | return; | |
1083 | ||
e5fe2541 | 1084 | if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { |
e921eb1a | 1085 | /* May be block on write-back, flush and detect again |
09357b00 JK |
1086 | * flush pending descriptor writebacks to memory |
1087 | */ | |
1088 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
1089 | /* execute the writes immediately */ | |
1090 | e1e_flush(); | |
e921eb1a | 1091 | /* Due to rare timing issues, write to TIDV again to ensure |
bf03085f MV |
1092 | * the write is successful |
1093 | */ | |
1094 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
1095 | /* execute the writes immediately */ | |
1096 | e1e_flush(); | |
09357b00 JK |
1097 | adapter->tx_hang_recheck = true; |
1098 | return; | |
1099 | } | |
1100 | /* Real hang detected */ | |
1101 | adapter->tx_hang_recheck = false; | |
1102 | netif_stop_queue(netdev); | |
1103 | ||
c2ade1a4 BA |
1104 | e1e_rphy(hw, MII_BMSR, &phy_status); |
1105 | e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); | |
1106 | e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); | |
bc7f75fa | 1107 | |
41cec6f1 BA |
1108 | pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); |
1109 | ||
1110 | /* detected Hardware unit hang */ | |
1111 | e_err("Detected Hardware Unit Hang:\n" | |
44defeb3 JK |
1112 | " TDH <%x>\n" |
1113 | " TDT <%x>\n" | |
1114 | " next_to_use <%x>\n" | |
1115 | " next_to_clean <%x>\n" | |
1116 | "buffer_info[next_to_clean]:\n" | |
1117 | " time_stamp <%lx>\n" | |
1118 | " next_to_watch <%x>\n" | |
1119 | " jiffies <%lx>\n" | |
41cec6f1 BA |
1120 | " next_to_watch.status <%x>\n" |
1121 | "MAC Status <%x>\n" | |
1122 | "PHY Status <%x>\n" | |
1123 | "PHY 1000BASE-T Status <%x>\n" | |
1124 | "PHY Extended Status <%x>\n" | |
1125 | "PCI Status <%x>\n", | |
e5fe2541 BA |
1126 | readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, |
1127 | tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, | |
1128 | eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), | |
1129 | phy_status, phy_1000t_status, phy_ext_status, pci_status); | |
7c0427ee BA |
1130 | |
1131 | /* Suggest workaround for known h/w issue */ | |
1132 | if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) | |
1133 | e_err("Try turning off Tx pause (flow control) via ethtool\n"); | |
bc7f75fa AK |
1134 | } |
1135 | ||
b67e1913 BA |
1136 | /** |
1137 | * e1000e_tx_hwtstamp_work - check for Tx time stamp | |
1138 | * @work: pointer to work struct | |
1139 | * | |
1140 | * This work function polls the TSYNCTXCTL valid bit to determine when a | |
1141 | * timestamp has been taken for the current stored skb. The timestamp must | |
1142 | * be for this skb because only one such packet is allowed in the queue. | |
1143 | */ | |
1144 | static void e1000e_tx_hwtstamp_work(struct work_struct *work) | |
1145 | { | |
1146 | struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, | |
1147 | tx_hwtstamp_work); | |
1148 | struct e1000_hw *hw = &adapter->hw; | |
1149 | ||
1150 | if (!adapter->tx_hwtstamp_skb) | |
1151 | return; | |
1152 | ||
1153 | if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { | |
1154 | struct skb_shared_hwtstamps shhwtstamps; | |
1155 | u64 txstmp; | |
1156 | ||
1157 | txstmp = er32(TXSTMPL); | |
1158 | txstmp |= (u64)er32(TXSTMPH) << 32; | |
1159 | ||
1160 | e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); | |
1161 | ||
1162 | skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps); | |
1163 | dev_kfree_skb_any(adapter->tx_hwtstamp_skb); | |
1164 | adapter->tx_hwtstamp_skb = NULL; | |
1165 | } else { | |
1166 | /* reschedule to check later */ | |
1167 | schedule_work(&adapter->tx_hwtstamp_work); | |
1168 | } | |
1169 | } | |
1170 | ||
bc7f75fa AK |
1171 | /** |
1172 | * e1000_clean_tx_irq - Reclaim resources after transmit completes | |
55aa6985 | 1173 | * @tx_ring: Tx descriptor ring |
bc7f75fa AK |
1174 | * |
1175 | * the return value indicates whether actual cleaning was done, there | |
1176 | * is no guarantee that everything was cleaned | |
1177 | **/ | |
55aa6985 | 1178 | static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) |
bc7f75fa | 1179 | { |
55aa6985 | 1180 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
1181 | struct net_device *netdev = adapter->netdev; |
1182 | struct e1000_hw *hw = &adapter->hw; | |
bc7f75fa AK |
1183 | struct e1000_tx_desc *tx_desc, *eop_desc; |
1184 | struct e1000_buffer *buffer_info; | |
1185 | unsigned int i, eop; | |
1186 | unsigned int count = 0; | |
bc7f75fa | 1187 | unsigned int total_tx_bytes = 0, total_tx_packets = 0; |
3f0cfa3b | 1188 | unsigned int bytes_compl = 0, pkts_compl = 0; |
bc7f75fa AK |
1189 | |
1190 | i = tx_ring->next_to_clean; | |
1191 | eop = tx_ring->buffer_info[i].next_to_watch; | |
1192 | eop_desc = E1000_TX_DESC(*tx_ring, eop); | |
1193 | ||
12d04a3c AD |
1194 | while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && |
1195 | (count < tx_ring->count)) { | |
a86043c2 | 1196 | bool cleaned = false; |
e80bd1d1 | 1197 | rmb(); /* read buffer_info after eop_desc */ |
a86043c2 | 1198 | for (; !cleaned; count++) { |
bc7f75fa AK |
1199 | tx_desc = E1000_TX_DESC(*tx_ring, i); |
1200 | buffer_info = &tx_ring->buffer_info[i]; | |
1201 | cleaned = (i == eop); | |
1202 | ||
1203 | if (cleaned) { | |
9ed318d5 TH |
1204 | total_tx_packets += buffer_info->segs; |
1205 | total_tx_bytes += buffer_info->bytecount; | |
3f0cfa3b TH |
1206 | if (buffer_info->skb) { |
1207 | bytes_compl += buffer_info->skb->len; | |
1208 | pkts_compl++; | |
1209 | } | |
bc7f75fa AK |
1210 | } |
1211 | ||
55aa6985 | 1212 | e1000_put_txbuf(tx_ring, buffer_info); |
bc7f75fa AK |
1213 | tx_desc->upper.data = 0; |
1214 | ||
1215 | i++; | |
1216 | if (i == tx_ring->count) | |
1217 | i = 0; | |
1218 | } | |
1219 | ||
dac87619 TL |
1220 | if (i == tx_ring->next_to_use) |
1221 | break; | |
bc7f75fa AK |
1222 | eop = tx_ring->buffer_info[i].next_to_watch; |
1223 | eop_desc = E1000_TX_DESC(*tx_ring, eop); | |
bc7f75fa AK |
1224 | } |
1225 | ||
1226 | tx_ring->next_to_clean = i; | |
1227 | ||
3f0cfa3b TH |
1228 | netdev_completed_queue(netdev, pkts_compl, bytes_compl); |
1229 | ||
bc7f75fa | 1230 | #define TX_WAKE_THRESHOLD 32 |
a86043c2 JB |
1231 | if (count && netif_carrier_ok(netdev) && |
1232 | e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { | |
bc7f75fa AK |
1233 | /* Make sure that anybody stopping the queue after this |
1234 | * sees the new next_to_clean. | |
1235 | */ | |
1236 | smp_mb(); | |
1237 | ||
1238 | if (netif_queue_stopped(netdev) && | |
1239 | !(test_bit(__E1000_DOWN, &adapter->state))) { | |
1240 | netif_wake_queue(netdev); | |
1241 | ++adapter->restart_queue; | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | if (adapter->detect_tx_hung) { | |
e921eb1a | 1246 | /* Detect a transmit hang in hardware, this serializes the |
41cec6f1 BA |
1247 | * check with the clearing of time_stamp and movement of i |
1248 | */ | |
3db1cd5c | 1249 | adapter->detect_tx_hung = false; |
12d04a3c AD |
1250 | if (tx_ring->buffer_info[i].time_stamp && |
1251 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp | |
8e95a202 | 1252 | + (adapter->tx_timeout_factor * HZ)) && |
09357b00 | 1253 | !(er32(STATUS) & E1000_STATUS_TXOFF)) |
41cec6f1 | 1254 | schedule_work(&adapter->print_hang_task); |
09357b00 JK |
1255 | else |
1256 | adapter->tx_hang_recheck = false; | |
bc7f75fa AK |
1257 | } |
1258 | adapter->total_tx_bytes += total_tx_bytes; | |
1259 | adapter->total_tx_packets += total_tx_packets; | |
807540ba | 1260 | return count < tx_ring->count; |
bc7f75fa AK |
1261 | } |
1262 | ||
bc7f75fa AK |
1263 | /** |
1264 | * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split | |
55aa6985 | 1265 | * @rx_ring: Rx descriptor ring |
bc7f75fa AK |
1266 | * |
1267 | * the return value indicates whether actual cleaning was done, there | |
1268 | * is no guarantee that everything was cleaned | |
1269 | **/ | |
55aa6985 BA |
1270 | static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, |
1271 | int work_to_do) | |
bc7f75fa | 1272 | { |
55aa6985 | 1273 | struct e1000_adapter *adapter = rx_ring->adapter; |
3bb99fe2 | 1274 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa AK |
1275 | union e1000_rx_desc_packet_split *rx_desc, *next_rxd; |
1276 | struct net_device *netdev = adapter->netdev; | |
1277 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
1278 | struct e1000_buffer *buffer_info, *next_buffer; |
1279 | struct e1000_ps_page *ps_page; | |
1280 | struct sk_buff *skb; | |
1281 | unsigned int i, j; | |
1282 | u32 length, staterr; | |
1283 | int cleaned_count = 0; | |
3db1cd5c | 1284 | bool cleaned = false; |
bc7f75fa AK |
1285 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
1286 | ||
1287 | i = rx_ring->next_to_clean; | |
1288 | rx_desc = E1000_RX_DESC_PS(*rx_ring, i); | |
1289 | staterr = le32_to_cpu(rx_desc->wb.middle.status_error); | |
1290 | buffer_info = &rx_ring->buffer_info[i]; | |
1291 | ||
1292 | while (staterr & E1000_RXD_STAT_DD) { | |
1293 | if (*work_done >= work_to_do) | |
1294 | break; | |
1295 | (*work_done)++; | |
1296 | skb = buffer_info->skb; | |
2d0bb1c1 | 1297 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
bc7f75fa AK |
1298 | |
1299 | /* in the packet split case this is header only */ | |
1300 | prefetch(skb->data - NET_IP_ALIGN); | |
1301 | ||
1302 | i++; | |
1303 | if (i == rx_ring->count) | |
1304 | i = 0; | |
1305 | next_rxd = E1000_RX_DESC_PS(*rx_ring, i); | |
1306 | prefetch(next_rxd); | |
1307 | ||
1308 | next_buffer = &rx_ring->buffer_info[i]; | |
1309 | ||
3db1cd5c | 1310 | cleaned = true; |
bc7f75fa | 1311 | cleaned_count++; |
0be3f55f | 1312 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
af667a29 | 1313 | adapter->rx_ps_bsize0, DMA_FROM_DEVICE); |
bc7f75fa AK |
1314 | buffer_info->dma = 0; |
1315 | ||
af667a29 | 1316 | /* see !EOP comment in other Rx routine */ |
b94b5028 JB |
1317 | if (!(staterr & E1000_RXD_STAT_EOP)) |
1318 | adapter->flags2 |= FLAG2_IS_DISCARDING; | |
1319 | ||
1320 | if (adapter->flags2 & FLAG2_IS_DISCARDING) { | |
ef456f85 | 1321 | e_dbg("Packet Split buffers didn't pick up the full packet\n"); |
bc7f75fa | 1322 | dev_kfree_skb_irq(skb); |
b94b5028 JB |
1323 | if (staterr & E1000_RXD_STAT_EOP) |
1324 | adapter->flags2 &= ~FLAG2_IS_DISCARDING; | |
bc7f75fa AK |
1325 | goto next_desc; |
1326 | } | |
1327 | ||
cf955e6c BG |
1328 | if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && |
1329 | !(netdev->features & NETIF_F_RXALL))) { | |
bc7f75fa AK |
1330 | dev_kfree_skb_irq(skb); |
1331 | goto next_desc; | |
1332 | } | |
1333 | ||
1334 | length = le16_to_cpu(rx_desc->wb.middle.length0); | |
1335 | ||
1336 | if (!length) { | |
ef456f85 | 1337 | e_dbg("Last part of the packet spanning multiple descriptors\n"); |
bc7f75fa AK |
1338 | dev_kfree_skb_irq(skb); |
1339 | goto next_desc; | |
1340 | } | |
1341 | ||
1342 | /* Good Receive */ | |
1343 | skb_put(skb, length); | |
1344 | ||
1345 | { | |
e921eb1a | 1346 | /* this looks ugly, but it seems compiler issues make |
0e15df49 BA |
1347 | * it more efficient than reusing j |
1348 | */ | |
1349 | int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); | |
bc7f75fa | 1350 | |
e921eb1a | 1351 | /* page alloc/put takes too long and effects small |
0e15df49 BA |
1352 | * packet throughput, so unsplit small packets and |
1353 | * save the alloc/put only valid in softirq (napi) | |
1354 | * context to call kmap_* | |
ad68076e | 1355 | */ |
0e15df49 BA |
1356 | if (l1 && (l1 <= copybreak) && |
1357 | ((length + l1) <= adapter->rx_ps_bsize0)) { | |
1358 | u8 *vaddr; | |
1359 | ||
1360 | ps_page = &buffer_info->ps_pages[0]; | |
1361 | ||
e921eb1a | 1362 | /* there is no documentation about how to call |
0e15df49 BA |
1363 | * kmap_atomic, so we can't hold the mapping |
1364 | * very long | |
1365 | */ | |
1366 | dma_sync_single_for_cpu(&pdev->dev, | |
1367 | ps_page->dma, | |
1368 | PAGE_SIZE, | |
1369 | DMA_FROM_DEVICE); | |
9f393834 | 1370 | vaddr = kmap_atomic(ps_page->page); |
0e15df49 | 1371 | memcpy(skb_tail_pointer(skb), vaddr, l1); |
9f393834 | 1372 | kunmap_atomic(vaddr); |
0e15df49 BA |
1373 | dma_sync_single_for_device(&pdev->dev, |
1374 | ps_page->dma, | |
1375 | PAGE_SIZE, | |
1376 | DMA_FROM_DEVICE); | |
1377 | ||
1378 | /* remove the CRC */ | |
0184039a BG |
1379 | if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { |
1380 | if (!(netdev->features & NETIF_F_RXFCS)) | |
1381 | l1 -= 4; | |
1382 | } | |
0e15df49 BA |
1383 | |
1384 | skb_put(skb, l1); | |
1385 | goto copydone; | |
e80bd1d1 | 1386 | } /* if */ |
bc7f75fa AK |
1387 | } |
1388 | ||
1389 | for (j = 0; j < PS_PAGE_BUFFERS; j++) { | |
1390 | length = le16_to_cpu(rx_desc->wb.upper.length[j]); | |
1391 | if (!length) | |
1392 | break; | |
1393 | ||
47f44e40 | 1394 | ps_page = &buffer_info->ps_pages[j]; |
0be3f55f NN |
1395 | dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, |
1396 | DMA_FROM_DEVICE); | |
bc7f75fa AK |
1397 | ps_page->dma = 0; |
1398 | skb_fill_page_desc(skb, j, ps_page->page, 0, length); | |
1399 | ps_page->page = NULL; | |
1400 | skb->len += length; | |
1401 | skb->data_len += length; | |
98a045d7 | 1402 | skb->truesize += PAGE_SIZE; |
bc7f75fa AK |
1403 | } |
1404 | ||
eb7c3adb JK |
1405 | /* strip the ethernet crc, problem is we're using pages now so |
1406 | * this whole operation can get a little cpu intensive | |
1407 | */ | |
0184039a BG |
1408 | if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { |
1409 | if (!(netdev->features & NETIF_F_RXFCS)) | |
1410 | pskb_trim(skb, skb->len - 4); | |
1411 | } | |
eb7c3adb | 1412 | |
bc7f75fa AK |
1413 | copydone: |
1414 | total_rx_bytes += skb->len; | |
1415 | total_rx_packets++; | |
1416 | ||
2e1706f2 | 1417 | e1000_rx_checksum(adapter, staterr, skb); |
bc7f75fa | 1418 | |
70495a50 BA |
1419 | e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); |
1420 | ||
bc7f75fa | 1421 | if (rx_desc->wb.upper.header_status & |
17e813ec | 1422 | cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) |
bc7f75fa AK |
1423 | adapter->rx_hdr_split++; |
1424 | ||
b67e1913 BA |
1425 | e1000_receive_skb(adapter, netdev, skb, staterr, |
1426 | rx_desc->wb.middle.vlan); | |
bc7f75fa AK |
1427 | |
1428 | next_desc: | |
1429 | rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); | |
1430 | buffer_info->skb = NULL; | |
1431 | ||
1432 | /* return some buffers to hardware, one at a time is too slow */ | |
1433 | if (cleaned_count >= E1000_RX_BUFFER_WRITE) { | |
55aa6985 | 1434 | adapter->alloc_rx_buf(rx_ring, cleaned_count, |
c2fed996 | 1435 | GFP_ATOMIC); |
bc7f75fa AK |
1436 | cleaned_count = 0; |
1437 | } | |
1438 | ||
1439 | /* use prefetched values */ | |
1440 | rx_desc = next_rxd; | |
1441 | buffer_info = next_buffer; | |
1442 | ||
1443 | staterr = le32_to_cpu(rx_desc->wb.middle.status_error); | |
1444 | } | |
1445 | rx_ring->next_to_clean = i; | |
1446 | ||
1447 | cleaned_count = e1000_desc_unused(rx_ring); | |
1448 | if (cleaned_count) | |
55aa6985 | 1449 | adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); |
bc7f75fa | 1450 | |
bc7f75fa | 1451 | adapter->total_rx_bytes += total_rx_bytes; |
7c25769f | 1452 | adapter->total_rx_packets += total_rx_packets; |
bc7f75fa AK |
1453 | return cleaned; |
1454 | } | |
1455 | ||
97ac8cae BA |
1456 | /** |
1457 | * e1000_consume_page - helper function | |
1458 | **/ | |
1459 | static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, | |
66501f56 | 1460 | u16 length) |
97ac8cae BA |
1461 | { |
1462 | bi->page = NULL; | |
1463 | skb->len += length; | |
1464 | skb->data_len += length; | |
98a045d7 | 1465 | skb->truesize += PAGE_SIZE; |
97ac8cae BA |
1466 | } |
1467 | ||
1468 | /** | |
1469 | * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy | |
1470 | * @adapter: board private structure | |
1471 | * | |
1472 | * the return value indicates whether actual cleaning was done, there | |
1473 | * is no guarantee that everything was cleaned | |
1474 | **/ | |
55aa6985 BA |
1475 | static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, |
1476 | int work_to_do) | |
97ac8cae | 1477 | { |
55aa6985 | 1478 | struct e1000_adapter *adapter = rx_ring->adapter; |
97ac8cae BA |
1479 | struct net_device *netdev = adapter->netdev; |
1480 | struct pci_dev *pdev = adapter->pdev; | |
5f450212 | 1481 | union e1000_rx_desc_extended *rx_desc, *next_rxd; |
97ac8cae | 1482 | struct e1000_buffer *buffer_info, *next_buffer; |
5f450212 | 1483 | u32 length, staterr; |
97ac8cae BA |
1484 | unsigned int i; |
1485 | int cleaned_count = 0; | |
1486 | bool cleaned = false; | |
362e20ca | 1487 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
17e813ec | 1488 | struct skb_shared_info *shinfo; |
97ac8cae BA |
1489 | |
1490 | i = rx_ring->next_to_clean; | |
5f450212 BA |
1491 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
1492 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
97ac8cae BA |
1493 | buffer_info = &rx_ring->buffer_info[i]; |
1494 | ||
5f450212 | 1495 | while (staterr & E1000_RXD_STAT_DD) { |
97ac8cae | 1496 | struct sk_buff *skb; |
97ac8cae BA |
1497 | |
1498 | if (*work_done >= work_to_do) | |
1499 | break; | |
1500 | (*work_done)++; | |
2d0bb1c1 | 1501 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
97ac8cae | 1502 | |
97ac8cae BA |
1503 | skb = buffer_info->skb; |
1504 | buffer_info->skb = NULL; | |
1505 | ||
1506 | ++i; | |
1507 | if (i == rx_ring->count) | |
1508 | i = 0; | |
5f450212 | 1509 | next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); |
97ac8cae BA |
1510 | prefetch(next_rxd); |
1511 | ||
1512 | next_buffer = &rx_ring->buffer_info[i]; | |
1513 | ||
1514 | cleaned = true; | |
1515 | cleaned_count++; | |
0be3f55f NN |
1516 | dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, |
1517 | DMA_FROM_DEVICE); | |
97ac8cae BA |
1518 | buffer_info->dma = 0; |
1519 | ||
5f450212 | 1520 | length = le16_to_cpu(rx_desc->wb.upper.length); |
97ac8cae BA |
1521 | |
1522 | /* errors is only valid for DD + EOP descriptors */ | |
5f450212 | 1523 | if (unlikely((staterr & E1000_RXD_STAT_EOP) && |
cf955e6c BG |
1524 | ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && |
1525 | !(netdev->features & NETIF_F_RXALL)))) { | |
5f450212 BA |
1526 | /* recycle both page and skb */ |
1527 | buffer_info->skb = skb; | |
1528 | /* an error means any chain goes out the window too */ | |
1529 | if (rx_ring->rx_skb_top) | |
1530 | dev_kfree_skb_irq(rx_ring->rx_skb_top); | |
1531 | rx_ring->rx_skb_top = NULL; | |
1532 | goto next_desc; | |
97ac8cae | 1533 | } |
f0f1a172 | 1534 | #define rxtop (rx_ring->rx_skb_top) |
5f450212 | 1535 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
97ac8cae BA |
1536 | /* this descriptor is only the beginning (or middle) */ |
1537 | if (!rxtop) { | |
1538 | /* this is the beginning of a chain */ | |
1539 | rxtop = skb; | |
1540 | skb_fill_page_desc(rxtop, 0, buffer_info->page, | |
f0ff4398 | 1541 | 0, length); |
97ac8cae BA |
1542 | } else { |
1543 | /* this is the middle of a chain */ | |
17e813ec BA |
1544 | shinfo = skb_shinfo(rxtop); |
1545 | skb_fill_page_desc(rxtop, shinfo->nr_frags, | |
1546 | buffer_info->page, 0, | |
1547 | length); | |
97ac8cae BA |
1548 | /* re-use the skb, only consumed the page */ |
1549 | buffer_info->skb = skb; | |
1550 | } | |
1551 | e1000_consume_page(buffer_info, rxtop, length); | |
1552 | goto next_desc; | |
1553 | } else { | |
1554 | if (rxtop) { | |
1555 | /* end of the chain */ | |
17e813ec BA |
1556 | shinfo = skb_shinfo(rxtop); |
1557 | skb_fill_page_desc(rxtop, shinfo->nr_frags, | |
1558 | buffer_info->page, 0, | |
1559 | length); | |
97ac8cae | 1560 | /* re-use the current skb, we only consumed the |
e921eb1a BA |
1561 | * page |
1562 | */ | |
97ac8cae BA |
1563 | buffer_info->skb = skb; |
1564 | skb = rxtop; | |
1565 | rxtop = NULL; | |
1566 | e1000_consume_page(buffer_info, skb, length); | |
1567 | } else { | |
1568 | /* no chain, got EOP, this buf is the packet | |
e921eb1a BA |
1569 | * copybreak to save the put_page/alloc_page |
1570 | */ | |
97ac8cae BA |
1571 | if (length <= copybreak && |
1572 | skb_tailroom(skb) >= length) { | |
1573 | u8 *vaddr; | |
4679026d | 1574 | vaddr = kmap_atomic(buffer_info->page); |
97ac8cae BA |
1575 | memcpy(skb_tail_pointer(skb), vaddr, |
1576 | length); | |
4679026d | 1577 | kunmap_atomic(vaddr); |
97ac8cae | 1578 | /* re-use the page, so don't erase |
e921eb1a BA |
1579 | * buffer_info->page |
1580 | */ | |
97ac8cae BA |
1581 | skb_put(skb, length); |
1582 | } else { | |
1583 | skb_fill_page_desc(skb, 0, | |
f0ff4398 BA |
1584 | buffer_info->page, 0, |
1585 | length); | |
97ac8cae | 1586 | e1000_consume_page(buffer_info, skb, |
f0ff4398 | 1587 | length); |
97ac8cae BA |
1588 | } |
1589 | } | |
1590 | } | |
1591 | ||
2e1706f2 BA |
1592 | /* Receive Checksum Offload */ |
1593 | e1000_rx_checksum(adapter, staterr, skb); | |
97ac8cae | 1594 | |
70495a50 BA |
1595 | e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); |
1596 | ||
97ac8cae BA |
1597 | /* probably a little skewed due to removing CRC */ |
1598 | total_rx_bytes += skb->len; | |
1599 | total_rx_packets++; | |
1600 | ||
1601 | /* eth type trans needs skb->data to point to something */ | |
1602 | if (!pskb_may_pull(skb, ETH_HLEN)) { | |
44defeb3 | 1603 | e_err("pskb_may_pull failed.\n"); |
ef5ab89c | 1604 | dev_kfree_skb_irq(skb); |
97ac8cae BA |
1605 | goto next_desc; |
1606 | } | |
1607 | ||
5f450212 BA |
1608 | e1000_receive_skb(adapter, netdev, skb, staterr, |
1609 | rx_desc->wb.upper.vlan); | |
97ac8cae BA |
1610 | |
1611 | next_desc: | |
5f450212 | 1612 | rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); |
97ac8cae BA |
1613 | |
1614 | /* return some buffers to hardware, one at a time is too slow */ | |
1615 | if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { | |
55aa6985 | 1616 | adapter->alloc_rx_buf(rx_ring, cleaned_count, |
c2fed996 | 1617 | GFP_ATOMIC); |
97ac8cae BA |
1618 | cleaned_count = 0; |
1619 | } | |
1620 | ||
1621 | /* use prefetched values */ | |
1622 | rx_desc = next_rxd; | |
1623 | buffer_info = next_buffer; | |
5f450212 BA |
1624 | |
1625 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
97ac8cae BA |
1626 | } |
1627 | rx_ring->next_to_clean = i; | |
1628 | ||
1629 | cleaned_count = e1000_desc_unused(rx_ring); | |
1630 | if (cleaned_count) | |
55aa6985 | 1631 | adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); |
97ac8cae BA |
1632 | |
1633 | adapter->total_rx_bytes += total_rx_bytes; | |
1634 | adapter->total_rx_packets += total_rx_packets; | |
97ac8cae BA |
1635 | return cleaned; |
1636 | } | |
1637 | ||
bc7f75fa AK |
1638 | /** |
1639 | * e1000_clean_rx_ring - Free Rx Buffers per Queue | |
55aa6985 | 1640 | * @rx_ring: Rx descriptor ring |
bc7f75fa | 1641 | **/ |
55aa6985 | 1642 | static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) |
bc7f75fa | 1643 | { |
55aa6985 | 1644 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
1645 | struct e1000_buffer *buffer_info; |
1646 | struct e1000_ps_page *ps_page; | |
1647 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
1648 | unsigned int i, j; |
1649 | ||
1650 | /* Free all the Rx ring sk_buffs */ | |
1651 | for (i = 0; i < rx_ring->count; i++) { | |
1652 | buffer_info = &rx_ring->buffer_info[i]; | |
1653 | if (buffer_info->dma) { | |
1654 | if (adapter->clean_rx == e1000_clean_rx_irq) | |
0be3f55f | 1655 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
bc7f75fa | 1656 | adapter->rx_buffer_len, |
0be3f55f | 1657 | DMA_FROM_DEVICE); |
97ac8cae | 1658 | else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) |
0be3f55f | 1659 | dma_unmap_page(&pdev->dev, buffer_info->dma, |
f0ff4398 | 1660 | PAGE_SIZE, DMA_FROM_DEVICE); |
bc7f75fa | 1661 | else if (adapter->clean_rx == e1000_clean_rx_irq_ps) |
0be3f55f | 1662 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
bc7f75fa | 1663 | adapter->rx_ps_bsize0, |
0be3f55f | 1664 | DMA_FROM_DEVICE); |
bc7f75fa AK |
1665 | buffer_info->dma = 0; |
1666 | } | |
1667 | ||
97ac8cae BA |
1668 | if (buffer_info->page) { |
1669 | put_page(buffer_info->page); | |
1670 | buffer_info->page = NULL; | |
1671 | } | |
1672 | ||
bc7f75fa AK |
1673 | if (buffer_info->skb) { |
1674 | dev_kfree_skb(buffer_info->skb); | |
1675 | buffer_info->skb = NULL; | |
1676 | } | |
1677 | ||
1678 | for (j = 0; j < PS_PAGE_BUFFERS; j++) { | |
47f44e40 | 1679 | ps_page = &buffer_info->ps_pages[j]; |
bc7f75fa AK |
1680 | if (!ps_page->page) |
1681 | break; | |
0be3f55f NN |
1682 | dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, |
1683 | DMA_FROM_DEVICE); | |
bc7f75fa AK |
1684 | ps_page->dma = 0; |
1685 | put_page(ps_page->page); | |
1686 | ps_page->page = NULL; | |
1687 | } | |
1688 | } | |
1689 | ||
1690 | /* there also may be some cached data from a chained receive */ | |
1691 | if (rx_ring->rx_skb_top) { | |
1692 | dev_kfree_skb(rx_ring->rx_skb_top); | |
1693 | rx_ring->rx_skb_top = NULL; | |
1694 | } | |
1695 | ||
bc7f75fa AK |
1696 | /* Zero out the descriptor ring */ |
1697 | memset(rx_ring->desc, 0, rx_ring->size); | |
1698 | ||
1699 | rx_ring->next_to_clean = 0; | |
1700 | rx_ring->next_to_use = 0; | |
b94b5028 | 1701 | adapter->flags2 &= ~FLAG2_IS_DISCARDING; |
bc7f75fa | 1702 | |
c5083cf6 | 1703 | writel(0, rx_ring->head); |
bdc125f7 BA |
1704 | if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
1705 | e1000e_update_rdt_wa(rx_ring, 0); | |
1706 | else | |
1707 | writel(0, rx_ring->tail); | |
bc7f75fa AK |
1708 | } |
1709 | ||
a8f88ff5 JB |
1710 | static void e1000e_downshift_workaround(struct work_struct *work) |
1711 | { | |
1712 | struct e1000_adapter *adapter = container_of(work, | |
17e813ec BA |
1713 | struct e1000_adapter, |
1714 | downshift_task); | |
a8f88ff5 | 1715 | |
615b32af JB |
1716 | if (test_bit(__E1000_DOWN, &adapter->state)) |
1717 | return; | |
1718 | ||
a8f88ff5 JB |
1719 | e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); |
1720 | } | |
1721 | ||
bc7f75fa AK |
1722 | /** |
1723 | * e1000_intr_msi - Interrupt Handler | |
1724 | * @irq: interrupt number | |
1725 | * @data: pointer to a network interface device structure | |
1726 | **/ | |
8bb62869 | 1727 | static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) |
bc7f75fa AK |
1728 | { |
1729 | struct net_device *netdev = data; | |
1730 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1731 | struct e1000_hw *hw = &adapter->hw; | |
1732 | u32 icr = er32(ICR); | |
1733 | ||
e921eb1a | 1734 | /* read ICR disables interrupts using IAM */ |
573cca8c | 1735 | if (icr & E1000_ICR_LSC) { |
f92518dd | 1736 | hw->mac.get_link_status = true; |
e921eb1a | 1737 | /* ICH8 workaround-- Call gig speed drop workaround on cable |
ad68076e BA |
1738 | * disconnect (LSC) before accessing any PHY registers |
1739 | */ | |
bc7f75fa AK |
1740 | if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && |
1741 | (!(er32(STATUS) & E1000_STATUS_LU))) | |
a8f88ff5 | 1742 | schedule_work(&adapter->downshift_task); |
bc7f75fa | 1743 | |
e921eb1a | 1744 | /* 80003ES2LAN workaround-- For packet buffer work-around on |
bc7f75fa | 1745 | * link down event; disable receives here in the ISR and reset |
ad68076e BA |
1746 | * adapter in watchdog |
1747 | */ | |
bc7f75fa AK |
1748 | if (netif_carrier_ok(netdev) && |
1749 | adapter->flags & FLAG_RX_NEEDS_RESTART) { | |
1750 | /* disable receives */ | |
1751 | u32 rctl = er32(RCTL); | |
1752 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
12d43f7d | 1753 | adapter->flags |= FLAG_RESTART_NOW; |
bc7f75fa AK |
1754 | } |
1755 | /* guard against interrupt when we're going down */ | |
1756 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
1757 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
1758 | } | |
1759 | ||
94fb848b BA |
1760 | /* Reset on uncorrectable ECC error */ |
1761 | if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { | |
1762 | u32 pbeccsts = er32(PBECCSTS); | |
1763 | ||
1764 | adapter->corr_errors += | |
1765 | pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; | |
1766 | adapter->uncorr_errors += | |
1767 | (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> | |
1768 | E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; | |
1769 | ||
1770 | /* Do the reset outside of interrupt context */ | |
1771 | schedule_work(&adapter->reset_task); | |
1772 | ||
1773 | /* return immediately since reset is imminent */ | |
1774 | return IRQ_HANDLED; | |
1775 | } | |
1776 | ||
288379f0 | 1777 | if (napi_schedule_prep(&adapter->napi)) { |
bc7f75fa AK |
1778 | adapter->total_tx_bytes = 0; |
1779 | adapter->total_tx_packets = 0; | |
1780 | adapter->total_rx_bytes = 0; | |
1781 | adapter->total_rx_packets = 0; | |
288379f0 | 1782 | __napi_schedule(&adapter->napi); |
bc7f75fa AK |
1783 | } |
1784 | ||
1785 | return IRQ_HANDLED; | |
1786 | } | |
1787 | ||
1788 | /** | |
1789 | * e1000_intr - Interrupt Handler | |
1790 | * @irq: interrupt number | |
1791 | * @data: pointer to a network interface device structure | |
1792 | **/ | |
8bb62869 | 1793 | static irqreturn_t e1000_intr(int __always_unused irq, void *data) |
bc7f75fa AK |
1794 | { |
1795 | struct net_device *netdev = data; | |
1796 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1797 | struct e1000_hw *hw = &adapter->hw; | |
bc7f75fa | 1798 | u32 rctl, icr = er32(ICR); |
4662e82b | 1799 | |
a68ea775 | 1800 | if (!icr || test_bit(__E1000_DOWN, &adapter->state)) |
e80bd1d1 | 1801 | return IRQ_NONE; /* Not our interrupt */ |
bc7f75fa | 1802 | |
e921eb1a | 1803 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is |
ad68076e BA |
1804 | * not set, then the adapter didn't send an interrupt |
1805 | */ | |
bc7f75fa AK |
1806 | if (!(icr & E1000_ICR_INT_ASSERTED)) |
1807 | return IRQ_NONE; | |
1808 | ||
e921eb1a | 1809 | /* Interrupt Auto-Mask...upon reading ICR, |
ad68076e BA |
1810 | * interrupts are masked. No need for the |
1811 | * IMC write | |
1812 | */ | |
bc7f75fa | 1813 | |
573cca8c | 1814 | if (icr & E1000_ICR_LSC) { |
f92518dd | 1815 | hw->mac.get_link_status = true; |
e921eb1a | 1816 | /* ICH8 workaround-- Call gig speed drop workaround on cable |
ad68076e BA |
1817 | * disconnect (LSC) before accessing any PHY registers |
1818 | */ | |
bc7f75fa AK |
1819 | if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && |
1820 | (!(er32(STATUS) & E1000_STATUS_LU))) | |
a8f88ff5 | 1821 | schedule_work(&adapter->downshift_task); |
bc7f75fa | 1822 | |
e921eb1a | 1823 | /* 80003ES2LAN workaround-- |
bc7f75fa AK |
1824 | * For packet buffer work-around on link down event; |
1825 | * disable receives here in the ISR and | |
1826 | * reset adapter in watchdog | |
1827 | */ | |
1828 | if (netif_carrier_ok(netdev) && | |
1829 | (adapter->flags & FLAG_RX_NEEDS_RESTART)) { | |
1830 | /* disable receives */ | |
1831 | rctl = er32(RCTL); | |
1832 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
12d43f7d | 1833 | adapter->flags |= FLAG_RESTART_NOW; |
bc7f75fa AK |
1834 | } |
1835 | /* guard against interrupt when we're going down */ | |
1836 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
1837 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
1838 | } | |
1839 | ||
94fb848b BA |
1840 | /* Reset on uncorrectable ECC error */ |
1841 | if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { | |
1842 | u32 pbeccsts = er32(PBECCSTS); | |
1843 | ||
1844 | adapter->corr_errors += | |
1845 | pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; | |
1846 | adapter->uncorr_errors += | |
1847 | (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> | |
1848 | E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; | |
1849 | ||
1850 | /* Do the reset outside of interrupt context */ | |
1851 | schedule_work(&adapter->reset_task); | |
1852 | ||
1853 | /* return immediately since reset is imminent */ | |
1854 | return IRQ_HANDLED; | |
1855 | } | |
1856 | ||
288379f0 | 1857 | if (napi_schedule_prep(&adapter->napi)) { |
bc7f75fa AK |
1858 | adapter->total_tx_bytes = 0; |
1859 | adapter->total_tx_packets = 0; | |
1860 | adapter->total_rx_bytes = 0; | |
1861 | adapter->total_rx_packets = 0; | |
288379f0 | 1862 | __napi_schedule(&adapter->napi); |
bc7f75fa AK |
1863 | } |
1864 | ||
1865 | return IRQ_HANDLED; | |
1866 | } | |
1867 | ||
8bb62869 | 1868 | static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) |
4662e82b BA |
1869 | { |
1870 | struct net_device *netdev = data; | |
1871 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1872 | struct e1000_hw *hw = &adapter->hw; | |
1873 | u32 icr = er32(ICR); | |
1874 | ||
1875 | if (!(icr & E1000_ICR_INT_ASSERTED)) { | |
a3c69fef JB |
1876 | if (!test_bit(__E1000_DOWN, &adapter->state)) |
1877 | ew32(IMS, E1000_IMS_OTHER); | |
4662e82b BA |
1878 | return IRQ_NONE; |
1879 | } | |
1880 | ||
1881 | if (icr & adapter->eiac_mask) | |
1882 | ew32(ICS, (icr & adapter->eiac_mask)); | |
1883 | ||
1884 | if (icr & E1000_ICR_OTHER) { | |
1885 | if (!(icr & E1000_ICR_LSC)) | |
1886 | goto no_link_interrupt; | |
f92518dd | 1887 | hw->mac.get_link_status = true; |
4662e82b BA |
1888 | /* guard against interrupt when we're going down */ |
1889 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
1890 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
1891 | } | |
1892 | ||
1893 | no_link_interrupt: | |
a3c69fef JB |
1894 | if (!test_bit(__E1000_DOWN, &adapter->state)) |
1895 | ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER); | |
4662e82b BA |
1896 | |
1897 | return IRQ_HANDLED; | |
1898 | } | |
1899 | ||
8bb62869 | 1900 | static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) |
4662e82b BA |
1901 | { |
1902 | struct net_device *netdev = data; | |
1903 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1904 | struct e1000_hw *hw = &adapter->hw; | |
1905 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
1906 | ||
4662e82b BA |
1907 | adapter->total_tx_bytes = 0; |
1908 | adapter->total_tx_packets = 0; | |
1909 | ||
55aa6985 | 1910 | if (!e1000_clean_tx_irq(tx_ring)) |
4662e82b BA |
1911 | /* Ring was not completely cleaned, so fire another interrupt */ |
1912 | ew32(ICS, tx_ring->ims_val); | |
1913 | ||
1914 | return IRQ_HANDLED; | |
1915 | } | |
1916 | ||
8bb62869 | 1917 | static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) |
4662e82b BA |
1918 | { |
1919 | struct net_device *netdev = data; | |
1920 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
55aa6985 | 1921 | struct e1000_ring *rx_ring = adapter->rx_ring; |
4662e82b BA |
1922 | |
1923 | /* Write the ITR value calculated at the end of the | |
1924 | * previous interrupt. | |
1925 | */ | |
55aa6985 BA |
1926 | if (rx_ring->set_itr) { |
1927 | writel(1000000000 / (rx_ring->itr_val * 256), | |
1928 | rx_ring->itr_register); | |
1929 | rx_ring->set_itr = 0; | |
4662e82b BA |
1930 | } |
1931 | ||
288379f0 | 1932 | if (napi_schedule_prep(&adapter->napi)) { |
4662e82b BA |
1933 | adapter->total_rx_bytes = 0; |
1934 | adapter->total_rx_packets = 0; | |
288379f0 | 1935 | __napi_schedule(&adapter->napi); |
4662e82b BA |
1936 | } |
1937 | return IRQ_HANDLED; | |
1938 | } | |
1939 | ||
1940 | /** | |
1941 | * e1000_configure_msix - Configure MSI-X hardware | |
1942 | * | |
1943 | * e1000_configure_msix sets up the hardware to properly | |
1944 | * generate MSI-X interrupts. | |
1945 | **/ | |
1946 | static void e1000_configure_msix(struct e1000_adapter *adapter) | |
1947 | { | |
1948 | struct e1000_hw *hw = &adapter->hw; | |
1949 | struct e1000_ring *rx_ring = adapter->rx_ring; | |
1950 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
1951 | int vector = 0; | |
1952 | u32 ctrl_ext, ivar = 0; | |
1953 | ||
1954 | adapter->eiac_mask = 0; | |
1955 | ||
1956 | /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ | |
1957 | if (hw->mac.type == e1000_82574) { | |
1958 | u32 rfctl = er32(RFCTL); | |
1959 | rfctl |= E1000_RFCTL_ACK_DIS; | |
1960 | ew32(RFCTL, rfctl); | |
1961 | } | |
1962 | ||
4662e82b BA |
1963 | /* Configure Rx vector */ |
1964 | rx_ring->ims_val = E1000_IMS_RXQ0; | |
1965 | adapter->eiac_mask |= rx_ring->ims_val; | |
1966 | if (rx_ring->itr_val) | |
1967 | writel(1000000000 / (rx_ring->itr_val * 256), | |
c5083cf6 | 1968 | rx_ring->itr_register); |
4662e82b | 1969 | else |
c5083cf6 | 1970 | writel(1, rx_ring->itr_register); |
4662e82b BA |
1971 | ivar = E1000_IVAR_INT_ALLOC_VALID | vector; |
1972 | ||
1973 | /* Configure Tx vector */ | |
1974 | tx_ring->ims_val = E1000_IMS_TXQ0; | |
1975 | vector++; | |
1976 | if (tx_ring->itr_val) | |
1977 | writel(1000000000 / (tx_ring->itr_val * 256), | |
c5083cf6 | 1978 | tx_ring->itr_register); |
4662e82b | 1979 | else |
c5083cf6 | 1980 | writel(1, tx_ring->itr_register); |
4662e82b BA |
1981 | adapter->eiac_mask |= tx_ring->ims_val; |
1982 | ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); | |
1983 | ||
1984 | /* set vector for Other Causes, e.g. link changes */ | |
1985 | vector++; | |
1986 | ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); | |
1987 | if (rx_ring->itr_val) | |
1988 | writel(1000000000 / (rx_ring->itr_val * 256), | |
1989 | hw->hw_addr + E1000_EITR_82574(vector)); | |
1990 | else | |
1991 | writel(1, hw->hw_addr + E1000_EITR_82574(vector)); | |
1992 | ||
1993 | /* Cause Tx interrupts on every write back */ | |
1994 | ivar |= (1 << 31); | |
1995 | ||
1996 | ew32(IVAR, ivar); | |
1997 | ||
1998 | /* enable MSI-X PBA support */ | |
1999 | ctrl_ext = er32(CTRL_EXT); | |
2000 | ctrl_ext |= E1000_CTRL_EXT_PBA_CLR; | |
2001 | ||
2002 | /* Auto-Mask Other interrupts upon ICR read */ | |
4662e82b BA |
2003 | ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER); |
2004 | ctrl_ext |= E1000_CTRL_EXT_EIAME; | |
2005 | ew32(CTRL_EXT, ctrl_ext); | |
2006 | e1e_flush(); | |
2007 | } | |
2008 | ||
2009 | void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) | |
2010 | { | |
2011 | if (adapter->msix_entries) { | |
2012 | pci_disable_msix(adapter->pdev); | |
2013 | kfree(adapter->msix_entries); | |
2014 | adapter->msix_entries = NULL; | |
2015 | } else if (adapter->flags & FLAG_MSI_ENABLED) { | |
2016 | pci_disable_msi(adapter->pdev); | |
2017 | adapter->flags &= ~FLAG_MSI_ENABLED; | |
2018 | } | |
4662e82b BA |
2019 | } |
2020 | ||
2021 | /** | |
2022 | * e1000e_set_interrupt_capability - set MSI or MSI-X if supported | |
2023 | * | |
2024 | * Attempt to configure interrupts using the best available | |
2025 | * capabilities of the hardware and kernel. | |
2026 | **/ | |
2027 | void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) | |
2028 | { | |
2029 | int err; | |
8e86acd7 | 2030 | int i; |
4662e82b BA |
2031 | |
2032 | switch (adapter->int_mode) { | |
2033 | case E1000E_INT_MODE_MSIX: | |
2034 | if (adapter->flags & FLAG_HAS_MSIX) { | |
8e86acd7 JK |
2035 | adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ |
2036 | adapter->msix_entries = kcalloc(adapter->num_vectors, | |
17e813ec BA |
2037 | sizeof(struct |
2038 | msix_entry), | |
2039 | GFP_KERNEL); | |
4662e82b | 2040 | if (adapter->msix_entries) { |
8e86acd7 | 2041 | for (i = 0; i < adapter->num_vectors; i++) |
4662e82b BA |
2042 | adapter->msix_entries[i].entry = i; |
2043 | ||
2044 | err = pci_enable_msix(adapter->pdev, | |
2045 | adapter->msix_entries, | |
8e86acd7 | 2046 | adapter->num_vectors); |
b1cdfead | 2047 | if (err == 0) |
4662e82b BA |
2048 | return; |
2049 | } | |
2050 | /* MSI-X failed, so fall through and try MSI */ | |
ef456f85 | 2051 | e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); |
4662e82b BA |
2052 | e1000e_reset_interrupt_capability(adapter); |
2053 | } | |
2054 | adapter->int_mode = E1000E_INT_MODE_MSI; | |
2055 | /* Fall through */ | |
2056 | case E1000E_INT_MODE_MSI: | |
2057 | if (!pci_enable_msi(adapter->pdev)) { | |
2058 | adapter->flags |= FLAG_MSI_ENABLED; | |
2059 | } else { | |
2060 | adapter->int_mode = E1000E_INT_MODE_LEGACY; | |
ef456f85 | 2061 | e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); |
4662e82b BA |
2062 | } |
2063 | /* Fall through */ | |
2064 | case E1000E_INT_MODE_LEGACY: | |
2065 | /* Don't do anything; this is the system default */ | |
2066 | break; | |
2067 | } | |
8e86acd7 JK |
2068 | |
2069 | /* store the number of vectors being used */ | |
2070 | adapter->num_vectors = 1; | |
4662e82b BA |
2071 | } |
2072 | ||
2073 | /** | |
2074 | * e1000_request_msix - Initialize MSI-X interrupts | |
2075 | * | |
2076 | * e1000_request_msix allocates MSI-X vectors and requests interrupts from the | |
2077 | * kernel. | |
2078 | **/ | |
2079 | static int e1000_request_msix(struct e1000_adapter *adapter) | |
2080 | { | |
2081 | struct net_device *netdev = adapter->netdev; | |
2082 | int err = 0, vector = 0; | |
2083 | ||
2084 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
79f5e840 BA |
2085 | snprintf(adapter->rx_ring->name, |
2086 | sizeof(adapter->rx_ring->name) - 1, | |
2087 | "%s-rx-0", netdev->name); | |
4662e82b BA |
2088 | else |
2089 | memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); | |
2090 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 2091 | e1000_intr_msix_rx, 0, adapter->rx_ring->name, |
4662e82b BA |
2092 | netdev); |
2093 | if (err) | |
5015e53a | 2094 | return err; |
c5083cf6 BA |
2095 | adapter->rx_ring->itr_register = adapter->hw.hw_addr + |
2096 | E1000_EITR_82574(vector); | |
4662e82b BA |
2097 | adapter->rx_ring->itr_val = adapter->itr; |
2098 | vector++; | |
2099 | ||
2100 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
79f5e840 BA |
2101 | snprintf(adapter->tx_ring->name, |
2102 | sizeof(adapter->tx_ring->name) - 1, | |
2103 | "%s-tx-0", netdev->name); | |
4662e82b BA |
2104 | else |
2105 | memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); | |
2106 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 2107 | e1000_intr_msix_tx, 0, adapter->tx_ring->name, |
4662e82b BA |
2108 | netdev); |
2109 | if (err) | |
5015e53a | 2110 | return err; |
c5083cf6 BA |
2111 | adapter->tx_ring->itr_register = adapter->hw.hw_addr + |
2112 | E1000_EITR_82574(vector); | |
4662e82b BA |
2113 | adapter->tx_ring->itr_val = adapter->itr; |
2114 | vector++; | |
2115 | ||
2116 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 2117 | e1000_msix_other, 0, netdev->name, netdev); |
4662e82b | 2118 | if (err) |
5015e53a | 2119 | return err; |
4662e82b BA |
2120 | |
2121 | e1000_configure_msix(adapter); | |
5015e53a | 2122 | |
4662e82b | 2123 | return 0; |
4662e82b BA |
2124 | } |
2125 | ||
f8d59f78 BA |
2126 | /** |
2127 | * e1000_request_irq - initialize interrupts | |
2128 | * | |
2129 | * Attempts to configure interrupts using the best available | |
2130 | * capabilities of the hardware and kernel. | |
2131 | **/ | |
bc7f75fa AK |
2132 | static int e1000_request_irq(struct e1000_adapter *adapter) |
2133 | { | |
2134 | struct net_device *netdev = adapter->netdev; | |
bc7f75fa AK |
2135 | int err; |
2136 | ||
4662e82b BA |
2137 | if (adapter->msix_entries) { |
2138 | err = e1000_request_msix(adapter); | |
2139 | if (!err) | |
2140 | return err; | |
2141 | /* fall back to MSI */ | |
2142 | e1000e_reset_interrupt_capability(adapter); | |
2143 | adapter->int_mode = E1000E_INT_MODE_MSI; | |
2144 | e1000e_set_interrupt_capability(adapter); | |
bc7f75fa | 2145 | } |
4662e82b | 2146 | if (adapter->flags & FLAG_MSI_ENABLED) { |
a0607fd3 | 2147 | err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, |
4662e82b BA |
2148 | netdev->name, netdev); |
2149 | if (!err) | |
2150 | return err; | |
bc7f75fa | 2151 | |
4662e82b BA |
2152 | /* fall back to legacy interrupt */ |
2153 | e1000e_reset_interrupt_capability(adapter); | |
2154 | adapter->int_mode = E1000E_INT_MODE_LEGACY; | |
bc7f75fa AK |
2155 | } |
2156 | ||
a0607fd3 | 2157 | err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, |
4662e82b BA |
2158 | netdev->name, netdev); |
2159 | if (err) | |
2160 | e_err("Unable to allocate interrupt, Error: %d\n", err); | |
2161 | ||
bc7f75fa AK |
2162 | return err; |
2163 | } | |
2164 | ||
2165 | static void e1000_free_irq(struct e1000_adapter *adapter) | |
2166 | { | |
2167 | struct net_device *netdev = adapter->netdev; | |
2168 | ||
4662e82b BA |
2169 | if (adapter->msix_entries) { |
2170 | int vector = 0; | |
2171 | ||
2172 | free_irq(adapter->msix_entries[vector].vector, netdev); | |
2173 | vector++; | |
2174 | ||
2175 | free_irq(adapter->msix_entries[vector].vector, netdev); | |
2176 | vector++; | |
2177 | ||
2178 | /* Other Causes interrupt vector */ | |
2179 | free_irq(adapter->msix_entries[vector].vector, netdev); | |
2180 | return; | |
bc7f75fa | 2181 | } |
4662e82b BA |
2182 | |
2183 | free_irq(adapter->pdev->irq, netdev); | |
bc7f75fa AK |
2184 | } |
2185 | ||
2186 | /** | |
2187 | * e1000_irq_disable - Mask off interrupt generation on the NIC | |
2188 | **/ | |
2189 | static void e1000_irq_disable(struct e1000_adapter *adapter) | |
2190 | { | |
2191 | struct e1000_hw *hw = &adapter->hw; | |
2192 | ||
bc7f75fa | 2193 | ew32(IMC, ~0); |
4662e82b BA |
2194 | if (adapter->msix_entries) |
2195 | ew32(EIAC_82574, 0); | |
bc7f75fa | 2196 | e1e_flush(); |
8e86acd7 JK |
2197 | |
2198 | if (adapter->msix_entries) { | |
2199 | int i; | |
2200 | for (i = 0; i < adapter->num_vectors; i++) | |
2201 | synchronize_irq(adapter->msix_entries[i].vector); | |
2202 | } else { | |
2203 | synchronize_irq(adapter->pdev->irq); | |
2204 | } | |
bc7f75fa AK |
2205 | } |
2206 | ||
2207 | /** | |
2208 | * e1000_irq_enable - Enable default interrupt generation settings | |
2209 | **/ | |
2210 | static void e1000_irq_enable(struct e1000_adapter *adapter) | |
2211 | { | |
2212 | struct e1000_hw *hw = &adapter->hw; | |
2213 | ||
4662e82b BA |
2214 | if (adapter->msix_entries) { |
2215 | ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); | |
2216 | ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC); | |
94fb848b BA |
2217 | } else if (hw->mac.type == e1000_pch_lpt) { |
2218 | ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); | |
4662e82b BA |
2219 | } else { |
2220 | ew32(IMS, IMS_ENABLE_MASK); | |
2221 | } | |
74ef9c39 | 2222 | e1e_flush(); |
bc7f75fa AK |
2223 | } |
2224 | ||
2225 | /** | |
31dbe5b4 | 2226 | * e1000e_get_hw_control - get control of the h/w from f/w |
bc7f75fa AK |
2227 | * @adapter: address of board private structure |
2228 | * | |
31dbe5b4 | 2229 | * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. |
bc7f75fa AK |
2230 | * For ASF and Pass Through versions of f/w this means that |
2231 | * the driver is loaded. For AMT version (only with 82573) | |
2232 | * of the f/w this means that the network i/f is open. | |
2233 | **/ | |
31dbe5b4 | 2234 | void e1000e_get_hw_control(struct e1000_adapter *adapter) |
bc7f75fa AK |
2235 | { |
2236 | struct e1000_hw *hw = &adapter->hw; | |
2237 | u32 ctrl_ext; | |
2238 | u32 swsm; | |
2239 | ||
2240 | /* Let firmware know the driver has taken over */ | |
2241 | if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { | |
2242 | swsm = er32(SWSM); | |
2243 | ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); | |
2244 | } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { | |
2245 | ctrl_ext = er32(CTRL_EXT); | |
ad68076e | 2246 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); |
bc7f75fa AK |
2247 | } |
2248 | } | |
2249 | ||
2250 | /** | |
31dbe5b4 | 2251 | * e1000e_release_hw_control - release control of the h/w to f/w |
bc7f75fa AK |
2252 | * @adapter: address of board private structure |
2253 | * | |
31dbe5b4 | 2254 | * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. |
bc7f75fa AK |
2255 | * For ASF and Pass Through versions of f/w this means that the |
2256 | * driver is no longer loaded. For AMT version (only with 82573) i | |
2257 | * of the f/w this means that the network i/f is closed. | |
2258 | * | |
2259 | **/ | |
31dbe5b4 | 2260 | void e1000e_release_hw_control(struct e1000_adapter *adapter) |
bc7f75fa AK |
2261 | { |
2262 | struct e1000_hw *hw = &adapter->hw; | |
2263 | u32 ctrl_ext; | |
2264 | u32 swsm; | |
2265 | ||
2266 | /* Let firmware taken over control of h/w */ | |
2267 | if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { | |
2268 | swsm = er32(SWSM); | |
2269 | ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); | |
2270 | } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { | |
2271 | ctrl_ext = er32(CTRL_EXT); | |
ad68076e | 2272 | ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); |
bc7f75fa AK |
2273 | } |
2274 | } | |
2275 | ||
bc7f75fa | 2276 | /** |
49ce9c2c | 2277 | * e1000_alloc_ring_dma - allocate memory for a ring structure |
bc7f75fa AK |
2278 | **/ |
2279 | static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, | |
2280 | struct e1000_ring *ring) | |
2281 | { | |
2282 | struct pci_dev *pdev = adapter->pdev; | |
2283 | ||
2284 | ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, | |
2285 | GFP_KERNEL); | |
2286 | if (!ring->desc) | |
2287 | return -ENOMEM; | |
2288 | ||
2289 | return 0; | |
2290 | } | |
2291 | ||
2292 | /** | |
2293 | * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) | |
55aa6985 | 2294 | * @tx_ring: Tx descriptor ring |
bc7f75fa AK |
2295 | * |
2296 | * Return 0 on success, negative on failure | |
2297 | **/ | |
55aa6985 | 2298 | int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) |
bc7f75fa | 2299 | { |
55aa6985 | 2300 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
2301 | int err = -ENOMEM, size; |
2302 | ||
2303 | size = sizeof(struct e1000_buffer) * tx_ring->count; | |
89bf67f1 | 2304 | tx_ring->buffer_info = vzalloc(size); |
bc7f75fa AK |
2305 | if (!tx_ring->buffer_info) |
2306 | goto err; | |
bc7f75fa AK |
2307 | |
2308 | /* round up to nearest 4K */ | |
2309 | tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); | |
2310 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
2311 | ||
2312 | err = e1000_alloc_ring_dma(adapter, tx_ring); | |
2313 | if (err) | |
2314 | goto err; | |
2315 | ||
2316 | tx_ring->next_to_use = 0; | |
2317 | tx_ring->next_to_clean = 0; | |
bc7f75fa AK |
2318 | |
2319 | return 0; | |
2320 | err: | |
2321 | vfree(tx_ring->buffer_info); | |
44defeb3 | 2322 | e_err("Unable to allocate memory for the transmit descriptor ring\n"); |
bc7f75fa AK |
2323 | return err; |
2324 | } | |
2325 | ||
2326 | /** | |
2327 | * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) | |
55aa6985 | 2328 | * @rx_ring: Rx descriptor ring |
bc7f75fa AK |
2329 | * |
2330 | * Returns 0 on success, negative on failure | |
2331 | **/ | |
55aa6985 | 2332 | int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) |
bc7f75fa | 2333 | { |
55aa6985 | 2334 | struct e1000_adapter *adapter = rx_ring->adapter; |
47f44e40 AK |
2335 | struct e1000_buffer *buffer_info; |
2336 | int i, size, desc_len, err = -ENOMEM; | |
bc7f75fa AK |
2337 | |
2338 | size = sizeof(struct e1000_buffer) * rx_ring->count; | |
89bf67f1 | 2339 | rx_ring->buffer_info = vzalloc(size); |
bc7f75fa AK |
2340 | if (!rx_ring->buffer_info) |
2341 | goto err; | |
bc7f75fa | 2342 | |
47f44e40 AK |
2343 | for (i = 0; i < rx_ring->count; i++) { |
2344 | buffer_info = &rx_ring->buffer_info[i]; | |
2345 | buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, | |
2346 | sizeof(struct e1000_ps_page), | |
2347 | GFP_KERNEL); | |
2348 | if (!buffer_info->ps_pages) | |
2349 | goto err_pages; | |
2350 | } | |
bc7f75fa AK |
2351 | |
2352 | desc_len = sizeof(union e1000_rx_desc_packet_split); | |
2353 | ||
2354 | /* Round up to nearest 4K */ | |
2355 | rx_ring->size = rx_ring->count * desc_len; | |
2356 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
2357 | ||
2358 | err = e1000_alloc_ring_dma(adapter, rx_ring); | |
2359 | if (err) | |
47f44e40 | 2360 | goto err_pages; |
bc7f75fa AK |
2361 | |
2362 | rx_ring->next_to_clean = 0; | |
2363 | rx_ring->next_to_use = 0; | |
2364 | rx_ring->rx_skb_top = NULL; | |
2365 | ||
2366 | return 0; | |
47f44e40 AK |
2367 | |
2368 | err_pages: | |
2369 | for (i = 0; i < rx_ring->count; i++) { | |
2370 | buffer_info = &rx_ring->buffer_info[i]; | |
2371 | kfree(buffer_info->ps_pages); | |
2372 | } | |
bc7f75fa AK |
2373 | err: |
2374 | vfree(rx_ring->buffer_info); | |
e9262447 | 2375 | e_err("Unable to allocate memory for the receive descriptor ring\n"); |
bc7f75fa AK |
2376 | return err; |
2377 | } | |
2378 | ||
2379 | /** | |
2380 | * e1000_clean_tx_ring - Free Tx Buffers | |
55aa6985 | 2381 | * @tx_ring: Tx descriptor ring |
bc7f75fa | 2382 | **/ |
55aa6985 | 2383 | static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) |
bc7f75fa | 2384 | { |
55aa6985 | 2385 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
2386 | struct e1000_buffer *buffer_info; |
2387 | unsigned long size; | |
2388 | unsigned int i; | |
2389 | ||
2390 | for (i = 0; i < tx_ring->count; i++) { | |
2391 | buffer_info = &tx_ring->buffer_info[i]; | |
55aa6985 | 2392 | e1000_put_txbuf(tx_ring, buffer_info); |
bc7f75fa AK |
2393 | } |
2394 | ||
3f0cfa3b | 2395 | netdev_reset_queue(adapter->netdev); |
bc7f75fa AK |
2396 | size = sizeof(struct e1000_buffer) * tx_ring->count; |
2397 | memset(tx_ring->buffer_info, 0, size); | |
2398 | ||
2399 | memset(tx_ring->desc, 0, tx_ring->size); | |
2400 | ||
2401 | tx_ring->next_to_use = 0; | |
2402 | tx_ring->next_to_clean = 0; | |
2403 | ||
c5083cf6 | 2404 | writel(0, tx_ring->head); |
bdc125f7 BA |
2405 | if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
2406 | e1000e_update_tdt_wa(tx_ring, 0); | |
2407 | else | |
2408 | writel(0, tx_ring->tail); | |
bc7f75fa AK |
2409 | } |
2410 | ||
2411 | /** | |
2412 | * e1000e_free_tx_resources - Free Tx Resources per Queue | |
55aa6985 | 2413 | * @tx_ring: Tx descriptor ring |
bc7f75fa AK |
2414 | * |
2415 | * Free all transmit software resources | |
2416 | **/ | |
55aa6985 | 2417 | void e1000e_free_tx_resources(struct e1000_ring *tx_ring) |
bc7f75fa | 2418 | { |
55aa6985 | 2419 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa | 2420 | struct pci_dev *pdev = adapter->pdev; |
bc7f75fa | 2421 | |
55aa6985 | 2422 | e1000_clean_tx_ring(tx_ring); |
bc7f75fa AK |
2423 | |
2424 | vfree(tx_ring->buffer_info); | |
2425 | tx_ring->buffer_info = NULL; | |
2426 | ||
2427 | dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, | |
2428 | tx_ring->dma); | |
2429 | tx_ring->desc = NULL; | |
2430 | } | |
2431 | ||
2432 | /** | |
2433 | * e1000e_free_rx_resources - Free Rx Resources | |
55aa6985 | 2434 | * @rx_ring: Rx descriptor ring |
bc7f75fa AK |
2435 | * |
2436 | * Free all receive software resources | |
2437 | **/ | |
55aa6985 | 2438 | void e1000e_free_rx_resources(struct e1000_ring *rx_ring) |
bc7f75fa | 2439 | { |
55aa6985 | 2440 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa | 2441 | struct pci_dev *pdev = adapter->pdev; |
47f44e40 | 2442 | int i; |
bc7f75fa | 2443 | |
55aa6985 | 2444 | e1000_clean_rx_ring(rx_ring); |
bc7f75fa | 2445 | |
b1cdfead | 2446 | for (i = 0; i < rx_ring->count; i++) |
47f44e40 | 2447 | kfree(rx_ring->buffer_info[i].ps_pages); |
47f44e40 | 2448 | |
bc7f75fa AK |
2449 | vfree(rx_ring->buffer_info); |
2450 | rx_ring->buffer_info = NULL; | |
2451 | ||
bc7f75fa AK |
2452 | dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, |
2453 | rx_ring->dma); | |
2454 | rx_ring->desc = NULL; | |
2455 | } | |
2456 | ||
2457 | /** | |
2458 | * e1000_update_itr - update the dynamic ITR value based on statistics | |
489815ce AK |
2459 | * @adapter: pointer to adapter |
2460 | * @itr_setting: current adapter->itr | |
2461 | * @packets: the number of packets during this measurement interval | |
2462 | * @bytes: the number of bytes during this measurement interval | |
2463 | * | |
bc7f75fa AK |
2464 | * Stores a new ITR value based on packets and byte |
2465 | * counts during the last interrupt. The advantage of per interrupt | |
2466 | * computation is faster updates and more accurate ITR for the current | |
2467 | * traffic pattern. Constants in this function were computed | |
2468 | * based on theoretical maximum wire speed and thresholds were set based | |
2469 | * on testing data as well as attempting to minimize response time | |
4662e82b BA |
2470 | * while increasing bulk throughput. This functionality is controlled |
2471 | * by the InterruptThrottleRate module parameter. | |
bc7f75fa | 2472 | **/ |
8bb62869 | 2473 | static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) |
bc7f75fa AK |
2474 | { |
2475 | unsigned int retval = itr_setting; | |
2476 | ||
2477 | if (packets == 0) | |
5015e53a | 2478 | return itr_setting; |
bc7f75fa AK |
2479 | |
2480 | switch (itr_setting) { | |
2481 | case lowest_latency: | |
2482 | /* handle TSO and jumbo frames */ | |
362e20ca | 2483 | if (bytes / packets > 8000) |
bc7f75fa | 2484 | retval = bulk_latency; |
b1cdfead | 2485 | else if ((packets < 5) && (bytes > 512)) |
bc7f75fa | 2486 | retval = low_latency; |
bc7f75fa | 2487 | break; |
e80bd1d1 | 2488 | case low_latency: /* 50 usec aka 20000 ints/s */ |
bc7f75fa AK |
2489 | if (bytes > 10000) { |
2490 | /* this if handles the TSO accounting */ | |
362e20ca | 2491 | if (bytes / packets > 8000) |
bc7f75fa | 2492 | retval = bulk_latency; |
362e20ca | 2493 | else if ((packets < 10) || ((bytes / packets) > 1200)) |
bc7f75fa | 2494 | retval = bulk_latency; |
b1cdfead | 2495 | else if ((packets > 35)) |
bc7f75fa | 2496 | retval = lowest_latency; |
362e20ca | 2497 | } else if (bytes / packets > 2000) { |
bc7f75fa AK |
2498 | retval = bulk_latency; |
2499 | } else if (packets <= 2 && bytes < 512) { | |
2500 | retval = lowest_latency; | |
2501 | } | |
2502 | break; | |
e80bd1d1 | 2503 | case bulk_latency: /* 250 usec aka 4000 ints/s */ |
bc7f75fa | 2504 | if (bytes > 25000) { |
b1cdfead | 2505 | if (packets > 35) |
bc7f75fa | 2506 | retval = low_latency; |
bc7f75fa AK |
2507 | } else if (bytes < 6000) { |
2508 | retval = low_latency; | |
2509 | } | |
2510 | break; | |
2511 | } | |
2512 | ||
bc7f75fa AK |
2513 | return retval; |
2514 | } | |
2515 | ||
2516 | static void e1000_set_itr(struct e1000_adapter *adapter) | |
2517 | { | |
bc7f75fa AK |
2518 | u16 current_itr; |
2519 | u32 new_itr = adapter->itr; | |
2520 | ||
2521 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
2522 | if (adapter->link_speed != SPEED_1000) { | |
2523 | current_itr = 0; | |
2524 | new_itr = 4000; | |
2525 | goto set_itr_now; | |
2526 | } | |
2527 | ||
828bac87 BA |
2528 | if (adapter->flags2 & FLAG2_DISABLE_AIM) { |
2529 | new_itr = 0; | |
2530 | goto set_itr_now; | |
2531 | } | |
2532 | ||
8bb62869 BA |
2533 | adapter->tx_itr = e1000_update_itr(adapter->tx_itr, |
2534 | adapter->total_tx_packets, | |
2535 | adapter->total_tx_bytes); | |
bc7f75fa AK |
2536 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
2537 | if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) | |
2538 | adapter->tx_itr = low_latency; | |
2539 | ||
8bb62869 BA |
2540 | adapter->rx_itr = e1000_update_itr(adapter->rx_itr, |
2541 | adapter->total_rx_packets, | |
2542 | adapter->total_rx_bytes); | |
bc7f75fa AK |
2543 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
2544 | if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) | |
2545 | adapter->rx_itr = low_latency; | |
2546 | ||
2547 | current_itr = max(adapter->rx_itr, adapter->tx_itr); | |
2548 | ||
bc7f75fa | 2549 | /* counts and packets in update_itr are dependent on these numbers */ |
33550cec | 2550 | switch (current_itr) { |
bc7f75fa AK |
2551 | case lowest_latency: |
2552 | new_itr = 70000; | |
2553 | break; | |
2554 | case low_latency: | |
e80bd1d1 | 2555 | new_itr = 20000; /* aka hwitr = ~200 */ |
bc7f75fa AK |
2556 | break; |
2557 | case bulk_latency: | |
2558 | new_itr = 4000; | |
2559 | break; | |
2560 | default: | |
2561 | break; | |
2562 | } | |
2563 | ||
2564 | set_itr_now: | |
2565 | if (new_itr != adapter->itr) { | |
e921eb1a | 2566 | /* this attempts to bias the interrupt rate towards Bulk |
bc7f75fa | 2567 | * by adding intermediate steps when interrupt rate is |
ad68076e BA |
2568 | * increasing |
2569 | */ | |
bc7f75fa | 2570 | new_itr = new_itr > adapter->itr ? |
f0ff4398 | 2571 | min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; |
bc7f75fa | 2572 | adapter->itr = new_itr; |
4662e82b BA |
2573 | adapter->rx_ring->itr_val = new_itr; |
2574 | if (adapter->msix_entries) | |
2575 | adapter->rx_ring->set_itr = 1; | |
2576 | else | |
e3d14b08 | 2577 | e1000e_write_itr(adapter, new_itr); |
bc7f75fa AK |
2578 | } |
2579 | } | |
2580 | ||
22a4cca2 MV |
2581 | /** |
2582 | * e1000e_write_itr - write the ITR value to the appropriate registers | |
2583 | * @adapter: address of board private structure | |
2584 | * @itr: new ITR value to program | |
2585 | * | |
2586 | * e1000e_write_itr determines if the adapter is in MSI-X mode | |
2587 | * and, if so, writes the EITR registers with the ITR value. | |
2588 | * Otherwise, it writes the ITR value into the ITR register. | |
2589 | **/ | |
2590 | void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) | |
2591 | { | |
2592 | struct e1000_hw *hw = &adapter->hw; | |
2593 | u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; | |
2594 | ||
2595 | if (adapter->msix_entries) { | |
2596 | int vector; | |
2597 | ||
2598 | for (vector = 0; vector < adapter->num_vectors; vector++) | |
2599 | writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); | |
2600 | } else { | |
2601 | ew32(ITR, new_itr); | |
2602 | } | |
2603 | } | |
2604 | ||
4662e82b BA |
2605 | /** |
2606 | * e1000_alloc_queues - Allocate memory for all rings | |
2607 | * @adapter: board private structure to initialize | |
2608 | **/ | |
9f9a12f8 | 2609 | static int e1000_alloc_queues(struct e1000_adapter *adapter) |
4662e82b | 2610 | { |
55aa6985 BA |
2611 | int size = sizeof(struct e1000_ring); |
2612 | ||
2613 | adapter->tx_ring = kzalloc(size, GFP_KERNEL); | |
4662e82b BA |
2614 | if (!adapter->tx_ring) |
2615 | goto err; | |
55aa6985 BA |
2616 | adapter->tx_ring->count = adapter->tx_ring_count; |
2617 | adapter->tx_ring->adapter = adapter; | |
4662e82b | 2618 | |
55aa6985 | 2619 | adapter->rx_ring = kzalloc(size, GFP_KERNEL); |
4662e82b BA |
2620 | if (!adapter->rx_ring) |
2621 | goto err; | |
55aa6985 BA |
2622 | adapter->rx_ring->count = adapter->rx_ring_count; |
2623 | adapter->rx_ring->adapter = adapter; | |
4662e82b BA |
2624 | |
2625 | return 0; | |
2626 | err: | |
2627 | e_err("Unable to allocate memory for queues\n"); | |
2628 | kfree(adapter->rx_ring); | |
2629 | kfree(adapter->tx_ring); | |
2630 | return -ENOMEM; | |
2631 | } | |
2632 | ||
bc7f75fa | 2633 | /** |
c58c8a78 | 2634 | * e1000e_poll - NAPI Rx polling callback |
ad68076e | 2635 | * @napi: struct associated with this polling callback |
c58c8a78 | 2636 | * @weight: number of packets driver is allowed to process this poll |
bc7f75fa | 2637 | **/ |
c58c8a78 | 2638 | static int e1000e_poll(struct napi_struct *napi, int weight) |
bc7f75fa | 2639 | { |
c58c8a78 BA |
2640 | struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, |
2641 | napi); | |
4662e82b | 2642 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa | 2643 | struct net_device *poll_dev = adapter->netdev; |
679e8a0f | 2644 | int tx_cleaned = 1, work_done = 0; |
bc7f75fa | 2645 | |
4cf1653a | 2646 | adapter = netdev_priv(poll_dev); |
bc7f75fa | 2647 | |
c58c8a78 BA |
2648 | if (!adapter->msix_entries || |
2649 | (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) | |
2650 | tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); | |
4662e82b | 2651 | |
c58c8a78 | 2652 | adapter->clean_rx(adapter->rx_ring, &work_done, weight); |
d2c7ddd6 | 2653 | |
12d04a3c | 2654 | if (!tx_cleaned) |
c58c8a78 | 2655 | work_done = weight; |
bc7f75fa | 2656 | |
c58c8a78 BA |
2657 | /* If weight not fully consumed, exit the polling mode */ |
2658 | if (work_done < weight) { | |
bc7f75fa AK |
2659 | if (adapter->itr_setting & 3) |
2660 | e1000_set_itr(adapter); | |
288379f0 | 2661 | napi_complete(napi); |
a3c69fef JB |
2662 | if (!test_bit(__E1000_DOWN, &adapter->state)) { |
2663 | if (adapter->msix_entries) | |
2664 | ew32(IMS, adapter->rx_ring->ims_val); | |
2665 | else | |
2666 | e1000_irq_enable(adapter); | |
2667 | } | |
bc7f75fa AK |
2668 | } |
2669 | ||
2670 | return work_done; | |
2671 | } | |
2672 | ||
80d5c368 | 2673 | static int e1000_vlan_rx_add_vid(struct net_device *netdev, |
603cdca9 | 2674 | __always_unused __be16 proto, u16 vid) |
bc7f75fa AK |
2675 | { |
2676 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
2677 | struct e1000_hw *hw = &adapter->hw; | |
2678 | u32 vfta, index; | |
2679 | ||
2680 | /* don't update vlan cookie if already programmed */ | |
2681 | if ((adapter->hw.mng_cookie.status & | |
2682 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
2683 | (vid == adapter->mng_vlan_id)) | |
8e586137 | 2684 | return 0; |
caaddaf8 | 2685 | |
bc7f75fa | 2686 | /* add VID to filter table */ |
caaddaf8 BA |
2687 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { |
2688 | index = (vid >> 5) & 0x7F; | |
2689 | vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); | |
2690 | vfta |= (1 << (vid & 0x1F)); | |
2691 | hw->mac.ops.write_vfta(hw, index, vfta); | |
2692 | } | |
86d70e53 JK |
2693 | |
2694 | set_bit(vid, adapter->active_vlans); | |
8e586137 JP |
2695 | |
2696 | return 0; | |
bc7f75fa AK |
2697 | } |
2698 | ||
80d5c368 | 2699 | static int e1000_vlan_rx_kill_vid(struct net_device *netdev, |
603cdca9 | 2700 | __always_unused __be16 proto, u16 vid) |
bc7f75fa AK |
2701 | { |
2702 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
2703 | struct e1000_hw *hw = &adapter->hw; | |
2704 | u32 vfta, index; | |
2705 | ||
bc7f75fa AK |
2706 | if ((adapter->hw.mng_cookie.status & |
2707 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
2708 | (vid == adapter->mng_vlan_id)) { | |
2709 | /* release control to f/w */ | |
31dbe5b4 | 2710 | e1000e_release_hw_control(adapter); |
8e586137 | 2711 | return 0; |
bc7f75fa AK |
2712 | } |
2713 | ||
2714 | /* remove VID from filter table */ | |
caaddaf8 BA |
2715 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { |
2716 | index = (vid >> 5) & 0x7F; | |
2717 | vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); | |
2718 | vfta &= ~(1 << (vid & 0x1F)); | |
2719 | hw->mac.ops.write_vfta(hw, index, vfta); | |
2720 | } | |
86d70e53 JK |
2721 | |
2722 | clear_bit(vid, adapter->active_vlans); | |
8e586137 JP |
2723 | |
2724 | return 0; | |
bc7f75fa AK |
2725 | } |
2726 | ||
86d70e53 JK |
2727 | /** |
2728 | * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering | |
2729 | * @adapter: board private structure to initialize | |
2730 | **/ | |
2731 | static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) | |
bc7f75fa AK |
2732 | { |
2733 | struct net_device *netdev = adapter->netdev; | |
86d70e53 JK |
2734 | struct e1000_hw *hw = &adapter->hw; |
2735 | u32 rctl; | |
bc7f75fa | 2736 | |
86d70e53 JK |
2737 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { |
2738 | /* disable VLAN receive filtering */ | |
2739 | rctl = er32(RCTL); | |
2740 | rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); | |
2741 | ew32(RCTL, rctl); | |
2742 | ||
2743 | if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { | |
80d5c368 PM |
2744 | e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), |
2745 | adapter->mng_vlan_id); | |
86d70e53 | 2746 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; |
bc7f75fa | 2747 | } |
bc7f75fa AK |
2748 | } |
2749 | } | |
2750 | ||
86d70e53 JK |
2751 | /** |
2752 | * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering | |
2753 | * @adapter: board private structure to initialize | |
2754 | **/ | |
2755 | static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) | |
2756 | { | |
2757 | struct e1000_hw *hw = &adapter->hw; | |
2758 | u32 rctl; | |
2759 | ||
2760 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { | |
2761 | /* enable VLAN receive filtering */ | |
2762 | rctl = er32(RCTL); | |
2763 | rctl |= E1000_RCTL_VFE; | |
2764 | rctl &= ~E1000_RCTL_CFIEN; | |
2765 | ew32(RCTL, rctl); | |
2766 | } | |
2767 | } | |
bc7f75fa | 2768 | |
86d70e53 JK |
2769 | /** |
2770 | * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping | |
2771 | * @adapter: board private structure to initialize | |
2772 | **/ | |
2773 | static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) | |
bc7f75fa | 2774 | { |
bc7f75fa | 2775 | struct e1000_hw *hw = &adapter->hw; |
86d70e53 | 2776 | u32 ctrl; |
bc7f75fa | 2777 | |
86d70e53 JK |
2778 | /* disable VLAN tag insert/strip */ |
2779 | ctrl = er32(CTRL); | |
2780 | ctrl &= ~E1000_CTRL_VME; | |
2781 | ew32(CTRL, ctrl); | |
2782 | } | |
bc7f75fa | 2783 | |
86d70e53 JK |
2784 | /** |
2785 | * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping | |
2786 | * @adapter: board private structure to initialize | |
2787 | **/ | |
2788 | static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) | |
2789 | { | |
2790 | struct e1000_hw *hw = &adapter->hw; | |
2791 | u32 ctrl; | |
bc7f75fa | 2792 | |
86d70e53 JK |
2793 | /* enable VLAN tag insert/strip */ |
2794 | ctrl = er32(CTRL); | |
2795 | ctrl |= E1000_CTRL_VME; | |
2796 | ew32(CTRL, ctrl); | |
2797 | } | |
bc7f75fa | 2798 | |
86d70e53 JK |
2799 | static void e1000_update_mng_vlan(struct e1000_adapter *adapter) |
2800 | { | |
2801 | struct net_device *netdev = adapter->netdev; | |
2802 | u16 vid = adapter->hw.mng_cookie.vlan_id; | |
2803 | u16 old_vid = adapter->mng_vlan_id; | |
2804 | ||
e5fe2541 | 2805 | if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { |
80d5c368 | 2806 | e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); |
86d70e53 | 2807 | adapter->mng_vlan_id = vid; |
bc7f75fa AK |
2808 | } |
2809 | ||
86d70e53 | 2810 | if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) |
80d5c368 | 2811 | e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); |
bc7f75fa AK |
2812 | } |
2813 | ||
2814 | static void e1000_restore_vlan(struct e1000_adapter *adapter) | |
2815 | { | |
2816 | u16 vid; | |
2817 | ||
80d5c368 | 2818 | e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); |
bc7f75fa | 2819 | |
86d70e53 | 2820 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
80d5c368 | 2821 | e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
bc7f75fa AK |
2822 | } |
2823 | ||
cd791618 | 2824 | static void e1000_init_manageability_pt(struct e1000_adapter *adapter) |
bc7f75fa AK |
2825 | { |
2826 | struct e1000_hw *hw = &adapter->hw; | |
cd791618 | 2827 | u32 manc, manc2h, mdef, i, j; |
bc7f75fa AK |
2828 | |
2829 | if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) | |
2830 | return; | |
2831 | ||
2832 | manc = er32(MANC); | |
2833 | ||
e921eb1a | 2834 | /* enable receiving management packets to the host. this will probably |
bc7f75fa | 2835 | * generate destination unreachable messages from the host OS, but |
ad68076e BA |
2836 | * the packets will be handled on SMBUS |
2837 | */ | |
bc7f75fa AK |
2838 | manc |= E1000_MANC_EN_MNG2HOST; |
2839 | manc2h = er32(MANC2H); | |
cd791618 BA |
2840 | |
2841 | switch (hw->mac.type) { | |
2842 | default: | |
2843 | manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); | |
2844 | break; | |
2845 | case e1000_82574: | |
2846 | case e1000_82583: | |
e921eb1a | 2847 | /* Check if IPMI pass-through decision filter already exists; |
cd791618 BA |
2848 | * if so, enable it. |
2849 | */ | |
2850 | for (i = 0, j = 0; i < 8; i++) { | |
2851 | mdef = er32(MDEF(i)); | |
2852 | ||
2853 | /* Ignore filters with anything other than IPMI ports */ | |
3b21b508 | 2854 | if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) |
cd791618 BA |
2855 | continue; |
2856 | ||
2857 | /* Enable this decision filter in MANC2H */ | |
2858 | if (mdef) | |
2859 | manc2h |= (1 << i); | |
2860 | ||
2861 | j |= mdef; | |
2862 | } | |
2863 | ||
2864 | if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) | |
2865 | break; | |
2866 | ||
2867 | /* Create new decision filter in an empty filter */ | |
2868 | for (i = 0, j = 0; i < 8; i++) | |
2869 | if (er32(MDEF(i)) == 0) { | |
2870 | ew32(MDEF(i), (E1000_MDEF_PORT_623 | | |
2871 | E1000_MDEF_PORT_664)); | |
2872 | manc2h |= (1 << 1); | |
2873 | j++; | |
2874 | break; | |
2875 | } | |
2876 | ||
2877 | if (!j) | |
2878 | e_warn("Unable to create IPMI pass-through filter\n"); | |
2879 | break; | |
2880 | } | |
2881 | ||
bc7f75fa AK |
2882 | ew32(MANC2H, manc2h); |
2883 | ew32(MANC, manc); | |
2884 | } | |
2885 | ||
2886 | /** | |
af667a29 | 2887 | * e1000_configure_tx - Configure Transmit Unit after Reset |
bc7f75fa AK |
2888 | * @adapter: board private structure |
2889 | * | |
2890 | * Configure the Tx unit of the MAC after a reset. | |
2891 | **/ | |
2892 | static void e1000_configure_tx(struct e1000_adapter *adapter) | |
2893 | { | |
2894 | struct e1000_hw *hw = &adapter->hw; | |
2895 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
2896 | u64 tdba; | |
c550b121 | 2897 | u32 tdlen, tarc; |
bc7f75fa AK |
2898 | |
2899 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
2900 | tdba = tx_ring->dma; | |
2901 | tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); | |
1e36052e BA |
2902 | ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); |
2903 | ew32(TDBAH(0), (tdba >> 32)); | |
2904 | ew32(TDLEN(0), tdlen); | |
2905 | ew32(TDH(0), 0); | |
2906 | ew32(TDT(0), 0); | |
2907 | tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); | |
2908 | tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); | |
bc7f75fa | 2909 | |
bc7f75fa AK |
2910 | /* Set the Tx Interrupt Delay register */ |
2911 | ew32(TIDV, adapter->tx_int_delay); | |
ad68076e | 2912 | /* Tx irq moderation */ |
bc7f75fa AK |
2913 | ew32(TADV, adapter->tx_abs_int_delay); |
2914 | ||
3a3b7586 JB |
2915 | if (adapter->flags2 & FLAG2_DMA_BURST) { |
2916 | u32 txdctl = er32(TXDCTL(0)); | |
2917 | txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | | |
2918 | E1000_TXDCTL_WTHRESH); | |
e921eb1a | 2919 | /* set up some performance related parameters to encourage the |
3a3b7586 JB |
2920 | * hardware to use the bus more efficiently in bursts, depends |
2921 | * on the tx_int_delay to be enabled, | |
8edc0e62 | 2922 | * wthresh = 1 ==> burst write is disabled to avoid Tx stalls |
3a3b7586 JB |
2923 | * hthresh = 1 ==> prefetch when one or more available |
2924 | * pthresh = 0x1f ==> prefetch if internal cache 31 or less | |
2925 | * BEWARE: this seems to work but should be considered first if | |
af667a29 | 2926 | * there are Tx hangs or other Tx related bugs |
3a3b7586 JB |
2927 | */ |
2928 | txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; | |
2929 | ew32(TXDCTL(0), txdctl); | |
3a3b7586 | 2930 | } |
56032be7 BA |
2931 | /* erratum work around: set txdctl the same for both queues */ |
2932 | ew32(TXDCTL(1), er32(TXDCTL(0))); | |
3a3b7586 | 2933 | |
bc7f75fa | 2934 | if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { |
e9ec2c0f | 2935 | tarc = er32(TARC(0)); |
e921eb1a | 2936 | /* set the speed mode bit, we'll clear it if we're not at |
ad68076e BA |
2937 | * gigabit link later |
2938 | */ | |
bc7f75fa AK |
2939 | #define SPEED_MODE_BIT (1 << 21) |
2940 | tarc |= SPEED_MODE_BIT; | |
e9ec2c0f | 2941 | ew32(TARC(0), tarc); |
bc7f75fa AK |
2942 | } |
2943 | ||
2944 | /* errata: program both queues to unweighted RR */ | |
2945 | if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { | |
e9ec2c0f | 2946 | tarc = er32(TARC(0)); |
bc7f75fa | 2947 | tarc |= 1; |
e9ec2c0f JK |
2948 | ew32(TARC(0), tarc); |
2949 | tarc = er32(TARC(1)); | |
bc7f75fa | 2950 | tarc |= 1; |
e9ec2c0f | 2951 | ew32(TARC(1), tarc); |
bc7f75fa AK |
2952 | } |
2953 | ||
bc7f75fa AK |
2954 | /* Setup Transmit Descriptor Settings for eop descriptor */ |
2955 | adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; | |
2956 | ||
2957 | /* only set IDE if we are delaying interrupts using the timers */ | |
2958 | if (adapter->tx_int_delay) | |
2959 | adapter->txd_cmd |= E1000_TXD_CMD_IDE; | |
2960 | ||
2961 | /* enable Report Status bit */ | |
2962 | adapter->txd_cmd |= E1000_TXD_CMD_RS; | |
2963 | ||
57cde763 | 2964 | hw->mac.ops.config_collision_dist(hw); |
bc7f75fa AK |
2965 | } |
2966 | ||
2967 | /** | |
2968 | * e1000_setup_rctl - configure the receive control registers | |
2969 | * @adapter: Board private structure | |
2970 | **/ | |
2971 | #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ | |
2972 | (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) | |
2973 | static void e1000_setup_rctl(struct e1000_adapter *adapter) | |
2974 | { | |
2975 | struct e1000_hw *hw = &adapter->hw; | |
2976 | u32 rctl, rfctl; | |
bc7f75fa AK |
2977 | u32 pages = 0; |
2978 | ||
2fbe4526 | 2979 | /* Workaround Si errata on PCHx - configure jumbo frame flow */ |
da1e2046 BA |
2980 | if ((hw->mac.type >= e1000_pch2lan) && |
2981 | (adapter->netdev->mtu > ETH_DATA_LEN) && | |
2982 | e1000_lv_jumbo_workaround_ich8lan(hw, true)) | |
2983 | e_dbg("failed to enable jumbo frame workaround mode\n"); | |
a1ce6473 | 2984 | |
bc7f75fa AK |
2985 | /* Program MC offset vector base */ |
2986 | rctl = er32(RCTL); | |
2987 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
2988 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | | |
f0ff4398 BA |
2989 | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | |
2990 | (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); | |
bc7f75fa AK |
2991 | |
2992 | /* Do not Store bad packets */ | |
2993 | rctl &= ~E1000_RCTL_SBP; | |
2994 | ||
2995 | /* Enable Long Packet receive */ | |
2996 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
2997 | rctl &= ~E1000_RCTL_LPE; | |
2998 | else | |
2999 | rctl |= E1000_RCTL_LPE; | |
3000 | ||
eb7c3adb JK |
3001 | /* Some systems expect that the CRC is included in SMBUS traffic. The |
3002 | * hardware strips the CRC before sending to both SMBUS (BMC) and to | |
3003 | * host memory when this is enabled | |
3004 | */ | |
3005 | if (adapter->flags2 & FLAG2_CRC_STRIPPING) | |
3006 | rctl |= E1000_RCTL_SECRC; | |
5918bd88 | 3007 | |
a4f58f54 BA |
3008 | /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ |
3009 | if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { | |
3010 | u16 phy_data; | |
3011 | ||
3012 | e1e_rphy(hw, PHY_REG(770, 26), &phy_data); | |
3013 | phy_data &= 0xfff8; | |
3014 | phy_data |= (1 << 2); | |
3015 | e1e_wphy(hw, PHY_REG(770, 26), phy_data); | |
3016 | ||
3017 | e1e_rphy(hw, 22, &phy_data); | |
3018 | phy_data &= 0x0fff; | |
3019 | phy_data |= (1 << 14); | |
3020 | e1e_wphy(hw, 0x10, 0x2823); | |
3021 | e1e_wphy(hw, 0x11, 0x0003); | |
3022 | e1e_wphy(hw, 22, phy_data); | |
3023 | } | |
3024 | ||
bc7f75fa AK |
3025 | /* Setup buffer sizes */ |
3026 | rctl &= ~E1000_RCTL_SZ_4096; | |
3027 | rctl |= E1000_RCTL_BSEX; | |
3028 | switch (adapter->rx_buffer_len) { | |
bc7f75fa AK |
3029 | case 2048: |
3030 | default: | |
3031 | rctl |= E1000_RCTL_SZ_2048; | |
3032 | rctl &= ~E1000_RCTL_BSEX; | |
3033 | break; | |
3034 | case 4096: | |
3035 | rctl |= E1000_RCTL_SZ_4096; | |
3036 | break; | |
3037 | case 8192: | |
3038 | rctl |= E1000_RCTL_SZ_8192; | |
3039 | break; | |
3040 | case 16384: | |
3041 | rctl |= E1000_RCTL_SZ_16384; | |
3042 | break; | |
3043 | } | |
3044 | ||
5f450212 BA |
3045 | /* Enable Extended Status in all Receive Descriptors */ |
3046 | rfctl = er32(RFCTL); | |
3047 | rfctl |= E1000_RFCTL_EXTEN; | |
f6bd5577 | 3048 | ew32(RFCTL, rfctl); |
5f450212 | 3049 | |
e921eb1a | 3050 | /* 82571 and greater support packet-split where the protocol |
bc7f75fa AK |
3051 | * header is placed in skb->data and the packet data is |
3052 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | |
3053 | * In the case of a non-split, skb->data is linearly filled, | |
3054 | * followed by the page buffers. Therefore, skb->data is | |
3055 | * sized to hold the largest protocol header. | |
3056 | * | |
3057 | * allocations using alloc_page take too long for regular MTU | |
3058 | * so only enable packet split for jumbo frames | |
3059 | * | |
3060 | * Using pages when the page size is greater than 16k wastes | |
3061 | * a lot of memory, since we allocate 3 pages at all times | |
3062 | * per packet. | |
3063 | */ | |
bc7f75fa | 3064 | pages = PAGE_USE_COUNT(adapter->netdev->mtu); |
79d4e908 | 3065 | if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) |
bc7f75fa | 3066 | adapter->rx_ps_pages = pages; |
97ac8cae BA |
3067 | else |
3068 | adapter->rx_ps_pages = 0; | |
bc7f75fa AK |
3069 | |
3070 | if (adapter->rx_ps_pages) { | |
90da0669 BA |
3071 | u32 psrctl = 0; |
3072 | ||
140a7480 AK |
3073 | /* Enable Packet split descriptors */ |
3074 | rctl |= E1000_RCTL_DTYP_PS; | |
bc7f75fa | 3075 | |
e5fe2541 | 3076 | psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; |
bc7f75fa AK |
3077 | |
3078 | switch (adapter->rx_ps_pages) { | |
3079 | case 3: | |
e5fe2541 BA |
3080 | psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; |
3081 | /* fall-through */ | |
bc7f75fa | 3082 | case 2: |
e5fe2541 BA |
3083 | psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; |
3084 | /* fall-through */ | |
bc7f75fa | 3085 | case 1: |
e5fe2541 | 3086 | psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; |
bc7f75fa AK |
3087 | break; |
3088 | } | |
3089 | ||
3090 | ew32(PSRCTL, psrctl); | |
3091 | } | |
3092 | ||
cf955e6c BG |
3093 | /* This is useful for sniffing bad packets. */ |
3094 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3095 | /* UPE and MPE will be handled by normal PROMISC logic | |
e921eb1a BA |
3096 | * in e1000e_set_rx_mode |
3097 | */ | |
e80bd1d1 BA |
3098 | rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ |
3099 | E1000_RCTL_BAM | /* RX All Bcast Pkts */ | |
3100 | E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ | |
cf955e6c | 3101 | |
e80bd1d1 BA |
3102 | rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ |
3103 | E1000_RCTL_DPF | /* Allow filtered pause */ | |
3104 | E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ | |
cf955e6c BG |
3105 | /* Do not mess with E1000_CTRL_VME, it affects transmit as well, |
3106 | * and that breaks VLANs. | |
3107 | */ | |
3108 | } | |
3109 | ||
bc7f75fa | 3110 | ew32(RCTL, rctl); |
318a94d6 | 3111 | /* just started the receive unit, no need to restart */ |
12d43f7d | 3112 | adapter->flags &= ~FLAG_RESTART_NOW; |
bc7f75fa AK |
3113 | } |
3114 | ||
3115 | /** | |
3116 | * e1000_configure_rx - Configure Receive Unit after Reset | |
3117 | * @adapter: board private structure | |
3118 | * | |
3119 | * Configure the Rx unit of the MAC after a reset. | |
3120 | **/ | |
3121 | static void e1000_configure_rx(struct e1000_adapter *adapter) | |
3122 | { | |
3123 | struct e1000_hw *hw = &adapter->hw; | |
3124 | struct e1000_ring *rx_ring = adapter->rx_ring; | |
3125 | u64 rdba; | |
3126 | u32 rdlen, rctl, rxcsum, ctrl_ext; | |
3127 | ||
3128 | if (adapter->rx_ps_pages) { | |
3129 | /* this is a 32 byte descriptor */ | |
3130 | rdlen = rx_ring->count * | |
af667a29 | 3131 | sizeof(union e1000_rx_desc_packet_split); |
bc7f75fa AK |
3132 | adapter->clean_rx = e1000_clean_rx_irq_ps; |
3133 | adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; | |
97ac8cae | 3134 | } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { |
5f450212 | 3135 | rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); |
97ac8cae BA |
3136 | adapter->clean_rx = e1000_clean_jumbo_rx_irq; |
3137 | adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; | |
bc7f75fa | 3138 | } else { |
5f450212 | 3139 | rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); |
bc7f75fa AK |
3140 | adapter->clean_rx = e1000_clean_rx_irq; |
3141 | adapter->alloc_rx_buf = e1000_alloc_rx_buffers; | |
3142 | } | |
3143 | ||
3144 | /* disable receives while setting up the descriptors */ | |
3145 | rctl = er32(RCTL); | |
7f99ae63 BA |
3146 | if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) |
3147 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
bc7f75fa | 3148 | e1e_flush(); |
1bba4386 | 3149 | usleep_range(10000, 20000); |
bc7f75fa | 3150 | |
3a3b7586 | 3151 | if (adapter->flags2 & FLAG2_DMA_BURST) { |
e921eb1a | 3152 | /* set the writeback threshold (only takes effect if the RDTR |
3a3b7586 | 3153 | * is set). set GRAN=1 and write back up to 0x4 worth, and |
af667a29 | 3154 | * enable prefetching of 0x20 Rx descriptors |
3a3b7586 JB |
3155 | * granularity = 01 |
3156 | * wthresh = 04, | |
3157 | * hthresh = 04, | |
3158 | * pthresh = 0x20 | |
3159 | */ | |
3160 | ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); | |
3161 | ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); | |
3162 | ||
e921eb1a | 3163 | /* override the delay timers for enabling bursting, only if |
3a3b7586 JB |
3164 | * the value was not set by the user via module options |
3165 | */ | |
3166 | if (adapter->rx_int_delay == DEFAULT_RDTR) | |
3167 | adapter->rx_int_delay = BURST_RDTR; | |
3168 | if (adapter->rx_abs_int_delay == DEFAULT_RADV) | |
3169 | adapter->rx_abs_int_delay = BURST_RADV; | |
3170 | } | |
3171 | ||
bc7f75fa AK |
3172 | /* set the Receive Delay Timer Register */ |
3173 | ew32(RDTR, adapter->rx_int_delay); | |
3174 | ||
3175 | /* irq moderation */ | |
3176 | ew32(RADV, adapter->rx_abs_int_delay); | |
828bac87 | 3177 | if ((adapter->itr_setting != 0) && (adapter->itr != 0)) |
22a4cca2 | 3178 | e1000e_write_itr(adapter, adapter->itr); |
bc7f75fa AK |
3179 | |
3180 | ctrl_ext = er32(CTRL_EXT); | |
bc7f75fa AK |
3181 | /* Auto-Mask interrupts upon ICR access */ |
3182 | ctrl_ext |= E1000_CTRL_EXT_IAME; | |
3183 | ew32(IAM, 0xffffffff); | |
3184 | ew32(CTRL_EXT, ctrl_ext); | |
3185 | e1e_flush(); | |
3186 | ||
e921eb1a | 3187 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
ad68076e BA |
3188 | * the Base and Length of the Rx Descriptor Ring |
3189 | */ | |
bc7f75fa | 3190 | rdba = rx_ring->dma; |
1e36052e BA |
3191 | ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); |
3192 | ew32(RDBAH(0), (rdba >> 32)); | |
3193 | ew32(RDLEN(0), rdlen); | |
3194 | ew32(RDH(0), 0); | |
3195 | ew32(RDT(0), 0); | |
3196 | rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); | |
3197 | rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); | |
bc7f75fa AK |
3198 | |
3199 | /* Enable Receive Checksum Offload for TCP and UDP */ | |
3200 | rxcsum = er32(RXCSUM); | |
2e1706f2 | 3201 | if (adapter->netdev->features & NETIF_F_RXCSUM) |
bc7f75fa | 3202 | rxcsum |= E1000_RXCSUM_TUOFL; |
2e1706f2 | 3203 | else |
bc7f75fa | 3204 | rxcsum &= ~E1000_RXCSUM_TUOFL; |
bc7f75fa AK |
3205 | ew32(RXCSUM, rxcsum); |
3206 | ||
3e35d991 BA |
3207 | /* With jumbo frames, excessive C-state transition latencies result |
3208 | * in dropped transactions. | |
3209 | */ | |
3210 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | |
3211 | u32 lat = | |
3212 | ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - | |
3213 | adapter->max_frame_size) * 8 / 1000; | |
3214 | ||
3215 | if (adapter->flags & FLAG_IS_ICH) { | |
53ec5498 BA |
3216 | u32 rxdctl = er32(RXDCTL(0)); |
3217 | ew32(RXDCTL(0), rxdctl | 0x3); | |
53ec5498 | 3218 | } |
3e35d991 BA |
3219 | |
3220 | pm_qos_update_request(&adapter->netdev->pm_qos_req, lat); | |
3221 | } else { | |
3222 | pm_qos_update_request(&adapter->netdev->pm_qos_req, | |
3223 | PM_QOS_DEFAULT_VALUE); | |
97ac8cae | 3224 | } |
bc7f75fa AK |
3225 | |
3226 | /* Enable Receives */ | |
3227 | ew32(RCTL, rctl); | |
3228 | } | |
3229 | ||
3230 | /** | |
ef9b965a JB |
3231 | * e1000e_write_mc_addr_list - write multicast addresses to MTA |
3232 | * @netdev: network interface device structure | |
bc7f75fa | 3233 | * |
ef9b965a JB |
3234 | * Writes multicast address list to the MTA hash table. |
3235 | * Returns: -ENOMEM on failure | |
3236 | * 0 on no addresses written | |
3237 | * X on writing X addresses to MTA | |
3238 | */ | |
3239 | static int e1000e_write_mc_addr_list(struct net_device *netdev) | |
3240 | { | |
3241 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
3242 | struct e1000_hw *hw = &adapter->hw; | |
3243 | struct netdev_hw_addr *ha; | |
3244 | u8 *mta_list; | |
3245 | int i; | |
3246 | ||
3247 | if (netdev_mc_empty(netdev)) { | |
3248 | /* nothing to program, so clear mc list */ | |
3249 | hw->mac.ops.update_mc_addr_list(hw, NULL, 0); | |
3250 | return 0; | |
3251 | } | |
3252 | ||
3253 | mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); | |
3254 | if (!mta_list) | |
3255 | return -ENOMEM; | |
3256 | ||
3257 | /* update_mc_addr_list expects a packed array of only addresses. */ | |
3258 | i = 0; | |
3259 | netdev_for_each_mc_addr(ha, netdev) | |
f0ff4398 | 3260 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); |
ef9b965a JB |
3261 | |
3262 | hw->mac.ops.update_mc_addr_list(hw, mta_list, i); | |
3263 | kfree(mta_list); | |
3264 | ||
3265 | return netdev_mc_count(netdev); | |
3266 | } | |
3267 | ||
3268 | /** | |
3269 | * e1000e_write_uc_addr_list - write unicast addresses to RAR table | |
3270 | * @netdev: network interface device structure | |
bc7f75fa | 3271 | * |
ef9b965a JB |
3272 | * Writes unicast address list to the RAR table. |
3273 | * Returns: -ENOMEM on failure/insufficient address space | |
3274 | * 0 on no addresses written | |
3275 | * X on writing X addresses to the RAR table | |
bc7f75fa | 3276 | **/ |
ef9b965a | 3277 | static int e1000e_write_uc_addr_list(struct net_device *netdev) |
bc7f75fa | 3278 | { |
ef9b965a JB |
3279 | struct e1000_adapter *adapter = netdev_priv(netdev); |
3280 | struct e1000_hw *hw = &adapter->hw; | |
3281 | unsigned int rar_entries = hw->mac.rar_entry_count; | |
3282 | int count = 0; | |
3283 | ||
3284 | /* save a rar entry for our hardware address */ | |
3285 | rar_entries--; | |
3286 | ||
3287 | /* save a rar entry for the LAA workaround */ | |
3288 | if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) | |
3289 | rar_entries--; | |
3290 | ||
3291 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3292 | if (netdev_uc_count(netdev) > rar_entries) | |
3293 | return -ENOMEM; | |
3294 | ||
3295 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3296 | struct netdev_hw_addr *ha; | |
3297 | ||
e921eb1a | 3298 | /* write the addresses in reverse order to avoid write |
ef9b965a JB |
3299 | * combining |
3300 | */ | |
3301 | netdev_for_each_uc_addr(ha, netdev) { | |
3302 | if (!rar_entries) | |
3303 | break; | |
69e1e019 | 3304 | hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); |
ef9b965a JB |
3305 | count++; |
3306 | } | |
3307 | } | |
3308 | ||
3309 | /* zero out the remaining RAR entries not used above */ | |
3310 | for (; rar_entries > 0; rar_entries--) { | |
3311 | ew32(RAH(rar_entries), 0); | |
3312 | ew32(RAL(rar_entries), 0); | |
3313 | } | |
3314 | e1e_flush(); | |
3315 | ||
3316 | return count; | |
bc7f75fa AK |
3317 | } |
3318 | ||
3319 | /** | |
ef9b965a | 3320 | * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set |
bc7f75fa AK |
3321 | * @netdev: network interface device structure |
3322 | * | |
ef9b965a JB |
3323 | * The ndo_set_rx_mode entry point is called whenever the unicast or multicast |
3324 | * address list or the network interface flags are updated. This routine is | |
3325 | * responsible for configuring the hardware for proper unicast, multicast, | |
bc7f75fa AK |
3326 | * promiscuous mode, and all-multi behavior. |
3327 | **/ | |
ef9b965a | 3328 | static void e1000e_set_rx_mode(struct net_device *netdev) |
bc7f75fa AK |
3329 | { |
3330 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
3331 | struct e1000_hw *hw = &adapter->hw; | |
bc7f75fa | 3332 | u32 rctl; |
bc7f75fa AK |
3333 | |
3334 | /* Check for Promiscuous and All Multicast modes */ | |
bc7f75fa AK |
3335 | rctl = er32(RCTL); |
3336 | ||
ef9b965a JB |
3337 | /* clear the affected bits */ |
3338 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | |
3339 | ||
bc7f75fa AK |
3340 | if (netdev->flags & IFF_PROMISC) { |
3341 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
86d70e53 JK |
3342 | /* Do not hardware filter VLANs in promisc mode */ |
3343 | e1000e_vlan_filter_disable(adapter); | |
bc7f75fa | 3344 | } else { |
ef9b965a | 3345 | int count; |
3d3a1676 | 3346 | |
746b9f02 PM |
3347 | if (netdev->flags & IFF_ALLMULTI) { |
3348 | rctl |= E1000_RCTL_MPE; | |
746b9f02 | 3349 | } else { |
e921eb1a | 3350 | /* Write addresses to the MTA, if the attempt fails |
ef9b965a JB |
3351 | * then we should just turn on promiscuous mode so |
3352 | * that we can at least receive multicast traffic | |
3353 | */ | |
3354 | count = e1000e_write_mc_addr_list(netdev); | |
3355 | if (count < 0) | |
3356 | rctl |= E1000_RCTL_MPE; | |
746b9f02 | 3357 | } |
86d70e53 | 3358 | e1000e_vlan_filter_enable(adapter); |
e921eb1a | 3359 | /* Write addresses to available RAR registers, if there is not |
ef9b965a JB |
3360 | * sufficient space to store all the addresses then enable |
3361 | * unicast promiscuous mode | |
bc7f75fa | 3362 | */ |
ef9b965a JB |
3363 | count = e1000e_write_uc_addr_list(netdev); |
3364 | if (count < 0) | |
3365 | rctl |= E1000_RCTL_UPE; | |
bc7f75fa | 3366 | } |
86d70e53 | 3367 | |
ef9b965a JB |
3368 | ew32(RCTL, rctl); |
3369 | ||
f646968f | 3370 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) |
86d70e53 JK |
3371 | e1000e_vlan_strip_enable(adapter); |
3372 | else | |
3373 | e1000e_vlan_strip_disable(adapter); | |
bc7f75fa AK |
3374 | } |
3375 | ||
70495a50 BA |
3376 | static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) |
3377 | { | |
3378 | struct e1000_hw *hw = &adapter->hw; | |
3379 | u32 mrqc, rxcsum; | |
3380 | int i; | |
3381 | static const u32 rsskey[10] = { | |
3382 | 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0, | |
3383 | 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe | |
3384 | }; | |
3385 | ||
3386 | /* Fill out hash function seed */ | |
3387 | for (i = 0; i < 10; i++) | |
3388 | ew32(RSSRK(i), rsskey[i]); | |
3389 | ||
3390 | /* Direct all traffic to queue 0 */ | |
3391 | for (i = 0; i < 32; i++) | |
3392 | ew32(RETA(i), 0); | |
3393 | ||
e921eb1a | 3394 | /* Disable raw packet checksumming so that RSS hash is placed in |
70495a50 BA |
3395 | * descriptor on writeback. |
3396 | */ | |
3397 | rxcsum = er32(RXCSUM); | |
3398 | rxcsum |= E1000_RXCSUM_PCSD; | |
3399 | ||
3400 | ew32(RXCSUM, rxcsum); | |
3401 | ||
3402 | mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | | |
3403 | E1000_MRQC_RSS_FIELD_IPV4_TCP | | |
3404 | E1000_MRQC_RSS_FIELD_IPV6 | | |
3405 | E1000_MRQC_RSS_FIELD_IPV6_TCP | | |
3406 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
3407 | ||
3408 | ew32(MRQC, mrqc); | |
3409 | } | |
3410 | ||
b67e1913 BA |
3411 | /** |
3412 | * e1000e_get_base_timinca - get default SYSTIM time increment attributes | |
3413 | * @adapter: board private structure | |
3414 | * @timinca: pointer to returned time increment attributes | |
3415 | * | |
3416 | * Get attributes for incrementing the System Time Register SYSTIML/H at | |
3417 | * the default base frequency, and set the cyclecounter shift value. | |
3418 | **/ | |
d89777bf | 3419 | s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) |
b67e1913 BA |
3420 | { |
3421 | struct e1000_hw *hw = &adapter->hw; | |
3422 | u32 incvalue, incperiod, shift; | |
3423 | ||
3424 | /* Make sure clock is enabled on I217 before checking the frequency */ | |
3425 | if ((hw->mac.type == e1000_pch_lpt) && | |
3426 | !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && | |
3427 | !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { | |
3428 | u32 fextnvm7 = er32(FEXTNVM7); | |
3429 | ||
3430 | if (!(fextnvm7 & (1 << 0))) { | |
3431 | ew32(FEXTNVM7, fextnvm7 | (1 << 0)); | |
3432 | e1e_flush(); | |
3433 | } | |
3434 | } | |
3435 | ||
3436 | switch (hw->mac.type) { | |
3437 | case e1000_pch2lan: | |
3438 | case e1000_pch_lpt: | |
3439 | /* On I217, the clock frequency is 25MHz or 96MHz as | |
3440 | * indicated by the System Clock Frequency Indication | |
3441 | */ | |
3442 | if ((hw->mac.type != e1000_pch_lpt) || | |
3443 | (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { | |
3444 | /* Stable 96MHz frequency */ | |
3445 | incperiod = INCPERIOD_96MHz; | |
3446 | incvalue = INCVALUE_96MHz; | |
3447 | shift = INCVALUE_SHIFT_96MHz; | |
3448 | adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz; | |
3449 | break; | |
3450 | } | |
3451 | /* fall-through */ | |
3452 | case e1000_82574: | |
3453 | case e1000_82583: | |
3454 | /* Stable 25MHz frequency */ | |
3455 | incperiod = INCPERIOD_25MHz; | |
3456 | incvalue = INCVALUE_25MHz; | |
3457 | shift = INCVALUE_SHIFT_25MHz; | |
3458 | adapter->cc.shift = shift; | |
3459 | break; | |
3460 | default: | |
3461 | return -EINVAL; | |
3462 | } | |
3463 | ||
3464 | *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | | |
3465 | ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); | |
3466 | ||
3467 | return 0; | |
3468 | } | |
3469 | ||
3470 | /** | |
3471 | * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable | |
3472 | * @adapter: board private structure | |
3473 | * | |
3474 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
3475 | * disable it when requested, although it shouldn't cause any overhead | |
3476 | * when no packet needs it. At most one packet in the queue may be | |
3477 | * marked for time stamping, otherwise it would be impossible to tell | |
3478 | * for sure to which packet the hardware time stamp belongs. | |
3479 | * | |
3480 | * Incoming time stamping has to be configured via the hardware filters. | |
3481 | * Not all combinations are supported, in particular event type has to be | |
3482 | * specified. Matching the kind of event packet is not supported, with the | |
3483 | * exception of "all V2 events regardless of level 2 or 4". | |
3484 | **/ | |
3485 | static int e1000e_config_hwtstamp(struct e1000_adapter *adapter) | |
3486 | { | |
3487 | struct e1000_hw *hw = &adapter->hw; | |
3488 | struct hwtstamp_config *config = &adapter->hwtstamp_config; | |
3489 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; | |
3490 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
d89777bf BA |
3491 | u32 rxmtrl = 0; |
3492 | u16 rxudp = 0; | |
3493 | bool is_l4 = false; | |
3494 | bool is_l2 = false; | |
b67e1913 BA |
3495 | u32 regval; |
3496 | s32 ret_val; | |
3497 | ||
3498 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) | |
3499 | return -EINVAL; | |
3500 | ||
3501 | /* flags reserved for future extensions - must be zero */ | |
3502 | if (config->flags) | |
3503 | return -EINVAL; | |
3504 | ||
3505 | switch (config->tx_type) { | |
3506 | case HWTSTAMP_TX_OFF: | |
3507 | tsync_tx_ctl = 0; | |
3508 | break; | |
3509 | case HWTSTAMP_TX_ON: | |
3510 | break; | |
3511 | default: | |
3512 | return -ERANGE; | |
3513 | } | |
3514 | ||
3515 | switch (config->rx_filter) { | |
3516 | case HWTSTAMP_FILTER_NONE: | |
3517 | tsync_rx_ctl = 0; | |
3518 | break; | |
d89777bf BA |
3519 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
3520 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
3521 | rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; | |
3522 | is_l4 = true; | |
3523 | break; | |
3524 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3525 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
3526 | rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; | |
3527 | is_l4 = true; | |
3528 | break; | |
3529 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3530 | /* Also time stamps V2 L2 Path Delay Request/Response */ | |
3531 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; | |
3532 | rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; | |
3533 | is_l2 = true; | |
3534 | break; | |
3535 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3536 | /* Also time stamps V2 L2 Path Delay Request/Response. */ | |
3537 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; | |
3538 | rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; | |
3539 | is_l2 = true; | |
3540 | break; | |
3541 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3542 | /* Hardware cannot filter just V2 L4 Sync messages; | |
3543 | * fall-through to V2 (both L2 and L4) Sync. | |
3544 | */ | |
3545 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3546 | /* Also time stamps V2 Path Delay Request/Response. */ | |
3547 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
3548 | rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; | |
3549 | is_l2 = true; | |
3550 | is_l4 = true; | |
3551 | break; | |
3552 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3553 | /* Hardware cannot filter just V2 L4 Delay Request messages; | |
3554 | * fall-through to V2 (both L2 and L4) Delay Request. | |
3555 | */ | |
3556 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3557 | /* Also time stamps V2 Path Delay Request/Response. */ | |
3558 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
3559 | rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; | |
3560 | is_l2 = true; | |
3561 | is_l4 = true; | |
3562 | break; | |
3563 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3564 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3565 | /* Hardware cannot filter just V2 L4 or L2 Event messages; | |
3566 | * fall-through to all V2 (both L2 and L4) Events. | |
3567 | */ | |
3568 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3569 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; | |
3570 | config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
3571 | is_l2 = true; | |
3572 | is_l4 = true; | |
3573 | break; | |
3574 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3575 | /* For V1, the hardware can only filter Sync messages or | |
3576 | * Delay Request messages but not both so fall-through to | |
3577 | * time stamp all packets. | |
3578 | */ | |
b67e1913 | 3579 | case HWTSTAMP_FILTER_ALL: |
d89777bf BA |
3580 | is_l2 = true; |
3581 | is_l4 = true; | |
b67e1913 BA |
3582 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
3583 | config->rx_filter = HWTSTAMP_FILTER_ALL; | |
3584 | break; | |
3585 | default: | |
3586 | return -ERANGE; | |
3587 | } | |
3588 | ||
3589 | /* enable/disable Tx h/w time stamping */ | |
3590 | regval = er32(TSYNCTXCTL); | |
3591 | regval &= ~E1000_TSYNCTXCTL_ENABLED; | |
3592 | regval |= tsync_tx_ctl; | |
3593 | ew32(TSYNCTXCTL, regval); | |
3594 | if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != | |
3595 | (regval & E1000_TSYNCTXCTL_ENABLED)) { | |
3596 | e_err("Timesync Tx Control register not set as expected\n"); | |
3597 | return -EAGAIN; | |
3598 | } | |
3599 | ||
3600 | /* enable/disable Rx h/w time stamping */ | |
3601 | regval = er32(TSYNCRXCTL); | |
3602 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); | |
3603 | regval |= tsync_rx_ctl; | |
3604 | ew32(TSYNCRXCTL, regval); | |
3605 | if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | | |
3606 | E1000_TSYNCRXCTL_TYPE_MASK)) != | |
3607 | (regval & (E1000_TSYNCRXCTL_ENABLED | | |
3608 | E1000_TSYNCRXCTL_TYPE_MASK))) { | |
3609 | e_err("Timesync Rx Control register not set as expected\n"); | |
3610 | return -EAGAIN; | |
3611 | } | |
3612 | ||
d89777bf BA |
3613 | /* L2: define ethertype filter for time stamped packets */ |
3614 | if (is_l2) | |
3615 | rxmtrl |= ETH_P_1588; | |
3616 | ||
3617 | /* define which PTP packets get time stamped */ | |
3618 | ew32(RXMTRL, rxmtrl); | |
3619 | ||
3620 | /* Filter by destination port */ | |
3621 | if (is_l4) { | |
3622 | rxudp = PTP_EV_PORT; | |
3623 | cpu_to_be16s(&rxudp); | |
3624 | } | |
3625 | ew32(RXUDP, rxudp); | |
3626 | ||
3627 | e1e_flush(); | |
3628 | ||
b67e1913 | 3629 | /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ |
70806a7f BA |
3630 | er32(RXSTMPH); |
3631 | er32(TXSTMPH); | |
b67e1913 BA |
3632 | |
3633 | /* Get and set the System Time Register SYSTIM base frequency */ | |
3634 | ret_val = e1000e_get_base_timinca(adapter, ®val); | |
3635 | if (ret_val) | |
3636 | return ret_val; | |
3637 | ew32(TIMINCA, regval); | |
3638 | ||
3639 | /* reset the ns time counter */ | |
3640 | timecounter_init(&adapter->tc, &adapter->cc, | |
3641 | ktime_to_ns(ktime_get_real())); | |
3642 | ||
3643 | return 0; | |
3644 | } | |
3645 | ||
bc7f75fa | 3646 | /** |
ad68076e | 3647 | * e1000_configure - configure the hardware for Rx and Tx |
bc7f75fa AK |
3648 | * @adapter: private board structure |
3649 | **/ | |
3650 | static void e1000_configure(struct e1000_adapter *adapter) | |
3651 | { | |
55aa6985 BA |
3652 | struct e1000_ring *rx_ring = adapter->rx_ring; |
3653 | ||
ef9b965a | 3654 | e1000e_set_rx_mode(adapter->netdev); |
bc7f75fa AK |
3655 | |
3656 | e1000_restore_vlan(adapter); | |
cd791618 | 3657 | e1000_init_manageability_pt(adapter); |
bc7f75fa AK |
3658 | |
3659 | e1000_configure_tx(adapter); | |
70495a50 BA |
3660 | |
3661 | if (adapter->netdev->features & NETIF_F_RXHASH) | |
3662 | e1000e_setup_rss_hash(adapter); | |
bc7f75fa AK |
3663 | e1000_setup_rctl(adapter); |
3664 | e1000_configure_rx(adapter); | |
55aa6985 | 3665 | adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); |
bc7f75fa AK |
3666 | } |
3667 | ||
3668 | /** | |
3669 | * e1000e_power_up_phy - restore link in case the phy was powered down | |
3670 | * @adapter: address of board private structure | |
3671 | * | |
3672 | * The phy may be powered down to save power and turn off link when the | |
3673 | * driver is unloaded and wake on lan is not enabled (among others) | |
3674 | * *** this routine MUST be followed by a call to e1000e_reset *** | |
3675 | **/ | |
3676 | void e1000e_power_up_phy(struct e1000_adapter *adapter) | |
3677 | { | |
17f208de BA |
3678 | if (adapter->hw.phy.ops.power_up) |
3679 | adapter->hw.phy.ops.power_up(&adapter->hw); | |
bc7f75fa AK |
3680 | |
3681 | adapter->hw.mac.ops.setup_link(&adapter->hw); | |
3682 | } | |
3683 | ||
3684 | /** | |
3685 | * e1000_power_down_phy - Power down the PHY | |
3686 | * | |
17f208de BA |
3687 | * Power down the PHY so no link is implied when interface is down. |
3688 | * The PHY cannot be powered down if management or WoL is active. | |
bc7f75fa AK |
3689 | */ |
3690 | static void e1000_power_down_phy(struct e1000_adapter *adapter) | |
3691 | { | |
bc7f75fa | 3692 | /* WoL is enabled */ |
23b66e2b | 3693 | if (adapter->wol) |
bc7f75fa AK |
3694 | return; |
3695 | ||
17f208de BA |
3696 | if (adapter->hw.phy.ops.power_down) |
3697 | adapter->hw.phy.ops.power_down(&adapter->hw); | |
bc7f75fa AK |
3698 | } |
3699 | ||
3700 | /** | |
3701 | * e1000e_reset - bring the hardware into a known good state | |
3702 | * | |
3703 | * This function boots the hardware and enables some settings that | |
3704 | * require a configuration cycle of the hardware - those cannot be | |
3705 | * set/changed during runtime. After reset the device needs to be | |
ad68076e | 3706 | * properly configured for Rx, Tx etc. |
bc7f75fa AK |
3707 | */ |
3708 | void e1000e_reset(struct e1000_adapter *adapter) | |
3709 | { | |
3710 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
318a94d6 | 3711 | struct e1000_fc_info *fc = &adapter->hw.fc; |
bc7f75fa AK |
3712 | struct e1000_hw *hw = &adapter->hw; |
3713 | u32 tx_space, min_tx_space, min_rx_space; | |
318a94d6 | 3714 | u32 pba = adapter->pba; |
bc7f75fa AK |
3715 | u16 hwm; |
3716 | ||
ad68076e | 3717 | /* reset Packet Buffer Allocation to default */ |
318a94d6 | 3718 | ew32(PBA, pba); |
df762464 | 3719 | |
318a94d6 | 3720 | if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { |
e921eb1a | 3721 | /* To maintain wire speed transmits, the Tx FIFO should be |
bc7f75fa AK |
3722 | * large enough to accommodate two full transmit packets, |
3723 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
3724 | * the Rx FIFO should be large enough to accommodate at least | |
3725 | * one full receive packet and is similarly rounded up and | |
ad68076e BA |
3726 | * expressed in KB. |
3727 | */ | |
df762464 | 3728 | pba = er32(PBA); |
bc7f75fa | 3729 | /* upper 16 bits has Tx packet buffer allocation size in KB */ |
df762464 | 3730 | tx_space = pba >> 16; |
bc7f75fa | 3731 | /* lower 16 bits has Rx packet buffer allocation size in KB */ |
df762464 | 3732 | pba &= 0xffff; |
e921eb1a | 3733 | /* the Tx fifo also stores 16 bytes of information about the Tx |
ad68076e | 3734 | * but don't include ethernet FCS because hardware appends it |
318a94d6 JK |
3735 | */ |
3736 | min_tx_space = (adapter->max_frame_size + | |
e5fe2541 | 3737 | sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; |
bc7f75fa AK |
3738 | min_tx_space = ALIGN(min_tx_space, 1024); |
3739 | min_tx_space >>= 10; | |
3740 | /* software strips receive CRC, so leave room for it */ | |
318a94d6 | 3741 | min_rx_space = adapter->max_frame_size; |
bc7f75fa AK |
3742 | min_rx_space = ALIGN(min_rx_space, 1024); |
3743 | min_rx_space >>= 10; | |
3744 | ||
e921eb1a | 3745 | /* If current Tx allocation is less than the min Tx FIFO size, |
bc7f75fa | 3746 | * and the min Tx FIFO size is less than the current Rx FIFO |
ad68076e BA |
3747 | * allocation, take space away from current Rx allocation |
3748 | */ | |
df762464 AK |
3749 | if ((tx_space < min_tx_space) && |
3750 | ((min_tx_space - tx_space) < pba)) { | |
3751 | pba -= min_tx_space - tx_space; | |
bc7f75fa | 3752 | |
e921eb1a | 3753 | /* if short on Rx space, Rx wins and must trump Tx |
419e551c | 3754 | * adjustment |
ad68076e | 3755 | */ |
79d4e908 | 3756 | if (pba < min_rx_space) |
df762464 | 3757 | pba = min_rx_space; |
bc7f75fa | 3758 | } |
df762464 AK |
3759 | |
3760 | ew32(PBA, pba); | |
bc7f75fa AK |
3761 | } |
3762 | ||
e921eb1a | 3763 | /* flow control settings |
ad68076e | 3764 | * |
38eb394e | 3765 | * The high water mark must be low enough to fit one full frame |
bc7f75fa AK |
3766 | * (or the size used for early receive) above it in the Rx FIFO. |
3767 | * Set it to the lower of: | |
3768 | * - 90% of the Rx FIFO size, and | |
38eb394e | 3769 | * - the full Rx FIFO size minus one full frame |
ad68076e | 3770 | */ |
d3738bb8 BA |
3771 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) |
3772 | fc->pause_time = 0xFFFF; | |
3773 | else | |
3774 | fc->pause_time = E1000_FC_PAUSE_TIME; | |
b20caa80 | 3775 | fc->send_xon = true; |
d3738bb8 BA |
3776 | fc->current_mode = fc->requested_mode; |
3777 | ||
3778 | switch (hw->mac.type) { | |
79d4e908 BA |
3779 | case e1000_ich9lan: |
3780 | case e1000_ich10lan: | |
3781 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | |
3782 | pba = 14; | |
3783 | ew32(PBA, pba); | |
3784 | fc->high_water = 0x2800; | |
3785 | fc->low_water = fc->high_water - 8; | |
3786 | break; | |
3787 | } | |
3788 | /* fall-through */ | |
d3738bb8 | 3789 | default: |
79d4e908 BA |
3790 | hwm = min(((pba << 10) * 9 / 10), |
3791 | ((pba << 10) - adapter->max_frame_size)); | |
d3738bb8 | 3792 | |
e80bd1d1 | 3793 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ |
d3738bb8 BA |
3794 | fc->low_water = fc->high_water - 8; |
3795 | break; | |
3796 | case e1000_pchlan: | |
e921eb1a | 3797 | /* Workaround PCH LOM adapter hangs with certain network |
38eb394e BA |
3798 | * loads. If hangs persist, try disabling Tx flow control. |
3799 | */ | |
3800 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | |
3801 | fc->high_water = 0x3500; | |
e80bd1d1 | 3802 | fc->low_water = 0x1500; |
38eb394e BA |
3803 | } else { |
3804 | fc->high_water = 0x5000; | |
e80bd1d1 | 3805 | fc->low_water = 0x3000; |
38eb394e | 3806 | } |
a305595b | 3807 | fc->refresh_time = 0x1000; |
d3738bb8 BA |
3808 | break; |
3809 | case e1000_pch2lan: | |
2fbe4526 | 3810 | case e1000_pch_lpt: |
d3738bb8 | 3811 | fc->refresh_time = 0x0400; |
347b5201 BA |
3812 | |
3813 | if (adapter->netdev->mtu <= ETH_DATA_LEN) { | |
3814 | fc->high_water = 0x05C20; | |
3815 | fc->low_water = 0x05048; | |
3816 | fc->pause_time = 0x0650; | |
3817 | break; | |
828bac87 | 3818 | } |
347b5201 | 3819 | |
ce345e08 BA |
3820 | pba = 14; |
3821 | ew32(PBA, pba); | |
347b5201 BA |
3822 | fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; |
3823 | fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; | |
d3738bb8 | 3824 | break; |
38eb394e | 3825 | } |
bc7f75fa | 3826 | |
e921eb1a | 3827 | /* Alignment of Tx data is on an arbitrary byte boundary with the |
d821a4c4 BA |
3828 | * maximum size per Tx descriptor limited only to the transmit |
3829 | * allocation of the packet buffer minus 96 bytes with an upper | |
3830 | * limit of 24KB due to receive synchronization limitations. | |
3831 | */ | |
3832 | adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, | |
3833 | 24 << 10); | |
3834 | ||
e921eb1a | 3835 | /* Disable Adaptive Interrupt Moderation if 2 full packets cannot |
79d4e908 | 3836 | * fit in receive buffer. |
828bac87 BA |
3837 | */ |
3838 | if (adapter->itr_setting & 0x3) { | |
79d4e908 | 3839 | if ((adapter->max_frame_size * 2) > (pba << 10)) { |
828bac87 BA |
3840 | if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { |
3841 | dev_info(&adapter->pdev->dev, | |
17e813ec | 3842 | "Interrupt Throttle Rate off\n"); |
828bac87 | 3843 | adapter->flags2 |= FLAG2_DISABLE_AIM; |
22a4cca2 | 3844 | e1000e_write_itr(adapter, 0); |
828bac87 BA |
3845 | } |
3846 | } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { | |
3847 | dev_info(&adapter->pdev->dev, | |
17e813ec | 3848 | "Interrupt Throttle Rate on\n"); |
828bac87 BA |
3849 | adapter->flags2 &= ~FLAG2_DISABLE_AIM; |
3850 | adapter->itr = 20000; | |
22a4cca2 | 3851 | e1000e_write_itr(adapter, adapter->itr); |
828bac87 BA |
3852 | } |
3853 | } | |
3854 | ||
bc7f75fa AK |
3855 | /* Allow time for pending master requests to run */ |
3856 | mac->ops.reset_hw(hw); | |
97ac8cae | 3857 | |
e921eb1a | 3858 | /* For parts with AMT enabled, let the firmware know |
97ac8cae BA |
3859 | * that the network interface is in control |
3860 | */ | |
c43bc57e | 3861 | if (adapter->flags & FLAG_HAS_AMT) |
31dbe5b4 | 3862 | e1000e_get_hw_control(adapter); |
97ac8cae | 3863 | |
bc7f75fa AK |
3864 | ew32(WUC, 0); |
3865 | ||
3866 | if (mac->ops.init_hw(hw)) | |
44defeb3 | 3867 | e_err("Hardware Error\n"); |
bc7f75fa AK |
3868 | |
3869 | e1000_update_mng_vlan(adapter); | |
3870 | ||
3871 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
3872 | ew32(VET, ETH_P_8021Q); | |
3873 | ||
3874 | e1000e_reset_adaptive(hw); | |
31dbe5b4 | 3875 | |
b67e1913 BA |
3876 | /* initialize systim and reset the ns time counter */ |
3877 | e1000e_config_hwtstamp(adapter); | |
3878 | ||
d495bcb8 BA |
3879 | /* Set EEE advertisement as appropriate */ |
3880 | if (adapter->flags2 & FLAG2_HAS_EEE) { | |
3881 | s32 ret_val; | |
3882 | u16 adv_addr; | |
3883 | ||
3884 | switch (hw->phy.type) { | |
3885 | case e1000_phy_82579: | |
3886 | adv_addr = I82579_EEE_ADVERTISEMENT; | |
3887 | break; | |
3888 | case e1000_phy_i217: | |
3889 | adv_addr = I217_EEE_ADVERTISEMENT; | |
3890 | break; | |
3891 | default: | |
3892 | dev_err(&adapter->pdev->dev, | |
3893 | "Invalid PHY type setting EEE advertisement\n"); | |
3894 | return; | |
3895 | } | |
3896 | ||
3897 | ret_val = hw->phy.ops.acquire(hw); | |
3898 | if (ret_val) { | |
3899 | dev_err(&adapter->pdev->dev, | |
3900 | "EEE advertisement - unable to acquire PHY\n"); | |
3901 | return; | |
3902 | } | |
3903 | ||
3904 | e1000_write_emi_reg_locked(hw, adv_addr, | |
3905 | hw->dev_spec.ich8lan.eee_disable ? | |
3906 | 0 : adapter->eee_advert); | |
3907 | ||
3908 | hw->phy.ops.release(hw); | |
3909 | } | |
3910 | ||
31dbe5b4 BA |
3911 | if (!netif_running(adapter->netdev) && |
3912 | !test_bit(__E1000_TESTING, &adapter->state)) { | |
3913 | e1000_power_down_phy(adapter); | |
3914 | return; | |
3915 | } | |
3916 | ||
bc7f75fa AK |
3917 | e1000_get_phy_info(hw); |
3918 | ||
918d7197 BA |
3919 | if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && |
3920 | !(adapter->flags & FLAG_SMART_POWER_DOWN)) { | |
bc7f75fa | 3921 | u16 phy_data = 0; |
e921eb1a | 3922 | /* speed up time to link by disabling smart power down, ignore |
bc7f75fa | 3923 | * the return value of this function because there is nothing |
ad68076e BA |
3924 | * different we would do if it failed |
3925 | */ | |
bc7f75fa AK |
3926 | e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
3927 | phy_data &= ~IGP02E1000_PM_SPD; | |
3928 | e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | |
3929 | } | |
bc7f75fa AK |
3930 | } |
3931 | ||
3932 | int e1000e_up(struct e1000_adapter *adapter) | |
3933 | { | |
3934 | struct e1000_hw *hw = &adapter->hw; | |
3935 | ||
3936 | /* hardware has been reset, we need to reload some things */ | |
3937 | e1000_configure(adapter); | |
3938 | ||
3939 | clear_bit(__E1000_DOWN, &adapter->state); | |
3940 | ||
4662e82b BA |
3941 | if (adapter->msix_entries) |
3942 | e1000_configure_msix(adapter); | |
bc7f75fa AK |
3943 | e1000_irq_enable(adapter); |
3944 | ||
400484fa | 3945 | netif_start_queue(adapter->netdev); |
4cb9be7a | 3946 | |
bc7f75fa | 3947 | /* fire a link change interrupt to start the watchdog */ |
52a9b231 BA |
3948 | if (adapter->msix_entries) |
3949 | ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); | |
3950 | else | |
3951 | ew32(ICS, E1000_ICS_LSC); | |
3952 | ||
bc7f75fa AK |
3953 | return 0; |
3954 | } | |
3955 | ||
713b3c9e JB |
3956 | static void e1000e_flush_descriptors(struct e1000_adapter *adapter) |
3957 | { | |
3958 | struct e1000_hw *hw = &adapter->hw; | |
3959 | ||
3960 | if (!(adapter->flags2 & FLAG2_DMA_BURST)) | |
3961 | return; | |
3962 | ||
3963 | /* flush pending descriptor writebacks to memory */ | |
3964 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
3965 | ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); | |
3966 | ||
3967 | /* execute the writes immediately */ | |
3968 | e1e_flush(); | |
bf03085f | 3969 | |
e921eb1a | 3970 | /* due to rare timing issues, write to TIDV/RDTR again to ensure the |
bf03085f MV |
3971 | * write is successful |
3972 | */ | |
3973 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
3974 | ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); | |
713b3c9e JB |
3975 | |
3976 | /* execute the writes immediately */ | |
3977 | e1e_flush(); | |
3978 | } | |
3979 | ||
67fd4fcb JK |
3980 | static void e1000e_update_stats(struct e1000_adapter *adapter); |
3981 | ||
bc7f75fa AK |
3982 | void e1000e_down(struct e1000_adapter *adapter) |
3983 | { | |
3984 | struct net_device *netdev = adapter->netdev; | |
3985 | struct e1000_hw *hw = &adapter->hw; | |
3986 | u32 tctl, rctl; | |
3987 | ||
e921eb1a | 3988 | /* signal that we're down so the interrupt handler does not |
ad68076e BA |
3989 | * reschedule our watchdog timer |
3990 | */ | |
bc7f75fa AK |
3991 | set_bit(__E1000_DOWN, &adapter->state); |
3992 | ||
3993 | /* disable receives in the hardware */ | |
3994 | rctl = er32(RCTL); | |
7f99ae63 BA |
3995 | if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) |
3996 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
bc7f75fa AK |
3997 | /* flush and sleep below */ |
3998 | ||
4cb9be7a | 3999 | netif_stop_queue(netdev); |
bc7f75fa AK |
4000 | |
4001 | /* disable transmits in the hardware */ | |
4002 | tctl = er32(TCTL); | |
4003 | tctl &= ~E1000_TCTL_EN; | |
4004 | ew32(TCTL, tctl); | |
7f99ae63 | 4005 | |
bc7f75fa AK |
4006 | /* flush both disables and wait for them to finish */ |
4007 | e1e_flush(); | |
1bba4386 | 4008 | usleep_range(10000, 20000); |
bc7f75fa | 4009 | |
bc7f75fa AK |
4010 | e1000_irq_disable(adapter); |
4011 | ||
a3b87a4c BA |
4012 | napi_synchronize(&adapter->napi); |
4013 | ||
bc7f75fa AK |
4014 | del_timer_sync(&adapter->watchdog_timer); |
4015 | del_timer_sync(&adapter->phy_info_timer); | |
4016 | ||
bc7f75fa | 4017 | netif_carrier_off(netdev); |
67fd4fcb JK |
4018 | |
4019 | spin_lock(&adapter->stats64_lock); | |
4020 | e1000e_update_stats(adapter); | |
4021 | spin_unlock(&adapter->stats64_lock); | |
4022 | ||
400484fa | 4023 | e1000e_flush_descriptors(adapter); |
55aa6985 BA |
4024 | e1000_clean_tx_ring(adapter->tx_ring); |
4025 | e1000_clean_rx_ring(adapter->rx_ring); | |
400484fa | 4026 | |
bc7f75fa AK |
4027 | adapter->link_speed = 0; |
4028 | adapter->link_duplex = 0; | |
4029 | ||
da1e2046 BA |
4030 | /* Disable Si errata workaround on PCHx for jumbo frame flow */ |
4031 | if ((hw->mac.type >= e1000_pch2lan) && | |
4032 | (adapter->netdev->mtu > ETH_DATA_LEN) && | |
4033 | e1000_lv_jumbo_workaround_ich8lan(hw, false)) | |
4034 | e_dbg("failed to disable jumbo frame workaround mode\n"); | |
4035 | ||
52cc3086 JK |
4036 | if (!pci_channel_offline(adapter->pdev)) |
4037 | e1000e_reset(adapter); | |
713b3c9e | 4038 | |
e921eb1a | 4039 | /* TODO: for power management, we could drop the link and |
bc7f75fa AK |
4040 | * pci_disable_device here. |
4041 | */ | |
4042 | } | |
4043 | ||
4044 | void e1000e_reinit_locked(struct e1000_adapter *adapter) | |
4045 | { | |
4046 | might_sleep(); | |
4047 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) | |
1bba4386 | 4048 | usleep_range(1000, 2000); |
bc7f75fa AK |
4049 | e1000e_down(adapter); |
4050 | e1000e_up(adapter); | |
4051 | clear_bit(__E1000_RESETTING, &adapter->state); | |
4052 | } | |
4053 | ||
b67e1913 BA |
4054 | /** |
4055 | * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) | |
4056 | * @cc: cyclecounter structure | |
4057 | **/ | |
4058 | static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc) | |
4059 | { | |
4060 | struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, | |
4061 | cc); | |
4062 | struct e1000_hw *hw = &adapter->hw; | |
4063 | cycle_t systim; | |
4064 | ||
4065 | /* latch SYSTIMH on read of SYSTIML */ | |
4066 | systim = (cycle_t)er32(SYSTIML); | |
4067 | systim |= (cycle_t)er32(SYSTIMH) << 32; | |
4068 | ||
4069 | return systim; | |
4070 | } | |
4071 | ||
bc7f75fa AK |
4072 | /** |
4073 | * e1000_sw_init - Initialize general software structures (struct e1000_adapter) | |
4074 | * @adapter: board private structure to initialize | |
4075 | * | |
4076 | * e1000_sw_init initializes the Adapter private data structure. | |
4077 | * Fields are initialized based on PCI device information and | |
4078 | * OS network device settings (MTU size). | |
4079 | **/ | |
9f9a12f8 | 4080 | static int e1000_sw_init(struct e1000_adapter *adapter) |
bc7f75fa | 4081 | { |
bc7f75fa AK |
4082 | struct net_device *netdev = adapter->netdev; |
4083 | ||
4084 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN; | |
4085 | adapter->rx_ps_bsize0 = 128; | |
318a94d6 JK |
4086 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
4087 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
55aa6985 BA |
4088 | adapter->tx_ring_count = E1000_DEFAULT_TXD; |
4089 | adapter->rx_ring_count = E1000_DEFAULT_RXD; | |
bc7f75fa | 4090 | |
67fd4fcb JK |
4091 | spin_lock_init(&adapter->stats64_lock); |
4092 | ||
4662e82b | 4093 | e1000e_set_interrupt_capability(adapter); |
bc7f75fa | 4094 | |
4662e82b BA |
4095 | if (e1000_alloc_queues(adapter)) |
4096 | return -ENOMEM; | |
bc7f75fa | 4097 | |
b67e1913 BA |
4098 | /* Setup hardware time stamping cyclecounter */ |
4099 | if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { | |
4100 | adapter->cc.read = e1000e_cyclecounter_read; | |
4101 | adapter->cc.mask = CLOCKSOURCE_MASK(64); | |
4102 | adapter->cc.mult = 1; | |
4103 | /* cc.shift set in e1000e_get_base_tininca() */ | |
4104 | ||
4105 | spin_lock_init(&adapter->systim_lock); | |
4106 | INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); | |
4107 | } | |
4108 | ||
bc7f75fa | 4109 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
bc7f75fa AK |
4110 | e1000_irq_disable(adapter); |
4111 | ||
bc7f75fa AK |
4112 | set_bit(__E1000_DOWN, &adapter->state); |
4113 | return 0; | |
bc7f75fa AK |
4114 | } |
4115 | ||
f8d59f78 BA |
4116 | /** |
4117 | * e1000_intr_msi_test - Interrupt Handler | |
4118 | * @irq: interrupt number | |
4119 | * @data: pointer to a network interface device structure | |
4120 | **/ | |
8bb62869 | 4121 | static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) |
f8d59f78 BA |
4122 | { |
4123 | struct net_device *netdev = data; | |
4124 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
4125 | struct e1000_hw *hw = &adapter->hw; | |
4126 | u32 icr = er32(ICR); | |
4127 | ||
3bb99fe2 | 4128 | e_dbg("icr is %08X\n", icr); |
f8d59f78 BA |
4129 | if (icr & E1000_ICR_RXSEQ) { |
4130 | adapter->flags &= ~FLAG_MSI_TEST_FAILED; | |
e921eb1a | 4131 | /* Force memory writes to complete before acknowledging the |
bc76329d BA |
4132 | * interrupt is handled. |
4133 | */ | |
f8d59f78 BA |
4134 | wmb(); |
4135 | } | |
4136 | ||
4137 | return IRQ_HANDLED; | |
4138 | } | |
4139 | ||
4140 | /** | |
4141 | * e1000_test_msi_interrupt - Returns 0 for successful test | |
4142 | * @adapter: board private struct | |
4143 | * | |
4144 | * code flow taken from tg3.c | |
4145 | **/ | |
4146 | static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) | |
4147 | { | |
4148 | struct net_device *netdev = adapter->netdev; | |
4149 | struct e1000_hw *hw = &adapter->hw; | |
4150 | int err; | |
4151 | ||
4152 | /* poll_enable hasn't been called yet, so don't need disable */ | |
4153 | /* clear any pending events */ | |
4154 | er32(ICR); | |
4155 | ||
4156 | /* free the real vector and request a test handler */ | |
4157 | e1000_free_irq(adapter); | |
4662e82b | 4158 | e1000e_reset_interrupt_capability(adapter); |
f8d59f78 BA |
4159 | |
4160 | /* Assume that the test fails, if it succeeds then the test | |
e921eb1a BA |
4161 | * MSI irq handler will unset this flag |
4162 | */ | |
f8d59f78 BA |
4163 | adapter->flags |= FLAG_MSI_TEST_FAILED; |
4164 | ||
4165 | err = pci_enable_msi(adapter->pdev); | |
4166 | if (err) | |
4167 | goto msi_test_failed; | |
4168 | ||
a0607fd3 | 4169 | err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, |
f8d59f78 BA |
4170 | netdev->name, netdev); |
4171 | if (err) { | |
4172 | pci_disable_msi(adapter->pdev); | |
4173 | goto msi_test_failed; | |
4174 | } | |
4175 | ||
e921eb1a | 4176 | /* Force memory writes to complete before enabling and firing an |
bc76329d BA |
4177 | * interrupt. |
4178 | */ | |
f8d59f78 BA |
4179 | wmb(); |
4180 | ||
4181 | e1000_irq_enable(adapter); | |
4182 | ||
4183 | /* fire an unusual interrupt on the test handler */ | |
4184 | ew32(ICS, E1000_ICS_RXSEQ); | |
4185 | e1e_flush(); | |
569a3aff | 4186 | msleep(100); |
f8d59f78 BA |
4187 | |
4188 | e1000_irq_disable(adapter); | |
4189 | ||
bc76329d | 4190 | rmb(); /* read flags after interrupt has been fired */ |
f8d59f78 BA |
4191 | |
4192 | if (adapter->flags & FLAG_MSI_TEST_FAILED) { | |
4662e82b | 4193 | adapter->int_mode = E1000E_INT_MODE_LEGACY; |
068e8a30 | 4194 | e_info("MSI interrupt test failed, using legacy interrupt.\n"); |
24b706b2 | 4195 | } else { |
068e8a30 | 4196 | e_dbg("MSI interrupt test succeeded!\n"); |
24b706b2 | 4197 | } |
f8d59f78 BA |
4198 | |
4199 | free_irq(adapter->pdev->irq, netdev); | |
4200 | pci_disable_msi(adapter->pdev); | |
4201 | ||
f8d59f78 | 4202 | msi_test_failed: |
4662e82b | 4203 | e1000e_set_interrupt_capability(adapter); |
068e8a30 | 4204 | return e1000_request_irq(adapter); |
f8d59f78 BA |
4205 | } |
4206 | ||
4207 | /** | |
4208 | * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored | |
4209 | * @adapter: board private struct | |
4210 | * | |
4211 | * code flow taken from tg3.c, called with e1000 interrupts disabled. | |
4212 | **/ | |
4213 | static int e1000_test_msi(struct e1000_adapter *adapter) | |
4214 | { | |
4215 | int err; | |
4216 | u16 pci_cmd; | |
4217 | ||
4218 | if (!(adapter->flags & FLAG_MSI_ENABLED)) | |
4219 | return 0; | |
4220 | ||
4221 | /* disable SERR in case the MSI write causes a master abort */ | |
4222 | pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); | |
36f2407f DN |
4223 | if (pci_cmd & PCI_COMMAND_SERR) |
4224 | pci_write_config_word(adapter->pdev, PCI_COMMAND, | |
4225 | pci_cmd & ~PCI_COMMAND_SERR); | |
f8d59f78 BA |
4226 | |
4227 | err = e1000_test_msi_interrupt(adapter); | |
4228 | ||
36f2407f DN |
4229 | /* re-enable SERR */ |
4230 | if (pci_cmd & PCI_COMMAND_SERR) { | |
4231 | pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); | |
4232 | pci_cmd |= PCI_COMMAND_SERR; | |
4233 | pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); | |
4234 | } | |
f8d59f78 | 4235 | |
f8d59f78 BA |
4236 | return err; |
4237 | } | |
4238 | ||
bc7f75fa AK |
4239 | /** |
4240 | * e1000_open - Called when a network interface is made active | |
4241 | * @netdev: network interface device structure | |
4242 | * | |
4243 | * Returns 0 on success, negative value on failure | |
4244 | * | |
4245 | * The open entry point is called when a network interface is made | |
4246 | * active by the system (IFF_UP). At this point all resources needed | |
4247 | * for transmit and receive operations are allocated, the interrupt | |
4248 | * handler is registered with the OS, the watchdog timer is started, | |
4249 | * and the stack is notified that the interface is ready. | |
4250 | **/ | |
4251 | static int e1000_open(struct net_device *netdev) | |
4252 | { | |
4253 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
4254 | struct e1000_hw *hw = &adapter->hw; | |
23606cf5 | 4255 | struct pci_dev *pdev = adapter->pdev; |
bc7f75fa AK |
4256 | int err; |
4257 | ||
4258 | /* disallow open during test */ | |
4259 | if (test_bit(__E1000_TESTING, &adapter->state)) | |
4260 | return -EBUSY; | |
4261 | ||
23606cf5 RW |
4262 | pm_runtime_get_sync(&pdev->dev); |
4263 | ||
9c563d20 JB |
4264 | netif_carrier_off(netdev); |
4265 | ||
bc7f75fa | 4266 | /* allocate transmit descriptors */ |
55aa6985 | 4267 | err = e1000e_setup_tx_resources(adapter->tx_ring); |
bc7f75fa AK |
4268 | if (err) |
4269 | goto err_setup_tx; | |
4270 | ||
4271 | /* allocate receive descriptors */ | |
55aa6985 | 4272 | err = e1000e_setup_rx_resources(adapter->rx_ring); |
bc7f75fa AK |
4273 | if (err) |
4274 | goto err_setup_rx; | |
4275 | ||
e921eb1a | 4276 | /* If AMT is enabled, let the firmware know that the network |
11b08be8 BA |
4277 | * interface is now open and reset the part to a known state. |
4278 | */ | |
4279 | if (adapter->flags & FLAG_HAS_AMT) { | |
31dbe5b4 | 4280 | e1000e_get_hw_control(adapter); |
11b08be8 BA |
4281 | e1000e_reset(adapter); |
4282 | } | |
4283 | ||
bc7f75fa AK |
4284 | e1000e_power_up_phy(adapter); |
4285 | ||
4286 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; | |
e5fe2541 | 4287 | if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) |
bc7f75fa AK |
4288 | e1000_update_mng_vlan(adapter); |
4289 | ||
79d4e908 | 4290 | /* DMA latency requirement to workaround jumbo issue */ |
3e35d991 BA |
4291 | pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, |
4292 | PM_QOS_DEFAULT_VALUE); | |
c128ec29 | 4293 | |
e921eb1a | 4294 | /* before we allocate an interrupt, we must be ready to handle it. |
bc7f75fa AK |
4295 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt |
4296 | * as soon as we call pci_request_irq, so we have to setup our | |
ad68076e BA |
4297 | * clean_rx handler before we do so. |
4298 | */ | |
bc7f75fa AK |
4299 | e1000_configure(adapter); |
4300 | ||
4301 | err = e1000_request_irq(adapter); | |
4302 | if (err) | |
4303 | goto err_req_irq; | |
4304 | ||
e921eb1a | 4305 | /* Work around PCIe errata with MSI interrupts causing some chipsets to |
f8d59f78 BA |
4306 | * ignore e1000e MSI messages, which means we need to test our MSI |
4307 | * interrupt now | |
4308 | */ | |
4662e82b | 4309 | if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { |
f8d59f78 BA |
4310 | err = e1000_test_msi(adapter); |
4311 | if (err) { | |
4312 | e_err("Interrupt allocation failed\n"); | |
4313 | goto err_req_irq; | |
4314 | } | |
4315 | } | |
4316 | ||
bc7f75fa AK |
4317 | /* From here on the code is the same as e1000e_up() */ |
4318 | clear_bit(__E1000_DOWN, &adapter->state); | |
4319 | ||
4320 | napi_enable(&adapter->napi); | |
4321 | ||
4322 | e1000_irq_enable(adapter); | |
4323 | ||
09357b00 | 4324 | adapter->tx_hang_recheck = false; |
4cb9be7a | 4325 | netif_start_queue(netdev); |
d55b53ff | 4326 | |
23606cf5 | 4327 | adapter->idle_check = true; |
66148bab | 4328 | hw->mac.get_link_status = true; |
23606cf5 RW |
4329 | pm_runtime_put(&pdev->dev); |
4330 | ||
bc7f75fa | 4331 | /* fire a link status change interrupt to start the watchdog */ |
52a9b231 BA |
4332 | if (adapter->msix_entries) |
4333 | ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); | |
4334 | else | |
4335 | ew32(ICS, E1000_ICS_LSC); | |
bc7f75fa AK |
4336 | |
4337 | return 0; | |
4338 | ||
4339 | err_req_irq: | |
31dbe5b4 | 4340 | e1000e_release_hw_control(adapter); |
bc7f75fa | 4341 | e1000_power_down_phy(adapter); |
55aa6985 | 4342 | e1000e_free_rx_resources(adapter->rx_ring); |
bc7f75fa | 4343 | err_setup_rx: |
55aa6985 | 4344 | e1000e_free_tx_resources(adapter->tx_ring); |
bc7f75fa AK |
4345 | err_setup_tx: |
4346 | e1000e_reset(adapter); | |
23606cf5 | 4347 | pm_runtime_put_sync(&pdev->dev); |
bc7f75fa AK |
4348 | |
4349 | return err; | |
4350 | } | |
4351 | ||
4352 | /** | |
4353 | * e1000_close - Disables a network interface | |
4354 | * @netdev: network interface device structure | |
4355 | * | |
4356 | * Returns 0, this is not allowed to fail | |
4357 | * | |
4358 | * The close entry point is called when an interface is de-activated | |
4359 | * by the OS. The hardware is still under the drivers control, but | |
4360 | * needs to be disabled. A global MAC reset is issued to stop the | |
4361 | * hardware, and all transmit and receive resources are freed. | |
4362 | **/ | |
4363 | static int e1000_close(struct net_device *netdev) | |
4364 | { | |
4365 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
23606cf5 | 4366 | struct pci_dev *pdev = adapter->pdev; |
bb9e44d0 BA |
4367 | int count = E1000_CHECK_RESET_COUNT; |
4368 | ||
4369 | while (test_bit(__E1000_RESETTING, &adapter->state) && count--) | |
4370 | usleep_range(10000, 20000); | |
bc7f75fa AK |
4371 | |
4372 | WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); | |
23606cf5 RW |
4373 | |
4374 | pm_runtime_get_sync(&pdev->dev); | |
4375 | ||
4376 | if (!test_bit(__E1000_DOWN, &adapter->state)) { | |
4377 | e1000e_down(adapter); | |
4378 | e1000_free_irq(adapter); | |
4379 | } | |
a3b87a4c BA |
4380 | |
4381 | napi_disable(&adapter->napi); | |
4382 | ||
bc7f75fa | 4383 | e1000_power_down_phy(adapter); |
bc7f75fa | 4384 | |
55aa6985 BA |
4385 | e1000e_free_tx_resources(adapter->tx_ring); |
4386 | e1000e_free_rx_resources(adapter->rx_ring); | |
bc7f75fa | 4387 | |
e921eb1a | 4388 | /* kill manageability vlan ID if supported, but not if a vlan with |
ad68076e BA |
4389 | * the same ID is registered on the host OS (let 8021q kill it) |
4390 | */ | |
e5fe2541 | 4391 | if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) |
80d5c368 PM |
4392 | e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), |
4393 | adapter->mng_vlan_id); | |
bc7f75fa | 4394 | |
e921eb1a | 4395 | /* If AMT is enabled, let the firmware know that the network |
ad68076e BA |
4396 | * interface is now closed |
4397 | */ | |
31dbe5b4 BA |
4398 | if ((adapter->flags & FLAG_HAS_AMT) && |
4399 | !test_bit(__E1000_TESTING, &adapter->state)) | |
4400 | e1000e_release_hw_control(adapter); | |
bc7f75fa | 4401 | |
3e35d991 | 4402 | pm_qos_remove_request(&adapter->netdev->pm_qos_req); |
c128ec29 | 4403 | |
23606cf5 RW |
4404 | pm_runtime_put_sync(&pdev->dev); |
4405 | ||
bc7f75fa AK |
4406 | return 0; |
4407 | } | |
fc830b78 | 4408 | |
bc7f75fa AK |
4409 | /** |
4410 | * e1000_set_mac - Change the Ethernet Address of the NIC | |
4411 | * @netdev: network interface device structure | |
4412 | * @p: pointer to an address structure | |
4413 | * | |
4414 | * Returns 0 on success, negative on failure | |
4415 | **/ | |
4416 | static int e1000_set_mac(struct net_device *netdev, void *p) | |
4417 | { | |
4418 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
69e1e019 | 4419 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa AK |
4420 | struct sockaddr *addr = p; |
4421 | ||
4422 | if (!is_valid_ether_addr(addr->sa_data)) | |
4423 | return -EADDRNOTAVAIL; | |
4424 | ||
4425 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
4426 | memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); | |
4427 | ||
69e1e019 | 4428 | hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); |
bc7f75fa AK |
4429 | |
4430 | if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { | |
4431 | /* activate the work around */ | |
4432 | e1000e_set_laa_state_82571(&adapter->hw, 1); | |
4433 | ||
e921eb1a | 4434 | /* Hold a copy of the LAA in RAR[14] This is done so that |
bc7f75fa AK |
4435 | * between the time RAR[0] gets clobbered and the time it |
4436 | * gets fixed (in e1000_watchdog), the actual LAA is in one | |
4437 | * of the RARs and no incoming packets directed to this port | |
4438 | * are dropped. Eventually the LAA will be in RAR[0] and | |
ad68076e BA |
4439 | * RAR[14] |
4440 | */ | |
69e1e019 BA |
4441 | hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, |
4442 | adapter->hw.mac.rar_entry_count - 1); | |
bc7f75fa AK |
4443 | } |
4444 | ||
4445 | return 0; | |
4446 | } | |
4447 | ||
a8f88ff5 JB |
4448 | /** |
4449 | * e1000e_update_phy_task - work thread to update phy | |
4450 | * @work: pointer to our work struct | |
4451 | * | |
4452 | * this worker thread exists because we must acquire a | |
4453 | * semaphore to read the phy, which we could msleep while | |
4454 | * waiting for it, and we can't msleep in a timer. | |
4455 | **/ | |
4456 | static void e1000e_update_phy_task(struct work_struct *work) | |
4457 | { | |
4458 | struct e1000_adapter *adapter = container_of(work, | |
17e813ec BA |
4459 | struct e1000_adapter, |
4460 | update_phy_task); | |
615b32af JB |
4461 | |
4462 | if (test_bit(__E1000_DOWN, &adapter->state)) | |
4463 | return; | |
4464 | ||
a8f88ff5 JB |
4465 | e1000_get_phy_info(&adapter->hw); |
4466 | } | |
4467 | ||
e921eb1a BA |
4468 | /** |
4469 | * e1000_update_phy_info - timre call-back to update PHY info | |
4470 | * @data: pointer to adapter cast into an unsigned long | |
4471 | * | |
ad68076e BA |
4472 | * Need to wait a few seconds after link up to get diagnostic information from |
4473 | * the phy | |
e921eb1a | 4474 | **/ |
bc7f75fa AK |
4475 | static void e1000_update_phy_info(unsigned long data) |
4476 | { | |
53aa82da | 4477 | struct e1000_adapter *adapter = (struct e1000_adapter *)data; |
615b32af JB |
4478 | |
4479 | if (test_bit(__E1000_DOWN, &adapter->state)) | |
4480 | return; | |
4481 | ||
a8f88ff5 | 4482 | schedule_work(&adapter->update_phy_task); |
bc7f75fa AK |
4483 | } |
4484 | ||
8c7bbb92 BA |
4485 | /** |
4486 | * e1000e_update_phy_stats - Update the PHY statistics counters | |
4487 | * @adapter: board private structure | |
2b6b168d BA |
4488 | * |
4489 | * Read/clear the upper 16-bit PHY registers and read/accumulate lower | |
8c7bbb92 BA |
4490 | **/ |
4491 | static void e1000e_update_phy_stats(struct e1000_adapter *adapter) | |
4492 | { | |
4493 | struct e1000_hw *hw = &adapter->hw; | |
4494 | s32 ret_val; | |
4495 | u16 phy_data; | |
4496 | ||
4497 | ret_val = hw->phy.ops.acquire(hw); | |
4498 | if (ret_val) | |
4499 | return; | |
4500 | ||
e921eb1a | 4501 | /* A page set is expensive so check if already on desired page. |
8c7bbb92 BA |
4502 | * If not, set to the page with the PHY status registers. |
4503 | */ | |
2b6b168d | 4504 | hw->phy.addr = 1; |
8c7bbb92 BA |
4505 | ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, |
4506 | &phy_data); | |
4507 | if (ret_val) | |
4508 | goto release; | |
2b6b168d BA |
4509 | if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { |
4510 | ret_val = hw->phy.ops.set_page(hw, | |
4511 | HV_STATS_PAGE << IGP_PAGE_SHIFT); | |
8c7bbb92 BA |
4512 | if (ret_val) |
4513 | goto release; | |
4514 | } | |
4515 | ||
8c7bbb92 | 4516 | /* Single Collision Count */ |
2b6b168d BA |
4517 | hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); |
4518 | ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); | |
8c7bbb92 BA |
4519 | if (!ret_val) |
4520 | adapter->stats.scc += phy_data; | |
4521 | ||
4522 | /* Excessive Collision Count */ | |
2b6b168d BA |
4523 | hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); |
4524 | ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); | |
8c7bbb92 BA |
4525 | if (!ret_val) |
4526 | adapter->stats.ecol += phy_data; | |
4527 | ||
4528 | /* Multiple Collision Count */ | |
2b6b168d BA |
4529 | hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); |
4530 | ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); | |
8c7bbb92 BA |
4531 | if (!ret_val) |
4532 | adapter->stats.mcc += phy_data; | |
4533 | ||
4534 | /* Late Collision Count */ | |
2b6b168d BA |
4535 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); |
4536 | ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); | |
8c7bbb92 BA |
4537 | if (!ret_val) |
4538 | adapter->stats.latecol += phy_data; | |
4539 | ||
4540 | /* Collision Count - also used for adaptive IFS */ | |
2b6b168d BA |
4541 | hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); |
4542 | ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); | |
8c7bbb92 BA |
4543 | if (!ret_val) |
4544 | hw->mac.collision_delta = phy_data; | |
4545 | ||
4546 | /* Defer Count */ | |
2b6b168d BA |
4547 | hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); |
4548 | ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); | |
8c7bbb92 BA |
4549 | if (!ret_val) |
4550 | adapter->stats.dc += phy_data; | |
4551 | ||
4552 | /* Transmit with no CRS */ | |
2b6b168d BA |
4553 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); |
4554 | ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); | |
8c7bbb92 BA |
4555 | if (!ret_val) |
4556 | adapter->stats.tncrs += phy_data; | |
4557 | ||
4558 | release: | |
4559 | hw->phy.ops.release(hw); | |
4560 | } | |
4561 | ||
bc7f75fa AK |
4562 | /** |
4563 | * e1000e_update_stats - Update the board statistics counters | |
4564 | * @adapter: board private structure | |
4565 | **/ | |
67fd4fcb | 4566 | static void e1000e_update_stats(struct e1000_adapter *adapter) |
bc7f75fa | 4567 | { |
7274c20f | 4568 | struct net_device *netdev = adapter->netdev; |
bc7f75fa AK |
4569 | struct e1000_hw *hw = &adapter->hw; |
4570 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa | 4571 | |
e921eb1a | 4572 | /* Prevent stats update while adapter is being reset, or if the pci |
bc7f75fa AK |
4573 | * connection is down. |
4574 | */ | |
4575 | if (adapter->link_speed == 0) | |
4576 | return; | |
4577 | if (pci_channel_offline(pdev)) | |
4578 | return; | |
4579 | ||
bc7f75fa AK |
4580 | adapter->stats.crcerrs += er32(CRCERRS); |
4581 | adapter->stats.gprc += er32(GPRC); | |
7c25769f | 4582 | adapter->stats.gorc += er32(GORCL); |
e80bd1d1 | 4583 | er32(GORCH); /* Clear gorc */ |
bc7f75fa AK |
4584 | adapter->stats.bprc += er32(BPRC); |
4585 | adapter->stats.mprc += er32(MPRC); | |
4586 | adapter->stats.roc += er32(ROC); | |
4587 | ||
bc7f75fa | 4588 | adapter->stats.mpc += er32(MPC); |
8c7bbb92 BA |
4589 | |
4590 | /* Half-duplex statistics */ | |
4591 | if (adapter->link_duplex == HALF_DUPLEX) { | |
4592 | if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { | |
4593 | e1000e_update_phy_stats(adapter); | |
4594 | } else { | |
4595 | adapter->stats.scc += er32(SCC); | |
4596 | adapter->stats.ecol += er32(ECOL); | |
4597 | adapter->stats.mcc += er32(MCC); | |
4598 | adapter->stats.latecol += er32(LATECOL); | |
4599 | adapter->stats.dc += er32(DC); | |
4600 | ||
4601 | hw->mac.collision_delta = er32(COLC); | |
4602 | ||
4603 | if ((hw->mac.type != e1000_82574) && | |
4604 | (hw->mac.type != e1000_82583)) | |
4605 | adapter->stats.tncrs += er32(TNCRS); | |
4606 | } | |
4607 | adapter->stats.colc += hw->mac.collision_delta; | |
a4f58f54 | 4608 | } |
8c7bbb92 | 4609 | |
bc7f75fa AK |
4610 | adapter->stats.xonrxc += er32(XONRXC); |
4611 | adapter->stats.xontxc += er32(XONTXC); | |
4612 | adapter->stats.xoffrxc += er32(XOFFRXC); | |
4613 | adapter->stats.xofftxc += er32(XOFFTXC); | |
bc7f75fa | 4614 | adapter->stats.gptc += er32(GPTC); |
7c25769f | 4615 | adapter->stats.gotc += er32(GOTCL); |
e80bd1d1 | 4616 | er32(GOTCH); /* Clear gotc */ |
bc7f75fa AK |
4617 | adapter->stats.rnbc += er32(RNBC); |
4618 | adapter->stats.ruc += er32(RUC); | |
bc7f75fa AK |
4619 | |
4620 | adapter->stats.mptc += er32(MPTC); | |
4621 | adapter->stats.bptc += er32(BPTC); | |
4622 | ||
4623 | /* used for adaptive IFS */ | |
4624 | ||
4625 | hw->mac.tx_packet_delta = er32(TPT); | |
4626 | adapter->stats.tpt += hw->mac.tx_packet_delta; | |
bc7f75fa AK |
4627 | |
4628 | adapter->stats.algnerrc += er32(ALGNERRC); | |
4629 | adapter->stats.rxerrc += er32(RXERRC); | |
bc7f75fa AK |
4630 | adapter->stats.cexterr += er32(CEXTERR); |
4631 | adapter->stats.tsctc += er32(TSCTC); | |
4632 | adapter->stats.tsctfc += er32(TSCTFC); | |
4633 | ||
bc7f75fa | 4634 | /* Fill out the OS statistics structure */ |
7274c20f AK |
4635 | netdev->stats.multicast = adapter->stats.mprc; |
4636 | netdev->stats.collisions = adapter->stats.colc; | |
bc7f75fa AK |
4637 | |
4638 | /* Rx Errors */ | |
4639 | ||
e921eb1a | 4640 | /* RLEC on some newer hardware can be incorrect so build |
ad68076e BA |
4641 | * our own version based on RUC and ROC |
4642 | */ | |
7274c20f | 4643 | netdev->stats.rx_errors = adapter->stats.rxerrc + |
f0ff4398 BA |
4644 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
4645 | adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; | |
7274c20f | 4646 | netdev->stats.rx_length_errors = adapter->stats.ruc + |
f0ff4398 | 4647 | adapter->stats.roc; |
7274c20f AK |
4648 | netdev->stats.rx_crc_errors = adapter->stats.crcerrs; |
4649 | netdev->stats.rx_frame_errors = adapter->stats.algnerrc; | |
4650 | netdev->stats.rx_missed_errors = adapter->stats.mpc; | |
bc7f75fa AK |
4651 | |
4652 | /* Tx Errors */ | |
f0ff4398 | 4653 | netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; |
7274c20f AK |
4654 | netdev->stats.tx_aborted_errors = adapter->stats.ecol; |
4655 | netdev->stats.tx_window_errors = adapter->stats.latecol; | |
4656 | netdev->stats.tx_carrier_errors = adapter->stats.tncrs; | |
bc7f75fa AK |
4657 | |
4658 | /* Tx Dropped needs to be maintained elsewhere */ | |
4659 | ||
bc7f75fa AK |
4660 | /* Management Stats */ |
4661 | adapter->stats.mgptc += er32(MGTPTC); | |
4662 | adapter->stats.mgprc += er32(MGTPRC); | |
4663 | adapter->stats.mgpdc += er32(MGTPDC); | |
94fb848b BA |
4664 | |
4665 | /* Correctable ECC Errors */ | |
4666 | if (hw->mac.type == e1000_pch_lpt) { | |
4667 | u32 pbeccsts = er32(PBECCSTS); | |
4668 | adapter->corr_errors += | |
4669 | pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; | |
4670 | adapter->uncorr_errors += | |
4671 | (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> | |
4672 | E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; | |
4673 | } | |
bc7f75fa AK |
4674 | } |
4675 | ||
7c25769f BA |
4676 | /** |
4677 | * e1000_phy_read_status - Update the PHY register status snapshot | |
4678 | * @adapter: board private structure | |
4679 | **/ | |
4680 | static void e1000_phy_read_status(struct e1000_adapter *adapter) | |
4681 | { | |
4682 | struct e1000_hw *hw = &adapter->hw; | |
4683 | struct e1000_phy_regs *phy = &adapter->phy_regs; | |
7c25769f | 4684 | |
97390ab8 BA |
4685 | if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && |
4686 | (er32(STATUS) & E1000_STATUS_LU) && | |
7c25769f | 4687 | (adapter->hw.phy.media_type == e1000_media_type_copper)) { |
90da0669 BA |
4688 | int ret_val; |
4689 | ||
c2ade1a4 BA |
4690 | ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); |
4691 | ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); | |
4692 | ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); | |
4693 | ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); | |
4694 | ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); | |
4695 | ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); | |
4696 | ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); | |
4697 | ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); | |
7c25769f | 4698 | if (ret_val) |
44defeb3 | 4699 | e_warn("Error reading PHY register\n"); |
7c25769f | 4700 | } else { |
e921eb1a | 4701 | /* Do not read PHY registers if link is not up |
7c25769f BA |
4702 | * Set values to typical power-on defaults |
4703 | */ | |
4704 | phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); | |
4705 | phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | | |
4706 | BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | | |
4707 | BMSR_ERCAP); | |
4708 | phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | | |
4709 | ADVERTISE_ALL | ADVERTISE_CSMA); | |
4710 | phy->lpa = 0; | |
4711 | phy->expansion = EXPANSION_ENABLENPAGE; | |
4712 | phy->ctrl1000 = ADVERTISE_1000FULL; | |
4713 | phy->stat1000 = 0; | |
4714 | phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); | |
4715 | } | |
7c25769f BA |
4716 | } |
4717 | ||
bc7f75fa AK |
4718 | static void e1000_print_link_info(struct e1000_adapter *adapter) |
4719 | { | |
bc7f75fa AK |
4720 | struct e1000_hw *hw = &adapter->hw; |
4721 | u32 ctrl = er32(CTRL); | |
4722 | ||
8f12fe86 | 4723 | /* Link status message must follow this format for user tools */ |
7dbc1672 BA |
4724 | pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", |
4725 | adapter->netdev->name, adapter->link_speed, | |
ef456f85 JK |
4726 | adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", |
4727 | (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : | |
4728 | (ctrl & E1000_CTRL_RFCE) ? "Rx" : | |
4729 | (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); | |
bc7f75fa AK |
4730 | } |
4731 | ||
0c6bdb30 | 4732 | static bool e1000e_has_link(struct e1000_adapter *adapter) |
318a94d6 JK |
4733 | { |
4734 | struct e1000_hw *hw = &adapter->hw; | |
3db1cd5c | 4735 | bool link_active = false; |
318a94d6 JK |
4736 | s32 ret_val = 0; |
4737 | ||
e921eb1a | 4738 | /* get_link_status is set on LSC (link status) interrupt or |
318a94d6 JK |
4739 | * Rx sequence error interrupt. get_link_status will stay |
4740 | * false until the check_for_link establishes link | |
4741 | * for copper adapters ONLY | |
4742 | */ | |
4743 | switch (hw->phy.media_type) { | |
4744 | case e1000_media_type_copper: | |
4745 | if (hw->mac.get_link_status) { | |
4746 | ret_val = hw->mac.ops.check_for_link(hw); | |
4747 | link_active = !hw->mac.get_link_status; | |
4748 | } else { | |
3db1cd5c | 4749 | link_active = true; |
318a94d6 JK |
4750 | } |
4751 | break; | |
4752 | case e1000_media_type_fiber: | |
4753 | ret_val = hw->mac.ops.check_for_link(hw); | |
4754 | link_active = !!(er32(STATUS) & E1000_STATUS_LU); | |
4755 | break; | |
4756 | case e1000_media_type_internal_serdes: | |
4757 | ret_val = hw->mac.ops.check_for_link(hw); | |
4758 | link_active = adapter->hw.mac.serdes_has_link; | |
4759 | break; | |
4760 | default: | |
4761 | case e1000_media_type_unknown: | |
4762 | break; | |
4763 | } | |
4764 | ||
4765 | if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && | |
4766 | (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { | |
4767 | /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ | |
44defeb3 | 4768 | e_info("Gigabit has been disabled, downgrading speed\n"); |
318a94d6 JK |
4769 | } |
4770 | ||
4771 | return link_active; | |
4772 | } | |
4773 | ||
4774 | static void e1000e_enable_receives(struct e1000_adapter *adapter) | |
4775 | { | |
4776 | /* make sure the receive unit is started */ | |
4777 | if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && | |
12d43f7d | 4778 | (adapter->flags & FLAG_RESTART_NOW)) { |
318a94d6 JK |
4779 | struct e1000_hw *hw = &adapter->hw; |
4780 | u32 rctl = er32(RCTL); | |
4781 | ew32(RCTL, rctl | E1000_RCTL_EN); | |
12d43f7d | 4782 | adapter->flags &= ~FLAG_RESTART_NOW; |
318a94d6 JK |
4783 | } |
4784 | } | |
4785 | ||
ff10e13c CW |
4786 | static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) |
4787 | { | |
4788 | struct e1000_hw *hw = &adapter->hw; | |
4789 | ||
e921eb1a | 4790 | /* With 82574 controllers, PHY needs to be checked periodically |
ff10e13c CW |
4791 | * for hung state and reset, if two calls return true |
4792 | */ | |
4793 | if (e1000_check_phy_82574(hw)) | |
4794 | adapter->phy_hang_count++; | |
4795 | else | |
4796 | adapter->phy_hang_count = 0; | |
4797 | ||
4798 | if (adapter->phy_hang_count > 1) { | |
4799 | adapter->phy_hang_count = 0; | |
4800 | schedule_work(&adapter->reset_task); | |
4801 | } | |
4802 | } | |
4803 | ||
bc7f75fa AK |
4804 | /** |
4805 | * e1000_watchdog - Timer Call-back | |
4806 | * @data: pointer to adapter cast into an unsigned long | |
4807 | **/ | |
4808 | static void e1000_watchdog(unsigned long data) | |
4809 | { | |
53aa82da | 4810 | struct e1000_adapter *adapter = (struct e1000_adapter *)data; |
bc7f75fa AK |
4811 | |
4812 | /* Do the rest outside of interrupt context */ | |
4813 | schedule_work(&adapter->watchdog_task); | |
4814 | ||
4815 | /* TODO: make this use queue_delayed_work() */ | |
4816 | } | |
4817 | ||
4818 | static void e1000_watchdog_task(struct work_struct *work) | |
4819 | { | |
4820 | struct e1000_adapter *adapter = container_of(work, | |
17e813ec BA |
4821 | struct e1000_adapter, |
4822 | watchdog_task); | |
bc7f75fa AK |
4823 | struct net_device *netdev = adapter->netdev; |
4824 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
75eb0fad | 4825 | struct e1000_phy_info *phy = &adapter->hw.phy; |
bc7f75fa AK |
4826 | struct e1000_ring *tx_ring = adapter->tx_ring; |
4827 | struct e1000_hw *hw = &adapter->hw; | |
4828 | u32 link, tctl; | |
bc7f75fa | 4829 | |
615b32af JB |
4830 | if (test_bit(__E1000_DOWN, &adapter->state)) |
4831 | return; | |
4832 | ||
b405e8df | 4833 | link = e1000e_has_link(adapter); |
318a94d6 | 4834 | if ((netif_carrier_ok(netdev)) && link) { |
23606cf5 RW |
4835 | /* Cancel scheduled suspend requests. */ |
4836 | pm_runtime_resume(netdev->dev.parent); | |
4837 | ||
318a94d6 | 4838 | e1000e_enable_receives(adapter); |
bc7f75fa | 4839 | goto link_up; |
bc7f75fa AK |
4840 | } |
4841 | ||
4842 | if ((e1000e_enable_tx_pkt_filtering(hw)) && | |
4843 | (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) | |
4844 | e1000_update_mng_vlan(adapter); | |
4845 | ||
bc7f75fa AK |
4846 | if (link) { |
4847 | if (!netif_carrier_ok(netdev)) { | |
3db1cd5c | 4848 | bool txb2b = true; |
23606cf5 RW |
4849 | |
4850 | /* Cancel scheduled suspend requests. */ | |
4851 | pm_runtime_resume(netdev->dev.parent); | |
4852 | ||
318a94d6 | 4853 | /* update snapshot of PHY registers on LSC */ |
7c25769f | 4854 | e1000_phy_read_status(adapter); |
bc7f75fa | 4855 | mac->ops.get_link_up_info(&adapter->hw, |
17e813ec BA |
4856 | &adapter->link_speed, |
4857 | &adapter->link_duplex); | |
bc7f75fa | 4858 | e1000_print_link_info(adapter); |
e792cd91 KS |
4859 | |
4860 | /* check if SmartSpeed worked */ | |
4861 | e1000e_check_downshift(hw); | |
4862 | if (phy->speed_downgraded) | |
4863 | netdev_warn(netdev, | |
4864 | "Link Speed was downgraded by SmartSpeed\n"); | |
4865 | ||
e921eb1a | 4866 | /* On supported PHYs, check for duplex mismatch only |
f4187b56 BA |
4867 | * if link has autonegotiated at 10/100 half |
4868 | */ | |
4869 | if ((hw->phy.type == e1000_phy_igp_3 || | |
4870 | hw->phy.type == e1000_phy_bm) && | |
138953bb | 4871 | hw->mac.autoneg && |
f4187b56 BA |
4872 | (adapter->link_speed == SPEED_10 || |
4873 | adapter->link_speed == SPEED_100) && | |
4874 | (adapter->link_duplex == HALF_DUPLEX)) { | |
4875 | u16 autoneg_exp; | |
4876 | ||
c2ade1a4 | 4877 | e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); |
f4187b56 | 4878 | |
c2ade1a4 | 4879 | if (!(autoneg_exp & EXPANSION_NWAY)) |
ef456f85 | 4880 | e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); |
f4187b56 BA |
4881 | } |
4882 | ||
f49c57e1 | 4883 | /* adjust timeout factor according to speed/duplex */ |
bc7f75fa AK |
4884 | adapter->tx_timeout_factor = 1; |
4885 | switch (adapter->link_speed) { | |
4886 | case SPEED_10: | |
3db1cd5c | 4887 | txb2b = false; |
10f1b492 | 4888 | adapter->tx_timeout_factor = 16; |
bc7f75fa AK |
4889 | break; |
4890 | case SPEED_100: | |
3db1cd5c | 4891 | txb2b = false; |
4c86e0b9 | 4892 | adapter->tx_timeout_factor = 10; |
bc7f75fa AK |
4893 | break; |
4894 | } | |
4895 | ||
e921eb1a | 4896 | /* workaround: re-program speed mode bit after |
ad68076e BA |
4897 | * link-up event |
4898 | */ | |
bc7f75fa AK |
4899 | if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && |
4900 | !txb2b) { | |
4901 | u32 tarc0; | |
e9ec2c0f | 4902 | tarc0 = er32(TARC(0)); |
bc7f75fa | 4903 | tarc0 &= ~SPEED_MODE_BIT; |
e9ec2c0f | 4904 | ew32(TARC(0), tarc0); |
bc7f75fa AK |
4905 | } |
4906 | ||
e921eb1a | 4907 | /* disable TSO for pcie and 10/100 speeds, to avoid |
ad68076e BA |
4908 | * some hardware issues |
4909 | */ | |
bc7f75fa AK |
4910 | if (!(adapter->flags & FLAG_TSO_FORCE)) { |
4911 | switch (adapter->link_speed) { | |
4912 | case SPEED_10: | |
4913 | case SPEED_100: | |
44defeb3 | 4914 | e_info("10/100 speed: disabling TSO\n"); |
bc7f75fa AK |
4915 | netdev->features &= ~NETIF_F_TSO; |
4916 | netdev->features &= ~NETIF_F_TSO6; | |
4917 | break; | |
4918 | case SPEED_1000: | |
4919 | netdev->features |= NETIF_F_TSO; | |
4920 | netdev->features |= NETIF_F_TSO6; | |
4921 | break; | |
4922 | default: | |
4923 | /* oops */ | |
4924 | break; | |
4925 | } | |
4926 | } | |
4927 | ||
e921eb1a | 4928 | /* enable transmits in the hardware, need to do this |
ad68076e BA |
4929 | * after setting TARC(0) |
4930 | */ | |
bc7f75fa AK |
4931 | tctl = er32(TCTL); |
4932 | tctl |= E1000_TCTL_EN; | |
4933 | ew32(TCTL, tctl); | |
4934 | ||
e921eb1a | 4935 | /* Perform any post-link-up configuration before |
75eb0fad BA |
4936 | * reporting link up. |
4937 | */ | |
4938 | if (phy->ops.cfg_on_link_up) | |
4939 | phy->ops.cfg_on_link_up(hw); | |
4940 | ||
bc7f75fa | 4941 | netif_carrier_on(netdev); |
bc7f75fa AK |
4942 | |
4943 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
4944 | mod_timer(&adapter->phy_info_timer, | |
4945 | round_jiffies(jiffies + 2 * HZ)); | |
bc7f75fa AK |
4946 | } |
4947 | } else { | |
4948 | if (netif_carrier_ok(netdev)) { | |
4949 | adapter->link_speed = 0; | |
4950 | adapter->link_duplex = 0; | |
8f12fe86 | 4951 | /* Link status message must follow this format */ |
7dbc1672 | 4952 | pr_info("%s NIC Link is Down\n", adapter->netdev->name); |
bc7f75fa | 4953 | netif_carrier_off(netdev); |
bc7f75fa AK |
4954 | if (!test_bit(__E1000_DOWN, &adapter->state)) |
4955 | mod_timer(&adapter->phy_info_timer, | |
4956 | round_jiffies(jiffies + 2 * HZ)); | |
4957 | ||
12d43f7d BA |
4958 | /* The link is lost so the controller stops DMA. |
4959 | * If there is queued Tx work that cannot be done | |
4960 | * or if on an 8000ES2LAN which requires a Rx packet | |
4961 | * buffer work-around on link down event, reset the | |
4962 | * controller to flush the Tx/Rx packet buffers. | |
4963 | * (Do the reset outside of interrupt context). | |
4964 | */ | |
4965 | if ((adapter->flags & FLAG_RX_NEEDS_RESTART) || | |
4966 | (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) | |
4967 | adapter->flags |= FLAG_RESTART_NOW; | |
23606cf5 RW |
4968 | else |
4969 | pm_schedule_suspend(netdev->dev.parent, | |
17e813ec | 4970 | LINK_TIMEOUT); |
bc7f75fa AK |
4971 | } |
4972 | } | |
4973 | ||
4974 | link_up: | |
67fd4fcb | 4975 | spin_lock(&adapter->stats64_lock); |
bc7f75fa AK |
4976 | e1000e_update_stats(adapter); |
4977 | ||
4978 | mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; | |
4979 | adapter->tpt_old = adapter->stats.tpt; | |
4980 | mac->collision_delta = adapter->stats.colc - adapter->colc_old; | |
4981 | adapter->colc_old = adapter->stats.colc; | |
4982 | ||
7c25769f BA |
4983 | adapter->gorc = adapter->stats.gorc - adapter->gorc_old; |
4984 | adapter->gorc_old = adapter->stats.gorc; | |
4985 | adapter->gotc = adapter->stats.gotc - adapter->gotc_old; | |
4986 | adapter->gotc_old = adapter->stats.gotc; | |
2084b114 | 4987 | spin_unlock(&adapter->stats64_lock); |
bc7f75fa | 4988 | |
12d43f7d | 4989 | if (adapter->flags & FLAG_RESTART_NOW) { |
90da0669 BA |
4990 | schedule_work(&adapter->reset_task); |
4991 | /* return immediately since reset is imminent */ | |
4992 | return; | |
bc7f75fa AK |
4993 | } |
4994 | ||
12d43f7d BA |
4995 | e1000e_update_adaptive(&adapter->hw); |
4996 | ||
eab2abf5 JB |
4997 | /* Simple mode for Interrupt Throttle Rate (ITR) */ |
4998 | if (adapter->itr_setting == 4) { | |
e921eb1a | 4999 | /* Symmetric Tx/Rx gets a reduced ITR=2000; |
eab2abf5 JB |
5000 | * Total asymmetrical Tx or Rx gets ITR=8000; |
5001 | * everyone else is between 2000-8000. | |
5002 | */ | |
5003 | u32 goc = (adapter->gotc + adapter->gorc) / 10000; | |
5004 | u32 dif = (adapter->gotc > adapter->gorc ? | |
17e813ec BA |
5005 | adapter->gotc - adapter->gorc : |
5006 | adapter->gorc - adapter->gotc) / 10000; | |
eab2abf5 JB |
5007 | u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; |
5008 | ||
22a4cca2 | 5009 | e1000e_write_itr(adapter, itr); |
eab2abf5 JB |
5010 | } |
5011 | ||
ad68076e | 5012 | /* Cause software interrupt to ensure Rx ring is cleaned */ |
4662e82b BA |
5013 | if (adapter->msix_entries) |
5014 | ew32(ICS, adapter->rx_ring->ims_val); | |
5015 | else | |
5016 | ew32(ICS, E1000_ICS_RXDMT0); | |
bc7f75fa | 5017 | |
713b3c9e JB |
5018 | /* flush pending descriptors to memory before detecting Tx hang */ |
5019 | e1000e_flush_descriptors(adapter); | |
5020 | ||
bc7f75fa | 5021 | /* Force detection of hung controller every watchdog period */ |
3db1cd5c | 5022 | adapter->detect_tx_hung = true; |
bc7f75fa | 5023 | |
e921eb1a | 5024 | /* With 82571 controllers, LAA may be overwritten due to controller |
ad68076e BA |
5025 | * reset from the other port. Set the appropriate LAA in RAR[0] |
5026 | */ | |
bc7f75fa | 5027 | if (e1000e_get_laa_state_82571(hw)) |
69e1e019 | 5028 | hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); |
bc7f75fa | 5029 | |
ff10e13c CW |
5030 | if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) |
5031 | e1000e_check_82574_phy_workaround(adapter); | |
5032 | ||
b67e1913 BA |
5033 | /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ |
5034 | if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { | |
5035 | if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && | |
5036 | (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { | |
5037 | er32(RXSTMPH); | |
5038 | adapter->rx_hwtstamp_cleared++; | |
5039 | } else { | |
5040 | adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; | |
5041 | } | |
5042 | } | |
5043 | ||
bc7f75fa AK |
5044 | /* Reset the timer */ |
5045 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
5046 | mod_timer(&adapter->watchdog_timer, | |
5047 | round_jiffies(jiffies + 2 * HZ)); | |
5048 | } | |
5049 | ||
5050 | #define E1000_TX_FLAGS_CSUM 0x00000001 | |
5051 | #define E1000_TX_FLAGS_VLAN 0x00000002 | |
5052 | #define E1000_TX_FLAGS_TSO 0x00000004 | |
5053 | #define E1000_TX_FLAGS_IPV4 0x00000008 | |
943146de | 5054 | #define E1000_TX_FLAGS_NO_FCS 0x00000010 |
b67e1913 | 5055 | #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 |
bc7f75fa AK |
5056 | #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 |
5057 | #define E1000_TX_FLAGS_VLAN_SHIFT 16 | |
5058 | ||
55aa6985 | 5059 | static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb) |
bc7f75fa | 5060 | { |
bc7f75fa AK |
5061 | struct e1000_context_desc *context_desc; |
5062 | struct e1000_buffer *buffer_info; | |
5063 | unsigned int i; | |
5064 | u32 cmd_length = 0; | |
70443ae9 | 5065 | u16 ipcse = 0, mss; |
bc7f75fa | 5066 | u8 ipcss, ipcso, tucss, tucso, hdr_len; |
bc7f75fa | 5067 | |
3d5e33c9 BA |
5068 | if (!skb_is_gso(skb)) |
5069 | return 0; | |
bc7f75fa | 5070 | |
3d5e33c9 | 5071 | if (skb_header_cloned(skb)) { |
90da0669 BA |
5072 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
5073 | ||
3d5e33c9 BA |
5074 | if (err) |
5075 | return err; | |
bc7f75fa AK |
5076 | } |
5077 | ||
3d5e33c9 BA |
5078 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
5079 | mss = skb_shinfo(skb)->gso_size; | |
5080 | if (skb->protocol == htons(ETH_P_IP)) { | |
5081 | struct iphdr *iph = ip_hdr(skb); | |
5082 | iph->tot_len = 0; | |
5083 | iph->check = 0; | |
5084 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, | |
f0ff4398 | 5085 | 0, IPPROTO_TCP, 0); |
3d5e33c9 BA |
5086 | cmd_length = E1000_TXD_CMD_IP; |
5087 | ipcse = skb_transport_offset(skb) - 1; | |
8e1e8a47 | 5088 | } else if (skb_is_gso_v6(skb)) { |
3d5e33c9 BA |
5089 | ipv6_hdr(skb)->payload_len = 0; |
5090 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
f0ff4398 BA |
5091 | &ipv6_hdr(skb)->daddr, |
5092 | 0, IPPROTO_TCP, 0); | |
3d5e33c9 BA |
5093 | ipcse = 0; |
5094 | } | |
5095 | ipcss = skb_network_offset(skb); | |
5096 | ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; | |
5097 | tucss = skb_transport_offset(skb); | |
5098 | tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; | |
3d5e33c9 BA |
5099 | |
5100 | cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | | |
f0ff4398 | 5101 | E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); |
3d5e33c9 BA |
5102 | |
5103 | i = tx_ring->next_to_use; | |
5104 | context_desc = E1000_CONTEXT_DESC(*tx_ring, i); | |
5105 | buffer_info = &tx_ring->buffer_info[i]; | |
5106 | ||
e80bd1d1 BA |
5107 | context_desc->lower_setup.ip_fields.ipcss = ipcss; |
5108 | context_desc->lower_setup.ip_fields.ipcso = ipcso; | |
5109 | context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); | |
3d5e33c9 BA |
5110 | context_desc->upper_setup.tcp_fields.tucss = tucss; |
5111 | context_desc->upper_setup.tcp_fields.tucso = tucso; | |
70443ae9 | 5112 | context_desc->upper_setup.tcp_fields.tucse = 0; |
e80bd1d1 | 5113 | context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); |
3d5e33c9 BA |
5114 | context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; |
5115 | context_desc->cmd_and_length = cpu_to_le32(cmd_length); | |
5116 | ||
5117 | buffer_info->time_stamp = jiffies; | |
5118 | buffer_info->next_to_watch = i; | |
5119 | ||
5120 | i++; | |
5121 | if (i == tx_ring->count) | |
5122 | i = 0; | |
5123 | tx_ring->next_to_use = i; | |
5124 | ||
5125 | return 1; | |
bc7f75fa AK |
5126 | } |
5127 | ||
55aa6985 | 5128 | static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb) |
bc7f75fa | 5129 | { |
55aa6985 | 5130 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
5131 | struct e1000_context_desc *context_desc; |
5132 | struct e1000_buffer *buffer_info; | |
5133 | unsigned int i; | |
5134 | u8 css; | |
af807c82 | 5135 | u32 cmd_len = E1000_TXD_CMD_DEXT; |
5f66f208 | 5136 | __be16 protocol; |
bc7f75fa | 5137 | |
af807c82 DG |
5138 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
5139 | return 0; | |
bc7f75fa | 5140 | |
5f66f208 AJ |
5141 | if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) |
5142 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
5143 | else | |
5144 | protocol = skb->protocol; | |
5145 | ||
3f518390 | 5146 | switch (protocol) { |
09640e63 | 5147 | case cpu_to_be16(ETH_P_IP): |
af807c82 DG |
5148 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
5149 | cmd_len |= E1000_TXD_CMD_TCP; | |
5150 | break; | |
09640e63 | 5151 | case cpu_to_be16(ETH_P_IPV6): |
af807c82 DG |
5152 | /* XXX not handling all IPV6 headers */ |
5153 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
5154 | cmd_len |= E1000_TXD_CMD_TCP; | |
5155 | break; | |
5156 | default: | |
5157 | if (unlikely(net_ratelimit())) | |
5f66f208 AJ |
5158 | e_warn("checksum_partial proto=%x!\n", |
5159 | be16_to_cpu(protocol)); | |
af807c82 | 5160 | break; |
bc7f75fa AK |
5161 | } |
5162 | ||
0d0b1672 | 5163 | css = skb_checksum_start_offset(skb); |
af807c82 DG |
5164 | |
5165 | i = tx_ring->next_to_use; | |
5166 | buffer_info = &tx_ring->buffer_info[i]; | |
5167 | context_desc = E1000_CONTEXT_DESC(*tx_ring, i); | |
5168 | ||
5169 | context_desc->lower_setup.ip_config = 0; | |
5170 | context_desc->upper_setup.tcp_fields.tucss = css; | |
f0ff4398 | 5171 | context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; |
af807c82 DG |
5172 | context_desc->upper_setup.tcp_fields.tucse = 0; |
5173 | context_desc->tcp_seg_setup.data = 0; | |
5174 | context_desc->cmd_and_length = cpu_to_le32(cmd_len); | |
5175 | ||
5176 | buffer_info->time_stamp = jiffies; | |
5177 | buffer_info->next_to_watch = i; | |
5178 | ||
5179 | i++; | |
5180 | if (i == tx_ring->count) | |
5181 | i = 0; | |
5182 | tx_ring->next_to_use = i; | |
5183 | ||
5184 | return 1; | |
bc7f75fa AK |
5185 | } |
5186 | ||
55aa6985 BA |
5187 | static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, |
5188 | unsigned int first, unsigned int max_per_txd, | |
d821a4c4 | 5189 | unsigned int nr_frags) |
bc7f75fa | 5190 | { |
55aa6985 | 5191 | struct e1000_adapter *adapter = tx_ring->adapter; |
03b1320d | 5192 | struct pci_dev *pdev = adapter->pdev; |
1b7719c4 | 5193 | struct e1000_buffer *buffer_info; |
8ddc951c | 5194 | unsigned int len = skb_headlen(skb); |
03b1320d | 5195 | unsigned int offset = 0, size, count = 0, i; |
9ed318d5 | 5196 | unsigned int f, bytecount, segs; |
bc7f75fa AK |
5197 | |
5198 | i = tx_ring->next_to_use; | |
5199 | ||
5200 | while (len) { | |
1b7719c4 | 5201 | buffer_info = &tx_ring->buffer_info[i]; |
bc7f75fa AK |
5202 | size = min(len, max_per_txd); |
5203 | ||
bc7f75fa | 5204 | buffer_info->length = size; |
bc7f75fa | 5205 | buffer_info->time_stamp = jiffies; |
bc7f75fa | 5206 | buffer_info->next_to_watch = i; |
0be3f55f NN |
5207 | buffer_info->dma = dma_map_single(&pdev->dev, |
5208 | skb->data + offset, | |
af667a29 | 5209 | size, DMA_TO_DEVICE); |
03b1320d | 5210 | buffer_info->mapped_as_page = false; |
0be3f55f | 5211 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) |
03b1320d | 5212 | goto dma_error; |
bc7f75fa AK |
5213 | |
5214 | len -= size; | |
5215 | offset += size; | |
03b1320d | 5216 | count++; |
1b7719c4 AD |
5217 | |
5218 | if (len) { | |
5219 | i++; | |
5220 | if (i == tx_ring->count) | |
5221 | i = 0; | |
5222 | } | |
bc7f75fa AK |
5223 | } |
5224 | ||
5225 | for (f = 0; f < nr_frags; f++) { | |
9e903e08 | 5226 | const struct skb_frag_struct *frag; |
bc7f75fa AK |
5227 | |
5228 | frag = &skb_shinfo(skb)->frags[f]; | |
9e903e08 | 5229 | len = skb_frag_size(frag); |
877749bf | 5230 | offset = 0; |
bc7f75fa AK |
5231 | |
5232 | while (len) { | |
1b7719c4 AD |
5233 | i++; |
5234 | if (i == tx_ring->count) | |
5235 | i = 0; | |
5236 | ||
bc7f75fa AK |
5237 | buffer_info = &tx_ring->buffer_info[i]; |
5238 | size = min(len, max_per_txd); | |
bc7f75fa AK |
5239 | |
5240 | buffer_info->length = size; | |
5241 | buffer_info->time_stamp = jiffies; | |
bc7f75fa | 5242 | buffer_info->next_to_watch = i; |
877749bf | 5243 | buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, |
17e813ec BA |
5244 | offset, size, |
5245 | DMA_TO_DEVICE); | |
03b1320d | 5246 | buffer_info->mapped_as_page = true; |
0be3f55f | 5247 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) |
03b1320d | 5248 | goto dma_error; |
bc7f75fa AK |
5249 | |
5250 | len -= size; | |
5251 | offset += size; | |
5252 | count++; | |
bc7f75fa AK |
5253 | } |
5254 | } | |
5255 | ||
af667a29 | 5256 | segs = skb_shinfo(skb)->gso_segs ? : 1; |
9ed318d5 TH |
5257 | /* multiply data chunks by size of headers */ |
5258 | bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; | |
5259 | ||
bc7f75fa | 5260 | tx_ring->buffer_info[i].skb = skb; |
9ed318d5 TH |
5261 | tx_ring->buffer_info[i].segs = segs; |
5262 | tx_ring->buffer_info[i].bytecount = bytecount; | |
bc7f75fa AK |
5263 | tx_ring->buffer_info[first].next_to_watch = i; |
5264 | ||
5265 | return count; | |
03b1320d AD |
5266 | |
5267 | dma_error: | |
af667a29 | 5268 | dev_err(&pdev->dev, "Tx DMA map failed\n"); |
03b1320d | 5269 | buffer_info->dma = 0; |
c1fa347f | 5270 | if (count) |
03b1320d | 5271 | count--; |
c1fa347f RK |
5272 | |
5273 | while (count--) { | |
af667a29 | 5274 | if (i == 0) |
03b1320d | 5275 | i += tx_ring->count; |
c1fa347f | 5276 | i--; |
03b1320d | 5277 | buffer_info = &tx_ring->buffer_info[i]; |
55aa6985 | 5278 | e1000_put_txbuf(tx_ring, buffer_info); |
03b1320d AD |
5279 | } |
5280 | ||
5281 | return 0; | |
bc7f75fa AK |
5282 | } |
5283 | ||
55aa6985 | 5284 | static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) |
bc7f75fa | 5285 | { |
55aa6985 | 5286 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
5287 | struct e1000_tx_desc *tx_desc = NULL; |
5288 | struct e1000_buffer *buffer_info; | |
5289 | u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; | |
5290 | unsigned int i; | |
5291 | ||
5292 | if (tx_flags & E1000_TX_FLAGS_TSO) { | |
5293 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | | |
f0ff4398 | 5294 | E1000_TXD_CMD_TSE; |
bc7f75fa AK |
5295 | txd_upper |= E1000_TXD_POPTS_TXSM << 8; |
5296 | ||
5297 | if (tx_flags & E1000_TX_FLAGS_IPV4) | |
5298 | txd_upper |= E1000_TXD_POPTS_IXSM << 8; | |
5299 | } | |
5300 | ||
5301 | if (tx_flags & E1000_TX_FLAGS_CSUM) { | |
5302 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; | |
5303 | txd_upper |= E1000_TXD_POPTS_TXSM << 8; | |
5304 | } | |
5305 | ||
5306 | if (tx_flags & E1000_TX_FLAGS_VLAN) { | |
5307 | txd_lower |= E1000_TXD_CMD_VLE; | |
5308 | txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); | |
5309 | } | |
5310 | ||
943146de BG |
5311 | if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) |
5312 | txd_lower &= ~(E1000_TXD_CMD_IFCS); | |
5313 | ||
b67e1913 BA |
5314 | if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { |
5315 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; | |
5316 | txd_upper |= E1000_TXD_EXTCMD_TSTAMP; | |
5317 | } | |
5318 | ||
bc7f75fa AK |
5319 | i = tx_ring->next_to_use; |
5320 | ||
36b973df | 5321 | do { |
bc7f75fa AK |
5322 | buffer_info = &tx_ring->buffer_info[i]; |
5323 | tx_desc = E1000_TX_DESC(*tx_ring, i); | |
5324 | tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); | |
f0ff4398 BA |
5325 | tx_desc->lower.data = cpu_to_le32(txd_lower | |
5326 | buffer_info->length); | |
bc7f75fa AK |
5327 | tx_desc->upper.data = cpu_to_le32(txd_upper); |
5328 | ||
5329 | i++; | |
5330 | if (i == tx_ring->count) | |
5331 | i = 0; | |
36b973df | 5332 | } while (--count > 0); |
bc7f75fa AK |
5333 | |
5334 | tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); | |
5335 | ||
943146de BG |
5336 | /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ |
5337 | if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) | |
5338 | tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); | |
5339 | ||
e921eb1a | 5340 | /* Force memory writes to complete before letting h/w |
bc7f75fa AK |
5341 | * know there are new descriptors to fetch. (Only |
5342 | * applicable for weak-ordered memory model archs, | |
ad68076e BA |
5343 | * such as IA-64). |
5344 | */ | |
bc7f75fa AK |
5345 | wmb(); |
5346 | ||
5347 | tx_ring->next_to_use = i; | |
c6e7f51e BA |
5348 | |
5349 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) | |
55aa6985 | 5350 | e1000e_update_tdt_wa(tx_ring, i); |
c6e7f51e | 5351 | else |
c5083cf6 | 5352 | writel(i, tx_ring->tail); |
c6e7f51e | 5353 | |
e921eb1a | 5354 | /* we need this if more than one processor can write to our tail |
ad68076e BA |
5355 | * at a time, it synchronizes IO on IA64/Altix systems |
5356 | */ | |
bc7f75fa AK |
5357 | mmiowb(); |
5358 | } | |
5359 | ||
5360 | #define MINIMUM_DHCP_PACKET_SIZE 282 | |
5361 | static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, | |
5362 | struct sk_buff *skb) | |
5363 | { | |
e80bd1d1 | 5364 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa AK |
5365 | u16 length, offset; |
5366 | ||
d60923c4 BA |
5367 | if (vlan_tx_tag_present(skb) && |
5368 | !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && | |
5369 | (adapter->hw.mng_cookie.status & | |
5370 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) | |
5371 | return 0; | |
bc7f75fa AK |
5372 | |
5373 | if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) | |
5374 | return 0; | |
5375 | ||
53aa82da | 5376 | if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) |
bc7f75fa AK |
5377 | return 0; |
5378 | ||
5379 | { | |
362e20ca | 5380 | const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); |
bc7f75fa AK |
5381 | struct udphdr *udp; |
5382 | ||
5383 | if (ip->protocol != IPPROTO_UDP) | |
5384 | return 0; | |
5385 | ||
5386 | udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); | |
5387 | if (ntohs(udp->dest) != 67) | |
5388 | return 0; | |
5389 | ||
5390 | offset = (u8 *)udp + 8 - skb->data; | |
5391 | length = skb->len - offset; | |
5392 | return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); | |
5393 | } | |
5394 | ||
5395 | return 0; | |
5396 | } | |
5397 | ||
55aa6985 | 5398 | static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) |
bc7f75fa | 5399 | { |
55aa6985 | 5400 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa | 5401 | |
55aa6985 | 5402 | netif_stop_queue(adapter->netdev); |
e921eb1a | 5403 | /* Herbert's original patch had: |
bc7f75fa | 5404 | * smp_mb__after_netif_stop_queue(); |
ad68076e BA |
5405 | * but since that doesn't exist yet, just open code it. |
5406 | */ | |
bc7f75fa AK |
5407 | smp_mb(); |
5408 | ||
e921eb1a | 5409 | /* We need to check again in a case another CPU has just |
ad68076e BA |
5410 | * made room available. |
5411 | */ | |
55aa6985 | 5412 | if (e1000_desc_unused(tx_ring) < size) |
bc7f75fa AK |
5413 | return -EBUSY; |
5414 | ||
5415 | /* A reprieve! */ | |
55aa6985 | 5416 | netif_start_queue(adapter->netdev); |
bc7f75fa AK |
5417 | ++adapter->restart_queue; |
5418 | return 0; | |
5419 | } | |
5420 | ||
55aa6985 | 5421 | static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) |
bc7f75fa | 5422 | { |
d821a4c4 BA |
5423 | BUG_ON(size > tx_ring->count); |
5424 | ||
55aa6985 | 5425 | if (e1000_desc_unused(tx_ring) >= size) |
bc7f75fa | 5426 | return 0; |
55aa6985 | 5427 | return __e1000_maybe_stop_tx(tx_ring, size); |
bc7f75fa AK |
5428 | } |
5429 | ||
3b29a56d SH |
5430 | static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, |
5431 | struct net_device *netdev) | |
bc7f75fa AK |
5432 | { |
5433 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5434 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
5435 | unsigned int first; | |
bc7f75fa | 5436 | unsigned int tx_flags = 0; |
e743d313 | 5437 | unsigned int len = skb_headlen(skb); |
4e6c709c AK |
5438 | unsigned int nr_frags; |
5439 | unsigned int mss; | |
bc7f75fa AK |
5440 | int count = 0; |
5441 | int tso; | |
5442 | unsigned int f; | |
bc7f75fa AK |
5443 | |
5444 | if (test_bit(__E1000_DOWN, &adapter->state)) { | |
5445 | dev_kfree_skb_any(skb); | |
5446 | return NETDEV_TX_OK; | |
5447 | } | |
5448 | ||
5449 | if (skb->len <= 0) { | |
5450 | dev_kfree_skb_any(skb); | |
5451 | return NETDEV_TX_OK; | |
5452 | } | |
5453 | ||
e921eb1a | 5454 | /* The minimum packet size with TCTL.PSP set is 17 bytes so |
6e97c170 TD |
5455 | * pad skb in order to meet this minimum size requirement |
5456 | */ | |
5457 | if (unlikely(skb->len < 17)) { | |
5458 | if (skb_pad(skb, 17 - skb->len)) | |
5459 | return NETDEV_TX_OK; | |
5460 | skb->len = 17; | |
5461 | skb_set_tail_pointer(skb, 17); | |
5462 | } | |
5463 | ||
bc7f75fa | 5464 | mss = skb_shinfo(skb)->gso_size; |
bc7f75fa AK |
5465 | if (mss) { |
5466 | u8 hdr_len; | |
bc7f75fa | 5467 | |
e921eb1a | 5468 | /* TSO Workaround for 82571/2/3 Controllers -- if skb->data |
ad68076e BA |
5469 | * points to just header, pull a few bytes of payload from |
5470 | * frags into skb->data | |
5471 | */ | |
bc7f75fa | 5472 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
e921eb1a | 5473 | /* we do this workaround for ES2LAN, but it is un-necessary, |
ad68076e BA |
5474 | * avoiding it could save a lot of cycles |
5475 | */ | |
4e6c709c | 5476 | if (skb->data_len && (hdr_len == len)) { |
bc7f75fa AK |
5477 | unsigned int pull_size; |
5478 | ||
a2a5b323 | 5479 | pull_size = min_t(unsigned int, 4, skb->data_len); |
bc7f75fa | 5480 | if (!__pskb_pull_tail(skb, pull_size)) { |
44defeb3 | 5481 | e_err("__pskb_pull_tail failed.\n"); |
bc7f75fa AK |
5482 | dev_kfree_skb_any(skb); |
5483 | return NETDEV_TX_OK; | |
5484 | } | |
e743d313 | 5485 | len = skb_headlen(skb); |
bc7f75fa AK |
5486 | } |
5487 | } | |
5488 | ||
5489 | /* reserve a descriptor for the offload context */ | |
5490 | if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) | |
5491 | count++; | |
5492 | count++; | |
5493 | ||
d821a4c4 | 5494 | count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); |
bc7f75fa AK |
5495 | |
5496 | nr_frags = skb_shinfo(skb)->nr_frags; | |
5497 | for (f = 0; f < nr_frags; f++) | |
d821a4c4 BA |
5498 | count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), |
5499 | adapter->tx_fifo_limit); | |
bc7f75fa AK |
5500 | |
5501 | if (adapter->hw.mac.tx_pkt_filtering) | |
5502 | e1000_transfer_dhcp_info(adapter, skb); | |
5503 | ||
e921eb1a | 5504 | /* need: count + 2 desc gap to keep tail from touching |
ad68076e BA |
5505 | * head, otherwise try next time |
5506 | */ | |
55aa6985 | 5507 | if (e1000_maybe_stop_tx(tx_ring, count + 2)) |
bc7f75fa | 5508 | return NETDEV_TX_BUSY; |
bc7f75fa | 5509 | |
eab6d18d | 5510 | if (vlan_tx_tag_present(skb)) { |
bc7f75fa AK |
5511 | tx_flags |= E1000_TX_FLAGS_VLAN; |
5512 | tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT); | |
5513 | } | |
5514 | ||
5515 | first = tx_ring->next_to_use; | |
5516 | ||
55aa6985 | 5517 | tso = e1000_tso(tx_ring, skb); |
bc7f75fa AK |
5518 | if (tso < 0) { |
5519 | dev_kfree_skb_any(skb); | |
bc7f75fa AK |
5520 | return NETDEV_TX_OK; |
5521 | } | |
5522 | ||
5523 | if (tso) | |
5524 | tx_flags |= E1000_TX_FLAGS_TSO; | |
55aa6985 | 5525 | else if (e1000_tx_csum(tx_ring, skb)) |
bc7f75fa AK |
5526 | tx_flags |= E1000_TX_FLAGS_CSUM; |
5527 | ||
e921eb1a | 5528 | /* Old method was to assume IPv4 packet by default if TSO was enabled. |
bc7f75fa | 5529 | * 82571 hardware supports TSO capabilities for IPv6 as well... |
ad68076e BA |
5530 | * no longer assume, we must. |
5531 | */ | |
bc7f75fa AK |
5532 | if (skb->protocol == htons(ETH_P_IP)) |
5533 | tx_flags |= E1000_TX_FLAGS_IPV4; | |
5534 | ||
943146de BG |
5535 | if (unlikely(skb->no_fcs)) |
5536 | tx_flags |= E1000_TX_FLAGS_NO_FCS; | |
5537 | ||
25985edc | 5538 | /* if count is 0 then mapping error has occurred */ |
d821a4c4 BA |
5539 | count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, |
5540 | nr_frags); | |
1b7719c4 | 5541 | if (count) { |
b67e1913 BA |
5542 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
5543 | !adapter->tx_hwtstamp_skb)) { | |
5544 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
5545 | tx_flags |= E1000_TX_FLAGS_HWTSTAMP; | |
5546 | adapter->tx_hwtstamp_skb = skb_get(skb); | |
5547 | schedule_work(&adapter->tx_hwtstamp_work); | |
5548 | } else { | |
5549 | skb_tx_timestamp(skb); | |
5550 | } | |
80be3129 | 5551 | |
3f0cfa3b | 5552 | netdev_sent_queue(netdev, skb->len); |
55aa6985 | 5553 | e1000_tx_queue(tx_ring, tx_flags, count); |
1b7719c4 | 5554 | /* Make sure there is space in the ring for the next send. */ |
d821a4c4 BA |
5555 | e1000_maybe_stop_tx(tx_ring, |
5556 | (MAX_SKB_FRAGS * | |
5557 | DIV_ROUND_UP(PAGE_SIZE, | |
5558 | adapter->tx_fifo_limit) + 2)); | |
1b7719c4 | 5559 | } else { |
bc7f75fa | 5560 | dev_kfree_skb_any(skb); |
1b7719c4 AD |
5561 | tx_ring->buffer_info[first].time_stamp = 0; |
5562 | tx_ring->next_to_use = first; | |
bc7f75fa AK |
5563 | } |
5564 | ||
bc7f75fa AK |
5565 | return NETDEV_TX_OK; |
5566 | } | |
5567 | ||
5568 | /** | |
5569 | * e1000_tx_timeout - Respond to a Tx Hang | |
5570 | * @netdev: network interface device structure | |
5571 | **/ | |
5572 | static void e1000_tx_timeout(struct net_device *netdev) | |
5573 | { | |
5574 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5575 | ||
5576 | /* Do the reset outside of interrupt context */ | |
5577 | adapter->tx_timeout_count++; | |
5578 | schedule_work(&adapter->reset_task); | |
5579 | } | |
5580 | ||
5581 | static void e1000_reset_task(struct work_struct *work) | |
5582 | { | |
5583 | struct e1000_adapter *adapter; | |
5584 | adapter = container_of(work, struct e1000_adapter, reset_task); | |
5585 | ||
615b32af JB |
5586 | /* don't run the task if already down */ |
5587 | if (test_bit(__E1000_DOWN, &adapter->state)) | |
5588 | return; | |
5589 | ||
12d43f7d | 5590 | if (!(adapter->flags & FLAG_RESTART_NOW)) { |
affa9dfb | 5591 | e1000e_dump(adapter); |
12d43f7d | 5592 | e_err("Reset adapter unexpectedly\n"); |
affa9dfb | 5593 | } |
bc7f75fa AK |
5594 | e1000e_reinit_locked(adapter); |
5595 | } | |
5596 | ||
5597 | /** | |
67fd4fcb | 5598 | * e1000_get_stats64 - Get System Network Statistics |
bc7f75fa | 5599 | * @netdev: network interface device structure |
67fd4fcb | 5600 | * @stats: rtnl_link_stats64 pointer |
bc7f75fa AK |
5601 | * |
5602 | * Returns the address of the device statistics structure. | |
bc7f75fa | 5603 | **/ |
67fd4fcb | 5604 | struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, |
66501f56 | 5605 | struct rtnl_link_stats64 *stats) |
bc7f75fa | 5606 | { |
67fd4fcb JK |
5607 | struct e1000_adapter *adapter = netdev_priv(netdev); |
5608 | ||
5609 | memset(stats, 0, sizeof(struct rtnl_link_stats64)); | |
5610 | spin_lock(&adapter->stats64_lock); | |
5611 | e1000e_update_stats(adapter); | |
5612 | /* Fill out the OS statistics structure */ | |
5613 | stats->rx_bytes = adapter->stats.gorc; | |
5614 | stats->rx_packets = adapter->stats.gprc; | |
5615 | stats->tx_bytes = adapter->stats.gotc; | |
5616 | stats->tx_packets = adapter->stats.gptc; | |
5617 | stats->multicast = adapter->stats.mprc; | |
5618 | stats->collisions = adapter->stats.colc; | |
5619 | ||
5620 | /* Rx Errors */ | |
5621 | ||
e921eb1a | 5622 | /* RLEC on some newer hardware can be incorrect so build |
67fd4fcb JK |
5623 | * our own version based on RUC and ROC |
5624 | */ | |
5625 | stats->rx_errors = adapter->stats.rxerrc + | |
f0ff4398 BA |
5626 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
5627 | adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; | |
5628 | stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; | |
67fd4fcb JK |
5629 | stats->rx_crc_errors = adapter->stats.crcerrs; |
5630 | stats->rx_frame_errors = adapter->stats.algnerrc; | |
5631 | stats->rx_missed_errors = adapter->stats.mpc; | |
5632 | ||
5633 | /* Tx Errors */ | |
f0ff4398 | 5634 | stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; |
67fd4fcb JK |
5635 | stats->tx_aborted_errors = adapter->stats.ecol; |
5636 | stats->tx_window_errors = adapter->stats.latecol; | |
5637 | stats->tx_carrier_errors = adapter->stats.tncrs; | |
5638 | ||
5639 | /* Tx Dropped needs to be maintained elsewhere */ | |
5640 | ||
5641 | spin_unlock(&adapter->stats64_lock); | |
5642 | return stats; | |
bc7f75fa AK |
5643 | } |
5644 | ||
5645 | /** | |
5646 | * e1000_change_mtu - Change the Maximum Transfer Unit | |
5647 | * @netdev: network interface device structure | |
5648 | * @new_mtu: new value for maximum frame size | |
5649 | * | |
5650 | * Returns 0 on success, negative on failure | |
5651 | **/ | |
5652 | static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |
5653 | { | |
5654 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5655 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
5656 | ||
2adc55c9 | 5657 | /* Jumbo frame support */ |
2e1706f2 BA |
5658 | if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) && |
5659 | !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { | |
5660 | e_err("Jumbo Frames not supported.\n"); | |
5661 | return -EINVAL; | |
bc7f75fa AK |
5662 | } |
5663 | ||
2adc55c9 BA |
5664 | /* Supported frame sizes */ |
5665 | if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) || | |
5666 | (max_frame > adapter->max_hw_frame_size)) { | |
5667 | e_err("Unsupported MTU setting\n"); | |
bc7f75fa AK |
5668 | return -EINVAL; |
5669 | } | |
5670 | ||
2fbe4526 BA |
5671 | /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ |
5672 | if ((adapter->hw.mac.type >= e1000_pch2lan) && | |
a1ce6473 BA |
5673 | !(adapter->flags2 & FLAG2_CRC_STRIPPING) && |
5674 | (new_mtu > ETH_DATA_LEN)) { | |
2fbe4526 | 5675 | e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); |
a1ce6473 BA |
5676 | return -EINVAL; |
5677 | } | |
5678 | ||
bc7f75fa | 5679 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) |
1bba4386 | 5680 | usleep_range(1000, 2000); |
610c9928 | 5681 | /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ |
318a94d6 | 5682 | adapter->max_frame_size = max_frame; |
610c9928 BA |
5683 | e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
5684 | netdev->mtu = new_mtu; | |
bc7f75fa AK |
5685 | if (netif_running(netdev)) |
5686 | e1000e_down(adapter); | |
5687 | ||
e921eb1a | 5688 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN |
bc7f75fa AK |
5689 | * means we reserve 2 more, this pushes us to allocate from the next |
5690 | * larger slab size. | |
ad68076e | 5691 | * i.e. RXBUFFER_2048 --> size-4096 slab |
97ac8cae BA |
5692 | * However with the new *_jumbo_rx* routines, jumbo receives will use |
5693 | * fragmented skbs | |
ad68076e | 5694 | */ |
bc7f75fa | 5695 | |
9926146b | 5696 | if (max_frame <= 2048) |
bc7f75fa AK |
5697 | adapter->rx_buffer_len = 2048; |
5698 | else | |
5699 | adapter->rx_buffer_len = 4096; | |
5700 | ||
5701 | /* adjust allocation if LPE protects us, and we aren't using SBP */ | |
5702 | if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || | |
17e813ec | 5703 | (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)) |
bc7f75fa | 5704 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN |
17e813ec | 5705 | + ETH_FCS_LEN; |
bc7f75fa | 5706 | |
bc7f75fa AK |
5707 | if (netif_running(netdev)) |
5708 | e1000e_up(adapter); | |
5709 | else | |
5710 | e1000e_reset(adapter); | |
5711 | ||
5712 | clear_bit(__E1000_RESETTING, &adapter->state); | |
5713 | ||
5714 | return 0; | |
5715 | } | |
5716 | ||
5717 | static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, | |
5718 | int cmd) | |
5719 | { | |
5720 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5721 | struct mii_ioctl_data *data = if_mii(ifr); | |
bc7f75fa | 5722 | |
318a94d6 | 5723 | if (adapter->hw.phy.media_type != e1000_media_type_copper) |
bc7f75fa AK |
5724 | return -EOPNOTSUPP; |
5725 | ||
5726 | switch (cmd) { | |
5727 | case SIOCGMIIPHY: | |
5728 | data->phy_id = adapter->hw.phy.addr; | |
5729 | break; | |
5730 | case SIOCGMIIREG: | |
b16a002e BA |
5731 | e1000_phy_read_status(adapter); |
5732 | ||
7c25769f BA |
5733 | switch (data->reg_num & 0x1F) { |
5734 | case MII_BMCR: | |
5735 | data->val_out = adapter->phy_regs.bmcr; | |
5736 | break; | |
5737 | case MII_BMSR: | |
5738 | data->val_out = adapter->phy_regs.bmsr; | |
5739 | break; | |
5740 | case MII_PHYSID1: | |
5741 | data->val_out = (adapter->hw.phy.id >> 16); | |
5742 | break; | |
5743 | case MII_PHYSID2: | |
5744 | data->val_out = (adapter->hw.phy.id & 0xFFFF); | |
5745 | break; | |
5746 | case MII_ADVERTISE: | |
5747 | data->val_out = adapter->phy_regs.advertise; | |
5748 | break; | |
5749 | case MII_LPA: | |
5750 | data->val_out = adapter->phy_regs.lpa; | |
5751 | break; | |
5752 | case MII_EXPANSION: | |
5753 | data->val_out = adapter->phy_regs.expansion; | |
5754 | break; | |
5755 | case MII_CTRL1000: | |
5756 | data->val_out = adapter->phy_regs.ctrl1000; | |
5757 | break; | |
5758 | case MII_STAT1000: | |
5759 | data->val_out = adapter->phy_regs.stat1000; | |
5760 | break; | |
5761 | case MII_ESTATUS: | |
5762 | data->val_out = adapter->phy_regs.estatus; | |
5763 | break; | |
5764 | default: | |
bc7f75fa AK |
5765 | return -EIO; |
5766 | } | |
bc7f75fa AK |
5767 | break; |
5768 | case SIOCSMIIREG: | |
5769 | default: | |
5770 | return -EOPNOTSUPP; | |
5771 | } | |
5772 | return 0; | |
5773 | } | |
5774 | ||
b67e1913 BA |
5775 | /** |
5776 | * e1000e_hwtstamp_ioctl - control hardware time stamping | |
5777 | * @netdev: network interface device structure | |
5778 | * @ifreq: interface request | |
5779 | * | |
5780 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
5781 | * disable it when requested, although it shouldn't cause any overhead | |
5782 | * when no packet needs it. At most one packet in the queue may be | |
5783 | * marked for time stamping, otherwise it would be impossible to tell | |
5784 | * for sure to which packet the hardware time stamp belongs. | |
5785 | * | |
5786 | * Incoming time stamping has to be configured via the hardware filters. | |
5787 | * Not all combinations are supported, in particular event type has to be | |
5788 | * specified. Matching the kind of event packet is not supported, with the | |
5789 | * exception of "all V2 events regardless of level 2 or 4". | |
5790 | **/ | |
5791 | static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr) | |
5792 | { | |
5793 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5794 | struct hwtstamp_config config; | |
5795 | int ret_val; | |
5796 | ||
5797 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
5798 | return -EFAULT; | |
5799 | ||
5800 | adapter->hwtstamp_config = config; | |
5801 | ||
5802 | ret_val = e1000e_config_hwtstamp(adapter); | |
5803 | if (ret_val) | |
5804 | return ret_val; | |
5805 | ||
5806 | config = adapter->hwtstamp_config; | |
5807 | ||
d89777bf BA |
5808 | switch (config.rx_filter) { |
5809 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
5810 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
5811 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
5812 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
5813 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
5814 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
5815 | /* With V2 type filters which specify a Sync or Delay Request, | |
5816 | * Path Delay Request/Response messages are also time stamped | |
5817 | * by hardware so notify the caller the requested packets plus | |
5818 | * some others are time stamped. | |
5819 | */ | |
5820 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
5821 | break; | |
5822 | default: | |
5823 | break; | |
5824 | } | |
5825 | ||
b67e1913 BA |
5826 | return copy_to_user(ifr->ifr_data, &config, |
5827 | sizeof(config)) ? -EFAULT : 0; | |
5828 | } | |
5829 | ||
bc7f75fa AK |
5830 | static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
5831 | { | |
5832 | switch (cmd) { | |
5833 | case SIOCGMIIPHY: | |
5834 | case SIOCGMIIREG: | |
5835 | case SIOCSMIIREG: | |
5836 | return e1000_mii_ioctl(netdev, ifr, cmd); | |
b67e1913 BA |
5837 | case SIOCSHWTSTAMP: |
5838 | return e1000e_hwtstamp_ioctl(netdev, ifr); | |
bc7f75fa AK |
5839 | default: |
5840 | return -EOPNOTSUPP; | |
5841 | } | |
5842 | } | |
5843 | ||
a4f58f54 BA |
5844 | static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) |
5845 | { | |
5846 | struct e1000_hw *hw = &adapter->hw; | |
5847 | u32 i, mac_reg; | |
2b6b168d | 5848 | u16 phy_reg, wuc_enable; |
70806a7f | 5849 | int retval; |
a4f58f54 BA |
5850 | |
5851 | /* copy MAC RARs to PHY RARs */ | |
d3738bb8 | 5852 | e1000_copy_rx_addrs_to_phy_ich8lan(hw); |
a4f58f54 | 5853 | |
2b6b168d BA |
5854 | retval = hw->phy.ops.acquire(hw); |
5855 | if (retval) { | |
5856 | e_err("Could not acquire PHY\n"); | |
5857 | return retval; | |
5858 | } | |
5859 | ||
5860 | /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ | |
5861 | retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); | |
5862 | if (retval) | |
75ce1532 | 5863 | goto release; |
2b6b168d BA |
5864 | |
5865 | /* copy MAC MTA to PHY MTA - only needed for pchlan */ | |
a4f58f54 BA |
5866 | for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { |
5867 | mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); | |
2b6b168d BA |
5868 | hw->phy.ops.write_reg_page(hw, BM_MTA(i), |
5869 | (u16)(mac_reg & 0xFFFF)); | |
5870 | hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, | |
5871 | (u16)((mac_reg >> 16) & 0xFFFF)); | |
a4f58f54 BA |
5872 | } |
5873 | ||
5874 | /* configure PHY Rx Control register */ | |
2b6b168d | 5875 | hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); |
a4f58f54 BA |
5876 | mac_reg = er32(RCTL); |
5877 | if (mac_reg & E1000_RCTL_UPE) | |
5878 | phy_reg |= BM_RCTL_UPE; | |
5879 | if (mac_reg & E1000_RCTL_MPE) | |
5880 | phy_reg |= BM_RCTL_MPE; | |
5881 | phy_reg &= ~(BM_RCTL_MO_MASK); | |
5882 | if (mac_reg & E1000_RCTL_MO_3) | |
5883 | phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) | |
17e813ec | 5884 | << BM_RCTL_MO_SHIFT); |
a4f58f54 BA |
5885 | if (mac_reg & E1000_RCTL_BAM) |
5886 | phy_reg |= BM_RCTL_BAM; | |
5887 | if (mac_reg & E1000_RCTL_PMCF) | |
5888 | phy_reg |= BM_RCTL_PMCF; | |
5889 | mac_reg = er32(CTRL); | |
5890 | if (mac_reg & E1000_CTRL_RFCE) | |
5891 | phy_reg |= BM_RCTL_RFCE; | |
2b6b168d | 5892 | hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); |
a4f58f54 BA |
5893 | |
5894 | /* enable PHY wakeup in MAC register */ | |
5895 | ew32(WUFC, wufc); | |
5896 | ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN); | |
5897 | ||
5898 | /* configure and enable PHY wakeup in PHY registers */ | |
2b6b168d BA |
5899 | hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); |
5900 | hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); | |
a4f58f54 BA |
5901 | |
5902 | /* activate PHY wakeup */ | |
2b6b168d BA |
5903 | wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; |
5904 | retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); | |
a4f58f54 BA |
5905 | if (retval) |
5906 | e_err("Could not set PHY Host Wakeup bit\n"); | |
75ce1532 | 5907 | release: |
94d8186a | 5908 | hw->phy.ops.release(hw); |
a4f58f54 BA |
5909 | |
5910 | return retval; | |
5911 | } | |
5912 | ||
66148bab | 5913 | static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) |
bc7f75fa AK |
5914 | { |
5915 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5916 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5917 | struct e1000_hw *hw = &adapter->hw; | |
5918 | u32 ctrl, ctrl_ext, rctl, status; | |
23606cf5 RW |
5919 | /* Runtime suspend should only enable wakeup for link changes */ |
5920 | u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; | |
bc7f75fa AK |
5921 | int retval = 0; |
5922 | ||
5923 | netif_device_detach(netdev); | |
5924 | ||
5925 | if (netif_running(netdev)) { | |
bb9e44d0 BA |
5926 | int count = E1000_CHECK_RESET_COUNT; |
5927 | ||
5928 | while (test_bit(__E1000_RESETTING, &adapter->state) && count--) | |
5929 | usleep_range(10000, 20000); | |
5930 | ||
bc7f75fa AK |
5931 | WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); |
5932 | e1000e_down(adapter); | |
5933 | e1000_free_irq(adapter); | |
5934 | } | |
4662e82b | 5935 | e1000e_reset_interrupt_capability(adapter); |
bc7f75fa | 5936 | |
bc7f75fa AK |
5937 | status = er32(STATUS); |
5938 | if (status & E1000_STATUS_LU) | |
5939 | wufc &= ~E1000_WUFC_LNKC; | |
5940 | ||
5941 | if (wufc) { | |
5942 | e1000_setup_rctl(adapter); | |
ef9b965a | 5943 | e1000e_set_rx_mode(netdev); |
bc7f75fa AK |
5944 | |
5945 | /* turn on all-multi mode if wake on multicast is enabled */ | |
5946 | if (wufc & E1000_WUFC_MC) { | |
5947 | rctl = er32(RCTL); | |
5948 | rctl |= E1000_RCTL_MPE; | |
5949 | ew32(RCTL, rctl); | |
5950 | } | |
5951 | ||
5952 | ctrl = er32(CTRL); | |
a4f58f54 BA |
5953 | ctrl |= E1000_CTRL_ADVD3WUC; |
5954 | if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) | |
5955 | ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; | |
bc7f75fa AK |
5956 | ew32(CTRL, ctrl); |
5957 | ||
318a94d6 JK |
5958 | if (adapter->hw.phy.media_type == e1000_media_type_fiber || |
5959 | adapter->hw.phy.media_type == | |
5960 | e1000_media_type_internal_serdes) { | |
bc7f75fa AK |
5961 | /* keep the laser running in D3 */ |
5962 | ctrl_ext = er32(CTRL_EXT); | |
93a23f48 | 5963 | ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; |
bc7f75fa AK |
5964 | ew32(CTRL_EXT, ctrl_ext); |
5965 | } | |
5966 | ||
97ac8cae | 5967 | if (adapter->flags & FLAG_IS_ICH) |
99730e4c | 5968 | e1000_suspend_workarounds_ich8lan(&adapter->hw); |
97ac8cae | 5969 | |
bc7f75fa AK |
5970 | /* Allow time for pending master requests to run */ |
5971 | e1000e_disable_pcie_master(&adapter->hw); | |
5972 | ||
82776a4b | 5973 | if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { |
a4f58f54 BA |
5974 | /* enable wakeup by the PHY */ |
5975 | retval = e1000_init_phy_wakeup(adapter, wufc); | |
5976 | if (retval) | |
5977 | return retval; | |
5978 | } else { | |
5979 | /* enable wakeup by the MAC */ | |
5980 | ew32(WUFC, wufc); | |
5981 | ew32(WUC, E1000_WUC_PME_EN); | |
5982 | } | |
bc7f75fa AK |
5983 | } else { |
5984 | ew32(WUC, 0); | |
5985 | ew32(WUFC, 0); | |
bc7f75fa AK |
5986 | } |
5987 | ||
bc7f75fa AK |
5988 | if (adapter->hw.phy.type == e1000_phy_igp_3) |
5989 | e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); | |
5990 | ||
e921eb1a | 5991 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
ad68076e BA |
5992 | * would have already happened in close and is redundant. |
5993 | */ | |
31dbe5b4 | 5994 | e1000e_release_hw_control(adapter); |
bc7f75fa | 5995 | |
24b41c97 DN |
5996 | pci_clear_master(pdev); |
5997 | ||
e921eb1a | 5998 | /* The pci-e switch on some quad port adapters will report a |
005cbdfc AD |
5999 | * correctable error when the MAC transitions from D0 to D3. To |
6000 | * prevent this we need to mask off the correctable errors on the | |
6001 | * downstream port of the pci-e switch. | |
e8c254c5 LZ |
6002 | * |
6003 | * We don't have the associated upstream bridge while assigning | |
6004 | * the PCI device into guest. For example, the KVM on power is | |
6005 | * one of the cases. | |
005cbdfc AD |
6006 | */ |
6007 | if (adapter->flags & FLAG_IS_QUAD_PORT) { | |
6008 | struct pci_dev *us_dev = pdev->bus->self; | |
005cbdfc AD |
6009 | u16 devctl; |
6010 | ||
e8c254c5 LZ |
6011 | if (!us_dev) |
6012 | return 0; | |
6013 | ||
f8c0fcac JL |
6014 | pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); |
6015 | pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, | |
6016 | (devctl & ~PCI_EXP_DEVCTL_CERE)); | |
005cbdfc | 6017 | |
66148bab KK |
6018 | pci_save_state(pdev); |
6019 | pci_prepare_to_sleep(pdev); | |
005cbdfc | 6020 | |
f8c0fcac | 6021 | pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); |
005cbdfc | 6022 | } |
66148bab KK |
6023 | |
6024 | return 0; | |
bc7f75fa AK |
6025 | } |
6026 | ||
13129d9b CW |
6027 | /** |
6028 | * e1000e_disable_aspm - Disable ASPM states | |
6029 | * @pdev: pointer to PCI device struct | |
6030 | * @state: bit-mask of ASPM states to disable | |
6031 | * | |
6032 | * Some devices *must* have certain ASPM states disabled per hardware errata. | |
6033 | **/ | |
6034 | static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) | |
6f461f6c | 6035 | { |
13129d9b CW |
6036 | struct pci_dev *parent = pdev->bus->self; |
6037 | u16 aspm_dis_mask = 0; | |
6038 | u16 pdev_aspmc, parent_aspmc; | |
6039 | ||
6040 | switch (state) { | |
6041 | case PCIE_LINK_STATE_L0S: | |
6042 | case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: | |
6043 | aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; | |
6044 | /* fall-through - can't have L1 without L0s */ | |
6045 | case PCIE_LINK_STATE_L1: | |
6046 | aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; | |
6047 | break; | |
6048 | default: | |
6049 | return; | |
6050 | } | |
6051 | ||
6052 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); | |
6053 | pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; | |
6054 | ||
6055 | if (parent) { | |
6056 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL, | |
6057 | &parent_aspmc); | |
6058 | parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; | |
6059 | } | |
6060 | ||
6061 | /* Nothing to do if the ASPM states to be disabled already are */ | |
6062 | if (!(pdev_aspmc & aspm_dis_mask) && | |
6063 | (!parent || !(parent_aspmc & aspm_dis_mask))) | |
6064 | return; | |
6065 | ||
6066 | dev_info(&pdev->dev, "Disabling ASPM %s %s\n", | |
6067 | (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? | |
6068 | "L0s" : "", | |
6069 | (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? | |
6070 | "L1" : ""); | |
6071 | ||
6072 | #ifdef CONFIG_PCIEASPM | |
9f728f53 | 6073 | pci_disable_link_state_locked(pdev, state); |
ffe0b2ff | 6074 | |
13129d9b CW |
6075 | /* Double-check ASPM control. If not disabled by the above, the |
6076 | * BIOS is preventing that from happening (or CONFIG_PCIEASPM is | |
6077 | * not enabled); override by writing PCI config space directly. | |
6078 | */ | |
6079 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); | |
6080 | pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; | |
6081 | ||
6082 | if (!(aspm_dis_mask & pdev_aspmc)) | |
6083 | return; | |
6084 | #endif | |
ffe0b2ff | 6085 | |
e921eb1a | 6086 | /* Both device and parent should have the same ASPM setting. |
6f461f6c | 6087 | * Disable ASPM in downstream component first and then upstream. |
1eae4eb2 | 6088 | */ |
13129d9b | 6089 | pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); |
6f461f6c | 6090 | |
13129d9b CW |
6091 | if (parent) |
6092 | pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, | |
6093 | aspm_dis_mask); | |
1eae4eb2 AK |
6094 | } |
6095 | ||
aa338601 | 6096 | #ifdef CONFIG_PM |
23606cf5 | 6097 | static bool e1000e_pm_ready(struct e1000_adapter *adapter) |
4f9de721 | 6098 | { |
23606cf5 | 6099 | return !!adapter->tx_ring->buffer_info; |
4f9de721 RW |
6100 | } |
6101 | ||
23606cf5 | 6102 | static int __e1000_resume(struct pci_dev *pdev) |
bc7f75fa AK |
6103 | { |
6104 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6105 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6106 | struct e1000_hw *hw = &adapter->hw; | |
78cd29d5 | 6107 | u16 aspm_disable_flag = 0; |
bc7f75fa AK |
6108 | u32 err; |
6109 | ||
78cd29d5 BA |
6110 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) |
6111 | aspm_disable_flag = PCIE_LINK_STATE_L0S; | |
6112 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) | |
6113 | aspm_disable_flag |= PCIE_LINK_STATE_L1; | |
6114 | if (aspm_disable_flag) | |
6115 | e1000e_disable_aspm(pdev, aspm_disable_flag); | |
6116 | ||
66148bab | 6117 | pci_set_master(pdev); |
6e4f6f6b | 6118 | |
4662e82b | 6119 | e1000e_set_interrupt_capability(adapter); |
bc7f75fa AK |
6120 | if (netif_running(netdev)) { |
6121 | err = e1000_request_irq(adapter); | |
6122 | if (err) | |
6123 | return err; | |
6124 | } | |
6125 | ||
2fbe4526 | 6126 | if (hw->mac.type >= e1000_pch2lan) |
99730e4c BA |
6127 | e1000_resume_workarounds_pchlan(&adapter->hw); |
6128 | ||
bc7f75fa | 6129 | e1000e_power_up_phy(adapter); |
a4f58f54 BA |
6130 | |
6131 | /* report the system wakeup cause from S3/S4 */ | |
6132 | if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { | |
6133 | u16 phy_data; | |
6134 | ||
6135 | e1e_rphy(&adapter->hw, BM_WUS, &phy_data); | |
6136 | if (phy_data) { | |
6137 | e_info("PHY Wakeup cause - %s\n", | |
17e813ec BA |
6138 | phy_data & E1000_WUS_EX ? "Unicast Packet" : |
6139 | phy_data & E1000_WUS_MC ? "Multicast Packet" : | |
6140 | phy_data & E1000_WUS_BC ? "Broadcast Packet" : | |
6141 | phy_data & E1000_WUS_MAG ? "Magic Packet" : | |
6142 | phy_data & E1000_WUS_LNKC ? | |
6143 | "Link Status Change" : "other"); | |
a4f58f54 BA |
6144 | } |
6145 | e1e_wphy(&adapter->hw, BM_WUS, ~0); | |
6146 | } else { | |
6147 | u32 wus = er32(WUS); | |
6148 | if (wus) { | |
6149 | e_info("MAC Wakeup cause - %s\n", | |
17e813ec BA |
6150 | wus & E1000_WUS_EX ? "Unicast Packet" : |
6151 | wus & E1000_WUS_MC ? "Multicast Packet" : | |
6152 | wus & E1000_WUS_BC ? "Broadcast Packet" : | |
6153 | wus & E1000_WUS_MAG ? "Magic Packet" : | |
6154 | wus & E1000_WUS_LNKC ? "Link Status Change" : | |
6155 | "other"); | |
a4f58f54 BA |
6156 | } |
6157 | ew32(WUS, ~0); | |
6158 | } | |
6159 | ||
bc7f75fa | 6160 | e1000e_reset(adapter); |
bc7f75fa | 6161 | |
cd791618 | 6162 | e1000_init_manageability_pt(adapter); |
bc7f75fa AK |
6163 | |
6164 | if (netif_running(netdev)) | |
6165 | e1000e_up(adapter); | |
6166 | ||
6167 | netif_device_attach(netdev); | |
6168 | ||
e921eb1a | 6169 | /* If the controller has AMT, do not set DRV_LOAD until the interface |
bc7f75fa | 6170 | * is up. For all other cases, let the f/w know that the h/w is now |
ad68076e BA |
6171 | * under the control of the driver. |
6172 | */ | |
c43bc57e | 6173 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 6174 | e1000e_get_hw_control(adapter); |
bc7f75fa AK |
6175 | |
6176 | return 0; | |
6177 | } | |
23606cf5 | 6178 | |
a0340162 RW |
6179 | #ifdef CONFIG_PM_SLEEP |
6180 | static int e1000_suspend(struct device *dev) | |
6181 | { | |
6182 | struct pci_dev *pdev = to_pci_dev(dev); | |
a0340162 | 6183 | |
66148bab | 6184 | return __e1000_shutdown(pdev, false); |
a0340162 RW |
6185 | } |
6186 | ||
23606cf5 RW |
6187 | static int e1000_resume(struct device *dev) |
6188 | { | |
6189 | struct pci_dev *pdev = to_pci_dev(dev); | |
6190 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6191 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6192 | ||
6193 | if (e1000e_pm_ready(adapter)) | |
6194 | adapter->idle_check = true; | |
6195 | ||
6196 | return __e1000_resume(pdev); | |
6197 | } | |
a0340162 RW |
6198 | #endif /* CONFIG_PM_SLEEP */ |
6199 | ||
6200 | #ifdef CONFIG_PM_RUNTIME | |
6201 | static int e1000_runtime_suspend(struct device *dev) | |
6202 | { | |
6203 | struct pci_dev *pdev = to_pci_dev(dev); | |
6204 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6205 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6206 | ||
66148bab KK |
6207 | if (!e1000e_pm_ready(adapter)) |
6208 | return 0; | |
a0340162 | 6209 | |
66148bab | 6210 | return __e1000_shutdown(pdev, true); |
a0340162 RW |
6211 | } |
6212 | ||
6213 | static int e1000_idle(struct device *dev) | |
6214 | { | |
6215 | struct pci_dev *pdev = to_pci_dev(dev); | |
6216 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6217 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6218 | ||
6219 | if (!e1000e_pm_ready(adapter)) | |
6220 | return 0; | |
6221 | ||
6222 | if (adapter->idle_check) { | |
6223 | adapter->idle_check = false; | |
6224 | if (!e1000e_has_link(adapter)) | |
6225 | pm_schedule_suspend(dev, MSEC_PER_SEC); | |
6226 | } | |
6227 | ||
6228 | return -EBUSY; | |
6229 | } | |
23606cf5 RW |
6230 | |
6231 | static int e1000_runtime_resume(struct device *dev) | |
6232 | { | |
6233 | struct pci_dev *pdev = to_pci_dev(dev); | |
6234 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6235 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6236 | ||
6237 | if (!e1000e_pm_ready(adapter)) | |
6238 | return 0; | |
6239 | ||
6240 | adapter->idle_check = !dev->power.runtime_auto; | |
6241 | return __e1000_resume(pdev); | |
6242 | } | |
a0340162 | 6243 | #endif /* CONFIG_PM_RUNTIME */ |
aa338601 | 6244 | #endif /* CONFIG_PM */ |
bc7f75fa AK |
6245 | |
6246 | static void e1000_shutdown(struct pci_dev *pdev) | |
6247 | { | |
66148bab | 6248 | __e1000_shutdown(pdev, false); |
bc7f75fa AK |
6249 | } |
6250 | ||
6251 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
147b2c8c | 6252 | |
8bb62869 | 6253 | static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) |
147b2c8c DD |
6254 | { |
6255 | struct net_device *netdev = data; | |
6256 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
147b2c8c DD |
6257 | |
6258 | if (adapter->msix_entries) { | |
90da0669 BA |
6259 | int vector, msix_irq; |
6260 | ||
147b2c8c DD |
6261 | vector = 0; |
6262 | msix_irq = adapter->msix_entries[vector].vector; | |
6263 | disable_irq(msix_irq); | |
6264 | e1000_intr_msix_rx(msix_irq, netdev); | |
6265 | enable_irq(msix_irq); | |
6266 | ||
6267 | vector++; | |
6268 | msix_irq = adapter->msix_entries[vector].vector; | |
6269 | disable_irq(msix_irq); | |
6270 | e1000_intr_msix_tx(msix_irq, netdev); | |
6271 | enable_irq(msix_irq); | |
6272 | ||
6273 | vector++; | |
6274 | msix_irq = adapter->msix_entries[vector].vector; | |
6275 | disable_irq(msix_irq); | |
6276 | e1000_msix_other(msix_irq, netdev); | |
6277 | enable_irq(msix_irq); | |
6278 | } | |
6279 | ||
6280 | return IRQ_HANDLED; | |
6281 | } | |
6282 | ||
e921eb1a BA |
6283 | /** |
6284 | * e1000_netpoll | |
6285 | * @netdev: network interface device structure | |
6286 | * | |
bc7f75fa AK |
6287 | * Polling 'interrupt' - used by things like netconsole to send skbs |
6288 | * without having to re-enable interrupts. It's not called while | |
6289 | * the interrupt routine is executing. | |
6290 | */ | |
6291 | static void e1000_netpoll(struct net_device *netdev) | |
6292 | { | |
6293 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6294 | ||
147b2c8c DD |
6295 | switch (adapter->int_mode) { |
6296 | case E1000E_INT_MODE_MSIX: | |
6297 | e1000_intr_msix(adapter->pdev->irq, netdev); | |
6298 | break; | |
6299 | case E1000E_INT_MODE_MSI: | |
6300 | disable_irq(adapter->pdev->irq); | |
6301 | e1000_intr_msi(adapter->pdev->irq, netdev); | |
6302 | enable_irq(adapter->pdev->irq); | |
6303 | break; | |
e80bd1d1 | 6304 | default: /* E1000E_INT_MODE_LEGACY */ |
147b2c8c DD |
6305 | disable_irq(adapter->pdev->irq); |
6306 | e1000_intr(adapter->pdev->irq, netdev); | |
6307 | enable_irq(adapter->pdev->irq); | |
6308 | break; | |
6309 | } | |
bc7f75fa AK |
6310 | } |
6311 | #endif | |
6312 | ||
6313 | /** | |
6314 | * e1000_io_error_detected - called when PCI error is detected | |
6315 | * @pdev: Pointer to PCI device | |
6316 | * @state: The current pci connection state | |
6317 | * | |
6318 | * This function is called after a PCI bus error affecting | |
6319 | * this device has been detected. | |
6320 | */ | |
6321 | static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, | |
6322 | pci_channel_state_t state) | |
6323 | { | |
6324 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6325 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6326 | ||
6327 | netif_device_detach(netdev); | |
6328 | ||
c93b5a76 MM |
6329 | if (state == pci_channel_io_perm_failure) |
6330 | return PCI_ERS_RESULT_DISCONNECT; | |
6331 | ||
bc7f75fa AK |
6332 | if (netif_running(netdev)) |
6333 | e1000e_down(adapter); | |
6334 | pci_disable_device(pdev); | |
6335 | ||
6336 | /* Request a slot slot reset. */ | |
6337 | return PCI_ERS_RESULT_NEED_RESET; | |
6338 | } | |
6339 | ||
6340 | /** | |
6341 | * e1000_io_slot_reset - called after the pci bus has been reset. | |
6342 | * @pdev: Pointer to PCI device | |
6343 | * | |
6344 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
6345 | * resembles the first-half of the e1000_resume routine. | |
6346 | */ | |
6347 | static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) | |
6348 | { | |
6349 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6350 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6351 | struct e1000_hw *hw = &adapter->hw; | |
78cd29d5 | 6352 | u16 aspm_disable_flag = 0; |
6e4f6f6b | 6353 | int err; |
111b9dc5 | 6354 | pci_ers_result_t result; |
bc7f75fa | 6355 | |
78cd29d5 BA |
6356 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) |
6357 | aspm_disable_flag = PCIE_LINK_STATE_L0S; | |
6f461f6c | 6358 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) |
78cd29d5 BA |
6359 | aspm_disable_flag |= PCIE_LINK_STATE_L1; |
6360 | if (aspm_disable_flag) | |
6361 | e1000e_disable_aspm(pdev, aspm_disable_flag); | |
6362 | ||
f0f422e5 | 6363 | err = pci_enable_device_mem(pdev); |
6e4f6f6b | 6364 | if (err) { |
bc7f75fa AK |
6365 | dev_err(&pdev->dev, |
6366 | "Cannot re-enable PCI device after reset.\n"); | |
111b9dc5 JB |
6367 | result = PCI_ERS_RESULT_DISCONNECT; |
6368 | } else { | |
23606cf5 | 6369 | pdev->state_saved = true; |
111b9dc5 | 6370 | pci_restore_state(pdev); |
66148bab | 6371 | pci_set_master(pdev); |
bc7f75fa | 6372 | |
111b9dc5 JB |
6373 | pci_enable_wake(pdev, PCI_D3hot, 0); |
6374 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
bc7f75fa | 6375 | |
111b9dc5 JB |
6376 | e1000e_reset(adapter); |
6377 | ew32(WUS, ~0); | |
6378 | result = PCI_ERS_RESULT_RECOVERED; | |
6379 | } | |
bc7f75fa | 6380 | |
111b9dc5 JB |
6381 | pci_cleanup_aer_uncorrect_error_status(pdev); |
6382 | ||
6383 | return result; | |
bc7f75fa AK |
6384 | } |
6385 | ||
6386 | /** | |
6387 | * e1000_io_resume - called when traffic can start flowing again. | |
6388 | * @pdev: Pointer to PCI device | |
6389 | * | |
6390 | * This callback is called when the error recovery driver tells us that | |
6391 | * its OK to resume normal operation. Implementation resembles the | |
6392 | * second-half of the e1000_resume routine. | |
6393 | */ | |
6394 | static void e1000_io_resume(struct pci_dev *pdev) | |
6395 | { | |
6396 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6397 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6398 | ||
cd791618 | 6399 | e1000_init_manageability_pt(adapter); |
bc7f75fa AK |
6400 | |
6401 | if (netif_running(netdev)) { | |
6402 | if (e1000e_up(adapter)) { | |
6403 | dev_err(&pdev->dev, | |
6404 | "can't bring device back up after reset\n"); | |
6405 | return; | |
6406 | } | |
6407 | } | |
6408 | ||
6409 | netif_device_attach(netdev); | |
6410 | ||
e921eb1a | 6411 | /* If the controller has AMT, do not set DRV_LOAD until the interface |
bc7f75fa | 6412 | * is up. For all other cases, let the f/w know that the h/w is now |
ad68076e BA |
6413 | * under the control of the driver. |
6414 | */ | |
c43bc57e | 6415 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 6416 | e1000e_get_hw_control(adapter); |
bc7f75fa AK |
6417 | } |
6418 | ||
6419 | static void e1000_print_device_info(struct e1000_adapter *adapter) | |
6420 | { | |
6421 | struct e1000_hw *hw = &adapter->hw; | |
6422 | struct net_device *netdev = adapter->netdev; | |
073287c0 BA |
6423 | u32 ret_val; |
6424 | u8 pba_str[E1000_PBANUM_LENGTH]; | |
bc7f75fa AK |
6425 | |
6426 | /* print bus type/speed/width info */ | |
a5cc7642 | 6427 | e_info("(PCI Express:2.5GT/s:%s) %pM\n", |
44defeb3 JK |
6428 | /* bus width */ |
6429 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : | |
f0ff4398 | 6430 | "Width x1"), |
44defeb3 | 6431 | /* MAC address */ |
7c510e4b | 6432 | netdev->dev_addr); |
44defeb3 JK |
6433 | e_info("Intel(R) PRO/%s Network Connection\n", |
6434 | (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); | |
073287c0 BA |
6435 | ret_val = e1000_read_pba_string_generic(hw, pba_str, |
6436 | E1000_PBANUM_LENGTH); | |
6437 | if (ret_val) | |
f2315bf1 | 6438 | strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); |
073287c0 BA |
6439 | e_info("MAC: %d, PHY: %d, PBA No: %s\n", |
6440 | hw->mac.type, hw->phy.type, pba_str); | |
bc7f75fa AK |
6441 | } |
6442 | ||
10aa4c04 AK |
6443 | static void e1000_eeprom_checks(struct e1000_adapter *adapter) |
6444 | { | |
6445 | struct e1000_hw *hw = &adapter->hw; | |
6446 | int ret_val; | |
6447 | u16 buf = 0; | |
6448 | ||
6449 | if (hw->mac.type != e1000_82573) | |
6450 | return; | |
6451 | ||
6452 | ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); | |
e885d762 BA |
6453 | le16_to_cpus(&buf); |
6454 | if (!ret_val && (!(buf & (1 << 0)))) { | |
10aa4c04 | 6455 | /* Deep Smart Power Down (DSPD) */ |
6c2a9efa FP |
6456 | dev_warn(&adapter->pdev->dev, |
6457 | "Warning: detected DSPD enabled in EEPROM\n"); | |
10aa4c04 | 6458 | } |
10aa4c04 AK |
6459 | } |
6460 | ||
c8f44aff | 6461 | static int e1000_set_features(struct net_device *netdev, |
70495a50 | 6462 | netdev_features_t features) |
dc221294 BA |
6463 | { |
6464 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
c8f44aff | 6465 | netdev_features_t changed = features ^ netdev->features; |
dc221294 BA |
6466 | |
6467 | if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) | |
6468 | adapter->flags |= FLAG_TSO_FORCE; | |
6469 | ||
f646968f | 6470 | if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | |
cf955e6c BG |
6471 | NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | |
6472 | NETIF_F_RXALL))) | |
dc221294 BA |
6473 | return 0; |
6474 | ||
0184039a BG |
6475 | if (changed & NETIF_F_RXFCS) { |
6476 | if (features & NETIF_F_RXFCS) { | |
6477 | adapter->flags2 &= ~FLAG2_CRC_STRIPPING; | |
6478 | } else { | |
6479 | /* We need to take it back to defaults, which might mean | |
6480 | * stripping is still disabled at the adapter level. | |
6481 | */ | |
6482 | if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) | |
6483 | adapter->flags2 |= FLAG2_CRC_STRIPPING; | |
6484 | else | |
6485 | adapter->flags2 &= ~FLAG2_CRC_STRIPPING; | |
6486 | } | |
6487 | } | |
6488 | ||
70495a50 BA |
6489 | netdev->features = features; |
6490 | ||
dc221294 BA |
6491 | if (netif_running(netdev)) |
6492 | e1000e_reinit_locked(adapter); | |
6493 | else | |
6494 | e1000e_reset(adapter); | |
6495 | ||
6496 | return 0; | |
6497 | } | |
6498 | ||
651c2466 SH |
6499 | static const struct net_device_ops e1000e_netdev_ops = { |
6500 | .ndo_open = e1000_open, | |
6501 | .ndo_stop = e1000_close, | |
00829823 | 6502 | .ndo_start_xmit = e1000_xmit_frame, |
67fd4fcb | 6503 | .ndo_get_stats64 = e1000e_get_stats64, |
ef9b965a | 6504 | .ndo_set_rx_mode = e1000e_set_rx_mode, |
651c2466 SH |
6505 | .ndo_set_mac_address = e1000_set_mac, |
6506 | .ndo_change_mtu = e1000_change_mtu, | |
6507 | .ndo_do_ioctl = e1000_ioctl, | |
6508 | .ndo_tx_timeout = e1000_tx_timeout, | |
6509 | .ndo_validate_addr = eth_validate_addr, | |
6510 | ||
651c2466 SH |
6511 | .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, |
6512 | .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, | |
6513 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
6514 | .ndo_poll_controller = e1000_netpoll, | |
6515 | #endif | |
dc221294 | 6516 | .ndo_set_features = e1000_set_features, |
651c2466 SH |
6517 | }; |
6518 | ||
bc7f75fa AK |
6519 | /** |
6520 | * e1000_probe - Device Initialization Routine | |
6521 | * @pdev: PCI device information struct | |
6522 | * @ent: entry in e1000_pci_tbl | |
6523 | * | |
6524 | * Returns 0 on success, negative on failure | |
6525 | * | |
6526 | * e1000_probe initializes an adapter identified by a pci_dev structure. | |
6527 | * The OS initialization, configuring of the adapter private structure, | |
6528 | * and a hardware reset occur. | |
6529 | **/ | |
1dd06ae8 | 6530 | static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
bc7f75fa AK |
6531 | { |
6532 | struct net_device *netdev; | |
6533 | struct e1000_adapter *adapter; | |
6534 | struct e1000_hw *hw; | |
6535 | const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; | |
f47e81fc BB |
6536 | resource_size_t mmio_start, mmio_len; |
6537 | resource_size_t flash_start, flash_len; | |
bc7f75fa | 6538 | static int cards_found; |
78cd29d5 | 6539 | u16 aspm_disable_flag = 0; |
17e813ec | 6540 | int bars, i, err, pci_using_dac; |
bc7f75fa AK |
6541 | u16 eeprom_data = 0; |
6542 | u16 eeprom_apme_mask = E1000_EEPROM_APME; | |
6543 | ||
78cd29d5 BA |
6544 | if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) |
6545 | aspm_disable_flag = PCIE_LINK_STATE_L0S; | |
6f461f6c | 6546 | if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) |
78cd29d5 BA |
6547 | aspm_disable_flag |= PCIE_LINK_STATE_L1; |
6548 | if (aspm_disable_flag) | |
6549 | e1000e_disable_aspm(pdev, aspm_disable_flag); | |
6e4f6f6b | 6550 | |
f0f422e5 | 6551 | err = pci_enable_device_mem(pdev); |
bc7f75fa AK |
6552 | if (err) |
6553 | return err; | |
6554 | ||
6555 | pci_using_dac = 0; | |
0be3f55f | 6556 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
bc7f75fa | 6557 | if (!err) { |
0be3f55f | 6558 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
bc7f75fa AK |
6559 | if (!err) |
6560 | pci_using_dac = 1; | |
6561 | } else { | |
0be3f55f | 6562 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
bc7f75fa | 6563 | if (err) { |
0be3f55f NN |
6564 | err = dma_set_coherent_mask(&pdev->dev, |
6565 | DMA_BIT_MASK(32)); | |
bc7f75fa | 6566 | if (err) { |
f0ff4398 BA |
6567 | dev_err(&pdev->dev, |
6568 | "No usable DMA configuration, aborting\n"); | |
bc7f75fa AK |
6569 | goto err_dma; |
6570 | } | |
6571 | } | |
6572 | } | |
6573 | ||
17e813ec BA |
6574 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
6575 | err = pci_request_selected_regions_exclusive(pdev, bars, | |
6576 | e1000e_driver_name); | |
bc7f75fa AK |
6577 | if (err) |
6578 | goto err_pci_reg; | |
6579 | ||
68eac460 | 6580 | /* AER (Advanced Error Reporting) hooks */ |
19d5afd4 | 6581 | pci_enable_pcie_error_reporting(pdev); |
68eac460 | 6582 | |
bc7f75fa | 6583 | pci_set_master(pdev); |
438b365a BA |
6584 | /* PCI config space info */ |
6585 | err = pci_save_state(pdev); | |
6586 | if (err) | |
6587 | goto err_alloc_etherdev; | |
bc7f75fa AK |
6588 | |
6589 | err = -ENOMEM; | |
6590 | netdev = alloc_etherdev(sizeof(struct e1000_adapter)); | |
6591 | if (!netdev) | |
6592 | goto err_alloc_etherdev; | |
6593 | ||
bc7f75fa AK |
6594 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6595 | ||
f85e4dfa TH |
6596 | netdev->irq = pdev->irq; |
6597 | ||
bc7f75fa AK |
6598 | pci_set_drvdata(pdev, netdev); |
6599 | adapter = netdev_priv(netdev); | |
6600 | hw = &adapter->hw; | |
6601 | adapter->netdev = netdev; | |
6602 | adapter->pdev = pdev; | |
6603 | adapter->ei = ei; | |
6604 | adapter->pba = ei->pba; | |
6605 | adapter->flags = ei->flags; | |
eb7c3adb | 6606 | adapter->flags2 = ei->flags2; |
bc7f75fa AK |
6607 | adapter->hw.adapter = adapter; |
6608 | adapter->hw.mac.type = ei->mac; | |
2adc55c9 | 6609 | adapter->max_hw_frame_size = ei->max_hw_frame_size; |
b3f4d599 | 6610 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
bc7f75fa AK |
6611 | |
6612 | mmio_start = pci_resource_start(pdev, 0); | |
6613 | mmio_len = pci_resource_len(pdev, 0); | |
6614 | ||
6615 | err = -EIO; | |
6616 | adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); | |
6617 | if (!adapter->hw.hw_addr) | |
6618 | goto err_ioremap; | |
6619 | ||
6620 | if ((adapter->flags & FLAG_HAS_FLASH) && | |
6621 | (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { | |
6622 | flash_start = pci_resource_start(pdev, 1); | |
6623 | flash_len = pci_resource_len(pdev, 1); | |
6624 | adapter->hw.flash_address = ioremap(flash_start, flash_len); | |
6625 | if (!adapter->hw.flash_address) | |
6626 | goto err_flashmap; | |
6627 | } | |
6628 | ||
d495bcb8 BA |
6629 | /* Set default EEE advertisement */ |
6630 | if (adapter->flags2 & FLAG2_HAS_EEE) | |
6631 | adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; | |
6632 | ||
bc7f75fa | 6633 | /* construct the net_device struct */ |
e80bd1d1 | 6634 | netdev->netdev_ops = &e1000e_netdev_ops; |
bc7f75fa | 6635 | e1000e_set_ethtool_ops(netdev); |
e80bd1d1 | 6636 | netdev->watchdog_timeo = 5 * HZ; |
c58c8a78 | 6637 | netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); |
f2315bf1 | 6638 | strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); |
bc7f75fa AK |
6639 | |
6640 | netdev->mem_start = mmio_start; | |
6641 | netdev->mem_end = mmio_start + mmio_len; | |
6642 | ||
6643 | adapter->bd_number = cards_found++; | |
6644 | ||
4662e82b BA |
6645 | e1000e_check_options(adapter); |
6646 | ||
bc7f75fa AK |
6647 | /* setup adapter struct */ |
6648 | err = e1000_sw_init(adapter); | |
6649 | if (err) | |
6650 | goto err_sw_init; | |
6651 | ||
bc7f75fa AK |
6652 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); |
6653 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
6654 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
6655 | ||
69e3fd8c | 6656 | err = ei->get_variants(adapter); |
bc7f75fa AK |
6657 | if (err) |
6658 | goto err_hw_init; | |
6659 | ||
4a770358 BA |
6660 | if ((adapter->flags & FLAG_IS_ICH) && |
6661 | (adapter->flags & FLAG_READ_ONLY_NVM)) | |
6662 | e1000e_write_protect_nvm_ich8lan(&adapter->hw); | |
6663 | ||
bc7f75fa AK |
6664 | hw->mac.ops.get_bus_info(&adapter->hw); |
6665 | ||
318a94d6 | 6666 | adapter->hw.phy.autoneg_wait_to_complete = 0; |
bc7f75fa AK |
6667 | |
6668 | /* Copper options */ | |
318a94d6 | 6669 | if (adapter->hw.phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
6670 | adapter->hw.phy.mdix = AUTO_ALL_MODES; |
6671 | adapter->hw.phy.disable_polarity_correction = 0; | |
6672 | adapter->hw.phy.ms_type = e1000_ms_hw_default; | |
6673 | } | |
6674 | ||
470a5420 | 6675 | if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) |
185095fb BA |
6676 | dev_info(&pdev->dev, |
6677 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
bc7f75fa | 6678 | |
dc221294 BA |
6679 | /* Set initial default active device features */ |
6680 | netdev->features = (NETIF_F_SG | | |
f646968f PM |
6681 | NETIF_F_HW_VLAN_CTAG_RX | |
6682 | NETIF_F_HW_VLAN_CTAG_TX | | |
dc221294 BA |
6683 | NETIF_F_TSO | |
6684 | NETIF_F_TSO6 | | |
70495a50 | 6685 | NETIF_F_RXHASH | |
dc221294 BA |
6686 | NETIF_F_RXCSUM | |
6687 | NETIF_F_HW_CSUM); | |
6688 | ||
6689 | /* Set user-changeable features (subset of all device features) */ | |
6690 | netdev->hw_features = netdev->features; | |
0184039a | 6691 | netdev->hw_features |= NETIF_F_RXFCS; |
943146de | 6692 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
cf955e6c | 6693 | netdev->hw_features |= NETIF_F_RXALL; |
bc7f75fa AK |
6694 | |
6695 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) | |
f646968f | 6696 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
bc7f75fa | 6697 | |
dc221294 BA |
6698 | netdev->vlan_features |= (NETIF_F_SG | |
6699 | NETIF_F_TSO | | |
6700 | NETIF_F_TSO6 | | |
6701 | NETIF_F_HW_CSUM); | |
a5136e23 | 6702 | |
ef9b965a JB |
6703 | netdev->priv_flags |= IFF_UNICAST_FLT; |
6704 | ||
7b872a55 | 6705 | if (pci_using_dac) { |
bc7f75fa | 6706 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
6707 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
6708 | } | |
bc7f75fa | 6709 | |
bc7f75fa AK |
6710 | if (e1000e_enable_mng_pass_thru(&adapter->hw)) |
6711 | adapter->flags |= FLAG_MNG_PT_ENABLED; | |
6712 | ||
e921eb1a | 6713 | /* before reading the NVM, reset the controller to |
ad68076e BA |
6714 | * put the device in a known good starting state |
6715 | */ | |
bc7f75fa AK |
6716 | adapter->hw.mac.ops.reset_hw(&adapter->hw); |
6717 | ||
e921eb1a | 6718 | /* systems with ASPM and others may see the checksum fail on the first |
bc7f75fa AK |
6719 | * attempt. Let's give it a few tries |
6720 | */ | |
6721 | for (i = 0;; i++) { | |
6722 | if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) | |
6723 | break; | |
6724 | if (i == 2) { | |
185095fb | 6725 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); |
bc7f75fa AK |
6726 | err = -EIO; |
6727 | goto err_eeprom; | |
6728 | } | |
6729 | } | |
6730 | ||
10aa4c04 AK |
6731 | e1000_eeprom_checks(adapter); |
6732 | ||
608f8a0d | 6733 | /* copy the MAC address */ |
bc7f75fa | 6734 | if (e1000e_read_mac_addr(&adapter->hw)) |
185095fb BA |
6735 | dev_err(&pdev->dev, |
6736 | "NVM Read Error while reading MAC address\n"); | |
bc7f75fa AK |
6737 | |
6738 | memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); | |
bc7f75fa | 6739 | |
aaeb6cdf | 6740 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
185095fb | 6741 | dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", |
aaeb6cdf | 6742 | netdev->dev_addr); |
bc7f75fa AK |
6743 | err = -EIO; |
6744 | goto err_eeprom; | |
6745 | } | |
6746 | ||
6747 | init_timer(&adapter->watchdog_timer); | |
c061b18d | 6748 | adapter->watchdog_timer.function = e1000_watchdog; |
53aa82da | 6749 | adapter->watchdog_timer.data = (unsigned long)adapter; |
bc7f75fa AK |
6750 | |
6751 | init_timer(&adapter->phy_info_timer); | |
c061b18d | 6752 | adapter->phy_info_timer.function = e1000_update_phy_info; |
53aa82da | 6753 | adapter->phy_info_timer.data = (unsigned long)adapter; |
bc7f75fa AK |
6754 | |
6755 | INIT_WORK(&adapter->reset_task, e1000_reset_task); | |
6756 | INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); | |
a8f88ff5 JB |
6757 | INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); |
6758 | INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); | |
41cec6f1 | 6759 | INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); |
bc7f75fa | 6760 | |
bc7f75fa AK |
6761 | /* Initialize link parameters. User can change them with ethtool */ |
6762 | adapter->hw.mac.autoneg = 1; | |
3db1cd5c | 6763 | adapter->fc_autoneg = true; |
5c48ef3e BA |
6764 | adapter->hw.fc.requested_mode = e1000_fc_default; |
6765 | adapter->hw.fc.current_mode = e1000_fc_default; | |
bc7f75fa AK |
6766 | adapter->hw.phy.autoneg_advertised = 0x2f; |
6767 | ||
e921eb1a | 6768 | /* Initial Wake on LAN setting - If APM wake is enabled in |
bc7f75fa AK |
6769 | * the EEPROM, enable the ACPI Magic Packet filter |
6770 | */ | |
6771 | if (adapter->flags & FLAG_APME_IN_WUC) { | |
6772 | /* APME bit in EEPROM is mapped to WUC.APME */ | |
6773 | eeprom_data = er32(WUC); | |
6774 | eeprom_apme_mask = E1000_WUC_APME; | |
4def99bb BA |
6775 | if ((hw->mac.type > e1000_ich10lan) && |
6776 | (eeprom_data & E1000_WUC_PHY_WAKE)) | |
a4f58f54 | 6777 | adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; |
bc7f75fa AK |
6778 | } else if (adapter->flags & FLAG_APME_IN_CTRL3) { |
6779 | if (adapter->flags & FLAG_APME_CHECK_PORT_B && | |
6780 | (adapter->hw.bus.func == 1)) | |
3d3a1676 BA |
6781 | e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B, |
6782 | 1, &eeprom_data); | |
bc7f75fa | 6783 | else |
3d3a1676 BA |
6784 | e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A, |
6785 | 1, &eeprom_data); | |
bc7f75fa AK |
6786 | } |
6787 | ||
6788 | /* fetch WoL from EEPROM */ | |
6789 | if (eeprom_data & eeprom_apme_mask) | |
6790 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
6791 | ||
e921eb1a | 6792 | /* now that we have the eeprom settings, apply the special cases |
bc7f75fa AK |
6793 | * where the eeprom may be wrong or the board simply won't support |
6794 | * wake on lan on a particular port | |
6795 | */ | |
6796 | if (!(adapter->flags & FLAG_HAS_WOL)) | |
6797 | adapter->eeprom_wol = 0; | |
6798 | ||
6799 | /* initialize the wol settings based on the eeprom settings */ | |
6800 | adapter->wol = adapter->eeprom_wol; | |
66148bab KK |
6801 | |
6802 | /* make sure adapter isn't asleep if manageability is enabled */ | |
6803 | if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || | |
6804 | (hw->mac.ops.check_mng_mode(hw))) | |
6805 | device_wakeup_enable(&pdev->dev); | |
bc7f75fa | 6806 | |
84527590 BA |
6807 | /* save off EEPROM version number */ |
6808 | e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); | |
6809 | ||
bc7f75fa AK |
6810 | /* reset the hardware with the new settings */ |
6811 | e1000e_reset(adapter); | |
6812 | ||
e921eb1a | 6813 | /* If the controller has AMT, do not set DRV_LOAD until the interface |
bc7f75fa | 6814 | * is up. For all other cases, let the f/w know that the h/w is now |
ad68076e BA |
6815 | * under the control of the driver. |
6816 | */ | |
c43bc57e | 6817 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 6818 | e1000e_get_hw_control(adapter); |
bc7f75fa | 6819 | |
f2315bf1 | 6820 | strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); |
bc7f75fa AK |
6821 | err = register_netdev(netdev); |
6822 | if (err) | |
6823 | goto err_register; | |
6824 | ||
9c563d20 JB |
6825 | /* carrier off reporting is important to ethtool even BEFORE open */ |
6826 | netif_carrier_off(netdev); | |
6827 | ||
d89777bf BA |
6828 | /* init PTP hardware clock */ |
6829 | e1000e_ptp_init(adapter); | |
6830 | ||
bc7f75fa AK |
6831 | e1000_print_device_info(adapter); |
6832 | ||
f3ec4f87 AS |
6833 | if (pci_dev_run_wake(pdev)) |
6834 | pm_runtime_put_noidle(&pdev->dev); | |
23606cf5 | 6835 | |
bc7f75fa AK |
6836 | return 0; |
6837 | ||
6838 | err_register: | |
c43bc57e | 6839 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 6840 | e1000e_release_hw_control(adapter); |
bc7f75fa | 6841 | err_eeprom: |
470a5420 | 6842 | if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) |
bc7f75fa | 6843 | e1000_phy_hw_reset(&adapter->hw); |
c43bc57e | 6844 | err_hw_init: |
bc7f75fa AK |
6845 | kfree(adapter->tx_ring); |
6846 | kfree(adapter->rx_ring); | |
6847 | err_sw_init: | |
c43bc57e JB |
6848 | if (adapter->hw.flash_address) |
6849 | iounmap(adapter->hw.flash_address); | |
e82f54ba | 6850 | e1000e_reset_interrupt_capability(adapter); |
c43bc57e | 6851 | err_flashmap: |
bc7f75fa AK |
6852 | iounmap(adapter->hw.hw_addr); |
6853 | err_ioremap: | |
6854 | free_netdev(netdev); | |
6855 | err_alloc_etherdev: | |
f0f422e5 | 6856 | pci_release_selected_regions(pdev, |
f0ff4398 | 6857 | pci_select_bars(pdev, IORESOURCE_MEM)); |
bc7f75fa AK |
6858 | err_pci_reg: |
6859 | err_dma: | |
6860 | pci_disable_device(pdev); | |
6861 | return err; | |
6862 | } | |
6863 | ||
6864 | /** | |
6865 | * e1000_remove - Device Removal Routine | |
6866 | * @pdev: PCI device information struct | |
6867 | * | |
6868 | * e1000_remove is called by the PCI subsystem to alert the driver | |
6869 | * that it should release a PCI device. The could be caused by a | |
6870 | * Hot-Plug event, or because the driver is going to be removed from | |
6871 | * memory. | |
6872 | **/ | |
9f9a12f8 | 6873 | static void e1000_remove(struct pci_dev *pdev) |
bc7f75fa AK |
6874 | { |
6875 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6876 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
23606cf5 RW |
6877 | bool down = test_bit(__E1000_DOWN, &adapter->state); |
6878 | ||
d89777bf BA |
6879 | e1000e_ptp_remove(adapter); |
6880 | ||
e921eb1a | 6881 | /* The timers may be rescheduled, so explicitly disable them |
23f333a2 | 6882 | * from being rescheduled. |
ad68076e | 6883 | */ |
23606cf5 RW |
6884 | if (!down) |
6885 | set_bit(__E1000_DOWN, &adapter->state); | |
bc7f75fa AK |
6886 | del_timer_sync(&adapter->watchdog_timer); |
6887 | del_timer_sync(&adapter->phy_info_timer); | |
6888 | ||
41cec6f1 BA |
6889 | cancel_work_sync(&adapter->reset_task); |
6890 | cancel_work_sync(&adapter->watchdog_task); | |
6891 | cancel_work_sync(&adapter->downshift_task); | |
6892 | cancel_work_sync(&adapter->update_phy_task); | |
6893 | cancel_work_sync(&adapter->print_hang_task); | |
bc7f75fa | 6894 | |
b67e1913 BA |
6895 | if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { |
6896 | cancel_work_sync(&adapter->tx_hwtstamp_work); | |
6897 | if (adapter->tx_hwtstamp_skb) { | |
6898 | dev_kfree_skb_any(adapter->tx_hwtstamp_skb); | |
6899 | adapter->tx_hwtstamp_skb = NULL; | |
6900 | } | |
6901 | } | |
6902 | ||
17f208de BA |
6903 | if (!(netdev->flags & IFF_UP)) |
6904 | e1000_power_down_phy(adapter); | |
6905 | ||
23606cf5 RW |
6906 | /* Don't lie to e1000_close() down the road. */ |
6907 | if (!down) | |
6908 | clear_bit(__E1000_DOWN, &adapter->state); | |
17f208de BA |
6909 | unregister_netdev(netdev); |
6910 | ||
f3ec4f87 AS |
6911 | if (pci_dev_run_wake(pdev)) |
6912 | pm_runtime_get_noresume(&pdev->dev); | |
23606cf5 | 6913 | |
e921eb1a | 6914 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
ad68076e BA |
6915 | * would have already happened in close and is redundant. |
6916 | */ | |
31dbe5b4 | 6917 | e1000e_release_hw_control(adapter); |
bc7f75fa | 6918 | |
4662e82b | 6919 | e1000e_reset_interrupt_capability(adapter); |
bc7f75fa AK |
6920 | kfree(adapter->tx_ring); |
6921 | kfree(adapter->rx_ring); | |
6922 | ||
6923 | iounmap(adapter->hw.hw_addr); | |
6924 | if (adapter->hw.flash_address) | |
6925 | iounmap(adapter->hw.flash_address); | |
f0f422e5 | 6926 | pci_release_selected_regions(pdev, |
f0ff4398 | 6927 | pci_select_bars(pdev, IORESOURCE_MEM)); |
bc7f75fa AK |
6928 | |
6929 | free_netdev(netdev); | |
6930 | ||
111b9dc5 | 6931 | /* AER disable */ |
19d5afd4 | 6932 | pci_disable_pcie_error_reporting(pdev); |
111b9dc5 | 6933 | |
bc7f75fa AK |
6934 | pci_disable_device(pdev); |
6935 | } | |
6936 | ||
6937 | /* PCI Error Recovery (ERS) */ | |
3646f0e5 | 6938 | static const struct pci_error_handlers e1000_err_handler = { |
bc7f75fa AK |
6939 | .error_detected = e1000_io_error_detected, |
6940 | .slot_reset = e1000_io_slot_reset, | |
6941 | .resume = e1000_io_resume, | |
6942 | }; | |
6943 | ||
a3aa1884 | 6944 | static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = { |
bc7f75fa AK |
6945 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, |
6946 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, | |
6947 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, | |
c29c3ba5 BA |
6948 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), |
6949 | board_82571 }, | |
bc7f75fa AK |
6950 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, |
6951 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, | |
040babf9 AK |
6952 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, |
6953 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, | |
6954 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, | |
ad68076e | 6955 | |
bc7f75fa AK |
6956 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, |
6957 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, | |
6958 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, | |
6959 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, | |
ad68076e | 6960 | |
bc7f75fa AK |
6961 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, |
6962 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, | |
6963 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, | |
ad68076e | 6964 | |
4662e82b | 6965 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, |
bef28b11 | 6966 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, |
8c81c9c3 | 6967 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, |
4662e82b | 6968 | |
bc7f75fa AK |
6969 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), |
6970 | board_80003es2lan }, | |
6971 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), | |
6972 | board_80003es2lan }, | |
6973 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), | |
6974 | board_80003es2lan }, | |
6975 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), | |
6976 | board_80003es2lan }, | |
ad68076e | 6977 | |
bc7f75fa AK |
6978 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, |
6979 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, | |
6980 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, | |
6981 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, | |
6982 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, | |
6983 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, | |
6984 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, | |
9e135a2e | 6985 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, |
ad68076e | 6986 | |
bc7f75fa AK |
6987 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, |
6988 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, | |
6989 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, | |
6990 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, | |
6991 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, | |
2f15f9d6 | 6992 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, |
97ac8cae BA |
6993 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, |
6994 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, | |
6995 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, | |
6996 | ||
6997 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, | |
6998 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, | |
6999 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, | |
bc7f75fa | 7000 | |
f4187b56 BA |
7001 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, |
7002 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, | |
10df0b91 | 7003 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, |
f4187b56 | 7004 | |
a4f58f54 BA |
7005 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, |
7006 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, | |
7007 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, | |
7008 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, | |
7009 | ||
d3738bb8 BA |
7010 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, |
7011 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, | |
7012 | ||
2fbe4526 BA |
7013 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, |
7014 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, | |
16e310ae BA |
7015 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, |
7016 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, | |
91a3d82f BA |
7017 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, |
7018 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, | |
7019 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, | |
7020 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, | |
2fbe4526 | 7021 | |
f36bb6ca | 7022 | { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ |
bc7f75fa AK |
7023 | }; |
7024 | MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); | |
7025 | ||
aa338601 | 7026 | #ifdef CONFIG_PM |
23606cf5 | 7027 | static const struct dev_pm_ops e1000_pm_ops = { |
a0340162 | 7028 | SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume) |
17e813ec BA |
7029 | SET_RUNTIME_PM_OPS(e1000_runtime_suspend, e1000_runtime_resume, |
7030 | e1000_idle) | |
23606cf5 | 7031 | }; |
e50208a0 | 7032 | #endif |
23606cf5 | 7033 | |
bc7f75fa AK |
7034 | /* PCI Device API Driver */ |
7035 | static struct pci_driver e1000_driver = { | |
7036 | .name = e1000e_driver_name, | |
7037 | .id_table = e1000_pci_tbl, | |
7038 | .probe = e1000_probe, | |
9f9a12f8 | 7039 | .remove = e1000_remove, |
aa338601 | 7040 | #ifdef CONFIG_PM |
f36bb6ca BA |
7041 | .driver = { |
7042 | .pm = &e1000_pm_ops, | |
7043 | }, | |
bc7f75fa AK |
7044 | #endif |
7045 | .shutdown = e1000_shutdown, | |
7046 | .err_handler = &e1000_err_handler | |
7047 | }; | |
7048 | ||
7049 | /** | |
7050 | * e1000_init_module - Driver Registration Routine | |
7051 | * | |
7052 | * e1000_init_module is the first routine called when the driver is | |
7053 | * loaded. All it does is register with the PCI subsystem. | |
7054 | **/ | |
7055 | static int __init e1000_init_module(void) | |
7056 | { | |
7057 | int ret; | |
8544b9f7 BA |
7058 | pr_info("Intel(R) PRO/1000 Network Driver - %s\n", |
7059 | e1000e_driver_version); | |
bf67044b | 7060 | pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n"); |
bc7f75fa | 7061 | ret = pci_register_driver(&e1000_driver); |
53ec5498 | 7062 | |
bc7f75fa AK |
7063 | return ret; |
7064 | } | |
7065 | module_init(e1000_init_module); | |
7066 | ||
7067 | /** | |
7068 | * e1000_exit_module - Driver Exit Cleanup Routine | |
7069 | * | |
7070 | * e1000_exit_module is called just before the driver is removed | |
7071 | * from memory. | |
7072 | **/ | |
7073 | static void __exit e1000_exit_module(void) | |
7074 | { | |
7075 | pci_unregister_driver(&e1000_driver); | |
7076 | } | |
7077 | module_exit(e1000_exit_module); | |
7078 | ||
bc7f75fa AK |
7079 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
7080 | MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); | |
7081 | MODULE_LICENSE("GPL"); | |
7082 | MODULE_VERSION(DRV_VERSION); | |
7083 | ||
06c24b91 | 7084 | /* netdev.c */ |