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7daa6bf3 JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
4fc8c676 | 4 | * Copyright(c) 2013 - 2017 Intel Corporation. |
7daa6bf3 JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
7daa6bf3 JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
27 | #ifndef _I40E_H_ | |
28 | #define _I40E_H_ | |
29 | ||
30 | #include <net/tcp.h> | |
8144f0f7 | 31 | #include <net/udp.h> |
7daa6bf3 JB |
32 | #include <linux/types.h> |
33 | #include <linux/errno.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/aer.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/ioport.h> | |
2bc7ee8a | 39 | #include <linux/iommu.h> |
7daa6bf3 JB |
40 | #include <linux/slab.h> |
41 | #include <linux/list.h> | |
278e7d0b | 42 | #include <linux/hashtable.h> |
7daa6bf3 JB |
43 | #include <linux/string.h> |
44 | #include <linux/in.h> | |
45 | #include <linux/ip.h> | |
7daa6bf3 JB |
46 | #include <linux/sctp.h> |
47 | #include <linux/pkt_sched.h> | |
48 | #include <linux/ipv6.h> | |
7daa6bf3 JB |
49 | #include <net/checksum.h> |
50 | #include <net/ip6_checksum.h> | |
51 | #include <linux/ethtool.h> | |
52 | #include <linux/if_vlan.h> | |
51616018 | 53 | #include <linux/if_bridge.h> |
beb0dff1 JK |
54 | #include <linux/clocksource.h> |
55 | #include <linux/net_tstamp.h> | |
56 | #include <linux/ptp_clock_kernel.h> | |
7daa6bf3 JB |
57 | #include "i40e_type.h" |
58 | #include "i40e_prototype.h" | |
e3219ce6 | 59 | #include "i40e_client.h" |
55cdfd48 | 60 | #include <linux/avf/virtchnl.h> |
7daa6bf3 JB |
61 | #include "i40e_virtchnl_pf.h" |
62 | #include "i40e_txrx.h" | |
4e3b35b0 | 63 | #include "i40e_dcb.h" |
7daa6bf3 JB |
64 | |
65 | /* Useful i40e defaults */ | |
c57c9959 JK |
66 | #define I40E_MAX_VEB 16 |
67 | ||
68 | #define I40E_MAX_NUM_DESCRIPTORS 4096 | |
69 | #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) | |
70 | #define I40E_DEFAULT_NUM_DESCRIPTORS 512 | |
71 | #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 | |
72 | #define I40E_MIN_NUM_DESCRIPTORS 64 | |
73 | #define I40E_MIN_MSIX 2 | |
74 | #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ | |
7ac4b5c6 | 75 | #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ |
e25d00b8 ASJ |
76 | /* max 16 qps */ |
77 | #define i40e_default_queues_per_vmdq(pf) \ | |
d36e41dc | 78 | (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) |
c57c9959 | 79 | #define I40E_DEFAULT_QUEUES_PER_VF 4 |
a3f5aa90 | 80 | #define I40E_MAX_VF_QUEUES 16 |
c57c9959 | 81 | #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ |
e25d00b8 | 82 | #define i40e_pf_get_max_q_per_tc(pf) \ |
d36e41dc | 83 | (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) |
c57c9959 JK |
84 | #define I40E_FDIR_RING 0 |
85 | #define I40E_FDIR_RING_COUNT 32 | |
c57c9959 JK |
86 | #define I40E_MAX_AQ_BUF_SIZE 4096 |
87 | #define I40E_AQ_LEN 256 | |
88 | #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ | |
89 | #define I40E_MAX_USER_PRIORITY 8 | |
ea6acb7e | 90 | #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) |
c57c9959 JK |
91 | #define I40E_DEFAULT_MSG_ENABLE 4 |
92 | #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 | |
93 | #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) | |
7daa6bf3 | 94 | |
c57c9959 JK |
95 | #define I40E_NVM_VERSION_LO_SHIFT 0 |
96 | #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) | |
97 | #define I40E_NVM_VERSION_HI_SHIFT 12 | |
98 | #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) | |
99 | #define I40E_OEM_VER_BUILD_MASK 0xffff | |
100 | #define I40E_OEM_VER_PATCH_MASK 0xff | |
101 | #define I40E_OEM_VER_BUILD_SHIFT 8 | |
102 | #define I40E_OEM_VER_SHIFT 24 | |
06c0e39b KS |
103 | #define I40E_PHY_DEBUG_ALL \ |
104 | (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ | |
105 | I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) | |
fe310704 | 106 | |
5bbb2e20 FS |
107 | #define I40E_OEM_EETRACK_ID 0xffffffff |
108 | #define I40E_OEM_GEN_SHIFT 24 | |
109 | #define I40E_OEM_SNAP_MASK 0x00ff0000 | |
110 | #define I40E_OEM_SNAP_SHIFT 16 | |
111 | #define I40E_OEM_RELEASE_MASK 0x0000ffff | |
112 | ||
fe310704 | 113 | /* The values in here are decimal coded as hex as is the case in the NVM map*/ |
c57c9959 JK |
114 | #define I40E_CURRENT_NVM_VERSION_HI 0x2 |
115 | #define I40E_CURRENT_NVM_VERSION_LO 0x40 | |
fe310704 | 116 | |
c57c9959 | 117 | #define I40E_RX_DESC(R, i) \ |
bec60fc4 | 118 | (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) |
c57c9959 | 119 | #define I40E_TX_DESC(R, i) \ |
7daa6bf3 | 120 | (&(((struct i40e_tx_desc *)((R)->desc))[i])) |
c57c9959 | 121 | #define I40E_TX_CTXTDESC(R, i) \ |
7daa6bf3 | 122 | (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) |
c57c9959 | 123 | #define I40E_TX_FDIRDESC(R, i) \ |
7daa6bf3 JB |
124 | (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) |
125 | ||
126 | /* default to trying for four seconds */ | |
c57c9959 | 127 | #define I40E_TRY_LINK_TIMEOUT (4 * HZ) |
7daa6bf3 JB |
128 | |
129 | /* driver state flags */ | |
130 | enum i40e_state_t { | |
131 | __I40E_TESTING, | |
132 | __I40E_CONFIG_BUSY, | |
133 | __I40E_CONFIG_DONE, | |
134 | __I40E_DOWN, | |
7daa6bf3 JB |
135 | __I40E_SERVICE_SCHED, |
136 | __I40E_ADMINQ_EVENT_PENDING, | |
137 | __I40E_MDD_EVENT_PENDING, | |
138 | __I40E_VFLR_EVENT_PENDING, | |
139 | __I40E_RESET_RECOVERY_PENDING, | |
c17401a1 | 140 | __I40E_MISC_IRQ_REQUESTED, |
7daa6bf3 JB |
141 | __I40E_RESET_INTR_RECEIVED, |
142 | __I40E_REINIT_REQUESTED, | |
143 | __I40E_PF_RESET_REQUESTED, | |
144 | __I40E_CORE_RESET_REQUESTED, | |
145 | __I40E_GLOBAL_RESET_REQUESTED, | |
7823fe34 | 146 | __I40E_EMP_RESET_REQUESTED, |
9df42d1a | 147 | __I40E_EMP_RESET_INTR_RECEIVED, |
9007bccd | 148 | __I40E_SUSPENDED, |
9ce34f02 | 149 | __I40E_PTP_TX_IN_PROGRESS, |
4eb3f768 | 150 | __I40E_BAD_EEPROM, |
b5d06f05 | 151 | __I40E_DOWN_REQUESTED, |
1e1be8f6 | 152 | __I40E_FD_FLUSH_REQUESTED, |
a316f651 | 153 | __I40E_RESET_FAILED, |
3480756f | 154 | __I40E_PORT_SUSPENDED, |
3ba9bcb4 | 155 | __I40E_VF_DISABLE, |
0da36b97 JK |
156 | /* This must be last as it determines the size of the BITMAP */ |
157 | __I40E_STATE_SIZE__, | |
7daa6bf3 JB |
158 | }; |
159 | ||
d19cb64b JK |
160 | /* VSI state flags */ |
161 | enum i40e_vsi_state_t { | |
162 | __I40E_VSI_DOWN, | |
163 | __I40E_VSI_NEEDS_RESTART, | |
164 | __I40E_VSI_SYNCING_FILTERS, | |
165 | __I40E_VSI_OVERFLOW_PROMISC, | |
166 | __I40E_VSI_REINIT_REQUESTED, | |
167 | __I40E_VSI_DOWN_REQUESTED, | |
0da36b97 JK |
168 | /* This must be last as it determines the size of the BITMAP */ |
169 | __I40E_VSI_STATE_SIZE__, | |
d19cb64b JK |
170 | }; |
171 | ||
7daa6bf3 JB |
172 | enum i40e_interrupt_policy { |
173 | I40E_INTERRUPT_BEST_CASE, | |
174 | I40E_INTERRUPT_MEDIUM, | |
175 | I40E_INTERRUPT_LOWEST | |
176 | }; | |
177 | ||
178 | struct i40e_lump_tracking { | |
179 | u16 num_entries; | |
180 | u16 search_hint; | |
181 | u16 list[0]; | |
182 | #define I40E_PILE_VALID_BIT 0x8000 | |
e3219ce6 | 183 | #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) |
7daa6bf3 JB |
184 | }; |
185 | ||
186 | #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 | |
55a5e60b ASJ |
187 | #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 |
188 | #define I40E_FDIR_BUFFER_FULL_MARGIN 10 | |
12957388 | 189 | #define I40E_FDIR_BUFFER_HEAD_ROOM 32 |
04294e38 | 190 | #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) |
55a5e60b | 191 | |
c57c9959 JK |
192 | #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) |
193 | #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) | |
194 | #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) | |
b29e13bb | 195 | |
433c47de ASJ |
196 | enum i40e_fd_stat_idx { |
197 | I40E_FD_STAT_ATR, | |
198 | I40E_FD_STAT_SB, | |
60ccd45c | 199 | I40E_FD_STAT_ATR_TUNNEL, |
433c47de ASJ |
200 | I40E_FD_STAT_PF_COUNT |
201 | }; | |
202 | #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) | |
203 | #define I40E_FD_ATR_STAT_IDX(pf_id) \ | |
204 | (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) | |
205 | #define I40E_FD_SB_STAT_IDX(pf_id) \ | |
206 | (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) | |
60ccd45c ASJ |
207 | #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ |
208 | (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) | |
433c47de | 209 | |
e793095e JK |
210 | /* The following structure contains the data parsed from the user-defined |
211 | * field of the ethtool_rx_flow_spec structure. | |
212 | */ | |
213 | struct i40e_rx_flow_userdef { | |
214 | bool flex_filter; | |
215 | u16 flex_word; | |
216 | u16 flex_offset; | |
217 | }; | |
218 | ||
17a73f6b JG |
219 | struct i40e_fdir_filter { |
220 | struct hlist_node fdir_node; | |
221 | /* filter ipnut set */ | |
222 | u8 flow_type; | |
223 | u8 ip4_proto; | |
04b73bd7 | 224 | /* TX packet view of src and dst */ |
8ce43dce JK |
225 | __be32 dst_ip; |
226 | __be32 src_ip; | |
17a73f6b JG |
227 | __be16 src_port; |
228 | __be16 dst_port; | |
229 | __be32 sctp_v_tag; | |
0e588de1 JK |
230 | |
231 | /* Flexible data to match within the packet payload */ | |
232 | __be16 flex_word; | |
233 | u16 flex_offset; | |
234 | bool flex_filter; | |
235 | ||
17a73f6b | 236 | /* filter control */ |
7daa6bf3 JB |
237 | u16 q_index; |
238 | u8 flex_off; | |
239 | u8 pctype; | |
240 | u16 dest_vsi; | |
241 | u8 dest_ctl; | |
242 | u8 fd_status; | |
243 | u16 cnt_index; | |
244 | u32 fd_id; | |
7daa6bf3 JB |
245 | }; |
246 | ||
4e3b35b0 NP |
247 | #define I40E_ETH_P_LLDP 0x88cc |
248 | ||
7daa6bf3 JB |
249 | #define I40E_DCB_PRIO_TYPE_STRICT 0 |
250 | #define I40E_DCB_PRIO_TYPE_ETS 1 | |
251 | #define I40E_DCB_STRICT_PRIO_CREDITS 127 | |
7daa6bf3 JB |
252 | /* DCB per TC information data structure */ |
253 | struct i40e_tc_info { | |
254 | u16 qoffset; /* Queue offset from base queue */ | |
255 | u16 qcount; /* Total Queues */ | |
256 | u8 netdev_tc; /* Netdev TC index if netdev associated */ | |
257 | }; | |
258 | ||
259 | /* TC configuration data structure */ | |
260 | struct i40e_tc_configuration { | |
261 | u8 numtc; /* Total number of enabled TCs */ | |
262 | u8 enabled_tc; /* TC map */ | |
263 | struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; | |
264 | }; | |
265 | ||
6a899024 | 266 | struct i40e_udp_port_config { |
fe0b0cd9 | 267 | /* AdminQ command interface expects port number in Host byte order */ |
27826fd5 | 268 | u16 port; |
6a899024 SA |
269 | u8 type; |
270 | }; | |
271 | ||
0e588de1 JK |
272 | /* macros related to FLX_PIT */ |
273 | #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ | |
274 | I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ | |
275 | I40E_PRTQF_FLX_PIT_FSIZE_MASK) | |
276 | #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ | |
277 | I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ | |
278 | I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) | |
279 | #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ | |
280 | I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ | |
281 | I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | |
282 | #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ | |
283 | I40E_FLEX_SET_FSIZE(fsize) | \ | |
284 | I40E_FLEX_SET_SRC_WORD(src)) | |
285 | ||
286 | #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ | |
287 | I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ | |
288 | I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) | |
289 | #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ | |
290 | I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ | |
291 | I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) | |
292 | #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ | |
293 | I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ | |
294 | I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) | |
295 | ||
296 | #define I40E_MAX_FLEX_SRC_OFFSET 0x1F | |
297 | ||
298 | /* macros related to GLQF_ORT */ | |
299 | #define I40E_ORT_SET_IDX(idx) (((idx) << \ | |
300 | I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ | |
301 | I40E_GLQF_ORT_PIT_INDX_MASK) | |
302 | ||
303 | #define I40E_ORT_SET_COUNT(count) (((count) << \ | |
304 | I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ | |
305 | I40E_GLQF_ORT_FIELD_CNT_MASK) | |
306 | ||
307 | #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ | |
308 | I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ | |
309 | I40E_GLQF_ORT_FLX_PAYLOAD_MASK) | |
310 | ||
311 | #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ | |
312 | I40E_ORT_SET_COUNT(count) | \ | |
313 | I40E_ORT_SET_PAYLOAD(payload)) | |
314 | ||
315 | #define I40E_L3_GLQF_ORT_IDX 34 | |
316 | #define I40E_L4_GLQF_ORT_IDX 35 | |
317 | ||
318 | /* Flex PIT register index */ | |
319 | #define I40E_FLEX_PIT_IDX_START_L2 0 | |
320 | #define I40E_FLEX_PIT_IDX_START_L3 3 | |
321 | #define I40E_FLEX_PIT_IDX_START_L4 6 | |
322 | ||
323 | #define I40E_FLEX_PIT_TABLE_SIZE 3 | |
324 | ||
325 | #define I40E_FLEX_DEST_UNUSED 63 | |
326 | ||
327 | #define I40E_FLEX_INDEX_ENTRIES 8 | |
328 | ||
329 | /* Flex MASK to disable all flexible entries */ | |
330 | #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ | |
331 | I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ | |
332 | I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ | |
333 | I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) | |
334 | ||
335 | struct i40e_flex_pit { | |
336 | struct list_head list; | |
337 | u16 src_offset; | |
338 | u8 pit_index; | |
339 | }; | |
340 | ||
7daa6bf3 JB |
341 | /* struct that defines the Ethernet device */ |
342 | struct i40e_pf { | |
343 | struct pci_dev *pdev; | |
344 | struct i40e_hw hw; | |
0da36b97 | 345 | DECLARE_BITMAP(state, __I40E_STATE_SIZE__); |
7daa6bf3 | 346 | struct msix_entry *msix_entries; |
7daa6bf3 JB |
347 | bool fc_autoneg_status; |
348 | ||
349 | u16 eeprom_version; | |
b40c82e6 | 350 | u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ |
7daa6bf3 JB |
351 | u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ |
352 | u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ | |
ec2f25d2 | 353 | u16 num_req_vfs; /* num VFs requested for this PF */ |
b40c82e6 | 354 | u16 num_vf_qps; /* num queue pairs per VF */ |
b40c82e6 JK |
355 | u16 num_lan_qps; /* num lan queues this PF has set up */ |
356 | u16 num_lan_msix; /* num queue vectors for the base PF vsi */ | |
a70e407f | 357 | u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ |
e3219ce6 ASJ |
358 | u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ |
359 | int iwarp_base_vector; | |
f8ff1464 | 360 | int queues_left; /* queues left unclaimed */ |
acd65448 | 361 | u16 alloc_rss_size; /* allocated RSS queues */ |
7daa6bf3 JB |
362 | u16 rss_size_max; /* HW defined max RSS queues */ |
363 | u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ | |
505682cd | 364 | u16 num_alloc_vsi; /* num VSIs this driver supports */ |
7daa6bf3 | 365 | u8 atr_sample_rate; |
8e2773ae | 366 | bool wol_en; |
7daa6bf3 | 367 | |
17a73f6b JG |
368 | struct hlist_head fdir_filter_list; |
369 | u16 fdir_pf_active_filters; | |
1e1be8f6 | 370 | unsigned long fd_flush_timestamp; |
60793f4a | 371 | u32 fd_flush_cnt; |
1e1be8f6 ASJ |
372 | u32 fd_add_err; |
373 | u32 fd_atr_cnt; | |
097dbf52 JK |
374 | |
375 | /* Book-keeping of side-band filter count per flow-type. | |
376 | * This is used to detect and handle input set changes for | |
377 | * respective flow-type. | |
378 | */ | |
379 | u16 fd_tcp4_filter_cnt; | |
380 | u16 fd_udp4_filter_cnt; | |
f223c875 | 381 | u16 fd_sctp4_filter_cnt; |
097dbf52 | 382 | u16 fd_ip4_filter_cnt; |
17a73f6b | 383 | |
0e588de1 JK |
384 | /* Flexible filter table values that need to be programmed into |
385 | * hardware, which expects L3 and L4 to be programmed separately. We | |
386 | * need to ensure that the values are in ascended order and don't have | |
387 | * duplicates, so we track each L3 and L4 values in separate lists. | |
388 | */ | |
389 | struct list_head l3_flex_pit_list; | |
390 | struct list_head l4_flex_pit_list; | |
391 | ||
6a899024 SA |
392 | struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; |
393 | u16 pending_udp_bitmap; | |
a1c9a9d9 | 394 | |
7daa6bf3 JB |
395 | enum i40e_interrupt_policy int_policy; |
396 | u16 rx_itr_default; | |
397 | u16 tx_itr_default; | |
71e6163a | 398 | u32 msg_enable; |
b294ac70 | 399 | char int_name[I40E_INT_NAME_STR_LEN]; |
7daa6bf3 | 400 | u16 adminq_work_limit; /* num of admin receive queue desc to process */ |
21536717 SN |
401 | unsigned long service_timer_period; |
402 | unsigned long service_timer_previous; | |
7daa6bf3 JB |
403 | struct timer_list service_timer; |
404 | struct work_struct service_task; | |
405 | ||
d36e41dc JK |
406 | u64 hw_features; |
407 | #define I40E_HW_RSS_AQ_CAPABLE BIT_ULL(0) | |
408 | #define I40E_HW_128_QP_RSS_CAPABLE BIT_ULL(1) | |
409 | #define I40E_HW_ATR_EVICT_CAPABLE BIT_ULL(2) | |
410 | #define I40E_HW_WB_ON_ITR_CAPABLE BIT_ULL(3) | |
411 | #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(4) | |
412 | #define I40E_HW_NO_PCI_LINK_CHECK BIT_ULL(5) | |
413 | #define I40E_HW_100M_SGMII_CAPABLE BIT_ULL(6) | |
414 | #define I40E_HW_NO_DCB_SUPPORT BIT_ULL(7) | |
415 | #define I40E_HW_USE_SET_LLDP_MIB BIT_ULL(8) | |
416 | #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT_ULL(9) | |
417 | #define I40E_HW_PTP_L4_CAPABLE BIT_ULL(10) | |
418 | #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT_ULL(11) | |
419 | #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT_ULL(12) | |
420 | #define I40E_HW_HAVE_CRT_RETIMER BIT_ULL(13) | |
421 | #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT_ULL(14) | |
422 | #define I40E_HW_PHY_CONTROLS_LEDS BIT_ULL(15) | |
423 | #define I40E_HW_STOP_FW_LLDP BIT_ULL(16) | |
424 | #define I40E_HW_PORT_ID_VALID BIT_ULL(17) | |
425 | #define I40E_HW_RESTART_AUTONEG BIT_ULL(18) | |
426 | ||
7daa6bf3 | 427 | u64 flags; |
41a1d04b JB |
428 | #define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1) |
429 | #define I40E_FLAG_MSI_ENABLED BIT_ULL(2) | |
430 | #define I40E_FLAG_MSIX_ENABLED BIT_ULL(3) | |
6964e53f | 431 | #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT_ULL(4) |
41a1d04b JB |
432 | #define I40E_FLAG_RSS_ENABLED BIT_ULL(6) |
433 | #define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7) | |
d502ce01 | 434 | #define I40E_FLAG_IWARP_ENABLED BIT_ULL(10) |
41a1d04b | 435 | #define I40E_FLAG_FILTER_SYNC BIT_ULL(15) |
e3219ce6 | 436 | #define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT_ULL(16) |
41a1d04b JB |
437 | #define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19) |
438 | #define I40E_FLAG_DCB_ENABLED BIT_ULL(20) | |
439 | #define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21) | |
440 | #define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22) | |
47994c11 JK |
441 | #define I40E_FLAG_FD_SB_AUTO_DISABLED BIT_ULL(23) |
442 | #define I40E_FLAG_FD_ATR_AUTO_DISABLED BIT_ULL(24) | |
41a1d04b JB |
443 | #define I40E_FLAG_PTP BIT_ULL(25) |
444 | #define I40E_FLAG_MFP_ENABLED BIT_ULL(26) | |
6a899024 | 445 | #define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27) |
41a1d04b | 446 | #define I40E_FLAG_DCB_CAPABLE BIT_ULL(29) |
d1a8d275 | 447 | #define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37) |
9ac77266 | 448 | #define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39) |
fc60861e | 449 | #define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40) |
b5569892 | 450 | #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT_ULL(51) |
0ef2d5af | 451 | #define I40E_FLAG_CLIENT_RESET BIT_ULL(54) |
ae136708 | 452 | #define I40E_FLAG_TEMP_LINK_POLLING BIT_ULL(55) |
0ef2d5af | 453 | #define I40E_FLAG_CLIENT_L2_CHANGE BIT_ULL(56) |
9a858178 | 454 | #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT_ULL(57) |
c424d4a3 | 455 | #define I40E_FLAG_LEGACY_RX BIT_ULL(58) |
64615b54 | 456 | #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT_ULL(59) |
7daa6bf3 | 457 | |
0ef2d5af | 458 | struct i40e_client_instance *cinst; |
7daa6bf3 JB |
459 | bool stat_offsets_loaded; |
460 | struct i40e_hw_port_stats stats; | |
461 | struct i40e_hw_port_stats stats_offsets; | |
462 | u32 tx_timeout_count; | |
463 | u32 tx_timeout_recovery_level; | |
464 | unsigned long tx_timeout_last_recovery; | |
810b3ae4 | 465 | u32 tx_sluggish_count; |
7daa6bf3 JB |
466 | u32 hw_csum_rx_error; |
467 | u32 led_status; | |
468 | u16 corer_count; /* Core reset count */ | |
469 | u16 globr_count; /* Global reset count */ | |
470 | u16 empr_count; /* EMP reset count */ | |
471 | u16 pfr_count; /* PF reset count */ | |
cd92e72f | 472 | u16 sw_int_count; /* SW interrupt count */ |
7daa6bf3 JB |
473 | |
474 | struct mutex switch_mutex; | |
475 | u16 lan_vsi; /* our default LAN VSI */ | |
476 | u16 lan_veb; /* initial relay, if exists */ | |
c57c9959 JK |
477 | #define I40E_NO_VEB 0xffff |
478 | #define I40E_NO_VSI 0xffff | |
7daa6bf3 JB |
479 | u16 next_vsi; /* Next unallocated VSI - 0-based! */ |
480 | struct i40e_vsi **vsi; | |
481 | struct i40e_veb *veb[I40E_MAX_VEB]; | |
482 | ||
483 | struct i40e_lump_tracking *qp_pile; | |
484 | struct i40e_lump_tracking *irq_pile; | |
485 | ||
486 | /* switch config info */ | |
487 | u16 pf_seid; | |
488 | u16 main_vsi_seid; | |
489 | u16 mac_seid; | |
7daa6bf3 JB |
490 | struct kobject *switch_kobj; |
491 | #ifdef CONFIG_DEBUG_FS | |
492 | struct dentry *i40e_dbg_pf; | |
493 | #endif /* CONFIG_DEBUG_FS */ | |
92faef85 | 494 | bool cur_promisc; |
7daa6bf3 | 495 | |
93cd765b ASJ |
496 | u16 instance; /* A unique number per i40e_pf instance in the system */ |
497 | ||
7daa6bf3 JB |
498 | /* sr-iov config info */ |
499 | struct i40e_vf *vf; | |
500 | int num_alloc_vfs; /* actual number of VFs allocated */ | |
501 | u32 vf_aq_requests; | |
1d0a4ada | 502 | u32 arq_overflows; /* Not fatal, possibly indicative of problems */ |
7daa6bf3 JB |
503 | |
504 | /* DCBx/DCBNL capability for PF that indicates | |
505 | * whether DCBx is managed by firmware or host | |
506 | * based agent (LLDPAD). Also, indicates what | |
507 | * flavor of DCBx protocol (IEEE/CEE) is supported | |
508 | * by the device. For now we're supporting IEEE | |
509 | * mode only. | |
510 | */ | |
511 | u16 dcbx_cap; | |
512 | ||
7daa6bf3 | 513 | struct i40e_filter_control_settings filter_settings; |
beb0dff1 JK |
514 | |
515 | struct ptp_clock *ptp_clock; | |
516 | struct ptp_clock_info ptp_caps; | |
517 | struct sk_buff *ptp_tx_skb; | |
0bc0706b | 518 | unsigned long ptp_tx_start; |
beb0dff1 | 519 | struct hwtstamp_config tstamp_config; |
19551262 | 520 | struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ |
beb0dff1 JK |
521 | u64 ptp_base_adj; |
522 | u32 tx_hwtstamp_timeouts; | |
2955faca | 523 | u32 tx_hwtstamp_skipped; |
beb0dff1 | 524 | u32 rx_hwtstamp_cleared; |
12490501 JK |
525 | u32 latch_event_flags; |
526 | spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ | |
527 | unsigned long latch_events[4]; | |
beb0dff1 JK |
528 | bool ptp_tx; |
529 | bool ptp_rx; | |
acd65448 | 530 | u16 rss_table_size; /* HW RSS table size */ |
4fc8c676 SN |
531 | u32 max_bw; |
532 | u32 min_bw; | |
2ac8b675 SN |
533 | |
534 | u32 ioremap_len; | |
3487b6c3 | 535 | u32 fd_inv; |
31b606d0 | 536 | u16 phy_led_val; |
7daa6bf3 JB |
537 | }; |
538 | ||
278e7d0b JK |
539 | /** |
540 | * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key | |
541 | * @macaddr: the MAC Address as the base key | |
542 | * | |
543 | * Simply copies the address and returns it as a u64 for hashing | |
544 | **/ | |
545 | static inline u64 i40e_addr_to_hkey(const u8 *macaddr) | |
546 | { | |
547 | u64 key = 0; | |
548 | ||
549 | ether_addr_copy((u8 *)&key, macaddr); | |
550 | return key; | |
551 | } | |
552 | ||
c3c7ea27 MW |
553 | enum i40e_filter_state { |
554 | I40E_FILTER_INVALID = 0, /* Invalid state */ | |
555 | I40E_FILTER_NEW, /* New, not sent to FW yet */ | |
556 | I40E_FILTER_ACTIVE, /* Added to switch by FW */ | |
557 | I40E_FILTER_FAILED, /* Rejected by FW */ | |
558 | I40E_FILTER_REMOVE, /* To be removed */ | |
559 | /* There is no 'removed' state; the filter struct is freed */ | |
560 | }; | |
7daa6bf3 | 561 | struct i40e_mac_filter { |
278e7d0b | 562 | struct hlist_node hlist; |
7daa6bf3 JB |
563 | u8 macaddr[ETH_ALEN]; |
564 | #define I40E_VLAN_ANY -1 | |
565 | s16 vlan; | |
c3c7ea27 | 566 | enum i40e_filter_state state; |
7daa6bf3 JB |
567 | }; |
568 | ||
671889e6 JK |
569 | /* Wrapper structure to keep track of filters while we are preparing to send |
570 | * firmware commands. We cannot send firmware commands while holding a | |
571 | * spinlock, since it might sleep. To avoid this, we wrap the added filters in | |
572 | * a separate structure, which will track the state change and update the real | |
573 | * filter while under lock. We can't simply hold the filters in a separate | |
574 | * list, as this opens a window for a race condition when adding new MAC | |
575 | * addresses to all VLANs, or when adding new VLANs to all MAC addresses. | |
576 | */ | |
577 | struct i40e_new_mac_filter { | |
578 | struct hlist_node hlist; | |
579 | struct i40e_mac_filter *f; | |
580 | ||
581 | /* Track future changes to state separately */ | |
582 | enum i40e_filter_state state; | |
583 | }; | |
584 | ||
7daa6bf3 JB |
585 | struct i40e_veb { |
586 | struct i40e_pf *pf; | |
587 | u16 idx; | |
c57c9959 | 588 | u16 veb_idx; /* index of VEB parent */ |
7daa6bf3 JB |
589 | u16 seid; |
590 | u16 uplink_seid; | |
c57c9959 | 591 | u16 stats_idx; /* index of VEB parent */ |
7daa6bf3 | 592 | u8 enabled_tc; |
51616018 | 593 | u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ |
7daa6bf3 JB |
594 | u16 flags; |
595 | u16 bw_limit; | |
596 | u8 bw_max_quanta; | |
597 | bool is_abs_credits; | |
598 | u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; | |
599 | u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; | |
600 | u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; | |
601 | struct kobject *kobj; | |
602 | bool stat_offsets_loaded; | |
603 | struct i40e_eth_stats stats; | |
604 | struct i40e_eth_stats stats_offsets; | |
fe860afb NP |
605 | struct i40e_veb_tc_stats tc_stats; |
606 | struct i40e_veb_tc_stats tc_stats_offsets; | |
7daa6bf3 JB |
607 | }; |
608 | ||
609 | /* struct that defines a VSI, associated with a dev */ | |
610 | struct i40e_vsi { | |
611 | struct net_device *netdev; | |
612 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
613 | bool netdev_registered; | |
614 | bool stat_offsets_loaded; | |
615 | ||
616 | u32 current_netdev_flags; | |
0da36b97 | 617 | DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); |
41a1d04b JB |
618 | #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) |
619 | #define I40E_VSI_FLAG_VEB_OWNER BIT(1) | |
7daa6bf3 JB |
620 | unsigned long flags; |
621 | ||
278e7d0b JK |
622 | /* Per VSI lock to protect elements/hash (MAC filter) */ |
623 | spinlock_t mac_filter_hash_lock; | |
624 | /* Fixed size hash table with 2^8 buckets for MAC filters */ | |
625 | DECLARE_HASHTABLE(mac_filter_hash, 8); | |
cbebb85f | 626 | bool has_vlan_filter; |
7daa6bf3 JB |
627 | |
628 | /* VSI stats */ | |
629 | struct rtnl_link_stats64 net_stats; | |
630 | struct rtnl_link_stats64 net_stats_offsets; | |
631 | struct i40e_eth_stats eth_stats; | |
632 | struct i40e_eth_stats eth_stats_offsets; | |
633 | u32 tx_restart; | |
634 | u32 tx_busy; | |
2fc3d715 | 635 | u64 tx_linearize; |
164c9f54 | 636 | u64 tx_force_wb; |
7daa6bf3 JB |
637 | u32 rx_buf_failed; |
638 | u32 rx_page_failed; | |
639 | ||
9f65e15b AD |
640 | /* These are containers of ring pointers, allocated at run-time */ |
641 | struct i40e_ring **rx_rings; | |
642 | struct i40e_ring **tx_rings; | |
74608d17 | 643 | struct i40e_ring **xdp_rings; /* XDP Tx rings */ |
7daa6bf3 | 644 | |
c3c7ea27 MW |
645 | u32 active_filters; |
646 | u32 promisc_threshold; | |
647 | ||
7daa6bf3 | 648 | u16 work_limit; |
c57c9959 JK |
649 | u16 int_rate_limit; /* value in usecs */ |
650 | ||
651 | u16 rss_table_size; /* HW RSS table size */ | |
652 | u16 rss_size; /* Allocated RSS queues */ | |
653 | u8 *rss_hkey_user; /* User configured hash keys */ | |
654 | u8 *rss_lut_user; /* User configured lookup table entries */ | |
7daa6bf3 | 655 | |
5db4cb59 | 656 | |
7daa6bf3 | 657 | u16 max_frame; |
7daa6bf3 | 658 | u16 rx_buf_len; |
7daa6bf3 | 659 | |
0c8493d9 BT |
660 | struct bpf_prog *xdp_prog; |
661 | ||
7daa6bf3 | 662 | /* List of q_vectors allocated to this VSI */ |
493fb300 | 663 | struct i40e_q_vector **q_vectors; |
7daa6bf3 JB |
664 | int num_q_vectors; |
665 | int base_vector; | |
63741846 | 666 | bool irqs_ready; |
7daa6bf3 | 667 | |
c57c9959 JK |
668 | u16 seid; /* HW index of this VSI (absolute index) */ |
669 | u16 id; /* VSI number */ | |
7daa6bf3 JB |
670 | u16 uplink_seid; |
671 | ||
c57c9959 JK |
672 | u16 base_queue; /* vsi's first queue in hw array */ |
673 | u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ | |
674 | u16 req_queue_pairs; /* User requested queue pairs */ | |
675 | u16 num_queue_pairs; /* Used tx and rx pairs */ | |
7daa6bf3 JB |
676 | u16 num_desc; |
677 | enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ | |
a1b5a24f | 678 | s16 vf_id; /* Virtual function ID for SRIOV VSIs */ |
7daa6bf3 JB |
679 | |
680 | struct i40e_tc_configuration tc_config; | |
681 | struct i40e_aqc_vsi_properties_data info; | |
682 | ||
683 | /* VSI BW limit (absolute across all TCs) */ | |
684 | u16 bw_limit; /* VSI BW Limit (0 = disabled) */ | |
685 | u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ | |
686 | ||
687 | /* Relative TC credits across VSIs */ | |
688 | u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; | |
689 | /* TC BW limit credits within VSI */ | |
690 | u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; | |
691 | /* TC BW limit max quanta within VSI */ | |
692 | u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; | |
693 | ||
c57c9959 JK |
694 | struct i40e_pf *back; /* Backreference to associated PF */ |
695 | u16 idx; /* index in pf->vsi[] */ | |
696 | u16 veb_idx; /* index of VEB parent */ | |
697 | struct kobject *kobj; /* sysfs object */ | |
698 | bool current_isup; /* Sync 'link up' logging */ | |
7ec9ba11 | 699 | enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ |
7daa6bf3 | 700 | |
e3219ce6 ASJ |
701 | void *priv; /* client driver data reference. */ |
702 | ||
7daa6bf3 JB |
703 | /* VSI specific handlers */ |
704 | irqreturn_t (*irq_handler)(int irq, void *data); | |
705 | } ____cacheline_internodealigned_in_smp; | |
706 | ||
707 | struct i40e_netdev_priv { | |
708 | struct i40e_vsi *vsi; | |
709 | }; | |
710 | ||
711 | /* struct that defines an interrupt vector */ | |
712 | struct i40e_q_vector { | |
713 | struct i40e_vsi *vsi; | |
714 | ||
715 | u16 v_idx; /* index in the vsi->q_vector array. */ | |
716 | u16 reg_idx; /* register index of the interrupt */ | |
717 | ||
718 | struct napi_struct napi; | |
719 | ||
720 | struct i40e_ring_container rx; | |
721 | struct i40e_ring_container tx; | |
722 | ||
723 | u8 num_ringpairs; /* total number of ring pairs in vector */ | |
724 | ||
7daa6bf3 | 725 | cpumask_t affinity_mask; |
96db776a AB |
726 | struct irq_affinity_notify affinity_notify; |
727 | ||
493fb300 | 728 | struct rcu_head rcu; /* to avoid race with update stats on free */ |
b294ac70 | 729 | char name[I40E_INT_NAME_STR_LEN]; |
8e0764b4 | 730 | bool arm_wb_state; |
ee2319cf JB |
731 | #define ITR_COUNTDOWN_START 100 |
732 | u8 itr_countdown; /* when 0 should adjust ITR */ | |
7daa6bf3 JB |
733 | } ____cacheline_internodealigned_in_smp; |
734 | ||
735 | /* lan device */ | |
736 | struct i40e_device { | |
737 | struct list_head list; | |
738 | struct i40e_pf *pf; | |
739 | }; | |
740 | ||
741 | /** | |
6dec1017 | 742 | * i40e_nvm_version_str - format the NVM version strings |
7daa6bf3 JB |
743 | * @hw: ptr to the hardware info |
744 | **/ | |
6dec1017 | 745 | static inline char *i40e_nvm_version_str(struct i40e_hw *hw) |
7daa6bf3 JB |
746 | { |
747 | static char buf[32]; | |
2efaad86 | 748 | u32 full_ver; |
2efaad86 CW |
749 | |
750 | full_ver = hw->nvm.oem_ver; | |
5bbb2e20 FS |
751 | |
752 | if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { | |
753 | u8 gen, snap; | |
754 | u16 release; | |
755 | ||
756 | gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); | |
757 | snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> | |
758 | I40E_OEM_SNAP_SHIFT); | |
759 | release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); | |
760 | ||
761 | snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); | |
762 | } else { | |
763 | u8 ver, patch; | |
764 | u16 build; | |
765 | ||
766 | ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); | |
767 | build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & | |
768 | I40E_OEM_VER_BUILD_MASK); | |
769 | patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); | |
770 | ||
771 | snprintf(buf, sizeof(buf), | |
772 | "%x.%02x 0x%x %d.%d.%d", | |
773 | (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> | |
774 | I40E_NVM_VERSION_HI_SHIFT, | |
775 | (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> | |
776 | I40E_NVM_VERSION_LO_SHIFT, | |
777 | hw->nvm.eetrack, ver, build, patch); | |
778 | } | |
7daa6bf3 JB |
779 | |
780 | return buf; | |
781 | } | |
782 | ||
783 | /** | |
784 | * i40e_netdev_to_pf: Retrieve the PF struct for given netdev | |
785 | * @netdev: the corresponding netdev | |
786 | * | |
787 | * Return the PF struct for the given netdev | |
788 | **/ | |
789 | static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) | |
790 | { | |
791 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
792 | struct i40e_vsi *vsi = np->vsi; | |
793 | ||
794 | return vsi->back; | |
795 | } | |
796 | ||
797 | static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, | |
798 | irqreturn_t (*irq_handler)(int, void *)) | |
799 | { | |
800 | vsi->irq_handler = irq_handler; | |
801 | } | |
802 | ||
082def10 ASJ |
803 | /** |
804 | * i40e_get_fd_cnt_all - get the total FD filter space available | |
b40c82e6 | 805 | * @pf: pointer to the PF struct |
082def10 ASJ |
806 | **/ |
807 | static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) | |
808 | { | |
809 | return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; | |
810 | } | |
811 | ||
36777d9f JK |
812 | /** |
813 | * i40e_read_fd_input_set - reads value of flow director input set register | |
814 | * @pf: pointer to the PF struct | |
815 | * @addr: register addr | |
816 | * | |
817 | * This function reads value of flow director input set register | |
818 | * specified by 'addr' (which is specific to flow-type) | |
819 | **/ | |
820 | static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) | |
821 | { | |
822 | u64 val; | |
823 | ||
824 | val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); | |
825 | val <<= 32; | |
826 | val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); | |
827 | ||
828 | return val; | |
829 | } | |
830 | ||
3bcee1e6 JK |
831 | /** |
832 | * i40e_write_fd_input_set - writes value into flow director input set register | |
833 | * @pf: pointer to the PF struct | |
834 | * @addr: register addr | |
835 | * @val: value to be written | |
836 | * | |
837 | * This function writes specified value to the register specified by 'addr'. | |
838 | * This register is input set register based on flow-type. | |
839 | **/ | |
840 | static inline void i40e_write_fd_input_set(struct i40e_pf *pf, | |
841 | u16 addr, u64 val) | |
842 | { | |
843 | i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), | |
844 | (u32)(val >> 32)); | |
845 | i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), | |
846 | (u32)(val & 0xFFFFFFFFULL)); | |
847 | } | |
848 | ||
7daa6bf3 JB |
849 | /* needed by i40e_ethtool.c */ |
850 | int i40e_up(struct i40e_vsi *vsi); | |
851 | void i40e_down(struct i40e_vsi *vsi); | |
852 | extern const char i40e_driver_name[]; | |
853 | extern const char i40e_driver_version_str[]; | |
23326186 | 854 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); |
373149fc | 855 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); |
043dd650 HZ |
856 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); |
857 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); | |
f1582351 AB |
858 | void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, |
859 | u16 rss_table_size, u16 rss_size); | |
fdf0e0bf | 860 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); |
4b816446 AD |
861 | /** |
862 | * i40e_find_vsi_by_type - Find and return Flow Director VSI | |
863 | * @pf: PF to search for VSI | |
864 | * @type: Value indicating type of VSI we are looking for | |
865 | **/ | |
866 | static inline struct i40e_vsi * | |
867 | i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) | |
868 | { | |
869 | int i; | |
870 | ||
871 | for (i = 0; i < pf->num_alloc_vsi; i++) { | |
872 | struct i40e_vsi *vsi = pf->vsi[i]; | |
873 | ||
874 | if (vsi && vsi->type == type) | |
875 | return vsi; | |
876 | } | |
877 | ||
878 | return NULL; | |
879 | } | |
7daa6bf3 JB |
880 | void i40e_update_stats(struct i40e_vsi *vsi); |
881 | void i40e_update_eth_stats(struct i40e_vsi *vsi); | |
882 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); | |
883 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, | |
884 | bool printconfig); | |
885 | ||
17a73f6b JG |
886 | int i40e_add_del_fdir(struct i40e_vsi *vsi, |
887 | struct i40e_fdir_filter *input, bool add); | |
55a5e60b | 888 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf); |
04294e38 ASJ |
889 | u32 i40e_get_current_fd_count(struct i40e_pf *pf); |
890 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); | |
891 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); | |
892 | u32 i40e_get_global_fd_count(struct i40e_pf *pf); | |
7c3c288b | 893 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); |
7daa6bf3 JB |
894 | void i40e_set_ethtool_ops(struct net_device *netdev); |
895 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
6622f5cd | 896 | const u8 *macaddr, s16 vlan); |
148141bb | 897 | void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); |
6622f5cd | 898 | void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); |
17652c63 | 899 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi); |
7daa6bf3 JB |
900 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, |
901 | u16 uplink, u32 param1); | |
902 | int i40e_vsi_release(struct i40e_vsi *vsi); | |
e3219ce6 ASJ |
903 | void i40e_service_event_schedule(struct i40e_pf *pf); |
904 | void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, | |
905 | u8 *msg, u16 len); | |
906 | ||
3aa7b74d FS |
907 | int i40e_vsi_start_rings(struct i40e_vsi *vsi); |
908 | void i40e_vsi_stop_rings(struct i40e_vsi *vsi); | |
e4b433f4 JK |
909 | void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); |
910 | int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); | |
f8ff1464 | 911 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); |
7daa6bf3 JB |
912 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, |
913 | u16 downlink_seid, u8 enabled_tc); | |
914 | void i40e_veb_release(struct i40e_veb *veb); | |
915 | ||
4e3b35b0 | 916 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); |
4eeb1fff | 917 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); |
7daa6bf3 JB |
918 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); |
919 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi); | |
920 | void i40e_pf_reset_stats(struct i40e_pf *pf); | |
921 | #ifdef CONFIG_DEBUG_FS | |
922 | void i40e_dbg_pf_init(struct i40e_pf *pf); | |
923 | void i40e_dbg_pf_exit(struct i40e_pf *pf); | |
924 | void i40e_dbg_init(void); | |
925 | void i40e_dbg_exit(void); | |
926 | #else | |
927 | static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} | |
928 | static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} | |
929 | static inline void i40e_dbg_init(void) {} | |
930 | static inline void i40e_dbg_exit(void) {} | |
931 | #endif /* CONFIG_DEBUG_FS*/ | |
e3219ce6 ASJ |
932 | /* needed by client drivers */ |
933 | int i40e_lan_add_device(struct i40e_pf *pf); | |
934 | int i40e_lan_del_device(struct i40e_pf *pf); | |
935 | void i40e_client_subtask(struct i40e_pf *pf); | |
936 | void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); | |
e3219ce6 ASJ |
937 | void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); |
938 | void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); | |
939 | void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); | |
0ef2d5af | 940 | int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); |
02d109be JB |
941 | /** |
942 | * i40e_irq_dynamic_enable - Enable default interrupt generation settings | |
943 | * @vsi: pointer to a vsi | |
944 | * @vector: enable a particular Hw Interrupt vector, without base_vector | |
945 | **/ | |
946 | static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) | |
947 | { | |
948 | struct i40e_pf *pf = vsi->back; | |
949 | struct i40e_hw *hw = &pf->hw; | |
950 | u32 val; | |
951 | ||
40d72a50 JB |
952 | /* definitely clear the PBA here, as this function is meant to |
953 | * clean out all previous interrupts AND enable the interrupt | |
954 | */ | |
02d109be JB |
955 | val = I40E_PFINT_DYN_CTLN_INTENA_MASK | |
956 | I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | | |
957 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
958 | wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); | |
959 | /* skip the flush */ | |
960 | } | |
961 | ||
2ef28cfb | 962 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); |
40d72a50 | 963 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba); |
7daa6bf3 | 964 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); |
96664483 | 965 | int i40e_open(struct net_device *netdev); |
08ca3874 | 966 | int i40e_close(struct net_device *netdev); |
6c167f58 | 967 | int i40e_vsi_open(struct i40e_vsi *vsi); |
7daa6bf3 | 968 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); |
9af52f60 | 969 | int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); |
f94484b7 | 970 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); |
9af52f60 | 971 | void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); |
f94484b7 | 972 | void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); |
feffdbe4 JK |
973 | struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, |
974 | const u8 *macaddr); | |
975 | int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); | |
7daa6bf3 | 976 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); |
6622f5cd | 977 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); |
7daa6bf3 | 978 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); |
4e3b35b0 NP |
979 | #ifdef CONFIG_I40E_DCB |
980 | void i40e_dcbnl_flush_apps(struct i40e_pf *pf, | |
750fcbcf | 981 | struct i40e_dcbx_config *old_cfg, |
4e3b35b0 NP |
982 | struct i40e_dcbx_config *new_cfg); |
983 | void i40e_dcbnl_set_all(struct i40e_vsi *vsi); | |
984 | void i40e_dcbnl_setup(struct i40e_vsi *vsi); | |
985 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
986 | struct i40e_dcbx_config *old_cfg, | |
987 | struct i40e_dcbx_config *new_cfg); | |
988 | #endif /* CONFIG_I40E_DCB */ | |
61189556 | 989 | void i40e_ptp_rx_hang(struct i40e_pf *pf); |
0bc0706b | 990 | void i40e_ptp_tx_hang(struct i40e_pf *pf); |
beb0dff1 JK |
991 | void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); |
992 | void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); | |
993 | void i40e_ptp_set_increment(struct i40e_pf *pf); | |
994 | int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); | |
995 | int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); | |
996 | void i40e_ptp_init(struct i40e_pf *pf); | |
997 | void i40e_ptp_stop(struct i40e_pf *pf); | |
51616018 | 998 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); |
4fc8c676 SN |
999 | i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); |
1000 | i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); | |
1001 | i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); | |
c156f856 | 1002 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); |
0c8493d9 BT |
1003 | |
1004 | static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) | |
1005 | { | |
1006 | return !!vsi->xdp_prog; | |
1007 | } | |
7daa6bf3 | 1008 | #endif /* _I40E_H_ */ |