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56a62fc8 JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
dc641b73 | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
56a62fc8 JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
56a62fc8 JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
27 | #include "i40e_status.h" | |
28 | #include "i40e_type.h" | |
29 | #include "i40e_register.h" | |
30 | #include "i40e_adminq.h" | |
31 | #include "i40e_prototype.h" | |
32 | ||
af28eec9 SH |
33 | static void i40e_resume_aq(struct i40e_hw *hw); |
34 | ||
c9296ad2 SN |
35 | /** |
36 | * i40e_is_nvm_update_op - return true if this is an NVM update operation | |
37 | * @desc: API request descriptor | |
38 | **/ | |
39 | static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc) | |
40 | { | |
41 | return (desc->opcode == i40e_aqc_opc_nvm_erase) || | |
42 | (desc->opcode == i40e_aqc_opc_nvm_update); | |
43 | } | |
44 | ||
56a62fc8 JB |
45 | /** |
46 | * i40e_adminq_init_regs - Initialize AdminQ registers | |
47 | * @hw: pointer to the hardware structure | |
48 | * | |
49 | * This assumes the alloc_asq and alloc_arq functions have already been called | |
50 | **/ | |
51 | static void i40e_adminq_init_regs(struct i40e_hw *hw) | |
52 | { | |
53 | /* set head and tail registers in our local struct */ | |
54 | if (hw->mac.type == I40E_MAC_VF) { | |
55 | hw->aq.asq.tail = I40E_VF_ATQT1; | |
56 | hw->aq.asq.head = I40E_VF_ATQH1; | |
17e6a845 | 57 | hw->aq.asq.len = I40E_VF_ATQLEN1; |
56a62fc8 JB |
58 | hw->aq.arq.tail = I40E_VF_ARQT1; |
59 | hw->aq.arq.head = I40E_VF_ARQH1; | |
17e6a845 | 60 | hw->aq.arq.len = I40E_VF_ARQLEN1; |
56a62fc8 JB |
61 | } else { |
62 | hw->aq.asq.tail = I40E_PF_ATQT; | |
63 | hw->aq.asq.head = I40E_PF_ATQH; | |
17e6a845 | 64 | hw->aq.asq.len = I40E_PF_ATQLEN; |
56a62fc8 JB |
65 | hw->aq.arq.tail = I40E_PF_ARQT; |
66 | hw->aq.arq.head = I40E_PF_ARQH; | |
17e6a845 | 67 | hw->aq.arq.len = I40E_PF_ARQLEN; |
56a62fc8 JB |
68 | } |
69 | } | |
70 | ||
71 | /** | |
72 | * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings | |
73 | * @hw: pointer to the hardware structure | |
74 | **/ | |
75 | static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) | |
76 | { | |
77 | i40e_status ret_code; | |
56a62fc8 | 78 | |
90bb776a | 79 | ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, |
56a62fc8 JB |
80 | i40e_mem_atq_ring, |
81 | (hw->aq.num_asq_entries * | |
82 | sizeof(struct i40e_aq_desc)), | |
83 | I40E_ADMINQ_DESC_ALIGNMENT); | |
84 | if (ret_code) | |
85 | return ret_code; | |
86 | ||
90bb776a | 87 | ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, |
56a62fc8 JB |
88 | (hw->aq.num_asq_entries * |
89 | sizeof(struct i40e_asq_cmd_details))); | |
90 | if (ret_code) { | |
90bb776a | 91 | i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); |
56a62fc8 JB |
92 | return ret_code; |
93 | } | |
94 | ||
56a62fc8 JB |
95 | return ret_code; |
96 | } | |
97 | ||
98 | /** | |
99 | * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings | |
100 | * @hw: pointer to the hardware structure | |
101 | **/ | |
102 | static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) | |
103 | { | |
104 | i40e_status ret_code; | |
105 | ||
90bb776a | 106 | ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, |
56a62fc8 JB |
107 | i40e_mem_arq_ring, |
108 | (hw->aq.num_arq_entries * | |
109 | sizeof(struct i40e_aq_desc)), | |
110 | I40E_ADMINQ_DESC_ALIGNMENT); | |
56a62fc8 JB |
111 | |
112 | return ret_code; | |
113 | } | |
114 | ||
115 | /** | |
116 | * i40e_free_adminq_asq - Free Admin Queue send rings | |
117 | * @hw: pointer to the hardware structure | |
118 | * | |
119 | * This assumes the posted send buffers have already been cleaned | |
120 | * and de-allocated | |
121 | **/ | |
122 | static void i40e_free_adminq_asq(struct i40e_hw *hw) | |
123 | { | |
90bb776a | 124 | i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); |
56a62fc8 JB |
125 | } |
126 | ||
127 | /** | |
128 | * i40e_free_adminq_arq - Free Admin Queue receive rings | |
129 | * @hw: pointer to the hardware structure | |
130 | * | |
131 | * This assumes the posted receive buffers have already been cleaned | |
132 | * and de-allocated | |
133 | **/ | |
134 | static void i40e_free_adminq_arq(struct i40e_hw *hw) | |
135 | { | |
90bb776a | 136 | i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); |
56a62fc8 JB |
137 | } |
138 | ||
139 | /** | |
140 | * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue | |
98d44381 | 141 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
142 | **/ |
143 | static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) | |
144 | { | |
145 | i40e_status ret_code; | |
146 | struct i40e_aq_desc *desc; | |
56a62fc8 JB |
147 | struct i40e_dma_mem *bi; |
148 | int i; | |
149 | ||
150 | /* We'll be allocating the buffer info memory first, then we can | |
151 | * allocate the mapped buffers for the event processing | |
152 | */ | |
153 | ||
154 | /* buffer_info structures do not need alignment */ | |
90bb776a DC |
155 | ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, |
156 | (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); | |
56a62fc8 JB |
157 | if (ret_code) |
158 | goto alloc_arq_bufs; | |
90bb776a | 159 | hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; |
56a62fc8 JB |
160 | |
161 | /* allocate the mapped buffers */ | |
162 | for (i = 0; i < hw->aq.num_arq_entries; i++) { | |
163 | bi = &hw->aq.arq.r.arq_bi[i]; | |
164 | ret_code = i40e_allocate_dma_mem(hw, bi, | |
165 | i40e_mem_arq_buf, | |
166 | hw->aq.arq_buf_size, | |
167 | I40E_ADMINQ_DESC_ALIGNMENT); | |
168 | if (ret_code) | |
169 | goto unwind_alloc_arq_bufs; | |
170 | ||
171 | /* now configure the descriptors for use */ | |
172 | desc = I40E_ADMINQ_DESC(hw->aq.arq, i); | |
173 | ||
174 | desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); | |
175 | if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) | |
176 | desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); | |
177 | desc->opcode = 0; | |
178 | /* This is in accordance with Admin queue design, there is no | |
179 | * register for buffer size configuration | |
180 | */ | |
181 | desc->datalen = cpu_to_le16((u16)bi->size); | |
182 | desc->retval = 0; | |
183 | desc->cookie_high = 0; | |
184 | desc->cookie_low = 0; | |
185 | desc->params.external.addr_high = | |
186 | cpu_to_le32(upper_32_bits(bi->pa)); | |
187 | desc->params.external.addr_low = | |
188 | cpu_to_le32(lower_32_bits(bi->pa)); | |
189 | desc->params.external.param0 = 0; | |
190 | desc->params.external.param1 = 0; | |
191 | } | |
192 | ||
193 | alloc_arq_bufs: | |
194 | return ret_code; | |
195 | ||
196 | unwind_alloc_arq_bufs: | |
197 | /* don't try to free the one that failed... */ | |
198 | i--; | |
199 | for (; i >= 0; i--) | |
200 | i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); | |
90bb776a | 201 | i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); |
56a62fc8 JB |
202 | |
203 | return ret_code; | |
204 | } | |
205 | ||
206 | /** | |
207 | * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue | |
98d44381 | 208 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
209 | **/ |
210 | static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) | |
211 | { | |
212 | i40e_status ret_code; | |
56a62fc8 JB |
213 | struct i40e_dma_mem *bi; |
214 | int i; | |
215 | ||
216 | /* No mapped memory needed yet, just the buffer info structures */ | |
90bb776a DC |
217 | ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, |
218 | (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); | |
56a62fc8 JB |
219 | if (ret_code) |
220 | goto alloc_asq_bufs; | |
90bb776a | 221 | hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; |
56a62fc8 JB |
222 | |
223 | /* allocate the mapped buffers */ | |
224 | for (i = 0; i < hw->aq.num_asq_entries; i++) { | |
225 | bi = &hw->aq.asq.r.asq_bi[i]; | |
226 | ret_code = i40e_allocate_dma_mem(hw, bi, | |
227 | i40e_mem_asq_buf, | |
228 | hw->aq.asq_buf_size, | |
229 | I40E_ADMINQ_DESC_ALIGNMENT); | |
230 | if (ret_code) | |
231 | goto unwind_alloc_asq_bufs; | |
232 | } | |
233 | alloc_asq_bufs: | |
234 | return ret_code; | |
235 | ||
236 | unwind_alloc_asq_bufs: | |
237 | /* don't try to free the one that failed... */ | |
238 | i--; | |
239 | for (; i >= 0; i--) | |
240 | i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); | |
90bb776a | 241 | i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); |
56a62fc8 JB |
242 | |
243 | return ret_code; | |
244 | } | |
245 | ||
246 | /** | |
247 | * i40e_free_arq_bufs - Free receive queue buffer info elements | |
98d44381 | 248 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
249 | **/ |
250 | static void i40e_free_arq_bufs(struct i40e_hw *hw) | |
251 | { | |
56a62fc8 JB |
252 | int i; |
253 | ||
90bb776a | 254 | /* free descriptors */ |
56a62fc8 JB |
255 | for (i = 0; i < hw->aq.num_arq_entries; i++) |
256 | i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); | |
257 | ||
90bb776a DC |
258 | /* free the descriptor memory */ |
259 | i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); | |
260 | ||
261 | /* free the dma header */ | |
262 | i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); | |
56a62fc8 JB |
263 | } |
264 | ||
265 | /** | |
266 | * i40e_free_asq_bufs - Free send queue buffer info elements | |
98d44381 | 267 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
268 | **/ |
269 | static void i40e_free_asq_bufs(struct i40e_hw *hw) | |
270 | { | |
56a62fc8 JB |
271 | int i; |
272 | ||
273 | /* only unmap if the address is non-NULL */ | |
274 | for (i = 0; i < hw->aq.num_asq_entries; i++) | |
275 | if (hw->aq.asq.r.asq_bi[i].pa) | |
276 | i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); | |
277 | ||
90bb776a DC |
278 | /* free the buffer info list */ |
279 | i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); | |
280 | ||
281 | /* free the descriptor memory */ | |
282 | i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); | |
283 | ||
284 | /* free the dma header */ | |
285 | i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); | |
56a62fc8 JB |
286 | } |
287 | ||
288 | /** | |
289 | * i40e_config_asq_regs - configure ASQ registers | |
98d44381 | 290 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
291 | * |
292 | * Configure base address and length registers for the transmit queue | |
293 | **/ | |
e03af1e1 | 294 | static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) |
56a62fc8 | 295 | { |
e03af1e1 KK |
296 | i40e_status ret_code = 0; |
297 | u32 reg = 0; | |
298 | ||
56a62fc8 JB |
299 | if (hw->mac.type == I40E_MAC_VF) { |
300 | /* configure the transmit queue */ | |
90bb776a DC |
301 | wr32(hw, I40E_VF_ATQBAH1, |
302 | upper_32_bits(hw->aq.asq.desc_buf.pa)); | |
303 | wr32(hw, I40E_VF_ATQBAL1, | |
304 | lower_32_bits(hw->aq.asq.desc_buf.pa)); | |
56a62fc8 JB |
305 | wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries | |
306 | I40E_VF_ATQLEN1_ATQENABLE_MASK)); | |
e03af1e1 | 307 | reg = rd32(hw, I40E_VF_ATQBAL1); |
56a62fc8 JB |
308 | } else { |
309 | /* configure the transmit queue */ | |
90bb776a DC |
310 | wr32(hw, I40E_PF_ATQBAH, |
311 | upper_32_bits(hw->aq.asq.desc_buf.pa)); | |
312 | wr32(hw, I40E_PF_ATQBAL, | |
313 | lower_32_bits(hw->aq.asq.desc_buf.pa)); | |
56a62fc8 JB |
314 | wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries | |
315 | I40E_PF_ATQLEN_ATQENABLE_MASK)); | |
e03af1e1 | 316 | reg = rd32(hw, I40E_PF_ATQBAL); |
56a62fc8 | 317 | } |
e03af1e1 KK |
318 | |
319 | /* Check one register to verify that config was applied */ | |
320 | if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) | |
321 | ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; | |
322 | ||
323 | return ret_code; | |
56a62fc8 JB |
324 | } |
325 | ||
326 | /** | |
327 | * i40e_config_arq_regs - ARQ register configuration | |
98d44381 | 328 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
329 | * |
330 | * Configure base address and length registers for the receive (event queue) | |
331 | **/ | |
e03af1e1 | 332 | static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) |
56a62fc8 | 333 | { |
e03af1e1 KK |
334 | i40e_status ret_code = 0; |
335 | u32 reg = 0; | |
336 | ||
56a62fc8 JB |
337 | if (hw->mac.type == I40E_MAC_VF) { |
338 | /* configure the receive queue */ | |
90bb776a DC |
339 | wr32(hw, I40E_VF_ARQBAH1, |
340 | upper_32_bits(hw->aq.arq.desc_buf.pa)); | |
341 | wr32(hw, I40E_VF_ARQBAL1, | |
342 | lower_32_bits(hw->aq.arq.desc_buf.pa)); | |
56a62fc8 JB |
343 | wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries | |
344 | I40E_VF_ARQLEN1_ARQENABLE_MASK)); | |
e03af1e1 | 345 | reg = rd32(hw, I40E_VF_ARQBAL1); |
56a62fc8 JB |
346 | } else { |
347 | /* configure the receive queue */ | |
90bb776a DC |
348 | wr32(hw, I40E_PF_ARQBAH, |
349 | upper_32_bits(hw->aq.arq.desc_buf.pa)); | |
350 | wr32(hw, I40E_PF_ARQBAL, | |
351 | lower_32_bits(hw->aq.arq.desc_buf.pa)); | |
56a62fc8 JB |
352 | wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries | |
353 | I40E_PF_ARQLEN_ARQENABLE_MASK)); | |
e03af1e1 | 354 | reg = rd32(hw, I40E_PF_ARQBAL); |
56a62fc8 JB |
355 | } |
356 | ||
357 | /* Update tail in the HW to post pre-allocated buffers */ | |
358 | wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); | |
e03af1e1 KK |
359 | |
360 | /* Check one register to verify that config was applied */ | |
361 | if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) | |
362 | ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; | |
363 | ||
364 | return ret_code; | |
56a62fc8 JB |
365 | } |
366 | ||
367 | /** | |
368 | * i40e_init_asq - main initialization routine for ASQ | |
98d44381 | 369 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
370 | * |
371 | * This is the main initialization routine for the Admin Send Queue | |
372 | * Prior to calling this function, drivers *MUST* set the following fields | |
373 | * in the hw->aq structure: | |
374 | * - hw->aq.num_asq_entries | |
375 | * - hw->aq.arq_buf_size | |
376 | * | |
377 | * Do *NOT* hold the lock when calling this as the memory allocation routines | |
378 | * called are not going to be atomic context safe | |
379 | **/ | |
380 | static i40e_status i40e_init_asq(struct i40e_hw *hw) | |
381 | { | |
382 | i40e_status ret_code = 0; | |
383 | ||
384 | if (hw->aq.asq.count > 0) { | |
385 | /* queue already initialized */ | |
386 | ret_code = I40E_ERR_NOT_READY; | |
387 | goto init_adminq_exit; | |
388 | } | |
389 | ||
390 | /* verify input for valid configuration */ | |
391 | if ((hw->aq.num_asq_entries == 0) || | |
392 | (hw->aq.asq_buf_size == 0)) { | |
393 | ret_code = I40E_ERR_CONFIG; | |
394 | goto init_adminq_exit; | |
395 | } | |
396 | ||
397 | hw->aq.asq.next_to_use = 0; | |
398 | hw->aq.asq.next_to_clean = 0; | |
399 | hw->aq.asq.count = hw->aq.num_asq_entries; | |
400 | ||
401 | /* allocate the ring memory */ | |
402 | ret_code = i40e_alloc_adminq_asq_ring(hw); | |
403 | if (ret_code) | |
404 | goto init_adminq_exit; | |
405 | ||
406 | /* allocate buffers in the rings */ | |
407 | ret_code = i40e_alloc_asq_bufs(hw); | |
408 | if (ret_code) | |
409 | goto init_adminq_free_rings; | |
410 | ||
411 | /* initialize base registers */ | |
e03af1e1 KK |
412 | ret_code = i40e_config_asq_regs(hw); |
413 | if (ret_code) | |
414 | goto init_adminq_free_rings; | |
56a62fc8 JB |
415 | |
416 | /* success! */ | |
417 | goto init_adminq_exit; | |
418 | ||
419 | init_adminq_free_rings: | |
420 | i40e_free_adminq_asq(hw); | |
421 | ||
422 | init_adminq_exit: | |
423 | return ret_code; | |
424 | } | |
425 | ||
426 | /** | |
427 | * i40e_init_arq - initialize ARQ | |
98d44381 | 428 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
429 | * |
430 | * The main initialization routine for the Admin Receive (Event) Queue. | |
431 | * Prior to calling this function, drivers *MUST* set the following fields | |
432 | * in the hw->aq structure: | |
433 | * - hw->aq.num_asq_entries | |
434 | * - hw->aq.arq_buf_size | |
435 | * | |
436 | * Do *NOT* hold the lock when calling this as the memory allocation routines | |
437 | * called are not going to be atomic context safe | |
438 | **/ | |
439 | static i40e_status i40e_init_arq(struct i40e_hw *hw) | |
440 | { | |
441 | i40e_status ret_code = 0; | |
442 | ||
443 | if (hw->aq.arq.count > 0) { | |
444 | /* queue already initialized */ | |
445 | ret_code = I40E_ERR_NOT_READY; | |
446 | goto init_adminq_exit; | |
447 | } | |
448 | ||
449 | /* verify input for valid configuration */ | |
450 | if ((hw->aq.num_arq_entries == 0) || | |
451 | (hw->aq.arq_buf_size == 0)) { | |
452 | ret_code = I40E_ERR_CONFIG; | |
453 | goto init_adminq_exit; | |
454 | } | |
455 | ||
456 | hw->aq.arq.next_to_use = 0; | |
457 | hw->aq.arq.next_to_clean = 0; | |
458 | hw->aq.arq.count = hw->aq.num_arq_entries; | |
459 | ||
460 | /* allocate the ring memory */ | |
461 | ret_code = i40e_alloc_adminq_arq_ring(hw); | |
462 | if (ret_code) | |
463 | goto init_adminq_exit; | |
464 | ||
465 | /* allocate buffers in the rings */ | |
466 | ret_code = i40e_alloc_arq_bufs(hw); | |
467 | if (ret_code) | |
468 | goto init_adminq_free_rings; | |
469 | ||
470 | /* initialize base registers */ | |
e03af1e1 KK |
471 | ret_code = i40e_config_arq_regs(hw); |
472 | if (ret_code) | |
473 | goto init_adminq_free_rings; | |
56a62fc8 JB |
474 | |
475 | /* success! */ | |
476 | goto init_adminq_exit; | |
477 | ||
478 | init_adminq_free_rings: | |
479 | i40e_free_adminq_arq(hw); | |
480 | ||
481 | init_adminq_exit: | |
482 | return ret_code; | |
483 | } | |
484 | ||
485 | /** | |
486 | * i40e_shutdown_asq - shutdown the ASQ | |
98d44381 | 487 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
488 | * |
489 | * The main shutdown routine for the Admin Send Queue | |
490 | **/ | |
491 | static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) | |
492 | { | |
493 | i40e_status ret_code = 0; | |
494 | ||
495 | if (hw->aq.asq.count == 0) | |
496 | return I40E_ERR_NOT_READY; | |
497 | ||
498 | /* Stop firmware AdminQ processing */ | |
17e6a845 SN |
499 | wr32(hw, hw->aq.asq.head, 0); |
500 | wr32(hw, hw->aq.asq.tail, 0); | |
501 | wr32(hw, hw->aq.asq.len, 0); | |
56a62fc8 JB |
502 | |
503 | /* make sure lock is available */ | |
504 | mutex_lock(&hw->aq.asq_mutex); | |
505 | ||
506 | hw->aq.asq.count = 0; /* to indicate uninitialized queue */ | |
507 | ||
508 | /* free ring buffers */ | |
509 | i40e_free_asq_bufs(hw); | |
56a62fc8 JB |
510 | |
511 | mutex_unlock(&hw->aq.asq_mutex); | |
512 | ||
513 | return ret_code; | |
514 | } | |
515 | ||
516 | /** | |
517 | * i40e_shutdown_arq - shutdown ARQ | |
98d44381 | 518 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
519 | * |
520 | * The main shutdown routine for the Admin Receive Queue | |
521 | **/ | |
522 | static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) | |
523 | { | |
524 | i40e_status ret_code = 0; | |
525 | ||
526 | if (hw->aq.arq.count == 0) | |
527 | return I40E_ERR_NOT_READY; | |
528 | ||
529 | /* Stop firmware AdminQ processing */ | |
17e6a845 SN |
530 | wr32(hw, hw->aq.arq.head, 0); |
531 | wr32(hw, hw->aq.arq.tail, 0); | |
532 | wr32(hw, hw->aq.arq.len, 0); | |
56a62fc8 JB |
533 | |
534 | /* make sure lock is available */ | |
535 | mutex_lock(&hw->aq.arq_mutex); | |
536 | ||
537 | hw->aq.arq.count = 0; /* to indicate uninitialized queue */ | |
538 | ||
539 | /* free ring buffers */ | |
540 | i40e_free_arq_bufs(hw); | |
56a62fc8 JB |
541 | |
542 | mutex_unlock(&hw->aq.arq_mutex); | |
543 | ||
544 | return ret_code; | |
545 | } | |
546 | ||
547 | /** | |
548 | * i40e_init_adminq - main initialization routine for Admin Queue | |
98d44381 | 549 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
550 | * |
551 | * Prior to calling this function, drivers *MUST* set the following fields | |
552 | * in the hw->aq structure: | |
553 | * - hw->aq.num_asq_entries | |
554 | * - hw->aq.num_arq_entries | |
555 | * - hw->aq.arq_buf_size | |
556 | * - hw->aq.asq_buf_size | |
557 | **/ | |
558 | i40e_status i40e_init_adminq(struct i40e_hw *hw) | |
559 | { | |
56a62fc8 | 560 | i40e_status ret_code; |
d4946cf5 SN |
561 | u16 eetrack_lo, eetrack_hi; |
562 | int retry = 0; | |
56a62fc8 JB |
563 | |
564 | /* verify input for valid configuration */ | |
565 | if ((hw->aq.num_arq_entries == 0) || | |
566 | (hw->aq.num_asq_entries == 0) || | |
567 | (hw->aq.arq_buf_size == 0) || | |
568 | (hw->aq.asq_buf_size == 0)) { | |
569 | ret_code = I40E_ERR_CONFIG; | |
570 | goto init_adminq_exit; | |
571 | } | |
572 | ||
573 | /* initialize locks */ | |
574 | mutex_init(&hw->aq.asq_mutex); | |
575 | mutex_init(&hw->aq.arq_mutex); | |
576 | ||
577 | /* Set up register offsets */ | |
578 | i40e_adminq_init_regs(hw); | |
579 | ||
580 | /* allocate the ASQ */ | |
581 | ret_code = i40e_init_asq(hw); | |
582 | if (ret_code) | |
583 | goto init_adminq_destroy_locks; | |
584 | ||
585 | /* allocate the ARQ */ | |
586 | ret_code = i40e_init_arq(hw); | |
587 | if (ret_code) | |
588 | goto init_adminq_free_asq; | |
589 | ||
d4946cf5 SN |
590 | /* There are some cases where the firmware may not be quite ready |
591 | * for AdminQ operations, so we retry the AdminQ setup a few times | |
592 | * if we see timeouts in this first AQ call. | |
593 | */ | |
594 | do { | |
595 | ret_code = i40e_aq_get_firmware_version(hw, | |
596 | &hw->aq.fw_maj_ver, | |
597 | &hw->aq.fw_min_ver, | |
598 | &hw->aq.api_maj_ver, | |
599 | &hw->aq.api_min_ver, | |
600 | NULL); | |
601 | if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) | |
602 | break; | |
603 | retry++; | |
604 | msleep(100); | |
605 | i40e_resume_aq(hw); | |
606 | } while (retry < 10); | |
607 | if (ret_code != I40E_SUCCESS) | |
56a62fc8 JB |
608 | goto init_adminq_free_arq; |
609 | ||
981b7545 | 610 | /* get the NVM version info */ |
56a62fc8 JB |
611 | i40e_read_nvm_word(hw, I40E_SR_NVM_IMAGE_VERSION, &hw->nvm.version); |
612 | i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); | |
613 | i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); | |
614 | hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; | |
615 | ||
7e612411 | 616 | if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { |
981b7545 SN |
617 | ret_code = I40E_ERR_FIRMWARE_API_VERSION; |
618 | goto init_adminq_free_arq; | |
619 | } | |
620 | ||
ff2ff3b4 SN |
621 | /* pre-emptive resource lock release */ |
622 | i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); | |
c9296ad2 | 623 | hw->aq.nvm_busy = false; |
ff2ff3b4 | 624 | |
56a62fc8 JB |
625 | ret_code = i40e_aq_set_hmc_resource_profile(hw, |
626 | I40E_HMC_PROFILE_DEFAULT, | |
627 | 0, | |
628 | NULL); | |
629 | ret_code = 0; | |
630 | ||
631 | /* success! */ | |
632 | goto init_adminq_exit; | |
633 | ||
634 | init_adminq_free_arq: | |
635 | i40e_shutdown_arq(hw); | |
636 | init_adminq_free_asq: | |
637 | i40e_shutdown_asq(hw); | |
638 | init_adminq_destroy_locks: | |
639 | ||
640 | init_adminq_exit: | |
641 | return ret_code; | |
642 | } | |
643 | ||
644 | /** | |
645 | * i40e_shutdown_adminq - shutdown routine for the Admin Queue | |
98d44381 | 646 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
647 | **/ |
648 | i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) | |
649 | { | |
650 | i40e_status ret_code = 0; | |
651 | ||
e1860d8f ASJ |
652 | if (i40e_check_asq_alive(hw)) |
653 | i40e_aq_queue_shutdown(hw, true); | |
654 | ||
56a62fc8 JB |
655 | i40e_shutdown_asq(hw); |
656 | i40e_shutdown_arq(hw); | |
657 | ||
658 | /* destroy the locks */ | |
659 | ||
660 | return ret_code; | |
661 | } | |
662 | ||
663 | /** | |
664 | * i40e_clean_asq - cleans Admin send queue | |
98d44381 | 665 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
666 | * |
667 | * returns the number of free desc | |
668 | **/ | |
669 | static u16 i40e_clean_asq(struct i40e_hw *hw) | |
670 | { | |
671 | struct i40e_adminq_ring *asq = &(hw->aq.asq); | |
672 | struct i40e_asq_cmd_details *details; | |
673 | u16 ntc = asq->next_to_clean; | |
674 | struct i40e_aq_desc desc_cb; | |
675 | struct i40e_aq_desc *desc; | |
676 | ||
677 | desc = I40E_ADMINQ_DESC(*asq, ntc); | |
678 | details = I40E_ADMINQ_DETAILS(*asq, ntc); | |
679 | while (rd32(hw, hw->aq.asq.head) != ntc) { | |
680 | if (details->callback) { | |
681 | I40E_ADMINQ_CALLBACK cb_func = | |
682 | (I40E_ADMINQ_CALLBACK)details->callback; | |
683 | desc_cb = *desc; | |
684 | cb_func(hw, &desc_cb); | |
685 | } | |
a63fa1cd MW |
686 | memset(desc, 0, sizeof(*desc)); |
687 | memset(details, 0, sizeof(*details)); | |
56a62fc8 JB |
688 | ntc++; |
689 | if (ntc == asq->count) | |
690 | ntc = 0; | |
691 | desc = I40E_ADMINQ_DESC(*asq, ntc); | |
692 | details = I40E_ADMINQ_DETAILS(*asq, ntc); | |
693 | } | |
694 | ||
695 | asq->next_to_clean = ntc; | |
696 | ||
697 | return I40E_DESC_UNUSED(asq); | |
698 | } | |
699 | ||
700 | /** | |
701 | * i40e_asq_done - check if FW has processed the Admin Send Queue | |
702 | * @hw: pointer to the hw struct | |
703 | * | |
704 | * Returns true if the firmware has processed all descriptors on the | |
705 | * admin send queue. Returns false if there are still requests pending. | |
706 | **/ | |
af28eec9 | 707 | static bool i40e_asq_done(struct i40e_hw *hw) |
56a62fc8 JB |
708 | { |
709 | /* AQ designers suggest use of head for better | |
710 | * timing reliability than DD bit | |
711 | */ | |
922680b9 | 712 | return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; |
56a62fc8 JB |
713 | |
714 | } | |
715 | ||
716 | /** | |
717 | * i40e_asq_send_command - send command to Admin Queue | |
718 | * @hw: pointer to the hw struct | |
719 | * @desc: prefilled descriptor describing the command (non DMA mem) | |
720 | * @buff: buffer to use for indirect commands | |
721 | * @buff_size: size of buffer for indirect commands | |
922680b9 | 722 | * @cmd_details: pointer to command details structure |
56a62fc8 JB |
723 | * |
724 | * This is the main send command driver routine for the Admin Queue send | |
725 | * queue. It runs the queue, cleans the queue, etc | |
726 | **/ | |
727 | i40e_status i40e_asq_send_command(struct i40e_hw *hw, | |
728 | struct i40e_aq_desc *desc, | |
729 | void *buff, /* can be NULL */ | |
730 | u16 buff_size, | |
731 | struct i40e_asq_cmd_details *cmd_details) | |
732 | { | |
733 | i40e_status status = 0; | |
734 | struct i40e_dma_mem *dma_buff = NULL; | |
735 | struct i40e_asq_cmd_details *details; | |
736 | struct i40e_aq_desc *desc_on_ring; | |
737 | bool cmd_completed = false; | |
738 | u16 retval = 0; | |
739 | ||
740 | if (hw->aq.asq.count == 0) { | |
741 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | |
742 | "AQTX: Admin queue not initialized.\n"); | |
743 | status = I40E_ERR_QUEUE_EMPTY; | |
744 | goto asq_send_command_exit; | |
745 | } | |
746 | ||
c9296ad2 SN |
747 | if (i40e_is_nvm_update_op(desc) && hw->aq.nvm_busy) { |
748 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: NVM busy.\n"); | |
749 | status = I40E_ERR_NVM; | |
750 | goto asq_send_command_exit; | |
751 | } | |
752 | ||
56a62fc8 JB |
753 | details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); |
754 | if (cmd_details) { | |
d7595a22 | 755 | *details = *cmd_details; |
56a62fc8 JB |
756 | |
757 | /* If the cmd_details are defined copy the cookie. The | |
758 | * cpu_to_le32 is not needed here because the data is ignored | |
759 | * by the FW, only used by the driver | |
760 | */ | |
761 | if (details->cookie) { | |
762 | desc->cookie_high = | |
763 | cpu_to_le32(upper_32_bits(details->cookie)); | |
764 | desc->cookie_low = | |
765 | cpu_to_le32(lower_32_bits(details->cookie)); | |
766 | } | |
767 | } else { | |
768 | memset(details, 0, sizeof(struct i40e_asq_cmd_details)); | |
769 | } | |
770 | ||
771 | /* clear requested flags and then set additional flags if defined */ | |
772 | desc->flags &= ~cpu_to_le16(details->flags_dis); | |
773 | desc->flags |= cpu_to_le16(details->flags_ena); | |
774 | ||
775 | mutex_lock(&hw->aq.asq_mutex); | |
776 | ||
777 | if (buff_size > hw->aq.asq_buf_size) { | |
778 | i40e_debug(hw, | |
779 | I40E_DEBUG_AQ_MESSAGE, | |
780 | "AQTX: Invalid buffer size: %d.\n", | |
781 | buff_size); | |
782 | status = I40E_ERR_INVALID_SIZE; | |
783 | goto asq_send_command_error; | |
784 | } | |
785 | ||
786 | if (details->postpone && !details->async) { | |
787 | i40e_debug(hw, | |
788 | I40E_DEBUG_AQ_MESSAGE, | |
789 | "AQTX: Async flag not set along with postpone flag"); | |
790 | status = I40E_ERR_PARAM; | |
791 | goto asq_send_command_error; | |
792 | } | |
793 | ||
794 | /* call clean and check queue available function to reclaim the | |
795 | * descriptors that were processed by FW, the function returns the | |
796 | * number of desc available | |
797 | */ | |
798 | /* the clean function called here could be called in a separate thread | |
799 | * in case of asynchronous completions | |
800 | */ | |
801 | if (i40e_clean_asq(hw) == 0) { | |
802 | i40e_debug(hw, | |
803 | I40E_DEBUG_AQ_MESSAGE, | |
804 | "AQTX: Error queue is full.\n"); | |
805 | status = I40E_ERR_ADMIN_QUEUE_FULL; | |
806 | goto asq_send_command_error; | |
807 | } | |
808 | ||
809 | /* initialize the temp desc pointer with the right desc */ | |
810 | desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); | |
811 | ||
812 | /* if the desc is available copy the temp desc to the right place */ | |
d7595a22 | 813 | *desc_on_ring = *desc; |
56a62fc8 JB |
814 | |
815 | /* if buff is not NULL assume indirect command */ | |
816 | if (buff != NULL) { | |
817 | dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); | |
818 | /* copy the user buff into the respective DMA buff */ | |
819 | memcpy(dma_buff->va, buff, buff_size); | |
820 | desc_on_ring->datalen = cpu_to_le16(buff_size); | |
821 | ||
822 | /* Update the address values in the desc with the pa value | |
823 | * for respective buffer | |
824 | */ | |
825 | desc_on_ring->params.external.addr_high = | |
826 | cpu_to_le32(upper_32_bits(dma_buff->pa)); | |
827 | desc_on_ring->params.external.addr_low = | |
828 | cpu_to_le32(lower_32_bits(dma_buff->pa)); | |
829 | } | |
830 | ||
831 | /* bump the tail */ | |
832 | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff); | |
833 | (hw->aq.asq.next_to_use)++; | |
834 | if (hw->aq.asq.next_to_use == hw->aq.asq.count) | |
835 | hw->aq.asq.next_to_use = 0; | |
836 | if (!details->postpone) | |
837 | wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); | |
838 | ||
839 | /* if cmd_details are not defined or async flag is not set, | |
840 | * we need to wait for desc write back | |
841 | */ | |
842 | if (!details->async && !details->postpone) { | |
843 | u32 total_delay = 0; | |
844 | u32 delay_len = 10; | |
845 | ||
846 | do { | |
847 | /* AQ designers suggest use of head for better | |
848 | * timing reliability than DD bit | |
849 | */ | |
850 | if (i40e_asq_done(hw)) | |
851 | break; | |
852 | /* ugh! delay while spin_lock */ | |
853 | udelay(delay_len); | |
854 | total_delay += delay_len; | |
855 | } while (total_delay < I40E_ASQ_CMD_TIMEOUT); | |
856 | } | |
857 | ||
858 | /* if ready, copy the desc back to temp */ | |
859 | if (i40e_asq_done(hw)) { | |
d7595a22 | 860 | *desc = *desc_on_ring; |
56a62fc8 JB |
861 | if (buff != NULL) |
862 | memcpy(buff, dma_buff->va, buff_size); | |
863 | retval = le16_to_cpu(desc->retval); | |
864 | if (retval != 0) { | |
865 | i40e_debug(hw, | |
866 | I40E_DEBUG_AQ_MESSAGE, | |
867 | "AQTX: Command completed with error 0x%X.\n", | |
868 | retval); | |
869 | /* strip off FW internal code */ | |
870 | retval &= 0xff; | |
871 | } | |
872 | cmd_completed = true; | |
873 | if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) | |
874 | status = 0; | |
875 | else | |
876 | status = I40E_ERR_ADMIN_QUEUE_ERROR; | |
877 | hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; | |
878 | } | |
879 | ||
c9296ad2 SN |
880 | if (i40e_is_nvm_update_op(desc)) |
881 | hw->aq.nvm_busy = true; | |
882 | ||
56a62fc8 JB |
883 | /* update the error if time out occurred */ |
884 | if ((!cmd_completed) && | |
885 | (!details->async && !details->postpone)) { | |
886 | i40e_debug(hw, | |
887 | I40E_DEBUG_AQ_MESSAGE, | |
888 | "AQTX: Writeback timeout.\n"); | |
889 | status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; | |
890 | } | |
891 | ||
892 | asq_send_command_error: | |
893 | mutex_unlock(&hw->aq.asq_mutex); | |
894 | asq_send_command_exit: | |
895 | return status; | |
896 | } | |
897 | ||
898 | /** | |
899 | * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function | |
900 | * @desc: pointer to the temp descriptor (non DMA mem) | |
901 | * @opcode: the opcode can be used to decide which flags to turn off or on | |
902 | * | |
903 | * Fill the desc with default values | |
904 | **/ | |
905 | void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, | |
906 | u16 opcode) | |
907 | { | |
908 | /* zero out the desc */ | |
909 | memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); | |
910 | desc->opcode = cpu_to_le16(opcode); | |
ab954cba | 911 | desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI); |
56a62fc8 JB |
912 | } |
913 | ||
914 | /** | |
915 | * i40e_clean_arq_element | |
916 | * @hw: pointer to the hw struct | |
917 | * @e: event info from the receive descriptor, includes any buffers | |
918 | * @pending: number of events that could be left to process | |
919 | * | |
920 | * This function cleans one Admin Receive Queue element and returns | |
921 | * the contents through e. It can also return how many events are | |
922 | * left to process through 'pending' | |
923 | **/ | |
924 | i40e_status i40e_clean_arq_element(struct i40e_hw *hw, | |
925 | struct i40e_arq_event_info *e, | |
926 | u16 *pending) | |
927 | { | |
928 | i40e_status ret_code = 0; | |
929 | u16 ntc = hw->aq.arq.next_to_clean; | |
930 | struct i40e_aq_desc *desc; | |
931 | struct i40e_dma_mem *bi; | |
932 | u16 desc_idx; | |
933 | u16 datalen; | |
934 | u16 flags; | |
935 | u16 ntu; | |
936 | ||
937 | /* take the lock before we start messing with the ring */ | |
938 | mutex_lock(&hw->aq.arq_mutex); | |
939 | ||
940 | /* set next_to_use to head */ | |
941 | ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); | |
942 | if (ntu == ntc) { | |
943 | /* nothing to do - shouldn't need to update ring's values */ | |
944 | i40e_debug(hw, | |
945 | I40E_DEBUG_AQ_MESSAGE, | |
946 | "AQRX: Queue is empty.\n"); | |
947 | ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; | |
948 | goto clean_arq_element_out; | |
949 | } | |
950 | ||
951 | /* now clean the next descriptor */ | |
952 | desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); | |
953 | desc_idx = ntc; | |
954 | i40e_debug_aq(hw, | |
955 | I40E_DEBUG_AQ_COMMAND, | |
956 | (void *)desc, | |
957 | hw->aq.arq.r.arq_bi[desc_idx].va); | |
958 | ||
959 | flags = le16_to_cpu(desc->flags); | |
960 | if (flags & I40E_AQ_FLAG_ERR) { | |
961 | ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; | |
962 | hw->aq.arq_last_status = | |
963 | (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); | |
964 | i40e_debug(hw, | |
965 | I40E_DEBUG_AQ_MESSAGE, | |
966 | "AQRX: Event received with error 0x%X.\n", | |
967 | hw->aq.arq_last_status); | |
968 | } else { | |
c36bd4a7 | 969 | e->desc = *desc; |
56a62fc8 JB |
970 | datalen = le16_to_cpu(desc->datalen); |
971 | e->msg_size = min(datalen, e->msg_size); | |
972 | if (e->msg_buf != NULL && (e->msg_size != 0)) | |
973 | memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, | |
974 | e->msg_size); | |
975 | } | |
976 | ||
c9296ad2 SN |
977 | if (i40e_is_nvm_update_op(&e->desc)) |
978 | hw->aq.nvm_busy = false; | |
979 | ||
56a62fc8 JB |
980 | /* Restore the original datalen and buffer address in the desc, |
981 | * FW updates datalen to indicate the event message | |
982 | * size | |
983 | */ | |
984 | bi = &hw->aq.arq.r.arq_bi[ntc]; | |
90077773 MW |
985 | memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); |
986 | ||
987 | desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); | |
988 | if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) | |
989 | desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); | |
56a62fc8 JB |
990 | desc->datalen = cpu_to_le16((u16)bi->size); |
991 | desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); | |
992 | desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); | |
993 | ||
994 | /* set tail = the last cleaned desc index. */ | |
995 | wr32(hw, hw->aq.arq.tail, ntc); | |
996 | /* ntc is updated to tail + 1 */ | |
997 | ntc++; | |
998 | if (ntc == hw->aq.num_arq_entries) | |
999 | ntc = 0; | |
1000 | hw->aq.arq.next_to_clean = ntc; | |
1001 | hw->aq.arq.next_to_use = ntu; | |
1002 | ||
1003 | clean_arq_element_out: | |
1004 | /* Set pending if needed, unlock and return */ | |
1005 | if (pending != NULL) | |
1006 | *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); | |
1007 | mutex_unlock(&hw->aq.arq_mutex); | |
1008 | ||
1009 | return ret_code; | |
1010 | } | |
1011 | ||
af28eec9 | 1012 | static void i40e_resume_aq(struct i40e_hw *hw) |
56a62fc8 | 1013 | { |
56a62fc8 JB |
1014 | /* Registers are reset after PF reset */ |
1015 | hw->aq.asq.next_to_use = 0; | |
1016 | hw->aq.asq.next_to_clean = 0; | |
1017 | ||
1018 | i40e_config_asq_regs(hw); | |
56a62fc8 JB |
1019 | |
1020 | hw->aq.arq.next_to_use = 0; | |
1021 | hw->aq.arq.next_to_clean = 0; | |
1022 | ||
1023 | i40e_config_arq_regs(hw); | |
56a62fc8 | 1024 | } |