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56a62fc8 JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
dc641b73 | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
56a62fc8 JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
56a62fc8 JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
27 | #include "i40e_status.h" | |
28 | #include "i40e_type.h" | |
29 | #include "i40e_register.h" | |
30 | #include "i40e_adminq.h" | |
31 | #include "i40e_prototype.h" | |
32 | ||
af28eec9 SH |
33 | static void i40e_resume_aq(struct i40e_hw *hw); |
34 | ||
c9296ad2 SN |
35 | /** |
36 | * i40e_is_nvm_update_op - return true if this is an NVM update operation | |
37 | * @desc: API request descriptor | |
38 | **/ | |
39 | static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc) | |
40 | { | |
cd552cb4 SN |
41 | return (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_erase)) || |
42 | (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_update)); | |
c9296ad2 SN |
43 | } |
44 | ||
56a62fc8 JB |
45 | /** |
46 | * i40e_adminq_init_regs - Initialize AdminQ registers | |
47 | * @hw: pointer to the hardware structure | |
48 | * | |
49 | * This assumes the alloc_asq and alloc_arq functions have already been called | |
50 | **/ | |
51 | static void i40e_adminq_init_regs(struct i40e_hw *hw) | |
52 | { | |
53 | /* set head and tail registers in our local struct */ | |
e7f2e4b9 | 54 | if (i40e_is_vf(hw)) { |
56a62fc8 JB |
55 | hw->aq.asq.tail = I40E_VF_ATQT1; |
56 | hw->aq.asq.head = I40E_VF_ATQH1; | |
17e6a845 | 57 | hw->aq.asq.len = I40E_VF_ATQLEN1; |
87dc3464 SN |
58 | hw->aq.asq.bal = I40E_VF_ATQBAL1; |
59 | hw->aq.asq.bah = I40E_VF_ATQBAH1; | |
56a62fc8 JB |
60 | hw->aq.arq.tail = I40E_VF_ARQT1; |
61 | hw->aq.arq.head = I40E_VF_ARQH1; | |
17e6a845 | 62 | hw->aq.arq.len = I40E_VF_ARQLEN1; |
87dc3464 SN |
63 | hw->aq.arq.bal = I40E_VF_ARQBAL1; |
64 | hw->aq.arq.bah = I40E_VF_ARQBAH1; | |
56a62fc8 JB |
65 | } else { |
66 | hw->aq.asq.tail = I40E_PF_ATQT; | |
67 | hw->aq.asq.head = I40E_PF_ATQH; | |
17e6a845 | 68 | hw->aq.asq.len = I40E_PF_ATQLEN; |
87dc3464 SN |
69 | hw->aq.asq.bal = I40E_PF_ATQBAL; |
70 | hw->aq.asq.bah = I40E_PF_ATQBAH; | |
56a62fc8 JB |
71 | hw->aq.arq.tail = I40E_PF_ARQT; |
72 | hw->aq.arq.head = I40E_PF_ARQH; | |
17e6a845 | 73 | hw->aq.arq.len = I40E_PF_ARQLEN; |
87dc3464 SN |
74 | hw->aq.arq.bal = I40E_PF_ARQBAL; |
75 | hw->aq.arq.bah = I40E_PF_ARQBAH; | |
56a62fc8 JB |
76 | } |
77 | } | |
78 | ||
79 | /** | |
80 | * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings | |
81 | * @hw: pointer to the hardware structure | |
82 | **/ | |
83 | static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) | |
84 | { | |
85 | i40e_status ret_code; | |
56a62fc8 | 86 | |
90bb776a | 87 | ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, |
56a62fc8 JB |
88 | i40e_mem_atq_ring, |
89 | (hw->aq.num_asq_entries * | |
90 | sizeof(struct i40e_aq_desc)), | |
91 | I40E_ADMINQ_DESC_ALIGNMENT); | |
92 | if (ret_code) | |
93 | return ret_code; | |
94 | ||
90bb776a | 95 | ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, |
56a62fc8 JB |
96 | (hw->aq.num_asq_entries * |
97 | sizeof(struct i40e_asq_cmd_details))); | |
98 | if (ret_code) { | |
90bb776a | 99 | i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); |
56a62fc8 JB |
100 | return ret_code; |
101 | } | |
102 | ||
56a62fc8 JB |
103 | return ret_code; |
104 | } | |
105 | ||
106 | /** | |
107 | * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings | |
108 | * @hw: pointer to the hardware structure | |
109 | **/ | |
110 | static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) | |
111 | { | |
112 | i40e_status ret_code; | |
113 | ||
90bb776a | 114 | ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, |
56a62fc8 JB |
115 | i40e_mem_arq_ring, |
116 | (hw->aq.num_arq_entries * | |
117 | sizeof(struct i40e_aq_desc)), | |
118 | I40E_ADMINQ_DESC_ALIGNMENT); | |
56a62fc8 JB |
119 | |
120 | return ret_code; | |
121 | } | |
122 | ||
123 | /** | |
124 | * i40e_free_adminq_asq - Free Admin Queue send rings | |
125 | * @hw: pointer to the hardware structure | |
126 | * | |
127 | * This assumes the posted send buffers have already been cleaned | |
128 | * and de-allocated | |
129 | **/ | |
130 | static void i40e_free_adminq_asq(struct i40e_hw *hw) | |
131 | { | |
90bb776a | 132 | i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); |
56a62fc8 JB |
133 | } |
134 | ||
135 | /** | |
136 | * i40e_free_adminq_arq - Free Admin Queue receive rings | |
137 | * @hw: pointer to the hardware structure | |
138 | * | |
139 | * This assumes the posted receive buffers have already been cleaned | |
140 | * and de-allocated | |
141 | **/ | |
142 | static void i40e_free_adminq_arq(struct i40e_hw *hw) | |
143 | { | |
90bb776a | 144 | i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); |
56a62fc8 JB |
145 | } |
146 | ||
147 | /** | |
148 | * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue | |
98d44381 | 149 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
150 | **/ |
151 | static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) | |
152 | { | |
153 | i40e_status ret_code; | |
154 | struct i40e_aq_desc *desc; | |
56a62fc8 JB |
155 | struct i40e_dma_mem *bi; |
156 | int i; | |
157 | ||
158 | /* We'll be allocating the buffer info memory first, then we can | |
159 | * allocate the mapped buffers for the event processing | |
160 | */ | |
161 | ||
162 | /* buffer_info structures do not need alignment */ | |
90bb776a DC |
163 | ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, |
164 | (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); | |
56a62fc8 JB |
165 | if (ret_code) |
166 | goto alloc_arq_bufs; | |
90bb776a | 167 | hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; |
56a62fc8 JB |
168 | |
169 | /* allocate the mapped buffers */ | |
170 | for (i = 0; i < hw->aq.num_arq_entries; i++) { | |
171 | bi = &hw->aq.arq.r.arq_bi[i]; | |
172 | ret_code = i40e_allocate_dma_mem(hw, bi, | |
173 | i40e_mem_arq_buf, | |
174 | hw->aq.arq_buf_size, | |
175 | I40E_ADMINQ_DESC_ALIGNMENT); | |
176 | if (ret_code) | |
177 | goto unwind_alloc_arq_bufs; | |
178 | ||
179 | /* now configure the descriptors for use */ | |
180 | desc = I40E_ADMINQ_DESC(hw->aq.arq, i); | |
181 | ||
182 | desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); | |
183 | if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) | |
184 | desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); | |
185 | desc->opcode = 0; | |
186 | /* This is in accordance with Admin queue design, there is no | |
187 | * register for buffer size configuration | |
188 | */ | |
189 | desc->datalen = cpu_to_le16((u16)bi->size); | |
190 | desc->retval = 0; | |
191 | desc->cookie_high = 0; | |
192 | desc->cookie_low = 0; | |
193 | desc->params.external.addr_high = | |
194 | cpu_to_le32(upper_32_bits(bi->pa)); | |
195 | desc->params.external.addr_low = | |
196 | cpu_to_le32(lower_32_bits(bi->pa)); | |
197 | desc->params.external.param0 = 0; | |
198 | desc->params.external.param1 = 0; | |
199 | } | |
200 | ||
201 | alloc_arq_bufs: | |
202 | return ret_code; | |
203 | ||
204 | unwind_alloc_arq_bufs: | |
205 | /* don't try to free the one that failed... */ | |
206 | i--; | |
207 | for (; i >= 0; i--) | |
208 | i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); | |
90bb776a | 209 | i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); |
56a62fc8 JB |
210 | |
211 | return ret_code; | |
212 | } | |
213 | ||
214 | /** | |
215 | * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue | |
98d44381 | 216 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
217 | **/ |
218 | static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) | |
219 | { | |
220 | i40e_status ret_code; | |
56a62fc8 JB |
221 | struct i40e_dma_mem *bi; |
222 | int i; | |
223 | ||
224 | /* No mapped memory needed yet, just the buffer info structures */ | |
90bb776a DC |
225 | ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, |
226 | (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); | |
56a62fc8 JB |
227 | if (ret_code) |
228 | goto alloc_asq_bufs; | |
90bb776a | 229 | hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; |
56a62fc8 JB |
230 | |
231 | /* allocate the mapped buffers */ | |
232 | for (i = 0; i < hw->aq.num_asq_entries; i++) { | |
233 | bi = &hw->aq.asq.r.asq_bi[i]; | |
234 | ret_code = i40e_allocate_dma_mem(hw, bi, | |
235 | i40e_mem_asq_buf, | |
236 | hw->aq.asq_buf_size, | |
237 | I40E_ADMINQ_DESC_ALIGNMENT); | |
238 | if (ret_code) | |
239 | goto unwind_alloc_asq_bufs; | |
240 | } | |
241 | alloc_asq_bufs: | |
242 | return ret_code; | |
243 | ||
244 | unwind_alloc_asq_bufs: | |
245 | /* don't try to free the one that failed... */ | |
246 | i--; | |
247 | for (; i >= 0; i--) | |
248 | i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); | |
90bb776a | 249 | i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); |
56a62fc8 JB |
250 | |
251 | return ret_code; | |
252 | } | |
253 | ||
254 | /** | |
255 | * i40e_free_arq_bufs - Free receive queue buffer info elements | |
98d44381 | 256 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
257 | **/ |
258 | static void i40e_free_arq_bufs(struct i40e_hw *hw) | |
259 | { | |
56a62fc8 JB |
260 | int i; |
261 | ||
90bb776a | 262 | /* free descriptors */ |
56a62fc8 JB |
263 | for (i = 0; i < hw->aq.num_arq_entries; i++) |
264 | i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); | |
265 | ||
90bb776a DC |
266 | /* free the descriptor memory */ |
267 | i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); | |
268 | ||
269 | /* free the dma header */ | |
270 | i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); | |
56a62fc8 JB |
271 | } |
272 | ||
273 | /** | |
274 | * i40e_free_asq_bufs - Free send queue buffer info elements | |
98d44381 | 275 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
276 | **/ |
277 | static void i40e_free_asq_bufs(struct i40e_hw *hw) | |
278 | { | |
56a62fc8 JB |
279 | int i; |
280 | ||
281 | /* only unmap if the address is non-NULL */ | |
282 | for (i = 0; i < hw->aq.num_asq_entries; i++) | |
283 | if (hw->aq.asq.r.asq_bi[i].pa) | |
284 | i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); | |
285 | ||
90bb776a DC |
286 | /* free the buffer info list */ |
287 | i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); | |
288 | ||
289 | /* free the descriptor memory */ | |
290 | i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); | |
291 | ||
292 | /* free the dma header */ | |
293 | i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); | |
56a62fc8 JB |
294 | } |
295 | ||
296 | /** | |
297 | * i40e_config_asq_regs - configure ASQ registers | |
98d44381 | 298 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
299 | * |
300 | * Configure base address and length registers for the transmit queue | |
301 | **/ | |
e03af1e1 | 302 | static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) |
56a62fc8 | 303 | { |
e03af1e1 KK |
304 | i40e_status ret_code = 0; |
305 | u32 reg = 0; | |
306 | ||
80a977e7 MK |
307 | /* Clear Head and Tail */ |
308 | wr32(hw, hw->aq.asq.head, 0); | |
309 | wr32(hw, hw->aq.asq.tail, 0); | |
310 | ||
87dc3464 SN |
311 | /* set starting point */ |
312 | wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | | |
313 | I40E_PF_ATQLEN_ATQENABLE_MASK)); | |
314 | wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); | |
315 | wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); | |
e03af1e1 KK |
316 | |
317 | /* Check one register to verify that config was applied */ | |
87dc3464 | 318 | reg = rd32(hw, hw->aq.asq.bal); |
e03af1e1 KK |
319 | if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) |
320 | ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; | |
321 | ||
322 | return ret_code; | |
56a62fc8 JB |
323 | } |
324 | ||
325 | /** | |
326 | * i40e_config_arq_regs - ARQ register configuration | |
98d44381 | 327 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
328 | * |
329 | * Configure base address and length registers for the receive (event queue) | |
330 | **/ | |
e03af1e1 | 331 | static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) |
56a62fc8 | 332 | { |
e03af1e1 KK |
333 | i40e_status ret_code = 0; |
334 | u32 reg = 0; | |
335 | ||
80a977e7 MK |
336 | /* Clear Head and Tail */ |
337 | wr32(hw, hw->aq.arq.head, 0); | |
338 | wr32(hw, hw->aq.arq.tail, 0); | |
339 | ||
87dc3464 SN |
340 | /* set starting point */ |
341 | wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | | |
342 | I40E_PF_ARQLEN_ARQENABLE_MASK)); | |
343 | wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); | |
344 | wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); | |
56a62fc8 JB |
345 | |
346 | /* Update tail in the HW to post pre-allocated buffers */ | |
347 | wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); | |
e03af1e1 KK |
348 | |
349 | /* Check one register to verify that config was applied */ | |
87dc3464 | 350 | reg = rd32(hw, hw->aq.arq.bal); |
e03af1e1 KK |
351 | if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) |
352 | ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; | |
353 | ||
354 | return ret_code; | |
56a62fc8 JB |
355 | } |
356 | ||
357 | /** | |
358 | * i40e_init_asq - main initialization routine for ASQ | |
98d44381 | 359 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
360 | * |
361 | * This is the main initialization routine for the Admin Send Queue | |
362 | * Prior to calling this function, drivers *MUST* set the following fields | |
363 | * in the hw->aq structure: | |
364 | * - hw->aq.num_asq_entries | |
365 | * - hw->aq.arq_buf_size | |
366 | * | |
367 | * Do *NOT* hold the lock when calling this as the memory allocation routines | |
368 | * called are not going to be atomic context safe | |
369 | **/ | |
370 | static i40e_status i40e_init_asq(struct i40e_hw *hw) | |
371 | { | |
372 | i40e_status ret_code = 0; | |
373 | ||
374 | if (hw->aq.asq.count > 0) { | |
375 | /* queue already initialized */ | |
376 | ret_code = I40E_ERR_NOT_READY; | |
377 | goto init_adminq_exit; | |
378 | } | |
379 | ||
380 | /* verify input for valid configuration */ | |
381 | if ((hw->aq.num_asq_entries == 0) || | |
382 | (hw->aq.asq_buf_size == 0)) { | |
383 | ret_code = I40E_ERR_CONFIG; | |
384 | goto init_adminq_exit; | |
385 | } | |
386 | ||
387 | hw->aq.asq.next_to_use = 0; | |
388 | hw->aq.asq.next_to_clean = 0; | |
56a62fc8 JB |
389 | |
390 | /* allocate the ring memory */ | |
391 | ret_code = i40e_alloc_adminq_asq_ring(hw); | |
392 | if (ret_code) | |
393 | goto init_adminq_exit; | |
394 | ||
395 | /* allocate buffers in the rings */ | |
396 | ret_code = i40e_alloc_asq_bufs(hw); | |
397 | if (ret_code) | |
398 | goto init_adminq_free_rings; | |
399 | ||
400 | /* initialize base registers */ | |
e03af1e1 KK |
401 | ret_code = i40e_config_asq_regs(hw); |
402 | if (ret_code) | |
403 | goto init_adminq_free_rings; | |
56a62fc8 JB |
404 | |
405 | /* success! */ | |
90d2c056 | 406 | hw->aq.asq.count = hw->aq.num_asq_entries; |
56a62fc8 JB |
407 | goto init_adminq_exit; |
408 | ||
409 | init_adminq_free_rings: | |
410 | i40e_free_adminq_asq(hw); | |
411 | ||
412 | init_adminq_exit: | |
413 | return ret_code; | |
414 | } | |
415 | ||
416 | /** | |
417 | * i40e_init_arq - initialize ARQ | |
98d44381 | 418 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
419 | * |
420 | * The main initialization routine for the Admin Receive (Event) Queue. | |
421 | * Prior to calling this function, drivers *MUST* set the following fields | |
422 | * in the hw->aq structure: | |
423 | * - hw->aq.num_asq_entries | |
424 | * - hw->aq.arq_buf_size | |
425 | * | |
426 | * Do *NOT* hold the lock when calling this as the memory allocation routines | |
427 | * called are not going to be atomic context safe | |
428 | **/ | |
429 | static i40e_status i40e_init_arq(struct i40e_hw *hw) | |
430 | { | |
431 | i40e_status ret_code = 0; | |
432 | ||
433 | if (hw->aq.arq.count > 0) { | |
434 | /* queue already initialized */ | |
435 | ret_code = I40E_ERR_NOT_READY; | |
436 | goto init_adminq_exit; | |
437 | } | |
438 | ||
439 | /* verify input for valid configuration */ | |
440 | if ((hw->aq.num_arq_entries == 0) || | |
441 | (hw->aq.arq_buf_size == 0)) { | |
442 | ret_code = I40E_ERR_CONFIG; | |
443 | goto init_adminq_exit; | |
444 | } | |
445 | ||
446 | hw->aq.arq.next_to_use = 0; | |
447 | hw->aq.arq.next_to_clean = 0; | |
56a62fc8 JB |
448 | |
449 | /* allocate the ring memory */ | |
450 | ret_code = i40e_alloc_adminq_arq_ring(hw); | |
451 | if (ret_code) | |
452 | goto init_adminq_exit; | |
453 | ||
454 | /* allocate buffers in the rings */ | |
455 | ret_code = i40e_alloc_arq_bufs(hw); | |
456 | if (ret_code) | |
457 | goto init_adminq_free_rings; | |
458 | ||
459 | /* initialize base registers */ | |
e03af1e1 KK |
460 | ret_code = i40e_config_arq_regs(hw); |
461 | if (ret_code) | |
462 | goto init_adminq_free_rings; | |
56a62fc8 JB |
463 | |
464 | /* success! */ | |
90d2c056 | 465 | hw->aq.arq.count = hw->aq.num_arq_entries; |
56a62fc8 JB |
466 | goto init_adminq_exit; |
467 | ||
468 | init_adminq_free_rings: | |
469 | i40e_free_adminq_arq(hw); | |
470 | ||
471 | init_adminq_exit: | |
472 | return ret_code; | |
473 | } | |
474 | ||
475 | /** | |
476 | * i40e_shutdown_asq - shutdown the ASQ | |
98d44381 | 477 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
478 | * |
479 | * The main shutdown routine for the Admin Send Queue | |
480 | **/ | |
481 | static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) | |
482 | { | |
483 | i40e_status ret_code = 0; | |
484 | ||
24408e7a SN |
485 | mutex_lock(&hw->aq.asq_mutex); |
486 | ||
487 | if (hw->aq.asq.count == 0) { | |
488 | ret_code = I40E_ERR_NOT_READY; | |
489 | goto shutdown_asq_out; | |
490 | } | |
56a62fc8 JB |
491 | |
492 | /* Stop firmware AdminQ processing */ | |
17e6a845 SN |
493 | wr32(hw, hw->aq.asq.head, 0); |
494 | wr32(hw, hw->aq.asq.tail, 0); | |
495 | wr32(hw, hw->aq.asq.len, 0); | |
4346940b SN |
496 | wr32(hw, hw->aq.asq.bal, 0); |
497 | wr32(hw, hw->aq.asq.bah, 0); | |
56a62fc8 | 498 | |
56a62fc8 JB |
499 | hw->aq.asq.count = 0; /* to indicate uninitialized queue */ |
500 | ||
501 | /* free ring buffers */ | |
502 | i40e_free_asq_bufs(hw); | |
56a62fc8 | 503 | |
24408e7a | 504 | shutdown_asq_out: |
56a62fc8 | 505 | mutex_unlock(&hw->aq.asq_mutex); |
56a62fc8 JB |
506 | return ret_code; |
507 | } | |
508 | ||
509 | /** | |
510 | * i40e_shutdown_arq - shutdown ARQ | |
98d44381 | 511 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
512 | * |
513 | * The main shutdown routine for the Admin Receive Queue | |
514 | **/ | |
515 | static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) | |
516 | { | |
517 | i40e_status ret_code = 0; | |
518 | ||
24408e7a SN |
519 | mutex_lock(&hw->aq.arq_mutex); |
520 | ||
521 | if (hw->aq.arq.count == 0) { | |
522 | ret_code = I40E_ERR_NOT_READY; | |
523 | goto shutdown_arq_out; | |
524 | } | |
56a62fc8 JB |
525 | |
526 | /* Stop firmware AdminQ processing */ | |
17e6a845 SN |
527 | wr32(hw, hw->aq.arq.head, 0); |
528 | wr32(hw, hw->aq.arq.tail, 0); | |
529 | wr32(hw, hw->aq.arq.len, 0); | |
4346940b SN |
530 | wr32(hw, hw->aq.arq.bal, 0); |
531 | wr32(hw, hw->aq.arq.bah, 0); | |
56a62fc8 | 532 | |
56a62fc8 JB |
533 | hw->aq.arq.count = 0; /* to indicate uninitialized queue */ |
534 | ||
535 | /* free ring buffers */ | |
536 | i40e_free_arq_bufs(hw); | |
56a62fc8 | 537 | |
24408e7a | 538 | shutdown_arq_out: |
56a62fc8 | 539 | mutex_unlock(&hw->aq.arq_mutex); |
56a62fc8 JB |
540 | return ret_code; |
541 | } | |
542 | ||
543 | /** | |
544 | * i40e_init_adminq - main initialization routine for Admin Queue | |
98d44381 | 545 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
546 | * |
547 | * Prior to calling this function, drivers *MUST* set the following fields | |
548 | * in the hw->aq structure: | |
549 | * - hw->aq.num_asq_entries | |
550 | * - hw->aq.num_arq_entries | |
551 | * - hw->aq.arq_buf_size | |
552 | * - hw->aq.asq_buf_size | |
553 | **/ | |
554 | i40e_status i40e_init_adminq(struct i40e_hw *hw) | |
555 | { | |
ac24382d | 556 | u16 cfg_ptr, oem_hi, oem_lo; |
d4946cf5 | 557 | u16 eetrack_lo, eetrack_hi; |
ac24382d | 558 | i40e_status ret_code; |
d4946cf5 | 559 | int retry = 0; |
56a62fc8 JB |
560 | |
561 | /* verify input for valid configuration */ | |
562 | if ((hw->aq.num_arq_entries == 0) || | |
563 | (hw->aq.num_asq_entries == 0) || | |
564 | (hw->aq.arq_buf_size == 0) || | |
565 | (hw->aq.asq_buf_size == 0)) { | |
566 | ret_code = I40E_ERR_CONFIG; | |
567 | goto init_adminq_exit; | |
568 | } | |
569 | ||
56a62fc8 JB |
570 | /* Set up register offsets */ |
571 | i40e_adminq_init_regs(hw); | |
572 | ||
09c4e56b KK |
573 | /* setup ASQ command write back timeout */ |
574 | hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; | |
575 | ||
56a62fc8 JB |
576 | /* allocate the ASQ */ |
577 | ret_code = i40e_init_asq(hw); | |
578 | if (ret_code) | |
579 | goto init_adminq_destroy_locks; | |
580 | ||
581 | /* allocate the ARQ */ | |
582 | ret_code = i40e_init_arq(hw); | |
583 | if (ret_code) | |
584 | goto init_adminq_free_asq; | |
585 | ||
d4946cf5 SN |
586 | /* There are some cases where the firmware may not be quite ready |
587 | * for AdminQ operations, so we retry the AdminQ setup a few times | |
588 | * if we see timeouts in this first AQ call. | |
589 | */ | |
590 | do { | |
591 | ret_code = i40e_aq_get_firmware_version(hw, | |
592 | &hw->aq.fw_maj_ver, | |
593 | &hw->aq.fw_min_ver, | |
7edf810c | 594 | &hw->aq.fw_build, |
d4946cf5 SN |
595 | &hw->aq.api_maj_ver, |
596 | &hw->aq.api_min_ver, | |
597 | NULL); | |
598 | if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) | |
599 | break; | |
600 | retry++; | |
601 | msleep(100); | |
602 | i40e_resume_aq(hw); | |
603 | } while (retry < 10); | |
604 | if (ret_code != I40E_SUCCESS) | |
56a62fc8 JB |
605 | goto init_adminq_free_arq; |
606 | ||
981b7545 | 607 | /* get the NVM version info */ |
4f651a5b SN |
608 | i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, |
609 | &hw->nvm.version); | |
56a62fc8 JB |
610 | i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); |
611 | i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); | |
612 | hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; | |
ac24382d CW |
613 | i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); |
614 | i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), | |
615 | &oem_hi); | |
616 | i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), | |
617 | &oem_lo); | |
618 | hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; | |
56a62fc8 | 619 | |
7e612411 | 620 | if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { |
981b7545 SN |
621 | ret_code = I40E_ERR_FIRMWARE_API_VERSION; |
622 | goto init_adminq_free_arq; | |
623 | } | |
624 | ||
ff2ff3b4 SN |
625 | /* pre-emptive resource lock release */ |
626 | i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); | |
0f52958b SN |
627 | hw->aq.nvm_release_on_done = false; |
628 | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | |
ff2ff3b4 | 629 | |
56a62fc8 JB |
630 | ret_code = i40e_aq_set_hmc_resource_profile(hw, |
631 | I40E_HMC_PROFILE_DEFAULT, | |
632 | 0, | |
633 | NULL); | |
634 | ret_code = 0; | |
635 | ||
636 | /* success! */ | |
637 | goto init_adminq_exit; | |
638 | ||
639 | init_adminq_free_arq: | |
640 | i40e_shutdown_arq(hw); | |
641 | init_adminq_free_asq: | |
642 | i40e_shutdown_asq(hw); | |
643 | init_adminq_destroy_locks: | |
644 | ||
645 | init_adminq_exit: | |
646 | return ret_code; | |
647 | } | |
648 | ||
649 | /** | |
650 | * i40e_shutdown_adminq - shutdown routine for the Admin Queue | |
98d44381 | 651 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
652 | **/ |
653 | i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) | |
654 | { | |
655 | i40e_status ret_code = 0; | |
656 | ||
e1860d8f ASJ |
657 | if (i40e_check_asq_alive(hw)) |
658 | i40e_aq_queue_shutdown(hw, true); | |
659 | ||
56a62fc8 JB |
660 | i40e_shutdown_asq(hw); |
661 | i40e_shutdown_arq(hw); | |
662 | ||
e4c83c20 SN |
663 | if (hw->nvm_buff.va) |
664 | i40e_free_virt_mem(hw, &hw->nvm_buff); | |
665 | ||
56a62fc8 JB |
666 | return ret_code; |
667 | } | |
668 | ||
669 | /** | |
670 | * i40e_clean_asq - cleans Admin send queue | |
98d44381 | 671 | * @hw: pointer to the hardware structure |
56a62fc8 JB |
672 | * |
673 | * returns the number of free desc | |
674 | **/ | |
675 | static u16 i40e_clean_asq(struct i40e_hw *hw) | |
676 | { | |
677 | struct i40e_adminq_ring *asq = &(hw->aq.asq); | |
678 | struct i40e_asq_cmd_details *details; | |
679 | u16 ntc = asq->next_to_clean; | |
680 | struct i40e_aq_desc desc_cb; | |
681 | struct i40e_aq_desc *desc; | |
682 | ||
683 | desc = I40E_ADMINQ_DESC(*asq, ntc); | |
684 | details = I40E_ADMINQ_DETAILS(*asq, ntc); | |
685 | while (rd32(hw, hw->aq.asq.head) != ntc) { | |
80a977e7 | 686 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, |
6995b36c | 687 | "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); |
80a977e7 | 688 | |
56a62fc8 JB |
689 | if (details->callback) { |
690 | I40E_ADMINQ_CALLBACK cb_func = | |
691 | (I40E_ADMINQ_CALLBACK)details->callback; | |
692 | desc_cb = *desc; | |
693 | cb_func(hw, &desc_cb); | |
694 | } | |
a63fa1cd MW |
695 | memset(desc, 0, sizeof(*desc)); |
696 | memset(details, 0, sizeof(*details)); | |
56a62fc8 JB |
697 | ntc++; |
698 | if (ntc == asq->count) | |
699 | ntc = 0; | |
700 | desc = I40E_ADMINQ_DESC(*asq, ntc); | |
701 | details = I40E_ADMINQ_DETAILS(*asq, ntc); | |
702 | } | |
703 | ||
704 | asq->next_to_clean = ntc; | |
705 | ||
706 | return I40E_DESC_UNUSED(asq); | |
707 | } | |
708 | ||
709 | /** | |
710 | * i40e_asq_done - check if FW has processed the Admin Send Queue | |
711 | * @hw: pointer to the hw struct | |
712 | * | |
713 | * Returns true if the firmware has processed all descriptors on the | |
714 | * admin send queue. Returns false if there are still requests pending. | |
715 | **/ | |
af28eec9 | 716 | static bool i40e_asq_done(struct i40e_hw *hw) |
56a62fc8 JB |
717 | { |
718 | /* AQ designers suggest use of head for better | |
719 | * timing reliability than DD bit | |
720 | */ | |
922680b9 | 721 | return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; |
56a62fc8 JB |
722 | |
723 | } | |
724 | ||
725 | /** | |
726 | * i40e_asq_send_command - send command to Admin Queue | |
727 | * @hw: pointer to the hw struct | |
728 | * @desc: prefilled descriptor describing the command (non DMA mem) | |
729 | * @buff: buffer to use for indirect commands | |
730 | * @buff_size: size of buffer for indirect commands | |
922680b9 | 731 | * @cmd_details: pointer to command details structure |
56a62fc8 JB |
732 | * |
733 | * This is the main send command driver routine for the Admin Queue send | |
734 | * queue. It runs the queue, cleans the queue, etc | |
735 | **/ | |
736 | i40e_status i40e_asq_send_command(struct i40e_hw *hw, | |
737 | struct i40e_aq_desc *desc, | |
738 | void *buff, /* can be NULL */ | |
739 | u16 buff_size, | |
740 | struct i40e_asq_cmd_details *cmd_details) | |
741 | { | |
742 | i40e_status status = 0; | |
743 | struct i40e_dma_mem *dma_buff = NULL; | |
744 | struct i40e_asq_cmd_details *details; | |
745 | struct i40e_aq_desc *desc_on_ring; | |
746 | bool cmd_completed = false; | |
747 | u16 retval = 0; | |
80a977e7 MK |
748 | u32 val = 0; |
749 | ||
24408e7a SN |
750 | mutex_lock(&hw->aq.asq_mutex); |
751 | ||
752 | if (hw->aq.asq.count == 0) { | |
80a977e7 | 753 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, |
24408e7a | 754 | "AQTX: Admin queue not initialized.\n"); |
80a977e7 | 755 | status = I40E_ERR_QUEUE_EMPTY; |
24408e7a | 756 | goto asq_send_command_error; |
80a977e7 | 757 | } |
56a62fc8 | 758 | |
9e1c26e3 SN |
759 | hw->aq.asq_last_status = I40E_AQ_RC_OK; |
760 | ||
24408e7a SN |
761 | val = rd32(hw, hw->aq.asq.head); |
762 | if (val >= hw->aq.num_asq_entries) { | |
56a62fc8 | 763 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, |
24408e7a | 764 | "AQTX: head overrun at %d\n", val); |
56a62fc8 | 765 | status = I40E_ERR_QUEUE_EMPTY; |
24408e7a | 766 | goto asq_send_command_error; |
56a62fc8 JB |
767 | } |
768 | ||
769 | details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); | |
770 | if (cmd_details) { | |
d7595a22 | 771 | *details = *cmd_details; |
56a62fc8 JB |
772 | |
773 | /* If the cmd_details are defined copy the cookie. The | |
774 | * cpu_to_le32 is not needed here because the data is ignored | |
775 | * by the FW, only used by the driver | |
776 | */ | |
777 | if (details->cookie) { | |
778 | desc->cookie_high = | |
779 | cpu_to_le32(upper_32_bits(details->cookie)); | |
780 | desc->cookie_low = | |
781 | cpu_to_le32(lower_32_bits(details->cookie)); | |
782 | } | |
783 | } else { | |
784 | memset(details, 0, sizeof(struct i40e_asq_cmd_details)); | |
785 | } | |
786 | ||
787 | /* clear requested flags and then set additional flags if defined */ | |
788 | desc->flags &= ~cpu_to_le16(details->flags_dis); | |
789 | desc->flags |= cpu_to_le16(details->flags_ena); | |
790 | ||
56a62fc8 JB |
791 | if (buff_size > hw->aq.asq_buf_size) { |
792 | i40e_debug(hw, | |
793 | I40E_DEBUG_AQ_MESSAGE, | |
794 | "AQTX: Invalid buffer size: %d.\n", | |
795 | buff_size); | |
796 | status = I40E_ERR_INVALID_SIZE; | |
797 | goto asq_send_command_error; | |
798 | } | |
799 | ||
800 | if (details->postpone && !details->async) { | |
801 | i40e_debug(hw, | |
802 | I40E_DEBUG_AQ_MESSAGE, | |
803 | "AQTX: Async flag not set along with postpone flag"); | |
804 | status = I40E_ERR_PARAM; | |
805 | goto asq_send_command_error; | |
806 | } | |
807 | ||
808 | /* call clean and check queue available function to reclaim the | |
809 | * descriptors that were processed by FW, the function returns the | |
810 | * number of desc available | |
811 | */ | |
812 | /* the clean function called here could be called in a separate thread | |
813 | * in case of asynchronous completions | |
814 | */ | |
815 | if (i40e_clean_asq(hw) == 0) { | |
816 | i40e_debug(hw, | |
817 | I40E_DEBUG_AQ_MESSAGE, | |
818 | "AQTX: Error queue is full.\n"); | |
819 | status = I40E_ERR_ADMIN_QUEUE_FULL; | |
820 | goto asq_send_command_error; | |
821 | } | |
822 | ||
823 | /* initialize the temp desc pointer with the right desc */ | |
824 | desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); | |
825 | ||
826 | /* if the desc is available copy the temp desc to the right place */ | |
d7595a22 | 827 | *desc_on_ring = *desc; |
56a62fc8 JB |
828 | |
829 | /* if buff is not NULL assume indirect command */ | |
830 | if (buff != NULL) { | |
831 | dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); | |
832 | /* copy the user buff into the respective DMA buff */ | |
833 | memcpy(dma_buff->va, buff, buff_size); | |
834 | desc_on_ring->datalen = cpu_to_le16(buff_size); | |
835 | ||
836 | /* Update the address values in the desc with the pa value | |
837 | * for respective buffer | |
838 | */ | |
839 | desc_on_ring->params.external.addr_high = | |
840 | cpu_to_le32(upper_32_bits(dma_buff->pa)); | |
841 | desc_on_ring->params.external.addr_low = | |
842 | cpu_to_le32(lower_32_bits(dma_buff->pa)); | |
843 | } | |
844 | ||
845 | /* bump the tail */ | |
66d90e7d | 846 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n"); |
f905dd62 SN |
847 | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, |
848 | buff, buff_size); | |
56a62fc8 JB |
849 | (hw->aq.asq.next_to_use)++; |
850 | if (hw->aq.asq.next_to_use == hw->aq.asq.count) | |
851 | hw->aq.asq.next_to_use = 0; | |
852 | if (!details->postpone) | |
853 | wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); | |
854 | ||
855 | /* if cmd_details are not defined or async flag is not set, | |
856 | * we need to wait for desc write back | |
857 | */ | |
858 | if (!details->async && !details->postpone) { | |
859 | u32 total_delay = 0; | |
56a62fc8 JB |
860 | |
861 | do { | |
862 | /* AQ designers suggest use of head for better | |
863 | * timing reliability than DD bit | |
864 | */ | |
865 | if (i40e_asq_done(hw)) | |
866 | break; | |
0db4e162 KK |
867 | usleep_range(1000, 2000); |
868 | total_delay++; | |
ec9a7db7 | 869 | } while (total_delay < hw->aq.asq_cmd_timeout); |
56a62fc8 JB |
870 | } |
871 | ||
872 | /* if ready, copy the desc back to temp */ | |
873 | if (i40e_asq_done(hw)) { | |
d7595a22 | 874 | *desc = *desc_on_ring; |
56a62fc8 JB |
875 | if (buff != NULL) |
876 | memcpy(buff, dma_buff->va, buff_size); | |
877 | retval = le16_to_cpu(desc->retval); | |
878 | if (retval != 0) { | |
879 | i40e_debug(hw, | |
880 | I40E_DEBUG_AQ_MESSAGE, | |
881 | "AQTX: Command completed with error 0x%X.\n", | |
882 | retval); | |
66d90e7d | 883 | |
56a62fc8 JB |
884 | /* strip off FW internal code */ |
885 | retval &= 0xff; | |
886 | } | |
887 | cmd_completed = true; | |
888 | if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) | |
889 | status = 0; | |
890 | else | |
891 | status = I40E_ERR_ADMIN_QUEUE_ERROR; | |
892 | hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; | |
893 | } | |
894 | ||
e3effd73 SN |
895 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, |
896 | "AQTX: desc and buffer writeback:\n"); | |
f905dd62 | 897 | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); |
87db27a9 SN |
898 | |
899 | /* save writeback aq if requested */ | |
900 | if (details->wb_desc) | |
901 | *details->wb_desc = *desc_on_ring; | |
66d90e7d | 902 | |
56a62fc8 JB |
903 | /* update the error if time out occurred */ |
904 | if ((!cmd_completed) && | |
905 | (!details->async && !details->postpone)) { | |
906 | i40e_debug(hw, | |
907 | I40E_DEBUG_AQ_MESSAGE, | |
908 | "AQTX: Writeback timeout.\n"); | |
909 | status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; | |
910 | } | |
911 | ||
912 | asq_send_command_error: | |
913 | mutex_unlock(&hw->aq.asq_mutex); | |
56a62fc8 JB |
914 | return status; |
915 | } | |
916 | ||
917 | /** | |
918 | * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function | |
919 | * @desc: pointer to the temp descriptor (non DMA mem) | |
920 | * @opcode: the opcode can be used to decide which flags to turn off or on | |
921 | * | |
922 | * Fill the desc with default values | |
923 | **/ | |
924 | void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, | |
925 | u16 opcode) | |
926 | { | |
927 | /* zero out the desc */ | |
928 | memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); | |
929 | desc->opcode = cpu_to_le16(opcode); | |
ab954cba | 930 | desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI); |
56a62fc8 JB |
931 | } |
932 | ||
933 | /** | |
934 | * i40e_clean_arq_element | |
935 | * @hw: pointer to the hw struct | |
936 | * @e: event info from the receive descriptor, includes any buffers | |
937 | * @pending: number of events that could be left to process | |
938 | * | |
939 | * This function cleans one Admin Receive Queue element and returns | |
940 | * the contents through e. It can also return how many events are | |
941 | * left to process through 'pending' | |
942 | **/ | |
943 | i40e_status i40e_clean_arq_element(struct i40e_hw *hw, | |
944 | struct i40e_arq_event_info *e, | |
945 | u16 *pending) | |
946 | { | |
947 | i40e_status ret_code = 0; | |
948 | u16 ntc = hw->aq.arq.next_to_clean; | |
949 | struct i40e_aq_desc *desc; | |
950 | struct i40e_dma_mem *bi; | |
951 | u16 desc_idx; | |
952 | u16 datalen; | |
953 | u16 flags; | |
954 | u16 ntu; | |
955 | ||
956 | /* take the lock before we start messing with the ring */ | |
957 | mutex_lock(&hw->aq.arq_mutex); | |
958 | ||
43ae93a9 MW |
959 | if (hw->aq.arq.count == 0) { |
960 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | |
961 | "AQRX: Admin queue not initialized.\n"); | |
962 | ret_code = I40E_ERR_QUEUE_EMPTY; | |
963 | goto clean_arq_element_err; | |
964 | } | |
965 | ||
56a62fc8 JB |
966 | /* set next_to_use to head */ |
967 | ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); | |
968 | if (ntu == ntc) { | |
969 | /* nothing to do - shouldn't need to update ring's values */ | |
56a62fc8 JB |
970 | ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; |
971 | goto clean_arq_element_out; | |
972 | } | |
973 | ||
974 | /* now clean the next descriptor */ | |
975 | desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); | |
976 | desc_idx = ntc; | |
56a62fc8 JB |
977 | |
978 | flags = le16_to_cpu(desc->flags); | |
979 | if (flags & I40E_AQ_FLAG_ERR) { | |
980 | ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; | |
981 | hw->aq.arq_last_status = | |
982 | (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); | |
983 | i40e_debug(hw, | |
984 | I40E_DEBUG_AQ_MESSAGE, | |
985 | "AQRX: Event received with error 0x%X.\n", | |
986 | hw->aq.arq_last_status); | |
56a62fc8 JB |
987 | } |
988 | ||
77813d0a KK |
989 | e->desc = *desc; |
990 | datalen = le16_to_cpu(desc->datalen); | |
1001dc37 MW |
991 | e->msg_len = min(datalen, e->buf_len); |
992 | if (e->msg_buf != NULL && (e->msg_len != 0)) | |
77813d0a | 993 | memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, |
1001dc37 | 994 | e->msg_len); |
77813d0a | 995 | |
66d90e7d | 996 | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n"); |
f905dd62 SN |
997 | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, |
998 | hw->aq.arq_buf_size); | |
66d90e7d | 999 | |
56a62fc8 JB |
1000 | /* Restore the original datalen and buffer address in the desc, |
1001 | * FW updates datalen to indicate the event message | |
1002 | * size | |
1003 | */ | |
1004 | bi = &hw->aq.arq.r.arq_bi[ntc]; | |
90077773 MW |
1005 | memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); |
1006 | ||
1007 | desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); | |
1008 | if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) | |
1009 | desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); | |
56a62fc8 JB |
1010 | desc->datalen = cpu_to_le16((u16)bi->size); |
1011 | desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); | |
1012 | desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); | |
1013 | ||
1014 | /* set tail = the last cleaned desc index. */ | |
1015 | wr32(hw, hw->aq.arq.tail, ntc); | |
1016 | /* ntc is updated to tail + 1 */ | |
1017 | ntc++; | |
1018 | if (ntc == hw->aq.num_arq_entries) | |
1019 | ntc = 0; | |
1020 | hw->aq.arq.next_to_clean = ntc; | |
1021 | hw->aq.arq.next_to_use = ntu; | |
1022 | ||
1023 | clean_arq_element_out: | |
1024 | /* Set pending if needed, unlock and return */ | |
1025 | if (pending != NULL) | |
1026 | *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); | |
43ae93a9 MW |
1027 | |
1028 | clean_arq_element_err: | |
56a62fc8 JB |
1029 | mutex_unlock(&hw->aq.arq_mutex); |
1030 | ||
cd552cb4 | 1031 | if (i40e_is_nvm_update_op(&e->desc)) { |
cd552cb4 SN |
1032 | if (hw->aq.nvm_release_on_done) { |
1033 | i40e_release_nvm(hw); | |
1034 | hw->aq.nvm_release_on_done = false; | |
1035 | } | |
2f1b5bc8 SN |
1036 | |
1037 | switch (hw->nvmupd_state) { | |
1038 | case I40E_NVMUPD_STATE_INIT_WAIT: | |
1039 | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | |
1040 | break; | |
1041 | ||
1042 | case I40E_NVMUPD_STATE_WRITE_WAIT: | |
1043 | hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; | |
1044 | break; | |
1045 | ||
1046 | default: | |
1047 | break; | |
1048 | } | |
cd552cb4 SN |
1049 | } |
1050 | ||
56a62fc8 JB |
1051 | return ret_code; |
1052 | } | |
1053 | ||
af28eec9 | 1054 | static void i40e_resume_aq(struct i40e_hw *hw) |
56a62fc8 | 1055 | { |
56a62fc8 JB |
1056 | /* Registers are reset after PF reset */ |
1057 | hw->aq.asq.next_to_use = 0; | |
1058 | hw->aq.asq.next_to_clean = 0; | |
1059 | ||
1060 | i40e_config_asq_regs(hw); | |
56a62fc8 JB |
1061 | |
1062 | hw->aq.arq.next_to_use = 0; | |
1063 | hw->aq.arq.next_to_clean = 0; | |
1064 | ||
1065 | i40e_config_arq_regs(hw); | |
56a62fc8 | 1066 | } |