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i40evf: set flags before sending message
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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
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5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
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15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
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17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_ADMINQ_H_
28#define _I40E_ADMINQ_H_
29
30#include "i40e_osdep.h"
31#include "i40e_adminq_cmd.h"
32
33#define I40E_ADMINQ_DESC(R, i) \
90bb776a 34 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
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35
36#define I40E_ADMINQ_DESC_ALIGNMENT 4096
37
38struct i40e_adminq_ring {
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39 struct i40e_virt_mem dma_head; /* space for dma structures */
40 struct i40e_dma_mem desc_buf; /* descriptor ring memory */
41 struct i40e_virt_mem cmd_buf; /* command buffer memory */
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42
43 union {
44 struct i40e_dma_mem *asq_bi;
45 struct i40e_dma_mem *arq_bi;
46 } r;
47
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48 u16 count; /* Number of descriptors */
49 u16 rx_buf_len; /* Admin Receive Queue buffer length */
50
51 /* used for interrupt processing */
52 u16 next_to_use;
53 u16 next_to_clean;
54
55 /* used for queue tracking */
56 u32 head;
57 u32 tail;
17e6a845 58 u32 len;
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59 u32 bah;
60 u32 bal;
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61};
62
63/* ASQ transaction details */
64struct i40e_asq_cmd_details {
65 void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
66 u64 cookie;
67 u16 flags_ena;
68 u16 flags_dis;
69 bool async;
70 bool postpone;
71};
72
73#define I40E_ADMINQ_DETAILS(R, i) \
90bb776a 74 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
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75
76/* ARQ event information */
77struct i40e_arq_event_info {
78 struct i40e_aq_desc desc;
79 u16 msg_size;
80 u8 *msg_buf;
81};
82
83/* Admin Queue information */
84struct i40e_adminq_info {
85 struct i40e_adminq_ring arq; /* receive queue */
86 struct i40e_adminq_ring asq; /* send queue */
87 u16 num_arq_entries; /* receive queue depth */
88 u16 num_asq_entries; /* send queue depth */
89 u16 arq_buf_size; /* receive queue buffer size */
90 u16 asq_buf_size; /* send queue buffer size */
91 u16 fw_maj_ver; /* firmware major version */
92 u16 fw_min_ver; /* firmware minor version */
93 u16 api_maj_ver; /* api major version */
94 u16 api_min_ver; /* api minor version */
c9296ad2 95 bool nvm_busy;
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96
97 struct mutex asq_mutex; /* Send queue lock */
98 struct mutex arq_mutex; /* Receive queue lock */
99
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100 /* last status values on send and receive queues */
101 enum i40e_admin_queue_err asq_last_status;
102 enum i40e_admin_queue_err arq_last_status;
103};
104
105/* general information */
106#define I40E_AQ_LARGE_BUF 512
107#define I40E_ASQ_CMD_TIMEOUT 100000 /* usecs */
108
109void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
110 u16 opcode);
111
112#endif /* _I40E_ADMINQ_H_ */