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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_adminq_cmd.h
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_ADMINQ_CMD_H_
28#define _I40E_ADMINQ_CMD_H_
29
30/* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36#define I40E_FW_API_VERSION_MAJOR 0x0001
981b7545 37#define I40E_FW_API_VERSION_MINOR 0x0001
56a62fc8
JB		 38
39struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61};
62
63/* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68/* command flags and offsets*/
69#define I40E_AQ_FLAG_DD_SHIFT 0
70#define I40E_AQ_FLAG_CMP_SHIFT 1
71#define I40E_AQ_FLAG_ERR_SHIFT 2
72#define I40E_AQ_FLAG_VFE_SHIFT 3
73#define I40E_AQ_FLAG_LB_SHIFT 9
74#define I40E_AQ_FLAG_RD_SHIFT 10
75#define I40E_AQ_FLAG_VFC_SHIFT 11
76#define I40E_AQ_FLAG_BUF_SHIFT 12
77#define I40E_AQ_FLAG_SI_SHIFT 13
78#define I40E_AQ_FLAG_EI_SHIFT 14
79#define I40E_AQ_FLAG_FE_SHIFT 15
80
81#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93/* error codes */
94enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118};
119
120/* Admin Queue command opcodes */
121enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126
127 /* resource ownership */
128 i40e_aqc_opc_request_resource = 0x0008,
129 i40e_aqc_opc_release_resource = 0x0009,
130
131 i40e_aqc_opc_list_func_capabilities = 0x000A,
132 i40e_aqc_opc_list_dev_capabilities = 0x000B,
133
134 i40e_aqc_opc_set_cppm_configuration = 0x0103,
135 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
136 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
137
138 /* LAA */
981b7545 139 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
56a62fc8
JB		 140 i40e_aqc_opc_mac_address_read = 0x0107,
141 i40e_aqc_opc_mac_address_write = 0x0108,
142
981b7545
SN		 143 /* PXE */
144 i40e_aqc_opc_clear_pxe_mode = 0x0110,
145
56a62fc8
JB		 146 /* internal switch commands */
147 i40e_aqc_opc_get_switch_config = 0x0200,
148 i40e_aqc_opc_add_statistics = 0x0201,
149 i40e_aqc_opc_remove_statistics = 0x0202,
150 i40e_aqc_opc_set_port_parameters = 0x0203,
151 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
152
153 i40e_aqc_opc_add_vsi = 0x0210,
154 i40e_aqc_opc_update_vsi_parameters = 0x0211,
155 i40e_aqc_opc_get_vsi_parameters = 0x0212,
156
157 i40e_aqc_opc_add_pv = 0x0220,
158 i40e_aqc_opc_update_pv_parameters = 0x0221,
159 i40e_aqc_opc_get_pv_parameters = 0x0222,
160
161 i40e_aqc_opc_add_veb = 0x0230,
162 i40e_aqc_opc_update_veb_parameters = 0x0231,
163 i40e_aqc_opc_get_veb_parameters = 0x0232,
164
165 i40e_aqc_opc_delete_element = 0x0243,
166
167 i40e_aqc_opc_add_macvlan = 0x0250,
168 i40e_aqc_opc_remove_macvlan = 0x0251,
169 i40e_aqc_opc_add_vlan = 0x0252,
170 i40e_aqc_opc_remove_vlan = 0x0253,
171 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
172 i40e_aqc_opc_add_tag = 0x0255,
173 i40e_aqc_opc_remove_tag = 0x0256,
174 i40e_aqc_opc_add_multicast_etag = 0x0257,
175 i40e_aqc_opc_remove_multicast_etag = 0x0258,
176 i40e_aqc_opc_update_tag = 0x0259,
177 i40e_aqc_opc_add_control_packet_filter = 0x025A,
178 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
179 i40e_aqc_opc_add_cloud_filters = 0x025C,
180 i40e_aqc_opc_remove_cloud_filters = 0x025D,
181
182 i40e_aqc_opc_add_mirror_rule = 0x0260,
183 i40e_aqc_opc_delete_mirror_rule = 0x0261,
184
185 i40e_aqc_opc_set_storm_control_config = 0x0280,
186 i40e_aqc_opc_get_storm_control_config = 0x0281,
187
188 /* DCB commands */
189 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
190 i40e_aqc_opc_dcb_updated = 0x0302,
191
192 /* TX scheduler */
193 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
194 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
195 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
196 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
197 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
198 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
199
200 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
201 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
202 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
203 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
204 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
205 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
206 i40e_aqc_opc_query_port_ets_config = 0x0419,
207 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
208 i40e_aqc_opc_suspend_port_tx = 0x041B,
209 i40e_aqc_opc_resume_port_tx = 0x041C,
210
211 /* hmc */
212 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
213 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
214
215 /* phy commands*/
216 i40e_aqc_opc_get_phy_abilities = 0x0600,
217 i40e_aqc_opc_set_phy_config = 0x0601,
218 i40e_aqc_opc_set_mac_config = 0x0603,
219 i40e_aqc_opc_set_link_restart_an = 0x0605,
220 i40e_aqc_opc_get_link_status = 0x0607,
221 i40e_aqc_opc_set_phy_int_mask = 0x0613,
222 i40e_aqc_opc_get_local_advt_reg = 0x0614,
223 i40e_aqc_opc_set_local_advt_reg = 0x0615,
224 i40e_aqc_opc_get_partner_advt = 0x0616,
225 i40e_aqc_opc_set_lb_modes = 0x0618,
226 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
227 i40e_aqc_opc_set_phy_reset = 0x0622,
228 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
229
230 /* NVM commands */
231 i40e_aqc_opc_nvm_read = 0x0701,
232 i40e_aqc_opc_nvm_erase = 0x0702,
233 i40e_aqc_opc_nvm_update = 0x0703,
234
235 /* virtualization commands */
236 i40e_aqc_opc_send_msg_to_pf = 0x0801,
237 i40e_aqc_opc_send_msg_to_vf = 0x0802,
238 i40e_aqc_opc_send_msg_to_peer = 0x0803,
239
240 /* alternate structure */
241 i40e_aqc_opc_alternate_write = 0x0900,
242 i40e_aqc_opc_alternate_write_indirect = 0x0901,
243 i40e_aqc_opc_alternate_read = 0x0902,
244 i40e_aqc_opc_alternate_read_indirect = 0x0903,
245 i40e_aqc_opc_alternate_write_done = 0x0904,
246 i40e_aqc_opc_alternate_set_mode = 0x0905,
247 i40e_aqc_opc_alternate_clear_port = 0x0906,
248
249 /* LLDP commands */
250 i40e_aqc_opc_lldp_get_mib = 0x0A00,
251 i40e_aqc_opc_lldp_update_mib = 0x0A01,
252 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
253 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
254 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
255 i40e_aqc_opc_lldp_stop = 0x0A05,
256 i40e_aqc_opc_lldp_start = 0x0A06,
257
258 /* Tunnel commands */
259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
261 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
262
263 /* Async Events */
264 i40e_aqc_opc_event_lan_overflow = 0x1001,
265
266 /* OEM commands */
267 i40e_aqc_opc_oem_parameter_change = 0xFE00,
268 i40e_aqc_opc_oem_device_status_change = 0xFE01,
269
270 /* debug commands */
271 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
272 i40e_aqc_opc_debug_set_mode = 0xFF01,
273 i40e_aqc_opc_debug_read_reg = 0xFF03,
274 i40e_aqc_opc_debug_write_reg = 0xFF04,
275 i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
276 i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
277 i40e_aqc_opc_debug_modify_reg = 0xFF07,
278 i40e_aqc_opc_debug_dump_internals = 0xFF08,
279 i40e_aqc_opc_debug_modify_internals = 0xFF09,
280};
281
282/* command structures and indirect data structures */
283
284/* Structure naming conventions:
285 * - no suffix for direct command descriptor structures
286 * - _data for indirect sent data
287 * - _resp for indirect return data (data which is both will use _data)
288 * - _completion for direct return data
289 * - _element_ for repeated elements (may also be _data or _resp)
290 *
291 * Command structures are expected to overlay the params.raw member of the basic
292 * descriptor, and as such cannot exceed 16 bytes in length.
293 */
294
295/* This macro is used to generate a compilation error if a structure
296 * is not exactly the correct length. It gives a divide by zero error if the
297 * structure is not of the correct size, otherwise it creates an enum that is
298 * never used.
299 */
300#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302
303/* This macro is used extensively to ensure that command structures are 16
304 * bytes in length as they have to map to the raw array of that size.
305 */
306#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
307
308/* internal (0x00XX) commands */
309
310/* Get version (direct 0x0001) */
311struct i40e_aqc_get_version {
312 __le32 rom_ver;
313 __le32 fw_build;
314 __le16 fw_major;
315 __le16 fw_minor;
316 __le16 api_major;
317 __le16 api_minor;
318};
319
320I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321
981b7545 322/* Send driver version (indirect 0x0002) */
56a62fc8
JB		 323struct i40e_aqc_driver_version {
324 u8 driver_major_ver;
325 u8 driver_minor_ver;
326 u8 driver_build_ver;
327 u8 driver_subbuild_ver;
981b7545
SN		 328 u8 reserved[4];
329 __le32 address_high;
330 __le32 address_low;
56a62fc8
JB		 331};
332
333I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334
335/* Queue Shutdown (direct 0x0003) */
336struct i40e_aqc_queue_shutdown {
337 __le32 driver_unloading;
338#define I40E_AQ_DRIVER_UNLOADING 0x1
339 u8 reserved[12];
340};
341
342I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343
344/* Request resource ownership (direct 0x0008)
345 * Release resource ownership (direct 0x0009)
346 */
347#define I40E_AQ_RESOURCE_NVM 1
348#define I40E_AQ_RESOURCE_SDP 2
349#define I40E_AQ_RESOURCE_ACCESS_READ 1
350#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
351#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
352#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
353
354struct i40e_aqc_request_resource {
355 __le16 resource_id;
356 __le16 access_type;
357 __le32 timeout;
358 __le32 resource_number;
359 u8 reserved[4];
360};
361
362I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
363
364/* Get function capabilities (indirect 0x000A)
365 * Get device capabilities (indirect 0x000B)
366 */
367struct i40e_aqc_list_capabilites {
368 u8 command_flags;
369#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
370 u8 pf_index;
371 u8 reserved[2];
372 __le32 count;
373 __le32 addr_high;
374 __le32 addr_low;
375};
376
377I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
378
379struct i40e_aqc_list_capabilities_element_resp {
380 __le16 id;
381 u8 major_rev;
382 u8 minor_rev;
383 __le32 number;
384 __le32 logical_id;
385 __le32 phys_id;
386 u8 reserved[16];
387};
388
389/* list of caps */
390
391#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
392#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
393#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
394#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
395#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
396#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
397#define I40E_AQ_CAP_ID_SRIOV 0x0012
398#define I40E_AQ_CAP_ID_VF 0x0013
399#define I40E_AQ_CAP_ID_VMDQ 0x0014
400#define I40E_AQ_CAP_ID_8021QBG 0x0015
401#define I40E_AQ_CAP_ID_8021QBR 0x0016
402#define I40E_AQ_CAP_ID_VSI 0x0017
403#define I40E_AQ_CAP_ID_DCB 0x0018
404#define I40E_AQ_CAP_ID_FCOE 0x0021
405#define I40E_AQ_CAP_ID_RSS 0x0040
406#define I40E_AQ_CAP_ID_RXQ 0x0041
407#define I40E_AQ_CAP_ID_TXQ 0x0042
408#define I40E_AQ_CAP_ID_MSIX 0x0043
409#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
410#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
411#define I40E_AQ_CAP_ID_1588 0x0046
412#define I40E_AQ_CAP_ID_IWARP 0x0051
413#define I40E_AQ_CAP_ID_LED 0x0061
414#define I40E_AQ_CAP_ID_SDP 0x0062
415#define I40E_AQ_CAP_ID_MDIO 0x0063
416#define I40E_AQ_CAP_ID_FLEX10 0x00F1
417#define I40E_AQ_CAP_ID_CEM 0x00F2
418
419/* Set CPPM Configuration (direct 0x0103) */
420struct i40e_aqc_cppm_configuration {
421 __le16 command_flags;
422#define I40E_AQ_CPPM_EN_LTRC 0x0800
423#define I40E_AQ_CPPM_EN_DMCTH 0x1000
424#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
425#define I40E_AQ_CPPM_EN_HPTC 0x4000
426#define I40E_AQ_CPPM_EN_DMARC 0x8000
427 __le16 ttlx;
428 __le32 dmacr;
429 __le16 dmcth;
430 u8 hptc;
431 u8 reserved;
432 __le32 pfltrc;
433};
434
435I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
436
437/* Set ARP Proxy command / response (indirect 0x0104) */
438struct i40e_aqc_arp_proxy_data {
439 __le16 command_flags;
440#define I40E_AQ_ARP_INIT_IPV4 0x0008
441#define I40E_AQ_ARP_UNSUP_CTL 0x0010
442#define I40E_AQ_ARP_ENA 0x0020
443#define I40E_AQ_ARP_ADD_IPV4 0x0040
444#define I40E_AQ_ARP_DEL_IPV4 0x0080
445 __le16 table_id;
446 __le32 pfpm_proxyfc;
447 __le32 ip_addr;
448 u8 mac_addr[6];
449};
450
451/* Set NS Proxy Table Entry Command (indirect 0x0105) */
452struct i40e_aqc_ns_proxy_data {
453 __le16 table_idx_mac_addr_0;
454 __le16 table_idx_mac_addr_1;
455 __le16 table_idx_ipv6_0;
456 __le16 table_idx_ipv6_1;
457 __le16 control;
458#define I40E_AQ_NS_PROXY_ADD_0 0x0100
459#define I40E_AQ_NS_PROXY_DEL_0 0x0200
460#define I40E_AQ_NS_PROXY_ADD_1 0x0400
461#define I40E_AQ_NS_PROXY_DEL_1 0x0800
462#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
463#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
464#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
465#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
466#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
467#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
468#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
469 u8 mac_addr_0[6];
470 u8 mac_addr_1[6];
471 u8 local_mac_addr[6];
472 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
473 u8 ipv6_addr_1[16];
474};
475
476/* Manage LAA Command (0x0106) - obsolete */
477struct i40e_aqc_mng_laa {
478 __le16 command_flags;
479#define I40E_AQ_LAA_FLAG_WR 0x8000
480 u8 reserved[2];
481 __le32 sal;
482 __le16 sah;
483 u8 reserved2[6];
484};
485
981b7545 486/* Manage MAC Address Read Command (indirect 0x0107) */
56a62fc8
JB		 487struct i40e_aqc_mac_address_read {
488 __le16 command_flags;
489#define I40E_AQC_LAN_ADDR_VALID 0x10
490#define I40E_AQC_SAN_ADDR_VALID 0x20
491#define I40E_AQC_PORT_ADDR_VALID 0x40
492#define I40E_AQC_WOL_ADDR_VALID 0x80
493#define I40E_AQC_ADDR_VALID_MASK 0xf0
494 u8 reserved[6];
495 __le32 addr_high;
496 __le32 addr_low;
497};
498
499I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
500
501struct i40e_aqc_mac_address_read_data {
502 u8 pf_lan_mac[6];
503 u8 pf_san_mac[6];
504 u8 port_mac[6];
505 u8 pf_wol_mac[6];
506};
507
508I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
509
510/* Manage MAC Address Write Command (0x0108) */
511struct i40e_aqc_mac_address_write {
512 __le16 command_flags;
513#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
514#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
515#define I40E_AQC_WRITE_TYPE_PORT 0x8000
516#define I40E_AQC_WRITE_TYPE_MASK 0xc000
517 __le16 mac_sah;
518 __le32 mac_sal;
519 u8 reserved[8];
520};
521
522I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
523
981b7545
SN		 524/* PXE commands (0x011x) */
525
526/* Clear PXE Command and response (direct 0x0110) */
527struct i40e_aqc_clear_pxe {
528 u8 rx_cnt;
529 u8 reserved[15];
530};
531
532I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
533
56a62fc8
JB		 534/* Switch configuration commands (0x02xx) */
535
536/* Used by many indirect commands that only pass an seid and a buffer in the
537 * command
538 */
539struct i40e_aqc_switch_seid {
540 __le16 seid;
541 u8 reserved[6];
542 __le32 addr_high;
543 __le32 addr_low;
544};
545
546I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
547
548/* Get Switch Configuration command (indirect 0x0200)
549 * uses i40e_aqc_switch_seid for the descriptor
550 */
551struct i40e_aqc_get_switch_config_header_resp {
552 __le16 num_reported;
553 __le16 num_total;
554 u8 reserved[12];
555};
556
557struct i40e_aqc_switch_config_element_resp {
558 u8 element_type;
559#define I40E_AQ_SW_ELEM_TYPE_MAC 1
560#define I40E_AQ_SW_ELEM_TYPE_PF 2
561#define I40E_AQ_SW_ELEM_TYPE_VF 3
562#define I40E_AQ_SW_ELEM_TYPE_EMP 4
563#define I40E_AQ_SW_ELEM_TYPE_BMC 5
564#define I40E_AQ_SW_ELEM_TYPE_PV 16
565#define I40E_AQ_SW_ELEM_TYPE_VEB 17
566#define I40E_AQ_SW_ELEM_TYPE_PA 18
567#define I40E_AQ_SW_ELEM_TYPE_VSI 19
568 u8 revision;
569#define I40E_AQ_SW_ELEM_REV_1 1
570 __le16 seid;
571 __le16 uplink_seid;
572 __le16 downlink_seid;
573 u8 reserved[3];
574 u8 connection_type;
575#define I40E_AQ_CONN_TYPE_REGULAR 0x1
576#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
577#define I40E_AQ_CONN_TYPE_CASCADED 0x3
578 __le16 scheduler_id;
579 __le16 element_info;
580};
581
582/* Get Switch Configuration (indirect 0x0200)
583 * an array of elements are returned in the response buffer
584 * the first in the array is the header, remainder are elements
585 */
586struct i40e_aqc_get_switch_config_resp {
587 struct i40e_aqc_get_switch_config_header_resp header;
588 struct i40e_aqc_switch_config_element_resp element[1];
589};
590
591/* Add Statistics (direct 0x0201)
592 * Remove Statistics (direct 0x0202)
593 */
594struct i40e_aqc_add_remove_statistics {
595 __le16 seid;
596 __le16 vlan;
597 __le16 stat_index;
598 u8 reserved[10];
599};
600
601I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
602
603/* Set Port Parameters command (direct 0x0203) */
604struct i40e_aqc_set_port_parameters {
605 __le16 command_flags;
606#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
607#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
608#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
609 __le16 bad_frame_vsi;
610 __le16 default_seid; /* reserved for command */
611 u8 reserved[10];
612};
613
614I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
615
616/* Get Switch Resource Allocation (indirect 0x0204) */
617struct i40e_aqc_get_switch_resource_alloc {
618 u8 num_entries; /* reserved for command */
619 u8 reserved[7];
620 __le32 addr_high;
621 __le32 addr_low;
622};
623
624I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
625
626/* expect an array of these structs in the response buffer */
627struct i40e_aqc_switch_resource_alloc_element_resp {
628 u8 resource_type;
629#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
630#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
631#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
632#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
633#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
634#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
635#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
636#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
637#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
638#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
639#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
640#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
641#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
642#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
643#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
644#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
645#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
646#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
647#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
648 u8 reserved1;
649 __le16 guaranteed;
650 __le16 total;
651 __le16 used;
652 __le16 total_unalloced;
653 u8 reserved2[6];
654};
655
981b7545 656/* Add VSI (indirect 0x0210)
56a62fc8
JB		 657 * this indirect command uses struct i40e_aqc_vsi_properties_data
658 * as the indirect buffer (128 bytes)
659 *
981b7545
SN		 660 * Update VSI (indirect 0x211)
661 * uses the same data structure as Add VSI
662 *
663 * Get VSI (indirect 0x0212)
664 * uses the same completion and data structure as Add VSI
56a62fc8
JB		 665 */
666struct i40e_aqc_add_get_update_vsi {
667 __le16 uplink_seid;
668 u8 connection_type;
669#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
670#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
671#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
672 u8 reserved1;
673 u8 vf_id;
674 u8 reserved2;
675 __le16 vsi_flags;
676#define I40E_AQ_VSI_TYPE_SHIFT 0x0
677#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
678#define I40E_AQ_VSI_TYPE_VF 0x0
679#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
680#define I40E_AQ_VSI_TYPE_PF 0x2
681#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
682#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
56a62fc8
JB		 683 __le32 addr_high;
684 __le32 addr_low;
685};
686
687I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
688
689struct i40e_aqc_add_get_update_vsi_completion {
690 __le16 seid;
691 __le16 vsi_number;
692 __le16 vsi_used;
693 __le16 vsi_free;
694 __le32 addr_high;
695 __le32 addr_low;
696};
697
698I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
699
700struct i40e_aqc_vsi_properties_data {
701 /* first 96 byte are written by SW */
702 __le16 valid_sections;
703#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
704#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
705#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
706#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
707#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
708#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
709#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
710#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
711#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
712#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
713 /* switch section */
714 __le16 switch_id; /* 12bit id combined with flags below */
715#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
716#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
717#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
718#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
719#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
720 u8 sw_reserved[2];
721 /* security section */
722 u8 sec_flags;
723#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
724#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
725#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
726 u8 sec_reserved;
727 /* VLAN section */
728 __le16 pvid; /* VLANS include priority bits */
729 __le16 fcoe_pvid;
730 u8 port_vlan_flags;
731#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
732#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
733 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
734#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
735#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
736#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
737#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
738#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
739#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
740 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
741#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
742#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
743#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
744#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
745 u8 pvlan_reserved[3];
746 /* ingress egress up sections */
747 __le32 ingress_table; /* bitmap, 3 bits per up */
748#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
749#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
750 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
751#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
752#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
753 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
754#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
755#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
756 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
757#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
758#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
759 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
760#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
761#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
762 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
763#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
764#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
765 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
766#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
767#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
768 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
769#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
770#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
771 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
772 __le32 egress_table; /* same defines as for ingress table */
773 /* cascaded PV section */
774 __le16 cas_pv_tag;
775 u8 cas_pv_flags;
776#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
777#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
778 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
779#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
780#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
781#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
782#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
783#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
784#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
785 u8 cas_pv_reserved;
786 /* queue mapping section */
787 __le16 mapping_flags;
788#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
789#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
790 __le16 queue_mapping[16];
791#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
792#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
793 __le16 tc_mapping[8];
794#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
795#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
796 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
797#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
798#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
799 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
800 /* queueing option section */
801 u8 queueing_opt_flags;
802#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
803#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
804 u8 queueing_opt_reserved[3];
805 /* scheduler section */
806 u8 up_enable_bits;
807 u8 sched_reserved;
808 /* outer up section */
809 __le32 outer_up_table; /* same structure and defines as ingress table */
810 u8 cmd_reserved[8];
811 /* last 32 bytes are written by FW */
812 __le16 qs_handle[8];
813#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
814 __le16 stat_counter_idx;
815 __le16 sched_id;
816 u8 resp_reserved[12];
817};
818
819I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
820
821/* Add Port Virtualizer (direct 0x0220)
822 * also used for update PV (direct 0x0221) but only flags are used
823 * (IS_CTRL_PORT only works on add PV)
824 */
825struct i40e_aqc_add_update_pv {
826 __le16 command_flags;
827#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
828#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
829#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
830#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
831 __le16 uplink_seid;
832 __le16 connected_seid;
833 u8 reserved[10];
834};
835
836I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
837
838struct i40e_aqc_add_update_pv_completion {
839 /* reserved for update; for add also encodes error if rc == ENOSPC */
840 __le16 pv_seid;
841#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
842#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
843#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
844#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
845 u8 reserved[14];
846};
847
848I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
849
850/* Get PV Params (direct 0x0222)
851 * uses i40e_aqc_switch_seid for the descriptor
852 */
853
854struct i40e_aqc_get_pv_params_completion {
855 __le16 seid;
856 __le16 default_stag;
857 __le16 pv_flags; /* same flags as add_pv */
858#define I40E_AQC_GET_PV_PV_TYPE 0x1
859#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
860#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
861 u8 reserved[8];
862 __le16 default_port_seid;
863};
864
865I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
866
867/* Add VEB (direct 0x0230) */
868struct i40e_aqc_add_veb {
869 __le16 uplink_seid;
870 __le16 downlink_seid;
871 __le16 veb_flags;
872#define I40E_AQC_ADD_VEB_FLOATING 0x1
873#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
874#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
875 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
876#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
877#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
878#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
879 u8 enable_tcs;
880 u8 reserved[9];
881};
882
883I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
884
885struct i40e_aqc_add_veb_completion {
886 u8 reserved[6];
887 __le16 switch_seid;
888 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
889 __le16 veb_seid;
890#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
891#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
892#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
893#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
894 __le16 statistic_index;
895 __le16 vebs_used;
896 __le16 vebs_free;
897};
898
899I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
900
901/* Get VEB Parameters (direct 0x0232)
902 * uses i40e_aqc_switch_seid for the descriptor
903 */
904struct i40e_aqc_get_veb_parameters_completion {
905 __le16 seid;
906 __le16 switch_id;
907 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
908 __le16 statistic_index;
909 __le16 vebs_used;
910 __le16 vebs_free;
911 u8 reserved[4];
912};
913
914I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
915
916/* Delete Element (direct 0x0243)
917 * uses the generic i40e_aqc_switch_seid
918 */
919
920/* Add MAC-VLAN (indirect 0x0250) */
921
922/* used for the command for most vlan commands */
923struct i40e_aqc_macvlan {
924 __le16 num_addresses;
925 __le16 seid[3];
926#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
927#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
928 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
929#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
930 __le32 addr_high;
931 __le32 addr_low;
932};
933
934I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
935
936/* indirect data for command and response */
937struct i40e_aqc_add_macvlan_element_data {
938 u8 mac_addr[6];
939 __le16 vlan_tag;
940 __le16 flags;
941#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
942#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
943#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
944#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
945 __le16 queue_number;
946#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
947#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
948 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
949 /* response section */
950 u8 match_method;
951#define I40E_AQC_MM_PERFECT_MATCH 0x01
952#define I40E_AQC_MM_HASH_MATCH 0x02
953#define I40E_AQC_MM_ERR_NO_RES 0xFF
954 u8 reserved1[3];
955};
956
957struct i40e_aqc_add_remove_macvlan_completion {
958 __le16 perfect_mac_used;
959 __le16 perfect_mac_free;
960 __le16 unicast_hash_free;
961 __le16 multicast_hash_free;
962 __le32 addr_high;
963 __le32 addr_low;
964};
965
966I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
967
968/* Remove MAC-VLAN (indirect 0x0251)
969 * uses i40e_aqc_macvlan for the descriptor
970 * data points to an array of num_addresses of elements
971 */
972
973struct i40e_aqc_remove_macvlan_element_data {
974 u8 mac_addr[6];
975 __le16 vlan_tag;
976 u8 flags;
977#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
978#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
979#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
980#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
981 u8 reserved[3];
982 /* reply section */
983 u8 error_code;
984#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
985#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
986 u8 reply_reserved[3];
987};
988
989/* Add VLAN (indirect 0x0252)
990 * Remove VLAN (indirect 0x0253)
991 * use the generic i40e_aqc_macvlan for the command
992 */
993struct i40e_aqc_add_remove_vlan_element_data {
994 __le16 vlan_tag;
995 u8 vlan_flags;
996/* flags for add VLAN */
997#define I40E_AQC_ADD_VLAN_LOCAL 0x1
998#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
999#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \
1000 I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1001#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1002#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1003#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1004#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1005#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1006#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1007#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1008#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1009#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1010/* flags for remove VLAN */
1011#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1012 u8 reserved;
1013 u8 result;
1014/* flags for add VLAN */
1015#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1016#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1017#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1018/* flags for remove VLAN */
1019#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1020#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1021 u8 reserved1[3];
1022};
1023
1024struct i40e_aqc_add_remove_vlan_completion {
1025 u8 reserved[4];
1026 __le16 vlans_used;
1027 __le16 vlans_free;
1028 __le32 addr_high;
1029 __le32 addr_low;
1030};
1031
1032/* Set VSI Promiscuous Modes (direct 0x0254) */
1033struct i40e_aqc_set_vsi_promiscuous_modes {
1034 __le16 promiscuous_flags;
1035 __le16 valid_flags;
1036/* flags used for both fields above */
1037#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1038#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1039#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1040#define I40E_AQC_SET_VSI_DEFAULT 0x08
1041#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1042 __le16 seid;
1043#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
0aebd2d9
SN		 1044 __le16 vlan_tag;
1045#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1046 u8 reserved[8];
56a62fc8
JB		 1047};
1048
1049I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1050
1051/* Add S/E-tag command (direct 0x0255)
1052 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1053 */
1054struct i40e_aqc_add_tag {
1055 __le16 flags;
1056#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1057 __le16 seid;
1058#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1059#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1060 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1061 __le16 tag;
1062 __le16 queue_number;
1063 u8 reserved[8];
1064};
1065
1066I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1067
1068struct i40e_aqc_add_remove_tag_completion {
1069 u8 reserved[12];
1070 __le16 tags_used;
1071 __le16 tags_free;
1072};
1073
1074I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1075
1076/* Remove S/E-tag command (direct 0x0256)
1077 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1078 */
1079struct i40e_aqc_remove_tag {
1080 __le16 seid;
1081#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1082#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1083 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1084 __le16 tag;
1085 u8 reserved[12];
1086};
1087
1088/* Add multicast E-Tag (direct 0x0257)
1089 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1090 * and no external data
1091 */
1092struct i40e_aqc_add_remove_mcast_etag {
1093 __le16 pv_seid;
1094 __le16 etag;
1095 u8 num_unicast_etags;
1096 u8 reserved[3];
1097 __le32 addr_high; /* address of array of 2-byte s-tags */
1098 __le32 addr_low;
1099};
1100
1101I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1102
1103struct i40e_aqc_add_remove_mcast_etag_completion {
1104 u8 reserved[4];
1105 __le16 mcast_etags_used;
1106 __le16 mcast_etags_free;
1107 __le32 addr_high;
1108 __le32 addr_low;
1109
1110};
1111
1112I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1113
1114/* Update S/E-Tag (direct 0x0259) */
1115struct i40e_aqc_update_tag {
1116 __le16 seid;
1117#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1118#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1119 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1120 __le16 old_tag;
1121 __le16 new_tag;
1122 u8 reserved[10];
1123};
1124
1125I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1126
1127struct i40e_aqc_update_tag_completion {
1128 u8 reserved[12];
1129 __le16 tags_used;
1130 __le16 tags_free;
1131};
1132
1133I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1134
1135/* Add Control Packet filter (direct 0x025A)
1136 * Remove Control Packet filter (direct 0x025B)
1137 * uses the i40e_aqc_add_oveb_cloud,
1138 * and the generic direct completion structure
1139 */
1140struct i40e_aqc_add_remove_control_packet_filter {
1141 u8 mac[6];
1142 __le16 etype;
1143 __le16 flags;
1144#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1145#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1146#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1147#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1148#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1149 __le16 seid;
1150#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1151#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1152 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1153 __le16 queue;
1154 u8 reserved[2];
1155};
1156
1157I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1158
1159struct i40e_aqc_add_remove_control_packet_filter_completion {
1160 __le16 mac_etype_used;
1161 __le16 etype_used;
1162 __le16 mac_etype_free;
1163 __le16 etype_free;
1164 u8 reserved[8];
1165};
1166
1167I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1168
1169/* Add Cloud filters (indirect 0x025C)
1170 * Remove Cloud filters (indirect 0x025D)
1171 * uses the i40e_aqc_add_remove_cloud_filters,
1172 * and the generic indirect completion structure
1173 */
1174struct i40e_aqc_add_remove_cloud_filters {
1175 u8 num_filters;
1176 u8 reserved;
1177 __le16 seid;
1178#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1179#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1180 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1181 u8 reserved2[4];
1182 __le32 addr_high;
1183 __le32 addr_low;
1184};
1185
1186I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1187
1188struct i40e_aqc_add_remove_cloud_filters_element_data {
1189 u8 outer_mac[6];
1190 u8 inner_mac[6];
1191 __le16 inner_vlan;
1192 union {
1193 struct {
1194 u8 reserved[12];
1195 u8 data[4];
1196 } v4;
1197 struct {
1198 u8 data[16];
6838b535
JB		 1199 } v6;
1200 } ipaddr;
56a62fc8
JB		 1201 __le16 flags;
1202#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1203#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1204 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
981b7545 1205/* 0x0000 reserved */
56a62fc8 1206#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
981b7545 1207/* 0x0002 reserved */
56a62fc8 1208#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
981b7545
SN		 1209#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1210/* 0x0005 reserved */
56a62fc8 1211#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
981b7545 1212/* 0x0007 reserved */
56a62fc8
JB		 1213/* 0x0008 reserved */
1214#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1215#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
981b7545
SN		 1216#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1217#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1218
56a62fc8
JB		 1219#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1220#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1221#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1222#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1223#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
981b7545
SN		 1224
1225#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1226#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1227#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1228#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1229#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1230#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1231
1232 __le32 tenant_id;
1233 u8 reserved[4];
56a62fc8
JB		 1234 __le16 queue_number;
1235#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1236#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \
1237 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
981b7545 1238 u8 reserved2[14];
56a62fc8
JB		 1239 /* response section */
1240 u8 allocation_result;
1241#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1242#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1243 u8 response_reserved[7];
1244};
1245
1246struct i40e_aqc_remove_cloud_filters_completion {
1247 __le16 perfect_ovlan_used;
1248 __le16 perfect_ovlan_free;
1249 __le16 vlan_used;
1250 __le16 vlan_free;
1251 __le32 addr_high;
1252 __le32 addr_low;
1253};
1254
1255I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1256
1257/* Add Mirror Rule (indirect or direct 0x0260)
1258 * Delete Mirror Rule (indirect or direct 0x0261)
1259 * note: some rule types (4,5) do not use an external buffer.
1260 * take care to set the flags correctly.
1261 */
1262struct i40e_aqc_add_delete_mirror_rule {
1263 __le16 seid;
1264 __le16 rule_type;
1265#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1266#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1267 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1268#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1269#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1270#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1271#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1272#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1273 __le16 num_entries;
1274 __le16 destination; /* VSI for add, rule id for delete */
1275 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1276 __le32 addr_low;
1277};
1278
1279I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1280
1281struct i40e_aqc_add_delete_mirror_rule_completion {
1282 u8 reserved[2];
1283 __le16 rule_id; /* only used on add */
1284 __le16 mirror_rules_used;
1285 __le16 mirror_rules_free;
1286 __le32 addr_high;
1287 __le32 addr_low;
1288};
1289
1290I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1291
1292/* Set Storm Control Configuration (direct 0x0280)
1293 * Get Storm Control Configuration (direct 0x0281)
1294 * the command and response use the same descriptor structure
1295 */
1296struct i40e_aqc_set_get_storm_control_config {
1297 __le32 broadcast_threshold;
1298 __le32 multicast_threshold;
1299 __le32 control_flags;
1300#define I40E_AQC_STORM_CONTROL_MDIPW 0x01
1301#define I40E_AQC_STORM_CONTROL_MDICW 0x02
1302#define I40E_AQC_STORM_CONTROL_BDIPW 0x04
1303#define I40E_AQC_STORM_CONTROL_BDICW 0x08
1304#define I40E_AQC_STORM_CONTROL_BIDU 0x10
1305#define I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT 8
1306#define I40E_AQC_STORM_CONTROL_INTERVAL_MASK (0x3FF << \
1307 I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT)
1308 u8 reserved[4];
1309};
1310
1311I40E_CHECK_CMD_LENGTH(i40e_aqc_set_get_storm_control_config);
1312
1313/* DCB 0x03xx*/
1314
1315/* PFC Ignore (direct 0x0301)
1316 * the command and response use the same descriptor structure
1317 */
1318struct i40e_aqc_pfc_ignore {
1319 u8 tc_bitmap;
1320 u8 command_flags; /* unused on response */
1321#define I40E_AQC_PFC_IGNORE_SET 0x80
1322#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1323 u8 reserved[14];
1324};
1325
1326I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1327
1328/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1329 * with no parameters
1330 */
1331
1332/* TX scheduler 0x04xx */
1333
1334/* Almost all the indirect commands use
1335 * this generic struct to pass the SEID in param0
1336 */
1337struct i40e_aqc_tx_sched_ind {
1338 __le16 vsi_seid;
1339 u8 reserved[6];
1340 __le32 addr_high;
1341 __le32 addr_low;
1342};
1343
1344I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1345
1346/* Several commands respond with a set of queue set handles */
1347struct i40e_aqc_qs_handles_resp {
1348 __le16 qs_handles[8];
1349};
1350
1351/* Configure VSI BW limits (direct 0x0400) */
1352struct i40e_aqc_configure_vsi_bw_limit {
1353 __le16 vsi_seid;
1354 u8 reserved[2];
1355 __le16 credit;
1356 u8 reserved1[2];
1357 u8 max_credit; /* 0-3, limit = 2^max */
1358 u8 reserved2[7];
1359};
1360
1361I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1362
1363/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1364 * responds with i40e_aqc_qs_handles_resp
1365 */
1366struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1367 u8 tc_valid_bits;
1368 u8 reserved[15];
1369 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1370
1371 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1372 __le16 tc_bw_max[2];
1373 u8 reserved1[28];
1374};
1375
1376/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1377 * responds with i40e_aqc_qs_handles_resp
1378 */
1379struct i40e_aqc_configure_vsi_tc_bw_data {
1380 u8 tc_valid_bits;
1381 u8 reserved[3];
1382 u8 tc_bw_credits[8];
1383 u8 reserved1[4];
1384 __le16 qs_handles[8];
1385};
1386
1387/* Query vsi bw configuration (indirect 0x0408) */
1388struct i40e_aqc_query_vsi_bw_config_resp {
1389 u8 tc_valid_bits;
1390 u8 tc_suspended_bits;
1391 u8 reserved[14];
1392 __le16 qs_handles[8];
1393 u8 reserved1[4];
1394 __le16 port_bw_limit;
1395 u8 reserved2[2];
1396 u8 max_bw; /* 0-3, limit = 2^max */
1397 u8 reserved3[23];
1398};
1399
1400/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1401struct i40e_aqc_query_vsi_ets_sla_config_resp {
1402 u8 tc_valid_bits;
1403 u8 reserved[3];
1404 u8 share_credits[8];
1405 __le16 credits[8];
1406
1407 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1408 __le16 tc_bw_max[2];
1409};
1410
1411/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1412struct i40e_aqc_configure_switching_comp_bw_limit {
1413 __le16 seid;
1414 u8 reserved[2];
1415 __le16 credit;
1416 u8 reserved1[2];
1417 u8 max_bw; /* 0-3, limit = 2^max */
1418 u8 reserved2[7];
1419};
1420
1421I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1422
1423/* Enable Physical Port ETS (indirect 0x0413)
1424 * Modify Physical Port ETS (indirect 0x0414)
1425 * Disable Physical Port ETS (indirect 0x0415)
1426 */
1427struct i40e_aqc_configure_switching_comp_ets_data {
1428 u8 reserved[4];
1429 u8 tc_valid_bits;
1430 u8 reserved1;
1431 u8 tc_strict_priority_flags;
1432 u8 reserved2[17];
1433 u8 tc_bw_share_credits[8];
1434 u8 reserved3[96];
1435};
1436
1437/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1438struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1439 u8 tc_valid_bits;
1440 u8 reserved[15];
1441 __le16 tc_bw_credit[8];
1442
1443 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1444 __le16 tc_bw_max[2];
1445 u8 reserved1[28];
1446};
1447
1448/* Configure Switching Component Bandwidth Allocation per Tc
1449 * (indirect 0x0417)
1450 */
1451struct i40e_aqc_configure_switching_comp_bw_config_data {
1452 u8 tc_valid_bits;
1453 u8 reserved[2];
1454 u8 absolute_credits; /* bool */
1455 u8 tc_bw_share_credits[8];
1456 u8 reserved1[20];
1457};
1458
1459/* Query Switching Component Configuration (indirect 0x0418) */
1460struct i40e_aqc_query_switching_comp_ets_config_resp {
1461 u8 tc_valid_bits;
1462 u8 reserved[35];
1463 __le16 port_bw_limit;
1464 u8 reserved1[2];
1465 u8 tc_bw_max; /* 0-3, limit = 2^max */
1466 u8 reserved2[23];
1467};
1468
1469/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1470struct i40e_aqc_query_port_ets_config_resp {
1471 u8 reserved[4];
1472 u8 tc_valid_bits;
1473 u8 reserved1;
1474 u8 tc_strict_priority_bits;
1475 u8 reserved2;
1476 u8 tc_bw_share_credits[8];
1477 __le16 tc_bw_limits[8];
1478
1479 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1480 __le16 tc_bw_max[2];
1481 u8 reserved3[32];
1482};
1483
1484/* Query Switching Component Bandwidth Allocation per Traffic Type
1485 * (indirect 0x041A)
1486 */
1487struct i40e_aqc_query_switching_comp_bw_config_resp {
1488 u8 tc_valid_bits;
1489 u8 reserved[2];
1490 u8 absolute_credits_enable; /* bool */
1491 u8 tc_bw_share_credits[8];
1492 __le16 tc_bw_limits[8];
1493
1494 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1495 __le16 tc_bw_max[2];
1496};
1497
1498/* Suspend/resume port TX traffic
1499 * (direct 0x041B and 0x041C) uses the generic SEID struct
1500 */
1501
1502/* Get and set the active HMC resource profile and status.
1503 * (direct 0x0500) and (direct 0x0501)
1504 */
1505struct i40e_aq_get_set_hmc_resource_profile {
1506 u8 pm_profile;
1507 u8 pe_vf_enabled;
1508 u8 reserved[14];
1509};
1510
1511I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1512
1513enum i40e_aq_hmc_profile {
1514 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1515 I40E_HMC_PROFILE_DEFAULT = 1,
1516 I40E_HMC_PROFILE_FAVOR_VF = 2,
1517 I40E_HMC_PROFILE_EQUAL = 3,
1518};
1519
1520#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1521#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1522
1523/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1524
1525/* set in param0 for get phy abilities to report qualified modules */
1526#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1527#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1528
1529enum i40e_aq_phy_type {
1530 I40E_PHY_TYPE_SGMII = 0x0,
1531 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1532 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1533 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1534 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1535 I40E_PHY_TYPE_XAUI = 0x5,
1536 I40E_PHY_TYPE_XFI = 0x6,
1537 I40E_PHY_TYPE_SFI = 0x7,
1538 I40E_PHY_TYPE_XLAUI = 0x8,
1539 I40E_PHY_TYPE_XLPPI = 0x9,
1540 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1541 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1542 I40E_PHY_TYPE_100BASE_TX = 0x11,
1543 I40E_PHY_TYPE_1000BASE_T = 0x12,
1544 I40E_PHY_TYPE_10GBASE_T = 0x13,
1545 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1546 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1547 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1548 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1549 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1550 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1551 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1552 I40E_PHY_TYPE_20GBASE_KR2 = 0x1B,
1553 I40E_PHY_TYPE_MAX
1554};
1555
1556#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1557#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1558#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1559#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1560#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1561
1562enum i40e_aq_link_speed {
1563 I40E_LINK_SPEED_UNKNOWN = 0,
1564 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1565 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1566 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1567 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1568 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1569};
1570
1571struct i40e_aqc_module_desc {
1572 u8 oui[3];
1573 u8 reserved1;
1574 u8 part_number[16];
1575 u8 revision[4];
1576 u8 reserved2[8];
1577};
1578
1579struct i40e_aq_get_phy_abilities_resp {
1580 __le32 phy_type; /* bitmap using the above enum for offsets */
981b7545 1581 u8 link_speed; /* bitmap using the above enum bit patterns */
56a62fc8
JB		 1582 u8 abilities;
1583#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1584#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1585#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1586#define I40E_AQ_PHY_FLAG_AN_SHIFT 3
1587#define I40E_AQ_PHY_FLAG_AN_MASK (0x3 << I40E_AQ_PHY_FLAG_AN_SHIFT)
1588#define I40E_AQ_PHY_FLAG_AN_OFF 0x00 /* link forced on */
1589#define I40E_AQ_PHY_FLAG_AN_OFF_LINK_DOWN 0x01
1590#define I40E_AQ_PHY_FLAG_AN_ON 0x02
1591#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1592 __le16 eee_capability;
1593#define I40E_AQ_EEE_100BASE_TX 0x0002
1594#define I40E_AQ_EEE_1000BASE_T 0x0004
1595#define I40E_AQ_EEE_10GBASE_T 0x0008
1596#define I40E_AQ_EEE_1000BASE_KX 0x0010
1597#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1598#define I40E_AQ_EEE_10GBASE_KR 0x0040
1599 __le32 eeer_val;
1600 u8 d3_lpan;
1601#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1602 u8 reserved[3];
1603 u8 phy_id[4];
1604 u8 module_type[3];
1605 u8 qualified_module_count;
1606#define I40E_AQ_PHY_MAX_QMS 16
1607 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1608};
1609
1610/* Set PHY Config (direct 0x0601) */
1611struct i40e_aq_set_phy_config { /* same bits as above in all */
1612 __le32 phy_type;
1613 u8 link_speed;
1614 u8 abilities;
981b7545
SN		 1615/* bits 0-2 use the values from get_phy_abilities_resp */
1616#define I40E_AQ_PHY_ENABLE_LINK 0x08
1617#define I40E_AQ_PHY_ENABLE_AN 0x10
1618#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
56a62fc8
JB		 1619 __le16 eee_capability;
1620 __le32 eeer;
1621 u8 low_power_ctrl;
1622 u8 reserved[3];
1623};
1624
1625I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1626
1627/* Set MAC Config command data structure (direct 0x0603) */
1628struct i40e_aq_set_mac_config {
1629 __le16 max_frame_size;
1630 u8 params;
1631#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1632#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1633#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1634#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1635#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1636#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1637#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1638#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1639#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1640#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1641#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1642#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1643#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1644#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1645 u8 tx_timer_priority; /* bitmap */
1646 __le16 tx_timer_value;
1647 __le16 fc_refresh_threshold;
1648 u8 reserved[8];
1649};
1650
1651I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1652
1653/* Restart Auto-Negotiation (direct 0x605) */
1654struct i40e_aqc_set_link_restart_an {
1655 u8 command;
1656#define I40E_AQ_PHY_RESTART_AN 0x02
1657#define I40E_AQ_PHY_LINK_ENABLE 0x04
1658 u8 reserved[15];
1659};
1660
1661I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1662
1663/* Get Link Status cmd & response data structure (direct 0x0607) */
1664struct i40e_aqc_get_link_status {
1665 __le16 command_flags; /* only field set on command */
1666#define I40E_AQ_LSE_MASK 0x3
1667#define I40E_AQ_LSE_NOP 0x0
1668#define I40E_AQ_LSE_DISABLE 0x2
1669#define I40E_AQ_LSE_ENABLE 0x3
1670/* only response uses this flag */
1671#define I40E_AQ_LSE_IS_ENABLED 0x1
1672 u8 phy_type; /* i40e_aq_phy_type */
1673 u8 link_speed; /* i40e_aq_link_speed */
1674 u8 link_info;
1675#define I40E_AQ_LINK_UP 0x01
1676#define I40E_AQ_LINK_FAULT 0x02
1677#define I40E_AQ_LINK_FAULT_TX 0x04
1678#define I40E_AQ_LINK_FAULT_RX 0x08
1679#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1680#define I40E_AQ_MEDIA_AVAILABLE 0x40
1681#define I40E_AQ_SIGNAL_DETECT 0x80
1682 u8 an_info;
1683#define I40E_AQ_AN_COMPLETED 0x01
1684#define I40E_AQ_LP_AN_ABILITY 0x02
1685#define I40E_AQ_PD_FAULT 0x04
1686#define I40E_AQ_FEC_EN 0x08
1687#define I40E_AQ_PHY_LOW_POWER 0x10
1688#define I40E_AQ_LINK_PAUSE_TX 0x20
1689#define I40E_AQ_LINK_PAUSE_RX 0x40
1690#define I40E_AQ_QUALIFIED_MODULE 0x80
1691 u8 ext_info;
1692#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1693#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1694#define I40E_AQ_LINK_TX_SHIFT 0x02
1695#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1696#define I40E_AQ_LINK_TX_ACTIVE 0x00
1697#define I40E_AQ_LINK_TX_DRAINED 0x01
1698#define I40E_AQ_LINK_TX_FLUSHED 0x03
1699 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1700 __le16 max_frame_size;
1701 u8 config;
1702#define I40E_AQ_CONFIG_CRC_ENA 0x04
1703#define I40E_AQ_CONFIG_PACING_MASK 0x78
1704 u8 reserved[5];
1705};
1706
1707I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1708
1709/* Set event mask command (direct 0x613) */
1710struct i40e_aqc_set_phy_int_mask {
1711 u8 reserved[8];
1712 __le16 event_mask;
1713#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1714#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1715#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1716#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1717#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1718#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1719#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1720#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1721#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1722 u8 reserved1[6];
1723};
1724
1725I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1726
1727/* Get Local AN advt register (direct 0x0614)
1728 * Set Local AN advt register (direct 0x0615)
1729 * Get Link Partner AN advt register (direct 0x0616)
1730 */
1731struct i40e_aqc_an_advt_reg {
1732 __le32 local_an_reg0;
1733 __le16 local_an_reg1;
1734 u8 reserved[10];
1735};
1736
1737I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1738
1739/* Set Loopback mode (0x0618) */
1740struct i40e_aqc_set_lb_mode {
1741 __le16 lb_mode;
1742#define I40E_AQ_LB_PHY_LOCAL 0x01
1743#define I40E_AQ_LB_PHY_REMOTE 0x02
1744#define I40E_AQ_LB_MAC_LOCAL 0x04
1745 u8 reserved[14];
1746};
1747
1748I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1749
1750/* Set PHY Reset command (0x0622) */
1751struct i40e_aqc_set_phy_reset {
1752 u8 reset_flags;
1753#define I40E_AQ_PHY_RESET_REQUEST 0x02
1754 u8 reserved[15];
1755};
1756
1757I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset);
1758
1759enum i40e_aq_phy_reg_type {
1760 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1761 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1762 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1763};
1764
1765/* NVM Read command (indirect 0x0701)
1766 * NVM Erase commands (direct 0x0702)
1767 * NVM Update commands (indirect 0x0703)
1768 */
1769struct i40e_aqc_nvm_update {
1770 u8 command_flags;
1771#define I40E_AQ_NVM_LAST_CMD 0x01
1772#define I40E_AQ_NVM_FLASH_ONLY 0x80
1773 u8 module_pointer;
1774 __le16 length;
1775 __le32 offset;
1776 __le32 addr_high;
1777 __le32 addr_low;
1778};
1779
1780I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1781
1782/* Send to PF command (indirect 0x0801) id is only used by PF
1783 * Send to VF command (indirect 0x0802) id is only used by PF
1784 * Send to Peer PF command (indirect 0x0803)
1785 */
1786struct i40e_aqc_pf_vf_message {
1787 __le32 id;
1788 u8 reserved[4];
1789 __le32 addr_high;
1790 __le32 addr_low;
1791};
1792
1793I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1794
1795/* Alternate structure */
1796
1797/* Direct write (direct 0x0900)
1798 * Direct read (direct 0x0902)
1799 */
1800struct i40e_aqc_alternate_write {
1801 __le32 address0;
1802 __le32 data0;
1803 __le32 address1;
1804 __le32 data1;
1805};
1806
1807I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1808
1809/* Indirect write (indirect 0x0901)
1810 * Indirect read (indirect 0x0903)
1811 */
1812
1813struct i40e_aqc_alternate_ind_write {
1814 __le32 address;
1815 __le32 length;
1816 __le32 addr_high;
1817 __le32 addr_low;
1818};
1819
1820I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1821
1822/* Done alternate write (direct 0x0904)
1823 * uses i40e_aq_desc
1824 */
1825struct i40e_aqc_alternate_write_done {
1826 __le16 cmd_flags;
1827#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1828#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1829#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1830#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1831 u8 reserved[14];
1832};
1833
1834I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1835
1836/* Set OEM mode (direct 0x0905) */
1837struct i40e_aqc_alternate_set_mode {
1838 __le32 mode;
1839#define I40E_AQ_ALTERNATE_MODE_NONE 0
1840#define I40E_AQ_ALTERNATE_MODE_OEM 1
1841 u8 reserved[12];
1842};
1843
1844I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1845
1846/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1847
1848/* async events 0x10xx */
1849
1850/* Lan Queue Overflow Event (direct, 0x1001) */
1851struct i40e_aqc_lan_overflow {
1852 __le32 prtdcb_rupto;
1853 __le32 otx_ctl;
1854 u8 reserved[8];
1855};
1856
1857I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1858
1859/* Get LLDP MIB (indirect 0x0A00) */
1860struct i40e_aqc_lldp_get_mib {
1861 u8 type;
1862 u8 reserved1;
1863#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1864#define I40E_AQ_LLDP_MIB_LOCAL 0x0
1865#define I40E_AQ_LLDP_MIB_REMOTE 0x1
1866#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1867#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1868#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1869#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1870#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1871#define I40E_AQ_LLDP_TX_SHIFT 0x4
1872#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1873/* TX pause flags use I40E_AQ_LINK_TX_* above */
1874 __le16 local_len;
1875 __le16 remote_len;
1876 u8 reserved2[2];
1877 __le32 addr_high;
1878 __le32 addr_low;
1879};
1880
1881I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1882
1883/* Configure LLDP MIB Change Event (direct 0x0A01)
1884 * also used for the event (with type in the command field)
1885 */
1886struct i40e_aqc_lldp_update_mib {
1887 u8 command;
1888#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1889#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1890 u8 reserved[7];
1891 __le32 addr_high;
1892 __le32 addr_low;
1893};
1894
1895I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1896
1897/* Add LLDP TLV (indirect 0x0A02)
1898 * Delete LLDP TLV (indirect 0x0A04)
1899 */
1900struct i40e_aqc_lldp_add_tlv {
1901 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1902 u8 reserved1[1];
1903 __le16 len;
1904 u8 reserved2[4];
1905 __le32 addr_high;
1906 __le32 addr_low;
1907};
1908
1909I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1910
1911/* Update LLDP TLV (indirect 0x0A03) */
1912struct i40e_aqc_lldp_update_tlv {
1913 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1914 u8 reserved;
1915 __le16 old_len;
1916 __le16 new_offset;
1917 __le16 new_len;
1918 __le32 addr_high;
1919 __le32 addr_low;
1920};
1921
1922I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1923
1924/* Stop LLDP (direct 0x0A05) */
1925struct i40e_aqc_lldp_stop {
1926 u8 command;
1927#define I40E_AQ_LLDP_AGENT_STOP 0x0
1928#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1929 u8 reserved[15];
1930};
1931
1932I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1933
1934/* Start LLDP (direct 0x0A06) */
1935
1936struct i40e_aqc_lldp_start {
1937 u8 command;
1938#define I40E_AQ_LLDP_AGENT_START 0x1
1939 u8 reserved[15];
1940};
1941
1942I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1943
1944/* Apply MIB changes (0x0A07)
1945 * uses the generic struc as it contains no data
1946 */
1947
1948/* Add Udp Tunnel command and completion (direct 0x0B00) */
1949struct i40e_aqc_add_udp_tunnel {
1950 __le16 udp_port;
0aebd2d9 1951 u8 reserved0[3];
981b7545 1952 u8 protocol_type;
0aebd2d9
SN		 1953#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
1954#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
1955#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
1956 u8 reserved1[10];
56a62fc8
JB		 1957};
1958
1959I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
1960
981b7545
SN		 1961struct i40e_aqc_add_udp_tunnel_completion {
1962 __le16 udp_port;
1963 u8 filter_entry_index;
1964 u8 multiple_pfs;
1965#define I40E_AQC_SINGLE_PF 0x0
1966#define I40E_AQC_MULTIPLE_PFS 0x1
1967 u8 total_filters;
1968 u8 reserved[11];
1969};
1970
1971I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
1972
56a62fc8
JB		 1973/* remove UDP Tunnel command (0x0B01) */
1974struct i40e_aqc_remove_udp_tunnel {
1975 u8 reserved[2];
1976 u8 index; /* 0 to 15 */
981b7545 1977 u8 reserved2[13];
56a62fc8
JB		 1978};
1979
1980I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
1981
1982struct i40e_aqc_del_udp_tunnel_completion {
1983 __le16 udp_port;
1984 u8 index; /* 0 to 15 */
981b7545
SN		 1985 u8 multiple_pfs;
1986 u8 total_filters_used;
1987 u8 reserved1[11];
56a62fc8
JB		 1988};
1989
1990I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
1991
1992/* tunnel key structure 0x0B10 */
981b7545 1993
56a62fc8 1994struct i40e_aqc_tunnel_key_structure {
981b7545
SN		 1995 u8 key1_off;
1996 u8 key2_off;
1997 u8 key1_len; /* 0 to 15 */
1998 u8 key2_len; /* 0 to 15 */
1999 u8 flags;
56a62fc8
JB		 2000#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2001/* response flags */
2002#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2003#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2004#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
981b7545
SN		 2005 u8 network_key_index;
2006#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2007#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2008#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2009#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2010 u8 reserved[10];
56a62fc8
JB		 2011};
2012
2013I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2014
2015/* OEM mode commands (direct 0xFE0x) */
2016struct i40e_aqc_oem_param_change {
2017 __le32 param_type;
2018#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2019#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2020#define I40E_AQ_OEM_PARAM_MAC 2
2021 __le32 param_value1;
2022 u8 param_value2[8];
2023};
2024
2025I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2026
2027struct i40e_aqc_oem_state_change {
2028 __le32 state;
2029#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2030#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2031 u8 reserved[12];
2032};
2033
2034I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2035
2036/* debug commands */
2037
2038/* get device id (0xFF00) uses the generic structure */
2039
2040/* set test more (0xFF01, internal) */
2041
2042struct i40e_acq_set_test_mode {
2043 u8 mode;
2044#define I40E_AQ_TEST_PARTIAL 0
2045#define I40E_AQ_TEST_FULL 1
2046#define I40E_AQ_TEST_NVM 2
2047 u8 reserved[3];
2048 u8 command;
2049#define I40E_AQ_TEST_OPEN 0
2050#define I40E_AQ_TEST_CLOSE 1
2051#define I40E_AQ_TEST_INC 2
2052 u8 reserved2[3];
2053 __le32 address_high;
2054 __le32 address_low;
2055};
2056
2057I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2058
2059/* Debug Read Register command (0xFF03)
2060 * Debug Write Register command (0xFF04)
2061 */
2062struct i40e_aqc_debug_reg_read_write {
2063 __le32 reserved;
2064 __le32 address;
2065 __le32 value_high;
2066 __le32 value_low;
2067};
2068
2069I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2070
2071/* Scatter/gather Reg Read (indirect 0xFF05)
2072 * Scatter/gather Reg Write (indirect 0xFF06)
2073 */
2074
2075/* i40e_aq_desc is used for the command */
2076struct i40e_aqc_debug_reg_sg_element_data {
2077 __le32 address;
2078 __le32 value;
2079};
2080
2081/* Debug Modify register (direct 0xFF07) */
2082struct i40e_aqc_debug_modify_reg {
2083 __le32 address;
2084 __le32 value;
2085 __le32 clear_mask;
2086 __le32 set_mask;
2087};
2088
2089I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2090
2091/* dump internal data (0xFF08, indirect) */
2092
2093#define I40E_AQ_CLUSTER_ID_AUX 0
2094#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2095#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2096#define I40E_AQ_CLUSTER_ID_HMC 3
2097#define I40E_AQ_CLUSTER_ID_MAC0 4
2098#define I40E_AQ_CLUSTER_ID_MAC1 5
2099#define I40E_AQ_CLUSTER_ID_MAC2 6
2100#define I40E_AQ_CLUSTER_ID_MAC3 7
2101#define I40E_AQ_CLUSTER_ID_DCB 8
2102#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2103#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
981b7545 2104#define I40E_AQ_CLUSTER_ID_ALTRAM 11
56a62fc8
JB		 2105
2106struct i40e_aqc_debug_dump_internals {
2107 u8 cluster_id;
2108 u8 table_id;
2109 __le16 data_size;
2110 __le32 idx;
2111 __le32 address_high;
2112 __le32 address_low;
2113};
2114
2115I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2116
2117struct i40e_aqc_debug_modify_internals {
2118 u8 cluster_id;
2119 u8 cluster_specific_params[7];
2120 __le32 address_high;
2121 __le32 address_low;
2122};
2123
2124I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2125
2126#endif
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