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i40e/i40evf: Remove unused variable an_enable and function update_link_info
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e
SN		 46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
ab60085e
SN		 50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
5960d33f 53 case I40E_DEV_ID_10G_BASE_T:
56a62fc8
JB		 54 hw->mac.type = I40E_MAC_XL710;
55 break;
ab60085e
SN		 56 case I40E_DEV_ID_VF:
57 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 58 hw->mac.type = I40E_MAC_VF;
59 break;
60 default:
61 hw->mac.type = I40E_MAC_GENERIC;
62 break;
63 }
64 } else {
65 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
66 }
67
68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
69 hw->mac.type, status);
70 return status;
71}
72
73/**
74 * i40e_debug_aq
75 * @hw: debug mask related to admin queue
98d44381
JK		 76 * @mask: debug mask
77 * @desc: pointer to admin queue descriptor
56a62fc8 78 * @buffer: pointer to command buffer
f905dd62 79 * @buf_len: max length of buffer
56a62fc8
JB		 80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 84 void *buffer, u16 buf_len)
56a62fc8
JB		 85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
f905dd62 87 u16 len = le16_to_cpu(aq_desc->datalen);
56a62fc8
JB		 88 u8 *aq_buffer = (u8 *)buffer;
89 u32 data[4];
90 u32 i = 0;
91
92 if ((!(mask & hw->debug_mask)) || (desc == NULL))
93 return;
94
95 i40e_debug(hw, mask,
96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
97 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
98 aq_desc->retval);
99 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
100 aq_desc->cookie_high, aq_desc->cookie_low);
101 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
102 aq_desc->params.internal.param0,
103 aq_desc->params.internal.param1);
104 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
105 aq_desc->params.external.addr_high,
106 aq_desc->params.external.addr_low);
107
108 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
109 memset(data, 0, sizeof(data));
110 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 111 if (buf_len < len)
112 len = buf_len;
113 for (i = 0; i < len; i++) {
56a62fc8
JB		 114 data[((i % 16) / 4)] |=
115 ((u32)aq_buffer[i]) << (8 * (i % 4));
116 if ((i % 16) == 15) {
117 i40e_debug(hw, mask,
118 "\t0x%04X %08X %08X %08X %08X\n",
119 i - 15, data[0], data[1], data[2],
120 data[3]);
121 memset(data, 0, sizeof(data));
122 }
123 }
124 if ((i % 16) != 0)
125 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
126 i - (i % 16), data[0], data[1], data[2],
127 data[3]);
128 }
129}
130
e1860d8f
ASJ		 131/**
132 * i40e_check_asq_alive
133 * @hw: pointer to the hw struct
134 *
135 * Returns true if Queue is enabled else false.
136 **/
137bool i40e_check_asq_alive(struct i40e_hw *hw)
138{
8b833b4f
KS		 139 if (hw->aq.asq.len)
140 return !!(rd32(hw, hw->aq.asq.len) &
141 I40E_PF_ATQLEN_ATQENABLE_MASK);
142 else
143 return false;
e1860d8f
ASJ		 144}
145
146/**
147 * i40e_aq_queue_shutdown
148 * @hw: pointer to the hw struct
149 * @unloading: is the driver unloading itself
150 *
151 * Tell the Firmware that we're shutting down the AdminQ and whether
152 * or not the driver is unloading as well.
153 **/
154i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
155 bool unloading)
156{
157 struct i40e_aq_desc desc;
158 struct i40e_aqc_queue_shutdown *cmd =
159 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
160 i40e_status status;
161
162 i40e_fill_default_direct_cmd_desc(&desc,
163 i40e_aqc_opc_queue_shutdown);
164
165 if (unloading)
166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
168
169 return status;
170}
171
206812b5
JB		 172/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
173 * hardware to a bit-field that can be used by SW to more easily determine the
174 * packet type.
175 *
176 * Macros are used to shorten the table lines and make this table human
177 * readable.
178 *
179 * We store the PTYPE in the top byte of the bit field - this is just so that
180 * we can check that the table doesn't have a row missing, as the index into
181 * the table should be the PTYPE.
182 *
183 * Typical work flow:
184 *
185 * IF NOT i40e_ptype_lookup[ptype].known
186 * THEN
187 * Packet is unknown
188 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
189 * Use the rest of the fields to look at the tunnels, inner protocols, etc
190 * ELSE
191 * Use the enum i40e_rx_l2_ptype to decode the packet type
192 * ENDIF
193 */
194
195/* macro to make the table lines short */
196#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
197 { PTYPE, \
198 1, \
199 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
200 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
201 I40E_RX_PTYPE_##OUTER_FRAG, \
202 I40E_RX_PTYPE_TUNNEL_##T, \
203 I40E_RX_PTYPE_TUNNEL_END_##TE, \
204 I40E_RX_PTYPE_##TEF, \
205 I40E_RX_PTYPE_INNER_PROT_##I, \
206 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
207
208#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
209 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
210
211/* shorter macros makes the table fit but are terse */
212#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
213#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
214#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
215
216/* Lookup table mapping the HW PTYPE to the bit field for decoding */
217struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
218 /* L2 Packet types */
219 I40E_PTT_UNUSED_ENTRY(0),
220 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
222 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT_UNUSED_ENTRY(4),
224 I40E_PTT_UNUSED_ENTRY(5),
225 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
226 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
227 I40E_PTT_UNUSED_ENTRY(8),
228 I40E_PTT_UNUSED_ENTRY(9),
229 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
231 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241
242 /* Non Tunneled IPv4 */
243 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
246 I40E_PTT_UNUSED_ENTRY(25),
247 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
248 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
249 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
250
251 /* IPv4 --> IPv4 */
252 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
253 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
254 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
255 I40E_PTT_UNUSED_ENTRY(32),
256 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
257 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
258 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
259
260 /* IPv4 --> IPv6 */
261 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
262 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
263 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
264 I40E_PTT_UNUSED_ENTRY(39),
265 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
266 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
267 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
268
269 /* IPv4 --> GRE/NAT */
270 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
271
272 /* IPv4 --> GRE/NAT --> IPv4 */
273 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
274 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
275 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
276 I40E_PTT_UNUSED_ENTRY(47),
277 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
278 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
279 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
280
281 /* IPv4 --> GRE/NAT --> IPv6 */
282 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
283 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
284 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
285 I40E_PTT_UNUSED_ENTRY(54),
286 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
287 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
288 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
289
290 /* IPv4 --> GRE/NAT --> MAC */
291 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
292
293 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
294 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
295 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
296 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
297 I40E_PTT_UNUSED_ENTRY(62),
298 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
299 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
300 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
301
302 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
303 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
304 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
305 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
306 I40E_PTT_UNUSED_ENTRY(69),
307 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
308 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
309 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
310
311 /* IPv4 --> GRE/NAT --> MAC/VLAN */
312 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
313
314 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
315 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
316 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
317 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
318 I40E_PTT_UNUSED_ENTRY(77),
319 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
320 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
321 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
322
323 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
324 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
325 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
326 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
327 I40E_PTT_UNUSED_ENTRY(84),
328 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
329 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
330 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
331
332 /* Non Tunneled IPv6 */
333 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
334 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
335 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
336 I40E_PTT_UNUSED_ENTRY(91),
337 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
338 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
339 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
340
341 /* IPv6 --> IPv4 */
342 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
343 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
344 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
345 I40E_PTT_UNUSED_ENTRY(98),
346 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
347 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
348 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
349
350 /* IPv6 --> IPv6 */
351 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
352 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
353 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
354 I40E_PTT_UNUSED_ENTRY(105),
355 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
356 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
357 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
358
359 /* IPv6 --> GRE/NAT */
360 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
361
362 /* IPv6 --> GRE/NAT -> IPv4 */
363 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
364 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
365 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
366 I40E_PTT_UNUSED_ENTRY(113),
367 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
368 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
369 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
370
371 /* IPv6 --> GRE/NAT -> IPv6 */
372 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
373 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
374 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
375 I40E_PTT_UNUSED_ENTRY(120),
376 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
377 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
378 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
379
380 /* IPv6 --> GRE/NAT -> MAC */
381 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
382
383 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
384 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
385 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
386 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
387 I40E_PTT_UNUSED_ENTRY(128),
388 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
389 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
390 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
391
392 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
393 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
394 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
395 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
396 I40E_PTT_UNUSED_ENTRY(135),
397 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
398 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
399 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
400
401 /* IPv6 --> GRE/NAT -> MAC/VLAN */
402 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
403
404 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
405 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
406 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
407 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
408 I40E_PTT_UNUSED_ENTRY(143),
409 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
410 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
411 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
412
413 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
414 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
415 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
416 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
417 I40E_PTT_UNUSED_ENTRY(150),
418 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
419 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
420 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
421
422 /* unused entries */
423 I40E_PTT_UNUSED_ENTRY(154),
424 I40E_PTT_UNUSED_ENTRY(155),
425 I40E_PTT_UNUSED_ENTRY(156),
426 I40E_PTT_UNUSED_ENTRY(157),
427 I40E_PTT_UNUSED_ENTRY(158),
428 I40E_PTT_UNUSED_ENTRY(159),
429
430 I40E_PTT_UNUSED_ENTRY(160),
431 I40E_PTT_UNUSED_ENTRY(161),
432 I40E_PTT_UNUSED_ENTRY(162),
433 I40E_PTT_UNUSED_ENTRY(163),
434 I40E_PTT_UNUSED_ENTRY(164),
435 I40E_PTT_UNUSED_ENTRY(165),
436 I40E_PTT_UNUSED_ENTRY(166),
437 I40E_PTT_UNUSED_ENTRY(167),
438 I40E_PTT_UNUSED_ENTRY(168),
439 I40E_PTT_UNUSED_ENTRY(169),
440
441 I40E_PTT_UNUSED_ENTRY(170),
442 I40E_PTT_UNUSED_ENTRY(171),
443 I40E_PTT_UNUSED_ENTRY(172),
444 I40E_PTT_UNUSED_ENTRY(173),
445 I40E_PTT_UNUSED_ENTRY(174),
446 I40E_PTT_UNUSED_ENTRY(175),
447 I40E_PTT_UNUSED_ENTRY(176),
448 I40E_PTT_UNUSED_ENTRY(177),
449 I40E_PTT_UNUSED_ENTRY(178),
450 I40E_PTT_UNUSED_ENTRY(179),
451
452 I40E_PTT_UNUSED_ENTRY(180),
453 I40E_PTT_UNUSED_ENTRY(181),
454 I40E_PTT_UNUSED_ENTRY(182),
455 I40E_PTT_UNUSED_ENTRY(183),
456 I40E_PTT_UNUSED_ENTRY(184),
457 I40E_PTT_UNUSED_ENTRY(185),
458 I40E_PTT_UNUSED_ENTRY(186),
459 I40E_PTT_UNUSED_ENTRY(187),
460 I40E_PTT_UNUSED_ENTRY(188),
461 I40E_PTT_UNUSED_ENTRY(189),
462
463 I40E_PTT_UNUSED_ENTRY(190),
464 I40E_PTT_UNUSED_ENTRY(191),
465 I40E_PTT_UNUSED_ENTRY(192),
466 I40E_PTT_UNUSED_ENTRY(193),
467 I40E_PTT_UNUSED_ENTRY(194),
468 I40E_PTT_UNUSED_ENTRY(195),
469 I40E_PTT_UNUSED_ENTRY(196),
470 I40E_PTT_UNUSED_ENTRY(197),
471 I40E_PTT_UNUSED_ENTRY(198),
472 I40E_PTT_UNUSED_ENTRY(199),
473
474 I40E_PTT_UNUSED_ENTRY(200),
475 I40E_PTT_UNUSED_ENTRY(201),
476 I40E_PTT_UNUSED_ENTRY(202),
477 I40E_PTT_UNUSED_ENTRY(203),
478 I40E_PTT_UNUSED_ENTRY(204),
479 I40E_PTT_UNUSED_ENTRY(205),
480 I40E_PTT_UNUSED_ENTRY(206),
481 I40E_PTT_UNUSED_ENTRY(207),
482 I40E_PTT_UNUSED_ENTRY(208),
483 I40E_PTT_UNUSED_ENTRY(209),
484
485 I40E_PTT_UNUSED_ENTRY(210),
486 I40E_PTT_UNUSED_ENTRY(211),
487 I40E_PTT_UNUSED_ENTRY(212),
488 I40E_PTT_UNUSED_ENTRY(213),
489 I40E_PTT_UNUSED_ENTRY(214),
490 I40E_PTT_UNUSED_ENTRY(215),
491 I40E_PTT_UNUSED_ENTRY(216),
492 I40E_PTT_UNUSED_ENTRY(217),
493 I40E_PTT_UNUSED_ENTRY(218),
494 I40E_PTT_UNUSED_ENTRY(219),
495
496 I40E_PTT_UNUSED_ENTRY(220),
497 I40E_PTT_UNUSED_ENTRY(221),
498 I40E_PTT_UNUSED_ENTRY(222),
499 I40E_PTT_UNUSED_ENTRY(223),
500 I40E_PTT_UNUSED_ENTRY(224),
501 I40E_PTT_UNUSED_ENTRY(225),
502 I40E_PTT_UNUSED_ENTRY(226),
503 I40E_PTT_UNUSED_ENTRY(227),
504 I40E_PTT_UNUSED_ENTRY(228),
505 I40E_PTT_UNUSED_ENTRY(229),
506
507 I40E_PTT_UNUSED_ENTRY(230),
508 I40E_PTT_UNUSED_ENTRY(231),
509 I40E_PTT_UNUSED_ENTRY(232),
510 I40E_PTT_UNUSED_ENTRY(233),
511 I40E_PTT_UNUSED_ENTRY(234),
512 I40E_PTT_UNUSED_ENTRY(235),
513 I40E_PTT_UNUSED_ENTRY(236),
514 I40E_PTT_UNUSED_ENTRY(237),
515 I40E_PTT_UNUSED_ENTRY(238),
516 I40E_PTT_UNUSED_ENTRY(239),
517
518 I40E_PTT_UNUSED_ENTRY(240),
519 I40E_PTT_UNUSED_ENTRY(241),
520 I40E_PTT_UNUSED_ENTRY(242),
521 I40E_PTT_UNUSED_ENTRY(243),
522 I40E_PTT_UNUSED_ENTRY(244),
523 I40E_PTT_UNUSED_ENTRY(245),
524 I40E_PTT_UNUSED_ENTRY(246),
525 I40E_PTT_UNUSED_ENTRY(247),
526 I40E_PTT_UNUSED_ENTRY(248),
527 I40E_PTT_UNUSED_ENTRY(249),
528
529 I40E_PTT_UNUSED_ENTRY(250),
530 I40E_PTT_UNUSED_ENTRY(251),
531 I40E_PTT_UNUSED_ENTRY(252),
532 I40E_PTT_UNUSED_ENTRY(253),
533 I40E_PTT_UNUSED_ENTRY(254),
534 I40E_PTT_UNUSED_ENTRY(255)
535};
536
537
56a62fc8
JB		 538/**
539 * i40e_init_shared_code - Initialize the shared code
540 * @hw: pointer to hardware structure
541 *
542 * This assigns the MAC type and PHY code and inits the NVM.
543 * Does not touch the hardware. This function must be called prior to any
544 * other function in the shared code. The i40e_hw structure should be
545 * memset to 0 prior to calling this function. The following fields in
546 * hw structure should be filled in prior to calling this function:
547 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
548 * subsystem_vendor_id, and revision_id
549 **/
550i40e_status i40e_init_shared_code(struct i40e_hw *hw)
551{
552 i40e_status status = 0;
5fb11d76 553 u32 port, ari, func_rid;
56a62fc8 554
56a62fc8
JB		 555 i40e_set_mac_type(hw);
556
557 switch (hw->mac.type) {
558 case I40E_MAC_XL710:
559 break;
560 default:
561 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 562 }
563
af89d26c
SN		 564 hw->phy.get_link_info = true;
565
5fb11d76
SN		 566 /* Determine port number and PF number*/
567 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
568 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
569 hw->port = (u8)port;
570 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
571 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
572 func_rid = rd32(hw, I40E_PF_FUNC_RID);
573 if (ari)
574 hw->pf_id = (u8)(func_rid & 0xff);
5f9116ac 575 else
5fb11d76 576 hw->pf_id = (u8)(func_rid & 0x7);
5f9116ac 577
56a62fc8
JB		 578 status = i40e_init_nvm(hw);
579 return status;
580}
581
582/**
583 * i40e_aq_mac_address_read - Retrieve the MAC addresses
584 * @hw: pointer to the hw struct
585 * @flags: a return indicator of what addresses were added to the addr store
586 * @addrs: the requestor's mac addr store
587 * @cmd_details: pointer to command details structure or NULL
588 **/
589static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
590 u16 *flags,
591 struct i40e_aqc_mac_address_read_data *addrs,
592 struct i40e_asq_cmd_details *cmd_details)
593{
594 struct i40e_aq_desc desc;
595 struct i40e_aqc_mac_address_read *cmd_data =
596 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
597 i40e_status status;
598
599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
600 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
601
602 status = i40e_asq_send_command(hw, &desc, addrs,
603 sizeof(*addrs), cmd_details);
604 *flags = le16_to_cpu(cmd_data->command_flags);
605
606 return status;
607}
608
609/**
610 * i40e_aq_mac_address_write - Change the MAC addresses
611 * @hw: pointer to the hw struct
612 * @flags: indicates which MAC to be written
613 * @mac_addr: address to write
614 * @cmd_details: pointer to command details structure or NULL
615 **/
616i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
617 u16 flags, u8 *mac_addr,
618 struct i40e_asq_cmd_details *cmd_details)
619{
620 struct i40e_aq_desc desc;
621 struct i40e_aqc_mac_address_write *cmd_data =
622 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
623 i40e_status status;
624
625 i40e_fill_default_direct_cmd_desc(&desc,
626 i40e_aqc_opc_mac_address_write);
627 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 628 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
629 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
630 ((u32)mac_addr[3] << 16) |
631 ((u32)mac_addr[4] << 8) |
632 mac_addr[5]);
56a62fc8
JB		 633
634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
635
636 return status;
637}
638
639/**
640 * i40e_get_mac_addr - get MAC address
641 * @hw: pointer to the HW structure
642 * @mac_addr: pointer to MAC address
643 *
644 * Reads the adapter's MAC address from register
645 **/
646i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
647{
648 struct i40e_aqc_mac_address_read_data addrs;
649 i40e_status status;
650 u16 flags = 0;
651
652 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
653
654 if (flags & I40E_AQC_LAN_ADDR_VALID)
655 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
656
657 return status;
658}
659
1f224ad2
NP		 660/**
661 * i40e_get_port_mac_addr - get Port MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to Port MAC address
664 *
665 * Reads the adapter's Port MAC address
666 **/
667i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
668{
669 struct i40e_aqc_mac_address_read_data addrs;
670 i40e_status status;
671 u16 flags = 0;
672
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
674 if (status)
675 return status;
676
677 if (flags & I40E_AQC_PORT_ADDR_VALID)
678 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
679 else
680 status = I40E_ERR_INVALID_MAC_ADDR;
681
682 return status;
683}
684
351499ab
MJ		 685/**
686 * i40e_pre_tx_queue_cfg - pre tx queue configure
687 * @hw: pointer to the HW structure
688 * @queue: target pf queue index
689 * @enable: state change request
690 *
691 * Handles hw requirement to indicate intention to enable
692 * or disable target queue.
693 **/
694void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
695{
dfb699f9 696 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 697 u32 reg_block = 0;
dfb699f9 698 u32 reg_val;
351499ab 699
24a768cf 700 if (abs_queue_idx >= 128) {
351499ab 701 reg_block = abs_queue_idx / 128;
24a768cf
CP		 702 abs_queue_idx %= 128;
703 }
351499ab
MJ		 704
705 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
706 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
707 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
708
709 if (enable)
710 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
711 else
712 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
713
714 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
715}
38e00438
VD		 716#ifdef I40E_FCOE
717
718/**
719 * i40e_get_san_mac_addr - get SAN MAC address
720 * @hw: pointer to the HW structure
721 * @mac_addr: pointer to SAN MAC address
722 *
723 * Reads the adapter's SAN MAC address from NVM
724 **/
725i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
726{
727 struct i40e_aqc_mac_address_read_data addrs;
728 i40e_status status;
729 u16 flags = 0;
730
731 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
732 if (status)
733 return status;
734
735 if (flags & I40E_AQC_SAN_ADDR_VALID)
736 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
737 else
738 status = I40E_ERR_INVALID_MAC_ADDR;
739
740 return status;
741}
742#endif
351499ab 743
18f680c6
KK		 744/**
745 * i40e_read_pba_string - Reads part number string from EEPROM
746 * @hw: pointer to hardware structure
747 * @pba_num: stores the part number string from the EEPROM
748 * @pba_num_size: part number string buffer length
749 *
750 * Reads the part number string from the EEPROM.
751 **/
752i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
753 u32 pba_num_size)
754{
755 i40e_status status = 0;
756 u16 pba_word = 0;
757 u16 pba_size = 0;
758 u16 pba_ptr = 0;
759 u16 i = 0;
760
761 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
762 if (status || (pba_word != 0xFAFA)) {
763 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
764 return status;
765 }
766
767 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
768 if (status) {
769 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
770 return status;
771 }
772
773 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
774 if (status) {
775 hw_dbg(hw, "Failed to read PBA Block size.\n");
776 return status;
777 }
778
779 /* Subtract one to get PBA word count (PBA Size word is included in
780 * total size)
781 */
782 pba_size--;
783 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
784 hw_dbg(hw, "Buffer to small for PBA data.\n");
785 return I40E_ERR_PARAM;
786 }
787
788 for (i = 0; i < pba_size; i++) {
789 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
790 if (status) {
791 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
792 return status;
793 }
794
795 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
796 pba_num[(i * 2) + 1] = pba_word & 0xFF;
797 }
798 pba_num[(pba_size * 2)] = '\0';
799
800 return status;
801}
802
be405eb0
JB		 803/**
804 * i40e_get_media_type - Gets media type
805 * @hw: pointer to the hardware structure
806 **/
807static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
808{
809 enum i40e_media_type media;
810
811 switch (hw->phy.link_info.phy_type) {
812 case I40E_PHY_TYPE_10GBASE_SR:
813 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 814 case I40E_PHY_TYPE_1000BASE_SX:
815 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 816 case I40E_PHY_TYPE_40GBASE_SR4:
817 case I40E_PHY_TYPE_40GBASE_LR4:
818 media = I40E_MEDIA_TYPE_FIBER;
819 break;
820 case I40E_PHY_TYPE_100BASE_TX:
821 case I40E_PHY_TYPE_1000BASE_T:
822 case I40E_PHY_TYPE_10GBASE_T:
823 media = I40E_MEDIA_TYPE_BASET;
824 break;
825 case I40E_PHY_TYPE_10GBASE_CR1_CU:
826 case I40E_PHY_TYPE_40GBASE_CR4_CU:
827 case I40E_PHY_TYPE_10GBASE_CR1:
828 case I40E_PHY_TYPE_40GBASE_CR4:
829 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
830 media = I40E_MEDIA_TYPE_DA;
831 break;
832 case I40E_PHY_TYPE_1000BASE_KX:
833 case I40E_PHY_TYPE_10GBASE_KX4:
834 case I40E_PHY_TYPE_10GBASE_KR:
835 case I40E_PHY_TYPE_40GBASE_KR4:
836 media = I40E_MEDIA_TYPE_BACKPLANE;
837 break;
838 case I40E_PHY_TYPE_SGMII:
839 case I40E_PHY_TYPE_XAUI:
840 case I40E_PHY_TYPE_XFI:
841 case I40E_PHY_TYPE_XLAUI:
842 case I40E_PHY_TYPE_XLPPI:
843 default:
844 media = I40E_MEDIA_TYPE_UNKNOWN;
845 break;
846 }
847
848 return media;
849}
850
7134f9ce 851#define I40E_PF_RESET_WAIT_COUNT_A0 200
b9a81b2b 852#define I40E_PF_RESET_WAIT_COUNT 110
56a62fc8
JB		 853/**
854 * i40e_pf_reset - Reset the PF
855 * @hw: pointer to the hardware structure
856 *
857 * Assuming someone else has triggered a global reset,
858 * assure the global reset is complete and then reset the PF
859 **/
860i40e_status i40e_pf_reset(struct i40e_hw *hw)
861{
7134f9ce 862 u32 cnt = 0;
42794bd8 863 u32 cnt1 = 0;
56a62fc8
JB		 864 u32 reg = 0;
865 u32 grst_del;
866
867 /* Poll for Global Reset steady state in case of recent GRST.
868 * The grst delay value is in 100ms units, and we'll wait a
869 * couple counts longer to be sure we don't just miss the end.
870 */
871 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
872 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 873 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 874 reg = rd32(hw, I40E_GLGEN_RSTAT);
875 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
876 break;
877 msleep(100);
878 }
879 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
880 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 881 return I40E_ERR_RESET_FAILED;
882 }
883
884 /* Now Wait for the FW to be ready */
885 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
886 reg = rd32(hw, I40E_GLNVM_ULD);
887 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
888 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
889 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
890 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
891 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
892 break;
893 }
894 usleep_range(10000, 20000);
895 }
896 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
897 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
898 hw_dbg(hw, "wait for FW Reset complete timedout\n");
899 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 900 return I40E_ERR_RESET_FAILED;
901 }
902
56a62fc8
JB		 903 /* If there was a Global Reset in progress when we got here,
904 * we don't need to do the PF Reset
905 */
7134f9ce
JB		 906 if (!cnt) {
907 if (hw->revision_id == 0)
908 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
909 else
910 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 911 reg = rd32(hw, I40E_PFGEN_CTRL);
912 wr32(hw, I40E_PFGEN_CTRL,
913 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 914 for (; cnt; cnt--) {
56a62fc8
JB		 915 reg = rd32(hw, I40E_PFGEN_CTRL);
916 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
917 break;
918 usleep_range(1000, 2000);
919 }
920 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
921 hw_dbg(hw, "PF reset polling failed to complete.\n");
922 return I40E_ERR_RESET_FAILED;
923 }
924 }
925
926 i40e_clear_pxe_mode(hw);
922680b9 927
56a62fc8
JB		 928 return 0;
929}
930
838d41d9
SN		 931/**
932 * i40e_clear_hw - clear out any left over hw state
933 * @hw: pointer to the hw struct
934 *
935 * Clear queues and interrupts, typically called at init time,
936 * but after the capabilities have been found so we know how many
937 * queues and msix vectors have been allocated.
938 **/
939void i40e_clear_hw(struct i40e_hw *hw)
940{
941 u32 num_queues, base_queue;
942 u32 num_pf_int;
943 u32 num_vf_int;
944 u32 num_vfs;
945 u32 i, j;
946 u32 val;
947 u32 eol = 0x7ff;
948
949 /* get number of interrupts, queues, and vfs */
950 val = rd32(hw, I40E_GLPCI_CNF2);
951 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
952 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
953 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
954 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
955
956 val = rd32(hw, I40E_PFLAN_QALLOC);
957 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
958 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
959 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
960 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
961 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
962 num_queues = (j - base_queue) + 1;
963 else
964 num_queues = 0;
965
966 val = rd32(hw, I40E_PF_VT_PFALLOC);
967 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
968 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
969 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
970 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
971 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
972 num_vfs = (j - i) + 1;
973 else
974 num_vfs = 0;
975
976 /* stop all the interrupts */
977 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
978 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
979 for (i = 0; i < num_pf_int - 2; i++)
980 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
981
982 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
983 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
984 wr32(hw, I40E_PFINT_LNKLST0, val);
985 for (i = 0; i < num_pf_int - 2; i++)
986 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
987 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
988 for (i = 0; i < num_vfs; i++)
989 wr32(hw, I40E_VPINT_LNKLST0(i), val);
990 for (i = 0; i < num_vf_int - 2; i++)
991 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
992
993 /* warn the HW of the coming Tx disables */
994 for (i = 0; i < num_queues; i++) {
995 u32 abs_queue_idx = base_queue + i;
996 u32 reg_block = 0;
997
998 if (abs_queue_idx >= 128) {
999 reg_block = abs_queue_idx / 128;
1000 abs_queue_idx %= 128;
1001 }
1002
1003 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1004 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1005 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1006 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1007
1008 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1009 }
1010 udelay(400);
1011
1012 /* stop all the queues */
1013 for (i = 0; i < num_queues; i++) {
1014 wr32(hw, I40E_QINT_TQCTL(i), 0);
1015 wr32(hw, I40E_QTX_ENA(i), 0);
1016 wr32(hw, I40E_QINT_RQCTL(i), 0);
1017 wr32(hw, I40E_QRX_ENA(i), 0);
1018 }
1019
1020 /* short wait for all queue disables to settle */
1021 udelay(50);
1022}
1023
56a62fc8
JB		 1024/**
1025 * i40e_clear_pxe_mode - clear pxe operations mode
1026 * @hw: pointer to the hw struct
1027 *
1028 * Make sure all PXE mode settings are cleared, including things
1029 * like descriptor fetch/write-back mode.
1030 **/
1031void i40e_clear_pxe_mode(struct i40e_hw *hw)
1032{
1033 u32 reg;
1034
c9b9b0ae
SN		 1035 if (i40e_check_asq_alive(hw))
1036 i40e_aq_clear_pxe_mode(hw, NULL);
1037
56a62fc8
JB		 1038 /* Clear single descriptor fetch/write-back mode */
1039 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 1040
1041 if (hw->revision_id == 0) {
1042 /* As a work around clear PXE_MODE instead of setting it */
1043 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1044 } else {
1045 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1046 }
56a62fc8
JB		 1047}
1048
0556a9e3
JB		 1049/**
1050 * i40e_led_is_mine - helper to find matching led
1051 * @hw: pointer to the hw struct
1052 * @idx: index into GPIO registers
1053 *
1054 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1055 */
1056static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1057{
1058 u32 gpio_val = 0;
1059 u32 port;
1060
1061 if (!hw->func_caps.led[idx])
1062 return 0;
1063
1064 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1065 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1066 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1067
1068 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1069 * if it is not our port then ignore
1070 */
1071 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1072 (port != hw->port))
1073 return 0;
1074
1075 return gpio_val;
1076}
1077
1078#define I40E_LED0 22
1079#define I40E_LINK_ACTIVITY 0xC
1080
56a62fc8
JB		 1081/**
1082 * i40e_led_get - return current on/off mode
1083 * @hw: pointer to the hw struct
1084 *
1085 * The value returned is the 'mode' field as defined in the
1086 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1087 * values are variations of possible behaviors relating to
1088 * blink, link, and wire.
1089 **/
1090u32 i40e_led_get(struct i40e_hw *hw)
1091{
56a62fc8 1092 u32 mode = 0;
56a62fc8
JB		 1093 int i;
1094
0556a9e3
JB		 1095 /* as per the documentation GPIO 22-29 are the LED
1096 * GPIO pins named LED0..LED7
1097 */
1098 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1099 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1100
0556a9e3 1101 if (!gpio_val)
56a62fc8
JB		 1102 continue;
1103
0556a9e3
JB		 1104 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1105 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1106 break;
1107 }
1108
1109 return mode;
1110}
1111
1112/**
1113 * i40e_led_set - set new on/off mode
1114 * @hw: pointer to the hw struct
0556a9e3
JB		 1115 * @mode: 0=off, 0xf=on (else see manual for mode details)
1116 * @blink: true if the LED should blink when on, false if steady
1117 *
1118 * if this function is used to turn on the blink it should
1119 * be used to disable the blink when restoring the original state.
56a62fc8 1120 **/
0556a9e3 1121void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1122{
56a62fc8
JB		 1123 int i;
1124
0556a9e3
JB		 1125 if (mode & 0xfffffff0)
1126 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1127
0556a9e3
JB		 1128 /* as per the documentation GPIO 22-29 are the LED
1129 * GPIO pins named LED0..LED7
1130 */
1131 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1132 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1133
0556a9e3 1134 if (!gpio_val)
56a62fc8
JB		 1135 continue;
1136
56a62fc8 1137 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1138 /* this & is a bit of paranoia, but serves as a range check */
1139 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1140 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1141
1142 if (mode == I40E_LINK_ACTIVITY)
1143 blink = false;
1144
9be00d67
MJ		 1145 if (blink)
1146 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1147 else
1148 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
0556a9e3 1149
56a62fc8 1150 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1151 break;
56a62fc8
JB		 1152 }
1153}
1154
1155/* Admin command wrappers */
56a62fc8 1156
8109e123
CS		 1157/**
1158 * i40e_aq_get_phy_capabilities
1159 * @hw: pointer to the hw struct
1160 * @abilities: structure for PHY capabilities to be filled
1161 * @qualified_modules: report Qualified Modules
1162 * @report_init: report init capabilities (active are default)
1163 * @cmd_details: pointer to command details structure or NULL
1164 *
1165 * Returns the various PHY abilities supported on the Port.
1166 **/
1167i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1168 bool qualified_modules, bool report_init,
1169 struct i40e_aq_get_phy_abilities_resp *abilities,
1170 struct i40e_asq_cmd_details *cmd_details)
1171{
1172 struct i40e_aq_desc desc;
1173 i40e_status status;
1174 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1175
1176 if (!abilities)
1177 return I40E_ERR_PARAM;
1178
1179 i40e_fill_default_direct_cmd_desc(&desc,
1180 i40e_aqc_opc_get_phy_abilities);
1181
1182 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1183 if (abilities_size > I40E_AQ_LARGE_BUF)
1184 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1185
1186 if (qualified_modules)
1187 desc.params.external.param0 |=
1188 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1189
1190 if (report_init)
1191 desc.params.external.param0 |=
1192 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1193
1194 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1195 cmd_details);
1196
1197 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1198 status = I40E_ERR_UNKNOWN_PHY;
1199
1200 return status;
1201}
1202
c56999f9
CS		 1203/**
1204 * i40e_aq_set_phy_config
1205 * @hw: pointer to the hw struct
1206 * @config: structure with PHY configuration to be set
1207 * @cmd_details: pointer to command details structure or NULL
1208 *
1209 * Set the various PHY configuration parameters
1210 * supported on the Port.One or more of the Set PHY config parameters may be
1211 * ignored in an MFP mode as the PF may not have the privilege to set some
1212 * of the PHY Config parameters. This status will be indicated by the
1213 * command response.
1214 **/
1215enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1216 struct i40e_aq_set_phy_config *config,
1217 struct i40e_asq_cmd_details *cmd_details)
1218{
1219 struct i40e_aq_desc desc;
1220 struct i40e_aq_set_phy_config *cmd =
1221 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1222 enum i40e_status_code status;
1223
1224 if (!config)
1225 return I40E_ERR_PARAM;
1226
1227 i40e_fill_default_direct_cmd_desc(&desc,
1228 i40e_aqc_opc_set_phy_config);
1229
1230 *cmd = *config;
1231
1232 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1233
1234 return status;
1235}
1236
1237/**
1238 * i40e_set_fc
1239 * @hw: pointer to the hw struct
1240 *
1241 * Set the requested flow control mode using set_phy_config.
1242 **/
1243enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1244 bool atomic_restart)
1245{
1246 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1247 struct i40e_aq_get_phy_abilities_resp abilities;
1248 struct i40e_aq_set_phy_config config;
1249 enum i40e_status_code status;
1250 u8 pause_mask = 0x0;
1251
1252 *aq_failures = 0x0;
1253
1254 switch (fc_mode) {
1255 case I40E_FC_FULL:
1256 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1257 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1258 break;
1259 case I40E_FC_RX_PAUSE:
1260 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1261 break;
1262 case I40E_FC_TX_PAUSE:
1263 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1264 break;
1265 default:
1266 break;
1267 }
1268
1269 /* Get the current phy config */
1270 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1271 NULL);
1272 if (status) {
1273 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1274 return status;
1275 }
1276
1277 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1278 /* clear the old pause settings */
1279 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1280 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1281 /* set the new abilities */
1282 config.abilities |= pause_mask;
1283 /* If the abilities have changed, then set the new config */
1284 if (config.abilities != abilities.abilities) {
1285 /* Auto restart link so settings take effect */
1286 if (atomic_restart)
1287 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1288 /* Copy over all the old settings */
1289 config.phy_type = abilities.phy_type;
1290 config.link_speed = abilities.link_speed;
1291 config.eee_capability = abilities.eee_capability;
1292 config.eeer = abilities.eeer_val;
1293 config.low_power_ctrl = abilities.d3_lpan;
1294 status = i40e_aq_set_phy_config(hw, &config, NULL);
1295
1296 if (status)
1297 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1298 }
1299 /* Update the link info */
21af70fb 1300 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
c56999f9
CS		 1301 if (status) {
1302 /* Wait a little bit (on 40G cards it sometimes takes a really
1303 * long time for link to come back from the atomic reset)
1304 * and try once more
1305 */
1306 msleep(1000);
21af70fb 1307 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
c56999f9
CS		 1308 }
1309 if (status)
1310 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1311
1312 return status;
1313}
1314
c9b9b0ae
SN		 1315/**
1316 * i40e_aq_clear_pxe_mode
1317 * @hw: pointer to the hw struct
1318 * @cmd_details: pointer to command details structure or NULL
1319 *
1320 * Tell the firmware that the driver is taking over from PXE
1321 **/
1322i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1323 struct i40e_asq_cmd_details *cmd_details)
1324{
1325 i40e_status status;
1326 struct i40e_aq_desc desc;
1327 struct i40e_aqc_clear_pxe *cmd =
1328 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1329
1330 i40e_fill_default_direct_cmd_desc(&desc,
1331 i40e_aqc_opc_clear_pxe_mode);
1332
1333 cmd->rx_cnt = 0x2;
1334
1335 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1336
1337 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1338
1339 return status;
1340}
1341
56a62fc8
JB		 1342/**
1343 * i40e_aq_set_link_restart_an
1344 * @hw: pointer to the hw struct
1ac978af 1345 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1346 * @cmd_details: pointer to command details structure or NULL
1347 *
1348 * Sets up the link and restarts the Auto-Negotiation over the link.
1349 **/
1350i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1351 bool enable_link,
1352 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1353{
1354 struct i40e_aq_desc desc;
1355 struct i40e_aqc_set_link_restart_an *cmd =
1356 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1357 i40e_status status;
1358
1359 i40e_fill_default_direct_cmd_desc(&desc,
1360 i40e_aqc_opc_set_link_restart_an);
1361
1362 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1363 if (enable_link)
1364 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1365 else
1366 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1367
1368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1369
1370 return status;
1371}
1372
1373/**
1374 * i40e_aq_get_link_info
1375 * @hw: pointer to the hw struct
1376 * @enable_lse: enable/disable LinkStatusEvent reporting
1377 * @link: pointer to link status structure - optional
1378 * @cmd_details: pointer to command details structure or NULL
1379 *
1380 * Returns the link status of the adapter.
1381 **/
1382i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1383 bool enable_lse, struct i40e_link_status *link,
1384 struct i40e_asq_cmd_details *cmd_details)
1385{
1386 struct i40e_aq_desc desc;
1387 struct i40e_aqc_get_link_status *resp =
1388 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1389 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1390 i40e_status status;
c56999f9 1391 bool tx_pause, rx_pause;
56a62fc8
JB		 1392 u16 command_flags;
1393
1394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1395
1396 if (enable_lse)
1397 command_flags = I40E_AQ_LSE_ENABLE;
1398 else
1399 command_flags = I40E_AQ_LSE_DISABLE;
1400 resp->command_flags = cpu_to_le16(command_flags);
1401
1402 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1403
1404 if (status)
1405 goto aq_get_link_info_exit;
1406
1407 /* save off old link status information */
c36bd4a7 1408 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1409
1410 /* update link status */
1411 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1412 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1413 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1414 hw_link_info->link_info = resp->link_info;
1415 hw_link_info->an_info = resp->an_info;
1416 hw_link_info->ext_info = resp->ext_info;
639dc377 1417 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1418 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1419 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1420
c56999f9
CS		 1421 /* update fc info */
1422 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1423 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1424 if (tx_pause & rx_pause)
1425 hw->fc.current_mode = I40E_FC_FULL;
1426 else if (tx_pause)
1427 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1428 else if (rx_pause)
1429 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1430 else
1431 hw->fc.current_mode = I40E_FC_NONE;
1432
6bb3f23c
NP		 1433 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1434 hw_link_info->crc_enable = true;
1435 else
1436 hw_link_info->crc_enable = false;
56a62fc8
JB		 1437
1438 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1439 hw_link_info->lse_enable = true;
1440 else
1441 hw_link_info->lse_enable = false;
1442
1443 /* save link status information */
1444 if (link)
d7595a22 1445 *link = *hw_link_info;
56a62fc8
JB		 1446
1447 /* flag cleared so helper functions don't call AQ again */
1448 hw->phy.get_link_info = false;
1449
1450aq_get_link_info_exit:
1451 return status;
1452}
1453
7e2453fe
JB		 1454/**
1455 * i40e_aq_set_phy_int_mask
1456 * @hw: pointer to the hw struct
1457 * @mask: interrupt mask to be set
1458 * @cmd_details: pointer to command details structure or NULL
1459 *
1460 * Set link interrupt mask.
1461 **/
1462i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1463 u16 mask,
1464 struct i40e_asq_cmd_details *cmd_details)
1465{
1466 struct i40e_aq_desc desc;
1467 struct i40e_aqc_set_phy_int_mask *cmd =
1468 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1469 i40e_status status;
1470
1471 i40e_fill_default_direct_cmd_desc(&desc,
1472 i40e_aqc_opc_set_phy_int_mask);
1473
1474 cmd->event_mask = cpu_to_le16(mask);
1475
1476 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1477
1478 return status;
1479}
1480
56a62fc8
JB		 1481/**
1482 * i40e_aq_add_vsi
1483 * @hw: pointer to the hw struct
98d44381 1484 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1485 * @cmd_details: pointer to command details structure or NULL
1486 *
1487 * Add a VSI context to the hardware.
1488**/
1489i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1490 struct i40e_vsi_context *vsi_ctx,
1491 struct i40e_asq_cmd_details *cmd_details)
1492{
1493 struct i40e_aq_desc desc;
1494 struct i40e_aqc_add_get_update_vsi *cmd =
1495 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1496 struct i40e_aqc_add_get_update_vsi_completion *resp =
1497 (struct i40e_aqc_add_get_update_vsi_completion *)
1498 &desc.params.raw;
1499 i40e_status status;
1500
1501 i40e_fill_default_direct_cmd_desc(&desc,
1502 i40e_aqc_opc_add_vsi);
1503
1504 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1505 cmd->connection_type = vsi_ctx->connection_type;
1506 cmd->vf_id = vsi_ctx->vf_num;
1507 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1508
1509 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1510
1511 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1512 sizeof(vsi_ctx->info), cmd_details);
1513
1514 if (status)
1515 goto aq_add_vsi_exit;
1516
1517 vsi_ctx->seid = le16_to_cpu(resp->seid);
1518 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1519 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1520 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1521
1522aq_add_vsi_exit:
1523 return status;
1524}
1525
1526/**
1527 * i40e_aq_set_vsi_unicast_promiscuous
1528 * @hw: pointer to the hw struct
1529 * @seid: vsi number
1530 * @set: set unicast promiscuous enable/disable
1531 * @cmd_details: pointer to command details structure or NULL
1532 **/
1533i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1534 u16 seid, bool set,
1535 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1536{
1537 struct i40e_aq_desc desc;
1538 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1539 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1540 i40e_status status;
1541 u16 flags = 0;
1542
1543 i40e_fill_default_direct_cmd_desc(&desc,
1544 i40e_aqc_opc_set_vsi_promiscuous_modes);
1545
1546 if (set)
1547 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1548
1549 cmd->promiscuous_flags = cpu_to_le16(flags);
1550
1551 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1552
1553 cmd->seid = cpu_to_le16(seid);
1554 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1555
1556 return status;
1557}
1558
1559/**
1560 * i40e_aq_set_vsi_multicast_promiscuous
1561 * @hw: pointer to the hw struct
1562 * @seid: vsi number
1563 * @set: set multicast promiscuous enable/disable
1564 * @cmd_details: pointer to command details structure or NULL
1565 **/
1566i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1567 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1568{
1569 struct i40e_aq_desc desc;
1570 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1571 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1572 i40e_status status;
1573 u16 flags = 0;
1574
1575 i40e_fill_default_direct_cmd_desc(&desc,
1576 i40e_aqc_opc_set_vsi_promiscuous_modes);
1577
1578 if (set)
1579 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1580
1581 cmd->promiscuous_flags = cpu_to_le16(flags);
1582
1583 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1584
1585 cmd->seid = cpu_to_le16(seid);
1586 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1587
1588 return status;
1589}
1590
1591/**
1592 * i40e_aq_set_vsi_broadcast
1593 * @hw: pointer to the hw struct
1594 * @seid: vsi number
1595 * @set_filter: true to set filter, false to clear filter
1596 * @cmd_details: pointer to command details structure or NULL
1597 *
1598 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1599 **/
1600i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1601 u16 seid, bool set_filter,
1602 struct i40e_asq_cmd_details *cmd_details)
1603{
1604 struct i40e_aq_desc desc;
1605 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1606 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1607 i40e_status status;
1608
1609 i40e_fill_default_direct_cmd_desc(&desc,
1610 i40e_aqc_opc_set_vsi_promiscuous_modes);
1611
1612 if (set_filter)
1613 cmd->promiscuous_flags
1614 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1615 else
1616 cmd->promiscuous_flags
1617 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1618
1619 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1620 cmd->seid = cpu_to_le16(seid);
1621 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1622
1623 return status;
1624}
1625
1626/**
1627 * i40e_get_vsi_params - get VSI configuration info
1628 * @hw: pointer to the hw struct
98d44381 1629 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1630 * @cmd_details: pointer to command details structure or NULL
1631 **/
1632i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1633 struct i40e_vsi_context *vsi_ctx,
1634 struct i40e_asq_cmd_details *cmd_details)
1635{
1636 struct i40e_aq_desc desc;
f5ac8579
SN		 1637 struct i40e_aqc_add_get_update_vsi *cmd =
1638 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1639 struct i40e_aqc_add_get_update_vsi_completion *resp =
1640 (struct i40e_aqc_add_get_update_vsi_completion *)
1641 &desc.params.raw;
1642 i40e_status status;
1643
1644 i40e_fill_default_direct_cmd_desc(&desc,
1645 i40e_aqc_opc_get_vsi_parameters);
1646
f5ac8579 1647 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1648
1649 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 1650
1651 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1652 sizeof(vsi_ctx->info), NULL);
1653
1654 if (status)
1655 goto aq_get_vsi_params_exit;
1656
1657 vsi_ctx->seid = le16_to_cpu(resp->seid);
1658 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1659 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1660 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1661
1662aq_get_vsi_params_exit:
1663 return status;
1664}
1665
1666/**
1667 * i40e_aq_update_vsi_params
1668 * @hw: pointer to the hw struct
98d44381 1669 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1670 * @cmd_details: pointer to command details structure or NULL
1671 *
1672 * Update a VSI context.
1673 **/
1674i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1675 struct i40e_vsi_context *vsi_ctx,
1676 struct i40e_asq_cmd_details *cmd_details)
1677{
1678 struct i40e_aq_desc desc;
f5ac8579
SN		 1679 struct i40e_aqc_add_get_update_vsi *cmd =
1680 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1681 i40e_status status;
1682
1683 i40e_fill_default_direct_cmd_desc(&desc,
1684 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1685 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1686
1687 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1688
1689 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1690 sizeof(vsi_ctx->info), cmd_details);
1691
1692 return status;
1693}
1694
1695/**
1696 * i40e_aq_get_switch_config
1697 * @hw: pointer to the hardware structure
1698 * @buf: pointer to the result buffer
1699 * @buf_size: length of input buffer
1700 * @start_seid: seid to start for the report, 0 == beginning
1701 * @cmd_details: pointer to command details structure or NULL
1702 *
1703 * Fill the buf with switch configuration returned from AdminQ command
1704 **/
1705i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1706 struct i40e_aqc_get_switch_config_resp *buf,
1707 u16 buf_size, u16 *start_seid,
1708 struct i40e_asq_cmd_details *cmd_details)
1709{
1710 struct i40e_aq_desc desc;
1711 struct i40e_aqc_switch_seid *scfg =
1712 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1713 i40e_status status;
1714
1715 i40e_fill_default_direct_cmd_desc(&desc,
1716 i40e_aqc_opc_get_switch_config);
1717 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1718 if (buf_size > I40E_AQ_LARGE_BUF)
1719 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1720 scfg->seid = cpu_to_le16(*start_seid);
1721
1722 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1723 *start_seid = le16_to_cpu(scfg->seid);
1724
1725 return status;
1726}
1727
1728/**
1729 * i40e_aq_get_firmware_version
1730 * @hw: pointer to the hw struct
1731 * @fw_major_version: firmware major version
1732 * @fw_minor_version: firmware minor version
1733 * @api_major_version: major queue version
1734 * @api_minor_version: minor queue version
1735 * @cmd_details: pointer to command details structure or NULL
1736 *
1737 * Get the firmware version from the admin queue commands
1738 **/
1739i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1740 u16 *fw_major_version, u16 *fw_minor_version,
1741 u16 *api_major_version, u16 *api_minor_version,
1742 struct i40e_asq_cmd_details *cmd_details)
1743{
1744 struct i40e_aq_desc desc;
1745 struct i40e_aqc_get_version *resp =
1746 (struct i40e_aqc_get_version *)&desc.params.raw;
1747 i40e_status status;
1748
1749 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1750
1751 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1752
1753 if (!status) {
1754 if (fw_major_version != NULL)
1755 *fw_major_version = le16_to_cpu(resp->fw_major);
1756 if (fw_minor_version != NULL)
1757 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1758 if (api_major_version != NULL)
1759 *api_major_version = le16_to_cpu(resp->api_major);
1760 if (api_minor_version != NULL)
1761 *api_minor_version = le16_to_cpu(resp->api_minor);
1762 }
1763
1764 return status;
1765}
1766
1767/**
1768 * i40e_aq_send_driver_version
1769 * @hw: pointer to the hw struct
56a62fc8
JB		 1770 * @dv: driver's major, minor version
1771 * @cmd_details: pointer to command details structure or NULL
1772 *
1773 * Send the driver version to the firmware
1774 **/
1775i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1776 struct i40e_driver_version *dv,
1777 struct i40e_asq_cmd_details *cmd_details)
1778{
1779 struct i40e_aq_desc desc;
1780 struct i40e_aqc_driver_version *cmd =
1781 (struct i40e_aqc_driver_version *)&desc.params.raw;
1782 i40e_status status;
9d2f98e1 1783 u16 len;
56a62fc8
JB		 1784
1785 if (dv == NULL)
1786 return I40E_ERR_PARAM;
1787
1788 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1789
1790 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1791 cmd->driver_major_ver = dv->major_version;
1792 cmd->driver_minor_ver = dv->minor_version;
1793 cmd->driver_build_ver = dv->build_version;
1794 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 1795
1796 len = 0;
1797 while (len < sizeof(dv->driver_string) &&
1798 (dv->driver_string[len] < 0x80) &&
1799 dv->driver_string[len])
1800 len++;
1801 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1802 len, cmd_details);
56a62fc8
JB		 1803
1804 return status;
1805}
1806
1807/**
1808 * i40e_get_link_status - get status of the HW network link
1809 * @hw: pointer to the hw struct
1810 *
1811 * Returns true if link is up, false if link is down.
1812 *
1813 * Side effect: LinkStatusEvent reporting becomes enabled
1814 **/
1815bool i40e_get_link_status(struct i40e_hw *hw)
1816{
1817 i40e_status status = 0;
1818 bool link_status = false;
1819
1820 if (hw->phy.get_link_info) {
1821 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1822
1823 if (status)
1824 goto i40e_get_link_status_exit;
1825 }
1826
1827 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1828
1829i40e_get_link_status_exit:
1830 return link_status;
1831}
1832
1833/**
1834 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1835 * @hw: pointer to the hw struct
1836 * @uplink_seid: the MAC or other gizmo SEID
1837 * @downlink_seid: the VSI SEID
1838 * @enabled_tc: bitmap of TCs to be enabled
1839 * @default_port: true for default port VSI, false for control port
e1c51b95 1840 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1841 * @veb_seid: pointer to where to put the resulting VEB SEID
1842 * @cmd_details: pointer to command details structure or NULL
1843 *
1844 * This asks the FW to add a VEB between the uplink and downlink
1845 * elements. If the uplink SEID is 0, this will be a floating VEB.
1846 **/
1847i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1848 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1849 bool default_port, bool enable_l2_filtering,
1850 u16 *veb_seid,
56a62fc8
JB		 1851 struct i40e_asq_cmd_details *cmd_details)
1852{
1853 struct i40e_aq_desc desc;
1854 struct i40e_aqc_add_veb *cmd =
1855 (struct i40e_aqc_add_veb *)&desc.params.raw;
1856 struct i40e_aqc_add_veb_completion *resp =
1857 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1858 i40e_status status;
1859 u16 veb_flags = 0;
1860
1861 /* SEIDs need to either both be set or both be 0 for floating VEB */
1862 if (!!uplink_seid != !!downlink_seid)
1863 return I40E_ERR_PARAM;
1864
1865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1866
1867 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1868 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1869 cmd->enable_tcs = enabled_tc;
1870 if (!uplink_seid)
1871 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1872 if (default_port)
1873 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1874 else
1875 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1876
1877 if (enable_l2_filtering)
1878 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1879
56a62fc8
JB		 1880 cmd->veb_flags = cpu_to_le16(veb_flags);
1881
1882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1883
1884 if (!status && veb_seid)
1885 *veb_seid = le16_to_cpu(resp->veb_seid);
1886
1887 return status;
1888}
1889
1890/**
1891 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1892 * @hw: pointer to the hw struct
1893 * @veb_seid: the SEID of the VEB to query
1894 * @switch_id: the uplink switch id
98d44381 1895 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1896 * @statistic_index: index of the stats counter block for this VEB
1897 * @vebs_used: number of VEB's used by function
98d44381 1898 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1899 * @cmd_details: pointer to command details structure or NULL
1900 *
1901 * This retrieves the parameters for a particular VEB, specified by
1902 * uplink_seid, and returns them to the caller.
1903 **/
1904i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1905 u16 veb_seid, u16 *switch_id,
1906 bool *floating, u16 *statistic_index,
1907 u16 *vebs_used, u16 *vebs_free,
1908 struct i40e_asq_cmd_details *cmd_details)
1909{
1910 struct i40e_aq_desc desc;
1911 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1912 (struct i40e_aqc_get_veb_parameters_completion *)
1913 &desc.params.raw;
1914 i40e_status status;
1915
1916 if (veb_seid == 0)
1917 return I40E_ERR_PARAM;
1918
1919 i40e_fill_default_direct_cmd_desc(&desc,
1920 i40e_aqc_opc_get_veb_parameters);
1921 cmd_resp->seid = cpu_to_le16(veb_seid);
1922
1923 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1924 if (status)
1925 goto get_veb_exit;
1926
1927 if (switch_id)
1928 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1929 if (statistic_index)
1930 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1931 if (vebs_used)
1932 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1933 if (vebs_free)
1934 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1935 if (floating) {
1936 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1937 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1938 *floating = true;
1939 else
1940 *floating = false;
1941 }
1942
1943get_veb_exit:
1944 return status;
1945}
1946
1947/**
1948 * i40e_aq_add_macvlan
1949 * @hw: pointer to the hw struct
1950 * @seid: VSI for the mac address
1951 * @mv_list: list of macvlans to be added
1952 * @count: length of the list
1953 * @cmd_details: pointer to command details structure or NULL
1954 *
1955 * Add MAC/VLAN addresses to the HW filtering
1956 **/
1957i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1958 struct i40e_aqc_add_macvlan_element_data *mv_list,
1959 u16 count, struct i40e_asq_cmd_details *cmd_details)
1960{
1961 struct i40e_aq_desc desc;
1962 struct i40e_aqc_macvlan *cmd =
1963 (struct i40e_aqc_macvlan *)&desc.params.raw;
1964 i40e_status status;
1965 u16 buf_size;
1966
1967 if (count == 0 || !mv_list || !hw)
1968 return I40E_ERR_PARAM;
1969
1970 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1971
1972 /* prep the rest of the request */
1973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1974 cmd->num_addresses = cpu_to_le16(count);
1975 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1976 cmd->seid[1] = 0;
1977 cmd->seid[2] = 0;
1978
1979 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1980 if (buf_size > I40E_AQ_LARGE_BUF)
1981 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1982
1983 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1984 cmd_details);
1985
1986 return status;
1987}
1988
1989/**
1990 * i40e_aq_remove_macvlan
1991 * @hw: pointer to the hw struct
1992 * @seid: VSI for the mac address
1993 * @mv_list: list of macvlans to be removed
1994 * @count: length of the list
1995 * @cmd_details: pointer to command details structure or NULL
1996 *
1997 * Remove MAC/VLAN addresses from the HW filtering
1998 **/
1999i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2000 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2001 u16 count, struct i40e_asq_cmd_details *cmd_details)
2002{
2003 struct i40e_aq_desc desc;
2004 struct i40e_aqc_macvlan *cmd =
2005 (struct i40e_aqc_macvlan *)&desc.params.raw;
2006 i40e_status status;
2007 u16 buf_size;
2008
2009 if (count == 0 || !mv_list || !hw)
2010 return I40E_ERR_PARAM;
2011
2012 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2013
2014 /* prep the rest of the request */
2015 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2016 cmd->num_addresses = cpu_to_le16(count);
2017 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2018 cmd->seid[1] = 0;
2019 cmd->seid[2] = 0;
2020
2021 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2022 if (buf_size > I40E_AQ_LARGE_BUF)
2023 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2024
2025 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2026 cmd_details);
2027
2028 return status;
2029}
2030
56a62fc8
JB		 2031/**
2032 * i40e_aq_send_msg_to_vf
2033 * @hw: pointer to the hardware structure
2034 * @vfid: vf id to send msg
98d44381
JK		 2035 * @v_opcode: opcodes for VF-PF communication
2036 * @v_retval: return error code
56a62fc8
JB		 2037 * @msg: pointer to the msg buffer
2038 * @msglen: msg length
2039 * @cmd_details: pointer to command details
2040 *
2041 * send msg to vf
2042 **/
2043i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2044 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2045 struct i40e_asq_cmd_details *cmd_details)
2046{
2047 struct i40e_aq_desc desc;
2048 struct i40e_aqc_pf_vf_message *cmd =
2049 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2050 i40e_status status;
2051
2052 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2053 cmd->id = cpu_to_le32(vfid);
2054 desc.cookie_high = cpu_to_le32(v_opcode);
2055 desc.cookie_low = cpu_to_le32(v_retval);
2056 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2057 if (msglen) {
2058 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2059 I40E_AQ_FLAG_RD));
2060 if (msglen > I40E_AQ_LARGE_BUF)
2061 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2062 desc.datalen = cpu_to_le16(msglen);
2063 }
2064 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2065
2066 return status;
2067}
2068
9fee9db5
SN		 2069/**
2070 * i40e_aq_debug_read_register
2071 * @hw: pointer to the hw struct
2072 * @reg_addr: register address
2073 * @reg_val: register value
2074 * @cmd_details: pointer to command details structure or NULL
2075 *
2076 * Read the register using the admin queue commands
2077 **/
2078i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2079 u32 reg_addr, u64 *reg_val,
2080 struct i40e_asq_cmd_details *cmd_details)
2081{
2082 struct i40e_aq_desc desc;
2083 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2084 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2085 i40e_status status;
2086
2087 if (reg_val == NULL)
2088 return I40E_ERR_PARAM;
2089
2090 i40e_fill_default_direct_cmd_desc(&desc,
2091 i40e_aqc_opc_debug_read_reg);
2092
2093 cmd_resp->address = cpu_to_le32(reg_addr);
2094
2095 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2096
2097 if (!status) {
2098 *reg_val = ((u64)cmd_resp->value_high << 32) |
2099 (u64)cmd_resp->value_low;
2100 *reg_val = le64_to_cpu(*reg_val);
2101 }
2102
2103 return status;
2104}
2105
53db45cd
SN		 2106/**
2107 * i40e_aq_debug_write_register
2108 * @hw: pointer to the hw struct
2109 * @reg_addr: register address
2110 * @reg_val: register value
2111 * @cmd_details: pointer to command details structure or NULL
2112 *
2113 * Write to a register using the admin queue commands
2114 **/
2115i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2116 u32 reg_addr, u64 reg_val,
2117 struct i40e_asq_cmd_details *cmd_details)
2118{
2119 struct i40e_aq_desc desc;
2120 struct i40e_aqc_debug_reg_read_write *cmd =
2121 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2122 i40e_status status;
2123
2124 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2125
2126 cmd->address = cpu_to_le32(reg_addr);
2127 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2128 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2129
2130 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2131
2132 return status;
2133}
2134
56a62fc8
JB		 2135/**
2136 * i40e_aq_set_hmc_resource_profile
2137 * @hw: pointer to the hw struct
2138 * @profile: type of profile the HMC is to be set as
2139 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2140 * @cmd_details: pointer to command details structure or NULL
2141 *
2142 * set the HMC profile of the device.
2143 **/
2144i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2145 enum i40e_aq_hmc_profile profile,
2146 u8 pe_vf_enabled_count,
2147 struct i40e_asq_cmd_details *cmd_details)
2148{
2149 struct i40e_aq_desc desc;
2150 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2151 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2152 i40e_status status;
2153
2154 i40e_fill_default_direct_cmd_desc(&desc,
2155 i40e_aqc_opc_set_hmc_resource_profile);
2156
2157 cmd->pm_profile = (u8)profile;
2158 cmd->pe_vf_enabled = pe_vf_enabled_count;
2159
2160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2161
2162 return status;
2163}
2164
2165/**
2166 * i40e_aq_request_resource
2167 * @hw: pointer to the hw struct
2168 * @resource: resource id
2169 * @access: access type
2170 * @sdp_number: resource number
2171 * @timeout: the maximum time in ms that the driver may hold the resource
2172 * @cmd_details: pointer to command details structure or NULL
2173 *
2174 * requests common resource using the admin queue commands
2175 **/
2176i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2177 enum i40e_aq_resources_ids resource,
2178 enum i40e_aq_resource_access_type access,
2179 u8 sdp_number, u64 *timeout,
2180 struct i40e_asq_cmd_details *cmd_details)
2181{
2182 struct i40e_aq_desc desc;
2183 struct i40e_aqc_request_resource *cmd_resp =
2184 (struct i40e_aqc_request_resource *)&desc.params.raw;
2185 i40e_status status;
2186
2187 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2188
2189 cmd_resp->resource_id = cpu_to_le16(resource);
2190 cmd_resp->access_type = cpu_to_le16(access);
2191 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2192
2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2194 /* The completion specifies the maximum time in ms that the driver
2195 * may hold the resource in the Timeout field.
2196 * If the resource is held by someone else, the command completes with
2197 * busy return value and the timeout field indicates the maximum time
2198 * the current owner of the resource has to free it.
2199 */
2200 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2201 *timeout = le32_to_cpu(cmd_resp->timeout);
2202
2203 return status;
2204}
2205
2206/**
2207 * i40e_aq_release_resource
2208 * @hw: pointer to the hw struct
2209 * @resource: resource id
2210 * @sdp_number: resource number
2211 * @cmd_details: pointer to command details structure or NULL
2212 *
2213 * release common resource using the admin queue commands
2214 **/
2215i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2216 enum i40e_aq_resources_ids resource,
2217 u8 sdp_number,
2218 struct i40e_asq_cmd_details *cmd_details)
2219{
2220 struct i40e_aq_desc desc;
2221 struct i40e_aqc_request_resource *cmd =
2222 (struct i40e_aqc_request_resource *)&desc.params.raw;
2223 i40e_status status;
2224
2225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2226
2227 cmd->resource_id = cpu_to_le16(resource);
2228 cmd->resource_number = cpu_to_le32(sdp_number);
2229
2230 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2231
2232 return status;
2233}
2234
2235/**
2236 * i40e_aq_read_nvm
2237 * @hw: pointer to the hw struct
2238 * @module_pointer: module pointer location in words from the NVM beginning
2239 * @offset: byte offset from the module beginning
2240 * @length: length of the section to be read (in bytes from the offset)
2241 * @data: command buffer (size [bytes] = length)
2242 * @last_command: tells if this is the last command in a series
2243 * @cmd_details: pointer to command details structure or NULL
2244 *
2245 * Read the NVM using the admin queue commands
2246 **/
2247i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2248 u32 offset, u16 length, void *data,
2249 bool last_command,
2250 struct i40e_asq_cmd_details *cmd_details)
2251{
2252 struct i40e_aq_desc desc;
2253 struct i40e_aqc_nvm_update *cmd =
2254 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2255 i40e_status status;
2256
2257 /* In offset the highest byte must be zeroed. */
2258 if (offset & 0xFF000000) {
2259 status = I40E_ERR_PARAM;
2260 goto i40e_aq_read_nvm_exit;
2261 }
2262
2263 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2264
2265 /* If this is the last command in a series, set the proper flag. */
2266 if (last_command)
2267 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2268 cmd->module_pointer = module_pointer;
2269 cmd->offset = cpu_to_le32(offset);
2270 cmd->length = cpu_to_le16(length);
2271
2272 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2273 if (length > I40E_AQ_LARGE_BUF)
2274 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2275
2276 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2277
2278i40e_aq_read_nvm_exit:
2279 return status;
2280}
2281
cd552cb4
SN		 2282/**
2283 * i40e_aq_erase_nvm
2284 * @hw: pointer to the hw struct
2285 * @module_pointer: module pointer location in words from the NVM beginning
2286 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2287 * @length: length of the section to be erased (expressed in 4 KB)
2288 * @last_command: tells if this is the last command in a series
2289 * @cmd_details: pointer to command details structure or NULL
2290 *
2291 * Erase the NVM sector using the admin queue commands
2292 **/
2293i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2294 u32 offset, u16 length, bool last_command,
2295 struct i40e_asq_cmd_details *cmd_details)
2296{
2297 struct i40e_aq_desc desc;
2298 struct i40e_aqc_nvm_update *cmd =
2299 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2300 i40e_status status;
2301
2302 /* In offset the highest byte must be zeroed. */
2303 if (offset & 0xFF000000) {
2304 status = I40E_ERR_PARAM;
2305 goto i40e_aq_erase_nvm_exit;
2306 }
2307
2308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2309
2310 /* If this is the last command in a series, set the proper flag. */
2311 if (last_command)
2312 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2313 cmd->module_pointer = module_pointer;
2314 cmd->offset = cpu_to_le32(offset);
2315 cmd->length = cpu_to_le16(length);
2316
2317 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2318
2319i40e_aq_erase_nvm_exit:
2320 return status;
2321}
2322
56a62fc8
JB		 2323#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2324#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2325#define I40E_DEV_FUNC_CAP_NPAR 0x03
2326#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2327#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2328#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2329#define I40E_DEV_FUNC_CAP_VF 0x13
2330#define I40E_DEV_FUNC_CAP_VMDQ 0x14
2331#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2332#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2333#define I40E_DEV_FUNC_CAP_VSI 0x17
2334#define I40E_DEV_FUNC_CAP_DCB 0x18
2335#define I40E_DEV_FUNC_CAP_FCOE 0x21
63d7e5a4 2336#define I40E_DEV_FUNC_CAP_ISCSI 0x22
56a62fc8
JB		 2337#define I40E_DEV_FUNC_CAP_RSS 0x40
2338#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2339#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2340#define I40E_DEV_FUNC_CAP_MSIX 0x43
2341#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2342#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2343#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2344#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2345#define I40E_DEV_FUNC_CAP_CEM 0xF2
2346#define I40E_DEV_FUNC_CAP_IWARP 0x51
2347#define I40E_DEV_FUNC_CAP_LED 0x61
2348#define I40E_DEV_FUNC_CAP_SDP 0x62
2349#define I40E_DEV_FUNC_CAP_MDIO 0x63
2350
2351/**
2352 * i40e_parse_discover_capabilities
2353 * @hw: pointer to the hw struct
2354 * @buff: pointer to a buffer containing device/function capability records
2355 * @cap_count: number of capability records in the list
2356 * @list_type_opc: type of capabilities list to parse
2357 *
2358 * Parse the device/function capabilities list.
2359 **/
2360static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2361 u32 cap_count,
2362 enum i40e_admin_queue_opc list_type_opc)
2363{
2364 struct i40e_aqc_list_capabilities_element_resp *cap;
9fee9db5 2365 u32 valid_functions, num_functions;
56a62fc8
JB		 2366 u32 number, logical_id, phys_id;
2367 struct i40e_hw_capabilities *p;
56a62fc8
JB		 2368 u32 i = 0;
2369 u16 id;
2370
2371 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2372
2373 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 2374 p = &hw->dev_caps;
56a62fc8 2375 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 2376 p = &hw->func_caps;
56a62fc8
JB		 2377 else
2378 return;
2379
2380 for (i = 0; i < cap_count; i++, cap++) {
2381 id = le16_to_cpu(cap->id);
2382 number = le32_to_cpu(cap->number);
2383 logical_id = le32_to_cpu(cap->logical_id);
2384 phys_id = le32_to_cpu(cap->phys_id);
2385
2386 switch (id) {
2387 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2388 p->switch_mode = number;
2389 break;
2390 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2391 p->management_mode = number;
2392 break;
2393 case I40E_DEV_FUNC_CAP_NPAR:
2394 p->npar_enable = number;
2395 break;
2396 case I40E_DEV_FUNC_CAP_OS2BMC:
2397 p->os2bmc = number;
2398 break;
2399 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2400 p->valid_functions = number;
2401 break;
2402 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2403 if (number == 1)
2404 p->sr_iov_1_1 = true;
2405 break;
2406 case I40E_DEV_FUNC_CAP_VF:
2407 p->num_vfs = number;
2408 p->vf_base_id = logical_id;
2409 break;
2410 case I40E_DEV_FUNC_CAP_VMDQ:
2411 if (number == 1)
2412 p->vmdq = true;
2413 break;
2414 case I40E_DEV_FUNC_CAP_802_1_QBG:
2415 if (number == 1)
2416 p->evb_802_1_qbg = true;
2417 break;
2418 case I40E_DEV_FUNC_CAP_802_1_QBH:
2419 if (number == 1)
2420 p->evb_802_1_qbh = true;
2421 break;
2422 case I40E_DEV_FUNC_CAP_VSI:
2423 p->num_vsis = number;
2424 break;
2425 case I40E_DEV_FUNC_CAP_DCB:
2426 if (number == 1) {
2427 p->dcb = true;
2428 p->enabled_tcmap = logical_id;
2429 p->maxtc = phys_id;
2430 }
2431 break;
2432 case I40E_DEV_FUNC_CAP_FCOE:
2433 if (number == 1)
2434 p->fcoe = true;
2435 break;
63d7e5a4
NP		 2436 case I40E_DEV_FUNC_CAP_ISCSI:
2437 if (number == 1)
2438 p->iscsi = true;
2439 break;
56a62fc8
JB		 2440 case I40E_DEV_FUNC_CAP_RSS:
2441 p->rss = true;
e157ea30 2442 p->rss_table_size = number;
56a62fc8
JB		 2443 p->rss_table_entry_width = logical_id;
2444 break;
2445 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2446 p->num_rx_qp = number;
2447 p->base_queue = phys_id;
2448 break;
2449 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2450 p->num_tx_qp = number;
2451 p->base_queue = phys_id;
2452 break;
2453 case I40E_DEV_FUNC_CAP_MSIX:
2454 p->num_msix_vectors = number;
2455 break;
2456 case I40E_DEV_FUNC_CAP_MSIX_VF:
2457 p->num_msix_vectors_vf = number;
2458 break;
2459 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2460 if (number == 1)
2461 p->mfp_mode_1 = true;
2462 break;
2463 case I40E_DEV_FUNC_CAP_CEM:
2464 if (number == 1)
2465 p->mgmt_cem = true;
2466 break;
2467 case I40E_DEV_FUNC_CAP_IWARP:
2468 if (number == 1)
2469 p->iwarp = true;
2470 break;
2471 case I40E_DEV_FUNC_CAP_LED:
2472 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2473 p->led[phys_id] = true;
2474 break;
2475 case I40E_DEV_FUNC_CAP_SDP:
2476 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2477 p->sdp[phys_id] = true;
2478 break;
2479 case I40E_DEV_FUNC_CAP_MDIO:
2480 if (number == 1) {
2481 p->mdio_port_num = phys_id;
2482 p->mdio_port_mode = logical_id;
2483 }
2484 break;
2485 case I40E_DEV_FUNC_CAP_IEEE_1588:
2486 if (number == 1)
2487 p->ieee_1588 = true;
2488 break;
2489 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2490 p->fd = true;
2491 p->fd_filters_guaranteed = number;
2492 p->fd_filters_best_effort = logical_id;
2493 break;
2494 default:
2495 break;
2496 }
2497 }
2498
566bb85d
VD		 2499 /* Software override ensuring FCoE is disabled if npar or mfp
2500 * mode because it is not supported in these modes.
2501 */
2502 if (p->npar_enable || p->mfp_mode_1)
2503 p->fcoe = false;
2504
9fee9db5
SN		 2505 /* count the enabled ports (aka the "not disabled" ports) */
2506 hw->num_ports = 0;
2507 for (i = 0; i < 4; i++) {
2508 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2509 u64 port_cfg = 0;
2510
2511 /* use AQ read to get the physical register offset instead
2512 * of the port relative offset
2513 */
2514 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2515 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2516 hw->num_ports++;
2517 }
2518
2519 valid_functions = p->valid_functions;
2520 num_functions = 0;
2521 while (valid_functions) {
2522 if (valid_functions & 1)
2523 num_functions++;
2524 valid_functions >>= 1;
2525 }
2526
2527 /* partition id is 1-based, and functions are evenly spread
2528 * across the ports as partitions
2529 */
2530 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2531 hw->num_partitions = num_functions / hw->num_ports;
2532
56a62fc8
JB		 2533 /* additional HW specific goodies that might
2534 * someday be HW version specific
2535 */
2536 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2537}
2538
2539/**
2540 * i40e_aq_discover_capabilities
2541 * @hw: pointer to the hw struct
2542 * @buff: a virtual buffer to hold the capabilities
2543 * @buff_size: Size of the virtual buffer
2544 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2545 * @list_type_opc: capabilities type to discover - pass in the command opcode
2546 * @cmd_details: pointer to command details structure or NULL
2547 *
2548 * Get the device capabilities descriptions from the firmware
2549 **/
2550i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2551 void *buff, u16 buff_size, u16 *data_size,
2552 enum i40e_admin_queue_opc list_type_opc,
2553 struct i40e_asq_cmd_details *cmd_details)
2554{
2555 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 2556 struct i40e_aq_desc desc;
8fb905b3 2557 i40e_status status = 0;
56a62fc8
JB		 2558
2559 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2560
2561 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2562 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2563 status = I40E_ERR_PARAM;
2564 goto exit;
2565 }
2566
2567 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2568
2569 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2570 if (buff_size > I40E_AQ_LARGE_BUF)
2571 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2572
2573 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2574 *data_size = le16_to_cpu(desc.datalen);
2575
2576 if (status)
2577 goto exit;
2578
2579 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2580 list_type_opc);
2581
2582exit:
2583 return status;
2584}
2585
cd552cb4
SN		 2586/**
2587 * i40e_aq_update_nvm
2588 * @hw: pointer to the hw struct
2589 * @module_pointer: module pointer location in words from the NVM beginning
2590 * @offset: byte offset from the module beginning
2591 * @length: length of the section to be written (in bytes from the offset)
2592 * @data: command buffer (size [bytes] = length)
2593 * @last_command: tells if this is the last command in a series
2594 * @cmd_details: pointer to command details structure or NULL
2595 *
2596 * Update the NVM using the admin queue commands
2597 **/
2598i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2599 u32 offset, u16 length, void *data,
2600 bool last_command,
2601 struct i40e_asq_cmd_details *cmd_details)
2602{
2603 struct i40e_aq_desc desc;
2604 struct i40e_aqc_nvm_update *cmd =
2605 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2606 i40e_status status;
2607
2608 /* In offset the highest byte must be zeroed. */
2609 if (offset & 0xFF000000) {
2610 status = I40E_ERR_PARAM;
2611 goto i40e_aq_update_nvm_exit;
2612 }
2613
2614 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2615
2616 /* If this is the last command in a series, set the proper flag. */
2617 if (last_command)
2618 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2619 cmd->module_pointer = module_pointer;
2620 cmd->offset = cpu_to_le32(offset);
2621 cmd->length = cpu_to_le16(length);
2622
2623 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2624 if (length > I40E_AQ_LARGE_BUF)
2625 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2626
2627 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2628
2629i40e_aq_update_nvm_exit:
2630 return status;
2631}
2632
56a62fc8
JB		 2633/**
2634 * i40e_aq_get_lldp_mib
2635 * @hw: pointer to the hw struct
2636 * @bridge_type: type of bridge requested
2637 * @mib_type: Local, Remote or both Local and Remote MIBs
2638 * @buff: pointer to a user supplied buffer to store the MIB block
2639 * @buff_size: size of the buffer (in bytes)
2640 * @local_len : length of the returned Local LLDP MIB
2641 * @remote_len: length of the returned Remote LLDP MIB
2642 * @cmd_details: pointer to command details structure or NULL
2643 *
2644 * Requests the complete LLDP MIB (entire packet).
2645 **/
2646i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2647 u8 mib_type, void *buff, u16 buff_size,
2648 u16 *local_len, u16 *remote_len,
2649 struct i40e_asq_cmd_details *cmd_details)
2650{
2651 struct i40e_aq_desc desc;
2652 struct i40e_aqc_lldp_get_mib *cmd =
2653 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2654 struct i40e_aqc_lldp_get_mib *resp =
2655 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2656 i40e_status status;
2657
2658 if (buff_size == 0 || !buff)
2659 return I40E_ERR_PARAM;
2660
2661 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2662 /* Indirect Command */
2663 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2664
2665 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2666 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2667 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2668
2669 desc.datalen = cpu_to_le16(buff_size);
2670
2671 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2672 if (buff_size > I40E_AQ_LARGE_BUF)
2673 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2674
2675 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2676 if (!status) {
2677 if (local_len != NULL)
2678 *local_len = le16_to_cpu(resp->local_len);
2679 if (remote_len != NULL)
2680 *remote_len = le16_to_cpu(resp->remote_len);
2681 }
2682
2683 return status;
2684}
2685
2686/**
2687 * i40e_aq_cfg_lldp_mib_change_event
2688 * @hw: pointer to the hw struct
2689 * @enable_update: Enable or Disable event posting
2690 * @cmd_details: pointer to command details structure or NULL
2691 *
2692 * Enable or Disable posting of an event on ARQ when LLDP MIB
2693 * associated with the interface changes
2694 **/
2695i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2696 bool enable_update,
2697 struct i40e_asq_cmd_details *cmd_details)
2698{
2699 struct i40e_aq_desc desc;
2700 struct i40e_aqc_lldp_update_mib *cmd =
2701 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2702 i40e_status status;
2703
2704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2705
2706 if (!enable_update)
2707 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2708
2709 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2710
2711 return status;
2712}
2713
2714/**
2715 * i40e_aq_stop_lldp
2716 * @hw: pointer to the hw struct
2717 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2718 * @cmd_details: pointer to command details structure or NULL
2719 *
2720 * Stop or Shutdown the embedded LLDP Agent
2721 **/
2722i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2723 struct i40e_asq_cmd_details *cmd_details)
2724{
2725 struct i40e_aq_desc desc;
2726 struct i40e_aqc_lldp_stop *cmd =
2727 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2728 i40e_status status;
2729
2730 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2731
2732 if (shutdown_agent)
2733 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2734
2735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2736
2737 return status;
2738}
2739
2740/**
2741 * i40e_aq_start_lldp
2742 * @hw: pointer to the hw struct
2743 * @cmd_details: pointer to command details structure or NULL
2744 *
2745 * Start the embedded LLDP Agent on all ports.
2746 **/
2747i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2748 struct i40e_asq_cmd_details *cmd_details)
2749{
2750 struct i40e_aq_desc desc;
2751 struct i40e_aqc_lldp_start *cmd =
2752 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2753 i40e_status status;
2754
2755 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2756
2757 cmd->command = I40E_AQ_LLDP_AGENT_START;
2758
2759 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2760
2761 return status;
2762}
2763
9fa61dd2
NP		 2764/**
2765 * i40e_aq_get_cee_dcb_config
2766 * @hw: pointer to the hw struct
2767 * @buff: response buffer that stores CEE operational configuration
2768 * @buff_size: size of the buffer passed
2769 * @cmd_details: pointer to command details structure or NULL
2770 *
2771 * Get CEE DCBX mode operational configuration from firmware
2772 **/
2773i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
2774 void *buff, u16 buff_size,
2775 struct i40e_asq_cmd_details *cmd_details)
2776{
2777 struct i40e_aq_desc desc;
2778 i40e_status status;
2779
2780 if (buff_size == 0 || !buff)
2781 return I40E_ERR_PARAM;
2782
2783 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
2784
2785 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2786 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
2787 cmd_details);
2788
2789 return status;
2790}
2791
a1c9a9d9
JK		 2792/**
2793 * i40e_aq_add_udp_tunnel
2794 * @hw: pointer to the hw struct
2795 * @udp_port: the UDP port to add
2796 * @header_len: length of the tunneling header length in DWords
2797 * @protocol_index: protocol index type
98d44381 2798 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2799 * @cmd_details: pointer to command details structure or NULL
2800 **/
2801i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 2802 u16 udp_port, u8 protocol_index,
2803 u8 *filter_index,
a1c9a9d9
JK		 2804 struct i40e_asq_cmd_details *cmd_details)
2805{
2806 struct i40e_aq_desc desc;
2807 struct i40e_aqc_add_udp_tunnel *cmd =
2808 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2809 struct i40e_aqc_del_udp_tunnel_completion *resp =
2810 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2811 i40e_status status;
2812
2813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2814
2815 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2816 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2817
2818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2819
2820 if (!status)
2821 *filter_index = resp->index;
2822
2823 return status;
2824}
2825
2826/**
2827 * i40e_aq_del_udp_tunnel
2828 * @hw: pointer to the hw struct
2829 * @index: filter index
2830 * @cmd_details: pointer to command details structure or NULL
2831 **/
2832i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2833 struct i40e_asq_cmd_details *cmd_details)
2834{
2835 struct i40e_aq_desc desc;
2836 struct i40e_aqc_remove_udp_tunnel *cmd =
2837 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2838 i40e_status status;
2839
2840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2841
2842 cmd->index = index;
2843
2844 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2845
2846 return status;
2847}
2848
56a62fc8
JB		 2849/**
2850 * i40e_aq_delete_element - Delete switch element
2851 * @hw: pointer to the hw struct
2852 * @seid: the SEID to delete from the switch
2853 * @cmd_details: pointer to command details structure or NULL
2854 *
2855 * This deletes a switch element from the switch.
2856 **/
2857i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2858 struct i40e_asq_cmd_details *cmd_details)
2859{
2860 struct i40e_aq_desc desc;
2861 struct i40e_aqc_switch_seid *cmd =
2862 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2863 i40e_status status;
2864
2865 if (seid == 0)
2866 return I40E_ERR_PARAM;
2867
2868 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2869
2870 cmd->seid = cpu_to_le16(seid);
2871
2872 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2873
2874 return status;
2875}
2876
afb3ff0d
NP		 2877/**
2878 * i40e_aq_dcb_updated - DCB Updated Command
2879 * @hw: pointer to the hw struct
2880 * @cmd_details: pointer to command details structure or NULL
2881 *
2882 * EMP will return when the shared RPB settings have been
2883 * recomputed and modified. The retval field in the descriptor
2884 * will be set to 0 when RPB is modified.
2885 **/
2886i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2887 struct i40e_asq_cmd_details *cmd_details)
2888{
2889 struct i40e_aq_desc desc;
2890 i40e_status status;
2891
2892 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2893
2894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2895
2896 return status;
2897}
2898
56a62fc8
JB		 2899/**
2900 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2901 * @hw: pointer to the hw struct
2902 * @seid: seid for the physical port/switching component/vsi
2903 * @buff: Indirect buffer to hold data parameters and response
2904 * @buff_size: Indirect buffer size
2905 * @opcode: Tx scheduler AQ command opcode
2906 * @cmd_details: pointer to command details structure or NULL
2907 *
2908 * Generic command handler for Tx scheduler AQ commands
2909 **/
2910static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2911 void *buff, u16 buff_size,
2912 enum i40e_admin_queue_opc opcode,
2913 struct i40e_asq_cmd_details *cmd_details)
2914{
2915 struct i40e_aq_desc desc;
2916 struct i40e_aqc_tx_sched_ind *cmd =
2917 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2918 i40e_status status;
2919 bool cmd_param_flag = false;
2920
2921 switch (opcode) {
2922 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2923 case i40e_aqc_opc_configure_vsi_tc_bw:
2924 case i40e_aqc_opc_enable_switching_comp_ets:
2925 case i40e_aqc_opc_modify_switching_comp_ets:
2926 case i40e_aqc_opc_disable_switching_comp_ets:
2927 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2928 case i40e_aqc_opc_configure_switching_comp_bw_config:
2929 cmd_param_flag = true;
2930 break;
2931 case i40e_aqc_opc_query_vsi_bw_config:
2932 case i40e_aqc_opc_query_vsi_ets_sla_config:
2933 case i40e_aqc_opc_query_switching_comp_ets_config:
2934 case i40e_aqc_opc_query_port_ets_config:
2935 case i40e_aqc_opc_query_switching_comp_bw_config:
2936 cmd_param_flag = false;
2937 break;
2938 default:
2939 return I40E_ERR_PARAM;
2940 }
2941
2942 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2943
2944 /* Indirect command */
2945 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2946 if (cmd_param_flag)
2947 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2948 if (buff_size > I40E_AQ_LARGE_BUF)
2949 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2950
2951 desc.datalen = cpu_to_le16(buff_size);
2952
2953 cmd->vsi_seid = cpu_to_le16(seid);
2954
2955 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2956
2957 return status;
2958}
2959
6b192891
MW		 2960/**
2961 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2962 * @hw: pointer to the hw struct
2963 * @seid: VSI seid
2964 * @credit: BW limit credits (0 = disabled)
2965 * @max_credit: Max BW limit credits
2966 * @cmd_details: pointer to command details structure or NULL
2967 **/
2968i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2969 u16 seid, u16 credit, u8 max_credit,
2970 struct i40e_asq_cmd_details *cmd_details)
2971{
2972 struct i40e_aq_desc desc;
2973 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2974 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2975 i40e_status status;
2976
2977 i40e_fill_default_direct_cmd_desc(&desc,
2978 i40e_aqc_opc_configure_vsi_bw_limit);
2979
2980 cmd->vsi_seid = cpu_to_le16(seid);
2981 cmd->credit = cpu_to_le16(credit);
2982 cmd->max_credit = max_credit;
2983
2984 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2985
2986 return status;
2987}
2988
56a62fc8
JB		 2989/**
2990 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2991 * @hw: pointer to the hw struct
2992 * @seid: VSI seid
2993 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2994 * @cmd_details: pointer to command details structure or NULL
2995 **/
2996i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2997 u16 seid,
2998 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2999 struct i40e_asq_cmd_details *cmd_details)
3000{
3001 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3002 i40e_aqc_opc_configure_vsi_tc_bw,
3003 cmd_details);
3004}
3005
afb3ff0d
NP		 3006/**
3007 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3008 * @hw: pointer to the hw struct
3009 * @seid: seid of the switching component connected to Physical Port
3010 * @ets_data: Buffer holding ETS parameters
3011 * @cmd_details: pointer to command details structure or NULL
3012 **/
3013i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3014 u16 seid,
3015 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3016 enum i40e_admin_queue_opc opcode,
3017 struct i40e_asq_cmd_details *cmd_details)
3018{
3019 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3020 sizeof(*ets_data), opcode, cmd_details);
3021}
3022
3023/**
3024 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3025 * @hw: pointer to the hw struct
3026 * @seid: seid of the switching component
3027 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3028 * @cmd_details: pointer to command details structure or NULL
3029 **/
3030i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3031 u16 seid,
3032 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3033 struct i40e_asq_cmd_details *cmd_details)
3034{
3035 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3036 i40e_aqc_opc_configure_switching_comp_bw_config,
3037 cmd_details);
3038}
3039
56a62fc8
JB		 3040/**
3041 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3042 * @hw: pointer to the hw struct
3043 * @seid: seid of the VSI
3044 * @bw_data: Buffer to hold VSI BW configuration
3045 * @cmd_details: pointer to command details structure or NULL
3046 **/
3047i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3048 u16 seid,
3049 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3050 struct i40e_asq_cmd_details *cmd_details)
3051{
3052 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3053 i40e_aqc_opc_query_vsi_bw_config,
3054 cmd_details);
3055}
3056
3057/**
3058 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3059 * @hw: pointer to the hw struct
3060 * @seid: seid of the VSI
3061 * @bw_data: Buffer to hold VSI BW configuration per TC
3062 * @cmd_details: pointer to command details structure or NULL
3063 **/
3064i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3065 u16 seid,
3066 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3067 struct i40e_asq_cmd_details *cmd_details)
3068{
3069 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3070 i40e_aqc_opc_query_vsi_ets_sla_config,
3071 cmd_details);
3072}
3073
3074/**
3075 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3076 * @hw: pointer to the hw struct
3077 * @seid: seid of the switching component
3078 * @bw_data: Buffer to hold switching component's per TC BW config
3079 * @cmd_details: pointer to command details structure or NULL
3080 **/
3081i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3082 u16 seid,
3083 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3084 struct i40e_asq_cmd_details *cmd_details)
3085{
3086 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3087 i40e_aqc_opc_query_switching_comp_ets_config,
3088 cmd_details);
3089}
3090
3091/**
3092 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3093 * @hw: pointer to the hw struct
3094 * @seid: seid of the VSI or switching component connected to Physical Port
3095 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3096 * @cmd_details: pointer to command details structure or NULL
3097 **/
3098i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3099 u16 seid,
3100 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3101 struct i40e_asq_cmd_details *cmd_details)
3102{
3103 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3104 i40e_aqc_opc_query_port_ets_config,
3105 cmd_details);
3106}
3107
3108/**
3109 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3110 * @hw: pointer to the hw struct
3111 * @seid: seid of the switching component
3112 * @bw_data: Buffer to hold switching component's BW configuration
3113 * @cmd_details: pointer to command details structure or NULL
3114 **/
3115i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3116 u16 seid,
3117 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3118 struct i40e_asq_cmd_details *cmd_details)
3119{
3120 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3121 i40e_aqc_opc_query_switching_comp_bw_config,
3122 cmd_details);
3123}
3124
3125/**
3126 * i40e_validate_filter_settings
3127 * @hw: pointer to the hardware structure
3128 * @settings: Filter control settings
3129 *
3130 * Check and validate the filter control settings passed.
3131 * The function checks for the valid filter/context sizes being
3132 * passed for FCoE and PE.
3133 *
3134 * Returns 0 if the values passed are valid and within
3135 * range else returns an error.
3136 **/
3137static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3138 struct i40e_filter_control_settings *settings)
3139{
3140 u32 fcoe_cntx_size, fcoe_filt_size;
3141 u32 pe_cntx_size, pe_filt_size;
467d729a 3142 u32 fcoe_fmax;
56a62fc8
JB		 3143 u32 val;
3144
3145 /* Validate FCoE settings passed */
3146 switch (settings->fcoe_filt_num) {
3147 case I40E_HASH_FILTER_SIZE_1K:
3148 case I40E_HASH_FILTER_SIZE_2K:
3149 case I40E_HASH_FILTER_SIZE_4K:
3150 case I40E_HASH_FILTER_SIZE_8K:
3151 case I40E_HASH_FILTER_SIZE_16K:
3152 case I40E_HASH_FILTER_SIZE_32K:
3153 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3154 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3155 break;
3156 default:
3157 return I40E_ERR_PARAM;
3158 }
3159
3160 switch (settings->fcoe_cntx_num) {
3161 case I40E_DMA_CNTX_SIZE_512:
3162 case I40E_DMA_CNTX_SIZE_1K:
3163 case I40E_DMA_CNTX_SIZE_2K:
3164 case I40E_DMA_CNTX_SIZE_4K:
3165 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3166 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3167 break;
3168 default:
3169 return I40E_ERR_PARAM;
3170 }
3171
3172 /* Validate PE settings passed */
3173 switch (settings->pe_filt_num) {
3174 case I40E_HASH_FILTER_SIZE_1K:
3175 case I40E_HASH_FILTER_SIZE_2K:
3176 case I40E_HASH_FILTER_SIZE_4K:
3177 case I40E_HASH_FILTER_SIZE_8K:
3178 case I40E_HASH_FILTER_SIZE_16K:
3179 case I40E_HASH_FILTER_SIZE_32K:
3180 case I40E_HASH_FILTER_SIZE_64K:
3181 case I40E_HASH_FILTER_SIZE_128K:
3182 case I40E_HASH_FILTER_SIZE_256K:
3183 case I40E_HASH_FILTER_SIZE_512K:
3184 case I40E_HASH_FILTER_SIZE_1M:
3185 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3186 pe_filt_size <<= (u32)settings->pe_filt_num;
3187 break;
3188 default:
3189 return I40E_ERR_PARAM;
3190 }
3191
3192 switch (settings->pe_cntx_num) {
3193 case I40E_DMA_CNTX_SIZE_512:
3194 case I40E_DMA_CNTX_SIZE_1K:
3195 case I40E_DMA_CNTX_SIZE_2K:
3196 case I40E_DMA_CNTX_SIZE_4K:
3197 case I40E_DMA_CNTX_SIZE_8K:
3198 case I40E_DMA_CNTX_SIZE_16K:
3199 case I40E_DMA_CNTX_SIZE_32K:
3200 case I40E_DMA_CNTX_SIZE_64K:
3201 case I40E_DMA_CNTX_SIZE_128K:
3202 case I40E_DMA_CNTX_SIZE_256K:
3203 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3204 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3205 break;
3206 default:
3207 return I40E_ERR_PARAM;
3208 }
3209
3210 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3211 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3212 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3213 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3214 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3215 return I40E_ERR_INVALID_SIZE;
3216
56a62fc8
JB		 3217 return 0;
3218}
3219
3220/**
3221 * i40e_set_filter_control
3222 * @hw: pointer to the hardware structure
3223 * @settings: Filter control settings
3224 *
3225 * Set the Queue Filters for PE/FCoE and enable filters required
3226 * for a single PF. It is expected that these settings are programmed
3227 * at the driver initialization time.
3228 **/
3229i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3230 struct i40e_filter_control_settings *settings)
3231{
3232 i40e_status ret = 0;
3233 u32 hash_lut_size = 0;
3234 u32 val;
3235
3236 if (!settings)
3237 return I40E_ERR_PARAM;
3238
3239 /* Validate the input settings */
3240 ret = i40e_validate_filter_settings(hw, settings);
3241 if (ret)
3242 return ret;
3243
3244 /* Read the PF Queue Filter control register */
3245 val = rd32(hw, I40E_PFQF_CTL_0);
3246
3247 /* Program required PE hash buckets for the PF */
3248 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3249 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3250 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3251 /* Program required PE contexts for the PF */
3252 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3253 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3254 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3255
3256 /* Program required FCoE hash buckets for the PF */
3257 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3258 val |= ((u32)settings->fcoe_filt_num <<
3259 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3260 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3261 /* Program required FCoE DDP contexts for the PF */
3262 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3263 val |= ((u32)settings->fcoe_cntx_num <<
3264 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3265 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3266
3267 /* Program Hash LUT size for the PF */
3268 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3269 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3270 hash_lut_size = 1;
3271 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3272 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3273
3274 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3275 if (settings->enable_fdir)
3276 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3277 if (settings->enable_ethtype)
3278 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3279 if (settings->enable_macvlan)
3280 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3281
3282 wr32(hw, I40E_PFQF_CTL_0, val);
3283
3284 return 0;
3285}
afb3ff0d
NP		 3286
3287/**
3288 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3289 * @hw: pointer to the hw struct
3290 * @mac_addr: MAC address to use in the filter
3291 * @ethtype: Ethertype to use in the filter
3292 * @flags: Flags that needs to be applied to the filter
3293 * @vsi_seid: seid of the control VSI
3294 * @queue: VSI queue number to send the packet to
3295 * @is_add: Add control packet filter if True else remove
3296 * @stats: Structure to hold information on control filter counts
3297 * @cmd_details: pointer to command details structure or NULL
3298 *
3299 * This command will Add or Remove control packet filter for a control VSI.
3300 * In return it will update the total number of perfect filter count in
3301 * the stats member.
3302 **/
3303i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3304 u8 *mac_addr, u16 ethtype, u16 flags,
3305 u16 vsi_seid, u16 queue, bool is_add,
3306 struct i40e_control_filter_stats *stats,
3307 struct i40e_asq_cmd_details *cmd_details)
3308{
3309 struct i40e_aq_desc desc;
3310 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3311 (struct i40e_aqc_add_remove_control_packet_filter *)
3312 &desc.params.raw;
3313 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3314 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3315 &desc.params.raw;
3316 i40e_status status;
3317
3318 if (vsi_seid == 0)
3319 return I40E_ERR_PARAM;
3320
3321 if (is_add) {
3322 i40e_fill_default_direct_cmd_desc(&desc,
3323 i40e_aqc_opc_add_control_packet_filter);
3324 cmd->queue = cpu_to_le16(queue);
3325 } else {
3326 i40e_fill_default_direct_cmd_desc(&desc,
3327 i40e_aqc_opc_remove_control_packet_filter);
3328 }
3329
3330 if (mac_addr)
3331 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3332
3333 cmd->etype = cpu_to_le16(ethtype);
3334 cmd->flags = cpu_to_le16(flags);
3335 cmd->seid = cpu_to_le16(vsi_seid);
3336
3337 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3338
3339 if (!status && stats) {
3340 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3341 stats->etype_used = le16_to_cpu(resp->etype_used);
3342 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3343 stats->etype_free = le16_to_cpu(resp->etype_free);
3344 }
3345
3346 return status;
3347}
3348
2fd75f31
NP		 3349/**
3350 * i40e_aq_resume_port_tx
3351 * @hw: pointer to the hardware structure
3352 * @cmd_details: pointer to command details structure or NULL
3353 *
3354 * Resume port's Tx traffic
3355 **/
3356i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3357 struct i40e_asq_cmd_details *cmd_details)
3358{
3359 struct i40e_aq_desc desc;
3360 i40e_status status;
3361
3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3363
3364 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3365
3366 return status;
3367}
3368
d4dfb81a
CS		 3369/**
3370 * i40e_set_pci_config_data - store PCI bus info
3371 * @hw: pointer to hardware structure
3372 * @link_status: the link status word from PCI config space
3373 *
3374 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3375 **/
3376void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3377{
3378 hw->bus.type = i40e_bus_type_pci_express;
3379
3380 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3381 case PCI_EXP_LNKSTA_NLW_X1:
3382 hw->bus.width = i40e_bus_width_pcie_x1;
3383 break;
3384 case PCI_EXP_LNKSTA_NLW_X2:
3385 hw->bus.width = i40e_bus_width_pcie_x2;
3386 break;
3387 case PCI_EXP_LNKSTA_NLW_X4:
3388 hw->bus.width = i40e_bus_width_pcie_x4;
3389 break;
3390 case PCI_EXP_LNKSTA_NLW_X8:
3391 hw->bus.width = i40e_bus_width_pcie_x8;
3392 break;
3393 default:
3394 hw->bus.width = i40e_bus_width_unknown;
3395 break;
3396 }
3397
3398 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3399 case PCI_EXP_LNKSTA_CLS_2_5GB:
3400 hw->bus.speed = i40e_bus_speed_2500;
3401 break;
3402 case PCI_EXP_LNKSTA_CLS_5_0GB:
3403 hw->bus.speed = i40e_bus_speed_5000;
3404 break;
3405 case PCI_EXP_LNKSTA_CLS_8_0GB:
3406 hw->bus.speed = i40e_bus_speed_8000;
3407 break;
3408 default:
3409 hw->bus.speed = i40e_bus_speed_unknown;
3410 break;
3411 }
3412}
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