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i40e: set broadcast promiscuous mode for each active VLAN
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
67be6eb2 4 * Copyright(c) 2013 - 2016 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e 45 case I40E_DEV_ID_SFP_XL710:
ab60085e 46 case I40E_DEV_ID_QEMU:
ab60085e
SN		 47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
ab60085e
SN		 49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
5960d33f 52 case I40E_DEV_ID_10G_BASE_T:
bc5166b9 53 case I40E_DEV_ID_10G_BASE_T4:
ae24b409 54 case I40E_DEV_ID_20G_KR2:
48a3b512 55 case I40E_DEV_ID_20G_KR2_A:
56a62fc8
JB		 56 hw->mac.type = I40E_MAC_XL710;
57 break;
35dae51d
ASJ		 58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
87e6c1d7
ASJ		 60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
d6bf58c2 63 case I40E_DEV_ID_SFP_I_X722:
87e6c1d7
ASJ		 64 hw->mac.type = I40E_MAC_X722;
65 break;
56a62fc8
JB		 66 default:
67 hw->mac.type = I40E_MAC_GENERIC;
68 break;
69 }
70 } else {
71 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
72 }
73
74 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
75 hw->mac.type, status);
76 return status;
77}
78
f1c7e72e
SN		 79/**
80 * i40e_aq_str - convert AQ err code to a string
81 * @hw: pointer to the HW structure
82 * @aq_err: the AQ error code to convert
83 **/
4e68adfe 84const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
f1c7e72e
SN		 85{
86 switch (aq_err) {
87 case I40E_AQ_RC_OK:
88 return "OK";
89 case I40E_AQ_RC_EPERM:
90 return "I40E_AQ_RC_EPERM";
91 case I40E_AQ_RC_ENOENT:
92 return "I40E_AQ_RC_ENOENT";
93 case I40E_AQ_RC_ESRCH:
94 return "I40E_AQ_RC_ESRCH";
95 case I40E_AQ_RC_EINTR:
96 return "I40E_AQ_RC_EINTR";
97 case I40E_AQ_RC_EIO:
98 return "I40E_AQ_RC_EIO";
99 case I40E_AQ_RC_ENXIO:
100 return "I40E_AQ_RC_ENXIO";
101 case I40E_AQ_RC_E2BIG:
102 return "I40E_AQ_RC_E2BIG";
103 case I40E_AQ_RC_EAGAIN:
104 return "I40E_AQ_RC_EAGAIN";
105 case I40E_AQ_RC_ENOMEM:
106 return "I40E_AQ_RC_ENOMEM";
107 case I40E_AQ_RC_EACCES:
108 return "I40E_AQ_RC_EACCES";
109 case I40E_AQ_RC_EFAULT:
110 return "I40E_AQ_RC_EFAULT";
111 case I40E_AQ_RC_EBUSY:
112 return "I40E_AQ_RC_EBUSY";
113 case I40E_AQ_RC_EEXIST:
114 return "I40E_AQ_RC_EEXIST";
115 case I40E_AQ_RC_EINVAL:
116 return "I40E_AQ_RC_EINVAL";
117 case I40E_AQ_RC_ENOTTY:
118 return "I40E_AQ_RC_ENOTTY";
119 case I40E_AQ_RC_ENOSPC:
120 return "I40E_AQ_RC_ENOSPC";
121 case I40E_AQ_RC_ENOSYS:
122 return "I40E_AQ_RC_ENOSYS";
123 case I40E_AQ_RC_ERANGE:
124 return "I40E_AQ_RC_ERANGE";
125 case I40E_AQ_RC_EFLUSHED:
126 return "I40E_AQ_RC_EFLUSHED";
127 case I40E_AQ_RC_BAD_ADDR:
128 return "I40E_AQ_RC_BAD_ADDR";
129 case I40E_AQ_RC_EMODE:
130 return "I40E_AQ_RC_EMODE";
131 case I40E_AQ_RC_EFBIG:
132 return "I40E_AQ_RC_EFBIG";
133 }
134
135 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
136 return hw->err_str;
137}
138
139/**
140 * i40e_stat_str - convert status err code to a string
141 * @hw: pointer to the HW structure
142 * @stat_err: the status error code to convert
143 **/
4e68adfe 144const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
f1c7e72e
SN		 145{
146 switch (stat_err) {
147 case 0:
148 return "OK";
149 case I40E_ERR_NVM:
150 return "I40E_ERR_NVM";
151 case I40E_ERR_NVM_CHECKSUM:
152 return "I40E_ERR_NVM_CHECKSUM";
153 case I40E_ERR_PHY:
154 return "I40E_ERR_PHY";
155 case I40E_ERR_CONFIG:
156 return "I40E_ERR_CONFIG";
157 case I40E_ERR_PARAM:
158 return "I40E_ERR_PARAM";
159 case I40E_ERR_MAC_TYPE:
160 return "I40E_ERR_MAC_TYPE";
161 case I40E_ERR_UNKNOWN_PHY:
162 return "I40E_ERR_UNKNOWN_PHY";
163 case I40E_ERR_LINK_SETUP:
164 return "I40E_ERR_LINK_SETUP";
165 case I40E_ERR_ADAPTER_STOPPED:
166 return "I40E_ERR_ADAPTER_STOPPED";
167 case I40E_ERR_INVALID_MAC_ADDR:
168 return "I40E_ERR_INVALID_MAC_ADDR";
169 case I40E_ERR_DEVICE_NOT_SUPPORTED:
170 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
171 case I40E_ERR_MASTER_REQUESTS_PENDING:
172 return "I40E_ERR_MASTER_REQUESTS_PENDING";
173 case I40E_ERR_INVALID_LINK_SETTINGS:
174 return "I40E_ERR_INVALID_LINK_SETTINGS";
175 case I40E_ERR_AUTONEG_NOT_COMPLETE:
176 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
177 case I40E_ERR_RESET_FAILED:
178 return "I40E_ERR_RESET_FAILED";
179 case I40E_ERR_SWFW_SYNC:
180 return "I40E_ERR_SWFW_SYNC";
181 case I40E_ERR_NO_AVAILABLE_VSI:
182 return "I40E_ERR_NO_AVAILABLE_VSI";
183 case I40E_ERR_NO_MEMORY:
184 return "I40E_ERR_NO_MEMORY";
185 case I40E_ERR_BAD_PTR:
186 return "I40E_ERR_BAD_PTR";
187 case I40E_ERR_RING_FULL:
188 return "I40E_ERR_RING_FULL";
189 case I40E_ERR_INVALID_PD_ID:
190 return "I40E_ERR_INVALID_PD_ID";
191 case I40E_ERR_INVALID_QP_ID:
192 return "I40E_ERR_INVALID_QP_ID";
193 case I40E_ERR_INVALID_CQ_ID:
194 return "I40E_ERR_INVALID_CQ_ID";
195 case I40E_ERR_INVALID_CEQ_ID:
196 return "I40E_ERR_INVALID_CEQ_ID";
197 case I40E_ERR_INVALID_AEQ_ID:
198 return "I40E_ERR_INVALID_AEQ_ID";
199 case I40E_ERR_INVALID_SIZE:
200 return "I40E_ERR_INVALID_SIZE";
201 case I40E_ERR_INVALID_ARP_INDEX:
202 return "I40E_ERR_INVALID_ARP_INDEX";
203 case I40E_ERR_INVALID_FPM_FUNC_ID:
204 return "I40E_ERR_INVALID_FPM_FUNC_ID";
205 case I40E_ERR_QP_INVALID_MSG_SIZE:
206 return "I40E_ERR_QP_INVALID_MSG_SIZE";
207 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
208 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
209 case I40E_ERR_INVALID_FRAG_COUNT:
210 return "I40E_ERR_INVALID_FRAG_COUNT";
211 case I40E_ERR_QUEUE_EMPTY:
212 return "I40E_ERR_QUEUE_EMPTY";
213 case I40E_ERR_INVALID_ALIGNMENT:
214 return "I40E_ERR_INVALID_ALIGNMENT";
215 case I40E_ERR_FLUSHED_QUEUE:
216 return "I40E_ERR_FLUSHED_QUEUE";
217 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
218 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
219 case I40E_ERR_INVALID_IMM_DATA_SIZE:
220 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
221 case I40E_ERR_TIMEOUT:
222 return "I40E_ERR_TIMEOUT";
223 case I40E_ERR_OPCODE_MISMATCH:
224 return "I40E_ERR_OPCODE_MISMATCH";
225 case I40E_ERR_CQP_COMPL_ERROR:
226 return "I40E_ERR_CQP_COMPL_ERROR";
227 case I40E_ERR_INVALID_VF_ID:
228 return "I40E_ERR_INVALID_VF_ID";
229 case I40E_ERR_INVALID_HMCFN_ID:
230 return "I40E_ERR_INVALID_HMCFN_ID";
231 case I40E_ERR_BACKING_PAGE_ERROR:
232 return "I40E_ERR_BACKING_PAGE_ERROR";
233 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
234 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
235 case I40E_ERR_INVALID_PBLE_INDEX:
236 return "I40E_ERR_INVALID_PBLE_INDEX";
237 case I40E_ERR_INVALID_SD_INDEX:
238 return "I40E_ERR_INVALID_SD_INDEX";
239 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
240 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
241 case I40E_ERR_INVALID_SD_TYPE:
242 return "I40E_ERR_INVALID_SD_TYPE";
243 case I40E_ERR_MEMCPY_FAILED:
244 return "I40E_ERR_MEMCPY_FAILED";
245 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
246 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
247 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
248 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
249 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
250 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
251 case I40E_ERR_SRQ_ENABLED:
252 return "I40E_ERR_SRQ_ENABLED";
253 case I40E_ERR_ADMIN_QUEUE_ERROR:
254 return "I40E_ERR_ADMIN_QUEUE_ERROR";
255 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
256 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
257 case I40E_ERR_BUF_TOO_SHORT:
258 return "I40E_ERR_BUF_TOO_SHORT";
259 case I40E_ERR_ADMIN_QUEUE_FULL:
260 return "I40E_ERR_ADMIN_QUEUE_FULL";
261 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
262 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
263 case I40E_ERR_BAD_IWARP_CQE:
264 return "I40E_ERR_BAD_IWARP_CQE";
265 case I40E_ERR_NVM_BLANK_MODE:
266 return "I40E_ERR_NVM_BLANK_MODE";
267 case I40E_ERR_NOT_IMPLEMENTED:
268 return "I40E_ERR_NOT_IMPLEMENTED";
269 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
270 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
271 case I40E_ERR_DIAG_TEST_FAILED:
272 return "I40E_ERR_DIAG_TEST_FAILED";
273 case I40E_ERR_NOT_READY:
274 return "I40E_ERR_NOT_READY";
275 case I40E_NOT_SUPPORTED:
276 return "I40E_NOT_SUPPORTED";
277 case I40E_ERR_FIRMWARE_API_VERSION:
278 return "I40E_ERR_FIRMWARE_API_VERSION";
279 }
280
281 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
282 return hw->err_str;
283}
284
56a62fc8
JB		 285/**
286 * i40e_debug_aq
287 * @hw: debug mask related to admin queue
98d44381
JK		 288 * @mask: debug mask
289 * @desc: pointer to admin queue descriptor
56a62fc8 290 * @buffer: pointer to command buffer
f905dd62 291 * @buf_len: max length of buffer
56a62fc8
JB		 292 *
293 * Dumps debug log about adminq command with descriptor contents.
294 **/
295void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
f905dd62 296 void *buffer, u16 buf_len)
56a62fc8
JB		 297{
298 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
cd956722 299 u16 len;
37a2973a
SN		 300 u8 *buf = (u8 *)buffer;
301 u16 i = 0;
56a62fc8
JB		 302
303 if ((!(mask & hw->debug_mask)) || (desc == NULL))
304 return;
305
cd956722
HS		 306 len = le16_to_cpu(aq_desc->datalen);
307
56a62fc8
JB		 308 i40e_debug(hw, mask,
309 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
f1abd7db
PSJ		 310 le16_to_cpu(aq_desc->opcode),
311 le16_to_cpu(aq_desc->flags),
312 le16_to_cpu(aq_desc->datalen),
313 le16_to_cpu(aq_desc->retval));
56a62fc8 314 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 315 le32_to_cpu(aq_desc->cookie_high),
316 le32_to_cpu(aq_desc->cookie_low));
56a62fc8 317 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 318 le32_to_cpu(aq_desc->params.internal.param0),
319 le32_to_cpu(aq_desc->params.internal.param1));
56a62fc8 320 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
f1abd7db
PSJ		 321 le32_to_cpu(aq_desc->params.external.addr_high),
322 le32_to_cpu(aq_desc->params.external.addr_low));
56a62fc8
JB		 323
324 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
56a62fc8 325 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
f905dd62
SN		 326 if (buf_len < len)
327 len = buf_len;
37a2973a
SN		 328 /* write the full 16-byte chunks */
329 for (i = 0; i < (len - 16); i += 16)
a3524e95 330 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
37a2973a 331 /* write whatever's left over without overrunning the buffer */
a3524e95
AS		 332 if (i < len)
333 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
334 i, len - i, buf + i);
56a62fc8
JB		 335 }
336}
337
e1860d8f
ASJ		 338/**
339 * i40e_check_asq_alive
340 * @hw: pointer to the hw struct
341 *
342 * Returns true if Queue is enabled else false.
343 **/
344bool i40e_check_asq_alive(struct i40e_hw *hw)
345{
8b833b4f
KS		 346 if (hw->aq.asq.len)
347 return !!(rd32(hw, hw->aq.asq.len) &
348 I40E_PF_ATQLEN_ATQENABLE_MASK);
349 else
350 return false;
e1860d8f
ASJ		 351}
352
353/**
354 * i40e_aq_queue_shutdown
355 * @hw: pointer to the hw struct
356 * @unloading: is the driver unloading itself
357 *
358 * Tell the Firmware that we're shutting down the AdminQ and whether
359 * or not the driver is unloading as well.
360 **/
361i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
362 bool unloading)
363{
364 struct i40e_aq_desc desc;
365 struct i40e_aqc_queue_shutdown *cmd =
366 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
367 i40e_status status;
368
369 i40e_fill_default_direct_cmd_desc(&desc,
370 i40e_aqc_opc_queue_shutdown);
371
372 if (unloading)
373 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
374 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
375
376 return status;
377}
378
e50c8d6d
ASJ		 379/**
380 * i40e_aq_get_set_rss_lut
381 * @hw: pointer to the hardware structure
382 * @vsi_id: vsi fw index
383 * @pf_lut: for PF table set true, for VSI table set false
384 * @lut: pointer to the lut buffer provided by the caller
385 * @lut_size: size of the lut buffer
386 * @set: set true to set the table, false to get the table
387 *
388 * Internal function to get or set RSS look up table
389 **/
390static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
391 u16 vsi_id, bool pf_lut,
392 u8 *lut, u16 lut_size,
393 bool set)
394{
395 i40e_status status;
396 struct i40e_aq_desc desc;
397 struct i40e_aqc_get_set_rss_lut *cmd_resp =
398 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
399
400 if (set)
401 i40e_fill_default_direct_cmd_desc(&desc,
402 i40e_aqc_opc_set_rss_lut);
403 else
404 i40e_fill_default_direct_cmd_desc(&desc,
405 i40e_aqc_opc_get_rss_lut);
406
407 /* Indirect command */
408 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
409 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
410
411 cmd_resp->vsi_id =
412 cpu_to_le16((u16)((vsi_id <<
413 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
414 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
415 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
416
417 if (pf_lut)
418 cmd_resp->flags |= cpu_to_le16((u16)
419 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
421 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
422 else
423 cmd_resp->flags |= cpu_to_le16((u16)
424 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
425 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
426 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
427
e50c8d6d
ASJ		 428 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
429
430 return status;
431}
432
433/**
434 * i40e_aq_get_rss_lut
435 * @hw: pointer to the hardware structure
436 * @vsi_id: vsi fw index
437 * @pf_lut: for PF table set true, for VSI table set false
438 * @lut: pointer to the lut buffer provided by the caller
439 * @lut_size: size of the lut buffer
440 *
441 * get the RSS lookup table, PF or VSI type
442 **/
443i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
444 bool pf_lut, u8 *lut, u16 lut_size)
445{
446 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
447 false);
448}
449
450/**
451 * i40e_aq_set_rss_lut
452 * @hw: pointer to the hardware structure
453 * @vsi_id: vsi fw index
454 * @pf_lut: for PF table set true, for VSI table set false
455 * @lut: pointer to the lut buffer provided by the caller
456 * @lut_size: size of the lut buffer
457 *
458 * set the RSS lookup table, PF or VSI type
459 **/
460i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
461 bool pf_lut, u8 *lut, u16 lut_size)
462{
463 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
464}
465
466/**
467 * i40e_aq_get_set_rss_key
468 * @hw: pointer to the hw struct
469 * @vsi_id: vsi fw index
470 * @key: pointer to key info struct
471 * @set: set true to set the key, false to get the key
472 *
473 * get the RSS key per VSI
474 **/
475static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
476 u16 vsi_id,
477 struct i40e_aqc_get_set_rss_key_data *key,
478 bool set)
479{
480 i40e_status status;
481 struct i40e_aq_desc desc;
482 struct i40e_aqc_get_set_rss_key *cmd_resp =
483 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
484 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
485
486 if (set)
487 i40e_fill_default_direct_cmd_desc(&desc,
488 i40e_aqc_opc_set_rss_key);
489 else
490 i40e_fill_default_direct_cmd_desc(&desc,
491 i40e_aqc_opc_get_rss_key);
492
493 /* Indirect command */
494 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
495 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
496
497 cmd_resp->vsi_id =
498 cpu_to_le16((u16)((vsi_id <<
499 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
500 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
501 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
e50c8d6d
ASJ		 502
503 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
504
505 return status;
506}
507
508/**
509 * i40e_aq_get_rss_key
510 * @hw: pointer to the hw struct
511 * @vsi_id: vsi fw index
512 * @key: pointer to key info struct
513 *
514 **/
515i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
516 u16 vsi_id,
517 struct i40e_aqc_get_set_rss_key_data *key)
518{
519 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
520}
521
522/**
523 * i40e_aq_set_rss_key
524 * @hw: pointer to the hw struct
525 * @vsi_id: vsi fw index
526 * @key: pointer to key info struct
527 *
528 * set the RSS key per VSI
529 **/
530i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
531 u16 vsi_id,
532 struct i40e_aqc_get_set_rss_key_data *key)
533{
534 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
535}
536
206812b5
JB		 537/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
538 * hardware to a bit-field that can be used by SW to more easily determine the
539 * packet type.
540 *
541 * Macros are used to shorten the table lines and make this table human
542 * readable.
543 *
544 * We store the PTYPE in the top byte of the bit field - this is just so that
545 * we can check that the table doesn't have a row missing, as the index into
546 * the table should be the PTYPE.
547 *
548 * Typical work flow:
549 *
550 * IF NOT i40e_ptype_lookup[ptype].known
551 * THEN
552 * Packet is unknown
553 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
554 * Use the rest of the fields to look at the tunnels, inner protocols, etc
555 * ELSE
556 * Use the enum i40e_rx_l2_ptype to decode the packet type
557 * ENDIF
558 */
559
560/* macro to make the table lines short */
561#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
562 { PTYPE, \
563 1, \
564 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
565 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
566 I40E_RX_PTYPE_##OUTER_FRAG, \
567 I40E_RX_PTYPE_TUNNEL_##T, \
568 I40E_RX_PTYPE_TUNNEL_END_##TE, \
569 I40E_RX_PTYPE_##TEF, \
570 I40E_RX_PTYPE_INNER_PROT_##I, \
571 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
572
573#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
574 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
575
576/* shorter macros makes the table fit but are terse */
577#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
578#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
579#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
580
581/* Lookup table mapping the HW PTYPE to the bit field for decoding */
582struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
583 /* L2 Packet types */
584 I40E_PTT_UNUSED_ENTRY(0),
585 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
586 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
587 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
588 I40E_PTT_UNUSED_ENTRY(4),
589 I40E_PTT_UNUSED_ENTRY(5),
590 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
592 I40E_PTT_UNUSED_ENTRY(8),
593 I40E_PTT_UNUSED_ENTRY(9),
594 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
595 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
596 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
606
607 /* Non Tunneled IPv4 */
608 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
609 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
610 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
611 I40E_PTT_UNUSED_ENTRY(25),
612 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
613 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
614 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
615
616 /* IPv4 --> IPv4 */
617 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
618 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
619 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
620 I40E_PTT_UNUSED_ENTRY(32),
621 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
622 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
623 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
624
625 /* IPv4 --> IPv6 */
626 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
627 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
628 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
629 I40E_PTT_UNUSED_ENTRY(39),
630 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
631 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
632 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
633
634 /* IPv4 --> GRE/NAT */
635 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
636
637 /* IPv4 --> GRE/NAT --> IPv4 */
638 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
639 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
640 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
641 I40E_PTT_UNUSED_ENTRY(47),
642 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
643 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
644 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
645
646 /* IPv4 --> GRE/NAT --> IPv6 */
647 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
648 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
649 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
650 I40E_PTT_UNUSED_ENTRY(54),
651 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
652 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
653 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
654
655 /* IPv4 --> GRE/NAT --> MAC */
656 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
657
658 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
659 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
660 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
661 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
662 I40E_PTT_UNUSED_ENTRY(62),
663 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
664 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
665 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
666
667 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
668 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
669 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
670 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
671 I40E_PTT_UNUSED_ENTRY(69),
672 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
673 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
674 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
675
676 /* IPv4 --> GRE/NAT --> MAC/VLAN */
677 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
678
679 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
680 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
681 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
682 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
683 I40E_PTT_UNUSED_ENTRY(77),
684 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
685 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
686 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
687
688 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
689 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
690 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
691 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
692 I40E_PTT_UNUSED_ENTRY(84),
693 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
694 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
695 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
696
697 /* Non Tunneled IPv6 */
698 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
699 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
73df8c9e 700 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
206812b5
JB		 701 I40E_PTT_UNUSED_ENTRY(91),
702 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
703 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
704 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
705
706 /* IPv6 --> IPv4 */
707 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
708 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
709 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
710 I40E_PTT_UNUSED_ENTRY(98),
711 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
712 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
713 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
714
715 /* IPv6 --> IPv6 */
716 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
717 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
718 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
719 I40E_PTT_UNUSED_ENTRY(105),
720 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
721 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
722 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
723
724 /* IPv6 --> GRE/NAT */
725 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
726
727 /* IPv6 --> GRE/NAT -> IPv4 */
728 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
729 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
730 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
731 I40E_PTT_UNUSED_ENTRY(113),
732 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
733 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
734 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
735
736 /* IPv6 --> GRE/NAT -> IPv6 */
737 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
738 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
739 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
740 I40E_PTT_UNUSED_ENTRY(120),
741 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
742 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
743 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
744
745 /* IPv6 --> GRE/NAT -> MAC */
746 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
747
748 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
749 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
750 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
751 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
752 I40E_PTT_UNUSED_ENTRY(128),
753 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
754 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
755 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
756
757 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
758 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
759 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
760 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
761 I40E_PTT_UNUSED_ENTRY(135),
762 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
763 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
764 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
765
766 /* IPv6 --> GRE/NAT -> MAC/VLAN */
767 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
768
769 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
770 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
771 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
772 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
773 I40E_PTT_UNUSED_ENTRY(143),
774 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
775 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
776 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
777
778 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
779 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
780 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
781 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
782 I40E_PTT_UNUSED_ENTRY(150),
783 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
784 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
785 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
786
787 /* unused entries */
788 I40E_PTT_UNUSED_ENTRY(154),
789 I40E_PTT_UNUSED_ENTRY(155),
790 I40E_PTT_UNUSED_ENTRY(156),
791 I40E_PTT_UNUSED_ENTRY(157),
792 I40E_PTT_UNUSED_ENTRY(158),
793 I40E_PTT_UNUSED_ENTRY(159),
794
795 I40E_PTT_UNUSED_ENTRY(160),
796 I40E_PTT_UNUSED_ENTRY(161),
797 I40E_PTT_UNUSED_ENTRY(162),
798 I40E_PTT_UNUSED_ENTRY(163),
799 I40E_PTT_UNUSED_ENTRY(164),
800 I40E_PTT_UNUSED_ENTRY(165),
801 I40E_PTT_UNUSED_ENTRY(166),
802 I40E_PTT_UNUSED_ENTRY(167),
803 I40E_PTT_UNUSED_ENTRY(168),
804 I40E_PTT_UNUSED_ENTRY(169),
805
806 I40E_PTT_UNUSED_ENTRY(170),
807 I40E_PTT_UNUSED_ENTRY(171),
808 I40E_PTT_UNUSED_ENTRY(172),
809 I40E_PTT_UNUSED_ENTRY(173),
810 I40E_PTT_UNUSED_ENTRY(174),
811 I40E_PTT_UNUSED_ENTRY(175),
812 I40E_PTT_UNUSED_ENTRY(176),
813 I40E_PTT_UNUSED_ENTRY(177),
814 I40E_PTT_UNUSED_ENTRY(178),
815 I40E_PTT_UNUSED_ENTRY(179),
816
817 I40E_PTT_UNUSED_ENTRY(180),
818 I40E_PTT_UNUSED_ENTRY(181),
819 I40E_PTT_UNUSED_ENTRY(182),
820 I40E_PTT_UNUSED_ENTRY(183),
821 I40E_PTT_UNUSED_ENTRY(184),
822 I40E_PTT_UNUSED_ENTRY(185),
823 I40E_PTT_UNUSED_ENTRY(186),
824 I40E_PTT_UNUSED_ENTRY(187),
825 I40E_PTT_UNUSED_ENTRY(188),
826 I40E_PTT_UNUSED_ENTRY(189),
827
828 I40E_PTT_UNUSED_ENTRY(190),
829 I40E_PTT_UNUSED_ENTRY(191),
830 I40E_PTT_UNUSED_ENTRY(192),
831 I40E_PTT_UNUSED_ENTRY(193),
832 I40E_PTT_UNUSED_ENTRY(194),
833 I40E_PTT_UNUSED_ENTRY(195),
834 I40E_PTT_UNUSED_ENTRY(196),
835 I40E_PTT_UNUSED_ENTRY(197),
836 I40E_PTT_UNUSED_ENTRY(198),
837 I40E_PTT_UNUSED_ENTRY(199),
838
839 I40E_PTT_UNUSED_ENTRY(200),
840 I40E_PTT_UNUSED_ENTRY(201),
841 I40E_PTT_UNUSED_ENTRY(202),
842 I40E_PTT_UNUSED_ENTRY(203),
843 I40E_PTT_UNUSED_ENTRY(204),
844 I40E_PTT_UNUSED_ENTRY(205),
845 I40E_PTT_UNUSED_ENTRY(206),
846 I40E_PTT_UNUSED_ENTRY(207),
847 I40E_PTT_UNUSED_ENTRY(208),
848 I40E_PTT_UNUSED_ENTRY(209),
849
850 I40E_PTT_UNUSED_ENTRY(210),
851 I40E_PTT_UNUSED_ENTRY(211),
852 I40E_PTT_UNUSED_ENTRY(212),
853 I40E_PTT_UNUSED_ENTRY(213),
854 I40E_PTT_UNUSED_ENTRY(214),
855 I40E_PTT_UNUSED_ENTRY(215),
856 I40E_PTT_UNUSED_ENTRY(216),
857 I40E_PTT_UNUSED_ENTRY(217),
858 I40E_PTT_UNUSED_ENTRY(218),
859 I40E_PTT_UNUSED_ENTRY(219),
860
861 I40E_PTT_UNUSED_ENTRY(220),
862 I40E_PTT_UNUSED_ENTRY(221),
863 I40E_PTT_UNUSED_ENTRY(222),
864 I40E_PTT_UNUSED_ENTRY(223),
865 I40E_PTT_UNUSED_ENTRY(224),
866 I40E_PTT_UNUSED_ENTRY(225),
867 I40E_PTT_UNUSED_ENTRY(226),
868 I40E_PTT_UNUSED_ENTRY(227),
869 I40E_PTT_UNUSED_ENTRY(228),
870 I40E_PTT_UNUSED_ENTRY(229),
871
872 I40E_PTT_UNUSED_ENTRY(230),
873 I40E_PTT_UNUSED_ENTRY(231),
874 I40E_PTT_UNUSED_ENTRY(232),
875 I40E_PTT_UNUSED_ENTRY(233),
876 I40E_PTT_UNUSED_ENTRY(234),
877 I40E_PTT_UNUSED_ENTRY(235),
878 I40E_PTT_UNUSED_ENTRY(236),
879 I40E_PTT_UNUSED_ENTRY(237),
880 I40E_PTT_UNUSED_ENTRY(238),
881 I40E_PTT_UNUSED_ENTRY(239),
882
883 I40E_PTT_UNUSED_ENTRY(240),
884 I40E_PTT_UNUSED_ENTRY(241),
885 I40E_PTT_UNUSED_ENTRY(242),
886 I40E_PTT_UNUSED_ENTRY(243),
887 I40E_PTT_UNUSED_ENTRY(244),
888 I40E_PTT_UNUSED_ENTRY(245),
889 I40E_PTT_UNUSED_ENTRY(246),
890 I40E_PTT_UNUSED_ENTRY(247),
891 I40E_PTT_UNUSED_ENTRY(248),
892 I40E_PTT_UNUSED_ENTRY(249),
893
894 I40E_PTT_UNUSED_ENTRY(250),
895 I40E_PTT_UNUSED_ENTRY(251),
896 I40E_PTT_UNUSED_ENTRY(252),
897 I40E_PTT_UNUSED_ENTRY(253),
898 I40E_PTT_UNUSED_ENTRY(254),
899 I40E_PTT_UNUSED_ENTRY(255)
900};
901
56a62fc8
JB		 902/**
903 * i40e_init_shared_code - Initialize the shared code
904 * @hw: pointer to hardware structure
905 *
906 * This assigns the MAC type and PHY code and inits the NVM.
907 * Does not touch the hardware. This function must be called prior to any
908 * other function in the shared code. The i40e_hw structure should be
909 * memset to 0 prior to calling this function. The following fields in
910 * hw structure should be filled in prior to calling this function:
911 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
912 * subsystem_vendor_id, and revision_id
913 **/
914i40e_status i40e_init_shared_code(struct i40e_hw *hw)
915{
916 i40e_status status = 0;
5fb11d76 917 u32 port, ari, func_rid;
56a62fc8 918
56a62fc8
JB		 919 i40e_set_mac_type(hw);
920
921 switch (hw->mac.type) {
922 case I40E_MAC_XL710:
87e6c1d7 923 case I40E_MAC_X722:
56a62fc8
JB		 924 break;
925 default:
926 return I40E_ERR_DEVICE_NOT_SUPPORTED;
56a62fc8
JB		 927 }
928
af89d26c
SN		 929 hw->phy.get_link_info = true;
930
5fb11d76
SN		 931 /* Determine port number and PF number*/
932 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
933 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
934 hw->port = (u8)port;
935 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
936 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
937 func_rid = rd32(hw, I40E_PF_FUNC_RID);
938 if (ari)
939 hw->pf_id = (u8)(func_rid & 0xff);
5f9116ac 940 else
5fb11d76 941 hw->pf_id = (u8)(func_rid & 0x7);
5f9116ac 942
07f89be8
AS		 943 if (hw->mac.type == I40E_MAC_X722)
944 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
945
56a62fc8
JB		 946 status = i40e_init_nvm(hw);
947 return status;
948}
949
950/**
951 * i40e_aq_mac_address_read - Retrieve the MAC addresses
952 * @hw: pointer to the hw struct
953 * @flags: a return indicator of what addresses were added to the addr store
954 * @addrs: the requestor's mac addr store
955 * @cmd_details: pointer to command details structure or NULL
956 **/
957static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
958 u16 *flags,
959 struct i40e_aqc_mac_address_read_data *addrs,
960 struct i40e_asq_cmd_details *cmd_details)
961{
962 struct i40e_aq_desc desc;
963 struct i40e_aqc_mac_address_read *cmd_data =
964 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
965 i40e_status status;
966
967 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
968 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
969
970 status = i40e_asq_send_command(hw, &desc, addrs,
971 sizeof(*addrs), cmd_details);
972 *flags = le16_to_cpu(cmd_data->command_flags);
973
974 return status;
975}
976
977/**
978 * i40e_aq_mac_address_write - Change the MAC addresses
979 * @hw: pointer to the hw struct
980 * @flags: indicates which MAC to be written
981 * @mac_addr: address to write
982 * @cmd_details: pointer to command details structure or NULL
983 **/
984i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
985 u16 flags, u8 *mac_addr,
986 struct i40e_asq_cmd_details *cmd_details)
987{
988 struct i40e_aq_desc desc;
989 struct i40e_aqc_mac_address_write *cmd_data =
990 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
991 i40e_status status;
992
993 i40e_fill_default_direct_cmd_desc(&desc,
994 i40e_aqc_opc_mac_address_write);
995 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 996 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
997 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
998 ((u32)mac_addr[3] << 16) |
999 ((u32)mac_addr[4] << 8) |
1000 mac_addr[5]);
56a62fc8
JB		 1001
1002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1003
1004 return status;
1005}
1006
1007/**
1008 * i40e_get_mac_addr - get MAC address
1009 * @hw: pointer to the HW structure
1010 * @mac_addr: pointer to MAC address
1011 *
1012 * Reads the adapter's MAC address from register
1013 **/
1014i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1015{
1016 struct i40e_aqc_mac_address_read_data addrs;
1017 i40e_status status;
1018 u16 flags = 0;
1019
1020 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1021
1022 if (flags & I40E_AQC_LAN_ADDR_VALID)
6995b36c 1023 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
56a62fc8
JB		 1024
1025 return status;
1026}
1027
1f224ad2
NP		 1028/**
1029 * i40e_get_port_mac_addr - get Port MAC address
1030 * @hw: pointer to the HW structure
1031 * @mac_addr: pointer to Port MAC address
1032 *
1033 * Reads the adapter's Port MAC address
1034 **/
1035i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1036{
1037 struct i40e_aqc_mac_address_read_data addrs;
1038 i40e_status status;
1039 u16 flags = 0;
1040
1041 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1042 if (status)
1043 return status;
1044
1045 if (flags & I40E_AQC_PORT_ADDR_VALID)
6995b36c 1046 ether_addr_copy(mac_addr, addrs.port_mac);
1f224ad2
NP		 1047 else
1048 status = I40E_ERR_INVALID_MAC_ADDR;
1049
1050 return status;
1051}
1052
351499ab
MJ		 1053/**
1054 * i40e_pre_tx_queue_cfg - pre tx queue configure
1055 * @hw: pointer to the HW structure
b40c82e6 1056 * @queue: target PF queue index
351499ab
MJ		 1057 * @enable: state change request
1058 *
1059 * Handles hw requirement to indicate intention to enable
1060 * or disable target queue.
1061 **/
1062void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1063{
dfb699f9 1064 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
351499ab 1065 u32 reg_block = 0;
dfb699f9 1066 u32 reg_val;
351499ab 1067
24a768cf 1068 if (abs_queue_idx >= 128) {
351499ab 1069 reg_block = abs_queue_idx / 128;
24a768cf
CP		 1070 abs_queue_idx %= 128;
1071 }
351499ab
MJ		 1072
1073 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1074 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1075 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1076
1077 if (enable)
1078 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1079 else
1080 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1081
1082 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1083}
38e00438
VD		 1084#ifdef I40E_FCOE
1085
1086/**
1087 * i40e_get_san_mac_addr - get SAN MAC address
1088 * @hw: pointer to the HW structure
1089 * @mac_addr: pointer to SAN MAC address
1090 *
1091 * Reads the adapter's SAN MAC address from NVM
1092 **/
1093i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1094{
1095 struct i40e_aqc_mac_address_read_data addrs;
1096 i40e_status status;
1097 u16 flags = 0;
1098
1099 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1100 if (status)
1101 return status;
1102
1103 if (flags & I40E_AQC_SAN_ADDR_VALID)
6995b36c 1104 ether_addr_copy(mac_addr, addrs.pf_san_mac);
38e00438
VD		 1105 else
1106 status = I40E_ERR_INVALID_MAC_ADDR;
1107
1108 return status;
1109}
1110#endif
351499ab 1111
18f680c6
KK		 1112/**
1113 * i40e_read_pba_string - Reads part number string from EEPROM
1114 * @hw: pointer to hardware structure
1115 * @pba_num: stores the part number string from the EEPROM
1116 * @pba_num_size: part number string buffer length
1117 *
1118 * Reads the part number string from the EEPROM.
1119 **/
1120i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1121 u32 pba_num_size)
1122{
1123 i40e_status status = 0;
1124 u16 pba_word = 0;
1125 u16 pba_size = 0;
1126 u16 pba_ptr = 0;
1127 u16 i = 0;
1128
1129 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1130 if (status || (pba_word != 0xFAFA)) {
1131 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1132 return status;
1133 }
1134
1135 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1136 if (status) {
1137 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1138 return status;
1139 }
1140
1141 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1142 if (status) {
1143 hw_dbg(hw, "Failed to read PBA Block size.\n");
1144 return status;
1145 }
1146
1147 /* Subtract one to get PBA word count (PBA Size word is included in
1148 * total size)
1149 */
1150 pba_size--;
1151 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1152 hw_dbg(hw, "Buffer to small for PBA data.\n");
1153 return I40E_ERR_PARAM;
1154 }
1155
1156 for (i = 0; i < pba_size; i++) {
1157 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1158 if (status) {
1159 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1160 return status;
1161 }
1162
1163 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1164 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1165 }
1166 pba_num[(pba_size * 2)] = '\0';
1167
1168 return status;
1169}
1170
be405eb0
JB		 1171/**
1172 * i40e_get_media_type - Gets media type
1173 * @hw: pointer to the hardware structure
1174 **/
1175static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1176{
1177 enum i40e_media_type media;
1178
1179 switch (hw->phy.link_info.phy_type) {
1180 case I40E_PHY_TYPE_10GBASE_SR:
1181 case I40E_PHY_TYPE_10GBASE_LR:
124ed15b
CS		 1182 case I40E_PHY_TYPE_1000BASE_SX:
1183 case I40E_PHY_TYPE_1000BASE_LX:
be405eb0
JB		 1184 case I40E_PHY_TYPE_40GBASE_SR4:
1185 case I40E_PHY_TYPE_40GBASE_LR4:
1186 media = I40E_MEDIA_TYPE_FIBER;
1187 break;
1188 case I40E_PHY_TYPE_100BASE_TX:
1189 case I40E_PHY_TYPE_1000BASE_T:
1190 case I40E_PHY_TYPE_10GBASE_T:
1191 media = I40E_MEDIA_TYPE_BASET;
1192 break;
1193 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1194 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1195 case I40E_PHY_TYPE_10GBASE_CR1:
1196 case I40E_PHY_TYPE_40GBASE_CR4:
1197 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
180204c7
CS		 1198 case I40E_PHY_TYPE_40GBASE_AOC:
1199 case I40E_PHY_TYPE_10GBASE_AOC:
be405eb0
JB		 1200 media = I40E_MEDIA_TYPE_DA;
1201 break;
1202 case I40E_PHY_TYPE_1000BASE_KX:
1203 case I40E_PHY_TYPE_10GBASE_KX4:
1204 case I40E_PHY_TYPE_10GBASE_KR:
1205 case I40E_PHY_TYPE_40GBASE_KR4:
ae24b409 1206 case I40E_PHY_TYPE_20GBASE_KR2:
be405eb0
JB		 1207 media = I40E_MEDIA_TYPE_BACKPLANE;
1208 break;
1209 case I40E_PHY_TYPE_SGMII:
1210 case I40E_PHY_TYPE_XAUI:
1211 case I40E_PHY_TYPE_XFI:
1212 case I40E_PHY_TYPE_XLAUI:
1213 case I40E_PHY_TYPE_XLPPI:
1214 default:
1215 media = I40E_MEDIA_TYPE_UNKNOWN;
1216 break;
1217 }
1218
1219 return media;
1220}
1221
7134f9ce 1222#define I40E_PF_RESET_WAIT_COUNT_A0 200
8af580df 1223#define I40E_PF_RESET_WAIT_COUNT 200
56a62fc8
JB		 1224/**
1225 * i40e_pf_reset - Reset the PF
1226 * @hw: pointer to the hardware structure
1227 *
1228 * Assuming someone else has triggered a global reset,
1229 * assure the global reset is complete and then reset the PF
1230 **/
1231i40e_status i40e_pf_reset(struct i40e_hw *hw)
1232{
7134f9ce 1233 u32 cnt = 0;
42794bd8 1234 u32 cnt1 = 0;
56a62fc8
JB		 1235 u32 reg = 0;
1236 u32 grst_del;
1237
1238 /* Poll for Global Reset steady state in case of recent GRST.
1239 * The grst delay value is in 100ms units, and we'll wait a
1240 * couple counts longer to be sure we don't just miss the end.
1241 */
de78fc5a
SN		 1242 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1243 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1244 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
4d7cec07
KS		 1245
1246 /* It can take upto 15 secs for GRST steady state.
1247 * Bump it to 16 secs max to be safe.
1248 */
1249 grst_del = grst_del * 20;
1250
1251 for (cnt = 0; cnt < grst_del; cnt++) {
56a62fc8
JB		 1252 reg = rd32(hw, I40E_GLGEN_RSTAT);
1253 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1254 break;
1255 msleep(100);
1256 }
1257 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1258 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 1259 return I40E_ERR_RESET_FAILED;
1260 }
1261
1262 /* Now Wait for the FW to be ready */
1263 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1264 reg = rd32(hw, I40E_GLNVM_ULD);
1265 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1267 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1268 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1269 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1270 break;
1271 }
1272 usleep_range(10000, 20000);
1273 }
1274 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1275 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1276 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1277 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 1278 return I40E_ERR_RESET_FAILED;
1279 }
1280
56a62fc8
JB		 1281 /* If there was a Global Reset in progress when we got here,
1282 * we don't need to do the PF Reset
1283 */
7134f9ce
JB		 1284 if (!cnt) {
1285 if (hw->revision_id == 0)
1286 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1287 else
1288 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 1289 reg = rd32(hw, I40E_PFGEN_CTRL);
1290 wr32(hw, I40E_PFGEN_CTRL,
1291 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 1292 for (; cnt; cnt--) {
56a62fc8
JB		 1293 reg = rd32(hw, I40E_PFGEN_CTRL);
1294 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1295 break;
1296 usleep_range(1000, 2000);
1297 }
1298 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1299 hw_dbg(hw, "PF reset polling failed to complete.\n");
1300 return I40E_ERR_RESET_FAILED;
1301 }
1302 }
1303
1304 i40e_clear_pxe_mode(hw);
922680b9 1305
56a62fc8
JB		 1306 return 0;
1307}
1308
838d41d9
SN		 1309/**
1310 * i40e_clear_hw - clear out any left over hw state
1311 * @hw: pointer to the hw struct
1312 *
1313 * Clear queues and interrupts, typically called at init time,
1314 * but after the capabilities have been found so we know how many
1315 * queues and msix vectors have been allocated.
1316 **/
1317void i40e_clear_hw(struct i40e_hw *hw)
1318{
1319 u32 num_queues, base_queue;
1320 u32 num_pf_int;
1321 u32 num_vf_int;
1322 u32 num_vfs;
1323 u32 i, j;
1324 u32 val;
1325 u32 eol = 0x7ff;
1326
b40c82e6 1327 /* get number of interrupts, queues, and VFs */
838d41d9
SN		 1328 val = rd32(hw, I40E_GLPCI_CNF2);
1329 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1330 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1331 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1332 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1333
272cdaf2 1334 val = rd32(hw, I40E_PFLAN_QALLOC);
838d41d9
SN		 1335 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1336 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1337 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1338 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1339 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1340 num_queues = (j - base_queue) + 1;
1341 else
1342 num_queues = 0;
1343
1344 val = rd32(hw, I40E_PF_VT_PFALLOC);
1345 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1346 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1347 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1348 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1349 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1350 num_vfs = (j - i) + 1;
1351 else
1352 num_vfs = 0;
1353
1354 /* stop all the interrupts */
1355 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1356 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1357 for (i = 0; i < num_pf_int - 2; i++)
1358 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1359
1360 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1361 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1362 wr32(hw, I40E_PFINT_LNKLST0, val);
1363 for (i = 0; i < num_pf_int - 2; i++)
1364 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1365 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1366 for (i = 0; i < num_vfs; i++)
1367 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1368 for (i = 0; i < num_vf_int - 2; i++)
1369 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1370
1371 /* warn the HW of the coming Tx disables */
1372 for (i = 0; i < num_queues; i++) {
1373 u32 abs_queue_idx = base_queue + i;
1374 u32 reg_block = 0;
1375
1376 if (abs_queue_idx >= 128) {
1377 reg_block = abs_queue_idx / 128;
1378 abs_queue_idx %= 128;
1379 }
1380
1381 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1382 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1383 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1384 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1385
1386 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1387 }
1388 udelay(400);
1389
1390 /* stop all the queues */
1391 for (i = 0; i < num_queues; i++) {
1392 wr32(hw, I40E_QINT_TQCTL(i), 0);
1393 wr32(hw, I40E_QTX_ENA(i), 0);
1394 wr32(hw, I40E_QINT_RQCTL(i), 0);
1395 wr32(hw, I40E_QRX_ENA(i), 0);
1396 }
1397
1398 /* short wait for all queue disables to settle */
1399 udelay(50);
1400}
1401
56a62fc8
JB		 1402/**
1403 * i40e_clear_pxe_mode - clear pxe operations mode
1404 * @hw: pointer to the hw struct
1405 *
1406 * Make sure all PXE mode settings are cleared, including things
1407 * like descriptor fetch/write-back mode.
1408 **/
1409void i40e_clear_pxe_mode(struct i40e_hw *hw)
1410{
1411 u32 reg;
1412
c9b9b0ae
SN		 1413 if (i40e_check_asq_alive(hw))
1414 i40e_aq_clear_pxe_mode(hw, NULL);
1415
56a62fc8
JB		 1416 /* Clear single descriptor fetch/write-back mode */
1417 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 1418
1419 if (hw->revision_id == 0) {
1420 /* As a work around clear PXE_MODE instead of setting it */
1421 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1422 } else {
1423 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1424 }
56a62fc8
JB		 1425}
1426
0556a9e3
JB		 1427/**
1428 * i40e_led_is_mine - helper to find matching led
1429 * @hw: pointer to the hw struct
1430 * @idx: index into GPIO registers
1431 *
1432 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1433 */
1434static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1435{
1436 u32 gpio_val = 0;
1437 u32 port;
1438
1439 if (!hw->func_caps.led[idx])
1440 return 0;
1441
1442 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1443 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1444 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1445
1446 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1447 * if it is not our port then ignore
1448 */
1449 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1450 (port != hw->port))
1451 return 0;
1452
1453 return gpio_val;
1454}
1455
b84d5cd8
MJ		 1456#define I40E_COMBINED_ACTIVITY 0xA
1457#define I40E_FILTER_ACTIVITY 0xE
0556a9e3 1458#define I40E_LINK_ACTIVITY 0xC
b84d5cd8
MJ		 1459#define I40E_MAC_ACTIVITY 0xD
1460#define I40E_LED0 22
0556a9e3 1461
56a62fc8
JB		 1462/**
1463 * i40e_led_get - return current on/off mode
1464 * @hw: pointer to the hw struct
1465 *
1466 * The value returned is the 'mode' field as defined in the
1467 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1468 * values are variations of possible behaviors relating to
1469 * blink, link, and wire.
1470 **/
1471u32 i40e_led_get(struct i40e_hw *hw)
1472{
b84d5cd8 1473 u32 current_mode = 0;
56a62fc8 1474 u32 mode = 0;
56a62fc8
JB		 1475 int i;
1476
0556a9e3
JB		 1477 /* as per the documentation GPIO 22-29 are the LED
1478 * GPIO pins named LED0..LED7
1479 */
1480 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1481 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1482
0556a9e3 1483 if (!gpio_val)
56a62fc8
JB		 1484 continue;
1485
b84d5cd8
MJ		 1486 /* ignore gpio LED src mode entries related to the activity
1487 * LEDs
1488 */
1489 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1490 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1491 switch (current_mode) {
1492 case I40E_COMBINED_ACTIVITY:
1493 case I40E_FILTER_ACTIVITY:
1494 case I40E_MAC_ACTIVITY:
1495 continue;
1496 default:
1497 break;
1498 }
1499
0556a9e3
JB		 1500 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1501 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 1502 break;
1503 }
1504
1505 return mode;
1506}
1507
1508/**
1509 * i40e_led_set - set new on/off mode
1510 * @hw: pointer to the hw struct
0556a9e3
JB		 1511 * @mode: 0=off, 0xf=on (else see manual for mode details)
1512 * @blink: true if the LED should blink when on, false if steady
1513 *
1514 * if this function is used to turn on the blink it should
1515 * be used to disable the blink when restoring the original state.
56a62fc8 1516 **/
0556a9e3 1517void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 1518{
b84d5cd8 1519 u32 current_mode = 0;
56a62fc8
JB		 1520 int i;
1521
0556a9e3
JB		 1522 if (mode & 0xfffffff0)
1523 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 1524
0556a9e3
JB		 1525 /* as per the documentation GPIO 22-29 are the LED
1526 * GPIO pins named LED0..LED7
1527 */
1528 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1529 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 1530
0556a9e3 1531 if (!gpio_val)
56a62fc8
JB		 1532 continue;
1533
b84d5cd8
MJ		 1534 /* ignore gpio LED src mode entries related to the activity
1535 * LEDs
1536 */
1537 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1538 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1539 switch (current_mode) {
1540 case I40E_COMBINED_ACTIVITY:
1541 case I40E_FILTER_ACTIVITY:
1542 case I40E_MAC_ACTIVITY:
1543 continue;
1544 default:
1545 break;
1546 }
1547
56a62fc8 1548 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 1549 /* this & is a bit of paranoia, but serves as a range check */
1550 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1551 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1552
1553 if (mode == I40E_LINK_ACTIVITY)
1554 blink = false;
1555
9be00d67 1556 if (blink)
41a1d04b 1557 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
9be00d67 1558 else
41a1d04b 1559 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
0556a9e3 1560
56a62fc8 1561 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 1562 break;
56a62fc8
JB		 1563 }
1564}
1565
1566/* Admin command wrappers */
56a62fc8 1567
8109e123
CS		 1568/**
1569 * i40e_aq_get_phy_capabilities
1570 * @hw: pointer to the hw struct
1571 * @abilities: structure for PHY capabilities to be filled
1572 * @qualified_modules: report Qualified Modules
1573 * @report_init: report init capabilities (active are default)
1574 * @cmd_details: pointer to command details structure or NULL
1575 *
1576 * Returns the various PHY abilities supported on the Port.
1577 **/
1578i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1579 bool qualified_modules, bool report_init,
1580 struct i40e_aq_get_phy_abilities_resp *abilities,
1581 struct i40e_asq_cmd_details *cmd_details)
1582{
1583 struct i40e_aq_desc desc;
1584 i40e_status status;
1585 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1586
1587 if (!abilities)
1588 return I40E_ERR_PARAM;
1589
1590 i40e_fill_default_direct_cmd_desc(&desc,
1591 i40e_aqc_opc_get_phy_abilities);
1592
1593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1594 if (abilities_size > I40E_AQ_LARGE_BUF)
1595 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1596
1597 if (qualified_modules)
1598 desc.params.external.param0 |=
1599 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1600
1601 if (report_init)
1602 desc.params.external.param0 |=
1603 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1604
1605 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1606 cmd_details);
1607
1608 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1609 status = I40E_ERR_UNKNOWN_PHY;
1610
3ac67d7b
KS		 1611 if (report_init)
1612 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1613
8109e123
CS		 1614 return status;
1615}
1616
c56999f9
CS		 1617/**
1618 * i40e_aq_set_phy_config
1619 * @hw: pointer to the hw struct
1620 * @config: structure with PHY configuration to be set
1621 * @cmd_details: pointer to command details structure or NULL
1622 *
1623 * Set the various PHY configuration parameters
1624 * supported on the Port.One or more of the Set PHY config parameters may be
1625 * ignored in an MFP mode as the PF may not have the privilege to set some
1626 * of the PHY Config parameters. This status will be indicated by the
1627 * command response.
1628 **/
1629enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1630 struct i40e_aq_set_phy_config *config,
1631 struct i40e_asq_cmd_details *cmd_details)
1632{
1633 struct i40e_aq_desc desc;
1634 struct i40e_aq_set_phy_config *cmd =
1635 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1636 enum i40e_status_code status;
1637
1638 if (!config)
1639 return I40E_ERR_PARAM;
1640
1641 i40e_fill_default_direct_cmd_desc(&desc,
1642 i40e_aqc_opc_set_phy_config);
1643
1644 *cmd = *config;
1645
1646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1647
1648 return status;
1649}
1650
1651/**
1652 * i40e_set_fc
1653 * @hw: pointer to the hw struct
1654 *
1655 * Set the requested flow control mode using set_phy_config.
1656 **/
1657enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1658 bool atomic_restart)
1659{
1660 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1661 struct i40e_aq_get_phy_abilities_resp abilities;
1662 struct i40e_aq_set_phy_config config;
1663 enum i40e_status_code status;
1664 u8 pause_mask = 0x0;
1665
1666 *aq_failures = 0x0;
1667
1668 switch (fc_mode) {
1669 case I40E_FC_FULL:
1670 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1671 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1672 break;
1673 case I40E_FC_RX_PAUSE:
1674 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1675 break;
1676 case I40E_FC_TX_PAUSE:
1677 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1678 break;
1679 default:
1680 break;
1681 }
1682
1683 /* Get the current phy config */
1684 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1685 NULL);
1686 if (status) {
1687 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1688 return status;
1689 }
1690
1691 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1692 /* clear the old pause settings */
1693 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1694 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1695 /* set the new abilities */
1696 config.abilities |= pause_mask;
1697 /* If the abilities have changed, then set the new config */
1698 if (config.abilities != abilities.abilities) {
1699 /* Auto restart link so settings take effect */
1700 if (atomic_restart)
1701 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1702 /* Copy over all the old settings */
1703 config.phy_type = abilities.phy_type;
1704 config.link_speed = abilities.link_speed;
1705 config.eee_capability = abilities.eee_capability;
1706 config.eeer = abilities.eeer_val;
1707 config.low_power_ctrl = abilities.d3_lpan;
1708 status = i40e_aq_set_phy_config(hw, &config, NULL);
1709
1710 if (status)
1711 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1712 }
1713 /* Update the link info */
0a862b43 1714 status = i40e_update_link_info(hw);
c56999f9
CS		 1715 if (status) {
1716 /* Wait a little bit (on 40G cards it sometimes takes a really
1717 * long time for link to come back from the atomic reset)
1718 * and try once more
1719 */
1720 msleep(1000);
0a862b43 1721 status = i40e_update_link_info(hw);
c56999f9
CS		 1722 }
1723 if (status)
1724 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1725
1726 return status;
1727}
1728
c9b9b0ae
SN		 1729/**
1730 * i40e_aq_clear_pxe_mode
1731 * @hw: pointer to the hw struct
1732 * @cmd_details: pointer to command details structure or NULL
1733 *
1734 * Tell the firmware that the driver is taking over from PXE
1735 **/
1736i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1737 struct i40e_asq_cmd_details *cmd_details)
1738{
1739 i40e_status status;
1740 struct i40e_aq_desc desc;
1741 struct i40e_aqc_clear_pxe *cmd =
1742 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1743
1744 i40e_fill_default_direct_cmd_desc(&desc,
1745 i40e_aqc_opc_clear_pxe_mode);
1746
1747 cmd->rx_cnt = 0x2;
1748
1749 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1750
1751 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1752
1753 return status;
1754}
1755
56a62fc8
JB		 1756/**
1757 * i40e_aq_set_link_restart_an
1758 * @hw: pointer to the hw struct
1ac978af 1759 * @enable_link: if true: enable link, if false: disable link
56a62fc8
JB		 1760 * @cmd_details: pointer to command details structure or NULL
1761 *
1762 * Sets up the link and restarts the Auto-Negotiation over the link.
1763 **/
1764i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1ac978af
CS		 1765 bool enable_link,
1766 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1767{
1768 struct i40e_aq_desc desc;
1769 struct i40e_aqc_set_link_restart_an *cmd =
1770 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1771 i40e_status status;
1772
1773 i40e_fill_default_direct_cmd_desc(&desc,
1774 i40e_aqc_opc_set_link_restart_an);
1775
1776 cmd->command = I40E_AQ_PHY_RESTART_AN;
1ac978af
CS		 1777 if (enable_link)
1778 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1779 else
1780 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
56a62fc8
JB		 1781
1782 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1783
1784 return status;
1785}
1786
1787/**
1788 * i40e_aq_get_link_info
1789 * @hw: pointer to the hw struct
1790 * @enable_lse: enable/disable LinkStatusEvent reporting
1791 * @link: pointer to link status structure - optional
1792 * @cmd_details: pointer to command details structure or NULL
1793 *
1794 * Returns the link status of the adapter.
1795 **/
1796i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1797 bool enable_lse, struct i40e_link_status *link,
1798 struct i40e_asq_cmd_details *cmd_details)
1799{
1800 struct i40e_aq_desc desc;
1801 struct i40e_aqc_get_link_status *resp =
1802 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1803 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1804 i40e_status status;
c56999f9 1805 bool tx_pause, rx_pause;
56a62fc8
JB		 1806 u16 command_flags;
1807
1808 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1809
1810 if (enable_lse)
1811 command_flags = I40E_AQ_LSE_ENABLE;
1812 else
1813 command_flags = I40E_AQ_LSE_DISABLE;
1814 resp->command_flags = cpu_to_le16(command_flags);
1815
1816 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1817
1818 if (status)
1819 goto aq_get_link_info_exit;
1820
1821 /* save off old link status information */
c36bd4a7 1822 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 1823
1824 /* update link status */
1825 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 1826 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 1827 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1828 hw_link_info->link_info = resp->link_info;
1829 hw_link_info->an_info = resp->an_info;
1830 hw_link_info->ext_info = resp->ext_info;
639dc377 1831 hw_link_info->loopback = resp->loopback;
6bb3f23c
NP		 1832 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1833 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1834
c56999f9
CS		 1835 /* update fc info */
1836 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1837 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1838 if (tx_pause & rx_pause)
1839 hw->fc.current_mode = I40E_FC_FULL;
1840 else if (tx_pause)
1841 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1842 else if (rx_pause)
1843 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1844 else
1845 hw->fc.current_mode = I40E_FC_NONE;
1846
6bb3f23c
NP		 1847 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1848 hw_link_info->crc_enable = true;
1849 else
1850 hw_link_info->crc_enable = false;
56a62fc8 1851
7ed35732 1852 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
56a62fc8
JB		 1853 hw_link_info->lse_enable = true;
1854 else
1855 hw_link_info->lse_enable = false;
1856
e586bb66
HT		 1857 if ((hw->mac.type == I40E_MAC_XL710) &&
1858 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
088c4ee3
CS		 1859 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1860 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1861
56a62fc8
JB		 1862 /* save link status information */
1863 if (link)
d7595a22 1864 *link = *hw_link_info;
56a62fc8
JB		 1865
1866 /* flag cleared so helper functions don't call AQ again */
1867 hw->phy.get_link_info = false;
1868
1869aq_get_link_info_exit:
1870 return status;
1871}
1872
7e2453fe
JB		 1873/**
1874 * i40e_aq_set_phy_int_mask
1875 * @hw: pointer to the hw struct
1876 * @mask: interrupt mask to be set
1877 * @cmd_details: pointer to command details structure or NULL
1878 *
1879 * Set link interrupt mask.
1880 **/
1881i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1882 u16 mask,
1883 struct i40e_asq_cmd_details *cmd_details)
1884{
1885 struct i40e_aq_desc desc;
1886 struct i40e_aqc_set_phy_int_mask *cmd =
1887 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1888 i40e_status status;
1889
1890 i40e_fill_default_direct_cmd_desc(&desc,
1891 i40e_aqc_opc_set_phy_int_mask);
1892
1893 cmd->event_mask = cpu_to_le16(mask);
1894
1895 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1896
1897 return status;
1898}
1899
31b606d0
CW		 1900/**
1901 * i40e_aq_set_phy_debug
1902 * @hw: pointer to the hw struct
1903 * @cmd_flags: debug command flags
1904 * @cmd_details: pointer to command details structure or NULL
1905 *
1906 * Reset the external PHY.
1907 **/
61829026
JB		 1908i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1909 struct i40e_asq_cmd_details *cmd_details)
31b606d0
CW		 1910{
1911 struct i40e_aq_desc desc;
1912 struct i40e_aqc_set_phy_debug *cmd =
1913 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
61829026 1914 i40e_status status;
31b606d0
CW		 1915
1916 i40e_fill_default_direct_cmd_desc(&desc,
1917 i40e_aqc_opc_set_phy_debug);
1918
1919 cmd->command_flags = cmd_flags;
1920
1921 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1922
1923 return status;
1924}
1925
56a62fc8
JB		 1926/**
1927 * i40e_aq_add_vsi
1928 * @hw: pointer to the hw struct
98d44381 1929 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1930 * @cmd_details: pointer to command details structure or NULL
1931 *
1932 * Add a VSI context to the hardware.
1933**/
1934i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1935 struct i40e_vsi_context *vsi_ctx,
1936 struct i40e_asq_cmd_details *cmd_details)
1937{
1938 struct i40e_aq_desc desc;
1939 struct i40e_aqc_add_get_update_vsi *cmd =
1940 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1941 struct i40e_aqc_add_get_update_vsi_completion *resp =
1942 (struct i40e_aqc_add_get_update_vsi_completion *)
1943 &desc.params.raw;
1944 i40e_status status;
1945
1946 i40e_fill_default_direct_cmd_desc(&desc,
1947 i40e_aqc_opc_add_vsi);
1948
1949 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1950 cmd->connection_type = vsi_ctx->connection_type;
1951 cmd->vf_id = vsi_ctx->vf_num;
1952 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1953
1954 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 1955
1956 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1957 sizeof(vsi_ctx->info), cmd_details);
1958
1959 if (status)
1960 goto aq_add_vsi_exit;
1961
1962 vsi_ctx->seid = le16_to_cpu(resp->seid);
1963 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1964 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1965 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1966
1967aq_add_vsi_exit:
1968 return status;
1969}
1970
fb70faba
MW		 1971/**
1972 * i40e_aq_set_default_vsi
1973 * @hw: pointer to the hw struct
1974 * @seid: vsi number
1975 * @cmd_details: pointer to command details structure or NULL
1976 **/
1977i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
1978 u16 seid,
1979 struct i40e_asq_cmd_details *cmd_details)
1980{
1981 struct i40e_aq_desc desc;
1982 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1983 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1984 &desc.params.raw;
1985 i40e_status status;
1986
1987 i40e_fill_default_direct_cmd_desc(&desc,
1988 i40e_aqc_opc_set_vsi_promiscuous_modes);
1989
1990 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1991 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1992 cmd->seid = cpu_to_le16(seid);
1993
1994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1995
1996 return status;
1997}
1998
1999/**
2000 * i40e_aq_clear_default_vsi
2001 * @hw: pointer to the hw struct
2002 * @seid: vsi number
2003 * @cmd_details: pointer to command details structure or NULL
2004 **/
2005i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2006 u16 seid,
2007 struct i40e_asq_cmd_details *cmd_details)
2008{
2009 struct i40e_aq_desc desc;
2010 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2011 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2012 &desc.params.raw;
2013 i40e_status status;
2014
2015 i40e_fill_default_direct_cmd_desc(&desc,
2016 i40e_aqc_opc_set_vsi_promiscuous_modes);
2017
2018 cmd->promiscuous_flags = cpu_to_le16(0);
2019 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2020 cmd->seid = cpu_to_le16(seid);
2021
2022 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2023
2024 return status;
2025}
2026
56a62fc8
JB		 2027/**
2028 * i40e_aq_set_vsi_unicast_promiscuous
2029 * @hw: pointer to the hw struct
2030 * @seid: vsi number
2031 * @set: set unicast promiscuous enable/disable
2032 * @cmd_details: pointer to command details structure or NULL
b5569892 2033 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
56a62fc8
JB		 2034 **/
2035i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2 2036 u16 seid, bool set,
b5569892
ASJ		 2037 struct i40e_asq_cmd_details *cmd_details,
2038 bool rx_only_promisc)
56a62fc8
JB		 2039{
2040 struct i40e_aq_desc desc;
2041 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2042 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2043 i40e_status status;
2044 u16 flags = 0;
2045
2046 i40e_fill_default_direct_cmd_desc(&desc,
2047 i40e_aqc_opc_set_vsi_promiscuous_modes);
2048
3b120089 2049 if (set) {
56a62fc8 2050 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
b5569892
ASJ		 2051 if (rx_only_promisc &&
2052 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2053 (hw->aq.api_maj_ver > 1)))
3b120089
ASJ		 2054 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2055 }
56a62fc8
JB		 2056
2057 cmd->promiscuous_flags = cpu_to_le16(flags);
2058
2059 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
3b120089
ASJ		 2060 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2061 (hw->aq.api_maj_ver > 1))
2062 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
56a62fc8
JB		 2063
2064 cmd->seid = cpu_to_le16(seid);
2065 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2066
2067 return status;
2068}
2069
2070/**
2071 * i40e_aq_set_vsi_multicast_promiscuous
2072 * @hw: pointer to the hw struct
2073 * @seid: vsi number
2074 * @set: set multicast promiscuous enable/disable
2075 * @cmd_details: pointer to command details structure or NULL
2076 **/
2077i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2078 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2079{
2080 struct i40e_aq_desc desc;
2081 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2082 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2083 i40e_status status;
2084 u16 flags = 0;
2085
2086 i40e_fill_default_direct_cmd_desc(&desc,
2087 i40e_aqc_opc_set_vsi_promiscuous_modes);
2088
2089 if (set)
2090 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2091
2092 cmd->promiscuous_flags = cpu_to_le16(flags);
2093
2094 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2095
2096 cmd->seid = cpu_to_le16(seid);
2097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2098
2099 return status;
2100}
2101
6c41a760
GR		 2102/**
2103 * i40e_aq_set_vsi_mc_promisc_on_vlan
2104 * @hw: pointer to the hw struct
2105 * @seid: vsi number
2106 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2107 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2108 * @cmd_details: pointer to command details structure or NULL
2109 **/
2110enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2111 u16 seid, bool enable,
2112 u16 vid,
2113 struct i40e_asq_cmd_details *cmd_details)
2114{
2115 struct i40e_aq_desc desc;
2116 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2117 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2118 enum i40e_status_code status;
2119 u16 flags = 0;
2120
2121 i40e_fill_default_direct_cmd_desc(&desc,
2122 i40e_aqc_opc_set_vsi_promiscuous_modes);
2123
2124 if (enable)
2125 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2126
2127 cmd->promiscuous_flags = cpu_to_le16(flags);
2128 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2129 cmd->seid = cpu_to_le16(seid);
2130 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2131
2132 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2133
2134 return status;
2135}
2136
2137/**
2138 * i40e_aq_set_vsi_uc_promisc_on_vlan
2139 * @hw: pointer to the hw struct
2140 * @seid: vsi number
2141 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2142 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2143 * @cmd_details: pointer to command details structure or NULL
2144 **/
2145enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2146 u16 seid, bool enable,
2147 u16 vid,
2148 struct i40e_asq_cmd_details *cmd_details)
2149{
2150 struct i40e_aq_desc desc;
2151 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2152 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2153 enum i40e_status_code status;
2154 u16 flags = 0;
2155
2156 i40e_fill_default_direct_cmd_desc(&desc,
2157 i40e_aqc_opc_set_vsi_promiscuous_modes);
2158
2159 if (enable)
2160 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2161
2162 cmd->promiscuous_flags = cpu_to_le16(flags);
2163 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2164 cmd->seid = cpu_to_le16(seid);
2165 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2166
2167 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2168
2169 return status;
2170}
2171
435c084a
JK		 2172/**
2173 * i40e_aq_set_vsi_bc_promisc_on_vlan
2174 * @hw: pointer to the hw struct
2175 * @seid: vsi number
2176 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2177 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2178 * @cmd_details: pointer to command details structure or NULL
2179 **/
2180i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2181 u16 seid, bool enable, u16 vid,
2182 struct i40e_asq_cmd_details *cmd_details)
2183{
2184 struct i40e_aq_desc desc;
2185 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2186 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2187 i40e_status status;
2188 u16 flags = 0;
2189
2190 i40e_fill_default_direct_cmd_desc(&desc,
2191 i40e_aqc_opc_set_vsi_promiscuous_modes);
2192
2193 if (enable)
2194 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2195
2196 cmd->promiscuous_flags = cpu_to_le16(flags);
2197 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2198 cmd->seid = cpu_to_le16(seid);
2199 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2200
2201 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2202
2203 return status;
2204}
2205
56a62fc8
JB		 2206/**
2207 * i40e_aq_set_vsi_broadcast
2208 * @hw: pointer to the hw struct
2209 * @seid: vsi number
2210 * @set_filter: true to set filter, false to clear filter
2211 * @cmd_details: pointer to command details structure or NULL
2212 *
2213 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2214 **/
2215i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2216 u16 seid, bool set_filter,
2217 struct i40e_asq_cmd_details *cmd_details)
2218{
2219 struct i40e_aq_desc desc;
2220 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222 i40e_status status;
2223
2224 i40e_fill_default_direct_cmd_desc(&desc,
2225 i40e_aqc_opc_set_vsi_promiscuous_modes);
2226
2227 if (set_filter)
2228 cmd->promiscuous_flags
2229 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2230 else
2231 cmd->promiscuous_flags
2232 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2233
2234 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2235 cmd->seid = cpu_to_le16(seid);
2236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2237
2238 return status;
2239}
2240
7bd6875b
KP		 2241/**
2242 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2243 * @hw: pointer to the hw struct
2244 * @seid: vsi number
2245 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2246 * @cmd_details: pointer to command details structure or NULL
2247 **/
2248i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2249 u16 seid, bool enable,
2250 struct i40e_asq_cmd_details *cmd_details)
2251{
2252 struct i40e_aq_desc desc;
2253 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2254 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2255 i40e_status status;
2256 u16 flags = 0;
2257
2258 i40e_fill_default_direct_cmd_desc(&desc,
2259 i40e_aqc_opc_set_vsi_promiscuous_modes);
2260 if (enable)
2261 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2262
2263 cmd->promiscuous_flags = cpu_to_le16(flags);
2264 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2265 cmd->seid = cpu_to_le16(seid);
2266
2267 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2268
2269 return status;
2270}
2271
56a62fc8
JB		 2272/**
2273 * i40e_get_vsi_params - get VSI configuration info
2274 * @hw: pointer to the hw struct
98d44381 2275 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2276 * @cmd_details: pointer to command details structure or NULL
2277 **/
2278i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2279 struct i40e_vsi_context *vsi_ctx,
2280 struct i40e_asq_cmd_details *cmd_details)
2281{
2282 struct i40e_aq_desc desc;
f5ac8579
SN		 2283 struct i40e_aqc_add_get_update_vsi *cmd =
2284 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 2285 struct i40e_aqc_add_get_update_vsi_completion *resp =
2286 (struct i40e_aqc_add_get_update_vsi_completion *)
2287 &desc.params.raw;
2288 i40e_status status;
2289
2290 i40e_fill_default_direct_cmd_desc(&desc,
2291 i40e_aqc_opc_get_vsi_parameters);
2292
f5ac8579 2293 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2294
2295 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
56a62fc8
JB		 2296
2297 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2298 sizeof(vsi_ctx->info), NULL);
2299
2300 if (status)
2301 goto aq_get_vsi_params_exit;
2302
2303 vsi_ctx->seid = le16_to_cpu(resp->seid);
2304 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2305 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2306 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2307
2308aq_get_vsi_params_exit:
2309 return status;
2310}
2311
2312/**
2313 * i40e_aq_update_vsi_params
2314 * @hw: pointer to the hw struct
98d44381 2315 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 2316 * @cmd_details: pointer to command details structure or NULL
2317 *
2318 * Update a VSI context.
2319 **/
2320i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2321 struct i40e_vsi_context *vsi_ctx,
2322 struct i40e_asq_cmd_details *cmd_details)
2323{
2324 struct i40e_aq_desc desc;
f5ac8579
SN		 2325 struct i40e_aqc_add_get_update_vsi *cmd =
2326 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
b6caccac
KS		 2327 struct i40e_aqc_add_get_update_vsi_completion *resp =
2328 (struct i40e_aqc_add_get_update_vsi_completion *)
2329 &desc.params.raw;
56a62fc8
JB		 2330 i40e_status status;
2331
2332 i40e_fill_default_direct_cmd_desc(&desc,
2333 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 2334 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 2335
2336 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
56a62fc8
JB		 2337
2338 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2339 sizeof(vsi_ctx->info), cmd_details);
2340
b6caccac
KS		 2341 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2342 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2343
56a62fc8
JB		 2344 return status;
2345}
2346
2347/**
2348 * i40e_aq_get_switch_config
2349 * @hw: pointer to the hardware structure
2350 * @buf: pointer to the result buffer
2351 * @buf_size: length of input buffer
2352 * @start_seid: seid to start for the report, 0 == beginning
2353 * @cmd_details: pointer to command details structure or NULL
2354 *
2355 * Fill the buf with switch configuration returned from AdminQ command
2356 **/
2357i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2358 struct i40e_aqc_get_switch_config_resp *buf,
2359 u16 buf_size, u16 *start_seid,
2360 struct i40e_asq_cmd_details *cmd_details)
2361{
2362 struct i40e_aq_desc desc;
2363 struct i40e_aqc_switch_seid *scfg =
2364 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2365 i40e_status status;
2366
2367 i40e_fill_default_direct_cmd_desc(&desc,
2368 i40e_aqc_opc_get_switch_config);
2369 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2370 if (buf_size > I40E_AQ_LARGE_BUF)
2371 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2372 scfg->seid = cpu_to_le16(*start_seid);
2373
2374 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2375 *start_seid = le16_to_cpu(scfg->seid);
2376
2377 return status;
2378}
2379
f3d58497
SN		 2380/**
2381 * i40e_aq_set_switch_config
2382 * @hw: pointer to the hardware structure
2383 * @flags: bit flag values to set
2384 * @valid_flags: which bit flags to set
2385 * @cmd_details: pointer to command details structure or NULL
2386 *
2387 * Set switch configuration bits
2388 **/
2389enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2390 u16 flags,
2391 u16 valid_flags,
2392 struct i40e_asq_cmd_details *cmd_details)
2393{
2394 struct i40e_aq_desc desc;
2395 struct i40e_aqc_set_switch_config *scfg =
2396 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2397 enum i40e_status_code status;
2398
2399 i40e_fill_default_direct_cmd_desc(&desc,
2400 i40e_aqc_opc_set_switch_config);
2401 scfg->flags = cpu_to_le16(flags);
2402 scfg->valid_flags = cpu_to_le16(valid_flags);
2403
2404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2405
2406 return status;
2407}
2408
56a62fc8
JB		 2409/**
2410 * i40e_aq_get_firmware_version
2411 * @hw: pointer to the hw struct
2412 * @fw_major_version: firmware major version
2413 * @fw_minor_version: firmware minor version
7edf810c 2414 * @fw_build: firmware build number
56a62fc8
JB		 2415 * @api_major_version: major queue version
2416 * @api_minor_version: minor queue version
2417 * @cmd_details: pointer to command details structure or NULL
2418 *
2419 * Get the firmware version from the admin queue commands
2420 **/
2421i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2422 u16 *fw_major_version, u16 *fw_minor_version,
7edf810c 2423 u32 *fw_build,
56a62fc8
JB		 2424 u16 *api_major_version, u16 *api_minor_version,
2425 struct i40e_asq_cmd_details *cmd_details)
2426{
2427 struct i40e_aq_desc desc;
2428 struct i40e_aqc_get_version *resp =
2429 (struct i40e_aqc_get_version *)&desc.params.raw;
2430 i40e_status status;
2431
2432 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2433
2434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2435
2436 if (!status) {
7edf810c 2437 if (fw_major_version)
56a62fc8 2438 *fw_major_version = le16_to_cpu(resp->fw_major);
7edf810c 2439 if (fw_minor_version)
56a62fc8 2440 *fw_minor_version = le16_to_cpu(resp->fw_minor);
7edf810c
SN		 2441 if (fw_build)
2442 *fw_build = le32_to_cpu(resp->fw_build);
2443 if (api_major_version)
56a62fc8 2444 *api_major_version = le16_to_cpu(resp->api_major);
7edf810c 2445 if (api_minor_version)
56a62fc8
JB		 2446 *api_minor_version = le16_to_cpu(resp->api_minor);
2447 }
2448
2449 return status;
2450}
2451
2452/**
2453 * i40e_aq_send_driver_version
2454 * @hw: pointer to the hw struct
56a62fc8
JB		 2455 * @dv: driver's major, minor version
2456 * @cmd_details: pointer to command details structure or NULL
2457 *
2458 * Send the driver version to the firmware
2459 **/
2460i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2461 struct i40e_driver_version *dv,
2462 struct i40e_asq_cmd_details *cmd_details)
2463{
2464 struct i40e_aq_desc desc;
2465 struct i40e_aqc_driver_version *cmd =
2466 (struct i40e_aqc_driver_version *)&desc.params.raw;
2467 i40e_status status;
9d2f98e1 2468 u16 len;
56a62fc8
JB		 2469
2470 if (dv == NULL)
2471 return I40E_ERR_PARAM;
2472
2473 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2474
3b38cd17 2475 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
56a62fc8
JB		 2476 cmd->driver_major_ver = dv->major_version;
2477 cmd->driver_minor_ver = dv->minor_version;
2478 cmd->driver_build_ver = dv->build_version;
2479 cmd->driver_subbuild_ver = dv->subbuild_version;
d2466013
SN		 2480
2481 len = 0;
2482 while (len < sizeof(dv->driver_string) &&
2483 (dv->driver_string[len] < 0x80) &&
2484 dv->driver_string[len])
2485 len++;
2486 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2487 len, cmd_details);
56a62fc8
JB		 2488
2489 return status;
2490}
2491
2492/**
2493 * i40e_get_link_status - get status of the HW network link
2494 * @hw: pointer to the hw struct
a72a5abc 2495 * @link_up: pointer to bool (true/false = linkup/linkdown)
56a62fc8 2496 *
a72a5abc
JB		 2497 * Variable link_up true if link is up, false if link is down.
2498 * The variable link_up is invalid if returned value of status != 0
56a62fc8
JB		 2499 *
2500 * Side effect: LinkStatusEvent reporting becomes enabled
2501 **/
a72a5abc 2502i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
56a62fc8
JB		 2503{
2504 i40e_status status = 0;
56a62fc8
JB		 2505
2506 if (hw->phy.get_link_info) {
0a862b43 2507 status = i40e_update_link_info(hw);
56a62fc8
JB		 2508
2509 if (status)
a72a5abc
JB		 2510 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2511 status);
56a62fc8
JB		 2512 }
2513
a72a5abc 2514 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
56a62fc8 2515
a72a5abc 2516 return status;
56a62fc8
JB		 2517}
2518
0a862b43
CS		 2519/**
2520 * i40e_updatelink_status - update status of the HW network link
2521 * @hw: pointer to the hw struct
2522 **/
2523i40e_status i40e_update_link_info(struct i40e_hw *hw)
2524{
2525 struct i40e_aq_get_phy_abilities_resp abilities;
2526 i40e_status status = 0;
2527
2528 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2529 if (status)
2530 return status;
2531
ab425cb7
CW		 2532 /* extra checking needed to ensure link info to user is timely */
2533 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2534 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2535 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
8589af70
CW		 2536 status = i40e_aq_get_phy_capabilities(hw, false, false,
2537 &abilities, NULL);
2538 if (status)
2539 return status;
0a862b43 2540
8589af70
CW		 2541 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2542 sizeof(hw->phy.link_info.module_type));
2543 }
0a862b43
CS		 2544
2545 return status;
2546}
2547
56a62fc8
JB		 2548/**
2549 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2550 * @hw: pointer to the hw struct
2551 * @uplink_seid: the MAC or other gizmo SEID
2552 * @downlink_seid: the VSI SEID
2553 * @enabled_tc: bitmap of TCs to be enabled
2554 * @default_port: true for default port VSI, false for control port
2555 * @veb_seid: pointer to where to put the resulting VEB SEID
8a187f44 2556 * @enable_stats: true to turn on VEB stats
56a62fc8
JB		 2557 * @cmd_details: pointer to command details structure or NULL
2558 *
2559 * This asks the FW to add a VEB between the uplink and downlink
2560 * elements. If the uplink SEID is 0, this will be a floating VEB.
2561 **/
2562i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2563 u16 downlink_seid, u8 enabled_tc,
8a187f44
SN		 2564 bool default_port, u16 *veb_seid,
2565 bool enable_stats,
56a62fc8
JB		 2566 struct i40e_asq_cmd_details *cmd_details)
2567{
2568 struct i40e_aq_desc desc;
2569 struct i40e_aqc_add_veb *cmd =
2570 (struct i40e_aqc_add_veb *)&desc.params.raw;
2571 struct i40e_aqc_add_veb_completion *resp =
2572 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2573 i40e_status status;
2574 u16 veb_flags = 0;
2575
2576 /* SEIDs need to either both be set or both be 0 for floating VEB */
2577 if (!!uplink_seid != !!downlink_seid)
2578 return I40E_ERR_PARAM;
2579
2580 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2581
2582 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2583 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2584 cmd->enable_tcs = enabled_tc;
2585 if (!uplink_seid)
2586 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2587 if (default_port)
2588 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2589 else
2590 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95 2591
8a187f44
SN		 2592 /* reverse logic here: set the bitflag to disable the stats */
2593 if (!enable_stats)
2594 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
e1c51b95 2595
56a62fc8
JB		 2596 cmd->veb_flags = cpu_to_le16(veb_flags);
2597
2598 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2599
2600 if (!status && veb_seid)
2601 *veb_seid = le16_to_cpu(resp->veb_seid);
2602
2603 return status;
2604}
2605
2606/**
2607 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2608 * @hw: pointer to the hw struct
2609 * @veb_seid: the SEID of the VEB to query
2610 * @switch_id: the uplink switch id
98d44381 2611 * @floating: set to true if the VEB is floating
56a62fc8
JB		 2612 * @statistic_index: index of the stats counter block for this VEB
2613 * @vebs_used: number of VEB's used by function
98d44381 2614 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 2615 * @cmd_details: pointer to command details structure or NULL
2616 *
2617 * This retrieves the parameters for a particular VEB, specified by
2618 * uplink_seid, and returns them to the caller.
2619 **/
2620i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2621 u16 veb_seid, u16 *switch_id,
2622 bool *floating, u16 *statistic_index,
2623 u16 *vebs_used, u16 *vebs_free,
2624 struct i40e_asq_cmd_details *cmd_details)
2625{
2626 struct i40e_aq_desc desc;
2627 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2628 (struct i40e_aqc_get_veb_parameters_completion *)
2629 &desc.params.raw;
2630 i40e_status status;
2631
2632 if (veb_seid == 0)
2633 return I40E_ERR_PARAM;
2634
2635 i40e_fill_default_direct_cmd_desc(&desc,
2636 i40e_aqc_opc_get_veb_parameters);
2637 cmd_resp->seid = cpu_to_le16(veb_seid);
2638
2639 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2640 if (status)
2641 goto get_veb_exit;
2642
2643 if (switch_id)
2644 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2645 if (statistic_index)
2646 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2647 if (vebs_used)
2648 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2649 if (vebs_free)
2650 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2651 if (floating) {
2652 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
6995b36c 2653
56a62fc8
JB		 2654 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2655 *floating = true;
2656 else
2657 *floating = false;
2658 }
2659
2660get_veb_exit:
2661 return status;
2662}
2663
2664/**
2665 * i40e_aq_add_macvlan
2666 * @hw: pointer to the hw struct
2667 * @seid: VSI for the mac address
2668 * @mv_list: list of macvlans to be added
2669 * @count: length of the list
2670 * @cmd_details: pointer to command details structure or NULL
2671 *
2672 * Add MAC/VLAN addresses to the HW filtering
2673 **/
2674i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2675 struct i40e_aqc_add_macvlan_element_data *mv_list,
2676 u16 count, struct i40e_asq_cmd_details *cmd_details)
2677{
2678 struct i40e_aq_desc desc;
2679 struct i40e_aqc_macvlan *cmd =
2680 (struct i40e_aqc_macvlan *)&desc.params.raw;
2681 i40e_status status;
2682 u16 buf_size;
67be6eb2 2683 int i;
56a62fc8
JB		 2684
2685 if (count == 0 || !mv_list || !hw)
2686 return I40E_ERR_PARAM;
2687
1efc80ee 2688 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2689
2690 /* prep the rest of the request */
2691 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2692 cmd->num_addresses = cpu_to_le16(count);
2693 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2694 cmd->seid[1] = 0;
2695 cmd->seid[2] = 0;
2696
67be6eb2
SN		 2697 for (i = 0; i < count; i++)
2698 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2699 mv_list[i].flags |=
2700 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2701
56a62fc8
JB		 2702 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2703 if (buf_size > I40E_AQ_LARGE_BUF)
2704 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2705
2706 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
67be6eb2 2707 cmd_details);
56a62fc8
JB		 2708
2709 return status;
2710}
2711
2712/**
2713 * i40e_aq_remove_macvlan
2714 * @hw: pointer to the hw struct
2715 * @seid: VSI for the mac address
2716 * @mv_list: list of macvlans to be removed
2717 * @count: length of the list
2718 * @cmd_details: pointer to command details structure or NULL
2719 *
2720 * Remove MAC/VLAN addresses from the HW filtering
2721 **/
2722i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2723 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2724 u16 count, struct i40e_asq_cmd_details *cmd_details)
2725{
2726 struct i40e_aq_desc desc;
2727 struct i40e_aqc_macvlan *cmd =
2728 (struct i40e_aqc_macvlan *)&desc.params.raw;
2729 i40e_status status;
2730 u16 buf_size;
2731
2732 if (count == 0 || !mv_list || !hw)
2733 return I40E_ERR_PARAM;
2734
1efc80ee 2735 buf_size = count * sizeof(*mv_list);
56a62fc8
JB		 2736
2737 /* prep the rest of the request */
2738 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2739 cmd->num_addresses = cpu_to_le16(count);
2740 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2741 cmd->seid[1] = 0;
2742 cmd->seid[2] = 0;
2743
2744 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2745 if (buf_size > I40E_AQ_LARGE_BUF)
2746 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2747
2748 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2749 cmd_details);
2750
2751 return status;
2752}
2753
7bd6875b
KP		 2754/**
2755 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2756 * @hw: pointer to the hw struct
2757 * @opcode: AQ opcode for add or delete mirror rule
2758 * @sw_seid: Switch SEID (to which rule refers)
2759 * @rule_type: Rule Type (ingress/egress/VLAN)
2760 * @id: Destination VSI SEID or Rule ID
2761 * @count: length of the list
2762 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2763 * @cmd_details: pointer to command details structure or NULL
2764 * @rule_id: Rule ID returned from FW
2765 * @rule_used: Number of rules used in internal switch
2766 * @rule_free: Number of rules free in internal switch
2767 *
2768 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2769 * VEBs/VEPA elements only
2770 **/
2771static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2772 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2773 u16 count, __le16 *mr_list,
2774 struct i40e_asq_cmd_details *cmd_details,
2775 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2776{
2777 struct i40e_aq_desc desc;
2778 struct i40e_aqc_add_delete_mirror_rule *cmd =
2779 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2780 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2781 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2782 i40e_status status;
2783 u16 buf_size;
2784
2785 buf_size = count * sizeof(*mr_list);
2786
2787 /* prep the rest of the request */
2788 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2789 cmd->seid = cpu_to_le16(sw_seid);
2790 cmd->rule_type = cpu_to_le16(rule_type &
2791 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2792 cmd->num_entries = cpu_to_le16(count);
2793 /* Dest VSI for add, rule_id for delete */
2794 cmd->destination = cpu_to_le16(id);
2795 if (mr_list) {
2796 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2797 I40E_AQ_FLAG_RD));
2798 if (buf_size > I40E_AQ_LARGE_BUF)
2799 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2800 }
2801
2802 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2803 cmd_details);
2804 if (!status ||
2805 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2806 if (rule_id)
2807 *rule_id = le16_to_cpu(resp->rule_id);
2808 if (rules_used)
2809 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2810 if (rules_free)
2811 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2812 }
2813 return status;
2814}
2815
2816/**
2817 * i40e_aq_add_mirrorrule - add a mirror rule
2818 * @hw: pointer to the hw struct
2819 * @sw_seid: Switch SEID (to which rule refers)
2820 * @rule_type: Rule Type (ingress/egress/VLAN)
2821 * @dest_vsi: SEID of VSI to which packets will be mirrored
2822 * @count: length of the list
2823 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2824 * @cmd_details: pointer to command details structure or NULL
2825 * @rule_id: Rule ID returned from FW
2826 * @rule_used: Number of rules used in internal switch
2827 * @rule_free: Number of rules free in internal switch
2828 *
2829 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2830 **/
2831i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2832 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2833 struct i40e_asq_cmd_details *cmd_details,
2834 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2835{
2836 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2837 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2838 if (count == 0 || !mr_list)
2839 return I40E_ERR_PARAM;
2840 }
2841
2842 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2843 rule_type, dest_vsi, count, mr_list,
2844 cmd_details, rule_id, rules_used, rules_free);
2845}
2846
2847/**
2848 * i40e_aq_delete_mirrorrule - delete a mirror rule
2849 * @hw: pointer to the hw struct
2850 * @sw_seid: Switch SEID (to which rule refers)
2851 * @rule_type: Rule Type (ingress/egress/VLAN)
2852 * @count: length of the list
2853 * @rule_id: Rule ID that is returned in the receive desc as part of
2854 * add_mirrorrule.
2855 * @mr_list: list of mirrored VLAN IDs to be removed
2856 * @cmd_details: pointer to command details structure or NULL
2857 * @rule_used: Number of rules used in internal switch
2858 * @rule_free: Number of rules free in internal switch
2859 *
2860 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2861 **/
2862i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2863 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2864 struct i40e_asq_cmd_details *cmd_details,
2865 u16 *rules_used, u16 *rules_free)
2866{
2867 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
db077278 2868 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7bd6875b
KP		 2869 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2870 * mirroring. For other rule_type, count and rule_type should
2871 * not matter.
2872 */
2873 if (count == 0 || !mr_list)
2874 return I40E_ERR_PARAM;
2875 }
2876
2877 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2878 rule_type, rule_id, count, mr_list,
2879 cmd_details, NULL, rules_used, rules_free);
2880}
2881
56a62fc8
JB		 2882/**
2883 * i40e_aq_send_msg_to_vf
2884 * @hw: pointer to the hardware structure
b40c82e6 2885 * @vfid: VF id to send msg
98d44381
JK		 2886 * @v_opcode: opcodes for VF-PF communication
2887 * @v_retval: return error code
56a62fc8
JB		 2888 * @msg: pointer to the msg buffer
2889 * @msglen: msg length
2890 * @cmd_details: pointer to command details
2891 *
2892 * send msg to vf
2893 **/
2894i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2895 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2896 struct i40e_asq_cmd_details *cmd_details)
2897{
2898 struct i40e_aq_desc desc;
2899 struct i40e_aqc_pf_vf_message *cmd =
2900 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2901 i40e_status status;
2902
2903 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2904 cmd->id = cpu_to_le32(vfid);
2905 desc.cookie_high = cpu_to_le32(v_opcode);
2906 desc.cookie_low = cpu_to_le32(v_retval);
2907 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2908 if (msglen) {
2909 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2910 I40E_AQ_FLAG_RD));
2911 if (msglen > I40E_AQ_LARGE_BUF)
2912 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2913 desc.datalen = cpu_to_le16(msglen);
2914 }
2915 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2916
2917 return status;
2918}
2919
9fee9db5
SN		 2920/**
2921 * i40e_aq_debug_read_register
2922 * @hw: pointer to the hw struct
2923 * @reg_addr: register address
2924 * @reg_val: register value
2925 * @cmd_details: pointer to command details structure or NULL
2926 *
2927 * Read the register using the admin queue commands
2928 **/
2929i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
7b115dd0 2930 u32 reg_addr, u64 *reg_val,
9fee9db5
SN		 2931 struct i40e_asq_cmd_details *cmd_details)
2932{
2933 struct i40e_aq_desc desc;
2934 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2935 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2936 i40e_status status;
2937
2938 if (reg_val == NULL)
2939 return I40E_ERR_PARAM;
2940
7b115dd0 2941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
9fee9db5
SN		 2942
2943 cmd_resp->address = cpu_to_le32(reg_addr);
2944
2945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2946
2947 if (!status) {
7b115dd0
JB		 2948 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2949 (u64)le32_to_cpu(cmd_resp->value_low);
9fee9db5
SN		 2950 }
2951
2952 return status;
2953}
2954
53db45cd
SN		 2955/**
2956 * i40e_aq_debug_write_register
2957 * @hw: pointer to the hw struct
2958 * @reg_addr: register address
2959 * @reg_val: register value
2960 * @cmd_details: pointer to command details structure or NULL
2961 *
2962 * Write to a register using the admin queue commands
2963 **/
2964i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2965 u32 reg_addr, u64 reg_val,
2966 struct i40e_asq_cmd_details *cmd_details)
2967{
2968 struct i40e_aq_desc desc;
2969 struct i40e_aqc_debug_reg_read_write *cmd =
2970 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2971 i40e_status status;
2972
2973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2974
2975 cmd->address = cpu_to_le32(reg_addr);
2976 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2977 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2978
2979 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2980
2981 return status;
2982}
2983
56a62fc8
JB		 2984/**
2985 * i40e_aq_request_resource
2986 * @hw: pointer to the hw struct
2987 * @resource: resource id
2988 * @access: access type
2989 * @sdp_number: resource number
2990 * @timeout: the maximum time in ms that the driver may hold the resource
2991 * @cmd_details: pointer to command details structure or NULL
2992 *
2993 * requests common resource using the admin queue commands
2994 **/
2995i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2996 enum i40e_aq_resources_ids resource,
2997 enum i40e_aq_resource_access_type access,
2998 u8 sdp_number, u64 *timeout,
2999 struct i40e_asq_cmd_details *cmd_details)
3000{
3001 struct i40e_aq_desc desc;
3002 struct i40e_aqc_request_resource *cmd_resp =
3003 (struct i40e_aqc_request_resource *)&desc.params.raw;
3004 i40e_status status;
3005
3006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3007
3008 cmd_resp->resource_id = cpu_to_le16(resource);
3009 cmd_resp->access_type = cpu_to_le16(access);
3010 cmd_resp->resource_number = cpu_to_le32(sdp_number);
3011
3012 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3013 /* The completion specifies the maximum time in ms that the driver
3014 * may hold the resource in the Timeout field.
3015 * If the resource is held by someone else, the command completes with
3016 * busy return value and the timeout field indicates the maximum time
3017 * the current owner of the resource has to free it.
3018 */
3019 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3020 *timeout = le32_to_cpu(cmd_resp->timeout);
3021
3022 return status;
3023}
3024
3025/**
3026 * i40e_aq_release_resource
3027 * @hw: pointer to the hw struct
3028 * @resource: resource id
3029 * @sdp_number: resource number
3030 * @cmd_details: pointer to command details structure or NULL
3031 *
3032 * release common resource using the admin queue commands
3033 **/
3034i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3035 enum i40e_aq_resources_ids resource,
3036 u8 sdp_number,
3037 struct i40e_asq_cmd_details *cmd_details)
3038{
3039 struct i40e_aq_desc desc;
3040 struct i40e_aqc_request_resource *cmd =
3041 (struct i40e_aqc_request_resource *)&desc.params.raw;
3042 i40e_status status;
3043
3044 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3045
3046 cmd->resource_id = cpu_to_le16(resource);
3047 cmd->resource_number = cpu_to_le32(sdp_number);
3048
3049 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3050
3051 return status;
3052}
3053
3054/**
3055 * i40e_aq_read_nvm
3056 * @hw: pointer to the hw struct
3057 * @module_pointer: module pointer location in words from the NVM beginning
3058 * @offset: byte offset from the module beginning
3059 * @length: length of the section to be read (in bytes from the offset)
3060 * @data: command buffer (size [bytes] = length)
3061 * @last_command: tells if this is the last command in a series
3062 * @cmd_details: pointer to command details structure or NULL
3063 *
3064 * Read the NVM using the admin queue commands
3065 **/
3066i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3067 u32 offset, u16 length, void *data,
3068 bool last_command,
3069 struct i40e_asq_cmd_details *cmd_details)
3070{
3071 struct i40e_aq_desc desc;
3072 struct i40e_aqc_nvm_update *cmd =
3073 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3074 i40e_status status;
3075
3076 /* In offset the highest byte must be zeroed. */
3077 if (offset & 0xFF000000) {
3078 status = I40E_ERR_PARAM;
3079 goto i40e_aq_read_nvm_exit;
3080 }
3081
3082 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3083
3084 /* If this is the last command in a series, set the proper flag. */
3085 if (last_command)
3086 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3087 cmd->module_pointer = module_pointer;
3088 cmd->offset = cpu_to_le32(offset);
3089 cmd->length = cpu_to_le16(length);
3090
3091 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3092 if (length > I40E_AQ_LARGE_BUF)
3093 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3094
3095 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3096
3097i40e_aq_read_nvm_exit:
3098 return status;
3099}
3100
cd552cb4
SN		 3101/**
3102 * i40e_aq_erase_nvm
3103 * @hw: pointer to the hw struct
3104 * @module_pointer: module pointer location in words from the NVM beginning
3105 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3106 * @length: length of the section to be erased (expressed in 4 KB)
3107 * @last_command: tells if this is the last command in a series
3108 * @cmd_details: pointer to command details structure or NULL
3109 *
3110 * Erase the NVM sector using the admin queue commands
3111 **/
3112i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3113 u32 offset, u16 length, bool last_command,
3114 struct i40e_asq_cmd_details *cmd_details)
3115{
3116 struct i40e_aq_desc desc;
3117 struct i40e_aqc_nvm_update *cmd =
3118 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3119 i40e_status status;
3120
3121 /* In offset the highest byte must be zeroed. */
3122 if (offset & 0xFF000000) {
3123 status = I40E_ERR_PARAM;
3124 goto i40e_aq_erase_nvm_exit;
3125 }
3126
3127 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3128
3129 /* If this is the last command in a series, set the proper flag. */
3130 if (last_command)
3131 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3132 cmd->module_pointer = module_pointer;
3133 cmd->offset = cpu_to_le32(offset);
3134 cmd->length = cpu_to_le16(length);
3135
3136 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3137
3138i40e_aq_erase_nvm_exit:
3139 return status;
3140}
3141
56a62fc8
JB		 3142/**
3143 * i40e_parse_discover_capabilities
3144 * @hw: pointer to the hw struct
3145 * @buff: pointer to a buffer containing device/function capability records
3146 * @cap_count: number of capability records in the list
3147 * @list_type_opc: type of capabilities list to parse
3148 *
3149 * Parse the device/function capabilities list.
3150 **/
3151static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3152 u32 cap_count,
3153 enum i40e_admin_queue_opc list_type_opc)
3154{
3155 struct i40e_aqc_list_capabilities_element_resp *cap;
9fee9db5 3156 u32 valid_functions, num_functions;
56a62fc8
JB		 3157 u32 number, logical_id, phys_id;
3158 struct i40e_hw_capabilities *p;
c78b953e 3159 u8 major_rev;
56a62fc8
JB		 3160 u32 i = 0;
3161 u16 id;
3162
3163 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3164
3165 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
b58f2f72 3166 p = &hw->dev_caps;
56a62fc8 3167 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
b58f2f72 3168 p = &hw->func_caps;
56a62fc8
JB		 3169 else
3170 return;
3171
3172 for (i = 0; i < cap_count; i++, cap++) {
3173 id = le16_to_cpu(cap->id);
3174 number = le32_to_cpu(cap->number);
3175 logical_id = le32_to_cpu(cap->logical_id);
3176 phys_id = le32_to_cpu(cap->phys_id);
c78b953e 3177 major_rev = cap->major_rev;
56a62fc8
JB		 3178
3179 switch (id) {
406e734a 3180 case I40E_AQ_CAP_ID_SWITCH_MODE:
56a62fc8
JB		 3181 p->switch_mode = number;
3182 break;
406e734a 3183 case I40E_AQ_CAP_ID_MNG_MODE:
56a62fc8 3184 p->management_mode = number;
64f5ead9
PR		 3185 if (major_rev > 1) {
3186 p->mng_protocols_over_mctp = logical_id;
3187 i40e_debug(hw, I40E_DEBUG_INIT,
3188 "HW Capability: Protocols over MCTP = %d\n",
3189 p->mng_protocols_over_mctp);
3190 } else {
3191 p->mng_protocols_over_mctp = 0;
3192 }
56a62fc8 3193 break;
406e734a 3194 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
56a62fc8
JB		 3195 p->npar_enable = number;
3196 break;
406e734a 3197 case I40E_AQ_CAP_ID_OS2BMC_CAP:
56a62fc8
JB		 3198 p->os2bmc = number;
3199 break;
406e734a 3200 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
56a62fc8
JB		 3201 p->valid_functions = number;
3202 break;
406e734a 3203 case I40E_AQ_CAP_ID_SRIOV:
56a62fc8
JB		 3204 if (number == 1)
3205 p->sr_iov_1_1 = true;
3206 break;
406e734a 3207 case I40E_AQ_CAP_ID_VF:
56a62fc8
JB		 3208 p->num_vfs = number;
3209 p->vf_base_id = logical_id;
3210 break;
406e734a 3211 case I40E_AQ_CAP_ID_VMDQ:
56a62fc8
JB		 3212 if (number == 1)
3213 p->vmdq = true;
3214 break;
406e734a 3215 case I40E_AQ_CAP_ID_8021QBG:
56a62fc8
JB		 3216 if (number == 1)
3217 p->evb_802_1_qbg = true;
3218 break;
406e734a 3219 case I40E_AQ_CAP_ID_8021QBR:
56a62fc8
JB		 3220 if (number == 1)
3221 p->evb_802_1_qbh = true;
3222 break;
406e734a 3223 case I40E_AQ_CAP_ID_VSI:
56a62fc8
JB		 3224 p->num_vsis = number;
3225 break;
406e734a 3226 case I40E_AQ_CAP_ID_DCB:
56a62fc8
JB		 3227 if (number == 1) {
3228 p->dcb = true;
3229 p->enabled_tcmap = logical_id;
3230 p->maxtc = phys_id;
3231 }
3232 break;
406e734a 3233 case I40E_AQ_CAP_ID_FCOE:
56a62fc8
JB		 3234 if (number == 1)
3235 p->fcoe = true;
3236 break;
406e734a 3237 case I40E_AQ_CAP_ID_ISCSI:
63d7e5a4
NP		 3238 if (number == 1)
3239 p->iscsi = true;
3240 break;
406e734a 3241 case I40E_AQ_CAP_ID_RSS:
56a62fc8 3242 p->rss = true;
e157ea30 3243 p->rss_table_size = number;
56a62fc8
JB		 3244 p->rss_table_entry_width = logical_id;
3245 break;
406e734a 3246 case I40E_AQ_CAP_ID_RXQ:
56a62fc8
JB		 3247 p->num_rx_qp = number;
3248 p->base_queue = phys_id;
3249 break;
406e734a 3250 case I40E_AQ_CAP_ID_TXQ:
56a62fc8
JB		 3251 p->num_tx_qp = number;
3252 p->base_queue = phys_id;
3253 break;
406e734a 3254 case I40E_AQ_CAP_ID_MSIX:
56a62fc8 3255 p->num_msix_vectors = number;
453e16e8
DK		 3256 i40e_debug(hw, I40E_DEBUG_INIT,
3257 "HW Capability: MSIX vector count = %d\n",
3258 p->num_msix_vectors);
56a62fc8 3259 break;
406e734a 3260 case I40E_AQ_CAP_ID_VF_MSIX:
56a62fc8
JB		 3261 p->num_msix_vectors_vf = number;
3262 break;
406e734a 3263 case I40E_AQ_CAP_ID_FLEX10:
c78b953e
PO		 3264 if (major_rev == 1) {
3265 if (number == 1) {
3266 p->flex10_enable = true;
3267 p->flex10_capable = true;
3268 }
3269 } else {
3270 /* Capability revision >= 2 */
3271 if (number & 1)
3272 p->flex10_enable = true;
3273 if (number & 2)
3274 p->flex10_capable = true;
3275 }
3276 p->flex10_mode = logical_id;
3277 p->flex10_status = phys_id;
56a62fc8 3278 break;
406e734a 3279 case I40E_AQ_CAP_ID_CEM:
56a62fc8
JB		 3280 if (number == 1)
3281 p->mgmt_cem = true;
3282 break;
406e734a 3283 case I40E_AQ_CAP_ID_IWARP:
56a62fc8
JB		 3284 if (number == 1)
3285 p->iwarp = true;
3286 break;
406e734a 3287 case I40E_AQ_CAP_ID_LED:
56a62fc8
JB		 3288 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3289 p->led[phys_id] = true;
3290 break;
406e734a 3291 case I40E_AQ_CAP_ID_SDP:
56a62fc8
JB		 3292 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3293 p->sdp[phys_id] = true;
3294 break;
406e734a 3295 case I40E_AQ_CAP_ID_MDIO:
56a62fc8
JB		 3296 if (number == 1) {
3297 p->mdio_port_num = phys_id;
3298 p->mdio_port_mode = logical_id;
3299 }
3300 break;
406e734a 3301 case I40E_AQ_CAP_ID_1588:
56a62fc8
JB		 3302 if (number == 1)
3303 p->ieee_1588 = true;
3304 break;
406e734a 3305 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
56a62fc8
JB		 3306 p->fd = true;
3307 p->fd_filters_guaranteed = number;
3308 p->fd_filters_best_effort = logical_id;
3309 break;
406e734a 3310 case I40E_AQ_CAP_ID_WSR_PROT:
73b23402
KS		 3311 p->wr_csr_prot = (u64)number;
3312 p->wr_csr_prot |= (u64)logical_id << 32;
3313 break;
68a1c5a7
MK		 3314 case I40E_AQ_CAP_ID_NVM_MGMT:
3315 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3316 p->sec_rev_disabled = true;
3317 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3318 p->update_disabled = true;
3319 break;
56a62fc8
JB		 3320 default:
3321 break;
3322 }
3323 }
3324
f18ae100
VD		 3325 if (p->fcoe)
3326 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3327
566bb85d
VD		 3328 /* Software override ensuring FCoE is disabled if npar or mfp
3329 * mode because it is not supported in these modes.
3330 */
c78b953e 3331 if (p->npar_enable || p->flex10_enable)
566bb85d
VD		 3332 p->fcoe = false;
3333
9fee9db5
SN		 3334 /* count the enabled ports (aka the "not disabled" ports) */
3335 hw->num_ports = 0;
3336 for (i = 0; i < 4; i++) {
3337 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3338 u64 port_cfg = 0;
3339
3340 /* use AQ read to get the physical register offset instead
3341 * of the port relative offset
3342 */
3343 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3344 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3345 hw->num_ports++;
3346 }
3347
3348 valid_functions = p->valid_functions;
3349 num_functions = 0;
3350 while (valid_functions) {
3351 if (valid_functions & 1)
3352 num_functions++;
3353 valid_functions >>= 1;
3354 }
3355
3356 /* partition id is 1-based, and functions are evenly spread
3357 * across the ports as partitions
3358 */
999b315d
MK		 3359 if (hw->num_ports != 0) {
3360 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3361 hw->num_partitions = num_functions / hw->num_ports;
3362 }
9fee9db5 3363
56a62fc8
JB		 3364 /* additional HW specific goodies that might
3365 * someday be HW version specific
3366 */
3367 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3368}
3369
3370/**
3371 * i40e_aq_discover_capabilities
3372 * @hw: pointer to the hw struct
3373 * @buff: a virtual buffer to hold the capabilities
3374 * @buff_size: Size of the virtual buffer
3375 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3376 * @list_type_opc: capabilities type to discover - pass in the command opcode
3377 * @cmd_details: pointer to command details structure or NULL
3378 *
3379 * Get the device capabilities descriptions from the firmware
3380 **/
3381i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3382 void *buff, u16 buff_size, u16 *data_size,
3383 enum i40e_admin_queue_opc list_type_opc,
3384 struct i40e_asq_cmd_details *cmd_details)
3385{
3386 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 3387 struct i40e_aq_desc desc;
8fb905b3 3388 i40e_status status = 0;
56a62fc8
JB		 3389
3390 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3391
3392 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3393 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3394 status = I40E_ERR_PARAM;
3395 goto exit;
3396 }
3397
3398 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3399
3400 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3401 if (buff_size > I40E_AQ_LARGE_BUF)
3402 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3403
3404 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3405 *data_size = le16_to_cpu(desc.datalen);
3406
3407 if (status)
3408 goto exit;
3409
3410 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3411 list_type_opc);
3412
3413exit:
3414 return status;
3415}
3416
cd552cb4
SN		 3417/**
3418 * i40e_aq_update_nvm
3419 * @hw: pointer to the hw struct
3420 * @module_pointer: module pointer location in words from the NVM beginning
3421 * @offset: byte offset from the module beginning
3422 * @length: length of the section to be written (in bytes from the offset)
3423 * @data: command buffer (size [bytes] = length)
3424 * @last_command: tells if this is the last command in a series
3425 * @cmd_details: pointer to command details structure or NULL
3426 *
3427 * Update the NVM using the admin queue commands
3428 **/
3429i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3430 u32 offset, u16 length, void *data,
3431 bool last_command,
3432 struct i40e_asq_cmd_details *cmd_details)
3433{
3434 struct i40e_aq_desc desc;
3435 struct i40e_aqc_nvm_update *cmd =
3436 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3437 i40e_status status;
3438
3439 /* In offset the highest byte must be zeroed. */
3440 if (offset & 0xFF000000) {
3441 status = I40E_ERR_PARAM;
3442 goto i40e_aq_update_nvm_exit;
3443 }
3444
3445 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3446
3447 /* If this is the last command in a series, set the proper flag. */
3448 if (last_command)
3449 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3450 cmd->module_pointer = module_pointer;
3451 cmd->offset = cpu_to_le32(offset);
3452 cmd->length = cpu_to_le16(length);
3453
3454 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3455 if (length > I40E_AQ_LARGE_BUF)
3456 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3457
3458 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3459
3460i40e_aq_update_nvm_exit:
3461 return status;
3462}
3463
56a62fc8
JB		 3464/**
3465 * i40e_aq_get_lldp_mib
3466 * @hw: pointer to the hw struct
3467 * @bridge_type: type of bridge requested
3468 * @mib_type: Local, Remote or both Local and Remote MIBs
3469 * @buff: pointer to a user supplied buffer to store the MIB block
3470 * @buff_size: size of the buffer (in bytes)
3471 * @local_len : length of the returned Local LLDP MIB
3472 * @remote_len: length of the returned Remote LLDP MIB
3473 * @cmd_details: pointer to command details structure or NULL
3474 *
3475 * Requests the complete LLDP MIB (entire packet).
3476 **/
3477i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3478 u8 mib_type, void *buff, u16 buff_size,
3479 u16 *local_len, u16 *remote_len,
3480 struct i40e_asq_cmd_details *cmd_details)
3481{
3482 struct i40e_aq_desc desc;
3483 struct i40e_aqc_lldp_get_mib *cmd =
3484 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3485 struct i40e_aqc_lldp_get_mib *resp =
3486 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3487 i40e_status status;
3488
3489 if (buff_size == 0 || !buff)
3490 return I40E_ERR_PARAM;
3491
3492 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3493 /* Indirect Command */
3494 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3495
3496 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3497 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3498 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3499
3500 desc.datalen = cpu_to_le16(buff_size);
3501
3502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3503 if (buff_size > I40E_AQ_LARGE_BUF)
3504 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3505
3506 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3507 if (!status) {
3508 if (local_len != NULL)
3509 *local_len = le16_to_cpu(resp->local_len);
3510 if (remote_len != NULL)
3511 *remote_len = le16_to_cpu(resp->remote_len);
3512 }
3513
3514 return status;
3515}
3516
3517/**
3518 * i40e_aq_cfg_lldp_mib_change_event
3519 * @hw: pointer to the hw struct
3520 * @enable_update: Enable or Disable event posting
3521 * @cmd_details: pointer to command details structure or NULL
3522 *
3523 * Enable or Disable posting of an event on ARQ when LLDP MIB
3524 * associated with the interface changes
3525 **/
3526i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3527 bool enable_update,
3528 struct i40e_asq_cmd_details *cmd_details)
3529{
3530 struct i40e_aq_desc desc;
3531 struct i40e_aqc_lldp_update_mib *cmd =
3532 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3533 i40e_status status;
3534
3535 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3536
3537 if (!enable_update)
3538 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3539
3540 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3541
3542 return status;
3543}
3544
3545/**
3546 * i40e_aq_stop_lldp
3547 * @hw: pointer to the hw struct
3548 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3549 * @cmd_details: pointer to command details structure or NULL
3550 *
3551 * Stop or Shutdown the embedded LLDP Agent
3552 **/
3553i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3554 struct i40e_asq_cmd_details *cmd_details)
3555{
3556 struct i40e_aq_desc desc;
3557 struct i40e_aqc_lldp_stop *cmd =
3558 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3559 i40e_status status;
3560
3561 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3562
3563 if (shutdown_agent)
3564 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3565
3566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3567
3568 return status;
3569}
3570
3571/**
3572 * i40e_aq_start_lldp
3573 * @hw: pointer to the hw struct
3574 * @cmd_details: pointer to command details structure or NULL
3575 *
3576 * Start the embedded LLDP Agent on all ports.
3577 **/
3578i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3579 struct i40e_asq_cmd_details *cmd_details)
3580{
3581 struct i40e_aq_desc desc;
3582 struct i40e_aqc_lldp_start *cmd =
3583 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3584 i40e_status status;
3585
3586 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3587
3588 cmd->command = I40E_AQ_LLDP_AGENT_START;
3589
3590 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3591
3592 return status;
3593}
3594
9fa61dd2
NP		 3595/**
3596 * i40e_aq_get_cee_dcb_config
3597 * @hw: pointer to the hw struct
3598 * @buff: response buffer that stores CEE operational configuration
3599 * @buff_size: size of the buffer passed
3600 * @cmd_details: pointer to command details structure or NULL
3601 *
3602 * Get CEE DCBX mode operational configuration from firmware
3603 **/
3604i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3605 void *buff, u16 buff_size,
3606 struct i40e_asq_cmd_details *cmd_details)
3607{
3608 struct i40e_aq_desc desc;
3609 i40e_status status;
3610
3611 if (buff_size == 0 || !buff)
3612 return I40E_ERR_PARAM;
3613
3614 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3615
3616 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3617 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3618 cmd_details);
3619
3620 return status;
3621}
3622
a1c9a9d9
JK		 3623/**
3624 * i40e_aq_add_udp_tunnel
3625 * @hw: pointer to the hw struct
3626 * @udp_port: the UDP port to add
3627 * @header_len: length of the tunneling header length in DWords
3628 * @protocol_index: protocol index type
98d44381 3629 * @filter_index: pointer to filter index
a1c9a9d9
JK		 3630 * @cmd_details: pointer to command details structure or NULL
3631 **/
3632i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
f4f94b94
KS		 3633 u16 udp_port, u8 protocol_index,
3634 u8 *filter_index,
a1c9a9d9
JK		 3635 struct i40e_asq_cmd_details *cmd_details)
3636{
3637 struct i40e_aq_desc desc;
3638 struct i40e_aqc_add_udp_tunnel *cmd =
3639 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3640 struct i40e_aqc_del_udp_tunnel_completion *resp =
3641 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3642 i40e_status status;
3643
3644 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3645
3646 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 3647 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 3648
3649 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3650
65d13461 3651 if (!status && filter_index)
a1c9a9d9
JK		 3652 *filter_index = resp->index;
3653
3654 return status;
3655}
3656
3657/**
3658 * i40e_aq_del_udp_tunnel
3659 * @hw: pointer to the hw struct
3660 * @index: filter index
3661 * @cmd_details: pointer to command details structure or NULL
3662 **/
3663i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3664 struct i40e_asq_cmd_details *cmd_details)
3665{
3666 struct i40e_aq_desc desc;
3667 struct i40e_aqc_remove_udp_tunnel *cmd =
3668 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3669 i40e_status status;
3670
3671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3672
3673 cmd->index = index;
3674
3675 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3676
3677 return status;
3678}
3679
56a62fc8
JB		 3680/**
3681 * i40e_aq_delete_element - Delete switch element
3682 * @hw: pointer to the hw struct
3683 * @seid: the SEID to delete from the switch
3684 * @cmd_details: pointer to command details structure or NULL
3685 *
3686 * This deletes a switch element from the switch.
3687 **/
3688i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3689 struct i40e_asq_cmd_details *cmd_details)
3690{
3691 struct i40e_aq_desc desc;
3692 struct i40e_aqc_switch_seid *cmd =
3693 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3694 i40e_status status;
3695
3696 if (seid == 0)
3697 return I40E_ERR_PARAM;
3698
3699 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3700
3701 cmd->seid = cpu_to_le16(seid);
3702
3703 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3704
3705 return status;
3706}
3707
afb3ff0d
NP		 3708/**
3709 * i40e_aq_dcb_updated - DCB Updated Command
3710 * @hw: pointer to the hw struct
3711 * @cmd_details: pointer to command details structure or NULL
3712 *
3713 * EMP will return when the shared RPB settings have been
3714 * recomputed and modified. The retval field in the descriptor
3715 * will be set to 0 when RPB is modified.
3716 **/
3717i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3718 struct i40e_asq_cmd_details *cmd_details)
3719{
3720 struct i40e_aq_desc desc;
3721 i40e_status status;
3722
3723 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3724
3725 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3726
3727 return status;
3728}
3729
56a62fc8
JB		 3730/**
3731 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3732 * @hw: pointer to the hw struct
3733 * @seid: seid for the physical port/switching component/vsi
3734 * @buff: Indirect buffer to hold data parameters and response
3735 * @buff_size: Indirect buffer size
3736 * @opcode: Tx scheduler AQ command opcode
3737 * @cmd_details: pointer to command details structure or NULL
3738 *
3739 * Generic command handler for Tx scheduler AQ commands
3740 **/
3741static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3742 void *buff, u16 buff_size,
3743 enum i40e_admin_queue_opc opcode,
3744 struct i40e_asq_cmd_details *cmd_details)
3745{
3746 struct i40e_aq_desc desc;
3747 struct i40e_aqc_tx_sched_ind *cmd =
3748 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3749 i40e_status status;
3750 bool cmd_param_flag = false;
3751
3752 switch (opcode) {
3753 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3754 case i40e_aqc_opc_configure_vsi_tc_bw:
3755 case i40e_aqc_opc_enable_switching_comp_ets:
3756 case i40e_aqc_opc_modify_switching_comp_ets:
3757 case i40e_aqc_opc_disable_switching_comp_ets:
3758 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3759 case i40e_aqc_opc_configure_switching_comp_bw_config:
3760 cmd_param_flag = true;
3761 break;
3762 case i40e_aqc_opc_query_vsi_bw_config:
3763 case i40e_aqc_opc_query_vsi_ets_sla_config:
3764 case i40e_aqc_opc_query_switching_comp_ets_config:
3765 case i40e_aqc_opc_query_port_ets_config:
3766 case i40e_aqc_opc_query_switching_comp_bw_config:
3767 cmd_param_flag = false;
3768 break;
3769 default:
3770 return I40E_ERR_PARAM;
3771 }
3772
3773 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3774
3775 /* Indirect command */
3776 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3777 if (cmd_param_flag)
3778 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3779 if (buff_size > I40E_AQ_LARGE_BUF)
3780 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3781
3782 desc.datalen = cpu_to_le16(buff_size);
3783
3784 cmd->vsi_seid = cpu_to_le16(seid);
3785
3786 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3787
3788 return status;
3789}
3790
6b192891
MW		 3791/**
3792 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3793 * @hw: pointer to the hw struct
3794 * @seid: VSI seid
3795 * @credit: BW limit credits (0 = disabled)
3796 * @max_credit: Max BW limit credits
3797 * @cmd_details: pointer to command details structure or NULL
3798 **/
3799i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3800 u16 seid, u16 credit, u8 max_credit,
3801 struct i40e_asq_cmd_details *cmd_details)
3802{
3803 struct i40e_aq_desc desc;
3804 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3805 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3806 i40e_status status;
3807
3808 i40e_fill_default_direct_cmd_desc(&desc,
3809 i40e_aqc_opc_configure_vsi_bw_limit);
3810
3811 cmd->vsi_seid = cpu_to_le16(seid);
3812 cmd->credit = cpu_to_le16(credit);
3813 cmd->max_credit = max_credit;
3814
3815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3816
3817 return status;
3818}
3819
56a62fc8
JB		 3820/**
3821 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3822 * @hw: pointer to the hw struct
3823 * @seid: VSI seid
3824 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3825 * @cmd_details: pointer to command details structure or NULL
3826 **/
3827i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3828 u16 seid,
3829 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3830 struct i40e_asq_cmd_details *cmd_details)
3831{
3832 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3833 i40e_aqc_opc_configure_vsi_tc_bw,
3834 cmd_details);
3835}
3836
afb3ff0d
NP		 3837/**
3838 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3839 * @hw: pointer to the hw struct
3840 * @seid: seid of the switching component connected to Physical Port
3841 * @ets_data: Buffer holding ETS parameters
3842 * @cmd_details: pointer to command details structure or NULL
3843 **/
3844i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3845 u16 seid,
3846 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3847 enum i40e_admin_queue_opc opcode,
3848 struct i40e_asq_cmd_details *cmd_details)
3849{
3850 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3851 sizeof(*ets_data), opcode, cmd_details);
3852}
3853
3854/**
3855 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3856 * @hw: pointer to the hw struct
3857 * @seid: seid of the switching component
3858 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3859 * @cmd_details: pointer to command details structure or NULL
3860 **/
3861i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3862 u16 seid,
3863 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3864 struct i40e_asq_cmd_details *cmd_details)
3865{
3866 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3867 i40e_aqc_opc_configure_switching_comp_bw_config,
3868 cmd_details);
3869}
3870
56a62fc8
JB		 3871/**
3872 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3873 * @hw: pointer to the hw struct
3874 * @seid: seid of the VSI
3875 * @bw_data: Buffer to hold VSI BW configuration
3876 * @cmd_details: pointer to command details structure or NULL
3877 **/
3878i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3879 u16 seid,
3880 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3881 struct i40e_asq_cmd_details *cmd_details)
3882{
3883 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3884 i40e_aqc_opc_query_vsi_bw_config,
3885 cmd_details);
3886}
3887
3888/**
3889 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3890 * @hw: pointer to the hw struct
3891 * @seid: seid of the VSI
3892 * @bw_data: Buffer to hold VSI BW configuration per TC
3893 * @cmd_details: pointer to command details structure or NULL
3894 **/
3895i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3896 u16 seid,
3897 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3898 struct i40e_asq_cmd_details *cmd_details)
3899{
3900 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3901 i40e_aqc_opc_query_vsi_ets_sla_config,
3902 cmd_details);
3903}
3904
3905/**
3906 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3907 * @hw: pointer to the hw struct
3908 * @seid: seid of the switching component
3909 * @bw_data: Buffer to hold switching component's per TC BW config
3910 * @cmd_details: pointer to command details structure or NULL
3911 **/
3912i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3913 u16 seid,
3914 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3915 struct i40e_asq_cmd_details *cmd_details)
3916{
3917 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3918 i40e_aqc_opc_query_switching_comp_ets_config,
3919 cmd_details);
3920}
3921
3922/**
3923 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3924 * @hw: pointer to the hw struct
3925 * @seid: seid of the VSI or switching component connected to Physical Port
3926 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3927 * @cmd_details: pointer to command details structure or NULL
3928 **/
3929i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3930 u16 seid,
3931 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3932 struct i40e_asq_cmd_details *cmd_details)
3933{
3934 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3935 i40e_aqc_opc_query_port_ets_config,
3936 cmd_details);
3937}
3938
3939/**
3940 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3941 * @hw: pointer to the hw struct
3942 * @seid: seid of the switching component
3943 * @bw_data: Buffer to hold switching component's BW configuration
3944 * @cmd_details: pointer to command details structure or NULL
3945 **/
3946i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3947 u16 seid,
3948 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3949 struct i40e_asq_cmd_details *cmd_details)
3950{
3951 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3952 i40e_aqc_opc_query_switching_comp_bw_config,
3953 cmd_details);
3954}
3955
3956/**
3957 * i40e_validate_filter_settings
3958 * @hw: pointer to the hardware structure
3959 * @settings: Filter control settings
3960 *
3961 * Check and validate the filter control settings passed.
3962 * The function checks for the valid filter/context sizes being
3963 * passed for FCoE and PE.
3964 *
3965 * Returns 0 if the values passed are valid and within
3966 * range else returns an error.
3967 **/
3968static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3969 struct i40e_filter_control_settings *settings)
3970{
3971 u32 fcoe_cntx_size, fcoe_filt_size;
3972 u32 pe_cntx_size, pe_filt_size;
467d729a 3973 u32 fcoe_fmax;
56a62fc8
JB		 3974 u32 val;
3975
3976 /* Validate FCoE settings passed */
3977 switch (settings->fcoe_filt_num) {
3978 case I40E_HASH_FILTER_SIZE_1K:
3979 case I40E_HASH_FILTER_SIZE_2K:
3980 case I40E_HASH_FILTER_SIZE_4K:
3981 case I40E_HASH_FILTER_SIZE_8K:
3982 case I40E_HASH_FILTER_SIZE_16K:
3983 case I40E_HASH_FILTER_SIZE_32K:
3984 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3985 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3986 break;
3987 default:
3988 return I40E_ERR_PARAM;
3989 }
3990
3991 switch (settings->fcoe_cntx_num) {
3992 case I40E_DMA_CNTX_SIZE_512:
3993 case I40E_DMA_CNTX_SIZE_1K:
3994 case I40E_DMA_CNTX_SIZE_2K:
3995 case I40E_DMA_CNTX_SIZE_4K:
3996 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3997 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3998 break;
3999 default:
4000 return I40E_ERR_PARAM;
4001 }
4002
4003 /* Validate PE settings passed */
4004 switch (settings->pe_filt_num) {
4005 case I40E_HASH_FILTER_SIZE_1K:
4006 case I40E_HASH_FILTER_SIZE_2K:
4007 case I40E_HASH_FILTER_SIZE_4K:
4008 case I40E_HASH_FILTER_SIZE_8K:
4009 case I40E_HASH_FILTER_SIZE_16K:
4010 case I40E_HASH_FILTER_SIZE_32K:
4011 case I40E_HASH_FILTER_SIZE_64K:
4012 case I40E_HASH_FILTER_SIZE_128K:
4013 case I40E_HASH_FILTER_SIZE_256K:
4014 case I40E_HASH_FILTER_SIZE_512K:
4015 case I40E_HASH_FILTER_SIZE_1M:
4016 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4017 pe_filt_size <<= (u32)settings->pe_filt_num;
4018 break;
4019 default:
4020 return I40E_ERR_PARAM;
4021 }
4022
4023 switch (settings->pe_cntx_num) {
4024 case I40E_DMA_CNTX_SIZE_512:
4025 case I40E_DMA_CNTX_SIZE_1K:
4026 case I40E_DMA_CNTX_SIZE_2K:
4027 case I40E_DMA_CNTX_SIZE_4K:
4028 case I40E_DMA_CNTX_SIZE_8K:
4029 case I40E_DMA_CNTX_SIZE_16K:
4030 case I40E_DMA_CNTX_SIZE_32K:
4031 case I40E_DMA_CNTX_SIZE_64K:
4032 case I40E_DMA_CNTX_SIZE_128K:
4033 case I40E_DMA_CNTX_SIZE_256K:
4034 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4035 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4036 break;
4037 default:
4038 return I40E_ERR_PARAM;
4039 }
4040
4041 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4042 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4043 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4044 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4045 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4046 return I40E_ERR_INVALID_SIZE;
4047
56a62fc8
JB		 4048 return 0;
4049}
4050
4051/**
4052 * i40e_set_filter_control
4053 * @hw: pointer to the hardware structure
4054 * @settings: Filter control settings
4055 *
4056 * Set the Queue Filters for PE/FCoE and enable filters required
4057 * for a single PF. It is expected that these settings are programmed
4058 * at the driver initialization time.
4059 **/
4060i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4061 struct i40e_filter_control_settings *settings)
4062{
4063 i40e_status ret = 0;
4064 u32 hash_lut_size = 0;
4065 u32 val;
4066
4067 if (!settings)
4068 return I40E_ERR_PARAM;
4069
4070 /* Validate the input settings */
4071 ret = i40e_validate_filter_settings(hw, settings);
4072 if (ret)
4073 return ret;
4074
4075 /* Read the PF Queue Filter control register */
f658137c 4076 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
56a62fc8
JB		 4077
4078 /* Program required PE hash buckets for the PF */
4079 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4080 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4081 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4082 /* Program required PE contexts for the PF */
4083 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4084 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4085 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4086
4087 /* Program required FCoE hash buckets for the PF */
4088 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4089 val |= ((u32)settings->fcoe_filt_num <<
4090 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4091 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4092 /* Program required FCoE DDP contexts for the PF */
4093 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4094 val |= ((u32)settings->fcoe_cntx_num <<
4095 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4096 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4097
4098 /* Program Hash LUT size for the PF */
4099 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4100 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4101 hash_lut_size = 1;
4102 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4103 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4104
4105 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4106 if (settings->enable_fdir)
4107 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4108 if (settings->enable_ethtype)
4109 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4110 if (settings->enable_macvlan)
4111 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4112
f658137c 4113 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
56a62fc8
JB		 4114
4115 return 0;
4116}
afb3ff0d
NP		 4117
4118/**
4119 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4120 * @hw: pointer to the hw struct
4121 * @mac_addr: MAC address to use in the filter
4122 * @ethtype: Ethertype to use in the filter
4123 * @flags: Flags that needs to be applied to the filter
4124 * @vsi_seid: seid of the control VSI
4125 * @queue: VSI queue number to send the packet to
4126 * @is_add: Add control packet filter if True else remove
4127 * @stats: Structure to hold information on control filter counts
4128 * @cmd_details: pointer to command details structure or NULL
4129 *
4130 * This command will Add or Remove control packet filter for a control VSI.
4131 * In return it will update the total number of perfect filter count in
4132 * the stats member.
4133 **/
4134i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4135 u8 *mac_addr, u16 ethtype, u16 flags,
4136 u16 vsi_seid, u16 queue, bool is_add,
4137 struct i40e_control_filter_stats *stats,
4138 struct i40e_asq_cmd_details *cmd_details)
4139{
4140 struct i40e_aq_desc desc;
4141 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4142 (struct i40e_aqc_add_remove_control_packet_filter *)
4143 &desc.params.raw;
4144 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4145 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4146 &desc.params.raw;
4147 i40e_status status;
4148
4149 if (vsi_seid == 0)
4150 return I40E_ERR_PARAM;
4151
4152 if (is_add) {
4153 i40e_fill_default_direct_cmd_desc(&desc,
4154 i40e_aqc_opc_add_control_packet_filter);
4155 cmd->queue = cpu_to_le16(queue);
4156 } else {
4157 i40e_fill_default_direct_cmd_desc(&desc,
4158 i40e_aqc_opc_remove_control_packet_filter);
4159 }
4160
4161 if (mac_addr)
6995b36c 4162 ether_addr_copy(cmd->mac, mac_addr);
afb3ff0d
NP		 4163
4164 cmd->etype = cpu_to_le16(ethtype);
4165 cmd->flags = cpu_to_le16(flags);
4166 cmd->seid = cpu_to_le16(vsi_seid);
4167
4168 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4169
4170 if (!status && stats) {
4171 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4172 stats->etype_used = le16_to_cpu(resp->etype_used);
4173 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4174 stats->etype_free = le16_to_cpu(resp->etype_free);
4175 }
4176
4177 return status;
4178}
4179
e7358f54
ASJ		 4180/**
4181 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4182 * @hw: pointer to the hw struct
4183 * @seid: VSI seid to add ethertype filter from
4184 **/
4185#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4186void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4187 u16 seid)
4188{
4189 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4190 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4191 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4192 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4193 i40e_status status;
4194
4195 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4196 seid, 0, true, NULL,
4197 NULL);
4198 if (status)
4199 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4200}
4201
f4492db1
GR		 4202/**
4203 * i40e_aq_alternate_read
4204 * @hw: pointer to the hardware structure
4205 * @reg_addr0: address of first dword to be read
4206 * @reg_val0: pointer for data read from 'reg_addr0'
4207 * @reg_addr1: address of second dword to be read
4208 * @reg_val1: pointer for data read from 'reg_addr1'
4209 *
4210 * Read one or two dwords from alternate structure. Fields are indicated
4211 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4212 * is not passed then only register at 'reg_addr0' is read.
4213 *
4214 **/
37a2973a
SN		 4215static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4216 u32 reg_addr0, u32 *reg_val0,
4217 u32 reg_addr1, u32 *reg_val1)
f4492db1
GR		 4218{
4219 struct i40e_aq_desc desc;
4220 struct i40e_aqc_alternate_write *cmd_resp =
4221 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4222 i40e_status status;
4223
4224 if (!reg_val0)
4225 return I40E_ERR_PARAM;
4226
4227 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4228 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4229 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4230
4231 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4232
4233 if (!status) {
4234 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4235
4236 if (reg_val1)
4237 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4238 }
4239
4240 return status;
4241}
4242
2fd75f31
NP		 4243/**
4244 * i40e_aq_resume_port_tx
4245 * @hw: pointer to the hardware structure
4246 * @cmd_details: pointer to command details structure or NULL
4247 *
4248 * Resume port's Tx traffic
4249 **/
4250i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4251 struct i40e_asq_cmd_details *cmd_details)
4252{
4253 struct i40e_aq_desc desc;
4254 i40e_status status;
4255
4256 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4257
4258 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4259
4260 return status;
4261}
4262
d4dfb81a
CS		 4263/**
4264 * i40e_set_pci_config_data - store PCI bus info
4265 * @hw: pointer to hardware structure
4266 * @link_status: the link status word from PCI config space
4267 *
4268 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4269 **/
4270void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4271{
4272 hw->bus.type = i40e_bus_type_pci_express;
4273
4274 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4275 case PCI_EXP_LNKSTA_NLW_X1:
4276 hw->bus.width = i40e_bus_width_pcie_x1;
4277 break;
4278 case PCI_EXP_LNKSTA_NLW_X2:
4279 hw->bus.width = i40e_bus_width_pcie_x2;
4280 break;
4281 case PCI_EXP_LNKSTA_NLW_X4:
4282 hw->bus.width = i40e_bus_width_pcie_x4;
4283 break;
4284 case PCI_EXP_LNKSTA_NLW_X8:
4285 hw->bus.width = i40e_bus_width_pcie_x8;
4286 break;
4287 default:
4288 hw->bus.width = i40e_bus_width_unknown;
4289 break;
4290 }
4291
4292 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4293 case PCI_EXP_LNKSTA_CLS_2_5GB:
4294 hw->bus.speed = i40e_bus_speed_2500;
4295 break;
4296 case PCI_EXP_LNKSTA_CLS_5_0GB:
4297 hw->bus.speed = i40e_bus_speed_5000;
4298 break;
4299 case PCI_EXP_LNKSTA_CLS_8_0GB:
4300 hw->bus.speed = i40e_bus_speed_8000;
4301 break;
4302 default:
4303 hw->bus.speed = i40e_bus_speed_unknown;
4304 break;
4305 }
4306}
f4492db1 4307
3169c323
JB		 4308/**
4309 * i40e_aq_debug_dump
4310 * @hw: pointer to the hardware structure
4311 * @cluster_id: specific cluster to dump
4312 * @table_id: table id within cluster
4313 * @start_index: index of line in the block to read
4314 * @buff_size: dump buffer size
4315 * @buff: dump buffer
4316 * @ret_buff_size: actual buffer size returned
4317 * @ret_next_table: next block to read
4318 * @ret_next_index: next index to read
4319 *
4320 * Dump internal FW/HW data for debug purposes.
4321 *
4322 **/
4323i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4324 u8 table_id, u32 start_index, u16 buff_size,
4325 void *buff, u16 *ret_buff_size,
4326 u8 *ret_next_table, u32 *ret_next_index,
4327 struct i40e_asq_cmd_details *cmd_details)
4328{
4329 struct i40e_aq_desc desc;
4330 struct i40e_aqc_debug_dump_internals *cmd =
4331 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4332 struct i40e_aqc_debug_dump_internals *resp =
4333 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4334 i40e_status status;
4335
4336 if (buff_size == 0 || !buff)
4337 return I40E_ERR_PARAM;
4338
4339 i40e_fill_default_direct_cmd_desc(&desc,
4340 i40e_aqc_opc_debug_dump_internals);
4341 /* Indirect Command */
4342 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4343 if (buff_size > I40E_AQ_LARGE_BUF)
4344 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4345
4346 cmd->cluster_id = cluster_id;
4347 cmd->table_id = table_id;
4348 cmd->idx = cpu_to_le32(start_index);
4349
4350 desc.datalen = cpu_to_le16(buff_size);
4351
4352 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4353 if (!status) {
4354 if (ret_buff_size)
4355 *ret_buff_size = le16_to_cpu(desc.datalen);
4356 if (ret_next_table)
4357 *ret_next_table = resp->table_id;
4358 if (ret_next_index)
4359 *ret_next_index = le32_to_cpu(resp->idx);
4360 }
4361
4362 return status;
4363}
4364
f4492db1
GR		 4365/**
4366 * i40e_read_bw_from_alt_ram
4367 * @hw: pointer to the hardware structure
4368 * @max_bw: pointer for max_bw read
4369 * @min_bw: pointer for min_bw read
4370 * @min_valid: pointer for bool that is true if min_bw is a valid value
4371 * @max_valid: pointer for bool that is true if max_bw is a valid value
4372 *
4373 * Read bw from the alternate ram for the given pf
4374 **/
4375i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4376 u32 *max_bw, u32 *min_bw,
4377 bool *min_valid, bool *max_valid)
4378{
4379 i40e_status status;
4380 u32 max_bw_addr, min_bw_addr;
4381
4382 /* Calculate the address of the min/max bw registers */
4383 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4384 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4385 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4386 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4387 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4388 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4389
4390 /* Read the bandwidths from alt ram */
4391 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4392 min_bw_addr, min_bw);
4393
4394 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4395 *min_valid = true;
4396 else
4397 *min_valid = false;
4398
4399 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4400 *max_valid = true;
4401 else
4402 *max_valid = false;
4403
4404 return status;
4405}
4406
4407/**
4408 * i40e_aq_configure_partition_bw
4409 * @hw: pointer to the hardware structure
4410 * @bw_data: Buffer holding valid pfs and bw limits
4411 * @cmd_details: pointer to command details
4412 *
4413 * Configure partitions guaranteed/max bw
4414 **/
4415i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4416 struct i40e_aqc_configure_partition_bw_data *bw_data,
4417 struct i40e_asq_cmd_details *cmd_details)
4418{
4419 i40e_status status;
4420 struct i40e_aq_desc desc;
4421 u16 bwd_size = sizeof(*bw_data);
4422
4423 i40e_fill_default_direct_cmd_desc(&desc,
4424 i40e_aqc_opc_configure_partition_bw);
4425
4426 /* Indirect command */
4427 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4428 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4429
4430 if (bwd_size > I40E_AQ_LARGE_BUF)
4431 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4432
4433 desc.datalen = cpu_to_le16(bwd_size);
4434
4435 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4436 cmd_details);
4437
4438 return status;
4439}
fd077cd3
CW		 4440
4441/**
91dc1e5d
MK		 4442 * i40e_read_phy_register_clause22
4443 * @hw: pointer to the HW structure
4444 * @reg: register address in the page
4445 * @phy_adr: PHY address on MDIO interface
4446 * @value: PHY register value
4447 *
4448 * Reads specified PHY register value
4449 **/
4450i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4451 u16 reg, u8 phy_addr, u16 *value)
4452{
4453 i40e_status status = I40E_ERR_TIMEOUT;
4454 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4455 u32 command = 0;
4456 u16 retry = 1000;
4457
4458 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4459 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4460 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4461 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4462 (I40E_GLGEN_MSCA_MDICMD_MASK);
4463 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4464 do {
4465 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4466 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4467 status = 0;
4468 break;
4469 }
4470 udelay(10);
4471 retry--;
4472 } while (retry);
4473
4474 if (status) {
4475 i40e_debug(hw, I40E_DEBUG_PHY,
4476 "PHY: Can't write command to external PHY.\n");
27e5f25b 4477 } else {
91dc1e5d
MK		 4478 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4479 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4480 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
91dc1e5d
MK		 4481 }
4482
91dc1e5d
MK		 4483 return status;
4484}
4485
4486/**
4487 * i40e_write_phy_register_clause22
4488 * @hw: pointer to the HW structure
4489 * @reg: register address in the page
4490 * @phy_adr: PHY address on MDIO interface
4491 * @value: PHY register value
4492 *
4493 * Writes specified PHY register value
4494 **/
4495i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4496 u16 reg, u8 phy_addr, u16 value)
4497{
4498 i40e_status status = I40E_ERR_TIMEOUT;
4499 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4500 u32 command = 0;
4501 u16 retry = 1000;
4502
4503 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4504 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4505
4506 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4507 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4508 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4509 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4510 (I40E_GLGEN_MSCA_MDICMD_MASK);
4511
4512 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4513 do {
4514 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4515 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4516 status = 0;
4517 break;
4518 }
4519 udelay(10);
4520 retry--;
4521 } while (retry);
4522
4523 return status;
4524}
4525
4526/**
4527 * i40e_read_phy_register_clause45
fd077cd3
CW		 4528 * @hw: pointer to the HW structure
4529 * @page: registers page number
4530 * @reg: register address in the page
4531 * @phy_adr: PHY address on MDIO interface
4532 * @value: PHY register value
4533 *
4534 * Reads specified PHY register value
4535 **/
91dc1e5d
MK		 4536i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4537 u8 page, u16 reg, u8 phy_addr, u16 *value)
fd077cd3
CW		 4538{
4539 i40e_status status = I40E_ERR_TIMEOUT;
4540 u32 command = 0;
4541 u16 retry = 1000;
4542 u8 port_num = hw->func_caps.mdio_port_num;
4543
4544 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4545 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4546 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
91dc1e5d
MK		 4547 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4548 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
fd077cd3
CW		 4549 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4550 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4551 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4552 do {
4553 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4554 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4555 status = 0;
4556 break;
4557 }
4558 usleep_range(10, 20);
4559 retry--;
4560 } while (retry);
4561
4562 if (status) {
4563 i40e_debug(hw, I40E_DEBUG_PHY,
4564 "PHY: Can't write command to external PHY.\n");
4565 goto phy_read_end;
4566 }
4567
4568 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4569 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
91dc1e5d
MK		 4570 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4571 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
fd077cd3
CW		 4572 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4573 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4574 status = I40E_ERR_TIMEOUT;
4575 retry = 1000;
4576 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4577 do {
4578 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4579 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4580 status = 0;
4581 break;
4582 }
4583 usleep_range(10, 20);
4584 retry--;
4585 } while (retry);
4586
4587 if (!status) {
4588 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4589 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4590 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4591 } else {
4592 i40e_debug(hw, I40E_DEBUG_PHY,
4593 "PHY: Can't read register value from external PHY.\n");
4594 }
4595
4596phy_read_end:
4597 return status;
4598}
4599
4600/**
91dc1e5d 4601 * i40e_write_phy_register_clause45
fd077cd3
CW		 4602 * @hw: pointer to the HW structure
4603 * @page: registers page number
4604 * @reg: register address in the page
4605 * @phy_adr: PHY address on MDIO interface
4606 * @value: PHY register value
4607 *
4608 * Writes value to specified PHY register
4609 **/
91dc1e5d
MK		 4610i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4611 u8 page, u16 reg, u8 phy_addr, u16 value)
fd077cd3
CW		 4612{
4613 i40e_status status = I40E_ERR_TIMEOUT;
4614 u32 command = 0;
4615 u16 retry = 1000;
4616 u8 port_num = hw->func_caps.mdio_port_num;
4617
4618 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4619 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4620 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
91dc1e5d
MK		 4621 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4622 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
fd077cd3
CW		 4623 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4624 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4625 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4626 do {
4627 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4628 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4629 status = 0;
4630 break;
4631 }
4632 usleep_range(10, 20);
4633 retry--;
4634 } while (retry);
4635 if (status) {
4636 i40e_debug(hw, I40E_DEBUG_PHY,
4637 "PHY: Can't write command to external PHY.\n");
4638 goto phy_write_end;
4639 }
4640
4641 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4642 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4643
4644 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4645 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
91dc1e5d
MK		 4646 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4647 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
fd077cd3
CW		 4648 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4649 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4650 status = I40E_ERR_TIMEOUT;
4651 retry = 1000;
4652 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4653 do {
4654 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4655 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4656 status = 0;
4657 break;
4658 }
4659 usleep_range(10, 20);
4660 retry--;
4661 } while (retry);
4662
4663phy_write_end:
4664 return status;
4665}
4666
4667/**
4668 * i40e_get_phy_address
4669 * @hw: pointer to the HW structure
4670 * @dev_num: PHY port num that address we want
4671 * @phy_addr: Returned PHY address
4672 *
4673 * Gets PHY address for current port
4674 **/
4675u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4676{
4677 u8 port_num = hw->func_caps.mdio_port_num;
4678 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4679
4680 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4681}
4682
4683/**
4684 * i40e_blink_phy_led
4685 * @hw: pointer to the HW structure
4686 * @time: time how long led will blinks in secs
4687 * @interval: gap between LED on and off in msecs
4688 *
4689 * Blinks PHY link LED
4690 **/
4691i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4692 u32 time, u32 interval)
4693{
4694 i40e_status status = 0;
4695 u32 i;
4696 u16 led_ctl;
4697 u16 gpio_led_port;
4698 u16 led_reg;
4699 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4700 u8 phy_addr = 0;
4701 u8 port_num;
4702
4703 i = rd32(hw, I40E_PFGEN_PORTNUM);
4704 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4705 phy_addr = i40e_get_phy_address(hw, port_num);
4706
4707 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4708 led_addr++) {
91dc1e5d
MK		 4709 status = i40e_read_phy_register_clause45(hw,
4710 I40E_PHY_COM_REG_PAGE,
4711 led_addr, phy_addr,
4712 &led_reg);
fd077cd3
CW		 4713 if (status)
4714 goto phy_blinking_end;
4715 led_ctl = led_reg;
4716 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4717 led_reg = 0;
91dc1e5d 4718 status = i40e_write_phy_register_clause45(hw,
fd077cd3
CW		 4719 I40E_PHY_COM_REG_PAGE,
4720 led_addr, phy_addr,
4721 led_reg);
4722 if (status)
4723 goto phy_blinking_end;
4724 break;
4725 }
4726 }
4727
4728 if (time > 0 && interval > 0) {
4729 for (i = 0; i < time * 1000; i += interval) {
91dc1e5d
MK		 4730 status = i40e_read_phy_register_clause45(hw,
4731 I40E_PHY_COM_REG_PAGE,
4732 led_addr, phy_addr, &led_reg);
fd077cd3
CW		 4733 if (status)
4734 goto restore_config;
4735 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4736 led_reg = 0;
4737 else
4738 led_reg = I40E_PHY_LED_MANUAL_ON;
91dc1e5d
MK		 4739 status = i40e_write_phy_register_clause45(hw,
4740 I40E_PHY_COM_REG_PAGE,
4741 led_addr, phy_addr, led_reg);
fd077cd3
CW		 4742 if (status)
4743 goto restore_config;
4744 msleep(interval);
4745 }
4746 }
4747
4748restore_config:
91dc1e5d
MK		 4749 status = i40e_write_phy_register_clause45(hw,
4750 I40E_PHY_COM_REG_PAGE,
4751 led_addr, phy_addr, led_ctl);
fd077cd3
CW		 4752
4753phy_blinking_end:
4754 return status;
4755}
4756
4757/**
4758 * i40e_led_get_phy - return current on/off mode
4759 * @hw: pointer to the hw struct
4760 * @led_addr: address of led register to use
4761 * @val: original value of register to use
4762 *
4763 **/
4764i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4765 u16 *val)
4766{
4767 i40e_status status = 0;
4768 u16 gpio_led_port;
4769 u8 phy_addr = 0;
4770 u16 reg_val;
4771 u16 temp_addr;
4772 u8 port_num;
4773 u32 i;
4774
4775 temp_addr = I40E_PHY_LED_PROV_REG_1;
4776 i = rd32(hw, I40E_PFGEN_PORTNUM);
4777 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4778 phy_addr = i40e_get_phy_address(hw, port_num);
4779
4780 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4781 temp_addr++) {
91dc1e5d
MK		 4782 status = i40e_read_phy_register_clause45(hw,
4783 I40E_PHY_COM_REG_PAGE,
4784 temp_addr, phy_addr,
4785 &reg_val);
fd077cd3
CW		 4786 if (status)
4787 return status;
4788 *val = reg_val;
4789 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4790 *led_addr = temp_addr;
4791 break;
4792 }
4793 }
4794 return status;
4795}
4796
4797/**
4798 * i40e_led_set_phy
4799 * @hw: pointer to the HW structure
4800 * @on: true or false
4801 * @mode: original val plus bit for set or ignore
4802 * Set led's on or off when controlled by the PHY
4803 *
4804 **/
4805i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4806 u16 led_addr, u32 mode)
4807{
4808 i40e_status status = 0;
4809 u16 led_ctl = 0;
4810 u16 led_reg = 0;
4811 u8 phy_addr = 0;
4812 u8 port_num;
4813 u32 i;
4814
4815 i = rd32(hw, I40E_PFGEN_PORTNUM);
4816 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4817 phy_addr = i40e_get_phy_address(hw, port_num);
91dc1e5d
MK		 4818 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4819 led_addr, phy_addr, &led_reg);
fd077cd3
CW		 4820 if (status)
4821 return status;
4822 led_ctl = led_reg;
4823 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4824 led_reg = 0;
91dc1e5d
MK		 4825 status = i40e_write_phy_register_clause45(hw,
4826 I40E_PHY_COM_REG_PAGE,
4827 led_addr, phy_addr,
4828 led_reg);
fd077cd3
CW		 4829 if (status)
4830 return status;
4831 }
91dc1e5d
MK		 4832 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4833 led_addr, phy_addr, &led_reg);
fd077cd3
CW		 4834 if (status)
4835 goto restore_config;
4836 if (on)
4837 led_reg = I40E_PHY_LED_MANUAL_ON;
4838 else
4839 led_reg = 0;
91dc1e5d
MK		 4840 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4841 led_addr, phy_addr, led_reg);
fd077cd3
CW		 4842 if (status)
4843 goto restore_config;
4844 if (mode & I40E_PHY_LED_MODE_ORIG) {
4845 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
91dc1e5d 4846 status = i40e_write_phy_register_clause45(hw,
fd077cd3
CW		 4847 I40E_PHY_COM_REG_PAGE,
4848 led_addr, phy_addr, led_ctl);
4849 }
4850 return status;
4851restore_config:
91dc1e5d
MK		 4852 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4853 led_addr, phy_addr, led_ctl);
fd077cd3
CW		 4854 return status;
4855}
f658137c
SN		 4856
4857/**
4858 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4859 * @hw: pointer to the hw struct
4860 * @reg_addr: register address
4861 * @reg_val: ptr to register value
4862 * @cmd_details: pointer to command details structure or NULL
4863 *
4864 * Use the firmware to read the Rx control register,
4865 * especially useful if the Rx unit is under heavy pressure
4866 **/
4867i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4868 u32 reg_addr, u32 *reg_val,
4869 struct i40e_asq_cmd_details *cmd_details)
4870{
4871 struct i40e_aq_desc desc;
4872 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4873 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4874 i40e_status status;
4875
4876 if (!reg_val)
4877 return I40E_ERR_PARAM;
4878
4879 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4880
4881 cmd_resp->address = cpu_to_le32(reg_addr);
4882
4883 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4884
4885 if (status == 0)
4886 *reg_val = le32_to_cpu(cmd_resp->value);
4887
4888 return status;
4889}
4890
4891/**
4892 * i40e_read_rx_ctl - read from an Rx control register
4893 * @hw: pointer to the hw struct
4894 * @reg_addr: register address
4895 **/
4896u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4897{
4898 i40e_status status = 0;
4899 bool use_register;
4900 int retry = 5;
4901 u32 val = 0;
4902
4903 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4904 if (!use_register) {
4905do_retry:
4906 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4907 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4908 usleep_range(1000, 2000);
4909 retry--;
4910 goto do_retry;
4911 }
4912 }
4913
4914 /* if the AQ access failed, try the old-fashioned way */
4915 if (status || use_register)
4916 val = rd32(hw, reg_addr);
4917
4918 return val;
4919}
4920
4921/**
4922 * i40e_aq_rx_ctl_write_register
4923 * @hw: pointer to the hw struct
4924 * @reg_addr: register address
4925 * @reg_val: register value
4926 * @cmd_details: pointer to command details structure or NULL
4927 *
4928 * Use the firmware to write to an Rx control register,
4929 * especially useful if the Rx unit is under heavy pressure
4930 **/
4931i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4932 u32 reg_addr, u32 reg_val,
4933 struct i40e_asq_cmd_details *cmd_details)
4934{
4935 struct i40e_aq_desc desc;
4936 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4937 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4938 i40e_status status;
4939
4940 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4941
4942 cmd->address = cpu_to_le32(reg_addr);
4943 cmd->value = cpu_to_le32(reg_val);
4944
4945 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4946
4947 return status;
4948}
4949
4950/**
4951 * i40e_write_rx_ctl - write to an Rx control register
4952 * @hw: pointer to the hw struct
4953 * @reg_addr: register address
4954 * @reg_val: register value
4955 **/
4956void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4957{
4958 i40e_status status = 0;
4959 bool use_register;
4960 int retry = 5;
4961
4962 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4963 if (!use_register) {
4964do_retry:
4965 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4966 reg_val, NULL);
4967 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4968 usleep_range(1000, 2000);
4969 retry--;
4970 goto do_retry;
4971 }
4972 }
4973
4974 /* if the AQ access failed, try the old-fashioned way */
4975 if (status || use_register)
4976 wr32(hw, reg_addr, reg_val);
4977}
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