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41c445ff JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
2818ccd9 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
41c445ff JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
41c445ff JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
b499ffb0 SV |
27 | #include <linux/etherdevice.h> |
28 | #include <linux/of_net.h> | |
29 | #include <linux/pci.h> | |
30 | ||
41c445ff JB |
31 | /* Local includes */ |
32 | #include "i40e.h" | |
4eb3f768 | 33 | #include "i40e_diag.h" |
06a5f7f1 | 34 | #include <net/udp_tunnel.h> |
41c445ff JB |
35 | |
36 | const char i40e_driver_name[] = "i40e"; | |
37 | static const char i40e_driver_string[] = | |
38 | "Intel(R) Ethernet Connection XL710 Network Driver"; | |
39 | ||
40 | #define DRV_KERN "-k" | |
41 | ||
e8e724db | 42 | #define DRV_VERSION_MAJOR 1 |
07061958 | 43 | #define DRV_VERSION_MINOR 6 |
cf465fe7 | 44 | #define DRV_VERSION_BUILD 21 |
41c445ff JB |
45 | #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ |
46 | __stringify(DRV_VERSION_MINOR) "." \ | |
47 | __stringify(DRV_VERSION_BUILD) DRV_KERN | |
48 | const char i40e_driver_version_str[] = DRV_VERSION; | |
8fb905b3 | 49 | static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation."; |
41c445ff JB |
50 | |
51 | /* a bit of forward declarations */ | |
52 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi); | |
53 | static void i40e_handle_reset_warning(struct i40e_pf *pf); | |
54 | static int i40e_add_vsi(struct i40e_vsi *vsi); | |
55 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi); | |
bc7d338f | 56 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit); |
41c445ff JB |
57 | static int i40e_setup_misc_vector(struct i40e_pf *pf); |
58 | static void i40e_determine_queue_usage(struct i40e_pf *pf); | |
59 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf); | |
cbf61325 | 60 | static void i40e_fdir_sb_setup(struct i40e_pf *pf); |
4e3b35b0 | 61 | static int i40e_veb_get_bw_info(struct i40e_veb *veb); |
41c445ff JB |
62 | |
63 | /* i40e_pci_tbl - PCI Device ID Table | |
64 | * | |
65 | * Last entry must be all 0s | |
66 | * | |
67 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
68 | * Class, Class Mask, private data (not used) } | |
69 | */ | |
9baa3c34 | 70 | static const struct pci_device_id i40e_pci_tbl[] = { |
ab60085e | 71 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0}, |
ab60085e | 72 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0}, |
ab60085e SN |
73 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0}, |
74 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0}, | |
ab60085e SN |
75 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, |
76 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, | |
77 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, | |
5960d33f | 78 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, |
bc5166b9 | 79 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, |
ae24b409 | 80 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
35dae51d ASJ |
81 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0}, |
82 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0}, | |
87e6c1d7 ASJ |
83 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0}, |
84 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0}, | |
85 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0}, | |
d6bf58c2 | 86 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0}, |
48a3b512 SN |
87 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
88 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0}, | |
41c445ff JB |
89 | /* required last entry */ |
90 | {0, } | |
91 | }; | |
92 | MODULE_DEVICE_TABLE(pci, i40e_pci_tbl); | |
93 | ||
94 | #define I40E_MAX_VF_COUNT 128 | |
95 | static int debug = -1; | |
5d4ca23e AD |
96 | module_param(debug, uint, 0); |
97 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX)"); | |
41c445ff JB |
98 | |
99 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
100 | MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); | |
101 | MODULE_LICENSE("GPL"); | |
102 | MODULE_VERSION(DRV_VERSION); | |
103 | ||
2803b16c JB |
104 | static struct workqueue_struct *i40e_wq; |
105 | ||
41c445ff JB |
106 | /** |
107 | * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code | |
108 | * @hw: pointer to the HW structure | |
109 | * @mem: ptr to mem struct to fill out | |
110 | * @size: size of memory requested | |
111 | * @alignment: what to align the allocation to | |
112 | **/ | |
113 | int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem, | |
114 | u64 size, u32 alignment) | |
115 | { | |
116 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
117 | ||
118 | mem->size = ALIGN(size, alignment); | |
119 | mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size, | |
120 | &mem->pa, GFP_KERNEL); | |
93bc73b8 JB |
121 | if (!mem->va) |
122 | return -ENOMEM; | |
41c445ff | 123 | |
93bc73b8 | 124 | return 0; |
41c445ff JB |
125 | } |
126 | ||
127 | /** | |
128 | * i40e_free_dma_mem_d - OS specific memory free for shared code | |
129 | * @hw: pointer to the HW structure | |
130 | * @mem: ptr to mem struct to free | |
131 | **/ | |
132 | int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem) | |
133 | { | |
134 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
135 | ||
136 | dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa); | |
137 | mem->va = NULL; | |
138 | mem->pa = 0; | |
139 | mem->size = 0; | |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
144 | /** | |
145 | * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code | |
146 | * @hw: pointer to the HW structure | |
147 | * @mem: ptr to mem struct to fill out | |
148 | * @size: size of memory requested | |
149 | **/ | |
150 | int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem, | |
151 | u32 size) | |
152 | { | |
153 | mem->size = size; | |
154 | mem->va = kzalloc(size, GFP_KERNEL); | |
155 | ||
93bc73b8 JB |
156 | if (!mem->va) |
157 | return -ENOMEM; | |
41c445ff | 158 | |
93bc73b8 | 159 | return 0; |
41c445ff JB |
160 | } |
161 | ||
162 | /** | |
163 | * i40e_free_virt_mem_d - OS specific memory free for shared code | |
164 | * @hw: pointer to the HW structure | |
165 | * @mem: ptr to mem struct to free | |
166 | **/ | |
167 | int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem) | |
168 | { | |
169 | /* it's ok to kfree a NULL pointer */ | |
170 | kfree(mem->va); | |
171 | mem->va = NULL; | |
172 | mem->size = 0; | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | /** | |
178 | * i40e_get_lump - find a lump of free generic resource | |
179 | * @pf: board private structure | |
180 | * @pile: the pile of resource to search | |
181 | * @needed: the number of items needed | |
182 | * @id: an owner id to stick on the items assigned | |
183 | * | |
184 | * Returns the base item index of the lump, or negative for error | |
185 | * | |
186 | * The search_hint trick and lack of advanced fit-finding only work | |
187 | * because we're highly likely to have all the same size lump requests. | |
188 | * Linear search time and any fragmentation should be minimal. | |
189 | **/ | |
190 | static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile, | |
191 | u16 needed, u16 id) | |
192 | { | |
193 | int ret = -ENOMEM; | |
ddf434ac | 194 | int i, j; |
41c445ff JB |
195 | |
196 | if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) { | |
197 | dev_info(&pf->pdev->dev, | |
198 | "param err: pile=%p needed=%d id=0x%04x\n", | |
199 | pile, needed, id); | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
203 | /* start the linear search with an imperfect hint */ | |
204 | i = pile->search_hint; | |
ddf434ac | 205 | while (i < pile->num_entries) { |
41c445ff JB |
206 | /* skip already allocated entries */ |
207 | if (pile->list[i] & I40E_PILE_VALID_BIT) { | |
208 | i++; | |
209 | continue; | |
210 | } | |
211 | ||
212 | /* do we have enough in this lump? */ | |
213 | for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) { | |
214 | if (pile->list[i+j] & I40E_PILE_VALID_BIT) | |
215 | break; | |
216 | } | |
217 | ||
218 | if (j == needed) { | |
219 | /* there was enough, so assign it to the requestor */ | |
220 | for (j = 0; j < needed; j++) | |
221 | pile->list[i+j] = id | I40E_PILE_VALID_BIT; | |
222 | ret = i; | |
223 | pile->search_hint = i + j; | |
ddf434ac | 224 | break; |
41c445ff | 225 | } |
6995b36c JB |
226 | |
227 | /* not enough, so skip over it and continue looking */ | |
228 | i += j; | |
41c445ff JB |
229 | } |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
234 | /** | |
235 | * i40e_put_lump - return a lump of generic resource | |
236 | * @pile: the pile of resource to search | |
237 | * @index: the base item index | |
238 | * @id: the owner id of the items assigned | |
239 | * | |
240 | * Returns the count of items in the lump | |
241 | **/ | |
242 | static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id) | |
243 | { | |
244 | int valid_id = (id | I40E_PILE_VALID_BIT); | |
245 | int count = 0; | |
246 | int i; | |
247 | ||
248 | if (!pile || index >= pile->num_entries) | |
249 | return -EINVAL; | |
250 | ||
251 | for (i = index; | |
252 | i < pile->num_entries && pile->list[i] == valid_id; | |
253 | i++) { | |
254 | pile->list[i] = 0; | |
255 | count++; | |
256 | } | |
257 | ||
258 | if (count && index < pile->search_hint) | |
259 | pile->search_hint = index; | |
260 | ||
261 | return count; | |
262 | } | |
263 | ||
fdf0e0bf ASJ |
264 | /** |
265 | * i40e_find_vsi_from_id - searches for the vsi with the given id | |
266 | * @pf - the pf structure to search for the vsi | |
267 | * @id - id of the vsi it is searching for | |
268 | **/ | |
269 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id) | |
270 | { | |
271 | int i; | |
272 | ||
273 | for (i = 0; i < pf->num_alloc_vsi; i++) | |
274 | if (pf->vsi[i] && (pf->vsi[i]->id == id)) | |
275 | return pf->vsi[i]; | |
276 | ||
277 | return NULL; | |
278 | } | |
279 | ||
41c445ff JB |
280 | /** |
281 | * i40e_service_event_schedule - Schedule the service task to wake up | |
282 | * @pf: board private structure | |
283 | * | |
284 | * If not already scheduled, this puts the task into the work queue | |
285 | **/ | |
e3219ce6 | 286 | void i40e_service_event_schedule(struct i40e_pf *pf) |
41c445ff JB |
287 | { |
288 | if (!test_bit(__I40E_DOWN, &pf->state) && | |
289 | !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) && | |
290 | !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state)) | |
2803b16c | 291 | queue_work(i40e_wq, &pf->service_task); |
41c445ff JB |
292 | } |
293 | ||
294 | /** | |
295 | * i40e_tx_timeout - Respond to a Tx Hang | |
296 | * @netdev: network interface device structure | |
297 | * | |
298 | * If any port has noticed a Tx timeout, it is likely that the whole | |
299 | * device is munged, not just the one netdev port, so go for the full | |
300 | * reset. | |
301 | **/ | |
38e00438 VD |
302 | #ifdef I40E_FCOE |
303 | void i40e_tx_timeout(struct net_device *netdev) | |
304 | #else | |
41c445ff | 305 | static void i40e_tx_timeout(struct net_device *netdev) |
38e00438 | 306 | #endif |
41c445ff JB |
307 | { |
308 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
309 | struct i40e_vsi *vsi = np->vsi; | |
310 | struct i40e_pf *pf = vsi->back; | |
b03a8c1f KP |
311 | struct i40e_ring *tx_ring = NULL; |
312 | unsigned int i, hung_queue = 0; | |
313 | u32 head, val; | |
41c445ff JB |
314 | |
315 | pf->tx_timeout_count++; | |
316 | ||
b03a8c1f KP |
317 | /* find the stopped queue the same way the stack does */ |
318 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
319 | struct netdev_queue *q; | |
320 | unsigned long trans_start; | |
321 | ||
322 | q = netdev_get_tx_queue(netdev, i); | |
9b36627a | 323 | trans_start = q->trans_start; |
b03a8c1f KP |
324 | if (netif_xmit_stopped(q) && |
325 | time_after(jiffies, | |
326 | (trans_start + netdev->watchdog_timeo))) { | |
327 | hung_queue = i; | |
328 | break; | |
329 | } | |
330 | } | |
331 | ||
332 | if (i == netdev->num_tx_queues) { | |
333 | netdev_info(netdev, "tx_timeout: no netdev hung queue found\n"); | |
334 | } else { | |
335 | /* now that we have an index, find the tx_ring struct */ | |
336 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
337 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
338 | if (hung_queue == | |
339 | vsi->tx_rings[i]->queue_index) { | |
340 | tx_ring = vsi->tx_rings[i]; | |
341 | break; | |
342 | } | |
343 | } | |
344 | } | |
345 | } | |
346 | ||
41c445ff | 347 | if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20))) |
b03a8c1f KP |
348 | pf->tx_timeout_recovery_level = 1; /* reset after some time */ |
349 | else if (time_before(jiffies, | |
350 | (pf->tx_timeout_last_recovery + netdev->watchdog_timeo))) | |
351 | return; /* don't do any new action before the next timeout */ | |
352 | ||
353 | if (tx_ring) { | |
354 | head = i40e_get_head(tx_ring); | |
355 | /* Read interrupt register */ | |
356 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
357 | val = rd32(&pf->hw, | |
358 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
359 | tx_ring->vsi->base_vector - 1)); | |
360 | else | |
361 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
362 | ||
363 | netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n", | |
364 | vsi->seid, hung_queue, tx_ring->next_to_clean, | |
365 | head, tx_ring->next_to_use, | |
366 | readl(tx_ring->tail), val); | |
367 | } | |
368 | ||
41c445ff | 369 | pf->tx_timeout_last_recovery = jiffies; |
b03a8c1f KP |
370 | netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n", |
371 | pf->tx_timeout_recovery_level, hung_queue); | |
41c445ff JB |
372 | |
373 | switch (pf->tx_timeout_recovery_level) { | |
41c445ff JB |
374 | case 1: |
375 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
376 | break; | |
377 | case 2: | |
378 | set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state); | |
379 | break; | |
380 | case 3: | |
381 | set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state); | |
382 | break; | |
383 | default: | |
384 | netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); | |
41c445ff JB |
385 | break; |
386 | } | |
b03a8c1f | 387 | |
41c445ff JB |
388 | i40e_service_event_schedule(pf); |
389 | pf->tx_timeout_recovery_level++; | |
390 | } | |
391 | ||
41c445ff JB |
392 | /** |
393 | * i40e_get_vsi_stats_struct - Get System Network Statistics | |
394 | * @vsi: the VSI we care about | |
395 | * | |
396 | * Returns the address of the device statistics structure. | |
397 | * The statistics are actually updated from the service task. | |
398 | **/ | |
399 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi) | |
400 | { | |
401 | return &vsi->net_stats; | |
402 | } | |
403 | ||
404 | /** | |
405 | * i40e_get_netdev_stats_struct - Get statistics for netdev interface | |
406 | * @netdev: network interface device structure | |
407 | * | |
408 | * Returns the address of the device statistics structure. | |
409 | * The statistics are actually updated from the service task. | |
410 | **/ | |
38e00438 VD |
411 | #ifdef I40E_FCOE |
412 | struct rtnl_link_stats64 *i40e_get_netdev_stats_struct( | |
413 | struct net_device *netdev, | |
414 | struct rtnl_link_stats64 *stats) | |
415 | #else | |
41c445ff JB |
416 | static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct( |
417 | struct net_device *netdev, | |
980e9b11 | 418 | struct rtnl_link_stats64 *stats) |
38e00438 | 419 | #endif |
41c445ff JB |
420 | { |
421 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
e7046ee1 | 422 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff | 423 | struct i40e_vsi *vsi = np->vsi; |
980e9b11 AD |
424 | struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi); |
425 | int i; | |
426 | ||
bc7d338f ASJ |
427 | if (test_bit(__I40E_DOWN, &vsi->state)) |
428 | return stats; | |
429 | ||
3c325ced JB |
430 | if (!vsi->tx_rings) |
431 | return stats; | |
432 | ||
980e9b11 AD |
433 | rcu_read_lock(); |
434 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
980e9b11 AD |
435 | u64 bytes, packets; |
436 | unsigned int start; | |
437 | ||
438 | tx_ring = ACCESS_ONCE(vsi->tx_rings[i]); | |
439 | if (!tx_ring) | |
440 | continue; | |
441 | ||
442 | do { | |
57a7744e | 443 | start = u64_stats_fetch_begin_irq(&tx_ring->syncp); |
980e9b11 AD |
444 | packets = tx_ring->stats.packets; |
445 | bytes = tx_ring->stats.bytes; | |
57a7744e | 446 | } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start)); |
980e9b11 AD |
447 | |
448 | stats->tx_packets += packets; | |
449 | stats->tx_bytes += bytes; | |
450 | rx_ring = &tx_ring[1]; | |
451 | ||
452 | do { | |
57a7744e | 453 | start = u64_stats_fetch_begin_irq(&rx_ring->syncp); |
980e9b11 AD |
454 | packets = rx_ring->stats.packets; |
455 | bytes = rx_ring->stats.bytes; | |
57a7744e | 456 | } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start)); |
41c445ff | 457 | |
980e9b11 AD |
458 | stats->rx_packets += packets; |
459 | stats->rx_bytes += bytes; | |
460 | } | |
461 | rcu_read_unlock(); | |
462 | ||
a5282f44 | 463 | /* following stats updated by i40e_watchdog_subtask() */ |
980e9b11 AD |
464 | stats->multicast = vsi_stats->multicast; |
465 | stats->tx_errors = vsi_stats->tx_errors; | |
466 | stats->tx_dropped = vsi_stats->tx_dropped; | |
467 | stats->rx_errors = vsi_stats->rx_errors; | |
d8201e20 | 468 | stats->rx_dropped = vsi_stats->rx_dropped; |
980e9b11 AD |
469 | stats->rx_crc_errors = vsi_stats->rx_crc_errors; |
470 | stats->rx_length_errors = vsi_stats->rx_length_errors; | |
41c445ff | 471 | |
980e9b11 | 472 | return stats; |
41c445ff JB |
473 | } |
474 | ||
475 | /** | |
476 | * i40e_vsi_reset_stats - Resets all stats of the given vsi | |
477 | * @vsi: the VSI to have its stats reset | |
478 | **/ | |
479 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi) | |
480 | { | |
481 | struct rtnl_link_stats64 *ns; | |
482 | int i; | |
483 | ||
484 | if (!vsi) | |
485 | return; | |
486 | ||
487 | ns = i40e_get_vsi_stats_struct(vsi); | |
488 | memset(ns, 0, sizeof(*ns)); | |
489 | memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets)); | |
490 | memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats)); | |
491 | memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets)); | |
8e9dca53 | 492 | if (vsi->rx_rings && vsi->rx_rings[0]) { |
41c445ff | 493 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
6995b36c | 494 | memset(&vsi->rx_rings[i]->stats, 0, |
9f65e15b | 495 | sizeof(vsi->rx_rings[i]->stats)); |
6995b36c | 496 | memset(&vsi->rx_rings[i]->rx_stats, 0, |
9f65e15b | 497 | sizeof(vsi->rx_rings[i]->rx_stats)); |
6995b36c | 498 | memset(&vsi->tx_rings[i]->stats, 0, |
9f65e15b AD |
499 | sizeof(vsi->tx_rings[i]->stats)); |
500 | memset(&vsi->tx_rings[i]->tx_stats, 0, | |
501 | sizeof(vsi->tx_rings[i]->tx_stats)); | |
41c445ff | 502 | } |
8e9dca53 | 503 | } |
41c445ff JB |
504 | vsi->stat_offsets_loaded = false; |
505 | } | |
506 | ||
507 | /** | |
b40c82e6 | 508 | * i40e_pf_reset_stats - Reset all of the stats for the given PF |
41c445ff JB |
509 | * @pf: the PF to be reset |
510 | **/ | |
511 | void i40e_pf_reset_stats(struct i40e_pf *pf) | |
512 | { | |
e91fdf76 SN |
513 | int i; |
514 | ||
41c445ff JB |
515 | memset(&pf->stats, 0, sizeof(pf->stats)); |
516 | memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); | |
517 | pf->stat_offsets_loaded = false; | |
e91fdf76 SN |
518 | |
519 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
520 | if (pf->veb[i]) { | |
521 | memset(&pf->veb[i]->stats, 0, | |
522 | sizeof(pf->veb[i]->stats)); | |
523 | memset(&pf->veb[i]->stats_offsets, 0, | |
524 | sizeof(pf->veb[i]->stats_offsets)); | |
525 | pf->veb[i]->stat_offsets_loaded = false; | |
526 | } | |
527 | } | |
42bce04e | 528 | pf->hw_csum_rx_error = 0; |
41c445ff JB |
529 | } |
530 | ||
531 | /** | |
532 | * i40e_stat_update48 - read and update a 48 bit stat from the chip | |
533 | * @hw: ptr to the hardware info | |
534 | * @hireg: the high 32 bit reg to read | |
535 | * @loreg: the low 32 bit reg to read | |
536 | * @offset_loaded: has the initial offset been loaded yet | |
537 | * @offset: ptr to current offset value | |
538 | * @stat: ptr to the stat | |
539 | * | |
540 | * Since the device stats are not reset at PFReset, they likely will not | |
541 | * be zeroed when the driver starts. We'll save the first values read | |
542 | * and use them as offsets to be subtracted from the raw values in order | |
543 | * to report stats that count from zero. In the process, we also manage | |
544 | * the potential roll-over. | |
545 | **/ | |
546 | static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, | |
547 | bool offset_loaded, u64 *offset, u64 *stat) | |
548 | { | |
549 | u64 new_data; | |
550 | ||
ab60085e | 551 | if (hw->device_id == I40E_DEV_ID_QEMU) { |
41c445ff JB |
552 | new_data = rd32(hw, loreg); |
553 | new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; | |
554 | } else { | |
555 | new_data = rd64(hw, loreg); | |
556 | } | |
557 | if (!offset_loaded) | |
558 | *offset = new_data; | |
559 | if (likely(new_data >= *offset)) | |
560 | *stat = new_data - *offset; | |
561 | else | |
41a1d04b | 562 | *stat = (new_data + BIT_ULL(48)) - *offset; |
41c445ff JB |
563 | *stat &= 0xFFFFFFFFFFFFULL; |
564 | } | |
565 | ||
566 | /** | |
567 | * i40e_stat_update32 - read and update a 32 bit stat from the chip | |
568 | * @hw: ptr to the hardware info | |
569 | * @reg: the hw reg to read | |
570 | * @offset_loaded: has the initial offset been loaded yet | |
571 | * @offset: ptr to current offset value | |
572 | * @stat: ptr to the stat | |
573 | **/ | |
574 | static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, | |
575 | bool offset_loaded, u64 *offset, u64 *stat) | |
576 | { | |
577 | u32 new_data; | |
578 | ||
579 | new_data = rd32(hw, reg); | |
580 | if (!offset_loaded) | |
581 | *offset = new_data; | |
582 | if (likely(new_data >= *offset)) | |
583 | *stat = (u32)(new_data - *offset); | |
584 | else | |
41a1d04b | 585 | *stat = (u32)((new_data + BIT_ULL(32)) - *offset); |
41c445ff JB |
586 | } |
587 | ||
588 | /** | |
589 | * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. | |
590 | * @vsi: the VSI to be updated | |
591 | **/ | |
592 | void i40e_update_eth_stats(struct i40e_vsi *vsi) | |
593 | { | |
594 | int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx); | |
595 | struct i40e_pf *pf = vsi->back; | |
596 | struct i40e_hw *hw = &pf->hw; | |
597 | struct i40e_eth_stats *oes; | |
598 | struct i40e_eth_stats *es; /* device's eth stats */ | |
599 | ||
600 | es = &vsi->eth_stats; | |
601 | oes = &vsi->eth_stats_offsets; | |
602 | ||
603 | /* Gather up the stats that the hw collects */ | |
604 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
605 | vsi->stat_offsets_loaded, | |
606 | &oes->tx_errors, &es->tx_errors); | |
607 | i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), | |
608 | vsi->stat_offsets_loaded, | |
609 | &oes->rx_discards, &es->rx_discards); | |
41a9e55c SN |
610 | i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx), |
611 | vsi->stat_offsets_loaded, | |
612 | &oes->rx_unknown_protocol, &es->rx_unknown_protocol); | |
613 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
614 | vsi->stat_offsets_loaded, | |
615 | &oes->tx_errors, &es->tx_errors); | |
41c445ff JB |
616 | |
617 | i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx), | |
618 | I40E_GLV_GORCL(stat_idx), | |
619 | vsi->stat_offsets_loaded, | |
620 | &oes->rx_bytes, &es->rx_bytes); | |
621 | i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), | |
622 | I40E_GLV_UPRCL(stat_idx), | |
623 | vsi->stat_offsets_loaded, | |
624 | &oes->rx_unicast, &es->rx_unicast); | |
625 | i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), | |
626 | I40E_GLV_MPRCL(stat_idx), | |
627 | vsi->stat_offsets_loaded, | |
628 | &oes->rx_multicast, &es->rx_multicast); | |
629 | i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), | |
630 | I40E_GLV_BPRCL(stat_idx), | |
631 | vsi->stat_offsets_loaded, | |
632 | &oes->rx_broadcast, &es->rx_broadcast); | |
633 | ||
634 | i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), | |
635 | I40E_GLV_GOTCL(stat_idx), | |
636 | vsi->stat_offsets_loaded, | |
637 | &oes->tx_bytes, &es->tx_bytes); | |
638 | i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), | |
639 | I40E_GLV_UPTCL(stat_idx), | |
640 | vsi->stat_offsets_loaded, | |
641 | &oes->tx_unicast, &es->tx_unicast); | |
642 | i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), | |
643 | I40E_GLV_MPTCL(stat_idx), | |
644 | vsi->stat_offsets_loaded, | |
645 | &oes->tx_multicast, &es->tx_multicast); | |
646 | i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), | |
647 | I40E_GLV_BPTCL(stat_idx), | |
648 | vsi->stat_offsets_loaded, | |
649 | &oes->tx_broadcast, &es->tx_broadcast); | |
650 | vsi->stat_offsets_loaded = true; | |
651 | } | |
652 | ||
653 | /** | |
654 | * i40e_update_veb_stats - Update Switch component statistics | |
655 | * @veb: the VEB being updated | |
656 | **/ | |
657 | static void i40e_update_veb_stats(struct i40e_veb *veb) | |
658 | { | |
659 | struct i40e_pf *pf = veb->pf; | |
660 | struct i40e_hw *hw = &pf->hw; | |
661 | struct i40e_eth_stats *oes; | |
662 | struct i40e_eth_stats *es; /* device's eth stats */ | |
fe860afb NP |
663 | struct i40e_veb_tc_stats *veb_oes; |
664 | struct i40e_veb_tc_stats *veb_es; | |
665 | int i, idx = 0; | |
41c445ff JB |
666 | |
667 | idx = veb->stats_idx; | |
668 | es = &veb->stats; | |
669 | oes = &veb->stats_offsets; | |
fe860afb NP |
670 | veb_es = &veb->tc_stats; |
671 | veb_oes = &veb->tc_stats_offsets; | |
41c445ff JB |
672 | |
673 | /* Gather up the stats that the hw collects */ | |
674 | i40e_stat_update32(hw, I40E_GLSW_TDPC(idx), | |
675 | veb->stat_offsets_loaded, | |
676 | &oes->tx_discards, &es->tx_discards); | |
7134f9ce JB |
677 | if (hw->revision_id > 0) |
678 | i40e_stat_update32(hw, I40E_GLSW_RUPP(idx), | |
679 | veb->stat_offsets_loaded, | |
680 | &oes->rx_unknown_protocol, | |
681 | &es->rx_unknown_protocol); | |
41c445ff JB |
682 | i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx), |
683 | veb->stat_offsets_loaded, | |
684 | &oes->rx_bytes, &es->rx_bytes); | |
685 | i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx), | |
686 | veb->stat_offsets_loaded, | |
687 | &oes->rx_unicast, &es->rx_unicast); | |
688 | i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx), | |
689 | veb->stat_offsets_loaded, | |
690 | &oes->rx_multicast, &es->rx_multicast); | |
691 | i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx), | |
692 | veb->stat_offsets_loaded, | |
693 | &oes->rx_broadcast, &es->rx_broadcast); | |
694 | ||
695 | i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx), | |
696 | veb->stat_offsets_loaded, | |
697 | &oes->tx_bytes, &es->tx_bytes); | |
698 | i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx), | |
699 | veb->stat_offsets_loaded, | |
700 | &oes->tx_unicast, &es->tx_unicast); | |
701 | i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx), | |
702 | veb->stat_offsets_loaded, | |
703 | &oes->tx_multicast, &es->tx_multicast); | |
704 | i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx), | |
705 | veb->stat_offsets_loaded, | |
706 | &oes->tx_broadcast, &es->tx_broadcast); | |
fe860afb NP |
707 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
708 | i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx), | |
709 | I40E_GLVEBTC_RPCL(i, idx), | |
710 | veb->stat_offsets_loaded, | |
711 | &veb_oes->tc_rx_packets[i], | |
712 | &veb_es->tc_rx_packets[i]); | |
713 | i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx), | |
714 | I40E_GLVEBTC_RBCL(i, idx), | |
715 | veb->stat_offsets_loaded, | |
716 | &veb_oes->tc_rx_bytes[i], | |
717 | &veb_es->tc_rx_bytes[i]); | |
718 | i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx), | |
719 | I40E_GLVEBTC_TPCL(i, idx), | |
720 | veb->stat_offsets_loaded, | |
721 | &veb_oes->tc_tx_packets[i], | |
722 | &veb_es->tc_tx_packets[i]); | |
723 | i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx), | |
724 | I40E_GLVEBTC_TBCL(i, idx), | |
725 | veb->stat_offsets_loaded, | |
726 | &veb_oes->tc_tx_bytes[i], | |
727 | &veb_es->tc_tx_bytes[i]); | |
728 | } | |
41c445ff JB |
729 | veb->stat_offsets_loaded = true; |
730 | } | |
731 | ||
38e00438 VD |
732 | #ifdef I40E_FCOE |
733 | /** | |
734 | * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters. | |
735 | * @vsi: the VSI that is capable of doing FCoE | |
736 | **/ | |
737 | static void i40e_update_fcoe_stats(struct i40e_vsi *vsi) | |
738 | { | |
739 | struct i40e_pf *pf = vsi->back; | |
740 | struct i40e_hw *hw = &pf->hw; | |
741 | struct i40e_fcoe_stats *ofs; | |
742 | struct i40e_fcoe_stats *fs; /* device's eth stats */ | |
743 | int idx; | |
744 | ||
745 | if (vsi->type != I40E_VSI_FCOE) | |
746 | return; | |
747 | ||
4147e2c5 | 748 | idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET; |
38e00438 VD |
749 | fs = &vsi->fcoe_stats; |
750 | ofs = &vsi->fcoe_stats_offsets; | |
751 | ||
752 | i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx), | |
753 | vsi->fcoe_stat_offsets_loaded, | |
754 | &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets); | |
755 | i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx), | |
756 | vsi->fcoe_stat_offsets_loaded, | |
757 | &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords); | |
758 | i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx), | |
759 | vsi->fcoe_stat_offsets_loaded, | |
760 | &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped); | |
761 | i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx), | |
762 | vsi->fcoe_stat_offsets_loaded, | |
763 | &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets); | |
764 | i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx), | |
765 | vsi->fcoe_stat_offsets_loaded, | |
766 | &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords); | |
767 | i40e_stat_update32(hw, I40E_GL_FCOECRC(idx), | |
768 | vsi->fcoe_stat_offsets_loaded, | |
769 | &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc); | |
770 | i40e_stat_update32(hw, I40E_GL_FCOELAST(idx), | |
771 | vsi->fcoe_stat_offsets_loaded, | |
772 | &ofs->fcoe_last_error, &fs->fcoe_last_error); | |
773 | i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx), | |
774 | vsi->fcoe_stat_offsets_loaded, | |
775 | &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count); | |
776 | ||
777 | vsi->fcoe_stat_offsets_loaded = true; | |
778 | } | |
779 | ||
780 | #endif | |
41c445ff | 781 | /** |
7812fddc | 782 | * i40e_update_vsi_stats - Update the vsi statistics counters. |
41c445ff JB |
783 | * @vsi: the VSI to be updated |
784 | * | |
785 | * There are a few instances where we store the same stat in a | |
786 | * couple of different structs. This is partly because we have | |
787 | * the netdev stats that need to be filled out, which is slightly | |
788 | * different from the "eth_stats" defined by the chip and used in | |
7812fddc | 789 | * VF communications. We sort it out here. |
41c445ff | 790 | **/ |
7812fddc | 791 | static void i40e_update_vsi_stats(struct i40e_vsi *vsi) |
41c445ff JB |
792 | { |
793 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
794 | struct rtnl_link_stats64 *ons; |
795 | struct rtnl_link_stats64 *ns; /* netdev stats */ | |
796 | struct i40e_eth_stats *oes; | |
797 | struct i40e_eth_stats *es; /* device's eth stats */ | |
798 | u32 tx_restart, tx_busy; | |
dd353109 | 799 | u64 tx_lost_interrupt; |
bf00b376 | 800 | struct i40e_ring *p; |
41c445ff | 801 | u32 rx_page, rx_buf; |
bf00b376 AA |
802 | u64 bytes, packets; |
803 | unsigned int start; | |
2fc3d715 | 804 | u64 tx_linearize; |
164c9f54 | 805 | u64 tx_force_wb; |
41c445ff JB |
806 | u64 rx_p, rx_b; |
807 | u64 tx_p, tx_b; | |
41c445ff JB |
808 | u16 q; |
809 | ||
810 | if (test_bit(__I40E_DOWN, &vsi->state) || | |
811 | test_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
812 | return; | |
813 | ||
814 | ns = i40e_get_vsi_stats_struct(vsi); | |
815 | ons = &vsi->net_stats_offsets; | |
816 | es = &vsi->eth_stats; | |
817 | oes = &vsi->eth_stats_offsets; | |
818 | ||
819 | /* Gather up the netdev and vsi stats that the driver collects | |
820 | * on the fly during packet processing | |
821 | */ | |
822 | rx_b = rx_p = 0; | |
823 | tx_b = tx_p = 0; | |
164c9f54 | 824 | tx_restart = tx_busy = tx_linearize = tx_force_wb = 0; |
dd353109 | 825 | tx_lost_interrupt = 0; |
41c445ff JB |
826 | rx_page = 0; |
827 | rx_buf = 0; | |
980e9b11 | 828 | rcu_read_lock(); |
41c445ff | 829 | for (q = 0; q < vsi->num_queue_pairs; q++) { |
980e9b11 AD |
830 | /* locate Tx ring */ |
831 | p = ACCESS_ONCE(vsi->tx_rings[q]); | |
832 | ||
833 | do { | |
57a7744e | 834 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
835 | packets = p->stats.packets; |
836 | bytes = p->stats.bytes; | |
57a7744e | 837 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
838 | tx_b += bytes; |
839 | tx_p += packets; | |
840 | tx_restart += p->tx_stats.restart_queue; | |
841 | tx_busy += p->tx_stats.tx_busy; | |
2fc3d715 | 842 | tx_linearize += p->tx_stats.tx_linearize; |
164c9f54 | 843 | tx_force_wb += p->tx_stats.tx_force_wb; |
dd353109 | 844 | tx_lost_interrupt += p->tx_stats.tx_lost_interrupt; |
41c445ff | 845 | |
980e9b11 AD |
846 | /* Rx queue is part of the same block as Tx queue */ |
847 | p = &p[1]; | |
848 | do { | |
57a7744e | 849 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
850 | packets = p->stats.packets; |
851 | bytes = p->stats.bytes; | |
57a7744e | 852 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
853 | rx_b += bytes; |
854 | rx_p += packets; | |
420136cc MW |
855 | rx_buf += p->rx_stats.alloc_buff_failed; |
856 | rx_page += p->rx_stats.alloc_page_failed; | |
41c445ff | 857 | } |
980e9b11 | 858 | rcu_read_unlock(); |
41c445ff JB |
859 | vsi->tx_restart = tx_restart; |
860 | vsi->tx_busy = tx_busy; | |
2fc3d715 | 861 | vsi->tx_linearize = tx_linearize; |
164c9f54 | 862 | vsi->tx_force_wb = tx_force_wb; |
dd353109 | 863 | vsi->tx_lost_interrupt = tx_lost_interrupt; |
41c445ff JB |
864 | vsi->rx_page_failed = rx_page; |
865 | vsi->rx_buf_failed = rx_buf; | |
866 | ||
867 | ns->rx_packets = rx_p; | |
868 | ns->rx_bytes = rx_b; | |
869 | ns->tx_packets = tx_p; | |
870 | ns->tx_bytes = tx_b; | |
871 | ||
41c445ff | 872 | /* update netdev stats from eth stats */ |
7812fddc | 873 | i40e_update_eth_stats(vsi); |
41c445ff JB |
874 | ons->tx_errors = oes->tx_errors; |
875 | ns->tx_errors = es->tx_errors; | |
876 | ons->multicast = oes->rx_multicast; | |
877 | ns->multicast = es->rx_multicast; | |
41a9e55c SN |
878 | ons->rx_dropped = oes->rx_discards; |
879 | ns->rx_dropped = es->rx_discards; | |
41c445ff JB |
880 | ons->tx_dropped = oes->tx_discards; |
881 | ns->tx_dropped = es->tx_discards; | |
882 | ||
7812fddc | 883 | /* pull in a couple PF stats if this is the main vsi */ |
41c445ff | 884 | if (vsi == pf->vsi[pf->lan_vsi]) { |
7812fddc SN |
885 | ns->rx_crc_errors = pf->stats.crc_errors; |
886 | ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes; | |
887 | ns->rx_length_errors = pf->stats.rx_length_errors; | |
888 | } | |
889 | } | |
41c445ff | 890 | |
7812fddc | 891 | /** |
b40c82e6 | 892 | * i40e_update_pf_stats - Update the PF statistics counters. |
7812fddc SN |
893 | * @pf: the PF to be updated |
894 | **/ | |
895 | static void i40e_update_pf_stats(struct i40e_pf *pf) | |
896 | { | |
897 | struct i40e_hw_port_stats *osd = &pf->stats_offsets; | |
898 | struct i40e_hw_port_stats *nsd = &pf->stats; | |
899 | struct i40e_hw *hw = &pf->hw; | |
900 | u32 val; | |
901 | int i; | |
41c445ff | 902 | |
7812fddc SN |
903 | i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), |
904 | I40E_GLPRT_GORCL(hw->port), | |
905 | pf->stat_offsets_loaded, | |
906 | &osd->eth.rx_bytes, &nsd->eth.rx_bytes); | |
907 | i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), | |
908 | I40E_GLPRT_GOTCL(hw->port), | |
909 | pf->stat_offsets_loaded, | |
910 | &osd->eth.tx_bytes, &nsd->eth.tx_bytes); | |
911 | i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), | |
912 | pf->stat_offsets_loaded, | |
913 | &osd->eth.rx_discards, | |
914 | &nsd->eth.rx_discards); | |
532d283d SN |
915 | i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), |
916 | I40E_GLPRT_UPRCL(hw->port), | |
917 | pf->stat_offsets_loaded, | |
918 | &osd->eth.rx_unicast, | |
919 | &nsd->eth.rx_unicast); | |
7812fddc SN |
920 | i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), |
921 | I40E_GLPRT_MPRCL(hw->port), | |
922 | pf->stat_offsets_loaded, | |
923 | &osd->eth.rx_multicast, | |
924 | &nsd->eth.rx_multicast); | |
532d283d SN |
925 | i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), |
926 | I40E_GLPRT_BPRCL(hw->port), | |
927 | pf->stat_offsets_loaded, | |
928 | &osd->eth.rx_broadcast, | |
929 | &nsd->eth.rx_broadcast); | |
930 | i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), | |
931 | I40E_GLPRT_UPTCL(hw->port), | |
932 | pf->stat_offsets_loaded, | |
933 | &osd->eth.tx_unicast, | |
934 | &nsd->eth.tx_unicast); | |
935 | i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), | |
936 | I40E_GLPRT_MPTCL(hw->port), | |
937 | pf->stat_offsets_loaded, | |
938 | &osd->eth.tx_multicast, | |
939 | &nsd->eth.tx_multicast); | |
940 | i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), | |
941 | I40E_GLPRT_BPTCL(hw->port), | |
942 | pf->stat_offsets_loaded, | |
943 | &osd->eth.tx_broadcast, | |
944 | &nsd->eth.tx_broadcast); | |
41c445ff | 945 | |
7812fddc SN |
946 | i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), |
947 | pf->stat_offsets_loaded, | |
948 | &osd->tx_dropped_link_down, | |
949 | &nsd->tx_dropped_link_down); | |
41c445ff | 950 | |
7812fddc SN |
951 | i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), |
952 | pf->stat_offsets_loaded, | |
953 | &osd->crc_errors, &nsd->crc_errors); | |
41c445ff | 954 | |
7812fddc SN |
955 | i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), |
956 | pf->stat_offsets_loaded, | |
957 | &osd->illegal_bytes, &nsd->illegal_bytes); | |
41c445ff | 958 | |
7812fddc SN |
959 | i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), |
960 | pf->stat_offsets_loaded, | |
961 | &osd->mac_local_faults, | |
962 | &nsd->mac_local_faults); | |
963 | i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), | |
964 | pf->stat_offsets_loaded, | |
965 | &osd->mac_remote_faults, | |
966 | &nsd->mac_remote_faults); | |
41c445ff | 967 | |
7812fddc SN |
968 | i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), |
969 | pf->stat_offsets_loaded, | |
970 | &osd->rx_length_errors, | |
971 | &nsd->rx_length_errors); | |
41c445ff | 972 | |
7812fddc SN |
973 | i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), |
974 | pf->stat_offsets_loaded, | |
975 | &osd->link_xon_rx, &nsd->link_xon_rx); | |
976 | i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), | |
977 | pf->stat_offsets_loaded, | |
978 | &osd->link_xon_tx, &nsd->link_xon_tx); | |
95db239f NP |
979 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), |
980 | pf->stat_offsets_loaded, | |
981 | &osd->link_xoff_rx, &nsd->link_xoff_rx); | |
7812fddc SN |
982 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), |
983 | pf->stat_offsets_loaded, | |
984 | &osd->link_xoff_tx, &nsd->link_xoff_tx); | |
41c445ff | 985 | |
7812fddc | 986 | for (i = 0; i < 8; i++) { |
95db239f NP |
987 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), |
988 | pf->stat_offsets_loaded, | |
989 | &osd->priority_xoff_rx[i], | |
990 | &nsd->priority_xoff_rx[i]); | |
7812fddc | 991 | i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i), |
41c445ff | 992 | pf->stat_offsets_loaded, |
7812fddc SN |
993 | &osd->priority_xon_rx[i], |
994 | &nsd->priority_xon_rx[i]); | |
995 | i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i), | |
41c445ff | 996 | pf->stat_offsets_loaded, |
7812fddc SN |
997 | &osd->priority_xon_tx[i], |
998 | &nsd->priority_xon_tx[i]); | |
999 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), | |
41c445ff | 1000 | pf->stat_offsets_loaded, |
7812fddc SN |
1001 | &osd->priority_xoff_tx[i], |
1002 | &nsd->priority_xoff_tx[i]); | |
1003 | i40e_stat_update32(hw, | |
1004 | I40E_GLPRT_RXON2OFFCNT(hw->port, i), | |
bee5af7e | 1005 | pf->stat_offsets_loaded, |
7812fddc SN |
1006 | &osd->priority_xon_2_xoff[i], |
1007 | &nsd->priority_xon_2_xoff[i]); | |
41c445ff JB |
1008 | } |
1009 | ||
7812fddc SN |
1010 | i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), |
1011 | I40E_GLPRT_PRC64L(hw->port), | |
1012 | pf->stat_offsets_loaded, | |
1013 | &osd->rx_size_64, &nsd->rx_size_64); | |
1014 | i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), | |
1015 | I40E_GLPRT_PRC127L(hw->port), | |
1016 | pf->stat_offsets_loaded, | |
1017 | &osd->rx_size_127, &nsd->rx_size_127); | |
1018 | i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), | |
1019 | I40E_GLPRT_PRC255L(hw->port), | |
1020 | pf->stat_offsets_loaded, | |
1021 | &osd->rx_size_255, &nsd->rx_size_255); | |
1022 | i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), | |
1023 | I40E_GLPRT_PRC511L(hw->port), | |
1024 | pf->stat_offsets_loaded, | |
1025 | &osd->rx_size_511, &nsd->rx_size_511); | |
1026 | i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), | |
1027 | I40E_GLPRT_PRC1023L(hw->port), | |
1028 | pf->stat_offsets_loaded, | |
1029 | &osd->rx_size_1023, &nsd->rx_size_1023); | |
1030 | i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), | |
1031 | I40E_GLPRT_PRC1522L(hw->port), | |
1032 | pf->stat_offsets_loaded, | |
1033 | &osd->rx_size_1522, &nsd->rx_size_1522); | |
1034 | i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), | |
1035 | I40E_GLPRT_PRC9522L(hw->port), | |
1036 | pf->stat_offsets_loaded, | |
1037 | &osd->rx_size_big, &nsd->rx_size_big); | |
1038 | ||
1039 | i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), | |
1040 | I40E_GLPRT_PTC64L(hw->port), | |
1041 | pf->stat_offsets_loaded, | |
1042 | &osd->tx_size_64, &nsd->tx_size_64); | |
1043 | i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), | |
1044 | I40E_GLPRT_PTC127L(hw->port), | |
1045 | pf->stat_offsets_loaded, | |
1046 | &osd->tx_size_127, &nsd->tx_size_127); | |
1047 | i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), | |
1048 | I40E_GLPRT_PTC255L(hw->port), | |
1049 | pf->stat_offsets_loaded, | |
1050 | &osd->tx_size_255, &nsd->tx_size_255); | |
1051 | i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), | |
1052 | I40E_GLPRT_PTC511L(hw->port), | |
1053 | pf->stat_offsets_loaded, | |
1054 | &osd->tx_size_511, &nsd->tx_size_511); | |
1055 | i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), | |
1056 | I40E_GLPRT_PTC1023L(hw->port), | |
1057 | pf->stat_offsets_loaded, | |
1058 | &osd->tx_size_1023, &nsd->tx_size_1023); | |
1059 | i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), | |
1060 | I40E_GLPRT_PTC1522L(hw->port), | |
1061 | pf->stat_offsets_loaded, | |
1062 | &osd->tx_size_1522, &nsd->tx_size_1522); | |
1063 | i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), | |
1064 | I40E_GLPRT_PTC9522L(hw->port), | |
1065 | pf->stat_offsets_loaded, | |
1066 | &osd->tx_size_big, &nsd->tx_size_big); | |
1067 | ||
1068 | i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port), | |
1069 | pf->stat_offsets_loaded, | |
1070 | &osd->rx_undersize, &nsd->rx_undersize); | |
1071 | i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port), | |
1072 | pf->stat_offsets_loaded, | |
1073 | &osd->rx_fragments, &nsd->rx_fragments); | |
1074 | i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port), | |
1075 | pf->stat_offsets_loaded, | |
1076 | &osd->rx_oversize, &nsd->rx_oversize); | |
1077 | i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port), | |
1078 | pf->stat_offsets_loaded, | |
1079 | &osd->rx_jabber, &nsd->rx_jabber); | |
1080 | ||
433c47de | 1081 | /* FDIR stats */ |
0bf4b1b0 ASJ |
1082 | i40e_stat_update32(hw, |
1083 | I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)), | |
433c47de ASJ |
1084 | pf->stat_offsets_loaded, |
1085 | &osd->fd_atr_match, &nsd->fd_atr_match); | |
0bf4b1b0 ASJ |
1086 | i40e_stat_update32(hw, |
1087 | I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)), | |
433c47de ASJ |
1088 | pf->stat_offsets_loaded, |
1089 | &osd->fd_sb_match, &nsd->fd_sb_match); | |
60ccd45c ASJ |
1090 | i40e_stat_update32(hw, |
1091 | I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)), | |
1092 | pf->stat_offsets_loaded, | |
1093 | &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match); | |
433c47de | 1094 | |
7812fddc SN |
1095 | val = rd32(hw, I40E_PRTPM_EEE_STAT); |
1096 | nsd->tx_lpi_status = | |
1097 | (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> | |
1098 | I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; | |
1099 | nsd->rx_lpi_status = | |
1100 | (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> | |
1101 | I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; | |
1102 | i40e_stat_update32(hw, I40E_PRTPM_TLPIC, | |
1103 | pf->stat_offsets_loaded, | |
1104 | &osd->tx_lpi_count, &nsd->tx_lpi_count); | |
1105 | i40e_stat_update32(hw, I40E_PRTPM_RLPIC, | |
1106 | pf->stat_offsets_loaded, | |
1107 | &osd->rx_lpi_count, &nsd->rx_lpi_count); | |
1108 | ||
d0389e51 ASJ |
1109 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED && |
1110 | !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) | |
1111 | nsd->fd_sb_status = true; | |
1112 | else | |
1113 | nsd->fd_sb_status = false; | |
1114 | ||
1115 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED && | |
1116 | !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) | |
1117 | nsd->fd_atr_status = true; | |
1118 | else | |
1119 | nsd->fd_atr_status = false; | |
1120 | ||
41c445ff JB |
1121 | pf->stat_offsets_loaded = true; |
1122 | } | |
1123 | ||
7812fddc SN |
1124 | /** |
1125 | * i40e_update_stats - Update the various statistics counters. | |
1126 | * @vsi: the VSI to be updated | |
1127 | * | |
1128 | * Update the various stats for this VSI and its related entities. | |
1129 | **/ | |
1130 | void i40e_update_stats(struct i40e_vsi *vsi) | |
1131 | { | |
1132 | struct i40e_pf *pf = vsi->back; | |
1133 | ||
1134 | if (vsi == pf->vsi[pf->lan_vsi]) | |
1135 | i40e_update_pf_stats(pf); | |
1136 | ||
1137 | i40e_update_vsi_stats(vsi); | |
38e00438 VD |
1138 | #ifdef I40E_FCOE |
1139 | i40e_update_fcoe_stats(vsi); | |
1140 | #endif | |
7812fddc SN |
1141 | } |
1142 | ||
41c445ff JB |
1143 | /** |
1144 | * i40e_find_filter - Search VSI filter list for specific mac/vlan filter | |
1145 | * @vsi: the VSI to be searched | |
1146 | * @macaddr: the MAC address | |
1147 | * @vlan: the vlan | |
41c445ff JB |
1148 | * |
1149 | * Returns ptr to the filter object or NULL | |
1150 | **/ | |
1151 | static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1152 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1153 | { |
1154 | struct i40e_mac_filter *f; | |
278e7d0b | 1155 | u64 key; |
41c445ff JB |
1156 | |
1157 | if (!vsi || !macaddr) | |
1158 | return NULL; | |
1159 | ||
278e7d0b JK |
1160 | key = i40e_addr_to_hkey(macaddr); |
1161 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
41c445ff | 1162 | if ((ether_addr_equal(macaddr, f->macaddr)) && |
1bc87e80 | 1163 | (vlan == f->vlan)) |
41c445ff JB |
1164 | return f; |
1165 | } | |
1166 | return NULL; | |
1167 | } | |
1168 | ||
1169 | /** | |
1170 | * i40e_find_mac - Find a mac addr in the macvlan filters list | |
1171 | * @vsi: the VSI to be searched | |
1172 | * @macaddr: the MAC address we are searching for | |
41c445ff JB |
1173 | * |
1174 | * Returns the first filter with the provided MAC address or NULL if | |
1175 | * MAC address was not found | |
1176 | **/ | |
6622f5cd | 1177 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr) |
41c445ff JB |
1178 | { |
1179 | struct i40e_mac_filter *f; | |
278e7d0b | 1180 | u64 key; |
41c445ff JB |
1181 | |
1182 | if (!vsi || !macaddr) | |
1183 | return NULL; | |
1184 | ||
278e7d0b JK |
1185 | key = i40e_addr_to_hkey(macaddr); |
1186 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
1bc87e80 | 1187 | if ((ether_addr_equal(macaddr, f->macaddr))) |
41c445ff JB |
1188 | return f; |
1189 | } | |
1190 | return NULL; | |
1191 | } | |
1192 | ||
1193 | /** | |
1194 | * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode | |
1195 | * @vsi: the VSI to be searched | |
1196 | * | |
1197 | * Returns true if VSI is in vlan mode or false otherwise | |
1198 | **/ | |
1199 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi) | |
1200 | { | |
cbebb85f JK |
1201 | /* If we have a PVID, always operate in VLAN mode */ |
1202 | if (vsi->info.pvid) | |
1203 | return true; | |
1204 | ||
1205 | /* We need to operate in VLAN mode whenever we have any filters with | |
1206 | * a VLAN other than I40E_VLAN_ALL. We could check the table each | |
1207 | * time, incurring search cost repeatedly. However, we can notice two | |
1208 | * things: | |
1209 | * | |
1210 | * 1) the only place where we can gain a VLAN filter is in | |
1211 | * i40e_add_filter. | |
1212 | * | |
1213 | * 2) the only place where filters are actually removed is in | |
0b7c8b5d | 1214 | * i40e_sync_filters_subtask. |
cbebb85f JK |
1215 | * |
1216 | * Thus, we can simply use a boolean value, has_vlan_filters which we | |
1217 | * will set to true when we add a VLAN filter in i40e_add_filter. Then | |
1218 | * we have to perform the full search after deleting filters in | |
0b7c8b5d | 1219 | * i40e_sync_filters_subtask, but we already have to search |
cbebb85f JK |
1220 | * filters here and can perform the check at the same time. This |
1221 | * results in avoiding embedding a loop for VLAN mode inside another | |
1222 | * loop over all the filters, and should maintain correctness as noted | |
1223 | * above. | |
41c445ff | 1224 | */ |
cbebb85f | 1225 | return vsi->has_vlan_filter; |
41c445ff JB |
1226 | } |
1227 | ||
1596b5dd JK |
1228 | /** |
1229 | * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM | |
1230 | * @vsi: the PF Main VSI - inappropriate for any other VSI | |
1231 | * @macaddr: the MAC address | |
1232 | * | |
1233 | * Remove whatever filter the firmware set up so the driver can manage | |
1234 | * its own filtering intelligently. | |
1235 | **/ | |
1236 | static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr) | |
1237 | { | |
1238 | struct i40e_aqc_remove_macvlan_element_data element; | |
1239 | struct i40e_pf *pf = vsi->back; | |
1240 | ||
1241 | /* Only appropriate for the PF main VSI */ | |
1242 | if (vsi->type != I40E_VSI_MAIN) | |
1243 | return; | |
1244 | ||
1245 | memset(&element, 0, sizeof(element)); | |
1246 | ether_addr_copy(element.mac_addr, macaddr); | |
1247 | element.vlan_tag = 0; | |
1248 | /* Ignore error returns, some firmware does it this way... */ | |
1249 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; | |
1250 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1251 | ||
1252 | memset(&element, 0, sizeof(element)); | |
1253 | ether_addr_copy(element.mac_addr, macaddr); | |
1254 | element.vlan_tag = 0; | |
1255 | /* ...and some firmware does it this way. */ | |
1256 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | | |
1257 | I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; | |
1258 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1259 | } | |
1260 | ||
41c445ff JB |
1261 | /** |
1262 | * i40e_add_filter - Add a mac/vlan filter to the VSI | |
1263 | * @vsi: the VSI to be searched | |
1264 | * @macaddr: the MAC address | |
1265 | * @vlan: the vlan | |
41c445ff JB |
1266 | * |
1267 | * Returns ptr to the filter object or NULL when no memory available. | |
21659035 | 1268 | * |
278e7d0b | 1269 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1270 | * being held. |
41c445ff JB |
1271 | **/ |
1272 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1273 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1274 | { |
1275 | struct i40e_mac_filter *f; | |
278e7d0b | 1276 | u64 key; |
41c445ff JB |
1277 | |
1278 | if (!vsi || !macaddr) | |
1279 | return NULL; | |
1280 | ||
1bc87e80 | 1281 | f = i40e_find_filter(vsi, macaddr, vlan); |
41c445ff JB |
1282 | if (!f) { |
1283 | f = kzalloc(sizeof(*f), GFP_ATOMIC); | |
1284 | if (!f) | |
1bc87e80 | 1285 | return NULL; |
41c445ff | 1286 | |
cbebb85f JK |
1287 | /* Update the boolean indicating if we need to function in |
1288 | * VLAN mode. | |
1289 | */ | |
1290 | if (vlan >= 0) | |
1291 | vsi->has_vlan_filter = true; | |
1292 | ||
9a173901 | 1293 | ether_addr_copy(f->macaddr, macaddr); |
41c445ff | 1294 | f->vlan = vlan; |
c3c7ea27 MW |
1295 | /* If we're in overflow promisc mode, set the state directly |
1296 | * to failed, so we don't bother to try sending the filter | |
1297 | * to the hardware. | |
1298 | */ | |
1299 | if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state)) | |
1300 | f->state = I40E_FILTER_FAILED; | |
1301 | else | |
1302 | f->state = I40E_FILTER_NEW; | |
278e7d0b JK |
1303 | INIT_HLIST_NODE(&f->hlist); |
1304 | ||
1305 | key = i40e_addr_to_hkey(macaddr); | |
1306 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
41c445ff | 1307 | |
41c445ff JB |
1308 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; |
1309 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1310 | } | |
1311 | ||
1bc87e80 JK |
1312 | /* If we're asked to add a filter that has been marked for removal, it |
1313 | * is safe to simply restore it to active state. __i40e_del_filter | |
1314 | * will have simply deleted any filters which were previously marked | |
1315 | * NEW or FAILED, so if it is currently marked REMOVE it must have | |
1316 | * previously been ACTIVE. Since we haven't yet run the sync filters | |
1317 | * task, just restore this filter to the ACTIVE state so that the | |
1318 | * sync task leaves it in place | |
1319 | */ | |
1320 | if (f->state == I40E_FILTER_REMOVE) | |
1321 | f->state = I40E_FILTER_ACTIVE; | |
1322 | ||
41c445ff JB |
1323 | return f; |
1324 | } | |
1325 | ||
1326 | /** | |
290d2557 JK |
1327 | * __i40e_del_filter - Remove a specific filter from the VSI |
1328 | * @vsi: VSI to remove from | |
1329 | * @f: the filter to remove from the list | |
1330 | * | |
1331 | * This function should be called instead of i40e_del_filter only if you know | |
1332 | * the exact filter you will remove already, such as via i40e_find_filter or | |
1333 | * i40e_find_mac. | |
21659035 | 1334 | * |
278e7d0b | 1335 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1336 | * being held. |
c3c7ea27 MW |
1337 | * ANOTHER NOTE: This function MUST be called from within the context of |
1338 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1339 | * instead of list_for_each_entry(). | |
41c445ff | 1340 | **/ |
290d2557 | 1341 | static void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f) |
41c445ff | 1342 | { |
1bc87e80 | 1343 | if (!f) |
41c445ff JB |
1344 | return; |
1345 | ||
1bc87e80 JK |
1346 | if ((f->state == I40E_FILTER_FAILED) || |
1347 | (f->state == I40E_FILTER_NEW)) { | |
1348 | /* this one never got added by the FW. Just remove it, | |
1349 | * no need to sync anything. | |
1350 | */ | |
278e7d0b | 1351 | hash_del(&f->hlist); |
1bc87e80 | 1352 | kfree(f); |
41c445ff | 1353 | } else { |
1bc87e80 JK |
1354 | f->state = I40E_FILTER_REMOVE; |
1355 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1356 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
41c445ff JB |
1357 | } |
1358 | } | |
1359 | ||
290d2557 JK |
1360 | /** |
1361 | * i40e_del_filter - Remove a MAC/VLAN filter from the VSI | |
1362 | * @vsi: the VSI to be searched | |
1363 | * @macaddr: the MAC address | |
1364 | * @vlan: the VLAN | |
1365 | * | |
278e7d0b | 1366 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
290d2557 JK |
1367 | * being held. |
1368 | * ANOTHER NOTE: This function MUST be called from within the context of | |
1369 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1370 | * instead of list_for_each_entry(). | |
1371 | **/ | |
1372 | void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan) | |
1373 | { | |
1374 | struct i40e_mac_filter *f; | |
1375 | ||
1376 | if (!vsi || !macaddr) | |
1377 | return; | |
1378 | ||
1379 | f = i40e_find_filter(vsi, macaddr, vlan); | |
1380 | __i40e_del_filter(vsi, f); | |
1381 | } | |
1382 | ||
35ec2ff3 JK |
1383 | /** |
1384 | * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans | |
1385 | * @vsi: the VSI to be searched | |
1386 | * @macaddr: the mac address to be filtered | |
1387 | * | |
5feb3d7b JK |
1388 | * Goes through all the macvlan filters and adds a macvlan filter for each |
1389 | * unique vlan that already exists. If a PVID has been assigned, instead only | |
1390 | * add the macaddr to that VLAN. | |
35ec2ff3 | 1391 | * |
5feb3d7b | 1392 | * Returns last filter added on success, else NULL |
35ec2ff3 JK |
1393 | **/ |
1394 | struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, | |
1395 | const u8 *macaddr) | |
1396 | { | |
5feb3d7b | 1397 | struct i40e_mac_filter *f, *add = NULL; |
278e7d0b JK |
1398 | struct hlist_node *h; |
1399 | int bkt; | |
5feb3d7b JK |
1400 | |
1401 | if (vsi->info.pvid) | |
1402 | return i40e_add_filter(vsi, macaddr, | |
1403 | le16_to_cpu(vsi->info.pvid)); | |
35ec2ff3 | 1404 | |
278e7d0b | 1405 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
1406 | if (f->state == I40E_FILTER_REMOVE) |
1407 | continue; | |
5feb3d7b JK |
1408 | add = i40e_add_filter(vsi, macaddr, f->vlan); |
1409 | if (!add) | |
1410 | return NULL; | |
35ec2ff3 JK |
1411 | } |
1412 | ||
5feb3d7b | 1413 | return add; |
35ec2ff3 JK |
1414 | } |
1415 | ||
1416 | /** | |
1417 | * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS | |
1418 | * @vsi: the VSI to be searched | |
1419 | * @macaddr: the mac address to be removed | |
1420 | * | |
1421 | * Removes a given MAC address from a VSI, regardless of VLAN | |
1422 | * | |
1423 | * Returns 0 for success, or error | |
1424 | **/ | |
1425 | int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, const u8 *macaddr) | |
1426 | { | |
278e7d0b JK |
1427 | struct i40e_mac_filter *f; |
1428 | struct hlist_node *h; | |
290d2557 | 1429 | bool found = false; |
278e7d0b | 1430 | int bkt; |
35ec2ff3 | 1431 | |
278e7d0b JK |
1432 | WARN(!spin_is_locked(&vsi->mac_filter_hash_lock), |
1433 | "Missing mac_filter_hash_lock\n"); | |
1434 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { | |
290d2557 JK |
1435 | if (ether_addr_equal(macaddr, f->macaddr)) { |
1436 | __i40e_del_filter(vsi, f); | |
1437 | found = true; | |
1438 | } | |
35ec2ff3 | 1439 | } |
290d2557 JK |
1440 | |
1441 | if (found) | |
35ec2ff3 | 1442 | return 0; |
290d2557 JK |
1443 | else |
1444 | return -ENOENT; | |
35ec2ff3 JK |
1445 | } |
1446 | ||
41c445ff JB |
1447 | /** |
1448 | * i40e_set_mac - NDO callback to set mac address | |
1449 | * @netdev: network interface device structure | |
1450 | * @p: pointer to an address structure | |
1451 | * | |
1452 | * Returns 0 on success, negative on failure | |
1453 | **/ | |
38e00438 VD |
1454 | #ifdef I40E_FCOE |
1455 | int i40e_set_mac(struct net_device *netdev, void *p) | |
1456 | #else | |
41c445ff | 1457 | static int i40e_set_mac(struct net_device *netdev, void *p) |
38e00438 | 1458 | #endif |
41c445ff JB |
1459 | { |
1460 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1461 | struct i40e_vsi *vsi = np->vsi; | |
30650cc5 SN |
1462 | struct i40e_pf *pf = vsi->back; |
1463 | struct i40e_hw *hw = &pf->hw; | |
41c445ff | 1464 | struct sockaddr *addr = p; |
41c445ff JB |
1465 | |
1466 | if (!is_valid_ether_addr(addr->sa_data)) | |
1467 | return -EADDRNOTAVAIL; | |
1468 | ||
30650cc5 SN |
1469 | if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) { |
1470 | netdev_info(netdev, "already using mac address %pM\n", | |
1471 | addr->sa_data); | |
1472 | return 0; | |
1473 | } | |
41c445ff | 1474 | |
80f6428f ASJ |
1475 | if (test_bit(__I40E_DOWN, &vsi->back->state) || |
1476 | test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) | |
1477 | return -EADDRNOTAVAIL; | |
1478 | ||
30650cc5 SN |
1479 | if (ether_addr_equal(hw->mac.addr, addr->sa_data)) |
1480 | netdev_info(netdev, "returning to hw mac address %pM\n", | |
1481 | hw->mac.addr); | |
1482 | else | |
1483 | netdev_info(netdev, "set new mac address %pM\n", addr->sa_data); | |
1484 | ||
278e7d0b | 1485 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
1bc87e80 JK |
1486 | i40e_del_mac_all_vlan(vsi, netdev->dev_addr); |
1487 | i40e_put_mac_in_vlan(vsi, addr->sa_data); | |
278e7d0b | 1488 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 1489 | ether_addr_copy(netdev->dev_addr, addr->sa_data); |
41c445ff JB |
1490 | if (vsi->type == I40E_VSI_MAIN) { |
1491 | i40e_status ret; | |
6995b36c | 1492 | |
41c445ff | 1493 | ret = i40e_aq_mac_address_write(&vsi->back->hw, |
cc41222c | 1494 | I40E_AQC_WRITE_TYPE_LAA_WOL, |
41c445ff | 1495 | addr->sa_data, NULL); |
c3c7ea27 MW |
1496 | if (ret) |
1497 | netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n", | |
1498 | i40e_stat_str(hw, ret), | |
1499 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
30650cc5 SN |
1500 | } |
1501 | ||
c53934c6 JB |
1502 | /* schedule our worker thread which will take care of |
1503 | * applying the new filter changes | |
1504 | */ | |
1505 | i40e_service_event_schedule(vsi->back); | |
1506 | return 0; | |
41c445ff JB |
1507 | } |
1508 | ||
1509 | /** | |
1510 | * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc | |
1511 | * @vsi: the VSI being setup | |
1512 | * @ctxt: VSI context structure | |
1513 | * @enabled_tc: Enabled TCs bitmap | |
1514 | * @is_add: True if called before Add VSI | |
1515 | * | |
1516 | * Setup VSI queue mapping for enabled traffic classes. | |
1517 | **/ | |
38e00438 VD |
1518 | #ifdef I40E_FCOE |
1519 | void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, | |
1520 | struct i40e_vsi_context *ctxt, | |
1521 | u8 enabled_tc, | |
1522 | bool is_add) | |
1523 | #else | |
41c445ff JB |
1524 | static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, |
1525 | struct i40e_vsi_context *ctxt, | |
1526 | u8 enabled_tc, | |
1527 | bool is_add) | |
38e00438 | 1528 | #endif |
41c445ff JB |
1529 | { |
1530 | struct i40e_pf *pf = vsi->back; | |
1531 | u16 sections = 0; | |
1532 | u8 netdev_tc = 0; | |
1533 | u16 numtc = 0; | |
1534 | u16 qcount; | |
1535 | u8 offset; | |
1536 | u16 qmap; | |
1537 | int i; | |
4e3b35b0 | 1538 | u16 num_tc_qps = 0; |
41c445ff JB |
1539 | |
1540 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1541 | offset = 0; | |
1542 | ||
1543 | if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { | |
1544 | /* Find numtc from enabled TC bitmap */ | |
1545 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 1546 | if (enabled_tc & BIT(i)) /* TC is enabled */ |
41c445ff JB |
1547 | numtc++; |
1548 | } | |
1549 | if (!numtc) { | |
1550 | dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n"); | |
1551 | numtc = 1; | |
1552 | } | |
1553 | } else { | |
1554 | /* At least TC0 is enabled in case of non-DCB case */ | |
1555 | numtc = 1; | |
1556 | } | |
1557 | ||
1558 | vsi->tc_config.numtc = numtc; | |
1559 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
4e3b35b0 | 1560 | /* Number of queues per enabled TC */ |
7d64402f CS |
1561 | qcount = vsi->alloc_queue_pairs; |
1562 | ||
7f9ff476 | 1563 | num_tc_qps = qcount / numtc; |
e25d00b8 | 1564 | num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf)); |
41c445ff JB |
1565 | |
1566 | /* Setup queue offset/count for all TCs for given VSI */ | |
1567 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1568 | /* See if the given TC is enabled for the given VSI */ | |
75f5cea9 | 1569 | if (vsi->tc_config.enabled_tc & BIT(i)) { |
41a1d04b | 1570 | /* TC is enabled */ |
41c445ff JB |
1571 | int pow, num_qps; |
1572 | ||
41c445ff JB |
1573 | switch (vsi->type) { |
1574 | case I40E_VSI_MAIN: | |
acd65448 HZ |
1575 | qcount = min_t(int, pf->alloc_rss_size, |
1576 | num_tc_qps); | |
41c445ff | 1577 | break; |
38e00438 VD |
1578 | #ifdef I40E_FCOE |
1579 | case I40E_VSI_FCOE: | |
1580 | qcount = num_tc_qps; | |
1581 | break; | |
1582 | #endif | |
41c445ff JB |
1583 | case I40E_VSI_FDIR: |
1584 | case I40E_VSI_SRIOV: | |
1585 | case I40E_VSI_VMDQ2: | |
1586 | default: | |
4e3b35b0 | 1587 | qcount = num_tc_qps; |
41c445ff JB |
1588 | WARN_ON(i != 0); |
1589 | break; | |
1590 | } | |
4e3b35b0 NP |
1591 | vsi->tc_config.tc_info[i].qoffset = offset; |
1592 | vsi->tc_config.tc_info[i].qcount = qcount; | |
41c445ff | 1593 | |
1e200e4a | 1594 | /* find the next higher power-of-2 of num queue pairs */ |
4e3b35b0 | 1595 | num_qps = qcount; |
41c445ff | 1596 | pow = 0; |
41a1d04b | 1597 | while (num_qps && (BIT_ULL(pow) < qcount)) { |
41c445ff JB |
1598 | pow++; |
1599 | num_qps >>= 1; | |
1600 | } | |
1601 | ||
1602 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1603 | qmap = | |
1604 | (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1605 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1606 | ||
4e3b35b0 | 1607 | offset += qcount; |
41c445ff JB |
1608 | } else { |
1609 | /* TC is not enabled so set the offset to | |
1610 | * default queue and allocate one queue | |
1611 | * for the given TC. | |
1612 | */ | |
1613 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1614 | vsi->tc_config.tc_info[i].qcount = 1; | |
1615 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1616 | ||
1617 | qmap = 0; | |
1618 | } | |
1619 | ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); | |
1620 | } | |
1621 | ||
1622 | /* Set actual Tx/Rx queue pairs */ | |
1623 | vsi->num_queue_pairs = offset; | |
9a3bd2f1 ASJ |
1624 | if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) { |
1625 | if (vsi->req_queue_pairs > 0) | |
1626 | vsi->num_queue_pairs = vsi->req_queue_pairs; | |
26cdc443 | 1627 | else if (pf->flags & I40E_FLAG_MSIX_ENABLED) |
9a3bd2f1 ASJ |
1628 | vsi->num_queue_pairs = pf->num_lan_msix; |
1629 | } | |
41c445ff JB |
1630 | |
1631 | /* Scheduler section valid can only be set for ADD VSI */ | |
1632 | if (is_add) { | |
1633 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1634 | ||
1635 | ctxt->info.up_enable_bits = enabled_tc; | |
1636 | } | |
1637 | if (vsi->type == I40E_VSI_SRIOV) { | |
1638 | ctxt->info.mapping_flags |= | |
1639 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); | |
1640 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
1641 | ctxt->info.queue_mapping[i] = | |
1642 | cpu_to_le16(vsi->base_queue + i); | |
1643 | } else { | |
1644 | ctxt->info.mapping_flags |= | |
1645 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1646 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1647 | } | |
1648 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1649 | } | |
1650 | ||
6622f5cd JK |
1651 | /** |
1652 | * i40e_addr_sync - Callback for dev_(mc|uc)_sync to add address | |
1653 | * @netdev: the netdevice | |
1654 | * @addr: address to add | |
1655 | * | |
1656 | * Called by __dev_(mc|uc)_sync when an address needs to be added. We call | |
1657 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1658 | */ | |
1659 | static int i40e_addr_sync(struct net_device *netdev, const u8 *addr) | |
1660 | { | |
1661 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1662 | struct i40e_vsi *vsi = np->vsi; | |
1663 | struct i40e_mac_filter *f; | |
1664 | ||
1665 | if (i40e_is_vsi_in_vlan(vsi)) | |
1666 | f = i40e_put_mac_in_vlan(vsi, addr); | |
1667 | else | |
1668 | f = i40e_add_filter(vsi, addr, I40E_VLAN_ANY); | |
1669 | ||
1670 | if (f) | |
1671 | return 0; | |
1672 | else | |
1673 | return -ENOMEM; | |
1674 | } | |
1675 | ||
1676 | /** | |
1677 | * i40e_addr_unsync - Callback for dev_(mc|uc)_sync to remove address | |
1678 | * @netdev: the netdevice | |
1679 | * @addr: address to add | |
1680 | * | |
1681 | * Called by __dev_(mc|uc)_sync when an address needs to be removed. We call | |
1682 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1683 | */ | |
1684 | static int i40e_addr_unsync(struct net_device *netdev, const u8 *addr) | |
1685 | { | |
1686 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1687 | struct i40e_vsi *vsi = np->vsi; | |
1688 | ||
1689 | if (i40e_is_vsi_in_vlan(vsi)) | |
1690 | i40e_del_mac_all_vlan(vsi, addr); | |
1691 | else | |
1692 | i40e_del_filter(vsi, addr, I40E_VLAN_ANY); | |
1693 | ||
1694 | return 0; | |
1695 | } | |
1696 | ||
41c445ff JB |
1697 | /** |
1698 | * i40e_set_rx_mode - NDO callback to set the netdev filters | |
1699 | * @netdev: network interface device structure | |
1700 | **/ | |
38e00438 VD |
1701 | #ifdef I40E_FCOE |
1702 | void i40e_set_rx_mode(struct net_device *netdev) | |
1703 | #else | |
41c445ff | 1704 | static void i40e_set_rx_mode(struct net_device *netdev) |
38e00438 | 1705 | #endif |
41c445ff JB |
1706 | { |
1707 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 1708 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 1709 | |
278e7d0b | 1710 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 1711 | |
6622f5cd JK |
1712 | __dev_uc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); |
1713 | __dev_mc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); | |
41c445ff | 1714 | |
278e7d0b | 1715 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
1716 | |
1717 | /* check for other flag changes */ | |
1718 | if (vsi->current_netdev_flags != vsi->netdev->flags) { | |
1719 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1720 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1721 | } | |
c53934c6 JB |
1722 | |
1723 | /* schedule our worker thread which will take care of | |
1724 | * applying the new filter changes | |
1725 | */ | |
1726 | i40e_service_event_schedule(vsi->back); | |
41c445ff JB |
1727 | } |
1728 | ||
21659035 | 1729 | /** |
4a2ce27b JK |
1730 | * i40e_undo_filter_entries - Undo the changes made to MAC filter entries |
1731 | * @vsi: Pointer to VSI struct | |
21659035 KP |
1732 | * @from: Pointer to list which contains MAC filter entries - changes to |
1733 | * those entries needs to be undone. | |
1734 | * | |
4a2ce27b JK |
1735 | * MAC filter entries from list were slated to be sent to firmware, either for |
1736 | * addition or deletion. | |
21659035 | 1737 | **/ |
4a2ce27b JK |
1738 | static void i40e_undo_filter_entries(struct i40e_vsi *vsi, |
1739 | struct hlist_head *from) | |
21659035 | 1740 | { |
278e7d0b JK |
1741 | struct i40e_mac_filter *f; |
1742 | struct hlist_node *h; | |
1743 | ||
1744 | hlist_for_each_entry_safe(f, h, from, hlist) { | |
1745 | u64 key = i40e_addr_to_hkey(f->macaddr); | |
21659035 | 1746 | |
21659035 | 1747 | /* Move the element back into MAC filter list*/ |
278e7d0b JK |
1748 | hlist_del(&f->hlist); |
1749 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
21659035 KP |
1750 | } |
1751 | } | |
1752 | ||
1753 | /** | |
c3c7ea27 MW |
1754 | * i40e_update_filter_state - Update filter state based on return data |
1755 | * from firmware | |
1756 | * @count: Number of filters added | |
1757 | * @add_list: return data from fw | |
1758 | * @head: pointer to first filter in current batch | |
1759 | * @aq_err: status from fw | |
21659035 | 1760 | * |
c3c7ea27 MW |
1761 | * MAC filter entries from list were slated to be added to device. Returns |
1762 | * number of successful filters. Note that 0 does NOT mean success! | |
21659035 | 1763 | **/ |
c3c7ea27 MW |
1764 | static int |
1765 | i40e_update_filter_state(int count, | |
1766 | struct i40e_aqc_add_macvlan_element_data *add_list, | |
1767 | struct i40e_mac_filter *add_head, int aq_err) | |
21659035 | 1768 | { |
c3c7ea27 MW |
1769 | int retval = 0; |
1770 | int i; | |
21659035 | 1771 | |
21659035 | 1772 | |
c3c7ea27 MW |
1773 | if (!aq_err) { |
1774 | retval = count; | |
1775 | /* Everything's good, mark all filters active. */ | |
1776 | for (i = 0; i < count ; i++) { | |
1777 | add_head->state = I40E_FILTER_ACTIVE; | |
278e7d0b JK |
1778 | add_head = hlist_entry(add_head->hlist.next, |
1779 | typeof(struct i40e_mac_filter), | |
1780 | hlist); | |
c3c7ea27 MW |
1781 | } |
1782 | } else if (aq_err == I40E_AQ_RC_ENOSPC) { | |
1783 | /* Device ran out of filter space. Check the return value | |
1784 | * for each filter to see which ones are active. | |
1785 | */ | |
1786 | for (i = 0; i < count ; i++) { | |
1787 | if (add_list[i].match_method == | |
1788 | I40E_AQC_MM_ERR_NO_RES) { | |
1789 | add_head->state = I40E_FILTER_FAILED; | |
1790 | } else { | |
1791 | add_head->state = I40E_FILTER_ACTIVE; | |
1792 | retval++; | |
1793 | } | |
278e7d0b JK |
1794 | add_head = hlist_entry(add_head->hlist.next, |
1795 | typeof(struct i40e_mac_filter), | |
1796 | hlist); | |
c3c7ea27 MW |
1797 | } |
1798 | } else { | |
1799 | /* Some other horrible thing happened, fail all filters */ | |
1800 | retval = 0; | |
1801 | for (i = 0; i < count ; i++) { | |
1802 | add_head->state = I40E_FILTER_FAILED; | |
278e7d0b JK |
1803 | add_head = hlist_entry(add_head->hlist.next, |
1804 | typeof(struct i40e_mac_filter), | |
1805 | hlist); | |
c3c7ea27 | 1806 | } |
21659035 | 1807 | } |
c3c7ea27 | 1808 | return retval; |
21659035 KP |
1809 | } |
1810 | ||
00936319 JK |
1811 | /** |
1812 | * i40e_aqc_del_filters - Request firmware to delete a set of filters | |
1813 | * @vsi: ptr to the VSI | |
1814 | * @vsi_name: name to display in messages | |
1815 | * @list: the list of filters to send to firmware | |
1816 | * @num_del: the number of filters to delete | |
1817 | * @retval: Set to -EIO on failure to delete | |
1818 | * | |
1819 | * Send a request to firmware via AdminQ to delete a set of filters. Uses | |
1820 | * *retval instead of a return value so that success does not force ret_val to | |
1821 | * be set to 0. This ensures that a sequence of calls to this function | |
1822 | * preserve the previous value of *retval on successful delete. | |
1823 | */ | |
1824 | static | |
1825 | void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
1826 | struct i40e_aqc_remove_macvlan_element_data *list, | |
1827 | int num_del, int *retval) | |
1828 | { | |
1829 | struct i40e_hw *hw = &vsi->back->hw; | |
1830 | i40e_status aq_ret; | |
1831 | int aq_err; | |
1832 | ||
1833 | aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, list, num_del, NULL); | |
1834 | aq_err = hw->aq.asq_last_status; | |
1835 | ||
1836 | /* Explicitly ignore and do not report when firmware returns ENOENT */ | |
1837 | if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { | |
1838 | *retval = -EIO; | |
1839 | dev_info(&vsi->back->pdev->dev, | |
1840 | "ignoring delete macvlan error on %s, err %s, aq_err %s\n", | |
1841 | vsi_name, i40e_stat_str(hw, aq_ret), | |
1842 | i40e_aq_str(hw, aq_err)); | |
1843 | } | |
1844 | } | |
1845 | ||
1846 | /** | |
1847 | * i40e_aqc_add_filters - Request firmware to add a set of filters | |
1848 | * @vsi: ptr to the VSI | |
1849 | * @vsi_name: name to display in messages | |
1850 | * @list: the list of filters to send to firmware | |
1851 | * @add_head: Position in the add hlist | |
1852 | * @num_add: the number of filters to add | |
1853 | * @promisc_change: set to true on exit if promiscuous mode was forced on | |
1854 | * | |
1855 | * Send a request to firmware via AdminQ to add a chunk of filters. Will set | |
1856 | * promisc_changed to true if the firmware has run out of space for more | |
1857 | * filters. | |
1858 | */ | |
1859 | static | |
1860 | void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
1861 | struct i40e_aqc_add_macvlan_element_data *list, | |
1862 | struct i40e_mac_filter *add_head, | |
1863 | int num_add, bool *promisc_changed) | |
1864 | { | |
1865 | struct i40e_hw *hw = &vsi->back->hw; | |
1866 | i40e_status aq_ret; | |
1867 | int aq_err, fcnt; | |
1868 | ||
1869 | aq_ret = i40e_aq_add_macvlan(hw, vsi->seid, list, num_add, NULL); | |
1870 | aq_err = hw->aq.asq_last_status; | |
1871 | fcnt = i40e_update_filter_state(num_add, list, add_head, aq_ret); | |
1872 | vsi->active_filters += fcnt; | |
1873 | ||
1874 | if (fcnt != num_add) { | |
1875 | *promisc_changed = true; | |
1876 | set_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); | |
1877 | vsi->promisc_threshold = (vsi->active_filters * 3) / 4; | |
1878 | dev_warn(&vsi->back->pdev->dev, | |
1879 | "Error %s adding RX filters on %s, promiscuous mode forced on\n", | |
1880 | i40e_aq_str(hw, aq_err), | |
1881 | vsi_name); | |
1882 | } | |
1883 | } | |
1884 | ||
435c084a JK |
1885 | /** |
1886 | * i40e_aqc_broadcast_filter - Set promiscuous broadcast flags | |
1887 | * @vsi: pointer to the VSI | |
1888 | * @f: filter data | |
1889 | * | |
1890 | * This function sets or clears the promiscuous broadcast flags for VLAN | |
1891 | * filters in order to properly receive broadcast frames. Assumes that only | |
1892 | * broadcast filters are passed. | |
1893 | **/ | |
1894 | static | |
1895 | void i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name, | |
1896 | struct i40e_mac_filter *f) | |
1897 | { | |
1898 | bool enable = f->state == I40E_FILTER_NEW; | |
1899 | struct i40e_hw *hw = &vsi->back->hw; | |
1900 | i40e_status aq_ret; | |
1901 | ||
1902 | if (f->vlan == I40E_VLAN_ANY) { | |
1903 | aq_ret = i40e_aq_set_vsi_broadcast(hw, | |
1904 | vsi->seid, | |
1905 | enable, | |
1906 | NULL); | |
1907 | } else { | |
1908 | aq_ret = i40e_aq_set_vsi_bc_promisc_on_vlan(hw, | |
1909 | vsi->seid, | |
1910 | enable, | |
1911 | f->vlan, | |
1912 | NULL); | |
1913 | } | |
1914 | ||
1915 | if (aq_ret) { | |
1916 | dev_warn(&vsi->back->pdev->dev, | |
1917 | "Error %s setting broadcast promiscuous mode on %s\n", | |
1918 | i40e_aq_str(hw, hw->aq.asq_last_status), | |
1919 | vsi_name); | |
1920 | f->state = I40E_FILTER_FAILED; | |
1921 | } else if (enable) { | |
1922 | f->state = I40E_FILTER_ACTIVE; | |
1923 | } | |
1924 | } | |
1925 | ||
41c445ff JB |
1926 | /** |
1927 | * i40e_sync_vsi_filters - Update the VSI filter list to the HW | |
1928 | * @vsi: ptr to the VSI | |
1929 | * | |
1930 | * Push any outstanding VSI filter changes through the AdminQ. | |
1931 | * | |
1932 | * Returns 0 or error value | |
1933 | **/ | |
17652c63 | 1934 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi) |
41c445ff | 1935 | { |
278e7d0b | 1936 | struct hlist_head tmp_add_list, tmp_del_list; |
84f5ca6c | 1937 | struct i40e_mac_filter *f, *add_head = NULL; |
3e25a8f3 | 1938 | struct i40e_hw *hw = &vsi->back->hw; |
84f5ca6c AB |
1939 | unsigned int vlan_any_filters = 0; |
1940 | unsigned int non_vlan_filters = 0; | |
1941 | unsigned int vlan_filters = 0; | |
c3c7ea27 | 1942 | bool promisc_changed = false; |
2d1de828 | 1943 | char vsi_name[16] = "PF"; |
41c445ff | 1944 | int filter_list_len = 0; |
ea02e90b | 1945 | i40e_status aq_ret = 0; |
84f5ca6c | 1946 | u32 changed_flags = 0; |
278e7d0b | 1947 | struct hlist_node *h; |
41c445ff JB |
1948 | struct i40e_pf *pf; |
1949 | int num_add = 0; | |
1950 | int num_del = 0; | |
84f5ca6c | 1951 | int retval = 0; |
41c445ff | 1952 | u16 cmd_flags; |
c3c7ea27 | 1953 | int list_size; |
278e7d0b | 1954 | int bkt; |
41c445ff JB |
1955 | |
1956 | /* empty array typed pointers, kcalloc later */ | |
1957 | struct i40e_aqc_add_macvlan_element_data *add_list; | |
1958 | struct i40e_aqc_remove_macvlan_element_data *del_list; | |
1959 | ||
1960 | while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state)) | |
1961 | usleep_range(1000, 2000); | |
1962 | pf = vsi->back; | |
1963 | ||
1964 | if (vsi->netdev) { | |
1965 | changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags; | |
1966 | vsi->current_netdev_flags = vsi->netdev->flags; | |
1967 | } | |
1968 | ||
278e7d0b JK |
1969 | INIT_HLIST_HEAD(&tmp_add_list); |
1970 | INIT_HLIST_HEAD(&tmp_del_list); | |
21659035 | 1971 | |
2d1de828 SN |
1972 | if (vsi->type == I40E_VSI_SRIOV) |
1973 | snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id); | |
1974 | else if (vsi->type != I40E_VSI_MAIN) | |
1975 | snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid); | |
1976 | ||
41c445ff JB |
1977 | if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) { |
1978 | vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED; | |
1979 | ||
278e7d0b | 1980 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 1981 | /* Create a list of filters to delete. */ |
278e7d0b | 1982 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 1983 | if (f->state == I40E_FILTER_REMOVE) { |
c3c7ea27 | 1984 | /* Move the element into temporary del_list */ |
278e7d0b JK |
1985 | hash_del(&f->hlist); |
1986 | hlist_add_head(&f->hlist, &tmp_del_list); | |
c3c7ea27 | 1987 | vsi->active_filters--; |
84f5ca6c AB |
1988 | |
1989 | /* Avoid counting removed filters */ | |
1990 | continue; | |
c3c7ea27 MW |
1991 | } |
1992 | if (f->state == I40E_FILTER_NEW) { | |
278e7d0b JK |
1993 | hash_del(&f->hlist); |
1994 | hlist_add_head(&f->hlist, &tmp_add_list); | |
21659035 | 1995 | } |
84f5ca6c AB |
1996 | |
1997 | /* Count the number of each type of filter we have | |
1998 | * remaining, ignoring any filters we're about to | |
1999 | * delete. | |
2000 | */ | |
2001 | if (f->vlan > 0) | |
2002 | vlan_filters++; | |
2003 | else if (!f->vlan) | |
2004 | non_vlan_filters++; | |
2005 | else | |
2006 | vlan_any_filters++; | |
2007 | } | |
2008 | ||
2009 | /* We should never have VLAN=-1 filters at the same time as we | |
2010 | * have either VLAN=0 or VLAN>0 filters, so warn about this | |
2011 | * case here to help catch any issues. | |
2012 | */ | |
2013 | WARN_ON(vlan_any_filters && (vlan_filters + non_vlan_filters)); | |
2014 | ||
2015 | /* If we only have VLAN=0 filters remaining, and don't have | |
2016 | * any other VLAN filters, we need to convert these VLAN=0 | |
2017 | * filters into VLAN=-1 (I40E_VLAN_ANY) so that we operate | |
2018 | * correctly in non-VLAN mode and receive all traffic tagged | |
2019 | * or untagged. | |
2020 | */ | |
2021 | if (non_vlan_filters && !vlan_filters) { | |
2022 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, | |
2023 | hlist) { | |
2024 | /* Only replace VLAN=0 filters */ | |
2025 | if (f->vlan) | |
2026 | continue; | |
2027 | ||
2028 | /* Allocate a replacement element */ | |
2029 | add_head = kzalloc(sizeof(*add_head), | |
2030 | GFP_KERNEL); | |
2031 | if (!add_head) | |
2032 | goto err_no_memory_locked; | |
2033 | ||
2034 | /* Copy the filter, with new state and VLAN */ | |
2035 | *add_head = *f; | |
2036 | add_head->state = I40E_FILTER_NEW; | |
2037 | add_head->vlan = I40E_VLAN_ANY; | |
2038 | ||
2039 | /* Move the replacement to the add list */ | |
2040 | INIT_HLIST_NODE(&add_head->hlist); | |
2041 | hlist_add_head(&add_head->hlist, | |
2042 | &tmp_add_list); | |
2043 | ||
2044 | /* Move the original to the delete list */ | |
2045 | f->state = I40E_FILTER_REMOVE; | |
2046 | hash_del(&f->hlist); | |
2047 | hlist_add_head(&f->hlist, &tmp_del_list); | |
2048 | vsi->active_filters--; | |
2049 | } | |
2050 | ||
2051 | /* Also update any filters on the tmp_add list */ | |
2052 | hlist_for_each_entry(f, &tmp_add_list, hlist) { | |
2053 | if (!f->vlan) | |
2054 | f->vlan = I40E_VLAN_ANY; | |
2055 | } | |
2056 | add_head = NULL; | |
21659035 | 2057 | } |
278e7d0b | 2058 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 KP |
2059 | } |
2060 | ||
2061 | /* Now process 'del_list' outside the lock */ | |
278e7d0b | 2062 | if (!hlist_empty(&tmp_del_list)) { |
3e25a8f3 | 2063 | filter_list_len = hw->aq.asq_buf_size / |
21659035 | 2064 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2065 | list_size = filter_list_len * |
f1199998 | 2066 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2067 | del_list = kzalloc(list_size, GFP_ATOMIC); |
4a2ce27b JK |
2068 | if (!del_list) |
2069 | goto err_no_memory; | |
21659035 | 2070 | |
278e7d0b | 2071 | hlist_for_each_entry_safe(f, h, &tmp_del_list, hlist) { |
41c445ff JB |
2072 | cmd_flags = 0; |
2073 | ||
435c084a JK |
2074 | /* handle broadcast filters by updating the broadcast |
2075 | * promiscuous flag instead of deleting a MAC filter. | |
2076 | */ | |
2077 | if (is_broadcast_ether_addr(f->macaddr)) { | |
2078 | i40e_aqc_broadcast_filter(vsi, vsi_name, f); | |
2079 | ||
2080 | hlist_del(&f->hlist); | |
2081 | kfree(f); | |
2082 | continue; | |
2083 | } | |
2084 | ||
41c445ff | 2085 | /* add to delete list */ |
9a173901 | 2086 | ether_addr_copy(del_list[num_del].mac_addr, f->macaddr); |
c3c7ea27 MW |
2087 | if (f->vlan == I40E_VLAN_ANY) { |
2088 | del_list[num_del].vlan_tag = 0; | |
a6cb9146 | 2089 | cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; |
c3c7ea27 MW |
2090 | } else { |
2091 | del_list[num_del].vlan_tag = | |
2092 | cpu_to_le16((u16)(f->vlan)); | |
2093 | } | |
41c445ff | 2094 | |
41c445ff JB |
2095 | cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; |
2096 | del_list[num_del].flags = cmd_flags; | |
2097 | num_del++; | |
2098 | ||
41c445ff JB |
2099 | /* flush a full buffer */ |
2100 | if (num_del == filter_list_len) { | |
00936319 JK |
2101 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2102 | num_del, &retval); | |
c3c7ea27 | 2103 | memset(del_list, 0, list_size); |
00936319 | 2104 | num_del = 0; |
41c445ff | 2105 | } |
21659035 KP |
2106 | /* Release memory for MAC filter entries which were |
2107 | * synced up with HW. | |
2108 | */ | |
278e7d0b | 2109 | hlist_del(&f->hlist); |
21659035 | 2110 | kfree(f); |
41c445ff | 2111 | } |
21659035 | 2112 | |
41c445ff | 2113 | if (num_del) { |
00936319 JK |
2114 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2115 | num_del, &retval); | |
41c445ff JB |
2116 | } |
2117 | ||
2118 | kfree(del_list); | |
2119 | del_list = NULL; | |
21659035 KP |
2120 | } |
2121 | ||
cbebb85f JK |
2122 | /* After finishing notifying firmware of the deleted filters, update |
2123 | * the cached value of vsi->has_vlan_filter. Note that we are safe to | |
2124 | * use just !!vlan_filters here because if we only have VLAN=0 (that | |
2125 | * is, non_vlan_filters) these will all be converted to VLAN=-1 in the | |
2126 | * logic above already so this value would still be correct. | |
2127 | */ | |
2128 | vsi->has_vlan_filter = !!vlan_filters; | |
2129 | ||
278e7d0b | 2130 | if (!hlist_empty(&tmp_add_list)) { |
c3c7ea27 | 2131 | /* Do all the adds now. */ |
3e25a8f3 | 2132 | filter_list_len = hw->aq.asq_buf_size / |
f1199998 | 2133 | sizeof(struct i40e_aqc_add_macvlan_element_data); |
c3c7ea27 MW |
2134 | list_size = filter_list_len * |
2135 | sizeof(struct i40e_aqc_add_macvlan_element_data); | |
2136 | add_list = kzalloc(list_size, GFP_ATOMIC); | |
4a2ce27b JK |
2137 | if (!add_list) |
2138 | goto err_no_memory; | |
2139 | ||
c3c7ea27 | 2140 | num_add = 0; |
435c084a | 2141 | hlist_for_each_entry_safe(f, h, &tmp_add_list, hlist) { |
c3c7ea27 MW |
2142 | if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, |
2143 | &vsi->state)) { | |
2144 | f->state = I40E_FILTER_FAILED; | |
2145 | continue; | |
2146 | } | |
435c084a JK |
2147 | |
2148 | /* handle broadcast filters by updating the broadcast | |
2149 | * promiscuous flag instead of adding a MAC filter. | |
2150 | */ | |
2151 | if (is_broadcast_ether_addr(f->macaddr)) { | |
2152 | u64 key = i40e_addr_to_hkey(f->macaddr); | |
2153 | i40e_aqc_broadcast_filter(vsi, vsi_name, f); | |
2154 | ||
2155 | hlist_del(&f->hlist); | |
2156 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
2157 | continue; | |
2158 | } | |
2159 | ||
41c445ff | 2160 | /* add to add array */ |
c3c7ea27 MW |
2161 | if (num_add == 0) |
2162 | add_head = f; | |
2163 | cmd_flags = 0; | |
9a173901 | 2164 | ether_addr_copy(add_list[num_add].mac_addr, f->macaddr); |
c3c7ea27 MW |
2165 | if (f->vlan == I40E_VLAN_ANY) { |
2166 | add_list[num_add].vlan_tag = 0; | |
2167 | cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
2168 | } else { | |
2169 | add_list[num_add].vlan_tag = | |
2170 | cpu_to_le16((u16)(f->vlan)); | |
2171 | } | |
41c445ff | 2172 | add_list[num_add].queue_number = 0; |
41c445ff | 2173 | cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; |
41c445ff JB |
2174 | add_list[num_add].flags = cpu_to_le16(cmd_flags); |
2175 | num_add++; | |
2176 | ||
2177 | /* flush a full buffer */ | |
2178 | if (num_add == filter_list_len) { | |
00936319 JK |
2179 | i40e_aqc_add_filters(vsi, vsi_name, add_list, |
2180 | add_head, num_add, | |
2181 | &promisc_changed); | |
c3c7ea27 | 2182 | memset(add_list, 0, list_size); |
41c445ff | 2183 | num_add = 0; |
41c445ff JB |
2184 | } |
2185 | } | |
2186 | if (num_add) { | |
00936319 JK |
2187 | i40e_aqc_add_filters(vsi, vsi_name, add_list, add_head, |
2188 | num_add, &promisc_changed); | |
41c445ff | 2189 | } |
c3c7ea27 MW |
2190 | /* Now move all of the filters from the temp add list back to |
2191 | * the VSI's list. | |
2192 | */ | |
278e7d0b JK |
2193 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
2194 | hlist_for_each_entry_safe(f, h, &tmp_add_list, hlist) { | |
2195 | u64 key = i40e_addr_to_hkey(f->macaddr); | |
2196 | ||
2197 | hlist_del(&f->hlist); | |
2198 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
c3c7ea27 | 2199 | } |
278e7d0b | 2200 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
2201 | kfree(add_list); |
2202 | add_list = NULL; | |
c3c7ea27 | 2203 | } |
41c445ff | 2204 | |
c3c7ea27 MW |
2205 | /* Check to see if we can drop out of overflow promiscuous mode. */ |
2206 | if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state) && | |
2207 | (vsi->active_filters < vsi->promisc_threshold)) { | |
2208 | int failed_count = 0; | |
2209 | /* See if we have any failed filters. We can't drop out of | |
2210 | * promiscuous until these have all been deleted. | |
2211 | */ | |
278e7d0b JK |
2212 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
2213 | hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) { | |
c3c7ea27 MW |
2214 | if (f->state == I40E_FILTER_FAILED) |
2215 | failed_count++; | |
2216 | } | |
278e7d0b | 2217 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 2218 | if (!failed_count) { |
41c445ff | 2219 | dev_info(&pf->pdev->dev, |
c3c7ea27 MW |
2220 | "filter logjam cleared on %s, leaving overflow promiscuous mode\n", |
2221 | vsi_name); | |
2222 | clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); | |
2223 | promisc_changed = true; | |
2224 | vsi->promisc_threshold = 0; | |
41c445ff JB |
2225 | } |
2226 | } | |
2227 | ||
a856b5cb ASJ |
2228 | /* if the VF is not trusted do not do promisc */ |
2229 | if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) { | |
2230 | clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); | |
2231 | goto out; | |
2232 | } | |
2233 | ||
41c445ff JB |
2234 | /* check for changes in promiscuous modes */ |
2235 | if (changed_flags & IFF_ALLMULTI) { | |
2236 | bool cur_multipromisc; | |
6995b36c | 2237 | |
41c445ff | 2238 | cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI); |
ea02e90b MW |
2239 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw, |
2240 | vsi->seid, | |
2241 | cur_multipromisc, | |
2242 | NULL); | |
2243 | if (aq_ret) { | |
2244 | retval = i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2245 | hw->aq.asq_last_status); |
41c445ff | 2246 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2247 | "set multi promisc failed on %s, err %s aq_err %s\n", |
2248 | vsi_name, | |
3e25a8f3 MW |
2249 | i40e_stat_str(hw, aq_ret), |
2250 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2251 | } |
41c445ff | 2252 | } |
c3c7ea27 MW |
2253 | if ((changed_flags & IFF_PROMISC) || |
2254 | (promisc_changed && | |
2255 | test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state))) { | |
41c445ff | 2256 | bool cur_promisc; |
6995b36c | 2257 | |
41c445ff JB |
2258 | cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) || |
2259 | test_bit(__I40E_FILTER_OVERFLOW_PROMISC, | |
2260 | &vsi->state)); | |
6784ed5a ASJ |
2261 | if ((vsi->type == I40E_VSI_MAIN) && |
2262 | (pf->lan_veb != I40E_NO_VEB) && | |
2263 | !(pf->flags & I40E_FLAG_MFP_ENABLED)) { | |
92faef85 ASJ |
2264 | /* set defport ON for Main VSI instead of true promisc |
2265 | * this way we will get all unicast/multicast and VLAN | |
2266 | * promisc behavior but will not get VF or VMDq traffic | |
2267 | * replicated on the Main VSI. | |
2268 | */ | |
2269 | if (pf->cur_promisc != cur_promisc) { | |
2270 | pf->cur_promisc = cur_promisc; | |
5bc16031 MW |
2271 | if (cur_promisc) |
2272 | aq_ret = | |
2273 | i40e_aq_set_default_vsi(hw, | |
2274 | vsi->seid, | |
2275 | NULL); | |
2276 | else | |
2277 | aq_ret = | |
2278 | i40e_aq_clear_default_vsi(hw, | |
2279 | vsi->seid, | |
2280 | NULL); | |
2281 | if (aq_ret) { | |
2282 | retval = i40e_aq_rc_to_posix(aq_ret, | |
2283 | hw->aq.asq_last_status); | |
2284 | dev_info(&pf->pdev->dev, | |
2d1de828 SN |
2285 | "Set default VSI failed on %s, err %s, aq_err %s\n", |
2286 | vsi_name, | |
5bc16031 MW |
2287 | i40e_stat_str(hw, aq_ret), |
2288 | i40e_aq_str(hw, | |
2289 | hw->aq.asq_last_status)); | |
2290 | } | |
92faef85 ASJ |
2291 | } |
2292 | } else { | |
ea02e90b | 2293 | aq_ret = i40e_aq_set_vsi_unicast_promiscuous( |
3e25a8f3 | 2294 | hw, |
f1c7e72e | 2295 | vsi->seid, |
b5569892 ASJ |
2296 | cur_promisc, NULL, |
2297 | true); | |
ea02e90b MW |
2298 | if (aq_ret) { |
2299 | retval = | |
2300 | i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2301 | hw->aq.asq_last_status); |
92faef85 | 2302 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2303 | "set unicast promisc failed on %s, err %s, aq_err %s\n", |
2304 | vsi_name, | |
3e25a8f3 MW |
2305 | i40e_stat_str(hw, aq_ret), |
2306 | i40e_aq_str(hw, | |
2307 | hw->aq.asq_last_status)); | |
ea02e90b MW |
2308 | } |
2309 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous( | |
3e25a8f3 | 2310 | hw, |
92faef85 ASJ |
2311 | vsi->seid, |
2312 | cur_promisc, NULL); | |
ea02e90b MW |
2313 | if (aq_ret) { |
2314 | retval = | |
2315 | i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2316 | hw->aq.asq_last_status); |
92faef85 | 2317 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2318 | "set multicast promisc failed on %s, err %s, aq_err %s\n", |
2319 | vsi_name, | |
3e25a8f3 MW |
2320 | i40e_stat_str(hw, aq_ret), |
2321 | i40e_aq_str(hw, | |
2322 | hw->aq.asq_last_status)); | |
ea02e90b | 2323 | } |
92faef85 | 2324 | } |
ea02e90b MW |
2325 | aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw, |
2326 | vsi->seid, | |
2327 | cur_promisc, NULL); | |
2328 | if (aq_ret) { | |
2329 | retval = i40e_aq_rc_to_posix(aq_ret, | |
2330 | pf->hw.aq.asq_last_status); | |
1a10370a | 2331 | dev_info(&pf->pdev->dev, |
f1c7e72e | 2332 | "set brdcast promisc failed, err %s, aq_err %s\n", |
3e25a8f3 MW |
2333 | i40e_stat_str(hw, aq_ret), |
2334 | i40e_aq_str(hw, | |
2335 | hw->aq.asq_last_status)); | |
ea02e90b | 2336 | } |
41c445ff | 2337 | } |
ea02e90b | 2338 | out: |
2818ccd9 JB |
2339 | /* if something went wrong then set the changed flag so we try again */ |
2340 | if (retval) | |
2341 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
2342 | ||
41c445ff | 2343 | clear_bit(__I40E_CONFIG_BUSY, &vsi->state); |
ea02e90b | 2344 | return retval; |
4a2ce27b JK |
2345 | |
2346 | err_no_memory: | |
2347 | /* Restore elements on the temporary add and delete lists */ | |
2348 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
84f5ca6c | 2349 | err_no_memory_locked: |
4a2ce27b JK |
2350 | i40e_undo_filter_entries(vsi, &tmp_del_list); |
2351 | i40e_undo_filter_entries(vsi, &tmp_add_list); | |
2352 | spin_unlock_bh(&vsi->mac_filter_hash_lock); | |
2353 | ||
2354 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
2355 | clear_bit(__I40E_CONFIG_BUSY, &vsi->state); | |
2356 | return -ENOMEM; | |
41c445ff JB |
2357 | } |
2358 | ||
2359 | /** | |
2360 | * i40e_sync_filters_subtask - Sync the VSI filter list with HW | |
2361 | * @pf: board private structure | |
2362 | **/ | |
2363 | static void i40e_sync_filters_subtask(struct i40e_pf *pf) | |
2364 | { | |
2365 | int v; | |
2366 | ||
2367 | if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC)) | |
2368 | return; | |
2369 | pf->flags &= ~I40E_FLAG_FILTER_SYNC; | |
2370 | ||
505682cd | 2371 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 2372 | if (pf->vsi[v] && |
17652c63 JB |
2373 | (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) { |
2374 | int ret = i40e_sync_vsi_filters(pf->vsi[v]); | |
2375 | ||
2376 | if (ret) { | |
2377 | /* come back and try again later */ | |
2378 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
2379 | break; | |
2380 | } | |
2381 | } | |
41c445ff JB |
2382 | } |
2383 | } | |
2384 | ||
2385 | /** | |
2386 | * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit | |
2387 | * @netdev: network interface device structure | |
2388 | * @new_mtu: new value for maximum frame size | |
2389 | * | |
2390 | * Returns 0 on success, negative on failure | |
2391 | **/ | |
2392 | static int i40e_change_mtu(struct net_device *netdev, int new_mtu) | |
2393 | { | |
2394 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff JB |
2395 | struct i40e_vsi *vsi = np->vsi; |
2396 | ||
41c445ff JB |
2397 | netdev_info(netdev, "changing MTU from %d to %d\n", |
2398 | netdev->mtu, new_mtu); | |
2399 | netdev->mtu = new_mtu; | |
2400 | if (netif_running(netdev)) | |
2401 | i40e_vsi_reinit_locked(vsi); | |
e3219ce6 | 2402 | i40e_notify_client_of_l2_param_changes(vsi); |
41c445ff JB |
2403 | return 0; |
2404 | } | |
2405 | ||
beb0dff1 JK |
2406 | /** |
2407 | * i40e_ioctl - Access the hwtstamp interface | |
2408 | * @netdev: network interface device structure | |
2409 | * @ifr: interface request data | |
2410 | * @cmd: ioctl command | |
2411 | **/ | |
2412 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
2413 | { | |
2414 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2415 | struct i40e_pf *pf = np->vsi->back; | |
2416 | ||
2417 | switch (cmd) { | |
2418 | case SIOCGHWTSTAMP: | |
2419 | return i40e_ptp_get_ts_config(pf, ifr); | |
2420 | case SIOCSHWTSTAMP: | |
2421 | return i40e_ptp_set_ts_config(pf, ifr); | |
2422 | default: | |
2423 | return -EOPNOTSUPP; | |
2424 | } | |
2425 | } | |
2426 | ||
41c445ff JB |
2427 | /** |
2428 | * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI | |
2429 | * @vsi: the vsi being adjusted | |
2430 | **/ | |
2431 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi) | |
2432 | { | |
2433 | struct i40e_vsi_context ctxt; | |
2434 | i40e_status ret; | |
2435 | ||
2436 | if ((vsi->info.valid_sections & | |
2437 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2438 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0)) | |
2439 | return; /* already enabled */ | |
2440 | ||
2441 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2442 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2443 | I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; | |
2444 | ||
2445 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2446 | ctxt.info = vsi->info; |
41c445ff JB |
2447 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2448 | if (ret) { | |
2449 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2450 | "update vlan stripping failed, err %s aq_err %s\n", |
2451 | i40e_stat_str(&vsi->back->hw, ret), | |
2452 | i40e_aq_str(&vsi->back->hw, | |
2453 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2454 | } |
2455 | } | |
2456 | ||
2457 | /** | |
2458 | * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI | |
2459 | * @vsi: the vsi being adjusted | |
2460 | **/ | |
2461 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi) | |
2462 | { | |
2463 | struct i40e_vsi_context ctxt; | |
2464 | i40e_status ret; | |
2465 | ||
2466 | if ((vsi->info.valid_sections & | |
2467 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2468 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) == | |
2469 | I40E_AQ_VSI_PVLAN_EMOD_MASK)) | |
2470 | return; /* already disabled */ | |
2471 | ||
2472 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2473 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2474 | I40E_AQ_VSI_PVLAN_EMOD_NOTHING; | |
2475 | ||
2476 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2477 | ctxt.info = vsi->info; |
41c445ff JB |
2478 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2479 | if (ret) { | |
2480 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2481 | "update vlan stripping failed, err %s aq_err %s\n", |
2482 | i40e_stat_str(&vsi->back->hw, ret), | |
2483 | i40e_aq_str(&vsi->back->hw, | |
2484 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2485 | } |
2486 | } | |
2487 | ||
2488 | /** | |
2489 | * i40e_vlan_rx_register - Setup or shutdown vlan offload | |
2490 | * @netdev: network interface to be adjusted | |
2491 | * @features: netdev features to test if VLAN offload is enabled or not | |
2492 | **/ | |
2493 | static void i40e_vlan_rx_register(struct net_device *netdev, u32 features) | |
2494 | { | |
2495 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2496 | struct i40e_vsi *vsi = np->vsi; | |
2497 | ||
2498 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2499 | i40e_vlan_stripping_enable(vsi); | |
2500 | else | |
2501 | i40e_vlan_stripping_disable(vsi); | |
2502 | } | |
2503 | ||
2504 | /** | |
2505 | * i40e_vsi_add_vlan - Add vsi membership for given vlan | |
2506 | * @vsi: the vsi being configured | |
2507 | * @vid: vlan id to be added (0 = untagged only , -1 = any) | |
2508 | **/ | |
2509 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid) | |
2510 | { | |
278e7d0b JK |
2511 | struct i40e_mac_filter *f, *add_f, *del_f; |
2512 | struct hlist_node *h; | |
2513 | int bkt; | |
41c445ff | 2514 | |
21659035 | 2515 | /* Locked once because all functions invoked below iterates list*/ |
278e7d0b | 2516 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2517 | |
278e7d0b | 2518 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
2519 | if (f->state == I40E_FILTER_REMOVE) |
2520 | continue; | |
1bc87e80 | 2521 | add_f = i40e_add_filter(vsi, f->macaddr, vid); |
41c445ff JB |
2522 | if (!add_f) { |
2523 | dev_info(&vsi->back->pdev->dev, | |
2524 | "Could not add vlan filter %d for %pM\n", | |
2525 | vid, f->macaddr); | |
278e7d0b | 2526 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
2527 | return -ENOMEM; |
2528 | } | |
2529 | } | |
2530 | ||
3c7cbd45 JK |
2531 | /* When we add a new VLAN filter, we need to make sure that all existing |
2532 | * filters which are marked as vid=-1 (I40E_VLAN_ANY) are converted to | |
2533 | * vid=0. The simplest way is just search for all filters marked as | |
2534 | * vid=-1 and replace them with vid=0. This converts all filters that | |
2535 | * were marked to receive all traffic (tagged or untagged) into | |
2536 | * filters to receive only untagged traffic, so that we don't receive | |
2537 | * tagged traffic for VLANs which we have not configured. | |
41c445ff | 2538 | */ |
8d82a7c5 | 2539 | if (vid > 0 && !vsi->info.pvid) { |
278e7d0b | 2540 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
2541 | if (f->state == I40E_FILTER_REMOVE) |
2542 | continue; | |
290d2557 JK |
2543 | del_f = i40e_find_filter(vsi, f->macaddr, |
2544 | I40E_VLAN_ANY); | |
2545 | if (!del_f) | |
21659035 | 2546 | continue; |
290d2557 | 2547 | __i40e_del_filter(vsi, del_f); |
1bc87e80 | 2548 | add_f = i40e_add_filter(vsi, f->macaddr, 0); |
21659035 KP |
2549 | if (!add_f) { |
2550 | dev_info(&vsi->back->pdev->dev, | |
2551 | "Could not add filter 0 for %pM\n", | |
2552 | f->macaddr); | |
278e7d0b | 2553 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2554 | return -ENOMEM; |
41c445ff JB |
2555 | } |
2556 | } | |
41c445ff JB |
2557 | } |
2558 | ||
278e7d0b | 2559 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2560 | |
0e4425ed JB |
2561 | /* schedule our worker thread which will take care of |
2562 | * applying the new filter changes | |
2563 | */ | |
2564 | i40e_service_event_schedule(vsi->back); | |
2565 | return 0; | |
41c445ff JB |
2566 | } |
2567 | ||
2568 | /** | |
2569 | * i40e_vsi_kill_vlan - Remove vsi membership for given vlan | |
2570 | * @vsi: the vsi being configured | |
2571 | * @vid: vlan id to be removed (0 = untagged only , -1 = any) | |
2572 | **/ | |
3aa7b74d | 2573 | void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2574 | { |
84f5ca6c | 2575 | struct i40e_mac_filter *f; |
278e7d0b | 2576 | struct hlist_node *h; |
278e7d0b | 2577 | int bkt; |
41c445ff | 2578 | |
21659035 | 2579 | /* Locked once because all functions invoked below iterates list */ |
278e7d0b | 2580 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2581 | |
278e7d0b | 2582 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
290d2557 JK |
2583 | if (f->vlan == vid) |
2584 | __i40e_del_filter(vsi, f); | |
2585 | } | |
41c445ff | 2586 | |
278e7d0b | 2587 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2588 | |
0e4425ed JB |
2589 | /* schedule our worker thread which will take care of |
2590 | * applying the new filter changes | |
2591 | */ | |
2592 | i40e_service_event_schedule(vsi->back); | |
41c445ff JB |
2593 | } |
2594 | ||
2595 | /** | |
2596 | * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload | |
2597 | * @netdev: network interface to be adjusted | |
2598 | * @vid: vlan id to be added | |
078b5876 JB |
2599 | * |
2600 | * net_device_ops implementation for adding vlan ids | |
41c445ff | 2601 | **/ |
38e00438 VD |
2602 | #ifdef I40E_FCOE |
2603 | int i40e_vlan_rx_add_vid(struct net_device *netdev, | |
2604 | __always_unused __be16 proto, u16 vid) | |
2605 | #else | |
41c445ff JB |
2606 | static int i40e_vlan_rx_add_vid(struct net_device *netdev, |
2607 | __always_unused __be16 proto, u16 vid) | |
38e00438 | 2608 | #endif |
41c445ff JB |
2609 | { |
2610 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2611 | struct i40e_vsi *vsi = np->vsi; | |
078b5876 | 2612 | int ret = 0; |
41c445ff | 2613 | |
6a112785 | 2614 | if (vid >= VLAN_N_VID) |
078b5876 JB |
2615 | return -EINVAL; |
2616 | ||
6982d429 ASJ |
2617 | /* If the network stack called us with vid = 0 then |
2618 | * it is asking to receive priority tagged packets with | |
2619 | * vlan id 0. Our HW receives them by default when configured | |
2620 | * to receive untagged packets so there is no need to add an | |
2621 | * extra filter for vlan 0 tagged packets. | |
41c445ff | 2622 | */ |
6982d429 ASJ |
2623 | if (vid) |
2624 | ret = i40e_vsi_add_vlan(vsi, vid); | |
41c445ff | 2625 | |
6a112785 | 2626 | if (!ret) |
078b5876 | 2627 | set_bit(vid, vsi->active_vlans); |
41c445ff | 2628 | |
078b5876 | 2629 | return ret; |
41c445ff JB |
2630 | } |
2631 | ||
2632 | /** | |
2633 | * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload | |
2634 | * @netdev: network interface to be adjusted | |
2635 | * @vid: vlan id to be removed | |
078b5876 | 2636 | * |
fdfd943e | 2637 | * net_device_ops implementation for removing vlan ids |
41c445ff | 2638 | **/ |
38e00438 VD |
2639 | #ifdef I40E_FCOE |
2640 | int i40e_vlan_rx_kill_vid(struct net_device *netdev, | |
2641 | __always_unused __be16 proto, u16 vid) | |
2642 | #else | |
41c445ff JB |
2643 | static int i40e_vlan_rx_kill_vid(struct net_device *netdev, |
2644 | __always_unused __be16 proto, u16 vid) | |
38e00438 | 2645 | #endif |
41c445ff JB |
2646 | { |
2647 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2648 | struct i40e_vsi *vsi = np->vsi; | |
2649 | ||
41c445ff JB |
2650 | /* return code is ignored as there is nothing a user |
2651 | * can do about failure to remove and a log message was | |
078b5876 | 2652 | * already printed from the other function |
41c445ff JB |
2653 | */ |
2654 | i40e_vsi_kill_vlan(vsi, vid); | |
2655 | ||
2656 | clear_bit(vid, vsi->active_vlans); | |
078b5876 | 2657 | |
41c445ff JB |
2658 | return 0; |
2659 | } | |
2660 | ||
b1b15df5 TD |
2661 | /** |
2662 | * i40e_macaddr_init - explicitly write the mac address filters | |
2663 | * | |
2664 | * @vsi: pointer to the vsi | |
2665 | * @macaddr: the MAC address | |
2666 | * | |
2667 | * This is needed when the macaddr has been obtained by other | |
2668 | * means than the default, e.g., from Open Firmware or IDPROM. | |
2669 | * Returns 0 on success, negative on failure | |
2670 | **/ | |
2671 | static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr) | |
2672 | { | |
2673 | int ret; | |
2674 | struct i40e_aqc_add_macvlan_element_data element; | |
2675 | ||
2676 | ret = i40e_aq_mac_address_write(&vsi->back->hw, | |
2677 | I40E_AQC_WRITE_TYPE_LAA_WOL, | |
2678 | macaddr, NULL); | |
2679 | if (ret) { | |
2680 | dev_info(&vsi->back->pdev->dev, | |
2681 | "Addr change for VSI failed: %d\n", ret); | |
2682 | return -EADDRNOTAVAIL; | |
2683 | } | |
2684 | ||
2685 | memset(&element, 0, sizeof(element)); | |
2686 | ether_addr_copy(element.mac_addr, macaddr); | |
2687 | element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH); | |
2688 | ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL); | |
2689 | if (ret) { | |
2690 | dev_info(&vsi->back->pdev->dev, | |
2691 | "add filter failed err %s aq_err %s\n", | |
2692 | i40e_stat_str(&vsi->back->hw, ret), | |
2693 | i40e_aq_str(&vsi->back->hw, | |
2694 | vsi->back->hw.aq.asq_last_status)); | |
2695 | } | |
2696 | return ret; | |
2697 | } | |
2698 | ||
41c445ff JB |
2699 | /** |
2700 | * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up | |
2701 | * @vsi: the vsi being brought back up | |
2702 | **/ | |
2703 | static void i40e_restore_vlan(struct i40e_vsi *vsi) | |
2704 | { | |
2705 | u16 vid; | |
2706 | ||
2707 | if (!vsi->netdev) | |
2708 | return; | |
2709 | ||
2710 | i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features); | |
2711 | ||
2712 | for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID) | |
2713 | i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q), | |
2714 | vid); | |
2715 | } | |
2716 | ||
2717 | /** | |
2718 | * i40e_vsi_add_pvid - Add pvid for the VSI | |
2719 | * @vsi: the vsi being adjusted | |
2720 | * @vid: the vlan id to set as a PVID | |
2721 | **/ | |
dcae29be | 2722 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) |
41c445ff JB |
2723 | { |
2724 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 2725 | i40e_status ret; |
41c445ff JB |
2726 | |
2727 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2728 | vsi->info.pvid = cpu_to_le16(vid); | |
6c12fcbf GR |
2729 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED | |
2730 | I40E_AQ_VSI_PVLAN_INSERT_PVID | | |
b774c7dd | 2731 | I40E_AQ_VSI_PVLAN_EMOD_STR; |
41c445ff JB |
2732 | |
2733 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2734 | ctxt.info = vsi->info; |
f1c7e72e SN |
2735 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2736 | if (ret) { | |
41c445ff | 2737 | dev_info(&vsi->back->pdev->dev, |
f1c7e72e SN |
2738 | "add pvid failed, err %s aq_err %s\n", |
2739 | i40e_stat_str(&vsi->back->hw, ret), | |
2740 | i40e_aq_str(&vsi->back->hw, | |
2741 | vsi->back->hw.aq.asq_last_status)); | |
dcae29be | 2742 | return -ENOENT; |
41c445ff JB |
2743 | } |
2744 | ||
dcae29be | 2745 | return 0; |
41c445ff JB |
2746 | } |
2747 | ||
2748 | /** | |
2749 | * i40e_vsi_remove_pvid - Remove the pvid from the VSI | |
2750 | * @vsi: the vsi being adjusted | |
2751 | * | |
2752 | * Just use the vlan_rx_register() service to put it back to normal | |
2753 | **/ | |
2754 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi) | |
2755 | { | |
6c12fcbf GR |
2756 | i40e_vlan_stripping_disable(vsi); |
2757 | ||
41c445ff | 2758 | vsi->info.pvid = 0; |
41c445ff JB |
2759 | } |
2760 | ||
2761 | /** | |
2762 | * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources | |
2763 | * @vsi: ptr to the VSI | |
2764 | * | |
2765 | * If this function returns with an error, then it's possible one or | |
2766 | * more of the rings is populated (while the rest are not). It is the | |
2767 | * callers duty to clean those orphaned rings. | |
2768 | * | |
2769 | * Return 0 on success, negative on failure | |
2770 | **/ | |
2771 | static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi) | |
2772 | { | |
2773 | int i, err = 0; | |
2774 | ||
2775 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2776 | err = i40e_setup_tx_descriptors(vsi->tx_rings[i]); |
41c445ff JB |
2777 | |
2778 | return err; | |
2779 | } | |
2780 | ||
2781 | /** | |
2782 | * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues | |
2783 | * @vsi: ptr to the VSI | |
2784 | * | |
2785 | * Free VSI's transmit software resources | |
2786 | **/ | |
2787 | static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi) | |
2788 | { | |
2789 | int i; | |
2790 | ||
8e9dca53 GR |
2791 | if (!vsi->tx_rings) |
2792 | return; | |
2793 | ||
41c445ff | 2794 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 2795 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) |
9f65e15b | 2796 | i40e_free_tx_resources(vsi->tx_rings[i]); |
41c445ff JB |
2797 | } |
2798 | ||
2799 | /** | |
2800 | * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources | |
2801 | * @vsi: ptr to the VSI | |
2802 | * | |
2803 | * If this function returns with an error, then it's possible one or | |
2804 | * more of the rings is populated (while the rest are not). It is the | |
2805 | * callers duty to clean those orphaned rings. | |
2806 | * | |
2807 | * Return 0 on success, negative on failure | |
2808 | **/ | |
2809 | static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi) | |
2810 | { | |
2811 | int i, err = 0; | |
2812 | ||
2813 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2814 | err = i40e_setup_rx_descriptors(vsi->rx_rings[i]); |
38e00438 VD |
2815 | #ifdef I40E_FCOE |
2816 | i40e_fcoe_setup_ddp_resources(vsi); | |
2817 | #endif | |
41c445ff JB |
2818 | return err; |
2819 | } | |
2820 | ||
2821 | /** | |
2822 | * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues | |
2823 | * @vsi: ptr to the VSI | |
2824 | * | |
2825 | * Free all receive software resources | |
2826 | **/ | |
2827 | static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) | |
2828 | { | |
2829 | int i; | |
2830 | ||
8e9dca53 GR |
2831 | if (!vsi->rx_rings) |
2832 | return; | |
2833 | ||
41c445ff | 2834 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 2835 | if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc) |
9f65e15b | 2836 | i40e_free_rx_resources(vsi->rx_rings[i]); |
38e00438 VD |
2837 | #ifdef I40E_FCOE |
2838 | i40e_fcoe_free_ddp_resources(vsi); | |
2839 | #endif | |
41c445ff JB |
2840 | } |
2841 | ||
3ffa037d NP |
2842 | /** |
2843 | * i40e_config_xps_tx_ring - Configure XPS for a Tx ring | |
2844 | * @ring: The Tx ring to configure | |
2845 | * | |
2846 | * This enables/disables XPS for a given Tx descriptor ring | |
2847 | * based on the TCs enabled for the VSI that ring belongs to. | |
2848 | **/ | |
2849 | static void i40e_config_xps_tx_ring(struct i40e_ring *ring) | |
2850 | { | |
2851 | struct i40e_vsi *vsi = ring->vsi; | |
2852 | cpumask_var_t mask; | |
2853 | ||
9a660eea JB |
2854 | if (!ring->q_vector || !ring->netdev) |
2855 | return; | |
2856 | ||
2857 | /* Single TC mode enable XPS */ | |
2858 | if (vsi->tc_config.numtc <= 1) { | |
2859 | if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state)) | |
3ffa037d NP |
2860 | netif_set_xps_queue(ring->netdev, |
2861 | &ring->q_vector->affinity_mask, | |
2862 | ring->queue_index); | |
9a660eea JB |
2863 | } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) { |
2864 | /* Disable XPS to allow selection based on TC */ | |
2865 | bitmap_zero(cpumask_bits(mask), nr_cpumask_bits); | |
2866 | netif_set_xps_queue(ring->netdev, mask, ring->queue_index); | |
2867 | free_cpumask_var(mask); | |
3ffa037d | 2868 | } |
0e4425ed JB |
2869 | |
2870 | /* schedule our worker thread which will take care of | |
2871 | * applying the new filter changes | |
2872 | */ | |
2873 | i40e_service_event_schedule(vsi->back); | |
3ffa037d NP |
2874 | } |
2875 | ||
41c445ff JB |
2876 | /** |
2877 | * i40e_configure_tx_ring - Configure a transmit ring context and rest | |
2878 | * @ring: The Tx ring to configure | |
2879 | * | |
2880 | * Configure the Tx descriptor ring in the HMC context. | |
2881 | **/ | |
2882 | static int i40e_configure_tx_ring(struct i40e_ring *ring) | |
2883 | { | |
2884 | struct i40e_vsi *vsi = ring->vsi; | |
2885 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
2886 | struct i40e_hw *hw = &vsi->back->hw; | |
2887 | struct i40e_hmc_obj_txq tx_ctx; | |
2888 | i40e_status err = 0; | |
2889 | u32 qtx_ctl = 0; | |
2890 | ||
2891 | /* some ATR related tx ring init */ | |
60ea5f83 | 2892 | if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) { |
41c445ff JB |
2893 | ring->atr_sample_rate = vsi->back->atr_sample_rate; |
2894 | ring->atr_count = 0; | |
2895 | } else { | |
2896 | ring->atr_sample_rate = 0; | |
2897 | } | |
2898 | ||
3ffa037d NP |
2899 | /* configure XPS */ |
2900 | i40e_config_xps_tx_ring(ring); | |
41c445ff JB |
2901 | |
2902 | /* clear the context structure first */ | |
2903 | memset(&tx_ctx, 0, sizeof(tx_ctx)); | |
2904 | ||
2905 | tx_ctx.new_context = 1; | |
2906 | tx_ctx.base = (ring->dma / 128); | |
2907 | tx_ctx.qlen = ring->count; | |
60ea5f83 JB |
2908 | tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED | |
2909 | I40E_FLAG_FD_ATR_ENABLED)); | |
38e00438 VD |
2910 | #ifdef I40E_FCOE |
2911 | tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE); | |
2912 | #endif | |
beb0dff1 | 2913 | tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP); |
1943d8ba JB |
2914 | /* FDIR VSI tx ring can still use RS bit and writebacks */ |
2915 | if (vsi->type != I40E_VSI_FDIR) | |
2916 | tx_ctx.head_wb_ena = 1; | |
2917 | tx_ctx.head_wb_addr = ring->dma + | |
2918 | (ring->count * sizeof(struct i40e_tx_desc)); | |
41c445ff JB |
2919 | |
2920 | /* As part of VSI creation/update, FW allocates certain | |
2921 | * Tx arbitration queue sets for each TC enabled for | |
2922 | * the VSI. The FW returns the handles to these queue | |
2923 | * sets as part of the response buffer to Add VSI, | |
2924 | * Update VSI, etc. AQ commands. It is expected that | |
2925 | * these queue set handles be associated with the Tx | |
2926 | * queues by the driver as part of the TX queue context | |
2927 | * initialization. This has to be done regardless of | |
2928 | * DCB as by default everything is mapped to TC0. | |
2929 | */ | |
2930 | tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]); | |
2931 | tx_ctx.rdylist_act = 0; | |
2932 | ||
2933 | /* clear the context in the HMC */ | |
2934 | err = i40e_clear_lan_tx_queue_context(hw, pf_q); | |
2935 | if (err) { | |
2936 | dev_info(&vsi->back->pdev->dev, | |
2937 | "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n", | |
2938 | ring->queue_index, pf_q, err); | |
2939 | return -ENOMEM; | |
2940 | } | |
2941 | ||
2942 | /* set the context in the HMC */ | |
2943 | err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); | |
2944 | if (err) { | |
2945 | dev_info(&vsi->back->pdev->dev, | |
2946 | "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n", | |
2947 | ring->queue_index, pf_q, err); | |
2948 | return -ENOMEM; | |
2949 | } | |
2950 | ||
2951 | /* Now associate this queue with this PCI function */ | |
7a28d885 | 2952 | if (vsi->type == I40E_VSI_VMDQ2) { |
9d8bf547 | 2953 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; |
7a28d885 MW |
2954 | qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & |
2955 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
2956 | } else { | |
9d8bf547 | 2957 | qtx_ctl = I40E_QTX_CTL_PF_QUEUE; |
7a28d885 MW |
2958 | } |
2959 | ||
13fd9774 SN |
2960 | qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & |
2961 | I40E_QTX_CTL_PF_INDX_MASK); | |
41c445ff JB |
2962 | wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); |
2963 | i40e_flush(hw); | |
2964 | ||
41c445ff JB |
2965 | /* cache tail off for easier writes later */ |
2966 | ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); | |
2967 | ||
2968 | return 0; | |
2969 | } | |
2970 | ||
2971 | /** | |
2972 | * i40e_configure_rx_ring - Configure a receive ring context | |
2973 | * @ring: The Rx ring to configure | |
2974 | * | |
2975 | * Configure the Rx descriptor ring in the HMC context. | |
2976 | **/ | |
2977 | static int i40e_configure_rx_ring(struct i40e_ring *ring) | |
2978 | { | |
2979 | struct i40e_vsi *vsi = ring->vsi; | |
2980 | u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len; | |
2981 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
2982 | struct i40e_hw *hw = &vsi->back->hw; | |
2983 | struct i40e_hmc_obj_rxq rx_ctx; | |
2984 | i40e_status err = 0; | |
2985 | ||
2986 | ring->state = 0; | |
2987 | ||
2988 | /* clear the context structure first */ | |
2989 | memset(&rx_ctx, 0, sizeof(rx_ctx)); | |
2990 | ||
2991 | ring->rx_buf_len = vsi->rx_buf_len; | |
41c445ff JB |
2992 | |
2993 | rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT; | |
41c445ff JB |
2994 | |
2995 | rx_ctx.base = (ring->dma / 128); | |
2996 | rx_ctx.qlen = ring->count; | |
2997 | ||
bec60fc4 JB |
2998 | /* use 32 byte descriptors */ |
2999 | rx_ctx.dsize = 1; | |
41c445ff | 3000 | |
bec60fc4 JB |
3001 | /* descriptor type is always zero |
3002 | * rx_ctx.dtype = 0; | |
3003 | */ | |
b32bfa17 | 3004 | rx_ctx.hsplit_0 = 0; |
41c445ff | 3005 | |
b32bfa17 | 3006 | rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len); |
7134f9ce JB |
3007 | if (hw->revision_id == 0) |
3008 | rx_ctx.lrxqthresh = 0; | |
3009 | else | |
3010 | rx_ctx.lrxqthresh = 2; | |
41c445ff JB |
3011 | rx_ctx.crcstrip = 1; |
3012 | rx_ctx.l2tsel = 1; | |
c4bbac39 JB |
3013 | /* this controls whether VLAN is stripped from inner headers */ |
3014 | rx_ctx.showiv = 0; | |
38e00438 VD |
3015 | #ifdef I40E_FCOE |
3016 | rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE); | |
3017 | #endif | |
acb3676b CS |
3018 | /* set the prefena field to 1 because the manual says to */ |
3019 | rx_ctx.prefena = 1; | |
41c445ff JB |
3020 | |
3021 | /* clear the context in the HMC */ | |
3022 | err = i40e_clear_lan_rx_queue_context(hw, pf_q); | |
3023 | if (err) { | |
3024 | dev_info(&vsi->back->pdev->dev, | |
3025 | "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3026 | ring->queue_index, pf_q, err); | |
3027 | return -ENOMEM; | |
3028 | } | |
3029 | ||
3030 | /* set the context in the HMC */ | |
3031 | err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx); | |
3032 | if (err) { | |
3033 | dev_info(&vsi->back->pdev->dev, | |
3034 | "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3035 | ring->queue_index, pf_q, err); | |
3036 | return -ENOMEM; | |
3037 | } | |
3038 | ||
3039 | /* cache tail for quicker writes, and clear the reg before use */ | |
3040 | ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q); | |
3041 | writel(0, ring->tail); | |
3042 | ||
1a557afc | 3043 | i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring)); |
41c445ff JB |
3044 | |
3045 | return 0; | |
3046 | } | |
3047 | ||
3048 | /** | |
3049 | * i40e_vsi_configure_tx - Configure the VSI for Tx | |
3050 | * @vsi: VSI structure describing this set of rings and resources | |
3051 | * | |
3052 | * Configure the Tx VSI for operation. | |
3053 | **/ | |
3054 | static int i40e_vsi_configure_tx(struct i40e_vsi *vsi) | |
3055 | { | |
3056 | int err = 0; | |
3057 | u16 i; | |
3058 | ||
9f65e15b AD |
3059 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) |
3060 | err = i40e_configure_tx_ring(vsi->tx_rings[i]); | |
41c445ff JB |
3061 | |
3062 | return err; | |
3063 | } | |
3064 | ||
3065 | /** | |
3066 | * i40e_vsi_configure_rx - Configure the VSI for Rx | |
3067 | * @vsi: the VSI being configured | |
3068 | * | |
3069 | * Configure the Rx VSI for operation. | |
3070 | **/ | |
3071 | static int i40e_vsi_configure_rx(struct i40e_vsi *vsi) | |
3072 | { | |
3073 | int err = 0; | |
3074 | u16 i; | |
3075 | ||
3076 | if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN)) | |
3077 | vsi->max_frame = vsi->netdev->mtu + ETH_HLEN | |
3078 | + ETH_FCS_LEN + VLAN_HLEN; | |
3079 | else | |
3080 | vsi->max_frame = I40E_RXBUFFER_2048; | |
3081 | ||
1a557afc | 3082 | vsi->rx_buf_len = I40E_RXBUFFER_2048; |
41c445ff | 3083 | |
38e00438 VD |
3084 | #ifdef I40E_FCOE |
3085 | /* setup rx buffer for FCoE */ | |
3086 | if ((vsi->type == I40E_VSI_FCOE) && | |
3087 | (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) { | |
38e00438 VD |
3088 | vsi->rx_buf_len = I40E_RXBUFFER_3072; |
3089 | vsi->max_frame = I40E_RXBUFFER_3072; | |
38e00438 VD |
3090 | } |
3091 | ||
3092 | #endif /* I40E_FCOE */ | |
41c445ff | 3093 | /* round up for the chip's needs */ |
41c445ff | 3094 | vsi->rx_buf_len = ALIGN(vsi->rx_buf_len, |
41a1d04b | 3095 | BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); |
41c445ff JB |
3096 | |
3097 | /* set up individual rings */ | |
3098 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3099 | err = i40e_configure_rx_ring(vsi->rx_rings[i]); |
41c445ff JB |
3100 | |
3101 | return err; | |
3102 | } | |
3103 | ||
3104 | /** | |
3105 | * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC | |
3106 | * @vsi: ptr to the VSI | |
3107 | **/ | |
3108 | static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi) | |
3109 | { | |
e7046ee1 | 3110 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff JB |
3111 | u16 qoffset, qcount; |
3112 | int i, n; | |
3113 | ||
cd238a3e PN |
3114 | if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
3115 | /* Reset the TC information */ | |
3116 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
3117 | rx_ring = vsi->rx_rings[i]; | |
3118 | tx_ring = vsi->tx_rings[i]; | |
3119 | rx_ring->dcb_tc = 0; | |
3120 | tx_ring->dcb_tc = 0; | |
3121 | } | |
3122 | } | |
41c445ff JB |
3123 | |
3124 | for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) { | |
41a1d04b | 3125 | if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) |
41c445ff JB |
3126 | continue; |
3127 | ||
3128 | qoffset = vsi->tc_config.tc_info[n].qoffset; | |
3129 | qcount = vsi->tc_config.tc_info[n].qcount; | |
3130 | for (i = qoffset; i < (qoffset + qcount); i++) { | |
e7046ee1 AA |
3131 | rx_ring = vsi->rx_rings[i]; |
3132 | tx_ring = vsi->tx_rings[i]; | |
41c445ff JB |
3133 | rx_ring->dcb_tc = n; |
3134 | tx_ring->dcb_tc = n; | |
3135 | } | |
3136 | } | |
3137 | } | |
3138 | ||
3139 | /** | |
3140 | * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI | |
3141 | * @vsi: ptr to the VSI | |
3142 | **/ | |
3143 | static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi) | |
3144 | { | |
b1b15df5 TD |
3145 | struct i40e_pf *pf = vsi->back; |
3146 | int err; | |
3147 | ||
41c445ff JB |
3148 | if (vsi->netdev) |
3149 | i40e_set_rx_mode(vsi->netdev); | |
b1b15df5 TD |
3150 | |
3151 | if (!!(pf->flags & I40E_FLAG_PF_MAC)) { | |
3152 | err = i40e_macaddr_init(vsi, pf->hw.mac.addr); | |
3153 | if (err) { | |
3154 | dev_warn(&pf->pdev->dev, | |
3155 | "could not set up macaddr; err %d\n", err); | |
3156 | } | |
3157 | } | |
41c445ff JB |
3158 | } |
3159 | ||
17a73f6b JG |
3160 | /** |
3161 | * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters | |
3162 | * @vsi: Pointer to the targeted VSI | |
3163 | * | |
3164 | * This function replays the hlist on the hw where all the SB Flow Director | |
3165 | * filters were saved. | |
3166 | **/ | |
3167 | static void i40e_fdir_filter_restore(struct i40e_vsi *vsi) | |
3168 | { | |
3169 | struct i40e_fdir_filter *filter; | |
3170 | struct i40e_pf *pf = vsi->back; | |
3171 | struct hlist_node *node; | |
3172 | ||
55a5e60b ASJ |
3173 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
3174 | return; | |
3175 | ||
17a73f6b JG |
3176 | hlist_for_each_entry_safe(filter, node, |
3177 | &pf->fdir_filter_list, fdir_node) { | |
3178 | i40e_add_del_fdir(vsi, filter, true); | |
3179 | } | |
3180 | } | |
3181 | ||
41c445ff JB |
3182 | /** |
3183 | * i40e_vsi_configure - Set up the VSI for action | |
3184 | * @vsi: the VSI being configured | |
3185 | **/ | |
3186 | static int i40e_vsi_configure(struct i40e_vsi *vsi) | |
3187 | { | |
3188 | int err; | |
3189 | ||
3190 | i40e_set_vsi_rx_mode(vsi); | |
3191 | i40e_restore_vlan(vsi); | |
3192 | i40e_vsi_config_dcb_rings(vsi); | |
3193 | err = i40e_vsi_configure_tx(vsi); | |
3194 | if (!err) | |
3195 | err = i40e_vsi_configure_rx(vsi); | |
3196 | ||
3197 | return err; | |
3198 | } | |
3199 | ||
3200 | /** | |
3201 | * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW | |
3202 | * @vsi: the VSI being configured | |
3203 | **/ | |
3204 | static void i40e_vsi_configure_msix(struct i40e_vsi *vsi) | |
3205 | { | |
3206 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
3207 | struct i40e_hw *hw = &pf->hw; |
3208 | u16 vector; | |
3209 | int i, q; | |
41c445ff JB |
3210 | u32 qp; |
3211 | ||
3212 | /* The interrupt indexing is offset by 1 in the PFINT_ITRn | |
3213 | * and PFINT_LNKLSTn registers, e.g.: | |
3214 | * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts) | |
3215 | */ | |
3216 | qp = vsi->base_queue; | |
3217 | vector = vsi->base_vector; | |
493fb300 | 3218 | for (i = 0; i < vsi->num_q_vectors; i++, vector++) { |
ac26fc13 JB |
3219 | struct i40e_q_vector *q_vector = vsi->q_vectors[i]; |
3220 | ||
ee2319cf | 3221 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3222 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting); |
41c445ff JB |
3223 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3224 | wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), | |
3225 | q_vector->rx.itr); | |
a75e8005 | 3226 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting); |
41c445ff JB |
3227 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3228 | wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), | |
3229 | q_vector->tx.itr); | |
ac26fc13 JB |
3230 | wr32(hw, I40E_PFINT_RATEN(vector - 1), |
3231 | INTRL_USEC_TO_REG(vsi->int_rate_limit)); | |
41c445ff JB |
3232 | |
3233 | /* Linked list for the queuepairs assigned to this vector */ | |
3234 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); | |
3235 | for (q = 0; q < q_vector->num_ringpairs; q++) { | |
ac26fc13 JB |
3236 | u32 val; |
3237 | ||
41c445ff JB |
3238 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3239 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3240 | (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | |
3241 | (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)| | |
3242 | (I40E_QUEUE_TYPE_TX | |
3243 | << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | |
3244 | ||
3245 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
3246 | ||
3247 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3248 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3249 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3250 | ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)| | |
3251 | (I40E_QUEUE_TYPE_RX | |
3252 | << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3253 | ||
3254 | /* Terminate the linked list */ | |
3255 | if (q == (q_vector->num_ringpairs - 1)) | |
3256 | val |= (I40E_QUEUE_END_OF_LIST | |
3257 | << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3258 | ||
3259 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
3260 | qp++; | |
3261 | } | |
3262 | } | |
3263 | ||
3264 | i40e_flush(hw); | |
3265 | } | |
3266 | ||
3267 | /** | |
3268 | * i40e_enable_misc_int_causes - enable the non-queue interrupts | |
3269 | * @hw: ptr to the hardware info | |
3270 | **/ | |
ab437b5a | 3271 | static void i40e_enable_misc_int_causes(struct i40e_pf *pf) |
41c445ff | 3272 | { |
ab437b5a | 3273 | struct i40e_hw *hw = &pf->hw; |
41c445ff JB |
3274 | u32 val; |
3275 | ||
3276 | /* clear things first */ | |
3277 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ | |
3278 | rd32(hw, I40E_PFINT_ICR0); /* read to clear */ | |
3279 | ||
3280 | val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | | |
3281 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | | |
3282 | I40E_PFINT_ICR0_ENA_GRST_MASK | | |
3283 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | | |
3284 | I40E_PFINT_ICR0_ENA_GPIO_MASK | | |
41c445ff JB |
3285 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | |
3286 | I40E_PFINT_ICR0_ENA_VFLR_MASK | | |
3287 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3288 | ||
0d8e1439 ASJ |
3289 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
3290 | val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3291 | ||
ab437b5a JK |
3292 | if (pf->flags & I40E_FLAG_PTP) |
3293 | val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; | |
3294 | ||
41c445ff JB |
3295 | wr32(hw, I40E_PFINT_ICR0_ENA, val); |
3296 | ||
3297 | /* SW_ITR_IDX = 0, but don't change INTENA */ | |
84ed40e7 ASJ |
3298 | wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | |
3299 | I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | |
41c445ff JB |
3300 | |
3301 | /* OTHER_ITR_IDX = 0 */ | |
3302 | wr32(hw, I40E_PFINT_STAT_CTL0, 0); | |
3303 | } | |
3304 | ||
3305 | /** | |
3306 | * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW | |
3307 | * @vsi: the VSI being configured | |
3308 | **/ | |
3309 | static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi) | |
3310 | { | |
493fb300 | 3311 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; |
41c445ff JB |
3312 | struct i40e_pf *pf = vsi->back; |
3313 | struct i40e_hw *hw = &pf->hw; | |
3314 | u32 val; | |
3315 | ||
3316 | /* set the ITR configuration */ | |
ee2319cf | 3317 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3318 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting); |
41c445ff JB |
3319 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3320 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr); | |
a75e8005 | 3321 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting); |
41c445ff JB |
3322 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3323 | wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr); | |
3324 | ||
ab437b5a | 3325 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
3326 | |
3327 | /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ | |
3328 | wr32(hw, I40E_PFINT_LNKLST0, 0); | |
3329 | ||
f29eaa3d | 3330 | /* Associate the queue pair to the vector and enable the queue int */ |
41c445ff JB |
3331 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3332 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3333 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3334 | ||
3335 | wr32(hw, I40E_QINT_RQCTL(0), val); | |
3336 | ||
3337 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3338 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3339 | (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3340 | ||
3341 | wr32(hw, I40E_QINT_TQCTL(0), val); | |
3342 | i40e_flush(hw); | |
3343 | } | |
3344 | ||
2ef28cfb MW |
3345 | /** |
3346 | * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0 | |
3347 | * @pf: board private structure | |
3348 | **/ | |
3349 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) | |
3350 | { | |
3351 | struct i40e_hw *hw = &pf->hw; | |
3352 | ||
3353 | wr32(hw, I40E_PFINT_DYN_CTL0, | |
3354 | I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
3355 | i40e_flush(hw); | |
3356 | } | |
3357 | ||
41c445ff JB |
3358 | /** |
3359 | * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 | |
3360 | * @pf: board private structure | |
40d72a50 | 3361 | * @clearpba: true when all pending interrupt events should be cleared |
41c445ff | 3362 | **/ |
40d72a50 | 3363 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba) |
41c445ff JB |
3364 | { |
3365 | struct i40e_hw *hw = &pf->hw; | |
3366 | u32 val; | |
3367 | ||
3368 | val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
40d72a50 | 3369 | (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) | |
41c445ff JB |
3370 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); |
3371 | ||
3372 | wr32(hw, I40E_PFINT_DYN_CTL0, val); | |
3373 | i40e_flush(hw); | |
3374 | } | |
3375 | ||
41c445ff JB |
3376 | /** |
3377 | * i40e_msix_clean_rings - MSIX mode Interrupt Handler | |
3378 | * @irq: interrupt number | |
3379 | * @data: pointer to a q_vector | |
3380 | **/ | |
3381 | static irqreturn_t i40e_msix_clean_rings(int irq, void *data) | |
3382 | { | |
3383 | struct i40e_q_vector *q_vector = data; | |
3384 | ||
cd0b6fa6 | 3385 | if (!q_vector->tx.ring && !q_vector->rx.ring) |
41c445ff JB |
3386 | return IRQ_HANDLED; |
3387 | ||
5d3465a1 | 3388 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3389 | |
3390 | return IRQ_HANDLED; | |
3391 | } | |
3392 | ||
96db776a AB |
3393 | /** |
3394 | * i40e_irq_affinity_notify - Callback for affinity changes | |
3395 | * @notify: context as to what irq was changed | |
3396 | * @mask: the new affinity mask | |
3397 | * | |
3398 | * This is a callback function used by the irq_set_affinity_notifier function | |
3399 | * so that we may register to receive changes to the irq affinity masks. | |
3400 | **/ | |
3401 | static void i40e_irq_affinity_notify(struct irq_affinity_notify *notify, | |
3402 | const cpumask_t *mask) | |
3403 | { | |
3404 | struct i40e_q_vector *q_vector = | |
3405 | container_of(notify, struct i40e_q_vector, affinity_notify); | |
3406 | ||
3407 | q_vector->affinity_mask = *mask; | |
3408 | } | |
3409 | ||
3410 | /** | |
3411 | * i40e_irq_affinity_release - Callback for affinity notifier release | |
3412 | * @ref: internal core kernel usage | |
3413 | * | |
3414 | * This is a callback function used by the irq_set_affinity_notifier function | |
3415 | * to inform the current notification subscriber that they will no longer | |
3416 | * receive notifications. | |
3417 | **/ | |
3418 | static void i40e_irq_affinity_release(struct kref *ref) {} | |
3419 | ||
41c445ff JB |
3420 | /** |
3421 | * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts | |
3422 | * @vsi: the VSI being configured | |
3423 | * @basename: name for the vector | |
3424 | * | |
3425 | * Allocates MSI-X vectors and requests interrupts from the kernel. | |
3426 | **/ | |
3427 | static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename) | |
3428 | { | |
3429 | int q_vectors = vsi->num_q_vectors; | |
3430 | struct i40e_pf *pf = vsi->back; | |
3431 | int base = vsi->base_vector; | |
3432 | int rx_int_idx = 0; | |
3433 | int tx_int_idx = 0; | |
3434 | int vector, err; | |
96db776a | 3435 | int irq_num; |
41c445ff JB |
3436 | |
3437 | for (vector = 0; vector < q_vectors; vector++) { | |
493fb300 | 3438 | struct i40e_q_vector *q_vector = vsi->q_vectors[vector]; |
41c445ff | 3439 | |
96db776a AB |
3440 | irq_num = pf->msix_entries[base + vector].vector; |
3441 | ||
cd0b6fa6 | 3442 | if (q_vector->tx.ring && q_vector->rx.ring) { |
41c445ff JB |
3443 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3444 | "%s-%s-%d", basename, "TxRx", rx_int_idx++); | |
3445 | tx_int_idx++; | |
cd0b6fa6 | 3446 | } else if (q_vector->rx.ring) { |
41c445ff JB |
3447 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3448 | "%s-%s-%d", basename, "rx", rx_int_idx++); | |
cd0b6fa6 | 3449 | } else if (q_vector->tx.ring) { |
41c445ff JB |
3450 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3451 | "%s-%s-%d", basename, "tx", tx_int_idx++); | |
3452 | } else { | |
3453 | /* skip this unused q_vector */ | |
3454 | continue; | |
3455 | } | |
96db776a | 3456 | err = request_irq(irq_num, |
41c445ff JB |
3457 | vsi->irq_handler, |
3458 | 0, | |
3459 | q_vector->name, | |
3460 | q_vector); | |
3461 | if (err) { | |
3462 | dev_info(&pf->pdev->dev, | |
fb43201f | 3463 | "MSIX request_irq failed, error: %d\n", err); |
41c445ff JB |
3464 | goto free_queue_irqs; |
3465 | } | |
96db776a AB |
3466 | |
3467 | /* register for affinity change notifications */ | |
3468 | q_vector->affinity_notify.notify = i40e_irq_affinity_notify; | |
3469 | q_vector->affinity_notify.release = i40e_irq_affinity_release; | |
3470 | irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify); | |
41c445ff | 3471 | /* assign the mask for this irq */ |
96db776a | 3472 | irq_set_affinity_hint(irq_num, &q_vector->affinity_mask); |
41c445ff JB |
3473 | } |
3474 | ||
63741846 | 3475 | vsi->irqs_ready = true; |
41c445ff JB |
3476 | return 0; |
3477 | ||
3478 | free_queue_irqs: | |
3479 | while (vector) { | |
3480 | vector--; | |
96db776a AB |
3481 | irq_num = pf->msix_entries[base + vector].vector; |
3482 | irq_set_affinity_notifier(irq_num, NULL); | |
3483 | irq_set_affinity_hint(irq_num, NULL); | |
3484 | free_irq(irq_num, &vsi->q_vectors[vector]); | |
41c445ff JB |
3485 | } |
3486 | return err; | |
3487 | } | |
3488 | ||
3489 | /** | |
3490 | * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI | |
3491 | * @vsi: the VSI being un-configured | |
3492 | **/ | |
3493 | static void i40e_vsi_disable_irq(struct i40e_vsi *vsi) | |
3494 | { | |
3495 | struct i40e_pf *pf = vsi->back; | |
3496 | struct i40e_hw *hw = &pf->hw; | |
3497 | int base = vsi->base_vector; | |
3498 | int i; | |
3499 | ||
3500 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b AD |
3501 | wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0); |
3502 | wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0); | |
41c445ff JB |
3503 | } |
3504 | ||
3505 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3506 | for (i = vsi->base_vector; | |
3507 | i < (vsi->num_q_vectors + vsi->base_vector); i++) | |
3508 | wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0); | |
3509 | ||
3510 | i40e_flush(hw); | |
3511 | for (i = 0; i < vsi->num_q_vectors; i++) | |
3512 | synchronize_irq(pf->msix_entries[i + base].vector); | |
3513 | } else { | |
3514 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
3515 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
3516 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
3517 | i40e_flush(hw); | |
3518 | synchronize_irq(pf->pdev->irq); | |
3519 | } | |
3520 | } | |
3521 | ||
3522 | /** | |
3523 | * i40e_vsi_enable_irq - Enable IRQ for the given VSI | |
3524 | * @vsi: the VSI being configured | |
3525 | **/ | |
3526 | static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) | |
3527 | { | |
3528 | struct i40e_pf *pf = vsi->back; | |
3529 | int i; | |
3530 | ||
3531 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
7845548d | 3532 | for (i = 0; i < vsi->num_q_vectors; i++) |
41c445ff JB |
3533 | i40e_irq_dynamic_enable(vsi, i); |
3534 | } else { | |
40d72a50 | 3535 | i40e_irq_dynamic_enable_icr0(pf, true); |
41c445ff JB |
3536 | } |
3537 | ||
1022cb6c | 3538 | i40e_flush(&pf->hw); |
41c445ff JB |
3539 | return 0; |
3540 | } | |
3541 | ||
3542 | /** | |
3543 | * i40e_stop_misc_vector - Stop the vector that handles non-queue events | |
3544 | * @pf: board private structure | |
3545 | **/ | |
3546 | static void i40e_stop_misc_vector(struct i40e_pf *pf) | |
3547 | { | |
3548 | /* Disable ICR 0 */ | |
3549 | wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0); | |
3550 | i40e_flush(&pf->hw); | |
3551 | } | |
3552 | ||
3553 | /** | |
3554 | * i40e_intr - MSI/Legacy and non-queue interrupt handler | |
3555 | * @irq: interrupt number | |
3556 | * @data: pointer to a q_vector | |
3557 | * | |
3558 | * This is the handler used for all MSI/Legacy interrupts, and deals | |
3559 | * with both queue and non-queue interrupts. This is also used in | |
3560 | * MSIX mode to handle the non-queue interrupts. | |
3561 | **/ | |
3562 | static irqreturn_t i40e_intr(int irq, void *data) | |
3563 | { | |
3564 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
3565 | struct i40e_hw *hw = &pf->hw; | |
5e823066 | 3566 | irqreturn_t ret = IRQ_NONE; |
41c445ff JB |
3567 | u32 icr0, icr0_remaining; |
3568 | u32 val, ena_mask; | |
3569 | ||
3570 | icr0 = rd32(hw, I40E_PFINT_ICR0); | |
5e823066 | 3571 | ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); |
41c445ff | 3572 | |
116a57d4 SN |
3573 | /* if sharing a legacy IRQ, we might get called w/o an intr pending */ |
3574 | if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0) | |
5e823066 | 3575 | goto enable_intr; |
41c445ff | 3576 | |
cd92e72f SN |
3577 | /* if interrupt but no bits showing, must be SWINT */ |
3578 | if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) || | |
3579 | (icr0 & I40E_PFINT_ICR0_SWINT_MASK)) | |
3580 | pf->sw_int_count++; | |
3581 | ||
0d8e1439 ASJ |
3582 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && |
3583 | (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) { | |
3584 | ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3585 | icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
23bb6dc3 | 3586 | dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n"); |
0d8e1439 ASJ |
3587 | } |
3588 | ||
41c445ff JB |
3589 | /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */ |
3590 | if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) { | |
5d3465a1 AD |
3591 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
3592 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; | |
41c445ff | 3593 | |
a16ae2d5 ASJ |
3594 | /* We do not have a way to disarm Queue causes while leaving |
3595 | * interrupt enabled for all other causes, ideally | |
3596 | * interrupt should be disabled while we are in NAPI but | |
3597 | * this is not a performance path and napi_schedule() | |
3598 | * can deal with rescheduling. | |
3599 | */ | |
41c445ff | 3600 | if (!test_bit(__I40E_DOWN, &pf->state)) |
5d3465a1 | 3601 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3602 | } |
3603 | ||
3604 | if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { | |
3605 | ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3606 | set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); | |
6e93d0c9 | 3607 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n"); |
41c445ff JB |
3608 | } |
3609 | ||
3610 | if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { | |
3611 | ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
3612 | set_bit(__I40E_MDD_EVENT_PENDING, &pf->state); | |
3613 | } | |
3614 | ||
3615 | if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { | |
3616 | ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; | |
3617 | set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state); | |
3618 | } | |
3619 | ||
3620 | if (icr0 & I40E_PFINT_ICR0_GRST_MASK) { | |
3621 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) | |
3622 | set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state); | |
3623 | ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; | |
3624 | val = rd32(hw, I40E_GLGEN_RSTAT); | |
3625 | val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) | |
3626 | >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; | |
4eb3f768 | 3627 | if (val == I40E_RESET_CORER) { |
41c445ff | 3628 | pf->corer_count++; |
4eb3f768 | 3629 | } else if (val == I40E_RESET_GLOBR) { |
41c445ff | 3630 | pf->globr_count++; |
4eb3f768 | 3631 | } else if (val == I40E_RESET_EMPR) { |
41c445ff | 3632 | pf->empr_count++; |
9df42d1a | 3633 | set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state); |
4eb3f768 | 3634 | } |
41c445ff JB |
3635 | } |
3636 | ||
9c010ee0 ASJ |
3637 | if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) { |
3638 | icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK; | |
3639 | dev_info(&pf->pdev->dev, "HMC error interrupt\n"); | |
25fc0e65 ASJ |
3640 | dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n", |
3641 | rd32(hw, I40E_PFHMC_ERRORINFO), | |
3642 | rd32(hw, I40E_PFHMC_ERRORDATA)); | |
9c010ee0 ASJ |
3643 | } |
3644 | ||
beb0dff1 JK |
3645 | if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) { |
3646 | u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0); | |
3647 | ||
3648 | if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) { | |
cafa1fca | 3649 | icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; |
beb0dff1 | 3650 | i40e_ptp_tx_hwtstamp(pf); |
beb0dff1 | 3651 | } |
beb0dff1 JK |
3652 | } |
3653 | ||
41c445ff JB |
3654 | /* If a critical error is pending we have no choice but to reset the |
3655 | * device. | |
3656 | * Report and mask out any remaining unexpected interrupts. | |
3657 | */ | |
3658 | icr0_remaining = icr0 & ena_mask; | |
3659 | if (icr0_remaining) { | |
3660 | dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n", | |
3661 | icr0_remaining); | |
9c010ee0 | 3662 | if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) || |
41c445ff | 3663 | (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) || |
c0c28975 | 3664 | (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) { |
9c010ee0 ASJ |
3665 | dev_info(&pf->pdev->dev, "device will be reset\n"); |
3666 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
3667 | i40e_service_event_schedule(pf); | |
41c445ff JB |
3668 | } |
3669 | ena_mask &= ~icr0_remaining; | |
3670 | } | |
5e823066 | 3671 | ret = IRQ_HANDLED; |
41c445ff | 3672 | |
5e823066 | 3673 | enable_intr: |
41c445ff JB |
3674 | /* re-enable interrupt causes */ |
3675 | wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); | |
41c445ff JB |
3676 | if (!test_bit(__I40E_DOWN, &pf->state)) { |
3677 | i40e_service_event_schedule(pf); | |
40d72a50 | 3678 | i40e_irq_dynamic_enable_icr0(pf, false); |
41c445ff JB |
3679 | } |
3680 | ||
5e823066 | 3681 | return ret; |
41c445ff JB |
3682 | } |
3683 | ||
cbf61325 ASJ |
3684 | /** |
3685 | * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes | |
3686 | * @tx_ring: tx ring to clean | |
3687 | * @budget: how many cleans we're allowed | |
3688 | * | |
3689 | * Returns true if there's any budget left (e.g. the clean is finished) | |
3690 | **/ | |
3691 | static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget) | |
3692 | { | |
3693 | struct i40e_vsi *vsi = tx_ring->vsi; | |
3694 | u16 i = tx_ring->next_to_clean; | |
3695 | struct i40e_tx_buffer *tx_buf; | |
3696 | struct i40e_tx_desc *tx_desc; | |
3697 | ||
3698 | tx_buf = &tx_ring->tx_bi[i]; | |
3699 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
3700 | i -= tx_ring->count; | |
3701 | ||
3702 | do { | |
3703 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
3704 | ||
3705 | /* if next_to_watch is not set then there is no work pending */ | |
3706 | if (!eop_desc) | |
3707 | break; | |
3708 | ||
3709 | /* prevent any other reads prior to eop_desc */ | |
3710 | read_barrier_depends(); | |
3711 | ||
3712 | /* if the descriptor isn't done, no work yet to do */ | |
3713 | if (!(eop_desc->cmd_type_offset_bsz & | |
3714 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
3715 | break; | |
3716 | ||
3717 | /* clear next_to_watch to prevent false hangs */ | |
3718 | tx_buf->next_to_watch = NULL; | |
3719 | ||
49d7d933 ASJ |
3720 | tx_desc->buffer_addr = 0; |
3721 | tx_desc->cmd_type_offset_bsz = 0; | |
3722 | /* move past filter desc */ | |
3723 | tx_buf++; | |
3724 | tx_desc++; | |
3725 | i++; | |
3726 | if (unlikely(!i)) { | |
3727 | i -= tx_ring->count; | |
3728 | tx_buf = tx_ring->tx_bi; | |
3729 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3730 | } | |
cbf61325 ASJ |
3731 | /* unmap skb header data */ |
3732 | dma_unmap_single(tx_ring->dev, | |
3733 | dma_unmap_addr(tx_buf, dma), | |
3734 | dma_unmap_len(tx_buf, len), | |
3735 | DMA_TO_DEVICE); | |
49d7d933 ASJ |
3736 | if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB) |
3737 | kfree(tx_buf->raw_buf); | |
cbf61325 | 3738 | |
49d7d933 ASJ |
3739 | tx_buf->raw_buf = NULL; |
3740 | tx_buf->tx_flags = 0; | |
3741 | tx_buf->next_to_watch = NULL; | |
cbf61325 | 3742 | dma_unmap_len_set(tx_buf, len, 0); |
49d7d933 ASJ |
3743 | tx_desc->buffer_addr = 0; |
3744 | tx_desc->cmd_type_offset_bsz = 0; | |
cbf61325 | 3745 | |
49d7d933 | 3746 | /* move us past the eop_desc for start of next FD desc */ |
cbf61325 ASJ |
3747 | tx_buf++; |
3748 | tx_desc++; | |
3749 | i++; | |
3750 | if (unlikely(!i)) { | |
3751 | i -= tx_ring->count; | |
3752 | tx_buf = tx_ring->tx_bi; | |
3753 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3754 | } | |
3755 | ||
3756 | /* update budget accounting */ | |
3757 | budget--; | |
3758 | } while (likely(budget)); | |
3759 | ||
3760 | i += tx_ring->count; | |
3761 | tx_ring->next_to_clean = i; | |
3762 | ||
6995b36c | 3763 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) |
7845548d | 3764 | i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx); |
6995b36c | 3765 | |
cbf61325 ASJ |
3766 | return budget > 0; |
3767 | } | |
3768 | ||
3769 | /** | |
3770 | * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring | |
3771 | * @irq: interrupt number | |
3772 | * @data: pointer to a q_vector | |
3773 | **/ | |
3774 | static irqreturn_t i40e_fdir_clean_ring(int irq, void *data) | |
3775 | { | |
3776 | struct i40e_q_vector *q_vector = data; | |
3777 | struct i40e_vsi *vsi; | |
3778 | ||
3779 | if (!q_vector->tx.ring) | |
3780 | return IRQ_HANDLED; | |
3781 | ||
3782 | vsi = q_vector->tx.ring->vsi; | |
3783 | i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit); | |
3784 | ||
3785 | return IRQ_HANDLED; | |
3786 | } | |
3787 | ||
41c445ff | 3788 | /** |
cd0b6fa6 | 3789 | * i40e_map_vector_to_qp - Assigns the queue pair to the vector |
41c445ff JB |
3790 | * @vsi: the VSI being configured |
3791 | * @v_idx: vector index | |
cd0b6fa6 | 3792 | * @qp_idx: queue pair index |
41c445ff | 3793 | **/ |
26cdc443 | 3794 | static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx) |
41c445ff | 3795 | { |
493fb300 | 3796 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; |
9f65e15b AD |
3797 | struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx]; |
3798 | struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx]; | |
41c445ff JB |
3799 | |
3800 | tx_ring->q_vector = q_vector; | |
cd0b6fa6 AD |
3801 | tx_ring->next = q_vector->tx.ring; |
3802 | q_vector->tx.ring = tx_ring; | |
41c445ff | 3803 | q_vector->tx.count++; |
cd0b6fa6 AD |
3804 | |
3805 | rx_ring->q_vector = q_vector; | |
3806 | rx_ring->next = q_vector->rx.ring; | |
3807 | q_vector->rx.ring = rx_ring; | |
3808 | q_vector->rx.count++; | |
41c445ff JB |
3809 | } |
3810 | ||
3811 | /** | |
3812 | * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors | |
3813 | * @vsi: the VSI being configured | |
3814 | * | |
3815 | * This function maps descriptor rings to the queue-specific vectors | |
3816 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
3817 | * one vector per queue pair, but on a constrained vector budget, we | |
3818 | * group the queue pairs as "efficiently" as possible. | |
3819 | **/ | |
3820 | static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi) | |
3821 | { | |
3822 | int qp_remaining = vsi->num_queue_pairs; | |
3823 | int q_vectors = vsi->num_q_vectors; | |
cd0b6fa6 | 3824 | int num_ringpairs; |
41c445ff JB |
3825 | int v_start = 0; |
3826 | int qp_idx = 0; | |
3827 | ||
3828 | /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to | |
3829 | * group them so there are multiple queues per vector. | |
70114ec4 ASJ |
3830 | * It is also important to go through all the vectors available to be |
3831 | * sure that if we don't use all the vectors, that the remaining vectors | |
3832 | * are cleared. This is especially important when decreasing the | |
3833 | * number of queues in use. | |
41c445ff | 3834 | */ |
70114ec4 | 3835 | for (; v_start < q_vectors; v_start++) { |
cd0b6fa6 AD |
3836 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; |
3837 | ||
3838 | num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); | |
3839 | ||
3840 | q_vector->num_ringpairs = num_ringpairs; | |
3841 | ||
3842 | q_vector->rx.count = 0; | |
3843 | q_vector->tx.count = 0; | |
3844 | q_vector->rx.ring = NULL; | |
3845 | q_vector->tx.ring = NULL; | |
3846 | ||
3847 | while (num_ringpairs--) { | |
26cdc443 | 3848 | i40e_map_vector_to_qp(vsi, v_start, qp_idx); |
cd0b6fa6 AD |
3849 | qp_idx++; |
3850 | qp_remaining--; | |
41c445ff JB |
3851 | } |
3852 | } | |
3853 | } | |
3854 | ||
3855 | /** | |
3856 | * i40e_vsi_request_irq - Request IRQ from the OS | |
3857 | * @vsi: the VSI being configured | |
3858 | * @basename: name for the vector | |
3859 | **/ | |
3860 | static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename) | |
3861 | { | |
3862 | struct i40e_pf *pf = vsi->back; | |
3863 | int err; | |
3864 | ||
3865 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
3866 | err = i40e_vsi_request_irq_msix(vsi, basename); | |
3867 | else if (pf->flags & I40E_FLAG_MSI_ENABLED) | |
3868 | err = request_irq(pf->pdev->irq, i40e_intr, 0, | |
b294ac70 | 3869 | pf->int_name, pf); |
41c445ff JB |
3870 | else |
3871 | err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED, | |
b294ac70 | 3872 | pf->int_name, pf); |
41c445ff JB |
3873 | |
3874 | if (err) | |
3875 | dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err); | |
3876 | ||
3877 | return err; | |
3878 | } | |
3879 | ||
3880 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3881 | /** | |
d89d967f | 3882 | * i40e_netpoll - A Polling 'interrupt' handler |
41c445ff JB |
3883 | * @netdev: network interface device structure |
3884 | * | |
3885 | * This is used by netconsole to send skbs without having to re-enable | |
3886 | * interrupts. It's not called while the normal interrupt routine is executing. | |
3887 | **/ | |
38e00438 VD |
3888 | #ifdef I40E_FCOE |
3889 | void i40e_netpoll(struct net_device *netdev) | |
3890 | #else | |
41c445ff | 3891 | static void i40e_netpoll(struct net_device *netdev) |
38e00438 | 3892 | #endif |
41c445ff JB |
3893 | { |
3894 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
3895 | struct i40e_vsi *vsi = np->vsi; | |
3896 | struct i40e_pf *pf = vsi->back; | |
3897 | int i; | |
3898 | ||
3899 | /* if interface is down do nothing */ | |
3900 | if (test_bit(__I40E_DOWN, &vsi->state)) | |
3901 | return; | |
3902 | ||
41c445ff JB |
3903 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
3904 | for (i = 0; i < vsi->num_q_vectors; i++) | |
493fb300 | 3905 | i40e_msix_clean_rings(0, vsi->q_vectors[i]); |
41c445ff JB |
3906 | } else { |
3907 | i40e_intr(pf->pdev->irq, netdev); | |
3908 | } | |
41c445ff JB |
3909 | } |
3910 | #endif | |
3911 | ||
23527308 NP |
3912 | /** |
3913 | * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled | |
3914 | * @pf: the PF being configured | |
3915 | * @pf_q: the PF queue | |
3916 | * @enable: enable or disable state of the queue | |
3917 | * | |
3918 | * This routine will wait for the given Tx queue of the PF to reach the | |
3919 | * enabled or disabled state. | |
3920 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
3921 | * multiple retries; else will return 0 in case of success. | |
3922 | **/ | |
3923 | static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
3924 | { | |
3925 | int i; | |
3926 | u32 tx_reg; | |
3927 | ||
3928 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
3929 | tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); | |
3930 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
3931 | break; | |
3932 | ||
f98a2006 | 3933 | usleep_range(10, 20); |
23527308 NP |
3934 | } |
3935 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
3936 | return -ETIMEDOUT; | |
3937 | ||
3938 | return 0; | |
3939 | } | |
3940 | ||
41c445ff JB |
3941 | /** |
3942 | * i40e_vsi_control_tx - Start or stop a VSI's rings | |
3943 | * @vsi: the VSI being configured | |
3944 | * @enable: start or stop the rings | |
3945 | **/ | |
3946 | static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) | |
3947 | { | |
3948 | struct i40e_pf *pf = vsi->back; | |
3949 | struct i40e_hw *hw = &pf->hw; | |
23527308 | 3950 | int i, j, pf_q, ret = 0; |
41c445ff JB |
3951 | u32 tx_reg; |
3952 | ||
3953 | pf_q = vsi->base_queue; | |
3954 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
351499ab MJ |
3955 | |
3956 | /* warn the TX unit of coming changes */ | |
3957 | i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable); | |
3958 | if (!enable) | |
f98a2006 | 3959 | usleep_range(10, 20); |
351499ab | 3960 | |
6c5ef620 | 3961 | for (j = 0; j < 50; j++) { |
41c445ff | 3962 | tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); |
6c5ef620 MW |
3963 | if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == |
3964 | ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) | |
3965 | break; | |
3966 | usleep_range(1000, 2000); | |
3967 | } | |
fda972f6 | 3968 | /* Skip if the queue is already in the requested state */ |
7c122007 | 3969 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) |
fda972f6 | 3970 | continue; |
41c445ff JB |
3971 | |
3972 | /* turn on/off the queue */ | |
c5c9eb9e SN |
3973 | if (enable) { |
3974 | wr32(hw, I40E_QTX_HEAD(pf_q), 0); | |
6c5ef620 | 3975 | tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; |
c5c9eb9e | 3976 | } else { |
41c445ff | 3977 | tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; |
c5c9eb9e | 3978 | } |
41c445ff JB |
3979 | |
3980 | wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); | |
69129dc3 NP |
3981 | /* No waiting for the Tx queue to disable */ |
3982 | if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state)) | |
3983 | continue; | |
41c445ff JB |
3984 | |
3985 | /* wait for the change to finish */ | |
23527308 NP |
3986 | ret = i40e_pf_txq_wait(pf, pf_q, enable); |
3987 | if (ret) { | |
3988 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
3989 | "VSI seid %d Tx ring %d %sable timeout\n", |
3990 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
23527308 | 3991 | break; |
41c445ff JB |
3992 | } |
3993 | } | |
3994 | ||
7134f9ce JB |
3995 | if (hw->revision_id == 0) |
3996 | mdelay(50); | |
23527308 NP |
3997 | return ret; |
3998 | } | |
3999 | ||
4000 | /** | |
4001 | * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled | |
4002 | * @pf: the PF being configured | |
4003 | * @pf_q: the PF queue | |
4004 | * @enable: enable or disable state of the queue | |
4005 | * | |
4006 | * This routine will wait for the given Rx queue of the PF to reach the | |
4007 | * enabled or disabled state. | |
4008 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4009 | * multiple retries; else will return 0 in case of success. | |
4010 | **/ | |
4011 | static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4012 | { | |
4013 | int i; | |
4014 | u32 rx_reg; | |
4015 | ||
4016 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4017 | rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); | |
4018 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4019 | break; | |
4020 | ||
f98a2006 | 4021 | usleep_range(10, 20); |
23527308 NP |
4022 | } |
4023 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4024 | return -ETIMEDOUT; | |
7134f9ce | 4025 | |
41c445ff JB |
4026 | return 0; |
4027 | } | |
4028 | ||
4029 | /** | |
4030 | * i40e_vsi_control_rx - Start or stop a VSI's rings | |
4031 | * @vsi: the VSI being configured | |
4032 | * @enable: start or stop the rings | |
4033 | **/ | |
4034 | static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) | |
4035 | { | |
4036 | struct i40e_pf *pf = vsi->back; | |
4037 | struct i40e_hw *hw = &pf->hw; | |
23527308 | 4038 | int i, j, pf_q, ret = 0; |
41c445ff JB |
4039 | u32 rx_reg; |
4040 | ||
4041 | pf_q = vsi->base_queue; | |
4042 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
6c5ef620 | 4043 | for (j = 0; j < 50; j++) { |
41c445ff | 4044 | rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); |
6c5ef620 MW |
4045 | if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == |
4046 | ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) | |
4047 | break; | |
4048 | usleep_range(1000, 2000); | |
4049 | } | |
41c445ff | 4050 | |
7c122007 CS |
4051 | /* Skip if the queue is already in the requested state */ |
4052 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4053 | continue; | |
41c445ff JB |
4054 | |
4055 | /* turn on/off the queue */ | |
4056 | if (enable) | |
6c5ef620 | 4057 | rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; |
41c445ff | 4058 | else |
6c5ef620 | 4059 | rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; |
41c445ff | 4060 | wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); |
3fe06f41 NP |
4061 | /* No waiting for the Tx queue to disable */ |
4062 | if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state)) | |
4063 | continue; | |
41c445ff JB |
4064 | |
4065 | /* wait for the change to finish */ | |
23527308 NP |
4066 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); |
4067 | if (ret) { | |
4068 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4069 | "VSI seid %d Rx ring %d %sable timeout\n", |
4070 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
23527308 | 4071 | break; |
41c445ff JB |
4072 | } |
4073 | } | |
4074 | ||
23527308 | 4075 | return ret; |
41c445ff JB |
4076 | } |
4077 | ||
4078 | /** | |
3aa7b74d | 4079 | * i40e_vsi_start_rings - Start a VSI's rings |
41c445ff | 4080 | * @vsi: the VSI being configured |
41c445ff | 4081 | **/ |
3aa7b74d | 4082 | int i40e_vsi_start_rings(struct i40e_vsi *vsi) |
41c445ff | 4083 | { |
3b867b28 | 4084 | int ret = 0; |
41c445ff JB |
4085 | |
4086 | /* do rx first for enable and last for disable */ | |
3aa7b74d FS |
4087 | ret = i40e_vsi_control_rx(vsi, true); |
4088 | if (ret) | |
4089 | return ret; | |
4090 | ret = i40e_vsi_control_tx(vsi, true); | |
41c445ff JB |
4091 | |
4092 | return ret; | |
4093 | } | |
4094 | ||
3aa7b74d FS |
4095 | /** |
4096 | * i40e_vsi_stop_rings - Stop a VSI's rings | |
4097 | * @vsi: the VSI being configured | |
4098 | **/ | |
4099 | void i40e_vsi_stop_rings(struct i40e_vsi *vsi) | |
4100 | { | |
4101 | /* do rx first for enable and last for disable | |
4102 | * Ignore return value, we need to shutdown whatever we can | |
4103 | */ | |
4104 | i40e_vsi_control_tx(vsi, false); | |
4105 | i40e_vsi_control_rx(vsi, false); | |
4106 | } | |
4107 | ||
41c445ff JB |
4108 | /** |
4109 | * i40e_vsi_free_irq - Free the irq association with the OS | |
4110 | * @vsi: the VSI being configured | |
4111 | **/ | |
4112 | static void i40e_vsi_free_irq(struct i40e_vsi *vsi) | |
4113 | { | |
4114 | struct i40e_pf *pf = vsi->back; | |
4115 | struct i40e_hw *hw = &pf->hw; | |
4116 | int base = vsi->base_vector; | |
4117 | u32 val, qp; | |
4118 | int i; | |
4119 | ||
4120 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4121 | if (!vsi->q_vectors) | |
4122 | return; | |
4123 | ||
63741846 SN |
4124 | if (!vsi->irqs_ready) |
4125 | return; | |
4126 | ||
4127 | vsi->irqs_ready = false; | |
41c445ff | 4128 | for (i = 0; i < vsi->num_q_vectors; i++) { |
96db776a AB |
4129 | int irq_num; |
4130 | u16 vector; | |
4131 | ||
4132 | vector = i + base; | |
4133 | irq_num = pf->msix_entries[vector].vector; | |
41c445ff JB |
4134 | |
4135 | /* free only the irqs that were actually requested */ | |
78681b1f SN |
4136 | if (!vsi->q_vectors[i] || |
4137 | !vsi->q_vectors[i]->num_ringpairs) | |
41c445ff JB |
4138 | continue; |
4139 | ||
96db776a AB |
4140 | /* clear the affinity notifier in the IRQ descriptor */ |
4141 | irq_set_affinity_notifier(irq_num, NULL); | |
41c445ff | 4142 | /* clear the affinity_mask in the IRQ descriptor */ |
96db776a AB |
4143 | irq_set_affinity_hint(irq_num, NULL); |
4144 | synchronize_irq(irq_num); | |
4145 | free_irq(irq_num, vsi->q_vectors[i]); | |
41c445ff JB |
4146 | |
4147 | /* Tear down the interrupt queue link list | |
4148 | * | |
4149 | * We know that they come in pairs and always | |
4150 | * the Rx first, then the Tx. To clear the | |
4151 | * link list, stick the EOL value into the | |
4152 | * next_q field of the registers. | |
4153 | */ | |
4154 | val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); | |
4155 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4156 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4157 | val |= I40E_QUEUE_END_OF_LIST | |
4158 | << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4159 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); | |
4160 | ||
4161 | while (qp != I40E_QUEUE_END_OF_LIST) { | |
4162 | u32 next; | |
4163 | ||
4164 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4165 | ||
4166 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4167 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4168 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4169 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4170 | ||
4171 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4172 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4173 | ||
4174 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4175 | ||
4176 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4177 | ||
4178 | next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) | |
4179 | >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; | |
4180 | ||
4181 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4182 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4183 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4184 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4185 | ||
4186 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4187 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4188 | ||
4189 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4190 | qp = next; | |
4191 | } | |
4192 | } | |
4193 | } else { | |
4194 | free_irq(pf->pdev->irq, pf); | |
4195 | ||
4196 | val = rd32(hw, I40E_PFINT_LNKLST0); | |
4197 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4198 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4199 | val |= I40E_QUEUE_END_OF_LIST | |
4200 | << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
4201 | wr32(hw, I40E_PFINT_LNKLST0, val); | |
4202 | ||
4203 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4204 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4205 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4206 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4207 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4208 | ||
4209 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4210 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4211 | ||
4212 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4213 | ||
4214 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4215 | ||
4216 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4217 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4218 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4219 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4220 | ||
4221 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4222 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4223 | ||
4224 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4225 | } | |
4226 | } | |
4227 | ||
493fb300 AD |
4228 | /** |
4229 | * i40e_free_q_vector - Free memory allocated for specific interrupt vector | |
4230 | * @vsi: the VSI being configured | |
4231 | * @v_idx: Index of vector to be freed | |
4232 | * | |
4233 | * This function frees the memory allocated to the q_vector. In addition if | |
4234 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4235 | * to freeing the q_vector. | |
4236 | **/ | |
4237 | static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx) | |
4238 | { | |
4239 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; | |
cd0b6fa6 | 4240 | struct i40e_ring *ring; |
493fb300 AD |
4241 | |
4242 | if (!q_vector) | |
4243 | return; | |
4244 | ||
4245 | /* disassociate q_vector from rings */ | |
cd0b6fa6 AD |
4246 | i40e_for_each_ring(ring, q_vector->tx) |
4247 | ring->q_vector = NULL; | |
4248 | ||
4249 | i40e_for_each_ring(ring, q_vector->rx) | |
4250 | ring->q_vector = NULL; | |
493fb300 AD |
4251 | |
4252 | /* only VSI w/ an associated netdev is set up w/ NAPI */ | |
4253 | if (vsi->netdev) | |
4254 | netif_napi_del(&q_vector->napi); | |
4255 | ||
4256 | vsi->q_vectors[v_idx] = NULL; | |
4257 | ||
4258 | kfree_rcu(q_vector, rcu); | |
4259 | } | |
4260 | ||
41c445ff JB |
4261 | /** |
4262 | * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors | |
4263 | * @vsi: the VSI being un-configured | |
4264 | * | |
4265 | * This frees the memory allocated to the q_vectors and | |
4266 | * deletes references to the NAPI struct. | |
4267 | **/ | |
4268 | static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi) | |
4269 | { | |
4270 | int v_idx; | |
4271 | ||
493fb300 AD |
4272 | for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) |
4273 | i40e_free_q_vector(vsi, v_idx); | |
41c445ff JB |
4274 | } |
4275 | ||
4276 | /** | |
4277 | * i40e_reset_interrupt_capability - Disable interrupt setup in OS | |
4278 | * @pf: board private structure | |
4279 | **/ | |
4280 | static void i40e_reset_interrupt_capability(struct i40e_pf *pf) | |
4281 | { | |
4282 | /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */ | |
4283 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4284 | pci_disable_msix(pf->pdev); | |
4285 | kfree(pf->msix_entries); | |
4286 | pf->msix_entries = NULL; | |
3b444399 SN |
4287 | kfree(pf->irq_pile); |
4288 | pf->irq_pile = NULL; | |
41c445ff JB |
4289 | } else if (pf->flags & I40E_FLAG_MSI_ENABLED) { |
4290 | pci_disable_msi(pf->pdev); | |
4291 | } | |
4292 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
4293 | } | |
4294 | ||
4295 | /** | |
4296 | * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4297 | * @pf: board private structure | |
4298 | * | |
4299 | * We go through and clear interrupt specific resources and reset the structure | |
4300 | * to pre-load conditions | |
4301 | **/ | |
4302 | static void i40e_clear_interrupt_scheme(struct i40e_pf *pf) | |
4303 | { | |
4304 | int i; | |
4305 | ||
e147758d | 4306 | i40e_stop_misc_vector(pf); |
69278398 | 4307 | if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) { |
e147758d SN |
4308 | synchronize_irq(pf->msix_entries[0].vector); |
4309 | free_irq(pf->msix_entries[0].vector, pf); | |
4310 | } | |
4311 | ||
e3219ce6 ASJ |
4312 | i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector, |
4313 | I40E_IWARP_IRQ_PILE_ID); | |
4314 | ||
41c445ff | 4315 | i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1); |
505682cd | 4316 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
4317 | if (pf->vsi[i]) |
4318 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
4319 | i40e_reset_interrupt_capability(pf); | |
4320 | } | |
4321 | ||
4322 | /** | |
4323 | * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI | |
4324 | * @vsi: the VSI being configured | |
4325 | **/ | |
4326 | static void i40e_napi_enable_all(struct i40e_vsi *vsi) | |
4327 | { | |
4328 | int q_idx; | |
4329 | ||
4330 | if (!vsi->netdev) | |
4331 | return; | |
4332 | ||
4333 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) | |
493fb300 | 4334 | napi_enable(&vsi->q_vectors[q_idx]->napi); |
41c445ff JB |
4335 | } |
4336 | ||
4337 | /** | |
4338 | * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI | |
4339 | * @vsi: the VSI being configured | |
4340 | **/ | |
4341 | static void i40e_napi_disable_all(struct i40e_vsi *vsi) | |
4342 | { | |
4343 | int q_idx; | |
4344 | ||
4345 | if (!vsi->netdev) | |
4346 | return; | |
4347 | ||
4348 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) | |
493fb300 | 4349 | napi_disable(&vsi->q_vectors[q_idx]->napi); |
41c445ff JB |
4350 | } |
4351 | ||
90ef8d47 SN |
4352 | /** |
4353 | * i40e_vsi_close - Shut down a VSI | |
4354 | * @vsi: the vsi to be quelled | |
4355 | **/ | |
4356 | static void i40e_vsi_close(struct i40e_vsi *vsi) | |
4357 | { | |
e3219ce6 ASJ |
4358 | bool reset = false; |
4359 | ||
90ef8d47 SN |
4360 | if (!test_and_set_bit(__I40E_DOWN, &vsi->state)) |
4361 | i40e_down(vsi); | |
4362 | i40e_vsi_free_irq(vsi); | |
4363 | i40e_vsi_free_tx_resources(vsi); | |
4364 | i40e_vsi_free_rx_resources(vsi); | |
92faef85 | 4365 | vsi->current_netdev_flags = 0; |
e3219ce6 ASJ |
4366 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) |
4367 | reset = true; | |
4368 | i40e_notify_client_of_netdev_close(vsi, reset); | |
90ef8d47 SN |
4369 | } |
4370 | ||
41c445ff JB |
4371 | /** |
4372 | * i40e_quiesce_vsi - Pause a given VSI | |
4373 | * @vsi: the VSI being paused | |
4374 | **/ | |
4375 | static void i40e_quiesce_vsi(struct i40e_vsi *vsi) | |
4376 | { | |
4377 | if (test_bit(__I40E_DOWN, &vsi->state)) | |
4378 | return; | |
4379 | ||
d341b7a5 NP |
4380 | /* No need to disable FCoE VSI when Tx suspended */ |
4381 | if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) && | |
4382 | vsi->type == I40E_VSI_FCOE) { | |
4383 | dev_dbg(&vsi->back->pdev->dev, | |
fb43201f | 4384 | "VSI seid %d skipping FCoE VSI disable\n", vsi->seid); |
d341b7a5 NP |
4385 | return; |
4386 | } | |
4387 | ||
41c445ff | 4388 | set_bit(__I40E_NEEDS_RESTART, &vsi->state); |
6995b36c | 4389 | if (vsi->netdev && netif_running(vsi->netdev)) |
41c445ff | 4390 | vsi->netdev->netdev_ops->ndo_stop(vsi->netdev); |
6995b36c | 4391 | else |
90ef8d47 | 4392 | i40e_vsi_close(vsi); |
41c445ff JB |
4393 | } |
4394 | ||
4395 | /** | |
4396 | * i40e_unquiesce_vsi - Resume a given VSI | |
4397 | * @vsi: the VSI being resumed | |
4398 | **/ | |
4399 | static void i40e_unquiesce_vsi(struct i40e_vsi *vsi) | |
4400 | { | |
4401 | if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state)) | |
4402 | return; | |
4403 | ||
4404 | clear_bit(__I40E_NEEDS_RESTART, &vsi->state); | |
4405 | if (vsi->netdev && netif_running(vsi->netdev)) | |
4406 | vsi->netdev->netdev_ops->ndo_open(vsi->netdev); | |
4407 | else | |
8276f757 | 4408 | i40e_vsi_open(vsi); /* this clears the DOWN bit */ |
41c445ff JB |
4409 | } |
4410 | ||
4411 | /** | |
4412 | * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF | |
4413 | * @pf: the PF | |
4414 | **/ | |
4415 | static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf) | |
4416 | { | |
4417 | int v; | |
4418 | ||
505682cd | 4419 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4420 | if (pf->vsi[v]) |
4421 | i40e_quiesce_vsi(pf->vsi[v]); | |
4422 | } | |
4423 | } | |
4424 | ||
4425 | /** | |
4426 | * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF | |
4427 | * @pf: the PF | |
4428 | **/ | |
4429 | static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) | |
4430 | { | |
4431 | int v; | |
4432 | ||
505682cd | 4433 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4434 | if (pf->vsi[v]) |
4435 | i40e_unquiesce_vsi(pf->vsi[v]); | |
4436 | } | |
4437 | } | |
4438 | ||
69129dc3 NP |
4439 | #ifdef CONFIG_I40E_DCB |
4440 | /** | |
3fe06f41 | 4441 | * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled |
69129dc3 NP |
4442 | * @vsi: the VSI being configured |
4443 | * | |
3fe06f41 | 4444 | * This function waits for the given VSI's queues to be disabled. |
69129dc3 | 4445 | **/ |
3fe06f41 | 4446 | static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi) |
69129dc3 NP |
4447 | { |
4448 | struct i40e_pf *pf = vsi->back; | |
4449 | int i, pf_q, ret; | |
4450 | ||
4451 | pf_q = vsi->base_queue; | |
4452 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4453 | /* Check and wait for the disable status of the queue */ | |
4454 | ret = i40e_pf_txq_wait(pf, pf_q, false); | |
4455 | if (ret) { | |
4456 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4457 | "VSI seid %d Tx ring %d disable timeout\n", |
4458 | vsi->seid, pf_q); | |
69129dc3 NP |
4459 | return ret; |
4460 | } | |
4461 | } | |
4462 | ||
3fe06f41 NP |
4463 | pf_q = vsi->base_queue; |
4464 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4465 | /* Check and wait for the disable status of the queue */ | |
4466 | ret = i40e_pf_rxq_wait(pf, pf_q, false); | |
4467 | if (ret) { | |
4468 | dev_info(&pf->pdev->dev, | |
4469 | "VSI seid %d Rx ring %d disable timeout\n", | |
4470 | vsi->seid, pf_q); | |
4471 | return ret; | |
4472 | } | |
4473 | } | |
4474 | ||
69129dc3 NP |
4475 | return 0; |
4476 | } | |
4477 | ||
4478 | /** | |
3fe06f41 | 4479 | * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled |
69129dc3 NP |
4480 | * @pf: the PF |
4481 | * | |
3fe06f41 | 4482 | * This function waits for the queues to be in disabled state for all the |
69129dc3 NP |
4483 | * VSIs that are managed by this PF. |
4484 | **/ | |
3fe06f41 | 4485 | static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf) |
69129dc3 NP |
4486 | { |
4487 | int v, ret = 0; | |
4488 | ||
4489 | for (v = 0; v < pf->hw.func_caps.num_vsis; v++) { | |
d341b7a5 NP |
4490 | /* No need to wait for FCoE VSI queues */ |
4491 | if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) { | |
3fe06f41 | 4492 | ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]); |
69129dc3 NP |
4493 | if (ret) |
4494 | break; | |
4495 | } | |
4496 | } | |
4497 | ||
4498 | return ret; | |
4499 | } | |
4500 | ||
4501 | #endif | |
b03a8c1f KP |
4502 | |
4503 | /** | |
4504 | * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue | |
4505 | * @q_idx: TX queue number | |
4506 | * @vsi: Pointer to VSI struct | |
4507 | * | |
4508 | * This function checks specified queue for given VSI. Detects hung condition. | |
4509 | * Sets hung bit since it is two step process. Before next run of service task | |
4510 | * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not, | |
4511 | * hung condition remain unchanged and during subsequent run, this function | |
4512 | * issues SW interrupt to recover from hung condition. | |
4513 | **/ | |
4514 | static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi) | |
4515 | { | |
4516 | struct i40e_ring *tx_ring = NULL; | |
4517 | struct i40e_pf *pf; | |
dd353109 | 4518 | u32 head, val, tx_pending_hw; |
b03a8c1f KP |
4519 | int i; |
4520 | ||
4521 | pf = vsi->back; | |
4522 | ||
4523 | /* now that we have an index, find the tx_ring struct */ | |
4524 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
4525 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
4526 | if (q_idx == vsi->tx_rings[i]->queue_index) { | |
4527 | tx_ring = vsi->tx_rings[i]; | |
4528 | break; | |
4529 | } | |
4530 | } | |
4531 | } | |
4532 | ||
4533 | if (!tx_ring) | |
4534 | return; | |
4535 | ||
4536 | /* Read interrupt register */ | |
4537 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
4538 | val = rd32(&pf->hw, | |
4539 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
4540 | tx_ring->vsi->base_vector - 1)); | |
4541 | else | |
4542 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
4543 | ||
4544 | head = i40e_get_head(tx_ring); | |
4545 | ||
dd353109 | 4546 | tx_pending_hw = i40e_get_tx_pending(tx_ring, false); |
b03a8c1f | 4547 | |
9c6c1259 KP |
4548 | /* HW is done executing descriptors, updated HEAD write back, |
4549 | * but SW hasn't processed those descriptors. If interrupt is | |
4550 | * not generated from this point ON, it could result into | |
4551 | * dev_watchdog detecting timeout on those netdev_queue, | |
4552 | * hence proactively trigger SW interrupt. | |
b03a8c1f | 4553 | */ |
dd353109 | 4554 | if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) { |
9c6c1259 KP |
4555 | /* NAPI Poll didn't run and clear since it was set */ |
4556 | if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT, | |
4557 | &tx_ring->q_vector->hung_detected)) { | |
dd353109 ASJ |
4558 | netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n", |
4559 | vsi->seid, q_idx, tx_pending_hw, | |
9c6c1259 KP |
4560 | tx_ring->next_to_clean, head, |
4561 | tx_ring->next_to_use, | |
4562 | readl(tx_ring->tail)); | |
4563 | netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n", | |
4564 | vsi->seid, q_idx, val); | |
4565 | i40e_force_wb(vsi, tx_ring->q_vector); | |
4566 | } else { | |
4567 | /* First Chance - detected possible hung */ | |
4568 | set_bit(I40E_Q_VECTOR_HUNG_DETECT, | |
4569 | &tx_ring->q_vector->hung_detected); | |
4570 | } | |
4571 | } | |
dd353109 ASJ |
4572 | |
4573 | /* This is the case where we have interrupts missing, | |
4574 | * so the tx_pending in HW will most likely be 0, but we | |
4575 | * will have tx_pending in SW since the WB happened but the | |
4576 | * interrupt got lost. | |
4577 | */ | |
4578 | if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) && | |
4579 | (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) { | |
4580 | if (napi_reschedule(&tx_ring->q_vector->napi)) | |
4581 | tx_ring->tx_stats.tx_lost_interrupt++; | |
4582 | } | |
b03a8c1f KP |
4583 | } |
4584 | ||
4585 | /** | |
4586 | * i40e_detect_recover_hung - Function to detect and recover hung_queues | |
4587 | * @pf: pointer to PF struct | |
4588 | * | |
4589 | * LAN VSI has netdev and netdev has TX queues. This function is to check | |
4590 | * each of those TX queues if they are hung, trigger recovery by issuing | |
4591 | * SW interrupt. | |
4592 | **/ | |
4593 | static void i40e_detect_recover_hung(struct i40e_pf *pf) | |
4594 | { | |
4595 | struct net_device *netdev; | |
4596 | struct i40e_vsi *vsi; | |
4597 | int i; | |
4598 | ||
4599 | /* Only for LAN VSI */ | |
4600 | vsi = pf->vsi[pf->lan_vsi]; | |
4601 | ||
4602 | if (!vsi) | |
4603 | return; | |
4604 | ||
4605 | /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */ | |
4606 | if (test_bit(__I40E_DOWN, &vsi->back->state) || | |
4607 | test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) | |
4608 | return; | |
4609 | ||
4610 | /* Make sure type is MAIN VSI */ | |
4611 | if (vsi->type != I40E_VSI_MAIN) | |
4612 | return; | |
4613 | ||
4614 | netdev = vsi->netdev; | |
4615 | if (!netdev) | |
4616 | return; | |
4617 | ||
4618 | /* Bail out if netif_carrier is not OK */ | |
4619 | if (!netif_carrier_ok(netdev)) | |
4620 | return; | |
4621 | ||
4622 | /* Go thru' TX queues for netdev */ | |
4623 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
4624 | struct netdev_queue *q; | |
4625 | ||
4626 | q = netdev_get_tx_queue(netdev, i); | |
4627 | if (q) | |
4628 | i40e_detect_recover_hung_queue(i, vsi); | |
4629 | } | |
4630 | } | |
4631 | ||
63d7e5a4 NP |
4632 | /** |
4633 | * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP | |
b40c82e6 | 4634 | * @pf: pointer to PF |
63d7e5a4 NP |
4635 | * |
4636 | * Get TC map for ISCSI PF type that will include iSCSI TC | |
4637 | * and LAN TC. | |
4638 | **/ | |
4639 | static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf) | |
4640 | { | |
4641 | struct i40e_dcb_app_priority_table app; | |
4642 | struct i40e_hw *hw = &pf->hw; | |
4643 | u8 enabled_tc = 1; /* TC0 is always enabled */ | |
4644 | u8 tc, i; | |
4645 | /* Get the iSCSI APP TLV */ | |
4646 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4647 | ||
4648 | for (i = 0; i < dcbcfg->numapps; i++) { | |
4649 | app = dcbcfg->app[i]; | |
4650 | if (app.selector == I40E_APP_SEL_TCPIP && | |
4651 | app.protocolid == I40E_APP_PROTOID_ISCSI) { | |
4652 | tc = dcbcfg->etscfg.prioritytable[app.priority]; | |
75f5cea9 | 4653 | enabled_tc |= BIT(tc); |
63d7e5a4 NP |
4654 | break; |
4655 | } | |
4656 | } | |
4657 | ||
4658 | return enabled_tc; | |
4659 | } | |
4660 | ||
41c445ff JB |
4661 | /** |
4662 | * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config | |
4663 | * @dcbcfg: the corresponding DCBx configuration structure | |
4664 | * | |
4665 | * Return the number of TCs from given DCBx configuration | |
4666 | **/ | |
4667 | static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) | |
4668 | { | |
fbfe12c6 | 4669 | int i, tc_unused = 0; |
078b5876 | 4670 | u8 num_tc = 0; |
fbfe12c6 | 4671 | u8 ret = 0; |
41c445ff JB |
4672 | |
4673 | /* Scan the ETS Config Priority Table to find | |
4674 | * traffic class enabled for a given priority | |
fbfe12c6 | 4675 | * and create a bitmask of enabled TCs |
41c445ff | 4676 | */ |
fbfe12c6 DE |
4677 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) |
4678 | num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]); | |
41c445ff | 4679 | |
fbfe12c6 DE |
4680 | /* Now scan the bitmask to check for |
4681 | * contiguous TCs starting with TC0 | |
41c445ff | 4682 | */ |
fbfe12c6 DE |
4683 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
4684 | if (num_tc & BIT(i)) { | |
4685 | if (!tc_unused) { | |
4686 | ret++; | |
4687 | } else { | |
4688 | pr_err("Non-contiguous TC - Disabling DCB\n"); | |
4689 | return 1; | |
4690 | } | |
4691 | } else { | |
4692 | tc_unused = 1; | |
4693 | } | |
4694 | } | |
4695 | ||
4696 | /* There is always at least TC0 */ | |
4697 | if (!ret) | |
4698 | ret = 1; | |
4699 | ||
4700 | return ret; | |
41c445ff JB |
4701 | } |
4702 | ||
4703 | /** | |
4704 | * i40e_dcb_get_enabled_tc - Get enabled traffic classes | |
4705 | * @dcbcfg: the corresponding DCBx configuration structure | |
4706 | * | |
4707 | * Query the current DCB configuration and return the number of | |
4708 | * traffic classes enabled from the given DCBX config | |
4709 | **/ | |
4710 | static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg) | |
4711 | { | |
4712 | u8 num_tc = i40e_dcb_get_num_tc(dcbcfg); | |
4713 | u8 enabled_tc = 1; | |
4714 | u8 i; | |
4715 | ||
4716 | for (i = 0; i < num_tc; i++) | |
41a1d04b | 4717 | enabled_tc |= BIT(i); |
41c445ff JB |
4718 | |
4719 | return enabled_tc; | |
4720 | } | |
4721 | ||
4722 | /** | |
4723 | * i40e_pf_get_num_tc - Get enabled traffic classes for PF | |
4724 | * @pf: PF being queried | |
4725 | * | |
4726 | * Return number of traffic classes enabled for the given PF | |
4727 | **/ | |
4728 | static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) | |
4729 | { | |
4730 | struct i40e_hw *hw = &pf->hw; | |
52a08caa | 4731 | u8 i, enabled_tc = 1; |
41c445ff JB |
4732 | u8 num_tc = 0; |
4733 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4734 | ||
4735 | /* If DCB is not enabled then always in single TC */ | |
4736 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) | |
4737 | return 1; | |
4738 | ||
63d7e5a4 NP |
4739 | /* SFP mode will be enabled for all TCs on port */ |
4740 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) | |
4741 | return i40e_dcb_get_num_tc(dcbcfg); | |
4742 | ||
41c445ff | 4743 | /* MFP mode return count of enabled TCs for this PF */ |
63d7e5a4 NP |
4744 | if (pf->hw.func_caps.iscsi) |
4745 | enabled_tc = i40e_get_iscsi_tc_map(pf); | |
4746 | else | |
fc51de96 | 4747 | return 1; /* Only TC0 */ |
41c445ff | 4748 | |
63d7e5a4 | 4749 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
75f5cea9 | 4750 | if (enabled_tc & BIT(i)) |
63d7e5a4 NP |
4751 | num_tc++; |
4752 | } | |
4753 | return num_tc; | |
41c445ff JB |
4754 | } |
4755 | ||
41c445ff JB |
4756 | /** |
4757 | * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes | |
4758 | * @pf: PF being queried | |
4759 | * | |
4760 | * Return a bitmap for enabled traffic classes for this PF. | |
4761 | **/ | |
4762 | static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) | |
4763 | { | |
4764 | /* If DCB is not enabled for this PF then just return default TC */ | |
4765 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) | |
ea6acb7e | 4766 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff | 4767 | |
41c445ff | 4768 | /* SFP mode we want PF to be enabled for all TCs */ |
63d7e5a4 NP |
4769 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
4770 | return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config); | |
4771 | ||
fc51de96 | 4772 | /* MFP enabled and iSCSI PF type */ |
63d7e5a4 NP |
4773 | if (pf->hw.func_caps.iscsi) |
4774 | return i40e_get_iscsi_tc_map(pf); | |
4775 | else | |
ea6acb7e | 4776 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff JB |
4777 | } |
4778 | ||
4779 | /** | |
4780 | * i40e_vsi_get_bw_info - Query VSI BW Information | |
4781 | * @vsi: the VSI being queried | |
4782 | * | |
4783 | * Returns 0 on success, negative value on failure | |
4784 | **/ | |
4785 | static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) | |
4786 | { | |
4787 | struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0}; | |
4788 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; | |
4789 | struct i40e_pf *pf = vsi->back; | |
4790 | struct i40e_hw *hw = &pf->hw; | |
f1c7e72e | 4791 | i40e_status ret; |
41c445ff | 4792 | u32 tc_bw_max; |
41c445ff JB |
4793 | int i; |
4794 | ||
4795 | /* Get the VSI level BW configuration */ | |
f1c7e72e SN |
4796 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); |
4797 | if (ret) { | |
41c445ff | 4798 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
4799 | "couldn't get PF vsi bw config, err %s aq_err %s\n", |
4800 | i40e_stat_str(&pf->hw, ret), | |
4801 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 4802 | return -EINVAL; |
41c445ff JB |
4803 | } |
4804 | ||
4805 | /* Get the VSI level BW configuration per TC */ | |
f1c7e72e SN |
4806 | ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config, |
4807 | NULL); | |
4808 | if (ret) { | |
41c445ff | 4809 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
4810 | "couldn't get PF vsi ets bw config, err %s aq_err %s\n", |
4811 | i40e_stat_str(&pf->hw, ret), | |
4812 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 4813 | return -EINVAL; |
41c445ff JB |
4814 | } |
4815 | ||
4816 | if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) { | |
4817 | dev_info(&pf->pdev->dev, | |
4818 | "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n", | |
4819 | bw_config.tc_valid_bits, | |
4820 | bw_ets_config.tc_valid_bits); | |
4821 | /* Still continuing */ | |
4822 | } | |
4823 | ||
4824 | vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit); | |
4825 | vsi->bw_max_quanta = bw_config.max_bw; | |
4826 | tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) | | |
4827 | (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16); | |
4828 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
4829 | vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i]; | |
4830 | vsi->bw_ets_limit_credits[i] = | |
4831 | le16_to_cpu(bw_ets_config.credits[i]); | |
4832 | /* 3 bits out of 4 for each TC */ | |
4833 | vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7); | |
4834 | } | |
078b5876 | 4835 | |
dcae29be | 4836 | return 0; |
41c445ff JB |
4837 | } |
4838 | ||
4839 | /** | |
4840 | * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC | |
4841 | * @vsi: the VSI being configured | |
4842 | * @enabled_tc: TC bitmap | |
4843 | * @bw_credits: BW shared credits per TC | |
4844 | * | |
4845 | * Returns 0 on success, negative value on failure | |
4846 | **/ | |
dcae29be | 4847 | static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, |
41c445ff JB |
4848 | u8 *bw_share) |
4849 | { | |
4850 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
f1c7e72e | 4851 | i40e_status ret; |
dcae29be | 4852 | int i; |
41c445ff JB |
4853 | |
4854 | bw_data.tc_valid_bits = enabled_tc; | |
4855 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
4856 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
4857 | ||
f1c7e72e SN |
4858 | ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data, |
4859 | NULL); | |
4860 | if (ret) { | |
41c445ff | 4861 | dev_info(&vsi->back->pdev->dev, |
69bfb110 JB |
4862 | "AQ command Config VSI BW allocation per TC failed = %d\n", |
4863 | vsi->back->hw.aq.asq_last_status); | |
dcae29be | 4864 | return -EINVAL; |
41c445ff JB |
4865 | } |
4866 | ||
4867 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
4868 | vsi->info.qs_handle[i] = bw_data.qs_handles[i]; | |
4869 | ||
dcae29be | 4870 | return 0; |
41c445ff JB |
4871 | } |
4872 | ||
4873 | /** | |
4874 | * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration | |
4875 | * @vsi: the VSI being configured | |
4876 | * @enabled_tc: TC map to be enabled | |
4877 | * | |
4878 | **/ | |
4879 | static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
4880 | { | |
4881 | struct net_device *netdev = vsi->netdev; | |
4882 | struct i40e_pf *pf = vsi->back; | |
4883 | struct i40e_hw *hw = &pf->hw; | |
4884 | u8 netdev_tc = 0; | |
4885 | int i; | |
4886 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4887 | ||
4888 | if (!netdev) | |
4889 | return; | |
4890 | ||
4891 | if (!enabled_tc) { | |
4892 | netdev_reset_tc(netdev); | |
4893 | return; | |
4894 | } | |
4895 | ||
4896 | /* Set up actual enabled TCs on the VSI */ | |
4897 | if (netdev_set_num_tc(netdev, vsi->tc_config.numtc)) | |
4898 | return; | |
4899 | ||
4900 | /* set per TC queues for the VSI */ | |
4901 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
4902 | /* Only set TC queues for enabled tcs | |
4903 | * | |
4904 | * e.g. For a VSI that has TC0 and TC3 enabled the | |
4905 | * enabled_tc bitmap would be 0x00001001; the driver | |
4906 | * will set the numtc for netdev as 2 that will be | |
4907 | * referenced by the netdev layer as TC 0 and 1. | |
4908 | */ | |
75f5cea9 | 4909 | if (vsi->tc_config.enabled_tc & BIT(i)) |
41c445ff JB |
4910 | netdev_set_tc_queue(netdev, |
4911 | vsi->tc_config.tc_info[i].netdev_tc, | |
4912 | vsi->tc_config.tc_info[i].qcount, | |
4913 | vsi->tc_config.tc_info[i].qoffset); | |
4914 | } | |
4915 | ||
4916 | /* Assign UP2TC map for the VSI */ | |
4917 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { | |
4918 | /* Get the actual TC# for the UP */ | |
4919 | u8 ets_tc = dcbcfg->etscfg.prioritytable[i]; | |
4920 | /* Get the mapped netdev TC# for the UP */ | |
4921 | netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc; | |
4922 | netdev_set_prio_tc_map(netdev, i, netdev_tc); | |
4923 | } | |
4924 | } | |
4925 | ||
4926 | /** | |
4927 | * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map | |
4928 | * @vsi: the VSI being configured | |
4929 | * @ctxt: the ctxt buffer returned from AQ VSI update param command | |
4930 | **/ | |
4931 | static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi, | |
4932 | struct i40e_vsi_context *ctxt) | |
4933 | { | |
4934 | /* copy just the sections touched not the entire info | |
4935 | * since not all sections are valid as returned by | |
4936 | * update vsi params | |
4937 | */ | |
4938 | vsi->info.mapping_flags = ctxt->info.mapping_flags; | |
4939 | memcpy(&vsi->info.queue_mapping, | |
4940 | &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping)); | |
4941 | memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping, | |
4942 | sizeof(vsi->info.tc_mapping)); | |
4943 | } | |
4944 | ||
4945 | /** | |
4946 | * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map | |
4947 | * @vsi: VSI to be configured | |
4948 | * @enabled_tc: TC bitmap | |
4949 | * | |
4950 | * This configures a particular VSI for TCs that are mapped to the | |
4951 | * given TC bitmap. It uses default bandwidth share for TCs across | |
4952 | * VSIs to configure TC for a particular VSI. | |
4953 | * | |
4954 | * NOTE: | |
4955 | * It is expected that the VSI queues have been quisced before calling | |
4956 | * this function. | |
4957 | **/ | |
4958 | static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
4959 | { | |
4960 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
4961 | struct i40e_vsi_context ctxt; | |
4962 | int ret = 0; | |
4963 | int i; | |
4964 | ||
4965 | /* Check if enabled_tc is same as existing or new TCs */ | |
4966 | if (vsi->tc_config.enabled_tc == enabled_tc) | |
4967 | return ret; | |
4968 | ||
4969 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
4970 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 4971 | if (enabled_tc & BIT(i)) |
41c445ff JB |
4972 | bw_share[i] = 1; |
4973 | } | |
4974 | ||
4975 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
4976 | if (ret) { | |
4977 | dev_info(&vsi->back->pdev->dev, | |
4978 | "Failed configuring TC map %d for VSI %d\n", | |
4979 | enabled_tc, vsi->seid); | |
4980 | goto out; | |
4981 | } | |
4982 | ||
4983 | /* Update Queue Pairs Mapping for currently enabled UPs */ | |
4984 | ctxt.seid = vsi->seid; | |
4985 | ctxt.pf_num = vsi->back->hw.pf_id; | |
4986 | ctxt.vf_num = 0; | |
4987 | ctxt.uplink_seid = vsi->uplink_seid; | |
1a2f6248 | 4988 | ctxt.info = vsi->info; |
41c445ff JB |
4989 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); |
4990 | ||
e3219ce6 ASJ |
4991 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
4992 | ctxt.info.valid_sections |= | |
4993 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
4994 | ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA; | |
4995 | } | |
4996 | ||
41c445ff JB |
4997 | /* Update the VSI after updating the VSI queue-mapping information */ |
4998 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); | |
4999 | if (ret) { | |
5000 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
5001 | "Update vsi tc config failed, err %s aq_err %s\n", |
5002 | i40e_stat_str(&vsi->back->hw, ret), | |
5003 | i40e_aq_str(&vsi->back->hw, | |
5004 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
5005 | goto out; |
5006 | } | |
5007 | /* update the local VSI info with updated queue map */ | |
5008 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
5009 | vsi->info.valid_sections = 0; | |
5010 | ||
5011 | /* Update current VSI BW information */ | |
5012 | ret = i40e_vsi_get_bw_info(vsi); | |
5013 | if (ret) { | |
5014 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
5015 | "Failed updating vsi bw info, err %s aq_err %s\n", |
5016 | i40e_stat_str(&vsi->back->hw, ret), | |
5017 | i40e_aq_str(&vsi->back->hw, | |
5018 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
5019 | goto out; |
5020 | } | |
5021 | ||
5022 | /* Update the netdev TC setup */ | |
5023 | i40e_vsi_config_netdev_tc(vsi, enabled_tc); | |
5024 | out: | |
5025 | return ret; | |
5026 | } | |
5027 | ||
4e3b35b0 NP |
5028 | /** |
5029 | * i40e_veb_config_tc - Configure TCs for given VEB | |
5030 | * @veb: given VEB | |
5031 | * @enabled_tc: TC bitmap | |
5032 | * | |
5033 | * Configures given TC bitmap for VEB (switching) element | |
5034 | **/ | |
5035 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc) | |
5036 | { | |
5037 | struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0}; | |
5038 | struct i40e_pf *pf = veb->pf; | |
5039 | int ret = 0; | |
5040 | int i; | |
5041 | ||
5042 | /* No TCs or already enabled TCs just return */ | |
5043 | if (!enabled_tc || veb->enabled_tc == enabled_tc) | |
5044 | return ret; | |
5045 | ||
5046 | bw_data.tc_valid_bits = enabled_tc; | |
5047 | /* bw_data.absolute_credits is not set (relative) */ | |
5048 | ||
5049 | /* Enable ETS TCs with equal BW Share for now */ | |
5050 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 5051 | if (enabled_tc & BIT(i)) |
4e3b35b0 NP |
5052 | bw_data.tc_bw_share_credits[i] = 1; |
5053 | } | |
5054 | ||
5055 | ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid, | |
5056 | &bw_data, NULL); | |
5057 | if (ret) { | |
5058 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
5059 | "VEB bw config failed, err %s aq_err %s\n", |
5060 | i40e_stat_str(&pf->hw, ret), | |
5061 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5062 | goto out; |
5063 | } | |
5064 | ||
5065 | /* Update the BW information */ | |
5066 | ret = i40e_veb_get_bw_info(veb); | |
5067 | if (ret) { | |
5068 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
5069 | "Failed getting veb bw config, err %s aq_err %s\n", |
5070 | i40e_stat_str(&pf->hw, ret), | |
5071 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5072 | } |
5073 | ||
5074 | out: | |
5075 | return ret; | |
5076 | } | |
5077 | ||
5078 | #ifdef CONFIG_I40E_DCB | |
5079 | /** | |
5080 | * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs | |
5081 | * @pf: PF struct | |
5082 | * | |
5083 | * Reconfigure VEB/VSIs on a given PF; it is assumed that | |
5084 | * the caller would've quiesce all the VSIs before calling | |
5085 | * this function | |
5086 | **/ | |
5087 | static void i40e_dcb_reconfigure(struct i40e_pf *pf) | |
5088 | { | |
5089 | u8 tc_map = 0; | |
5090 | int ret; | |
5091 | u8 v; | |
5092 | ||
5093 | /* Enable the TCs available on PF to all VEBs */ | |
5094 | tc_map = i40e_pf_get_tc_map(pf); | |
5095 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
5096 | if (!pf->veb[v]) | |
5097 | continue; | |
5098 | ret = i40e_veb_config_tc(pf->veb[v], tc_map); | |
5099 | if (ret) { | |
5100 | dev_info(&pf->pdev->dev, | |
5101 | "Failed configuring TC for VEB seid=%d\n", | |
5102 | pf->veb[v]->seid); | |
5103 | /* Will try to configure as many components */ | |
5104 | } | |
5105 | } | |
5106 | ||
5107 | /* Update each VSI */ | |
505682cd | 5108 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
4e3b35b0 NP |
5109 | if (!pf->vsi[v]) |
5110 | continue; | |
5111 | ||
5112 | /* - Enable all TCs for the LAN VSI | |
38e00438 VD |
5113 | #ifdef I40E_FCOE |
5114 | * - For FCoE VSI only enable the TC configured | |
5115 | * as per the APP TLV | |
5116 | #endif | |
4e3b35b0 NP |
5117 | * - For all others keep them at TC0 for now |
5118 | */ | |
5119 | if (v == pf->lan_vsi) | |
5120 | tc_map = i40e_pf_get_tc_map(pf); | |
5121 | else | |
ea6acb7e | 5122 | tc_map = I40E_DEFAULT_TRAFFIC_CLASS; |
38e00438 VD |
5123 | #ifdef I40E_FCOE |
5124 | if (pf->vsi[v]->type == I40E_VSI_FCOE) | |
5125 | tc_map = i40e_get_fcoe_tc_map(pf); | |
5126 | #endif /* #ifdef I40E_FCOE */ | |
4e3b35b0 NP |
5127 | |
5128 | ret = i40e_vsi_config_tc(pf->vsi[v], tc_map); | |
5129 | if (ret) { | |
5130 | dev_info(&pf->pdev->dev, | |
5131 | "Failed configuring TC for VSI seid=%d\n", | |
5132 | pf->vsi[v]->seid); | |
5133 | /* Will try to configure as many components */ | |
5134 | } else { | |
0672a091 NP |
5135 | /* Re-configure VSI vectors based on updated TC map */ |
5136 | i40e_vsi_map_rings_to_vectors(pf->vsi[v]); | |
4e3b35b0 NP |
5137 | if (pf->vsi[v]->netdev) |
5138 | i40e_dcbnl_set_all(pf->vsi[v]); | |
5139 | } | |
5140 | } | |
5141 | } | |
5142 | ||
2fd75f31 NP |
5143 | /** |
5144 | * i40e_resume_port_tx - Resume port Tx | |
5145 | * @pf: PF struct | |
5146 | * | |
5147 | * Resume a port's Tx and issue a PF reset in case of failure to | |
5148 | * resume. | |
5149 | **/ | |
5150 | static int i40e_resume_port_tx(struct i40e_pf *pf) | |
5151 | { | |
5152 | struct i40e_hw *hw = &pf->hw; | |
5153 | int ret; | |
5154 | ||
5155 | ret = i40e_aq_resume_port_tx(hw, NULL); | |
5156 | if (ret) { | |
5157 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
5158 | "Resume Port Tx failed, err %s aq_err %s\n", |
5159 | i40e_stat_str(&pf->hw, ret), | |
5160 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
2fd75f31 NP |
5161 | /* Schedule PF reset to recover */ |
5162 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
5163 | i40e_service_event_schedule(pf); | |
5164 | } | |
5165 | ||
5166 | return ret; | |
5167 | } | |
5168 | ||
4e3b35b0 NP |
5169 | /** |
5170 | * i40e_init_pf_dcb - Initialize DCB configuration | |
5171 | * @pf: PF being configured | |
5172 | * | |
5173 | * Query the current DCB configuration and cache it | |
5174 | * in the hardware structure | |
5175 | **/ | |
5176 | static int i40e_init_pf_dcb(struct i40e_pf *pf) | |
5177 | { | |
5178 | struct i40e_hw *hw = &pf->hw; | |
5179 | int err = 0; | |
5180 | ||
025b4a54 | 5181 | /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */ |
f1bbad33 | 5182 | if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT) |
025b4a54 ASJ |
5183 | goto out; |
5184 | ||
4e3b35b0 NP |
5185 | /* Get the initial DCB configuration */ |
5186 | err = i40e_init_dcb(hw); | |
5187 | if (!err) { | |
5188 | /* Device/Function is not DCBX capable */ | |
5189 | if ((!hw->func_caps.dcb) || | |
5190 | (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) { | |
5191 | dev_info(&pf->pdev->dev, | |
5192 | "DCBX offload is not supported or is disabled for this PF.\n"); | |
5193 | ||
5194 | if (pf->flags & I40E_FLAG_MFP_ENABLED) | |
5195 | goto out; | |
5196 | ||
5197 | } else { | |
5198 | /* When status is not DISABLED then DCBX in FW */ | |
5199 | pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | | |
5200 | DCB_CAP_DCBX_VER_IEEE; | |
4d9b6043 NP |
5201 | |
5202 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
a036244c DE |
5203 | /* Enable DCB tagging only when more than one TC |
5204 | * or explicitly disable if only one TC | |
5205 | */ | |
4d9b6043 NP |
5206 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
5207 | pf->flags |= I40E_FLAG_DCB_ENABLED; | |
a036244c DE |
5208 | else |
5209 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
9fa61dd2 NP |
5210 | dev_dbg(&pf->pdev->dev, |
5211 | "DCBX offload is supported for this PF.\n"); | |
4e3b35b0 | 5212 | } |
014269ff | 5213 | } else { |
aebfc816 | 5214 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5215 | "Query for DCB configuration failed, err %s aq_err %s\n", |
5216 | i40e_stat_str(&pf->hw, err), | |
5217 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5218 | } |
5219 | ||
5220 | out: | |
5221 | return err; | |
5222 | } | |
5223 | #endif /* CONFIG_I40E_DCB */ | |
cf05ed08 JB |
5224 | #define SPEED_SIZE 14 |
5225 | #define FC_SIZE 8 | |
5226 | /** | |
5227 | * i40e_print_link_message - print link up or down | |
5228 | * @vsi: the VSI for which link needs a message | |
5229 | */ | |
c156f856 | 5230 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup) |
cf05ed08 | 5231 | { |
7ec9ba11 | 5232 | enum i40e_aq_link_speed new_speed; |
a9165490 SN |
5233 | char *speed = "Unknown"; |
5234 | char *fc = "Unknown"; | |
cf05ed08 | 5235 | |
7ec9ba11 FS |
5236 | new_speed = vsi->back->hw.phy.link_info.link_speed; |
5237 | ||
5238 | if ((vsi->current_isup == isup) && (vsi->current_speed == new_speed)) | |
c156f856 MJ |
5239 | return; |
5240 | vsi->current_isup = isup; | |
7ec9ba11 | 5241 | vsi->current_speed = new_speed; |
cf05ed08 JB |
5242 | if (!isup) { |
5243 | netdev_info(vsi->netdev, "NIC Link is Down\n"); | |
5244 | return; | |
5245 | } | |
5246 | ||
148c2d80 GR |
5247 | /* Warn user if link speed on NPAR enabled partition is not at |
5248 | * least 10GB | |
5249 | */ | |
5250 | if (vsi->back->hw.func_caps.npar_enable && | |
5251 | (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB || | |
5252 | vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) | |
5253 | netdev_warn(vsi->netdev, | |
5254 | "The partition detected link speed that is less than 10Gbps\n"); | |
5255 | ||
cf05ed08 JB |
5256 | switch (vsi->back->hw.phy.link_info.link_speed) { |
5257 | case I40E_LINK_SPEED_40GB: | |
a9165490 | 5258 | speed = "40 G"; |
cf05ed08 | 5259 | break; |
ae24b409 | 5260 | case I40E_LINK_SPEED_20GB: |
a9165490 | 5261 | speed = "20 G"; |
ae24b409 | 5262 | break; |
cf05ed08 | 5263 | case I40E_LINK_SPEED_10GB: |
a9165490 | 5264 | speed = "10 G"; |
cf05ed08 JB |
5265 | break; |
5266 | case I40E_LINK_SPEED_1GB: | |
a9165490 | 5267 | speed = "1000 M"; |
cf05ed08 | 5268 | break; |
5960d33f | 5269 | case I40E_LINK_SPEED_100MB: |
a9165490 | 5270 | speed = "100 M"; |
5960d33f | 5271 | break; |
cf05ed08 JB |
5272 | default: |
5273 | break; | |
5274 | } | |
5275 | ||
5276 | switch (vsi->back->hw.fc.current_mode) { | |
5277 | case I40E_FC_FULL: | |
a9165490 | 5278 | fc = "RX/TX"; |
cf05ed08 JB |
5279 | break; |
5280 | case I40E_FC_TX_PAUSE: | |
a9165490 | 5281 | fc = "TX"; |
cf05ed08 JB |
5282 | break; |
5283 | case I40E_FC_RX_PAUSE: | |
a9165490 | 5284 | fc = "RX"; |
cf05ed08 JB |
5285 | break; |
5286 | default: | |
a9165490 | 5287 | fc = "None"; |
cf05ed08 JB |
5288 | break; |
5289 | } | |
5290 | ||
a9165490 | 5291 | netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n", |
cf05ed08 JB |
5292 | speed, fc); |
5293 | } | |
4e3b35b0 | 5294 | |
41c445ff JB |
5295 | /** |
5296 | * i40e_up_complete - Finish the last steps of bringing up a connection | |
5297 | * @vsi: the VSI being configured | |
5298 | **/ | |
5299 | static int i40e_up_complete(struct i40e_vsi *vsi) | |
5300 | { | |
5301 | struct i40e_pf *pf = vsi->back; | |
5302 | int err; | |
5303 | ||
5304 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
5305 | i40e_vsi_configure_msix(vsi); | |
5306 | else | |
5307 | i40e_configure_msi_and_legacy(vsi); | |
5308 | ||
5309 | /* start rings */ | |
3aa7b74d | 5310 | err = i40e_vsi_start_rings(vsi); |
41c445ff JB |
5311 | if (err) |
5312 | return err; | |
5313 | ||
5314 | clear_bit(__I40E_DOWN, &vsi->state); | |
5315 | i40e_napi_enable_all(vsi); | |
5316 | i40e_vsi_enable_irq(vsi); | |
5317 | ||
5318 | if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) && | |
5319 | (vsi->netdev)) { | |
cf05ed08 | 5320 | i40e_print_link_message(vsi, true); |
41c445ff JB |
5321 | netif_tx_start_all_queues(vsi->netdev); |
5322 | netif_carrier_on(vsi->netdev); | |
6d779b41 | 5323 | } else if (vsi->netdev) { |
cf05ed08 | 5324 | i40e_print_link_message(vsi, false); |
7b592f61 CW |
5325 | /* need to check for qualified module here*/ |
5326 | if ((pf->hw.phy.link_info.link_info & | |
5327 | I40E_AQ_MEDIA_AVAILABLE) && | |
5328 | (!(pf->hw.phy.link_info.an_info & | |
5329 | I40E_AQ_QUALIFIED_MODULE))) | |
5330 | netdev_err(vsi->netdev, | |
5331 | "the driver failed to link because an unqualified module was detected."); | |
41c445ff | 5332 | } |
ca64fa4e ASJ |
5333 | |
5334 | /* replay FDIR SB filters */ | |
1e1be8f6 ASJ |
5335 | if (vsi->type == I40E_VSI_FDIR) { |
5336 | /* reset fd counters */ | |
5337 | pf->fd_add_err = pf->fd_atr_cnt = 0; | |
5338 | if (pf->fd_tcp_rule > 0) { | |
234dc4e6 | 5339 | pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; |
2e4875e3 ASJ |
5340 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
5341 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n"); | |
1e1be8f6 ASJ |
5342 | pf->fd_tcp_rule = 0; |
5343 | } | |
ca64fa4e | 5344 | i40e_fdir_filter_restore(vsi); |
1e1be8f6 | 5345 | } |
e3219ce6 ASJ |
5346 | |
5347 | /* On the next run of the service_task, notify any clients of the new | |
5348 | * opened netdev | |
5349 | */ | |
5350 | pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED; | |
41c445ff JB |
5351 | i40e_service_event_schedule(pf); |
5352 | ||
5353 | return 0; | |
5354 | } | |
5355 | ||
5356 | /** | |
5357 | * i40e_vsi_reinit_locked - Reset the VSI | |
5358 | * @vsi: the VSI being configured | |
5359 | * | |
5360 | * Rebuild the ring structs after some configuration | |
5361 | * has changed, e.g. MTU size. | |
5362 | **/ | |
5363 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi) | |
5364 | { | |
5365 | struct i40e_pf *pf = vsi->back; | |
5366 | ||
5367 | WARN_ON(in_interrupt()); | |
5368 | while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
5369 | usleep_range(1000, 2000); | |
5370 | i40e_down(vsi); | |
5371 | ||
41c445ff JB |
5372 | i40e_up(vsi); |
5373 | clear_bit(__I40E_CONFIG_BUSY, &pf->state); | |
5374 | } | |
5375 | ||
5376 | /** | |
5377 | * i40e_up - Bring the connection back up after being down | |
5378 | * @vsi: the VSI being configured | |
5379 | **/ | |
5380 | int i40e_up(struct i40e_vsi *vsi) | |
5381 | { | |
5382 | int err; | |
5383 | ||
5384 | err = i40e_vsi_configure(vsi); | |
5385 | if (!err) | |
5386 | err = i40e_up_complete(vsi); | |
5387 | ||
5388 | return err; | |
5389 | } | |
5390 | ||
5391 | /** | |
5392 | * i40e_down - Shutdown the connection processing | |
5393 | * @vsi: the VSI being stopped | |
5394 | **/ | |
5395 | void i40e_down(struct i40e_vsi *vsi) | |
5396 | { | |
5397 | int i; | |
5398 | ||
5399 | /* It is assumed that the caller of this function | |
5400 | * sets the vsi->state __I40E_DOWN bit. | |
5401 | */ | |
5402 | if (vsi->netdev) { | |
5403 | netif_carrier_off(vsi->netdev); | |
5404 | netif_tx_disable(vsi->netdev); | |
5405 | } | |
5406 | i40e_vsi_disable_irq(vsi); | |
3aa7b74d | 5407 | i40e_vsi_stop_rings(vsi); |
41c445ff JB |
5408 | i40e_napi_disable_all(vsi); |
5409 | ||
5410 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b AD |
5411 | i40e_clean_tx_ring(vsi->tx_rings[i]); |
5412 | i40e_clean_rx_ring(vsi->rx_rings[i]); | |
41c445ff | 5413 | } |
f980d445 CS |
5414 | |
5415 | i40e_notify_client_of_netdev_close(vsi, false); | |
5416 | ||
41c445ff JB |
5417 | } |
5418 | ||
5419 | /** | |
5420 | * i40e_setup_tc - configure multiple traffic classes | |
5421 | * @netdev: net device to configure | |
5422 | * @tc: number of traffic classes to enable | |
5423 | **/ | |
5424 | static int i40e_setup_tc(struct net_device *netdev, u8 tc) | |
5425 | { | |
5426 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5427 | struct i40e_vsi *vsi = np->vsi; | |
5428 | struct i40e_pf *pf = vsi->back; | |
5429 | u8 enabled_tc = 0; | |
5430 | int ret = -EINVAL; | |
5431 | int i; | |
5432 | ||
5433 | /* Check if DCB enabled to continue */ | |
5434 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) { | |
5435 | netdev_info(netdev, "DCB is not enabled for adapter\n"); | |
5436 | goto exit; | |
5437 | } | |
5438 | ||
5439 | /* Check if MFP enabled */ | |
5440 | if (pf->flags & I40E_FLAG_MFP_ENABLED) { | |
5441 | netdev_info(netdev, "Configuring TC not supported in MFP mode\n"); | |
5442 | goto exit; | |
5443 | } | |
5444 | ||
5445 | /* Check whether tc count is within enabled limit */ | |
5446 | if (tc > i40e_pf_get_num_tc(pf)) { | |
5447 | netdev_info(netdev, "TC count greater than enabled on link for adapter\n"); | |
5448 | goto exit; | |
5449 | } | |
5450 | ||
5451 | /* Generate TC map for number of tc requested */ | |
5452 | for (i = 0; i < tc; i++) | |
75f5cea9 | 5453 | enabled_tc |= BIT(i); |
41c445ff JB |
5454 | |
5455 | /* Requesting same TC configuration as already enabled */ | |
5456 | if (enabled_tc == vsi->tc_config.enabled_tc) | |
5457 | return 0; | |
5458 | ||
5459 | /* Quiesce VSI queues */ | |
5460 | i40e_quiesce_vsi(vsi); | |
5461 | ||
5462 | /* Configure VSI for enabled TCs */ | |
5463 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
5464 | if (ret) { | |
5465 | netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n", | |
5466 | vsi->seid); | |
5467 | goto exit; | |
5468 | } | |
5469 | ||
5470 | /* Unquiesce VSI */ | |
5471 | i40e_unquiesce_vsi(vsi); | |
5472 | ||
5473 | exit: | |
5474 | return ret; | |
5475 | } | |
5476 | ||
e4c6734e | 5477 | #ifdef I40E_FCOE |
16e5cc64 JF |
5478 | int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, |
5479 | struct tc_to_netdev *tc) | |
e4c6734e | 5480 | #else |
16e5cc64 JF |
5481 | static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, |
5482 | struct tc_to_netdev *tc) | |
e4c6734e JF |
5483 | #endif |
5484 | { | |
16e5cc64 | 5485 | if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO) |
e4c6734e | 5486 | return -EINVAL; |
16e5cc64 | 5487 | return i40e_setup_tc(netdev, tc->tc); |
e4c6734e JF |
5488 | } |
5489 | ||
41c445ff JB |
5490 | /** |
5491 | * i40e_open - Called when a network interface is made active | |
5492 | * @netdev: network interface device structure | |
5493 | * | |
5494 | * The open entry point is called when a network interface is made | |
5495 | * active by the system (IFF_UP). At this point all resources needed | |
5496 | * for transmit and receive operations are allocated, the interrupt | |
5497 | * handler is registered with the OS, the netdev watchdog subtask is | |
5498 | * enabled, and the stack is notified that the interface is ready. | |
5499 | * | |
5500 | * Returns 0 on success, negative value on failure | |
5501 | **/ | |
38e00438 | 5502 | int i40e_open(struct net_device *netdev) |
41c445ff JB |
5503 | { |
5504 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5505 | struct i40e_vsi *vsi = np->vsi; | |
5506 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
5507 | int err; |
5508 | ||
4eb3f768 SN |
5509 | /* disallow open during test or if eeprom is broken */ |
5510 | if (test_bit(__I40E_TESTING, &pf->state) || | |
5511 | test_bit(__I40E_BAD_EEPROM, &pf->state)) | |
41c445ff JB |
5512 | return -EBUSY; |
5513 | ||
5514 | netif_carrier_off(netdev); | |
5515 | ||
6c167f58 EK |
5516 | err = i40e_vsi_open(vsi); |
5517 | if (err) | |
5518 | return err; | |
5519 | ||
059dab69 JB |
5520 | /* configure global TSO hardware offload settings */ |
5521 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH | | |
5522 | TCP_FLAG_FIN) >> 16); | |
5523 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH | | |
5524 | TCP_FLAG_FIN | | |
5525 | TCP_FLAG_CWR) >> 16); | |
5526 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16); | |
5527 | ||
06a5f7f1 | 5528 | udp_tunnel_get_rx_info(netdev); |
e3219ce6 | 5529 | |
6c167f58 EK |
5530 | return 0; |
5531 | } | |
5532 | ||
5533 | /** | |
5534 | * i40e_vsi_open - | |
5535 | * @vsi: the VSI to open | |
5536 | * | |
5537 | * Finish initialization of the VSI. | |
5538 | * | |
5539 | * Returns 0 on success, negative value on failure | |
5540 | **/ | |
5541 | int i40e_vsi_open(struct i40e_vsi *vsi) | |
5542 | { | |
5543 | struct i40e_pf *pf = vsi->back; | |
b294ac70 | 5544 | char int_name[I40E_INT_NAME_STR_LEN]; |
6c167f58 EK |
5545 | int err; |
5546 | ||
41c445ff JB |
5547 | /* allocate descriptors */ |
5548 | err = i40e_vsi_setup_tx_resources(vsi); | |
5549 | if (err) | |
5550 | goto err_setup_tx; | |
5551 | err = i40e_vsi_setup_rx_resources(vsi); | |
5552 | if (err) | |
5553 | goto err_setup_rx; | |
5554 | ||
5555 | err = i40e_vsi_configure(vsi); | |
5556 | if (err) | |
5557 | goto err_setup_rx; | |
5558 | ||
c22e3c6c SN |
5559 | if (vsi->netdev) { |
5560 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s", | |
5561 | dev_driver_string(&pf->pdev->dev), vsi->netdev->name); | |
5562 | err = i40e_vsi_request_irq(vsi, int_name); | |
5563 | if (err) | |
5564 | goto err_setup_rx; | |
41c445ff | 5565 | |
c22e3c6c SN |
5566 | /* Notify the stack of the actual queue counts. */ |
5567 | err = netif_set_real_num_tx_queues(vsi->netdev, | |
5568 | vsi->num_queue_pairs); | |
5569 | if (err) | |
5570 | goto err_set_queues; | |
25946ddb | 5571 | |
c22e3c6c SN |
5572 | err = netif_set_real_num_rx_queues(vsi->netdev, |
5573 | vsi->num_queue_pairs); | |
5574 | if (err) | |
5575 | goto err_set_queues; | |
8a9eb7d3 SN |
5576 | |
5577 | } else if (vsi->type == I40E_VSI_FDIR) { | |
e240f674 | 5578 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir", |
b2008cbf CW |
5579 | dev_driver_string(&pf->pdev->dev), |
5580 | dev_name(&pf->pdev->dev)); | |
8a9eb7d3 | 5581 | err = i40e_vsi_request_irq(vsi, int_name); |
b2008cbf | 5582 | |
c22e3c6c | 5583 | } else { |
ce9ccb17 | 5584 | err = -EINVAL; |
6c167f58 EK |
5585 | goto err_setup_rx; |
5586 | } | |
25946ddb | 5587 | |
41c445ff JB |
5588 | err = i40e_up_complete(vsi); |
5589 | if (err) | |
5590 | goto err_up_complete; | |
5591 | ||
41c445ff JB |
5592 | return 0; |
5593 | ||
5594 | err_up_complete: | |
5595 | i40e_down(vsi); | |
25946ddb | 5596 | err_set_queues: |
41c445ff JB |
5597 | i40e_vsi_free_irq(vsi); |
5598 | err_setup_rx: | |
5599 | i40e_vsi_free_rx_resources(vsi); | |
5600 | err_setup_tx: | |
5601 | i40e_vsi_free_tx_resources(vsi); | |
5602 | if (vsi == pf->vsi[pf->lan_vsi]) | |
41a1d04b | 5603 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); |
41c445ff JB |
5604 | |
5605 | return err; | |
5606 | } | |
5607 | ||
17a73f6b JG |
5608 | /** |
5609 | * i40e_fdir_filter_exit - Cleans up the Flow Director accounting | |
b40c82e6 | 5610 | * @pf: Pointer to PF |
17a73f6b JG |
5611 | * |
5612 | * This function destroys the hlist where all the Flow Director | |
5613 | * filters were saved. | |
5614 | **/ | |
5615 | static void i40e_fdir_filter_exit(struct i40e_pf *pf) | |
5616 | { | |
5617 | struct i40e_fdir_filter *filter; | |
5618 | struct hlist_node *node2; | |
5619 | ||
5620 | hlist_for_each_entry_safe(filter, node2, | |
5621 | &pf->fdir_filter_list, fdir_node) { | |
5622 | hlist_del(&filter->fdir_node); | |
5623 | kfree(filter); | |
5624 | } | |
5625 | pf->fdir_pf_active_filters = 0; | |
5626 | } | |
5627 | ||
41c445ff JB |
5628 | /** |
5629 | * i40e_close - Disables a network interface | |
5630 | * @netdev: network interface device structure | |
5631 | * | |
5632 | * The close entry point is called when an interface is de-activated | |
5633 | * by the OS. The hardware is still under the driver's control, but | |
5634 | * this netdev interface is disabled. | |
5635 | * | |
5636 | * Returns 0, this is not allowed to fail | |
5637 | **/ | |
38e00438 | 5638 | int i40e_close(struct net_device *netdev) |
41c445ff JB |
5639 | { |
5640 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5641 | struct i40e_vsi *vsi = np->vsi; | |
5642 | ||
90ef8d47 | 5643 | i40e_vsi_close(vsi); |
41c445ff JB |
5644 | |
5645 | return 0; | |
5646 | } | |
5647 | ||
5648 | /** | |
5649 | * i40e_do_reset - Start a PF or Core Reset sequence | |
5650 | * @pf: board private structure | |
5651 | * @reset_flags: which reset is requested | |
5652 | * | |
5653 | * The essential difference in resets is that the PF Reset | |
5654 | * doesn't clear the packet buffers, doesn't reset the PE | |
5655 | * firmware, and doesn't bother the other PFs on the chip. | |
5656 | **/ | |
5657 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags) | |
5658 | { | |
5659 | u32 val; | |
5660 | ||
5661 | WARN_ON(in_interrupt()); | |
5662 | ||
263fc48f | 5663 | |
41c445ff | 5664 | /* do the biggest reset indicated */ |
41a1d04b | 5665 | if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { |
41c445ff JB |
5666 | |
5667 | /* Request a Global Reset | |
5668 | * | |
5669 | * This will start the chip's countdown to the actual full | |
5670 | * chip reset event, and a warning interrupt to be sent | |
5671 | * to all PFs, including the requestor. Our handler | |
5672 | * for the warning interrupt will deal with the shutdown | |
5673 | * and recovery of the switch setup. | |
5674 | */ | |
69bfb110 | 5675 | dev_dbg(&pf->pdev->dev, "GlobalR requested\n"); |
41c445ff JB |
5676 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
5677 | val |= I40E_GLGEN_RTRIG_GLOBR_MASK; | |
5678 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
5679 | ||
41a1d04b | 5680 | } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) { |
41c445ff JB |
5681 | |
5682 | /* Request a Core Reset | |
5683 | * | |
5684 | * Same as Global Reset, except does *not* include the MAC/PHY | |
5685 | */ | |
69bfb110 | 5686 | dev_dbg(&pf->pdev->dev, "CoreR requested\n"); |
41c445ff JB |
5687 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
5688 | val |= I40E_GLGEN_RTRIG_CORER_MASK; | |
5689 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
5690 | i40e_flush(&pf->hw); | |
5691 | ||
41a1d04b | 5692 | } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) { |
41c445ff JB |
5693 | |
5694 | /* Request a PF Reset | |
5695 | * | |
5696 | * Resets only the PF-specific registers | |
5697 | * | |
5698 | * This goes directly to the tear-down and rebuild of | |
5699 | * the switch, since we need to do all the recovery as | |
5700 | * for the Core Reset. | |
5701 | */ | |
69bfb110 | 5702 | dev_dbg(&pf->pdev->dev, "PFR requested\n"); |
41c445ff JB |
5703 | i40e_handle_reset_warning(pf); |
5704 | ||
41a1d04b | 5705 | } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) { |
41c445ff JB |
5706 | int v; |
5707 | ||
5708 | /* Find the VSI(s) that requested a re-init */ | |
5709 | dev_info(&pf->pdev->dev, | |
5710 | "VSI reinit requested\n"); | |
505682cd | 5711 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 5712 | struct i40e_vsi *vsi = pf->vsi[v]; |
6995b36c | 5713 | |
41c445ff JB |
5714 | if (vsi != NULL && |
5715 | test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) { | |
5716 | i40e_vsi_reinit_locked(pf->vsi[v]); | |
5717 | clear_bit(__I40E_REINIT_REQUESTED, &vsi->state); | |
5718 | } | |
5719 | } | |
41a1d04b | 5720 | } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) { |
b5d06f05 NP |
5721 | int v; |
5722 | ||
5723 | /* Find the VSI(s) that needs to be brought down */ | |
5724 | dev_info(&pf->pdev->dev, "VSI down requested\n"); | |
5725 | for (v = 0; v < pf->num_alloc_vsi; v++) { | |
5726 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 5727 | |
b5d06f05 NP |
5728 | if (vsi != NULL && |
5729 | test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) { | |
5730 | set_bit(__I40E_DOWN, &vsi->state); | |
5731 | i40e_down(vsi); | |
5732 | clear_bit(__I40E_DOWN_REQUESTED, &vsi->state); | |
5733 | } | |
5734 | } | |
41c445ff JB |
5735 | } else { |
5736 | dev_info(&pf->pdev->dev, | |
5737 | "bad reset request 0x%08x\n", reset_flags); | |
41c445ff JB |
5738 | } |
5739 | } | |
5740 | ||
4e3b35b0 NP |
5741 | #ifdef CONFIG_I40E_DCB |
5742 | /** | |
5743 | * i40e_dcb_need_reconfig - Check if DCB needs reconfig | |
5744 | * @pf: board private structure | |
5745 | * @old_cfg: current DCB config | |
5746 | * @new_cfg: new DCB config | |
5747 | **/ | |
5748 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
5749 | struct i40e_dcbx_config *old_cfg, | |
5750 | struct i40e_dcbx_config *new_cfg) | |
5751 | { | |
5752 | bool need_reconfig = false; | |
5753 | ||
5754 | /* Check if ETS configuration has changed */ | |
5755 | if (memcmp(&new_cfg->etscfg, | |
5756 | &old_cfg->etscfg, | |
5757 | sizeof(new_cfg->etscfg))) { | |
5758 | /* If Priority Table has changed reconfig is needed */ | |
5759 | if (memcmp(&new_cfg->etscfg.prioritytable, | |
5760 | &old_cfg->etscfg.prioritytable, | |
5761 | sizeof(new_cfg->etscfg.prioritytable))) { | |
5762 | need_reconfig = true; | |
69bfb110 | 5763 | dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n"); |
4e3b35b0 NP |
5764 | } |
5765 | ||
5766 | if (memcmp(&new_cfg->etscfg.tcbwtable, | |
5767 | &old_cfg->etscfg.tcbwtable, | |
5768 | sizeof(new_cfg->etscfg.tcbwtable))) | |
69bfb110 | 5769 | dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n"); |
4e3b35b0 NP |
5770 | |
5771 | if (memcmp(&new_cfg->etscfg.tsatable, | |
5772 | &old_cfg->etscfg.tsatable, | |
5773 | sizeof(new_cfg->etscfg.tsatable))) | |
69bfb110 | 5774 | dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n"); |
4e3b35b0 NP |
5775 | } |
5776 | ||
5777 | /* Check if PFC configuration has changed */ | |
5778 | if (memcmp(&new_cfg->pfc, | |
5779 | &old_cfg->pfc, | |
5780 | sizeof(new_cfg->pfc))) { | |
5781 | need_reconfig = true; | |
69bfb110 | 5782 | dev_dbg(&pf->pdev->dev, "PFC config change detected.\n"); |
4e3b35b0 NP |
5783 | } |
5784 | ||
5785 | /* Check if APP Table has changed */ | |
5786 | if (memcmp(&new_cfg->app, | |
5787 | &old_cfg->app, | |
3d9667a9 | 5788 | sizeof(new_cfg->app))) { |
4e3b35b0 | 5789 | need_reconfig = true; |
69bfb110 | 5790 | dev_dbg(&pf->pdev->dev, "APP Table change detected.\n"); |
3d9667a9 | 5791 | } |
4e3b35b0 | 5792 | |
fb43201f | 5793 | dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig); |
4e3b35b0 NP |
5794 | return need_reconfig; |
5795 | } | |
5796 | ||
5797 | /** | |
5798 | * i40e_handle_lldp_event - Handle LLDP Change MIB event | |
5799 | * @pf: board private structure | |
5800 | * @e: event info posted on ARQ | |
5801 | **/ | |
5802 | static int i40e_handle_lldp_event(struct i40e_pf *pf, | |
5803 | struct i40e_arq_event_info *e) | |
5804 | { | |
5805 | struct i40e_aqc_lldp_get_mib *mib = | |
5806 | (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; | |
5807 | struct i40e_hw *hw = &pf->hw; | |
4e3b35b0 NP |
5808 | struct i40e_dcbx_config tmp_dcbx_cfg; |
5809 | bool need_reconfig = false; | |
5810 | int ret = 0; | |
5811 | u8 type; | |
5812 | ||
4d9b6043 | 5813 | /* Not DCB capable or capability disabled */ |
ea6acb7e | 5814 | if (!(pf->flags & I40E_FLAG_DCB_CAPABLE)) |
4d9b6043 NP |
5815 | return ret; |
5816 | ||
4e3b35b0 NP |
5817 | /* Ignore if event is not for Nearest Bridge */ |
5818 | type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) | |
5819 | & I40E_AQ_LLDP_BRIDGE_TYPE_MASK); | |
fb43201f | 5820 | dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type); |
4e3b35b0 NP |
5821 | if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE) |
5822 | return ret; | |
5823 | ||
5824 | /* Check MIB Type and return if event for Remote MIB update */ | |
5825 | type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK; | |
9fa61dd2 | 5826 | dev_dbg(&pf->pdev->dev, |
fb43201f | 5827 | "LLDP event mib type %s\n", type ? "remote" : "local"); |
4e3b35b0 NP |
5828 | if (type == I40E_AQ_LLDP_MIB_REMOTE) { |
5829 | /* Update the remote cached instance and return */ | |
5830 | ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, | |
5831 | I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, | |
5832 | &hw->remote_dcbx_config); | |
5833 | goto exit; | |
5834 | } | |
5835 | ||
9fa61dd2 | 5836 | /* Store the old configuration */ |
1a2f6248 | 5837 | tmp_dcbx_cfg = hw->local_dcbx_config; |
9fa61dd2 | 5838 | |
750fcbcf NP |
5839 | /* Reset the old DCBx configuration data */ |
5840 | memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config)); | |
9fa61dd2 NP |
5841 | /* Get updated DCBX data from firmware */ |
5842 | ret = i40e_get_dcb_config(&pf->hw); | |
4e3b35b0 | 5843 | if (ret) { |
f1c7e72e SN |
5844 | dev_info(&pf->pdev->dev, |
5845 | "Failed querying DCB configuration data from firmware, err %s aq_err %s\n", | |
5846 | i40e_stat_str(&pf->hw, ret), | |
5847 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5848 | goto exit; |
5849 | } | |
5850 | ||
5851 | /* No change detected in DCBX configs */ | |
750fcbcf NP |
5852 | if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config, |
5853 | sizeof(tmp_dcbx_cfg))) { | |
69bfb110 | 5854 | dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n"); |
4e3b35b0 NP |
5855 | goto exit; |
5856 | } | |
5857 | ||
750fcbcf NP |
5858 | need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, |
5859 | &hw->local_dcbx_config); | |
4e3b35b0 | 5860 | |
750fcbcf | 5861 | i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config); |
4e3b35b0 NP |
5862 | |
5863 | if (!need_reconfig) | |
5864 | goto exit; | |
5865 | ||
4d9b6043 | 5866 | /* Enable DCB tagging only when more than one TC */ |
750fcbcf | 5867 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
4d9b6043 NP |
5868 | pf->flags |= I40E_FLAG_DCB_ENABLED; |
5869 | else | |
5870 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
5871 | ||
69129dc3 | 5872 | set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state); |
4e3b35b0 NP |
5873 | /* Reconfiguration needed quiesce all VSIs */ |
5874 | i40e_pf_quiesce_all_vsi(pf); | |
5875 | ||
5876 | /* Changes in configuration update VEB/VSI */ | |
5877 | i40e_dcb_reconfigure(pf); | |
5878 | ||
2fd75f31 NP |
5879 | ret = i40e_resume_port_tx(pf); |
5880 | ||
69129dc3 | 5881 | clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state); |
2fd75f31 | 5882 | /* In case of error no point in resuming VSIs */ |
69129dc3 NP |
5883 | if (ret) |
5884 | goto exit; | |
5885 | ||
3fe06f41 NP |
5886 | /* Wait for the PF's queues to be disabled */ |
5887 | ret = i40e_pf_wait_queues_disabled(pf); | |
11e47708 PN |
5888 | if (ret) { |
5889 | /* Schedule PF reset to recover */ | |
5890 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
5891 | i40e_service_event_schedule(pf); | |
5892 | } else { | |
2fd75f31 | 5893 | i40e_pf_unquiesce_all_vsi(pf); |
85a1aab7 NP |
5894 | /* Notify the client for the DCB changes */ |
5895 | i40e_notify_client_of_l2_param_changes(pf->vsi[pf->lan_vsi]); | |
11e47708 PN |
5896 | } |
5897 | ||
4e3b35b0 NP |
5898 | exit: |
5899 | return ret; | |
5900 | } | |
5901 | #endif /* CONFIG_I40E_DCB */ | |
5902 | ||
23326186 ASJ |
5903 | /** |
5904 | * i40e_do_reset_safe - Protected reset path for userland calls. | |
5905 | * @pf: board private structure | |
5906 | * @reset_flags: which reset is requested | |
5907 | * | |
5908 | **/ | |
5909 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags) | |
5910 | { | |
5911 | rtnl_lock(); | |
5912 | i40e_do_reset(pf, reset_flags); | |
5913 | rtnl_unlock(); | |
5914 | } | |
5915 | ||
41c445ff JB |
5916 | /** |
5917 | * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event | |
5918 | * @pf: board private structure | |
5919 | * @e: event info posted on ARQ | |
5920 | * | |
5921 | * Handler for LAN Queue Overflow Event generated by the firmware for PF | |
5922 | * and VF queues | |
5923 | **/ | |
5924 | static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, | |
5925 | struct i40e_arq_event_info *e) | |
5926 | { | |
5927 | struct i40e_aqc_lan_overflow *data = | |
5928 | (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; | |
5929 | u32 queue = le32_to_cpu(data->prtdcb_rupto); | |
5930 | u32 qtx_ctl = le32_to_cpu(data->otx_ctl); | |
5931 | struct i40e_hw *hw = &pf->hw; | |
5932 | struct i40e_vf *vf; | |
5933 | u16 vf_id; | |
5934 | ||
69bfb110 JB |
5935 | dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", |
5936 | queue, qtx_ctl); | |
41c445ff JB |
5937 | |
5938 | /* Queue belongs to VF, find the VF and issue VF reset */ | |
5939 | if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) | |
5940 | >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { | |
5941 | vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) | |
5942 | >> I40E_QTX_CTL_VFVM_INDX_SHIFT); | |
5943 | vf_id -= hw->func_caps.vf_base_id; | |
5944 | vf = &pf->vf[vf_id]; | |
5945 | i40e_vc_notify_vf_reset(vf); | |
5946 | /* Allow VF to process pending reset notification */ | |
5947 | msleep(20); | |
5948 | i40e_reset_vf(vf, false); | |
5949 | } | |
5950 | } | |
5951 | ||
5952 | /** | |
5953 | * i40e_service_event_complete - Finish up the service event | |
5954 | * @pf: board private structure | |
5955 | **/ | |
5956 | static void i40e_service_event_complete(struct i40e_pf *pf) | |
5957 | { | |
b875f99b | 5958 | WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state)); |
41c445ff JB |
5959 | |
5960 | /* flush memory to make sure state is correct before next watchog */ | |
4e857c58 | 5961 | smp_mb__before_atomic(); |
41c445ff JB |
5962 | clear_bit(__I40E_SERVICE_SCHED, &pf->state); |
5963 | } | |
5964 | ||
55a5e60b | 5965 | /** |
12957388 ASJ |
5966 | * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters |
5967 | * @pf: board private structure | |
5968 | **/ | |
04294e38 | 5969 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf) |
12957388 | 5970 | { |
04294e38 | 5971 | u32 val, fcnt_prog; |
12957388 ASJ |
5972 | |
5973 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); | |
5974 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); | |
5975 | return fcnt_prog; | |
5976 | } | |
5977 | ||
5978 | /** | |
04294e38 | 5979 | * i40e_get_current_fd_count - Get total FD filters programmed for this PF |
55a5e60b ASJ |
5980 | * @pf: board private structure |
5981 | **/ | |
04294e38 | 5982 | u32 i40e_get_current_fd_count(struct i40e_pf *pf) |
55a5e60b | 5983 | { |
04294e38 ASJ |
5984 | u32 val, fcnt_prog; |
5985 | ||
55a5e60b ASJ |
5986 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); |
5987 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + | |
5988 | ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> | |
5989 | I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); | |
5990 | return fcnt_prog; | |
5991 | } | |
1e1be8f6 | 5992 | |
04294e38 ASJ |
5993 | /** |
5994 | * i40e_get_global_fd_count - Get total FD filters programmed on device | |
5995 | * @pf: board private structure | |
5996 | **/ | |
5997 | u32 i40e_get_global_fd_count(struct i40e_pf *pf) | |
5998 | { | |
5999 | u32 val, fcnt_prog; | |
6000 | ||
6001 | val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); | |
6002 | fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + | |
6003 | ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> | |
6004 | I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); | |
6005 | return fcnt_prog; | |
6006 | } | |
6007 | ||
55a5e60b ASJ |
6008 | /** |
6009 | * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled | |
6010 | * @pf: board private structure | |
6011 | **/ | |
6012 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf) | |
6013 | { | |
3487b6c3 | 6014 | struct i40e_fdir_filter *filter; |
55a5e60b | 6015 | u32 fcnt_prog, fcnt_avail; |
3487b6c3 | 6016 | struct hlist_node *node; |
55a5e60b | 6017 | |
1e1be8f6 ASJ |
6018 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) |
6019 | return; | |
6020 | ||
55a5e60b ASJ |
6021 | /* Check if, FD SB or ATR was auto disabled and if there is enough room |
6022 | * to re-enable | |
6023 | */ | |
04294e38 | 6024 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 6025 | fcnt_avail = pf->fdir_pf_filter_count; |
1e1be8f6 ASJ |
6026 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) || |
6027 | (pf->fd_add_err == 0) || | |
6028 | (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) { | |
55a5e60b ASJ |
6029 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
6030 | (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { | |
6031 | pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2e4875e3 ASJ |
6032 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
6033 | dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n"); | |
55a5e60b ASJ |
6034 | } |
6035 | } | |
a3417d28 JK |
6036 | |
6037 | /* Wait for some more space to be available to turn on ATR. We also | |
6038 | * must check that no existing ntuple rules for TCP are in effect | |
6039 | */ | |
55a5e60b ASJ |
6040 | if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) { |
6041 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
a3417d28 JK |
6042 | (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED) && |
6043 | (pf->fd_tcp_rule == 0)) { | |
55a5e60b | 6044 | pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; |
2e4875e3 | 6045 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
a3417d28 | 6046 | dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n"); |
55a5e60b ASJ |
6047 | } |
6048 | } | |
3487b6c3 CW |
6049 | |
6050 | /* if hw had a problem adding a filter, delete it */ | |
6051 | if (pf->fd_inv > 0) { | |
6052 | hlist_for_each_entry_safe(filter, node, | |
6053 | &pf->fdir_filter_list, fdir_node) { | |
6054 | if (filter->fd_id == pf->fd_inv) { | |
6055 | hlist_del(&filter->fdir_node); | |
6056 | kfree(filter); | |
6057 | pf->fdir_pf_active_filters--; | |
6058 | } | |
6059 | } | |
6060 | } | |
55a5e60b ASJ |
6061 | } |
6062 | ||
1e1be8f6 | 6063 | #define I40E_MIN_FD_FLUSH_INTERVAL 10 |
04294e38 | 6064 | #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30 |
1e1be8f6 ASJ |
6065 | /** |
6066 | * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB | |
6067 | * @pf: board private structure | |
6068 | **/ | |
6069 | static void i40e_fdir_flush_and_replay(struct i40e_pf *pf) | |
6070 | { | |
04294e38 | 6071 | unsigned long min_flush_time; |
1e1be8f6 | 6072 | int flush_wait_retry = 50; |
04294e38 ASJ |
6073 | bool disable_atr = false; |
6074 | int fd_room; | |
1e1be8f6 ASJ |
6075 | int reg; |
6076 | ||
a5fdaf34 JB |
6077 | if (!time_after(jiffies, pf->fd_flush_timestamp + |
6078 | (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) | |
6079 | return; | |
04294e38 | 6080 | |
a5fdaf34 JB |
6081 | /* If the flush is happening too quick and we have mostly SB rules we |
6082 | * should not re-enable ATR for some time. | |
6083 | */ | |
6084 | min_flush_time = pf->fd_flush_timestamp + | |
6085 | (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ); | |
6086 | fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters; | |
6087 | ||
6088 | if (!(time_after(jiffies, min_flush_time)) && | |
6089 | (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) { | |
6090 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
6091 | dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n"); | |
6092 | disable_atr = true; | |
6093 | } | |
6094 | ||
6095 | pf->fd_flush_timestamp = jiffies; | |
234dc4e6 | 6096 | pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; |
a5fdaf34 JB |
6097 | /* flush all filters */ |
6098 | wr32(&pf->hw, I40E_PFQF_CTL_1, | |
6099 | I40E_PFQF_CTL_1_CLEARFDTABLE_MASK); | |
6100 | i40e_flush(&pf->hw); | |
6101 | pf->fd_flush_cnt++; | |
6102 | pf->fd_add_err = 0; | |
6103 | do { | |
6104 | /* Check FD flush status every 5-6msec */ | |
6105 | usleep_range(5000, 6000); | |
6106 | reg = rd32(&pf->hw, I40E_PFQF_CTL_1); | |
6107 | if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) | |
6108 | break; | |
6109 | } while (flush_wait_retry--); | |
6110 | if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { | |
6111 | dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n"); | |
6112 | } else { | |
6113 | /* replay sideband filters */ | |
6114 | i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]); | |
6115 | if (!disable_atr) | |
234dc4e6 | 6116 | pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; |
a5fdaf34 JB |
6117 | clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); |
6118 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
6119 | dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n"); | |
1e1be8f6 ASJ |
6120 | } |
6121 | } | |
6122 | ||
6123 | /** | |
6124 | * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed | |
6125 | * @pf: board private structure | |
6126 | **/ | |
04294e38 | 6127 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf) |
1e1be8f6 ASJ |
6128 | { |
6129 | return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; | |
6130 | } | |
6131 | ||
6132 | /* We can see up to 256 filter programming desc in transit if the filters are | |
6133 | * being applied really fast; before we see the first | |
6134 | * filter miss error on Rx queue 0. Accumulating enough error messages before | |
6135 | * reacting will make sure we don't cause flush too often. | |
6136 | */ | |
6137 | #define I40E_MAX_FD_PROGRAM_ERROR 256 | |
6138 | ||
41c445ff JB |
6139 | /** |
6140 | * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table | |
6141 | * @pf: board private structure | |
6142 | **/ | |
6143 | static void i40e_fdir_reinit_subtask(struct i40e_pf *pf) | |
6144 | { | |
41c445ff | 6145 | |
41c445ff JB |
6146 | /* if interface is down do nothing */ |
6147 | if (test_bit(__I40E_DOWN, &pf->state)) | |
6148 | return; | |
1e1be8f6 | 6149 | |
04294e38 | 6150 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) |
1e1be8f6 ASJ |
6151 | i40e_fdir_flush_and_replay(pf); |
6152 | ||
55a5e60b ASJ |
6153 | i40e_fdir_check_and_reenable(pf); |
6154 | ||
41c445ff JB |
6155 | } |
6156 | ||
6157 | /** | |
6158 | * i40e_vsi_link_event - notify VSI of a link event | |
6159 | * @vsi: vsi to be notified | |
6160 | * @link_up: link up or down | |
6161 | **/ | |
6162 | static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up) | |
6163 | { | |
32b5b811 | 6164 | if (!vsi || test_bit(__I40E_DOWN, &vsi->state)) |
41c445ff JB |
6165 | return; |
6166 | ||
6167 | switch (vsi->type) { | |
6168 | case I40E_VSI_MAIN: | |
38e00438 VD |
6169 | #ifdef I40E_FCOE |
6170 | case I40E_VSI_FCOE: | |
6171 | #endif | |
41c445ff JB |
6172 | if (!vsi->netdev || !vsi->netdev_registered) |
6173 | break; | |
6174 | ||
6175 | if (link_up) { | |
6176 | netif_carrier_on(vsi->netdev); | |
6177 | netif_tx_wake_all_queues(vsi->netdev); | |
6178 | } else { | |
6179 | netif_carrier_off(vsi->netdev); | |
6180 | netif_tx_stop_all_queues(vsi->netdev); | |
6181 | } | |
6182 | break; | |
6183 | ||
6184 | case I40E_VSI_SRIOV: | |
41c445ff JB |
6185 | case I40E_VSI_VMDQ2: |
6186 | case I40E_VSI_CTRL: | |
e3219ce6 | 6187 | case I40E_VSI_IWARP: |
41c445ff JB |
6188 | case I40E_VSI_MIRROR: |
6189 | default: | |
6190 | /* there is no notification for other VSIs */ | |
6191 | break; | |
6192 | } | |
6193 | } | |
6194 | ||
6195 | /** | |
6196 | * i40e_veb_link_event - notify elements on the veb of a link event | |
6197 | * @veb: veb to be notified | |
6198 | * @link_up: link up or down | |
6199 | **/ | |
6200 | static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up) | |
6201 | { | |
6202 | struct i40e_pf *pf; | |
6203 | int i; | |
6204 | ||
6205 | if (!veb || !veb->pf) | |
6206 | return; | |
6207 | pf = veb->pf; | |
6208 | ||
6209 | /* depth first... */ | |
6210 | for (i = 0; i < I40E_MAX_VEB; i++) | |
6211 | if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid)) | |
6212 | i40e_veb_link_event(pf->veb[i], link_up); | |
6213 | ||
6214 | /* ... now the local VSIs */ | |
505682cd | 6215 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
6216 | if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid)) |
6217 | i40e_vsi_link_event(pf->vsi[i], link_up); | |
6218 | } | |
6219 | ||
6220 | /** | |
6221 | * i40e_link_event - Update netif_carrier status | |
6222 | * @pf: board private structure | |
6223 | **/ | |
6224 | static void i40e_link_event(struct i40e_pf *pf) | |
6225 | { | |
320684cd | 6226 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
fef59ddf | 6227 | u8 new_link_speed, old_link_speed; |
a72a5abc JB |
6228 | i40e_status status; |
6229 | bool new_link, old_link; | |
41c445ff | 6230 | |
1f9610e4 CS |
6231 | /* save off old link status information */ |
6232 | pf->hw.phy.link_info_old = pf->hw.phy.link_info; | |
6233 | ||
1e701e09 JB |
6234 | /* set this to force the get_link_status call to refresh state */ |
6235 | pf->hw.phy.get_link_info = true; | |
6236 | ||
41c445ff | 6237 | old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP); |
a72a5abc JB |
6238 | |
6239 | status = i40e_get_link_status(&pf->hw, &new_link); | |
6240 | if (status) { | |
6241 | dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n", | |
6242 | status); | |
6243 | return; | |
6244 | } | |
6245 | ||
fef59ddf CS |
6246 | old_link_speed = pf->hw.phy.link_info_old.link_speed; |
6247 | new_link_speed = pf->hw.phy.link_info.link_speed; | |
41c445ff | 6248 | |
1e701e09 | 6249 | if (new_link == old_link && |
fef59ddf | 6250 | new_link_speed == old_link_speed && |
320684cd MW |
6251 | (test_bit(__I40E_DOWN, &vsi->state) || |
6252 | new_link == netif_carrier_ok(vsi->netdev))) | |
41c445ff | 6253 | return; |
320684cd MW |
6254 | |
6255 | if (!test_bit(__I40E_DOWN, &vsi->state)) | |
6256 | i40e_print_link_message(vsi, new_link); | |
41c445ff JB |
6257 | |
6258 | /* Notify the base of the switch tree connected to | |
6259 | * the link. Floating VEBs are not notified. | |
6260 | */ | |
6261 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
6262 | i40e_veb_link_event(pf->veb[pf->lan_veb], new_link); | |
6263 | else | |
320684cd | 6264 | i40e_vsi_link_event(vsi, new_link); |
41c445ff JB |
6265 | |
6266 | if (pf->vf) | |
6267 | i40e_vc_notify_link_state(pf); | |
beb0dff1 JK |
6268 | |
6269 | if (pf->flags & I40E_FLAG_PTP) | |
6270 | i40e_ptp_set_increment(pf); | |
41c445ff JB |
6271 | } |
6272 | ||
41c445ff | 6273 | /** |
21536717 | 6274 | * i40e_watchdog_subtask - periodic checks not using event driven response |
41c445ff JB |
6275 | * @pf: board private structure |
6276 | **/ | |
6277 | static void i40e_watchdog_subtask(struct i40e_pf *pf) | |
6278 | { | |
6279 | int i; | |
6280 | ||
6281 | /* if interface is down do nothing */ | |
6282 | if (test_bit(__I40E_DOWN, &pf->state) || | |
6283 | test_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
6284 | return; | |
6285 | ||
21536717 SN |
6286 | /* make sure we don't do these things too often */ |
6287 | if (time_before(jiffies, (pf->service_timer_previous + | |
6288 | pf->service_timer_period))) | |
6289 | return; | |
6290 | pf->service_timer_previous = jiffies; | |
6291 | ||
9ac77266 SN |
6292 | if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) |
6293 | i40e_link_event(pf); | |
21536717 | 6294 | |
41c445ff JB |
6295 | /* Update the stats for active netdevs so the network stack |
6296 | * can look at updated numbers whenever it cares to | |
6297 | */ | |
505682cd | 6298 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
6299 | if (pf->vsi[i] && pf->vsi[i]->netdev) |
6300 | i40e_update_stats(pf->vsi[i]); | |
6301 | ||
d1a8d275 ASJ |
6302 | if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) { |
6303 | /* Update the stats for the active switching components */ | |
6304 | for (i = 0; i < I40E_MAX_VEB; i++) | |
6305 | if (pf->veb[i]) | |
6306 | i40e_update_veb_stats(pf->veb[i]); | |
6307 | } | |
beb0dff1 JK |
6308 | |
6309 | i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
6310 | } |
6311 | ||
6312 | /** | |
6313 | * i40e_reset_subtask - Set up for resetting the device and driver | |
6314 | * @pf: board private structure | |
6315 | **/ | |
6316 | static void i40e_reset_subtask(struct i40e_pf *pf) | |
6317 | { | |
6318 | u32 reset_flags = 0; | |
6319 | ||
23326186 | 6320 | rtnl_lock(); |
41c445ff | 6321 | if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) { |
75f5cea9 | 6322 | reset_flags |= BIT(__I40E_REINIT_REQUESTED); |
41c445ff JB |
6323 | clear_bit(__I40E_REINIT_REQUESTED, &pf->state); |
6324 | } | |
6325 | if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) { | |
75f5cea9 | 6326 | reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); |
41c445ff JB |
6327 | clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state); |
6328 | } | |
6329 | if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) { | |
75f5cea9 | 6330 | reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); |
41c445ff JB |
6331 | clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state); |
6332 | } | |
6333 | if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) { | |
75f5cea9 | 6334 | reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); |
41c445ff JB |
6335 | clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state); |
6336 | } | |
b5d06f05 | 6337 | if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) { |
75f5cea9 | 6338 | reset_flags |= BIT(__I40E_DOWN_REQUESTED); |
b5d06f05 NP |
6339 | clear_bit(__I40E_DOWN_REQUESTED, &pf->state); |
6340 | } | |
41c445ff JB |
6341 | |
6342 | /* If there's a recovery already waiting, it takes | |
6343 | * precedence before starting a new reset sequence. | |
6344 | */ | |
6345 | if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) { | |
6346 | i40e_handle_reset_warning(pf); | |
23326186 | 6347 | goto unlock; |
41c445ff JB |
6348 | } |
6349 | ||
6350 | /* If we're already down or resetting, just bail */ | |
6351 | if (reset_flags && | |
6352 | !test_bit(__I40E_DOWN, &pf->state) && | |
6353 | !test_bit(__I40E_CONFIG_BUSY, &pf->state)) | |
6354 | i40e_do_reset(pf, reset_flags); | |
23326186 ASJ |
6355 | |
6356 | unlock: | |
6357 | rtnl_unlock(); | |
41c445ff JB |
6358 | } |
6359 | ||
6360 | /** | |
6361 | * i40e_handle_link_event - Handle link event | |
6362 | * @pf: board private structure | |
6363 | * @e: event info posted on ARQ | |
6364 | **/ | |
6365 | static void i40e_handle_link_event(struct i40e_pf *pf, | |
6366 | struct i40e_arq_event_info *e) | |
6367 | { | |
41c445ff JB |
6368 | struct i40e_aqc_get_link_status *status = |
6369 | (struct i40e_aqc_get_link_status *)&e->desc.params.raw; | |
41c445ff | 6370 | |
1e701e09 JB |
6371 | /* Do a new status request to re-enable LSE reporting |
6372 | * and load new status information into the hw struct | |
6373 | * This completely ignores any state information | |
6374 | * in the ARQ event info, instead choosing to always | |
6375 | * issue the AQ update link status command. | |
6376 | */ | |
6377 | i40e_link_event(pf); | |
6378 | ||
7b592f61 CW |
6379 | /* check for unqualified module, if link is down */ |
6380 | if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && | |
6381 | (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && | |
6382 | (!(status->link_info & I40E_AQ_LINK_UP))) | |
6383 | dev_err(&pf->pdev->dev, | |
6384 | "The driver failed to link because an unqualified module was detected.\n"); | |
41c445ff JB |
6385 | } |
6386 | ||
6387 | /** | |
6388 | * i40e_clean_adminq_subtask - Clean the AdminQ rings | |
6389 | * @pf: board private structure | |
6390 | **/ | |
6391 | static void i40e_clean_adminq_subtask(struct i40e_pf *pf) | |
6392 | { | |
6393 | struct i40e_arq_event_info event; | |
6394 | struct i40e_hw *hw = &pf->hw; | |
6395 | u16 pending, i = 0; | |
6396 | i40e_status ret; | |
6397 | u16 opcode; | |
86df242b | 6398 | u32 oldval; |
41c445ff JB |
6399 | u32 val; |
6400 | ||
a316f651 ASJ |
6401 | /* Do not run clean AQ when PF reset fails */ |
6402 | if (test_bit(__I40E_RESET_FAILED, &pf->state)) | |
6403 | return; | |
6404 | ||
86df242b SN |
6405 | /* check for error indications */ |
6406 | val = rd32(&pf->hw, pf->hw.aq.arq.len); | |
6407 | oldval = val; | |
6408 | if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { | |
75eb73c1 MW |
6409 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6410 | dev_info(&pf->pdev->dev, "ARQ VF Error detected\n"); | |
86df242b SN |
6411 | val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; |
6412 | } | |
6413 | if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { | |
75eb73c1 MW |
6414 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6415 | dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n"); | |
86df242b | 6416 | val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; |
1d0a4ada | 6417 | pf->arq_overflows++; |
86df242b SN |
6418 | } |
6419 | if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { | |
75eb73c1 MW |
6420 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6421 | dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n"); | |
86df242b SN |
6422 | val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; |
6423 | } | |
6424 | if (oldval != val) | |
6425 | wr32(&pf->hw, pf->hw.aq.arq.len, val); | |
6426 | ||
6427 | val = rd32(&pf->hw, pf->hw.aq.asq.len); | |
6428 | oldval = val; | |
6429 | if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { | |
75eb73c1 MW |
6430 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6431 | dev_info(&pf->pdev->dev, "ASQ VF Error detected\n"); | |
86df242b SN |
6432 | val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; |
6433 | } | |
6434 | if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { | |
75eb73c1 MW |
6435 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6436 | dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n"); | |
86df242b SN |
6437 | val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; |
6438 | } | |
6439 | if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { | |
75eb73c1 MW |
6440 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6441 | dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n"); | |
86df242b SN |
6442 | val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; |
6443 | } | |
6444 | if (oldval != val) | |
6445 | wr32(&pf->hw, pf->hw.aq.asq.len, val); | |
6446 | ||
1001dc37 MW |
6447 | event.buf_len = I40E_MAX_AQ_BUF_SIZE; |
6448 | event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); | |
41c445ff JB |
6449 | if (!event.msg_buf) |
6450 | return; | |
6451 | ||
6452 | do { | |
6453 | ret = i40e_clean_arq_element(hw, &event, &pending); | |
56497978 | 6454 | if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) |
41c445ff | 6455 | break; |
56497978 | 6456 | else if (ret) { |
41c445ff JB |
6457 | dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret); |
6458 | break; | |
6459 | } | |
6460 | ||
6461 | opcode = le16_to_cpu(event.desc.opcode); | |
6462 | switch (opcode) { | |
6463 | ||
6464 | case i40e_aqc_opc_get_link_status: | |
6465 | i40e_handle_link_event(pf, &event); | |
6466 | break; | |
6467 | case i40e_aqc_opc_send_msg_to_pf: | |
6468 | ret = i40e_vc_process_vf_msg(pf, | |
6469 | le16_to_cpu(event.desc.retval), | |
6470 | le32_to_cpu(event.desc.cookie_high), | |
6471 | le32_to_cpu(event.desc.cookie_low), | |
6472 | event.msg_buf, | |
1001dc37 | 6473 | event.msg_len); |
41c445ff JB |
6474 | break; |
6475 | case i40e_aqc_opc_lldp_update_mib: | |
69bfb110 | 6476 | dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n"); |
4e3b35b0 NP |
6477 | #ifdef CONFIG_I40E_DCB |
6478 | rtnl_lock(); | |
6479 | ret = i40e_handle_lldp_event(pf, &event); | |
6480 | rtnl_unlock(); | |
6481 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
6482 | break; |
6483 | case i40e_aqc_opc_event_lan_overflow: | |
69bfb110 | 6484 | dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n"); |
41c445ff JB |
6485 | i40e_handle_lan_overflow_event(pf, &event); |
6486 | break; | |
0467bc91 SN |
6487 | case i40e_aqc_opc_send_msg_to_peer: |
6488 | dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n"); | |
6489 | break; | |
91a0f930 SN |
6490 | case i40e_aqc_opc_nvm_erase: |
6491 | case i40e_aqc_opc_nvm_update: | |
00ada50d | 6492 | case i40e_aqc_opc_oem_post_update: |
6e93d0c9 SN |
6493 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, |
6494 | "ARQ NVM operation 0x%04x completed\n", | |
6495 | opcode); | |
91a0f930 | 6496 | break; |
41c445ff JB |
6497 | default: |
6498 | dev_info(&pf->pdev->dev, | |
56e5ca68 | 6499 | "ARQ: Unknown event 0x%04x ignored\n", |
0467bc91 | 6500 | opcode); |
41c445ff JB |
6501 | break; |
6502 | } | |
6503 | } while (pending && (i++ < pf->adminq_work_limit)); | |
6504 | ||
6505 | clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); | |
6506 | /* re-enable Admin queue interrupt cause */ | |
6507 | val = rd32(hw, I40E_PFINT_ICR0_ENA); | |
6508 | val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
6509 | wr32(hw, I40E_PFINT_ICR0_ENA, val); | |
6510 | i40e_flush(hw); | |
6511 | ||
6512 | kfree(event.msg_buf); | |
6513 | } | |
6514 | ||
4eb3f768 SN |
6515 | /** |
6516 | * i40e_verify_eeprom - make sure eeprom is good to use | |
6517 | * @pf: board private structure | |
6518 | **/ | |
6519 | static void i40e_verify_eeprom(struct i40e_pf *pf) | |
6520 | { | |
6521 | int err; | |
6522 | ||
6523 | err = i40e_diag_eeprom_test(&pf->hw); | |
6524 | if (err) { | |
6525 | /* retry in case of garbage read */ | |
6526 | err = i40e_diag_eeprom_test(&pf->hw); | |
6527 | if (err) { | |
6528 | dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n", | |
6529 | err); | |
6530 | set_bit(__I40E_BAD_EEPROM, &pf->state); | |
6531 | } | |
6532 | } | |
6533 | ||
6534 | if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) { | |
6535 | dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n"); | |
6536 | clear_bit(__I40E_BAD_EEPROM, &pf->state); | |
6537 | } | |
6538 | } | |
6539 | ||
386a0afa AA |
6540 | /** |
6541 | * i40e_enable_pf_switch_lb | |
b40c82e6 | 6542 | * @pf: pointer to the PF structure |
386a0afa AA |
6543 | * |
6544 | * enable switch loop back or die - no point in a return value | |
6545 | **/ | |
6546 | static void i40e_enable_pf_switch_lb(struct i40e_pf *pf) | |
6547 | { | |
6548 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
6549 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 6550 | int ret; |
386a0afa AA |
6551 | |
6552 | ctxt.seid = pf->main_vsi_seid; | |
6553 | ctxt.pf_num = pf->hw.pf_id; | |
6554 | ctxt.vf_num = 0; | |
f1c7e72e SN |
6555 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
6556 | if (ret) { | |
386a0afa | 6557 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6558 | "couldn't get PF vsi config, err %s aq_err %s\n", |
6559 | i40e_stat_str(&pf->hw, ret), | |
6560 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6561 | return; |
6562 | } | |
6563 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
6564 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
6565 | ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
6566 | ||
f1c7e72e SN |
6567 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
6568 | if (ret) { | |
386a0afa | 6569 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6570 | "update vsi switch failed, err %s aq_err %s\n", |
6571 | i40e_stat_str(&pf->hw, ret), | |
6572 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6573 | } |
6574 | } | |
6575 | ||
6576 | /** | |
6577 | * i40e_disable_pf_switch_lb | |
b40c82e6 | 6578 | * @pf: pointer to the PF structure |
386a0afa AA |
6579 | * |
6580 | * disable switch loop back or die - no point in a return value | |
6581 | **/ | |
6582 | static void i40e_disable_pf_switch_lb(struct i40e_pf *pf) | |
6583 | { | |
6584 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
6585 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 6586 | int ret; |
386a0afa AA |
6587 | |
6588 | ctxt.seid = pf->main_vsi_seid; | |
6589 | ctxt.pf_num = pf->hw.pf_id; | |
6590 | ctxt.vf_num = 0; | |
f1c7e72e SN |
6591 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
6592 | if (ret) { | |
386a0afa | 6593 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6594 | "couldn't get PF vsi config, err %s aq_err %s\n", |
6595 | i40e_stat_str(&pf->hw, ret), | |
6596 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6597 | return; |
6598 | } | |
6599 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
6600 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
6601 | ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
6602 | ||
f1c7e72e SN |
6603 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
6604 | if (ret) { | |
386a0afa | 6605 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6606 | "update vsi switch failed, err %s aq_err %s\n", |
6607 | i40e_stat_str(&pf->hw, ret), | |
6608 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6609 | } |
6610 | } | |
6611 | ||
51616018 NP |
6612 | /** |
6613 | * i40e_config_bridge_mode - Configure the HW bridge mode | |
6614 | * @veb: pointer to the bridge instance | |
6615 | * | |
6616 | * Configure the loop back mode for the LAN VSI that is downlink to the | |
6617 | * specified HW bridge instance. It is expected this function is called | |
6618 | * when a new HW bridge is instantiated. | |
6619 | **/ | |
6620 | static void i40e_config_bridge_mode(struct i40e_veb *veb) | |
6621 | { | |
6622 | struct i40e_pf *pf = veb->pf; | |
6623 | ||
6dec1017 SN |
6624 | if (pf->hw.debug_mask & I40E_DEBUG_LAN) |
6625 | dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n", | |
6626 | veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
51616018 NP |
6627 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) |
6628 | i40e_disable_pf_switch_lb(pf); | |
6629 | else | |
6630 | i40e_enable_pf_switch_lb(pf); | |
6631 | } | |
6632 | ||
41c445ff JB |
6633 | /** |
6634 | * i40e_reconstitute_veb - rebuild the VEB and anything connected to it | |
6635 | * @veb: pointer to the VEB instance | |
6636 | * | |
6637 | * This is a recursive function that first builds the attached VSIs then | |
6638 | * recurses in to build the next layer of VEB. We track the connections | |
6639 | * through our own index numbers because the seid's from the HW could | |
6640 | * change across the reset. | |
6641 | **/ | |
6642 | static int i40e_reconstitute_veb(struct i40e_veb *veb) | |
6643 | { | |
6644 | struct i40e_vsi *ctl_vsi = NULL; | |
6645 | struct i40e_pf *pf = veb->pf; | |
6646 | int v, veb_idx; | |
6647 | int ret; | |
6648 | ||
6649 | /* build VSI that owns this VEB, temporarily attached to base VEB */ | |
505682cd | 6650 | for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) { |
41c445ff JB |
6651 | if (pf->vsi[v] && |
6652 | pf->vsi[v]->veb_idx == veb->idx && | |
6653 | pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
6654 | ctl_vsi = pf->vsi[v]; | |
6655 | break; | |
6656 | } | |
6657 | } | |
6658 | if (!ctl_vsi) { | |
6659 | dev_info(&pf->pdev->dev, | |
6660 | "missing owner VSI for veb_idx %d\n", veb->idx); | |
6661 | ret = -ENOENT; | |
6662 | goto end_reconstitute; | |
6663 | } | |
6664 | if (ctl_vsi != pf->vsi[pf->lan_vsi]) | |
6665 | ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
6666 | ret = i40e_add_vsi(ctl_vsi); | |
6667 | if (ret) { | |
6668 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6669 | "rebuild of veb_idx %d owner VSI failed: %d\n", |
6670 | veb->idx, ret); | |
41c445ff JB |
6671 | goto end_reconstitute; |
6672 | } | |
6673 | i40e_vsi_reset_stats(ctl_vsi); | |
6674 | ||
6675 | /* create the VEB in the switch and move the VSI onto the VEB */ | |
6676 | ret = i40e_add_veb(veb, ctl_vsi); | |
6677 | if (ret) | |
6678 | goto end_reconstitute; | |
6679 | ||
fc60861e ASJ |
6680 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
6681 | veb->bridge_mode = BRIDGE_MODE_VEB; | |
6682 | else | |
6683 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
51616018 | 6684 | i40e_config_bridge_mode(veb); |
b64ba084 | 6685 | |
41c445ff | 6686 | /* create the remaining VSIs attached to this VEB */ |
505682cd | 6687 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
6688 | if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi) |
6689 | continue; | |
6690 | ||
6691 | if (pf->vsi[v]->veb_idx == veb->idx) { | |
6692 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 6693 | |
41c445ff JB |
6694 | vsi->uplink_seid = veb->seid; |
6695 | ret = i40e_add_vsi(vsi); | |
6696 | if (ret) { | |
6697 | dev_info(&pf->pdev->dev, | |
6698 | "rebuild of vsi_idx %d failed: %d\n", | |
6699 | v, ret); | |
6700 | goto end_reconstitute; | |
6701 | } | |
6702 | i40e_vsi_reset_stats(vsi); | |
6703 | } | |
6704 | } | |
6705 | ||
6706 | /* create any VEBs attached to this VEB - RECURSION */ | |
6707 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
6708 | if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) { | |
6709 | pf->veb[veb_idx]->uplink_seid = veb->seid; | |
6710 | ret = i40e_reconstitute_veb(pf->veb[veb_idx]); | |
6711 | if (ret) | |
6712 | break; | |
6713 | } | |
6714 | } | |
6715 | ||
6716 | end_reconstitute: | |
6717 | return ret; | |
6718 | } | |
6719 | ||
6720 | /** | |
6721 | * i40e_get_capabilities - get info about the HW | |
6722 | * @pf: the PF struct | |
6723 | **/ | |
6724 | static int i40e_get_capabilities(struct i40e_pf *pf) | |
6725 | { | |
6726 | struct i40e_aqc_list_capabilities_element_resp *cap_buf; | |
6727 | u16 data_size; | |
6728 | int buf_len; | |
6729 | int err; | |
6730 | ||
6731 | buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); | |
6732 | do { | |
6733 | cap_buf = kzalloc(buf_len, GFP_KERNEL); | |
6734 | if (!cap_buf) | |
6735 | return -ENOMEM; | |
6736 | ||
6737 | /* this loads the data into the hw struct for us */ | |
6738 | err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len, | |
6739 | &data_size, | |
6740 | i40e_aqc_opc_list_func_capabilities, | |
6741 | NULL); | |
6742 | /* data loaded, buffer no longer needed */ | |
6743 | kfree(cap_buf); | |
6744 | ||
6745 | if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { | |
6746 | /* retry with a larger buffer */ | |
6747 | buf_len = data_size; | |
6748 | } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { | |
6749 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6750 | "capability discovery failed, err %s aq_err %s\n", |
6751 | i40e_stat_str(&pf->hw, err), | |
6752 | i40e_aq_str(&pf->hw, | |
6753 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
6754 | return -ENODEV; |
6755 | } | |
6756 | } while (err); | |
6757 | ||
6758 | if (pf->hw.debug_mask & I40E_DEBUG_USER) | |
6759 | dev_info(&pf->pdev->dev, | |
6760 | "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n", | |
6761 | pf->hw.pf_id, pf->hw.func_caps.num_vfs, | |
6762 | pf->hw.func_caps.num_msix_vectors, | |
6763 | pf->hw.func_caps.num_msix_vectors_vf, | |
6764 | pf->hw.func_caps.fd_filters_guaranteed, | |
6765 | pf->hw.func_caps.fd_filters_best_effort, | |
6766 | pf->hw.func_caps.num_tx_qp, | |
6767 | pf->hw.func_caps.num_vsis); | |
6768 | ||
7134f9ce JB |
6769 | #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \ |
6770 | + pf->hw.func_caps.num_vfs) | |
6771 | if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) { | |
6772 | dev_info(&pf->pdev->dev, | |
6773 | "got num_vsis %d, setting num_vsis to %d\n", | |
6774 | pf->hw.func_caps.num_vsis, DEF_NUM_VSI); | |
6775 | pf->hw.func_caps.num_vsis = DEF_NUM_VSI; | |
6776 | } | |
6777 | ||
41c445ff JB |
6778 | return 0; |
6779 | } | |
6780 | ||
cbf61325 ASJ |
6781 | static int i40e_vsi_clear(struct i40e_vsi *vsi); |
6782 | ||
41c445ff | 6783 | /** |
cbf61325 | 6784 | * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband |
41c445ff JB |
6785 | * @pf: board private structure |
6786 | **/ | |
cbf61325 | 6787 | static void i40e_fdir_sb_setup(struct i40e_pf *pf) |
41c445ff JB |
6788 | { |
6789 | struct i40e_vsi *vsi; | |
41c445ff | 6790 | |
407e063c JB |
6791 | /* quick workaround for an NVM issue that leaves a critical register |
6792 | * uninitialized | |
6793 | */ | |
6794 | if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) { | |
6795 | static const u32 hkey[] = { | |
6796 | 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36, | |
6797 | 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb, | |
6798 | 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21, | |
6799 | 0x95b3a76d}; | |
4b816446 | 6800 | int i; |
407e063c JB |
6801 | |
6802 | for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++) | |
6803 | wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]); | |
6804 | } | |
6805 | ||
cbf61325 | 6806 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
41c445ff JB |
6807 | return; |
6808 | ||
cbf61325 | 6809 | /* find existing VSI and see if it needs configuring */ |
4b816446 | 6810 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
cbf61325 ASJ |
6811 | |
6812 | /* create a new VSI if none exists */ | |
41c445ff | 6813 | if (!vsi) { |
cbf61325 ASJ |
6814 | vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, |
6815 | pf->vsi[pf->lan_vsi]->seid, 0); | |
41c445ff JB |
6816 | if (!vsi) { |
6817 | dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n"); | |
8a9eb7d3 SN |
6818 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
6819 | return; | |
41c445ff | 6820 | } |
cbf61325 | 6821 | } |
41c445ff | 6822 | |
8a9eb7d3 | 6823 | i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring); |
41c445ff JB |
6824 | } |
6825 | ||
6826 | /** | |
6827 | * i40e_fdir_teardown - release the Flow Director resources | |
6828 | * @pf: board private structure | |
6829 | **/ | |
6830 | static void i40e_fdir_teardown(struct i40e_pf *pf) | |
6831 | { | |
4b816446 | 6832 | struct i40e_vsi *vsi; |
41c445ff | 6833 | |
17a73f6b | 6834 | i40e_fdir_filter_exit(pf); |
4b816446 AD |
6835 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
6836 | if (vsi) | |
6837 | i40e_vsi_release(vsi); | |
41c445ff JB |
6838 | } |
6839 | ||
6840 | /** | |
f650a38b | 6841 | * i40e_prep_for_reset - prep for the core to reset |
41c445ff JB |
6842 | * @pf: board private structure |
6843 | * | |
b40c82e6 | 6844 | * Close up the VFs and other things in prep for PF Reset. |
f650a38b | 6845 | **/ |
23cfbe07 | 6846 | static void i40e_prep_for_reset(struct i40e_pf *pf) |
41c445ff | 6847 | { |
41c445ff | 6848 | struct i40e_hw *hw = &pf->hw; |
60442dea | 6849 | i40e_status ret = 0; |
41c445ff JB |
6850 | u32 v; |
6851 | ||
6852 | clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state); | |
6853 | if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) | |
23cfbe07 | 6854 | return; |
d3ce5734 MW |
6855 | if (i40e_check_asq_alive(&pf->hw)) |
6856 | i40e_vc_notify_reset(pf); | |
41c445ff | 6857 | |
69bfb110 | 6858 | dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n"); |
41c445ff | 6859 | |
41c445ff JB |
6860 | /* quiesce the VSIs and their queues that are not already DOWN */ |
6861 | i40e_pf_quiesce_all_vsi(pf); | |
6862 | ||
505682cd | 6863 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
6864 | if (pf->vsi[v]) |
6865 | pf->vsi[v]->seid = 0; | |
6866 | } | |
6867 | ||
6868 | i40e_shutdown_adminq(&pf->hw); | |
6869 | ||
f650a38b | 6870 | /* call shutdown HMC */ |
60442dea SN |
6871 | if (hw->hmc.hmc_obj) { |
6872 | ret = i40e_shutdown_lan_hmc(hw); | |
23cfbe07 | 6873 | if (ret) |
60442dea SN |
6874 | dev_warn(&pf->pdev->dev, |
6875 | "shutdown_lan_hmc failed: %d\n", ret); | |
f650a38b | 6876 | } |
f650a38b ASJ |
6877 | } |
6878 | ||
44033fac JB |
6879 | /** |
6880 | * i40e_send_version - update firmware with driver version | |
6881 | * @pf: PF struct | |
6882 | */ | |
6883 | static void i40e_send_version(struct i40e_pf *pf) | |
6884 | { | |
6885 | struct i40e_driver_version dv; | |
6886 | ||
6887 | dv.major_version = DRV_VERSION_MAJOR; | |
6888 | dv.minor_version = DRV_VERSION_MINOR; | |
6889 | dv.build_version = DRV_VERSION_BUILD; | |
6890 | dv.subbuild_version = 0; | |
35a7d804 | 6891 | strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string)); |
44033fac JB |
6892 | i40e_aq_send_driver_version(&pf->hw, &dv, NULL); |
6893 | } | |
6894 | ||
f650a38b | 6895 | /** |
4dda12e6 | 6896 | * i40e_reset_and_rebuild - reset and rebuild using a saved config |
f650a38b | 6897 | * @pf: board private structure |
bc7d338f | 6898 | * @reinit: if the Main VSI needs to re-initialized. |
f650a38b | 6899 | **/ |
bc7d338f | 6900 | static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit) |
f650a38b | 6901 | { |
f650a38b | 6902 | struct i40e_hw *hw = &pf->hw; |
cafa2ee6 | 6903 | u8 set_fc_aq_fail = 0; |
f650a38b | 6904 | i40e_status ret; |
4f2f017c | 6905 | u32 val; |
f650a38b ASJ |
6906 | u32 v; |
6907 | ||
41c445ff JB |
6908 | /* Now we wait for GRST to settle out. |
6909 | * We don't have to delete the VEBs or VSIs from the hw switch | |
6910 | * because the reset will make them disappear. | |
6911 | */ | |
6912 | ret = i40e_pf_reset(hw); | |
b5565400 | 6913 | if (ret) { |
41c445ff | 6914 | dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret); |
a316f651 ASJ |
6915 | set_bit(__I40E_RESET_FAILED, &pf->state); |
6916 | goto clear_recovery; | |
b5565400 | 6917 | } |
41c445ff JB |
6918 | pf->pfr_count++; |
6919 | ||
6920 | if (test_bit(__I40E_DOWN, &pf->state)) | |
a316f651 | 6921 | goto clear_recovery; |
69bfb110 | 6922 | dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n"); |
41c445ff JB |
6923 | |
6924 | /* rebuild the basics for the AdminQ, HMC, and initial HW switch */ | |
6925 | ret = i40e_init_adminq(&pf->hw); | |
6926 | if (ret) { | |
f1c7e72e SN |
6927 | dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n", |
6928 | i40e_stat_str(&pf->hw, ret), | |
6929 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
a316f651 | 6930 | goto clear_recovery; |
41c445ff JB |
6931 | } |
6932 | ||
4eb3f768 | 6933 | /* re-verify the eeprom if we just had an EMP reset */ |
9df42d1a | 6934 | if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state)) |
4eb3f768 | 6935 | i40e_verify_eeprom(pf); |
4eb3f768 | 6936 | |
e78ac4bf | 6937 | i40e_clear_pxe_mode(hw); |
41c445ff | 6938 | ret = i40e_get_capabilities(pf); |
f1c7e72e | 6939 | if (ret) |
41c445ff | 6940 | goto end_core_reset; |
41c445ff | 6941 | |
41c445ff JB |
6942 | ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
6943 | hw->func_caps.num_rx_qp, | |
6944 | pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num); | |
6945 | if (ret) { | |
6946 | dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret); | |
6947 | goto end_core_reset; | |
6948 | } | |
6949 | ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
6950 | if (ret) { | |
6951 | dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret); | |
6952 | goto end_core_reset; | |
6953 | } | |
6954 | ||
4e3b35b0 NP |
6955 | #ifdef CONFIG_I40E_DCB |
6956 | ret = i40e_init_pf_dcb(pf); | |
6957 | if (ret) { | |
aebfc816 SN |
6958 | dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret); |
6959 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; | |
6960 | /* Continue without DCB enabled */ | |
4e3b35b0 NP |
6961 | } |
6962 | #endif /* CONFIG_I40E_DCB */ | |
38e00438 | 6963 | #ifdef I40E_FCOE |
21364bcf | 6964 | i40e_init_pf_fcoe(pf); |
4e3b35b0 | 6965 | |
38e00438 | 6966 | #endif |
41c445ff | 6967 | /* do basic switch setup */ |
bc7d338f | 6968 | ret = i40e_setup_pf_switch(pf, reinit); |
41c445ff JB |
6969 | if (ret) |
6970 | goto end_core_reset; | |
6971 | ||
2f0aff41 SN |
6972 | /* The driver only wants link up/down and module qualification |
6973 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
6974 | */ |
6975 | ret = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 6976 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 6977 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 6978 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 6979 | if (ret) |
f1c7e72e SN |
6980 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
6981 | i40e_stat_str(&pf->hw, ret), | |
6982 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 6983 | |
cafa2ee6 ASJ |
6984 | /* make sure our flow control settings are restored */ |
6985 | ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true); | |
6986 | if (ret) | |
8279e495 NP |
6987 | dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n", |
6988 | i40e_stat_str(&pf->hw, ret), | |
6989 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 6990 | |
41c445ff JB |
6991 | /* Rebuild the VSIs and VEBs that existed before reset. |
6992 | * They are still in our local switch element arrays, so only | |
6993 | * need to rebuild the switch model in the HW. | |
6994 | * | |
6995 | * If there were VEBs but the reconstitution failed, we'll try | |
6996 | * try to recover minimal use by getting the basic PF VSI working. | |
6997 | */ | |
6998 | if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) { | |
69bfb110 | 6999 | dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n"); |
41c445ff JB |
7000 | /* find the one VEB connected to the MAC, and find orphans */ |
7001 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
7002 | if (!pf->veb[v]) | |
7003 | continue; | |
7004 | ||
7005 | if (pf->veb[v]->uplink_seid == pf->mac_seid || | |
7006 | pf->veb[v]->uplink_seid == 0) { | |
7007 | ret = i40e_reconstitute_veb(pf->veb[v]); | |
7008 | ||
7009 | if (!ret) | |
7010 | continue; | |
7011 | ||
7012 | /* If Main VEB failed, we're in deep doodoo, | |
7013 | * so give up rebuilding the switch and set up | |
7014 | * for minimal rebuild of PF VSI. | |
7015 | * If orphan failed, we'll report the error | |
7016 | * but try to keep going. | |
7017 | */ | |
7018 | if (pf->veb[v]->uplink_seid == pf->mac_seid) { | |
7019 | dev_info(&pf->pdev->dev, | |
7020 | "rebuild of switch failed: %d, will try to set up simple PF connection\n", | |
7021 | ret); | |
7022 | pf->vsi[pf->lan_vsi]->uplink_seid | |
7023 | = pf->mac_seid; | |
7024 | break; | |
7025 | } else if (pf->veb[v]->uplink_seid == 0) { | |
7026 | dev_info(&pf->pdev->dev, | |
7027 | "rebuild of orphan VEB failed: %d\n", | |
7028 | ret); | |
7029 | } | |
7030 | } | |
7031 | } | |
7032 | } | |
7033 | ||
7034 | if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) { | |
cde4cbc7 | 7035 | dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n"); |
41c445ff JB |
7036 | /* no VEB, so rebuild only the Main VSI */ |
7037 | ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]); | |
7038 | if (ret) { | |
7039 | dev_info(&pf->pdev->dev, | |
7040 | "rebuild of Main VSI failed: %d\n", ret); | |
7041 | goto end_core_reset; | |
7042 | } | |
7043 | } | |
7044 | ||
4f2f017c ASJ |
7045 | /* Reconfigure hardware for allowing smaller MSS in the case |
7046 | * of TSO, so that we avoid the MDD being fired and causing | |
7047 | * a reset in the case of small MSS+TSO. | |
7048 | */ | |
7049 | #define I40E_REG_MSS 0x000E64DC | |
7050 | #define I40E_REG_MSS_MIN_MASK 0x3FF0000 | |
7051 | #define I40E_64BYTE_MSS 0x400000 | |
7052 | val = rd32(hw, I40E_REG_MSS); | |
7053 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
7054 | val &= ~I40E_REG_MSS_MIN_MASK; | |
7055 | val |= I40E_64BYTE_MSS; | |
7056 | wr32(hw, I40E_REG_MSS, val); | |
7057 | } | |
7058 | ||
8eed76fa | 7059 | if (pf->flags & I40E_FLAG_RESTART_AUTONEG) { |
025b4a54 ASJ |
7060 | msleep(75); |
7061 | ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
7062 | if (ret) | |
f1c7e72e SN |
7063 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
7064 | i40e_stat_str(&pf->hw, ret), | |
7065 | i40e_aq_str(&pf->hw, | |
7066 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 7067 | } |
41c445ff JB |
7068 | /* reinit the misc interrupt */ |
7069 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7070 | ret = i40e_setup_misc_vector(pf); | |
7071 | ||
e7358f54 ASJ |
7072 | /* Add a filter to drop all Flow control frames from any VSI from being |
7073 | * transmitted. By doing so we stop a malicious VF from sending out | |
7074 | * PAUSE or PFC frames and potentially controlling traffic for other | |
7075 | * PF/VF VSIs. | |
7076 | * The FW can still send Flow control frames if enabled. | |
7077 | */ | |
7078 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
7079 | pf->main_vsi_seid); | |
7080 | ||
41c445ff JB |
7081 | /* restart the VSIs that were rebuilt and running before the reset */ |
7082 | i40e_pf_unquiesce_all_vsi(pf); | |
7083 | ||
69f64b2b MW |
7084 | if (pf->num_alloc_vfs) { |
7085 | for (v = 0; v < pf->num_alloc_vfs; v++) | |
7086 | i40e_reset_vf(&pf->vf[v], true); | |
7087 | } | |
7088 | ||
41c445ff | 7089 | /* tell the firmware that we're starting */ |
44033fac | 7090 | i40e_send_version(pf); |
41c445ff JB |
7091 | |
7092 | end_core_reset: | |
a316f651 ASJ |
7093 | clear_bit(__I40E_RESET_FAILED, &pf->state); |
7094 | clear_recovery: | |
41c445ff JB |
7095 | clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state); |
7096 | } | |
7097 | ||
f650a38b | 7098 | /** |
b40c82e6 | 7099 | * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild |
f650a38b ASJ |
7100 | * @pf: board private structure |
7101 | * | |
7102 | * Close up the VFs and other things in prep for a Core Reset, | |
7103 | * then get ready to rebuild the world. | |
7104 | **/ | |
7105 | static void i40e_handle_reset_warning(struct i40e_pf *pf) | |
7106 | { | |
23cfbe07 SN |
7107 | i40e_prep_for_reset(pf); |
7108 | i40e_reset_and_rebuild(pf, false); | |
f650a38b ASJ |
7109 | } |
7110 | ||
41c445ff JB |
7111 | /** |
7112 | * i40e_handle_mdd_event | |
b40c82e6 | 7113 | * @pf: pointer to the PF structure |
41c445ff JB |
7114 | * |
7115 | * Called from the MDD irq handler to identify possibly malicious vfs | |
7116 | **/ | |
7117 | static void i40e_handle_mdd_event(struct i40e_pf *pf) | |
7118 | { | |
7119 | struct i40e_hw *hw = &pf->hw; | |
7120 | bool mdd_detected = false; | |
df430b12 | 7121 | bool pf_mdd_detected = false; |
41c445ff JB |
7122 | struct i40e_vf *vf; |
7123 | u32 reg; | |
7124 | int i; | |
7125 | ||
7126 | if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state)) | |
7127 | return; | |
7128 | ||
7129 | /* find what triggered the MDD event */ | |
7130 | reg = rd32(hw, I40E_GL_MDET_TX); | |
7131 | if (reg & I40E_GL_MDET_TX_VALID_MASK) { | |
4c33f83a ASJ |
7132 | u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> |
7133 | I40E_GL_MDET_TX_PF_NUM_SHIFT; | |
2089ad03 | 7134 | u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> |
4c33f83a | 7135 | I40E_GL_MDET_TX_VF_NUM_SHIFT; |
013f6579 | 7136 | u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> |
4c33f83a | 7137 | I40E_GL_MDET_TX_EVENT_SHIFT; |
2089ad03 MW |
7138 | u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> |
7139 | I40E_GL_MDET_TX_QUEUE_SHIFT) - | |
7140 | pf->hw.func_caps.base_queue; | |
faf32978 | 7141 | if (netif_msg_tx_err(pf)) |
b40c82e6 | 7142 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", |
faf32978 | 7143 | event, queue, pf_num, vf_num); |
41c445ff JB |
7144 | wr32(hw, I40E_GL_MDET_TX, 0xffffffff); |
7145 | mdd_detected = true; | |
7146 | } | |
7147 | reg = rd32(hw, I40E_GL_MDET_RX); | |
7148 | if (reg & I40E_GL_MDET_RX_VALID_MASK) { | |
4c33f83a ASJ |
7149 | u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> |
7150 | I40E_GL_MDET_RX_FUNCTION_SHIFT; | |
013f6579 | 7151 | u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> |
4c33f83a | 7152 | I40E_GL_MDET_RX_EVENT_SHIFT; |
2089ad03 MW |
7153 | u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> |
7154 | I40E_GL_MDET_RX_QUEUE_SHIFT) - | |
7155 | pf->hw.func_caps.base_queue; | |
faf32978 JB |
7156 | if (netif_msg_rx_err(pf)) |
7157 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", | |
7158 | event, queue, func); | |
41c445ff JB |
7159 | wr32(hw, I40E_GL_MDET_RX, 0xffffffff); |
7160 | mdd_detected = true; | |
7161 | } | |
7162 | ||
df430b12 NP |
7163 | if (mdd_detected) { |
7164 | reg = rd32(hw, I40E_PF_MDET_TX); | |
7165 | if (reg & I40E_PF_MDET_TX_VALID_MASK) { | |
7166 | wr32(hw, I40E_PF_MDET_TX, 0xFFFF); | |
faf32978 | 7167 | dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n"); |
df430b12 NP |
7168 | pf_mdd_detected = true; |
7169 | } | |
7170 | reg = rd32(hw, I40E_PF_MDET_RX); | |
7171 | if (reg & I40E_PF_MDET_RX_VALID_MASK) { | |
7172 | wr32(hw, I40E_PF_MDET_RX, 0xFFFF); | |
faf32978 | 7173 | dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n"); |
df430b12 NP |
7174 | pf_mdd_detected = true; |
7175 | } | |
7176 | /* Queue belongs to the PF, initiate a reset */ | |
7177 | if (pf_mdd_detected) { | |
7178 | set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); | |
7179 | i40e_service_event_schedule(pf); | |
7180 | } | |
7181 | } | |
7182 | ||
41c445ff JB |
7183 | /* see if one of the VFs needs its hand slapped */ |
7184 | for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) { | |
7185 | vf = &(pf->vf[i]); | |
7186 | reg = rd32(hw, I40E_VP_MDET_TX(i)); | |
7187 | if (reg & I40E_VP_MDET_TX_VALID_MASK) { | |
7188 | wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF); | |
7189 | vf->num_mdd_events++; | |
faf32978 JB |
7190 | dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n", |
7191 | i); | |
41c445ff JB |
7192 | } |
7193 | ||
7194 | reg = rd32(hw, I40E_VP_MDET_RX(i)); | |
7195 | if (reg & I40E_VP_MDET_RX_VALID_MASK) { | |
7196 | wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF); | |
7197 | vf->num_mdd_events++; | |
faf32978 JB |
7198 | dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n", |
7199 | i); | |
41c445ff JB |
7200 | } |
7201 | ||
7202 | if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) { | |
7203 | dev_info(&pf->pdev->dev, | |
7204 | "Too many MDD events on VF %d, disabled\n", i); | |
7205 | dev_info(&pf->pdev->dev, | |
7206 | "Use PF Control I/F to re-enable the VF\n"); | |
7207 | set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states); | |
7208 | } | |
7209 | } | |
7210 | ||
7211 | /* re-enable mdd interrupt cause */ | |
7212 | clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state); | |
7213 | reg = rd32(hw, I40E_PFINT_ICR0_ENA); | |
7214 | reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
7215 | wr32(hw, I40E_PFINT_ICR0_ENA, reg); | |
7216 | i40e_flush(hw); | |
7217 | } | |
7218 | ||
a1c9a9d9 | 7219 | /** |
6a899024 | 7220 | * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW |
a1c9a9d9 JK |
7221 | * @pf: board private structure |
7222 | **/ | |
6a899024 | 7223 | static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf) |
a1c9a9d9 | 7224 | { |
a1c9a9d9 JK |
7225 | struct i40e_hw *hw = &pf->hw; |
7226 | i40e_status ret; | |
a1c9a9d9 JK |
7227 | __be16 port; |
7228 | int i; | |
7229 | ||
6a899024 | 7230 | if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC)) |
a1c9a9d9 JK |
7231 | return; |
7232 | ||
6a899024 | 7233 | pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC; |
a1c9a9d9 JK |
7234 | |
7235 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
6a899024 SA |
7236 | if (pf->pending_udp_bitmap & BIT_ULL(i)) { |
7237 | pf->pending_udp_bitmap &= ~BIT_ULL(i); | |
7238 | port = pf->udp_ports[i].index; | |
c22c06c8 | 7239 | if (port) |
b3f5c7bc CW |
7240 | ret = i40e_aq_add_udp_tunnel(hw, port, |
7241 | pf->udp_ports[i].type, | |
7242 | NULL, NULL); | |
c22c06c8 SN |
7243 | else |
7244 | ret = i40e_aq_del_udp_tunnel(hw, i, NULL); | |
a1c9a9d9 JK |
7245 | |
7246 | if (ret) { | |
730a8f87 CW |
7247 | dev_dbg(&pf->pdev->dev, |
7248 | "%s %s port %d, index %d failed, err %s aq_err %s\n", | |
7249 | pf->udp_ports[i].type ? "vxlan" : "geneve", | |
7250 | port ? "add" : "delete", | |
7251 | ntohs(port), i, | |
7252 | i40e_stat_str(&pf->hw, ret), | |
7253 | i40e_aq_str(&pf->hw, | |
f1c7e72e | 7254 | pf->hw.aq.asq_last_status)); |
6a899024 | 7255 | pf->udp_ports[i].index = 0; |
a1c9a9d9 JK |
7256 | } |
7257 | } | |
7258 | } | |
7259 | } | |
7260 | ||
41c445ff JB |
7261 | /** |
7262 | * i40e_service_task - Run the driver's async subtasks | |
7263 | * @work: pointer to work_struct containing our data | |
7264 | **/ | |
7265 | static void i40e_service_task(struct work_struct *work) | |
7266 | { | |
7267 | struct i40e_pf *pf = container_of(work, | |
7268 | struct i40e_pf, | |
7269 | service_task); | |
7270 | unsigned long start_time = jiffies; | |
7271 | ||
e57a2fea SN |
7272 | /* don't bother with service tasks if a reset is in progress */ |
7273 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) { | |
7274 | i40e_service_event_complete(pf); | |
7275 | return; | |
7276 | } | |
7277 | ||
b03a8c1f | 7278 | i40e_detect_recover_hung(pf); |
2818ccd9 | 7279 | i40e_sync_filters_subtask(pf); |
41c445ff JB |
7280 | i40e_reset_subtask(pf); |
7281 | i40e_handle_mdd_event(pf); | |
7282 | i40e_vc_process_vflr_event(pf); | |
7283 | i40e_watchdog_subtask(pf); | |
7284 | i40e_fdir_reinit_subtask(pf); | |
e3219ce6 | 7285 | i40e_client_subtask(pf); |
41c445ff | 7286 | i40e_sync_filters_subtask(pf); |
6a899024 | 7287 | i40e_sync_udp_filters_subtask(pf); |
41c445ff JB |
7288 | i40e_clean_adminq_subtask(pf); |
7289 | ||
7290 | i40e_service_event_complete(pf); | |
7291 | ||
7292 | /* If the tasks have taken longer than one timer cycle or there | |
7293 | * is more work to be done, reschedule the service task now | |
7294 | * rather than wait for the timer to tick again. | |
7295 | */ | |
7296 | if (time_after(jiffies, (start_time + pf->service_timer_period)) || | |
7297 | test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) || | |
7298 | test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) || | |
7299 | test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state)) | |
7300 | i40e_service_event_schedule(pf); | |
7301 | } | |
7302 | ||
7303 | /** | |
7304 | * i40e_service_timer - timer callback | |
7305 | * @data: pointer to PF struct | |
7306 | **/ | |
7307 | static void i40e_service_timer(unsigned long data) | |
7308 | { | |
7309 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
7310 | ||
7311 | mod_timer(&pf->service_timer, | |
7312 | round_jiffies(jiffies + pf->service_timer_period)); | |
7313 | i40e_service_event_schedule(pf); | |
7314 | } | |
7315 | ||
7316 | /** | |
7317 | * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI | |
7318 | * @vsi: the VSI being configured | |
7319 | **/ | |
7320 | static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) | |
7321 | { | |
7322 | struct i40e_pf *pf = vsi->back; | |
7323 | ||
7324 | switch (vsi->type) { | |
7325 | case I40E_VSI_MAIN: | |
7326 | vsi->alloc_queue_pairs = pf->num_lan_qps; | |
7327 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7328 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7329 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7330 | vsi->num_q_vectors = pf->num_lan_msix; | |
7331 | else | |
7332 | vsi->num_q_vectors = 1; | |
7333 | ||
7334 | break; | |
7335 | ||
7336 | case I40E_VSI_FDIR: | |
7337 | vsi->alloc_queue_pairs = 1; | |
7338 | vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT, | |
7339 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
a70e407f | 7340 | vsi->num_q_vectors = pf->num_fdsb_msix; |
41c445ff JB |
7341 | break; |
7342 | ||
7343 | case I40E_VSI_VMDQ2: | |
7344 | vsi->alloc_queue_pairs = pf->num_vmdq_qps; | |
7345 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7346 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7347 | vsi->num_q_vectors = pf->num_vmdq_msix; | |
7348 | break; | |
7349 | ||
7350 | case I40E_VSI_SRIOV: | |
7351 | vsi->alloc_queue_pairs = pf->num_vf_qps; | |
7352 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7353 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7354 | break; | |
7355 | ||
38e00438 VD |
7356 | #ifdef I40E_FCOE |
7357 | case I40E_VSI_FCOE: | |
7358 | vsi->alloc_queue_pairs = pf->num_fcoe_qps; | |
7359 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7360 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7361 | vsi->num_q_vectors = pf->num_fcoe_msix; | |
7362 | break; | |
7363 | ||
7364 | #endif /* I40E_FCOE */ | |
41c445ff JB |
7365 | default: |
7366 | WARN_ON(1); | |
7367 | return -ENODATA; | |
7368 | } | |
7369 | ||
7370 | return 0; | |
7371 | } | |
7372 | ||
f650a38b ASJ |
7373 | /** |
7374 | * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi | |
7375 | * @type: VSI pointer | |
bc7d338f | 7376 | * @alloc_qvectors: a bool to specify if q_vectors need to be allocated. |
f650a38b ASJ |
7377 | * |
7378 | * On error: returns error code (negative) | |
7379 | * On success: returns 0 | |
7380 | **/ | |
bc7d338f | 7381 | static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors) |
f650a38b ASJ |
7382 | { |
7383 | int size; | |
7384 | int ret = 0; | |
7385 | ||
ac6c5e3d | 7386 | /* allocate memory for both Tx and Rx ring pointers */ |
f650a38b ASJ |
7387 | size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2; |
7388 | vsi->tx_rings = kzalloc(size, GFP_KERNEL); | |
7389 | if (!vsi->tx_rings) | |
7390 | return -ENOMEM; | |
f650a38b ASJ |
7391 | vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs]; |
7392 | ||
bc7d338f ASJ |
7393 | if (alloc_qvectors) { |
7394 | /* allocate memory for q_vector pointers */ | |
f57e4fbd | 7395 | size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors; |
bc7d338f ASJ |
7396 | vsi->q_vectors = kzalloc(size, GFP_KERNEL); |
7397 | if (!vsi->q_vectors) { | |
7398 | ret = -ENOMEM; | |
7399 | goto err_vectors; | |
7400 | } | |
f650a38b ASJ |
7401 | } |
7402 | return ret; | |
7403 | ||
7404 | err_vectors: | |
7405 | kfree(vsi->tx_rings); | |
7406 | return ret; | |
7407 | } | |
7408 | ||
41c445ff JB |
7409 | /** |
7410 | * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF | |
7411 | * @pf: board private structure | |
7412 | * @type: type of VSI | |
7413 | * | |
7414 | * On error: returns error code (negative) | |
7415 | * On success: returns vsi index in PF (positive) | |
7416 | **/ | |
7417 | static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type) | |
7418 | { | |
7419 | int ret = -ENODEV; | |
7420 | struct i40e_vsi *vsi; | |
7421 | int vsi_idx; | |
7422 | int i; | |
7423 | ||
7424 | /* Need to protect the allocation of the VSIs at the PF level */ | |
7425 | mutex_lock(&pf->switch_mutex); | |
7426 | ||
7427 | /* VSI list may be fragmented if VSI creation/destruction has | |
7428 | * been happening. We can afford to do a quick scan to look | |
7429 | * for any free VSIs in the list. | |
7430 | * | |
7431 | * find next empty vsi slot, looping back around if necessary | |
7432 | */ | |
7433 | i = pf->next_vsi; | |
505682cd | 7434 | while (i < pf->num_alloc_vsi && pf->vsi[i]) |
41c445ff | 7435 | i++; |
505682cd | 7436 | if (i >= pf->num_alloc_vsi) { |
41c445ff JB |
7437 | i = 0; |
7438 | while (i < pf->next_vsi && pf->vsi[i]) | |
7439 | i++; | |
7440 | } | |
7441 | ||
505682cd | 7442 | if (i < pf->num_alloc_vsi && !pf->vsi[i]) { |
41c445ff JB |
7443 | vsi_idx = i; /* Found one! */ |
7444 | } else { | |
7445 | ret = -ENODEV; | |
493fb300 | 7446 | goto unlock_pf; /* out of VSI slots! */ |
41c445ff JB |
7447 | } |
7448 | pf->next_vsi = ++i; | |
7449 | ||
7450 | vsi = kzalloc(sizeof(*vsi), GFP_KERNEL); | |
7451 | if (!vsi) { | |
7452 | ret = -ENOMEM; | |
493fb300 | 7453 | goto unlock_pf; |
41c445ff JB |
7454 | } |
7455 | vsi->type = type; | |
7456 | vsi->back = pf; | |
7457 | set_bit(__I40E_DOWN, &vsi->state); | |
7458 | vsi->flags = 0; | |
7459 | vsi->idx = vsi_idx; | |
ac26fc13 | 7460 | vsi->int_rate_limit = 0; |
5db4cb59 ASJ |
7461 | vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ? |
7462 | pf->rss_table_size : 64; | |
41c445ff JB |
7463 | vsi->netdev_registered = false; |
7464 | vsi->work_limit = I40E_DEFAULT_IRQ_WORK; | |
278e7d0b | 7465 | hash_init(vsi->mac_filter_hash); |
63741846 | 7466 | vsi->irqs_ready = false; |
41c445ff | 7467 | |
9f65e15b AD |
7468 | ret = i40e_set_num_rings_in_vsi(vsi); |
7469 | if (ret) | |
7470 | goto err_rings; | |
7471 | ||
bc7d338f | 7472 | ret = i40e_vsi_alloc_arrays(vsi, true); |
f650a38b | 7473 | if (ret) |
9f65e15b | 7474 | goto err_rings; |
493fb300 | 7475 | |
41c445ff JB |
7476 | /* Setup default MSIX irq handler for VSI */ |
7477 | i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings); | |
7478 | ||
21659035 | 7479 | /* Initialize VSI lock */ |
278e7d0b | 7480 | spin_lock_init(&vsi->mac_filter_hash_lock); |
41c445ff JB |
7481 | pf->vsi[vsi_idx] = vsi; |
7482 | ret = vsi_idx; | |
493fb300 AD |
7483 | goto unlock_pf; |
7484 | ||
9f65e15b | 7485 | err_rings: |
493fb300 AD |
7486 | pf->next_vsi = i - 1; |
7487 | kfree(vsi); | |
7488 | unlock_pf: | |
41c445ff JB |
7489 | mutex_unlock(&pf->switch_mutex); |
7490 | return ret; | |
7491 | } | |
7492 | ||
f650a38b ASJ |
7493 | /** |
7494 | * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI | |
7495 | * @type: VSI pointer | |
bc7d338f | 7496 | * @free_qvectors: a bool to specify if q_vectors need to be freed. |
f650a38b ASJ |
7497 | * |
7498 | * On error: returns error code (negative) | |
7499 | * On success: returns 0 | |
7500 | **/ | |
bc7d338f | 7501 | static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors) |
f650a38b ASJ |
7502 | { |
7503 | /* free the ring and vector containers */ | |
bc7d338f ASJ |
7504 | if (free_qvectors) { |
7505 | kfree(vsi->q_vectors); | |
7506 | vsi->q_vectors = NULL; | |
7507 | } | |
f650a38b ASJ |
7508 | kfree(vsi->tx_rings); |
7509 | vsi->tx_rings = NULL; | |
7510 | vsi->rx_rings = NULL; | |
7511 | } | |
7512 | ||
28c5869f HZ |
7513 | /** |
7514 | * i40e_clear_rss_config_user - clear the user configured RSS hash keys | |
7515 | * and lookup table | |
7516 | * @vsi: Pointer to VSI structure | |
7517 | */ | |
7518 | static void i40e_clear_rss_config_user(struct i40e_vsi *vsi) | |
7519 | { | |
7520 | if (!vsi) | |
7521 | return; | |
7522 | ||
7523 | kfree(vsi->rss_hkey_user); | |
7524 | vsi->rss_hkey_user = NULL; | |
7525 | ||
7526 | kfree(vsi->rss_lut_user); | |
7527 | vsi->rss_lut_user = NULL; | |
7528 | } | |
7529 | ||
41c445ff JB |
7530 | /** |
7531 | * i40e_vsi_clear - Deallocate the VSI provided | |
7532 | * @vsi: the VSI being un-configured | |
7533 | **/ | |
7534 | static int i40e_vsi_clear(struct i40e_vsi *vsi) | |
7535 | { | |
7536 | struct i40e_pf *pf; | |
7537 | ||
7538 | if (!vsi) | |
7539 | return 0; | |
7540 | ||
7541 | if (!vsi->back) | |
7542 | goto free_vsi; | |
7543 | pf = vsi->back; | |
7544 | ||
7545 | mutex_lock(&pf->switch_mutex); | |
7546 | if (!pf->vsi[vsi->idx]) { | |
7547 | dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n", | |
7548 | vsi->idx, vsi->idx, vsi, vsi->type); | |
7549 | goto unlock_vsi; | |
7550 | } | |
7551 | ||
7552 | if (pf->vsi[vsi->idx] != vsi) { | |
7553 | dev_err(&pf->pdev->dev, | |
7554 | "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n", | |
7555 | pf->vsi[vsi->idx]->idx, | |
7556 | pf->vsi[vsi->idx], | |
7557 | pf->vsi[vsi->idx]->type, | |
7558 | vsi->idx, vsi, vsi->type); | |
7559 | goto unlock_vsi; | |
7560 | } | |
7561 | ||
b40c82e6 | 7562 | /* updates the PF for this cleared vsi */ |
41c445ff JB |
7563 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
7564 | i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx); | |
7565 | ||
bc7d338f | 7566 | i40e_vsi_free_arrays(vsi, true); |
28c5869f | 7567 | i40e_clear_rss_config_user(vsi); |
493fb300 | 7568 | |
41c445ff JB |
7569 | pf->vsi[vsi->idx] = NULL; |
7570 | if (vsi->idx < pf->next_vsi) | |
7571 | pf->next_vsi = vsi->idx; | |
7572 | ||
7573 | unlock_vsi: | |
7574 | mutex_unlock(&pf->switch_mutex); | |
7575 | free_vsi: | |
7576 | kfree(vsi); | |
7577 | ||
7578 | return 0; | |
7579 | } | |
7580 | ||
9f65e15b AD |
7581 | /** |
7582 | * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI | |
7583 | * @vsi: the VSI being cleaned | |
7584 | **/ | |
be1d5eea | 7585 | static void i40e_vsi_clear_rings(struct i40e_vsi *vsi) |
9f65e15b AD |
7586 | { |
7587 | int i; | |
7588 | ||
8e9dca53 | 7589 | if (vsi->tx_rings && vsi->tx_rings[0]) { |
d7397644 | 7590 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
00403f04 MW |
7591 | kfree_rcu(vsi->tx_rings[i], rcu); |
7592 | vsi->tx_rings[i] = NULL; | |
7593 | vsi->rx_rings[i] = NULL; | |
7594 | } | |
be1d5eea | 7595 | } |
9f65e15b AD |
7596 | } |
7597 | ||
41c445ff JB |
7598 | /** |
7599 | * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI | |
7600 | * @vsi: the VSI being configured | |
7601 | **/ | |
7602 | static int i40e_alloc_rings(struct i40e_vsi *vsi) | |
7603 | { | |
e7046ee1 | 7604 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff | 7605 | struct i40e_pf *pf = vsi->back; |
41c445ff JB |
7606 | int i; |
7607 | ||
41c445ff | 7608 | /* Set basic values in the rings to be used later during open() */ |
d7397644 | 7609 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
ac6c5e3d | 7610 | /* allocate space for both Tx and Rx in one shot */ |
9f65e15b AD |
7611 | tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL); |
7612 | if (!tx_ring) | |
7613 | goto err_out; | |
41c445ff JB |
7614 | |
7615 | tx_ring->queue_index = i; | |
7616 | tx_ring->reg_idx = vsi->base_queue + i; | |
7617 | tx_ring->ring_active = false; | |
7618 | tx_ring->vsi = vsi; | |
7619 | tx_ring->netdev = vsi->netdev; | |
7620 | tx_ring->dev = &pf->pdev->dev; | |
7621 | tx_ring->count = vsi->num_desc; | |
7622 | tx_ring->size = 0; | |
7623 | tx_ring->dcb_tc = 0; | |
8e0764b4 ASJ |
7624 | if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE) |
7625 | tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; | |
a75e8005 | 7626 | tx_ring->tx_itr_setting = pf->tx_itr_default; |
9f65e15b | 7627 | vsi->tx_rings[i] = tx_ring; |
41c445ff | 7628 | |
9f65e15b | 7629 | rx_ring = &tx_ring[1]; |
41c445ff JB |
7630 | rx_ring->queue_index = i; |
7631 | rx_ring->reg_idx = vsi->base_queue + i; | |
7632 | rx_ring->ring_active = false; | |
7633 | rx_ring->vsi = vsi; | |
7634 | rx_ring->netdev = vsi->netdev; | |
7635 | rx_ring->dev = &pf->pdev->dev; | |
7636 | rx_ring->count = vsi->num_desc; | |
7637 | rx_ring->size = 0; | |
7638 | rx_ring->dcb_tc = 0; | |
a75e8005 | 7639 | rx_ring->rx_itr_setting = pf->rx_itr_default; |
9f65e15b | 7640 | vsi->rx_rings[i] = rx_ring; |
41c445ff JB |
7641 | } |
7642 | ||
7643 | return 0; | |
9f65e15b AD |
7644 | |
7645 | err_out: | |
7646 | i40e_vsi_clear_rings(vsi); | |
7647 | return -ENOMEM; | |
41c445ff JB |
7648 | } |
7649 | ||
7650 | /** | |
7651 | * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel | |
7652 | * @pf: board private structure | |
7653 | * @vectors: the number of MSI-X vectors to request | |
7654 | * | |
7655 | * Returns the number of vectors reserved, or error | |
7656 | **/ | |
7657 | static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors) | |
7658 | { | |
7b37f376 AG |
7659 | vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries, |
7660 | I40E_MIN_MSIX, vectors); | |
7661 | if (vectors < 0) { | |
41c445ff | 7662 | dev_info(&pf->pdev->dev, |
7b37f376 | 7663 | "MSI-X vector reservation failed: %d\n", vectors); |
41c445ff JB |
7664 | vectors = 0; |
7665 | } | |
7666 | ||
7667 | return vectors; | |
7668 | } | |
7669 | ||
7670 | /** | |
7671 | * i40e_init_msix - Setup the MSIX capability | |
7672 | * @pf: board private structure | |
7673 | * | |
7674 | * Work with the OS to set up the MSIX vectors needed. | |
7675 | * | |
3b444399 | 7676 | * Returns the number of vectors reserved or negative on failure |
41c445ff JB |
7677 | **/ |
7678 | static int i40e_init_msix(struct i40e_pf *pf) | |
7679 | { | |
41c445ff | 7680 | struct i40e_hw *hw = &pf->hw; |
1e200e4a | 7681 | int vectors_left; |
41c445ff | 7682 | int v_budget, i; |
3b444399 | 7683 | int v_actual; |
e3219ce6 | 7684 | int iwarp_requested = 0; |
41c445ff JB |
7685 | |
7686 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
7687 | return -ENODEV; | |
7688 | ||
7689 | /* The number of vectors we'll request will be comprised of: | |
7690 | * - Add 1 for "other" cause for Admin Queue events, etc. | |
7691 | * - The number of LAN queue pairs | |
f8ff1464 ASJ |
7692 | * - Queues being used for RSS. |
7693 | * We don't need as many as max_rss_size vectors. | |
7694 | * use rss_size instead in the calculation since that | |
7695 | * is governed by number of cpus in the system. | |
7696 | * - assumes symmetric Tx/Rx pairing | |
41c445ff | 7697 | * - The number of VMDq pairs |
e3219ce6 | 7698 | * - The CPU count within the NUMA node if iWARP is enabled |
38e00438 VD |
7699 | #ifdef I40E_FCOE |
7700 | * - The number of FCOE qps. | |
7701 | #endif | |
41c445ff JB |
7702 | * Once we count this up, try the request. |
7703 | * | |
7704 | * If we can't get what we want, we'll simplify to nearly nothing | |
7705 | * and try again. If that still fails, we punt. | |
7706 | */ | |
1e200e4a SN |
7707 | vectors_left = hw->func_caps.num_msix_vectors; |
7708 | v_budget = 0; | |
7709 | ||
7710 | /* reserve one vector for miscellaneous handler */ | |
7711 | if (vectors_left) { | |
7712 | v_budget++; | |
7713 | vectors_left--; | |
7714 | } | |
7715 | ||
7716 | /* reserve vectors for the main PF traffic queues */ | |
7717 | pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left); | |
7718 | vectors_left -= pf->num_lan_msix; | |
7719 | v_budget += pf->num_lan_msix; | |
7720 | ||
7721 | /* reserve one vector for sideband flow director */ | |
7722 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
7723 | if (vectors_left) { | |
a70e407f | 7724 | pf->num_fdsb_msix = 1; |
1e200e4a SN |
7725 | v_budget++; |
7726 | vectors_left--; | |
7727 | } else { | |
a70e407f | 7728 | pf->num_fdsb_msix = 0; |
1e200e4a SN |
7729 | } |
7730 | } | |
83840e4b | 7731 | |
38e00438 | 7732 | #ifdef I40E_FCOE |
1e200e4a | 7733 | /* can we reserve enough for FCoE? */ |
38e00438 | 7734 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { |
1e200e4a SN |
7735 | if (!vectors_left) |
7736 | pf->num_fcoe_msix = 0; | |
7737 | else if (vectors_left >= pf->num_fcoe_qps) | |
7738 | pf->num_fcoe_msix = pf->num_fcoe_qps; | |
7739 | else | |
7740 | pf->num_fcoe_msix = 1; | |
38e00438 | 7741 | v_budget += pf->num_fcoe_msix; |
1e200e4a | 7742 | vectors_left -= pf->num_fcoe_msix; |
38e00438 | 7743 | } |
1e200e4a | 7744 | |
38e00438 | 7745 | #endif |
e3219ce6 ASJ |
7746 | /* can we reserve enough for iWARP? */ |
7747 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { | |
4ce20abc SA |
7748 | iwarp_requested = pf->num_iwarp_msix; |
7749 | ||
e3219ce6 ASJ |
7750 | if (!vectors_left) |
7751 | pf->num_iwarp_msix = 0; | |
7752 | else if (vectors_left < pf->num_iwarp_msix) | |
7753 | pf->num_iwarp_msix = 1; | |
7754 | v_budget += pf->num_iwarp_msix; | |
7755 | vectors_left -= pf->num_iwarp_msix; | |
7756 | } | |
7757 | ||
1e200e4a SN |
7758 | /* any vectors left over go for VMDq support */ |
7759 | if (pf->flags & I40E_FLAG_VMDQ_ENABLED) { | |
7760 | int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps; | |
7761 | int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted); | |
7762 | ||
9ca57e97 SA |
7763 | if (!vectors_left) { |
7764 | pf->num_vmdq_msix = 0; | |
7765 | pf->num_vmdq_qps = 0; | |
7766 | } else { | |
7767 | /* if we're short on vectors for what's desired, we limit | |
7768 | * the queues per vmdq. If this is still more than are | |
7769 | * available, the user will need to change the number of | |
7770 | * queues/vectors used by the PF later with the ethtool | |
7771 | * channels command | |
7772 | */ | |
7773 | if (vmdq_vecs < vmdq_vecs_wanted) | |
7774 | pf->num_vmdq_qps = 1; | |
7775 | pf->num_vmdq_msix = pf->num_vmdq_qps; | |
1e200e4a | 7776 | |
9ca57e97 SA |
7777 | v_budget += vmdq_vecs; |
7778 | vectors_left -= vmdq_vecs; | |
7779 | } | |
1e200e4a | 7780 | } |
41c445ff JB |
7781 | |
7782 | pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), | |
7783 | GFP_KERNEL); | |
7784 | if (!pf->msix_entries) | |
7785 | return -ENOMEM; | |
7786 | ||
7787 | for (i = 0; i < v_budget; i++) | |
7788 | pf->msix_entries[i].entry = i; | |
3b444399 | 7789 | v_actual = i40e_reserve_msix_vectors(pf, v_budget); |
a34977ba | 7790 | |
3b444399 | 7791 | if (v_actual < I40E_MIN_MSIX) { |
41c445ff JB |
7792 | pf->flags &= ~I40E_FLAG_MSIX_ENABLED; |
7793 | kfree(pf->msix_entries); | |
7794 | pf->msix_entries = NULL; | |
4c95aa5d | 7795 | pci_disable_msix(pf->pdev); |
41c445ff JB |
7796 | return -ENODEV; |
7797 | ||
3b444399 | 7798 | } else if (v_actual == I40E_MIN_MSIX) { |
41c445ff | 7799 | /* Adjust for minimal MSIX use */ |
41c445ff JB |
7800 | pf->num_vmdq_vsis = 0; |
7801 | pf->num_vmdq_qps = 0; | |
41c445ff JB |
7802 | pf->num_lan_qps = 1; |
7803 | pf->num_lan_msix = 1; | |
7804 | ||
4ce20abc SA |
7805 | } else if (!vectors_left) { |
7806 | /* If we have limited resources, we will start with no vectors | |
7807 | * for the special features and then allocate vectors to some | |
7808 | * of these features based on the policy and at the end disable | |
7809 | * the features that did not get any vectors. | |
7810 | */ | |
3b444399 SN |
7811 | int vec; |
7812 | ||
4ce20abc SA |
7813 | dev_info(&pf->pdev->dev, |
7814 | "MSI-X vector limit reached, attempting to redistribute vectors\n"); | |
a34977ba | 7815 | /* reserve the misc vector */ |
3b444399 | 7816 | vec = v_actual - 1; |
a34977ba | 7817 | |
41c445ff JB |
7818 | /* Scale vector usage down */ |
7819 | pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */ | |
a34977ba | 7820 | pf->num_vmdq_vsis = 1; |
1e200e4a | 7821 | pf->num_vmdq_qps = 1; |
4ce20abc SA |
7822 | #ifdef I40E_FCOE |
7823 | pf->num_fcoe_qps = 0; | |
7824 | pf->num_fcoe_msix = 0; | |
7825 | #endif | |
41c445ff JB |
7826 | |
7827 | /* partition out the remaining vectors */ | |
7828 | switch (vec) { | |
7829 | case 2: | |
41c445ff JB |
7830 | pf->num_lan_msix = 1; |
7831 | break; | |
7832 | case 3: | |
e3219ce6 ASJ |
7833 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
7834 | pf->num_lan_msix = 1; | |
7835 | pf->num_iwarp_msix = 1; | |
7836 | } else { | |
7837 | pf->num_lan_msix = 2; | |
7838 | } | |
38e00438 VD |
7839 | #ifdef I40E_FCOE |
7840 | /* give one vector to FCoE */ | |
7841 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { | |
7842 | pf->num_lan_msix = 1; | |
7843 | pf->num_fcoe_msix = 1; | |
7844 | } | |
38e00438 | 7845 | #endif |
41c445ff JB |
7846 | break; |
7847 | default: | |
e3219ce6 ASJ |
7848 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
7849 | pf->num_iwarp_msix = min_t(int, (vec / 3), | |
7850 | iwarp_requested); | |
7851 | pf->num_vmdq_vsis = min_t(int, (vec / 3), | |
7852 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
7853 | } else { | |
7854 | pf->num_vmdq_vsis = min_t(int, (vec / 2), | |
7855 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
7856 | } | |
abd97a94 SA |
7857 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
7858 | pf->num_fdsb_msix = 1; | |
7859 | vec--; | |
7860 | } | |
e3219ce6 ASJ |
7861 | pf->num_lan_msix = min_t(int, |
7862 | (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)), | |
7863 | pf->num_lan_msix); | |
4ce20abc | 7864 | pf->num_lan_qps = pf->num_lan_msix; |
38e00438 VD |
7865 | #ifdef I40E_FCOE |
7866 | /* give one vector to FCoE */ | |
7867 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { | |
7868 | pf->num_fcoe_msix = 1; | |
7869 | vec--; | |
7870 | } | |
7871 | #endif | |
41c445ff JB |
7872 | break; |
7873 | } | |
7874 | } | |
7875 | ||
abd97a94 SA |
7876 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
7877 | (pf->num_fdsb_msix == 0)) { | |
7878 | dev_info(&pf->pdev->dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n"); | |
7879 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
7880 | } | |
a34977ba ASJ |
7881 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && |
7882 | (pf->num_vmdq_msix == 0)) { | |
7883 | dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n"); | |
7884 | pf->flags &= ~I40E_FLAG_VMDQ_ENABLED; | |
7885 | } | |
e3219ce6 ASJ |
7886 | |
7887 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && | |
7888 | (pf->num_iwarp_msix == 0)) { | |
7889 | dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n"); | |
7890 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
7891 | } | |
38e00438 VD |
7892 | #ifdef I40E_FCOE |
7893 | ||
7894 | if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) { | |
7895 | dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n"); | |
7896 | pf->flags &= ~I40E_FLAG_FCOE_ENABLED; | |
7897 | } | |
7898 | #endif | |
4ce20abc SA |
7899 | i40e_debug(&pf->hw, I40E_DEBUG_INIT, |
7900 | "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n", | |
7901 | pf->num_lan_msix, | |
7902 | pf->num_vmdq_msix * pf->num_vmdq_vsis, | |
7903 | pf->num_fdsb_msix, | |
7904 | pf->num_iwarp_msix); | |
7905 | ||
3b444399 | 7906 | return v_actual; |
41c445ff JB |
7907 | } |
7908 | ||
493fb300 | 7909 | /** |
90e04070 | 7910 | * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector |
493fb300 AD |
7911 | * @vsi: the VSI being configured |
7912 | * @v_idx: index of the vector in the vsi struct | |
7f6c5539 | 7913 | * @cpu: cpu to be used on affinity_mask |
493fb300 AD |
7914 | * |
7915 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
7916 | **/ | |
7f6c5539 | 7917 | static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu) |
493fb300 AD |
7918 | { |
7919 | struct i40e_q_vector *q_vector; | |
7920 | ||
7921 | /* allocate q_vector */ | |
7922 | q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL); | |
7923 | if (!q_vector) | |
7924 | return -ENOMEM; | |
7925 | ||
7926 | q_vector->vsi = vsi; | |
7927 | q_vector->v_idx = v_idx; | |
7f6c5539 GP |
7928 | cpumask_set_cpu(cpu, &q_vector->affinity_mask); |
7929 | ||
493fb300 AD |
7930 | if (vsi->netdev) |
7931 | netif_napi_add(vsi->netdev, &q_vector->napi, | |
eefeacee | 7932 | i40e_napi_poll, NAPI_POLL_WEIGHT); |
493fb300 | 7933 | |
cd0b6fa6 AD |
7934 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
7935 | q_vector->tx.latency_range = I40E_LOW_LATENCY; | |
7936 | ||
493fb300 AD |
7937 | /* tie q_vector and vsi together */ |
7938 | vsi->q_vectors[v_idx] = q_vector; | |
7939 | ||
7940 | return 0; | |
7941 | } | |
7942 | ||
41c445ff | 7943 | /** |
90e04070 | 7944 | * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors |
41c445ff JB |
7945 | * @vsi: the VSI being configured |
7946 | * | |
7947 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
7948 | * return -ENOMEM. | |
7949 | **/ | |
90e04070 | 7950 | static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi) |
41c445ff JB |
7951 | { |
7952 | struct i40e_pf *pf = vsi->back; | |
7f6c5539 | 7953 | int err, v_idx, num_q_vectors, current_cpu; |
41c445ff JB |
7954 | |
7955 | /* if not MSIX, give the one vector only to the LAN VSI */ | |
7956 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7957 | num_q_vectors = vsi->num_q_vectors; | |
7958 | else if (vsi == pf->vsi[pf->lan_vsi]) | |
7959 | num_q_vectors = 1; | |
7960 | else | |
7961 | return -EINVAL; | |
7962 | ||
7f6c5539 GP |
7963 | current_cpu = cpumask_first(cpu_online_mask); |
7964 | ||
41c445ff | 7965 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
7f6c5539 | 7966 | err = i40e_vsi_alloc_q_vector(vsi, v_idx, current_cpu); |
493fb300 AD |
7967 | if (err) |
7968 | goto err_out; | |
7f6c5539 GP |
7969 | current_cpu = cpumask_next(current_cpu, cpu_online_mask); |
7970 | if (unlikely(current_cpu >= nr_cpu_ids)) | |
7971 | current_cpu = cpumask_first(cpu_online_mask); | |
41c445ff JB |
7972 | } |
7973 | ||
7974 | return 0; | |
493fb300 AD |
7975 | |
7976 | err_out: | |
7977 | while (v_idx--) | |
7978 | i40e_free_q_vector(vsi, v_idx); | |
7979 | ||
7980 | return err; | |
41c445ff JB |
7981 | } |
7982 | ||
7983 | /** | |
7984 | * i40e_init_interrupt_scheme - Determine proper interrupt scheme | |
7985 | * @pf: board private structure to initialize | |
7986 | **/ | |
c1147280 | 7987 | static int i40e_init_interrupt_scheme(struct i40e_pf *pf) |
41c445ff | 7988 | { |
3b444399 SN |
7989 | int vectors = 0; |
7990 | ssize_t size; | |
41c445ff JB |
7991 | |
7992 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3b444399 SN |
7993 | vectors = i40e_init_msix(pf); |
7994 | if (vectors < 0) { | |
60ea5f83 | 7995 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | |
e3219ce6 | 7996 | I40E_FLAG_IWARP_ENABLED | |
38e00438 VD |
7997 | #ifdef I40E_FCOE |
7998 | I40E_FLAG_FCOE_ENABLED | | |
7999 | #endif | |
60ea5f83 | 8000 | I40E_FLAG_RSS_ENABLED | |
4d9b6043 | 8001 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 8002 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
8003 | I40E_FLAG_SRIOV_ENABLED | |
8004 | I40E_FLAG_FD_SB_ENABLED | | |
8005 | I40E_FLAG_FD_ATR_ENABLED | | |
8006 | I40E_FLAG_VMDQ_ENABLED); | |
41c445ff JB |
8007 | |
8008 | /* rework the queue expectations without MSIX */ | |
8009 | i40e_determine_queue_usage(pf); | |
8010 | } | |
8011 | } | |
8012 | ||
8013 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
8014 | (pf->flags & I40E_FLAG_MSI_ENABLED)) { | |
77fa28be | 8015 | dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n"); |
3b444399 SN |
8016 | vectors = pci_enable_msi(pf->pdev); |
8017 | if (vectors < 0) { | |
8018 | dev_info(&pf->pdev->dev, "MSI init failed - %d\n", | |
8019 | vectors); | |
41c445ff JB |
8020 | pf->flags &= ~I40E_FLAG_MSI_ENABLED; |
8021 | } | |
3b444399 | 8022 | vectors = 1; /* one MSI or Legacy vector */ |
41c445ff JB |
8023 | } |
8024 | ||
958a3e3b | 8025 | if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) |
77fa28be | 8026 | dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n"); |
958a3e3b | 8027 | |
3b444399 SN |
8028 | /* set up vector assignment tracking */ |
8029 | size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors); | |
8030 | pf->irq_pile = kzalloc(size, GFP_KERNEL); | |
c1147280 JB |
8031 | if (!pf->irq_pile) { |
8032 | dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n"); | |
8033 | return -ENOMEM; | |
8034 | } | |
3b444399 SN |
8035 | pf->irq_pile->num_entries = vectors; |
8036 | pf->irq_pile->search_hint = 0; | |
8037 | ||
c1147280 | 8038 | /* track first vector for misc interrupts, ignore return */ |
3b444399 | 8039 | (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1); |
c1147280 JB |
8040 | |
8041 | return 0; | |
41c445ff JB |
8042 | } |
8043 | ||
8044 | /** | |
8045 | * i40e_setup_misc_vector - Setup the misc vector to handle non queue events | |
8046 | * @pf: board private structure | |
8047 | * | |
8048 | * This sets up the handler for MSIX 0, which is used to manage the | |
8049 | * non-queue interrupts, e.g. AdminQ and errors. This is not used | |
8050 | * when in MSI or Legacy interrupt mode. | |
8051 | **/ | |
8052 | static int i40e_setup_misc_vector(struct i40e_pf *pf) | |
8053 | { | |
8054 | struct i40e_hw *hw = &pf->hw; | |
8055 | int err = 0; | |
8056 | ||
8057 | /* Only request the irq if this is the first time through, and | |
8058 | * not when we're rebuilding after a Reset | |
8059 | */ | |
8060 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) { | |
8061 | err = request_irq(pf->msix_entries[0].vector, | |
b294ac70 | 8062 | i40e_intr, 0, pf->int_name, pf); |
41c445ff JB |
8063 | if (err) { |
8064 | dev_info(&pf->pdev->dev, | |
77fa28be | 8065 | "request_irq for %s failed: %d\n", |
b294ac70 | 8066 | pf->int_name, err); |
41c445ff JB |
8067 | return -EFAULT; |
8068 | } | |
8069 | } | |
8070 | ||
ab437b5a | 8071 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
8072 | |
8073 | /* associate no queues to the misc vector */ | |
8074 | wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST); | |
8075 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K); | |
8076 | ||
8077 | i40e_flush(hw); | |
8078 | ||
40d72a50 | 8079 | i40e_irq_dynamic_enable_icr0(pf, true); |
41c445ff JB |
8080 | |
8081 | return err; | |
8082 | } | |
8083 | ||
8084 | /** | |
e25d00b8 ASJ |
8085 | * i40e_config_rss_aq - Prepare for RSS using AQ commands |
8086 | * @vsi: vsi structure | |
8087 | * @seed: RSS hash seed | |
8088 | **/ | |
e69ff813 HZ |
8089 | static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed, |
8090 | u8 *lut, u16 lut_size) | |
e25d00b8 | 8091 | { |
e25d00b8 ASJ |
8092 | struct i40e_pf *pf = vsi->back; |
8093 | struct i40e_hw *hw = &pf->hw; | |
776b2e15 | 8094 | int ret = 0; |
e25d00b8 | 8095 | |
776b2e15 JK |
8096 | if (seed) { |
8097 | struct i40e_aqc_get_set_rss_key_data *seed_dw = | |
8098 | (struct i40e_aqc_get_set_rss_key_data *)seed; | |
8099 | ret = i40e_aq_set_rss_key(hw, vsi->id, seed_dw); | |
8100 | if (ret) { | |
8101 | dev_info(&pf->pdev->dev, | |
8102 | "Cannot set RSS key, err %s aq_err %s\n", | |
8103 | i40e_stat_str(hw, ret), | |
8104 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
8105 | return ret; | |
8106 | } | |
e25d00b8 | 8107 | } |
776b2e15 JK |
8108 | if (lut) { |
8109 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
e25d00b8 | 8110 | |
776b2e15 JK |
8111 | ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); |
8112 | if (ret) { | |
8113 | dev_info(&pf->pdev->dev, | |
8114 | "Cannot set RSS lut, err %s aq_err %s\n", | |
8115 | i40e_stat_str(hw, ret), | |
8116 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
8117 | return ret; | |
8118 | } | |
8119 | } | |
e25d00b8 ASJ |
8120 | return ret; |
8121 | } | |
8122 | ||
95a73780 ASJ |
8123 | /** |
8124 | * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands | |
8125 | * @vsi: Pointer to vsi structure | |
8126 | * @seed: Buffter to store the hash keys | |
8127 | * @lut: Buffer to store the lookup table entries | |
8128 | * @lut_size: Size of buffer to store the lookup table entries | |
8129 | * | |
8130 | * Return 0 on success, negative on failure | |
8131 | */ | |
8132 | static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
8133 | u8 *lut, u16 lut_size) | |
8134 | { | |
8135 | struct i40e_pf *pf = vsi->back; | |
8136 | struct i40e_hw *hw = &pf->hw; | |
8137 | int ret = 0; | |
8138 | ||
8139 | if (seed) { | |
8140 | ret = i40e_aq_get_rss_key(hw, vsi->id, | |
8141 | (struct i40e_aqc_get_set_rss_key_data *)seed); | |
8142 | if (ret) { | |
8143 | dev_info(&pf->pdev->dev, | |
8144 | "Cannot get RSS key, err %s aq_err %s\n", | |
8145 | i40e_stat_str(&pf->hw, ret), | |
8146 | i40e_aq_str(&pf->hw, | |
8147 | pf->hw.aq.asq_last_status)); | |
8148 | return ret; | |
8149 | } | |
8150 | } | |
8151 | ||
8152 | if (lut) { | |
8153 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
8154 | ||
8155 | ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
8156 | if (ret) { | |
8157 | dev_info(&pf->pdev->dev, | |
8158 | "Cannot get RSS lut, err %s aq_err %s\n", | |
8159 | i40e_stat_str(&pf->hw, ret), | |
8160 | i40e_aq_str(&pf->hw, | |
8161 | pf->hw.aq.asq_last_status)); | |
8162 | return ret; | |
8163 | } | |
8164 | } | |
8165 | ||
8166 | return ret; | |
8167 | } | |
8168 | ||
0582b964 JK |
8169 | /** |
8170 | * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used | |
8171 | * @vsi: VSI structure | |
8172 | **/ | |
8173 | static int i40e_vsi_config_rss(struct i40e_vsi *vsi) | |
8174 | { | |
8175 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
8176 | struct i40e_pf *pf = vsi->back; | |
8177 | u8 *lut; | |
8178 | int ret; | |
8179 | ||
8180 | if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) | |
8181 | return 0; | |
8182 | ||
552b9962 JK |
8183 | if (!vsi->rss_size) |
8184 | vsi->rss_size = min_t(int, pf->alloc_rss_size, | |
8185 | vsi->num_queue_pairs); | |
8186 | if (!vsi->rss_size) | |
8187 | return -EINVAL; | |
8188 | ||
0582b964 JK |
8189 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
8190 | if (!lut) | |
8191 | return -ENOMEM; | |
552b9962 JK |
8192 | /* Use the user configured hash keys and lookup table if there is one, |
8193 | * otherwise use default | |
8194 | */ | |
8195 | if (vsi->rss_lut_user) | |
8196 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
8197 | else | |
8198 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
8199 | if (vsi->rss_hkey_user) | |
8200 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
8201 | else | |
8202 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
0582b964 JK |
8203 | ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size); |
8204 | kfree(lut); | |
8205 | ||
8206 | return ret; | |
8207 | } | |
8208 | ||
e25d00b8 | 8209 | /** |
043dd650 | 8210 | * i40e_config_rss_reg - Configure RSS keys and lut by writing registers |
e69ff813 | 8211 | * @vsi: Pointer to vsi structure |
e25d00b8 | 8212 | * @seed: RSS hash seed |
e69ff813 HZ |
8213 | * @lut: Lookup table |
8214 | * @lut_size: Lookup table size | |
8215 | * | |
8216 | * Returns 0 on success, negative on failure | |
41c445ff | 8217 | **/ |
e69ff813 HZ |
8218 | static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed, |
8219 | const u8 *lut, u16 lut_size) | |
41c445ff | 8220 | { |
e69ff813 | 8221 | struct i40e_pf *pf = vsi->back; |
4617e8c0 | 8222 | struct i40e_hw *hw = &pf->hw; |
c4e1868c | 8223 | u16 vf_id = vsi->vf_id; |
e69ff813 | 8224 | u8 i; |
41c445ff | 8225 | |
e25d00b8 | 8226 | /* Fill out hash function seed */ |
e69ff813 HZ |
8227 | if (seed) { |
8228 | u32 *seed_dw = (u32 *)seed; | |
8229 | ||
c4e1868c MW |
8230 | if (vsi->type == I40E_VSI_MAIN) { |
8231 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
8232 | i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), | |
8233 | seed_dw[i]); | |
8234 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
8235 | for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++) | |
8236 | i40e_write_rx_ctl(hw, | |
8237 | I40E_VFQF_HKEY1(i, vf_id), | |
8238 | seed_dw[i]); | |
8239 | } else { | |
8240 | dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n"); | |
8241 | } | |
e69ff813 HZ |
8242 | } |
8243 | ||
8244 | if (lut) { | |
8245 | u32 *lut_dw = (u32 *)lut; | |
8246 | ||
c4e1868c MW |
8247 | if (vsi->type == I40E_VSI_MAIN) { |
8248 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
8249 | return -EINVAL; | |
8250 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
8251 | wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]); | |
8252 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
8253 | if (lut_size != I40E_VF_HLUT_ARRAY_SIZE) | |
8254 | return -EINVAL; | |
8255 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
8256 | i40e_write_rx_ctl(hw, | |
8257 | I40E_VFQF_HLUT1(i, vf_id), | |
8258 | lut_dw[i]); | |
8259 | } else { | |
8260 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
8261 | } | |
e25d00b8 ASJ |
8262 | } |
8263 | i40e_flush(hw); | |
8264 | ||
8265 | return 0; | |
8266 | } | |
8267 | ||
043dd650 HZ |
8268 | /** |
8269 | * i40e_get_rss_reg - Get the RSS keys and lut by reading registers | |
8270 | * @vsi: Pointer to VSI structure | |
8271 | * @seed: Buffer to store the keys | |
8272 | * @lut: Buffer to store the lookup table entries | |
8273 | * @lut_size: Size of buffer to store the lookup table entries | |
8274 | * | |
8275 | * Returns 0 on success, negative on failure | |
8276 | */ | |
8277 | static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed, | |
8278 | u8 *lut, u16 lut_size) | |
8279 | { | |
8280 | struct i40e_pf *pf = vsi->back; | |
8281 | struct i40e_hw *hw = &pf->hw; | |
8282 | u16 i; | |
8283 | ||
8284 | if (seed) { | |
8285 | u32 *seed_dw = (u32 *)seed; | |
8286 | ||
8287 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
272cdaf2 | 8288 | seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); |
043dd650 HZ |
8289 | } |
8290 | if (lut) { | |
8291 | u32 *lut_dw = (u32 *)lut; | |
8292 | ||
8293 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
8294 | return -EINVAL; | |
8295 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
8296 | lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i)); | |
8297 | } | |
8298 | ||
8299 | return 0; | |
8300 | } | |
8301 | ||
8302 | /** | |
8303 | * i40e_config_rss - Configure RSS keys and lut | |
8304 | * @vsi: Pointer to VSI structure | |
8305 | * @seed: RSS hash seed | |
8306 | * @lut: Lookup table | |
8307 | * @lut_size: Lookup table size | |
8308 | * | |
8309 | * Returns 0 on success, negative on failure | |
8310 | */ | |
8311 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
8312 | { | |
8313 | struct i40e_pf *pf = vsi->back; | |
8314 | ||
8315 | if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) | |
8316 | return i40e_config_rss_aq(vsi, seed, lut, lut_size); | |
8317 | else | |
8318 | return i40e_config_rss_reg(vsi, seed, lut, lut_size); | |
8319 | } | |
8320 | ||
8321 | /** | |
8322 | * i40e_get_rss - Get RSS keys and lut | |
8323 | * @vsi: Pointer to VSI structure | |
8324 | * @seed: Buffer to store the keys | |
8325 | * @lut: Buffer to store the lookup table entries | |
8326 | * lut_size: Size of buffer to store the lookup table entries | |
8327 | * | |
8328 | * Returns 0 on success, negative on failure | |
8329 | */ | |
8330 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
8331 | { | |
95a73780 ASJ |
8332 | struct i40e_pf *pf = vsi->back; |
8333 | ||
8334 | if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) | |
8335 | return i40e_get_rss_aq(vsi, seed, lut, lut_size); | |
8336 | else | |
8337 | return i40e_get_rss_reg(vsi, seed, lut, lut_size); | |
043dd650 HZ |
8338 | } |
8339 | ||
e69ff813 HZ |
8340 | /** |
8341 | * i40e_fill_rss_lut - Fill the RSS lookup table with default values | |
8342 | * @pf: Pointer to board private structure | |
8343 | * @lut: Lookup table | |
8344 | * @rss_table_size: Lookup table size | |
8345 | * @rss_size: Range of queue number for hashing | |
8346 | */ | |
f1582351 AB |
8347 | void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, |
8348 | u16 rss_table_size, u16 rss_size) | |
e69ff813 HZ |
8349 | { |
8350 | u16 i; | |
8351 | ||
8352 | for (i = 0; i < rss_table_size; i++) | |
8353 | lut[i] = i % rss_size; | |
8354 | } | |
8355 | ||
e25d00b8 | 8356 | /** |
043dd650 | 8357 | * i40e_pf_config_rss - Prepare for RSS if used |
e25d00b8 ASJ |
8358 | * @pf: board private structure |
8359 | **/ | |
043dd650 | 8360 | static int i40e_pf_config_rss(struct i40e_pf *pf) |
e25d00b8 ASJ |
8361 | { |
8362 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
8363 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
e69ff813 | 8364 | u8 *lut; |
e25d00b8 ASJ |
8365 | struct i40e_hw *hw = &pf->hw; |
8366 | u32 reg_val; | |
8367 | u64 hena; | |
e69ff813 | 8368 | int ret; |
e25d00b8 | 8369 | |
41c445ff | 8370 | /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */ |
272cdaf2 SN |
8371 | hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) | |
8372 | ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32); | |
e25d00b8 ASJ |
8373 | hena |= i40e_pf_get_default_rss_hena(pf); |
8374 | ||
272cdaf2 SN |
8375 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena); |
8376 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); | |
41c445ff | 8377 | |
e25d00b8 | 8378 | /* Determine the RSS table size based on the hardware capabilities */ |
272cdaf2 | 8379 | reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); |
e25d00b8 ASJ |
8380 | reg_val = (pf->rss_table_size == 512) ? |
8381 | (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : | |
8382 | (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); | |
272cdaf2 | 8383 | i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); |
e157ea30 | 8384 | |
28c5869f HZ |
8385 | /* Determine the RSS size of the VSI */ |
8386 | if (!vsi->rss_size) | |
acd65448 HZ |
8387 | vsi->rss_size = min_t(int, pf->alloc_rss_size, |
8388 | vsi->num_queue_pairs); | |
a4fa59cc MW |
8389 | if (!vsi->rss_size) |
8390 | return -EINVAL; | |
28c5869f | 8391 | |
e69ff813 HZ |
8392 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
8393 | if (!lut) | |
8394 | return -ENOMEM; | |
8395 | ||
28c5869f HZ |
8396 | /* Use user configured lut if there is one, otherwise use default */ |
8397 | if (vsi->rss_lut_user) | |
8398 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
8399 | else | |
8400 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
e69ff813 | 8401 | |
28c5869f HZ |
8402 | /* Use user configured hash key if there is one, otherwise |
8403 | * use default. | |
8404 | */ | |
8405 | if (vsi->rss_hkey_user) | |
8406 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
8407 | else | |
8408 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
043dd650 | 8409 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); |
e69ff813 HZ |
8410 | kfree(lut); |
8411 | ||
8412 | return ret; | |
41c445ff JB |
8413 | } |
8414 | ||
f8ff1464 ASJ |
8415 | /** |
8416 | * i40e_reconfig_rss_queues - change number of queues for rss and rebuild | |
8417 | * @pf: board private structure | |
8418 | * @queue_count: the requested queue count for rss. | |
8419 | * | |
8420 | * returns 0 if rss is not enabled, if enabled returns the final rss queue | |
8421 | * count which may be different from the requested queue count. | |
8422 | **/ | |
8423 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count) | |
8424 | { | |
9a3bd2f1 ASJ |
8425 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
8426 | int new_rss_size; | |
8427 | ||
f8ff1464 ASJ |
8428 | if (!(pf->flags & I40E_FLAG_RSS_ENABLED)) |
8429 | return 0; | |
8430 | ||
9a3bd2f1 | 8431 | new_rss_size = min_t(int, queue_count, pf->rss_size_max); |
f8ff1464 | 8432 | |
9a3bd2f1 ASJ |
8433 | if (queue_count != vsi->num_queue_pairs) { |
8434 | vsi->req_queue_pairs = queue_count; | |
f8ff1464 ASJ |
8435 | i40e_prep_for_reset(pf); |
8436 | ||
acd65448 | 8437 | pf->alloc_rss_size = new_rss_size; |
f8ff1464 ASJ |
8438 | |
8439 | i40e_reset_and_rebuild(pf, true); | |
28c5869f HZ |
8440 | |
8441 | /* Discard the user configured hash keys and lut, if less | |
8442 | * queues are enabled. | |
8443 | */ | |
8444 | if (queue_count < vsi->rss_size) { | |
8445 | i40e_clear_rss_config_user(vsi); | |
8446 | dev_dbg(&pf->pdev->dev, | |
8447 | "discard user configured hash keys and lut\n"); | |
8448 | } | |
8449 | ||
8450 | /* Reset vsi->rss_size, as number of enabled queues changed */ | |
acd65448 HZ |
8451 | vsi->rss_size = min_t(int, pf->alloc_rss_size, |
8452 | vsi->num_queue_pairs); | |
28c5869f | 8453 | |
043dd650 | 8454 | i40e_pf_config_rss(pf); |
f8ff1464 | 8455 | } |
12815057 LY |
8456 | dev_info(&pf->pdev->dev, "User requested queue count/HW max RSS count: %d/%d\n", |
8457 | vsi->req_queue_pairs, pf->rss_size_max); | |
acd65448 | 8458 | return pf->alloc_rss_size; |
f8ff1464 ASJ |
8459 | } |
8460 | ||
f4492db1 GR |
8461 | /** |
8462 | * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition | |
8463 | * @pf: board private structure | |
8464 | **/ | |
8465 | i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf) | |
8466 | { | |
8467 | i40e_status status; | |
8468 | bool min_valid, max_valid; | |
8469 | u32 max_bw, min_bw; | |
8470 | ||
8471 | status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw, | |
8472 | &min_valid, &max_valid); | |
8473 | ||
8474 | if (!status) { | |
8475 | if (min_valid) | |
8476 | pf->npar_min_bw = min_bw; | |
8477 | if (max_valid) | |
8478 | pf->npar_max_bw = max_bw; | |
8479 | } | |
8480 | ||
8481 | return status; | |
8482 | } | |
8483 | ||
8484 | /** | |
8485 | * i40e_set_npar_bw_setting - Set BW settings for this PF partition | |
8486 | * @pf: board private structure | |
8487 | **/ | |
8488 | i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf) | |
8489 | { | |
8490 | struct i40e_aqc_configure_partition_bw_data bw_data; | |
8491 | i40e_status status; | |
8492 | ||
b40c82e6 | 8493 | /* Set the valid bit for this PF */ |
41a1d04b | 8494 | bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); |
f4492db1 GR |
8495 | bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK; |
8496 | bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK; | |
8497 | ||
8498 | /* Set the new bandwidths */ | |
8499 | status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL); | |
8500 | ||
8501 | return status; | |
8502 | } | |
8503 | ||
8504 | /** | |
8505 | * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition | |
8506 | * @pf: board private structure | |
8507 | **/ | |
8508 | i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf) | |
8509 | { | |
8510 | /* Commit temporary BW setting to permanent NVM image */ | |
8511 | enum i40e_admin_queue_err last_aq_status; | |
8512 | i40e_status ret; | |
8513 | u16 nvm_word; | |
8514 | ||
8515 | if (pf->hw.partition_id != 1) { | |
8516 | dev_info(&pf->pdev->dev, | |
8517 | "Commit BW only works on partition 1! This is partition %d", | |
8518 | pf->hw.partition_id); | |
8519 | ret = I40E_NOT_SUPPORTED; | |
8520 | goto bw_commit_out; | |
8521 | } | |
8522 | ||
8523 | /* Acquire NVM for read access */ | |
8524 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ); | |
8525 | last_aq_status = pf->hw.aq.asq_last_status; | |
8526 | if (ret) { | |
8527 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8528 | "Cannot acquire NVM for read access, err %s aq_err %s\n", |
8529 | i40e_stat_str(&pf->hw, ret), | |
8530 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8531 | goto bw_commit_out; |
8532 | } | |
8533 | ||
8534 | /* Read word 0x10 of NVM - SW compatibility word 1 */ | |
8535 | ret = i40e_aq_read_nvm(&pf->hw, | |
8536 | I40E_SR_NVM_CONTROL_WORD, | |
8537 | 0x10, sizeof(nvm_word), &nvm_word, | |
8538 | false, NULL); | |
8539 | /* Save off last admin queue command status before releasing | |
8540 | * the NVM | |
8541 | */ | |
8542 | last_aq_status = pf->hw.aq.asq_last_status; | |
8543 | i40e_release_nvm(&pf->hw); | |
8544 | if (ret) { | |
f1c7e72e SN |
8545 | dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n", |
8546 | i40e_stat_str(&pf->hw, ret), | |
8547 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8548 | goto bw_commit_out; |
8549 | } | |
8550 | ||
8551 | /* Wait a bit for NVM release to complete */ | |
8552 | msleep(50); | |
8553 | ||
8554 | /* Acquire NVM for write access */ | |
8555 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE); | |
8556 | last_aq_status = pf->hw.aq.asq_last_status; | |
8557 | if (ret) { | |
8558 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8559 | "Cannot acquire NVM for write access, err %s aq_err %s\n", |
8560 | i40e_stat_str(&pf->hw, ret), | |
8561 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8562 | goto bw_commit_out; |
8563 | } | |
8564 | /* Write it back out unchanged to initiate update NVM, | |
8565 | * which will force a write of the shadow (alt) RAM to | |
8566 | * the NVM - thus storing the bandwidth values permanently. | |
8567 | */ | |
8568 | ret = i40e_aq_update_nvm(&pf->hw, | |
8569 | I40E_SR_NVM_CONTROL_WORD, | |
8570 | 0x10, sizeof(nvm_word), | |
8571 | &nvm_word, true, NULL); | |
8572 | /* Save off last admin queue command status before releasing | |
8573 | * the NVM | |
8574 | */ | |
8575 | last_aq_status = pf->hw.aq.asq_last_status; | |
8576 | i40e_release_nvm(&pf->hw); | |
8577 | if (ret) | |
8578 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8579 | "BW settings NOT SAVED, err %s aq_err %s\n", |
8580 | i40e_stat_str(&pf->hw, ret), | |
8581 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8582 | bw_commit_out: |
8583 | ||
8584 | return ret; | |
8585 | } | |
8586 | ||
41c445ff JB |
8587 | /** |
8588 | * i40e_sw_init - Initialize general software structures (struct i40e_pf) | |
8589 | * @pf: board private structure to initialize | |
8590 | * | |
8591 | * i40e_sw_init initializes the Adapter private data structure. | |
8592 | * Fields are initialized based on PCI device information and | |
8593 | * OS network device settings (MTU size). | |
8594 | **/ | |
8595 | static int i40e_sw_init(struct i40e_pf *pf) | |
8596 | { | |
8597 | int err = 0; | |
8598 | int size; | |
8599 | ||
41c445ff JB |
8600 | /* Set default capability flags */ |
8601 | pf->flags = I40E_FLAG_RX_CSUM_ENABLED | | |
8602 | I40E_FLAG_MSI_ENABLED | | |
2bc7ee8a MW |
8603 | I40E_FLAG_MSIX_ENABLED; |
8604 | ||
ca99eb99 MW |
8605 | /* Set default ITR */ |
8606 | pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF; | |
8607 | pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF; | |
8608 | ||
7134f9ce JB |
8609 | /* Depending on PF configurations, it is possible that the RSS |
8610 | * maximum might end up larger than the available queues | |
8611 | */ | |
41a1d04b | 8612 | pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); |
acd65448 | 8613 | pf->alloc_rss_size = 1; |
5db4cb59 | 8614 | pf->rss_table_size = pf->hw.func_caps.rss_table_size; |
7134f9ce JB |
8615 | pf->rss_size_max = min_t(int, pf->rss_size_max, |
8616 | pf->hw.func_caps.num_tx_qp); | |
41c445ff JB |
8617 | if (pf->hw.func_caps.rss) { |
8618 | pf->flags |= I40E_FLAG_RSS_ENABLED; | |
acd65448 HZ |
8619 | pf->alloc_rss_size = min_t(int, pf->rss_size_max, |
8620 | num_online_cpus()); | |
41c445ff JB |
8621 | } |
8622 | ||
2050bc65 | 8623 | /* MFP mode enabled */ |
c78b953e | 8624 | if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) { |
2050bc65 CS |
8625 | pf->flags |= I40E_FLAG_MFP_ENABLED; |
8626 | dev_info(&pf->pdev->dev, "MFP mode Enabled\n"); | |
f4492db1 GR |
8627 | if (i40e_get_npar_bw_setting(pf)) |
8628 | dev_warn(&pf->pdev->dev, | |
8629 | "Could not get NPAR bw settings\n"); | |
8630 | else | |
8631 | dev_info(&pf->pdev->dev, | |
8632 | "Min BW = %8.8x, Max BW = %8.8x\n", | |
8633 | pf->npar_min_bw, pf->npar_max_bw); | |
2050bc65 CS |
8634 | } |
8635 | ||
cbf61325 ASJ |
8636 | /* FW/NVM is not yet fixed in this regard */ |
8637 | if ((pf->hw.func_caps.fd_filters_guaranteed > 0) || | |
8638 | (pf->hw.func_caps.fd_filters_best_effort > 0)) { | |
8639 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
8640 | pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE; | |
6eae9c6a SN |
8641 | if (pf->flags & I40E_FLAG_MFP_ENABLED && |
8642 | pf->hw.num_partitions > 1) | |
cbf61325 | 8643 | dev_info(&pf->pdev->dev, |
0b67584f | 8644 | "Flow Director Sideband mode Disabled in MFP mode\n"); |
6eae9c6a SN |
8645 | else |
8646 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
cbf61325 ASJ |
8647 | pf->fdir_pf_filter_count = |
8648 | pf->hw.func_caps.fd_filters_guaranteed; | |
8649 | pf->hw.fdir_shared_filter_count = | |
8650 | pf->hw.func_caps.fd_filters_best_effort; | |
41c445ff JB |
8651 | } |
8652 | ||
f1bbad33 | 8653 | if (i40e_is_mac_710(&pf->hw) && |
8eed76fa | 8654 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) || |
f1bbad33 | 8655 | (pf->hw.aq.fw_maj_ver < 4))) { |
8eed76fa | 8656 | pf->flags |= I40E_FLAG_RESTART_AUTONEG; |
f1bbad33 NP |
8657 | /* No DCB support for FW < v4.33 */ |
8658 | pf->flags |= I40E_FLAG_NO_DCB_SUPPORT; | |
8659 | } | |
8660 | ||
8661 | /* Disable FW LLDP if FW < v4.3 */ | |
8662 | if (i40e_is_mac_710(&pf->hw) && | |
8663 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) || | |
8664 | (pf->hw.aq.fw_maj_ver < 4))) | |
8665 | pf->flags |= I40E_FLAG_STOP_FW_LLDP; | |
8666 | ||
8667 | /* Use the FW Set LLDP MIB API if FW > v4.40 */ | |
8668 | if (i40e_is_mac_710(&pf->hw) && | |
8669 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) || | |
8670 | (pf->hw.aq.fw_maj_ver >= 5))) | |
8671 | pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB; | |
8eed76fa | 8672 | |
41c445ff | 8673 | if (pf->hw.func_caps.vmdq) { |
41c445ff | 8674 | pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI; |
e25d00b8 | 8675 | pf->flags |= I40E_FLAG_VMDQ_ENABLED; |
e9e53662 | 8676 | pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf); |
41c445ff JB |
8677 | } |
8678 | ||
e3219ce6 ASJ |
8679 | if (pf->hw.func_caps.iwarp) { |
8680 | pf->flags |= I40E_FLAG_IWARP_ENABLED; | |
8681 | /* IWARP needs one extra vector for CQP just like MISC.*/ | |
8682 | pf->num_iwarp_msix = (int)num_online_cpus() + 1; | |
8683 | } | |
8684 | ||
38e00438 | 8685 | #ifdef I40E_FCOE |
21364bcf | 8686 | i40e_init_pf_fcoe(pf); |
38e00438 VD |
8687 | |
8688 | #endif /* I40E_FCOE */ | |
41c445ff | 8689 | #ifdef CONFIG_PCI_IOV |
ba252f13 | 8690 | if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) { |
41c445ff JB |
8691 | pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF; |
8692 | pf->flags |= I40E_FLAG_SRIOV_ENABLED; | |
8693 | pf->num_req_vfs = min_t(int, | |
8694 | pf->hw.func_caps.num_vfs, | |
8695 | I40E_MAX_VF_COUNT); | |
8696 | } | |
8697 | #endif /* CONFIG_PCI_IOV */ | |
d502ce01 ASJ |
8698 | if (pf->hw.mac.type == I40E_MAC_X722) { |
8699 | pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE | | |
8700 | I40E_FLAG_128_QP_RSS_CAPABLE | | |
8701 | I40E_FLAG_HW_ATR_EVICT_CAPABLE | | |
8702 | I40E_FLAG_OUTER_UDP_CSUM_CAPABLE | | |
8703 | I40E_FLAG_WB_ON_ITR_CAPABLE | | |
6a899024 | 8704 | I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE | |
8e2cc0e6 | 8705 | I40E_FLAG_NO_PCI_LINK_CHECK | |
f1bbad33 | 8706 | I40E_FLAG_USE_SET_LLDP_MIB | |
6a899024 | 8707 | I40E_FLAG_GENEVE_OFFLOAD_CAPABLE; |
a340c789 AS |
8708 | } else if ((pf->hw.aq.api_maj_ver > 1) || |
8709 | ((pf->hw.aq.api_maj_ver == 1) && | |
8710 | (pf->hw.aq.api_min_ver > 4))) { | |
8711 | /* Supported in FW API version higher than 1.4 */ | |
8712 | pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE; | |
72b74869 ASJ |
8713 | pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE; |
8714 | } else { | |
8715 | pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE; | |
d502ce01 | 8716 | } |
a340c789 | 8717 | |
41c445ff JB |
8718 | pf->eeprom_version = 0xDEAD; |
8719 | pf->lan_veb = I40E_NO_VEB; | |
8720 | pf->lan_vsi = I40E_NO_VSI; | |
8721 | ||
d1a8d275 ASJ |
8722 | /* By default FW has this off for performance reasons */ |
8723 | pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED; | |
8724 | ||
41c445ff JB |
8725 | /* set up queue assignment tracking */ |
8726 | size = sizeof(struct i40e_lump_tracking) | |
8727 | + (sizeof(u16) * pf->hw.func_caps.num_tx_qp); | |
8728 | pf->qp_pile = kzalloc(size, GFP_KERNEL); | |
8729 | if (!pf->qp_pile) { | |
8730 | err = -ENOMEM; | |
8731 | goto sw_init_done; | |
8732 | } | |
8733 | pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp; | |
8734 | pf->qp_pile->search_hint = 0; | |
8735 | ||
327fe04b ASJ |
8736 | pf->tx_timeout_recovery_level = 1; |
8737 | ||
41c445ff JB |
8738 | mutex_init(&pf->switch_mutex); |
8739 | ||
c668a12c GR |
8740 | /* If NPAR is enabled nudge the Tx scheduler */ |
8741 | if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf))) | |
8742 | i40e_set_npar_bw_setting(pf); | |
8743 | ||
41c445ff JB |
8744 | sw_init_done: |
8745 | return err; | |
8746 | } | |
8747 | ||
7c3c288b ASJ |
8748 | /** |
8749 | * i40e_set_ntuple - set the ntuple feature flag and take action | |
8750 | * @pf: board private structure to initialize | |
8751 | * @features: the feature set that the stack is suggesting | |
8752 | * | |
8753 | * returns a bool to indicate if reset needs to happen | |
8754 | **/ | |
8755 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features) | |
8756 | { | |
8757 | bool need_reset = false; | |
8758 | ||
8759 | /* Check if Flow Director n-tuple support was enabled or disabled. If | |
8760 | * the state changed, we need to reset. | |
8761 | */ | |
8762 | if (features & NETIF_F_NTUPLE) { | |
8763 | /* Enable filters and mark for reset */ | |
8764 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) | |
8765 | need_reset = true; | |
a70e407f TD |
8766 | /* enable FD_SB only if there is MSI-X vector */ |
8767 | if (pf->num_fdsb_msix > 0) | |
8768 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
7c3c288b ASJ |
8769 | } else { |
8770 | /* turn off filters, mark for reset and clear SW filter list */ | |
8771 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
8772 | need_reset = true; | |
8773 | i40e_fdir_filter_exit(pf); | |
8774 | } | |
8775 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
8a4f34fb | 8776 | pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED; |
1e1be8f6 ASJ |
8777 | /* reset fd counters */ |
8778 | pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0; | |
8779 | pf->fdir_pf_active_filters = 0; | |
8a4f34fb ASJ |
8780 | /* if ATR was auto disabled it can be re-enabled. */ |
8781 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
234dc4e6 | 8782 | (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) { |
8a4f34fb | 8783 | pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; |
234dc4e6 JK |
8784 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
8785 | dev_info(&pf->pdev->dev, "ATR re-enabled.\n"); | |
8786 | } | |
7c3c288b ASJ |
8787 | } |
8788 | return need_reset; | |
8789 | } | |
8790 | ||
d8ec9864 AB |
8791 | /** |
8792 | * i40e_clear_rss_lut - clear the rx hash lookup table | |
8793 | * @vsi: the VSI being configured | |
8794 | **/ | |
8795 | static void i40e_clear_rss_lut(struct i40e_vsi *vsi) | |
8796 | { | |
8797 | struct i40e_pf *pf = vsi->back; | |
8798 | struct i40e_hw *hw = &pf->hw; | |
8799 | u16 vf_id = vsi->vf_id; | |
8800 | u8 i; | |
8801 | ||
8802 | if (vsi->type == I40E_VSI_MAIN) { | |
8803 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
8804 | wr32(hw, I40E_PFQF_HLUT(i), 0); | |
8805 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
8806 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
8807 | i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0); | |
8808 | } else { | |
8809 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
8810 | } | |
8811 | } | |
8812 | ||
41c445ff JB |
8813 | /** |
8814 | * i40e_set_features - set the netdev feature flags | |
8815 | * @netdev: ptr to the netdev being adjusted | |
8816 | * @features: the feature set that the stack is suggesting | |
8817 | **/ | |
8818 | static int i40e_set_features(struct net_device *netdev, | |
8819 | netdev_features_t features) | |
8820 | { | |
8821 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8822 | struct i40e_vsi *vsi = np->vsi; | |
7c3c288b ASJ |
8823 | struct i40e_pf *pf = vsi->back; |
8824 | bool need_reset; | |
41c445ff | 8825 | |
d8ec9864 AB |
8826 | if (features & NETIF_F_RXHASH && !(netdev->features & NETIF_F_RXHASH)) |
8827 | i40e_pf_config_rss(pf); | |
8828 | else if (!(features & NETIF_F_RXHASH) && | |
8829 | netdev->features & NETIF_F_RXHASH) | |
8830 | i40e_clear_rss_lut(vsi); | |
8831 | ||
41c445ff JB |
8832 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
8833 | i40e_vlan_stripping_enable(vsi); | |
8834 | else | |
8835 | i40e_vlan_stripping_disable(vsi); | |
8836 | ||
7c3c288b ASJ |
8837 | need_reset = i40e_set_ntuple(pf, features); |
8838 | ||
8839 | if (need_reset) | |
41a1d04b | 8840 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); |
7c3c288b | 8841 | |
41c445ff JB |
8842 | return 0; |
8843 | } | |
8844 | ||
a1c9a9d9 | 8845 | /** |
6a899024 | 8846 | * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port |
a1c9a9d9 JK |
8847 | * @pf: board private structure |
8848 | * @port: The UDP port to look up | |
8849 | * | |
8850 | * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found | |
8851 | **/ | |
6a899024 | 8852 | static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port) |
a1c9a9d9 JK |
8853 | { |
8854 | u8 i; | |
8855 | ||
8856 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
6a899024 | 8857 | if (pf->udp_ports[i].index == port) |
a1c9a9d9 JK |
8858 | return i; |
8859 | } | |
8860 | ||
8861 | return i; | |
8862 | } | |
8863 | ||
8864 | /** | |
06a5f7f1 | 8865 | * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up |
a1c9a9d9 | 8866 | * @netdev: This physical port's netdev |
06a5f7f1 | 8867 | * @ti: Tunnel endpoint information |
a1c9a9d9 | 8868 | **/ |
06a5f7f1 AD |
8869 | static void i40e_udp_tunnel_add(struct net_device *netdev, |
8870 | struct udp_tunnel_info *ti) | |
a1c9a9d9 JK |
8871 | { |
8872 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8873 | struct i40e_vsi *vsi = np->vsi; | |
8874 | struct i40e_pf *pf = vsi->back; | |
06a5f7f1 | 8875 | __be16 port = ti->port; |
a1c9a9d9 JK |
8876 | u8 next_idx; |
8877 | u8 idx; | |
8878 | ||
6a899024 | 8879 | idx = i40e_get_udp_port_idx(pf, port); |
a1c9a9d9 JK |
8880 | |
8881 | /* Check if port already exists */ | |
8882 | if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
06a5f7f1 | 8883 | netdev_info(netdev, "port %d already offloaded\n", |
c22c06c8 | 8884 | ntohs(port)); |
a1c9a9d9 JK |
8885 | return; |
8886 | } | |
8887 | ||
8888 | /* Now check if there is space to add the new port */ | |
6a899024 | 8889 | next_idx = i40e_get_udp_port_idx(pf, 0); |
a1c9a9d9 JK |
8890 | |
8891 | if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
06a5f7f1 | 8892 | netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n", |
6a899024 SA |
8893 | ntohs(port)); |
8894 | return; | |
8895 | } | |
8896 | ||
06a5f7f1 AD |
8897 | switch (ti->type) { |
8898 | case UDP_TUNNEL_TYPE_VXLAN: | |
8899 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN; | |
8900 | break; | |
8901 | case UDP_TUNNEL_TYPE_GENEVE: | |
8902 | if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE)) | |
8903 | return; | |
8904 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE; | |
8905 | break; | |
8906 | default: | |
6a899024 SA |
8907 | return; |
8908 | } | |
8909 | ||
8910 | /* New port: add it and mark its index in the bitmap */ | |
8911 | pf->udp_ports[next_idx].index = port; | |
6a899024 SA |
8912 | pf->pending_udp_bitmap |= BIT_ULL(next_idx); |
8913 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
a1c9a9d9 JK |
8914 | } |
8915 | ||
6a899024 | 8916 | /** |
06a5f7f1 | 8917 | * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away |
6a899024 | 8918 | * @netdev: This physical port's netdev |
06a5f7f1 | 8919 | * @ti: Tunnel endpoint information |
6a899024 | 8920 | **/ |
06a5f7f1 AD |
8921 | static void i40e_udp_tunnel_del(struct net_device *netdev, |
8922 | struct udp_tunnel_info *ti) | |
6a899024 | 8923 | { |
6a899024 SA |
8924 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
8925 | struct i40e_vsi *vsi = np->vsi; | |
8926 | struct i40e_pf *pf = vsi->back; | |
06a5f7f1 | 8927 | __be16 port = ti->port; |
6a899024 SA |
8928 | u8 idx; |
8929 | ||
6a899024 SA |
8930 | idx = i40e_get_udp_port_idx(pf, port); |
8931 | ||
8932 | /* Check if port already exists */ | |
06a5f7f1 AD |
8933 | if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS) |
8934 | goto not_found; | |
6a899024 | 8935 | |
06a5f7f1 AD |
8936 | switch (ti->type) { |
8937 | case UDP_TUNNEL_TYPE_VXLAN: | |
8938 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN) | |
8939 | goto not_found; | |
8940 | break; | |
8941 | case UDP_TUNNEL_TYPE_GENEVE: | |
8942 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE) | |
8943 | goto not_found; | |
8944 | break; | |
8945 | default: | |
8946 | goto not_found; | |
6a899024 | 8947 | } |
06a5f7f1 AD |
8948 | |
8949 | /* if port exists, set it to 0 (mark for deletion) | |
8950 | * and make it pending | |
8951 | */ | |
8952 | pf->udp_ports[idx].index = 0; | |
8953 | pf->pending_udp_bitmap |= BIT_ULL(idx); | |
8954 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
8955 | ||
8956 | return; | |
8957 | not_found: | |
8958 | netdev_warn(netdev, "UDP port %d was not found, not deleting\n", | |
8959 | ntohs(port)); | |
6a899024 SA |
8960 | } |
8961 | ||
1f224ad2 | 8962 | static int i40e_get_phys_port_id(struct net_device *netdev, |
02637fce | 8963 | struct netdev_phys_item_id *ppid) |
1f224ad2 NP |
8964 | { |
8965 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8966 | struct i40e_pf *pf = np->vsi->back; | |
8967 | struct i40e_hw *hw = &pf->hw; | |
8968 | ||
8969 | if (!(pf->flags & I40E_FLAG_PORT_ID_VALID)) | |
8970 | return -EOPNOTSUPP; | |
8971 | ||
8972 | ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id)); | |
8973 | memcpy(ppid->id, hw->mac.port_addr, ppid->id_len); | |
8974 | ||
8975 | return 0; | |
8976 | } | |
8977 | ||
2f90ade6 JB |
8978 | /** |
8979 | * i40e_ndo_fdb_add - add an entry to the hardware database | |
8980 | * @ndm: the input from the stack | |
8981 | * @tb: pointer to array of nladdr (unused) | |
8982 | * @dev: the net device pointer | |
8983 | * @addr: the MAC address entry being added | |
8984 | * @flags: instructions from stack about fdb operation | |
8985 | */ | |
4ba0dea5 GR |
8986 | static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
8987 | struct net_device *dev, | |
f6f6424b | 8988 | const unsigned char *addr, u16 vid, |
4ba0dea5 | 8989 | u16 flags) |
4ba0dea5 GR |
8990 | { |
8991 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
8992 | struct i40e_pf *pf = np->vsi->back; | |
8993 | int err = 0; | |
8994 | ||
8995 | if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED)) | |
8996 | return -EOPNOTSUPP; | |
8997 | ||
65891fea OG |
8998 | if (vid) { |
8999 | pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name); | |
9000 | return -EINVAL; | |
9001 | } | |
9002 | ||
4ba0dea5 GR |
9003 | /* Hardware does not support aging addresses so if a |
9004 | * ndm_state is given only allow permanent addresses | |
9005 | */ | |
9006 | if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { | |
9007 | netdev_info(dev, "FDB only supports static addresses\n"); | |
9008 | return -EINVAL; | |
9009 | } | |
9010 | ||
9011 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) | |
9012 | err = dev_uc_add_excl(dev, addr); | |
9013 | else if (is_multicast_ether_addr(addr)) | |
9014 | err = dev_mc_add_excl(dev, addr); | |
9015 | else | |
9016 | err = -EINVAL; | |
9017 | ||
9018 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
9019 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
9020 | err = 0; | |
9021 | ||
9022 | return err; | |
9023 | } | |
9024 | ||
51616018 NP |
9025 | /** |
9026 | * i40e_ndo_bridge_setlink - Set the hardware bridge mode | |
9027 | * @dev: the netdev being configured | |
9028 | * @nlh: RTNL message | |
9029 | * | |
9030 | * Inserts a new hardware bridge if not already created and | |
9031 | * enables the bridging mode requested (VEB or VEPA). If the | |
9032 | * hardware bridge has already been inserted and the request | |
9033 | * is to change the mode then that requires a PF reset to | |
9034 | * allow rebuild of the components with required hardware | |
9035 | * bridge mode enabled. | |
9036 | **/ | |
9037 | static int i40e_ndo_bridge_setlink(struct net_device *dev, | |
9df70b66 CW |
9038 | struct nlmsghdr *nlh, |
9039 | u16 flags) | |
51616018 NP |
9040 | { |
9041 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
9042 | struct i40e_vsi *vsi = np->vsi; | |
9043 | struct i40e_pf *pf = vsi->back; | |
9044 | struct i40e_veb *veb = NULL; | |
9045 | struct nlattr *attr, *br_spec; | |
9046 | int i, rem; | |
9047 | ||
9048 | /* Only for PF VSI for now */ | |
9049 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
9050 | return -EOPNOTSUPP; | |
9051 | ||
9052 | /* Find the HW bridge for PF VSI */ | |
9053 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
9054 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
9055 | veb = pf->veb[i]; | |
9056 | } | |
9057 | ||
9058 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
9059 | ||
9060 | nla_for_each_nested(attr, br_spec, rem) { | |
9061 | __u16 mode; | |
9062 | ||
9063 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
9064 | continue; | |
9065 | ||
9066 | mode = nla_get_u16(attr); | |
9067 | if ((mode != BRIDGE_MODE_VEPA) && | |
9068 | (mode != BRIDGE_MODE_VEB)) | |
9069 | return -EINVAL; | |
9070 | ||
9071 | /* Insert a new HW bridge */ | |
9072 | if (!veb) { | |
9073 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
9074 | vsi->tc_config.enabled_tc); | |
9075 | if (veb) { | |
9076 | veb->bridge_mode = mode; | |
9077 | i40e_config_bridge_mode(veb); | |
9078 | } else { | |
9079 | /* No Bridge HW offload available */ | |
9080 | return -ENOENT; | |
9081 | } | |
9082 | break; | |
9083 | } else if (mode != veb->bridge_mode) { | |
9084 | /* Existing HW bridge but different mode needs reset */ | |
9085 | veb->bridge_mode = mode; | |
fc60861e ASJ |
9086 | /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */ |
9087 | if (mode == BRIDGE_MODE_VEB) | |
9088 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
9089 | else | |
9090 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
9091 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); | |
51616018 NP |
9092 | break; |
9093 | } | |
9094 | } | |
9095 | ||
9096 | return 0; | |
9097 | } | |
9098 | ||
9099 | /** | |
9100 | * i40e_ndo_bridge_getlink - Get the hardware bridge mode | |
9101 | * @skb: skb buff | |
9102 | * @pid: process id | |
9103 | * @seq: RTNL message seq # | |
9104 | * @dev: the netdev being configured | |
9105 | * @filter_mask: unused | |
d4b2f9fe | 9106 | * @nlflags: netlink flags passed in |
51616018 NP |
9107 | * |
9108 | * Return the mode in which the hardware bridge is operating in | |
9109 | * i.e VEB or VEPA. | |
9110 | **/ | |
51616018 NP |
9111 | static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
9112 | struct net_device *dev, | |
9f4ffc44 CW |
9113 | u32 __always_unused filter_mask, |
9114 | int nlflags) | |
51616018 NP |
9115 | { |
9116 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
9117 | struct i40e_vsi *vsi = np->vsi; | |
9118 | struct i40e_pf *pf = vsi->back; | |
9119 | struct i40e_veb *veb = NULL; | |
9120 | int i; | |
9121 | ||
9122 | /* Only for PF VSI for now */ | |
9123 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
9124 | return -EOPNOTSUPP; | |
9125 | ||
9126 | /* Find the HW bridge for the PF VSI */ | |
9127 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
9128 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
9129 | veb = pf->veb[i]; | |
9130 | } | |
9131 | ||
9132 | if (!veb) | |
9133 | return 0; | |
9134 | ||
46c264da | 9135 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode, |
599b076d | 9136 | 0, 0, nlflags, filter_mask, NULL); |
51616018 | 9137 | } |
51616018 | 9138 | |
f44a75e2 JS |
9139 | /** |
9140 | * i40e_features_check - Validate encapsulated packet conforms to limits | |
9141 | * @skb: skb buff | |
2bc11c63 | 9142 | * @dev: This physical port's netdev |
f44a75e2 JS |
9143 | * @features: Offload features that the stack believes apply |
9144 | **/ | |
9145 | static netdev_features_t i40e_features_check(struct sk_buff *skb, | |
9146 | struct net_device *dev, | |
9147 | netdev_features_t features) | |
9148 | { | |
f114dca2 AD |
9149 | size_t len; |
9150 | ||
9151 | /* No point in doing any of this if neither checksum nor GSO are | |
9152 | * being requested for this frame. We can rule out both by just | |
9153 | * checking for CHECKSUM_PARTIAL | |
9154 | */ | |
9155 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
9156 | return features; | |
9157 | ||
9158 | /* We cannot support GSO if the MSS is going to be less than | |
9159 | * 64 bytes. If it is then we need to drop support for GSO. | |
9160 | */ | |
9161 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_size < 64)) | |
9162 | features &= ~NETIF_F_GSO_MASK; | |
9163 | ||
9164 | /* MACLEN can support at most 63 words */ | |
9165 | len = skb_network_header(skb) - skb->data; | |
9166 | if (len & ~(63 * 2)) | |
9167 | goto out_err; | |
9168 | ||
9169 | /* IPLEN and EIPLEN can support at most 127 dwords */ | |
9170 | len = skb_transport_header(skb) - skb_network_header(skb); | |
9171 | if (len & ~(127 * 4)) | |
9172 | goto out_err; | |
9173 | ||
9174 | if (skb->encapsulation) { | |
9175 | /* L4TUNLEN can support 127 words */ | |
9176 | len = skb_inner_network_header(skb) - skb_transport_header(skb); | |
9177 | if (len & ~(127 * 2)) | |
9178 | goto out_err; | |
9179 | ||
9180 | /* IPLEN can support at most 127 dwords */ | |
9181 | len = skb_inner_transport_header(skb) - | |
9182 | skb_inner_network_header(skb); | |
9183 | if (len & ~(127 * 4)) | |
9184 | goto out_err; | |
9185 | } | |
9186 | ||
9187 | /* No need to validate L4LEN as TCP is the only protocol with a | |
9188 | * a flexible value and we support all possible values supported | |
9189 | * by TCP, which is at most 15 dwords | |
9190 | */ | |
f44a75e2 JS |
9191 | |
9192 | return features; | |
f114dca2 AD |
9193 | out_err: |
9194 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
f44a75e2 JS |
9195 | } |
9196 | ||
37a2973a | 9197 | static const struct net_device_ops i40e_netdev_ops = { |
41c445ff JB |
9198 | .ndo_open = i40e_open, |
9199 | .ndo_stop = i40e_close, | |
9200 | .ndo_start_xmit = i40e_lan_xmit_frame, | |
9201 | .ndo_get_stats64 = i40e_get_netdev_stats_struct, | |
9202 | .ndo_set_rx_mode = i40e_set_rx_mode, | |
9203 | .ndo_validate_addr = eth_validate_addr, | |
9204 | .ndo_set_mac_address = i40e_set_mac, | |
9205 | .ndo_change_mtu = i40e_change_mtu, | |
beb0dff1 | 9206 | .ndo_do_ioctl = i40e_ioctl, |
41c445ff JB |
9207 | .ndo_tx_timeout = i40e_tx_timeout, |
9208 | .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid, | |
9209 | .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid, | |
9210 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
9211 | .ndo_poll_controller = i40e_netpoll, | |
9212 | #endif | |
e4c6734e | 9213 | .ndo_setup_tc = __i40e_setup_tc, |
38e00438 VD |
9214 | #ifdef I40E_FCOE |
9215 | .ndo_fcoe_enable = i40e_fcoe_enable, | |
9216 | .ndo_fcoe_disable = i40e_fcoe_disable, | |
9217 | #endif | |
41c445ff JB |
9218 | .ndo_set_features = i40e_set_features, |
9219 | .ndo_set_vf_mac = i40e_ndo_set_vf_mac, | |
9220 | .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan, | |
ed616689 | 9221 | .ndo_set_vf_rate = i40e_ndo_set_vf_bw, |
41c445ff | 9222 | .ndo_get_vf_config = i40e_ndo_get_vf_config, |
588aefa0 | 9223 | .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state, |
e6d9004d | 9224 | .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk, |
c3bbbd20 | 9225 | .ndo_set_vf_trust = i40e_ndo_set_vf_trust, |
06a5f7f1 AD |
9226 | .ndo_udp_tunnel_add = i40e_udp_tunnel_add, |
9227 | .ndo_udp_tunnel_del = i40e_udp_tunnel_del, | |
1f224ad2 | 9228 | .ndo_get_phys_port_id = i40e_get_phys_port_id, |
4ba0dea5 | 9229 | .ndo_fdb_add = i40e_ndo_fdb_add, |
f44a75e2 | 9230 | .ndo_features_check = i40e_features_check, |
51616018 NP |
9231 | .ndo_bridge_getlink = i40e_ndo_bridge_getlink, |
9232 | .ndo_bridge_setlink = i40e_ndo_bridge_setlink, | |
41c445ff JB |
9233 | }; |
9234 | ||
9235 | /** | |
9236 | * i40e_config_netdev - Setup the netdev flags | |
9237 | * @vsi: the VSI being configured | |
9238 | * | |
9239 | * Returns 0 on success, negative value on failure | |
9240 | **/ | |
9241 | static int i40e_config_netdev(struct i40e_vsi *vsi) | |
9242 | { | |
9243 | struct i40e_pf *pf = vsi->back; | |
9244 | struct i40e_hw *hw = &pf->hw; | |
9245 | struct i40e_netdev_priv *np; | |
9246 | struct net_device *netdev; | |
435c084a | 9247 | u8 broadcast[ETH_ALEN]; |
41c445ff JB |
9248 | u8 mac_addr[ETH_ALEN]; |
9249 | int etherdev_size; | |
9250 | ||
9251 | etherdev_size = sizeof(struct i40e_netdev_priv); | |
f8ff1464 | 9252 | netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs); |
41c445ff JB |
9253 | if (!netdev) |
9254 | return -ENOMEM; | |
9255 | ||
9256 | vsi->netdev = netdev; | |
9257 | np = netdev_priv(netdev); | |
9258 | np->vsi = vsi; | |
9259 | ||
b0fe3306 AD |
9260 | netdev->hw_enc_features |= NETIF_F_SG | |
9261 | NETIF_F_IP_CSUM | | |
9262 | NETIF_F_IPV6_CSUM | | |
9263 | NETIF_F_HIGHDMA | | |
9264 | NETIF_F_SOFT_FEATURES | | |
9265 | NETIF_F_TSO | | |
9266 | NETIF_F_TSO_ECN | | |
9267 | NETIF_F_TSO6 | | |
9268 | NETIF_F_GSO_GRE | | |
1c7b4a23 | 9269 | NETIF_F_GSO_GRE_CSUM | |
7e13318d | 9270 | NETIF_F_GSO_IPXIP4 | |
bf2d1df3 | 9271 | NETIF_F_GSO_IPXIP6 | |
b0fe3306 AD |
9272 | NETIF_F_GSO_UDP_TUNNEL | |
9273 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
1c7b4a23 | 9274 | NETIF_F_GSO_PARTIAL | |
b0fe3306 AD |
9275 | NETIF_F_SCTP_CRC | |
9276 | NETIF_F_RXHASH | | |
9277 | NETIF_F_RXCSUM | | |
5afdaaa0 | 9278 | 0; |
41c445ff | 9279 | |
b0fe3306 | 9280 | if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)) |
1c7b4a23 AD |
9281 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; |
9282 | ||
9283 | netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; | |
b0fe3306 AD |
9284 | |
9285 | /* record features VLANs can make use of */ | |
1c7b4a23 AD |
9286 | netdev->vlan_features |= netdev->hw_enc_features | |
9287 | NETIF_F_TSO_MANGLEID; | |
41c445ff | 9288 | |
2e86a0b6 | 9289 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
b0fe3306 AD |
9290 | netdev->hw_features |= NETIF_F_NTUPLE; |
9291 | ||
9292 | netdev->hw_features |= netdev->hw_enc_features | | |
9293 | NETIF_F_HW_VLAN_CTAG_TX | | |
9294 | NETIF_F_HW_VLAN_CTAG_RX; | |
2e86a0b6 | 9295 | |
b0fe3306 | 9296 | netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; |
1c7b4a23 | 9297 | netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; |
41c445ff JB |
9298 | |
9299 | if (vsi->type == I40E_VSI_MAIN) { | |
9300 | SET_NETDEV_DEV(netdev, &pf->pdev->dev); | |
9a173901 | 9301 | ether_addr_copy(mac_addr, hw->mac.perm_addr); |
1596b5dd JK |
9302 | /* The following steps are necessary to prevent reception |
9303 | * of tagged packets - some older NVM configurations load a | |
9304 | * default a MAC-VLAN filter that accepts any tagged packet | |
9305 | * which must be replaced by a normal filter. | |
9306 | */ | |
9307 | i40e_rm_default_mac_filter(vsi, mac_addr); | |
278e7d0b | 9308 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
1bc87e80 | 9309 | i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY); |
278e7d0b | 9310 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
9311 | } else { |
9312 | /* relate the VSI_VMDQ name to the VSI_MAIN name */ | |
9313 | snprintf(netdev->name, IFNAMSIZ, "%sv%%d", | |
9314 | pf->vsi[pf->lan_vsi]->netdev->name); | |
9315 | random_ether_addr(mac_addr); | |
21659035 | 9316 | |
278e7d0b | 9317 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
1bc87e80 | 9318 | i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY); |
278e7d0b | 9319 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 9320 | } |
21659035 | 9321 | |
435c084a JK |
9322 | /* Add the broadcast filter so that we initially will receive |
9323 | * broadcast packets. Note that when a new VLAN is first added the | |
9324 | * driver will convert all filters marked I40E_VLAN_ANY into VLAN | |
9325 | * specific filters as part of transitioning into "vlan" operation. | |
9326 | * When more VLANs are added, the driver will copy each existing MAC | |
9327 | * filter and add it for the new VLAN. | |
9328 | * | |
9329 | * Broadcast filters are handled specially by | |
9330 | * i40e_sync_filters_subtask, as the driver must to set the broadcast | |
9331 | * promiscuous bit instead of adding this directly as a MAC/VLAN | |
9332 | * filter. The subtask will update the correct broadcast promiscuous | |
9333 | * bits as VLANs become active or inactive. | |
9334 | */ | |
9335 | eth_broadcast_addr(broadcast); | |
9336 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
9337 | i40e_add_filter(vsi, broadcast, I40E_VLAN_ANY); | |
9338 | spin_unlock_bh(&vsi->mac_filter_hash_lock); | |
9339 | ||
9a173901 GR |
9340 | ether_addr_copy(netdev->dev_addr, mac_addr); |
9341 | ether_addr_copy(netdev->perm_addr, mac_addr); | |
b0fe3306 | 9342 | |
41c445ff JB |
9343 | netdev->priv_flags |= IFF_UNICAST_FLT; |
9344 | netdev->priv_flags |= IFF_SUPP_NOFCS; | |
9345 | /* Setup netdev TC information */ | |
9346 | i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc); | |
9347 | ||
9348 | netdev->netdev_ops = &i40e_netdev_ops; | |
9349 | netdev->watchdog_timeo = 5 * HZ; | |
9350 | i40e_set_ethtool_ops(netdev); | |
38e00438 VD |
9351 | #ifdef I40E_FCOE |
9352 | i40e_fcoe_config_netdev(netdev, vsi); | |
9353 | #endif | |
41c445ff | 9354 | |
91c527a5 JW |
9355 | /* MTU range: 68 - 9706 */ |
9356 | netdev->min_mtu = ETH_MIN_MTU; | |
9357 | netdev->max_mtu = I40E_MAX_RXBUFFER - | |
9358 | (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
9359 | ||
41c445ff JB |
9360 | return 0; |
9361 | } | |
9362 | ||
9363 | /** | |
9364 | * i40e_vsi_delete - Delete a VSI from the switch | |
9365 | * @vsi: the VSI being removed | |
9366 | * | |
9367 | * Returns 0 on success, negative value on failure | |
9368 | **/ | |
9369 | static void i40e_vsi_delete(struct i40e_vsi *vsi) | |
9370 | { | |
9371 | /* remove default VSI is not allowed */ | |
9372 | if (vsi == vsi->back->vsi[vsi->back->lan_vsi]) | |
9373 | return; | |
9374 | ||
41c445ff | 9375 | i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL); |
41c445ff JB |
9376 | } |
9377 | ||
51616018 NP |
9378 | /** |
9379 | * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB | |
9380 | * @vsi: the VSI being queried | |
9381 | * | |
9382 | * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode | |
9383 | **/ | |
9384 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi) | |
9385 | { | |
9386 | struct i40e_veb *veb; | |
9387 | struct i40e_pf *pf = vsi->back; | |
9388 | ||
9389 | /* Uplink is not a bridge so default to VEB */ | |
9390 | if (vsi->veb_idx == I40E_NO_VEB) | |
9391 | return 1; | |
9392 | ||
9393 | veb = pf->veb[vsi->veb_idx]; | |
09603eaa AA |
9394 | if (!veb) { |
9395 | dev_info(&pf->pdev->dev, | |
9396 | "There is no veb associated with the bridge\n"); | |
9397 | return -ENOENT; | |
9398 | } | |
9399 | ||
51616018 | 9400 | /* Uplink is a bridge in VEPA mode */ |
09603eaa | 9401 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) { |
51616018 | 9402 | return 0; |
09603eaa AA |
9403 | } else { |
9404 | /* Uplink is a bridge in VEB mode */ | |
9405 | return 1; | |
9406 | } | |
51616018 | 9407 | |
09603eaa AA |
9408 | /* VEPA is now default bridge, so return 0 */ |
9409 | return 0; | |
51616018 NP |
9410 | } |
9411 | ||
41c445ff JB |
9412 | /** |
9413 | * i40e_add_vsi - Add a VSI to the switch | |
9414 | * @vsi: the VSI being configured | |
9415 | * | |
9416 | * This initializes a VSI context depending on the VSI type to be added and | |
9417 | * passes it down to the add_vsi aq command. | |
9418 | **/ | |
9419 | static int i40e_add_vsi(struct i40e_vsi *vsi) | |
9420 | { | |
9421 | int ret = -ENODEV; | |
41c445ff JB |
9422 | struct i40e_pf *pf = vsi->back; |
9423 | struct i40e_hw *hw = &pf->hw; | |
9424 | struct i40e_vsi_context ctxt; | |
278e7d0b JK |
9425 | struct i40e_mac_filter *f; |
9426 | struct hlist_node *h; | |
9427 | int bkt; | |
21659035 | 9428 | |
41c445ff JB |
9429 | u8 enabled_tc = 0x1; /* TC0 enabled */ |
9430 | int f_count = 0; | |
9431 | ||
9432 | memset(&ctxt, 0, sizeof(ctxt)); | |
9433 | switch (vsi->type) { | |
9434 | case I40E_VSI_MAIN: | |
9435 | /* The PF's main VSI is already setup as part of the | |
9436 | * device initialization, so we'll not bother with | |
9437 | * the add_vsi call, but we will retrieve the current | |
9438 | * VSI context. | |
9439 | */ | |
9440 | ctxt.seid = pf->main_vsi_seid; | |
9441 | ctxt.pf_num = pf->hw.pf_id; | |
9442 | ctxt.vf_num = 0; | |
9443 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); | |
9444 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
9445 | if (ret) { | |
9446 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9447 | "couldn't get PF vsi config, err %s aq_err %s\n", |
9448 | i40e_stat_str(&pf->hw, ret), | |
9449 | i40e_aq_str(&pf->hw, | |
9450 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9451 | return -ENOENT; |
9452 | } | |
1a2f6248 | 9453 | vsi->info = ctxt.info; |
41c445ff JB |
9454 | vsi->info.valid_sections = 0; |
9455 | ||
9456 | vsi->seid = ctxt.seid; | |
9457 | vsi->id = ctxt.vsi_number; | |
9458 | ||
9459 | enabled_tc = i40e_pf_get_tc_map(pf); | |
9460 | ||
9461 | /* MFP mode setup queue map and update VSI */ | |
63d7e5a4 NP |
9462 | if ((pf->flags & I40E_FLAG_MFP_ENABLED) && |
9463 | !(pf->hw.func_caps.iscsi)) { /* NIC type PF */ | |
41c445ff JB |
9464 | memset(&ctxt, 0, sizeof(ctxt)); |
9465 | ctxt.seid = pf->main_vsi_seid; | |
9466 | ctxt.pf_num = pf->hw.pf_id; | |
9467 | ctxt.vf_num = 0; | |
9468 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
9469 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
9470 | if (ret) { | |
9471 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9472 | "update vsi failed, err %s aq_err %s\n", |
9473 | i40e_stat_str(&pf->hw, ret), | |
9474 | i40e_aq_str(&pf->hw, | |
9475 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9476 | ret = -ENOENT; |
9477 | goto err; | |
9478 | } | |
9479 | /* update the local VSI info queue map */ | |
9480 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
9481 | vsi->info.valid_sections = 0; | |
9482 | } else { | |
9483 | /* Default/Main VSI is only enabled for TC0 | |
9484 | * reconfigure it to enable all TCs that are | |
9485 | * available on the port in SFP mode. | |
63d7e5a4 NP |
9486 | * For MFP case the iSCSI PF would use this |
9487 | * flow to enable LAN+iSCSI TC. | |
41c445ff JB |
9488 | */ |
9489 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
9490 | if (ret) { | |
9491 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9492 | "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n", |
9493 | enabled_tc, | |
9494 | i40e_stat_str(&pf->hw, ret), | |
9495 | i40e_aq_str(&pf->hw, | |
9496 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9497 | ret = -ENOENT; |
9498 | } | |
9499 | } | |
9500 | break; | |
9501 | ||
9502 | case I40E_VSI_FDIR: | |
cbf61325 ASJ |
9503 | ctxt.pf_num = hw->pf_id; |
9504 | ctxt.vf_num = 0; | |
9505 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 9506 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
cbf61325 | 9507 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; |
fc60861e ASJ |
9508 | if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) && |
9509 | (i40e_is_vsi_uplink_mode_veb(vsi))) { | |
51616018 | 9510 | ctxt.info.valid_sections |= |
fc60861e | 9511 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); |
51616018 | 9512 | ctxt.info.switch_id = |
fc60861e | 9513 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); |
51616018 | 9514 | } |
41c445ff | 9515 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); |
41c445ff JB |
9516 | break; |
9517 | ||
9518 | case I40E_VSI_VMDQ2: | |
9519 | ctxt.pf_num = hw->pf_id; | |
9520 | ctxt.vf_num = 0; | |
9521 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 9522 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
9523 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; |
9524 | ||
41c445ff JB |
9525 | /* This VSI is connected to VEB so the switch_id |
9526 | * should be set to zero by default. | |
9527 | */ | |
51616018 NP |
9528 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
9529 | ctxt.info.valid_sections |= | |
9530 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
9531 | ctxt.info.switch_id = | |
9532 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
9533 | } | |
41c445ff JB |
9534 | |
9535 | /* Setup the VSI tx/rx queue map for TC0 only for now */ | |
9536 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
9537 | break; | |
9538 | ||
9539 | case I40E_VSI_SRIOV: | |
9540 | ctxt.pf_num = hw->pf_id; | |
9541 | ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id; | |
9542 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 9543 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
9544 | ctxt.flags = I40E_AQ_VSI_TYPE_VF; |
9545 | ||
41c445ff JB |
9546 | /* This VSI is connected to VEB so the switch_id |
9547 | * should be set to zero by default. | |
9548 | */ | |
51616018 NP |
9549 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
9550 | ctxt.info.valid_sections |= | |
9551 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
9552 | ctxt.info.switch_id = | |
9553 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
9554 | } | |
41c445ff | 9555 | |
e3219ce6 ASJ |
9556 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
9557 | ctxt.info.valid_sections |= | |
9558 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
9559 | ctxt.info.queueing_opt_flags |= | |
4b28cdba AS |
9560 | (I40E_AQ_VSI_QUE_OPT_TCP_ENA | |
9561 | I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI); | |
e3219ce6 ASJ |
9562 | } |
9563 | ||
41c445ff JB |
9564 | ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); |
9565 | ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; | |
c674d125 MW |
9566 | if (pf->vf[vsi->vf_id].spoofchk) { |
9567 | ctxt.info.valid_sections |= | |
9568 | cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID); | |
9569 | ctxt.info.sec_flags |= | |
9570 | (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK | | |
9571 | I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK); | |
9572 | } | |
41c445ff JB |
9573 | /* Setup the VSI tx/rx queue map for TC0 only for now */ |
9574 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
9575 | break; | |
9576 | ||
38e00438 VD |
9577 | #ifdef I40E_FCOE |
9578 | case I40E_VSI_FCOE: | |
9579 | ret = i40e_fcoe_vsi_init(vsi, &ctxt); | |
9580 | if (ret) { | |
9581 | dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n"); | |
9582 | return ret; | |
9583 | } | |
9584 | break; | |
9585 | ||
9586 | #endif /* I40E_FCOE */ | |
e3219ce6 ASJ |
9587 | case I40E_VSI_IWARP: |
9588 | /* send down message to iWARP */ | |
9589 | break; | |
9590 | ||
41c445ff JB |
9591 | default: |
9592 | return -ENODEV; | |
9593 | } | |
9594 | ||
9595 | if (vsi->type != I40E_VSI_MAIN) { | |
9596 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
9597 | if (ret) { | |
9598 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
9599 | "add vsi failed, err %s aq_err %s\n", |
9600 | i40e_stat_str(&pf->hw, ret), | |
9601 | i40e_aq_str(&pf->hw, | |
9602 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9603 | ret = -ENOENT; |
9604 | goto err; | |
9605 | } | |
1a2f6248 | 9606 | vsi->info = ctxt.info; |
41c445ff JB |
9607 | vsi->info.valid_sections = 0; |
9608 | vsi->seid = ctxt.seid; | |
9609 | vsi->id = ctxt.vsi_number; | |
9610 | } | |
9611 | ||
c3c7ea27 MW |
9612 | vsi->active_filters = 0; |
9613 | clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); | |
278e7d0b | 9614 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 9615 | /* If macvlan filters already exist, force them to get loaded */ |
278e7d0b | 9616 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 9617 | f->state = I40E_FILTER_NEW; |
41c445ff | 9618 | f_count++; |
21659035 | 9619 | } |
278e7d0b | 9620 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
30650cc5 | 9621 | |
41c445ff JB |
9622 | if (f_count) { |
9623 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
9624 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
9625 | } | |
9626 | ||
9627 | /* Update VSI BW information */ | |
9628 | ret = i40e_vsi_get_bw_info(vsi); | |
9629 | if (ret) { | |
9630 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9631 | "couldn't get vsi bw info, err %s aq_err %s\n", |
9632 | i40e_stat_str(&pf->hw, ret), | |
9633 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9634 | /* VSI is already added so not tearing that up */ |
9635 | ret = 0; | |
9636 | } | |
9637 | ||
9638 | err: | |
9639 | return ret; | |
9640 | } | |
9641 | ||
9642 | /** | |
9643 | * i40e_vsi_release - Delete a VSI and free its resources | |
9644 | * @vsi: the VSI being removed | |
9645 | * | |
9646 | * Returns 0 on success or < 0 on error | |
9647 | **/ | |
9648 | int i40e_vsi_release(struct i40e_vsi *vsi) | |
9649 | { | |
278e7d0b JK |
9650 | struct i40e_mac_filter *f; |
9651 | struct hlist_node *h; | |
41c445ff JB |
9652 | struct i40e_veb *veb = NULL; |
9653 | struct i40e_pf *pf; | |
9654 | u16 uplink_seid; | |
278e7d0b | 9655 | int i, n, bkt; |
41c445ff JB |
9656 | |
9657 | pf = vsi->back; | |
9658 | ||
9659 | /* release of a VEB-owner or last VSI is not allowed */ | |
9660 | if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
9661 | dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n", | |
9662 | vsi->seid, vsi->uplink_seid); | |
9663 | return -ENODEV; | |
9664 | } | |
9665 | if (vsi == pf->vsi[pf->lan_vsi] && | |
9666 | !test_bit(__I40E_DOWN, &pf->state)) { | |
9667 | dev_info(&pf->pdev->dev, "Can't remove PF VSI\n"); | |
9668 | return -ENODEV; | |
9669 | } | |
9670 | ||
9671 | uplink_seid = vsi->uplink_seid; | |
9672 | if (vsi->type != I40E_VSI_SRIOV) { | |
9673 | if (vsi->netdev_registered) { | |
9674 | vsi->netdev_registered = false; | |
9675 | if (vsi->netdev) { | |
9676 | /* results in a call to i40e_close() */ | |
9677 | unregister_netdev(vsi->netdev); | |
41c445ff JB |
9678 | } |
9679 | } else { | |
90ef8d47 | 9680 | i40e_vsi_close(vsi); |
41c445ff JB |
9681 | } |
9682 | i40e_vsi_disable_irq(vsi); | |
9683 | } | |
9684 | ||
278e7d0b | 9685 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
6622f5cd JK |
9686 | |
9687 | /* clear the sync flag on all filters */ | |
9688 | if (vsi->netdev) { | |
9689 | __dev_uc_unsync(vsi->netdev, NULL); | |
9690 | __dev_mc_unsync(vsi->netdev, NULL); | |
9691 | } | |
9692 | ||
9693 | /* make sure any remaining filters are marked for deletion */ | |
278e7d0b | 9694 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) |
290d2557 | 9695 | __i40e_del_filter(vsi, f); |
6622f5cd | 9696 | |
278e7d0b | 9697 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 9698 | |
17652c63 | 9699 | i40e_sync_vsi_filters(vsi); |
41c445ff JB |
9700 | |
9701 | i40e_vsi_delete(vsi); | |
9702 | i40e_vsi_free_q_vectors(vsi); | |
a4866597 SN |
9703 | if (vsi->netdev) { |
9704 | free_netdev(vsi->netdev); | |
9705 | vsi->netdev = NULL; | |
9706 | } | |
41c445ff JB |
9707 | i40e_vsi_clear_rings(vsi); |
9708 | i40e_vsi_clear(vsi); | |
9709 | ||
9710 | /* If this was the last thing on the VEB, except for the | |
9711 | * controlling VSI, remove the VEB, which puts the controlling | |
9712 | * VSI onto the next level down in the switch. | |
9713 | * | |
9714 | * Well, okay, there's one more exception here: don't remove | |
9715 | * the orphan VEBs yet. We'll wait for an explicit remove request | |
9716 | * from up the network stack. | |
9717 | */ | |
505682cd | 9718 | for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
9719 | if (pf->vsi[i] && |
9720 | pf->vsi[i]->uplink_seid == uplink_seid && | |
9721 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
9722 | n++; /* count the VSIs */ | |
9723 | } | |
9724 | } | |
9725 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
9726 | if (!pf->veb[i]) | |
9727 | continue; | |
9728 | if (pf->veb[i]->uplink_seid == uplink_seid) | |
9729 | n++; /* count the VEBs */ | |
9730 | if (pf->veb[i]->seid == uplink_seid) | |
9731 | veb = pf->veb[i]; | |
9732 | } | |
9733 | if (n == 0 && veb && veb->uplink_seid != 0) | |
9734 | i40e_veb_release(veb); | |
9735 | ||
9736 | return 0; | |
9737 | } | |
9738 | ||
9739 | /** | |
9740 | * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI | |
9741 | * @vsi: ptr to the VSI | |
9742 | * | |
9743 | * This should only be called after i40e_vsi_mem_alloc() which allocates the | |
9744 | * corresponding SW VSI structure and initializes num_queue_pairs for the | |
9745 | * newly allocated VSI. | |
9746 | * | |
9747 | * Returns 0 on success or negative on failure | |
9748 | **/ | |
9749 | static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi) | |
9750 | { | |
9751 | int ret = -ENOENT; | |
9752 | struct i40e_pf *pf = vsi->back; | |
9753 | ||
493fb300 | 9754 | if (vsi->q_vectors[0]) { |
41c445ff JB |
9755 | dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n", |
9756 | vsi->seid); | |
9757 | return -EEXIST; | |
9758 | } | |
9759 | ||
9760 | if (vsi->base_vector) { | |
f29eaa3d | 9761 | dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n", |
41c445ff JB |
9762 | vsi->seid, vsi->base_vector); |
9763 | return -EEXIST; | |
9764 | } | |
9765 | ||
90e04070 | 9766 | ret = i40e_vsi_alloc_q_vectors(vsi); |
41c445ff JB |
9767 | if (ret) { |
9768 | dev_info(&pf->pdev->dev, | |
9769 | "failed to allocate %d q_vector for VSI %d, ret=%d\n", | |
9770 | vsi->num_q_vectors, vsi->seid, ret); | |
9771 | vsi->num_q_vectors = 0; | |
9772 | goto vector_setup_out; | |
9773 | } | |
9774 | ||
26cdc443 ASJ |
9775 | /* In Legacy mode, we do not have to get any other vector since we |
9776 | * piggyback on the misc/ICR0 for queue interrupts. | |
9777 | */ | |
9778 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
9779 | return ret; | |
958a3e3b SN |
9780 | if (vsi->num_q_vectors) |
9781 | vsi->base_vector = i40e_get_lump(pf, pf->irq_pile, | |
9782 | vsi->num_q_vectors, vsi->idx); | |
41c445ff JB |
9783 | if (vsi->base_vector < 0) { |
9784 | dev_info(&pf->pdev->dev, | |
049a2be8 SN |
9785 | "failed to get tracking for %d vectors for VSI %d, err=%d\n", |
9786 | vsi->num_q_vectors, vsi->seid, vsi->base_vector); | |
41c445ff JB |
9787 | i40e_vsi_free_q_vectors(vsi); |
9788 | ret = -ENOENT; | |
9789 | goto vector_setup_out; | |
9790 | } | |
9791 | ||
9792 | vector_setup_out: | |
9793 | return ret; | |
9794 | } | |
9795 | ||
bc7d338f ASJ |
9796 | /** |
9797 | * i40e_vsi_reinit_setup - return and reallocate resources for a VSI | |
9798 | * @vsi: pointer to the vsi. | |
9799 | * | |
9800 | * This re-allocates a vsi's queue resources. | |
9801 | * | |
9802 | * Returns pointer to the successfully allocated and configured VSI sw struct | |
9803 | * on success, otherwise returns NULL on failure. | |
9804 | **/ | |
9805 | static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi) | |
9806 | { | |
f534039d | 9807 | struct i40e_pf *pf; |
bc7d338f ASJ |
9808 | u8 enabled_tc; |
9809 | int ret; | |
9810 | ||
f534039d JU |
9811 | if (!vsi) |
9812 | return NULL; | |
9813 | ||
9814 | pf = vsi->back; | |
9815 | ||
bc7d338f ASJ |
9816 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
9817 | i40e_vsi_clear_rings(vsi); | |
9818 | ||
9819 | i40e_vsi_free_arrays(vsi, false); | |
9820 | i40e_set_num_rings_in_vsi(vsi); | |
9821 | ret = i40e_vsi_alloc_arrays(vsi, false); | |
9822 | if (ret) | |
9823 | goto err_vsi; | |
9824 | ||
9825 | ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx); | |
9826 | if (ret < 0) { | |
049a2be8 | 9827 | dev_info(&pf->pdev->dev, |
f1c7e72e | 9828 | "failed to get tracking for %d queues for VSI %d err %d\n", |
049a2be8 | 9829 | vsi->alloc_queue_pairs, vsi->seid, ret); |
bc7d338f ASJ |
9830 | goto err_vsi; |
9831 | } | |
9832 | vsi->base_queue = ret; | |
9833 | ||
9834 | /* Update the FW view of the VSI. Force a reset of TC and queue | |
9835 | * layout configurations. | |
9836 | */ | |
9837 | enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
9838 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; | |
9839 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
9840 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
1596b5dd JK |
9841 | if (vsi->type == I40E_VSI_MAIN) |
9842 | i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr); | |
bc7d338f ASJ |
9843 | |
9844 | /* assign it some queues */ | |
9845 | ret = i40e_alloc_rings(vsi); | |
9846 | if (ret) | |
9847 | goto err_rings; | |
9848 | ||
9849 | /* map all of the rings to the q_vectors */ | |
9850 | i40e_vsi_map_rings_to_vectors(vsi); | |
9851 | return vsi; | |
9852 | ||
9853 | err_rings: | |
9854 | i40e_vsi_free_q_vectors(vsi); | |
9855 | if (vsi->netdev_registered) { | |
9856 | vsi->netdev_registered = false; | |
9857 | unregister_netdev(vsi->netdev); | |
9858 | free_netdev(vsi->netdev); | |
9859 | vsi->netdev = NULL; | |
9860 | } | |
9861 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
9862 | err_vsi: | |
9863 | i40e_vsi_clear(vsi); | |
9864 | return NULL; | |
9865 | } | |
9866 | ||
41c445ff JB |
9867 | /** |
9868 | * i40e_vsi_setup - Set up a VSI by a given type | |
9869 | * @pf: board private structure | |
9870 | * @type: VSI type | |
9871 | * @uplink_seid: the switch element to link to | |
9872 | * @param1: usage depends upon VSI type. For VF types, indicates VF id | |
9873 | * | |
9874 | * This allocates the sw VSI structure and its queue resources, then add a VSI | |
9875 | * to the identified VEB. | |
9876 | * | |
9877 | * Returns pointer to the successfully allocated and configure VSI sw struct on | |
9878 | * success, otherwise returns NULL on failure. | |
9879 | **/ | |
9880 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, | |
9881 | u16 uplink_seid, u32 param1) | |
9882 | { | |
9883 | struct i40e_vsi *vsi = NULL; | |
9884 | struct i40e_veb *veb = NULL; | |
9885 | int ret, i; | |
9886 | int v_idx; | |
9887 | ||
9888 | /* The requested uplink_seid must be either | |
9889 | * - the PF's port seid | |
9890 | * no VEB is needed because this is the PF | |
9891 | * or this is a Flow Director special case VSI | |
9892 | * - seid of an existing VEB | |
9893 | * - seid of a VSI that owns an existing VEB | |
9894 | * - seid of a VSI that doesn't own a VEB | |
9895 | * a new VEB is created and the VSI becomes the owner | |
9896 | * - seid of the PF VSI, which is what creates the first VEB | |
9897 | * this is a special case of the previous | |
9898 | * | |
9899 | * Find which uplink_seid we were given and create a new VEB if needed | |
9900 | */ | |
9901 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
9902 | if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) { | |
9903 | veb = pf->veb[i]; | |
9904 | break; | |
9905 | } | |
9906 | } | |
9907 | ||
9908 | if (!veb && uplink_seid != pf->mac_seid) { | |
9909 | ||
505682cd | 9910 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
9911 | if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) { |
9912 | vsi = pf->vsi[i]; | |
9913 | break; | |
9914 | } | |
9915 | } | |
9916 | if (!vsi) { | |
9917 | dev_info(&pf->pdev->dev, "no such uplink_seid %d\n", | |
9918 | uplink_seid); | |
9919 | return NULL; | |
9920 | } | |
9921 | ||
9922 | if (vsi->uplink_seid == pf->mac_seid) | |
9923 | veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid, | |
9924 | vsi->tc_config.enabled_tc); | |
9925 | else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) | |
9926 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
9927 | vsi->tc_config.enabled_tc); | |
79c21a82 ASJ |
9928 | if (veb) { |
9929 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) { | |
9930 | dev_info(&vsi->back->pdev->dev, | |
fb43201f | 9931 | "New VSI creation error, uplink seid of LAN VSI expected.\n"); |
79c21a82 ASJ |
9932 | return NULL; |
9933 | } | |
fa11cb3d ASJ |
9934 | /* We come up by default in VEPA mode if SRIOV is not |
9935 | * already enabled, in which case we can't force VEPA | |
9936 | * mode. | |
9937 | */ | |
9938 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
9939 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
9940 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
9941 | } | |
51616018 | 9942 | i40e_config_bridge_mode(veb); |
79c21a82 | 9943 | } |
41c445ff JB |
9944 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { |
9945 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
9946 | veb = pf->veb[i]; | |
9947 | } | |
9948 | if (!veb) { | |
9949 | dev_info(&pf->pdev->dev, "couldn't add VEB\n"); | |
9950 | return NULL; | |
9951 | } | |
9952 | ||
9953 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
9954 | uplink_seid = veb->seid; | |
9955 | } | |
9956 | ||
9957 | /* get vsi sw struct */ | |
9958 | v_idx = i40e_vsi_mem_alloc(pf, type); | |
9959 | if (v_idx < 0) | |
9960 | goto err_alloc; | |
9961 | vsi = pf->vsi[v_idx]; | |
cbf61325 ASJ |
9962 | if (!vsi) |
9963 | goto err_alloc; | |
41c445ff JB |
9964 | vsi->type = type; |
9965 | vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB); | |
9966 | ||
9967 | if (type == I40E_VSI_MAIN) | |
9968 | pf->lan_vsi = v_idx; | |
9969 | else if (type == I40E_VSI_SRIOV) | |
9970 | vsi->vf_id = param1; | |
9971 | /* assign it some queues */ | |
cbf61325 ASJ |
9972 | ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, |
9973 | vsi->idx); | |
41c445ff | 9974 | if (ret < 0) { |
049a2be8 SN |
9975 | dev_info(&pf->pdev->dev, |
9976 | "failed to get tracking for %d queues for VSI %d err=%d\n", | |
9977 | vsi->alloc_queue_pairs, vsi->seid, ret); | |
41c445ff JB |
9978 | goto err_vsi; |
9979 | } | |
9980 | vsi->base_queue = ret; | |
9981 | ||
9982 | /* get a VSI from the hardware */ | |
9983 | vsi->uplink_seid = uplink_seid; | |
9984 | ret = i40e_add_vsi(vsi); | |
9985 | if (ret) | |
9986 | goto err_vsi; | |
9987 | ||
9988 | switch (vsi->type) { | |
9989 | /* setup the netdev if needed */ | |
9990 | case I40E_VSI_MAIN: | |
b499ffb0 SV |
9991 | /* Apply relevant filters if a platform-specific mac |
9992 | * address was selected. | |
9993 | */ | |
9994 | if (!!(pf->flags & I40E_FLAG_PF_MAC)) { | |
9995 | ret = i40e_macaddr_init(vsi, pf->hw.mac.addr); | |
9996 | if (ret) { | |
9997 | dev_warn(&pf->pdev->dev, | |
9998 | "could not set up macaddr; err %d\n", | |
9999 | ret); | |
10000 | } | |
10001 | } | |
41c445ff | 10002 | case I40E_VSI_VMDQ2: |
38e00438 | 10003 | case I40E_VSI_FCOE: |
41c445ff JB |
10004 | ret = i40e_config_netdev(vsi); |
10005 | if (ret) | |
10006 | goto err_netdev; | |
10007 | ret = register_netdev(vsi->netdev); | |
10008 | if (ret) | |
10009 | goto err_netdev; | |
10010 | vsi->netdev_registered = true; | |
10011 | netif_carrier_off(vsi->netdev); | |
4e3b35b0 NP |
10012 | #ifdef CONFIG_I40E_DCB |
10013 | /* Setup DCB netlink interface */ | |
10014 | i40e_dcbnl_setup(vsi); | |
10015 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
10016 | /* fall through */ |
10017 | ||
10018 | case I40E_VSI_FDIR: | |
10019 | /* set up vectors and rings if needed */ | |
10020 | ret = i40e_vsi_setup_vectors(vsi); | |
10021 | if (ret) | |
10022 | goto err_msix; | |
10023 | ||
10024 | ret = i40e_alloc_rings(vsi); | |
10025 | if (ret) | |
10026 | goto err_rings; | |
10027 | ||
10028 | /* map all of the rings to the q_vectors */ | |
10029 | i40e_vsi_map_rings_to_vectors(vsi); | |
10030 | ||
10031 | i40e_vsi_reset_stats(vsi); | |
10032 | break; | |
10033 | ||
10034 | default: | |
10035 | /* no netdev or rings for the other VSI types */ | |
10036 | break; | |
10037 | } | |
10038 | ||
e25d00b8 ASJ |
10039 | if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) && |
10040 | (vsi->type == I40E_VSI_VMDQ2)) { | |
10041 | ret = i40e_vsi_config_rss(vsi); | |
10042 | } | |
41c445ff JB |
10043 | return vsi; |
10044 | ||
10045 | err_rings: | |
10046 | i40e_vsi_free_q_vectors(vsi); | |
10047 | err_msix: | |
10048 | if (vsi->netdev_registered) { | |
10049 | vsi->netdev_registered = false; | |
10050 | unregister_netdev(vsi->netdev); | |
10051 | free_netdev(vsi->netdev); | |
10052 | vsi->netdev = NULL; | |
10053 | } | |
10054 | err_netdev: | |
10055 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
10056 | err_vsi: | |
10057 | i40e_vsi_clear(vsi); | |
10058 | err_alloc: | |
10059 | return NULL; | |
10060 | } | |
10061 | ||
10062 | /** | |
10063 | * i40e_veb_get_bw_info - Query VEB BW information | |
10064 | * @veb: the veb to query | |
10065 | * | |
10066 | * Query the Tx scheduler BW configuration data for given VEB | |
10067 | **/ | |
10068 | static int i40e_veb_get_bw_info(struct i40e_veb *veb) | |
10069 | { | |
10070 | struct i40e_aqc_query_switching_comp_ets_config_resp ets_data; | |
10071 | struct i40e_aqc_query_switching_comp_bw_config_resp bw_data; | |
10072 | struct i40e_pf *pf = veb->pf; | |
10073 | struct i40e_hw *hw = &pf->hw; | |
10074 | u32 tc_bw_max; | |
10075 | int ret = 0; | |
10076 | int i; | |
10077 | ||
10078 | ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, | |
10079 | &bw_data, NULL); | |
10080 | if (ret) { | |
10081 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10082 | "query veb bw config failed, err %s aq_err %s\n", |
10083 | i40e_stat_str(&pf->hw, ret), | |
10084 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
10085 | goto out; |
10086 | } | |
10087 | ||
10088 | ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, | |
10089 | &ets_data, NULL); | |
10090 | if (ret) { | |
10091 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10092 | "query veb bw ets config failed, err %s aq_err %s\n", |
10093 | i40e_stat_str(&pf->hw, ret), | |
10094 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
10095 | goto out; |
10096 | } | |
10097 | ||
10098 | veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit); | |
10099 | veb->bw_max_quanta = ets_data.tc_bw_max; | |
10100 | veb->is_abs_credits = bw_data.absolute_credits_enable; | |
23cd1f09 | 10101 | veb->enabled_tc = ets_data.tc_valid_bits; |
41c445ff JB |
10102 | tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) | |
10103 | (le16_to_cpu(bw_data.tc_bw_max[1]) << 16); | |
10104 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
10105 | veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i]; | |
10106 | veb->bw_tc_limit_credits[i] = | |
10107 | le16_to_cpu(bw_data.tc_bw_limits[i]); | |
10108 | veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7); | |
10109 | } | |
10110 | ||
10111 | out: | |
10112 | return ret; | |
10113 | } | |
10114 | ||
10115 | /** | |
10116 | * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF | |
10117 | * @pf: board private structure | |
10118 | * | |
10119 | * On error: returns error code (negative) | |
10120 | * On success: returns vsi index in PF (positive) | |
10121 | **/ | |
10122 | static int i40e_veb_mem_alloc(struct i40e_pf *pf) | |
10123 | { | |
10124 | int ret = -ENOENT; | |
10125 | struct i40e_veb *veb; | |
10126 | int i; | |
10127 | ||
10128 | /* Need to protect the allocation of switch elements at the PF level */ | |
10129 | mutex_lock(&pf->switch_mutex); | |
10130 | ||
10131 | /* VEB list may be fragmented if VEB creation/destruction has | |
10132 | * been happening. We can afford to do a quick scan to look | |
10133 | * for any free slots in the list. | |
10134 | * | |
10135 | * find next empty veb slot, looping back around if necessary | |
10136 | */ | |
10137 | i = 0; | |
10138 | while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL)) | |
10139 | i++; | |
10140 | if (i >= I40E_MAX_VEB) { | |
10141 | ret = -ENOMEM; | |
10142 | goto err_alloc_veb; /* out of VEB slots! */ | |
10143 | } | |
10144 | ||
10145 | veb = kzalloc(sizeof(*veb), GFP_KERNEL); | |
10146 | if (!veb) { | |
10147 | ret = -ENOMEM; | |
10148 | goto err_alloc_veb; | |
10149 | } | |
10150 | veb->pf = pf; | |
10151 | veb->idx = i; | |
10152 | veb->enabled_tc = 1; | |
10153 | ||
10154 | pf->veb[i] = veb; | |
10155 | ret = i; | |
10156 | err_alloc_veb: | |
10157 | mutex_unlock(&pf->switch_mutex); | |
10158 | return ret; | |
10159 | } | |
10160 | ||
10161 | /** | |
10162 | * i40e_switch_branch_release - Delete a branch of the switch tree | |
10163 | * @branch: where to start deleting | |
10164 | * | |
10165 | * This uses recursion to find the tips of the branch to be | |
10166 | * removed, deleting until we get back to and can delete this VEB. | |
10167 | **/ | |
10168 | static void i40e_switch_branch_release(struct i40e_veb *branch) | |
10169 | { | |
10170 | struct i40e_pf *pf = branch->pf; | |
10171 | u16 branch_seid = branch->seid; | |
10172 | u16 veb_idx = branch->idx; | |
10173 | int i; | |
10174 | ||
10175 | /* release any VEBs on this VEB - RECURSION */ | |
10176 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
10177 | if (!pf->veb[i]) | |
10178 | continue; | |
10179 | if (pf->veb[i]->uplink_seid == branch->seid) | |
10180 | i40e_switch_branch_release(pf->veb[i]); | |
10181 | } | |
10182 | ||
10183 | /* Release the VSIs on this VEB, but not the owner VSI. | |
10184 | * | |
10185 | * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing | |
10186 | * the VEB itself, so don't use (*branch) after this loop. | |
10187 | */ | |
505682cd | 10188 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
10189 | if (!pf->vsi[i]) |
10190 | continue; | |
10191 | if (pf->vsi[i]->uplink_seid == branch_seid && | |
10192 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
10193 | i40e_vsi_release(pf->vsi[i]); | |
10194 | } | |
10195 | } | |
10196 | ||
10197 | /* There's one corner case where the VEB might not have been | |
10198 | * removed, so double check it here and remove it if needed. | |
10199 | * This case happens if the veb was created from the debugfs | |
10200 | * commands and no VSIs were added to it. | |
10201 | */ | |
10202 | if (pf->veb[veb_idx]) | |
10203 | i40e_veb_release(pf->veb[veb_idx]); | |
10204 | } | |
10205 | ||
10206 | /** | |
10207 | * i40e_veb_clear - remove veb struct | |
10208 | * @veb: the veb to remove | |
10209 | **/ | |
10210 | static void i40e_veb_clear(struct i40e_veb *veb) | |
10211 | { | |
10212 | if (!veb) | |
10213 | return; | |
10214 | ||
10215 | if (veb->pf) { | |
10216 | struct i40e_pf *pf = veb->pf; | |
10217 | ||
10218 | mutex_lock(&pf->switch_mutex); | |
10219 | if (pf->veb[veb->idx] == veb) | |
10220 | pf->veb[veb->idx] = NULL; | |
10221 | mutex_unlock(&pf->switch_mutex); | |
10222 | } | |
10223 | ||
10224 | kfree(veb); | |
10225 | } | |
10226 | ||
10227 | /** | |
10228 | * i40e_veb_release - Delete a VEB and free its resources | |
10229 | * @veb: the VEB being removed | |
10230 | **/ | |
10231 | void i40e_veb_release(struct i40e_veb *veb) | |
10232 | { | |
10233 | struct i40e_vsi *vsi = NULL; | |
10234 | struct i40e_pf *pf; | |
10235 | int i, n = 0; | |
10236 | ||
10237 | pf = veb->pf; | |
10238 | ||
10239 | /* find the remaining VSI and check for extras */ | |
505682cd | 10240 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
10241 | if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) { |
10242 | n++; | |
10243 | vsi = pf->vsi[i]; | |
10244 | } | |
10245 | } | |
10246 | if (n != 1) { | |
10247 | dev_info(&pf->pdev->dev, | |
10248 | "can't remove VEB %d with %d VSIs left\n", | |
10249 | veb->seid, n); | |
10250 | return; | |
10251 | } | |
10252 | ||
10253 | /* move the remaining VSI to uplink veb */ | |
10254 | vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER; | |
10255 | if (veb->uplink_seid) { | |
10256 | vsi->uplink_seid = veb->uplink_seid; | |
10257 | if (veb->uplink_seid == pf->mac_seid) | |
10258 | vsi->veb_idx = I40E_NO_VEB; | |
10259 | else | |
10260 | vsi->veb_idx = veb->veb_idx; | |
10261 | } else { | |
10262 | /* floating VEB */ | |
10263 | vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
10264 | vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx; | |
10265 | } | |
10266 | ||
10267 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
10268 | i40e_veb_clear(veb); | |
41c445ff JB |
10269 | } |
10270 | ||
10271 | /** | |
10272 | * i40e_add_veb - create the VEB in the switch | |
10273 | * @veb: the VEB to be instantiated | |
10274 | * @vsi: the controlling VSI | |
10275 | **/ | |
10276 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi) | |
10277 | { | |
f1c7e72e | 10278 | struct i40e_pf *pf = veb->pf; |
66fc360a | 10279 | bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED); |
41c445ff JB |
10280 | int ret; |
10281 | ||
f1c7e72e | 10282 | ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid, |
5bc16031 | 10283 | veb->enabled_tc, false, |
66fc360a | 10284 | &veb->seid, enable_stats, NULL); |
5bc16031 MW |
10285 | |
10286 | /* get a VEB from the hardware */ | |
41c445ff | 10287 | if (ret) { |
f1c7e72e SN |
10288 | dev_info(&pf->pdev->dev, |
10289 | "couldn't add VEB, err %s aq_err %s\n", | |
10290 | i40e_stat_str(&pf->hw, ret), | |
10291 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10292 | return -EPERM; |
10293 | } | |
10294 | ||
10295 | /* get statistics counter */ | |
f1c7e72e | 10296 | ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL, |
41c445ff JB |
10297 | &veb->stats_idx, NULL, NULL, NULL); |
10298 | if (ret) { | |
f1c7e72e SN |
10299 | dev_info(&pf->pdev->dev, |
10300 | "couldn't get VEB statistics idx, err %s aq_err %s\n", | |
10301 | i40e_stat_str(&pf->hw, ret), | |
10302 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10303 | return -EPERM; |
10304 | } | |
10305 | ret = i40e_veb_get_bw_info(veb); | |
10306 | if (ret) { | |
f1c7e72e SN |
10307 | dev_info(&pf->pdev->dev, |
10308 | "couldn't get VEB bw info, err %s aq_err %s\n", | |
10309 | i40e_stat_str(&pf->hw, ret), | |
10310 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
10311 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
41c445ff JB |
10312 | return -ENOENT; |
10313 | } | |
10314 | ||
10315 | vsi->uplink_seid = veb->seid; | |
10316 | vsi->veb_idx = veb->idx; | |
10317 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
10318 | ||
10319 | return 0; | |
10320 | } | |
10321 | ||
10322 | /** | |
10323 | * i40e_veb_setup - Set up a VEB | |
10324 | * @pf: board private structure | |
10325 | * @flags: VEB setup flags | |
10326 | * @uplink_seid: the switch element to link to | |
10327 | * @vsi_seid: the initial VSI seid | |
10328 | * @enabled_tc: Enabled TC bit-map | |
10329 | * | |
10330 | * This allocates the sw VEB structure and links it into the switch | |
10331 | * It is possible and legal for this to be a duplicate of an already | |
10332 | * existing VEB. It is also possible for both uplink and vsi seids | |
10333 | * to be zero, in order to create a floating VEB. | |
10334 | * | |
10335 | * Returns pointer to the successfully allocated VEB sw struct on | |
10336 | * success, otherwise returns NULL on failure. | |
10337 | **/ | |
10338 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, | |
10339 | u16 uplink_seid, u16 vsi_seid, | |
10340 | u8 enabled_tc) | |
10341 | { | |
10342 | struct i40e_veb *veb, *uplink_veb = NULL; | |
10343 | int vsi_idx, veb_idx; | |
10344 | int ret; | |
10345 | ||
10346 | /* if one seid is 0, the other must be 0 to create a floating relay */ | |
10347 | if ((uplink_seid == 0 || vsi_seid == 0) && | |
10348 | (uplink_seid + vsi_seid != 0)) { | |
10349 | dev_info(&pf->pdev->dev, | |
10350 | "one, not both seid's are 0: uplink=%d vsi=%d\n", | |
10351 | uplink_seid, vsi_seid); | |
10352 | return NULL; | |
10353 | } | |
10354 | ||
10355 | /* make sure there is such a vsi and uplink */ | |
505682cd | 10356 | for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++) |
41c445ff JB |
10357 | if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid) |
10358 | break; | |
505682cd | 10359 | if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) { |
41c445ff JB |
10360 | dev_info(&pf->pdev->dev, "vsi seid %d not found\n", |
10361 | vsi_seid); | |
10362 | return NULL; | |
10363 | } | |
10364 | ||
10365 | if (uplink_seid && uplink_seid != pf->mac_seid) { | |
10366 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
10367 | if (pf->veb[veb_idx] && | |
10368 | pf->veb[veb_idx]->seid == uplink_seid) { | |
10369 | uplink_veb = pf->veb[veb_idx]; | |
10370 | break; | |
10371 | } | |
10372 | } | |
10373 | if (!uplink_veb) { | |
10374 | dev_info(&pf->pdev->dev, | |
10375 | "uplink seid %d not found\n", uplink_seid); | |
10376 | return NULL; | |
10377 | } | |
10378 | } | |
10379 | ||
10380 | /* get veb sw struct */ | |
10381 | veb_idx = i40e_veb_mem_alloc(pf); | |
10382 | if (veb_idx < 0) | |
10383 | goto err_alloc; | |
10384 | veb = pf->veb[veb_idx]; | |
10385 | veb->flags = flags; | |
10386 | veb->uplink_seid = uplink_seid; | |
10387 | veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB); | |
10388 | veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1); | |
10389 | ||
10390 | /* create the VEB in the switch */ | |
10391 | ret = i40e_add_veb(veb, pf->vsi[vsi_idx]); | |
10392 | if (ret) | |
10393 | goto err_veb; | |
1bb8b935 SN |
10394 | if (vsi_idx == pf->lan_vsi) |
10395 | pf->lan_veb = veb->idx; | |
41c445ff JB |
10396 | |
10397 | return veb; | |
10398 | ||
10399 | err_veb: | |
10400 | i40e_veb_clear(veb); | |
10401 | err_alloc: | |
10402 | return NULL; | |
10403 | } | |
10404 | ||
10405 | /** | |
b40c82e6 | 10406 | * i40e_setup_pf_switch_element - set PF vars based on switch type |
41c445ff JB |
10407 | * @pf: board private structure |
10408 | * @ele: element we are building info from | |
10409 | * @num_reported: total number of elements | |
10410 | * @printconfig: should we print the contents | |
10411 | * | |
10412 | * helper function to assist in extracting a few useful SEID values. | |
10413 | **/ | |
10414 | static void i40e_setup_pf_switch_element(struct i40e_pf *pf, | |
10415 | struct i40e_aqc_switch_config_element_resp *ele, | |
10416 | u16 num_reported, bool printconfig) | |
10417 | { | |
10418 | u16 downlink_seid = le16_to_cpu(ele->downlink_seid); | |
10419 | u16 uplink_seid = le16_to_cpu(ele->uplink_seid); | |
10420 | u8 element_type = ele->element_type; | |
10421 | u16 seid = le16_to_cpu(ele->seid); | |
10422 | ||
10423 | if (printconfig) | |
10424 | dev_info(&pf->pdev->dev, | |
10425 | "type=%d seid=%d uplink=%d downlink=%d\n", | |
10426 | element_type, seid, uplink_seid, downlink_seid); | |
10427 | ||
10428 | switch (element_type) { | |
10429 | case I40E_SWITCH_ELEMENT_TYPE_MAC: | |
10430 | pf->mac_seid = seid; | |
10431 | break; | |
10432 | case I40E_SWITCH_ELEMENT_TYPE_VEB: | |
10433 | /* Main VEB? */ | |
10434 | if (uplink_seid != pf->mac_seid) | |
10435 | break; | |
10436 | if (pf->lan_veb == I40E_NO_VEB) { | |
10437 | int v; | |
10438 | ||
10439 | /* find existing or else empty VEB */ | |
10440 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
10441 | if (pf->veb[v] && (pf->veb[v]->seid == seid)) { | |
10442 | pf->lan_veb = v; | |
10443 | break; | |
10444 | } | |
10445 | } | |
10446 | if (pf->lan_veb == I40E_NO_VEB) { | |
10447 | v = i40e_veb_mem_alloc(pf); | |
10448 | if (v < 0) | |
10449 | break; | |
10450 | pf->lan_veb = v; | |
10451 | } | |
10452 | } | |
10453 | ||
10454 | pf->veb[pf->lan_veb]->seid = seid; | |
10455 | pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid; | |
10456 | pf->veb[pf->lan_veb]->pf = pf; | |
10457 | pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB; | |
10458 | break; | |
10459 | case I40E_SWITCH_ELEMENT_TYPE_VSI: | |
10460 | if (num_reported != 1) | |
10461 | break; | |
10462 | /* This is immediately after a reset so we can assume this is | |
10463 | * the PF's VSI | |
10464 | */ | |
10465 | pf->mac_seid = uplink_seid; | |
10466 | pf->pf_seid = downlink_seid; | |
10467 | pf->main_vsi_seid = seid; | |
10468 | if (printconfig) | |
10469 | dev_info(&pf->pdev->dev, | |
10470 | "pf_seid=%d main_vsi_seid=%d\n", | |
10471 | pf->pf_seid, pf->main_vsi_seid); | |
10472 | break; | |
10473 | case I40E_SWITCH_ELEMENT_TYPE_PF: | |
10474 | case I40E_SWITCH_ELEMENT_TYPE_VF: | |
10475 | case I40E_SWITCH_ELEMENT_TYPE_EMP: | |
10476 | case I40E_SWITCH_ELEMENT_TYPE_BMC: | |
10477 | case I40E_SWITCH_ELEMENT_TYPE_PE: | |
10478 | case I40E_SWITCH_ELEMENT_TYPE_PA: | |
10479 | /* ignore these for now */ | |
10480 | break; | |
10481 | default: | |
10482 | dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n", | |
10483 | element_type, seid); | |
10484 | break; | |
10485 | } | |
10486 | } | |
10487 | ||
10488 | /** | |
10489 | * i40e_fetch_switch_configuration - Get switch config from firmware | |
10490 | * @pf: board private structure | |
10491 | * @printconfig: should we print the contents | |
10492 | * | |
10493 | * Get the current switch configuration from the device and | |
10494 | * extract a few useful SEID values. | |
10495 | **/ | |
10496 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig) | |
10497 | { | |
10498 | struct i40e_aqc_get_switch_config_resp *sw_config; | |
10499 | u16 next_seid = 0; | |
10500 | int ret = 0; | |
10501 | u8 *aq_buf; | |
10502 | int i; | |
10503 | ||
10504 | aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL); | |
10505 | if (!aq_buf) | |
10506 | return -ENOMEM; | |
10507 | ||
10508 | sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; | |
10509 | do { | |
10510 | u16 num_reported, num_total; | |
10511 | ||
10512 | ret = i40e_aq_get_switch_config(&pf->hw, sw_config, | |
10513 | I40E_AQ_LARGE_BUF, | |
10514 | &next_seid, NULL); | |
10515 | if (ret) { | |
10516 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10517 | "get switch config failed err %s aq_err %s\n", |
10518 | i40e_stat_str(&pf->hw, ret), | |
10519 | i40e_aq_str(&pf->hw, | |
10520 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10521 | kfree(aq_buf); |
10522 | return -ENOENT; | |
10523 | } | |
10524 | ||
10525 | num_reported = le16_to_cpu(sw_config->header.num_reported); | |
10526 | num_total = le16_to_cpu(sw_config->header.num_total); | |
10527 | ||
10528 | if (printconfig) | |
10529 | dev_info(&pf->pdev->dev, | |
10530 | "header: %d reported %d total\n", | |
10531 | num_reported, num_total); | |
10532 | ||
41c445ff JB |
10533 | for (i = 0; i < num_reported; i++) { |
10534 | struct i40e_aqc_switch_config_element_resp *ele = | |
10535 | &sw_config->element[i]; | |
10536 | ||
10537 | i40e_setup_pf_switch_element(pf, ele, num_reported, | |
10538 | printconfig); | |
10539 | } | |
10540 | } while (next_seid != 0); | |
10541 | ||
10542 | kfree(aq_buf); | |
10543 | return ret; | |
10544 | } | |
10545 | ||
10546 | /** | |
10547 | * i40e_setup_pf_switch - Setup the HW switch on startup or after reset | |
10548 | * @pf: board private structure | |
bc7d338f | 10549 | * @reinit: if the Main VSI needs to re-initialized. |
41c445ff JB |
10550 | * |
10551 | * Returns 0 on success, negative value on failure | |
10552 | **/ | |
bc7d338f | 10553 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit) |
41c445ff | 10554 | { |
b5569892 | 10555 | u16 flags = 0; |
41c445ff JB |
10556 | int ret; |
10557 | ||
10558 | /* find out what's out there already */ | |
10559 | ret = i40e_fetch_switch_configuration(pf, false); | |
10560 | if (ret) { | |
10561 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10562 | "couldn't fetch switch config, err %s aq_err %s\n", |
10563 | i40e_stat_str(&pf->hw, ret), | |
10564 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10565 | return ret; |
10566 | } | |
10567 | i40e_pf_reset_stats(pf); | |
10568 | ||
b5569892 ASJ |
10569 | /* set the switch config bit for the whole device to |
10570 | * support limited promisc or true promisc | |
10571 | * when user requests promisc. The default is limited | |
10572 | * promisc. | |
10573 | */ | |
10574 | ||
10575 | if ((pf->hw.pf_id == 0) && | |
10576 | !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) | |
10577 | flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
10578 | ||
10579 | if (pf->hw.pf_id == 0) { | |
10580 | u16 valid_flags; | |
10581 | ||
10582 | valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
10583 | ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, | |
10584 | NULL); | |
10585 | if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { | |
10586 | dev_info(&pf->pdev->dev, | |
10587 | "couldn't set switch config bits, err %s aq_err %s\n", | |
10588 | i40e_stat_str(&pf->hw, ret), | |
10589 | i40e_aq_str(&pf->hw, | |
10590 | pf->hw.aq.asq_last_status)); | |
10591 | /* not a fatal problem, just keep going */ | |
10592 | } | |
10593 | } | |
10594 | ||
41c445ff | 10595 | /* first time setup */ |
bc7d338f | 10596 | if (pf->lan_vsi == I40E_NO_VSI || reinit) { |
41c445ff JB |
10597 | struct i40e_vsi *vsi = NULL; |
10598 | u16 uplink_seid; | |
10599 | ||
10600 | /* Set up the PF VSI associated with the PF's main VSI | |
10601 | * that is already in the HW switch | |
10602 | */ | |
10603 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
10604 | uplink_seid = pf->veb[pf->lan_veb]->seid; | |
10605 | else | |
10606 | uplink_seid = pf->mac_seid; | |
bc7d338f ASJ |
10607 | if (pf->lan_vsi == I40E_NO_VSI) |
10608 | vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0); | |
10609 | else if (reinit) | |
10610 | vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
10611 | if (!vsi) { |
10612 | dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n"); | |
10613 | i40e_fdir_teardown(pf); | |
10614 | return -EAGAIN; | |
10615 | } | |
41c445ff JB |
10616 | } else { |
10617 | /* force a reset of TC and queue layout configurations */ | |
10618 | u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
6995b36c | 10619 | |
41c445ff JB |
10620 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; |
10621 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
10622 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
10623 | } | |
10624 | i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]); | |
10625 | ||
cbf61325 ASJ |
10626 | i40e_fdir_sb_setup(pf); |
10627 | ||
41c445ff JB |
10628 | /* Setup static PF queue filter control settings */ |
10629 | ret = i40e_setup_pf_filter_control(pf); | |
10630 | if (ret) { | |
10631 | dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n", | |
10632 | ret); | |
10633 | /* Failure here should not stop continuing other steps */ | |
10634 | } | |
10635 | ||
10636 | /* enable RSS in the HW, even for only one queue, as the stack can use | |
10637 | * the hash | |
10638 | */ | |
10639 | if ((pf->flags & I40E_FLAG_RSS_ENABLED)) | |
043dd650 | 10640 | i40e_pf_config_rss(pf); |
41c445ff JB |
10641 | |
10642 | /* fill in link information and enable LSE reporting */ | |
0a862b43 | 10643 | i40e_update_link_info(&pf->hw); |
a34a6711 MW |
10644 | i40e_link_event(pf); |
10645 | ||
d52c20b7 | 10646 | /* Initialize user-specific link properties */ |
41c445ff JB |
10647 | pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info & |
10648 | I40E_AQ_AN_COMPLETED) ? true : false); | |
d52c20b7 | 10649 | |
beb0dff1 JK |
10650 | i40e_ptp_init(pf); |
10651 | ||
41c445ff JB |
10652 | return ret; |
10653 | } | |
10654 | ||
41c445ff JB |
10655 | /** |
10656 | * i40e_determine_queue_usage - Work out queue distribution | |
10657 | * @pf: board private structure | |
10658 | **/ | |
10659 | static void i40e_determine_queue_usage(struct i40e_pf *pf) | |
10660 | { | |
41c445ff JB |
10661 | int queues_left; |
10662 | ||
10663 | pf->num_lan_qps = 0; | |
38e00438 VD |
10664 | #ifdef I40E_FCOE |
10665 | pf->num_fcoe_qps = 0; | |
10666 | #endif | |
41c445ff JB |
10667 | |
10668 | /* Find the max queues to be put into basic use. We'll always be | |
10669 | * using TC0, whether or not DCB is running, and TC0 will get the | |
10670 | * big RSS set. | |
10671 | */ | |
10672 | queues_left = pf->hw.func_caps.num_tx_qp; | |
10673 | ||
cbf61325 | 10674 | if ((queues_left == 1) || |
9aa7e935 | 10675 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) { |
41c445ff JB |
10676 | /* one qp for PF, no queues for anything else */ |
10677 | queues_left = 0; | |
acd65448 | 10678 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
41c445ff JB |
10679 | |
10680 | /* make sure all the fancies are disabled */ | |
60ea5f83 | 10681 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | |
e3219ce6 | 10682 | I40E_FLAG_IWARP_ENABLED | |
38e00438 VD |
10683 | #ifdef I40E_FCOE |
10684 | I40E_FLAG_FCOE_ENABLED | | |
10685 | #endif | |
60ea5f83 JB |
10686 | I40E_FLAG_FD_SB_ENABLED | |
10687 | I40E_FLAG_FD_ATR_ENABLED | | |
4d9b6043 | 10688 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 10689 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
10690 | I40E_FLAG_SRIOV_ENABLED | |
10691 | I40E_FLAG_VMDQ_ENABLED); | |
9aa7e935 FZ |
10692 | } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED | |
10693 | I40E_FLAG_FD_SB_ENABLED | | |
bbe7d0e0 | 10694 | I40E_FLAG_FD_ATR_ENABLED | |
4d9b6043 | 10695 | I40E_FLAG_DCB_CAPABLE))) { |
9aa7e935 | 10696 | /* one qp for PF */ |
acd65448 | 10697 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
9aa7e935 FZ |
10698 | queues_left -= pf->num_lan_qps; |
10699 | ||
10700 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | | |
e3219ce6 | 10701 | I40E_FLAG_IWARP_ENABLED | |
38e00438 VD |
10702 | #ifdef I40E_FCOE |
10703 | I40E_FLAG_FCOE_ENABLED | | |
10704 | #endif | |
9aa7e935 FZ |
10705 | I40E_FLAG_FD_SB_ENABLED | |
10706 | I40E_FLAG_FD_ATR_ENABLED | | |
10707 | I40E_FLAG_DCB_ENABLED | | |
10708 | I40E_FLAG_VMDQ_ENABLED); | |
41c445ff | 10709 | } else { |
cbf61325 | 10710 | /* Not enough queues for all TCs */ |
4d9b6043 | 10711 | if ((pf->flags & I40E_FLAG_DCB_CAPABLE) && |
cbf61325 | 10712 | (queues_left < I40E_MAX_TRAFFIC_CLASS)) { |
a036244c DE |
10713 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | |
10714 | I40E_FLAG_DCB_ENABLED); | |
cbf61325 ASJ |
10715 | dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n"); |
10716 | } | |
9a3bd2f1 ASJ |
10717 | pf->num_lan_qps = max_t(int, pf->rss_size_max, |
10718 | num_online_cpus()); | |
10719 | pf->num_lan_qps = min_t(int, pf->num_lan_qps, | |
10720 | pf->hw.func_caps.num_tx_qp); | |
10721 | ||
cbf61325 ASJ |
10722 | queues_left -= pf->num_lan_qps; |
10723 | } | |
10724 | ||
38e00438 VD |
10725 | #ifdef I40E_FCOE |
10726 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) { | |
10727 | if (I40E_DEFAULT_FCOE <= queues_left) { | |
10728 | pf->num_fcoe_qps = I40E_DEFAULT_FCOE; | |
10729 | } else if (I40E_MINIMUM_FCOE <= queues_left) { | |
10730 | pf->num_fcoe_qps = I40E_MINIMUM_FCOE; | |
10731 | } else { | |
10732 | pf->num_fcoe_qps = 0; | |
10733 | pf->flags &= ~I40E_FLAG_FCOE_ENABLED; | |
10734 | dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n"); | |
10735 | } | |
10736 | ||
10737 | queues_left -= pf->num_fcoe_qps; | |
10738 | } | |
10739 | ||
10740 | #endif | |
cbf61325 ASJ |
10741 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
10742 | if (queues_left > 1) { | |
10743 | queues_left -= 1; /* save 1 queue for FD */ | |
10744 | } else { | |
10745 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
10746 | dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n"); | |
10747 | } | |
41c445ff JB |
10748 | } |
10749 | ||
10750 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
10751 | pf->num_vf_qps && pf->num_req_vfs && queues_left) { | |
cbf61325 ASJ |
10752 | pf->num_req_vfs = min_t(int, pf->num_req_vfs, |
10753 | (queues_left / pf->num_vf_qps)); | |
41c445ff JB |
10754 | queues_left -= (pf->num_req_vfs * pf->num_vf_qps); |
10755 | } | |
10756 | ||
10757 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && | |
10758 | pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) { | |
10759 | pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis, | |
10760 | (queues_left / pf->num_vmdq_qps)); | |
10761 | queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps); | |
10762 | } | |
10763 | ||
f8ff1464 | 10764 | pf->queues_left = queues_left; |
8279e495 NP |
10765 | dev_dbg(&pf->pdev->dev, |
10766 | "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n", | |
10767 | pf->hw.func_caps.num_tx_qp, | |
10768 | !!(pf->flags & I40E_FLAG_FD_SB_ENABLED), | |
acd65448 HZ |
10769 | pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs, |
10770 | pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps, | |
10771 | queues_left); | |
38e00438 | 10772 | #ifdef I40E_FCOE |
8279e495 | 10773 | dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps); |
38e00438 | 10774 | #endif |
41c445ff JB |
10775 | } |
10776 | ||
10777 | /** | |
10778 | * i40e_setup_pf_filter_control - Setup PF static filter control | |
10779 | * @pf: PF to be setup | |
10780 | * | |
b40c82e6 | 10781 | * i40e_setup_pf_filter_control sets up a PF's initial filter control |
41c445ff JB |
10782 | * settings. If PE/FCoE are enabled then it will also set the per PF |
10783 | * based filter sizes required for them. It also enables Flow director, | |
10784 | * ethertype and macvlan type filter settings for the pf. | |
10785 | * | |
10786 | * Returns 0 on success, negative on failure | |
10787 | **/ | |
10788 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf) | |
10789 | { | |
10790 | struct i40e_filter_control_settings *settings = &pf->filter_settings; | |
10791 | ||
10792 | settings->hash_lut_size = I40E_HASH_LUT_SIZE_128; | |
10793 | ||
10794 | /* Flow Director is enabled */ | |
60ea5f83 | 10795 | if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)) |
41c445ff JB |
10796 | settings->enable_fdir = true; |
10797 | ||
10798 | /* Ethtype and MACVLAN filters enabled for PF */ | |
10799 | settings->enable_ethtype = true; | |
10800 | settings->enable_macvlan = true; | |
10801 | ||
10802 | if (i40e_set_filter_control(&pf->hw, settings)) | |
10803 | return -ENOENT; | |
10804 | ||
10805 | return 0; | |
10806 | } | |
10807 | ||
0c22b3dd | 10808 | #define INFO_STRING_LEN 255 |
7fd89545 | 10809 | #define REMAIN(__x) (INFO_STRING_LEN - (__x)) |
0c22b3dd JB |
10810 | static void i40e_print_features(struct i40e_pf *pf) |
10811 | { | |
10812 | struct i40e_hw *hw = &pf->hw; | |
3b195843 JP |
10813 | char *buf; |
10814 | int i; | |
0c22b3dd | 10815 | |
3b195843 JP |
10816 | buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL); |
10817 | if (!buf) | |
0c22b3dd | 10818 | return; |
0c22b3dd | 10819 | |
3b195843 | 10820 | i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id); |
0c22b3dd | 10821 | #ifdef CONFIG_PCI_IOV |
3b195843 | 10822 | i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs); |
0c22b3dd | 10823 | #endif |
1a557afc | 10824 | i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d", |
7fd89545 | 10825 | pf->hw.func_caps.num_vsis, |
1a557afc | 10826 | pf->vsi[pf->lan_vsi]->num_queue_pairs); |
0c22b3dd | 10827 | if (pf->flags & I40E_FLAG_RSS_ENABLED) |
3b195843 | 10828 | i += snprintf(&buf[i], REMAIN(i), " RSS"); |
0c22b3dd | 10829 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) |
3b195843 | 10830 | i += snprintf(&buf[i], REMAIN(i), " FD_ATR"); |
c6423ff1 | 10831 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
3b195843 JP |
10832 | i += snprintf(&buf[i], REMAIN(i), " FD_SB"); |
10833 | i += snprintf(&buf[i], REMAIN(i), " NTUPLE"); | |
c6423ff1 | 10834 | } |
4d9b6043 | 10835 | if (pf->flags & I40E_FLAG_DCB_CAPABLE) |
3b195843 | 10836 | i += snprintf(&buf[i], REMAIN(i), " DCB"); |
3b195843 | 10837 | i += snprintf(&buf[i], REMAIN(i), " VxLAN"); |
6a899024 | 10838 | i += snprintf(&buf[i], REMAIN(i), " Geneve"); |
0c22b3dd | 10839 | if (pf->flags & I40E_FLAG_PTP) |
3b195843 | 10840 | i += snprintf(&buf[i], REMAIN(i), " PTP"); |
38e00438 VD |
10841 | #ifdef I40E_FCOE |
10842 | if (pf->flags & I40E_FLAG_FCOE_ENABLED) | |
3b195843 | 10843 | i += snprintf(&buf[i], REMAIN(i), " FCOE"); |
38e00438 | 10844 | #endif |
6dec1017 | 10845 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
3b195843 | 10846 | i += snprintf(&buf[i], REMAIN(i), " VEB"); |
6dec1017 | 10847 | else |
3b195843 | 10848 | i += snprintf(&buf[i], REMAIN(i), " VEPA"); |
0c22b3dd | 10849 | |
3b195843 JP |
10850 | dev_info(&pf->pdev->dev, "%s\n", buf); |
10851 | kfree(buf); | |
7fd89545 | 10852 | WARN_ON(i > INFO_STRING_LEN); |
0c22b3dd JB |
10853 | } |
10854 | ||
b499ffb0 SV |
10855 | /** |
10856 | * i40e_get_platform_mac_addr - get platform-specific MAC address | |
10857 | * | |
10858 | * @pdev: PCI device information struct | |
10859 | * @pf: board private structure | |
10860 | * | |
10861 | * Look up the MAC address in Open Firmware on systems that support it, | |
10862 | * and use IDPROM on SPARC if no OF address is found. On return, the | |
10863 | * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value | |
10864 | * has been selected. | |
10865 | **/ | |
10866 | static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf) | |
10867 | { | |
b499ffb0 | 10868 | pf->flags &= ~I40E_FLAG_PF_MAC; |
ba94272d | 10869 | if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr)) |
b499ffb0 | 10870 | pf->flags |= I40E_FLAG_PF_MAC; |
b499ffb0 SV |
10871 | } |
10872 | ||
41c445ff JB |
10873 | /** |
10874 | * i40e_probe - Device initialization routine | |
10875 | * @pdev: PCI device information struct | |
10876 | * @ent: entry in i40e_pci_tbl | |
10877 | * | |
b40c82e6 JK |
10878 | * i40e_probe initializes a PF identified by a pci_dev structure. |
10879 | * The OS initialization, configuring of the PF private structure, | |
41c445ff JB |
10880 | * and a hardware reset occur. |
10881 | * | |
10882 | * Returns 0 on success, negative on failure | |
10883 | **/ | |
10884 | static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
10885 | { | |
e827845c | 10886 | struct i40e_aq_get_phy_abilities_resp abilities; |
41c445ff JB |
10887 | struct i40e_pf *pf; |
10888 | struct i40e_hw *hw; | |
93cd765b | 10889 | static u16 pfs_found; |
1d5109d1 | 10890 | u16 wol_nvm_bits; |
d4dfb81a | 10891 | u16 link_status; |
6f66a484 | 10892 | int err; |
4f2f017c | 10893 | u32 val; |
8a9eb7d3 | 10894 | u32 i; |
58fc3267 | 10895 | u8 set_fc_aq_fail; |
41c445ff JB |
10896 | |
10897 | err = pci_enable_device_mem(pdev); | |
10898 | if (err) | |
10899 | return err; | |
10900 | ||
10901 | /* set up for high or low dma */ | |
6494294f | 10902 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
6494294f | 10903 | if (err) { |
e3e3bfdd JS |
10904 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
10905 | if (err) { | |
10906 | dev_err(&pdev->dev, | |
10907 | "DMA configuration failed: 0x%x\n", err); | |
10908 | goto err_dma; | |
10909 | } | |
41c445ff JB |
10910 | } |
10911 | ||
10912 | /* set up pci connections */ | |
56d766d6 | 10913 | err = pci_request_mem_regions(pdev, i40e_driver_name); |
41c445ff JB |
10914 | if (err) { |
10915 | dev_info(&pdev->dev, | |
10916 | "pci_request_selected_regions failed %d\n", err); | |
10917 | goto err_pci_reg; | |
10918 | } | |
10919 | ||
10920 | pci_enable_pcie_error_reporting(pdev); | |
10921 | pci_set_master(pdev); | |
10922 | ||
10923 | /* Now that we have a PCI connection, we need to do the | |
10924 | * low level device setup. This is primarily setting up | |
10925 | * the Admin Queue structures and then querying for the | |
10926 | * device's current profile information. | |
10927 | */ | |
10928 | pf = kzalloc(sizeof(*pf), GFP_KERNEL); | |
10929 | if (!pf) { | |
10930 | err = -ENOMEM; | |
10931 | goto err_pf_alloc; | |
10932 | } | |
10933 | pf->next_vsi = 0; | |
10934 | pf->pdev = pdev; | |
10935 | set_bit(__I40E_DOWN, &pf->state); | |
10936 | ||
10937 | hw = &pf->hw; | |
10938 | hw->back = pf; | |
232f4706 | 10939 | |
2ac8b675 SN |
10940 | pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0), |
10941 | I40E_MAX_CSR_SPACE); | |
232f4706 | 10942 | |
2ac8b675 | 10943 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len); |
41c445ff JB |
10944 | if (!hw->hw_addr) { |
10945 | err = -EIO; | |
10946 | dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n", | |
10947 | (unsigned int)pci_resource_start(pdev, 0), | |
2ac8b675 | 10948 | pf->ioremap_len, err); |
41c445ff JB |
10949 | goto err_ioremap; |
10950 | } | |
10951 | hw->vendor_id = pdev->vendor; | |
10952 | hw->device_id = pdev->device; | |
10953 | pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | |
10954 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
10955 | hw->subsystem_device_id = pdev->subsystem_device; | |
10956 | hw->bus.device = PCI_SLOT(pdev->devfn); | |
10957 | hw->bus.func = PCI_FUNC(pdev->devfn); | |
93cd765b | 10958 | pf->instance = pfs_found; |
41c445ff | 10959 | |
de03d2b0 SN |
10960 | /* set up the locks for the AQ, do this only once in probe |
10961 | * and destroy them only once in remove | |
10962 | */ | |
10963 | mutex_init(&hw->aq.asq_mutex); | |
10964 | mutex_init(&hw->aq.arq_mutex); | |
10965 | ||
5d4ca23e AD |
10966 | pf->msg_enable = netif_msg_init(debug, |
10967 | NETIF_MSG_DRV | | |
10968 | NETIF_MSG_PROBE | | |
10969 | NETIF_MSG_LINK); | |
10970 | if (debug < -1) | |
10971 | pf->hw.debug_mask = debug; | |
5b5faa43 | 10972 | |
7134f9ce JB |
10973 | /* do a special CORER for clearing PXE mode once at init */ |
10974 | if (hw->revision_id == 0 && | |
10975 | (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) { | |
10976 | wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK); | |
10977 | i40e_flush(hw); | |
10978 | msleep(200); | |
10979 | pf->corer_count++; | |
10980 | ||
10981 | i40e_clear_pxe_mode(hw); | |
10982 | } | |
10983 | ||
41c445ff | 10984 | /* Reset here to make sure all is clean and to define PF 'n' */ |
838d41d9 | 10985 | i40e_clear_hw(hw); |
41c445ff JB |
10986 | err = i40e_pf_reset(hw); |
10987 | if (err) { | |
10988 | dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err); | |
10989 | goto err_pf_reset; | |
10990 | } | |
10991 | pf->pfr_count++; | |
10992 | ||
10993 | hw->aq.num_arq_entries = I40E_AQ_LEN; | |
10994 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
10995 | hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
10996 | hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
10997 | pf->adminq_work_limit = I40E_AQ_WORK_LIMIT; | |
b2008cbf | 10998 | |
b294ac70 | 10999 | snprintf(pf->int_name, sizeof(pf->int_name) - 1, |
b2008cbf CW |
11000 | "%s-%s:misc", |
11001 | dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev)); | |
41c445ff JB |
11002 | |
11003 | err = i40e_init_shared_code(hw); | |
11004 | if (err) { | |
b2a75c58 ASJ |
11005 | dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", |
11006 | err); | |
41c445ff JB |
11007 | goto err_pf_reset; |
11008 | } | |
11009 | ||
d52c20b7 JB |
11010 | /* set up a default setting for link flow control */ |
11011 | pf->hw.fc.requested_mode = I40E_FC_NONE; | |
11012 | ||
41c445ff | 11013 | err = i40e_init_adminq(hw); |
2b2426a7 CW |
11014 | if (err) { |
11015 | if (err == I40E_ERR_FIRMWARE_API_VERSION) | |
11016 | dev_info(&pdev->dev, | |
11017 | "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n"); | |
11018 | else | |
11019 | dev_info(&pdev->dev, | |
11020 | "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n"); | |
11021 | ||
11022 | goto err_pf_reset; | |
11023 | } | |
f0b44440 | 11024 | |
6dec1017 SN |
11025 | /* provide nvm, fw, api versions */ |
11026 | dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n", | |
11027 | hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build, | |
11028 | hw->aq.api_maj_ver, hw->aq.api_min_ver, | |
11029 | i40e_nvm_version_str(hw)); | |
f0b44440 | 11030 | |
7aa67613 CS |
11031 | if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && |
11032 | hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) | |
278b6f62 | 11033 | dev_info(&pdev->dev, |
7aa67613 CS |
11034 | "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n"); |
11035 | else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || | |
11036 | hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) | |
278b6f62 | 11037 | dev_info(&pdev->dev, |
7aa67613 | 11038 | "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n"); |
278b6f62 | 11039 | |
4eb3f768 SN |
11040 | i40e_verify_eeprom(pf); |
11041 | ||
2c5fe33b JB |
11042 | /* Rev 0 hardware was never productized */ |
11043 | if (hw->revision_id < 1) | |
11044 | dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); | |
11045 | ||
6ff4ef86 | 11046 | i40e_clear_pxe_mode(hw); |
41c445ff JB |
11047 | err = i40e_get_capabilities(pf); |
11048 | if (err) | |
11049 | goto err_adminq_setup; | |
11050 | ||
11051 | err = i40e_sw_init(pf); | |
11052 | if (err) { | |
11053 | dev_info(&pdev->dev, "sw_init failed: %d\n", err); | |
11054 | goto err_sw_init; | |
11055 | } | |
11056 | ||
11057 | err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, | |
11058 | hw->func_caps.num_rx_qp, | |
11059 | pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num); | |
11060 | if (err) { | |
11061 | dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err); | |
11062 | goto err_init_lan_hmc; | |
11063 | } | |
11064 | ||
11065 | err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
11066 | if (err) { | |
11067 | dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err); | |
11068 | err = -ENOENT; | |
11069 | goto err_configure_lan_hmc; | |
11070 | } | |
11071 | ||
b686ece5 NP |
11072 | /* Disable LLDP for NICs that have firmware versions lower than v4.3. |
11073 | * Ignore error return codes because if it was already disabled via | |
11074 | * hardware settings this will fail | |
11075 | */ | |
f1bbad33 | 11076 | if (pf->flags & I40E_FLAG_STOP_FW_LLDP) { |
b686ece5 NP |
11077 | dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n"); |
11078 | i40e_aq_stop_lldp(hw, true, NULL); | |
11079 | } | |
11080 | ||
41c445ff | 11081 | i40e_get_mac_addr(hw, hw->mac.addr); |
b499ffb0 SV |
11082 | /* allow a platform config to override the HW addr */ |
11083 | i40e_get_platform_mac_addr(pdev, pf); | |
f62b5060 | 11084 | if (!is_valid_ether_addr(hw->mac.addr)) { |
41c445ff JB |
11085 | dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr); |
11086 | err = -EIO; | |
11087 | goto err_mac_addr; | |
11088 | } | |
11089 | dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr); | |
9a173901 | 11090 | ether_addr_copy(hw->mac.perm_addr, hw->mac.addr); |
1f224ad2 NP |
11091 | i40e_get_port_mac_addr(hw, hw->mac.port_addr); |
11092 | if (is_valid_ether_addr(hw->mac.port_addr)) | |
11093 | pf->flags |= I40E_FLAG_PORT_ID_VALID; | |
38e00438 VD |
11094 | #ifdef I40E_FCOE |
11095 | err = i40e_get_san_mac_addr(hw, hw->mac.san_addr); | |
11096 | if (err) | |
11097 | dev_info(&pdev->dev, | |
11098 | "(non-fatal) SAN MAC retrieval failed: %d\n", err); | |
11099 | if (!is_valid_ether_addr(hw->mac.san_addr)) { | |
11100 | dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n", | |
11101 | hw->mac.san_addr); | |
11102 | ether_addr_copy(hw->mac.san_addr, hw->mac.addr); | |
11103 | } | |
11104 | dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr); | |
11105 | #endif /* I40E_FCOE */ | |
41c445ff JB |
11106 | |
11107 | pci_set_drvdata(pdev, pf); | |
11108 | pci_save_state(pdev); | |
4e3b35b0 NP |
11109 | #ifdef CONFIG_I40E_DCB |
11110 | err = i40e_init_pf_dcb(pf); | |
11111 | if (err) { | |
aebfc816 | 11112 | dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err); |
c17ef430 | 11113 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED); |
014269ff | 11114 | /* Continue without DCB enabled */ |
4e3b35b0 NP |
11115 | } |
11116 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
11117 | |
11118 | /* set up periodic task facility */ | |
11119 | setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf); | |
11120 | pf->service_timer_period = HZ; | |
11121 | ||
11122 | INIT_WORK(&pf->service_task, i40e_service_task); | |
11123 | clear_bit(__I40E_SERVICE_SCHED, &pf->state); | |
11124 | pf->flags |= I40E_FLAG_NEED_LINK_UPDATE; | |
41c445ff | 11125 | |
1d5109d1 SN |
11126 | /* NVM bit on means WoL disabled for the port */ |
11127 | i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits); | |
75f5cea9 | 11128 | if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) |
1d5109d1 SN |
11129 | pf->wol_en = false; |
11130 | else | |
11131 | pf->wol_en = true; | |
8e2773ae SN |
11132 | device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en); |
11133 | ||
41c445ff JB |
11134 | /* set up the main switch operations */ |
11135 | i40e_determine_queue_usage(pf); | |
c1147280 JB |
11136 | err = i40e_init_interrupt_scheme(pf); |
11137 | if (err) | |
11138 | goto err_switch_setup; | |
41c445ff | 11139 | |
505682cd MW |
11140 | /* The number of VSIs reported by the FW is the minimum guaranteed |
11141 | * to us; HW supports far more and we share the remaining pool with | |
11142 | * the other PFs. We allocate space for more than the guarantee with | |
11143 | * the understanding that we might not get them all later. | |
41c445ff | 11144 | */ |
505682cd MW |
11145 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) |
11146 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
11147 | else | |
11148 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
11149 | ||
11150 | /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */ | |
d17038d6 JB |
11151 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), |
11152 | GFP_KERNEL); | |
ed87ac09 WY |
11153 | if (!pf->vsi) { |
11154 | err = -ENOMEM; | |
41c445ff | 11155 | goto err_switch_setup; |
ed87ac09 | 11156 | } |
41c445ff | 11157 | |
fa11cb3d ASJ |
11158 | #ifdef CONFIG_PCI_IOV |
11159 | /* prep for VF support */ | |
11160 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
11161 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
11162 | !test_bit(__I40E_BAD_EEPROM, &pf->state)) { | |
11163 | if (pci_num_vf(pdev)) | |
11164 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
11165 | } | |
11166 | #endif | |
bc7d338f | 11167 | err = i40e_setup_pf_switch(pf, false); |
41c445ff JB |
11168 | if (err) { |
11169 | dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err); | |
11170 | goto err_vsis; | |
11171 | } | |
58fc3267 HZ |
11172 | |
11173 | /* Make sure flow control is set according to current settings */ | |
11174 | err = i40e_set_fc(hw, &set_fc_aq_fail, true); | |
11175 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET) | |
11176 | dev_dbg(&pf->pdev->dev, | |
11177 | "Set fc with err %s aq_err %s on get_phy_cap\n", | |
11178 | i40e_stat_str(hw, err), | |
11179 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
11180 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET) | |
11181 | dev_dbg(&pf->pdev->dev, | |
11182 | "Set fc with err %s aq_err %s on set_phy_config\n", | |
11183 | i40e_stat_str(hw, err), | |
11184 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
11185 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE) | |
11186 | dev_dbg(&pf->pdev->dev, | |
11187 | "Set fc with err %s aq_err %s on get_link_info\n", | |
11188 | i40e_stat_str(hw, err), | |
11189 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
11190 | ||
8a9eb7d3 | 11191 | /* if FDIR VSI was set up, start it now */ |
505682cd | 11192 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
8a9eb7d3 SN |
11193 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
11194 | i40e_vsi_open(pf->vsi[i]); | |
11195 | break; | |
11196 | } | |
11197 | } | |
41c445ff | 11198 | |
2f0aff41 SN |
11199 | /* The driver only wants link up/down and module qualification |
11200 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
11201 | */ |
11202 | err = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 11203 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 11204 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 11205 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 11206 | if (err) |
f1c7e72e SN |
11207 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
11208 | i40e_stat_str(&pf->hw, err), | |
11209 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 11210 | |
4f2f017c ASJ |
11211 | /* Reconfigure hardware for allowing smaller MSS in the case |
11212 | * of TSO, so that we avoid the MDD being fired and causing | |
11213 | * a reset in the case of small MSS+TSO. | |
11214 | */ | |
11215 | val = rd32(hw, I40E_REG_MSS); | |
11216 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
11217 | val &= ~I40E_REG_MSS_MIN_MASK; | |
11218 | val |= I40E_64BYTE_MSS; | |
11219 | wr32(hw, I40E_REG_MSS, val); | |
11220 | } | |
11221 | ||
8eed76fa | 11222 | if (pf->flags & I40E_FLAG_RESTART_AUTONEG) { |
025b4a54 ASJ |
11223 | msleep(75); |
11224 | err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
11225 | if (err) | |
f1c7e72e SN |
11226 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
11227 | i40e_stat_str(&pf->hw, err), | |
11228 | i40e_aq_str(&pf->hw, | |
11229 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 11230 | } |
41c445ff JB |
11231 | /* The main driver is (mostly) up and happy. We need to set this state |
11232 | * before setting up the misc vector or we get a race and the vector | |
11233 | * ends up disabled forever. | |
11234 | */ | |
11235 | clear_bit(__I40E_DOWN, &pf->state); | |
11236 | ||
11237 | /* In case of MSIX we are going to setup the misc vector right here | |
11238 | * to handle admin queue events etc. In case of legacy and MSI | |
11239 | * the misc functionality and queue processing is combined in | |
11240 | * the same vector and that gets setup at open. | |
11241 | */ | |
11242 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
11243 | err = i40e_setup_misc_vector(pf); | |
11244 | if (err) { | |
11245 | dev_info(&pdev->dev, | |
11246 | "setup of misc vector failed: %d\n", err); | |
11247 | goto err_vsis; | |
11248 | } | |
11249 | } | |
11250 | ||
df805f62 | 11251 | #ifdef CONFIG_PCI_IOV |
41c445ff JB |
11252 | /* prep for VF support */ |
11253 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
4eb3f768 SN |
11254 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && |
11255 | !test_bit(__I40E_BAD_EEPROM, &pf->state)) { | |
41c445ff JB |
11256 | /* disable link interrupts for VFs */ |
11257 | val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); | |
11258 | val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; | |
11259 | wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); | |
11260 | i40e_flush(hw); | |
4aeec010 MW |
11261 | |
11262 | if (pci_num_vf(pdev)) { | |
11263 | dev_info(&pdev->dev, | |
11264 | "Active VFs found, allocating resources.\n"); | |
11265 | err = i40e_alloc_vfs(pf, pci_num_vf(pdev)); | |
11266 | if (err) | |
11267 | dev_info(&pdev->dev, | |
11268 | "Error %d allocating resources for existing VFs\n", | |
11269 | err); | |
11270 | } | |
41c445ff | 11271 | } |
df805f62 | 11272 | #endif /* CONFIG_PCI_IOV */ |
41c445ff | 11273 | |
e3219ce6 ASJ |
11274 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
11275 | pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile, | |
11276 | pf->num_iwarp_msix, | |
11277 | I40E_IWARP_IRQ_PILE_ID); | |
11278 | if (pf->iwarp_base_vector < 0) { | |
11279 | dev_info(&pdev->dev, | |
11280 | "failed to get tracking for %d vectors for IWARP err=%d\n", | |
11281 | pf->num_iwarp_msix, pf->iwarp_base_vector); | |
11282 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
11283 | } | |
11284 | } | |
93cd765b | 11285 | |
41c445ff JB |
11286 | i40e_dbg_pf_init(pf); |
11287 | ||
11288 | /* tell the firmware that we're starting */ | |
44033fac | 11289 | i40e_send_version(pf); |
41c445ff JB |
11290 | |
11291 | /* since everything's happy, start the service_task timer */ | |
11292 | mod_timer(&pf->service_timer, | |
11293 | round_jiffies(jiffies + pf->service_timer_period)); | |
11294 | ||
e3219ce6 ASJ |
11295 | /* add this PF to client device list and launch a client service task */ |
11296 | err = i40e_lan_add_device(pf); | |
11297 | if (err) | |
11298 | dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n", | |
11299 | err); | |
11300 | ||
38e00438 VD |
11301 | #ifdef I40E_FCOE |
11302 | /* create FCoE interface */ | |
11303 | i40e_fcoe_vsi_setup(pf); | |
11304 | ||
11305 | #endif | |
3fced535 ASJ |
11306 | #define PCI_SPEED_SIZE 8 |
11307 | #define PCI_WIDTH_SIZE 8 | |
11308 | /* Devices on the IOSF bus do not have this information | |
11309 | * and will report PCI Gen 1 x 1 by default so don't bother | |
11310 | * checking them. | |
11311 | */ | |
11312 | if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) { | |
11313 | char speed[PCI_SPEED_SIZE] = "Unknown"; | |
11314 | char width[PCI_WIDTH_SIZE] = "Unknown"; | |
11315 | ||
11316 | /* Get the negotiated link width and speed from PCI config | |
11317 | * space | |
11318 | */ | |
11319 | pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, | |
11320 | &link_status); | |
11321 | ||
11322 | i40e_set_pci_config_data(hw, link_status); | |
11323 | ||
11324 | switch (hw->bus.speed) { | |
11325 | case i40e_bus_speed_8000: | |
11326 | strncpy(speed, "8.0", PCI_SPEED_SIZE); break; | |
11327 | case i40e_bus_speed_5000: | |
11328 | strncpy(speed, "5.0", PCI_SPEED_SIZE); break; | |
11329 | case i40e_bus_speed_2500: | |
11330 | strncpy(speed, "2.5", PCI_SPEED_SIZE); break; | |
11331 | default: | |
11332 | break; | |
11333 | } | |
11334 | switch (hw->bus.width) { | |
11335 | case i40e_bus_width_pcie_x8: | |
11336 | strncpy(width, "8", PCI_WIDTH_SIZE); break; | |
11337 | case i40e_bus_width_pcie_x4: | |
11338 | strncpy(width, "4", PCI_WIDTH_SIZE); break; | |
11339 | case i40e_bus_width_pcie_x2: | |
11340 | strncpy(width, "2", PCI_WIDTH_SIZE); break; | |
11341 | case i40e_bus_width_pcie_x1: | |
11342 | strncpy(width, "1", PCI_WIDTH_SIZE); break; | |
11343 | default: | |
11344 | break; | |
11345 | } | |
11346 | ||
11347 | dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n", | |
11348 | speed, width); | |
11349 | ||
11350 | if (hw->bus.width < i40e_bus_width_pcie_x8 || | |
11351 | hw->bus.speed < i40e_bus_speed_8000) { | |
11352 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n"); | |
11353 | dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n"); | |
11354 | } | |
d4dfb81a CS |
11355 | } |
11356 | ||
e827845c CS |
11357 | /* get the requested speeds from the fw */ |
11358 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); | |
11359 | if (err) | |
8279e495 NP |
11360 | dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n", |
11361 | i40e_stat_str(&pf->hw, err), | |
11362 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
e827845c CS |
11363 | pf->hw.phy.link_info.requested_speeds = abilities.link_speed; |
11364 | ||
fc72dbce CS |
11365 | /* get the supported phy types from the fw */ |
11366 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); | |
11367 | if (err) | |
11368 | dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n", | |
11369 | i40e_stat_str(&pf->hw, err), | |
11370 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
11371 | pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type); | |
11372 | ||
e7358f54 ASJ |
11373 | /* Add a filter to drop all Flow control frames from any VSI from being |
11374 | * transmitted. By doing so we stop a malicious VF from sending out | |
11375 | * PAUSE or PFC frames and potentially controlling traffic for other | |
11376 | * PF/VF VSIs. | |
11377 | * The FW can still send Flow control frames if enabled. | |
11378 | */ | |
11379 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
11380 | pf->main_vsi_seid); | |
11381 | ||
31b606d0 | 11382 | if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) || |
4f9b4307 HT |
11383 | (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4)) |
11384 | pf->flags |= I40E_FLAG_PHY_CONTROLS_LEDS; | |
4ad9f4f9 HR |
11385 | if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722) |
11386 | pf->flags |= I40E_FLAG_HAVE_CRT_RETIMER; | |
0c22b3dd JB |
11387 | /* print a string summarizing features */ |
11388 | i40e_print_features(pf); | |
11389 | ||
41c445ff JB |
11390 | return 0; |
11391 | ||
11392 | /* Unwind what we've done if something failed in the setup */ | |
11393 | err_vsis: | |
11394 | set_bit(__I40E_DOWN, &pf->state); | |
41c445ff JB |
11395 | i40e_clear_interrupt_scheme(pf); |
11396 | kfree(pf->vsi); | |
04b03013 SN |
11397 | err_switch_setup: |
11398 | i40e_reset_interrupt_capability(pf); | |
41c445ff JB |
11399 | del_timer_sync(&pf->service_timer); |
11400 | err_mac_addr: | |
11401 | err_configure_lan_hmc: | |
11402 | (void)i40e_shutdown_lan_hmc(hw); | |
11403 | err_init_lan_hmc: | |
11404 | kfree(pf->qp_pile); | |
41c445ff JB |
11405 | err_sw_init: |
11406 | err_adminq_setup: | |
41c445ff JB |
11407 | err_pf_reset: |
11408 | iounmap(hw->hw_addr); | |
11409 | err_ioremap: | |
11410 | kfree(pf); | |
11411 | err_pf_alloc: | |
11412 | pci_disable_pcie_error_reporting(pdev); | |
56d766d6 | 11413 | pci_release_mem_regions(pdev); |
41c445ff JB |
11414 | err_pci_reg: |
11415 | err_dma: | |
11416 | pci_disable_device(pdev); | |
11417 | return err; | |
11418 | } | |
11419 | ||
11420 | /** | |
11421 | * i40e_remove - Device removal routine | |
11422 | * @pdev: PCI device information struct | |
11423 | * | |
11424 | * i40e_remove is called by the PCI subsystem to alert the driver | |
11425 | * that is should release a PCI device. This could be caused by a | |
11426 | * Hot-Plug event, or because the driver is going to be removed from | |
11427 | * memory. | |
11428 | **/ | |
11429 | static void i40e_remove(struct pci_dev *pdev) | |
11430 | { | |
11431 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
bcab2db9 | 11432 | struct i40e_hw *hw = &pf->hw; |
41c445ff | 11433 | i40e_status ret_code; |
41c445ff JB |
11434 | int i; |
11435 | ||
11436 | i40e_dbg_pf_exit(pf); | |
11437 | ||
beb0dff1 JK |
11438 | i40e_ptp_stop(pf); |
11439 | ||
bcab2db9 | 11440 | /* Disable RSS in hw */ |
272cdaf2 SN |
11441 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); |
11442 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); | |
bcab2db9 | 11443 | |
41c445ff | 11444 | /* no more scheduling of any task */ |
a4618ec8 | 11445 | set_bit(__I40E_SUSPENDED, &pf->state); |
41c445ff | 11446 | set_bit(__I40E_DOWN, &pf->state); |
c99abb4c SN |
11447 | if (pf->service_timer.data) |
11448 | del_timer_sync(&pf->service_timer); | |
11449 | if (pf->service_task.func) | |
11450 | cancel_work_sync(&pf->service_task); | |
41c445ff | 11451 | |
eb2d80bc MW |
11452 | if (pf->flags & I40E_FLAG_SRIOV_ENABLED) { |
11453 | i40e_free_vfs(pf); | |
11454 | pf->flags &= ~I40E_FLAG_SRIOV_ENABLED; | |
11455 | } | |
11456 | ||
41c445ff JB |
11457 | i40e_fdir_teardown(pf); |
11458 | ||
11459 | /* If there is a switch structure or any orphans, remove them. | |
11460 | * This will leave only the PF's VSI remaining. | |
11461 | */ | |
11462 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
11463 | if (!pf->veb[i]) | |
11464 | continue; | |
11465 | ||
11466 | if (pf->veb[i]->uplink_seid == pf->mac_seid || | |
11467 | pf->veb[i]->uplink_seid == 0) | |
11468 | i40e_switch_branch_release(pf->veb[i]); | |
11469 | } | |
11470 | ||
11471 | /* Now we can shutdown the PF's VSI, just before we kill | |
11472 | * adminq and hmc. | |
11473 | */ | |
11474 | if (pf->vsi[pf->lan_vsi]) | |
11475 | i40e_vsi_release(pf->vsi[pf->lan_vsi]); | |
11476 | ||
e3219ce6 ASJ |
11477 | /* remove attached clients */ |
11478 | ret_code = i40e_lan_del_device(pf); | |
11479 | if (ret_code) { | |
11480 | dev_warn(&pdev->dev, "Failed to delete client device: %d\n", | |
11481 | ret_code); | |
11482 | } | |
11483 | ||
41c445ff | 11484 | /* shutdown and destroy the HMC */ |
f734dfff JB |
11485 | if (hw->hmc.hmc_obj) { |
11486 | ret_code = i40e_shutdown_lan_hmc(hw); | |
60442dea SN |
11487 | if (ret_code) |
11488 | dev_warn(&pdev->dev, | |
11489 | "Failed to destroy the HMC resources: %d\n", | |
11490 | ret_code); | |
11491 | } | |
41c445ff JB |
11492 | |
11493 | /* shutdown the adminq */ | |
ac9c5c6d | 11494 | i40e_shutdown_adminq(hw); |
41c445ff | 11495 | |
8ddb3326 JB |
11496 | /* destroy the locks only once, here */ |
11497 | mutex_destroy(&hw->aq.arq_mutex); | |
11498 | mutex_destroy(&hw->aq.asq_mutex); | |
11499 | ||
41c445ff JB |
11500 | /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */ |
11501 | i40e_clear_interrupt_scheme(pf); | |
505682cd | 11502 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
11503 | if (pf->vsi[i]) { |
11504 | i40e_vsi_clear_rings(pf->vsi[i]); | |
11505 | i40e_vsi_clear(pf->vsi[i]); | |
11506 | pf->vsi[i] = NULL; | |
11507 | } | |
11508 | } | |
11509 | ||
11510 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
11511 | kfree(pf->veb[i]); | |
11512 | pf->veb[i] = NULL; | |
11513 | } | |
11514 | ||
11515 | kfree(pf->qp_pile); | |
41c445ff JB |
11516 | kfree(pf->vsi); |
11517 | ||
f734dfff | 11518 | iounmap(hw->hw_addr); |
41c445ff | 11519 | kfree(pf); |
56d766d6 | 11520 | pci_release_mem_regions(pdev); |
41c445ff JB |
11521 | |
11522 | pci_disable_pcie_error_reporting(pdev); | |
11523 | pci_disable_device(pdev); | |
11524 | } | |
11525 | ||
11526 | /** | |
11527 | * i40e_pci_error_detected - warning that something funky happened in PCI land | |
11528 | * @pdev: PCI device information struct | |
11529 | * | |
11530 | * Called to warn that something happened and the error handling steps | |
11531 | * are in progress. Allows the driver to quiesce things, be ready for | |
11532 | * remediation. | |
11533 | **/ | |
11534 | static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev, | |
11535 | enum pci_channel_state error) | |
11536 | { | |
11537 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11538 | ||
11539 | dev_info(&pdev->dev, "%s: error %d\n", __func__, error); | |
11540 | ||
edfc23ee GP |
11541 | if (!pf) { |
11542 | dev_info(&pdev->dev, | |
11543 | "Cannot recover - error happened during device probe\n"); | |
11544 | return PCI_ERS_RESULT_DISCONNECT; | |
11545 | } | |
11546 | ||
41c445ff | 11547 | /* shutdown all operations */ |
9007bccd SN |
11548 | if (!test_bit(__I40E_SUSPENDED, &pf->state)) { |
11549 | rtnl_lock(); | |
11550 | i40e_prep_for_reset(pf); | |
11551 | rtnl_unlock(); | |
11552 | } | |
41c445ff JB |
11553 | |
11554 | /* Request a slot reset */ | |
11555 | return PCI_ERS_RESULT_NEED_RESET; | |
11556 | } | |
11557 | ||
11558 | /** | |
11559 | * i40e_pci_error_slot_reset - a PCI slot reset just happened | |
11560 | * @pdev: PCI device information struct | |
11561 | * | |
11562 | * Called to find if the driver can work with the device now that | |
11563 | * the pci slot has been reset. If a basic connection seems good | |
11564 | * (registers are readable and have sane content) then return a | |
11565 | * happy little PCI_ERS_RESULT_xxx. | |
11566 | **/ | |
11567 | static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev) | |
11568 | { | |
11569 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11570 | pci_ers_result_t result; | |
11571 | int err; | |
11572 | u32 reg; | |
11573 | ||
fb43201f | 11574 | dev_dbg(&pdev->dev, "%s\n", __func__); |
41c445ff JB |
11575 | if (pci_enable_device_mem(pdev)) { |
11576 | dev_info(&pdev->dev, | |
11577 | "Cannot re-enable PCI device after reset.\n"); | |
11578 | result = PCI_ERS_RESULT_DISCONNECT; | |
11579 | } else { | |
11580 | pci_set_master(pdev); | |
11581 | pci_restore_state(pdev); | |
11582 | pci_save_state(pdev); | |
11583 | pci_wake_from_d3(pdev, false); | |
11584 | ||
11585 | reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); | |
11586 | if (reg == 0) | |
11587 | result = PCI_ERS_RESULT_RECOVERED; | |
11588 | else | |
11589 | result = PCI_ERS_RESULT_DISCONNECT; | |
11590 | } | |
11591 | ||
11592 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
11593 | if (err) { | |
11594 | dev_info(&pdev->dev, | |
11595 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
11596 | err); | |
11597 | /* non-fatal, continue */ | |
11598 | } | |
11599 | ||
11600 | return result; | |
11601 | } | |
11602 | ||
11603 | /** | |
11604 | * i40e_pci_error_resume - restart operations after PCI error recovery | |
11605 | * @pdev: PCI device information struct | |
11606 | * | |
11607 | * Called to allow the driver to bring things back up after PCI error | |
11608 | * and/or reset recovery has finished. | |
11609 | **/ | |
11610 | static void i40e_pci_error_resume(struct pci_dev *pdev) | |
11611 | { | |
11612 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11613 | ||
fb43201f | 11614 | dev_dbg(&pdev->dev, "%s\n", __func__); |
9007bccd SN |
11615 | if (test_bit(__I40E_SUSPENDED, &pf->state)) |
11616 | return; | |
11617 | ||
11618 | rtnl_lock(); | |
41c445ff | 11619 | i40e_handle_reset_warning(pf); |
4c4935a9 | 11620 | rtnl_unlock(); |
9007bccd SN |
11621 | } |
11622 | ||
11623 | /** | |
11624 | * i40e_shutdown - PCI callback for shutting down | |
11625 | * @pdev: PCI device information struct | |
11626 | **/ | |
11627 | static void i40e_shutdown(struct pci_dev *pdev) | |
11628 | { | |
11629 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 11630 | struct i40e_hw *hw = &pf->hw; |
9007bccd SN |
11631 | |
11632 | set_bit(__I40E_SUSPENDED, &pf->state); | |
11633 | set_bit(__I40E_DOWN, &pf->state); | |
11634 | rtnl_lock(); | |
11635 | i40e_prep_for_reset(pf); | |
11636 | rtnl_unlock(); | |
11637 | ||
8e2773ae SN |
11638 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
11639 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
11640 | ||
02b42498 CS |
11641 | del_timer_sync(&pf->service_timer); |
11642 | cancel_work_sync(&pf->service_task); | |
11643 | i40e_fdir_teardown(pf); | |
11644 | ||
11645 | rtnl_lock(); | |
11646 | i40e_prep_for_reset(pf); | |
11647 | rtnl_unlock(); | |
11648 | ||
11649 | wr32(hw, I40E_PFPM_APM, | |
11650 | (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); | |
11651 | wr32(hw, I40E_PFPM_WUFC, | |
11652 | (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
11653 | ||
e147758d SN |
11654 | i40e_clear_interrupt_scheme(pf); |
11655 | ||
9007bccd | 11656 | if (system_state == SYSTEM_POWER_OFF) { |
8e2773ae | 11657 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
11658 | pci_set_power_state(pdev, PCI_D3hot); |
11659 | } | |
11660 | } | |
11661 | ||
11662 | #ifdef CONFIG_PM | |
11663 | /** | |
11664 | * i40e_suspend - PCI callback for moving to D3 | |
11665 | * @pdev: PCI device information struct | |
11666 | **/ | |
11667 | static int i40e_suspend(struct pci_dev *pdev, pm_message_t state) | |
11668 | { | |
11669 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 11670 | struct i40e_hw *hw = &pf->hw; |
059ff69b | 11671 | int retval = 0; |
9007bccd SN |
11672 | |
11673 | set_bit(__I40E_SUSPENDED, &pf->state); | |
11674 | set_bit(__I40E_DOWN, &pf->state); | |
3932dbfe | 11675 | |
9007bccd SN |
11676 | rtnl_lock(); |
11677 | i40e_prep_for_reset(pf); | |
11678 | rtnl_unlock(); | |
11679 | ||
8e2773ae SN |
11680 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
11681 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
11682 | ||
b33d3b73 GR |
11683 | i40e_stop_misc_vector(pf); |
11684 | ||
059ff69b GR |
11685 | retval = pci_save_state(pdev); |
11686 | if (retval) | |
11687 | return retval; | |
11688 | ||
8e2773ae | 11689 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
11690 | pci_set_power_state(pdev, PCI_D3hot); |
11691 | ||
059ff69b | 11692 | return retval; |
41c445ff JB |
11693 | } |
11694 | ||
9007bccd SN |
11695 | /** |
11696 | * i40e_resume - PCI callback for waking up from D3 | |
11697 | * @pdev: PCI device information struct | |
11698 | **/ | |
11699 | static int i40e_resume(struct pci_dev *pdev) | |
11700 | { | |
11701 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11702 | u32 err; | |
11703 | ||
11704 | pci_set_power_state(pdev, PCI_D0); | |
11705 | pci_restore_state(pdev); | |
11706 | /* pci_restore_state() clears dev->state_saves, so | |
11707 | * call pci_save_state() again to restore it. | |
11708 | */ | |
11709 | pci_save_state(pdev); | |
11710 | ||
11711 | err = pci_enable_device_mem(pdev); | |
11712 | if (err) { | |
fb43201f | 11713 | dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n"); |
9007bccd SN |
11714 | return err; |
11715 | } | |
11716 | pci_set_master(pdev); | |
11717 | ||
11718 | /* no wakeup events while running */ | |
11719 | pci_wake_from_d3(pdev, false); | |
11720 | ||
11721 | /* handling the reset will rebuild the device state */ | |
11722 | if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) { | |
11723 | clear_bit(__I40E_DOWN, &pf->state); | |
11724 | rtnl_lock(); | |
11725 | i40e_reset_and_rebuild(pf, false); | |
11726 | rtnl_unlock(); | |
11727 | } | |
11728 | ||
11729 | return 0; | |
11730 | } | |
11731 | ||
11732 | #endif | |
41c445ff JB |
11733 | static const struct pci_error_handlers i40e_err_handler = { |
11734 | .error_detected = i40e_pci_error_detected, | |
11735 | .slot_reset = i40e_pci_error_slot_reset, | |
11736 | .resume = i40e_pci_error_resume, | |
11737 | }; | |
11738 | ||
11739 | static struct pci_driver i40e_driver = { | |
11740 | .name = i40e_driver_name, | |
11741 | .id_table = i40e_pci_tbl, | |
11742 | .probe = i40e_probe, | |
11743 | .remove = i40e_remove, | |
9007bccd SN |
11744 | #ifdef CONFIG_PM |
11745 | .suspend = i40e_suspend, | |
11746 | .resume = i40e_resume, | |
11747 | #endif | |
11748 | .shutdown = i40e_shutdown, | |
41c445ff JB |
11749 | .err_handler = &i40e_err_handler, |
11750 | .sriov_configure = i40e_pci_sriov_configure, | |
11751 | }; | |
11752 | ||
11753 | /** | |
11754 | * i40e_init_module - Driver registration routine | |
11755 | * | |
11756 | * i40e_init_module is the first routine called when the driver is | |
11757 | * loaded. All it does is register with the PCI subsystem. | |
11758 | **/ | |
11759 | static int __init i40e_init_module(void) | |
11760 | { | |
11761 | pr_info("%s: %s - version %s\n", i40e_driver_name, | |
11762 | i40e_driver_string, i40e_driver_version_str); | |
11763 | pr_info("%s: %s\n", i40e_driver_name, i40e_copyright); | |
96664483 | 11764 | |
2803b16c JB |
11765 | /* we will see if single thread per module is enough for now, |
11766 | * it can't be any worse than using the system workqueue which | |
11767 | * was already single threaded | |
11768 | */ | |
6992a6c9 JK |
11769 | i40e_wq = alloc_workqueue("%s", WQ_UNBOUND | WQ_MEM_RECLAIM, 1, |
11770 | i40e_driver_name); | |
2803b16c JB |
11771 | if (!i40e_wq) { |
11772 | pr_err("%s: Failed to create workqueue\n", i40e_driver_name); | |
11773 | return -ENOMEM; | |
11774 | } | |
11775 | ||
41c445ff JB |
11776 | i40e_dbg_init(); |
11777 | return pci_register_driver(&i40e_driver); | |
11778 | } | |
11779 | module_init(i40e_init_module); | |
11780 | ||
11781 | /** | |
11782 | * i40e_exit_module - Driver exit cleanup routine | |
11783 | * | |
11784 | * i40e_exit_module is called just before the driver is removed | |
11785 | * from memory. | |
11786 | **/ | |
11787 | static void __exit i40e_exit_module(void) | |
11788 | { | |
11789 | pci_unregister_driver(&i40e_driver); | |
2803b16c | 11790 | destroy_workqueue(i40e_wq); |
41c445ff JB |
11791 | i40e_dbg_exit(); |
11792 | } | |
11793 | module_exit(i40e_exit_module); |