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i40e: Fix MAC format in Write MAC address AQ cmd
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
7f61d1f7 41#define DRV_VERSION_BUILD 25
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
46static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
57
58/* i40e_pci_tbl - PCI Device ID Table
59 *
60 * Last entry must be all 0s
61 *
62 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
63 * Class, Class Mask, private data (not used) }
64 */
65static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
66 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
67 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
76 /* required last entry */
77 {0, }
78};
79MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
80
81#define I40E_MAX_VF_COUNT 128
82static int debug = -1;
83module_param(debug, int, 0);
84MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
85
86MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
87MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
88MODULE_LICENSE("GPL");
89MODULE_VERSION(DRV_VERSION);
90
91/**
92 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
93 * @hw: pointer to the HW structure
94 * @mem: ptr to mem struct to fill out
95 * @size: size of memory requested
96 * @alignment: what to align the allocation to
97 **/
98int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
99 u64 size, u32 alignment)
100{
101 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
102
103 mem->size = ALIGN(size, alignment);
104 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
105 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 106 if (!mem->va)
107 return -ENOMEM;
41c445ff 108
93bc73b8 109 return 0;
41c445ff
JB		 110}
111
112/**
113 * i40e_free_dma_mem_d - OS specific memory free for shared code
114 * @hw: pointer to the HW structure
115 * @mem: ptr to mem struct to free
116 **/
117int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
122 mem->va = NULL;
123 mem->pa = 0;
124 mem->size = 0;
125
126 return 0;
127}
128
129/**
130 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
131 * @hw: pointer to the HW structure
132 * @mem: ptr to mem struct to fill out
133 * @size: size of memory requested
134 **/
135int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
136 u32 size)
137{
138 mem->size = size;
139 mem->va = kzalloc(size, GFP_KERNEL);
140
93bc73b8
JB		 141 if (!mem->va)
142 return -ENOMEM;
41c445ff 143
93bc73b8 144 return 0;
41c445ff
JB		 145}
146
147/**
148 * i40e_free_virt_mem_d - OS specific memory free for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to free
151 **/
152int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
153{
154 /* it's ok to kfree a NULL pointer */
155 kfree(mem->va);
156 mem->va = NULL;
157 mem->size = 0;
158
159 return 0;
160}
161
162/**
163 * i40e_get_lump - find a lump of free generic resource
164 * @pf: board private structure
165 * @pile: the pile of resource to search
166 * @needed: the number of items needed
167 * @id: an owner id to stick on the items assigned
168 *
169 * Returns the base item index of the lump, or negative for error
170 *
171 * The search_hint trick and lack of advanced fit-finding only work
172 * because we're highly likely to have all the same size lump requests.
173 * Linear search time and any fragmentation should be minimal.
174 **/
175static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
176 u16 needed, u16 id)
177{
178 int ret = -ENOMEM;
ddf434ac 179 int i, j;
41c445ff
JB		 180
181 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
182 dev_info(&pf->pdev->dev,
183 "param err: pile=%p needed=%d id=0x%04x\n",
184 pile, needed, id);
185 return -EINVAL;
186 }
187
188 /* start the linear search with an imperfect hint */
189 i = pile->search_hint;
ddf434ac 190 while (i < pile->num_entries) {
41c445ff
JB		 191 /* skip already allocated entries */
192 if (pile->list[i] & I40E_PILE_VALID_BIT) {
193 i++;
194 continue;
195 }
196
197 /* do we have enough in this lump? */
198 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
199 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
200 break;
201 }
202
203 if (j == needed) {
204 /* there was enough, so assign it to the requestor */
205 for (j = 0; j < needed; j++)
206 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
207 ret = i;
208 pile->search_hint = i + j;
ddf434ac 209 break;
41c445ff
JB		 210 } else {
211 /* not enough, so skip over it and continue looking */
212 i += j;
213 }
214 }
215
216 return ret;
217}
218
219/**
220 * i40e_put_lump - return a lump of generic resource
221 * @pile: the pile of resource to search
222 * @index: the base item index
223 * @id: the owner id of the items assigned
224 *
225 * Returns the count of items in the lump
226 **/
227static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
228{
229 int valid_id = (id | I40E_PILE_VALID_BIT);
230 int count = 0;
231 int i;
232
233 if (!pile || index >= pile->num_entries)
234 return -EINVAL;
235
236 for (i = index;
237 i < pile->num_entries && pile->list[i] == valid_id;
238 i++) {
239 pile->list[i] = 0;
240 count++;
241 }
242
243 if (count && index < pile->search_hint)
244 pile->search_hint = index;
245
246 return count;
247}
248
249/**
250 * i40e_service_event_schedule - Schedule the service task to wake up
251 * @pf: board private structure
252 *
253 * If not already scheduled, this puts the task into the work queue
254 **/
255static void i40e_service_event_schedule(struct i40e_pf *pf)
256{
257 if (!test_bit(__I40E_DOWN, &pf->state) &&
258 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
259 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
260 schedule_work(&pf->service_task);
261}
262
263/**
264 * i40e_tx_timeout - Respond to a Tx Hang
265 * @netdev: network interface device structure
266 *
267 * If any port has noticed a Tx timeout, it is likely that the whole
268 * device is munged, not just the one netdev port, so go for the full
269 * reset.
270 **/
271static void i40e_tx_timeout(struct net_device *netdev)
272{
273 struct i40e_netdev_priv *np = netdev_priv(netdev);
274 struct i40e_vsi *vsi = np->vsi;
275 struct i40e_pf *pf = vsi->back;
276
277 pf->tx_timeout_count++;
278
279 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
280 pf->tx_timeout_recovery_level = 0;
281 pf->tx_timeout_last_recovery = jiffies;
282 netdev_info(netdev, "tx_timeout recovery level %d\n",
283 pf->tx_timeout_recovery_level);
284
285 switch (pf->tx_timeout_recovery_level) {
286 case 0:
287 /* disable and re-enable queues for the VSI */
288 if (in_interrupt()) {
289 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
290 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
291 } else {
292 i40e_vsi_reinit_locked(vsi);
293 }
294 break;
295 case 1:
296 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
297 break;
298 case 2:
299 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
300 break;
301 case 3:
302 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
303 break;
304 default:
305 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
306 i40e_down(vsi);
307 break;
308 }
309 i40e_service_event_schedule(pf);
310 pf->tx_timeout_recovery_level++;
311}
312
313/**
314 * i40e_release_rx_desc - Store the new tail and head values
315 * @rx_ring: ring to bump
316 * @val: new head index
317 **/
318static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
319{
320 rx_ring->next_to_use = val;
321
322 /* Force memory writes to complete before letting h/w
323 * know there are new descriptors to fetch. (Only
324 * applicable for weak-ordered memory model archs,
325 * such as IA-64).
326 */
327 wmb();
328 writel(val, rx_ring->tail);
329}
330
331/**
332 * i40e_get_vsi_stats_struct - Get System Network Statistics
333 * @vsi: the VSI we care about
334 *
335 * Returns the address of the device statistics structure.
336 * The statistics are actually updated from the service task.
337 **/
338struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
339{
340 return &vsi->net_stats;
341}
342
343/**
344 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
345 * @netdev: network interface device structure
346 *
347 * Returns the address of the device statistics structure.
348 * The statistics are actually updated from the service task.
349 **/
350static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
351 struct net_device *netdev,
980e9b11 352 struct rtnl_link_stats64 *stats)
41c445ff
JB		 353{
354 struct i40e_netdev_priv *np = netdev_priv(netdev);
355 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 356 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
357 int i;
358
143c9054 359
bc7d338f
ASJ		 360 if (test_bit(__I40E_DOWN, &vsi->state))
361 return stats;
362
3c325ced
JB		 363 if (!vsi->tx_rings)
364 return stats;
365
980e9b11
AD		 366 rcu_read_lock();
367 for (i = 0; i < vsi->num_queue_pairs; i++) {
368 struct i40e_ring *tx_ring, *rx_ring;
369 u64 bytes, packets;
370 unsigned int start;
371
372 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
373 if (!tx_ring)
374 continue;
375
376 do {
377 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
378 packets = tx_ring->stats.packets;
379 bytes = tx_ring->stats.bytes;
380 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
381
382 stats->tx_packets += packets;
383 stats->tx_bytes += bytes;
384 rx_ring = &tx_ring[1];
385
386 do {
387 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
388 packets = rx_ring->stats.packets;
389 bytes = rx_ring->stats.bytes;
390 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 391
980e9b11
AD		 392 stats->rx_packets += packets;
393 stats->rx_bytes += bytes;
394 }
395 rcu_read_unlock();
396
397 /* following stats updated by ixgbe_watchdog_task() */
398 stats->multicast = vsi_stats->multicast;
399 stats->tx_errors = vsi_stats->tx_errors;
400 stats->tx_dropped = vsi_stats->tx_dropped;
401 stats->rx_errors = vsi_stats->rx_errors;
402 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
403 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 404
980e9b11 405 return stats;
41c445ff
JB		 406}
407
408/**
409 * i40e_vsi_reset_stats - Resets all stats of the given vsi
410 * @vsi: the VSI to have its stats reset
411 **/
412void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
413{
414 struct rtnl_link_stats64 *ns;
415 int i;
416
417 if (!vsi)
418 return;
419
420 ns = i40e_get_vsi_stats_struct(vsi);
421 memset(ns, 0, sizeof(*ns));
422 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
423 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
424 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
425 if (vsi->rx_rings)
426 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 427 memset(&vsi->rx_rings[i]->stats, 0 ,
428 sizeof(vsi->rx_rings[i]->stats));
429 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
430 sizeof(vsi->rx_rings[i]->rx_stats));
431 memset(&vsi->tx_rings[i]->stats, 0 ,
432 sizeof(vsi->tx_rings[i]->stats));
433 memset(&vsi->tx_rings[i]->tx_stats, 0,
434 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff
JB		 435 }
436 vsi->stat_offsets_loaded = false;
437}
438
439/**
440 * i40e_pf_reset_stats - Reset all of the stats for the given pf
441 * @pf: the PF to be reset
442 **/
443void i40e_pf_reset_stats(struct i40e_pf *pf)
444{
445 memset(&pf->stats, 0, sizeof(pf->stats));
446 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
447 pf->stat_offsets_loaded = false;
448}
449
450/**
451 * i40e_stat_update48 - read and update a 48 bit stat from the chip
452 * @hw: ptr to the hardware info
453 * @hireg: the high 32 bit reg to read
454 * @loreg: the low 32 bit reg to read
455 * @offset_loaded: has the initial offset been loaded yet
456 * @offset: ptr to current offset value
457 * @stat: ptr to the stat
458 *
459 * Since the device stats are not reset at PFReset, they likely will not
460 * be zeroed when the driver starts. We'll save the first values read
461 * and use them as offsets to be subtracted from the raw values in order
462 * to report stats that count from zero. In the process, we also manage
463 * the potential roll-over.
464 **/
465static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
466 bool offset_loaded, u64 *offset, u64 *stat)
467{
468 u64 new_data;
469
470 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
471 new_data = rd32(hw, loreg);
472 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
473 } else {
474 new_data = rd64(hw, loreg);
475 }
476 if (!offset_loaded)
477 *offset = new_data;
478 if (likely(new_data >= *offset))
479 *stat = new_data - *offset;
480 else
481 *stat = (new_data + ((u64)1 << 48)) - *offset;
482 *stat &= 0xFFFFFFFFFFFFULL;
483}
484
485/**
486 * i40e_stat_update32 - read and update a 32 bit stat from the chip
487 * @hw: ptr to the hardware info
488 * @reg: the hw reg to read
489 * @offset_loaded: has the initial offset been loaded yet
490 * @offset: ptr to current offset value
491 * @stat: ptr to the stat
492 **/
493static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
494 bool offset_loaded, u64 *offset, u64 *stat)
495{
496 u32 new_data;
497
498 new_data = rd32(hw, reg);
499 if (!offset_loaded)
500 *offset = new_data;
501 if (likely(new_data >= *offset))
502 *stat = (u32)(new_data - *offset);
503 else
504 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
505}
506
507/**
508 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
509 * @vsi: the VSI to be updated
510 **/
511void i40e_update_eth_stats(struct i40e_vsi *vsi)
512{
513 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
514 struct i40e_pf *pf = vsi->back;
515 struct i40e_hw *hw = &pf->hw;
516 struct i40e_eth_stats *oes;
517 struct i40e_eth_stats *es; /* device's eth stats */
518
519 es = &vsi->eth_stats;
520 oes = &vsi->eth_stats_offsets;
521
522 /* Gather up the stats that the hw collects */
523 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
524 vsi->stat_offsets_loaded,
525 &oes->tx_errors, &es->tx_errors);
526 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
527 vsi->stat_offsets_loaded,
528 &oes->rx_discards, &es->rx_discards);
529
530 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
531 I40E_GLV_GORCL(stat_idx),
532 vsi->stat_offsets_loaded,
533 &oes->rx_bytes, &es->rx_bytes);
534 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
535 I40E_GLV_UPRCL(stat_idx),
536 vsi->stat_offsets_loaded,
537 &oes->rx_unicast, &es->rx_unicast);
538 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
539 I40E_GLV_MPRCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_multicast, &es->rx_multicast);
542 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
543 I40E_GLV_BPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_broadcast, &es->rx_broadcast);
546
547 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
548 I40E_GLV_GOTCL(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_bytes, &es->tx_bytes);
551 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
552 I40E_GLV_UPTCL(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->tx_unicast, &es->tx_unicast);
555 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
556 I40E_GLV_MPTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_multicast, &es->tx_multicast);
559 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
560 I40E_GLV_BPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_broadcast, &es->tx_broadcast);
563 vsi->stat_offsets_loaded = true;
564}
565
566/**
567 * i40e_update_veb_stats - Update Switch component statistics
568 * @veb: the VEB being updated
569 **/
570static void i40e_update_veb_stats(struct i40e_veb *veb)
571{
572 struct i40e_pf *pf = veb->pf;
573 struct i40e_hw *hw = &pf->hw;
574 struct i40e_eth_stats *oes;
575 struct i40e_eth_stats *es; /* device's eth stats */
576 int idx = 0;
577
578 idx = veb->stats_idx;
579 es = &veb->stats;
580 oes = &veb->stats_offsets;
581
582 /* Gather up the stats that the hw collects */
583 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
584 veb->stat_offsets_loaded,
585 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 586 if (hw->revision_id > 0)
587 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
588 veb->stat_offsets_loaded,
589 &oes->rx_unknown_protocol,
590 &es->rx_unknown_protocol);
41c445ff
JB		 591 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
592 veb->stat_offsets_loaded,
593 &oes->rx_bytes, &es->rx_bytes);
594 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
595 veb->stat_offsets_loaded,
596 &oes->rx_unicast, &es->rx_unicast);
597 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
598 veb->stat_offsets_loaded,
599 &oes->rx_multicast, &es->rx_multicast);
600 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
601 veb->stat_offsets_loaded,
602 &oes->rx_broadcast, &es->rx_broadcast);
603
604 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->tx_bytes, &es->tx_bytes);
607 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
608 veb->stat_offsets_loaded,
609 &oes->tx_unicast, &es->tx_unicast);
610 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
611 veb->stat_offsets_loaded,
612 &oes->tx_multicast, &es->tx_multicast);
613 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
614 veb->stat_offsets_loaded,
615 &oes->tx_broadcast, &es->tx_broadcast);
616 veb->stat_offsets_loaded = true;
617}
618
619/**
620 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
621 * @pf: the corresponding PF
622 *
623 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
624 **/
625static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
626{
627 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
628 struct i40e_hw_port_stats *nsd = &pf->stats;
629 struct i40e_hw *hw = &pf->hw;
630 u64 xoff = 0;
631 u16 i, v;
632
633 if ((hw->fc.current_mode != I40E_FC_FULL) &&
634 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
635 return;
636
637 xoff = nsd->link_xoff_rx;
638 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
639 pf->stat_offsets_loaded,
640 &osd->link_xoff_rx, &nsd->link_xoff_rx);
641
642 /* No new LFC xoff rx */
643 if (!(nsd->link_xoff_rx - xoff))
644 return;
645
646 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
647 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
648 struct i40e_vsi *vsi = pf->vsi[v];
649
650 if (!vsi)
651 continue;
652
653 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 654 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 655 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
656 }
657 }
658}
659
660/**
661 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
662 * @pf: the corresponding PF
663 *
664 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
665 **/
666static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
667{
668 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
669 struct i40e_hw_port_stats *nsd = &pf->stats;
670 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
671 struct i40e_dcbx_config *dcb_cfg;
672 struct i40e_hw *hw = &pf->hw;
673 u16 i, v;
674 u8 tc;
675
676 dcb_cfg = &hw->local_dcbx_config;
677
678 /* See if DCB enabled with PFC TC */
679 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
680 !(dcb_cfg->pfc.pfcenable)) {
681 i40e_update_link_xoff_rx(pf);
682 return;
683 }
684
685 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
686 u64 prio_xoff = nsd->priority_xoff_rx[i];
687 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
688 pf->stat_offsets_loaded,
689 &osd->priority_xoff_rx[i],
690 &nsd->priority_xoff_rx[i]);
691
692 /* No new PFC xoff rx */
693 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
694 continue;
695 /* Get the TC for given priority */
696 tc = dcb_cfg->etscfg.prioritytable[i];
697 xoff[tc] = true;
698 }
699
700 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
701 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
702 struct i40e_vsi *vsi = pf->vsi[v];
703
704 if (!vsi)
705 continue;
706
707 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 708 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 709
710 tc = ring->dcb_tc;
711 if (xoff[tc])
712 clear_bit(__I40E_HANG_CHECK_ARMED,
713 &ring->state);
714 }
715 }
716}
717
718/**
719 * i40e_update_stats - Update the board statistics counters.
720 * @vsi: the VSI to be updated
721 *
722 * There are a few instances where we store the same stat in a
723 * couple of different structs. This is partly because we have
724 * the netdev stats that need to be filled out, which is slightly
725 * different from the "eth_stats" defined by the chip and used in
726 * VF communications. We sort it all out here in a central place.
727 **/
728void i40e_update_stats(struct i40e_vsi *vsi)
729{
730 struct i40e_pf *pf = vsi->back;
731 struct i40e_hw *hw = &pf->hw;
732 struct rtnl_link_stats64 *ons;
733 struct rtnl_link_stats64 *ns; /* netdev stats */
734 struct i40e_eth_stats *oes;
735 struct i40e_eth_stats *es; /* device's eth stats */
736 u32 tx_restart, tx_busy;
737 u32 rx_page, rx_buf;
738 u64 rx_p, rx_b;
739 u64 tx_p, tx_b;
740 int i;
741 u16 q;
742
743 if (test_bit(__I40E_DOWN, &vsi->state) ||
744 test_bit(__I40E_CONFIG_BUSY, &pf->state))
745 return;
746
747 ns = i40e_get_vsi_stats_struct(vsi);
748 ons = &vsi->net_stats_offsets;
749 es = &vsi->eth_stats;
750 oes = &vsi->eth_stats_offsets;
751
752 /* Gather up the netdev and vsi stats that the driver collects
753 * on the fly during packet processing
754 */
755 rx_b = rx_p = 0;
756 tx_b = tx_p = 0;
757 tx_restart = tx_busy = 0;
758 rx_page = 0;
759 rx_buf = 0;
980e9b11 760 rcu_read_lock();
41c445ff
JB		 761 for (q = 0; q < vsi->num_queue_pairs; q++) {
762 struct i40e_ring *p;
980e9b11
AD		 763 u64 bytes, packets;
764 unsigned int start;
765
766 /* locate Tx ring */
767 p = ACCESS_ONCE(vsi->tx_rings[q]);
768
769 do {
770 start = u64_stats_fetch_begin_bh(&p->syncp);
771 packets = p->stats.packets;
772 bytes = p->stats.bytes;
773 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
774 tx_b += bytes;
775 tx_p += packets;
776 tx_restart += p->tx_stats.restart_queue;
777 tx_busy += p->tx_stats.tx_busy;
41c445ff 778
980e9b11
AD		 779 /* Rx queue is part of the same block as Tx queue */
780 p = &p[1];
781 do {
782 start = u64_stats_fetch_begin_bh(&p->syncp);
783 packets = p->stats.packets;
784 bytes = p->stats.bytes;
785 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
786 rx_b += bytes;
787 rx_p += packets;
41c445ff
JB		 788 rx_buf += p->rx_stats.alloc_rx_buff_failed;
789 rx_page += p->rx_stats.alloc_rx_page_failed;
41c445ff 790 }
980e9b11 791 rcu_read_unlock();
41c445ff
JB		 792 vsi->tx_restart = tx_restart;
793 vsi->tx_busy = tx_busy;
794 vsi->rx_page_failed = rx_page;
795 vsi->rx_buf_failed = rx_buf;
796
797 ns->rx_packets = rx_p;
798 ns->rx_bytes = rx_b;
799 ns->tx_packets = tx_p;
800 ns->tx_bytes = tx_b;
801
802 i40e_update_eth_stats(vsi);
803 /* update netdev stats from eth stats */
804 ons->rx_errors = oes->rx_errors;
805 ns->rx_errors = es->rx_errors;
806 ons->tx_errors = oes->tx_errors;
807 ns->tx_errors = es->tx_errors;
808 ons->multicast = oes->rx_multicast;
809 ns->multicast = es->rx_multicast;
810 ons->tx_dropped = oes->tx_discards;
811 ns->tx_dropped = es->tx_discards;
812
813 /* Get the port data only if this is the main PF VSI */
814 if (vsi == pf->vsi[pf->lan_vsi]) {
815 struct i40e_hw_port_stats *nsd = &pf->stats;
816 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
817
818 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
819 I40E_GLPRT_GORCL(hw->port),
820 pf->stat_offsets_loaded,
821 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
822 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
823 I40E_GLPRT_GOTCL(hw->port),
824 pf->stat_offsets_loaded,
825 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
826 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
827 pf->stat_offsets_loaded,
828 &osd->eth.rx_discards,
829 &nsd->eth.rx_discards);
830 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
831 pf->stat_offsets_loaded,
832 &osd->eth.tx_discards,
833 &nsd->eth.tx_discards);
834 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
835 I40E_GLPRT_MPRCL(hw->port),
836 pf->stat_offsets_loaded,
837 &osd->eth.rx_multicast,
838 &nsd->eth.rx_multicast);
839
840 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->tx_dropped_link_down,
843 &nsd->tx_dropped_link_down);
844
845 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
846 pf->stat_offsets_loaded,
847 &osd->crc_errors, &nsd->crc_errors);
848 ns->rx_crc_errors = nsd->crc_errors;
849
850 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->illegal_bytes, &nsd->illegal_bytes);
853 ns->rx_errors = nsd->crc_errors
854 + nsd->illegal_bytes;
855
856 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
857 pf->stat_offsets_loaded,
858 &osd->mac_local_faults,
859 &nsd->mac_local_faults);
860 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
861 pf->stat_offsets_loaded,
862 &osd->mac_remote_faults,
863 &nsd->mac_remote_faults);
864
865 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
866 pf->stat_offsets_loaded,
867 &osd->rx_length_errors,
868 &nsd->rx_length_errors);
869 ns->rx_length_errors = nsd->rx_length_errors;
870
871 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
872 pf->stat_offsets_loaded,
873 &osd->link_xon_rx, &nsd->link_xon_rx);
874 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
875 pf->stat_offsets_loaded,
876 &osd->link_xon_tx, &nsd->link_xon_tx);
877 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
878 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
879 pf->stat_offsets_loaded,
880 &osd->link_xoff_tx, &nsd->link_xoff_tx);
881
882 for (i = 0; i < 8; i++) {
883 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
884 pf->stat_offsets_loaded,
885 &osd->priority_xon_rx[i],
886 &nsd->priority_xon_rx[i]);
887 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
888 pf->stat_offsets_loaded,
889 &osd->priority_xon_tx[i],
890 &nsd->priority_xon_tx[i]);
891 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
892 pf->stat_offsets_loaded,
893 &osd->priority_xoff_tx[i],
894 &nsd->priority_xoff_tx[i]);
895 i40e_stat_update32(hw,
896 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
897 pf->stat_offsets_loaded,
898 &osd->priority_xon_2_xoff[i],
899 &nsd->priority_xon_2_xoff[i]);
900 }
901
902 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
903 I40E_GLPRT_PRC64L(hw->port),
904 pf->stat_offsets_loaded,
905 &osd->rx_size_64, &nsd->rx_size_64);
906 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
907 I40E_GLPRT_PRC127L(hw->port),
908 pf->stat_offsets_loaded,
909 &osd->rx_size_127, &nsd->rx_size_127);
910 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
911 I40E_GLPRT_PRC255L(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->rx_size_255, &nsd->rx_size_255);
914 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
915 I40E_GLPRT_PRC511L(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->rx_size_511, &nsd->rx_size_511);
918 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
919 I40E_GLPRT_PRC1023L(hw->port),
920 pf->stat_offsets_loaded,
921 &osd->rx_size_1023, &nsd->rx_size_1023);
922 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
923 I40E_GLPRT_PRC1522L(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->rx_size_1522, &nsd->rx_size_1522);
926 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
927 I40E_GLPRT_PRC9522L(hw->port),
928 pf->stat_offsets_loaded,
929 &osd->rx_size_big, &nsd->rx_size_big);
930
931 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
932 I40E_GLPRT_PTC64L(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->tx_size_64, &nsd->tx_size_64);
935 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
936 I40E_GLPRT_PTC127L(hw->port),
937 pf->stat_offsets_loaded,
938 &osd->tx_size_127, &nsd->tx_size_127);
939 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
940 I40E_GLPRT_PTC255L(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->tx_size_255, &nsd->tx_size_255);
943 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
944 I40E_GLPRT_PTC511L(hw->port),
945 pf->stat_offsets_loaded,
946 &osd->tx_size_511, &nsd->tx_size_511);
947 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
948 I40E_GLPRT_PTC1023L(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->tx_size_1023, &nsd->tx_size_1023);
951 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
952 I40E_GLPRT_PTC1522L(hw->port),
953 pf->stat_offsets_loaded,
954 &osd->tx_size_1522, &nsd->tx_size_1522);
955 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
956 I40E_GLPRT_PTC9522L(hw->port),
957 pf->stat_offsets_loaded,
958 &osd->tx_size_big, &nsd->tx_size_big);
959
960 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->rx_undersize, &nsd->rx_undersize);
963 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->rx_fragments, &nsd->rx_fragments);
966 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_oversize, &nsd->rx_oversize);
969 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
970 pf->stat_offsets_loaded,
971 &osd->rx_jabber, &nsd->rx_jabber);
972 }
973
974 pf->stat_offsets_loaded = true;
975}
976
977/**
978 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
979 * @vsi: the VSI to be searched
980 * @macaddr: the MAC address
981 * @vlan: the vlan
982 * @is_vf: make sure its a vf filter, else doesn't matter
983 * @is_netdev: make sure its a netdev filter, else doesn't matter
984 *
985 * Returns ptr to the filter object or NULL
986 **/
987static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
988 u8 *macaddr, s16 vlan,
989 bool is_vf, bool is_netdev)
990{
991 struct i40e_mac_filter *f;
992
993 if (!vsi || !macaddr)
994 return NULL;
995
996 list_for_each_entry(f, &vsi->mac_filter_list, list) {
997 if ((ether_addr_equal(macaddr, f->macaddr)) &&
998 (vlan == f->vlan) &&
999 (!is_vf || f->is_vf) &&
1000 (!is_netdev || f->is_netdev))
1001 return f;
1002 }
1003 return NULL;
1004}
1005
1006/**
1007 * i40e_find_mac - Find a mac addr in the macvlan filters list
1008 * @vsi: the VSI to be searched
1009 * @macaddr: the MAC address we are searching for
1010 * @is_vf: make sure its a vf filter, else doesn't matter
1011 * @is_netdev: make sure its a netdev filter, else doesn't matter
1012 *
1013 * Returns the first filter with the provided MAC address or NULL if
1014 * MAC address was not found
1015 **/
1016struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1017 bool is_vf, bool is_netdev)
1018{
1019 struct i40e_mac_filter *f;
1020
1021 if (!vsi || !macaddr)
1022 return NULL;
1023
1024 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1025 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1026 (!is_vf || f->is_vf) &&
1027 (!is_netdev || f->is_netdev))
1028 return f;
1029 }
1030 return NULL;
1031}
1032
1033/**
1034 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1035 * @vsi: the VSI to be searched
1036 *
1037 * Returns true if VSI is in vlan mode or false otherwise
1038 **/
1039bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1040{
1041 struct i40e_mac_filter *f;
1042
1043 /* Only -1 for all the filters denotes not in vlan mode
1044 * so we have to go through all the list in order to make sure
1045 */
1046 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1047 if (f->vlan >= 0)
1048 return true;
1049 }
1050
1051 return false;
1052}
1053
1054/**
1055 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1056 * @vsi: the VSI to be searched
1057 * @macaddr: the mac address to be filtered
1058 * @is_vf: true if it is a vf
1059 * @is_netdev: true if it is a netdev
1060 *
1061 * Goes through all the macvlan filters and adds a
1062 * macvlan filter for each unique vlan that already exists
1063 *
1064 * Returns first filter found on success, else NULL
1065 **/
1066struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1067 bool is_vf, bool is_netdev)
1068{
1069 struct i40e_mac_filter *f;
1070
1071 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1072 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1073 is_vf, is_netdev)) {
1074 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1075 is_vf, is_netdev))
1076 return NULL;
1077 }
1078 }
1079
1080 return list_first_entry_or_null(&vsi->mac_filter_list,
1081 struct i40e_mac_filter, list);
1082}
1083
1084/**
1085 * i40e_add_filter - Add a mac/vlan filter to the VSI
1086 * @vsi: the VSI to be searched
1087 * @macaddr: the MAC address
1088 * @vlan: the vlan
1089 * @is_vf: make sure its a vf filter, else doesn't matter
1090 * @is_netdev: make sure its a netdev filter, else doesn't matter
1091 *
1092 * Returns ptr to the filter object or NULL when no memory available.
1093 **/
1094struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1095 u8 *macaddr, s16 vlan,
1096 bool is_vf, bool is_netdev)
1097{
1098 struct i40e_mac_filter *f;
1099
1100 if (!vsi || !macaddr)
1101 return NULL;
1102
1103 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1104 if (!f) {
1105 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1106 if (!f)
1107 goto add_filter_out;
1108
1109 memcpy(f->macaddr, macaddr, ETH_ALEN);
1110 f->vlan = vlan;
1111 f->changed = true;
1112
1113 INIT_LIST_HEAD(&f->list);
1114 list_add(&f->list, &vsi->mac_filter_list);
1115 }
1116
1117 /* increment counter and add a new flag if needed */
1118 if (is_vf) {
1119 if (!f->is_vf) {
1120 f->is_vf = true;
1121 f->counter++;
1122 }
1123 } else if (is_netdev) {
1124 if (!f->is_netdev) {
1125 f->is_netdev = true;
1126 f->counter++;
1127 }
1128 } else {
1129 f->counter++;
1130 }
1131
1132 /* changed tells sync_filters_subtask to
1133 * push the filter down to the firmware
1134 */
1135 if (f->changed) {
1136 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1137 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1138 }
1139
1140add_filter_out:
1141 return f;
1142}
1143
1144/**
1145 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1146 * @vsi: the VSI to be searched
1147 * @macaddr: the MAC address
1148 * @vlan: the vlan
1149 * @is_vf: make sure it's a vf filter, else doesn't matter
1150 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1151 **/
1152void i40e_del_filter(struct i40e_vsi *vsi,
1153 u8 *macaddr, s16 vlan,
1154 bool is_vf, bool is_netdev)
1155{
1156 struct i40e_mac_filter *f;
1157
1158 if (!vsi || !macaddr)
1159 return;
1160
1161 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1162 if (!f || f->counter == 0)
1163 return;
1164
1165 if (is_vf) {
1166 if (f->is_vf) {
1167 f->is_vf = false;
1168 f->counter--;
1169 }
1170 } else if (is_netdev) {
1171 if (f->is_netdev) {
1172 f->is_netdev = false;
1173 f->counter--;
1174 }
1175 } else {
1176 /* make sure we don't remove a filter in use by vf or netdev */
1177 int min_f = 0;
1178 min_f += (f->is_vf ? 1 : 0);
1179 min_f += (f->is_netdev ? 1 : 0);
1180
1181 if (f->counter > min_f)
1182 f->counter--;
1183 }
1184
1185 /* counter == 0 tells sync_filters_subtask to
1186 * remove the filter from the firmware's list
1187 */
1188 if (f->counter == 0) {
1189 f->changed = true;
1190 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1191 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1192 }
1193}
1194
1195/**
1196 * i40e_set_mac - NDO callback to set mac address
1197 * @netdev: network interface device structure
1198 * @p: pointer to an address structure
1199 *
1200 * Returns 0 on success, negative on failure
1201 **/
1202static int i40e_set_mac(struct net_device *netdev, void *p)
1203{
1204 struct i40e_netdev_priv *np = netdev_priv(netdev);
1205 struct i40e_vsi *vsi = np->vsi;
1206 struct sockaddr *addr = p;
1207 struct i40e_mac_filter *f;
1208
1209 if (!is_valid_ether_addr(addr->sa_data))
1210 return -EADDRNOTAVAIL;
1211
1212 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1213
1214 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1215 return 0;
1216
80f6428f
ASJ		 1217 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1218 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1219 return -EADDRNOTAVAIL;
1220
41c445ff
JB		 1221 if (vsi->type == I40E_VSI_MAIN) {
1222 i40e_status ret;
1223 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1224 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1225 addr->sa_data, NULL);
1226 if (ret) {
1227 netdev_info(netdev,
1228 "Addr change for Main VSI failed: %d\n",
1229 ret);
1230 return -EADDRNOTAVAIL;
1231 }
1232
1233 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1234 }
1235
1236 /* In order to be sure to not drop any packets, add the new address
1237 * then delete the old one.
1238 */
1239 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1240 if (!f)
1241 return -ENOMEM;
1242
1243 i40e_sync_vsi_filters(vsi);
1244 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1245 i40e_sync_vsi_filters(vsi);
1246
1247 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1248
1249 return 0;
1250}
1251
1252/**
1253 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1254 * @vsi: the VSI being setup
1255 * @ctxt: VSI context structure
1256 * @enabled_tc: Enabled TCs bitmap
1257 * @is_add: True if called before Add VSI
1258 *
1259 * Setup VSI queue mapping for enabled traffic classes.
1260 **/
1261static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1262 struct i40e_vsi_context *ctxt,
1263 u8 enabled_tc,
1264 bool is_add)
1265{
1266 struct i40e_pf *pf = vsi->back;
1267 u16 sections = 0;
1268 u8 netdev_tc = 0;
1269 u16 numtc = 0;
1270 u16 qcount;
1271 u8 offset;
1272 u16 qmap;
1273 int i;
1274
1275 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1276 offset = 0;
1277
1278 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1279 /* Find numtc from enabled TC bitmap */
1280 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1281 if (enabled_tc & (1 << i)) /* TC is enabled */
1282 numtc++;
1283 }
1284 if (!numtc) {
1285 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1286 numtc = 1;
1287 }
1288 } else {
1289 /* At least TC0 is enabled in case of non-DCB case */
1290 numtc = 1;
1291 }
1292
1293 vsi->tc_config.numtc = numtc;
1294 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1295
1296 /* Setup queue offset/count for all TCs for given VSI */
1297 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1298 /* See if the given TC is enabled for the given VSI */
1299 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1300 int pow, num_qps;
1301
1302 vsi->tc_config.tc_info[i].qoffset = offset;
1303 switch (vsi->type) {
1304 case I40E_VSI_MAIN:
1305 if (i == 0)
1306 qcount = pf->rss_size;
1307 else
1308 qcount = pf->num_tc_qps;
1309 vsi->tc_config.tc_info[i].qcount = qcount;
1310 break;
1311 case I40E_VSI_FDIR:
1312 case I40E_VSI_SRIOV:
1313 case I40E_VSI_VMDQ2:
1314 default:
1315 qcount = vsi->alloc_queue_pairs;
1316 vsi->tc_config.tc_info[i].qcount = qcount;
1317 WARN_ON(i != 0);
1318 break;
1319 }
1320
1321 /* find the power-of-2 of the number of queue pairs */
1322 num_qps = vsi->tc_config.tc_info[i].qcount;
1323 pow = 0;
1324 while (num_qps &&
1325 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1326 pow++;
1327 num_qps >>= 1;
1328 }
1329
1330 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1331 qmap =
1332 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1333 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1334
1335 offset += vsi->tc_config.tc_info[i].qcount;
1336 } else {
1337 /* TC is not enabled so set the offset to
1338 * default queue and allocate one queue
1339 * for the given TC.
1340 */
1341 vsi->tc_config.tc_info[i].qoffset = 0;
1342 vsi->tc_config.tc_info[i].qcount = 1;
1343 vsi->tc_config.tc_info[i].netdev_tc = 0;
1344
1345 qmap = 0;
1346 }
1347 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1348 }
1349
1350 /* Set actual Tx/Rx queue pairs */
1351 vsi->num_queue_pairs = offset;
1352
1353 /* Scheduler section valid can only be set for ADD VSI */
1354 if (is_add) {
1355 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1356
1357 ctxt->info.up_enable_bits = enabled_tc;
1358 }
1359 if (vsi->type == I40E_VSI_SRIOV) {
1360 ctxt->info.mapping_flags |=
1361 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1362 for (i = 0; i < vsi->num_queue_pairs; i++)
1363 ctxt->info.queue_mapping[i] =
1364 cpu_to_le16(vsi->base_queue + i);
1365 } else {
1366 ctxt->info.mapping_flags |=
1367 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1368 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1369 }
1370 ctxt->info.valid_sections |= cpu_to_le16(sections);
1371}
1372
1373/**
1374 * i40e_set_rx_mode - NDO callback to set the netdev filters
1375 * @netdev: network interface device structure
1376 **/
1377static void i40e_set_rx_mode(struct net_device *netdev)
1378{
1379 struct i40e_netdev_priv *np = netdev_priv(netdev);
1380 struct i40e_mac_filter *f, *ftmp;
1381 struct i40e_vsi *vsi = np->vsi;
1382 struct netdev_hw_addr *uca;
1383 struct netdev_hw_addr *mca;
1384 struct netdev_hw_addr *ha;
1385
1386 /* add addr if not already in the filter list */
1387 netdev_for_each_uc_addr(uca, netdev) {
1388 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1389 if (i40e_is_vsi_in_vlan(vsi))
1390 i40e_put_mac_in_vlan(vsi, uca->addr,
1391 false, true);
1392 else
1393 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1394 false, true);
1395 }
1396 }
1397
1398 netdev_for_each_mc_addr(mca, netdev) {
1399 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1400 if (i40e_is_vsi_in_vlan(vsi))
1401 i40e_put_mac_in_vlan(vsi, mca->addr,
1402 false, true);
1403 else
1404 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1405 false, true);
1406 }
1407 }
1408
1409 /* remove filter if not in netdev list */
1410 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1411 bool found = false;
1412
1413 if (!f->is_netdev)
1414 continue;
1415
1416 if (is_multicast_ether_addr(f->macaddr)) {
1417 netdev_for_each_mc_addr(mca, netdev) {
1418 if (ether_addr_equal(mca->addr, f->macaddr)) {
1419 found = true;
1420 break;
1421 }
1422 }
1423 } else {
1424 netdev_for_each_uc_addr(uca, netdev) {
1425 if (ether_addr_equal(uca->addr, f->macaddr)) {
1426 found = true;
1427 break;
1428 }
1429 }
1430
1431 for_each_dev_addr(netdev, ha) {
1432 if (ether_addr_equal(ha->addr, f->macaddr)) {
1433 found = true;
1434 break;
1435 }
1436 }
1437 }
1438 if (!found)
1439 i40e_del_filter(
1440 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1441 }
1442
1443 /* check for other flag changes */
1444 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1445 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1446 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1447 }
1448}
1449
1450/**
1451 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1452 * @vsi: ptr to the VSI
1453 *
1454 * Push any outstanding VSI filter changes through the AdminQ.
1455 *
1456 * Returns 0 or error value
1457 **/
1458int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1459{
1460 struct i40e_mac_filter *f, *ftmp;
1461 bool promisc_forced_on = false;
1462 bool add_happened = false;
1463 int filter_list_len = 0;
1464 u32 changed_flags = 0;
dcae29be 1465 i40e_status aq_ret = 0;
41c445ff
JB		 1466 struct i40e_pf *pf;
1467 int num_add = 0;
1468 int num_del = 0;
1469 u16 cmd_flags;
1470
1471 /* empty array typed pointers, kcalloc later */
1472 struct i40e_aqc_add_macvlan_element_data *add_list;
1473 struct i40e_aqc_remove_macvlan_element_data *del_list;
1474
1475 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1476 usleep_range(1000, 2000);
1477 pf = vsi->back;
1478
1479 if (vsi->netdev) {
1480 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1481 vsi->current_netdev_flags = vsi->netdev->flags;
1482 }
1483
1484 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1485 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1486
1487 filter_list_len = pf->hw.aq.asq_buf_size /
1488 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1489 del_list = kcalloc(filter_list_len,
1490 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1491 GFP_KERNEL);
1492 if (!del_list)
1493 return -ENOMEM;
1494
1495 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1496 if (!f->changed)
1497 continue;
1498
1499 if (f->counter != 0)
1500 continue;
1501 f->changed = false;
1502 cmd_flags = 0;
1503
1504 /* add to delete list */
1505 memcpy(del_list[num_del].mac_addr,
1506 f->macaddr, ETH_ALEN);
1507 del_list[num_del].vlan_tag =
1508 cpu_to_le16((u16)(f->vlan ==
1509 I40E_VLAN_ANY ? 0 : f->vlan));
1510
41c445ff
JB		 1511 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1512 del_list[num_del].flags = cmd_flags;
1513 num_del++;
1514
1515 /* unlink from filter list */
1516 list_del(&f->list);
1517 kfree(f);
1518
1519 /* flush a full buffer */
1520 if (num_del == filter_list_len) {
dcae29be 1521 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1522 vsi->seid, del_list, num_del,
1523 NULL);
1524 num_del = 0;
1525 memset(del_list, 0, sizeof(*del_list));
1526
dcae29be 1527 if (aq_ret)
41c445ff
JB		 1528 dev_info(&pf->pdev->dev,
1529 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1530 aq_ret,
41c445ff
JB		 1531 pf->hw.aq.asq_last_status);
1532 }
1533 }
1534 if (num_del) {
dcae29be 1535 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1536 del_list, num_del, NULL);
1537 num_del = 0;
1538
dcae29be 1539 if (aq_ret)
41c445ff
JB		 1540 dev_info(&pf->pdev->dev,
1541 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1542 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1543 }
1544
1545 kfree(del_list);
1546 del_list = NULL;
1547
1548 /* do all the adds now */
1549 filter_list_len = pf->hw.aq.asq_buf_size /
1550 sizeof(struct i40e_aqc_add_macvlan_element_data),
1551 add_list = kcalloc(filter_list_len,
1552 sizeof(struct i40e_aqc_add_macvlan_element_data),
1553 GFP_KERNEL);
1554 if (!add_list)
1555 return -ENOMEM;
1556
1557 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1558 if (!f->changed)
1559 continue;
1560
1561 if (f->counter == 0)
1562 continue;
1563 f->changed = false;
1564 add_happened = true;
1565 cmd_flags = 0;
1566
1567 /* add to add array */
1568 memcpy(add_list[num_add].mac_addr,
1569 f->macaddr, ETH_ALEN);
1570 add_list[num_add].vlan_tag =
1571 cpu_to_le16(
1572 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1573 add_list[num_add].queue_number = 0;
1574
1575 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1576 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1577 num_add++;
1578
1579 /* flush a full buffer */
1580 if (num_add == filter_list_len) {
dcae29be
JB		 1581 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1582 add_list, num_add,
1583 NULL);
41c445ff
JB		 1584 num_add = 0;
1585
dcae29be 1586 if (aq_ret)
41c445ff
JB		 1587 break;
1588 memset(add_list, 0, sizeof(*add_list));
1589 }
1590 }
1591 if (num_add) {
dcae29be
JB		 1592 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1593 add_list, num_add, NULL);
41c445ff
JB		 1594 num_add = 0;
1595 }
1596 kfree(add_list);
1597 add_list = NULL;
1598
dcae29be 1599 if (add_happened && (!aq_ret)) {
41c445ff 1600 /* do nothing */;
dcae29be 1601 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1602 dev_info(&pf->pdev->dev,
1603 "add filter failed, err %d, aq_err %d\n",
dcae29be 1604 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1605 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1606 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1607 &vsi->state)) {
1608 promisc_forced_on = true;
1609 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1610 &vsi->state);
1611 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1612 }
1613 }
1614 }
1615
1616 /* check for changes in promiscuous modes */
1617 if (changed_flags & IFF_ALLMULTI) {
1618 bool cur_multipromisc;
1619 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1620 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1621 vsi->seid,
1622 cur_multipromisc,
1623 NULL);
1624 if (aq_ret)
41c445ff
JB		 1625 dev_info(&pf->pdev->dev,
1626 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1627 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1628 }
1629 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1630 bool cur_promisc;
1631 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1632 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1633 &vsi->state));
dcae29be
JB		 1634 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1635 vsi->seid,
1636 cur_promisc, NULL);
1637 if (aq_ret)
41c445ff
JB		 1638 dev_info(&pf->pdev->dev,
1639 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1640 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1641 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1642 vsi->seid,
1643 cur_promisc, NULL);
1644 if (aq_ret)
1645 dev_info(&pf->pdev->dev,
1646 "set brdcast promisc failed, err %d, aq_err %d\n",
1647 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1648 }
1649
1650 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1651 return 0;
1652}
1653
1654/**
1655 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1656 * @pf: board private structure
1657 **/
1658static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1659{
1660 int v;
1661
1662 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1663 return;
1664 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1665
1666 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1667 if (pf->vsi[v] &&
1668 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1669 i40e_sync_vsi_filters(pf->vsi[v]);
1670 }
1671}
1672
1673/**
1674 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1675 * @netdev: network interface device structure
1676 * @new_mtu: new value for maximum frame size
1677 *
1678 * Returns 0 on success, negative on failure
1679 **/
1680static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1681{
1682 struct i40e_netdev_priv *np = netdev_priv(netdev);
1683 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1684 struct i40e_vsi *vsi = np->vsi;
1685
1686 /* MTU < 68 is an error and causes problems on some kernels */
1687 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1688 return -EINVAL;
1689
1690 netdev_info(netdev, "changing MTU from %d to %d\n",
1691 netdev->mtu, new_mtu);
1692 netdev->mtu = new_mtu;
1693 if (netif_running(netdev))
1694 i40e_vsi_reinit_locked(vsi);
1695
1696 return 0;
1697}
1698
1699/**
1700 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1701 * @vsi: the vsi being adjusted
1702 **/
1703void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1704{
1705 struct i40e_vsi_context ctxt;
1706 i40e_status ret;
1707
1708 if ((vsi->info.valid_sections &
1709 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1710 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1711 return; /* already enabled */
1712
1713 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1714 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1715 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1716
1717 ctxt.seid = vsi->seid;
1718 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1719 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1720 if (ret) {
1721 dev_info(&vsi->back->pdev->dev,
1722 "%s: update vsi failed, aq_err=%d\n",
1723 __func__, vsi->back->hw.aq.asq_last_status);
1724 }
1725}
1726
1727/**
1728 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1729 * @vsi: the vsi being adjusted
1730 **/
1731void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1732{
1733 struct i40e_vsi_context ctxt;
1734 i40e_status ret;
1735
1736 if ((vsi->info.valid_sections &
1737 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1738 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1739 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1740 return; /* already disabled */
1741
1742 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1743 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1744 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1745
1746 ctxt.seid = vsi->seid;
1747 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1748 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1749 if (ret) {
1750 dev_info(&vsi->back->pdev->dev,
1751 "%s: update vsi failed, aq_err=%d\n",
1752 __func__, vsi->back->hw.aq.asq_last_status);
1753 }
1754}
1755
1756/**
1757 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1758 * @netdev: network interface to be adjusted
1759 * @features: netdev features to test if VLAN offload is enabled or not
1760 **/
1761static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1762{
1763 struct i40e_netdev_priv *np = netdev_priv(netdev);
1764 struct i40e_vsi *vsi = np->vsi;
1765
1766 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1767 i40e_vlan_stripping_enable(vsi);
1768 else
1769 i40e_vlan_stripping_disable(vsi);
1770}
1771
1772/**
1773 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1774 * @vsi: the vsi being configured
1775 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1776 **/
1777int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1778{
1779 struct i40e_mac_filter *f, *add_f;
1780 bool is_netdev, is_vf;
41c445ff
JB		 1781
1782 is_vf = (vsi->type == I40E_VSI_SRIOV);
1783 is_netdev = !!(vsi->netdev);
1784
1785 if (is_netdev) {
1786 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1787 is_vf, is_netdev);
1788 if (!add_f) {
1789 dev_info(&vsi->back->pdev->dev,
1790 "Could not add vlan filter %d for %pM\n",
1791 vid, vsi->netdev->dev_addr);
1792 return -ENOMEM;
1793 }
1794 }
1795
1796 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1797 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1798 if (!add_f) {
1799 dev_info(&vsi->back->pdev->dev,
1800 "Could not add vlan filter %d for %pM\n",
1801 vid, f->macaddr);
1802 return -ENOMEM;
1803 }
1804 }
1805
41c445ff
JB		 1806 /* Now if we add a vlan tag, make sure to check if it is the first
1807 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1808 * with 0, so we now accept untagged and specified tagged traffic
1809 * (and not any taged and untagged)
1810 */
1811 if (vid > 0) {
1812 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1813 I40E_VLAN_ANY,
1814 is_vf, is_netdev)) {
1815 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1816 I40E_VLAN_ANY, is_vf, is_netdev);
1817 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1818 is_vf, is_netdev);
1819 if (!add_f) {
1820 dev_info(&vsi->back->pdev->dev,
1821 "Could not add filter 0 for %pM\n",
1822 vsi->netdev->dev_addr);
1823 return -ENOMEM;
1824 }
1825 }
1826
1827 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1828 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1829 is_vf, is_netdev)) {
1830 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1831 is_vf, is_netdev);
1832 add_f = i40e_add_filter(vsi, f->macaddr,
1833 0, is_vf, is_netdev);
1834 if (!add_f) {
1835 dev_info(&vsi->back->pdev->dev,
1836 "Could not add filter 0 for %pM\n",
1837 f->macaddr);
1838 return -ENOMEM;
1839 }
1840 }
1841 }
41c445ff
JB		 1842 }
1843
80f6428f
ASJ		 1844 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1845 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1846 return 0;
1847
1848 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1849}
1850
1851/**
1852 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1853 * @vsi: the vsi being configured
1854 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1855 *
1856 * Return: 0 on success or negative otherwise
41c445ff
JB		 1857 **/
1858int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1859{
1860 struct net_device *netdev = vsi->netdev;
1861 struct i40e_mac_filter *f, *add_f;
1862 bool is_vf, is_netdev;
1863 int filter_count = 0;
41c445ff
JB		 1864
1865 is_vf = (vsi->type == I40E_VSI_SRIOV);
1866 is_netdev = !!(netdev);
1867
1868 if (is_netdev)
1869 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1870
1871 list_for_each_entry(f, &vsi->mac_filter_list, list)
1872 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1873
41c445ff
JB		 1874 /* go through all the filters for this VSI and if there is only
1875 * vid == 0 it means there are no other filters, so vid 0 must
1876 * be replaced with -1. This signifies that we should from now
1877 * on accept any traffic (with any tag present, or untagged)
1878 */
1879 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1880 if (is_netdev) {
1881 if (f->vlan &&
1882 ether_addr_equal(netdev->dev_addr, f->macaddr))
1883 filter_count++;
1884 }
1885
1886 if (f->vlan)
1887 filter_count++;
1888 }
1889
1890 if (!filter_count && is_netdev) {
1891 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1892 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1893 is_vf, is_netdev);
1894 if (!f) {
1895 dev_info(&vsi->back->pdev->dev,
1896 "Could not add filter %d for %pM\n",
1897 I40E_VLAN_ANY, netdev->dev_addr);
1898 return -ENOMEM;
1899 }
1900 }
1901
1902 if (!filter_count) {
1903 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1904 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1905 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1906 is_vf, is_netdev);
1907 if (!add_f) {
1908 dev_info(&vsi->back->pdev->dev,
1909 "Could not add filter %d for %pM\n",
1910 I40E_VLAN_ANY, f->macaddr);
1911 return -ENOMEM;
1912 }
1913 }
1914 }
1915
80f6428f
ASJ		 1916 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1917 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1918 return 0;
1919
41c445ff
JB		 1920 return i40e_sync_vsi_filters(vsi);
1921}
1922
1923/**
1924 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1925 * @netdev: network interface to be adjusted
1926 * @vid: vlan id to be added
078b5876
JB		 1927 *
1928 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1929 **/
1930static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1931 __always_unused __be16 proto, u16 vid)
1932{
1933 struct i40e_netdev_priv *np = netdev_priv(netdev);
1934 struct i40e_vsi *vsi = np->vsi;
078b5876 1935 int ret = 0;
41c445ff
JB		 1936
1937 if (vid > 4095)
078b5876
JB		 1938 return -EINVAL;
1939
1940 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1941
41c445ff
JB		 1942 /* If the network stack called us with vid = 0, we should
1943 * indicate to i40e_vsi_add_vlan() that we want to receive
1944 * any traffic (i.e. with any vlan tag, or untagged)
1945 */
1946 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1947
078b5876
JB		 1948 if (!ret && (vid < VLAN_N_VID))
1949 set_bit(vid, vsi->active_vlans);
41c445ff 1950
078b5876 1951 return ret;
41c445ff
JB		 1952}
1953
1954/**
1955 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1956 * @netdev: network interface to be adjusted
1957 * @vid: vlan id to be removed
078b5876
JB		 1958 *
1959 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1960 **/
1961static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1962 __always_unused __be16 proto, u16 vid)
1963{
1964 struct i40e_netdev_priv *np = netdev_priv(netdev);
1965 struct i40e_vsi *vsi = np->vsi;
1966
078b5876
JB		 1967 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1968
41c445ff
JB		 1969 /* return code is ignored as there is nothing a user
1970 * can do about failure to remove and a log message was
078b5876 1971 * already printed from the other function
41c445ff
JB		 1972 */
1973 i40e_vsi_kill_vlan(vsi, vid);
1974
1975 clear_bit(vid, vsi->active_vlans);
078b5876 1976
41c445ff
JB		 1977 return 0;
1978}
1979
1980/**
1981 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
1982 * @vsi: the vsi being brought back up
1983 **/
1984static void i40e_restore_vlan(struct i40e_vsi *vsi)
1985{
1986 u16 vid;
1987
1988 if (!vsi->netdev)
1989 return;
1990
1991 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
1992
1993 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
1994 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
1995 vid);
1996}
1997
1998/**
1999 * i40e_vsi_add_pvid - Add pvid for the VSI
2000 * @vsi: the vsi being adjusted
2001 * @vid: the vlan id to set as a PVID
2002 **/
dcae29be 2003int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2004{
2005 struct i40e_vsi_context ctxt;
dcae29be 2006 i40e_status aq_ret;
41c445ff
JB		 2007
2008 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2009 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2010 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2011 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2012 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2013
2014 ctxt.seid = vsi->seid;
2015 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2016 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2017 if (aq_ret) {
41c445ff
JB		 2018 dev_info(&vsi->back->pdev->dev,
2019 "%s: update vsi failed, aq_err=%d\n",
2020 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2021 return -ENOENT;
41c445ff
JB		 2022 }
2023
dcae29be 2024 return 0;
41c445ff
JB		 2025}
2026
2027/**
2028 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2029 * @vsi: the vsi being adjusted
2030 *
2031 * Just use the vlan_rx_register() service to put it back to normal
2032 **/
2033void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2034{
6c12fcbf
GR		 2035 i40e_vlan_stripping_disable(vsi);
2036
41c445ff 2037 vsi->info.pvid = 0;
41c445ff
JB		 2038}
2039
2040/**
2041 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2042 * @vsi: ptr to the VSI
2043 *
2044 * If this function returns with an error, then it's possible one or
2045 * more of the rings is populated (while the rest are not). It is the
2046 * callers duty to clean those orphaned rings.
2047 *
2048 * Return 0 on success, negative on failure
2049 **/
2050static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2051{
2052 int i, err = 0;
2053
2054 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2055 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2056
2057 return err;
2058}
2059
2060/**
2061 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2062 * @vsi: ptr to the VSI
2063 *
2064 * Free VSI's transmit software resources
2065 **/
2066static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2067{
2068 int i;
2069
2070 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2071 if (vsi->tx_rings[i]->desc)
2072 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2073}
2074
2075/**
2076 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2077 * @vsi: ptr to the VSI
2078 *
2079 * If this function returns with an error, then it's possible one or
2080 * more of the rings is populated (while the rest are not). It is the
2081 * callers duty to clean those orphaned rings.
2082 *
2083 * Return 0 on success, negative on failure
2084 **/
2085static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2086{
2087 int i, err = 0;
2088
2089 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2090 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2091 return err;
2092}
2093
2094/**
2095 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2096 * @vsi: ptr to the VSI
2097 *
2098 * Free all receive software resources
2099 **/
2100static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2101{
2102 int i;
2103
2104 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2105 if (vsi->rx_rings[i]->desc)
2106 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2107}
2108
2109/**
2110 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2111 * @ring: The Tx ring to configure
2112 *
2113 * Configure the Tx descriptor ring in the HMC context.
2114 **/
2115static int i40e_configure_tx_ring(struct i40e_ring *ring)
2116{
2117 struct i40e_vsi *vsi = ring->vsi;
2118 u16 pf_q = vsi->base_queue + ring->queue_index;
2119 struct i40e_hw *hw = &vsi->back->hw;
2120 struct i40e_hmc_obj_txq tx_ctx;
2121 i40e_status err = 0;
2122 u32 qtx_ctl = 0;
2123
2124 /* some ATR related tx ring init */
2125 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2126 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2127 ring->atr_count = 0;
2128 } else {
2129 ring->atr_sample_rate = 0;
2130 }
2131
2132 /* initialize XPS */
2133 if (ring->q_vector && ring->netdev &&
2134 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2135 netif_set_xps_queue(ring->netdev,
2136 &ring->q_vector->affinity_mask,
2137 ring->queue_index);
2138
2139 /* clear the context structure first */
2140 memset(&tx_ctx, 0, sizeof(tx_ctx));
2141
2142 tx_ctx.new_context = 1;
2143 tx_ctx.base = (ring->dma / 128);
2144 tx_ctx.qlen = ring->count;
2145 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
2146 I40E_FLAG_FDIR_ATR_ENABLED));
2147
2148 /* As part of VSI creation/update, FW allocates certain
2149 * Tx arbitration queue sets for each TC enabled for
2150 * the VSI. The FW returns the handles to these queue
2151 * sets as part of the response buffer to Add VSI,
2152 * Update VSI, etc. AQ commands. It is expected that
2153 * these queue set handles be associated with the Tx
2154 * queues by the driver as part of the TX queue context
2155 * initialization. This has to be done regardless of
2156 * DCB as by default everything is mapped to TC0.
2157 */
2158 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2159 tx_ctx.rdylist_act = 0;
2160
2161 /* clear the context in the HMC */
2162 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2163 if (err) {
2164 dev_info(&vsi->back->pdev->dev,
2165 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2166 ring->queue_index, pf_q, err);
2167 return -ENOMEM;
2168 }
2169
2170 /* set the context in the HMC */
2171 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2172 if (err) {
2173 dev_info(&vsi->back->pdev->dev,
2174 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2175 ring->queue_index, pf_q, err);
2176 return -ENOMEM;
2177 }
2178
2179 /* Now associate this queue with this PCI function */
2180 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2181 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2182 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2183 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2184 i40e_flush(hw);
2185
2186 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2187
2188 /* cache tail off for easier writes later */
2189 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2190
2191 return 0;
2192}
2193
2194/**
2195 * i40e_configure_rx_ring - Configure a receive ring context
2196 * @ring: The Rx ring to configure
2197 *
2198 * Configure the Rx descriptor ring in the HMC context.
2199 **/
2200static int i40e_configure_rx_ring(struct i40e_ring *ring)
2201{
2202 struct i40e_vsi *vsi = ring->vsi;
2203 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2204 u16 pf_q = vsi->base_queue + ring->queue_index;
2205 struct i40e_hw *hw = &vsi->back->hw;
2206 struct i40e_hmc_obj_rxq rx_ctx;
2207 i40e_status err = 0;
2208
2209 ring->state = 0;
2210
2211 /* clear the context structure first */
2212 memset(&rx_ctx, 0, sizeof(rx_ctx));
2213
2214 ring->rx_buf_len = vsi->rx_buf_len;
2215 ring->rx_hdr_len = vsi->rx_hdr_len;
2216
2217 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2218 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2219
2220 rx_ctx.base = (ring->dma / 128);
2221 rx_ctx.qlen = ring->count;
2222
2223 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2224 set_ring_16byte_desc_enabled(ring);
2225 rx_ctx.dsize = 0;
2226 } else {
2227 rx_ctx.dsize = 1;
2228 }
2229
2230 rx_ctx.dtype = vsi->dtype;
2231 if (vsi->dtype) {
2232 set_ring_ps_enabled(ring);
2233 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2234 I40E_RX_SPLIT_IP |
2235 I40E_RX_SPLIT_TCP_UDP |
2236 I40E_RX_SPLIT_SCTP;
2237 } else {
2238 rx_ctx.hsplit_0 = 0;
2239 }
2240
2241 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2242 (chain_len * ring->rx_buf_len));
2243 rx_ctx.tphrdesc_ena = 1;
2244 rx_ctx.tphwdesc_ena = 1;
2245 rx_ctx.tphdata_ena = 1;
2246 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2247 if (hw->revision_id == 0)
2248 rx_ctx.lrxqthresh = 0;
2249 else
2250 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2251 rx_ctx.crcstrip = 1;
2252 rx_ctx.l2tsel = 1;
2253 rx_ctx.showiv = 1;
2254
2255 /* clear the context in the HMC */
2256 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2257 if (err) {
2258 dev_info(&vsi->back->pdev->dev,
2259 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2260 ring->queue_index, pf_q, err);
2261 return -ENOMEM;
2262 }
2263
2264 /* set the context in the HMC */
2265 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2266 if (err) {
2267 dev_info(&vsi->back->pdev->dev,
2268 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2269 ring->queue_index, pf_q, err);
2270 return -ENOMEM;
2271 }
2272
2273 /* cache tail for quicker writes, and clear the reg before use */
2274 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2275 writel(0, ring->tail);
2276
2277 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2278
2279 return 0;
2280}
2281
2282/**
2283 * i40e_vsi_configure_tx - Configure the VSI for Tx
2284 * @vsi: VSI structure describing this set of rings and resources
2285 *
2286 * Configure the Tx VSI for operation.
2287 **/
2288static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2289{
2290 int err = 0;
2291 u16 i;
2292
9f65e15b
AD		 2293 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2294 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2295
2296 return err;
2297}
2298
2299/**
2300 * i40e_vsi_configure_rx - Configure the VSI for Rx
2301 * @vsi: the VSI being configured
2302 *
2303 * Configure the Rx VSI for operation.
2304 **/
2305static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2306{
2307 int err = 0;
2308 u16 i;
2309
2310 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2311 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2312 + ETH_FCS_LEN + VLAN_HLEN;
2313 else
2314 vsi->max_frame = I40E_RXBUFFER_2048;
2315
2316 /* figure out correct receive buffer length */
2317 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2318 I40E_FLAG_RX_PS_ENABLED)) {
2319 case I40E_FLAG_RX_1BUF_ENABLED:
2320 vsi->rx_hdr_len = 0;
2321 vsi->rx_buf_len = vsi->max_frame;
2322 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2323 break;
2324 case I40E_FLAG_RX_PS_ENABLED:
2325 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2326 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2327 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2328 break;
2329 default:
2330 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2331 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2332 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2333 break;
2334 }
2335
2336 /* round up for the chip's needs */
2337 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2338 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2339 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2340 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2341
2342 /* set up individual rings */
2343 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2344 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2345
2346 return err;
2347}
2348
2349/**
2350 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2351 * @vsi: ptr to the VSI
2352 **/
2353static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2354{
2355 u16 qoffset, qcount;
2356 int i, n;
2357
2358 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2359 return;
2360
2361 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2362 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2363 continue;
2364
2365 qoffset = vsi->tc_config.tc_info[n].qoffset;
2366 qcount = vsi->tc_config.tc_info[n].qcount;
2367 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2368 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2369 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2370 rx_ring->dcb_tc = n;
2371 tx_ring->dcb_tc = n;
2372 }
2373 }
2374}
2375
2376/**
2377 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2378 * @vsi: ptr to the VSI
2379 **/
2380static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2381{
2382 if (vsi->netdev)
2383 i40e_set_rx_mode(vsi->netdev);
2384}
2385
2386/**
2387 * i40e_vsi_configure - Set up the VSI for action
2388 * @vsi: the VSI being configured
2389 **/
2390static int i40e_vsi_configure(struct i40e_vsi *vsi)
2391{
2392 int err;
2393
2394 i40e_set_vsi_rx_mode(vsi);
2395 i40e_restore_vlan(vsi);
2396 i40e_vsi_config_dcb_rings(vsi);
2397 err = i40e_vsi_configure_tx(vsi);
2398 if (!err)
2399 err = i40e_vsi_configure_rx(vsi);
2400
2401 return err;
2402}
2403
2404/**
2405 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2406 * @vsi: the VSI being configured
2407 **/
2408static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2409{
2410 struct i40e_pf *pf = vsi->back;
2411 struct i40e_q_vector *q_vector;
2412 struct i40e_hw *hw = &pf->hw;
2413 u16 vector;
2414 int i, q;
2415 u32 val;
2416 u32 qp;
2417
2418 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2419 * and PFINT_LNKLSTn registers, e.g.:
2420 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2421 */
2422 qp = vsi->base_queue;
2423 vector = vsi->base_vector;
493fb300
AD		 2424 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2425 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2426 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2427 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2428 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2429 q_vector->rx.itr);
2430 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2431 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2432 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2433 q_vector->tx.itr);
2434
2435 /* Linked list for the queuepairs assigned to this vector */
2436 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2437 for (q = 0; q < q_vector->num_ringpairs; q++) {
2438 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2439 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2440 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2441 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2442 (I40E_QUEUE_TYPE_TX
2443 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2444
2445 wr32(hw, I40E_QINT_RQCTL(qp), val);
2446
2447 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2448 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2449 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2450 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2451 (I40E_QUEUE_TYPE_RX
2452 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2453
2454 /* Terminate the linked list */
2455 if (q == (q_vector->num_ringpairs - 1))
2456 val |= (I40E_QUEUE_END_OF_LIST
2457 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2458
2459 wr32(hw, I40E_QINT_TQCTL(qp), val);
2460 qp++;
2461 }
2462 }
2463
2464 i40e_flush(hw);
2465}
2466
2467/**
2468 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2469 * @hw: ptr to the hardware info
2470 **/
2471static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2472{
2473 u32 val;
2474
2475 /* clear things first */
2476 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2477 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2478
2479 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2480 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2481 I40E_PFINT_ICR0_ENA_GRST_MASK |
2482 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2483 I40E_PFINT_ICR0_ENA_GPIO_MASK |
2484 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2485 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2486 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2487 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2488
2489 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2490
2491 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2492 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2493 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2494
2495 /* OTHER_ITR_IDX = 0 */
2496 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2497}
2498
2499/**
2500 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2501 * @vsi: the VSI being configured
2502 **/
2503static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2504{
493fb300 2505 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2506 struct i40e_pf *pf = vsi->back;
2507 struct i40e_hw *hw = &pf->hw;
2508 u32 val;
2509
2510 /* set the ITR configuration */
2511 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2512 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2513 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2514 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2515 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2516 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2517
2518 i40e_enable_misc_int_causes(hw);
2519
2520 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2521 wr32(hw, I40E_PFINT_LNKLST0, 0);
2522
2523 /* Associate the queue pair to the vector and enable the q int */
2524 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2525 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2526 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2527
2528 wr32(hw, I40E_QINT_RQCTL(0), val);
2529
2530 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2531 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2532 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2533
2534 wr32(hw, I40E_QINT_TQCTL(0), val);
2535 i40e_flush(hw);
2536}
2537
2ef28cfb
MW		 2538/**
2539 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2540 * @pf: board private structure
2541 **/
2542void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2543{
2544 struct i40e_hw *hw = &pf->hw;
2545
2546 wr32(hw, I40E_PFINT_DYN_CTL0,
2547 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2548 i40e_flush(hw);
2549}
2550
41c445ff
JB		 2551/**
2552 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2553 * @pf: board private structure
2554 **/
116a57d4 2555void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2556{
2557 struct i40e_hw *hw = &pf->hw;
2558 u32 val;
2559
2560 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2561 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2562 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2563
2564 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2565 i40e_flush(hw);
2566}
2567
2568/**
2569 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2570 * @vsi: pointer to a vsi
2571 * @vector: enable a particular Hw Interrupt vector
2572 **/
2573void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2574{
2575 struct i40e_pf *pf = vsi->back;
2576 struct i40e_hw *hw = &pf->hw;
2577 u32 val;
2578
2579 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2580 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2581 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2582 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2583 /* skip the flush */
41c445ff
JB		 2584}
2585
2586/**
2587 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2588 * @irq: interrupt number
2589 * @data: pointer to a q_vector
2590 **/
2591static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2592{
2593 struct i40e_q_vector *q_vector = data;
2594
cd0b6fa6 2595 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2596 return IRQ_HANDLED;
2597
2598 napi_schedule(&q_vector->napi);
2599
2600 return IRQ_HANDLED;
2601}
2602
2603/**
2604 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2605 * @irq: interrupt number
2606 * @data: pointer to a q_vector
2607 **/
2608static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2609{
2610 struct i40e_q_vector *q_vector = data;
2611
cd0b6fa6 2612 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2613 return IRQ_HANDLED;
2614
2615 pr_info("fdir ring cleaning needed\n");
2616
2617 return IRQ_HANDLED;
2618}
2619
2620/**
2621 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2622 * @vsi: the VSI being configured
2623 * @basename: name for the vector
2624 *
2625 * Allocates MSI-X vectors and requests interrupts from the kernel.
2626 **/
2627static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2628{
2629 int q_vectors = vsi->num_q_vectors;
2630 struct i40e_pf *pf = vsi->back;
2631 int base = vsi->base_vector;
2632 int rx_int_idx = 0;
2633 int tx_int_idx = 0;
2634 int vector, err;
2635
2636 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2637 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2638
cd0b6fa6 2639 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2640 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2641 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2642 tx_int_idx++;
cd0b6fa6 2643 } else if (q_vector->rx.ring) {
41c445ff
JB		 2644 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2645 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2646 } else if (q_vector->tx.ring) {
41c445ff
JB		 2647 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2648 "%s-%s-%d", basename, "tx", tx_int_idx++);
2649 } else {
2650 /* skip this unused q_vector */
2651 continue;
2652 }
2653 err = request_irq(pf->msix_entries[base + vector].vector,
2654 vsi->irq_handler,
2655 0,
2656 q_vector->name,
2657 q_vector);
2658 if (err) {
2659 dev_info(&pf->pdev->dev,
2660 "%s: request_irq failed, error: %d\n",
2661 __func__, err);
2662 goto free_queue_irqs;
2663 }
2664 /* assign the mask for this irq */
2665 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2666 &q_vector->affinity_mask);
2667 }
2668
2669 return 0;
2670
2671free_queue_irqs:
2672 while (vector) {
2673 vector--;
2674 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2675 NULL);
2676 free_irq(pf->msix_entries[base + vector].vector,
2677 &(vsi->q_vectors[vector]));
2678 }
2679 return err;
2680}
2681
2682/**
2683 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2684 * @vsi: the VSI being un-configured
2685 **/
2686static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2687{
2688 struct i40e_pf *pf = vsi->back;
2689 struct i40e_hw *hw = &pf->hw;
2690 int base = vsi->base_vector;
2691 int i;
2692
2693 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2694 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2695 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2696 }
2697
2698 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2699 for (i = vsi->base_vector;
2700 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2701 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2702
2703 i40e_flush(hw);
2704 for (i = 0; i < vsi->num_q_vectors; i++)
2705 synchronize_irq(pf->msix_entries[i + base].vector);
2706 } else {
2707 /* Legacy and MSI mode - this stops all interrupt handling */
2708 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2709 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2710 i40e_flush(hw);
2711 synchronize_irq(pf->pdev->irq);
2712 }
2713}
2714
2715/**
2716 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2717 * @vsi: the VSI being configured
2718 **/
2719static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2720{
2721 struct i40e_pf *pf = vsi->back;
2722 int i;
2723
2724 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2725 for (i = vsi->base_vector;
2726 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2727 i40e_irq_dynamic_enable(vsi, i);
2728 } else {
2729 i40e_irq_dynamic_enable_icr0(pf);
2730 }
2731
1022cb6c 2732 i40e_flush(&pf->hw);
41c445ff
JB		 2733 return 0;
2734}
2735
2736/**
2737 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2738 * @pf: board private structure
2739 **/
2740static void i40e_stop_misc_vector(struct i40e_pf *pf)
2741{
2742 /* Disable ICR 0 */
2743 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2744 i40e_flush(&pf->hw);
2745}
2746
2747/**
2748 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2749 * @irq: interrupt number
2750 * @data: pointer to a q_vector
2751 *
2752 * This is the handler used for all MSI/Legacy interrupts, and deals
2753 * with both queue and non-queue interrupts. This is also used in
2754 * MSIX mode to handle the non-queue interrupts.
2755 **/
2756static irqreturn_t i40e_intr(int irq, void *data)
2757{
2758 struct i40e_pf *pf = (struct i40e_pf *)data;
2759 struct i40e_hw *hw = &pf->hw;
5e823066 2760 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2761 u32 icr0, icr0_remaining;
2762 u32 val, ena_mask;
2763
2764 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2765 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2766
116a57d4
SN		 2767 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2768 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2769 goto enable_intr;
41c445ff 2770
cd92e72f
SN		 2771 /* if interrupt but no bits showing, must be SWINT */
2772 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2773 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2774 pf->sw_int_count++;
2775
41c445ff
JB		 2776 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2777 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2778
2779 /* temporarily disable queue cause for NAPI processing */
2780 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2781 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2782 wr32(hw, I40E_QINT_RQCTL(0), qval);
2783
2784 qval = rd32(hw, I40E_QINT_TQCTL(0));
2785 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2786 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2787
2788 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2789 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2790 }
2791
2792 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2793 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2794 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2795 }
2796
2797 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2798 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2799 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2800 }
2801
2802 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2803 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2804 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2805 }
2806
2807 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2808 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2809 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2810 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2811 val = rd32(hw, I40E_GLGEN_RSTAT);
2812 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2813 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2814 if (val == I40E_RESET_CORER)
41c445ff 2815 pf->corer_count++;
d52cf0a9 2816 else if (val == I40E_RESET_GLOBR)
41c445ff 2817 pf->globr_count++;
d52cf0a9 2818 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2819 pf->empr_count++;
2820 }
2821
9c010ee0
ASJ		 2822 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2823 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2824 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2825 }
2826
41c445ff
JB		 2827 /* If a critical error is pending we have no choice but to reset the
2828 * device.
2829 * Report and mask out any remaining unexpected interrupts.
2830 */
2831 icr0_remaining = icr0 & ena_mask;
2832 if (icr0_remaining) {
2833 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2834 icr0_remaining);
9c010ee0 2835 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2836 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2837 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2838 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2839 dev_info(&pf->pdev->dev, "device will be reset\n");
2840 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2841 i40e_service_event_schedule(pf);
41c445ff
JB		 2842 }
2843 ena_mask &= ~icr0_remaining;
2844 }
5e823066 2845 ret = IRQ_HANDLED;
41c445ff 2846
5e823066 2847enable_intr:
41c445ff
JB		 2848 /* re-enable interrupt causes */
2849 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2850 if (!test_bit(__I40E_DOWN, &pf->state)) {
2851 i40e_service_event_schedule(pf);
2852 i40e_irq_dynamic_enable_icr0(pf);
2853 }
2854
5e823066 2855 return ret;
41c445ff
JB		 2856}
2857
2858/**
cd0b6fa6 2859 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2860 * @vsi: the VSI being configured
2861 * @v_idx: vector index
cd0b6fa6 2862 * @qp_idx: queue pair index
41c445ff 2863 **/
cd0b6fa6 2864static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2865{
493fb300 2866 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2867 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2868 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2869
2870 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2871 tx_ring->next = q_vector->tx.ring;
2872 q_vector->tx.ring = tx_ring;
41c445ff 2873 q_vector->tx.count++;
cd0b6fa6
AD		 2874
2875 rx_ring->q_vector = q_vector;
2876 rx_ring->next = q_vector->rx.ring;
2877 q_vector->rx.ring = rx_ring;
2878 q_vector->rx.count++;
41c445ff
JB		 2879}
2880
2881/**
2882 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2883 * @vsi: the VSI being configured
2884 *
2885 * This function maps descriptor rings to the queue-specific vectors
2886 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2887 * one vector per queue pair, but on a constrained vector budget, we
2888 * group the queue pairs as "efficiently" as possible.
2889 **/
2890static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2891{
2892 int qp_remaining = vsi->num_queue_pairs;
2893 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2894 int num_ringpairs;
41c445ff
JB		 2895 int v_start = 0;
2896 int qp_idx = 0;
2897
2898 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2899 * group them so there are multiple queues per vector.
2900 */
2901 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2902 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2903
2904 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2905
2906 q_vector->num_ringpairs = num_ringpairs;
2907
2908 q_vector->rx.count = 0;
2909 q_vector->tx.count = 0;
2910 q_vector->rx.ring = NULL;
2911 q_vector->tx.ring = NULL;
2912
2913 while (num_ringpairs--) {
2914 map_vector_to_qp(vsi, v_start, qp_idx);
2915 qp_idx++;
2916 qp_remaining--;
41c445ff
JB		 2917 }
2918 }
2919}
2920
2921/**
2922 * i40e_vsi_request_irq - Request IRQ from the OS
2923 * @vsi: the VSI being configured
2924 * @basename: name for the vector
2925 **/
2926static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2927{
2928 struct i40e_pf *pf = vsi->back;
2929 int err;
2930
2931 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2932 err = i40e_vsi_request_irq_msix(vsi, basename);
2933 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2934 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2935 pf->misc_int_name, pf);
2936 else
2937 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2938 pf->misc_int_name, pf);
2939
2940 if (err)
2941 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2942
2943 return err;
2944}
2945
2946#ifdef CONFIG_NET_POLL_CONTROLLER
2947/**
2948 * i40e_netpoll - A Polling 'interrupt'handler
2949 * @netdev: network interface device structure
2950 *
2951 * This is used by netconsole to send skbs without having to re-enable
2952 * interrupts. It's not called while the normal interrupt routine is executing.
2953 **/
2954static void i40e_netpoll(struct net_device *netdev)
2955{
2956 struct i40e_netdev_priv *np = netdev_priv(netdev);
2957 struct i40e_vsi *vsi = np->vsi;
2958 struct i40e_pf *pf = vsi->back;
2959 int i;
2960
2961 /* if interface is down do nothing */
2962 if (test_bit(__I40E_DOWN, &vsi->state))
2963 return;
2964
2965 pf->flags |= I40E_FLAG_IN_NETPOLL;
2966 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2967 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 2968 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 2969 } else {
2970 i40e_intr(pf->pdev->irq, netdev);
2971 }
2972 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
2973}
2974#endif
2975
2976/**
2977 * i40e_vsi_control_tx - Start or stop a VSI's rings
2978 * @vsi: the VSI being configured
2979 * @enable: start or stop the rings
2980 **/
2981static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
2982{
2983 struct i40e_pf *pf = vsi->back;
2984 struct i40e_hw *hw = &pf->hw;
2985 int i, j, pf_q;
2986 u32 tx_reg;
2987
2988 pf_q = vsi->base_queue;
2989 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
2990 j = 1000;
2991 do {
2992 usleep_range(1000, 2000);
2993 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
2994 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
2995 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
2996
fda972f6
MW		 2997 /* Skip if the queue is already in the requested state */
2998 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
2999 continue;
3000 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3001 continue;
41c445ff
JB		 3002
3003 /* turn on/off the queue */
3004 if (enable)
3005 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3006 I40E_QTX_ENA_QENA_STAT_MASK;
3007 else
3008 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3009
3010 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3011
3012 /* wait for the change to finish */
3013 for (j = 0; j < 10; j++) {
3014 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3015 if (enable) {
3016 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3017 break;
3018 } else {
3019 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3020 break;
3021 }
3022
3023 udelay(10);
3024 }
3025 if (j >= 10) {
3026 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3027 pf_q, (enable ? "en" : "dis"));
3028 return -ETIMEDOUT;
3029 }
3030 }
3031
7134f9ce
JB		 3032 if (hw->revision_id == 0)
3033 mdelay(50);
3034
41c445ff
JB		 3035 return 0;
3036}
3037
3038/**
3039 * i40e_vsi_control_rx - Start or stop a VSI's rings
3040 * @vsi: the VSI being configured
3041 * @enable: start or stop the rings
3042 **/
3043static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3044{
3045 struct i40e_pf *pf = vsi->back;
3046 struct i40e_hw *hw = &pf->hw;
3047 int i, j, pf_q;
3048 u32 rx_reg;
3049
3050 pf_q = vsi->base_queue;
3051 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3052 j = 1000;
3053 do {
3054 usleep_range(1000, 2000);
3055 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3056 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3057 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3058
3059 if (enable) {
3060 /* is STAT set ? */
3061 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3062 continue;
3063 } else {
3064 /* is !STAT set ? */
3065 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3066 continue;
3067 }
3068
3069 /* turn on/off the queue */
3070 if (enable)
3071 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3072 I40E_QRX_ENA_QENA_STAT_MASK;
3073 else
3074 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3075 I40E_QRX_ENA_QENA_STAT_MASK);
3076 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3077
3078 /* wait for the change to finish */
3079 for (j = 0; j < 10; j++) {
3080 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3081
3082 if (enable) {
3083 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3084 break;
3085 } else {
3086 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3087 break;
3088 }
3089
3090 udelay(10);
3091 }
3092 if (j >= 10) {
3093 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3094 pf_q, (enable ? "en" : "dis"));
3095 return -ETIMEDOUT;
3096 }
3097 }
3098
3099 return 0;
3100}
3101
3102/**
3103 * i40e_vsi_control_rings - Start or stop a VSI's rings
3104 * @vsi: the VSI being configured
3105 * @enable: start or stop the rings
3106 **/
fc18eaa0 3107int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff
JB		 3108{
3109 int ret;
3110
3111 /* do rx first for enable and last for disable */
3112 if (request) {
3113 ret = i40e_vsi_control_rx(vsi, request);
3114 if (ret)
3115 return ret;
3116 ret = i40e_vsi_control_tx(vsi, request);
3117 } else {
3118 ret = i40e_vsi_control_tx(vsi, request);
3119 if (ret)
3120 return ret;
3121 ret = i40e_vsi_control_rx(vsi, request);
3122 }
3123
3124 return ret;
3125}
3126
3127/**
3128 * i40e_vsi_free_irq - Free the irq association with the OS
3129 * @vsi: the VSI being configured
3130 **/
3131static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3132{
3133 struct i40e_pf *pf = vsi->back;
3134 struct i40e_hw *hw = &pf->hw;
3135 int base = vsi->base_vector;
3136 u32 val, qp;
3137 int i;
3138
3139 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3140 if (!vsi->q_vectors)
3141 return;
3142
3143 for (i = 0; i < vsi->num_q_vectors; i++) {
3144 u16 vector = i + base;
3145
3146 /* free only the irqs that were actually requested */
78681b1f
SN		 3147 if (!vsi->q_vectors[i] ||
3148 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3149 continue;
3150
3151 /* clear the affinity_mask in the IRQ descriptor */
3152 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3153 NULL);
3154 free_irq(pf->msix_entries[vector].vector,
493fb300 3155 vsi->q_vectors[i]);
41c445ff
JB		 3156
3157 /* Tear down the interrupt queue link list
3158 *
3159 * We know that they come in pairs and always
3160 * the Rx first, then the Tx. To clear the
3161 * link list, stick the EOL value into the
3162 * next_q field of the registers.
3163 */
3164 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3165 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3166 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3167 val |= I40E_QUEUE_END_OF_LIST
3168 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3169 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3170
3171 while (qp != I40E_QUEUE_END_OF_LIST) {
3172 u32 next;
3173
3174 val = rd32(hw, I40E_QINT_RQCTL(qp));
3175
3176 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3177 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3178 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3179 I40E_QINT_RQCTL_INTEVENT_MASK);
3180
3181 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3182 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3183
3184 wr32(hw, I40E_QINT_RQCTL(qp), val);
3185
3186 val = rd32(hw, I40E_QINT_TQCTL(qp));
3187
3188 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3189 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3190
3191 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3192 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3193 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3194 I40E_QINT_TQCTL_INTEVENT_MASK);
3195
3196 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3197 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3198
3199 wr32(hw, I40E_QINT_TQCTL(qp), val);
3200 qp = next;
3201 }
3202 }
3203 } else {
3204 free_irq(pf->pdev->irq, pf);
3205
3206 val = rd32(hw, I40E_PFINT_LNKLST0);
3207 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3208 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3209 val |= I40E_QUEUE_END_OF_LIST
3210 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3211 wr32(hw, I40E_PFINT_LNKLST0, val);
3212
3213 val = rd32(hw, I40E_QINT_RQCTL(qp));
3214 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3215 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3216 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3217 I40E_QINT_RQCTL_INTEVENT_MASK);
3218
3219 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3220 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3221
3222 wr32(hw, I40E_QINT_RQCTL(qp), val);
3223
3224 val = rd32(hw, I40E_QINT_TQCTL(qp));
3225
3226 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3227 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3228 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3229 I40E_QINT_TQCTL_INTEVENT_MASK);
3230
3231 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3232 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3233
3234 wr32(hw, I40E_QINT_TQCTL(qp), val);
3235 }
3236}
3237
493fb300
AD		 3238/**
3239 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3240 * @vsi: the VSI being configured
3241 * @v_idx: Index of vector to be freed
3242 *
3243 * This function frees the memory allocated to the q_vector. In addition if
3244 * NAPI is enabled it will delete any references to the NAPI struct prior
3245 * to freeing the q_vector.
3246 **/
3247static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3248{
3249 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3250 struct i40e_ring *ring;
493fb300
AD		 3251
3252 if (!q_vector)
3253 return;
3254
3255 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3256 i40e_for_each_ring(ring, q_vector->tx)
3257 ring->q_vector = NULL;
3258
3259 i40e_for_each_ring(ring, q_vector->rx)
3260 ring->q_vector = NULL;
493fb300
AD		 3261
3262 /* only VSI w/ an associated netdev is set up w/ NAPI */
3263 if (vsi->netdev)
3264 netif_napi_del(&q_vector->napi);
3265
3266 vsi->q_vectors[v_idx] = NULL;
3267
3268 kfree_rcu(q_vector, rcu);
3269}
3270
41c445ff
JB		 3271/**
3272 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3273 * @vsi: the VSI being un-configured
3274 *
3275 * This frees the memory allocated to the q_vectors and
3276 * deletes references to the NAPI struct.
3277 **/
3278static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3279{
3280 int v_idx;
3281
493fb300
AD		 3282 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3283 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3284}
3285
3286/**
3287 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3288 * @pf: board private structure
3289 **/
3290static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3291{
3292 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3293 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3294 pci_disable_msix(pf->pdev);
3295 kfree(pf->msix_entries);
3296 pf->msix_entries = NULL;
3297 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3298 pci_disable_msi(pf->pdev);
3299 }
3300 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3301}
3302
3303/**
3304 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3305 * @pf: board private structure
3306 *
3307 * We go through and clear interrupt specific resources and reset the structure
3308 * to pre-load conditions
3309 **/
3310static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3311{
3312 int i;
3313
3314 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3315 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3316 if (pf->vsi[i])
3317 i40e_vsi_free_q_vectors(pf->vsi[i]);
3318 i40e_reset_interrupt_capability(pf);
3319}
3320
3321/**
3322 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3323 * @vsi: the VSI being configured
3324 **/
3325static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3326{
3327 int q_idx;
3328
3329 if (!vsi->netdev)
3330 return;
3331
3332 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3333 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3334}
3335
3336/**
3337 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3338 * @vsi: the VSI being configured
3339 **/
3340static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3341{
3342 int q_idx;
3343
3344 if (!vsi->netdev)
3345 return;
3346
3347 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3348 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3349}
3350
3351/**
3352 * i40e_quiesce_vsi - Pause a given VSI
3353 * @vsi: the VSI being paused
3354 **/
3355static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3356{
3357 if (test_bit(__I40E_DOWN, &vsi->state))
3358 return;
3359
3360 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3361 if (vsi->netdev && netif_running(vsi->netdev)) {
3362 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3363 } else {
3364 set_bit(__I40E_DOWN, &vsi->state);
3365 i40e_down(vsi);
3366 }
3367}
3368
3369/**
3370 * i40e_unquiesce_vsi - Resume a given VSI
3371 * @vsi: the VSI being resumed
3372 **/
3373static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3374{
3375 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3376 return;
3377
3378 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3379 if (vsi->netdev && netif_running(vsi->netdev))
3380 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3381 else
3382 i40e_up(vsi); /* this clears the DOWN bit */
3383}
3384
3385/**
3386 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3387 * @pf: the PF
3388 **/
3389static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3390{
3391 int v;
3392
3393 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3394 if (pf->vsi[v])
3395 i40e_quiesce_vsi(pf->vsi[v]);
3396 }
3397}
3398
3399/**
3400 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3401 * @pf: the PF
3402 **/
3403static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3404{
3405 int v;
3406
3407 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3408 if (pf->vsi[v])
3409 i40e_unquiesce_vsi(pf->vsi[v]);
3410 }
3411}
3412
3413/**
3414 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3415 * @dcbcfg: the corresponding DCBx configuration structure
3416 *
3417 * Return the number of TCs from given DCBx configuration
3418 **/
3419static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3420{
078b5876
JB		 3421 u8 num_tc = 0;
3422 int i;
41c445ff
JB		 3423
3424 /* Scan the ETS Config Priority Table to find
3425 * traffic class enabled for a given priority
3426 * and use the traffic class index to get the
3427 * number of traffic classes enabled
3428 */
3429 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3430 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3431 num_tc = dcbcfg->etscfg.prioritytable[i];
3432 }
3433
3434 /* Traffic class index starts from zero so
3435 * increment to return the actual count
3436 */
078b5876 3437 return num_tc + 1;
41c445ff
JB		 3438}
3439
3440/**
3441 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3442 * @dcbcfg: the corresponding DCBx configuration structure
3443 *
3444 * Query the current DCB configuration and return the number of
3445 * traffic classes enabled from the given DCBX config
3446 **/
3447static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3448{
3449 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3450 u8 enabled_tc = 1;
3451 u8 i;
3452
3453 for (i = 0; i < num_tc; i++)
3454 enabled_tc |= 1 << i;
3455
3456 return enabled_tc;
3457}
3458
3459/**
3460 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3461 * @pf: PF being queried
3462 *
3463 * Return number of traffic classes enabled for the given PF
3464 **/
3465static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3466{
3467 struct i40e_hw *hw = &pf->hw;
3468 u8 i, enabled_tc;
3469 u8 num_tc = 0;
3470 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3471
3472 /* If DCB is not enabled then always in single TC */
3473 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3474 return 1;
3475
3476 /* MFP mode return count of enabled TCs for this PF */
3477 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3478 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3479 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3480 if (enabled_tc & (1 << i))
3481 num_tc++;
3482 }
3483 return num_tc;
3484 }
3485
3486 /* SFP mode will be enabled for all TCs on port */
3487 return i40e_dcb_get_num_tc(dcbcfg);
3488}
3489
3490/**
3491 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3492 * @pf: PF being queried
3493 *
3494 * Return a bitmap for first enabled traffic class for this PF.
3495 **/
3496static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3497{
3498 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3499 u8 i = 0;
3500
3501 if (!enabled_tc)
3502 return 0x1; /* TC0 */
3503
3504 /* Find the first enabled TC */
3505 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3506 if (enabled_tc & (1 << i))
3507 break;
3508 }
3509
3510 return 1 << i;
3511}
3512
3513/**
3514 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3515 * @pf: PF being queried
3516 *
3517 * Return a bitmap for enabled traffic classes for this PF.
3518 **/
3519static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3520{
3521 /* If DCB is not enabled for this PF then just return default TC */
3522 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3523 return i40e_pf_get_default_tc(pf);
3524
3525 /* MFP mode will have enabled TCs set by FW */
3526 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3527 return pf->hw.func_caps.enabled_tcmap;
3528
3529 /* SFP mode we want PF to be enabled for all TCs */
3530 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3531}
3532
3533/**
3534 * i40e_vsi_get_bw_info - Query VSI BW Information
3535 * @vsi: the VSI being queried
3536 *
3537 * Returns 0 on success, negative value on failure
3538 **/
3539static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3540{
3541 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3542 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3543 struct i40e_pf *pf = vsi->back;
3544 struct i40e_hw *hw = &pf->hw;
dcae29be 3545 i40e_status aq_ret;
41c445ff 3546 u32 tc_bw_max;
41c445ff
JB		 3547 int i;
3548
3549 /* Get the VSI level BW configuration */
dcae29be
JB		 3550 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3551 if (aq_ret) {
41c445ff
JB		 3552 dev_info(&pf->pdev->dev,
3553 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3554 aq_ret, pf->hw.aq.asq_last_status);
3555 return -EINVAL;
41c445ff
JB		 3556 }
3557
3558 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3559 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3560 NULL);
3561 if (aq_ret) {
41c445ff
JB		 3562 dev_info(&pf->pdev->dev,
3563 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3564 aq_ret, pf->hw.aq.asq_last_status);
3565 return -EINVAL;
41c445ff
JB		 3566 }
3567
3568 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3569 dev_info(&pf->pdev->dev,
3570 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3571 bw_config.tc_valid_bits,
3572 bw_ets_config.tc_valid_bits);
3573 /* Still continuing */
3574 }
3575
3576 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3577 vsi->bw_max_quanta = bw_config.max_bw;
3578 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3579 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3580 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3581 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3582 vsi->bw_ets_limit_credits[i] =
3583 le16_to_cpu(bw_ets_config.credits[i]);
3584 /* 3 bits out of 4 for each TC */
3585 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3586 }
078b5876 3587
dcae29be 3588 return 0;
41c445ff
JB		 3589}
3590
3591/**
3592 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3593 * @vsi: the VSI being configured
3594 * @enabled_tc: TC bitmap
3595 * @bw_credits: BW shared credits per TC
3596 *
3597 * Returns 0 on success, negative value on failure
3598 **/
dcae29be 3599static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3600 u8 *bw_share)
3601{
3602 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3603 i40e_status aq_ret;
3604 int i;
41c445ff
JB		 3605
3606 bw_data.tc_valid_bits = enabled_tc;
3607 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3608 bw_data.tc_bw_credits[i] = bw_share[i];
3609
dcae29be
JB		 3610 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3611 NULL);
3612 if (aq_ret) {
41c445ff
JB		 3613 dev_info(&vsi->back->pdev->dev,
3614 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3615 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3616 return -EINVAL;
41c445ff
JB		 3617 }
3618
3619 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3620 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3621
dcae29be 3622 return 0;
41c445ff
JB		 3623}
3624
3625/**
3626 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3627 * @vsi: the VSI being configured
3628 * @enabled_tc: TC map to be enabled
3629 *
3630 **/
3631static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3632{
3633 struct net_device *netdev = vsi->netdev;
3634 struct i40e_pf *pf = vsi->back;
3635 struct i40e_hw *hw = &pf->hw;
3636 u8 netdev_tc = 0;
3637 int i;
3638 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3639
3640 if (!netdev)
3641 return;
3642
3643 if (!enabled_tc) {
3644 netdev_reset_tc(netdev);
3645 return;
3646 }
3647
3648 /* Set up actual enabled TCs on the VSI */
3649 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3650 return;
3651
3652 /* set per TC queues for the VSI */
3653 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3654 /* Only set TC queues for enabled tcs
3655 *
3656 * e.g. For a VSI that has TC0 and TC3 enabled the
3657 * enabled_tc bitmap would be 0x00001001; the driver
3658 * will set the numtc for netdev as 2 that will be
3659 * referenced by the netdev layer as TC 0 and 1.
3660 */
3661 if (vsi->tc_config.enabled_tc & (1 << i))
3662 netdev_set_tc_queue(netdev,
3663 vsi->tc_config.tc_info[i].netdev_tc,
3664 vsi->tc_config.tc_info[i].qcount,
3665 vsi->tc_config.tc_info[i].qoffset);
3666 }
3667
3668 /* Assign UP2TC map for the VSI */
3669 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3670 /* Get the actual TC# for the UP */
3671 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3672 /* Get the mapped netdev TC# for the UP */
3673 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3674 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3675 }
3676}
3677
3678/**
3679 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3680 * @vsi: the VSI being configured
3681 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3682 **/
3683static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3684 struct i40e_vsi_context *ctxt)
3685{
3686 /* copy just the sections touched not the entire info
3687 * since not all sections are valid as returned by
3688 * update vsi params
3689 */
3690 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3691 memcpy(&vsi->info.queue_mapping,
3692 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3693 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3694 sizeof(vsi->info.tc_mapping));
3695}
3696
3697/**
3698 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3699 * @vsi: VSI to be configured
3700 * @enabled_tc: TC bitmap
3701 *
3702 * This configures a particular VSI for TCs that are mapped to the
3703 * given TC bitmap. It uses default bandwidth share for TCs across
3704 * VSIs to configure TC for a particular VSI.
3705 *
3706 * NOTE:
3707 * It is expected that the VSI queues have been quisced before calling
3708 * this function.
3709 **/
3710static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3711{
3712 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3713 struct i40e_vsi_context ctxt;
3714 int ret = 0;
3715 int i;
3716
3717 /* Check if enabled_tc is same as existing or new TCs */
3718 if (vsi->tc_config.enabled_tc == enabled_tc)
3719 return ret;
3720
3721 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3722 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3723 if (enabled_tc & (1 << i))
3724 bw_share[i] = 1;
3725 }
3726
3727 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3728 if (ret) {
3729 dev_info(&vsi->back->pdev->dev,
3730 "Failed configuring TC map %d for VSI %d\n",
3731 enabled_tc, vsi->seid);
3732 goto out;
3733 }
3734
3735 /* Update Queue Pairs Mapping for currently enabled UPs */
3736 ctxt.seid = vsi->seid;
3737 ctxt.pf_num = vsi->back->hw.pf_id;
3738 ctxt.vf_num = 0;
3739 ctxt.uplink_seid = vsi->uplink_seid;
3740 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3741 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3742
3743 /* Update the VSI after updating the VSI queue-mapping information */
3744 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3745 if (ret) {
3746 dev_info(&vsi->back->pdev->dev,
3747 "update vsi failed, aq_err=%d\n",
3748 vsi->back->hw.aq.asq_last_status);
3749 goto out;
3750 }
3751 /* update the local VSI info with updated queue map */
3752 i40e_vsi_update_queue_map(vsi, &ctxt);
3753 vsi->info.valid_sections = 0;
3754
3755 /* Update current VSI BW information */
3756 ret = i40e_vsi_get_bw_info(vsi);
3757 if (ret) {
3758 dev_info(&vsi->back->pdev->dev,
3759 "Failed updating vsi bw info, aq_err=%d\n",
3760 vsi->back->hw.aq.asq_last_status);
3761 goto out;
3762 }
3763
3764 /* Update the netdev TC setup */
3765 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3766out:
3767 return ret;
3768}
3769
3770/**
3771 * i40e_up_complete - Finish the last steps of bringing up a connection
3772 * @vsi: the VSI being configured
3773 **/
3774static int i40e_up_complete(struct i40e_vsi *vsi)
3775{
3776 struct i40e_pf *pf = vsi->back;
3777 int err;
3778
3779 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3780 i40e_vsi_configure_msix(vsi);
3781 else
3782 i40e_configure_msi_and_legacy(vsi);
3783
3784 /* start rings */
3785 err = i40e_vsi_control_rings(vsi, true);
3786 if (err)
3787 return err;
3788
3789 clear_bit(__I40E_DOWN, &vsi->state);
3790 i40e_napi_enable_all(vsi);
3791 i40e_vsi_enable_irq(vsi);
3792
3793 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3794 (vsi->netdev)) {
6d779b41 3795 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3796 netif_tx_start_all_queues(vsi->netdev);
3797 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3798 } else if (vsi->netdev) {
3799 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3800 }
3801 i40e_service_event_schedule(pf);
3802
3803 return 0;
3804}
3805
3806/**
3807 * i40e_vsi_reinit_locked - Reset the VSI
3808 * @vsi: the VSI being configured
3809 *
3810 * Rebuild the ring structs after some configuration
3811 * has changed, e.g. MTU size.
3812 **/
3813static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3814{
3815 struct i40e_pf *pf = vsi->back;
3816
3817 WARN_ON(in_interrupt());
3818 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3819 usleep_range(1000, 2000);
3820 i40e_down(vsi);
3821
3822 /* Give a VF some time to respond to the reset. The
3823 * two second wait is based upon the watchdog cycle in
3824 * the VF driver.
3825 */
3826 if (vsi->type == I40E_VSI_SRIOV)
3827 msleep(2000);
3828 i40e_up(vsi);
3829 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3830}
3831
3832/**
3833 * i40e_up - Bring the connection back up after being down
3834 * @vsi: the VSI being configured
3835 **/
3836int i40e_up(struct i40e_vsi *vsi)
3837{
3838 int err;
3839
3840 err = i40e_vsi_configure(vsi);
3841 if (!err)
3842 err = i40e_up_complete(vsi);
3843
3844 return err;
3845}
3846
3847/**
3848 * i40e_down - Shutdown the connection processing
3849 * @vsi: the VSI being stopped
3850 **/
3851void i40e_down(struct i40e_vsi *vsi)
3852{
3853 int i;
3854
3855 /* It is assumed that the caller of this function
3856 * sets the vsi->state __I40E_DOWN bit.
3857 */
3858 if (vsi->netdev) {
3859 netif_carrier_off(vsi->netdev);
3860 netif_tx_disable(vsi->netdev);
3861 }
3862 i40e_vsi_disable_irq(vsi);
3863 i40e_vsi_control_rings(vsi, false);
3864 i40e_napi_disable_all(vsi);
3865
3866 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3867 i40e_clean_tx_ring(vsi->tx_rings[i]);
3868 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3869 }
3870}
3871
3872/**
3873 * i40e_setup_tc - configure multiple traffic classes
3874 * @netdev: net device to configure
3875 * @tc: number of traffic classes to enable
3876 **/
3877static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3878{
3879 struct i40e_netdev_priv *np = netdev_priv(netdev);
3880 struct i40e_vsi *vsi = np->vsi;
3881 struct i40e_pf *pf = vsi->back;
3882 u8 enabled_tc = 0;
3883 int ret = -EINVAL;
3884 int i;
3885
3886 /* Check if DCB enabled to continue */
3887 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3888 netdev_info(netdev, "DCB is not enabled for adapter\n");
3889 goto exit;
3890 }
3891
3892 /* Check if MFP enabled */
3893 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3894 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3895 goto exit;
3896 }
3897
3898 /* Check whether tc count is within enabled limit */
3899 if (tc > i40e_pf_get_num_tc(pf)) {
3900 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3901 goto exit;
3902 }
3903
3904 /* Generate TC map for number of tc requested */
3905 for (i = 0; i < tc; i++)
3906 enabled_tc |= (1 << i);
3907
3908 /* Requesting same TC configuration as already enabled */
3909 if (enabled_tc == vsi->tc_config.enabled_tc)
3910 return 0;
3911
3912 /* Quiesce VSI queues */
3913 i40e_quiesce_vsi(vsi);
3914
3915 /* Configure VSI for enabled TCs */
3916 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3917 if (ret) {
3918 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3919 vsi->seid);
3920 goto exit;
3921 }
3922
3923 /* Unquiesce VSI */
3924 i40e_unquiesce_vsi(vsi);
3925
3926exit:
3927 return ret;
3928}
3929
3930/**
3931 * i40e_open - Called when a network interface is made active
3932 * @netdev: network interface device structure
3933 *
3934 * The open entry point is called when a network interface is made
3935 * active by the system (IFF_UP). At this point all resources needed
3936 * for transmit and receive operations are allocated, the interrupt
3937 * handler is registered with the OS, the netdev watchdog subtask is
3938 * enabled, and the stack is notified that the interface is ready.
3939 *
3940 * Returns 0 on success, negative value on failure
3941 **/
3942static int i40e_open(struct net_device *netdev)
3943{
3944 struct i40e_netdev_priv *np = netdev_priv(netdev);
3945 struct i40e_vsi *vsi = np->vsi;
3946 struct i40e_pf *pf = vsi->back;
3947 char int_name[IFNAMSIZ];
3948 int err;
3949
3950 /* disallow open during test */
3951 if (test_bit(__I40E_TESTING, &pf->state))
3952 return -EBUSY;
3953
3954 netif_carrier_off(netdev);
3955
3956 /* allocate descriptors */
3957 err = i40e_vsi_setup_tx_resources(vsi);
3958 if (err)
3959 goto err_setup_tx;
3960 err = i40e_vsi_setup_rx_resources(vsi);
3961 if (err)
3962 goto err_setup_rx;
3963
3964 err = i40e_vsi_configure(vsi);
3965 if (err)
3966 goto err_setup_rx;
3967
3968 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
3969 dev_driver_string(&pf->pdev->dev), netdev->name);
3970 err = i40e_vsi_request_irq(vsi, int_name);
3971 if (err)
3972 goto err_setup_rx;
3973
25946ddb 3974 /* Notify the stack of the actual queue counts. */
d7397644 3975 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3976 if (err)
3977 goto err_set_queues;
3978
d7397644 3979 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3980 if (err)
3981 goto err_set_queues;
3982
41c445ff
JB		 3983 err = i40e_up_complete(vsi);
3984 if (err)
3985 goto err_up_complete;
3986
a1c9a9d9
JK		 3987#ifdef CONFIG_I40E_VXLAN
3988 vxlan_get_rx_port(netdev);
3989#endif
41c445ff
JB		 3990
3991 return 0;
3992
3993err_up_complete:
3994 i40e_down(vsi);
25946ddb 3995err_set_queues:
41c445ff
JB		 3996 i40e_vsi_free_irq(vsi);
3997err_setup_rx:
3998 i40e_vsi_free_rx_resources(vsi);
3999err_setup_tx:
4000 i40e_vsi_free_tx_resources(vsi);
4001 if (vsi == pf->vsi[pf->lan_vsi])
4002 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4003
4004 return err;
4005}
4006
4007/**
4008 * i40e_close - Disables a network interface
4009 * @netdev: network interface device structure
4010 *
4011 * The close entry point is called when an interface is de-activated
4012 * by the OS. The hardware is still under the driver's control, but
4013 * this netdev interface is disabled.
4014 *
4015 * Returns 0, this is not allowed to fail
4016 **/
4017static int i40e_close(struct net_device *netdev)
4018{
4019 struct i40e_netdev_priv *np = netdev_priv(netdev);
4020 struct i40e_vsi *vsi = np->vsi;
4021
4022 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4023 return 0;
4024
4025 i40e_down(vsi);
4026 i40e_vsi_free_irq(vsi);
4027
4028 i40e_vsi_free_tx_resources(vsi);
4029 i40e_vsi_free_rx_resources(vsi);
4030
4031 return 0;
4032}
4033
4034/**
4035 * i40e_do_reset - Start a PF or Core Reset sequence
4036 * @pf: board private structure
4037 * @reset_flags: which reset is requested
4038 *
4039 * The essential difference in resets is that the PF Reset
4040 * doesn't clear the packet buffers, doesn't reset the PE
4041 * firmware, and doesn't bother the other PFs on the chip.
4042 **/
4043void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4044{
4045 u32 val;
4046
4047 WARN_ON(in_interrupt());
4048
4049 /* do the biggest reset indicated */
4050 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4051
4052 /* Request a Global Reset
4053 *
4054 * This will start the chip's countdown to the actual full
4055 * chip reset event, and a warning interrupt to be sent
4056 * to all PFs, including the requestor. Our handler
4057 * for the warning interrupt will deal with the shutdown
4058 * and recovery of the switch setup.
4059 */
4060 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4061 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4062 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4063 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4064
4065 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4066
4067 /* Request a Core Reset
4068 *
4069 * Same as Global Reset, except does *not* include the MAC/PHY
4070 */
4071 dev_info(&pf->pdev->dev, "CoreR requested\n");
4072 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4073 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4074 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4075 i40e_flush(&pf->hw);
4076
7823fe34
SN		 4077 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4078
4079 /* Request a Firmware Reset
4080 *
4081 * Same as Global reset, plus restarting the
4082 * embedded firmware engine.
4083 */
4084 /* enable EMP Reset */
4085 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4086 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4087 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4088
4089 /* force the reset */
4090 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4091 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4092 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4093 i40e_flush(&pf->hw);
4094
41c445ff
JB		 4095 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4096
4097 /* Request a PF Reset
4098 *
4099 * Resets only the PF-specific registers
4100 *
4101 * This goes directly to the tear-down and rebuild of
4102 * the switch, since we need to do all the recovery as
4103 * for the Core Reset.
4104 */
4105 dev_info(&pf->pdev->dev, "PFR requested\n");
4106 i40e_handle_reset_warning(pf);
4107
4108 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4109 int v;
4110
4111 /* Find the VSI(s) that requested a re-init */
4112 dev_info(&pf->pdev->dev,
4113 "VSI reinit requested\n");
4114 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4115 struct i40e_vsi *vsi = pf->vsi[v];
4116 if (vsi != NULL &&
4117 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4118 i40e_vsi_reinit_locked(pf->vsi[v]);
4119 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4120 }
4121 }
4122
4123 /* no further action needed, so return now */
4124 return;
4125 } else {
4126 dev_info(&pf->pdev->dev,
4127 "bad reset request 0x%08x\n", reset_flags);
4128 return;
4129 }
4130}
4131
23326186
ASJ		 4132/**
4133 * i40e_do_reset_safe - Protected reset path for userland calls.
4134 * @pf: board private structure
4135 * @reset_flags: which reset is requested
4136 *
4137 **/
4138void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4139{
4140 rtnl_lock();
4141 i40e_do_reset(pf, reset_flags);
4142 rtnl_unlock();
4143}
4144
41c445ff
JB		 4145/**
4146 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4147 * @pf: board private structure
4148 * @e: event info posted on ARQ
4149 *
4150 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4151 * and VF queues
4152 **/
4153static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4154 struct i40e_arq_event_info *e)
4155{
4156 struct i40e_aqc_lan_overflow *data =
4157 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4158 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4159 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4160 struct i40e_hw *hw = &pf->hw;
4161 struct i40e_vf *vf;
4162 u16 vf_id;
4163
4164 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4165 __func__, queue, qtx_ctl);
4166
4167 /* Queue belongs to VF, find the VF and issue VF reset */
4168 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4169 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4170 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4171 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4172 vf_id -= hw->func_caps.vf_base_id;
4173 vf = &pf->vf[vf_id];
4174 i40e_vc_notify_vf_reset(vf);
4175 /* Allow VF to process pending reset notification */
4176 msleep(20);
4177 i40e_reset_vf(vf, false);
4178 }
4179}
4180
4181/**
4182 * i40e_service_event_complete - Finish up the service event
4183 * @pf: board private structure
4184 **/
4185static void i40e_service_event_complete(struct i40e_pf *pf)
4186{
4187 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4188
4189 /* flush memory to make sure state is correct before next watchog */
4190 smp_mb__before_clear_bit();
4191 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4192}
4193
4194/**
4195 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4196 * @pf: board private structure
4197 **/
4198static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4199{
4200 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4201 return;
4202
4203 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4204
4205 /* if interface is down do nothing */
4206 if (test_bit(__I40E_DOWN, &pf->state))
4207 return;
4208}
4209
4210/**
4211 * i40e_vsi_link_event - notify VSI of a link event
4212 * @vsi: vsi to be notified
4213 * @link_up: link up or down
4214 **/
4215static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4216{
4217 if (!vsi)
4218 return;
4219
4220 switch (vsi->type) {
4221 case I40E_VSI_MAIN:
4222 if (!vsi->netdev || !vsi->netdev_registered)
4223 break;
4224
4225 if (link_up) {
4226 netif_carrier_on(vsi->netdev);
4227 netif_tx_wake_all_queues(vsi->netdev);
4228 } else {
4229 netif_carrier_off(vsi->netdev);
4230 netif_tx_stop_all_queues(vsi->netdev);
4231 }
4232 break;
4233
4234 case I40E_VSI_SRIOV:
4235 break;
4236
4237 case I40E_VSI_VMDQ2:
4238 case I40E_VSI_CTRL:
4239 case I40E_VSI_MIRROR:
4240 default:
4241 /* there is no notification for other VSIs */
4242 break;
4243 }
4244}
4245
4246/**
4247 * i40e_veb_link_event - notify elements on the veb of a link event
4248 * @veb: veb to be notified
4249 * @link_up: link up or down
4250 **/
4251static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4252{
4253 struct i40e_pf *pf;
4254 int i;
4255
4256 if (!veb || !veb->pf)
4257 return;
4258 pf = veb->pf;
4259
4260 /* depth first... */
4261 for (i = 0; i < I40E_MAX_VEB; i++)
4262 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4263 i40e_veb_link_event(pf->veb[i], link_up);
4264
4265 /* ... now the local VSIs */
4266 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4267 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4268 i40e_vsi_link_event(pf->vsi[i], link_up);
4269}
4270
4271/**
4272 * i40e_link_event - Update netif_carrier status
4273 * @pf: board private structure
4274 **/
4275static void i40e_link_event(struct i40e_pf *pf)
4276{
4277 bool new_link, old_link;
4278
4279 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4280 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4281
4282 if (new_link == old_link)
4283 return;
4284
6d779b41
AS		 4285 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4286 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4287 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4288
4289 /* Notify the base of the switch tree connected to
4290 * the link. Floating VEBs are not notified.
4291 */
4292 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4293 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4294 else
4295 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4296
4297 if (pf->vf)
4298 i40e_vc_notify_link_state(pf);
4299}
4300
4301/**
4302 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4303 * @pf: board private structure
4304 *
4305 * Set the per-queue flags to request a check for stuck queues in the irq
4306 * clean functions, then force interrupts to be sure the irq clean is called.
4307 **/
4308static void i40e_check_hang_subtask(struct i40e_pf *pf)
4309{
4310 int i, v;
4311
4312 /* If we're down or resetting, just bail */
4313 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4314 return;
4315
4316 /* for each VSI/netdev
4317 * for each Tx queue
4318 * set the check flag
4319 * for each q_vector
4320 * force an interrupt
4321 */
4322 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4323 struct i40e_vsi *vsi = pf->vsi[v];
4324 int armed = 0;
4325
4326 if (!pf->vsi[v] ||
4327 test_bit(__I40E_DOWN, &vsi->state) ||
4328 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4329 continue;
4330
4331 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4332 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4333 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4334 &vsi->tx_rings[i]->state))
41c445ff
JB		 4335 armed++;
4336 }
4337
4338 if (armed) {
4339 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4340 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4341 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4342 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4343 } else {
4344 u16 vec = vsi->base_vector - 1;
4345 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4346 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4347 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4348 wr32(&vsi->back->hw,
4349 I40E_PFINT_DYN_CTLN(vec), val);
4350 }
4351 i40e_flush(&vsi->back->hw);
4352 }
4353 }
4354}
4355
4356/**
4357 * i40e_watchdog_subtask - Check and bring link up
4358 * @pf: board private structure
4359 **/
4360static void i40e_watchdog_subtask(struct i40e_pf *pf)
4361{
4362 int i;
4363
4364 /* if interface is down do nothing */
4365 if (test_bit(__I40E_DOWN, &pf->state) ||
4366 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4367 return;
4368
4369 /* Update the stats for active netdevs so the network stack
4370 * can look at updated numbers whenever it cares to
4371 */
4372 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4373 if (pf->vsi[i] && pf->vsi[i]->netdev)
4374 i40e_update_stats(pf->vsi[i]);
4375
4376 /* Update the stats for the active switching components */
4377 for (i = 0; i < I40E_MAX_VEB; i++)
4378 if (pf->veb[i])
4379 i40e_update_veb_stats(pf->veb[i]);
4380}
4381
4382/**
4383 * i40e_reset_subtask - Set up for resetting the device and driver
4384 * @pf: board private structure
4385 **/
4386static void i40e_reset_subtask(struct i40e_pf *pf)
4387{
4388 u32 reset_flags = 0;
4389
23326186 4390 rtnl_lock();
41c445ff
JB		 4391 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4392 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4393 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4394 }
4395 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4396 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4397 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4398 }
4399 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4400 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4401 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4402 }
4403 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4404 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4405 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4406 }
4407
4408 /* If there's a recovery already waiting, it takes
4409 * precedence before starting a new reset sequence.
4410 */
4411 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4412 i40e_handle_reset_warning(pf);
23326186 4413 goto unlock;
41c445ff
JB		 4414 }
4415
4416 /* If we're already down or resetting, just bail */
4417 if (reset_flags &&
4418 !test_bit(__I40E_DOWN, &pf->state) &&
4419 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4420 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4421
4422unlock:
4423 rtnl_unlock();
41c445ff
JB		 4424}
4425
4426/**
4427 * i40e_handle_link_event - Handle link event
4428 * @pf: board private structure
4429 * @e: event info posted on ARQ
4430 **/
4431static void i40e_handle_link_event(struct i40e_pf *pf,
4432 struct i40e_arq_event_info *e)
4433{
4434 struct i40e_hw *hw = &pf->hw;
4435 struct i40e_aqc_get_link_status *status =
4436 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4437 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4438
4439 /* save off old link status information */
4440 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4441 sizeof(pf->hw.phy.link_info_old));
4442
4443 /* update link status */
4444 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4445 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4446 hw_link_info->link_info = status->link_info;
4447 hw_link_info->an_info = status->an_info;
4448 hw_link_info->ext_info = status->ext_info;
4449 hw_link_info->lse_enable =
4450 le16_to_cpu(status->command_flags) &
4451 I40E_AQ_LSE_ENABLE;
4452
4453 /* process the event */
4454 i40e_link_event(pf);
4455
4456 /* Do a new status request to re-enable LSE reporting
4457 * and load new status information into the hw struct,
4458 * then see if the status changed while processing the
4459 * initial event.
4460 */
4461 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4462 i40e_link_event(pf);
4463}
4464
4465/**
4466 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4467 * @pf: board private structure
4468 **/
4469static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4470{
4471 struct i40e_arq_event_info event;
4472 struct i40e_hw *hw = &pf->hw;
4473 u16 pending, i = 0;
4474 i40e_status ret;
4475 u16 opcode;
4476 u32 val;
4477
4478 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4479 return;
4480
3197ce22 4481 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4482 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4483 if (!event.msg_buf)
4484 return;
4485
4486 do {
2f019123 4487 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4488 ret = i40e_clean_arq_element(hw, &event, &pending);
4489 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4490 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4491 break;
4492 } else if (ret) {
4493 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4494 break;
4495 }
4496
4497 opcode = le16_to_cpu(event.desc.opcode);
4498 switch (opcode) {
4499
4500 case i40e_aqc_opc_get_link_status:
4501 i40e_handle_link_event(pf, &event);
4502 break;
4503 case i40e_aqc_opc_send_msg_to_pf:
4504 ret = i40e_vc_process_vf_msg(pf,
4505 le16_to_cpu(event.desc.retval),
4506 le32_to_cpu(event.desc.cookie_high),
4507 le32_to_cpu(event.desc.cookie_low),
4508 event.msg_buf,
4509 event.msg_size);
4510 break;
4511 case i40e_aqc_opc_lldp_update_mib:
4512 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4513 break;
4514 case i40e_aqc_opc_event_lan_overflow:
4515 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4516 i40e_handle_lan_overflow_event(pf, &event);
4517 break;
4518 default:
4519 dev_info(&pf->pdev->dev,
4520 "ARQ Error: Unknown event %d received\n",
4521 event.desc.opcode);
4522 break;
4523 }
4524 } while (pending && (i++ < pf->adminq_work_limit));
4525
4526 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4527 /* re-enable Admin queue interrupt cause */
4528 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4529 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4530 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4531 i40e_flush(hw);
4532
4533 kfree(event.msg_buf);
4534}
4535
4536/**
4537 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4538 * @veb: pointer to the VEB instance
4539 *
4540 * This is a recursive function that first builds the attached VSIs then
4541 * recurses in to build the next layer of VEB. We track the connections
4542 * through our own index numbers because the seid's from the HW could
4543 * change across the reset.
4544 **/
4545static int i40e_reconstitute_veb(struct i40e_veb *veb)
4546{
4547 struct i40e_vsi *ctl_vsi = NULL;
4548 struct i40e_pf *pf = veb->pf;
4549 int v, veb_idx;
4550 int ret;
4551
4552 /* build VSI that owns this VEB, temporarily attached to base VEB */
4553 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4554 if (pf->vsi[v] &&
4555 pf->vsi[v]->veb_idx == veb->idx &&
4556 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4557 ctl_vsi = pf->vsi[v];
4558 break;
4559 }
4560 }
4561 if (!ctl_vsi) {
4562 dev_info(&pf->pdev->dev,
4563 "missing owner VSI for veb_idx %d\n", veb->idx);
4564 ret = -ENOENT;
4565 goto end_reconstitute;
4566 }
4567 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4568 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4569 ret = i40e_add_vsi(ctl_vsi);
4570 if (ret) {
4571 dev_info(&pf->pdev->dev,
4572 "rebuild of owner VSI failed: %d\n", ret);
4573 goto end_reconstitute;
4574 }
4575 i40e_vsi_reset_stats(ctl_vsi);
4576
4577 /* create the VEB in the switch and move the VSI onto the VEB */
4578 ret = i40e_add_veb(veb, ctl_vsi);
4579 if (ret)
4580 goto end_reconstitute;
4581
4582 /* create the remaining VSIs attached to this VEB */
4583 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4584 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4585 continue;
4586
4587 if (pf->vsi[v]->veb_idx == veb->idx) {
4588 struct i40e_vsi *vsi = pf->vsi[v];
4589 vsi->uplink_seid = veb->seid;
4590 ret = i40e_add_vsi(vsi);
4591 if (ret) {
4592 dev_info(&pf->pdev->dev,
4593 "rebuild of vsi_idx %d failed: %d\n",
4594 v, ret);
4595 goto end_reconstitute;
4596 }
4597 i40e_vsi_reset_stats(vsi);
4598 }
4599 }
4600
4601 /* create any VEBs attached to this VEB - RECURSION */
4602 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4603 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4604 pf->veb[veb_idx]->uplink_seid = veb->seid;
4605 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4606 if (ret)
4607 break;
4608 }
4609 }
4610
4611end_reconstitute:
4612 return ret;
4613}
4614
4615/**
4616 * i40e_get_capabilities - get info about the HW
4617 * @pf: the PF struct
4618 **/
4619static int i40e_get_capabilities(struct i40e_pf *pf)
4620{
4621 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4622 u16 data_size;
4623 int buf_len;
4624 int err;
4625
4626 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4627 do {
4628 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4629 if (!cap_buf)
4630 return -ENOMEM;
4631
4632 /* this loads the data into the hw struct for us */
4633 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4634 &data_size,
4635 i40e_aqc_opc_list_func_capabilities,
4636 NULL);
4637 /* data loaded, buffer no longer needed */
4638 kfree(cap_buf);
4639
4640 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4641 /* retry with a larger buffer */
4642 buf_len = data_size;
4643 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4644 dev_info(&pf->pdev->dev,
4645 "capability discovery failed: aq=%d\n",
4646 pf->hw.aq.asq_last_status);
4647 return -ENODEV;
4648 }
4649 } while (err);
4650
7134f9ce
JB		 4651 if (pf->hw.revision_id == 0 && pf->hw.func_caps.npar_enable) {
4652 pf->hw.func_caps.num_msix_vectors += 1;
4653 pf->hw.func_caps.num_tx_qp =
4654 min_t(int, pf->hw.func_caps.num_tx_qp,
4655 I40E_MAX_NPAR_QPS);
4656 }
4657
41c445ff
JB		 4658 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4659 dev_info(&pf->pdev->dev,
4660 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4661 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4662 pf->hw.func_caps.num_msix_vectors,
4663 pf->hw.func_caps.num_msix_vectors_vf,
4664 pf->hw.func_caps.fd_filters_guaranteed,
4665 pf->hw.func_caps.fd_filters_best_effort,
4666 pf->hw.func_caps.num_tx_qp,
4667 pf->hw.func_caps.num_vsis);
4668
7134f9ce
JB		 4669#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4670 + pf->hw.func_caps.num_vfs)
4671 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4672 dev_info(&pf->pdev->dev,
4673 "got num_vsis %d, setting num_vsis to %d\n",
4674 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4675 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4676 }
4677
41c445ff
JB		 4678 return 0;
4679}
4680
4681/**
4682 * i40e_fdir_setup - initialize the Flow Director resources
4683 * @pf: board private structure
4684 **/
4685static void i40e_fdir_setup(struct i40e_pf *pf)
4686{
4687 struct i40e_vsi *vsi;
4688 bool new_vsi = false;
4689 int err, i;
4690
958a3e3b
SN		 4691 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4692 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4693 return;
4694
4695 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4696
4697 /* find existing or make new FDIR VSI */
4698 vsi = NULL;
4699 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4700 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4701 vsi = pf->vsi[i];
4702 if (!vsi) {
4703 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4704 if (!vsi) {
4705 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4706 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4707 return;
4708 }
4709 new_vsi = true;
4710 }
4711 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4712 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4713
4714 err = i40e_vsi_setup_tx_resources(vsi);
4715 if (!err)
4716 err = i40e_vsi_setup_rx_resources(vsi);
4717 if (!err)
4718 err = i40e_vsi_configure(vsi);
4719 if (!err && new_vsi) {
4720 char int_name[IFNAMSIZ + 9];
4721 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4722 dev_driver_string(&pf->pdev->dev));
4723 err = i40e_vsi_request_irq(vsi, int_name);
4724 }
4725 if (!err)
4726 err = i40e_up_complete(vsi);
4727
4728 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4729}
4730
4731/**
4732 * i40e_fdir_teardown - release the Flow Director resources
4733 * @pf: board private structure
4734 **/
4735static void i40e_fdir_teardown(struct i40e_pf *pf)
4736{
4737 int i;
4738
4739 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4740 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4741 i40e_vsi_release(pf->vsi[i]);
4742 break;
4743 }
4744 }
4745}
4746
4747/**
f650a38b 4748 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4749 * @pf: board private structure
4750 *
f650a38b
ASJ		 4751 * Close up the VFs and other things in prep for pf Reset.
4752 **/
4753static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4754{
41c445ff
JB		 4755 struct i40e_hw *hw = &pf->hw;
4756 i40e_status ret;
4757 u32 v;
4758
4759 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4760 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4761 return 0;
41c445ff
JB		 4762
4763 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4764
37f0be6d
ASJ		 4765 if (i40e_check_asq_alive(hw))
4766 i40e_vc_notify_reset(pf);
41c445ff
JB		 4767
4768 /* quiesce the VSIs and their queues that are not already DOWN */
4769 i40e_pf_quiesce_all_vsi(pf);
4770
4771 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4772 if (pf->vsi[v])
4773 pf->vsi[v]->seid = 0;
4774 }
4775
4776 i40e_shutdown_adminq(&pf->hw);
4777
f650a38b
ASJ		 4778 /* call shutdown HMC */
4779 ret = i40e_shutdown_lan_hmc(hw);
4780 if (ret) {
4781 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4782 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4783 }
4784 return ret;
4785}
4786
4787/**
4788 * i40e_reset_and_rebuild - reset and rebuid using a saved config
4789 * @pf: board private structure
bc7d338f 4790 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4791 **/
bc7d338f 4792static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4793{
4794 struct i40e_driver_version dv;
4795 struct i40e_hw *hw = &pf->hw;
4796 i40e_status ret;
4797 u32 v;
4798
41c445ff
JB		 4799 /* Now we wait for GRST to settle out.
4800 * We don't have to delete the VEBs or VSIs from the hw switch
4801 * because the reset will make them disappear.
4802 */
4803 ret = i40e_pf_reset(hw);
4804 if (ret)
4805 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4806 pf->pfr_count++;
4807
4808 if (test_bit(__I40E_DOWN, &pf->state))
4809 goto end_core_reset;
4810 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4811
4812 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4813 ret = i40e_init_adminq(&pf->hw);
4814 if (ret) {
4815 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4816 goto end_core_reset;
4817 }
4818
4819 ret = i40e_get_capabilities(pf);
4820 if (ret) {
4821 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4822 ret);
4823 goto end_core_reset;
4824 }
4825
41c445ff
JB		 4826 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4827 hw->func_caps.num_rx_qp,
4828 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4829 if (ret) {
4830 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4831 goto end_core_reset;
4832 }
4833 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4834 if (ret) {
4835 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4836 goto end_core_reset;
4837 }
4838
4839 /* do basic switch setup */
bc7d338f 4840 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4841 if (ret)
4842 goto end_core_reset;
4843
4844 /* Rebuild the VSIs and VEBs that existed before reset.
4845 * They are still in our local switch element arrays, so only
4846 * need to rebuild the switch model in the HW.
4847 *
4848 * If there were VEBs but the reconstitution failed, we'll try
4849 * try to recover minimal use by getting the basic PF VSI working.
4850 */
4851 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4852 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4853 /* find the one VEB connected to the MAC, and find orphans */
4854 for (v = 0; v < I40E_MAX_VEB; v++) {
4855 if (!pf->veb[v])
4856 continue;
4857
4858 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4859 pf->veb[v]->uplink_seid == 0) {
4860 ret = i40e_reconstitute_veb(pf->veb[v]);
4861
4862 if (!ret)
4863 continue;
4864
4865 /* If Main VEB failed, we're in deep doodoo,
4866 * so give up rebuilding the switch and set up
4867 * for minimal rebuild of PF VSI.
4868 * If orphan failed, we'll report the error
4869 * but try to keep going.
4870 */
4871 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4872 dev_info(&pf->pdev->dev,
4873 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4874 ret);
4875 pf->vsi[pf->lan_vsi]->uplink_seid
4876 = pf->mac_seid;
4877 break;
4878 } else if (pf->veb[v]->uplink_seid == 0) {
4879 dev_info(&pf->pdev->dev,
4880 "rebuild of orphan VEB failed: %d\n",
4881 ret);
4882 }
4883 }
4884 }
4885 }
4886
4887 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4888 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4889 /* no VEB, so rebuild only the Main VSI */
4890 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4891 if (ret) {
4892 dev_info(&pf->pdev->dev,
4893 "rebuild of Main VSI failed: %d\n", ret);
4894 goto end_core_reset;
4895 }
4896 }
4897
4898 /* reinit the misc interrupt */
4899 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4900 ret = i40e_setup_misc_vector(pf);
4901
4902 /* restart the VSIs that were rebuilt and running before the reset */
4903 i40e_pf_unquiesce_all_vsi(pf);
4904
4905 /* tell the firmware that we're starting */
4906 dv.major_version = DRV_VERSION_MAJOR;
4907 dv.minor_version = DRV_VERSION_MINOR;
4908 dv.build_version = DRV_VERSION_BUILD;
4909 dv.subbuild_version = 0;
4910 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4911
4912 dev_info(&pf->pdev->dev, "PF reset done\n");
4913
4914end_core_reset:
4915 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4916}
4917
f650a38b
ASJ		 4918/**
4919 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4920 * @pf: board private structure
4921 *
4922 * Close up the VFs and other things in prep for a Core Reset,
4923 * then get ready to rebuild the world.
4924 **/
4925static void i40e_handle_reset_warning(struct i40e_pf *pf)
4926{
4927 i40e_status ret;
4928
4929 ret = i40e_prep_for_reset(pf);
4930 if (!ret)
bc7d338f 4931 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4932}
4933
41c445ff
JB		 4934/**
4935 * i40e_handle_mdd_event
4936 * @pf: pointer to the pf structure
4937 *
4938 * Called from the MDD irq handler to identify possibly malicious vfs
4939 **/
4940static void i40e_handle_mdd_event(struct i40e_pf *pf)
4941{
4942 struct i40e_hw *hw = &pf->hw;
4943 bool mdd_detected = false;
4944 struct i40e_vf *vf;
4945 u32 reg;
4946 int i;
4947
4948 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
4949 return;
4950
4951 /* find what triggered the MDD event */
4952 reg = rd32(hw, I40E_GL_MDET_TX);
4953 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4954 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
4955 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
4956 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
4957 >> I40E_GL_MDET_TX_EVENT_SHIFT;
4958 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
4959 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
4960 dev_info(&pf->pdev->dev,
4961 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
4962 event, queue, func);
4963 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
4964 mdd_detected = true;
4965 }
4966 reg = rd32(hw, I40E_GL_MDET_RX);
4967 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4968 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
4969 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
4970 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
4971 >> I40E_GL_MDET_RX_EVENT_SHIFT;
4972 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
4973 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
4974 dev_info(&pf->pdev->dev,
4975 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
4976 event, queue, func);
4977 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
4978 mdd_detected = true;
4979 }
4980
4981 /* see if one of the VFs needs its hand slapped */
4982 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
4983 vf = &(pf->vf[i]);
4984 reg = rd32(hw, I40E_VP_MDET_TX(i));
4985 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
4986 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
4987 vf->num_mdd_events++;
4988 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
4989 }
4990
4991 reg = rd32(hw, I40E_VP_MDET_RX(i));
4992 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
4993 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
4994 vf->num_mdd_events++;
4995 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
4996 }
4997
4998 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
4999 dev_info(&pf->pdev->dev,
5000 "Too many MDD events on VF %d, disabled\n", i);
5001 dev_info(&pf->pdev->dev,
5002 "Use PF Control I/F to re-enable the VF\n");
5003 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5004 }
5005 }
5006
5007 /* re-enable mdd interrupt cause */
5008 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5009 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5010 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5011 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5012 i40e_flush(hw);
5013}
5014
a1c9a9d9
JK		 5015#ifdef CONFIG_I40E_VXLAN
5016/**
5017 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5018 * @pf: board private structure
5019 **/
5020static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5021{
5022 const int vxlan_hdr_qwords = 4;
5023 struct i40e_hw *hw = &pf->hw;
5024 i40e_status ret;
5025 u8 filter_index;
5026 __be16 port;
5027 int i;
5028
5029 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5030 return;
5031
5032 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5033
5034 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5035 if (pf->pending_vxlan_bitmap & (1 << i)) {
5036 pf->pending_vxlan_bitmap &= ~(1 << i);
5037 port = pf->vxlan_ports[i];
5038 ret = port ?
5039 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5040 vxlan_hdr_qwords,
5041 I40E_AQC_TUNNEL_TYPE_VXLAN,
5042 &filter_index, NULL)
5043 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5044
5045 if (ret) {
5046 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5047 port ? "adding" : "deleting",
5048 ntohs(port), port ? i : i);
5049
5050 pf->vxlan_ports[i] = 0;
5051 } else {
5052 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5053 port ? "Added" : "Deleted",
5054 ntohs(port), port ? i : filter_index);
5055 }
5056 }
5057 }
5058}
5059
5060#endif
41c445ff
JB		 5061/**
5062 * i40e_service_task - Run the driver's async subtasks
5063 * @work: pointer to work_struct containing our data
5064 **/
5065static void i40e_service_task(struct work_struct *work)
5066{
5067 struct i40e_pf *pf = container_of(work,
5068 struct i40e_pf,
5069 service_task);
5070 unsigned long start_time = jiffies;
5071
5072 i40e_reset_subtask(pf);
5073 i40e_handle_mdd_event(pf);
5074 i40e_vc_process_vflr_event(pf);
5075 i40e_watchdog_subtask(pf);
5076 i40e_fdir_reinit_subtask(pf);
5077 i40e_check_hang_subtask(pf);
5078 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5079#ifdef CONFIG_I40E_VXLAN
5080 i40e_sync_vxlan_filters_subtask(pf);
5081#endif
41c445ff
JB		 5082 i40e_clean_adminq_subtask(pf);
5083
5084 i40e_service_event_complete(pf);
5085
5086 /* If the tasks have taken longer than one timer cycle or there
5087 * is more work to be done, reschedule the service task now
5088 * rather than wait for the timer to tick again.
5089 */
5090 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5091 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5092 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5093 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5094 i40e_service_event_schedule(pf);
5095}
5096
5097/**
5098 * i40e_service_timer - timer callback
5099 * @data: pointer to PF struct
5100 **/
5101static void i40e_service_timer(unsigned long data)
5102{
5103 struct i40e_pf *pf = (struct i40e_pf *)data;
5104
5105 mod_timer(&pf->service_timer,
5106 round_jiffies(jiffies + pf->service_timer_period));
5107 i40e_service_event_schedule(pf);
5108}
5109
5110/**
5111 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5112 * @vsi: the VSI being configured
5113 **/
5114static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5115{
5116 struct i40e_pf *pf = vsi->back;
5117
5118 switch (vsi->type) {
5119 case I40E_VSI_MAIN:
5120 vsi->alloc_queue_pairs = pf->num_lan_qps;
5121 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5122 I40E_REQ_DESCRIPTOR_MULTIPLE);
5123 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5124 vsi->num_q_vectors = pf->num_lan_msix;
5125 else
5126 vsi->num_q_vectors = 1;
5127
5128 break;
5129
5130 case I40E_VSI_FDIR:
5131 vsi->alloc_queue_pairs = 1;
5132 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5133 I40E_REQ_DESCRIPTOR_MULTIPLE);
5134 vsi->num_q_vectors = 1;
5135 break;
5136
5137 case I40E_VSI_VMDQ2:
5138 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5139 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5140 I40E_REQ_DESCRIPTOR_MULTIPLE);
5141 vsi->num_q_vectors = pf->num_vmdq_msix;
5142 break;
5143
5144 case I40E_VSI_SRIOV:
5145 vsi->alloc_queue_pairs = pf->num_vf_qps;
5146 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5147 I40E_REQ_DESCRIPTOR_MULTIPLE);
5148 break;
5149
5150 default:
5151 WARN_ON(1);
5152 return -ENODATA;
5153 }
5154
5155 return 0;
5156}
5157
f650a38b
ASJ		 5158/**
5159 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5160 * @type: VSI pointer
bc7d338f 5161 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5162 *
5163 * On error: returns error code (negative)
5164 * On success: returns 0
5165 **/
bc7d338f 5166static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5167{
5168 int size;
5169 int ret = 0;
5170
ac6c5e3d 5171 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5172 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5173 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5174 if (!vsi->tx_rings)
5175 return -ENOMEM;
f650a38b
ASJ		 5176 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5177
bc7d338f
ASJ		 5178 if (alloc_qvectors) {
5179 /* allocate memory for q_vector pointers */
5180 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5181 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5182 if (!vsi->q_vectors) {
5183 ret = -ENOMEM;
5184 goto err_vectors;
5185 }
f650a38b
ASJ		 5186 }
5187 return ret;
5188
5189err_vectors:
5190 kfree(vsi->tx_rings);
5191 return ret;
5192}
5193
41c445ff
JB		 5194/**
5195 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5196 * @pf: board private structure
5197 * @type: type of VSI
5198 *
5199 * On error: returns error code (negative)
5200 * On success: returns vsi index in PF (positive)
5201 **/
5202static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5203{
5204 int ret = -ENODEV;
5205 struct i40e_vsi *vsi;
5206 int vsi_idx;
5207 int i;
5208
5209 /* Need to protect the allocation of the VSIs at the PF level */
5210 mutex_lock(&pf->switch_mutex);
5211
5212 /* VSI list may be fragmented if VSI creation/destruction has
5213 * been happening. We can afford to do a quick scan to look
5214 * for any free VSIs in the list.
5215 *
5216 * find next empty vsi slot, looping back around if necessary
5217 */
5218 i = pf->next_vsi;
5219 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5220 i++;
5221 if (i >= pf->hw.func_caps.num_vsis) {
5222 i = 0;
5223 while (i < pf->next_vsi && pf->vsi[i])
5224 i++;
5225 }
5226
5227 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5228 vsi_idx = i; /* Found one! */
5229 } else {
5230 ret = -ENODEV;
493fb300 5231 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5232 }
5233 pf->next_vsi = ++i;
5234
5235 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5236 if (!vsi) {
5237 ret = -ENOMEM;
493fb300 5238 goto unlock_pf;
41c445ff
JB		 5239 }
5240 vsi->type = type;
5241 vsi->back = pf;
5242 set_bit(__I40E_DOWN, &vsi->state);
5243 vsi->flags = 0;
5244 vsi->idx = vsi_idx;
5245 vsi->rx_itr_setting = pf->rx_itr_default;
5246 vsi->tx_itr_setting = pf->tx_itr_default;
5247 vsi->netdev_registered = false;
5248 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5249 INIT_LIST_HEAD(&vsi->mac_filter_list);
5250
9f65e15b
AD		 5251 ret = i40e_set_num_rings_in_vsi(vsi);
5252 if (ret)
5253 goto err_rings;
5254
bc7d338f 5255 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5256 if (ret)
9f65e15b 5257 goto err_rings;
493fb300 5258
41c445ff
JB		 5259 /* Setup default MSIX irq handler for VSI */
5260 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5261
5262 pf->vsi[vsi_idx] = vsi;
5263 ret = vsi_idx;
493fb300
AD		 5264 goto unlock_pf;
5265
9f65e15b 5266err_rings:
493fb300
AD		 5267 pf->next_vsi = i - 1;
5268 kfree(vsi);
5269unlock_pf:
41c445ff
JB		 5270 mutex_unlock(&pf->switch_mutex);
5271 return ret;
5272}
5273
f650a38b
ASJ		 5274/**
5275 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5276 * @type: VSI pointer
bc7d338f 5277 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5278 *
5279 * On error: returns error code (negative)
5280 * On success: returns 0
5281 **/
bc7d338f 5282static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5283{
5284 /* free the ring and vector containers */
bc7d338f
ASJ		 5285 if (free_qvectors) {
5286 kfree(vsi->q_vectors);
5287 vsi->q_vectors = NULL;
5288 }
f650a38b
ASJ		 5289 kfree(vsi->tx_rings);
5290 vsi->tx_rings = NULL;
5291 vsi->rx_rings = NULL;
5292}
5293
41c445ff
JB		 5294/**
5295 * i40e_vsi_clear - Deallocate the VSI provided
5296 * @vsi: the VSI being un-configured
5297 **/
5298static int i40e_vsi_clear(struct i40e_vsi *vsi)
5299{
5300 struct i40e_pf *pf;
5301
5302 if (!vsi)
5303 return 0;
5304
5305 if (!vsi->back)
5306 goto free_vsi;
5307 pf = vsi->back;
5308
5309 mutex_lock(&pf->switch_mutex);
5310 if (!pf->vsi[vsi->idx]) {
5311 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5312 vsi->idx, vsi->idx, vsi, vsi->type);
5313 goto unlock_vsi;
5314 }
5315
5316 if (pf->vsi[vsi->idx] != vsi) {
5317 dev_err(&pf->pdev->dev,
5318 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5319 pf->vsi[vsi->idx]->idx,
5320 pf->vsi[vsi->idx],
5321 pf->vsi[vsi->idx]->type,
5322 vsi->idx, vsi, vsi->type);
5323 goto unlock_vsi;
5324 }
5325
5326 /* updates the pf for this cleared vsi */
5327 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5328 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5329
bc7d338f 5330 i40e_vsi_free_arrays(vsi, true);
493fb300 5331
41c445ff
JB		 5332 pf->vsi[vsi->idx] = NULL;
5333 if (vsi->idx < pf->next_vsi)
5334 pf->next_vsi = vsi->idx;
5335
5336unlock_vsi:
5337 mutex_unlock(&pf->switch_mutex);
5338free_vsi:
5339 kfree(vsi);
5340
5341 return 0;
5342}
5343
9f65e15b
AD		 5344/**
5345 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5346 * @vsi: the VSI being cleaned
5347 **/
be1d5eea 5348static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5349{
5350 int i;
5351
be1d5eea 5352 if (vsi->tx_rings[0]) {
d7397644 5353 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5354 kfree_rcu(vsi->tx_rings[i], rcu);
5355 vsi->tx_rings[i] = NULL;
5356 vsi->rx_rings[i] = NULL;
5357 }
be1d5eea 5358 }
9f65e15b
AD		 5359}
5360
41c445ff
JB		 5361/**
5362 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5363 * @vsi: the VSI being configured
5364 **/
5365static int i40e_alloc_rings(struct i40e_vsi *vsi)
5366{
5367 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5368 int i;
5369
41c445ff 5370 /* Set basic values in the rings to be used later during open() */
d7397644 5371 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5372 struct i40e_ring *tx_ring;
5373 struct i40e_ring *rx_ring;
5374
ac6c5e3d 5375 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5376 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5377 if (!tx_ring)
5378 goto err_out;
41c445ff
JB		 5379
5380 tx_ring->queue_index = i;
5381 tx_ring->reg_idx = vsi->base_queue + i;
5382 tx_ring->ring_active = false;
5383 tx_ring->vsi = vsi;
5384 tx_ring->netdev = vsi->netdev;
5385 tx_ring->dev = &pf->pdev->dev;
5386 tx_ring->count = vsi->num_desc;
5387 tx_ring->size = 0;
5388 tx_ring->dcb_tc = 0;
9f65e15b 5389 vsi->tx_rings[i] = tx_ring;
41c445ff 5390
9f65e15b 5391 rx_ring = &tx_ring[1];
41c445ff
JB		 5392 rx_ring->queue_index = i;
5393 rx_ring->reg_idx = vsi->base_queue + i;
5394 rx_ring->ring_active = false;
5395 rx_ring->vsi = vsi;
5396 rx_ring->netdev = vsi->netdev;
5397 rx_ring->dev = &pf->pdev->dev;
5398 rx_ring->count = vsi->num_desc;
5399 rx_ring->size = 0;
5400 rx_ring->dcb_tc = 0;
5401 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5402 set_ring_16byte_desc_enabled(rx_ring);
5403 else
5404 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5405 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5406 }
5407
5408 return 0;
9f65e15b
AD		 5409
5410err_out:
5411 i40e_vsi_clear_rings(vsi);
5412 return -ENOMEM;
41c445ff
JB		 5413}
5414
5415/**
5416 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5417 * @pf: board private structure
5418 * @vectors: the number of MSI-X vectors to request
5419 *
5420 * Returns the number of vectors reserved, or error
5421 **/
5422static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5423{
5424 int err = 0;
5425
5426 pf->num_msix_entries = 0;
5427 while (vectors >= I40E_MIN_MSIX) {
5428 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5429 if (err == 0) {
5430 /* good to go */
5431 pf->num_msix_entries = vectors;
5432 break;
5433 } else if (err < 0) {
5434 /* total failure */
5435 dev_info(&pf->pdev->dev,
5436 "MSI-X vector reservation failed: %d\n", err);
5437 vectors = 0;
5438 break;
5439 } else {
5440 /* err > 0 is the hint for retry */
5441 dev_info(&pf->pdev->dev,
5442 "MSI-X vectors wanted %d, retrying with %d\n",
5443 vectors, err);
5444 vectors = err;
5445 }
5446 }
5447
5448 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5449 dev_info(&pf->pdev->dev,
5450 "Couldn't get enough vectors, only %d available\n",
5451 vectors);
5452 vectors = 0;
5453 }
5454
5455 return vectors;
5456}
5457
5458/**
5459 * i40e_init_msix - Setup the MSIX capability
5460 * @pf: board private structure
5461 *
5462 * Work with the OS to set up the MSIX vectors needed.
5463 *
5464 * Returns 0 on success, negative on failure
5465 **/
5466static int i40e_init_msix(struct i40e_pf *pf)
5467{
5468 i40e_status err = 0;
5469 struct i40e_hw *hw = &pf->hw;
5470 int v_budget, i;
5471 int vec;
5472
5473 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5474 return -ENODEV;
5475
5476 /* The number of vectors we'll request will be comprised of:
5477 * - Add 1 for "other" cause for Admin Queue events, etc.
5478 * - The number of LAN queue pairs
f8ff1464
ASJ		 5479 * - Queues being used for RSS.
5480 * We don't need as many as max_rss_size vectors.
5481 * use rss_size instead in the calculation since that
5482 * is governed by number of cpus in the system.
5483 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5484 * - The number of VMDq pairs
5485 * Once we count this up, try the request.
5486 *
5487 * If we can't get what we want, we'll simplify to nearly nothing
5488 * and try again. If that still fails, we punt.
5489 */
f8ff1464 5490 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5491 pf->num_vmdq_msix = pf->num_vmdq_qps;
5492 v_budget = 1 + pf->num_lan_msix;
5493 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5494 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5495 v_budget++;
5496
5497 /* Scale down if necessary, and the rings will share vectors */
5498 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5499
5500 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5501 GFP_KERNEL);
5502 if (!pf->msix_entries)
5503 return -ENOMEM;
5504
5505 for (i = 0; i < v_budget; i++)
5506 pf->msix_entries[i].entry = i;
5507 vec = i40e_reserve_msix_vectors(pf, v_budget);
5508 if (vec < I40E_MIN_MSIX) {
5509 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5510 kfree(pf->msix_entries);
5511 pf->msix_entries = NULL;
5512 return -ENODEV;
5513
5514 } else if (vec == I40E_MIN_MSIX) {
5515 /* Adjust for minimal MSIX use */
5516 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5517 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5518 pf->num_vmdq_vsis = 0;
5519 pf->num_vmdq_qps = 0;
5520 pf->num_vmdq_msix = 0;
5521 pf->num_lan_qps = 1;
5522 pf->num_lan_msix = 1;
5523
5524 } else if (vec != v_budget) {
5525 /* Scale vector usage down */
5526 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5527 vec--; /* reserve the misc vector */
5528
5529 /* partition out the remaining vectors */
5530 switch (vec) {
5531 case 2:
5532 pf->num_vmdq_vsis = 1;
5533 pf->num_lan_msix = 1;
5534 break;
5535 case 3:
5536 pf->num_vmdq_vsis = 1;
5537 pf->num_lan_msix = 2;
5538 break;
5539 default:
5540 pf->num_lan_msix = min_t(int, (vec / 2),
5541 pf->num_lan_qps);
5542 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5543 I40E_DEFAULT_NUM_VMDQ_VSI);
5544 break;
5545 }
5546 }
5547
5548 return err;
5549}
5550
493fb300
AD		 5551/**
5552 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5553 * @vsi: the VSI being configured
5554 * @v_idx: index of the vector in the vsi struct
5555 *
5556 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5557 **/
5558static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5559{
5560 struct i40e_q_vector *q_vector;
5561
5562 /* allocate q_vector */
5563 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5564 if (!q_vector)
5565 return -ENOMEM;
5566
5567 q_vector->vsi = vsi;
5568 q_vector->v_idx = v_idx;
5569 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5570 if (vsi->netdev)
5571 netif_napi_add(vsi->netdev, &q_vector->napi,
5572 i40e_napi_poll, vsi->work_limit);
5573
cd0b6fa6
AD		 5574 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5575 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5576
493fb300
AD		 5577 /* tie q_vector and vsi together */
5578 vsi->q_vectors[v_idx] = q_vector;
5579
5580 return 0;
5581}
5582
41c445ff
JB		 5583/**
5584 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5585 * @vsi: the VSI being configured
5586 *
5587 * We allocate one q_vector per queue interrupt. If allocation fails we
5588 * return -ENOMEM.
5589 **/
5590static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5591{
5592 struct i40e_pf *pf = vsi->back;
5593 int v_idx, num_q_vectors;
493fb300 5594 int err;
41c445ff
JB		 5595
5596 /* if not MSIX, give the one vector only to the LAN VSI */
5597 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5598 num_q_vectors = vsi->num_q_vectors;
5599 else if (vsi == pf->vsi[pf->lan_vsi])
5600 num_q_vectors = 1;
5601 else
5602 return -EINVAL;
5603
41c445ff 5604 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5605 err = i40e_alloc_q_vector(vsi, v_idx);
5606 if (err)
5607 goto err_out;
41c445ff
JB		 5608 }
5609
5610 return 0;
493fb300
AD		 5611
5612err_out:
5613 while (v_idx--)
5614 i40e_free_q_vector(vsi, v_idx);
5615
5616 return err;
41c445ff
JB		 5617}
5618
5619/**
5620 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5621 * @pf: board private structure to initialize
5622 **/
5623static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5624{
5625 int err = 0;
5626
5627 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5628 err = i40e_init_msix(pf);
5629 if (err) {
958a3e3b
SN		 5630 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5631 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5632 I40E_FLAG_DCB_ENABLED |
5633 I40E_FLAG_SRIOV_ENABLED |
5634 I40E_FLAG_FDIR_ENABLED |
5635 I40E_FLAG_FDIR_ATR_ENABLED |
5636 I40E_FLAG_VMDQ_ENABLED);
5637
5638 /* rework the queue expectations without MSIX */
5639 i40e_determine_queue_usage(pf);
5640 }
5641 }
5642
5643 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5644 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5645 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5646 err = pci_enable_msi(pf->pdev);
5647 if (err) {
958a3e3b 5648 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5649 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5650 }
5651 }
5652
958a3e3b
SN		 5653 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5654 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5655
41c445ff
JB		 5656 /* track first vector for misc interrupts */
5657 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5658}
5659
5660/**
5661 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5662 * @pf: board private structure
5663 *
5664 * This sets up the handler for MSIX 0, which is used to manage the
5665 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5666 * when in MSI or Legacy interrupt mode.
5667 **/
5668static int i40e_setup_misc_vector(struct i40e_pf *pf)
5669{
5670 struct i40e_hw *hw = &pf->hw;
5671 int err = 0;
5672
5673 /* Only request the irq if this is the first time through, and
5674 * not when we're rebuilding after a Reset
5675 */
5676 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5677 err = request_irq(pf->msix_entries[0].vector,
5678 i40e_intr, 0, pf->misc_int_name, pf);
5679 if (err) {
5680 dev_info(&pf->pdev->dev,
5681 "request_irq for msix_misc failed: %d\n", err);
5682 return -EFAULT;
5683 }
5684 }
5685
5686 i40e_enable_misc_int_causes(hw);
5687
5688 /* associate no queues to the misc vector */
5689 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5690 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5691
5692 i40e_flush(hw);
5693
5694 i40e_irq_dynamic_enable_icr0(pf);
5695
5696 return err;
5697}
5698
5699/**
5700 * i40e_config_rss - Prepare for RSS if used
5701 * @pf: board private structure
5702 **/
5703static int i40e_config_rss(struct i40e_pf *pf)
5704{
41c445ff
JB		 5705 /* Set of random keys generated using kernel random number generator */
5706 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5707 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5708 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5709 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5710 struct i40e_hw *hw = &pf->hw;
5711 u32 lut = 0;
5712 int i, j;
5713 u64 hena;
41c445ff
JB		 5714
5715 /* Fill out hash function seed */
5716 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5717 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5718
5719 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5720 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5721 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 5722 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 5723 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5724 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5725
5726 /* Populate the LUT with max no. of queues in round robin fashion */
5727 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5728
5729 /* The assumption is that lan qp count will be the highest
5730 * qp count for any PF VSI that needs RSS.
5731 * If multiple VSIs need RSS support, all the qp counts
5732 * for those VSIs should be a power of 2 for RSS to work.
5733 * If LAN VSI is the only consumer for RSS then this requirement
5734 * is not necessary.
5735 */
5736 if (j == pf->rss_size)
5737 j = 0;
5738 /* lut = 4-byte sliding window of 4 lut entries */
5739 lut = (lut << 8) | (j &
5740 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5741 /* On i = 3, we have 4 entries in lut; write to the register */
5742 if ((i & 3) == 3)
5743 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5744 }
5745 i40e_flush(hw);
5746
5747 return 0;
5748}
5749
f8ff1464
ASJ		 5750/**
5751 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5752 * @pf: board private structure
5753 * @queue_count: the requested queue count for rss.
5754 *
5755 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5756 * count which may be different from the requested queue count.
5757 **/
5758int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5759{
5760 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5761 return 0;
5762
5763 queue_count = min_t(int, queue_count, pf->rss_size_max);
5764 queue_count = rounddown_pow_of_two(queue_count);
5765
5766 if (queue_count != pf->rss_size) {
5767 if (pf->queues_left < (queue_count - pf->rss_size)) {
5768 dev_info(&pf->pdev->dev,
5769 "Not enough queues to do RSS on %d queues: remaining queues %d\n",
5770 queue_count, pf->queues_left);
5771 return pf->rss_size;
5772 }
5773 i40e_prep_for_reset(pf);
5774
5775 pf->num_lan_qps += (queue_count - pf->rss_size);
5776 pf->queues_left -= (queue_count - pf->rss_size);
5777 pf->rss_size = queue_count;
5778
5779 i40e_reset_and_rebuild(pf, true);
5780 i40e_config_rss(pf);
5781 }
5782 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5783 return pf->rss_size;
5784}
5785
41c445ff
JB		 5786/**
5787 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5788 * @pf: board private structure to initialize
5789 *
5790 * i40e_sw_init initializes the Adapter private data structure.
5791 * Fields are initialized based on PCI device information and
5792 * OS network device settings (MTU size).
5793 **/
5794static int i40e_sw_init(struct i40e_pf *pf)
5795{
5796 int err = 0;
5797 int size;
5798
5799 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5800 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5801 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5802 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5803 if (I40E_DEBUG_USER & debug)
5804 pf->hw.debug_mask = debug;
5805 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5806 I40E_DEFAULT_MSG_ENABLE);
5807 }
5808
5809 /* Set default capability flags */
5810 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5811 I40E_FLAG_MSI_ENABLED |
5812 I40E_FLAG_MSIX_ENABLED |
5813 I40E_FLAG_RX_PS_ENABLED |
41c445ff
JB		 5814 I40E_FLAG_RX_1BUF_ENABLED;
5815
7134f9ce
JB		 5816 /* Depending on PF configurations, it is possible that the RSS
5817 * maximum might end up larger than the available queues
5818 */
41c445ff 5819 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5820 pf->rss_size_max = min_t(int, pf->rss_size_max,
5821 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5822 if (pf->hw.func_caps.rss) {
5823 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5824 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5825 } else {
5826 pf->rss_size = 1;
5827 }
5828
5829 if (pf->hw.func_caps.dcb)
5830 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5831 else
5832 pf->num_tc_qps = 0;
5833
5834 if (pf->hw.func_caps.fd) {
5835 /* FW/NVM is not yet fixed in this regard */
5836 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5837 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5838 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5839 dev_info(&pf->pdev->dev,
5840 "Flow Director ATR mode Enabled\n");
5841 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5842 dev_info(&pf->pdev->dev,
5843 "Flow Director Side Band mode Enabled\n");
5844 pf->fdir_pf_filter_count =
5845 pf->hw.func_caps.fd_filters_guaranteed;
5846 }
5847 } else {
5848 pf->fdir_pf_filter_count = 0;
5849 }
5850
5851 if (pf->hw.func_caps.vmdq) {
5852 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5853 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5854 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5855 }
5856
5857 /* MFP mode enabled */
5858 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5859 pf->flags |= I40E_FLAG_MFP_ENABLED;
5860 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5861 }
5862
5863#ifdef CONFIG_PCI_IOV
5864 if (pf->hw.func_caps.num_vfs) {
5865 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5866 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5867 pf->num_req_vfs = min_t(int,
5868 pf->hw.func_caps.num_vfs,
5869 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5870 dev_info(&pf->pdev->dev,
5871 "Number of VFs being requested for PF[%d] = %d\n",
5872 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5873 }
5874#endif /* CONFIG_PCI_IOV */
5875 pf->eeprom_version = 0xDEAD;
5876 pf->lan_veb = I40E_NO_VEB;
5877 pf->lan_vsi = I40E_NO_VSI;
5878
5879 /* set up queue assignment tracking */
5880 size = sizeof(struct i40e_lump_tracking)
5881 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5882 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5883 if (!pf->qp_pile) {
5884 err = -ENOMEM;
5885 goto sw_init_done;
5886 }
5887 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5888 pf->qp_pile->search_hint = 0;
5889
5890 /* set up vector assignment tracking */
5891 size = sizeof(struct i40e_lump_tracking)
5892 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5893 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5894 if (!pf->irq_pile) {
5895 kfree(pf->qp_pile);
5896 err = -ENOMEM;
5897 goto sw_init_done;
5898 }
5899 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5900 pf->irq_pile->search_hint = 0;
5901
5902 mutex_init(&pf->switch_mutex);
5903
5904sw_init_done:
5905 return err;
5906}
5907
5908/**
5909 * i40e_set_features - set the netdev feature flags
5910 * @netdev: ptr to the netdev being adjusted
5911 * @features: the feature set that the stack is suggesting
5912 **/
5913static int i40e_set_features(struct net_device *netdev,
5914 netdev_features_t features)
5915{
5916 struct i40e_netdev_priv *np = netdev_priv(netdev);
5917 struct i40e_vsi *vsi = np->vsi;
5918
5919 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5920 i40e_vlan_stripping_enable(vsi);
5921 else
5922 i40e_vlan_stripping_disable(vsi);
5923
5924 return 0;
5925}
5926
a1c9a9d9
JK		 5927#ifdef CONFIG_I40E_VXLAN
5928/**
5929 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5930 * @pf: board private structure
5931 * @port: The UDP port to look up
5932 *
5933 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5934 **/
5935static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5936{
5937 u8 i;
5938
5939 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5940 if (pf->vxlan_ports[i] == port)
5941 return i;
5942 }
5943
5944 return i;
5945}
5946
5947/**
5948 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5949 * @netdev: This physical port's netdev
5950 * @sa_family: Socket Family that VXLAN is notifying us about
5951 * @port: New UDP port number that VXLAN started listening to
5952 **/
5953static void i40e_add_vxlan_port(struct net_device *netdev,
5954 sa_family_t sa_family, __be16 port)
5955{
5956 struct i40e_netdev_priv *np = netdev_priv(netdev);
5957 struct i40e_vsi *vsi = np->vsi;
5958 struct i40e_pf *pf = vsi->back;
5959 u8 next_idx;
5960 u8 idx;
5961
5962 if (sa_family == AF_INET6)
5963 return;
5964
5965 idx = i40e_get_vxlan_port_idx(pf, port);
5966
5967 /* Check if port already exists */
5968 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5969 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
5970 return;
5971 }
5972
5973 /* Now check if there is space to add the new port */
5974 next_idx = i40e_get_vxlan_port_idx(pf, 0);
5975
5976 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5977 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
5978 ntohs(port));
5979 return;
5980 }
5981
5982 /* New port: add it and mark its index in the bitmap */
5983 pf->vxlan_ports[next_idx] = port;
5984 pf->pending_vxlan_bitmap |= (1 << next_idx);
5985
5986 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
5987}
5988
5989/**
5990 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
5991 * @netdev: This physical port's netdev
5992 * @sa_family: Socket Family that VXLAN is notifying us about
5993 * @port: UDP port number that VXLAN stopped listening to
5994 **/
5995static void i40e_del_vxlan_port(struct net_device *netdev,
5996 sa_family_t sa_family, __be16 port)
5997{
5998 struct i40e_netdev_priv *np = netdev_priv(netdev);
5999 struct i40e_vsi *vsi = np->vsi;
6000 struct i40e_pf *pf = vsi->back;
6001 u8 idx;
6002
6003 if (sa_family == AF_INET6)
6004 return;
6005
6006 idx = i40e_get_vxlan_port_idx(pf, port);
6007
6008 /* Check if port already exists */
6009 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6010 /* if port exists, set it to 0 (mark for deletion)
6011 * and make it pending
6012 */
6013 pf->vxlan_ports[idx] = 0;
6014
6015 pf->pending_vxlan_bitmap |= (1 << idx);
6016
6017 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6018 } else {
6019 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6020 ntohs(port));
6021 }
6022}
6023
6024#endif
41c445ff
JB		 6025static const struct net_device_ops i40e_netdev_ops = {
6026 .ndo_open = i40e_open,
6027 .ndo_stop = i40e_close,
6028 .ndo_start_xmit = i40e_lan_xmit_frame,
6029 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6030 .ndo_set_rx_mode = i40e_set_rx_mode,
6031 .ndo_validate_addr = eth_validate_addr,
6032 .ndo_set_mac_address = i40e_set_mac,
6033 .ndo_change_mtu = i40e_change_mtu,
6034 .ndo_tx_timeout = i40e_tx_timeout,
6035 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6036 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6037#ifdef CONFIG_NET_POLL_CONTROLLER
6038 .ndo_poll_controller = i40e_netpoll,
6039#endif
6040 .ndo_setup_tc = i40e_setup_tc,
6041 .ndo_set_features = i40e_set_features,
6042 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6043 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6044 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6045 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6046#ifdef CONFIG_I40E_VXLAN
6047 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6048 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6049#endif
41c445ff
JB		 6050};
6051
6052/**
6053 * i40e_config_netdev - Setup the netdev flags
6054 * @vsi: the VSI being configured
6055 *
6056 * Returns 0 on success, negative value on failure
6057 **/
6058static int i40e_config_netdev(struct i40e_vsi *vsi)
6059{
1a10370a 6060 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6061 struct i40e_pf *pf = vsi->back;
6062 struct i40e_hw *hw = &pf->hw;
6063 struct i40e_netdev_priv *np;
6064 struct net_device *netdev;
6065 u8 mac_addr[ETH_ALEN];
6066 int etherdev_size;
6067
6068 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6069 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6070 if (!netdev)
6071 return -ENOMEM;
6072
6073 vsi->netdev = netdev;
6074 np = netdev_priv(netdev);
6075 np->vsi = vsi;
6076
6077 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6078 NETIF_F_GSO_UDP_TUNNEL |
6079 NETIF_F_TSO |
6080 NETIF_F_SG;
6081
6082 netdev->features = NETIF_F_SG |
6083 NETIF_F_IP_CSUM |
6084 NETIF_F_SCTP_CSUM |
6085 NETIF_F_HIGHDMA |
6086 NETIF_F_GSO_UDP_TUNNEL |
6087 NETIF_F_HW_VLAN_CTAG_TX |
6088 NETIF_F_HW_VLAN_CTAG_RX |
6089 NETIF_F_HW_VLAN_CTAG_FILTER |
6090 NETIF_F_IPV6_CSUM |
6091 NETIF_F_TSO |
6092 NETIF_F_TSO6 |
6093 NETIF_F_RXCSUM |
6094 NETIF_F_RXHASH |
6095 0;
6096
6097 /* copy netdev features into list of user selectable features */
6098 netdev->hw_features |= netdev->features;
6099
6100 if (vsi->type == I40E_VSI_MAIN) {
6101 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6102 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6103 } else {
6104 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6105 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6106 pf->vsi[pf->lan_vsi]->netdev->name);
6107 random_ether_addr(mac_addr);
6108 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6109 }
1a10370a 6110 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6111
6112 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6113 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6114 /* vlan gets same features (except vlan offload)
6115 * after any tweaks for specific VSI types
6116 */
6117 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6118 NETIF_F_HW_VLAN_CTAG_RX |
6119 NETIF_F_HW_VLAN_CTAG_FILTER);
6120 netdev->priv_flags |= IFF_UNICAST_FLT;
6121 netdev->priv_flags |= IFF_SUPP_NOFCS;
6122 /* Setup netdev TC information */
6123 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6124
6125 netdev->netdev_ops = &i40e_netdev_ops;
6126 netdev->watchdog_timeo = 5 * HZ;
6127 i40e_set_ethtool_ops(netdev);
6128
6129 return 0;
6130}
6131
6132/**
6133 * i40e_vsi_delete - Delete a VSI from the switch
6134 * @vsi: the VSI being removed
6135 *
6136 * Returns 0 on success, negative value on failure
6137 **/
6138static void i40e_vsi_delete(struct i40e_vsi *vsi)
6139{
6140 /* remove default VSI is not allowed */
6141 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6142 return;
6143
6144 /* there is no HW VSI for FDIR */
6145 if (vsi->type == I40E_VSI_FDIR)
6146 return;
6147
6148 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6149 return;
6150}
6151
6152/**
6153 * i40e_add_vsi - Add a VSI to the switch
6154 * @vsi: the VSI being configured
6155 *
6156 * This initializes a VSI context depending on the VSI type to be added and
6157 * passes it down to the add_vsi aq command.
6158 **/
6159static int i40e_add_vsi(struct i40e_vsi *vsi)
6160{
6161 int ret = -ENODEV;
6162 struct i40e_mac_filter *f, *ftmp;
6163 struct i40e_pf *pf = vsi->back;
6164 struct i40e_hw *hw = &pf->hw;
6165 struct i40e_vsi_context ctxt;
6166 u8 enabled_tc = 0x1; /* TC0 enabled */
6167 int f_count = 0;
6168
6169 memset(&ctxt, 0, sizeof(ctxt));
6170 switch (vsi->type) {
6171 case I40E_VSI_MAIN:
6172 /* The PF's main VSI is already setup as part of the
6173 * device initialization, so we'll not bother with
6174 * the add_vsi call, but we will retrieve the current
6175 * VSI context.
6176 */
6177 ctxt.seid = pf->main_vsi_seid;
6178 ctxt.pf_num = pf->hw.pf_id;
6179 ctxt.vf_num = 0;
6180 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6181 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6182 if (ret) {
6183 dev_info(&pf->pdev->dev,
6184 "couldn't get pf vsi config, err %d, aq_err %d\n",
6185 ret, pf->hw.aq.asq_last_status);
6186 return -ENOENT;
6187 }
6188 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6189 vsi->info.valid_sections = 0;
6190
6191 vsi->seid = ctxt.seid;
6192 vsi->id = ctxt.vsi_number;
6193
6194 enabled_tc = i40e_pf_get_tc_map(pf);
6195
6196 /* MFP mode setup queue map and update VSI */
6197 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6198 memset(&ctxt, 0, sizeof(ctxt));
6199 ctxt.seid = pf->main_vsi_seid;
6200 ctxt.pf_num = pf->hw.pf_id;
6201 ctxt.vf_num = 0;
6202 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6203 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6204 if (ret) {
6205 dev_info(&pf->pdev->dev,
6206 "update vsi failed, aq_err=%d\n",
6207 pf->hw.aq.asq_last_status);
6208 ret = -ENOENT;
6209 goto err;
6210 }
6211 /* update the local VSI info queue map */
6212 i40e_vsi_update_queue_map(vsi, &ctxt);
6213 vsi->info.valid_sections = 0;
6214 } else {
6215 /* Default/Main VSI is only enabled for TC0
6216 * reconfigure it to enable all TCs that are
6217 * available on the port in SFP mode.
6218 */
6219 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6220 if (ret) {
6221 dev_info(&pf->pdev->dev,
6222 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6223 enabled_tc, ret,
6224 pf->hw.aq.asq_last_status);
6225 ret = -ENOENT;
6226 }
6227 }
6228 break;
6229
6230 case I40E_VSI_FDIR:
6231 /* no queue mapping or actual HW VSI needed */
6232 vsi->info.valid_sections = 0;
6233 vsi->seid = 0;
6234 vsi->id = 0;
6235 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6236 return 0;
6237 break;
6238
6239 case I40E_VSI_VMDQ2:
6240 ctxt.pf_num = hw->pf_id;
6241 ctxt.vf_num = 0;
6242 ctxt.uplink_seid = vsi->uplink_seid;
6243 ctxt.connection_type = 0x1; /* regular data port */
6244 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6245
6246 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6247
6248 /* This VSI is connected to VEB so the switch_id
6249 * should be set to zero by default.
6250 */
6251 ctxt.info.switch_id = 0;
6252 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6253 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6254
6255 /* Setup the VSI tx/rx queue map for TC0 only for now */
6256 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6257 break;
6258
6259 case I40E_VSI_SRIOV:
6260 ctxt.pf_num = hw->pf_id;
6261 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6262 ctxt.uplink_seid = vsi->uplink_seid;
6263 ctxt.connection_type = 0x1; /* regular data port */
6264 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6265
6266 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6267
6268 /* This VSI is connected to VEB so the switch_id
6269 * should be set to zero by default.
6270 */
6271 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6272
6273 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6274 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6275 /* Setup the VSI tx/rx queue map for TC0 only for now */
6276 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6277 break;
6278
6279 default:
6280 return -ENODEV;
6281 }
6282
6283 if (vsi->type != I40E_VSI_MAIN) {
6284 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6285 if (ret) {
6286 dev_info(&vsi->back->pdev->dev,
6287 "add vsi failed, aq_err=%d\n",
6288 vsi->back->hw.aq.asq_last_status);
6289 ret = -ENOENT;
6290 goto err;
6291 }
6292 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6293 vsi->info.valid_sections = 0;
6294 vsi->seid = ctxt.seid;
6295 vsi->id = ctxt.vsi_number;
6296 }
6297
6298 /* If macvlan filters already exist, force them to get loaded */
6299 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6300 f->changed = true;
6301 f_count++;
6302 }
6303 if (f_count) {
6304 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6305 pf->flags |= I40E_FLAG_FILTER_SYNC;
6306 }
6307
6308 /* Update VSI BW information */
6309 ret = i40e_vsi_get_bw_info(vsi);
6310 if (ret) {
6311 dev_info(&pf->pdev->dev,
6312 "couldn't get vsi bw info, err %d, aq_err %d\n",
6313 ret, pf->hw.aq.asq_last_status);
6314 /* VSI is already added so not tearing that up */
6315 ret = 0;
6316 }
6317
6318err:
6319 return ret;
6320}
6321
6322/**
6323 * i40e_vsi_release - Delete a VSI and free its resources
6324 * @vsi: the VSI being removed
6325 *
6326 * Returns 0 on success or < 0 on error
6327 **/
6328int i40e_vsi_release(struct i40e_vsi *vsi)
6329{
6330 struct i40e_mac_filter *f, *ftmp;
6331 struct i40e_veb *veb = NULL;
6332 struct i40e_pf *pf;
6333 u16 uplink_seid;
6334 int i, n;
6335
6336 pf = vsi->back;
6337
6338 /* release of a VEB-owner or last VSI is not allowed */
6339 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6340 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6341 vsi->seid, vsi->uplink_seid);
6342 return -ENODEV;
6343 }
6344 if (vsi == pf->vsi[pf->lan_vsi] &&
6345 !test_bit(__I40E_DOWN, &pf->state)) {
6346 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6347 return -ENODEV;
6348 }
6349
6350 uplink_seid = vsi->uplink_seid;
6351 if (vsi->type != I40E_VSI_SRIOV) {
6352 if (vsi->netdev_registered) {
6353 vsi->netdev_registered = false;
6354 if (vsi->netdev) {
6355 /* results in a call to i40e_close() */
6356 unregister_netdev(vsi->netdev);
6357 free_netdev(vsi->netdev);
6358 vsi->netdev = NULL;
6359 }
6360 } else {
6361 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6362 i40e_down(vsi);
6363 i40e_vsi_free_irq(vsi);
6364 i40e_vsi_free_tx_resources(vsi);
6365 i40e_vsi_free_rx_resources(vsi);
6366 }
6367 i40e_vsi_disable_irq(vsi);
6368 }
6369
6370 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6371 i40e_del_filter(vsi, f->macaddr, f->vlan,
6372 f->is_vf, f->is_netdev);
6373 i40e_sync_vsi_filters(vsi);
6374
6375 i40e_vsi_delete(vsi);
6376 i40e_vsi_free_q_vectors(vsi);
6377 i40e_vsi_clear_rings(vsi);
6378 i40e_vsi_clear(vsi);
6379
6380 /* If this was the last thing on the VEB, except for the
6381 * controlling VSI, remove the VEB, which puts the controlling
6382 * VSI onto the next level down in the switch.
6383 *
6384 * Well, okay, there's one more exception here: don't remove
6385 * the orphan VEBs yet. We'll wait for an explicit remove request
6386 * from up the network stack.
6387 */
6388 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6389 if (pf->vsi[i] &&
6390 pf->vsi[i]->uplink_seid == uplink_seid &&
6391 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6392 n++; /* count the VSIs */
6393 }
6394 }
6395 for (i = 0; i < I40E_MAX_VEB; i++) {
6396 if (!pf->veb[i])
6397 continue;
6398 if (pf->veb[i]->uplink_seid == uplink_seid)
6399 n++; /* count the VEBs */
6400 if (pf->veb[i]->seid == uplink_seid)
6401 veb = pf->veb[i];
6402 }
6403 if (n == 0 && veb && veb->uplink_seid != 0)
6404 i40e_veb_release(veb);
6405
6406 return 0;
6407}
6408
6409/**
6410 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6411 * @vsi: ptr to the VSI
6412 *
6413 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6414 * corresponding SW VSI structure and initializes num_queue_pairs for the
6415 * newly allocated VSI.
6416 *
6417 * Returns 0 on success or negative on failure
6418 **/
6419static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6420{
6421 int ret = -ENOENT;
6422 struct i40e_pf *pf = vsi->back;
6423
493fb300 6424 if (vsi->q_vectors[0]) {
41c445ff
JB		 6425 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6426 vsi->seid);
6427 return -EEXIST;
6428 }
6429
6430 if (vsi->base_vector) {
6431 dev_info(&pf->pdev->dev,
6432 "VSI %d has non-zero base vector %d\n",
6433 vsi->seid, vsi->base_vector);
6434 return -EEXIST;
6435 }
6436
6437 ret = i40e_alloc_q_vectors(vsi);
6438 if (ret) {
6439 dev_info(&pf->pdev->dev,
6440 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6441 vsi->num_q_vectors, vsi->seid, ret);
6442 vsi->num_q_vectors = 0;
6443 goto vector_setup_out;
6444 }
6445
958a3e3b
SN		 6446 if (vsi->num_q_vectors)
6447 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6448 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6449 if (vsi->base_vector < 0) {
6450 dev_info(&pf->pdev->dev,
6451 "failed to get q tracking for VSI %d, err=%d\n",
6452 vsi->seid, vsi->base_vector);
6453 i40e_vsi_free_q_vectors(vsi);
6454 ret = -ENOENT;
6455 goto vector_setup_out;
6456 }
6457
6458vector_setup_out:
6459 return ret;
6460}
6461
bc7d338f
ASJ		 6462/**
6463 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6464 * @vsi: pointer to the vsi.
6465 *
6466 * This re-allocates a vsi's queue resources.
6467 *
6468 * Returns pointer to the successfully allocated and configured VSI sw struct
6469 * on success, otherwise returns NULL on failure.
6470 **/
6471static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6472{
6473 struct i40e_pf *pf = vsi->back;
6474 u8 enabled_tc;
6475 int ret;
6476
6477 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6478 i40e_vsi_clear_rings(vsi);
6479
6480 i40e_vsi_free_arrays(vsi, false);
6481 i40e_set_num_rings_in_vsi(vsi);
6482 ret = i40e_vsi_alloc_arrays(vsi, false);
6483 if (ret)
6484 goto err_vsi;
6485
6486 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6487 if (ret < 0) {
6488 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6489 vsi->seid, ret);
6490 goto err_vsi;
6491 }
6492 vsi->base_queue = ret;
6493
6494 /* Update the FW view of the VSI. Force a reset of TC and queue
6495 * layout configurations.
6496 */
6497 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6498 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6499 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6500 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6501
6502 /* assign it some queues */
6503 ret = i40e_alloc_rings(vsi);
6504 if (ret)
6505 goto err_rings;
6506
6507 /* map all of the rings to the q_vectors */
6508 i40e_vsi_map_rings_to_vectors(vsi);
6509 return vsi;
6510
6511err_rings:
6512 i40e_vsi_free_q_vectors(vsi);
6513 if (vsi->netdev_registered) {
6514 vsi->netdev_registered = false;
6515 unregister_netdev(vsi->netdev);
6516 free_netdev(vsi->netdev);
6517 vsi->netdev = NULL;
6518 }
6519 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6520err_vsi:
6521 i40e_vsi_clear(vsi);
6522 return NULL;
6523}
6524
41c445ff
JB		 6525/**
6526 * i40e_vsi_setup - Set up a VSI by a given type
6527 * @pf: board private structure
6528 * @type: VSI type
6529 * @uplink_seid: the switch element to link to
6530 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6531 *
6532 * This allocates the sw VSI structure and its queue resources, then add a VSI
6533 * to the identified VEB.
6534 *
6535 * Returns pointer to the successfully allocated and configure VSI sw struct on
6536 * success, otherwise returns NULL on failure.
6537 **/
6538struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6539 u16 uplink_seid, u32 param1)
6540{
6541 struct i40e_vsi *vsi = NULL;
6542 struct i40e_veb *veb = NULL;
6543 int ret, i;
6544 int v_idx;
6545
6546 /* The requested uplink_seid must be either
6547 * - the PF's port seid
6548 * no VEB is needed because this is the PF
6549 * or this is a Flow Director special case VSI
6550 * - seid of an existing VEB
6551 * - seid of a VSI that owns an existing VEB
6552 * - seid of a VSI that doesn't own a VEB
6553 * a new VEB is created and the VSI becomes the owner
6554 * - seid of the PF VSI, which is what creates the first VEB
6555 * this is a special case of the previous
6556 *
6557 * Find which uplink_seid we were given and create a new VEB if needed
6558 */
6559 for (i = 0; i < I40E_MAX_VEB; i++) {
6560 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6561 veb = pf->veb[i];
6562 break;
6563 }
6564 }
6565
6566 if (!veb && uplink_seid != pf->mac_seid) {
6567
6568 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6569 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6570 vsi = pf->vsi[i];
6571 break;
6572 }
6573 }
6574 if (!vsi) {
6575 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6576 uplink_seid);
6577 return NULL;
6578 }
6579
6580 if (vsi->uplink_seid == pf->mac_seid)
6581 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6582 vsi->tc_config.enabled_tc);
6583 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6584 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6585 vsi->tc_config.enabled_tc);
6586
6587 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6588 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6589 veb = pf->veb[i];
6590 }
6591 if (!veb) {
6592 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6593 return NULL;
6594 }
6595
6596 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6597 uplink_seid = veb->seid;
6598 }
6599
6600 /* get vsi sw struct */
6601 v_idx = i40e_vsi_mem_alloc(pf, type);
6602 if (v_idx < 0)
6603 goto err_alloc;
6604 vsi = pf->vsi[v_idx];
6605 vsi->type = type;
6606 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6607
6608 if (type == I40E_VSI_MAIN)
6609 pf->lan_vsi = v_idx;
6610 else if (type == I40E_VSI_SRIOV)
6611 vsi->vf_id = param1;
6612 /* assign it some queues */
6613 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6614 if (ret < 0) {
6615 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6616 vsi->seid, ret);
6617 goto err_vsi;
6618 }
6619 vsi->base_queue = ret;
6620
6621 /* get a VSI from the hardware */
6622 vsi->uplink_seid = uplink_seid;
6623 ret = i40e_add_vsi(vsi);
6624 if (ret)
6625 goto err_vsi;
6626
6627 switch (vsi->type) {
6628 /* setup the netdev if needed */
6629 case I40E_VSI_MAIN:
6630 case I40E_VSI_VMDQ2:
6631 ret = i40e_config_netdev(vsi);
6632 if (ret)
6633 goto err_netdev;
6634 ret = register_netdev(vsi->netdev);
6635 if (ret)
6636 goto err_netdev;
6637 vsi->netdev_registered = true;
6638 netif_carrier_off(vsi->netdev);
6639 /* fall through */
6640
6641 case I40E_VSI_FDIR:
6642 /* set up vectors and rings if needed */
6643 ret = i40e_vsi_setup_vectors(vsi);
6644 if (ret)
6645 goto err_msix;
6646
6647 ret = i40e_alloc_rings(vsi);
6648 if (ret)
6649 goto err_rings;
6650
6651 /* map all of the rings to the q_vectors */
6652 i40e_vsi_map_rings_to_vectors(vsi);
6653
6654 i40e_vsi_reset_stats(vsi);
6655 break;
6656
6657 default:
6658 /* no netdev or rings for the other VSI types */
6659 break;
6660 }
6661
6662 return vsi;
6663
6664err_rings:
6665 i40e_vsi_free_q_vectors(vsi);
6666err_msix:
6667 if (vsi->netdev_registered) {
6668 vsi->netdev_registered = false;
6669 unregister_netdev(vsi->netdev);
6670 free_netdev(vsi->netdev);
6671 vsi->netdev = NULL;
6672 }
6673err_netdev:
6674 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6675err_vsi:
6676 i40e_vsi_clear(vsi);
6677err_alloc:
6678 return NULL;
6679}
6680
6681/**
6682 * i40e_veb_get_bw_info - Query VEB BW information
6683 * @veb: the veb to query
6684 *
6685 * Query the Tx scheduler BW configuration data for given VEB
6686 **/
6687static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6688{
6689 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6690 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6691 struct i40e_pf *pf = veb->pf;
6692 struct i40e_hw *hw = &pf->hw;
6693 u32 tc_bw_max;
6694 int ret = 0;
6695 int i;
6696
6697 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6698 &bw_data, NULL);
6699 if (ret) {
6700 dev_info(&pf->pdev->dev,
6701 "query veb bw config failed, aq_err=%d\n",
6702 hw->aq.asq_last_status);
6703 goto out;
6704 }
6705
6706 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6707 &ets_data, NULL);
6708 if (ret) {
6709 dev_info(&pf->pdev->dev,
6710 "query veb bw ets config failed, aq_err=%d\n",
6711 hw->aq.asq_last_status);
6712 goto out;
6713 }
6714
6715 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6716 veb->bw_max_quanta = ets_data.tc_bw_max;
6717 veb->is_abs_credits = bw_data.absolute_credits_enable;
6718 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6719 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6720 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6721 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6722 veb->bw_tc_limit_credits[i] =
6723 le16_to_cpu(bw_data.tc_bw_limits[i]);
6724 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6725 }
6726
6727out:
6728 return ret;
6729}
6730
6731/**
6732 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6733 * @pf: board private structure
6734 *
6735 * On error: returns error code (negative)
6736 * On success: returns vsi index in PF (positive)
6737 **/
6738static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6739{
6740 int ret = -ENOENT;
6741 struct i40e_veb *veb;
6742 int i;
6743
6744 /* Need to protect the allocation of switch elements at the PF level */
6745 mutex_lock(&pf->switch_mutex);
6746
6747 /* VEB list may be fragmented if VEB creation/destruction has
6748 * been happening. We can afford to do a quick scan to look
6749 * for any free slots in the list.
6750 *
6751 * find next empty veb slot, looping back around if necessary
6752 */
6753 i = 0;
6754 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6755 i++;
6756 if (i >= I40E_MAX_VEB) {
6757 ret = -ENOMEM;
6758 goto err_alloc_veb; /* out of VEB slots! */
6759 }
6760
6761 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6762 if (!veb) {
6763 ret = -ENOMEM;
6764 goto err_alloc_veb;
6765 }
6766 veb->pf = pf;
6767 veb->idx = i;
6768 veb->enabled_tc = 1;
6769
6770 pf->veb[i] = veb;
6771 ret = i;
6772err_alloc_veb:
6773 mutex_unlock(&pf->switch_mutex);
6774 return ret;
6775}
6776
6777/**
6778 * i40e_switch_branch_release - Delete a branch of the switch tree
6779 * @branch: where to start deleting
6780 *
6781 * This uses recursion to find the tips of the branch to be
6782 * removed, deleting until we get back to and can delete this VEB.
6783 **/
6784static void i40e_switch_branch_release(struct i40e_veb *branch)
6785{
6786 struct i40e_pf *pf = branch->pf;
6787 u16 branch_seid = branch->seid;
6788 u16 veb_idx = branch->idx;
6789 int i;
6790
6791 /* release any VEBs on this VEB - RECURSION */
6792 for (i = 0; i < I40E_MAX_VEB; i++) {
6793 if (!pf->veb[i])
6794 continue;
6795 if (pf->veb[i]->uplink_seid == branch->seid)
6796 i40e_switch_branch_release(pf->veb[i]);
6797 }
6798
6799 /* Release the VSIs on this VEB, but not the owner VSI.
6800 *
6801 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6802 * the VEB itself, so don't use (*branch) after this loop.
6803 */
6804 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6805 if (!pf->vsi[i])
6806 continue;
6807 if (pf->vsi[i]->uplink_seid == branch_seid &&
6808 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6809 i40e_vsi_release(pf->vsi[i]);
6810 }
6811 }
6812
6813 /* There's one corner case where the VEB might not have been
6814 * removed, so double check it here and remove it if needed.
6815 * This case happens if the veb was created from the debugfs
6816 * commands and no VSIs were added to it.
6817 */
6818 if (pf->veb[veb_idx])
6819 i40e_veb_release(pf->veb[veb_idx]);
6820}
6821
6822/**
6823 * i40e_veb_clear - remove veb struct
6824 * @veb: the veb to remove
6825 **/
6826static void i40e_veb_clear(struct i40e_veb *veb)
6827{
6828 if (!veb)
6829 return;
6830
6831 if (veb->pf) {
6832 struct i40e_pf *pf = veb->pf;
6833
6834 mutex_lock(&pf->switch_mutex);
6835 if (pf->veb[veb->idx] == veb)
6836 pf->veb[veb->idx] = NULL;
6837 mutex_unlock(&pf->switch_mutex);
6838 }
6839
6840 kfree(veb);
6841}
6842
6843/**
6844 * i40e_veb_release - Delete a VEB and free its resources
6845 * @veb: the VEB being removed
6846 **/
6847void i40e_veb_release(struct i40e_veb *veb)
6848{
6849 struct i40e_vsi *vsi = NULL;
6850 struct i40e_pf *pf;
6851 int i, n = 0;
6852
6853 pf = veb->pf;
6854
6855 /* find the remaining VSI and check for extras */
6856 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6857 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6858 n++;
6859 vsi = pf->vsi[i];
6860 }
6861 }
6862 if (n != 1) {
6863 dev_info(&pf->pdev->dev,
6864 "can't remove VEB %d with %d VSIs left\n",
6865 veb->seid, n);
6866 return;
6867 }
6868
6869 /* move the remaining VSI to uplink veb */
6870 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6871 if (veb->uplink_seid) {
6872 vsi->uplink_seid = veb->uplink_seid;
6873 if (veb->uplink_seid == pf->mac_seid)
6874 vsi->veb_idx = I40E_NO_VEB;
6875 else
6876 vsi->veb_idx = veb->veb_idx;
6877 } else {
6878 /* floating VEB */
6879 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6880 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6881 }
6882
6883 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6884 i40e_veb_clear(veb);
6885
6886 return;
6887}
6888
6889/**
6890 * i40e_add_veb - create the VEB in the switch
6891 * @veb: the VEB to be instantiated
6892 * @vsi: the controlling VSI
6893 **/
6894static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6895{
56747264 6896 bool is_default = false;
e1c51b95 6897 bool is_cloud = false;
41c445ff
JB		 6898 int ret;
6899
6900 /* get a VEB from the hardware */
6901 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6902 veb->enabled_tc, is_default,
6903 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6904 if (ret) {
6905 dev_info(&veb->pf->pdev->dev,
6906 "couldn't add VEB, err %d, aq_err %d\n",
6907 ret, veb->pf->hw.aq.asq_last_status);
6908 return -EPERM;
6909 }
6910
6911 /* get statistics counter */
6912 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6913 &veb->stats_idx, NULL, NULL, NULL);
6914 if (ret) {
6915 dev_info(&veb->pf->pdev->dev,
6916 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6917 ret, veb->pf->hw.aq.asq_last_status);
6918 return -EPERM;
6919 }
6920 ret = i40e_veb_get_bw_info(veb);
6921 if (ret) {
6922 dev_info(&veb->pf->pdev->dev,
6923 "couldn't get VEB bw info, err %d, aq_err %d\n",
6924 ret, veb->pf->hw.aq.asq_last_status);
6925 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6926 return -ENOENT;
6927 }
6928
6929 vsi->uplink_seid = veb->seid;
6930 vsi->veb_idx = veb->idx;
6931 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6932
6933 return 0;
6934}
6935
6936/**
6937 * i40e_veb_setup - Set up a VEB
6938 * @pf: board private structure
6939 * @flags: VEB setup flags
6940 * @uplink_seid: the switch element to link to
6941 * @vsi_seid: the initial VSI seid
6942 * @enabled_tc: Enabled TC bit-map
6943 *
6944 * This allocates the sw VEB structure and links it into the switch
6945 * It is possible and legal for this to be a duplicate of an already
6946 * existing VEB. It is also possible for both uplink and vsi seids
6947 * to be zero, in order to create a floating VEB.
6948 *
6949 * Returns pointer to the successfully allocated VEB sw struct on
6950 * success, otherwise returns NULL on failure.
6951 **/
6952struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6953 u16 uplink_seid, u16 vsi_seid,
6954 u8 enabled_tc)
6955{
6956 struct i40e_veb *veb, *uplink_veb = NULL;
6957 int vsi_idx, veb_idx;
6958 int ret;
6959
6960 /* if one seid is 0, the other must be 0 to create a floating relay */
6961 if ((uplink_seid == 0 || vsi_seid == 0) &&
6962 (uplink_seid + vsi_seid != 0)) {
6963 dev_info(&pf->pdev->dev,
6964 "one, not both seid's are 0: uplink=%d vsi=%d\n",
6965 uplink_seid, vsi_seid);
6966 return NULL;
6967 }
6968
6969 /* make sure there is such a vsi and uplink */
6970 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
6971 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
6972 break;
6973 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
6974 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
6975 vsi_seid);
6976 return NULL;
6977 }
6978
6979 if (uplink_seid && uplink_seid != pf->mac_seid) {
6980 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6981 if (pf->veb[veb_idx] &&
6982 pf->veb[veb_idx]->seid == uplink_seid) {
6983 uplink_veb = pf->veb[veb_idx];
6984 break;
6985 }
6986 }
6987 if (!uplink_veb) {
6988 dev_info(&pf->pdev->dev,
6989 "uplink seid %d not found\n", uplink_seid);
6990 return NULL;
6991 }
6992 }
6993
6994 /* get veb sw struct */
6995 veb_idx = i40e_veb_mem_alloc(pf);
6996 if (veb_idx < 0)
6997 goto err_alloc;
6998 veb = pf->veb[veb_idx];
6999 veb->flags = flags;
7000 veb->uplink_seid = uplink_seid;
7001 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7002 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7003
7004 /* create the VEB in the switch */
7005 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7006 if (ret)
7007 goto err_veb;
7008
7009 return veb;
7010
7011err_veb:
7012 i40e_veb_clear(veb);
7013err_alloc:
7014 return NULL;
7015}
7016
7017/**
7018 * i40e_setup_pf_switch_element - set pf vars based on switch type
7019 * @pf: board private structure
7020 * @ele: element we are building info from
7021 * @num_reported: total number of elements
7022 * @printconfig: should we print the contents
7023 *
7024 * helper function to assist in extracting a few useful SEID values.
7025 **/
7026static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7027 struct i40e_aqc_switch_config_element_resp *ele,
7028 u16 num_reported, bool printconfig)
7029{
7030 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7031 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7032 u8 element_type = ele->element_type;
7033 u16 seid = le16_to_cpu(ele->seid);
7034
7035 if (printconfig)
7036 dev_info(&pf->pdev->dev,
7037 "type=%d seid=%d uplink=%d downlink=%d\n",
7038 element_type, seid, uplink_seid, downlink_seid);
7039
7040 switch (element_type) {
7041 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7042 pf->mac_seid = seid;
7043 break;
7044 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7045 /* Main VEB? */
7046 if (uplink_seid != pf->mac_seid)
7047 break;
7048 if (pf->lan_veb == I40E_NO_VEB) {
7049 int v;
7050
7051 /* find existing or else empty VEB */
7052 for (v = 0; v < I40E_MAX_VEB; v++) {
7053 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7054 pf->lan_veb = v;
7055 break;
7056 }
7057 }
7058 if (pf->lan_veb == I40E_NO_VEB) {
7059 v = i40e_veb_mem_alloc(pf);
7060 if (v < 0)
7061 break;
7062 pf->lan_veb = v;
7063 }
7064 }
7065
7066 pf->veb[pf->lan_veb]->seid = seid;
7067 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7068 pf->veb[pf->lan_veb]->pf = pf;
7069 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7070 break;
7071 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7072 if (num_reported != 1)
7073 break;
7074 /* This is immediately after a reset so we can assume this is
7075 * the PF's VSI
7076 */
7077 pf->mac_seid = uplink_seid;
7078 pf->pf_seid = downlink_seid;
7079 pf->main_vsi_seid = seid;
7080 if (printconfig)
7081 dev_info(&pf->pdev->dev,
7082 "pf_seid=%d main_vsi_seid=%d\n",
7083 pf->pf_seid, pf->main_vsi_seid);
7084 break;
7085 case I40E_SWITCH_ELEMENT_TYPE_PF:
7086 case I40E_SWITCH_ELEMENT_TYPE_VF:
7087 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7088 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7089 case I40E_SWITCH_ELEMENT_TYPE_PE:
7090 case I40E_SWITCH_ELEMENT_TYPE_PA:
7091 /* ignore these for now */
7092 break;
7093 default:
7094 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7095 element_type, seid);
7096 break;
7097 }
7098}
7099
7100/**
7101 * i40e_fetch_switch_configuration - Get switch config from firmware
7102 * @pf: board private structure
7103 * @printconfig: should we print the contents
7104 *
7105 * Get the current switch configuration from the device and
7106 * extract a few useful SEID values.
7107 **/
7108int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7109{
7110 struct i40e_aqc_get_switch_config_resp *sw_config;
7111 u16 next_seid = 0;
7112 int ret = 0;
7113 u8 *aq_buf;
7114 int i;
7115
7116 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7117 if (!aq_buf)
7118 return -ENOMEM;
7119
7120 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7121 do {
7122 u16 num_reported, num_total;
7123
7124 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7125 I40E_AQ_LARGE_BUF,
7126 &next_seid, NULL);
7127 if (ret) {
7128 dev_info(&pf->pdev->dev,
7129 "get switch config failed %d aq_err=%x\n",
7130 ret, pf->hw.aq.asq_last_status);
7131 kfree(aq_buf);
7132 return -ENOENT;
7133 }
7134
7135 num_reported = le16_to_cpu(sw_config->header.num_reported);
7136 num_total = le16_to_cpu(sw_config->header.num_total);
7137
7138 if (printconfig)
7139 dev_info(&pf->pdev->dev,
7140 "header: %d reported %d total\n",
7141 num_reported, num_total);
7142
7143 if (num_reported) {
7144 int sz = sizeof(*sw_config) * num_reported;
7145
7146 kfree(pf->sw_config);
7147 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7148 if (pf->sw_config)
7149 memcpy(pf->sw_config, sw_config, sz);
7150 }
7151
7152 for (i = 0; i < num_reported; i++) {
7153 struct i40e_aqc_switch_config_element_resp *ele =
7154 &sw_config->element[i];
7155
7156 i40e_setup_pf_switch_element(pf, ele, num_reported,
7157 printconfig);
7158 }
7159 } while (next_seid != 0);
7160
7161 kfree(aq_buf);
7162 return ret;
7163}
7164
7165/**
7166 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7167 * @pf: board private structure
bc7d338f 7168 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7169 *
7170 * Returns 0 on success, negative value on failure
7171 **/
bc7d338f 7172static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7173{
895106a5 7174 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7175 int ret;
7176
7177 /* find out what's out there already */
7178 ret = i40e_fetch_switch_configuration(pf, false);
7179 if (ret) {
7180 dev_info(&pf->pdev->dev,
7181 "couldn't fetch switch config, err %d, aq_err %d\n",
7182 ret, pf->hw.aq.asq_last_status);
7183 return ret;
7184 }
7185 i40e_pf_reset_stats(pf);
7186
7187 /* fdir VSI must happen first to be sure it gets queue 0, but only
7188 * if there is enough room for the fdir VSI
7189 */
7190 if (pf->num_lan_qps > 1)
7191 i40e_fdir_setup(pf);
7192
7193 /* first time setup */
bc7d338f 7194 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7195 struct i40e_vsi *vsi = NULL;
7196 u16 uplink_seid;
7197
7198 /* Set up the PF VSI associated with the PF's main VSI
7199 * that is already in the HW switch
7200 */
7201 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7202 uplink_seid = pf->veb[pf->lan_veb]->seid;
7203 else
7204 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7205 if (pf->lan_vsi == I40E_NO_VSI)
7206 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7207 else if (reinit)
7208 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7209 if (!vsi) {
7210 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7211 i40e_fdir_teardown(pf);
7212 return -EAGAIN;
7213 }
41c445ff
JB		 7214 } else {
7215 /* force a reset of TC and queue layout configurations */
7216 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7217 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7218 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7219 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7220 }
7221 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7222
7223 /* Setup static PF queue filter control settings */
7224 ret = i40e_setup_pf_filter_control(pf);
7225 if (ret) {
7226 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7227 ret);
7228 /* Failure here should not stop continuing other steps */
7229 }
7230
7231 /* enable RSS in the HW, even for only one queue, as the stack can use
7232 * the hash
7233 */
7234 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7235 i40e_config_rss(pf);
7236
7237 /* fill in link information and enable LSE reporting */
7238 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7239 i40e_link_event(pf);
7240
d52c20b7 7241 /* Initialize user-specific link properties */
41c445ff
JB		 7242 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7243 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7244 /* requested_mode is set in probe or by ethtool */
7245 if (!pf->fc_autoneg_status)
7246 goto no_autoneg;
7247
7248 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7249 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7250 pf->hw.fc.current_mode = I40E_FC_FULL;
7251 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7252 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7253 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7254 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7255 else
d52c20b7
JB		 7256 pf->hw.fc.current_mode = I40E_FC_NONE;
7257
7258 /* sync the flow control settings with the auto-neg values */
7259 switch (pf->hw.fc.current_mode) {
7260 case I40E_FC_FULL:
7261 txfc = 1;
7262 rxfc = 1;
7263 break;
7264 case I40E_FC_TX_PAUSE:
7265 txfc = 1;
7266 rxfc = 0;
7267 break;
7268 case I40E_FC_RX_PAUSE:
7269 txfc = 0;
7270 rxfc = 1;
7271 break;
7272 case I40E_FC_NONE:
7273 case I40E_FC_DEFAULT:
7274 txfc = 0;
7275 rxfc = 0;
7276 break;
7277 case I40E_FC_PFC:
7278 /* TBD */
7279 break;
7280 /* no default case, we have to handle all possibilities here */
7281 }
7282
7283 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7284
7285 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7286 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7287 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7288
7289 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7290
d52c20b7
JB		 7291 goto fc_complete;
7292
7293no_autoneg:
7294 /* disable L2 flow control, user can turn it on if they wish */
7295 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7296 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7297 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7298
7299fc_complete:
41c445ff
JB		 7300 return ret;
7301}
7302
7303/**
7304 * i40e_set_rss_size - helper to set rss_size
7305 * @pf: board private structure
7306 * @queues_left: how many queues
7307 */
7308static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7309{
7310 int num_tc0;
7311
7312 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7313 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7314 num_tc0 = rounddown_pow_of_two(num_tc0);
7315
7316 return num_tc0;
7317}
7318
7319/**
7320 * i40e_determine_queue_usage - Work out queue distribution
7321 * @pf: board private structure
7322 **/
7323static void i40e_determine_queue_usage(struct i40e_pf *pf)
7324{
7325 int accum_tc_size;
7326 int queues_left;
7327
7328 pf->num_lan_qps = 0;
7329 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7330 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7331
7332 /* Find the max queues to be put into basic use. We'll always be
7333 * using TC0, whether or not DCB is running, and TC0 will get the
7334 * big RSS set.
7335 */
7336 queues_left = pf->hw.func_caps.num_tx_qp;
7337
9f52987b 7338 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
41c445ff
JB		 7339 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7340 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7341 (queues_left == 1)) {
7342
7343 /* one qp for PF, no queues for anything else */
7344 queues_left = 0;
7345 pf->rss_size = pf->num_lan_qps = 1;
7346
7347 /* make sure all the fancies are disabled */
7348 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 7349 I40E_FLAG_FDIR_ENABLED |
7350 I40E_FLAG_FDIR_ATR_ENABLED |
7351 I40E_FLAG_DCB_ENABLED |
7352 I40E_FLAG_SRIOV_ENABLED |
7353 I40E_FLAG_VMDQ_ENABLED);
7354
7355 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7356 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7357 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7358
7359 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7360
7361 queues_left -= pf->rss_size;
f8ff1464 7362 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7363
7364 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7365 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7366 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7367
7368 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7369 * are set up for RSS in TC0
7370 */
7371 queues_left -= accum_tc_size;
7372
7373 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7374
7375 queues_left -= pf->rss_size;
7376 if (queues_left < 0) {
7377 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7378 return;
7379 }
7380
f8ff1464 7381 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7382
7383 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7384 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7385 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7386
7387 queues_left -= 1; /* save 1 queue for FD */
7388
7389 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7390
7391 queues_left -= pf->rss_size;
7392 if (queues_left < 0) {
7393 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7394 return;
7395 }
7396
f8ff1464 7397 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7398
7399 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7400 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7401 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7402
7403 /* save 1 queue for TCs 1 thru 7,
7404 * 1 queue for flow director,
7405 * and the rest are set up for RSS in TC0
7406 */
7407 queues_left -= 1;
7408 queues_left -= accum_tc_size;
7409
7410 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7411 queues_left -= pf->rss_size;
7412 if (queues_left < 0) {
7413 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7414 return;
7415 }
7416
f8ff1464 7417 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7418
7419 } else {
7420 dev_info(&pf->pdev->dev,
7421 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7422 return;
7423 }
7424
7425 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7426 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7427 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7428 pf->num_vf_qps));
7429 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7430 }
7431
7432 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7433 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7434 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7435 (queues_left / pf->num_vmdq_qps));
7436 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7437 }
7438
f8ff1464 7439 pf->queues_left = queues_left;
41c445ff
JB		 7440 return;
7441}
7442
7443/**
7444 * i40e_setup_pf_filter_control - Setup PF static filter control
7445 * @pf: PF to be setup
7446 *
7447 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7448 * settings. If PE/FCoE are enabled then it will also set the per PF
7449 * based filter sizes required for them. It also enables Flow director,
7450 * ethertype and macvlan type filter settings for the pf.
7451 *
7452 * Returns 0 on success, negative on failure
7453 **/
7454static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7455{
7456 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7457
7458 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7459
7460 /* Flow Director is enabled */
7461 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7462 settings->enable_fdir = true;
7463
7464 /* Ethtype and MACVLAN filters enabled for PF */
7465 settings->enable_ethtype = true;
7466 settings->enable_macvlan = true;
7467
7468 if (i40e_set_filter_control(&pf->hw, settings))
7469 return -ENOENT;
7470
7471 return 0;
7472}
7473
7474/**
7475 * i40e_probe - Device initialization routine
7476 * @pdev: PCI device information struct
7477 * @ent: entry in i40e_pci_tbl
7478 *
7479 * i40e_probe initializes a pf identified by a pci_dev structure.
7480 * The OS initialization, configuring of the pf private structure,
7481 * and a hardware reset occur.
7482 *
7483 * Returns 0 on success, negative on failure
7484 **/
7485static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7486{
7487 struct i40e_driver_version dv;
7488 struct i40e_pf *pf;
7489 struct i40e_hw *hw;
93cd765b 7490 static u16 pfs_found;
d4dfb81a 7491 u16 link_status;
41c445ff
JB		 7492 int err = 0;
7493 u32 len;
7494
7495 err = pci_enable_device_mem(pdev);
7496 if (err)
7497 return err;
7498
7499 /* set up for high or low dma */
7500 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7501 /* coherent mask for the same size will always succeed if
7502 * dma_set_mask does
7503 */
7504 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7505 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7506 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7507 } else {
7508 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7509 err = -EIO;
7510 goto err_dma;
7511 }
7512
7513 /* set up pci connections */
7514 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7515 IORESOURCE_MEM), i40e_driver_name);
7516 if (err) {
7517 dev_info(&pdev->dev,
7518 "pci_request_selected_regions failed %d\n", err);
7519 goto err_pci_reg;
7520 }
7521
7522 pci_enable_pcie_error_reporting(pdev);
7523 pci_set_master(pdev);
7524
7525 /* Now that we have a PCI connection, we need to do the
7526 * low level device setup. This is primarily setting up
7527 * the Admin Queue structures and then querying for the
7528 * device's current profile information.
7529 */
7530 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7531 if (!pf) {
7532 err = -ENOMEM;
7533 goto err_pf_alloc;
7534 }
7535 pf->next_vsi = 0;
7536 pf->pdev = pdev;
7537 set_bit(__I40E_DOWN, &pf->state);
7538
7539 hw = &pf->hw;
7540 hw->back = pf;
7541 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7542 pci_resource_len(pdev, 0));
7543 if (!hw->hw_addr) {
7544 err = -EIO;
7545 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7546 (unsigned int)pci_resource_start(pdev, 0),
7547 (unsigned int)pci_resource_len(pdev, 0), err);
7548 goto err_ioremap;
7549 }
7550 hw->vendor_id = pdev->vendor;
7551 hw->device_id = pdev->device;
7552 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7553 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7554 hw->subsystem_device_id = pdev->subsystem_device;
7555 hw->bus.device = PCI_SLOT(pdev->devfn);
7556 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7557 pf->instance = pfs_found;
41c445ff 7558
7134f9ce
JB		 7559 /* do a special CORER for clearing PXE mode once at init */
7560 if (hw->revision_id == 0 &&
7561 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7562 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7563 i40e_flush(hw);
7564 msleep(200);
7565 pf->corer_count++;
7566
7567 i40e_clear_pxe_mode(hw);
7568 }
7569
41c445ff
JB		 7570 /* Reset here to make sure all is clean and to define PF 'n' */
7571 err = i40e_pf_reset(hw);
7572 if (err) {
7573 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7574 goto err_pf_reset;
7575 }
7576 pf->pfr_count++;
7577
7578 hw->aq.num_arq_entries = I40E_AQ_LEN;
7579 hw->aq.num_asq_entries = I40E_AQ_LEN;
7580 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7581 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7582 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7583 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7584 "%s-pf%d:misc",
7585 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7586
7587 err = i40e_init_shared_code(hw);
7588 if (err) {
7589 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7590 goto err_pf_reset;
7591 }
7592
d52c20b7
JB		 7593 /* set up a default setting for link flow control */
7594 pf->hw.fc.requested_mode = I40E_FC_NONE;
7595
41c445ff
JB		 7596 err = i40e_init_adminq(hw);
7597 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7598 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7599 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7600 dev_info(&pdev->dev,
7601 "warning: NVM version not supported, supported version: %02x.%02x\n",
7602 I40E_CURRENT_NVM_VERSION_HI,
7603 I40E_CURRENT_NVM_VERSION_LO);
7604 }
41c445ff
JB		 7605 if (err) {
7606 dev_info(&pdev->dev,
7607 "init_adminq failed: %d expecting API %02x.%02x\n",
7608 err,
7609 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7610 goto err_pf_reset;
7611 }
7612
7613 err = i40e_get_capabilities(pf);
7614 if (err)
7615 goto err_adminq_setup;
7616
7617 err = i40e_sw_init(pf);
7618 if (err) {
7619 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7620 goto err_sw_init;
7621 }
7622
7623 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7624 hw->func_caps.num_rx_qp,
7625 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7626 if (err) {
7627 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7628 goto err_init_lan_hmc;
7629 }
7630
7631 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7632 if (err) {
7633 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7634 err = -ENOENT;
7635 goto err_configure_lan_hmc;
7636 }
7637
7638 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7639 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7640 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7641 err = -EIO;
7642 goto err_mac_addr;
7643 }
7644 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7645 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7646
7647 pci_set_drvdata(pdev, pf);
7648 pci_save_state(pdev);
7649
7650 /* set up periodic task facility */
7651 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7652 pf->service_timer_period = HZ;
7653
7654 INIT_WORK(&pf->service_task, i40e_service_task);
7655 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7656 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7657 pf->link_check_timeout = jiffies;
7658
8e2773ae
SN		 7659 /* WoL defaults to disabled */
7660 pf->wol_en = false;
7661 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7662
41c445ff
JB		 7663 /* set up the main switch operations */
7664 i40e_determine_queue_usage(pf);
7665 i40e_init_interrupt_scheme(pf);
7666
7667 /* Set up the *vsi struct based on the number of VSIs in the HW,
7668 * and set up our local tracking of the MAIN PF vsi.
7669 */
7670 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7671 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7672 if (!pf->vsi) {
7673 err = -ENOMEM;
41c445ff 7674 goto err_switch_setup;
ed87ac09 7675 }
41c445ff 7676
bc7d338f 7677 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7678 if (err) {
7679 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7680 goto err_vsis;
7681 }
7682
7683 /* The main driver is (mostly) up and happy. We need to set this state
7684 * before setting up the misc vector or we get a race and the vector
7685 * ends up disabled forever.
7686 */
7687 clear_bit(__I40E_DOWN, &pf->state);
7688
7689 /* In case of MSIX we are going to setup the misc vector right here
7690 * to handle admin queue events etc. In case of legacy and MSI
7691 * the misc functionality and queue processing is combined in
7692 * the same vector and that gets setup at open.
7693 */
7694 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7695 err = i40e_setup_misc_vector(pf);
7696 if (err) {
7697 dev_info(&pdev->dev,
7698 "setup of misc vector failed: %d\n", err);
7699 goto err_vsis;
7700 }
7701 }
7702
7703 /* prep for VF support */
7704 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7705 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7706 u32 val;
7707
7708 /* disable link interrupts for VFs */
7709 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7710 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7711 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7712 i40e_flush(hw);
7713 }
7714
93cd765b
ASJ		 7715 pfs_found++;
7716
41c445ff
JB		 7717 i40e_dbg_pf_init(pf);
7718
7719 /* tell the firmware that we're starting */
7720 dv.major_version = DRV_VERSION_MAJOR;
7721 dv.minor_version = DRV_VERSION_MINOR;
7722 dv.build_version = DRV_VERSION_BUILD;
7723 dv.subbuild_version = 0;
7724 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7725
7726 /* since everything's happy, start the service_task timer */
7727 mod_timer(&pf->service_timer,
7728 round_jiffies(jiffies + pf->service_timer_period));
7729
d4dfb81a
CS		 7730 /* Get the negotiated link width and speed from PCI config space */
7731 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7732
7733 i40e_set_pci_config_data(hw, link_status);
7734
7735 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7736 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7737 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7738 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7739 "Unknown"),
7740 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7741 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7742 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7743 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7744 "Unknown"));
7745
7746 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7747 hw->bus.speed < i40e_bus_speed_8000) {
7748 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7749 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7750 }
7751
41c445ff
JB		 7752 return 0;
7753
7754 /* Unwind what we've done if something failed in the setup */
7755err_vsis:
7756 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 7757 i40e_clear_interrupt_scheme(pf);
7758 kfree(pf->vsi);
04b03013
SN		 7759err_switch_setup:
7760 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 7761 del_timer_sync(&pf->service_timer);
7762err_mac_addr:
7763err_configure_lan_hmc:
7764 (void)i40e_shutdown_lan_hmc(hw);
7765err_init_lan_hmc:
7766 kfree(pf->qp_pile);
7767 kfree(pf->irq_pile);
7768err_sw_init:
7769err_adminq_setup:
7770 (void)i40e_shutdown_adminq(hw);
7771err_pf_reset:
7772 iounmap(hw->hw_addr);
7773err_ioremap:
7774 kfree(pf);
7775err_pf_alloc:
7776 pci_disable_pcie_error_reporting(pdev);
7777 pci_release_selected_regions(pdev,
7778 pci_select_bars(pdev, IORESOURCE_MEM));
7779err_pci_reg:
7780err_dma:
7781 pci_disable_device(pdev);
7782 return err;
7783}
7784
7785/**
7786 * i40e_remove - Device removal routine
7787 * @pdev: PCI device information struct
7788 *
7789 * i40e_remove is called by the PCI subsystem to alert the driver
7790 * that is should release a PCI device. This could be caused by a
7791 * Hot-Plug event, or because the driver is going to be removed from
7792 * memory.
7793 **/
7794static void i40e_remove(struct pci_dev *pdev)
7795{
7796 struct i40e_pf *pf = pci_get_drvdata(pdev);
7797 i40e_status ret_code;
7798 u32 reg;
7799 int i;
7800
7801 i40e_dbg_pf_exit(pf);
7802
7803 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7804 i40e_free_vfs(pf);
7805 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7806 }
7807
7808 /* no more scheduling of any task */
7809 set_bit(__I40E_DOWN, &pf->state);
7810 del_timer_sync(&pf->service_timer);
7811 cancel_work_sync(&pf->service_task);
7812
7813 i40e_fdir_teardown(pf);
7814
7815 /* If there is a switch structure or any orphans, remove them.
7816 * This will leave only the PF's VSI remaining.
7817 */
7818 for (i = 0; i < I40E_MAX_VEB; i++) {
7819 if (!pf->veb[i])
7820 continue;
7821
7822 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7823 pf->veb[i]->uplink_seid == 0)
7824 i40e_switch_branch_release(pf->veb[i]);
7825 }
7826
7827 /* Now we can shutdown the PF's VSI, just before we kill
7828 * adminq and hmc.
7829 */
7830 if (pf->vsi[pf->lan_vsi])
7831 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7832
7833 i40e_stop_misc_vector(pf);
7834 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7835 synchronize_irq(pf->msix_entries[0].vector);
7836 free_irq(pf->msix_entries[0].vector, pf);
7837 }
7838
7839 /* shutdown and destroy the HMC */
7840 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7841 if (ret_code)
7842 dev_warn(&pdev->dev,
7843 "Failed to destroy the HMC resources: %d\n", ret_code);
7844
7845 /* shutdown the adminq */
41c445ff
JB		 7846 ret_code = i40e_shutdown_adminq(&pf->hw);
7847 if (ret_code)
7848 dev_warn(&pdev->dev,
7849 "Failed to destroy the Admin Queue resources: %d\n",
7850 ret_code);
7851
7852 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7853 i40e_clear_interrupt_scheme(pf);
7854 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7855 if (pf->vsi[i]) {
7856 i40e_vsi_clear_rings(pf->vsi[i]);
7857 i40e_vsi_clear(pf->vsi[i]);
7858 pf->vsi[i] = NULL;
7859 }
7860 }
7861
7862 for (i = 0; i < I40E_MAX_VEB; i++) {
7863 kfree(pf->veb[i]);
7864 pf->veb[i] = NULL;
7865 }
7866
7867 kfree(pf->qp_pile);
7868 kfree(pf->irq_pile);
7869 kfree(pf->sw_config);
7870 kfree(pf->vsi);
7871
7872 /* force a PF reset to clean anything leftover */
7873 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7874 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7875 i40e_flush(&pf->hw);
7876
7877 iounmap(pf->hw.hw_addr);
7878 kfree(pf);
7879 pci_release_selected_regions(pdev,
7880 pci_select_bars(pdev, IORESOURCE_MEM));
7881
7882 pci_disable_pcie_error_reporting(pdev);
7883 pci_disable_device(pdev);
7884}
7885
7886/**
7887 * i40e_pci_error_detected - warning that something funky happened in PCI land
7888 * @pdev: PCI device information struct
7889 *
7890 * Called to warn that something happened and the error handling steps
7891 * are in progress. Allows the driver to quiesce things, be ready for
7892 * remediation.
7893 **/
7894static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7895 enum pci_channel_state error)
7896{
7897 struct i40e_pf *pf = pci_get_drvdata(pdev);
7898
7899 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7900
7901 /* shutdown all operations */
9007bccd
SN		 7902 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7903 rtnl_lock();
7904 i40e_prep_for_reset(pf);
7905 rtnl_unlock();
7906 }
41c445ff
JB		 7907
7908 /* Request a slot reset */
7909 return PCI_ERS_RESULT_NEED_RESET;
7910}
7911
7912/**
7913 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7914 * @pdev: PCI device information struct
7915 *
7916 * Called to find if the driver can work with the device now that
7917 * the pci slot has been reset. If a basic connection seems good
7918 * (registers are readable and have sane content) then return a
7919 * happy little PCI_ERS_RESULT_xxx.
7920 **/
7921static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7922{
7923 struct i40e_pf *pf = pci_get_drvdata(pdev);
7924 pci_ers_result_t result;
7925 int err;
7926 u32 reg;
7927
7928 dev_info(&pdev->dev, "%s\n", __func__);
7929 if (pci_enable_device_mem(pdev)) {
7930 dev_info(&pdev->dev,
7931 "Cannot re-enable PCI device after reset.\n");
7932 result = PCI_ERS_RESULT_DISCONNECT;
7933 } else {
7934 pci_set_master(pdev);
7935 pci_restore_state(pdev);
7936 pci_save_state(pdev);
7937 pci_wake_from_d3(pdev, false);
7938
7939 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7940 if (reg == 0)
7941 result = PCI_ERS_RESULT_RECOVERED;
7942 else
7943 result = PCI_ERS_RESULT_DISCONNECT;
7944 }
7945
7946 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7947 if (err) {
7948 dev_info(&pdev->dev,
7949 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7950 err);
7951 /* non-fatal, continue */
7952 }
7953
7954 return result;
7955}
7956
7957/**
7958 * i40e_pci_error_resume - restart operations after PCI error recovery
7959 * @pdev: PCI device information struct
7960 *
7961 * Called to allow the driver to bring things back up after PCI error
7962 * and/or reset recovery has finished.
7963 **/
7964static void i40e_pci_error_resume(struct pci_dev *pdev)
7965{
7966 struct i40e_pf *pf = pci_get_drvdata(pdev);
7967
7968 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 7969 if (test_bit(__I40E_SUSPENDED, &pf->state))
7970 return;
7971
7972 rtnl_lock();
41c445ff 7973 i40e_handle_reset_warning(pf);
9007bccd
SN		 7974 rtnl_lock();
7975}
7976
7977/**
7978 * i40e_shutdown - PCI callback for shutting down
7979 * @pdev: PCI device information struct
7980 **/
7981static void i40e_shutdown(struct pci_dev *pdev)
7982{
7983 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 7984 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 7985
7986 set_bit(__I40E_SUSPENDED, &pf->state);
7987 set_bit(__I40E_DOWN, &pf->state);
7988 rtnl_lock();
7989 i40e_prep_for_reset(pf);
7990 rtnl_unlock();
7991
8e2773ae
SN		 7992 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
7993 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
7994
9007bccd 7995 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 7996 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 7997 pci_set_power_state(pdev, PCI_D3hot);
7998 }
7999}
8000
8001#ifdef CONFIG_PM
8002/**
8003 * i40e_suspend - PCI callback for moving to D3
8004 * @pdev: PCI device information struct
8005 **/
8006static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8007{
8008 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8009 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8010
8011 set_bit(__I40E_SUSPENDED, &pf->state);
8012 set_bit(__I40E_DOWN, &pf->state);
8013 rtnl_lock();
8014 i40e_prep_for_reset(pf);
8015 rtnl_unlock();
8016
8e2773ae
SN		 8017 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8018 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8019
8020 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8021 pci_set_power_state(pdev, PCI_D3hot);
8022
8023 return 0;
41c445ff
JB		 8024}
8025
9007bccd
SN		 8026/**
8027 * i40e_resume - PCI callback for waking up from D3
8028 * @pdev: PCI device information struct
8029 **/
8030static int i40e_resume(struct pci_dev *pdev)
8031{
8032 struct i40e_pf *pf = pci_get_drvdata(pdev);
8033 u32 err;
8034
8035 pci_set_power_state(pdev, PCI_D0);
8036 pci_restore_state(pdev);
8037 /* pci_restore_state() clears dev->state_saves, so
8038 * call pci_save_state() again to restore it.
8039 */
8040 pci_save_state(pdev);
8041
8042 err = pci_enable_device_mem(pdev);
8043 if (err) {
8044 dev_err(&pdev->dev,
8045 "%s: Cannot enable PCI device from suspend\n",
8046 __func__);
8047 return err;
8048 }
8049 pci_set_master(pdev);
8050
8051 /* no wakeup events while running */
8052 pci_wake_from_d3(pdev, false);
8053
8054 /* handling the reset will rebuild the device state */
8055 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8056 clear_bit(__I40E_DOWN, &pf->state);
8057 rtnl_lock();
8058 i40e_reset_and_rebuild(pf, false);
8059 rtnl_unlock();
8060 }
8061
8062 return 0;
8063}
8064
8065#endif
41c445ff
JB		 8066static const struct pci_error_handlers i40e_err_handler = {
8067 .error_detected = i40e_pci_error_detected,
8068 .slot_reset = i40e_pci_error_slot_reset,
8069 .resume = i40e_pci_error_resume,
8070};
8071
8072static struct pci_driver i40e_driver = {
8073 .name = i40e_driver_name,
8074 .id_table = i40e_pci_tbl,
8075 .probe = i40e_probe,
8076 .remove = i40e_remove,
9007bccd
SN		 8077#ifdef CONFIG_PM
8078 .suspend = i40e_suspend,
8079 .resume = i40e_resume,
8080#endif
8081 .shutdown = i40e_shutdown,
41c445ff
JB		 8082 .err_handler = &i40e_err_handler,
8083 .sriov_configure = i40e_pci_sriov_configure,
8084};
8085
8086/**
8087 * i40e_init_module - Driver registration routine
8088 *
8089 * i40e_init_module is the first routine called when the driver is
8090 * loaded. All it does is register with the PCI subsystem.
8091 **/
8092static int __init i40e_init_module(void)
8093{
8094 pr_info("%s: %s - version %s\n", i40e_driver_name,
8095 i40e_driver_string, i40e_driver_version_str);
8096 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8097 i40e_dbg_init();
8098 return pci_register_driver(&i40e_driver);
8099}
8100module_init(i40e_init_module);
8101
8102/**
8103 * i40e_exit_module - Driver exit cleanup routine
8104 *
8105 * i40e_exit_module is called just before the driver is removed
8106 * from memory.
8107 **/
8108static void __exit i40e_exit_module(void)
8109{
8110 pci_unregister_driver(&i40e_driver);
8111 i40e_dbg_exit();
8112}
8113module_exit(i40e_exit_module);
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