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i40e: process link events when setting up switch
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db
CS		 40#define DRV_VERSION_MAJOR 1
41#define DRV_VERSION_MINOR 0
e966d5c6 42#define DRV_VERSION_BUILD 11
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
38e00438
VD		 272#ifdef I40E_FCOE
273void i40e_tx_timeout(struct net_device *netdev)
274#else
41c445ff 275static void i40e_tx_timeout(struct net_device *netdev)
38e00438 276#endif
41c445ff
JB		 277{
278 struct i40e_netdev_priv *np = netdev_priv(netdev);
279 struct i40e_vsi *vsi = np->vsi;
280 struct i40e_pf *pf = vsi->back;
281
282 pf->tx_timeout_count++;
283
284 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 285 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 286 pf->tx_timeout_last_recovery = jiffies;
287 netdev_info(netdev, "tx_timeout recovery level %d\n",
288 pf->tx_timeout_recovery_level);
289
290 switch (pf->tx_timeout_recovery_level) {
291 case 0:
292 /* disable and re-enable queues for the VSI */
293 if (in_interrupt()) {
294 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
295 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
296 } else {
297 i40e_vsi_reinit_locked(vsi);
298 }
299 break;
300 case 1:
301 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
302 break;
303 case 2:
304 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
305 break;
306 case 3:
307 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
308 break;
309 default:
310 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 311 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
312 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 313 break;
314 }
315 i40e_service_event_schedule(pf);
316 pf->tx_timeout_recovery_level++;
317}
318
319/**
320 * i40e_release_rx_desc - Store the new tail and head values
321 * @rx_ring: ring to bump
322 * @val: new head index
323 **/
324static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
325{
326 rx_ring->next_to_use = val;
327
328 /* Force memory writes to complete before letting h/w
329 * know there are new descriptors to fetch. (Only
330 * applicable for weak-ordered memory model archs,
331 * such as IA-64).
332 */
333 wmb();
334 writel(val, rx_ring->tail);
335}
336
337/**
338 * i40e_get_vsi_stats_struct - Get System Network Statistics
339 * @vsi: the VSI we care about
340 *
341 * Returns the address of the device statistics structure.
342 * The statistics are actually updated from the service task.
343 **/
344struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
345{
346 return &vsi->net_stats;
347}
348
349/**
350 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
351 * @netdev: network interface device structure
352 *
353 * Returns the address of the device statistics structure.
354 * The statistics are actually updated from the service task.
355 **/
38e00438
VD		 356#ifdef I40E_FCOE
357struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
358 struct net_device *netdev,
359 struct rtnl_link_stats64 *stats)
360#else
41c445ff
JB		 361static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
362 struct net_device *netdev,
980e9b11 363 struct rtnl_link_stats64 *stats)
38e00438 364#endif
41c445ff
JB		 365{
366 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 367 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 368 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 369 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
370 int i;
371
bc7d338f
ASJ		 372 if (test_bit(__I40E_DOWN, &vsi->state))
373 return stats;
374
3c325ced
JB		 375 if (!vsi->tx_rings)
376 return stats;
377
980e9b11
AD		 378 rcu_read_lock();
379 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 380 u64 bytes, packets;
381 unsigned int start;
382
383 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
384 if (!tx_ring)
385 continue;
386
387 do {
57a7744e 388 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 389 packets = tx_ring->stats.packets;
390 bytes = tx_ring->stats.bytes;
57a7744e 391 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 392
393 stats->tx_packets += packets;
394 stats->tx_bytes += bytes;
395 rx_ring = &tx_ring[1];
396
397 do {
57a7744e 398 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 399 packets = rx_ring->stats.packets;
400 bytes = rx_ring->stats.bytes;
57a7744e 401 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 402
980e9b11
AD		 403 stats->rx_packets += packets;
404 stats->rx_bytes += bytes;
405 }
406 rcu_read_unlock();
407
a5282f44 408 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 409 stats->multicast = vsi_stats->multicast;
410 stats->tx_errors = vsi_stats->tx_errors;
411 stats->tx_dropped = vsi_stats->tx_dropped;
412 stats->rx_errors = vsi_stats->rx_errors;
413 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
414 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 415
980e9b11 416 return stats;
41c445ff
JB		 417}
418
419/**
420 * i40e_vsi_reset_stats - Resets all stats of the given vsi
421 * @vsi: the VSI to have its stats reset
422 **/
423void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
424{
425 struct rtnl_link_stats64 *ns;
426 int i;
427
428 if (!vsi)
429 return;
430
431 ns = i40e_get_vsi_stats_struct(vsi);
432 memset(ns, 0, sizeof(*ns));
433 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
434 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
435 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 436 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 437 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 438 memset(&vsi->rx_rings[i]->stats, 0 ,
439 sizeof(vsi->rx_rings[i]->stats));
440 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
441 sizeof(vsi->rx_rings[i]->rx_stats));
442 memset(&vsi->tx_rings[i]->stats, 0 ,
443 sizeof(vsi->tx_rings[i]->stats));
444 memset(&vsi->tx_rings[i]->tx_stats, 0,
445 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 446 }
8e9dca53 447 }
41c445ff
JB		 448 vsi->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_pf_reset_stats - Reset all of the stats for the given pf
453 * @pf: the PF to be reset
454 **/
455void i40e_pf_reset_stats(struct i40e_pf *pf)
456{
e91fdf76
SN		 457 int i;
458
41c445ff
JB		 459 memset(&pf->stats, 0, sizeof(pf->stats));
460 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
461 pf->stat_offsets_loaded = false;
e91fdf76
SN		 462
463 for (i = 0; i < I40E_MAX_VEB; i++) {
464 if (pf->veb[i]) {
465 memset(&pf->veb[i]->stats, 0,
466 sizeof(pf->veb[i]->stats));
467 memset(&pf->veb[i]->stats_offsets, 0,
468 sizeof(pf->veb[i]->stats_offsets));
469 pf->veb[i]->stat_offsets_loaded = false;
470 }
471 }
41c445ff
JB		 472}
473
474/**
475 * i40e_stat_update48 - read and update a 48 bit stat from the chip
476 * @hw: ptr to the hardware info
477 * @hireg: the high 32 bit reg to read
478 * @loreg: the low 32 bit reg to read
479 * @offset_loaded: has the initial offset been loaded yet
480 * @offset: ptr to current offset value
481 * @stat: ptr to the stat
482 *
483 * Since the device stats are not reset at PFReset, they likely will not
484 * be zeroed when the driver starts. We'll save the first values read
485 * and use them as offsets to be subtracted from the raw values in order
486 * to report stats that count from zero. In the process, we also manage
487 * the potential roll-over.
488 **/
489static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
490 bool offset_loaded, u64 *offset, u64 *stat)
491{
492 u64 new_data;
493
ab60085e 494 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 495 new_data = rd32(hw, loreg);
496 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
497 } else {
498 new_data = rd64(hw, loreg);
499 }
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = new_data - *offset;
504 else
505 *stat = (new_data + ((u64)1 << 48)) - *offset;
506 *stat &= 0xFFFFFFFFFFFFULL;
507}
508
509/**
510 * i40e_stat_update32 - read and update a 32 bit stat from the chip
511 * @hw: ptr to the hardware info
512 * @reg: the hw reg to read
513 * @offset_loaded: has the initial offset been loaded yet
514 * @offset: ptr to current offset value
515 * @stat: ptr to the stat
516 **/
517static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
518 bool offset_loaded, u64 *offset, u64 *stat)
519{
520 u32 new_data;
521
522 new_data = rd32(hw, reg);
523 if (!offset_loaded)
524 *offset = new_data;
525 if (likely(new_data >= *offset))
526 *stat = (u32)(new_data - *offset);
527 else
528 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
529}
530
531/**
532 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
533 * @vsi: the VSI to be updated
534 **/
535void i40e_update_eth_stats(struct i40e_vsi *vsi)
536{
537 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
538 struct i40e_pf *pf = vsi->back;
539 struct i40e_hw *hw = &pf->hw;
540 struct i40e_eth_stats *oes;
541 struct i40e_eth_stats *es; /* device's eth stats */
542
543 es = &vsi->eth_stats;
544 oes = &vsi->eth_stats_offsets;
545
546 /* Gather up the stats that the hw collects */
547 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->tx_errors, &es->tx_errors);
550 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
551 vsi->stat_offsets_loaded,
552 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 553 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
556 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 559
560 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
561 I40E_GLV_GORCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->rx_bytes, &es->rx_bytes);
564 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
565 I40E_GLV_UPRCL(stat_idx),
566 vsi->stat_offsets_loaded,
567 &oes->rx_unicast, &es->rx_unicast);
568 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
569 I40E_GLV_MPRCL(stat_idx),
570 vsi->stat_offsets_loaded,
571 &oes->rx_multicast, &es->rx_multicast);
572 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
573 I40E_GLV_BPRCL(stat_idx),
574 vsi->stat_offsets_loaded,
575 &oes->rx_broadcast, &es->rx_broadcast);
576
577 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
578 I40E_GLV_GOTCL(stat_idx),
579 vsi->stat_offsets_loaded,
580 &oes->tx_bytes, &es->tx_bytes);
581 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
582 I40E_GLV_UPTCL(stat_idx),
583 vsi->stat_offsets_loaded,
584 &oes->tx_unicast, &es->tx_unicast);
585 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
586 I40E_GLV_MPTCL(stat_idx),
587 vsi->stat_offsets_loaded,
588 &oes->tx_multicast, &es->tx_multicast);
589 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
590 I40E_GLV_BPTCL(stat_idx),
591 vsi->stat_offsets_loaded,
592 &oes->tx_broadcast, &es->tx_broadcast);
593 vsi->stat_offsets_loaded = true;
594}
595
596/**
597 * i40e_update_veb_stats - Update Switch component statistics
598 * @veb: the VEB being updated
599 **/
600static void i40e_update_veb_stats(struct i40e_veb *veb)
601{
602 struct i40e_pf *pf = veb->pf;
603 struct i40e_hw *hw = &pf->hw;
604 struct i40e_eth_stats *oes;
605 struct i40e_eth_stats *es; /* device's eth stats */
606 int idx = 0;
607
608 idx = veb->stats_idx;
609 es = &veb->stats;
610 oes = &veb->stats_offsets;
611
612 /* Gather up the stats that the hw collects */
613 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
614 veb->stat_offsets_loaded,
615 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 616 if (hw->revision_id > 0)
617 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
618 veb->stat_offsets_loaded,
619 &oes->rx_unknown_protocol,
620 &es->rx_unknown_protocol);
41c445ff
JB		 621 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
622 veb->stat_offsets_loaded,
623 &oes->rx_bytes, &es->rx_bytes);
624 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
625 veb->stat_offsets_loaded,
626 &oes->rx_unicast, &es->rx_unicast);
627 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
628 veb->stat_offsets_loaded,
629 &oes->rx_multicast, &es->rx_multicast);
630 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
631 veb->stat_offsets_loaded,
632 &oes->rx_broadcast, &es->rx_broadcast);
633
634 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
635 veb->stat_offsets_loaded,
636 &oes->tx_bytes, &es->tx_bytes);
637 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
638 veb->stat_offsets_loaded,
639 &oes->tx_unicast, &es->tx_unicast);
640 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
641 veb->stat_offsets_loaded,
642 &oes->tx_multicast, &es->tx_multicast);
643 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
644 veb->stat_offsets_loaded,
645 &oes->tx_broadcast, &es->tx_broadcast);
646 veb->stat_offsets_loaded = true;
647}
648
38e00438
VD		 649#ifdef I40E_FCOE
650/**
651 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
652 * @vsi: the VSI that is capable of doing FCoE
653 **/
654static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
655{
656 struct i40e_pf *pf = vsi->back;
657 struct i40e_hw *hw = &pf->hw;
658 struct i40e_fcoe_stats *ofs;
659 struct i40e_fcoe_stats *fs; /* device's eth stats */
660 int idx;
661
662 if (vsi->type != I40E_VSI_FCOE)
663 return;
664
665 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
666 fs = &vsi->fcoe_stats;
667 ofs = &vsi->fcoe_stats_offsets;
668
669 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
670 vsi->fcoe_stat_offsets_loaded,
671 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
672 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
673 vsi->fcoe_stat_offsets_loaded,
674 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
675 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
676 vsi->fcoe_stat_offsets_loaded,
677 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
678 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
679 vsi->fcoe_stat_offsets_loaded,
680 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
681 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
682 vsi->fcoe_stat_offsets_loaded,
683 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
684 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
685 vsi->fcoe_stat_offsets_loaded,
686 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
687 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
688 vsi->fcoe_stat_offsets_loaded,
689 &ofs->fcoe_last_error, &fs->fcoe_last_error);
690 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
691 vsi->fcoe_stat_offsets_loaded,
692 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
693
694 vsi->fcoe_stat_offsets_loaded = true;
695}
696
697#endif
41c445ff
JB		 698/**
699 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
700 * @pf: the corresponding PF
701 *
702 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
703 **/
704static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
705{
706 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
707 struct i40e_hw_port_stats *nsd = &pf->stats;
708 struct i40e_hw *hw = &pf->hw;
709 u64 xoff = 0;
710 u16 i, v;
711
712 if ((hw->fc.current_mode != I40E_FC_FULL) &&
713 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
714 return;
715
716 xoff = nsd->link_xoff_rx;
717 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
718 pf->stat_offsets_loaded,
719 &osd->link_xoff_rx, &nsd->link_xoff_rx);
720
721 /* No new LFC xoff rx */
722 if (!(nsd->link_xoff_rx - xoff))
723 return;
724
725 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 726 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 727 struct i40e_vsi *vsi = pf->vsi[v];
728
ddfda80f 729 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 730 continue;
731
732 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 733 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 734 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
735 }
736 }
737}
738
739/**
740 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
741 * @pf: the corresponding PF
742 *
743 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
744 **/
745static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
746{
747 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
748 struct i40e_hw_port_stats *nsd = &pf->stats;
749 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
750 struct i40e_dcbx_config *dcb_cfg;
751 struct i40e_hw *hw = &pf->hw;
752 u16 i, v;
753 u8 tc;
754
755 dcb_cfg = &hw->local_dcbx_config;
756
757 /* See if DCB enabled with PFC TC */
758 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
759 !(dcb_cfg->pfc.pfcenable)) {
760 i40e_update_link_xoff_rx(pf);
761 return;
762 }
763
764 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
765 u64 prio_xoff = nsd->priority_xoff_rx[i];
766 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
767 pf->stat_offsets_loaded,
768 &osd->priority_xoff_rx[i],
769 &nsd->priority_xoff_rx[i]);
770
771 /* No new PFC xoff rx */
772 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
773 continue;
774 /* Get the TC for given priority */
775 tc = dcb_cfg->etscfg.prioritytable[i];
776 xoff[tc] = true;
777 }
778
779 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 780 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 781 struct i40e_vsi *vsi = pf->vsi[v];
782
ddfda80f 783 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 784 continue;
785
786 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 787 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 788
789 tc = ring->dcb_tc;
790 if (xoff[tc])
791 clear_bit(__I40E_HANG_CHECK_ARMED,
792 &ring->state);
793 }
794 }
795}
796
797/**
7812fddc 798 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 799 * @vsi: the VSI to be updated
800 *
801 * There are a few instances where we store the same stat in a
802 * couple of different structs. This is partly because we have
803 * the netdev stats that need to be filled out, which is slightly
804 * different from the "eth_stats" defined by the chip and used in
7812fddc 805 * VF communications. We sort it out here.
41c445ff 806 **/
7812fddc 807static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 808{
809 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 810 struct rtnl_link_stats64 *ons;
811 struct rtnl_link_stats64 *ns; /* netdev stats */
812 struct i40e_eth_stats *oes;
813 struct i40e_eth_stats *es; /* device's eth stats */
814 u32 tx_restart, tx_busy;
815 u32 rx_page, rx_buf;
816 u64 rx_p, rx_b;
817 u64 tx_p, tx_b;
41c445ff
JB		 818 u16 q;
819
820 if (test_bit(__I40E_DOWN, &vsi->state) ||
821 test_bit(__I40E_CONFIG_BUSY, &pf->state))
822 return;
823
824 ns = i40e_get_vsi_stats_struct(vsi);
825 ons = &vsi->net_stats_offsets;
826 es = &vsi->eth_stats;
827 oes = &vsi->eth_stats_offsets;
828
829 /* Gather up the netdev and vsi stats that the driver collects
830 * on the fly during packet processing
831 */
832 rx_b = rx_p = 0;
833 tx_b = tx_p = 0;
834 tx_restart = tx_busy = 0;
835 rx_page = 0;
836 rx_buf = 0;
980e9b11 837 rcu_read_lock();
41c445ff
JB		 838 for (q = 0; q < vsi->num_queue_pairs; q++) {
839 struct i40e_ring *p;
980e9b11
AD		 840 u64 bytes, packets;
841 unsigned int start;
842
843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
922 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->eth.tx_discards,
925 &nsd->eth.tx_discards);
41c445ff 926
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
928 I40E_GLPRT_UPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_unicast,
931 &nsd->eth.rx_unicast);
7812fddc
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
933 I40E_GLPRT_MPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_multicast,
936 &nsd->eth.rx_multicast);
532d283d
SN		 937 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
938 I40E_GLPRT_BPRCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.rx_broadcast,
941 &nsd->eth.rx_broadcast);
942 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
943 I40E_GLPRT_UPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_unicast,
946 &nsd->eth.tx_unicast);
947 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
948 I40E_GLPRT_MPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_multicast,
951 &nsd->eth.tx_multicast);
952 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
953 I40E_GLPRT_BPTCL(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->eth.tx_broadcast,
956 &nsd->eth.tx_broadcast);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->tx_dropped_link_down,
961 &nsd->tx_dropped_link_down);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->crc_errors, &nsd->crc_errors);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 970
7812fddc
SN		 971 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_local_faults,
974 &nsd->mac_local_faults);
975 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->mac_remote_faults,
978 &nsd->mac_remote_faults);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_length_errors,
983 &nsd->rx_length_errors);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_rx, &nsd->link_xon_rx);
988 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xon_tx, &nsd->link_xon_tx);
991 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
992 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 995
7812fddc
SN		 996 for (i = 0; i < 8; i++) {
997 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_rx[i],
1000 &nsd->priority_xon_rx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xon_tx[i],
1004 &nsd->priority_xon_tx[i]);
1005 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xoff_tx[i],
1008 &nsd->priority_xoff_tx[i]);
1009 i40e_stat_update32(hw,
1010 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1011 pf->stat_offsets_loaded,
7812fddc
SN		 1012 &osd->priority_xon_2_xoff[i],
1013 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1014 }
1015
7812fddc
SN		 1016 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1017 I40E_GLPRT_PRC64L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_64, &nsd->rx_size_64);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1021 I40E_GLPRT_PRC127L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_127, &nsd->rx_size_127);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1025 I40E_GLPRT_PRC255L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_255, &nsd->rx_size_255);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1029 I40E_GLPRT_PRC511L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_511, &nsd->rx_size_511);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1033 I40E_GLPRT_PRC1023L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1023, &nsd->rx_size_1023);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1037 I40E_GLPRT_PRC1522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_1522, &nsd->rx_size_1522);
1040 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1041 I40E_GLPRT_PRC9522L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_size_big, &nsd->rx_size_big);
1044
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1046 I40E_GLPRT_PTC64L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_64, &nsd->tx_size_64);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1050 I40E_GLPRT_PTC127L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_127, &nsd->tx_size_127);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1054 I40E_GLPRT_PTC255L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_255, &nsd->tx_size_255);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1058 I40E_GLPRT_PTC511L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_511, &nsd->tx_size_511);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1062 I40E_GLPRT_PTC1023L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1023, &nsd->tx_size_1023);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1066 I40E_GLPRT_PTC1522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_1522, &nsd->tx_size_1522);
1069 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1070 I40E_GLPRT_PTC9522L(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->tx_size_big, &nsd->tx_size_big);
1073
1074 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1075 pf->stat_offsets_loaded,
1076 &osd->rx_undersize, &nsd->rx_undersize);
1077 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_fragments, &nsd->rx_fragments);
1080 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_oversize, &nsd->rx_oversize);
1083 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_jabber, &nsd->rx_jabber);
1086
433c47de
ASJ		 1087 /* FDIR stats */
1088 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1089 pf->stat_offsets_loaded,
1090 &osd->fd_atr_match, &nsd->fd_atr_match);
1091 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1092 pf->stat_offsets_loaded,
1093 &osd->fd_sb_match, &nsd->fd_sb_match);
1094
7812fddc
SN		 1095 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1096 nsd->tx_lpi_status =
1097 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1098 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1099 nsd->rx_lpi_status =
1100 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1101 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1102 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1103 pf->stat_offsets_loaded,
1104 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1105 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1106 pf->stat_offsets_loaded,
1107 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1108
41c445ff
JB		 1109 pf->stat_offsets_loaded = true;
1110}
1111
7812fddc
SN		 1112/**
1113 * i40e_update_stats - Update the various statistics counters.
1114 * @vsi: the VSI to be updated
1115 *
1116 * Update the various stats for this VSI and its related entities.
1117 **/
1118void i40e_update_stats(struct i40e_vsi *vsi)
1119{
1120 struct i40e_pf *pf = vsi->back;
1121
1122 if (vsi == pf->vsi[pf->lan_vsi])
1123 i40e_update_pf_stats(pf);
1124
1125 i40e_update_vsi_stats(vsi);
38e00438
VD		 1126#ifdef I40E_FCOE
1127 i40e_update_fcoe_stats(vsi);
1128#endif
7812fddc
SN		 1129}
1130
41c445ff
JB		 1131/**
1132 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1133 * @vsi: the VSI to be searched
1134 * @macaddr: the MAC address
1135 * @vlan: the vlan
1136 * @is_vf: make sure its a vf filter, else doesn't matter
1137 * @is_netdev: make sure its a netdev filter, else doesn't matter
1138 *
1139 * Returns ptr to the filter object or NULL
1140 **/
1141static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1142 u8 *macaddr, s16 vlan,
1143 bool is_vf, bool is_netdev)
1144{
1145 struct i40e_mac_filter *f;
1146
1147 if (!vsi || !macaddr)
1148 return NULL;
1149
1150 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1151 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1152 (vlan == f->vlan) &&
1153 (!is_vf || f->is_vf) &&
1154 (!is_netdev || f->is_netdev))
1155 return f;
1156 }
1157 return NULL;
1158}
1159
1160/**
1161 * i40e_find_mac - Find a mac addr in the macvlan filters list
1162 * @vsi: the VSI to be searched
1163 * @macaddr: the MAC address we are searching for
1164 * @is_vf: make sure its a vf filter, else doesn't matter
1165 * @is_netdev: make sure its a netdev filter, else doesn't matter
1166 *
1167 * Returns the first filter with the provided MAC address or NULL if
1168 * MAC address was not found
1169 **/
1170struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1171 bool is_vf, bool is_netdev)
1172{
1173 struct i40e_mac_filter *f;
1174
1175 if (!vsi || !macaddr)
1176 return NULL;
1177
1178 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1179 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1180 (!is_vf || f->is_vf) &&
1181 (!is_netdev || f->is_netdev))
1182 return f;
1183 }
1184 return NULL;
1185}
1186
1187/**
1188 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1189 * @vsi: the VSI to be searched
1190 *
1191 * Returns true if VSI is in vlan mode or false otherwise
1192 **/
1193bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1194{
1195 struct i40e_mac_filter *f;
1196
1197 /* Only -1 for all the filters denotes not in vlan mode
1198 * so we have to go through all the list in order to make sure
1199 */
1200 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1201 if (f->vlan >= 0)
1202 return true;
1203 }
1204
1205 return false;
1206}
1207
1208/**
1209 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1210 * @vsi: the VSI to be searched
1211 * @macaddr: the mac address to be filtered
1212 * @is_vf: true if it is a vf
1213 * @is_netdev: true if it is a netdev
1214 *
1215 * Goes through all the macvlan filters and adds a
1216 * macvlan filter for each unique vlan that already exists
1217 *
1218 * Returns first filter found on success, else NULL
1219 **/
1220struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1221 bool is_vf, bool is_netdev)
1222{
1223 struct i40e_mac_filter *f;
1224
1225 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1226 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1227 is_vf, is_netdev)) {
1228 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1229 is_vf, is_netdev))
41c445ff
JB		 1230 return NULL;
1231 }
1232 }
1233
1234 return list_first_entry_or_null(&vsi->mac_filter_list,
1235 struct i40e_mac_filter, list);
1236}
1237
8c27d42e
GR		 1238/**
1239 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1240 * @vsi: the PF Main VSI - inappropriate for any other VSI
1241 * @macaddr: the MAC address
30650cc5
SN		 1242 *
1243 * Some older firmware configurations set up a default promiscuous VLAN
1244 * filter that needs to be removed.
8c27d42e 1245 **/
30650cc5 1246static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1247{
1248 struct i40e_aqc_remove_macvlan_element_data element;
1249 struct i40e_pf *pf = vsi->back;
1250 i40e_status aq_ret;
1251
1252 /* Only appropriate for the PF main VSI */
1253 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1254 return -EINVAL;
8c27d42e 1255
30650cc5 1256 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1257 ether_addr_copy(element.mac_addr, macaddr);
1258 element.vlan_tag = 0;
1259 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1260 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1261 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1262 if (aq_ret)
30650cc5
SN		 1263 return -ENOENT;
1264
1265 return 0;
8c27d42e
GR		 1266}
1267
41c445ff
JB		 1268/**
1269 * i40e_add_filter - Add a mac/vlan filter to the VSI
1270 * @vsi: the VSI to be searched
1271 * @macaddr: the MAC address
1272 * @vlan: the vlan
1273 * @is_vf: make sure its a vf filter, else doesn't matter
1274 * @is_netdev: make sure its a netdev filter, else doesn't matter
1275 *
1276 * Returns ptr to the filter object or NULL when no memory available.
1277 **/
1278struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1279 u8 *macaddr, s16 vlan,
1280 bool is_vf, bool is_netdev)
1281{
1282 struct i40e_mac_filter *f;
1283
1284 if (!vsi || !macaddr)
1285 return NULL;
1286
1287 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1288 if (!f) {
1289 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1290 if (!f)
1291 goto add_filter_out;
1292
9a173901 1293 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1294 f->vlan = vlan;
1295 f->changed = true;
1296
1297 INIT_LIST_HEAD(&f->list);
1298 list_add(&f->list, &vsi->mac_filter_list);
1299 }
1300
1301 /* increment counter and add a new flag if needed */
1302 if (is_vf) {
1303 if (!f->is_vf) {
1304 f->is_vf = true;
1305 f->counter++;
1306 }
1307 } else if (is_netdev) {
1308 if (!f->is_netdev) {
1309 f->is_netdev = true;
1310 f->counter++;
1311 }
1312 } else {
1313 f->counter++;
1314 }
1315
1316 /* changed tells sync_filters_subtask to
1317 * push the filter down to the firmware
1318 */
1319 if (f->changed) {
1320 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1321 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1322 }
1323
1324add_filter_out:
1325 return f;
1326}
1327
1328/**
1329 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1330 * @vsi: the VSI to be searched
1331 * @macaddr: the MAC address
1332 * @vlan: the vlan
1333 * @is_vf: make sure it's a vf filter, else doesn't matter
1334 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1335 **/
1336void i40e_del_filter(struct i40e_vsi *vsi,
1337 u8 *macaddr, s16 vlan,
1338 bool is_vf, bool is_netdev)
1339{
1340 struct i40e_mac_filter *f;
1341
1342 if (!vsi || !macaddr)
1343 return;
1344
1345 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1346 if (!f || f->counter == 0)
1347 return;
1348
1349 if (is_vf) {
1350 if (f->is_vf) {
1351 f->is_vf = false;
1352 f->counter--;
1353 }
1354 } else if (is_netdev) {
1355 if (f->is_netdev) {
1356 f->is_netdev = false;
1357 f->counter--;
1358 }
1359 } else {
1360 /* make sure we don't remove a filter in use by vf or netdev */
1361 int min_f = 0;
1362 min_f += (f->is_vf ? 1 : 0);
1363 min_f += (f->is_netdev ? 1 : 0);
1364
1365 if (f->counter > min_f)
1366 f->counter--;
1367 }
1368
1369 /* counter == 0 tells sync_filters_subtask to
1370 * remove the filter from the firmware's list
1371 */
1372 if (f->counter == 0) {
1373 f->changed = true;
1374 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1375 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1376 }
1377}
1378
1379/**
1380 * i40e_set_mac - NDO callback to set mac address
1381 * @netdev: network interface device structure
1382 * @p: pointer to an address structure
1383 *
1384 * Returns 0 on success, negative on failure
1385 **/
38e00438
VD		 1386#ifdef I40E_FCOE
1387int i40e_set_mac(struct net_device *netdev, void *p)
1388#else
41c445ff 1389static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1390#endif
41c445ff
JB		 1391{
1392 struct i40e_netdev_priv *np = netdev_priv(netdev);
1393 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1394 struct i40e_pf *pf = vsi->back;
1395 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1396 struct sockaddr *addr = p;
1397 struct i40e_mac_filter *f;
1398
1399 if (!is_valid_ether_addr(addr->sa_data))
1400 return -EADDRNOTAVAIL;
1401
30650cc5
SN		 1402 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1403 netdev_info(netdev, "already using mac address %pM\n",
1404 addr->sa_data);
1405 return 0;
1406 }
41c445ff 1407
80f6428f
ASJ		 1408 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1409 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1410 return -EADDRNOTAVAIL;
1411
30650cc5
SN		 1412 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1413 netdev_info(netdev, "returning to hw mac address %pM\n",
1414 hw->mac.addr);
1415 else
1416 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1417
41c445ff
JB		 1418 if (vsi->type == I40E_VSI_MAIN) {
1419 i40e_status ret;
1420 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1421 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1422 addr->sa_data, NULL);
1423 if (ret) {
1424 netdev_info(netdev,
1425 "Addr change for Main VSI failed: %d\n",
1426 ret);
1427 return -EADDRNOTAVAIL;
1428 }
41c445ff
JB		 1429 }
1430
30650cc5
SN		 1431 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1432 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1433
30650cc5
SN		 1434 memset(&element, 0, sizeof(element));
1435 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1436 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1437 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1438 } else {
6c8ad1ba
SN		 1439 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1440 false, false);
6c8ad1ba 1441 }
41c445ff 1442
30650cc5
SN		 1443 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1444 struct i40e_aqc_add_macvlan_element_data element;
1445
1446 memset(&element, 0, sizeof(element));
1447 ether_addr_copy(element.mac_addr, hw->mac.addr);
1448 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1449 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1450 } else {
1451 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1452 false, false);
1453 if (f)
1454 f->is_laa = true;
1455 }
1456
1457 i40e_sync_vsi_filters(vsi);
1458 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1459
1460 return 0;
1461}
1462
1463/**
1464 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1465 * @vsi: the VSI being setup
1466 * @ctxt: VSI context structure
1467 * @enabled_tc: Enabled TCs bitmap
1468 * @is_add: True if called before Add VSI
1469 *
1470 * Setup VSI queue mapping for enabled traffic classes.
1471 **/
38e00438
VD		 1472#ifdef I40E_FCOE
1473void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
1477#else
41c445ff
JB		 1478static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1479 struct i40e_vsi_context *ctxt,
1480 u8 enabled_tc,
1481 bool is_add)
38e00438 1482#endif
41c445ff
JB		 1483{
1484 struct i40e_pf *pf = vsi->back;
1485 u16 sections = 0;
1486 u8 netdev_tc = 0;
1487 u16 numtc = 0;
1488 u16 qcount;
1489 u8 offset;
1490 u16 qmap;
1491 int i;
4e3b35b0 1492 u16 num_tc_qps = 0;
41c445ff
JB		 1493
1494 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1495 offset = 0;
1496
1497 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1498 /* Find numtc from enabled TC bitmap */
1499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1500 if (enabled_tc & (1 << i)) /* TC is enabled */
1501 numtc++;
1502 }
1503 if (!numtc) {
1504 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1505 numtc = 1;
1506 }
1507 } else {
1508 /* At least TC0 is enabled in case of non-DCB case */
1509 numtc = 1;
1510 }
1511
1512 vsi->tc_config.numtc = numtc;
1513 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1514 /* Number of queues per enabled TC */
eb051afe 1515 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1516 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1517
1518 /* Setup queue offset/count for all TCs for given VSI */
1519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1520 /* See if the given TC is enabled for the given VSI */
1521 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1522 int pow, num_qps;
1523
41c445ff
JB		 1524 switch (vsi->type) {
1525 case I40E_VSI_MAIN:
4e3b35b0 1526 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1527 break;
38e00438
VD		 1528#ifdef I40E_FCOE
1529 case I40E_VSI_FCOE:
1530 qcount = num_tc_qps;
1531 break;
1532#endif
41c445ff
JB		 1533 case I40E_VSI_FDIR:
1534 case I40E_VSI_SRIOV:
1535 case I40E_VSI_VMDQ2:
1536 default:
4e3b35b0 1537 qcount = num_tc_qps;
41c445ff
JB		 1538 WARN_ON(i != 0);
1539 break;
1540 }
4e3b35b0
NP		 1541 vsi->tc_config.tc_info[i].qoffset = offset;
1542 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1543
1544 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1545 num_qps = qcount;
41c445ff 1546 pow = 0;
4e3b35b0 1547 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1548 pow++;
1549 num_qps >>= 1;
1550 }
1551
1552 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1553 qmap =
1554 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1555 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1556
4e3b35b0 1557 offset += qcount;
41c445ff
JB		 1558 } else {
1559 /* TC is not enabled so set the offset to
1560 * default queue and allocate one queue
1561 * for the given TC.
1562 */
1563 vsi->tc_config.tc_info[i].qoffset = 0;
1564 vsi->tc_config.tc_info[i].qcount = 1;
1565 vsi->tc_config.tc_info[i].netdev_tc = 0;
1566
1567 qmap = 0;
1568 }
1569 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1570 }
1571
1572 /* Set actual Tx/Rx queue pairs */
1573 vsi->num_queue_pairs = offset;
1574
1575 /* Scheduler section valid can only be set for ADD VSI */
1576 if (is_add) {
1577 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1578
1579 ctxt->info.up_enable_bits = enabled_tc;
1580 }
1581 if (vsi->type == I40E_VSI_SRIOV) {
1582 ctxt->info.mapping_flags |=
1583 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1584 for (i = 0; i < vsi->num_queue_pairs; i++)
1585 ctxt->info.queue_mapping[i] =
1586 cpu_to_le16(vsi->base_queue + i);
1587 } else {
1588 ctxt->info.mapping_flags |=
1589 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1590 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1591 }
1592 ctxt->info.valid_sections |= cpu_to_le16(sections);
1593}
1594
1595/**
1596 * i40e_set_rx_mode - NDO callback to set the netdev filters
1597 * @netdev: network interface device structure
1598 **/
38e00438
VD		 1599#ifdef I40E_FCOE
1600void i40e_set_rx_mode(struct net_device *netdev)
1601#else
41c445ff 1602static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1603#endif
41c445ff
JB		 1604{
1605 struct i40e_netdev_priv *np = netdev_priv(netdev);
1606 struct i40e_mac_filter *f, *ftmp;
1607 struct i40e_vsi *vsi = np->vsi;
1608 struct netdev_hw_addr *uca;
1609 struct netdev_hw_addr *mca;
1610 struct netdev_hw_addr *ha;
1611
1612 /* add addr if not already in the filter list */
1613 netdev_for_each_uc_addr(uca, netdev) {
1614 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1615 if (i40e_is_vsi_in_vlan(vsi))
1616 i40e_put_mac_in_vlan(vsi, uca->addr,
1617 false, true);
1618 else
1619 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1620 false, true);
1621 }
1622 }
1623
1624 netdev_for_each_mc_addr(mca, netdev) {
1625 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1626 if (i40e_is_vsi_in_vlan(vsi))
1627 i40e_put_mac_in_vlan(vsi, mca->addr,
1628 false, true);
1629 else
1630 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1631 false, true);
1632 }
1633 }
1634
1635 /* remove filter if not in netdev list */
1636 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1637 bool found = false;
1638
1639 if (!f->is_netdev)
1640 continue;
1641
1642 if (is_multicast_ether_addr(f->macaddr)) {
1643 netdev_for_each_mc_addr(mca, netdev) {
1644 if (ether_addr_equal(mca->addr, f->macaddr)) {
1645 found = true;
1646 break;
1647 }
1648 }
1649 } else {
1650 netdev_for_each_uc_addr(uca, netdev) {
1651 if (ether_addr_equal(uca->addr, f->macaddr)) {
1652 found = true;
1653 break;
1654 }
1655 }
1656
1657 for_each_dev_addr(netdev, ha) {
1658 if (ether_addr_equal(ha->addr, f->macaddr)) {
1659 found = true;
1660 break;
1661 }
1662 }
1663 }
1664 if (!found)
1665 i40e_del_filter(
1666 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1667 }
1668
1669 /* check for other flag changes */
1670 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1671 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1672 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1673 }
1674}
1675
1676/**
1677 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1678 * @vsi: ptr to the VSI
1679 *
1680 * Push any outstanding VSI filter changes through the AdminQ.
1681 *
1682 * Returns 0 or error value
1683 **/
1684int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1685{
1686 struct i40e_mac_filter *f, *ftmp;
1687 bool promisc_forced_on = false;
1688 bool add_happened = false;
1689 int filter_list_len = 0;
1690 u32 changed_flags = 0;
dcae29be 1691 i40e_status aq_ret = 0;
41c445ff
JB		 1692 struct i40e_pf *pf;
1693 int num_add = 0;
1694 int num_del = 0;
1695 u16 cmd_flags;
1696
1697 /* empty array typed pointers, kcalloc later */
1698 struct i40e_aqc_add_macvlan_element_data *add_list;
1699 struct i40e_aqc_remove_macvlan_element_data *del_list;
1700
1701 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1702 usleep_range(1000, 2000);
1703 pf = vsi->back;
1704
1705 if (vsi->netdev) {
1706 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1707 vsi->current_netdev_flags = vsi->netdev->flags;
1708 }
1709
1710 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1711 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1712
1713 filter_list_len = pf->hw.aq.asq_buf_size /
1714 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1715 del_list = kcalloc(filter_list_len,
1716 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1717 GFP_KERNEL);
1718 if (!del_list)
1719 return -ENOMEM;
1720
1721 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1722 if (!f->changed)
1723 continue;
1724
1725 if (f->counter != 0)
1726 continue;
1727 f->changed = false;
1728 cmd_flags = 0;
1729
1730 /* add to delete list */
9a173901 1731 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1732 del_list[num_del].vlan_tag =
1733 cpu_to_le16((u16)(f->vlan ==
1734 I40E_VLAN_ANY ? 0 : f->vlan));
1735
41c445ff
JB		 1736 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1737 del_list[num_del].flags = cmd_flags;
1738 num_del++;
1739
1740 /* unlink from filter list */
1741 list_del(&f->list);
1742 kfree(f);
1743
1744 /* flush a full buffer */
1745 if (num_del == filter_list_len) {
dcae29be 1746 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1747 vsi->seid, del_list, num_del,
1748 NULL);
1749 num_del = 0;
1750 memset(del_list, 0, sizeof(*del_list));
1751
fdfe9cbe
SN		 1752 if (aq_ret &&
1753 pf->hw.aq.asq_last_status !=
1754 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1755 dev_info(&pf->pdev->dev,
1756 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1757 aq_ret,
41c445ff
JB		 1758 pf->hw.aq.asq_last_status);
1759 }
1760 }
1761 if (num_del) {
dcae29be 1762 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1763 del_list, num_del, NULL);
1764 num_del = 0;
1765
fdfe9cbe
SN		 1766 if (aq_ret &&
1767 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1768 dev_info(&pf->pdev->dev,
1769 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1770 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1771 }
1772
1773 kfree(del_list);
1774 del_list = NULL;
1775
1776 /* do all the adds now */
1777 filter_list_len = pf->hw.aq.asq_buf_size /
1778 sizeof(struct i40e_aqc_add_macvlan_element_data),
1779 add_list = kcalloc(filter_list_len,
1780 sizeof(struct i40e_aqc_add_macvlan_element_data),
1781 GFP_KERNEL);
1782 if (!add_list)
1783 return -ENOMEM;
1784
1785 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1786 if (!f->changed)
1787 continue;
1788
1789 if (f->counter == 0)
1790 continue;
1791 f->changed = false;
1792 add_happened = true;
1793 cmd_flags = 0;
1794
1795 /* add to add array */
9a173901 1796 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1797 add_list[num_add].vlan_tag =
1798 cpu_to_le16(
1799 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1800 add_list[num_add].queue_number = 0;
1801
1802 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1803 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1804 num_add++;
1805
1806 /* flush a full buffer */
1807 if (num_add == filter_list_len) {
dcae29be
JB		 1808 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1809 add_list, num_add,
1810 NULL);
41c445ff
JB		 1811 num_add = 0;
1812
dcae29be 1813 if (aq_ret)
41c445ff
JB		 1814 break;
1815 memset(add_list, 0, sizeof(*add_list));
1816 }
1817 }
1818 if (num_add) {
dcae29be
JB		 1819 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1820 add_list, num_add, NULL);
41c445ff
JB		 1821 num_add = 0;
1822 }
1823 kfree(add_list);
1824 add_list = NULL;
1825
30650cc5
SN		 1826 if (add_happened && aq_ret &&
1827 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1828 dev_info(&pf->pdev->dev,
1829 "add filter failed, err %d, aq_err %d\n",
dcae29be 1830 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1831 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1832 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1833 &vsi->state)) {
1834 promisc_forced_on = true;
1835 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1836 &vsi->state);
1837 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1838 }
1839 }
1840 }
1841
1842 /* check for changes in promiscuous modes */
1843 if (changed_flags & IFF_ALLMULTI) {
1844 bool cur_multipromisc;
1845 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1846 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1847 vsi->seid,
1848 cur_multipromisc,
1849 NULL);
1850 if (aq_ret)
41c445ff
JB		 1851 dev_info(&pf->pdev->dev,
1852 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1853 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1854 }
1855 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1856 bool cur_promisc;
1857 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1858 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1859 &vsi->state));
dcae29be
JB		 1860 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1861 vsi->seid,
1862 cur_promisc, NULL);
1863 if (aq_ret)
41c445ff
JB		 1864 dev_info(&pf->pdev->dev,
1865 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1866 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1867 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1868 vsi->seid,
1869 cur_promisc, NULL);
1870 if (aq_ret)
1871 dev_info(&pf->pdev->dev,
1872 "set brdcast promisc failed, err %d, aq_err %d\n",
1873 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1874 }
1875
1876 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1877 return 0;
1878}
1879
1880/**
1881 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1882 * @pf: board private structure
1883 **/
1884static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1885{
1886 int v;
1887
1888 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1889 return;
1890 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1891
505682cd 1892 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1893 if (pf->vsi[v] &&
1894 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1895 i40e_sync_vsi_filters(pf->vsi[v]);
1896 }
1897}
1898
1899/**
1900 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1901 * @netdev: network interface device structure
1902 * @new_mtu: new value for maximum frame size
1903 *
1904 * Returns 0 on success, negative on failure
1905 **/
1906static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1907{
1908 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1909 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1910 struct i40e_vsi *vsi = np->vsi;
1911
1912 /* MTU < 68 is an error and causes problems on some kernels */
1913 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1914 return -EINVAL;
1915
1916 netdev_info(netdev, "changing MTU from %d to %d\n",
1917 netdev->mtu, new_mtu);
1918 netdev->mtu = new_mtu;
1919 if (netif_running(netdev))
1920 i40e_vsi_reinit_locked(vsi);
1921
1922 return 0;
1923}
1924
beb0dff1
JK		 1925/**
1926 * i40e_ioctl - Access the hwtstamp interface
1927 * @netdev: network interface device structure
1928 * @ifr: interface request data
1929 * @cmd: ioctl command
1930 **/
1931int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1932{
1933 struct i40e_netdev_priv *np = netdev_priv(netdev);
1934 struct i40e_pf *pf = np->vsi->back;
1935
1936 switch (cmd) {
1937 case SIOCGHWTSTAMP:
1938 return i40e_ptp_get_ts_config(pf, ifr);
1939 case SIOCSHWTSTAMP:
1940 return i40e_ptp_set_ts_config(pf, ifr);
1941 default:
1942 return -EOPNOTSUPP;
1943 }
1944}
1945
41c445ff
JB		 1946/**
1947 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1948 * @vsi: the vsi being adjusted
1949 **/
1950void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1951{
1952 struct i40e_vsi_context ctxt;
1953 i40e_status ret;
1954
1955 if ((vsi->info.valid_sections &
1956 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1957 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1958 return; /* already enabled */
1959
1960 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1961 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1962 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1963
1964 ctxt.seid = vsi->seid;
1965 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1966 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1967 if (ret) {
1968 dev_info(&vsi->back->pdev->dev,
1969 "%s: update vsi failed, aq_err=%d\n",
1970 __func__, vsi->back->hw.aq.asq_last_status);
1971 }
1972}
1973
1974/**
1975 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1976 * @vsi: the vsi being adjusted
1977 **/
1978void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1979{
1980 struct i40e_vsi_context ctxt;
1981 i40e_status ret;
1982
1983 if ((vsi->info.valid_sections &
1984 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1985 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1986 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1987 return; /* already disabled */
1988
1989 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1990 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1991 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1992
1993 ctxt.seid = vsi->seid;
1994 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1995 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1996 if (ret) {
1997 dev_info(&vsi->back->pdev->dev,
1998 "%s: update vsi failed, aq_err=%d\n",
1999 __func__, vsi->back->hw.aq.asq_last_status);
2000 }
2001}
2002
2003/**
2004 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2005 * @netdev: network interface to be adjusted
2006 * @features: netdev features to test if VLAN offload is enabled or not
2007 **/
2008static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2009{
2010 struct i40e_netdev_priv *np = netdev_priv(netdev);
2011 struct i40e_vsi *vsi = np->vsi;
2012
2013 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2014 i40e_vlan_stripping_enable(vsi);
2015 else
2016 i40e_vlan_stripping_disable(vsi);
2017}
2018
2019/**
2020 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2021 * @vsi: the vsi being configured
2022 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2023 **/
2024int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2025{
2026 struct i40e_mac_filter *f, *add_f;
2027 bool is_netdev, is_vf;
41c445ff
JB		 2028
2029 is_vf = (vsi->type == I40E_VSI_SRIOV);
2030 is_netdev = !!(vsi->netdev);
2031
2032 if (is_netdev) {
2033 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2034 is_vf, is_netdev);
2035 if (!add_f) {
2036 dev_info(&vsi->back->pdev->dev,
2037 "Could not add vlan filter %d for %pM\n",
2038 vid, vsi->netdev->dev_addr);
2039 return -ENOMEM;
2040 }
2041 }
2042
2043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2044 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2045 if (!add_f) {
2046 dev_info(&vsi->back->pdev->dev,
2047 "Could not add vlan filter %d for %pM\n",
2048 vid, f->macaddr);
2049 return -ENOMEM;
2050 }
2051 }
2052
41c445ff
JB		 2053 /* Now if we add a vlan tag, make sure to check if it is the first
2054 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2055 * with 0, so we now accept untagged and specified tagged traffic
2056 * (and not any taged and untagged)
2057 */
2058 if (vid > 0) {
2059 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2060 I40E_VLAN_ANY,
2061 is_vf, is_netdev)) {
2062 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2063 I40E_VLAN_ANY, is_vf, is_netdev);
2064 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2065 is_vf, is_netdev);
2066 if (!add_f) {
2067 dev_info(&vsi->back->pdev->dev,
2068 "Could not add filter 0 for %pM\n",
2069 vsi->netdev->dev_addr);
2070 return -ENOMEM;
2071 }
2072 }
8d82a7c5 2073 }
41c445ff 2074
8d82a7c5
GR		 2075 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2076 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2077 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2078 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2079 is_vf, is_netdev)) {
2080 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2081 is_vf, is_netdev);
2082 add_f = i40e_add_filter(vsi, f->macaddr,
2083 0, is_vf, is_netdev);
2084 if (!add_f) {
2085 dev_info(&vsi->back->pdev->dev,
2086 "Could not add filter 0 for %pM\n",
2087 f->macaddr);
2088 return -ENOMEM;
2089 }
2090 }
2091 }
41c445ff
JB		 2092 }
2093
80f6428f
ASJ		 2094 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2095 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2096 return 0;
2097
2098 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2099}
2100
2101/**
2102 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2103 * @vsi: the vsi being configured
2104 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2105 *
2106 * Return: 0 on success or negative otherwise
41c445ff
JB		 2107 **/
2108int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2109{
2110 struct net_device *netdev = vsi->netdev;
2111 struct i40e_mac_filter *f, *add_f;
2112 bool is_vf, is_netdev;
2113 int filter_count = 0;
41c445ff
JB		 2114
2115 is_vf = (vsi->type == I40E_VSI_SRIOV);
2116 is_netdev = !!(netdev);
2117
2118 if (is_netdev)
2119 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2120
2121 list_for_each_entry(f, &vsi->mac_filter_list, list)
2122 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2123
41c445ff
JB		 2124 /* go through all the filters for this VSI and if there is only
2125 * vid == 0 it means there are no other filters, so vid 0 must
2126 * be replaced with -1. This signifies that we should from now
2127 * on accept any traffic (with any tag present, or untagged)
2128 */
2129 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2130 if (is_netdev) {
2131 if (f->vlan &&
2132 ether_addr_equal(netdev->dev_addr, f->macaddr))
2133 filter_count++;
2134 }
2135
2136 if (f->vlan)
2137 filter_count++;
2138 }
2139
2140 if (!filter_count && is_netdev) {
2141 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2142 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2143 is_vf, is_netdev);
2144 if (!f) {
2145 dev_info(&vsi->back->pdev->dev,
2146 "Could not add filter %d for %pM\n",
2147 I40E_VLAN_ANY, netdev->dev_addr);
2148 return -ENOMEM;
2149 }
2150 }
2151
2152 if (!filter_count) {
2153 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2154 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2155 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2156 is_vf, is_netdev);
2157 if (!add_f) {
2158 dev_info(&vsi->back->pdev->dev,
2159 "Could not add filter %d for %pM\n",
2160 I40E_VLAN_ANY, f->macaddr);
2161 return -ENOMEM;
2162 }
2163 }
2164 }
2165
80f6428f
ASJ		 2166 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2167 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2168 return 0;
2169
41c445ff
JB		 2170 return i40e_sync_vsi_filters(vsi);
2171}
2172
2173/**
2174 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2175 * @netdev: network interface to be adjusted
2176 * @vid: vlan id to be added
078b5876
JB		 2177 *
2178 * net_device_ops implementation for adding vlan ids
41c445ff 2179 **/
38e00438
VD		 2180#ifdef I40E_FCOE
2181int i40e_vlan_rx_add_vid(struct net_device *netdev,
2182 __always_unused __be16 proto, u16 vid)
2183#else
41c445ff
JB		 2184static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2185 __always_unused __be16 proto, u16 vid)
38e00438 2186#endif
41c445ff
JB		 2187{
2188 struct i40e_netdev_priv *np = netdev_priv(netdev);
2189 struct i40e_vsi *vsi = np->vsi;
078b5876 2190 int ret = 0;
41c445ff
JB		 2191
2192 if (vid > 4095)
078b5876
JB		 2193 return -EINVAL;
2194
2195 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2196
6982d429
ASJ		 2197 /* If the network stack called us with vid = 0 then
2198 * it is asking to receive priority tagged packets with
2199 * vlan id 0. Our HW receives them by default when configured
2200 * to receive untagged packets so there is no need to add an
2201 * extra filter for vlan 0 tagged packets.
41c445ff 2202 */
6982d429
ASJ		 2203 if (vid)
2204 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2205
078b5876
JB		 2206 if (!ret && (vid < VLAN_N_VID))
2207 set_bit(vid, vsi->active_vlans);
41c445ff 2208
078b5876 2209 return ret;
41c445ff
JB		 2210}
2211
2212/**
2213 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2214 * @netdev: network interface to be adjusted
2215 * @vid: vlan id to be removed
078b5876 2216 *
fdfd943e 2217 * net_device_ops implementation for removing vlan ids
41c445ff 2218 **/
38e00438
VD		 2219#ifdef I40E_FCOE
2220int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2221 __always_unused __be16 proto, u16 vid)
2222#else
41c445ff
JB		 2223static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2224 __always_unused __be16 proto, u16 vid)
38e00438 2225#endif
41c445ff
JB		 2226{
2227 struct i40e_netdev_priv *np = netdev_priv(netdev);
2228 struct i40e_vsi *vsi = np->vsi;
2229
078b5876
JB		 2230 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2231
41c445ff
JB		 2232 /* return code is ignored as there is nothing a user
2233 * can do about failure to remove and a log message was
078b5876 2234 * already printed from the other function
41c445ff
JB		 2235 */
2236 i40e_vsi_kill_vlan(vsi, vid);
2237
2238 clear_bit(vid, vsi->active_vlans);
078b5876 2239
41c445ff
JB		 2240 return 0;
2241}
2242
2243/**
2244 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2245 * @vsi: the vsi being brought back up
2246 **/
2247static void i40e_restore_vlan(struct i40e_vsi *vsi)
2248{
2249 u16 vid;
2250
2251 if (!vsi->netdev)
2252 return;
2253
2254 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2255
2256 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2257 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2258 vid);
2259}
2260
2261/**
2262 * i40e_vsi_add_pvid - Add pvid for the VSI
2263 * @vsi: the vsi being adjusted
2264 * @vid: the vlan id to set as a PVID
2265 **/
dcae29be 2266int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2267{
2268 struct i40e_vsi_context ctxt;
dcae29be 2269 i40e_status aq_ret;
41c445ff
JB		 2270
2271 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2272 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2273 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2274 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2275 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2276
2277 ctxt.seid = vsi->seid;
2278 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2279 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2280 if (aq_ret) {
41c445ff
JB		 2281 dev_info(&vsi->back->pdev->dev,
2282 "%s: update vsi failed, aq_err=%d\n",
2283 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2284 return -ENOENT;
41c445ff
JB		 2285 }
2286
dcae29be 2287 return 0;
41c445ff
JB		 2288}
2289
2290/**
2291 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2292 * @vsi: the vsi being adjusted
2293 *
2294 * Just use the vlan_rx_register() service to put it back to normal
2295 **/
2296void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2297{
6c12fcbf
GR		 2298 i40e_vlan_stripping_disable(vsi);
2299
41c445ff 2300 vsi->info.pvid = 0;
41c445ff
JB		 2301}
2302
2303/**
2304 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2305 * @vsi: ptr to the VSI
2306 *
2307 * If this function returns with an error, then it's possible one or
2308 * more of the rings is populated (while the rest are not). It is the
2309 * callers duty to clean those orphaned rings.
2310 *
2311 * Return 0 on success, negative on failure
2312 **/
2313static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2314{
2315 int i, err = 0;
2316
2317 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2318 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2319
2320 return err;
2321}
2322
2323/**
2324 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2325 * @vsi: ptr to the VSI
2326 *
2327 * Free VSI's transmit software resources
2328 **/
2329static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2330{
2331 int i;
2332
8e9dca53
GR		 2333 if (!vsi->tx_rings)
2334 return;
2335
41c445ff 2336 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2337 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2338 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2343 * @vsi: ptr to the VSI
2344 *
2345 * If this function returns with an error, then it's possible one or
2346 * more of the rings is populated (while the rest are not). It is the
2347 * callers duty to clean those orphaned rings.
2348 *
2349 * Return 0 on success, negative on failure
2350 **/
2351static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2352{
2353 int i, err = 0;
2354
2355 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2356 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2357#ifdef I40E_FCOE
2358 i40e_fcoe_setup_ddp_resources(vsi);
2359#endif
41c445ff
JB		 2360 return err;
2361}
2362
2363/**
2364 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2365 * @vsi: ptr to the VSI
2366 *
2367 * Free all receive software resources
2368 **/
2369static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2370{
2371 int i;
2372
8e9dca53
GR		 2373 if (!vsi->rx_rings)
2374 return;
2375
41c445ff 2376 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2377 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2378 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2379#ifdef I40E_FCOE
2380 i40e_fcoe_free_ddp_resources(vsi);
2381#endif
41c445ff
JB		 2382}
2383
2384/**
2385 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2386 * @ring: The Tx ring to configure
2387 *
2388 * Configure the Tx descriptor ring in the HMC context.
2389 **/
2390static int i40e_configure_tx_ring(struct i40e_ring *ring)
2391{
2392 struct i40e_vsi *vsi = ring->vsi;
2393 u16 pf_q = vsi->base_queue + ring->queue_index;
2394 struct i40e_hw *hw = &vsi->back->hw;
2395 struct i40e_hmc_obj_txq tx_ctx;
2396 i40e_status err = 0;
2397 u32 qtx_ctl = 0;
2398
2399 /* some ATR related tx ring init */
60ea5f83 2400 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2401 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2402 ring->atr_count = 0;
2403 } else {
2404 ring->atr_sample_rate = 0;
2405 }
2406
2407 /* initialize XPS */
2408 if (ring->q_vector && ring->netdev &&
4e3b35b0 2409 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2410 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2411 netif_set_xps_queue(ring->netdev,
2412 &ring->q_vector->affinity_mask,
2413 ring->queue_index);
2414
2415 /* clear the context structure first */
2416 memset(&tx_ctx, 0, sizeof(tx_ctx));
2417
2418 tx_ctx.new_context = 1;
2419 tx_ctx.base = (ring->dma / 128);
2420 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2421 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2422 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2423#ifdef I40E_FCOE
2424 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2425#endif
beb0dff1 2426 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2427 /* FDIR VSI tx ring can still use RS bit and writebacks */
2428 if (vsi->type != I40E_VSI_FDIR)
2429 tx_ctx.head_wb_ena = 1;
2430 tx_ctx.head_wb_addr = ring->dma +
2431 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2432
2433 /* As part of VSI creation/update, FW allocates certain
2434 * Tx arbitration queue sets for each TC enabled for
2435 * the VSI. The FW returns the handles to these queue
2436 * sets as part of the response buffer to Add VSI,
2437 * Update VSI, etc. AQ commands. It is expected that
2438 * these queue set handles be associated with the Tx
2439 * queues by the driver as part of the TX queue context
2440 * initialization. This has to be done regardless of
2441 * DCB as by default everything is mapped to TC0.
2442 */
2443 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2444 tx_ctx.rdylist_act = 0;
2445
2446 /* clear the context in the HMC */
2447 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2448 if (err) {
2449 dev_info(&vsi->back->pdev->dev,
2450 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2451 ring->queue_index, pf_q, err);
2452 return -ENOMEM;
2453 }
2454
2455 /* set the context in the HMC */
2456 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2457 if (err) {
2458 dev_info(&vsi->back->pdev->dev,
2459 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2460 ring->queue_index, pf_q, err);
2461 return -ENOMEM;
2462 }
2463
2464 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2465 if (vsi->type == I40E_VSI_VMDQ2)
2466 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2467 else
2468 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2469 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2470 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2471 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2472 i40e_flush(hw);
2473
2474 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2475
2476 /* cache tail off for easier writes later */
2477 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2478
2479 return 0;
2480}
2481
2482/**
2483 * i40e_configure_rx_ring - Configure a receive ring context
2484 * @ring: The Rx ring to configure
2485 *
2486 * Configure the Rx descriptor ring in the HMC context.
2487 **/
2488static int i40e_configure_rx_ring(struct i40e_ring *ring)
2489{
2490 struct i40e_vsi *vsi = ring->vsi;
2491 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2492 u16 pf_q = vsi->base_queue + ring->queue_index;
2493 struct i40e_hw *hw = &vsi->back->hw;
2494 struct i40e_hmc_obj_rxq rx_ctx;
2495 i40e_status err = 0;
2496
2497 ring->state = 0;
2498
2499 /* clear the context structure first */
2500 memset(&rx_ctx, 0, sizeof(rx_ctx));
2501
2502 ring->rx_buf_len = vsi->rx_buf_len;
2503 ring->rx_hdr_len = vsi->rx_hdr_len;
2504
2505 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2506 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2507
2508 rx_ctx.base = (ring->dma / 128);
2509 rx_ctx.qlen = ring->count;
2510
2511 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2512 set_ring_16byte_desc_enabled(ring);
2513 rx_ctx.dsize = 0;
2514 } else {
2515 rx_ctx.dsize = 1;
2516 }
2517
2518 rx_ctx.dtype = vsi->dtype;
2519 if (vsi->dtype) {
2520 set_ring_ps_enabled(ring);
2521 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2522 I40E_RX_SPLIT_IP |
2523 I40E_RX_SPLIT_TCP_UDP |
2524 I40E_RX_SPLIT_SCTP;
2525 } else {
2526 rx_ctx.hsplit_0 = 0;
2527 }
2528
2529 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2530 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2531 if (hw->revision_id == 0)
2532 rx_ctx.lrxqthresh = 0;
2533 else
2534 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2535 rx_ctx.crcstrip = 1;
2536 rx_ctx.l2tsel = 1;
2537 rx_ctx.showiv = 1;
38e00438
VD		 2538#ifdef I40E_FCOE
2539 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2540#endif
acb3676b
CS		 2541 /* set the prefena field to 1 because the manual says to */
2542 rx_ctx.prefena = 1;
41c445ff
JB		 2543
2544 /* clear the context in the HMC */
2545 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2546 if (err) {
2547 dev_info(&vsi->back->pdev->dev,
2548 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2549 ring->queue_index, pf_q, err);
2550 return -ENOMEM;
2551 }
2552
2553 /* set the context in the HMC */
2554 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2555 if (err) {
2556 dev_info(&vsi->back->pdev->dev,
2557 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2558 ring->queue_index, pf_q, err);
2559 return -ENOMEM;
2560 }
2561
2562 /* cache tail for quicker writes, and clear the reg before use */
2563 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2564 writel(0, ring->tail);
2565
2566 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2567
2568 return 0;
2569}
2570
2571/**
2572 * i40e_vsi_configure_tx - Configure the VSI for Tx
2573 * @vsi: VSI structure describing this set of rings and resources
2574 *
2575 * Configure the Tx VSI for operation.
2576 **/
2577static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2578{
2579 int err = 0;
2580 u16 i;
2581
9f65e15b
AD		 2582 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2583 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2584
2585 return err;
2586}
2587
2588/**
2589 * i40e_vsi_configure_rx - Configure the VSI for Rx
2590 * @vsi: the VSI being configured
2591 *
2592 * Configure the Rx VSI for operation.
2593 **/
2594static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2595{
2596 int err = 0;
2597 u16 i;
2598
2599 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2600 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2601 + ETH_FCS_LEN + VLAN_HLEN;
2602 else
2603 vsi->max_frame = I40E_RXBUFFER_2048;
2604
2605 /* figure out correct receive buffer length */
2606 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2607 I40E_FLAG_RX_PS_ENABLED)) {
2608 case I40E_FLAG_RX_1BUF_ENABLED:
2609 vsi->rx_hdr_len = 0;
2610 vsi->rx_buf_len = vsi->max_frame;
2611 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2612 break;
2613 case I40E_FLAG_RX_PS_ENABLED:
2614 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2615 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2616 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2617 break;
2618 default:
2619 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2620 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2621 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2622 break;
2623 }
2624
38e00438
VD		 2625#ifdef I40E_FCOE
2626 /* setup rx buffer for FCoE */
2627 if ((vsi->type == I40E_VSI_FCOE) &&
2628 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2629 vsi->rx_hdr_len = 0;
2630 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2631 vsi->max_frame = I40E_RXBUFFER_3072;
2632 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2633 }
2634
2635#endif /* I40E_FCOE */
41c445ff
JB		 2636 /* round up for the chip's needs */
2637 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2638 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2639 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2640 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2641
2642 /* set up individual rings */
2643 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2644 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2645
2646 return err;
2647}
2648
2649/**
2650 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2651 * @vsi: ptr to the VSI
2652 **/
2653static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2654{
e7046ee1 2655 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2656 u16 qoffset, qcount;
2657 int i, n;
2658
2659 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2660 return;
2661
2662 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2663 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2664 continue;
2665
2666 qoffset = vsi->tc_config.tc_info[n].qoffset;
2667 qcount = vsi->tc_config.tc_info[n].qcount;
2668 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2669 rx_ring = vsi->rx_rings[i];
2670 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2671 rx_ring->dcb_tc = n;
2672 tx_ring->dcb_tc = n;
2673 }
2674 }
2675}
2676
2677/**
2678 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2679 * @vsi: ptr to the VSI
2680 **/
2681static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2682{
2683 if (vsi->netdev)
2684 i40e_set_rx_mode(vsi->netdev);
2685}
2686
17a73f6b
JG		 2687/**
2688 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2689 * @vsi: Pointer to the targeted VSI
2690 *
2691 * This function replays the hlist on the hw where all the SB Flow Director
2692 * filters were saved.
2693 **/
2694static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2695{
2696 struct i40e_fdir_filter *filter;
2697 struct i40e_pf *pf = vsi->back;
2698 struct hlist_node *node;
2699
55a5e60b
ASJ		 2700 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2701 return;
2702
17a73f6b
JG		 2703 hlist_for_each_entry_safe(filter, node,
2704 &pf->fdir_filter_list, fdir_node) {
2705 i40e_add_del_fdir(vsi, filter, true);
2706 }
2707}
2708
41c445ff
JB		 2709/**
2710 * i40e_vsi_configure - Set up the VSI for action
2711 * @vsi: the VSI being configured
2712 **/
2713static int i40e_vsi_configure(struct i40e_vsi *vsi)
2714{
2715 int err;
2716
2717 i40e_set_vsi_rx_mode(vsi);
2718 i40e_restore_vlan(vsi);
2719 i40e_vsi_config_dcb_rings(vsi);
2720 err = i40e_vsi_configure_tx(vsi);
2721 if (!err)
2722 err = i40e_vsi_configure_rx(vsi);
2723
2724 return err;
2725}
2726
2727/**
2728 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2729 * @vsi: the VSI being configured
2730 **/
2731static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2732{
2733 struct i40e_pf *pf = vsi->back;
2734 struct i40e_q_vector *q_vector;
2735 struct i40e_hw *hw = &pf->hw;
2736 u16 vector;
2737 int i, q;
2738 u32 val;
2739 u32 qp;
2740
2741 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2742 * and PFINT_LNKLSTn registers, e.g.:
2743 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2744 */
2745 qp = vsi->base_queue;
2746 vector = vsi->base_vector;
493fb300
AD		 2747 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2748 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2749 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2750 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2751 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2752 q_vector->rx.itr);
2753 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2754 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2755 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2756 q_vector->tx.itr);
2757
2758 /* Linked list for the queuepairs assigned to this vector */
2759 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2760 for (q = 0; q < q_vector->num_ringpairs; q++) {
2761 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2762 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2763 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2764 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2765 (I40E_QUEUE_TYPE_TX
2766 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2767
2768 wr32(hw, I40E_QINT_RQCTL(qp), val);
2769
2770 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2771 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2772 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2773 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2774 (I40E_QUEUE_TYPE_RX
2775 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2776
2777 /* Terminate the linked list */
2778 if (q == (q_vector->num_ringpairs - 1))
2779 val |= (I40E_QUEUE_END_OF_LIST
2780 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2781
2782 wr32(hw, I40E_QINT_TQCTL(qp), val);
2783 qp++;
2784 }
2785 }
2786
2787 i40e_flush(hw);
2788}
2789
2790/**
2791 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2792 * @hw: ptr to the hardware info
2793 **/
2794static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2795{
2796 u32 val;
2797
2798 /* clear things first */
2799 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2800 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2801
2802 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2803 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2804 I40E_PFINT_ICR0_ENA_GRST_MASK |
2805 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2806 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2807 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2808 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2809 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2810 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2811
2812 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2813
2814 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2815 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2816 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2817
2818 /* OTHER_ITR_IDX = 0 */
2819 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2820}
2821
2822/**
2823 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2824 * @vsi: the VSI being configured
2825 **/
2826static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2827{
493fb300 2828 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2829 struct i40e_pf *pf = vsi->back;
2830 struct i40e_hw *hw = &pf->hw;
2831 u32 val;
2832
2833 /* set the ITR configuration */
2834 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2835 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2836 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2837 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2838 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2839 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2840
2841 i40e_enable_misc_int_causes(hw);
2842
2843 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2844 wr32(hw, I40E_PFINT_LNKLST0, 0);
2845
f29eaa3d 2846 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2847 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2848 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2849 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2850
2851 wr32(hw, I40E_QINT_RQCTL(0), val);
2852
2853 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2854 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2855 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2856
2857 wr32(hw, I40E_QINT_TQCTL(0), val);
2858 i40e_flush(hw);
2859}
2860
2ef28cfb
MW		 2861/**
2862 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2863 * @pf: board private structure
2864 **/
2865void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2866{
2867 struct i40e_hw *hw = &pf->hw;
2868
2869 wr32(hw, I40E_PFINT_DYN_CTL0,
2870 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2871 i40e_flush(hw);
2872}
2873
41c445ff
JB		 2874/**
2875 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2876 * @pf: board private structure
2877 **/
116a57d4 2878void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2879{
2880 struct i40e_hw *hw = &pf->hw;
2881 u32 val;
2882
2883 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2884 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2885 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2886
2887 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2888 i40e_flush(hw);
2889}
2890
2891/**
2892 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2893 * @vsi: pointer to a vsi
2894 * @vector: enable a particular Hw Interrupt vector
2895 **/
2896void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2897{
2898 struct i40e_pf *pf = vsi->back;
2899 struct i40e_hw *hw = &pf->hw;
2900 u32 val;
2901
2902 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2903 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2904 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2905 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2906 /* skip the flush */
41c445ff
JB		 2907}
2908
5c2cebda
CW		 2909/**
2910 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2911 * @vsi: pointer to a vsi
2912 * @vector: enable a particular Hw Interrupt vector
2913 **/
2914void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2915{
2916 struct i40e_pf *pf = vsi->back;
2917 struct i40e_hw *hw = &pf->hw;
2918 u32 val;
2919
2920 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2921 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2922 i40e_flush(hw);
2923}
2924
41c445ff
JB		 2925/**
2926 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2927 * @irq: interrupt number
2928 * @data: pointer to a q_vector
2929 **/
2930static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2931{
2932 struct i40e_q_vector *q_vector = data;
2933
cd0b6fa6 2934 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2935 return IRQ_HANDLED;
2936
2937 napi_schedule(&q_vector->napi);
2938
2939 return IRQ_HANDLED;
2940}
2941
41c445ff
JB		 2942/**
2943 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2944 * @vsi: the VSI being configured
2945 * @basename: name for the vector
2946 *
2947 * Allocates MSI-X vectors and requests interrupts from the kernel.
2948 **/
2949static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2950{
2951 int q_vectors = vsi->num_q_vectors;
2952 struct i40e_pf *pf = vsi->back;
2953 int base = vsi->base_vector;
2954 int rx_int_idx = 0;
2955 int tx_int_idx = 0;
2956 int vector, err;
2957
2958 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2959 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2960
cd0b6fa6 2961 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2962 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2963 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2964 tx_int_idx++;
cd0b6fa6 2965 } else if (q_vector->rx.ring) {
41c445ff
JB		 2966 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2967 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2968 } else if (q_vector->tx.ring) {
41c445ff
JB		 2969 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2970 "%s-%s-%d", basename, "tx", tx_int_idx++);
2971 } else {
2972 /* skip this unused q_vector */
2973 continue;
2974 }
2975 err = request_irq(pf->msix_entries[base + vector].vector,
2976 vsi->irq_handler,
2977 0,
2978 q_vector->name,
2979 q_vector);
2980 if (err) {
2981 dev_info(&pf->pdev->dev,
2982 "%s: request_irq failed, error: %d\n",
2983 __func__, err);
2984 goto free_queue_irqs;
2985 }
2986 /* assign the mask for this irq */
2987 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2988 &q_vector->affinity_mask);
2989 }
2990
63741846 2991 vsi->irqs_ready = true;
41c445ff
JB		 2992 return 0;
2993
2994free_queue_irqs:
2995 while (vector) {
2996 vector--;
2997 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2998 NULL);
2999 free_irq(pf->msix_entries[base + vector].vector,
3000 &(vsi->q_vectors[vector]));
3001 }
3002 return err;
3003}
3004
3005/**
3006 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3007 * @vsi: the VSI being un-configured
3008 **/
3009static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3010{
3011 struct i40e_pf *pf = vsi->back;
3012 struct i40e_hw *hw = &pf->hw;
3013 int base = vsi->base_vector;
3014 int i;
3015
3016 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3017 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3018 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3019 }
3020
3021 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3022 for (i = vsi->base_vector;
3023 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3024 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3025
3026 i40e_flush(hw);
3027 for (i = 0; i < vsi->num_q_vectors; i++)
3028 synchronize_irq(pf->msix_entries[i + base].vector);
3029 } else {
3030 /* Legacy and MSI mode - this stops all interrupt handling */
3031 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3032 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3033 i40e_flush(hw);
3034 synchronize_irq(pf->pdev->irq);
3035 }
3036}
3037
3038/**
3039 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3040 * @vsi: the VSI being configured
3041 **/
3042static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3043{
3044 struct i40e_pf *pf = vsi->back;
3045 int i;
3046
3047 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3048 for (i = vsi->base_vector;
3049 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3050 i40e_irq_dynamic_enable(vsi, i);
3051 } else {
3052 i40e_irq_dynamic_enable_icr0(pf);
3053 }
3054
1022cb6c 3055 i40e_flush(&pf->hw);
41c445ff
JB		 3056 return 0;
3057}
3058
3059/**
3060 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3061 * @pf: board private structure
3062 **/
3063static void i40e_stop_misc_vector(struct i40e_pf *pf)
3064{
3065 /* Disable ICR 0 */
3066 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3067 i40e_flush(&pf->hw);
3068}
3069
3070/**
3071 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3072 * @irq: interrupt number
3073 * @data: pointer to a q_vector
3074 *
3075 * This is the handler used for all MSI/Legacy interrupts, and deals
3076 * with both queue and non-queue interrupts. This is also used in
3077 * MSIX mode to handle the non-queue interrupts.
3078 **/
3079static irqreturn_t i40e_intr(int irq, void *data)
3080{
3081 struct i40e_pf *pf = (struct i40e_pf *)data;
3082 struct i40e_hw *hw = &pf->hw;
5e823066 3083 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3084 u32 icr0, icr0_remaining;
3085 u32 val, ena_mask;
3086
3087 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3088 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3089
116a57d4
SN		 3090 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3091 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3092 goto enable_intr;
41c445ff 3093
cd92e72f
SN		 3094 /* if interrupt but no bits showing, must be SWINT */
3095 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3096 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3097 pf->sw_int_count++;
3098
41c445ff
JB		 3099 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3100 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3101
3102 /* temporarily disable queue cause for NAPI processing */
3103 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3104 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3105 wr32(hw, I40E_QINT_RQCTL(0), qval);
3106
3107 qval = rd32(hw, I40E_QINT_TQCTL(0));
3108 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3109 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3110
3111 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3112 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3113 }
3114
3115 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3116 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3117 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3118 }
3119
3120 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3121 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3122 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3123 }
3124
3125 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3126 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3127 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3128 }
3129
3130 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3131 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3132 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3133 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3134 val = rd32(hw, I40E_GLGEN_RSTAT);
3135 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3136 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3137 if (val == I40E_RESET_CORER) {
41c445ff 3138 pf->corer_count++;
4eb3f768 3139 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3140 pf->globr_count++;
4eb3f768 3141 } else if (val == I40E_RESET_EMPR) {
41c445ff 3142 pf->empr_count++;
4eb3f768
SN		 3143 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3144 }
41c445ff
JB		 3145 }
3146
9c010ee0
ASJ		 3147 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3148 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3149 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3150 }
3151
beb0dff1
JK		 3152 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3153 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3154
3155 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3156 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3157 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3158 }
beb0dff1
JK		 3159 }
3160
41c445ff
JB		 3161 /* If a critical error is pending we have no choice but to reset the
3162 * device.
3163 * Report and mask out any remaining unexpected interrupts.
3164 */
3165 icr0_remaining = icr0 & ena_mask;
3166 if (icr0_remaining) {
3167 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3168 icr0_remaining);
9c010ee0 3169 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3170 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3171 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3172 dev_info(&pf->pdev->dev, "device will be reset\n");
3173 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3174 i40e_service_event_schedule(pf);
41c445ff
JB		 3175 }
3176 ena_mask &= ~icr0_remaining;
3177 }
5e823066 3178 ret = IRQ_HANDLED;
41c445ff 3179
5e823066 3180enable_intr:
41c445ff
JB		 3181 /* re-enable interrupt causes */
3182 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3183 if (!test_bit(__I40E_DOWN, &pf->state)) {
3184 i40e_service_event_schedule(pf);
3185 i40e_irq_dynamic_enable_icr0(pf);
3186 }
3187
5e823066 3188 return ret;
41c445ff
JB		 3189}
3190
cbf61325
ASJ		 3191/**
3192 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3193 * @tx_ring: tx ring to clean
3194 * @budget: how many cleans we're allowed
3195 *
3196 * Returns true if there's any budget left (e.g. the clean is finished)
3197 **/
3198static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3199{
3200 struct i40e_vsi *vsi = tx_ring->vsi;
3201 u16 i = tx_ring->next_to_clean;
3202 struct i40e_tx_buffer *tx_buf;
3203 struct i40e_tx_desc *tx_desc;
3204
3205 tx_buf = &tx_ring->tx_bi[i];
3206 tx_desc = I40E_TX_DESC(tx_ring, i);
3207 i -= tx_ring->count;
3208
3209 do {
3210 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3211
3212 /* if next_to_watch is not set then there is no work pending */
3213 if (!eop_desc)
3214 break;
3215
3216 /* prevent any other reads prior to eop_desc */
3217 read_barrier_depends();
3218
3219 /* if the descriptor isn't done, no work yet to do */
3220 if (!(eop_desc->cmd_type_offset_bsz &
3221 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3222 break;
3223
3224 /* clear next_to_watch to prevent false hangs */
3225 tx_buf->next_to_watch = NULL;
3226
49d7d933
ASJ		 3227 tx_desc->buffer_addr = 0;
3228 tx_desc->cmd_type_offset_bsz = 0;
3229 /* move past filter desc */
3230 tx_buf++;
3231 tx_desc++;
3232 i++;
3233 if (unlikely(!i)) {
3234 i -= tx_ring->count;
3235 tx_buf = tx_ring->tx_bi;
3236 tx_desc = I40E_TX_DESC(tx_ring, 0);
3237 }
cbf61325
ASJ		 3238 /* unmap skb header data */
3239 dma_unmap_single(tx_ring->dev,
3240 dma_unmap_addr(tx_buf, dma),
3241 dma_unmap_len(tx_buf, len),
3242 DMA_TO_DEVICE);
49d7d933
ASJ		 3243 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3244 kfree(tx_buf->raw_buf);
cbf61325 3245
49d7d933
ASJ		 3246 tx_buf->raw_buf = NULL;
3247 tx_buf->tx_flags = 0;
3248 tx_buf->next_to_watch = NULL;
cbf61325 3249 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3250 tx_desc->buffer_addr = 0;
3251 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3252
49d7d933 3253 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3254 tx_buf++;
3255 tx_desc++;
3256 i++;
3257 if (unlikely(!i)) {
3258 i -= tx_ring->count;
3259 tx_buf = tx_ring->tx_bi;
3260 tx_desc = I40E_TX_DESC(tx_ring, 0);
3261 }
3262
3263 /* update budget accounting */
3264 budget--;
3265 } while (likely(budget));
3266
3267 i += tx_ring->count;
3268 tx_ring->next_to_clean = i;
3269
3270 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3271 i40e_irq_dynamic_enable(vsi,
3272 tx_ring->q_vector->v_idx + vsi->base_vector);
3273 }
3274 return budget > 0;
3275}
3276
3277/**
3278 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3279 * @irq: interrupt number
3280 * @data: pointer to a q_vector
3281 **/
3282static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3283{
3284 struct i40e_q_vector *q_vector = data;
3285 struct i40e_vsi *vsi;
3286
3287 if (!q_vector->tx.ring)
3288 return IRQ_HANDLED;
3289
3290 vsi = q_vector->tx.ring->vsi;
3291 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3292
3293 return IRQ_HANDLED;
3294}
3295
41c445ff 3296/**
cd0b6fa6 3297 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3298 * @vsi: the VSI being configured
3299 * @v_idx: vector index
cd0b6fa6 3300 * @qp_idx: queue pair index
41c445ff 3301 **/
cd0b6fa6 3302static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3303{
493fb300 3304 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3305 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3306 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3307
3308 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3309 tx_ring->next = q_vector->tx.ring;
3310 q_vector->tx.ring = tx_ring;
41c445ff 3311 q_vector->tx.count++;
cd0b6fa6
AD		 3312
3313 rx_ring->q_vector = q_vector;
3314 rx_ring->next = q_vector->rx.ring;
3315 q_vector->rx.ring = rx_ring;
3316 q_vector->rx.count++;
41c445ff
JB		 3317}
3318
3319/**
3320 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3321 * @vsi: the VSI being configured
3322 *
3323 * This function maps descriptor rings to the queue-specific vectors
3324 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3325 * one vector per queue pair, but on a constrained vector budget, we
3326 * group the queue pairs as "efficiently" as possible.
3327 **/
3328static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3329{
3330 int qp_remaining = vsi->num_queue_pairs;
3331 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3332 int num_ringpairs;
41c445ff
JB		 3333 int v_start = 0;
3334 int qp_idx = 0;
3335
3336 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3337 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3338 * It is also important to go through all the vectors available to be
3339 * sure that if we don't use all the vectors, that the remaining vectors
3340 * are cleared. This is especially important when decreasing the
3341 * number of queues in use.
41c445ff 3342 */
70114ec4 3343 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3344 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3345
3346 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3347
3348 q_vector->num_ringpairs = num_ringpairs;
3349
3350 q_vector->rx.count = 0;
3351 q_vector->tx.count = 0;
3352 q_vector->rx.ring = NULL;
3353 q_vector->tx.ring = NULL;
3354
3355 while (num_ringpairs--) {
3356 map_vector_to_qp(vsi, v_start, qp_idx);
3357 qp_idx++;
3358 qp_remaining--;
41c445ff
JB		 3359 }
3360 }
3361}
3362
3363/**
3364 * i40e_vsi_request_irq - Request IRQ from the OS
3365 * @vsi: the VSI being configured
3366 * @basename: name for the vector
3367 **/
3368static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3369{
3370 struct i40e_pf *pf = vsi->back;
3371 int err;
3372
3373 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3374 err = i40e_vsi_request_irq_msix(vsi, basename);
3375 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3376 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3377 pf->misc_int_name, pf);
3378 else
3379 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3380 pf->misc_int_name, pf);
3381
3382 if (err)
3383 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3384
3385 return err;
3386}
3387
3388#ifdef CONFIG_NET_POLL_CONTROLLER
3389/**
3390 * i40e_netpoll - A Polling 'interrupt'handler
3391 * @netdev: network interface device structure
3392 *
3393 * This is used by netconsole to send skbs without having to re-enable
3394 * interrupts. It's not called while the normal interrupt routine is executing.
3395 **/
38e00438
VD		 3396#ifdef I40E_FCOE
3397void i40e_netpoll(struct net_device *netdev)
3398#else
41c445ff 3399static void i40e_netpoll(struct net_device *netdev)
38e00438 3400#endif
41c445ff
JB		 3401{
3402 struct i40e_netdev_priv *np = netdev_priv(netdev);
3403 struct i40e_vsi *vsi = np->vsi;
3404 struct i40e_pf *pf = vsi->back;
3405 int i;
3406
3407 /* if interface is down do nothing */
3408 if (test_bit(__I40E_DOWN, &vsi->state))
3409 return;
3410
3411 pf->flags |= I40E_FLAG_IN_NETPOLL;
3412 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3413 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3414 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3415 } else {
3416 i40e_intr(pf->pdev->irq, netdev);
3417 }
3418 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3419}
3420#endif
3421
23527308
NP		 3422/**
3423 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3424 * @pf: the PF being configured
3425 * @pf_q: the PF queue
3426 * @enable: enable or disable state of the queue
3427 *
3428 * This routine will wait for the given Tx queue of the PF to reach the
3429 * enabled or disabled state.
3430 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3431 * multiple retries; else will return 0 in case of success.
3432 **/
3433static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3434{
3435 int i;
3436 u32 tx_reg;
3437
3438 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3439 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3440 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3441 break;
3442
f98a2006 3443 usleep_range(10, 20);
23527308
NP		 3444 }
3445 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3446 return -ETIMEDOUT;
3447
3448 return 0;
3449}
3450
41c445ff
JB		 3451/**
3452 * i40e_vsi_control_tx - Start or stop a VSI's rings
3453 * @vsi: the VSI being configured
3454 * @enable: start or stop the rings
3455 **/
3456static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3457{
3458 struct i40e_pf *pf = vsi->back;
3459 struct i40e_hw *hw = &pf->hw;
23527308 3460 int i, j, pf_q, ret = 0;
41c445ff
JB		 3461 u32 tx_reg;
3462
3463 pf_q = vsi->base_queue;
3464 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3465
3466 /* warn the TX unit of coming changes */
3467 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3468 if (!enable)
f98a2006 3469 usleep_range(10, 20);
351499ab 3470
6c5ef620 3471 for (j = 0; j < 50; j++) {
41c445ff 3472 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3473 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3474 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3475 break;
3476 usleep_range(1000, 2000);
3477 }
fda972f6 3478 /* Skip if the queue is already in the requested state */
7c122007 3479 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3480 continue;
41c445ff
JB		 3481
3482 /* turn on/off the queue */
c5c9eb9e
SN		 3483 if (enable) {
3484 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3485 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3486 } else {
41c445ff 3487 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3488 }
41c445ff
JB		 3489
3490 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3491
3492 /* wait for the change to finish */
23527308
NP		 3493 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3494 if (ret) {
3495 dev_info(&pf->pdev->dev,
3496 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3497 __func__, vsi->seid, pf_q,
3498 (enable ? "en" : "dis"));
3499 break;
41c445ff
JB		 3500 }
3501 }
3502
7134f9ce
JB		 3503 if (hw->revision_id == 0)
3504 mdelay(50);
23527308
NP		 3505 return ret;
3506}
3507
3508/**
3509 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3510 * @pf: the PF being configured
3511 * @pf_q: the PF queue
3512 * @enable: enable or disable state of the queue
3513 *
3514 * This routine will wait for the given Rx queue of the PF to reach the
3515 * enabled or disabled state.
3516 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3517 * multiple retries; else will return 0 in case of success.
3518 **/
3519static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3520{
3521 int i;
3522 u32 rx_reg;
3523
3524 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3525 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3526 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3527 break;
3528
f98a2006 3529 usleep_range(10, 20);
23527308
NP		 3530 }
3531 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3532 return -ETIMEDOUT;
7134f9ce 3533
41c445ff
JB		 3534 return 0;
3535}
3536
3537/**
3538 * i40e_vsi_control_rx - Start or stop a VSI's rings
3539 * @vsi: the VSI being configured
3540 * @enable: start or stop the rings
3541 **/
3542static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3543{
3544 struct i40e_pf *pf = vsi->back;
3545 struct i40e_hw *hw = &pf->hw;
23527308 3546 int i, j, pf_q, ret = 0;
41c445ff
JB		 3547 u32 rx_reg;
3548
3549 pf_q = vsi->base_queue;
3550 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3551 for (j = 0; j < 50; j++) {
41c445ff 3552 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3553 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3554 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3555 break;
3556 usleep_range(1000, 2000);
3557 }
41c445ff 3558
7c122007
CS		 3559 /* Skip if the queue is already in the requested state */
3560 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3561 continue;
41c445ff
JB		 3562
3563 /* turn on/off the queue */
3564 if (enable)
6c5ef620 3565 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3566 else
6c5ef620 3567 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3568 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3569
3570 /* wait for the change to finish */
23527308
NP		 3571 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3572 if (ret) {
3573 dev_info(&pf->pdev->dev,
3574 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3575 __func__, vsi->seid, pf_q,
3576 (enable ? "en" : "dis"));
3577 break;
41c445ff
JB		 3578 }
3579 }
3580
23527308 3581 return ret;
41c445ff
JB		 3582}
3583
3584/**
3585 * i40e_vsi_control_rings - Start or stop a VSI's rings
3586 * @vsi: the VSI being configured
3587 * @enable: start or stop the rings
3588 **/
fc18eaa0 3589int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3590{
3b867b28 3591 int ret = 0;
41c445ff
JB		 3592
3593 /* do rx first for enable and last for disable */
3594 if (request) {
3595 ret = i40e_vsi_control_rx(vsi, request);
3596 if (ret)
3597 return ret;
3598 ret = i40e_vsi_control_tx(vsi, request);
3599 } else {
3b867b28
ASJ		 3600 /* Ignore return value, we need to shutdown whatever we can */
3601 i40e_vsi_control_tx(vsi, request);
3602 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3603 }
3604
3605 return ret;
3606}
3607
3608/**
3609 * i40e_vsi_free_irq - Free the irq association with the OS
3610 * @vsi: the VSI being configured
3611 **/
3612static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3613{
3614 struct i40e_pf *pf = vsi->back;
3615 struct i40e_hw *hw = &pf->hw;
3616 int base = vsi->base_vector;
3617 u32 val, qp;
3618 int i;
3619
3620 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3621 if (!vsi->q_vectors)
3622 return;
3623
63741846
SN		 3624 if (!vsi->irqs_ready)
3625 return;
3626
3627 vsi->irqs_ready = false;
41c445ff
JB		 3628 for (i = 0; i < vsi->num_q_vectors; i++) {
3629 u16 vector = i + base;
3630
3631 /* free only the irqs that were actually requested */
78681b1f
SN		 3632 if (!vsi->q_vectors[i] ||
3633 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3634 continue;
3635
3636 /* clear the affinity_mask in the IRQ descriptor */
3637 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3638 NULL);
3639 free_irq(pf->msix_entries[vector].vector,
493fb300 3640 vsi->q_vectors[i]);
41c445ff
JB		 3641
3642 /* Tear down the interrupt queue link list
3643 *
3644 * We know that they come in pairs and always
3645 * the Rx first, then the Tx. To clear the
3646 * link list, stick the EOL value into the
3647 * next_q field of the registers.
3648 */
3649 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3650 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3651 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3652 val |= I40E_QUEUE_END_OF_LIST
3653 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3654 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3655
3656 while (qp != I40E_QUEUE_END_OF_LIST) {
3657 u32 next;
3658
3659 val = rd32(hw, I40E_QINT_RQCTL(qp));
3660
3661 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3662 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3663 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3664 I40E_QINT_RQCTL_INTEVENT_MASK);
3665
3666 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3667 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3668
3669 wr32(hw, I40E_QINT_RQCTL(qp), val);
3670
3671 val = rd32(hw, I40E_QINT_TQCTL(qp));
3672
3673 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3674 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3675
3676 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3677 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3678 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3679 I40E_QINT_TQCTL_INTEVENT_MASK);
3680
3681 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3682 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3683
3684 wr32(hw, I40E_QINT_TQCTL(qp), val);
3685 qp = next;
3686 }
3687 }
3688 } else {
3689 free_irq(pf->pdev->irq, pf);
3690
3691 val = rd32(hw, I40E_PFINT_LNKLST0);
3692 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3693 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3694 val |= I40E_QUEUE_END_OF_LIST
3695 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3696 wr32(hw, I40E_PFINT_LNKLST0, val);
3697
3698 val = rd32(hw, I40E_QINT_RQCTL(qp));
3699 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3700 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3701 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3702 I40E_QINT_RQCTL_INTEVENT_MASK);
3703
3704 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3705 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3706
3707 wr32(hw, I40E_QINT_RQCTL(qp), val);
3708
3709 val = rd32(hw, I40E_QINT_TQCTL(qp));
3710
3711 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3712 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3713 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3714 I40E_QINT_TQCTL_INTEVENT_MASK);
3715
3716 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3717 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3718
3719 wr32(hw, I40E_QINT_TQCTL(qp), val);
3720 }
3721}
3722
493fb300
AD		 3723/**
3724 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3725 * @vsi: the VSI being configured
3726 * @v_idx: Index of vector to be freed
3727 *
3728 * This function frees the memory allocated to the q_vector. In addition if
3729 * NAPI is enabled it will delete any references to the NAPI struct prior
3730 * to freeing the q_vector.
3731 **/
3732static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3733{
3734 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3735 struct i40e_ring *ring;
493fb300
AD		 3736
3737 if (!q_vector)
3738 return;
3739
3740 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3741 i40e_for_each_ring(ring, q_vector->tx)
3742 ring->q_vector = NULL;
3743
3744 i40e_for_each_ring(ring, q_vector->rx)
3745 ring->q_vector = NULL;
493fb300
AD		 3746
3747 /* only VSI w/ an associated netdev is set up w/ NAPI */
3748 if (vsi->netdev)
3749 netif_napi_del(&q_vector->napi);
3750
3751 vsi->q_vectors[v_idx] = NULL;
3752
3753 kfree_rcu(q_vector, rcu);
3754}
3755
41c445ff
JB		 3756/**
3757 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3758 * @vsi: the VSI being un-configured
3759 *
3760 * This frees the memory allocated to the q_vectors and
3761 * deletes references to the NAPI struct.
3762 **/
3763static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3764{
3765 int v_idx;
3766
493fb300
AD		 3767 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3768 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3769}
3770
3771/**
3772 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3773 * @pf: board private structure
3774 **/
3775static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3776{
3777 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3778 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3779 pci_disable_msix(pf->pdev);
3780 kfree(pf->msix_entries);
3781 pf->msix_entries = NULL;
3782 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3783 pci_disable_msi(pf->pdev);
3784 }
3785 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3786}
3787
3788/**
3789 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3790 * @pf: board private structure
3791 *
3792 * We go through and clear interrupt specific resources and reset the structure
3793 * to pre-load conditions
3794 **/
3795static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3796{
3797 int i;
3798
3799 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3800 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3801 if (pf->vsi[i])
3802 i40e_vsi_free_q_vectors(pf->vsi[i]);
3803 i40e_reset_interrupt_capability(pf);
3804}
3805
3806/**
3807 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3808 * @vsi: the VSI being configured
3809 **/
3810static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3811{
3812 int q_idx;
3813
3814 if (!vsi->netdev)
3815 return;
3816
3817 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3818 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3819}
3820
3821/**
3822 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3823 * @vsi: the VSI being configured
3824 **/
3825static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3826{
3827 int q_idx;
3828
3829 if (!vsi->netdev)
3830 return;
3831
3832 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3833 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3834}
3835
90ef8d47
SN		 3836/**
3837 * i40e_vsi_close - Shut down a VSI
3838 * @vsi: the vsi to be quelled
3839 **/
3840static void i40e_vsi_close(struct i40e_vsi *vsi)
3841{
3842 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3843 i40e_down(vsi);
3844 i40e_vsi_free_irq(vsi);
3845 i40e_vsi_free_tx_resources(vsi);
3846 i40e_vsi_free_rx_resources(vsi);
3847}
3848
41c445ff
JB		 3849/**
3850 * i40e_quiesce_vsi - Pause a given VSI
3851 * @vsi: the VSI being paused
3852 **/
3853static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3854{
3855 if (test_bit(__I40E_DOWN, &vsi->state))
3856 return;
3857
3858 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3859 if (vsi->netdev && netif_running(vsi->netdev)) {
3860 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3861 } else {
90ef8d47 3862 i40e_vsi_close(vsi);
41c445ff
JB		 3863 }
3864}
3865
3866/**
3867 * i40e_unquiesce_vsi - Resume a given VSI
3868 * @vsi: the VSI being resumed
3869 **/
3870static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3871{
3872 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3873 return;
3874
3875 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3876 if (vsi->netdev && netif_running(vsi->netdev))
3877 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3878 else
8276f757 3879 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3880}
3881
3882/**
3883 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3884 * @pf: the PF
3885 **/
3886static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3887{
3888 int v;
3889
505682cd 3890 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3891 if (pf->vsi[v])
3892 i40e_quiesce_vsi(pf->vsi[v]);
3893 }
3894}
3895
3896/**
3897 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3898 * @pf: the PF
3899 **/
3900static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3901{
3902 int v;
3903
505682cd 3904 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3905 if (pf->vsi[v])
3906 i40e_unquiesce_vsi(pf->vsi[v]);
3907 }
3908}
3909
3910/**
3911 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3912 * @dcbcfg: the corresponding DCBx configuration structure
3913 *
3914 * Return the number of TCs from given DCBx configuration
3915 **/
3916static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3917{
078b5876
JB		 3918 u8 num_tc = 0;
3919 int i;
41c445ff
JB		 3920
3921 /* Scan the ETS Config Priority Table to find
3922 * traffic class enabled for a given priority
3923 * and use the traffic class index to get the
3924 * number of traffic classes enabled
3925 */
3926 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3927 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3928 num_tc = dcbcfg->etscfg.prioritytable[i];
3929 }
3930
3931 /* Traffic class index starts from zero so
3932 * increment to return the actual count
3933 */
078b5876 3934 return num_tc + 1;
41c445ff
JB		 3935}
3936
3937/**
3938 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3939 * @dcbcfg: the corresponding DCBx configuration structure
3940 *
3941 * Query the current DCB configuration and return the number of
3942 * traffic classes enabled from the given DCBX config
3943 **/
3944static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3945{
3946 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3947 u8 enabled_tc = 1;
3948 u8 i;
3949
3950 for (i = 0; i < num_tc; i++)
3951 enabled_tc |= 1 << i;
3952
3953 return enabled_tc;
3954}
3955
3956/**
3957 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3958 * @pf: PF being queried
3959 *
3960 * Return number of traffic classes enabled for the given PF
3961 **/
3962static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3963{
3964 struct i40e_hw *hw = &pf->hw;
3965 u8 i, enabled_tc;
3966 u8 num_tc = 0;
3967 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3968
3969 /* If DCB is not enabled then always in single TC */
3970 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3971 return 1;
3972
3973 /* MFP mode return count of enabled TCs for this PF */
3974 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3975 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3976 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3977 if (enabled_tc & (1 << i))
3978 num_tc++;
3979 }
3980 return num_tc;
3981 }
3982
3983 /* SFP mode will be enabled for all TCs on port */
3984 return i40e_dcb_get_num_tc(dcbcfg);
3985}
3986
3987/**
3988 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3989 * @pf: PF being queried
3990 *
3991 * Return a bitmap for first enabled traffic class for this PF.
3992 **/
3993static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3994{
3995 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3996 u8 i = 0;
3997
3998 if (!enabled_tc)
3999 return 0x1; /* TC0 */
4000
4001 /* Find the first enabled TC */
4002 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4003 if (enabled_tc & (1 << i))
4004 break;
4005 }
4006
4007 return 1 << i;
4008}
4009
4010/**
4011 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4012 * @pf: PF being queried
4013 *
4014 * Return a bitmap for enabled traffic classes for this PF.
4015 **/
4016static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4017{
4018 /* If DCB is not enabled for this PF then just return default TC */
4019 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4020 return i40e_pf_get_default_tc(pf);
4021
4022 /* MFP mode will have enabled TCs set by FW */
4023 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4024 return pf->hw.func_caps.enabled_tcmap;
4025
4026 /* SFP mode we want PF to be enabled for all TCs */
4027 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4028}
4029
4030/**
4031 * i40e_vsi_get_bw_info - Query VSI BW Information
4032 * @vsi: the VSI being queried
4033 *
4034 * Returns 0 on success, negative value on failure
4035 **/
4036static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4037{
4038 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4039 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4040 struct i40e_pf *pf = vsi->back;
4041 struct i40e_hw *hw = &pf->hw;
dcae29be 4042 i40e_status aq_ret;
41c445ff 4043 u32 tc_bw_max;
41c445ff
JB		 4044 int i;
4045
4046 /* Get the VSI level BW configuration */
dcae29be
JB		 4047 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4048 if (aq_ret) {
41c445ff
JB		 4049 dev_info(&pf->pdev->dev,
4050 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4051 aq_ret, pf->hw.aq.asq_last_status);
4052 return -EINVAL;
41c445ff
JB		 4053 }
4054
4055 /* Get the VSI level BW configuration per TC */
dcae29be 4056 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4057 NULL);
dcae29be 4058 if (aq_ret) {
41c445ff
JB		 4059 dev_info(&pf->pdev->dev,
4060 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4061 aq_ret, pf->hw.aq.asq_last_status);
4062 return -EINVAL;
41c445ff
JB		 4063 }
4064
4065 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4066 dev_info(&pf->pdev->dev,
4067 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4068 bw_config.tc_valid_bits,
4069 bw_ets_config.tc_valid_bits);
4070 /* Still continuing */
4071 }
4072
4073 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4074 vsi->bw_max_quanta = bw_config.max_bw;
4075 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4076 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4077 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4078 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4079 vsi->bw_ets_limit_credits[i] =
4080 le16_to_cpu(bw_ets_config.credits[i]);
4081 /* 3 bits out of 4 for each TC */
4082 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4083 }
078b5876 4084
dcae29be 4085 return 0;
41c445ff
JB		 4086}
4087
4088/**
4089 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4090 * @vsi: the VSI being configured
4091 * @enabled_tc: TC bitmap
4092 * @bw_credits: BW shared credits per TC
4093 *
4094 * Returns 0 on success, negative value on failure
4095 **/
dcae29be 4096static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4097 u8 *bw_share)
4098{
4099 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4100 i40e_status aq_ret;
4101 int i;
41c445ff
JB		 4102
4103 bw_data.tc_valid_bits = enabled_tc;
4104 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4105 bw_data.tc_bw_credits[i] = bw_share[i];
4106
dcae29be
JB		 4107 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4108 NULL);
4109 if (aq_ret) {
41c445ff 4110 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4111 "AQ command Config VSI BW allocation per TC failed = %d\n",
4112 vsi->back->hw.aq.asq_last_status);
dcae29be 4113 return -EINVAL;
41c445ff
JB		 4114 }
4115
4116 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4117 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4118
dcae29be 4119 return 0;
41c445ff
JB		 4120}
4121
4122/**
4123 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4124 * @vsi: the VSI being configured
4125 * @enabled_tc: TC map to be enabled
4126 *
4127 **/
4128static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4129{
4130 struct net_device *netdev = vsi->netdev;
4131 struct i40e_pf *pf = vsi->back;
4132 struct i40e_hw *hw = &pf->hw;
4133 u8 netdev_tc = 0;
4134 int i;
4135 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4136
4137 if (!netdev)
4138 return;
4139
4140 if (!enabled_tc) {
4141 netdev_reset_tc(netdev);
4142 return;
4143 }
4144
4145 /* Set up actual enabled TCs on the VSI */
4146 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4147 return;
4148
4149 /* set per TC queues for the VSI */
4150 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4151 /* Only set TC queues for enabled tcs
4152 *
4153 * e.g. For a VSI that has TC0 and TC3 enabled the
4154 * enabled_tc bitmap would be 0x00001001; the driver
4155 * will set the numtc for netdev as 2 that will be
4156 * referenced by the netdev layer as TC 0 and 1.
4157 */
4158 if (vsi->tc_config.enabled_tc & (1 << i))
4159 netdev_set_tc_queue(netdev,
4160 vsi->tc_config.tc_info[i].netdev_tc,
4161 vsi->tc_config.tc_info[i].qcount,
4162 vsi->tc_config.tc_info[i].qoffset);
4163 }
4164
4165 /* Assign UP2TC map for the VSI */
4166 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4167 /* Get the actual TC# for the UP */
4168 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4169 /* Get the mapped netdev TC# for the UP */
4170 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4171 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4172 }
4173}
4174
4175/**
4176 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4177 * @vsi: the VSI being configured
4178 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4179 **/
4180static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4181 struct i40e_vsi_context *ctxt)
4182{
4183 /* copy just the sections touched not the entire info
4184 * since not all sections are valid as returned by
4185 * update vsi params
4186 */
4187 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4188 memcpy(&vsi->info.queue_mapping,
4189 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4190 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4191 sizeof(vsi->info.tc_mapping));
4192}
4193
4194/**
4195 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4196 * @vsi: VSI to be configured
4197 * @enabled_tc: TC bitmap
4198 *
4199 * This configures a particular VSI for TCs that are mapped to the
4200 * given TC bitmap. It uses default bandwidth share for TCs across
4201 * VSIs to configure TC for a particular VSI.
4202 *
4203 * NOTE:
4204 * It is expected that the VSI queues have been quisced before calling
4205 * this function.
4206 **/
4207static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4208{
4209 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4210 struct i40e_vsi_context ctxt;
4211 int ret = 0;
4212 int i;
4213
4214 /* Check if enabled_tc is same as existing or new TCs */
4215 if (vsi->tc_config.enabled_tc == enabled_tc)
4216 return ret;
4217
4218 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4219 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4220 if (enabled_tc & (1 << i))
4221 bw_share[i] = 1;
4222 }
4223
4224 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4225 if (ret) {
4226 dev_info(&vsi->back->pdev->dev,
4227 "Failed configuring TC map %d for VSI %d\n",
4228 enabled_tc, vsi->seid);
4229 goto out;
4230 }
4231
4232 /* Update Queue Pairs Mapping for currently enabled UPs */
4233 ctxt.seid = vsi->seid;
4234 ctxt.pf_num = vsi->back->hw.pf_id;
4235 ctxt.vf_num = 0;
4236 ctxt.uplink_seid = vsi->uplink_seid;
4237 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4238 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4239
4240 /* Update the VSI after updating the VSI queue-mapping information */
4241 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4242 if (ret) {
4243 dev_info(&vsi->back->pdev->dev,
4244 "update vsi failed, aq_err=%d\n",
4245 vsi->back->hw.aq.asq_last_status);
4246 goto out;
4247 }
4248 /* update the local VSI info with updated queue map */
4249 i40e_vsi_update_queue_map(vsi, &ctxt);
4250 vsi->info.valid_sections = 0;
4251
4252 /* Update current VSI BW information */
4253 ret = i40e_vsi_get_bw_info(vsi);
4254 if (ret) {
4255 dev_info(&vsi->back->pdev->dev,
4256 "Failed updating vsi bw info, aq_err=%d\n",
4257 vsi->back->hw.aq.asq_last_status);
4258 goto out;
4259 }
4260
4261 /* Update the netdev TC setup */
4262 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4263out:
4264 return ret;
4265}
4266
4e3b35b0
NP		 4267/**
4268 * i40e_veb_config_tc - Configure TCs for given VEB
4269 * @veb: given VEB
4270 * @enabled_tc: TC bitmap
4271 *
4272 * Configures given TC bitmap for VEB (switching) element
4273 **/
4274int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4275{
4276 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4277 struct i40e_pf *pf = veb->pf;
4278 int ret = 0;
4279 int i;
4280
4281 /* No TCs or already enabled TCs just return */
4282 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4283 return ret;
4284
4285 bw_data.tc_valid_bits = enabled_tc;
4286 /* bw_data.absolute_credits is not set (relative) */
4287
4288 /* Enable ETS TCs with equal BW Share for now */
4289 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4290 if (enabled_tc & (1 << i))
4291 bw_data.tc_bw_share_credits[i] = 1;
4292 }
4293
4294 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4295 &bw_data, NULL);
4296 if (ret) {
4297 dev_info(&pf->pdev->dev,
4298 "veb bw config failed, aq_err=%d\n",
4299 pf->hw.aq.asq_last_status);
4300 goto out;
4301 }
4302
4303 /* Update the BW information */
4304 ret = i40e_veb_get_bw_info(veb);
4305 if (ret) {
4306 dev_info(&pf->pdev->dev,
4307 "Failed getting veb bw config, aq_err=%d\n",
4308 pf->hw.aq.asq_last_status);
4309 }
4310
4311out:
4312 return ret;
4313}
4314
4315#ifdef CONFIG_I40E_DCB
4316/**
4317 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4318 * @pf: PF struct
4319 *
4320 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4321 * the caller would've quiesce all the VSIs before calling
4322 * this function
4323 **/
4324static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4325{
4326 u8 tc_map = 0;
4327 int ret;
4328 u8 v;
4329
4330 /* Enable the TCs available on PF to all VEBs */
4331 tc_map = i40e_pf_get_tc_map(pf);
4332 for (v = 0; v < I40E_MAX_VEB; v++) {
4333 if (!pf->veb[v])
4334 continue;
4335 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4336 if (ret) {
4337 dev_info(&pf->pdev->dev,
4338 "Failed configuring TC for VEB seid=%d\n",
4339 pf->veb[v]->seid);
4340 /* Will try to configure as many components */
4341 }
4342 }
4343
4344 /* Update each VSI */
505682cd 4345 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4346 if (!pf->vsi[v])
4347 continue;
4348
4349 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4350#ifdef I40E_FCOE
4351 * - For FCoE VSI only enable the TC configured
4352 * as per the APP TLV
4353#endif
4e3b35b0
NP		 4354 * - For all others keep them at TC0 for now
4355 */
4356 if (v == pf->lan_vsi)
4357 tc_map = i40e_pf_get_tc_map(pf);
4358 else
4359 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4360#ifdef I40E_FCOE
4361 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4362 tc_map = i40e_get_fcoe_tc_map(pf);
4363#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4364
4365 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4366 if (ret) {
4367 dev_info(&pf->pdev->dev,
4368 "Failed configuring TC for VSI seid=%d\n",
4369 pf->vsi[v]->seid);
4370 /* Will try to configure as many components */
4371 } else {
0672a091
NP		 4372 /* Re-configure VSI vectors based on updated TC map */
4373 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4374 if (pf->vsi[v]->netdev)
4375 i40e_dcbnl_set_all(pf->vsi[v]);
4376 }
4377 }
4378}
4379
4380/**
4381 * i40e_init_pf_dcb - Initialize DCB configuration
4382 * @pf: PF being configured
4383 *
4384 * Query the current DCB configuration and cache it
4385 * in the hardware structure
4386 **/
4387static int i40e_init_pf_dcb(struct i40e_pf *pf)
4388{
4389 struct i40e_hw *hw = &pf->hw;
4390 int err = 0;
4391
4392 if (pf->hw.func_caps.npar_enable)
4393 goto out;
4394
4395 /* Get the initial DCB configuration */
4396 err = i40e_init_dcb(hw);
4397 if (!err) {
4398 /* Device/Function is not DCBX capable */
4399 if ((!hw->func_caps.dcb) ||
4400 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4401 dev_info(&pf->pdev->dev,
4402 "DCBX offload is not supported or is disabled for this PF.\n");
4403
4404 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4405 goto out;
4406
4407 } else {
4408 /* When status is not DISABLED then DCBX in FW */
4409 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4410 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4411
4412 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4413 /* Enable DCB tagging only when more than one TC */
4414 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4415 pf->flags |= I40E_FLAG_DCB_ENABLED;
4e3b35b0 4416 }
014269ff
NP		 4417 } else {
4418 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4419 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4420 }
4421
4422out:
4423 return err;
4424}
4425#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4426#define SPEED_SIZE 14
4427#define FC_SIZE 8
4428/**
4429 * i40e_print_link_message - print link up or down
4430 * @vsi: the VSI for which link needs a message
4431 */
4432static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4433{
4434 char speed[SPEED_SIZE] = "Unknown";
4435 char fc[FC_SIZE] = "RX/TX";
4436
4437 if (!isup) {
4438 netdev_info(vsi->netdev, "NIC Link is Down\n");
4439 return;
4440 }
4441
4442 switch (vsi->back->hw.phy.link_info.link_speed) {
4443 case I40E_LINK_SPEED_40GB:
35a7d804 4444 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4445 break;
4446 case I40E_LINK_SPEED_10GB:
35a7d804 4447 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4448 break;
4449 case I40E_LINK_SPEED_1GB:
35a7d804 4450 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08
JB		 4451 break;
4452 default:
4453 break;
4454 }
4455
4456 switch (vsi->back->hw.fc.current_mode) {
4457 case I40E_FC_FULL:
35a7d804 4458 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4459 break;
4460 case I40E_FC_TX_PAUSE:
35a7d804 4461 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4462 break;
4463 case I40E_FC_RX_PAUSE:
35a7d804 4464 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4465 break;
4466 default:
35a7d804 4467 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4468 break;
4469 }
4470
4471 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4472 speed, fc);
4473}
4e3b35b0 4474
41c445ff
JB		 4475/**
4476 * i40e_up_complete - Finish the last steps of bringing up a connection
4477 * @vsi: the VSI being configured
4478 **/
4479static int i40e_up_complete(struct i40e_vsi *vsi)
4480{
4481 struct i40e_pf *pf = vsi->back;
4482 int err;
4483
4484 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4485 i40e_vsi_configure_msix(vsi);
4486 else
4487 i40e_configure_msi_and_legacy(vsi);
4488
4489 /* start rings */
4490 err = i40e_vsi_control_rings(vsi, true);
4491 if (err)
4492 return err;
4493
4494 clear_bit(__I40E_DOWN, &vsi->state);
4495 i40e_napi_enable_all(vsi);
4496 i40e_vsi_enable_irq(vsi);
4497
4498 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4499 (vsi->netdev)) {
cf05ed08 4500 i40e_print_link_message(vsi, true);
41c445ff
JB		 4501 netif_tx_start_all_queues(vsi->netdev);
4502 netif_carrier_on(vsi->netdev);
6d779b41 4503 } else if (vsi->netdev) {
cf05ed08 4504 i40e_print_link_message(vsi, false);
7b592f61
CW		 4505 /* need to check for qualified module here*/
4506 if ((pf->hw.phy.link_info.link_info &
4507 I40E_AQ_MEDIA_AVAILABLE) &&
4508 (!(pf->hw.phy.link_info.an_info &
4509 I40E_AQ_QUALIFIED_MODULE)))
4510 netdev_err(vsi->netdev,
4511 "the driver failed to link because an unqualified module was detected.");
41c445ff 4512 }
ca64fa4e
ASJ		 4513
4514 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4515 if (vsi->type == I40E_VSI_FDIR) {
4516 /* reset fd counters */
4517 pf->fd_add_err = pf->fd_atr_cnt = 0;
4518 if (pf->fd_tcp_rule > 0) {
4519 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4520 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4521 pf->fd_tcp_rule = 0;
4522 }
ca64fa4e 4523 i40e_fdir_filter_restore(vsi);
1e1be8f6 4524 }
41c445ff
JB		 4525 i40e_service_event_schedule(pf);
4526
4527 return 0;
4528}
4529
4530/**
4531 * i40e_vsi_reinit_locked - Reset the VSI
4532 * @vsi: the VSI being configured
4533 *
4534 * Rebuild the ring structs after some configuration
4535 * has changed, e.g. MTU size.
4536 **/
4537static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4538{
4539 struct i40e_pf *pf = vsi->back;
4540
4541 WARN_ON(in_interrupt());
4542 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4543 usleep_range(1000, 2000);
4544 i40e_down(vsi);
4545
4546 /* Give a VF some time to respond to the reset. The
4547 * two second wait is based upon the watchdog cycle in
4548 * the VF driver.
4549 */
4550 if (vsi->type == I40E_VSI_SRIOV)
4551 msleep(2000);
4552 i40e_up(vsi);
4553 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4554}
4555
4556/**
4557 * i40e_up - Bring the connection back up after being down
4558 * @vsi: the VSI being configured
4559 **/
4560int i40e_up(struct i40e_vsi *vsi)
4561{
4562 int err;
4563
4564 err = i40e_vsi_configure(vsi);
4565 if (!err)
4566 err = i40e_up_complete(vsi);
4567
4568 return err;
4569}
4570
4571/**
4572 * i40e_down - Shutdown the connection processing
4573 * @vsi: the VSI being stopped
4574 **/
4575void i40e_down(struct i40e_vsi *vsi)
4576{
4577 int i;
4578
4579 /* It is assumed that the caller of this function
4580 * sets the vsi->state __I40E_DOWN bit.
4581 */
4582 if (vsi->netdev) {
4583 netif_carrier_off(vsi->netdev);
4584 netif_tx_disable(vsi->netdev);
4585 }
4586 i40e_vsi_disable_irq(vsi);
4587 i40e_vsi_control_rings(vsi, false);
4588 i40e_napi_disable_all(vsi);
4589
4590 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4591 i40e_clean_tx_ring(vsi->tx_rings[i]);
4592 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4593 }
4594}
4595
4596/**
4597 * i40e_setup_tc - configure multiple traffic classes
4598 * @netdev: net device to configure
4599 * @tc: number of traffic classes to enable
4600 **/
38e00438
VD		 4601#ifdef I40E_FCOE
4602int i40e_setup_tc(struct net_device *netdev, u8 tc)
4603#else
41c445ff 4604static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4605#endif
41c445ff
JB		 4606{
4607 struct i40e_netdev_priv *np = netdev_priv(netdev);
4608 struct i40e_vsi *vsi = np->vsi;
4609 struct i40e_pf *pf = vsi->back;
4610 u8 enabled_tc = 0;
4611 int ret = -EINVAL;
4612 int i;
4613
4614 /* Check if DCB enabled to continue */
4615 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4616 netdev_info(netdev, "DCB is not enabled for adapter\n");
4617 goto exit;
4618 }
4619
4620 /* Check if MFP enabled */
4621 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4622 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4623 goto exit;
4624 }
4625
4626 /* Check whether tc count is within enabled limit */
4627 if (tc > i40e_pf_get_num_tc(pf)) {
4628 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4629 goto exit;
4630 }
4631
4632 /* Generate TC map for number of tc requested */
4633 for (i = 0; i < tc; i++)
4634 enabled_tc |= (1 << i);
4635
4636 /* Requesting same TC configuration as already enabled */
4637 if (enabled_tc == vsi->tc_config.enabled_tc)
4638 return 0;
4639
4640 /* Quiesce VSI queues */
4641 i40e_quiesce_vsi(vsi);
4642
4643 /* Configure VSI for enabled TCs */
4644 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4645 if (ret) {
4646 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4647 vsi->seid);
4648 goto exit;
4649 }
4650
4651 /* Unquiesce VSI */
4652 i40e_unquiesce_vsi(vsi);
4653
4654exit:
4655 return ret;
4656}
4657
4658/**
4659 * i40e_open - Called when a network interface is made active
4660 * @netdev: network interface device structure
4661 *
4662 * The open entry point is called when a network interface is made
4663 * active by the system (IFF_UP). At this point all resources needed
4664 * for transmit and receive operations are allocated, the interrupt
4665 * handler is registered with the OS, the netdev watchdog subtask is
4666 * enabled, and the stack is notified that the interface is ready.
4667 *
4668 * Returns 0 on success, negative value on failure
4669 **/
38e00438
VD		 4670#ifdef I40E_FCOE
4671int i40e_open(struct net_device *netdev)
4672#else
41c445ff 4673static int i40e_open(struct net_device *netdev)
38e00438 4674#endif
41c445ff
JB		 4675{
4676 struct i40e_netdev_priv *np = netdev_priv(netdev);
4677 struct i40e_vsi *vsi = np->vsi;
4678 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4679 int err;
4680
4eb3f768
SN		 4681 /* disallow open during test or if eeprom is broken */
4682 if (test_bit(__I40E_TESTING, &pf->state) ||
4683 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4684 return -EBUSY;
4685
4686 netif_carrier_off(netdev);
4687
6c167f58
EK		 4688 err = i40e_vsi_open(vsi);
4689 if (err)
4690 return err;
4691
059dab69
JB		 4692 /* configure global TSO hardware offload settings */
4693 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4694 TCP_FLAG_FIN) >> 16);
4695 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4696 TCP_FLAG_FIN |
4697 TCP_FLAG_CWR) >> 16);
4698 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4699
6c167f58
EK		 4700#ifdef CONFIG_I40E_VXLAN
4701 vxlan_get_rx_port(netdev);
4702#endif
4703
4704 return 0;
4705}
4706
4707/**
4708 * i40e_vsi_open -
4709 * @vsi: the VSI to open
4710 *
4711 * Finish initialization of the VSI.
4712 *
4713 * Returns 0 on success, negative value on failure
4714 **/
4715int i40e_vsi_open(struct i40e_vsi *vsi)
4716{
4717 struct i40e_pf *pf = vsi->back;
4718 char int_name[IFNAMSIZ];
4719 int err;
4720
41c445ff
JB		 4721 /* allocate descriptors */
4722 err = i40e_vsi_setup_tx_resources(vsi);
4723 if (err)
4724 goto err_setup_tx;
4725 err = i40e_vsi_setup_rx_resources(vsi);
4726 if (err)
4727 goto err_setup_rx;
4728
4729 err = i40e_vsi_configure(vsi);
4730 if (err)
4731 goto err_setup_rx;
4732
c22e3c6c
SN		 4733 if (vsi->netdev) {
4734 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4735 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4736 err = i40e_vsi_request_irq(vsi, int_name);
4737 if (err)
4738 goto err_setup_rx;
41c445ff 4739
c22e3c6c
SN		 4740 /* Notify the stack of the actual queue counts. */
4741 err = netif_set_real_num_tx_queues(vsi->netdev,
4742 vsi->num_queue_pairs);
4743 if (err)
4744 goto err_set_queues;
25946ddb 4745
c22e3c6c
SN		 4746 err = netif_set_real_num_rx_queues(vsi->netdev,
4747 vsi->num_queue_pairs);
4748 if (err)
4749 goto err_set_queues;
8a9eb7d3
SN		 4750
4751 } else if (vsi->type == I40E_VSI_FDIR) {
4752 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4753 dev_driver_string(&pf->pdev->dev));
4754 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4755 } else {
ce9ccb17 4756 err = -EINVAL;
6c167f58
EK		 4757 goto err_setup_rx;
4758 }
25946ddb 4759
41c445ff
JB		 4760 err = i40e_up_complete(vsi);
4761 if (err)
4762 goto err_up_complete;
4763
41c445ff
JB		 4764 return 0;
4765
4766err_up_complete:
4767 i40e_down(vsi);
25946ddb 4768err_set_queues:
41c445ff
JB		 4769 i40e_vsi_free_irq(vsi);
4770err_setup_rx:
4771 i40e_vsi_free_rx_resources(vsi);
4772err_setup_tx:
4773 i40e_vsi_free_tx_resources(vsi);
4774 if (vsi == pf->vsi[pf->lan_vsi])
4775 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4776
4777 return err;
4778}
4779
17a73f6b
JG		 4780/**
4781 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4782 * @pf: Pointer to pf
4783 *
4784 * This function destroys the hlist where all the Flow Director
4785 * filters were saved.
4786 **/
4787static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4788{
4789 struct i40e_fdir_filter *filter;
4790 struct hlist_node *node2;
4791
4792 hlist_for_each_entry_safe(filter, node2,
4793 &pf->fdir_filter_list, fdir_node) {
4794 hlist_del(&filter->fdir_node);
4795 kfree(filter);
4796 }
4797 pf->fdir_pf_active_filters = 0;
4798}
4799
41c445ff
JB		 4800/**
4801 * i40e_close - Disables a network interface
4802 * @netdev: network interface device structure
4803 *
4804 * The close entry point is called when an interface is de-activated
4805 * by the OS. The hardware is still under the driver's control, but
4806 * this netdev interface is disabled.
4807 *
4808 * Returns 0, this is not allowed to fail
4809 **/
38e00438
VD		 4810#ifdef I40E_FCOE
4811int i40e_close(struct net_device *netdev)
4812#else
41c445ff 4813static int i40e_close(struct net_device *netdev)
38e00438 4814#endif
41c445ff
JB		 4815{
4816 struct i40e_netdev_priv *np = netdev_priv(netdev);
4817 struct i40e_vsi *vsi = np->vsi;
4818
90ef8d47 4819 i40e_vsi_close(vsi);
41c445ff
JB		 4820
4821 return 0;
4822}
4823
4824/**
4825 * i40e_do_reset - Start a PF or Core Reset sequence
4826 * @pf: board private structure
4827 * @reset_flags: which reset is requested
4828 *
4829 * The essential difference in resets is that the PF Reset
4830 * doesn't clear the packet buffers, doesn't reset the PE
4831 * firmware, and doesn't bother the other PFs on the chip.
4832 **/
4833void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4834{
4835 u32 val;
4836
4837 WARN_ON(in_interrupt());
4838
263fc48f
MW		 4839 if (i40e_check_asq_alive(&pf->hw))
4840 i40e_vc_notify_reset(pf);
4841
41c445ff
JB		 4842 /* do the biggest reset indicated */
4843 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4844
4845 /* Request a Global Reset
4846 *
4847 * This will start the chip's countdown to the actual full
4848 * chip reset event, and a warning interrupt to be sent
4849 * to all PFs, including the requestor. Our handler
4850 * for the warning interrupt will deal with the shutdown
4851 * and recovery of the switch setup.
4852 */
69bfb110 4853 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4854 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4855 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4856 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4857
4858 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4859
4860 /* Request a Core Reset
4861 *
4862 * Same as Global Reset, except does *not* include the MAC/PHY
4863 */
69bfb110 4864 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4865 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4866 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4867 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4868 i40e_flush(&pf->hw);
4869
7823fe34
SN		 4870 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4871
4872 /* Request a Firmware Reset
4873 *
4874 * Same as Global reset, plus restarting the
4875 * embedded firmware engine.
4876 */
4877 /* enable EMP Reset */
4878 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4879 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4880 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4881
4882 /* force the reset */
4883 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4884 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4885 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4886 i40e_flush(&pf->hw);
4887
41c445ff
JB		 4888 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4889
4890 /* Request a PF Reset
4891 *
4892 * Resets only the PF-specific registers
4893 *
4894 * This goes directly to the tear-down and rebuild of
4895 * the switch, since we need to do all the recovery as
4896 * for the Core Reset.
4897 */
69bfb110 4898 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4899 i40e_handle_reset_warning(pf);
4900
4901 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4902 int v;
4903
4904 /* Find the VSI(s) that requested a re-init */
4905 dev_info(&pf->pdev->dev,
4906 "VSI reinit requested\n");
505682cd 4907 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4908 struct i40e_vsi *vsi = pf->vsi[v];
4909 if (vsi != NULL &&
4910 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4911 i40e_vsi_reinit_locked(pf->vsi[v]);
4912 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4913 }
4914 }
4915
b5d06f05
NP		 4916 /* no further action needed, so return now */
4917 return;
4918 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4919 int v;
4920
4921 /* Find the VSI(s) that needs to be brought down */
4922 dev_info(&pf->pdev->dev, "VSI down requested\n");
4923 for (v = 0; v < pf->num_alloc_vsi; v++) {
4924 struct i40e_vsi *vsi = pf->vsi[v];
4925 if (vsi != NULL &&
4926 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4927 set_bit(__I40E_DOWN, &vsi->state);
4928 i40e_down(vsi);
4929 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4930 }
4931 }
4932
41c445ff
JB		 4933 /* no further action needed, so return now */
4934 return;
4935 } else {
4936 dev_info(&pf->pdev->dev,
4937 "bad reset request 0x%08x\n", reset_flags);
4938 return;
4939 }
4940}
4941
4e3b35b0
NP		 4942#ifdef CONFIG_I40E_DCB
4943/**
4944 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4945 * @pf: board private structure
4946 * @old_cfg: current DCB config
4947 * @new_cfg: new DCB config
4948 **/
4949bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4950 struct i40e_dcbx_config *old_cfg,
4951 struct i40e_dcbx_config *new_cfg)
4952{
4953 bool need_reconfig = false;
4954
4955 /* Check if ETS configuration has changed */
4956 if (memcmp(&new_cfg->etscfg,
4957 &old_cfg->etscfg,
4958 sizeof(new_cfg->etscfg))) {
4959 /* If Priority Table has changed reconfig is needed */
4960 if (memcmp(&new_cfg->etscfg.prioritytable,
4961 &old_cfg->etscfg.prioritytable,
4962 sizeof(new_cfg->etscfg.prioritytable))) {
4963 need_reconfig = true;
69bfb110 4964 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4965 }
4966
4967 if (memcmp(&new_cfg->etscfg.tcbwtable,
4968 &old_cfg->etscfg.tcbwtable,
4969 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4970 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4971
4972 if (memcmp(&new_cfg->etscfg.tsatable,
4973 &old_cfg->etscfg.tsatable,
4974 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4975 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4976 }
4977
4978 /* Check if PFC configuration has changed */
4979 if (memcmp(&new_cfg->pfc,
4980 &old_cfg->pfc,
4981 sizeof(new_cfg->pfc))) {
4982 need_reconfig = true;
69bfb110 4983 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4984 }
4985
4986 /* Check if APP Table has changed */
4987 if (memcmp(&new_cfg->app,
4988 &old_cfg->app,
3d9667a9 4989 sizeof(new_cfg->app))) {
4e3b35b0 4990 need_reconfig = true;
69bfb110 4991 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4992 }
4e3b35b0
NP		 4993
4994 return need_reconfig;
4995}
4996
4997/**
4998 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4999 * @pf: board private structure
5000 * @e: event info posted on ARQ
5001 **/
5002static int i40e_handle_lldp_event(struct i40e_pf *pf,
5003 struct i40e_arq_event_info *e)
5004{
5005 struct i40e_aqc_lldp_get_mib *mib =
5006 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5007 struct i40e_hw *hw = &pf->hw;
5008 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
5009 struct i40e_dcbx_config tmp_dcbx_cfg;
5010 bool need_reconfig = false;
5011 int ret = 0;
5012 u8 type;
5013
4d9b6043
NP		 5014 /* Not DCB capable or capability disabled */
5015 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5016 return ret;
5017
4e3b35b0
NP		 5018 /* Ignore if event is not for Nearest Bridge */
5019 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5020 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
5021 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5022 return ret;
5023
5024 /* Check MIB Type and return if event for Remote MIB update */
5025 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
5026 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5027 /* Update the remote cached instance and return */
5028 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5029 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5030 &hw->remote_dcbx_config);
5031 goto exit;
5032 }
5033
5034 /* Convert/store the DCBX data from LLDPDU temporarily */
5035 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
5036 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
5037 if (ret) {
5038 /* Error in LLDPDU parsing return */
5039 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
5040 goto exit;
5041 }
5042
5043 /* No change detected in DCBX configs */
5044 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5045 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5046 goto exit;
5047 }
5048
5049 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
5050
5051 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
5052
5053 /* Overwrite the new configuration */
5054 *dcbx_cfg = tmp_dcbx_cfg;
5055
5056 if (!need_reconfig)
5057 goto exit;
5058
4d9b6043
NP		 5059 /* Enable DCB tagging only when more than one TC */
5060 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5061 pf->flags |= I40E_FLAG_DCB_ENABLED;
5062 else
5063 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5064
4e3b35b0
NP		 5065 /* Reconfiguration needed quiesce all VSIs */
5066 i40e_pf_quiesce_all_vsi(pf);
5067
5068 /* Changes in configuration update VEB/VSI */
5069 i40e_dcb_reconfigure(pf);
5070
5071 i40e_pf_unquiesce_all_vsi(pf);
5072exit:
5073 return ret;
5074}
5075#endif /* CONFIG_I40E_DCB */
5076
23326186
ASJ		 5077/**
5078 * i40e_do_reset_safe - Protected reset path for userland calls.
5079 * @pf: board private structure
5080 * @reset_flags: which reset is requested
5081 *
5082 **/
5083void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5084{
5085 rtnl_lock();
5086 i40e_do_reset(pf, reset_flags);
5087 rtnl_unlock();
5088}
5089
41c445ff
JB		 5090/**
5091 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5092 * @pf: board private structure
5093 * @e: event info posted on ARQ
5094 *
5095 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5096 * and VF queues
5097 **/
5098static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5099 struct i40e_arq_event_info *e)
5100{
5101 struct i40e_aqc_lan_overflow *data =
5102 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5103 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5104 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5105 struct i40e_hw *hw = &pf->hw;
5106 struct i40e_vf *vf;
5107 u16 vf_id;
5108
69bfb110
JB		 5109 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5110 queue, qtx_ctl);
41c445ff
JB		 5111
5112 /* Queue belongs to VF, find the VF and issue VF reset */
5113 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5114 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5115 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5116 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5117 vf_id -= hw->func_caps.vf_base_id;
5118 vf = &pf->vf[vf_id];
5119 i40e_vc_notify_vf_reset(vf);
5120 /* Allow VF to process pending reset notification */
5121 msleep(20);
5122 i40e_reset_vf(vf, false);
5123 }
5124}
5125
5126/**
5127 * i40e_service_event_complete - Finish up the service event
5128 * @pf: board private structure
5129 **/
5130static void i40e_service_event_complete(struct i40e_pf *pf)
5131{
5132 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5133
5134 /* flush memory to make sure state is correct before next watchog */
4e857c58 5135 smp_mb__before_atomic();
41c445ff
JB		 5136 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5137}
5138
55a5e60b 5139/**
12957388
ASJ		 5140 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5141 * @pf: board private structure
5142 **/
5143int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5144{
5145 int val, fcnt_prog;
5146
5147 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5148 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5149 return fcnt_prog;
5150}
5151
5152/**
5153 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5154 * @pf: board private structure
5155 **/
5156int i40e_get_current_fd_count(struct i40e_pf *pf)
5157{
5158 int val, fcnt_prog;
5159 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5160 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5161 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5162 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5163 return fcnt_prog;
5164}
1e1be8f6 5165
55a5e60b
ASJ		 5166/**
5167 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5168 * @pf: board private structure
5169 **/
5170void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5171{
5172 u32 fcnt_prog, fcnt_avail;
5173
1e1be8f6
ASJ		 5174 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5175 return;
5176
55a5e60b
ASJ		 5177 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5178 * to re-enable
5179 */
12957388
ASJ		 5180 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5181 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5182 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5183 (pf->fd_add_err == 0) ||
5184 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5185 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5186 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5187 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5188 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5189 }
5190 }
5191 /* Wait for some more space to be available to turn on ATR */
5192 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5193 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5194 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5195 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5196 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5197 }
5198 }
5199}
5200
1e1be8f6
ASJ		 5201#define I40E_MIN_FD_FLUSH_INTERVAL 10
5202/**
5203 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5204 * @pf: board private structure
5205 **/
5206static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5207{
5208 int flush_wait_retry = 50;
5209 int reg;
5210
5211 if (time_after(jiffies, pf->fd_flush_timestamp +
5212 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5213 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5214 pf->fd_flush_timestamp = jiffies;
5215 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5216 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5217 /* flush all filters */
5218 wr32(&pf->hw, I40E_PFQF_CTL_1,
5219 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5220 i40e_flush(&pf->hw);
60793f4a 5221 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5222 pf->fd_add_err = 0;
5223 do {
5224 /* Check FD flush status every 5-6msec */
5225 usleep_range(5000, 6000);
5226 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5227 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5228 break;
5229 } while (flush_wait_retry--);
5230 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5231 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5232 } else {
5233 /* replay sideband filters */
5234 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5235
5236 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5237 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5238 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5239 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5240 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5241 }
5242 }
5243}
5244
5245/**
5246 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5247 * @pf: board private structure
5248 **/
5249int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5250{
5251 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5252}
5253
5254/* We can see up to 256 filter programming desc in transit if the filters are
5255 * being applied really fast; before we see the first
5256 * filter miss error on Rx queue 0. Accumulating enough error messages before
5257 * reacting will make sure we don't cause flush too often.
5258 */
5259#define I40E_MAX_FD_PROGRAM_ERROR 256
5260
41c445ff
JB		 5261/**
5262 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5263 * @pf: board private structure
5264 **/
5265static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5266{
41c445ff 5267
41c445ff
JB		 5268 /* if interface is down do nothing */
5269 if (test_bit(__I40E_DOWN, &pf->state))
5270 return;
1e1be8f6
ASJ		 5271
5272 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5273 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5274 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5275 i40e_fdir_flush_and_replay(pf);
5276
55a5e60b
ASJ		 5277 i40e_fdir_check_and_reenable(pf);
5278
41c445ff
JB		 5279}
5280
5281/**
5282 * i40e_vsi_link_event - notify VSI of a link event
5283 * @vsi: vsi to be notified
5284 * @link_up: link up or down
5285 **/
5286static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5287{
32b5b811 5288 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5289 return;
5290
5291 switch (vsi->type) {
5292 case I40E_VSI_MAIN:
38e00438
VD		 5293#ifdef I40E_FCOE
5294 case I40E_VSI_FCOE:
5295#endif
41c445ff
JB		 5296 if (!vsi->netdev || !vsi->netdev_registered)
5297 break;
5298
5299 if (link_up) {
5300 netif_carrier_on(vsi->netdev);
5301 netif_tx_wake_all_queues(vsi->netdev);
5302 } else {
5303 netif_carrier_off(vsi->netdev);
5304 netif_tx_stop_all_queues(vsi->netdev);
5305 }
5306 break;
5307
5308 case I40E_VSI_SRIOV:
5309 break;
5310
5311 case I40E_VSI_VMDQ2:
5312 case I40E_VSI_CTRL:
5313 case I40E_VSI_MIRROR:
5314 default:
5315 /* there is no notification for other VSIs */
5316 break;
5317 }
5318}
5319
5320/**
5321 * i40e_veb_link_event - notify elements on the veb of a link event
5322 * @veb: veb to be notified
5323 * @link_up: link up or down
5324 **/
5325static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5326{
5327 struct i40e_pf *pf;
5328 int i;
5329
5330 if (!veb || !veb->pf)
5331 return;
5332 pf = veb->pf;
5333
5334 /* depth first... */
5335 for (i = 0; i < I40E_MAX_VEB; i++)
5336 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5337 i40e_veb_link_event(pf->veb[i], link_up);
5338
5339 /* ... now the local VSIs */
505682cd 5340 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5341 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5342 i40e_vsi_link_event(pf->vsi[i], link_up);
5343}
5344
5345/**
5346 * i40e_link_event - Update netif_carrier status
5347 * @pf: board private structure
5348 **/
5349static void i40e_link_event(struct i40e_pf *pf)
5350{
5351 bool new_link, old_link;
5352
1e701e09
JB		 5353 /* set this to force the get_link_status call to refresh state */
5354 pf->hw.phy.get_link_info = true;
5355
41c445ff 5356 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5357 new_link = i40e_get_link_status(&pf->hw);
41c445ff 5358
1e701e09
JB		 5359 if (new_link == old_link &&
5360 new_link == netif_carrier_ok(pf->vsi[pf->lan_vsi]->netdev))
41c445ff 5361 return;
6d779b41 5362 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 5363 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 5364
5365 /* Notify the base of the switch tree connected to
5366 * the link. Floating VEBs are not notified.
5367 */
5368 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5369 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5370 else
5371 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
5372
5373 if (pf->vf)
5374 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5375
5376 if (pf->flags & I40E_FLAG_PTP)
5377 i40e_ptp_set_increment(pf);
41c445ff
JB		 5378}
5379
5380/**
5381 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5382 * @pf: board private structure
5383 *
5384 * Set the per-queue flags to request a check for stuck queues in the irq
5385 * clean functions, then force interrupts to be sure the irq clean is called.
5386 **/
5387static void i40e_check_hang_subtask(struct i40e_pf *pf)
5388{
5389 int i, v;
5390
5391 /* If we're down or resetting, just bail */
5392 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5393 return;
5394
5395 /* for each VSI/netdev
5396 * for each Tx queue
5397 * set the check flag
5398 * for each q_vector
5399 * force an interrupt
5400 */
505682cd 5401 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5402 struct i40e_vsi *vsi = pf->vsi[v];
5403 int armed = 0;
5404
5405 if (!pf->vsi[v] ||
5406 test_bit(__I40E_DOWN, &vsi->state) ||
5407 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5408 continue;
5409
5410 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5411 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5412 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5413 &vsi->tx_rings[i]->state))
41c445ff
JB		 5414 armed++;
5415 }
5416
5417 if (armed) {
5418 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5419 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5420 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5421 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5422 } else {
5423 u16 vec = vsi->base_vector - 1;
5424 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5425 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5426 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5427 wr32(&vsi->back->hw,
5428 I40E_PFINT_DYN_CTLN(vec), val);
5429 }
5430 i40e_flush(&vsi->back->hw);
5431 }
5432 }
5433}
5434
5435/**
5436 * i40e_watchdog_subtask - Check and bring link up
5437 * @pf: board private structure
5438 **/
5439static void i40e_watchdog_subtask(struct i40e_pf *pf)
5440{
5441 int i;
5442
5443 /* if interface is down do nothing */
5444 if (test_bit(__I40E_DOWN, &pf->state) ||
5445 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5446 return;
5447
5448 /* Update the stats for active netdevs so the network stack
5449 * can look at updated numbers whenever it cares to
5450 */
505682cd 5451 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5452 if (pf->vsi[i] && pf->vsi[i]->netdev)
5453 i40e_update_stats(pf->vsi[i]);
5454
5455 /* Update the stats for the active switching components */
5456 for (i = 0; i < I40E_MAX_VEB; i++)
5457 if (pf->veb[i])
5458 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5459
5460 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5461}
5462
5463/**
5464 * i40e_reset_subtask - Set up for resetting the device and driver
5465 * @pf: board private structure
5466 **/
5467static void i40e_reset_subtask(struct i40e_pf *pf)
5468{
5469 u32 reset_flags = 0;
5470
23326186 5471 rtnl_lock();
41c445ff
JB		 5472 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5473 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5474 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5475 }
5476 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5477 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5478 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5479 }
5480 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5481 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5482 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5483 }
5484 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5485 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5486 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5487 }
b5d06f05
NP		 5488 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5489 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5490 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5491 }
41c445ff
JB		 5492
5493 /* If there's a recovery already waiting, it takes
5494 * precedence before starting a new reset sequence.
5495 */
5496 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5497 i40e_handle_reset_warning(pf);
23326186 5498 goto unlock;
41c445ff
JB		 5499 }
5500
5501 /* If we're already down or resetting, just bail */
5502 if (reset_flags &&
5503 !test_bit(__I40E_DOWN, &pf->state) &&
5504 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5505 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5506
5507unlock:
5508 rtnl_unlock();
41c445ff
JB		 5509}
5510
5511/**
5512 * i40e_handle_link_event - Handle link event
5513 * @pf: board private structure
5514 * @e: event info posted on ARQ
5515 **/
5516static void i40e_handle_link_event(struct i40e_pf *pf,
5517 struct i40e_arq_event_info *e)
5518{
5519 struct i40e_hw *hw = &pf->hw;
5520 struct i40e_aqc_get_link_status *status =
5521 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5522 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5523
5524 /* save off old link status information */
5525 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5526 sizeof(pf->hw.phy.link_info_old));
5527
1e701e09
JB		 5528 /* Do a new status request to re-enable LSE reporting
5529 * and load new status information into the hw struct
5530 * This completely ignores any state information
5531 * in the ARQ event info, instead choosing to always
5532 * issue the AQ update link status command.
5533 */
5534 i40e_link_event(pf);
5535
7b592f61
CW		 5536 /* check for unqualified module, if link is down */
5537 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5538 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5539 (!(status->link_info & I40E_AQ_LINK_UP)))
5540 dev_err(&pf->pdev->dev,
5541 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5542}
5543
5544/**
5545 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5546 * @pf: board private structure
5547 **/
5548static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5549{
5550 struct i40e_arq_event_info event;
5551 struct i40e_hw *hw = &pf->hw;
5552 u16 pending, i = 0;
5553 i40e_status ret;
5554 u16 opcode;
86df242b 5555 u32 oldval;
41c445ff
JB		 5556 u32 val;
5557
a316f651
ASJ		 5558 /* Do not run clean AQ when PF reset fails */
5559 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5560 return;
5561
86df242b
SN		 5562 /* check for error indications */
5563 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5564 oldval = val;
5565 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5566 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5567 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5568 }
5569 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5570 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5571 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5572 }
5573 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5574 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5575 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5576 }
5577 if (oldval != val)
5578 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5579
5580 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5581 oldval = val;
5582 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5583 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5584 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5585 }
5586 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5587 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5588 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5589 }
5590 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5591 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5592 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5593 }
5594 if (oldval != val)
5595 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5596
3197ce22 5597 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5598 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5599 if (!event.msg_buf)
5600 return;
5601
5602 do {
2f019123 5603 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff 5604 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5605 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5606 break;
56497978 5607 else if (ret) {
41c445ff
JB		 5608 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5609 break;
5610 }
5611
5612 opcode = le16_to_cpu(event.desc.opcode);
5613 switch (opcode) {
5614
5615 case i40e_aqc_opc_get_link_status:
5616 i40e_handle_link_event(pf, &event);
5617 break;
5618 case i40e_aqc_opc_send_msg_to_pf:
5619 ret = i40e_vc_process_vf_msg(pf,
5620 le16_to_cpu(event.desc.retval),
5621 le32_to_cpu(event.desc.cookie_high),
5622 le32_to_cpu(event.desc.cookie_low),
5623 event.msg_buf,
5624 event.msg_size);
5625 break;
5626 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5627 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5628#ifdef CONFIG_I40E_DCB
5629 rtnl_lock();
5630 ret = i40e_handle_lldp_event(pf, &event);
5631 rtnl_unlock();
5632#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5633 break;
5634 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5635 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5636 i40e_handle_lan_overflow_event(pf, &event);
5637 break;
0467bc91
SN		 5638 case i40e_aqc_opc_send_msg_to_peer:
5639 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5640 break;
41c445ff
JB		 5641 default:
5642 dev_info(&pf->pdev->dev,
0467bc91
SN		 5643 "ARQ Error: Unknown event 0x%04x received\n",
5644 opcode);
41c445ff
JB		 5645 break;
5646 }
5647 } while (pending && (i++ < pf->adminq_work_limit));
5648
5649 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5650 /* re-enable Admin queue interrupt cause */
5651 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5652 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5653 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5654 i40e_flush(hw);
5655
5656 kfree(event.msg_buf);
5657}
5658
4eb3f768
SN		 5659/**
5660 * i40e_verify_eeprom - make sure eeprom is good to use
5661 * @pf: board private structure
5662 **/
5663static void i40e_verify_eeprom(struct i40e_pf *pf)
5664{
5665 int err;
5666
5667 err = i40e_diag_eeprom_test(&pf->hw);
5668 if (err) {
5669 /* retry in case of garbage read */
5670 err = i40e_diag_eeprom_test(&pf->hw);
5671 if (err) {
5672 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5673 err);
5674 set_bit(__I40E_BAD_EEPROM, &pf->state);
5675 }
5676 }
5677
5678 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5679 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5680 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5681 }
5682}
5683
41c445ff
JB		 5684/**
5685 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5686 * @veb: pointer to the VEB instance
5687 *
5688 * This is a recursive function that first builds the attached VSIs then
5689 * recurses in to build the next layer of VEB. We track the connections
5690 * through our own index numbers because the seid's from the HW could
5691 * change across the reset.
5692 **/
5693static int i40e_reconstitute_veb(struct i40e_veb *veb)
5694{
5695 struct i40e_vsi *ctl_vsi = NULL;
5696 struct i40e_pf *pf = veb->pf;
5697 int v, veb_idx;
5698 int ret;
5699
5700 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5701 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5702 if (pf->vsi[v] &&
5703 pf->vsi[v]->veb_idx == veb->idx &&
5704 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5705 ctl_vsi = pf->vsi[v];
5706 break;
5707 }
5708 }
5709 if (!ctl_vsi) {
5710 dev_info(&pf->pdev->dev,
5711 "missing owner VSI for veb_idx %d\n", veb->idx);
5712 ret = -ENOENT;
5713 goto end_reconstitute;
5714 }
5715 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5716 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5717 ret = i40e_add_vsi(ctl_vsi);
5718 if (ret) {
5719 dev_info(&pf->pdev->dev,
5720 "rebuild of owner VSI failed: %d\n", ret);
5721 goto end_reconstitute;
5722 }
5723 i40e_vsi_reset_stats(ctl_vsi);
5724
5725 /* create the VEB in the switch and move the VSI onto the VEB */
5726 ret = i40e_add_veb(veb, ctl_vsi);
5727 if (ret)
5728 goto end_reconstitute;
5729
5730 /* create the remaining VSIs attached to this VEB */
505682cd 5731 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5732 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5733 continue;
5734
5735 if (pf->vsi[v]->veb_idx == veb->idx) {
5736 struct i40e_vsi *vsi = pf->vsi[v];
5737 vsi->uplink_seid = veb->seid;
5738 ret = i40e_add_vsi(vsi);
5739 if (ret) {
5740 dev_info(&pf->pdev->dev,
5741 "rebuild of vsi_idx %d failed: %d\n",
5742 v, ret);
5743 goto end_reconstitute;
5744 }
5745 i40e_vsi_reset_stats(vsi);
5746 }
5747 }
5748
5749 /* create any VEBs attached to this VEB - RECURSION */
5750 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5751 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5752 pf->veb[veb_idx]->uplink_seid = veb->seid;
5753 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5754 if (ret)
5755 break;
5756 }
5757 }
5758
5759end_reconstitute:
5760 return ret;
5761}
5762
5763/**
5764 * i40e_get_capabilities - get info about the HW
5765 * @pf: the PF struct
5766 **/
5767static int i40e_get_capabilities(struct i40e_pf *pf)
5768{
5769 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5770 u16 data_size;
5771 int buf_len;
5772 int err;
5773
5774 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5775 do {
5776 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5777 if (!cap_buf)
5778 return -ENOMEM;
5779
5780 /* this loads the data into the hw struct for us */
5781 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5782 &data_size,
5783 i40e_aqc_opc_list_func_capabilities,
5784 NULL);
5785 /* data loaded, buffer no longer needed */
5786 kfree(cap_buf);
5787
5788 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5789 /* retry with a larger buffer */
5790 buf_len = data_size;
5791 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5792 dev_info(&pf->pdev->dev,
5793 "capability discovery failed: aq=%d\n",
5794 pf->hw.aq.asq_last_status);
5795 return -ENODEV;
5796 }
5797 } while (err);
5798
ac71b7ba
ASJ		 5799 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5800 (pf->hw.aq.fw_maj_ver < 2)) {
5801 pf->hw.func_caps.num_msix_vectors++;
5802 pf->hw.func_caps.num_msix_vectors_vf++;
5803 }
5804
41c445ff
JB		 5805 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5806 dev_info(&pf->pdev->dev,
5807 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5808 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5809 pf->hw.func_caps.num_msix_vectors,
5810 pf->hw.func_caps.num_msix_vectors_vf,
5811 pf->hw.func_caps.fd_filters_guaranteed,
5812 pf->hw.func_caps.fd_filters_best_effort,
5813 pf->hw.func_caps.num_tx_qp,
5814 pf->hw.func_caps.num_vsis);
5815
7134f9ce
JB		 5816#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5817 + pf->hw.func_caps.num_vfs)
5818 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5819 dev_info(&pf->pdev->dev,
5820 "got num_vsis %d, setting num_vsis to %d\n",
5821 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5822 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5823 }
5824
41c445ff
JB		 5825 return 0;
5826}
5827
cbf61325
ASJ		 5828static int i40e_vsi_clear(struct i40e_vsi *vsi);
5829
41c445ff 5830/**
cbf61325 5831 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5832 * @pf: board private structure
5833 **/
cbf61325 5834static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5835{
5836 struct i40e_vsi *vsi;
8a9eb7d3 5837 int i;
41c445ff 5838
407e063c
JB		 5839 /* quick workaround for an NVM issue that leaves a critical register
5840 * uninitialized
5841 */
5842 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5843 static const u32 hkey[] = {
5844 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5845 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5846 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5847 0x95b3a76d};
5848
5849 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5850 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5851 }
5852
cbf61325 5853 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5854 return;
5855
cbf61325 5856 /* find existing VSI and see if it needs configuring */
41c445ff 5857 vsi = NULL;
505682cd 5858 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5859 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5860 vsi = pf->vsi[i];
cbf61325
ASJ		 5861 break;
5862 }
5863 }
5864
5865 /* create a new VSI if none exists */
41c445ff 5866 if (!vsi) {
cbf61325
ASJ		 5867 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5868 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5869 if (!vsi) {
5870 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5871 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5872 return;
41c445ff 5873 }
cbf61325 5874 }
41c445ff 5875
8a9eb7d3 5876 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5877}
5878
5879/**
5880 * i40e_fdir_teardown - release the Flow Director resources
5881 * @pf: board private structure
5882 **/
5883static void i40e_fdir_teardown(struct i40e_pf *pf)
5884{
5885 int i;
5886
17a73f6b 5887 i40e_fdir_filter_exit(pf);
505682cd 5888 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5889 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5890 i40e_vsi_release(pf->vsi[i]);
5891 break;
5892 }
5893 }
5894}
5895
5896/**
f650a38b 5897 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5898 * @pf: board private structure
5899 *
f650a38b
ASJ		 5900 * Close up the VFs and other things in prep for pf Reset.
5901 **/
23cfbe07 5902static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5903{
41c445ff 5904 struct i40e_hw *hw = &pf->hw;
60442dea 5905 i40e_status ret = 0;
41c445ff
JB		 5906 u32 v;
5907
5908 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5909 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 5910 return;
41c445ff 5911
69bfb110 5912 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5913
41c445ff
JB		 5914 /* quiesce the VSIs and their queues that are not already DOWN */
5915 i40e_pf_quiesce_all_vsi(pf);
5916
505682cd 5917 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5918 if (pf->vsi[v])
5919 pf->vsi[v]->seid = 0;
5920 }
5921
5922 i40e_shutdown_adminq(&pf->hw);
5923
f650a38b 5924 /* call shutdown HMC */
60442dea
SN		 5925 if (hw->hmc.hmc_obj) {
5926 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 5927 if (ret)
60442dea
SN		 5928 dev_warn(&pf->pdev->dev,
5929 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 5930 }
f650a38b
ASJ		 5931}
5932
44033fac
JB		 5933/**
5934 * i40e_send_version - update firmware with driver version
5935 * @pf: PF struct
5936 */
5937static void i40e_send_version(struct i40e_pf *pf)
5938{
5939 struct i40e_driver_version dv;
5940
5941 dv.major_version = DRV_VERSION_MAJOR;
5942 dv.minor_version = DRV_VERSION_MINOR;
5943 dv.build_version = DRV_VERSION_BUILD;
5944 dv.subbuild_version = 0;
35a7d804 5945 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 5946 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5947}
5948
f650a38b 5949/**
4dda12e6 5950 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5951 * @pf: board private structure
bc7d338f 5952 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5953 **/
bc7d338f 5954static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5955{
f650a38b 5956 struct i40e_hw *hw = &pf->hw;
cafa2ee6 5957 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 5958 i40e_status ret;
5959 u32 v;
5960
41c445ff
JB		 5961 /* Now we wait for GRST to settle out.
5962 * We don't have to delete the VEBs or VSIs from the hw switch
5963 * because the reset will make them disappear.
5964 */
5965 ret = i40e_pf_reset(hw);
b5565400 5966 if (ret) {
41c445ff 5967 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 5968 set_bit(__I40E_RESET_FAILED, &pf->state);
5969 goto clear_recovery;
b5565400 5970 }
41c445ff
JB		 5971 pf->pfr_count++;
5972
5973 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 5974 goto clear_recovery;
69bfb110 5975 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5976
5977 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5978 ret = i40e_init_adminq(&pf->hw);
5979 if (ret) {
5980 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 5981 goto clear_recovery;
41c445ff
JB		 5982 }
5983
4eb3f768
SN		 5984 /* re-verify the eeprom if we just had an EMP reset */
5985 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5986 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5987 i40e_verify_eeprom(pf);
5988 }
5989
e78ac4bf 5990 i40e_clear_pxe_mode(hw);
41c445ff
JB		 5991 ret = i40e_get_capabilities(pf);
5992 if (ret) {
5993 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5994 ret);
5995 goto end_core_reset;
5996 }
5997
41c445ff
JB		 5998 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5999 hw->func_caps.num_rx_qp,
6000 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6001 if (ret) {
6002 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6003 goto end_core_reset;
6004 }
6005 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6006 if (ret) {
6007 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6008 goto end_core_reset;
6009 }
6010
4e3b35b0
NP		 6011#ifdef CONFIG_I40E_DCB
6012 ret = i40e_init_pf_dcb(pf);
6013 if (ret) {
6014 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
6015 goto end_core_reset;
6016 }
6017#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6018#ifdef I40E_FCOE
6019 ret = i40e_init_pf_fcoe(pf);
6020 if (ret)
6021 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6022
38e00438 6023#endif
41c445ff 6024 /* do basic switch setup */
bc7d338f 6025 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6026 if (ret)
6027 goto end_core_reset;
6028
7e2453fe
JB		 6029 /* driver is only interested in link up/down and module qualification
6030 * reports from firmware
6031 */
6032 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6033 I40E_AQ_EVENT_LINK_UPDOWN |
6034 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6035 if (ret)
6036 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6037
cafa2ee6
ASJ		 6038 /* make sure our flow control settings are restored */
6039 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6040 if (ret)
6041 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6042
41c445ff
JB		 6043 /* Rebuild the VSIs and VEBs that existed before reset.
6044 * They are still in our local switch element arrays, so only
6045 * need to rebuild the switch model in the HW.
6046 *
6047 * If there were VEBs but the reconstitution failed, we'll try
6048 * try to recover minimal use by getting the basic PF VSI working.
6049 */
6050 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6051 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6052 /* find the one VEB connected to the MAC, and find orphans */
6053 for (v = 0; v < I40E_MAX_VEB; v++) {
6054 if (!pf->veb[v])
6055 continue;
6056
6057 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6058 pf->veb[v]->uplink_seid == 0) {
6059 ret = i40e_reconstitute_veb(pf->veb[v]);
6060
6061 if (!ret)
6062 continue;
6063
6064 /* If Main VEB failed, we're in deep doodoo,
6065 * so give up rebuilding the switch and set up
6066 * for minimal rebuild of PF VSI.
6067 * If orphan failed, we'll report the error
6068 * but try to keep going.
6069 */
6070 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6071 dev_info(&pf->pdev->dev,
6072 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6073 ret);
6074 pf->vsi[pf->lan_vsi]->uplink_seid
6075 = pf->mac_seid;
6076 break;
6077 } else if (pf->veb[v]->uplink_seid == 0) {
6078 dev_info(&pf->pdev->dev,
6079 "rebuild of orphan VEB failed: %d\n",
6080 ret);
6081 }
6082 }
6083 }
6084 }
6085
6086 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6087 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6088 /* no VEB, so rebuild only the Main VSI */
6089 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6090 if (ret) {
6091 dev_info(&pf->pdev->dev,
6092 "rebuild of Main VSI failed: %d\n", ret);
6093 goto end_core_reset;
6094 }
6095 }
6096
cafa2ee6
ASJ		 6097 msleep(75);
6098 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6099 if (ret) {
6100 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6101 pf->hw.aq.asq_last_status);
6102 }
6103
41c445ff
JB		 6104 /* reinit the misc interrupt */
6105 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6106 ret = i40e_setup_misc_vector(pf);
6107
6108 /* restart the VSIs that were rebuilt and running before the reset */
6109 i40e_pf_unquiesce_all_vsi(pf);
6110
69f64b2b
MW		 6111 if (pf->num_alloc_vfs) {
6112 for (v = 0; v < pf->num_alloc_vfs; v++)
6113 i40e_reset_vf(&pf->vf[v], true);
6114 }
6115
41c445ff 6116 /* tell the firmware that we're starting */
44033fac 6117 i40e_send_version(pf);
41c445ff
JB		 6118
6119end_core_reset:
a316f651
ASJ		 6120 clear_bit(__I40E_RESET_FAILED, &pf->state);
6121clear_recovery:
41c445ff
JB		 6122 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6123}
6124
f650a38b
ASJ		 6125/**
6126 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6127 * @pf: board private structure
6128 *
6129 * Close up the VFs and other things in prep for a Core Reset,
6130 * then get ready to rebuild the world.
6131 **/
6132static void i40e_handle_reset_warning(struct i40e_pf *pf)
6133{
23cfbe07
SN		 6134 i40e_prep_for_reset(pf);
6135 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6136}
6137
41c445ff
JB		 6138/**
6139 * i40e_handle_mdd_event
6140 * @pf: pointer to the pf structure
6141 *
6142 * Called from the MDD irq handler to identify possibly malicious vfs
6143 **/
6144static void i40e_handle_mdd_event(struct i40e_pf *pf)
6145{
6146 struct i40e_hw *hw = &pf->hw;
6147 bool mdd_detected = false;
df430b12 6148 bool pf_mdd_detected = false;
41c445ff
JB		 6149 struct i40e_vf *vf;
6150 u32 reg;
6151 int i;
6152
6153 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6154 return;
6155
6156 /* find what triggered the MDD event */
6157 reg = rd32(hw, I40E_GL_MDET_TX);
6158 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6159 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6160 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6161 u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6162 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6163 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) >>
6164 I40E_GL_MDET_TX_EVENT_SHIFT;
6165 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6166 I40E_GL_MDET_TX_QUEUE_SHIFT;
faf32978
JB		 6167 if (netif_msg_tx_err(pf))
6168 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6169 event, queue, pf_num, vf_num);
41c445ff
JB		 6170 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6171 mdd_detected = true;
6172 }
6173 reg = rd32(hw, I40E_GL_MDET_RX);
6174 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6175 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6176 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6177 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) >>
6178 I40E_GL_MDET_RX_EVENT_SHIFT;
6179 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6180 I40E_GL_MDET_RX_QUEUE_SHIFT;
faf32978
JB		 6181 if (netif_msg_rx_err(pf))
6182 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6183 event, queue, func);
41c445ff
JB		 6184 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6185 mdd_detected = true;
6186 }
6187
df430b12
NP		 6188 if (mdd_detected) {
6189 reg = rd32(hw, I40E_PF_MDET_TX);
6190 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6191 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6192 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6193 pf_mdd_detected = true;
6194 }
6195 reg = rd32(hw, I40E_PF_MDET_RX);
6196 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6197 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6198 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6199 pf_mdd_detected = true;
6200 }
6201 /* Queue belongs to the PF, initiate a reset */
6202 if (pf_mdd_detected) {
6203 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6204 i40e_service_event_schedule(pf);
6205 }
6206 }
6207
41c445ff
JB		 6208 /* see if one of the VFs needs its hand slapped */
6209 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6210 vf = &(pf->vf[i]);
6211 reg = rd32(hw, I40E_VP_MDET_TX(i));
6212 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6213 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6214 vf->num_mdd_events++;
faf32978
JB		 6215 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6216 i);
41c445ff
JB		 6217 }
6218
6219 reg = rd32(hw, I40E_VP_MDET_RX(i));
6220 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6221 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6222 vf->num_mdd_events++;
faf32978
JB		 6223 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6224 i);
41c445ff
JB		 6225 }
6226
6227 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6228 dev_info(&pf->pdev->dev,
6229 "Too many MDD events on VF %d, disabled\n", i);
6230 dev_info(&pf->pdev->dev,
6231 "Use PF Control I/F to re-enable the VF\n");
6232 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6233 }
6234 }
6235
6236 /* re-enable mdd interrupt cause */
6237 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6238 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6239 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6240 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6241 i40e_flush(hw);
6242}
6243
a1c9a9d9
JK		 6244#ifdef CONFIG_I40E_VXLAN
6245/**
6246 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6247 * @pf: board private structure
6248 **/
6249static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6250{
a1c9a9d9
JK		 6251 struct i40e_hw *hw = &pf->hw;
6252 i40e_status ret;
6253 u8 filter_index;
6254 __be16 port;
6255 int i;
6256
6257 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6258 return;
6259
6260 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6261
6262 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6263 if (pf->pending_vxlan_bitmap & (1 << i)) {
6264 pf->pending_vxlan_bitmap &= ~(1 << i);
6265 port = pf->vxlan_ports[i];
6266 ret = port ?
6267 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6268 I40E_AQC_TUNNEL_TYPE_VXLAN,
6269 &filter_index, NULL)
6270 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6271
6272 if (ret) {
6273 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6274 port ? "adding" : "deleting",
6275 ntohs(port), port ? i : i);
6276
6277 pf->vxlan_ports[i] = 0;
6278 } else {
6279 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6280 port ? "Added" : "Deleted",
6281 ntohs(port), port ? i : filter_index);
6282 }
6283 }
6284 }
6285}
6286
6287#endif
41c445ff
JB		 6288/**
6289 * i40e_service_task - Run the driver's async subtasks
6290 * @work: pointer to work_struct containing our data
6291 **/
6292static void i40e_service_task(struct work_struct *work)
6293{
6294 struct i40e_pf *pf = container_of(work,
6295 struct i40e_pf,
6296 service_task);
6297 unsigned long start_time = jiffies;
6298
e57a2fea
SN		 6299 /* don't bother with service tasks if a reset is in progress */
6300 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6301 i40e_service_event_complete(pf);
6302 return;
6303 }
6304
41c445ff
JB		 6305 i40e_reset_subtask(pf);
6306 i40e_handle_mdd_event(pf);
6307 i40e_vc_process_vflr_event(pf);
6308 i40e_watchdog_subtask(pf);
6309 i40e_fdir_reinit_subtask(pf);
6310 i40e_check_hang_subtask(pf);
6311 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6312#ifdef CONFIG_I40E_VXLAN
6313 i40e_sync_vxlan_filters_subtask(pf);
6314#endif
41c445ff
JB		 6315 i40e_clean_adminq_subtask(pf);
6316
1e701e09
JB		 6317 i40e_link_event(pf);
6318
41c445ff
JB		 6319 i40e_service_event_complete(pf);
6320
6321 /* If the tasks have taken longer than one timer cycle or there
6322 * is more work to be done, reschedule the service task now
6323 * rather than wait for the timer to tick again.
6324 */
6325 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6326 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6327 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6328 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6329 i40e_service_event_schedule(pf);
6330}
6331
6332/**
6333 * i40e_service_timer - timer callback
6334 * @data: pointer to PF struct
6335 **/
6336static void i40e_service_timer(unsigned long data)
6337{
6338 struct i40e_pf *pf = (struct i40e_pf *)data;
6339
6340 mod_timer(&pf->service_timer,
6341 round_jiffies(jiffies + pf->service_timer_period));
6342 i40e_service_event_schedule(pf);
6343}
6344
6345/**
6346 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6347 * @vsi: the VSI being configured
6348 **/
6349static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6350{
6351 struct i40e_pf *pf = vsi->back;
6352
6353 switch (vsi->type) {
6354 case I40E_VSI_MAIN:
6355 vsi->alloc_queue_pairs = pf->num_lan_qps;
6356 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6357 I40E_REQ_DESCRIPTOR_MULTIPLE);
6358 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6359 vsi->num_q_vectors = pf->num_lan_msix;
6360 else
6361 vsi->num_q_vectors = 1;
6362
6363 break;
6364
6365 case I40E_VSI_FDIR:
6366 vsi->alloc_queue_pairs = 1;
6367 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6368 I40E_REQ_DESCRIPTOR_MULTIPLE);
6369 vsi->num_q_vectors = 1;
6370 break;
6371
6372 case I40E_VSI_VMDQ2:
6373 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6374 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6375 I40E_REQ_DESCRIPTOR_MULTIPLE);
6376 vsi->num_q_vectors = pf->num_vmdq_msix;
6377 break;
6378
6379 case I40E_VSI_SRIOV:
6380 vsi->alloc_queue_pairs = pf->num_vf_qps;
6381 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6382 I40E_REQ_DESCRIPTOR_MULTIPLE);
6383 break;
6384
38e00438
VD		 6385#ifdef I40E_FCOE
6386 case I40E_VSI_FCOE:
6387 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6388 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6389 I40E_REQ_DESCRIPTOR_MULTIPLE);
6390 vsi->num_q_vectors = pf->num_fcoe_msix;
6391 break;
6392
6393#endif /* I40E_FCOE */
41c445ff
JB		 6394 default:
6395 WARN_ON(1);
6396 return -ENODATA;
6397 }
6398
6399 return 0;
6400}
6401
f650a38b
ASJ		 6402/**
6403 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6404 * @type: VSI pointer
bc7d338f 6405 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6406 *
6407 * On error: returns error code (negative)
6408 * On success: returns 0
6409 **/
bc7d338f 6410static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6411{
6412 int size;
6413 int ret = 0;
6414
ac6c5e3d 6415 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6416 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6417 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6418 if (!vsi->tx_rings)
6419 return -ENOMEM;
f650a38b
ASJ		 6420 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6421
bc7d338f
ASJ		 6422 if (alloc_qvectors) {
6423 /* allocate memory for q_vector pointers */
f57e4fbd 6424 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6425 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6426 if (!vsi->q_vectors) {
6427 ret = -ENOMEM;
6428 goto err_vectors;
6429 }
f650a38b
ASJ		 6430 }
6431 return ret;
6432
6433err_vectors:
6434 kfree(vsi->tx_rings);
6435 return ret;
6436}
6437
41c445ff
JB		 6438/**
6439 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6440 * @pf: board private structure
6441 * @type: type of VSI
6442 *
6443 * On error: returns error code (negative)
6444 * On success: returns vsi index in PF (positive)
6445 **/
6446static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6447{
6448 int ret = -ENODEV;
6449 struct i40e_vsi *vsi;
6450 int vsi_idx;
6451 int i;
6452
6453 /* Need to protect the allocation of the VSIs at the PF level */
6454 mutex_lock(&pf->switch_mutex);
6455
6456 /* VSI list may be fragmented if VSI creation/destruction has
6457 * been happening. We can afford to do a quick scan to look
6458 * for any free VSIs in the list.
6459 *
6460 * find next empty vsi slot, looping back around if necessary
6461 */
6462 i = pf->next_vsi;
505682cd 6463 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6464 i++;
505682cd 6465 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6466 i = 0;
6467 while (i < pf->next_vsi && pf->vsi[i])
6468 i++;
6469 }
6470
505682cd 6471 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6472 vsi_idx = i; /* Found one! */
6473 } else {
6474 ret = -ENODEV;
493fb300 6475 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6476 }
6477 pf->next_vsi = ++i;
6478
6479 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6480 if (!vsi) {
6481 ret = -ENOMEM;
493fb300 6482 goto unlock_pf;
41c445ff
JB		 6483 }
6484 vsi->type = type;
6485 vsi->back = pf;
6486 set_bit(__I40E_DOWN, &vsi->state);
6487 vsi->flags = 0;
6488 vsi->idx = vsi_idx;
6489 vsi->rx_itr_setting = pf->rx_itr_default;
6490 vsi->tx_itr_setting = pf->tx_itr_default;
6491 vsi->netdev_registered = false;
6492 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6493 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6494 vsi->irqs_ready = false;
41c445ff 6495
9f65e15b
AD		 6496 ret = i40e_set_num_rings_in_vsi(vsi);
6497 if (ret)
6498 goto err_rings;
6499
bc7d338f 6500 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6501 if (ret)
9f65e15b 6502 goto err_rings;
493fb300 6503
41c445ff
JB		 6504 /* Setup default MSIX irq handler for VSI */
6505 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6506
6507 pf->vsi[vsi_idx] = vsi;
6508 ret = vsi_idx;
493fb300
AD		 6509 goto unlock_pf;
6510
9f65e15b 6511err_rings:
493fb300
AD		 6512 pf->next_vsi = i - 1;
6513 kfree(vsi);
6514unlock_pf:
41c445ff
JB		 6515 mutex_unlock(&pf->switch_mutex);
6516 return ret;
6517}
6518
f650a38b
ASJ		 6519/**
6520 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6521 * @type: VSI pointer
bc7d338f 6522 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6523 *
6524 * On error: returns error code (negative)
6525 * On success: returns 0
6526 **/
bc7d338f 6527static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6528{
6529 /* free the ring and vector containers */
bc7d338f
ASJ		 6530 if (free_qvectors) {
6531 kfree(vsi->q_vectors);
6532 vsi->q_vectors = NULL;
6533 }
f650a38b
ASJ		 6534 kfree(vsi->tx_rings);
6535 vsi->tx_rings = NULL;
6536 vsi->rx_rings = NULL;
6537}
6538
41c445ff
JB		 6539/**
6540 * i40e_vsi_clear - Deallocate the VSI provided
6541 * @vsi: the VSI being un-configured
6542 **/
6543static int i40e_vsi_clear(struct i40e_vsi *vsi)
6544{
6545 struct i40e_pf *pf;
6546
6547 if (!vsi)
6548 return 0;
6549
6550 if (!vsi->back)
6551 goto free_vsi;
6552 pf = vsi->back;
6553
6554 mutex_lock(&pf->switch_mutex);
6555 if (!pf->vsi[vsi->idx]) {
6556 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6557 vsi->idx, vsi->idx, vsi, vsi->type);
6558 goto unlock_vsi;
6559 }
6560
6561 if (pf->vsi[vsi->idx] != vsi) {
6562 dev_err(&pf->pdev->dev,
6563 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6564 pf->vsi[vsi->idx]->idx,
6565 pf->vsi[vsi->idx],
6566 pf->vsi[vsi->idx]->type,
6567 vsi->idx, vsi, vsi->type);
6568 goto unlock_vsi;
6569 }
6570
6571 /* updates the pf for this cleared vsi */
6572 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6573 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6574
bc7d338f 6575 i40e_vsi_free_arrays(vsi, true);
493fb300 6576
41c445ff
JB		 6577 pf->vsi[vsi->idx] = NULL;
6578 if (vsi->idx < pf->next_vsi)
6579 pf->next_vsi = vsi->idx;
6580
6581unlock_vsi:
6582 mutex_unlock(&pf->switch_mutex);
6583free_vsi:
6584 kfree(vsi);
6585
6586 return 0;
6587}
6588
9f65e15b
AD		 6589/**
6590 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6591 * @vsi: the VSI being cleaned
6592 **/
be1d5eea 6593static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6594{
6595 int i;
6596
8e9dca53 6597 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6598 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6599 kfree_rcu(vsi->tx_rings[i], rcu);
6600 vsi->tx_rings[i] = NULL;
6601 vsi->rx_rings[i] = NULL;
6602 }
be1d5eea 6603 }
9f65e15b
AD		 6604}
6605
41c445ff
JB		 6606/**
6607 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6608 * @vsi: the VSI being configured
6609 **/
6610static int i40e_alloc_rings(struct i40e_vsi *vsi)
6611{
e7046ee1 6612 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6613 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6614 int i;
6615
41c445ff 6616 /* Set basic values in the rings to be used later during open() */
d7397644 6617 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6618 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6619 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6620 if (!tx_ring)
6621 goto err_out;
41c445ff
JB		 6622
6623 tx_ring->queue_index = i;
6624 tx_ring->reg_idx = vsi->base_queue + i;
6625 tx_ring->ring_active = false;
6626 tx_ring->vsi = vsi;
6627 tx_ring->netdev = vsi->netdev;
6628 tx_ring->dev = &pf->pdev->dev;
6629 tx_ring->count = vsi->num_desc;
6630 tx_ring->size = 0;
6631 tx_ring->dcb_tc = 0;
9f65e15b 6632 vsi->tx_rings[i] = tx_ring;
41c445ff 6633
9f65e15b 6634 rx_ring = &tx_ring[1];
41c445ff
JB		 6635 rx_ring->queue_index = i;
6636 rx_ring->reg_idx = vsi->base_queue + i;
6637 rx_ring->ring_active = false;
6638 rx_ring->vsi = vsi;
6639 rx_ring->netdev = vsi->netdev;
6640 rx_ring->dev = &pf->pdev->dev;
6641 rx_ring->count = vsi->num_desc;
6642 rx_ring->size = 0;
6643 rx_ring->dcb_tc = 0;
6644 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6645 set_ring_16byte_desc_enabled(rx_ring);
6646 else
6647 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6648 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6649 }
6650
6651 return 0;
9f65e15b
AD		 6652
6653err_out:
6654 i40e_vsi_clear_rings(vsi);
6655 return -ENOMEM;
41c445ff
JB		 6656}
6657
6658/**
6659 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6660 * @pf: board private structure
6661 * @vectors: the number of MSI-X vectors to request
6662 *
6663 * Returns the number of vectors reserved, or error
6664 **/
6665static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6666{
7b37f376
AG		 6667 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6668 I40E_MIN_MSIX, vectors);
6669 if (vectors < 0) {
41c445ff 6670 dev_info(&pf->pdev->dev,
7b37f376 6671 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6672 vectors = 0;
6673 }
6674
6675 return vectors;
6676}
6677
6678/**
6679 * i40e_init_msix - Setup the MSIX capability
6680 * @pf: board private structure
6681 *
6682 * Work with the OS to set up the MSIX vectors needed.
6683 *
6684 * Returns 0 on success, negative on failure
6685 **/
6686static int i40e_init_msix(struct i40e_pf *pf)
6687{
6688 i40e_status err = 0;
6689 struct i40e_hw *hw = &pf->hw;
6690 int v_budget, i;
6691 int vec;
6692
6693 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6694 return -ENODEV;
6695
6696 /* The number of vectors we'll request will be comprised of:
6697 * - Add 1 for "other" cause for Admin Queue events, etc.
6698 * - The number of LAN queue pairs
f8ff1464
ASJ		 6699 * - Queues being used for RSS.
6700 * We don't need as many as max_rss_size vectors.
6701 * use rss_size instead in the calculation since that
6702 * is governed by number of cpus in the system.
6703 * - assumes symmetric Tx/Rx pairing
41c445ff 6704 * - The number of VMDq pairs
38e00438
VD		 6705#ifdef I40E_FCOE
6706 * - The number of FCOE qps.
6707#endif
41c445ff
JB		 6708 * Once we count this up, try the request.
6709 *
6710 * If we can't get what we want, we'll simplify to nearly nothing
6711 * and try again. If that still fails, we punt.
6712 */
f8ff1464 6713 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6714 pf->num_vmdq_msix = pf->num_vmdq_qps;
6715 v_budget = 1 + pf->num_lan_msix;
6716 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6717 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6718 v_budget++;
6719
38e00438
VD		 6720#ifdef I40E_FCOE
6721 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6722 pf->num_fcoe_msix = pf->num_fcoe_qps;
6723 v_budget += pf->num_fcoe_msix;
6724 }
6725
6726#endif
41c445ff
JB		 6727 /* Scale down if necessary, and the rings will share vectors */
6728 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6729
6730 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6731 GFP_KERNEL);
6732 if (!pf->msix_entries)
6733 return -ENOMEM;
6734
6735 for (i = 0; i < v_budget; i++)
6736 pf->msix_entries[i].entry = i;
6737 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6738
6739 if (vec != v_budget) {
6740 /* If we have limited resources, we will start with no vectors
6741 * for the special features and then allocate vectors to some
6742 * of these features based on the policy and at the end disable
6743 * the features that did not get any vectors.
6744 */
38e00438
VD		 6745#ifdef I40E_FCOE
6746 pf->num_fcoe_qps = 0;
6747 pf->num_fcoe_msix = 0;
6748#endif
a34977ba
ASJ		 6749 pf->num_vmdq_msix = 0;
6750 }
6751
41c445ff
JB		 6752 if (vec < I40E_MIN_MSIX) {
6753 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6754 kfree(pf->msix_entries);
6755 pf->msix_entries = NULL;
6756 return -ENODEV;
6757
6758 } else if (vec == I40E_MIN_MSIX) {
6759 /* Adjust for minimal MSIX use */
41c445ff
JB		 6760 pf->num_vmdq_vsis = 0;
6761 pf->num_vmdq_qps = 0;
41c445ff
JB		 6762 pf->num_lan_qps = 1;
6763 pf->num_lan_msix = 1;
6764
6765 } else if (vec != v_budget) {
a34977ba
ASJ		 6766 /* reserve the misc vector */
6767 vec--;
6768
41c445ff
JB		 6769 /* Scale vector usage down */
6770 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6771 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6772
6773 /* partition out the remaining vectors */
6774 switch (vec) {
6775 case 2:
41c445ff
JB		 6776 pf->num_lan_msix = 1;
6777 break;
6778 case 3:
38e00438
VD		 6779#ifdef I40E_FCOE
6780 /* give one vector to FCoE */
6781 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6782 pf->num_lan_msix = 1;
6783 pf->num_fcoe_msix = 1;
6784 }
6785#else
41c445ff 6786 pf->num_lan_msix = 2;
38e00438 6787#endif
41c445ff
JB		 6788 break;
6789 default:
38e00438
VD		 6790#ifdef I40E_FCOE
6791 /* give one vector to FCoE */
6792 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6793 pf->num_fcoe_msix = 1;
6794 vec--;
6795 }
6796#endif
41c445ff
JB		 6797 pf->num_lan_msix = min_t(int, (vec / 2),
6798 pf->num_lan_qps);
6799 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6800 I40E_DEFAULT_NUM_VMDQ_VSI);
6801 break;
6802 }
6803 }
6804
a34977ba
ASJ		 6805 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6806 (pf->num_vmdq_msix == 0)) {
6807 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6808 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6809 }
38e00438
VD		 6810#ifdef I40E_FCOE
6811
6812 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
6813 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
6814 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
6815 }
6816#endif
41c445ff
JB		 6817 return err;
6818}
6819
493fb300 6820/**
90e04070 6821 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6822 * @vsi: the VSI being configured
6823 * @v_idx: index of the vector in the vsi struct
6824 *
6825 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6826 **/
90e04070 6827static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6828{
6829 struct i40e_q_vector *q_vector;
6830
6831 /* allocate q_vector */
6832 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6833 if (!q_vector)
6834 return -ENOMEM;
6835
6836 q_vector->vsi = vsi;
6837 q_vector->v_idx = v_idx;
6838 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6839 if (vsi->netdev)
6840 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6841 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6842
cd0b6fa6
AD		 6843 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6844 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6845
493fb300
AD		 6846 /* tie q_vector and vsi together */
6847 vsi->q_vectors[v_idx] = q_vector;
6848
6849 return 0;
6850}
6851
41c445ff 6852/**
90e04070 6853 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6854 * @vsi: the VSI being configured
6855 *
6856 * We allocate one q_vector per queue interrupt. If allocation fails we
6857 * return -ENOMEM.
6858 **/
90e04070 6859static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6860{
6861 struct i40e_pf *pf = vsi->back;
6862 int v_idx, num_q_vectors;
493fb300 6863 int err;
41c445ff
JB		 6864
6865 /* if not MSIX, give the one vector only to the LAN VSI */
6866 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6867 num_q_vectors = vsi->num_q_vectors;
6868 else if (vsi == pf->vsi[pf->lan_vsi])
6869 num_q_vectors = 1;
6870 else
6871 return -EINVAL;
6872
41c445ff 6873 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6874 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6875 if (err)
6876 goto err_out;
41c445ff
JB		 6877 }
6878
6879 return 0;
493fb300
AD		 6880
6881err_out:
6882 while (v_idx--)
6883 i40e_free_q_vector(vsi, v_idx);
6884
6885 return err;
41c445ff
JB		 6886}
6887
6888/**
6889 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6890 * @pf: board private structure to initialize
6891 **/
6892static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6893{
6894 int err = 0;
6895
6896 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6897 err = i40e_init_msix(pf);
6898 if (err) {
60ea5f83 6899 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 6900#ifdef I40E_FCOE
6901 I40E_FLAG_FCOE_ENABLED |
6902#endif
60ea5f83 6903 I40E_FLAG_RSS_ENABLED |
4d9b6043 6904 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6905 I40E_FLAG_SRIOV_ENABLED |
6906 I40E_FLAG_FD_SB_ENABLED |
6907 I40E_FLAG_FD_ATR_ENABLED |
6908 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6909
6910 /* rework the queue expectations without MSIX */
6911 i40e_determine_queue_usage(pf);
6912 }
6913 }
6914
6915 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6916 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6917 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6918 err = pci_enable_msi(pf->pdev);
6919 if (err) {
958a3e3b 6920 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6921 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6922 }
6923 }
6924
958a3e3b 6925 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6926 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6927
41c445ff
JB		 6928 /* track first vector for misc interrupts */
6929 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6930}
6931
6932/**
6933 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6934 * @pf: board private structure
6935 *
6936 * This sets up the handler for MSIX 0, which is used to manage the
6937 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6938 * when in MSI or Legacy interrupt mode.
6939 **/
6940static int i40e_setup_misc_vector(struct i40e_pf *pf)
6941{
6942 struct i40e_hw *hw = &pf->hw;
6943 int err = 0;
6944
6945 /* Only request the irq if this is the first time through, and
6946 * not when we're rebuilding after a Reset
6947 */
6948 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6949 err = request_irq(pf->msix_entries[0].vector,
6950 i40e_intr, 0, pf->misc_int_name, pf);
6951 if (err) {
6952 dev_info(&pf->pdev->dev,
77fa28be
CS		 6953 "request_irq for %s failed: %d\n",
6954 pf->misc_int_name, err);
41c445ff
JB		 6955 return -EFAULT;
6956 }
6957 }
6958
6959 i40e_enable_misc_int_causes(hw);
6960
6961 /* associate no queues to the misc vector */
6962 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6963 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6964
6965 i40e_flush(hw);
6966
6967 i40e_irq_dynamic_enable_icr0(pf);
6968
6969 return err;
6970}
6971
6972/**
6973 * i40e_config_rss - Prepare for RSS if used
6974 * @pf: board private structure
6975 **/
6976static int i40e_config_rss(struct i40e_pf *pf)
6977{
41c445ff
JB		 6978 /* Set of random keys generated using kernel random number generator */
6979 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6980 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6981 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6982 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6983 struct i40e_hw *hw = &pf->hw;
6984 u32 lut = 0;
6985 int i, j;
6986 u64 hena;
e157ea30 6987 u32 reg_val;
41c445ff
JB		 6988
6989 /* Fill out hash function seed */
6990 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6991 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6992
6993 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6994 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6995 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6996 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6997 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6998 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6999
e157ea30
CW		 7000 /* Check capability and Set table size and register per hw expectation*/
7001 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7002 if (hw->func_caps.rss_table_size == 512) {
7003 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7004 pf->rss_table_size = 512;
7005 } else {
7006 pf->rss_table_size = 128;
7007 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7008 }
7009 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7010
41c445ff 7011 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7012 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7013
7014 /* The assumption is that lan qp count will be the highest
7015 * qp count for any PF VSI that needs RSS.
7016 * If multiple VSIs need RSS support, all the qp counts
7017 * for those VSIs should be a power of 2 for RSS to work.
7018 * If LAN VSI is the only consumer for RSS then this requirement
7019 * is not necessary.
7020 */
7021 if (j == pf->rss_size)
7022 j = 0;
7023 /* lut = 4-byte sliding window of 4 lut entries */
7024 lut = (lut << 8) | (j &
7025 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7026 /* On i = 3, we have 4 entries in lut; write to the register */
7027 if ((i & 3) == 3)
7028 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7029 }
7030 i40e_flush(hw);
7031
7032 return 0;
7033}
7034
f8ff1464
ASJ		 7035/**
7036 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7037 * @pf: board private structure
7038 * @queue_count: the requested queue count for rss.
7039 *
7040 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7041 * count which may be different from the requested queue count.
7042 **/
7043int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7044{
7045 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7046 return 0;
7047
7048 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 7049
7050 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 7051 i40e_prep_for_reset(pf);
7052
f8ff1464
ASJ		 7053 pf->rss_size = queue_count;
7054
7055 i40e_reset_and_rebuild(pf, true);
7056 i40e_config_rss(pf);
7057 }
7058 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7059 return pf->rss_size;
7060}
7061
41c445ff
JB		 7062/**
7063 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7064 * @pf: board private structure to initialize
7065 *
7066 * i40e_sw_init initializes the Adapter private data structure.
7067 * Fields are initialized based on PCI device information and
7068 * OS network device settings (MTU size).
7069 **/
7070static int i40e_sw_init(struct i40e_pf *pf)
7071{
7072 int err = 0;
7073 int size;
7074
7075 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7076 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7077 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7078 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7079 if (I40E_DEBUG_USER & debug)
7080 pf->hw.debug_mask = debug;
7081 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7082 I40E_DEFAULT_MSG_ENABLE);
7083 }
7084
7085 /* Set default capability flags */
7086 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7087 I40E_FLAG_MSI_ENABLED |
7088 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 7089 I40E_FLAG_RX_1BUF_ENABLED;
7090
ca99eb99
MW		 7091 /* Set default ITR */
7092 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7093 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7094
7134f9ce
JB		 7095 /* Depending on PF configurations, it is possible that the RSS
7096 * maximum might end up larger than the available queues
7097 */
41c445ff 7098 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7099 pf->rss_size = 1;
7134f9ce
JB		 7100 pf->rss_size_max = min_t(int, pf->rss_size_max,
7101 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7102 if (pf->hw.func_caps.rss) {
7103 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7104 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7105 }
7106
2050bc65
CS		 7107 /* MFP mode enabled */
7108 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7109 pf->flags |= I40E_FLAG_MFP_ENABLED;
7110 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
7111 }
7112
cbf61325
ASJ		 7113 /* FW/NVM is not yet fixed in this regard */
7114 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7115 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7116 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7117 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7118 /* Setup a counter for fd_atr per pf */
7119 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7120 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7121 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7122 /* Setup a counter for fd_sb per pf */
7123 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7124 } else {
7125 dev_info(&pf->pdev->dev,
0b67584f 7126 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7127 }
cbf61325
ASJ		 7128 pf->fdir_pf_filter_count =
7129 pf->hw.func_caps.fd_filters_guaranteed;
7130 pf->hw.fdir_shared_filter_count =
7131 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7132 }
7133
7134 if (pf->hw.func_caps.vmdq) {
7135 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7136 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7137 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7138 }
7139
38e00438
VD		 7140#ifdef I40E_FCOE
7141 err = i40e_init_pf_fcoe(pf);
7142 if (err)
7143 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7144
7145#endif /* I40E_FCOE */
41c445ff
JB		 7146#ifdef CONFIG_PCI_IOV
7147 if (pf->hw.func_caps.num_vfs) {
7148 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7149 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7150 pf->num_req_vfs = min_t(int,
7151 pf->hw.func_caps.num_vfs,
7152 I40E_MAX_VF_COUNT);
7153 }
7154#endif /* CONFIG_PCI_IOV */
7155 pf->eeprom_version = 0xDEAD;
7156 pf->lan_veb = I40E_NO_VEB;
7157 pf->lan_vsi = I40E_NO_VSI;
7158
7159 /* set up queue assignment tracking */
7160 size = sizeof(struct i40e_lump_tracking)
7161 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7162 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7163 if (!pf->qp_pile) {
7164 err = -ENOMEM;
7165 goto sw_init_done;
7166 }
7167 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7168 pf->qp_pile->search_hint = 0;
7169
7170 /* set up vector assignment tracking */
7171 size = sizeof(struct i40e_lump_tracking)
7172 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7173 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7174 if (!pf->irq_pile) {
7175 kfree(pf->qp_pile);
7176 err = -ENOMEM;
7177 goto sw_init_done;
7178 }
7179 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7180 pf->irq_pile->search_hint = 0;
7181
327fe04b
ASJ		 7182 pf->tx_timeout_recovery_level = 1;
7183
41c445ff
JB		 7184 mutex_init(&pf->switch_mutex);
7185
7186sw_init_done:
7187 return err;
7188}
7189
7c3c288b
ASJ		 7190/**
7191 * i40e_set_ntuple - set the ntuple feature flag and take action
7192 * @pf: board private structure to initialize
7193 * @features: the feature set that the stack is suggesting
7194 *
7195 * returns a bool to indicate if reset needs to happen
7196 **/
7197bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7198{
7199 bool need_reset = false;
7200
7201 /* Check if Flow Director n-tuple support was enabled or disabled. If
7202 * the state changed, we need to reset.
7203 */
7204 if (features & NETIF_F_NTUPLE) {
7205 /* Enable filters and mark for reset */
7206 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7207 need_reset = true;
7208 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7209 } else {
7210 /* turn off filters, mark for reset and clear SW filter list */
7211 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7212 need_reset = true;
7213 i40e_fdir_filter_exit(pf);
7214 }
7215 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7216 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7217 /* reset fd counters */
7218 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7219 pf->fdir_pf_active_filters = 0;
7220 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7221 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7222 /* if ATR was auto disabled it can be re-enabled. */
7223 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7224 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7225 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7226 }
7227 return need_reset;
7228}
7229
41c445ff
JB		 7230/**
7231 * i40e_set_features - set the netdev feature flags
7232 * @netdev: ptr to the netdev being adjusted
7233 * @features: the feature set that the stack is suggesting
7234 **/
7235static int i40e_set_features(struct net_device *netdev,
7236 netdev_features_t features)
7237{
7238 struct i40e_netdev_priv *np = netdev_priv(netdev);
7239 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7240 struct i40e_pf *pf = vsi->back;
7241 bool need_reset;
41c445ff
JB		 7242
7243 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7244 i40e_vlan_stripping_enable(vsi);
7245 else
7246 i40e_vlan_stripping_disable(vsi);
7247
7c3c288b
ASJ		 7248 need_reset = i40e_set_ntuple(pf, features);
7249
7250 if (need_reset)
7251 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7252
41c445ff
JB		 7253 return 0;
7254}
7255
a1c9a9d9
JK		 7256#ifdef CONFIG_I40E_VXLAN
7257/**
7258 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7259 * @pf: board private structure
7260 * @port: The UDP port to look up
7261 *
7262 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7263 **/
7264static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7265{
7266 u8 i;
7267
7268 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7269 if (pf->vxlan_ports[i] == port)
7270 return i;
7271 }
7272
7273 return i;
7274}
7275
7276/**
7277 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7278 * @netdev: This physical port's netdev
7279 * @sa_family: Socket Family that VXLAN is notifying us about
7280 * @port: New UDP port number that VXLAN started listening to
7281 **/
7282static void i40e_add_vxlan_port(struct net_device *netdev,
7283 sa_family_t sa_family, __be16 port)
7284{
7285 struct i40e_netdev_priv *np = netdev_priv(netdev);
7286 struct i40e_vsi *vsi = np->vsi;
7287 struct i40e_pf *pf = vsi->back;
7288 u8 next_idx;
7289 u8 idx;
7290
7291 if (sa_family == AF_INET6)
7292 return;
7293
7294 idx = i40e_get_vxlan_port_idx(pf, port);
7295
7296 /* Check if port already exists */
7297 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7298 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7299 return;
7300 }
7301
7302 /* Now check if there is space to add the new port */
7303 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7304
7305 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7306 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7307 ntohs(port));
7308 return;
7309 }
7310
7311 /* New port: add it and mark its index in the bitmap */
7312 pf->vxlan_ports[next_idx] = port;
7313 pf->pending_vxlan_bitmap |= (1 << next_idx);
7314
7315 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7316}
7317
7318/**
7319 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7320 * @netdev: This physical port's netdev
7321 * @sa_family: Socket Family that VXLAN is notifying us about
7322 * @port: UDP port number that VXLAN stopped listening to
7323 **/
7324static void i40e_del_vxlan_port(struct net_device *netdev,
7325 sa_family_t sa_family, __be16 port)
7326{
7327 struct i40e_netdev_priv *np = netdev_priv(netdev);
7328 struct i40e_vsi *vsi = np->vsi;
7329 struct i40e_pf *pf = vsi->back;
7330 u8 idx;
7331
7332 if (sa_family == AF_INET6)
7333 return;
7334
7335 idx = i40e_get_vxlan_port_idx(pf, port);
7336
7337 /* Check if port already exists */
7338 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7339 /* if port exists, set it to 0 (mark for deletion)
7340 * and make it pending
7341 */
7342 pf->vxlan_ports[idx] = 0;
7343
7344 pf->pending_vxlan_bitmap |= (1 << idx);
7345
7346 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7347 } else {
7348 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7349 ntohs(port));
7350 }
7351}
7352
7353#endif
1f224ad2
NP		 7354static int i40e_get_phys_port_id(struct net_device *netdev,
7355 struct netdev_phys_port_id *ppid)
7356{
7357 struct i40e_netdev_priv *np = netdev_priv(netdev);
7358 struct i40e_pf *pf = np->vsi->back;
7359 struct i40e_hw *hw = &pf->hw;
7360
7361 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7362 return -EOPNOTSUPP;
7363
7364 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7365 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7366
7367 return 0;
7368}
7369
4ba0dea5
GR		 7370#ifdef HAVE_FDB_OPS
7371#ifdef USE_CONST_DEV_UC_CHAR
7372static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7373 struct net_device *dev,
7374 const unsigned char *addr,
7375 u16 flags)
7376#else
7377static int i40e_ndo_fdb_add(struct ndmsg *ndm,
7378 struct net_device *dev,
7379 unsigned char *addr,
7380 u16 flags)
7381#endif
7382{
7383 struct i40e_netdev_priv *np = netdev_priv(dev);
7384 struct i40e_pf *pf = np->vsi->back;
7385 int err = 0;
7386
7387 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7388 return -EOPNOTSUPP;
7389
7390 /* Hardware does not support aging addresses so if a
7391 * ndm_state is given only allow permanent addresses
7392 */
7393 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7394 netdev_info(dev, "FDB only supports static addresses\n");
7395 return -EINVAL;
7396 }
7397
7398 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7399 err = dev_uc_add_excl(dev, addr);
7400 else if (is_multicast_ether_addr(addr))
7401 err = dev_mc_add_excl(dev, addr);
7402 else
7403 err = -EINVAL;
7404
7405 /* Only return duplicate errors if NLM_F_EXCL is set */
7406 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7407 err = 0;
7408
7409 return err;
7410}
7411
7412#ifndef USE_DEFAULT_FDB_DEL_DUMP
7413#ifdef USE_CONST_DEV_UC_CHAR
7414static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7415 struct net_device *dev,
7416 const unsigned char *addr)
7417#else
7418static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7419 struct net_device *dev,
7420 unsigned char *addr)
7421#endif
7422{
7423 struct i40e_netdev_priv *np = netdev_priv(dev);
7424 struct i40e_pf *pf = np->vsi->back;
7425 int err = -EOPNOTSUPP;
7426
7427 if (ndm->ndm_state & NUD_PERMANENT) {
7428 netdev_info(dev, "FDB only supports static addresses\n");
7429 return -EINVAL;
7430 }
7431
7432 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7433 if (is_unicast_ether_addr(addr))
7434 err = dev_uc_del(dev, addr);
7435 else if (is_multicast_ether_addr(addr))
7436 err = dev_mc_del(dev, addr);
7437 else
7438 err = -EINVAL;
7439 }
7440
7441 return err;
7442}
7443
7444static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7445 struct netlink_callback *cb,
7446 struct net_device *dev,
5d5eacb3 7447 struct net_device *filter_dev,
4ba0dea5
GR		 7448 int idx)
7449{
7450 struct i40e_netdev_priv *np = netdev_priv(dev);
7451 struct i40e_pf *pf = np->vsi->back;
7452
7453 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
5d5eacb3 7454 idx = ndo_dflt_fdb_dump(skb, cb, dev, filter_dev, idx);
4ba0dea5
GR		 7455
7456 return idx;
7457}
7458
7459#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7460#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7461static const struct net_device_ops i40e_netdev_ops = {
7462 .ndo_open = i40e_open,
7463 .ndo_stop = i40e_close,
7464 .ndo_start_xmit = i40e_lan_xmit_frame,
7465 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7466 .ndo_set_rx_mode = i40e_set_rx_mode,
7467 .ndo_validate_addr = eth_validate_addr,
7468 .ndo_set_mac_address = i40e_set_mac,
7469 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7470 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7471 .ndo_tx_timeout = i40e_tx_timeout,
7472 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7473 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7474#ifdef CONFIG_NET_POLL_CONTROLLER
7475 .ndo_poll_controller = i40e_netpoll,
7476#endif
7477 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7478#ifdef I40E_FCOE
7479 .ndo_fcoe_enable = i40e_fcoe_enable,
7480 .ndo_fcoe_disable = i40e_fcoe_disable,
7481#endif
41c445ff
JB		 7482 .ndo_set_features = i40e_set_features,
7483 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7484 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7485 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7486 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7487 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7488 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7489#ifdef CONFIG_I40E_VXLAN
7490 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7491 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7492#endif
1f224ad2 7493 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5
GR		 7494#ifdef HAVE_FDB_OPS
7495 .ndo_fdb_add = i40e_ndo_fdb_add,
7496#ifndef USE_DEFAULT_FDB_DEL_DUMP
7497 .ndo_fdb_del = i40e_ndo_fdb_del,
7498 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7499#endif
7500#endif
41c445ff
JB		 7501};
7502
7503/**
7504 * i40e_config_netdev - Setup the netdev flags
7505 * @vsi: the VSI being configured
7506 *
7507 * Returns 0 on success, negative value on failure
7508 **/
7509static int i40e_config_netdev(struct i40e_vsi *vsi)
7510{
1a10370a 7511 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7512 struct i40e_pf *pf = vsi->back;
7513 struct i40e_hw *hw = &pf->hw;
7514 struct i40e_netdev_priv *np;
7515 struct net_device *netdev;
7516 u8 mac_addr[ETH_ALEN];
7517 int etherdev_size;
7518
7519 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7520 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7521 if (!netdev)
7522 return -ENOMEM;
7523
7524 vsi->netdev = netdev;
7525 np = netdev_priv(netdev);
7526 np->vsi = vsi;
7527
d70e941b 7528 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7529 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7530 NETIF_F_TSO;
41c445ff
JB		 7531
7532 netdev->features = NETIF_F_SG |
7533 NETIF_F_IP_CSUM |
7534 NETIF_F_SCTP_CSUM |
7535 NETIF_F_HIGHDMA |
7536 NETIF_F_GSO_UDP_TUNNEL |
7537 NETIF_F_HW_VLAN_CTAG_TX |
7538 NETIF_F_HW_VLAN_CTAG_RX |
7539 NETIF_F_HW_VLAN_CTAG_FILTER |
7540 NETIF_F_IPV6_CSUM |
7541 NETIF_F_TSO |
059dab69 7542 NETIF_F_TSO_ECN |
41c445ff
JB		 7543 NETIF_F_TSO6 |
7544 NETIF_F_RXCSUM |
7545 NETIF_F_RXHASH |
7546 0;
7547
2e86a0b6
ASJ		 7548 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7549 netdev->features |= NETIF_F_NTUPLE;
7550
41c445ff
JB		 7551 /* copy netdev features into list of user selectable features */
7552 netdev->hw_features |= netdev->features;
7553
7554 if (vsi->type == I40E_VSI_MAIN) {
7555 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7556 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 7557 /* The following steps are necessary to prevent reception
7558 * of tagged packets - some older NVM configurations load a
7559 * default a MAC-VLAN filter that accepts any tagged packet
7560 * which must be replaced by a normal filter.
8c27d42e 7561 */
30650cc5
SN		 7562 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
7563 i40e_add_filter(vsi, mac_addr,
7564 I40E_VLAN_ANY, false, true);
41c445ff
JB		 7565 } else {
7566 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7567 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7568 pf->vsi[pf->lan_vsi]->netdev->name);
7569 random_ether_addr(mac_addr);
7570 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7571 }
1a10370a 7572 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7573
9a173901
GR		 7574 ether_addr_copy(netdev->dev_addr, mac_addr);
7575 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7576 /* vlan gets same features (except vlan offload)
7577 * after any tweaks for specific VSI types
7578 */
7579 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7580 NETIF_F_HW_VLAN_CTAG_RX |
7581 NETIF_F_HW_VLAN_CTAG_FILTER);
7582 netdev->priv_flags |= IFF_UNICAST_FLT;
7583 netdev->priv_flags |= IFF_SUPP_NOFCS;
7584 /* Setup netdev TC information */
7585 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7586
7587 netdev->netdev_ops = &i40e_netdev_ops;
7588 netdev->watchdog_timeo = 5 * HZ;
7589 i40e_set_ethtool_ops(netdev);
38e00438
VD		 7590#ifdef I40E_FCOE
7591 i40e_fcoe_config_netdev(netdev, vsi);
7592#endif
41c445ff
JB		 7593
7594 return 0;
7595}
7596
7597/**
7598 * i40e_vsi_delete - Delete a VSI from the switch
7599 * @vsi: the VSI being removed
7600 *
7601 * Returns 0 on success, negative value on failure
7602 **/
7603static void i40e_vsi_delete(struct i40e_vsi *vsi)
7604{
7605 /* remove default VSI is not allowed */
7606 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7607 return;
7608
41c445ff 7609 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7610}
7611
7612/**
7613 * i40e_add_vsi - Add a VSI to the switch
7614 * @vsi: the VSI being configured
7615 *
7616 * This initializes a VSI context depending on the VSI type to be added and
7617 * passes it down to the add_vsi aq command.
7618 **/
7619static int i40e_add_vsi(struct i40e_vsi *vsi)
7620{
7621 int ret = -ENODEV;
7622 struct i40e_mac_filter *f, *ftmp;
7623 struct i40e_pf *pf = vsi->back;
7624 struct i40e_hw *hw = &pf->hw;
7625 struct i40e_vsi_context ctxt;
7626 u8 enabled_tc = 0x1; /* TC0 enabled */
7627 int f_count = 0;
7628
7629 memset(&ctxt, 0, sizeof(ctxt));
7630 switch (vsi->type) {
7631 case I40E_VSI_MAIN:
7632 /* The PF's main VSI is already setup as part of the
7633 * device initialization, so we'll not bother with
7634 * the add_vsi call, but we will retrieve the current
7635 * VSI context.
7636 */
7637 ctxt.seid = pf->main_vsi_seid;
7638 ctxt.pf_num = pf->hw.pf_id;
7639 ctxt.vf_num = 0;
7640 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7641 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7642 if (ret) {
7643 dev_info(&pf->pdev->dev,
7644 "couldn't get pf vsi config, err %d, aq_err %d\n",
7645 ret, pf->hw.aq.asq_last_status);
7646 return -ENOENT;
7647 }
7648 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7649 vsi->info.valid_sections = 0;
7650
7651 vsi->seid = ctxt.seid;
7652 vsi->id = ctxt.vsi_number;
7653
7654 enabled_tc = i40e_pf_get_tc_map(pf);
7655
7656 /* MFP mode setup queue map and update VSI */
7657 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7658 memset(&ctxt, 0, sizeof(ctxt));
7659 ctxt.seid = pf->main_vsi_seid;
7660 ctxt.pf_num = pf->hw.pf_id;
7661 ctxt.vf_num = 0;
7662 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7663 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7664 if (ret) {
7665 dev_info(&pf->pdev->dev,
7666 "update vsi failed, aq_err=%d\n",
7667 pf->hw.aq.asq_last_status);
7668 ret = -ENOENT;
7669 goto err;
7670 }
7671 /* update the local VSI info queue map */
7672 i40e_vsi_update_queue_map(vsi, &ctxt);
7673 vsi->info.valid_sections = 0;
7674 } else {
7675 /* Default/Main VSI is only enabled for TC0
7676 * reconfigure it to enable all TCs that are
7677 * available on the port in SFP mode.
7678 */
7679 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7680 if (ret) {
7681 dev_info(&pf->pdev->dev,
7682 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7683 enabled_tc, ret,
7684 pf->hw.aq.asq_last_status);
7685 ret = -ENOENT;
7686 }
7687 }
7688 break;
7689
7690 case I40E_VSI_FDIR:
cbf61325
ASJ		 7691 ctxt.pf_num = hw->pf_id;
7692 ctxt.vf_num = 0;
7693 ctxt.uplink_seid = vsi->uplink_seid;
7694 ctxt.connection_type = 0x1; /* regular data port */
7695 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7696 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7697 break;
7698
7699 case I40E_VSI_VMDQ2:
7700 ctxt.pf_num = hw->pf_id;
7701 ctxt.vf_num = 0;
7702 ctxt.uplink_seid = vsi->uplink_seid;
7703 ctxt.connection_type = 0x1; /* regular data port */
7704 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7705
7706 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7707
7708 /* This VSI is connected to VEB so the switch_id
7709 * should be set to zero by default.
7710 */
7711 ctxt.info.switch_id = 0;
41c445ff
JB		 7712 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7713
7714 /* Setup the VSI tx/rx queue map for TC0 only for now */
7715 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7716 break;
7717
7718 case I40E_VSI_SRIOV:
7719 ctxt.pf_num = hw->pf_id;
7720 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7721 ctxt.uplink_seid = vsi->uplink_seid;
7722 ctxt.connection_type = 0x1; /* regular data port */
7723 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7724
7725 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7726
7727 /* This VSI is connected to VEB so the switch_id
7728 * should be set to zero by default.
7729 */
7730 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7731
7732 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7733 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7734 if (pf->vf[vsi->vf_id].spoofchk) {
7735 ctxt.info.valid_sections |=
7736 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7737 ctxt.info.sec_flags |=
7738 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7739 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7740 }
41c445ff
JB		 7741 /* Setup the VSI tx/rx queue map for TC0 only for now */
7742 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7743 break;
7744
38e00438
VD		 7745#ifdef I40E_FCOE
7746 case I40E_VSI_FCOE:
7747 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
7748 if (ret) {
7749 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
7750 return ret;
7751 }
7752 break;
7753
7754#endif /* I40E_FCOE */
41c445ff
JB		 7755 default:
7756 return -ENODEV;
7757 }
7758
7759 if (vsi->type != I40E_VSI_MAIN) {
7760 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7761 if (ret) {
7762 dev_info(&vsi->back->pdev->dev,
7763 "add vsi failed, aq_err=%d\n",
7764 vsi->back->hw.aq.asq_last_status);
7765 ret = -ENOENT;
7766 goto err;
7767 }
7768 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7769 vsi->info.valid_sections = 0;
7770 vsi->seid = ctxt.seid;
7771 vsi->id = ctxt.vsi_number;
7772 }
7773
7774 /* If macvlan filters already exist, force them to get loaded */
7775 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7776 f->changed = true;
7777 f_count++;
6252c7e4
SN		 7778
7779 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 7780 struct i40e_aqc_remove_macvlan_element_data element;
7781
7782 memset(&element, 0, sizeof(element));
7783 ether_addr_copy(element.mac_addr, f->macaddr);
7784 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7785 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
7786 &element, 1, NULL);
7787 if (ret) {
7788 /* some older FW has a different default */
7789 element.flags |=
7790 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7791 i40e_aq_remove_macvlan(hw, vsi->seid,
7792 &element, 1, NULL);
7793 }
7794
7795 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 7796 I40E_AQC_WRITE_TYPE_LAA_WOL,
7797 f->macaddr, NULL);
7798 }
41c445ff
JB		 7799 }
7800 if (f_count) {
7801 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7802 pf->flags |= I40E_FLAG_FILTER_SYNC;
7803 }
7804
7805 /* Update VSI BW information */
7806 ret = i40e_vsi_get_bw_info(vsi);
7807 if (ret) {
7808 dev_info(&pf->pdev->dev,
7809 "couldn't get vsi bw info, err %d, aq_err %d\n",
7810 ret, pf->hw.aq.asq_last_status);
7811 /* VSI is already added so not tearing that up */
7812 ret = 0;
7813 }
7814
7815err:
7816 return ret;
7817}
7818
7819/**
7820 * i40e_vsi_release - Delete a VSI and free its resources
7821 * @vsi: the VSI being removed
7822 *
7823 * Returns 0 on success or < 0 on error
7824 **/
7825int i40e_vsi_release(struct i40e_vsi *vsi)
7826{
7827 struct i40e_mac_filter *f, *ftmp;
7828 struct i40e_veb *veb = NULL;
7829 struct i40e_pf *pf;
7830 u16 uplink_seid;
7831 int i, n;
7832
7833 pf = vsi->back;
7834
7835 /* release of a VEB-owner or last VSI is not allowed */
7836 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7837 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7838 vsi->seid, vsi->uplink_seid);
7839 return -ENODEV;
7840 }
7841 if (vsi == pf->vsi[pf->lan_vsi] &&
7842 !test_bit(__I40E_DOWN, &pf->state)) {
7843 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7844 return -ENODEV;
7845 }
7846
7847 uplink_seid = vsi->uplink_seid;
7848 if (vsi->type != I40E_VSI_SRIOV) {
7849 if (vsi->netdev_registered) {
7850 vsi->netdev_registered = false;
7851 if (vsi->netdev) {
7852 /* results in a call to i40e_close() */
7853 unregister_netdev(vsi->netdev);
41c445ff
JB		 7854 }
7855 } else {
90ef8d47 7856 i40e_vsi_close(vsi);
41c445ff
JB		 7857 }
7858 i40e_vsi_disable_irq(vsi);
7859 }
7860
7861 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7862 i40e_del_filter(vsi, f->macaddr, f->vlan,
7863 f->is_vf, f->is_netdev);
7864 i40e_sync_vsi_filters(vsi);
7865
7866 i40e_vsi_delete(vsi);
7867 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7868 if (vsi->netdev) {
7869 free_netdev(vsi->netdev);
7870 vsi->netdev = NULL;
7871 }
41c445ff
JB		 7872 i40e_vsi_clear_rings(vsi);
7873 i40e_vsi_clear(vsi);
7874
7875 /* If this was the last thing on the VEB, except for the
7876 * controlling VSI, remove the VEB, which puts the controlling
7877 * VSI onto the next level down in the switch.
7878 *
7879 * Well, okay, there's one more exception here: don't remove
7880 * the orphan VEBs yet. We'll wait for an explicit remove request
7881 * from up the network stack.
7882 */
505682cd 7883 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7884 if (pf->vsi[i] &&
7885 pf->vsi[i]->uplink_seid == uplink_seid &&
7886 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7887 n++; /* count the VSIs */
7888 }
7889 }
7890 for (i = 0; i < I40E_MAX_VEB; i++) {
7891 if (!pf->veb[i])
7892 continue;
7893 if (pf->veb[i]->uplink_seid == uplink_seid)
7894 n++; /* count the VEBs */
7895 if (pf->veb[i]->seid == uplink_seid)
7896 veb = pf->veb[i];
7897 }
7898 if (n == 0 && veb && veb->uplink_seid != 0)
7899 i40e_veb_release(veb);
7900
7901 return 0;
7902}
7903
7904/**
7905 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7906 * @vsi: ptr to the VSI
7907 *
7908 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7909 * corresponding SW VSI structure and initializes num_queue_pairs for the
7910 * newly allocated VSI.
7911 *
7912 * Returns 0 on success or negative on failure
7913 **/
7914static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7915{
7916 int ret = -ENOENT;
7917 struct i40e_pf *pf = vsi->back;
7918
493fb300 7919 if (vsi->q_vectors[0]) {
41c445ff
JB		 7920 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7921 vsi->seid);
7922 return -EEXIST;
7923 }
7924
7925 if (vsi->base_vector) {
f29eaa3d 7926 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7927 vsi->seid, vsi->base_vector);
7928 return -EEXIST;
7929 }
7930
90e04070 7931 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7932 if (ret) {
7933 dev_info(&pf->pdev->dev,
7934 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7935 vsi->num_q_vectors, vsi->seid, ret);
7936 vsi->num_q_vectors = 0;
7937 goto vector_setup_out;
7938 }
7939
958a3e3b
SN		 7940 if (vsi->num_q_vectors)
7941 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7942 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7943 if (vsi->base_vector < 0) {
7944 dev_info(&pf->pdev->dev,
f29eaa3d 7945 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7946 vsi->seid, vsi->base_vector);
7947 i40e_vsi_free_q_vectors(vsi);
7948 ret = -ENOENT;
7949 goto vector_setup_out;
7950 }
7951
7952vector_setup_out:
7953 return ret;
7954}
7955
bc7d338f
ASJ		 7956/**
7957 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7958 * @vsi: pointer to the vsi.
7959 *
7960 * This re-allocates a vsi's queue resources.
7961 *
7962 * Returns pointer to the successfully allocated and configured VSI sw struct
7963 * on success, otherwise returns NULL on failure.
7964 **/
7965static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7966{
7967 struct i40e_pf *pf = vsi->back;
7968 u8 enabled_tc;
7969 int ret;
7970
7971 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7972 i40e_vsi_clear_rings(vsi);
7973
7974 i40e_vsi_free_arrays(vsi, false);
7975 i40e_set_num_rings_in_vsi(vsi);
7976 ret = i40e_vsi_alloc_arrays(vsi, false);
7977 if (ret)
7978 goto err_vsi;
7979
7980 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7981 if (ret < 0) {
7982 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7983 vsi->seid, ret);
7984 goto err_vsi;
7985 }
7986 vsi->base_queue = ret;
7987
7988 /* Update the FW view of the VSI. Force a reset of TC and queue
7989 * layout configurations.
7990 */
7991 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7992 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7993 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7994 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7995
7996 /* assign it some queues */
7997 ret = i40e_alloc_rings(vsi);
7998 if (ret)
7999 goto err_rings;
8000
8001 /* map all of the rings to the q_vectors */
8002 i40e_vsi_map_rings_to_vectors(vsi);
8003 return vsi;
8004
8005err_rings:
8006 i40e_vsi_free_q_vectors(vsi);
8007 if (vsi->netdev_registered) {
8008 vsi->netdev_registered = false;
8009 unregister_netdev(vsi->netdev);
8010 free_netdev(vsi->netdev);
8011 vsi->netdev = NULL;
8012 }
8013 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8014err_vsi:
8015 i40e_vsi_clear(vsi);
8016 return NULL;
8017}
8018
41c445ff
JB		 8019/**
8020 * i40e_vsi_setup - Set up a VSI by a given type
8021 * @pf: board private structure
8022 * @type: VSI type
8023 * @uplink_seid: the switch element to link to
8024 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8025 *
8026 * This allocates the sw VSI structure and its queue resources, then add a VSI
8027 * to the identified VEB.
8028 *
8029 * Returns pointer to the successfully allocated and configure VSI sw struct on
8030 * success, otherwise returns NULL on failure.
8031 **/
8032struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8033 u16 uplink_seid, u32 param1)
8034{
8035 struct i40e_vsi *vsi = NULL;
8036 struct i40e_veb *veb = NULL;
8037 int ret, i;
8038 int v_idx;
8039
8040 /* The requested uplink_seid must be either
8041 * - the PF's port seid
8042 * no VEB is needed because this is the PF
8043 * or this is a Flow Director special case VSI
8044 * - seid of an existing VEB
8045 * - seid of a VSI that owns an existing VEB
8046 * - seid of a VSI that doesn't own a VEB
8047 * a new VEB is created and the VSI becomes the owner
8048 * - seid of the PF VSI, which is what creates the first VEB
8049 * this is a special case of the previous
8050 *
8051 * Find which uplink_seid we were given and create a new VEB if needed
8052 */
8053 for (i = 0; i < I40E_MAX_VEB; i++) {
8054 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8055 veb = pf->veb[i];
8056 break;
8057 }
8058 }
8059
8060 if (!veb && uplink_seid != pf->mac_seid) {
8061
505682cd 8062 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8063 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8064 vsi = pf->vsi[i];
8065 break;
8066 }
8067 }
8068 if (!vsi) {
8069 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8070 uplink_seid);
8071 return NULL;
8072 }
8073
8074 if (vsi->uplink_seid == pf->mac_seid)
8075 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8076 vsi->tc_config.enabled_tc);
8077 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8078 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8079 vsi->tc_config.enabled_tc);
8080
8081 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8082 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8083 veb = pf->veb[i];
8084 }
8085 if (!veb) {
8086 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8087 return NULL;
8088 }
8089
8090 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8091 uplink_seid = veb->seid;
8092 }
8093
8094 /* get vsi sw struct */
8095 v_idx = i40e_vsi_mem_alloc(pf, type);
8096 if (v_idx < 0)
8097 goto err_alloc;
8098 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8099 if (!vsi)
8100 goto err_alloc;
41c445ff
JB		 8101 vsi->type = type;
8102 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8103
8104 if (type == I40E_VSI_MAIN)
8105 pf->lan_vsi = v_idx;
8106 else if (type == I40E_VSI_SRIOV)
8107 vsi->vf_id = param1;
8108 /* assign it some queues */
cbf61325
ASJ		 8109 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8110 vsi->idx);
41c445ff
JB		 8111 if (ret < 0) {
8112 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
8113 vsi->seid, ret);
8114 goto err_vsi;
8115 }
8116 vsi->base_queue = ret;
8117
8118 /* get a VSI from the hardware */
8119 vsi->uplink_seid = uplink_seid;
8120 ret = i40e_add_vsi(vsi);
8121 if (ret)
8122 goto err_vsi;
8123
8124 switch (vsi->type) {
8125 /* setup the netdev if needed */
8126 case I40E_VSI_MAIN:
8127 case I40E_VSI_VMDQ2:
38e00438 8128 case I40E_VSI_FCOE:
41c445ff
JB		 8129 ret = i40e_config_netdev(vsi);
8130 if (ret)
8131 goto err_netdev;
8132 ret = register_netdev(vsi->netdev);
8133 if (ret)
8134 goto err_netdev;
8135 vsi->netdev_registered = true;
8136 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8137#ifdef CONFIG_I40E_DCB
8138 /* Setup DCB netlink interface */
8139 i40e_dcbnl_setup(vsi);
8140#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8141 /* fall through */
8142
8143 case I40E_VSI_FDIR:
8144 /* set up vectors and rings if needed */
8145 ret = i40e_vsi_setup_vectors(vsi);
8146 if (ret)
8147 goto err_msix;
8148
8149 ret = i40e_alloc_rings(vsi);
8150 if (ret)
8151 goto err_rings;
8152
8153 /* map all of the rings to the q_vectors */
8154 i40e_vsi_map_rings_to_vectors(vsi);
8155
8156 i40e_vsi_reset_stats(vsi);
8157 break;
8158
8159 default:
8160 /* no netdev or rings for the other VSI types */
8161 break;
8162 }
8163
8164 return vsi;
8165
8166err_rings:
8167 i40e_vsi_free_q_vectors(vsi);
8168err_msix:
8169 if (vsi->netdev_registered) {
8170 vsi->netdev_registered = false;
8171 unregister_netdev(vsi->netdev);
8172 free_netdev(vsi->netdev);
8173 vsi->netdev = NULL;
8174 }
8175err_netdev:
8176 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8177err_vsi:
8178 i40e_vsi_clear(vsi);
8179err_alloc:
8180 return NULL;
8181}
8182
8183/**
8184 * i40e_veb_get_bw_info - Query VEB BW information
8185 * @veb: the veb to query
8186 *
8187 * Query the Tx scheduler BW configuration data for given VEB
8188 **/
8189static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8190{
8191 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8192 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8193 struct i40e_pf *pf = veb->pf;
8194 struct i40e_hw *hw = &pf->hw;
8195 u32 tc_bw_max;
8196 int ret = 0;
8197 int i;
8198
8199 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8200 &bw_data, NULL);
8201 if (ret) {
8202 dev_info(&pf->pdev->dev,
8203 "query veb bw config failed, aq_err=%d\n",
8204 hw->aq.asq_last_status);
8205 goto out;
8206 }
8207
8208 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8209 &ets_data, NULL);
8210 if (ret) {
8211 dev_info(&pf->pdev->dev,
8212 "query veb bw ets config failed, aq_err=%d\n",
8213 hw->aq.asq_last_status);
8214 goto out;
8215 }
8216
8217 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8218 veb->bw_max_quanta = ets_data.tc_bw_max;
8219 veb->is_abs_credits = bw_data.absolute_credits_enable;
8220 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8221 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8222 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8223 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8224 veb->bw_tc_limit_credits[i] =
8225 le16_to_cpu(bw_data.tc_bw_limits[i]);
8226 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8227 }
8228
8229out:
8230 return ret;
8231}
8232
8233/**
8234 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8235 * @pf: board private structure
8236 *
8237 * On error: returns error code (negative)
8238 * On success: returns vsi index in PF (positive)
8239 **/
8240static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8241{
8242 int ret = -ENOENT;
8243 struct i40e_veb *veb;
8244 int i;
8245
8246 /* Need to protect the allocation of switch elements at the PF level */
8247 mutex_lock(&pf->switch_mutex);
8248
8249 /* VEB list may be fragmented if VEB creation/destruction has
8250 * been happening. We can afford to do a quick scan to look
8251 * for any free slots in the list.
8252 *
8253 * find next empty veb slot, looping back around if necessary
8254 */
8255 i = 0;
8256 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8257 i++;
8258 if (i >= I40E_MAX_VEB) {
8259 ret = -ENOMEM;
8260 goto err_alloc_veb; /* out of VEB slots! */
8261 }
8262
8263 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8264 if (!veb) {
8265 ret = -ENOMEM;
8266 goto err_alloc_veb;
8267 }
8268 veb->pf = pf;
8269 veb->idx = i;
8270 veb->enabled_tc = 1;
8271
8272 pf->veb[i] = veb;
8273 ret = i;
8274err_alloc_veb:
8275 mutex_unlock(&pf->switch_mutex);
8276 return ret;
8277}
8278
8279/**
8280 * i40e_switch_branch_release - Delete a branch of the switch tree
8281 * @branch: where to start deleting
8282 *
8283 * This uses recursion to find the tips of the branch to be
8284 * removed, deleting until we get back to and can delete this VEB.
8285 **/
8286static void i40e_switch_branch_release(struct i40e_veb *branch)
8287{
8288 struct i40e_pf *pf = branch->pf;
8289 u16 branch_seid = branch->seid;
8290 u16 veb_idx = branch->idx;
8291 int i;
8292
8293 /* release any VEBs on this VEB - RECURSION */
8294 for (i = 0; i < I40E_MAX_VEB; i++) {
8295 if (!pf->veb[i])
8296 continue;
8297 if (pf->veb[i]->uplink_seid == branch->seid)
8298 i40e_switch_branch_release(pf->veb[i]);
8299 }
8300
8301 /* Release the VSIs on this VEB, but not the owner VSI.
8302 *
8303 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8304 * the VEB itself, so don't use (*branch) after this loop.
8305 */
505682cd 8306 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8307 if (!pf->vsi[i])
8308 continue;
8309 if (pf->vsi[i]->uplink_seid == branch_seid &&
8310 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8311 i40e_vsi_release(pf->vsi[i]);
8312 }
8313 }
8314
8315 /* There's one corner case where the VEB might not have been
8316 * removed, so double check it here and remove it if needed.
8317 * This case happens if the veb was created from the debugfs
8318 * commands and no VSIs were added to it.
8319 */
8320 if (pf->veb[veb_idx])
8321 i40e_veb_release(pf->veb[veb_idx]);
8322}
8323
8324/**
8325 * i40e_veb_clear - remove veb struct
8326 * @veb: the veb to remove
8327 **/
8328static void i40e_veb_clear(struct i40e_veb *veb)
8329{
8330 if (!veb)
8331 return;
8332
8333 if (veb->pf) {
8334 struct i40e_pf *pf = veb->pf;
8335
8336 mutex_lock(&pf->switch_mutex);
8337 if (pf->veb[veb->idx] == veb)
8338 pf->veb[veb->idx] = NULL;
8339 mutex_unlock(&pf->switch_mutex);
8340 }
8341
8342 kfree(veb);
8343}
8344
8345/**
8346 * i40e_veb_release - Delete a VEB and free its resources
8347 * @veb: the VEB being removed
8348 **/
8349void i40e_veb_release(struct i40e_veb *veb)
8350{
8351 struct i40e_vsi *vsi = NULL;
8352 struct i40e_pf *pf;
8353 int i, n = 0;
8354
8355 pf = veb->pf;
8356
8357 /* find the remaining VSI and check for extras */
505682cd 8358 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8359 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8360 n++;
8361 vsi = pf->vsi[i];
8362 }
8363 }
8364 if (n != 1) {
8365 dev_info(&pf->pdev->dev,
8366 "can't remove VEB %d with %d VSIs left\n",
8367 veb->seid, n);
8368 return;
8369 }
8370
8371 /* move the remaining VSI to uplink veb */
8372 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8373 if (veb->uplink_seid) {
8374 vsi->uplink_seid = veb->uplink_seid;
8375 if (veb->uplink_seid == pf->mac_seid)
8376 vsi->veb_idx = I40E_NO_VEB;
8377 else
8378 vsi->veb_idx = veb->veb_idx;
8379 } else {
8380 /* floating VEB */
8381 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8382 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8383 }
8384
8385 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8386 i40e_veb_clear(veb);
41c445ff
JB		 8387}
8388
8389/**
8390 * i40e_add_veb - create the VEB in the switch
8391 * @veb: the VEB to be instantiated
8392 * @vsi: the controlling VSI
8393 **/
8394static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8395{
56747264 8396 bool is_default = false;
e1c51b95 8397 bool is_cloud = false;
41c445ff
JB		 8398 int ret;
8399
8400 /* get a VEB from the hardware */
8401 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8402 veb->enabled_tc, is_default,
8403 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8404 if (ret) {
8405 dev_info(&veb->pf->pdev->dev,
8406 "couldn't add VEB, err %d, aq_err %d\n",
8407 ret, veb->pf->hw.aq.asq_last_status);
8408 return -EPERM;
8409 }
8410
8411 /* get statistics counter */
8412 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8413 &veb->stats_idx, NULL, NULL, NULL);
8414 if (ret) {
8415 dev_info(&veb->pf->pdev->dev,
8416 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8417 ret, veb->pf->hw.aq.asq_last_status);
8418 return -EPERM;
8419 }
8420 ret = i40e_veb_get_bw_info(veb);
8421 if (ret) {
8422 dev_info(&veb->pf->pdev->dev,
8423 "couldn't get VEB bw info, err %d, aq_err %d\n",
8424 ret, veb->pf->hw.aq.asq_last_status);
8425 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8426 return -ENOENT;
8427 }
8428
8429 vsi->uplink_seid = veb->seid;
8430 vsi->veb_idx = veb->idx;
8431 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8432
8433 return 0;
8434}
8435
8436/**
8437 * i40e_veb_setup - Set up a VEB
8438 * @pf: board private structure
8439 * @flags: VEB setup flags
8440 * @uplink_seid: the switch element to link to
8441 * @vsi_seid: the initial VSI seid
8442 * @enabled_tc: Enabled TC bit-map
8443 *
8444 * This allocates the sw VEB structure and links it into the switch
8445 * It is possible and legal for this to be a duplicate of an already
8446 * existing VEB. It is also possible for both uplink and vsi seids
8447 * to be zero, in order to create a floating VEB.
8448 *
8449 * Returns pointer to the successfully allocated VEB sw struct on
8450 * success, otherwise returns NULL on failure.
8451 **/
8452struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8453 u16 uplink_seid, u16 vsi_seid,
8454 u8 enabled_tc)
8455{
8456 struct i40e_veb *veb, *uplink_veb = NULL;
8457 int vsi_idx, veb_idx;
8458 int ret;
8459
8460 /* if one seid is 0, the other must be 0 to create a floating relay */
8461 if ((uplink_seid == 0 || vsi_seid == 0) &&
8462 (uplink_seid + vsi_seid != 0)) {
8463 dev_info(&pf->pdev->dev,
8464 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8465 uplink_seid, vsi_seid);
8466 return NULL;
8467 }
8468
8469 /* make sure there is such a vsi and uplink */
505682cd 8470 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8471 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8472 break;
505682cd 8473 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8474 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8475 vsi_seid);
8476 return NULL;
8477 }
8478
8479 if (uplink_seid && uplink_seid != pf->mac_seid) {
8480 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8481 if (pf->veb[veb_idx] &&
8482 pf->veb[veb_idx]->seid == uplink_seid) {
8483 uplink_veb = pf->veb[veb_idx];
8484 break;
8485 }
8486 }
8487 if (!uplink_veb) {
8488 dev_info(&pf->pdev->dev,
8489 "uplink seid %d not found\n", uplink_seid);
8490 return NULL;
8491 }
8492 }
8493
8494 /* get veb sw struct */
8495 veb_idx = i40e_veb_mem_alloc(pf);
8496 if (veb_idx < 0)
8497 goto err_alloc;
8498 veb = pf->veb[veb_idx];
8499 veb->flags = flags;
8500 veb->uplink_seid = uplink_seid;
8501 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8502 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8503
8504 /* create the VEB in the switch */
8505 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8506 if (ret)
8507 goto err_veb;
1bb8b935
SN		 8508 if (vsi_idx == pf->lan_vsi)
8509 pf->lan_veb = veb->idx;
41c445ff
JB		 8510
8511 return veb;
8512
8513err_veb:
8514 i40e_veb_clear(veb);
8515err_alloc:
8516 return NULL;
8517}
8518
8519/**
8520 * i40e_setup_pf_switch_element - set pf vars based on switch type
8521 * @pf: board private structure
8522 * @ele: element we are building info from
8523 * @num_reported: total number of elements
8524 * @printconfig: should we print the contents
8525 *
8526 * helper function to assist in extracting a few useful SEID values.
8527 **/
8528static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8529 struct i40e_aqc_switch_config_element_resp *ele,
8530 u16 num_reported, bool printconfig)
8531{
8532 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8533 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8534 u8 element_type = ele->element_type;
8535 u16 seid = le16_to_cpu(ele->seid);
8536
8537 if (printconfig)
8538 dev_info(&pf->pdev->dev,
8539 "type=%d seid=%d uplink=%d downlink=%d\n",
8540 element_type, seid, uplink_seid, downlink_seid);
8541
8542 switch (element_type) {
8543 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8544 pf->mac_seid = seid;
8545 break;
8546 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8547 /* Main VEB? */
8548 if (uplink_seid != pf->mac_seid)
8549 break;
8550 if (pf->lan_veb == I40E_NO_VEB) {
8551 int v;
8552
8553 /* find existing or else empty VEB */
8554 for (v = 0; v < I40E_MAX_VEB; v++) {
8555 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8556 pf->lan_veb = v;
8557 break;
8558 }
8559 }
8560 if (pf->lan_veb == I40E_NO_VEB) {
8561 v = i40e_veb_mem_alloc(pf);
8562 if (v < 0)
8563 break;
8564 pf->lan_veb = v;
8565 }
8566 }
8567
8568 pf->veb[pf->lan_veb]->seid = seid;
8569 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8570 pf->veb[pf->lan_veb]->pf = pf;
8571 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8572 break;
8573 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8574 if (num_reported != 1)
8575 break;
8576 /* This is immediately after a reset so we can assume this is
8577 * the PF's VSI
8578 */
8579 pf->mac_seid = uplink_seid;
8580 pf->pf_seid = downlink_seid;
8581 pf->main_vsi_seid = seid;
8582 if (printconfig)
8583 dev_info(&pf->pdev->dev,
8584 "pf_seid=%d main_vsi_seid=%d\n",
8585 pf->pf_seid, pf->main_vsi_seid);
8586 break;
8587 case I40E_SWITCH_ELEMENT_TYPE_PF:
8588 case I40E_SWITCH_ELEMENT_TYPE_VF:
8589 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8590 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8591 case I40E_SWITCH_ELEMENT_TYPE_PE:
8592 case I40E_SWITCH_ELEMENT_TYPE_PA:
8593 /* ignore these for now */
8594 break;
8595 default:
8596 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8597 element_type, seid);
8598 break;
8599 }
8600}
8601
8602/**
8603 * i40e_fetch_switch_configuration - Get switch config from firmware
8604 * @pf: board private structure
8605 * @printconfig: should we print the contents
8606 *
8607 * Get the current switch configuration from the device and
8608 * extract a few useful SEID values.
8609 **/
8610int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8611{
8612 struct i40e_aqc_get_switch_config_resp *sw_config;
8613 u16 next_seid = 0;
8614 int ret = 0;
8615 u8 *aq_buf;
8616 int i;
8617
8618 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8619 if (!aq_buf)
8620 return -ENOMEM;
8621
8622 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8623 do {
8624 u16 num_reported, num_total;
8625
8626 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8627 I40E_AQ_LARGE_BUF,
8628 &next_seid, NULL);
8629 if (ret) {
8630 dev_info(&pf->pdev->dev,
8631 "get switch config failed %d aq_err=%x\n",
8632 ret, pf->hw.aq.asq_last_status);
8633 kfree(aq_buf);
8634 return -ENOENT;
8635 }
8636
8637 num_reported = le16_to_cpu(sw_config->header.num_reported);
8638 num_total = le16_to_cpu(sw_config->header.num_total);
8639
8640 if (printconfig)
8641 dev_info(&pf->pdev->dev,
8642 "header: %d reported %d total\n",
8643 num_reported, num_total);
8644
41c445ff
JB		 8645 for (i = 0; i < num_reported; i++) {
8646 struct i40e_aqc_switch_config_element_resp *ele =
8647 &sw_config->element[i];
8648
8649 i40e_setup_pf_switch_element(pf, ele, num_reported,
8650 printconfig);
8651 }
8652 } while (next_seid != 0);
8653
8654 kfree(aq_buf);
8655 return ret;
8656}
8657
8658/**
8659 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8660 * @pf: board private structure
bc7d338f 8661 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8662 *
8663 * Returns 0 on success, negative value on failure
8664 **/
bc7d338f 8665static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 8666{
8667 int ret;
8668
8669 /* find out what's out there already */
8670 ret = i40e_fetch_switch_configuration(pf, false);
8671 if (ret) {
8672 dev_info(&pf->pdev->dev,
8673 "couldn't fetch switch config, err %d, aq_err %d\n",
8674 ret, pf->hw.aq.asq_last_status);
8675 return ret;
8676 }
8677 i40e_pf_reset_stats(pf);
8678
41c445ff 8679 /* first time setup */
bc7d338f 8680 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8681 struct i40e_vsi *vsi = NULL;
8682 u16 uplink_seid;
8683
8684 /* Set up the PF VSI associated with the PF's main VSI
8685 * that is already in the HW switch
8686 */
8687 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8688 uplink_seid = pf->veb[pf->lan_veb]->seid;
8689 else
8690 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8691 if (pf->lan_vsi == I40E_NO_VSI)
8692 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8693 else if (reinit)
8694 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8695 if (!vsi) {
8696 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8697 i40e_fdir_teardown(pf);
8698 return -EAGAIN;
8699 }
41c445ff
JB		 8700 } else {
8701 /* force a reset of TC and queue layout configurations */
8702 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8703 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8704 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8705 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8706 }
8707 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8708
cbf61325
ASJ		 8709 i40e_fdir_sb_setup(pf);
8710
41c445ff
JB		 8711 /* Setup static PF queue filter control settings */
8712 ret = i40e_setup_pf_filter_control(pf);
8713 if (ret) {
8714 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8715 ret);
8716 /* Failure here should not stop continuing other steps */
8717 }
8718
8719 /* enable RSS in the HW, even for only one queue, as the stack can use
8720 * the hash
8721 */
8722 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8723 i40e_config_rss(pf);
8724
8725 /* fill in link information and enable LSE reporting */
a34a6711
MW		 8726 i40e_update_link_info(&pf->hw, true);
8727 i40e_link_event(pf);
8728
8729 /* Initialize user-specific link properties */
8730 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8731 I40E_AQ_AN_COMPLETED) ? true : false);
8732
8733 /* fill in link information and enable LSE reporting */
8109e123 8734 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 8735 i40e_link_event(pf);
8736
d52c20b7 8737 /* Initialize user-specific link properties */
41c445ff
JB		 8738 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8739 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 8740
beb0dff1
JK		 8741 i40e_ptp_init(pf);
8742
41c445ff
JB		 8743 return ret;
8744}
8745
41c445ff
JB		 8746/**
8747 * i40e_determine_queue_usage - Work out queue distribution
8748 * @pf: board private structure
8749 **/
8750static void i40e_determine_queue_usage(struct i40e_pf *pf)
8751{
41c445ff
JB		 8752 int queues_left;
8753
8754 pf->num_lan_qps = 0;
38e00438
VD		 8755#ifdef I40E_FCOE
8756 pf->num_fcoe_qps = 0;
8757#endif
41c445ff
JB		 8758
8759 /* Find the max queues to be put into basic use. We'll always be
8760 * using TC0, whether or not DCB is running, and TC0 will get the
8761 * big RSS set.
8762 */
8763 queues_left = pf->hw.func_caps.num_tx_qp;
8764
cbf61325 8765 if ((queues_left == 1) ||
9aa7e935 8766 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8767 /* one qp for PF, no queues for anything else */
8768 queues_left = 0;
8769 pf->rss_size = pf->num_lan_qps = 1;
8770
8771 /* make sure all the fancies are disabled */
60ea5f83 8772 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8773#ifdef I40E_FCOE
8774 I40E_FLAG_FCOE_ENABLED |
8775#endif
60ea5f83
JB		 8776 I40E_FLAG_FD_SB_ENABLED |
8777 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8778 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8779 I40E_FLAG_SRIOV_ENABLED |
8780 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8781 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8782 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8783 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8784 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8785 /* one qp for PF */
8786 pf->rss_size = pf->num_lan_qps = 1;
8787 queues_left -= pf->num_lan_qps;
8788
8789 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8790#ifdef I40E_FCOE
8791 I40E_FLAG_FCOE_ENABLED |
8792#endif
9aa7e935
FZ		 8793 I40E_FLAG_FD_SB_ENABLED |
8794 I40E_FLAG_FD_ATR_ENABLED |
8795 I40E_FLAG_DCB_ENABLED |
8796 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8797 } else {
cbf61325 8798 /* Not enough queues for all TCs */
4d9b6043 8799 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8800 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8801 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8802 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8803 }
8804 pf->num_lan_qps = pf->rss_size_max;
8805 queues_left -= pf->num_lan_qps;
8806 }
8807
38e00438
VD		 8808#ifdef I40E_FCOE
8809 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
8810 if (I40E_DEFAULT_FCOE <= queues_left) {
8811 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
8812 } else if (I40E_MINIMUM_FCOE <= queues_left) {
8813 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
8814 } else {
8815 pf->num_fcoe_qps = 0;
8816 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
8817 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
8818 }
8819
8820 queues_left -= pf->num_fcoe_qps;
8821 }
8822
8823#endif
cbf61325
ASJ		 8824 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8825 if (queues_left > 1) {
8826 queues_left -= 1; /* save 1 queue for FD */
8827 } else {
8828 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8829 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8830 }
41c445ff
JB		 8831 }
8832
8833 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8834 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8835 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8836 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8837 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8838 }
8839
8840 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8841 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8842 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8843 (queues_left / pf->num_vmdq_qps));
8844 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8845 }
8846
f8ff1464 8847 pf->queues_left = queues_left;
38e00438
VD		 8848#ifdef I40E_FCOE
8849 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
8850#endif
41c445ff
JB		 8851}
8852
8853/**
8854 * i40e_setup_pf_filter_control - Setup PF static filter control
8855 * @pf: PF to be setup
8856 *
8857 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8858 * settings. If PE/FCoE are enabled then it will also set the per PF
8859 * based filter sizes required for them. It also enables Flow director,
8860 * ethertype and macvlan type filter settings for the pf.
8861 *
8862 * Returns 0 on success, negative on failure
8863 **/
8864static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8865{
8866 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8867
8868 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8869
8870 /* Flow Director is enabled */
60ea5f83 8871 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8872 settings->enable_fdir = true;
8873
8874 /* Ethtype and MACVLAN filters enabled for PF */
8875 settings->enable_ethtype = true;
8876 settings->enable_macvlan = true;
8877
8878 if (i40e_set_filter_control(&pf->hw, settings))
8879 return -ENOENT;
8880
8881 return 0;
8882}
8883
0c22b3dd
JB		 8884#define INFO_STRING_LEN 255
8885static void i40e_print_features(struct i40e_pf *pf)
8886{
8887 struct i40e_hw *hw = &pf->hw;
8888 char *buf, *string;
8889
8890 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8891 if (!string) {
8892 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8893 return;
8894 }
8895
8896 buf = string;
8897
8898 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8899#ifdef CONFIG_PCI_IOV
8900 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8901#endif
8902 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8903 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8904
8905 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8906 buf += sprintf(buf, "RSS ");
0c22b3dd 8907 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8908 buf += sprintf(buf, "FD_ATR ");
8909 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8910 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8911 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8912 }
4d9b6043 8913 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8914 buf += sprintf(buf, "DCB ");
8915 if (pf->flags & I40E_FLAG_PTP)
8916 buf += sprintf(buf, "PTP ");
38e00438
VD		 8917#ifdef I40E_FCOE
8918 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
8919 buf += sprintf(buf, "FCOE ");
8920#endif
0c22b3dd
JB		 8921
8922 BUG_ON(buf > (string + INFO_STRING_LEN));
8923 dev_info(&pf->pdev->dev, "%s\n", string);
8924 kfree(string);
8925}
8926
41c445ff
JB		 8927/**
8928 * i40e_probe - Device initialization routine
8929 * @pdev: PCI device information struct
8930 * @ent: entry in i40e_pci_tbl
8931 *
8932 * i40e_probe initializes a pf identified by a pci_dev structure.
8933 * The OS initialization, configuring of the pf private structure,
8934 * and a hardware reset occur.
8935 *
8936 * Returns 0 on success, negative on failure
8937 **/
8938static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8939{
41c445ff
JB		 8940 struct i40e_pf *pf;
8941 struct i40e_hw *hw;
93cd765b 8942 static u16 pfs_found;
d4dfb81a 8943 u16 link_status;
41c445ff
JB		 8944 int err = 0;
8945 u32 len;
8a9eb7d3 8946 u32 i;
41c445ff
JB		 8947
8948 err = pci_enable_device_mem(pdev);
8949 if (err)
8950 return err;
8951
8952 /* set up for high or low dma */
6494294f 8953 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8954 if (err) {
e3e3bfdd
JS		 8955 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8956 if (err) {
8957 dev_err(&pdev->dev,
8958 "DMA configuration failed: 0x%x\n", err);
8959 goto err_dma;
8960 }
41c445ff
JB		 8961 }
8962
8963 /* set up pci connections */
8964 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8965 IORESOURCE_MEM), i40e_driver_name);
8966 if (err) {
8967 dev_info(&pdev->dev,
8968 "pci_request_selected_regions failed %d\n", err);
8969 goto err_pci_reg;
8970 }
8971
8972 pci_enable_pcie_error_reporting(pdev);
8973 pci_set_master(pdev);
8974
8975 /* Now that we have a PCI connection, we need to do the
8976 * low level device setup. This is primarily setting up
8977 * the Admin Queue structures and then querying for the
8978 * device's current profile information.
8979 */
8980 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8981 if (!pf) {
8982 err = -ENOMEM;
8983 goto err_pf_alloc;
8984 }
8985 pf->next_vsi = 0;
8986 pf->pdev = pdev;
8987 set_bit(__I40E_DOWN, &pf->state);
8988
8989 hw = &pf->hw;
8990 hw->back = pf;
8991 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8992 pci_resource_len(pdev, 0));
8993 if (!hw->hw_addr) {
8994 err = -EIO;
8995 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8996 (unsigned int)pci_resource_start(pdev, 0),
8997 (unsigned int)pci_resource_len(pdev, 0), err);
8998 goto err_ioremap;
8999 }
9000 hw->vendor_id = pdev->vendor;
9001 hw->device_id = pdev->device;
9002 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9003 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9004 hw->subsystem_device_id = pdev->subsystem_device;
9005 hw->bus.device = PCI_SLOT(pdev->devfn);
9006 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9007 pf->instance = pfs_found;
41c445ff 9008
7134f9ce
JB		 9009 /* do a special CORER for clearing PXE mode once at init */
9010 if (hw->revision_id == 0 &&
9011 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9012 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9013 i40e_flush(hw);
9014 msleep(200);
9015 pf->corer_count++;
9016
9017 i40e_clear_pxe_mode(hw);
9018 }
9019
41c445ff 9020 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9021 i40e_clear_hw(hw);
41c445ff
JB		 9022 err = i40e_pf_reset(hw);
9023 if (err) {
9024 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9025 goto err_pf_reset;
9026 }
9027 pf->pfr_count++;
9028
9029 hw->aq.num_arq_entries = I40E_AQ_LEN;
9030 hw->aq.num_asq_entries = I40E_AQ_LEN;
9031 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9032 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9033 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
9034 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
9035 "%s-pf%d:misc",
9036 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
9037
9038 err = i40e_init_shared_code(hw);
9039 if (err) {
9040 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9041 goto err_pf_reset;
9042 }
9043
d52c20b7
JB		 9044 /* set up a default setting for link flow control */
9045 pf->hw.fc.requested_mode = I40E_FC_NONE;
9046
41c445ff
JB		 9047 err = i40e_init_adminq(hw);
9048 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9049 if (err) {
9050 dev_info(&pdev->dev,
7aa67613 9051 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9052 goto err_pf_reset;
9053 }
9054
7aa67613
CS		 9055 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9056 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9057 dev_info(&pdev->dev,
7aa67613
CS		 9058 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9059 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9060 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9061 dev_info(&pdev->dev,
7aa67613 9062 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9063
9064
4eb3f768
SN		 9065 i40e_verify_eeprom(pf);
9066
2c5fe33b
JB		 9067 /* Rev 0 hardware was never productized */
9068 if (hw->revision_id < 1)
9069 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9070
6ff4ef86 9071 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9072 err = i40e_get_capabilities(pf);
9073 if (err)
9074 goto err_adminq_setup;
9075
9076 err = i40e_sw_init(pf);
9077 if (err) {
9078 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9079 goto err_sw_init;
9080 }
9081
9082 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9083 hw->func_caps.num_rx_qp,
9084 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9085 if (err) {
9086 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9087 goto err_init_lan_hmc;
9088 }
9089
9090 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9091 if (err) {
9092 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9093 err = -ENOENT;
9094 goto err_configure_lan_hmc;
9095 }
9096
9097 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9098 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9099 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9100 err = -EIO;
9101 goto err_mac_addr;
9102 }
9103 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9104 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9105 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9106 if (is_valid_ether_addr(hw->mac.port_addr))
9107 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9108#ifdef I40E_FCOE
9109 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9110 if (err)
9111 dev_info(&pdev->dev,
9112 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9113 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9114 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9115 hw->mac.san_addr);
9116 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9117 }
9118 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9119#endif /* I40E_FCOE */
41c445ff
JB		 9120
9121 pci_set_drvdata(pdev, pf);
9122 pci_save_state(pdev);
4e3b35b0
NP		 9123#ifdef CONFIG_I40E_DCB
9124 err = i40e_init_pf_dcb(pf);
9125 if (err) {
9126 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 9127 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9128 /* Continue without DCB enabled */
4e3b35b0
NP		 9129 }
9130#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9131
9132 /* set up periodic task facility */
9133 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9134 pf->service_timer_period = HZ;
9135
9136 INIT_WORK(&pf->service_task, i40e_service_task);
9137 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9138 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9139 pf->link_check_timeout = jiffies;
9140
8e2773ae
SN		 9141 /* WoL defaults to disabled */
9142 pf->wol_en = false;
9143 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9144
41c445ff
JB		 9145 /* set up the main switch operations */
9146 i40e_determine_queue_usage(pf);
9147 i40e_init_interrupt_scheme(pf);
9148
505682cd
MW		 9149 /* The number of VSIs reported by the FW is the minimum guaranteed
9150 * to us; HW supports far more and we share the remaining pool with
9151 * the other PFs. We allocate space for more than the guarantee with
9152 * the understanding that we might not get them all later.
41c445ff 9153 */
505682cd
MW		 9154 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9155 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9156 else
9157 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9158
9159 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9160 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9161 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9162 if (!pf->vsi) {
9163 err = -ENOMEM;
41c445ff 9164 goto err_switch_setup;
ed87ac09 9165 }
41c445ff 9166
bc7d338f 9167 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9168 if (err) {
9169 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9170 goto err_vsis;
9171 }
8a9eb7d3 9172 /* if FDIR VSI was set up, start it now */
505682cd 9173 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9174 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9175 i40e_vsi_open(pf->vsi[i]);
9176 break;
9177 }
9178 }
41c445ff 9179
7e2453fe
JB		 9180 /* driver is only interested in link up/down and module qualification
9181 * reports from firmware
9182 */
9183 err = i40e_aq_set_phy_int_mask(&pf->hw,
9184 I40E_AQ_EVENT_LINK_UPDOWN |
9185 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9186 if (err)
9187 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9188
cafa2ee6
ASJ		 9189 msleep(75);
9190 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9191 if (err) {
9192 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9193 pf->hw.aq.asq_last_status);
9194 }
9195
41c445ff
JB		 9196 /* The main driver is (mostly) up and happy. We need to set this state
9197 * before setting up the misc vector or we get a race and the vector
9198 * ends up disabled forever.
9199 */
9200 clear_bit(__I40E_DOWN, &pf->state);
9201
9202 /* In case of MSIX we are going to setup the misc vector right here
9203 * to handle admin queue events etc. In case of legacy and MSI
9204 * the misc functionality and queue processing is combined in
9205 * the same vector and that gets setup at open.
9206 */
9207 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9208 err = i40e_setup_misc_vector(pf);
9209 if (err) {
9210 dev_info(&pdev->dev,
9211 "setup of misc vector failed: %d\n", err);
9212 goto err_vsis;
9213 }
9214 }
9215
df805f62 9216#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9217 /* prep for VF support */
9218 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9219 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9220 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9221 u32 val;
9222
9223 /* disable link interrupts for VFs */
9224 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9225 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9226 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9227 i40e_flush(hw);
4aeec010
MW		 9228
9229 if (pci_num_vf(pdev)) {
9230 dev_info(&pdev->dev,
9231 "Active VFs found, allocating resources.\n");
9232 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9233 if (err)
9234 dev_info(&pdev->dev,
9235 "Error %d allocating resources for existing VFs\n",
9236 err);
9237 }
41c445ff 9238 }
df805f62 9239#endif /* CONFIG_PCI_IOV */
41c445ff 9240
93cd765b
ASJ		 9241 pfs_found++;
9242
41c445ff
JB		 9243 i40e_dbg_pf_init(pf);
9244
9245 /* tell the firmware that we're starting */
44033fac 9246 i40e_send_version(pf);
41c445ff
JB		 9247
9248 /* since everything's happy, start the service_task timer */
9249 mod_timer(&pf->service_timer,
9250 round_jiffies(jiffies + pf->service_timer_period));
9251
38e00438
VD		 9252#ifdef I40E_FCOE
9253 /* create FCoE interface */
9254 i40e_fcoe_vsi_setup(pf);
9255
9256#endif
d4dfb81a
CS		 9257 /* Get the negotiated link width and speed from PCI config space */
9258 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9259
9260 i40e_set_pci_config_data(hw, link_status);
9261
69bfb110 9262 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9263 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9264 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9265 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9266 "Unknown"),
9267 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9268 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9269 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9270 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9271 "Unknown"));
9272
9273 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9274 hw->bus.speed < i40e_bus_speed_8000) {
9275 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9276 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9277 }
9278
0c22b3dd
JB		 9279 /* print a string summarizing features */
9280 i40e_print_features(pf);
9281
41c445ff
JB		 9282 return 0;
9283
9284 /* Unwind what we've done if something failed in the setup */
9285err_vsis:
9286 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9287 i40e_clear_interrupt_scheme(pf);
9288 kfree(pf->vsi);
04b03013
SN		 9289err_switch_setup:
9290 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9291 del_timer_sync(&pf->service_timer);
9292err_mac_addr:
9293err_configure_lan_hmc:
9294 (void)i40e_shutdown_lan_hmc(hw);
9295err_init_lan_hmc:
9296 kfree(pf->qp_pile);
9297 kfree(pf->irq_pile);
9298err_sw_init:
9299err_adminq_setup:
9300 (void)i40e_shutdown_adminq(hw);
9301err_pf_reset:
9302 iounmap(hw->hw_addr);
9303err_ioremap:
9304 kfree(pf);
9305err_pf_alloc:
9306 pci_disable_pcie_error_reporting(pdev);
9307 pci_release_selected_regions(pdev,
9308 pci_select_bars(pdev, IORESOURCE_MEM));
9309err_pci_reg:
9310err_dma:
9311 pci_disable_device(pdev);
9312 return err;
9313}
9314
9315/**
9316 * i40e_remove - Device removal routine
9317 * @pdev: PCI device information struct
9318 *
9319 * i40e_remove is called by the PCI subsystem to alert the driver
9320 * that is should release a PCI device. This could be caused by a
9321 * Hot-Plug event, or because the driver is going to be removed from
9322 * memory.
9323 **/
9324static void i40e_remove(struct pci_dev *pdev)
9325{
9326 struct i40e_pf *pf = pci_get_drvdata(pdev);
9327 i40e_status ret_code;
41c445ff
JB		 9328 int i;
9329
9330 i40e_dbg_pf_exit(pf);
9331
beb0dff1
JK		 9332 i40e_ptp_stop(pf);
9333
41c445ff
JB		 9334 /* no more scheduling of any task */
9335 set_bit(__I40E_DOWN, &pf->state);
9336 del_timer_sync(&pf->service_timer);
9337 cancel_work_sync(&pf->service_task);
9338
eb2d80bc
MW		 9339 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9340 i40e_free_vfs(pf);
9341 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9342 }
9343
41c445ff
JB		 9344 i40e_fdir_teardown(pf);
9345
9346 /* If there is a switch structure or any orphans, remove them.
9347 * This will leave only the PF's VSI remaining.
9348 */
9349 for (i = 0; i < I40E_MAX_VEB; i++) {
9350 if (!pf->veb[i])
9351 continue;
9352
9353 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9354 pf->veb[i]->uplink_seid == 0)
9355 i40e_switch_branch_release(pf->veb[i]);
9356 }
9357
9358 /* Now we can shutdown the PF's VSI, just before we kill
9359 * adminq and hmc.
9360 */
9361 if (pf->vsi[pf->lan_vsi])
9362 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9363
9364 i40e_stop_misc_vector(pf);
9365 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9366 synchronize_irq(pf->msix_entries[0].vector);
9367 free_irq(pf->msix_entries[0].vector, pf);
9368 }
9369
9370 /* shutdown and destroy the HMC */
60442dea
SN		 9371 if (pf->hw.hmc.hmc_obj) {
9372 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9373 if (ret_code)
9374 dev_warn(&pdev->dev,
9375 "Failed to destroy the HMC resources: %d\n",
9376 ret_code);
9377 }
41c445ff
JB		 9378
9379 /* shutdown the adminq */
41c445ff
JB		 9380 ret_code = i40e_shutdown_adminq(&pf->hw);
9381 if (ret_code)
9382 dev_warn(&pdev->dev,
9383 "Failed to destroy the Admin Queue resources: %d\n",
9384 ret_code);
9385
9386 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9387 i40e_clear_interrupt_scheme(pf);
505682cd 9388 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9389 if (pf->vsi[i]) {
9390 i40e_vsi_clear_rings(pf->vsi[i]);
9391 i40e_vsi_clear(pf->vsi[i]);
9392 pf->vsi[i] = NULL;
9393 }
9394 }
9395
9396 for (i = 0; i < I40E_MAX_VEB; i++) {
9397 kfree(pf->veb[i]);
9398 pf->veb[i] = NULL;
9399 }
9400
9401 kfree(pf->qp_pile);
9402 kfree(pf->irq_pile);
41c445ff
JB		 9403 kfree(pf->vsi);
9404
41c445ff
JB		 9405 iounmap(pf->hw.hw_addr);
9406 kfree(pf);
9407 pci_release_selected_regions(pdev,
9408 pci_select_bars(pdev, IORESOURCE_MEM));
9409
9410 pci_disable_pcie_error_reporting(pdev);
9411 pci_disable_device(pdev);
9412}
9413
9414/**
9415 * i40e_pci_error_detected - warning that something funky happened in PCI land
9416 * @pdev: PCI device information struct
9417 *
9418 * Called to warn that something happened and the error handling steps
9419 * are in progress. Allows the driver to quiesce things, be ready for
9420 * remediation.
9421 **/
9422static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9423 enum pci_channel_state error)
9424{
9425 struct i40e_pf *pf = pci_get_drvdata(pdev);
9426
9427 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9428
9429 /* shutdown all operations */
9007bccd
SN		 9430 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9431 rtnl_lock();
9432 i40e_prep_for_reset(pf);
9433 rtnl_unlock();
9434 }
41c445ff
JB		 9435
9436 /* Request a slot reset */
9437 return PCI_ERS_RESULT_NEED_RESET;
9438}
9439
9440/**
9441 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9442 * @pdev: PCI device information struct
9443 *
9444 * Called to find if the driver can work with the device now that
9445 * the pci slot has been reset. If a basic connection seems good
9446 * (registers are readable and have sane content) then return a
9447 * happy little PCI_ERS_RESULT_xxx.
9448 **/
9449static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9450{
9451 struct i40e_pf *pf = pci_get_drvdata(pdev);
9452 pci_ers_result_t result;
9453 int err;
9454 u32 reg;
9455
9456 dev_info(&pdev->dev, "%s\n", __func__);
9457 if (pci_enable_device_mem(pdev)) {
9458 dev_info(&pdev->dev,
9459 "Cannot re-enable PCI device after reset.\n");
9460 result = PCI_ERS_RESULT_DISCONNECT;
9461 } else {
9462 pci_set_master(pdev);
9463 pci_restore_state(pdev);
9464 pci_save_state(pdev);
9465 pci_wake_from_d3(pdev, false);
9466
9467 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9468 if (reg == 0)
9469 result = PCI_ERS_RESULT_RECOVERED;
9470 else
9471 result = PCI_ERS_RESULT_DISCONNECT;
9472 }
9473
9474 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9475 if (err) {
9476 dev_info(&pdev->dev,
9477 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9478 err);
9479 /* non-fatal, continue */
9480 }
9481
9482 return result;
9483}
9484
9485/**
9486 * i40e_pci_error_resume - restart operations after PCI error recovery
9487 * @pdev: PCI device information struct
9488 *
9489 * Called to allow the driver to bring things back up after PCI error
9490 * and/or reset recovery has finished.
9491 **/
9492static void i40e_pci_error_resume(struct pci_dev *pdev)
9493{
9494 struct i40e_pf *pf = pci_get_drvdata(pdev);
9495
9496 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9497 if (test_bit(__I40E_SUSPENDED, &pf->state))
9498 return;
9499
9500 rtnl_lock();
41c445ff 9501 i40e_handle_reset_warning(pf);
9007bccd
SN		 9502 rtnl_lock();
9503}
9504
9505/**
9506 * i40e_shutdown - PCI callback for shutting down
9507 * @pdev: PCI device information struct
9508 **/
9509static void i40e_shutdown(struct pci_dev *pdev)
9510{
9511 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9512 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9513
9514 set_bit(__I40E_SUSPENDED, &pf->state);
9515 set_bit(__I40E_DOWN, &pf->state);
9516 rtnl_lock();
9517 i40e_prep_for_reset(pf);
9518 rtnl_unlock();
9519
8e2773ae
SN		 9520 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9521 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9522
9007bccd 9523 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9524 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9525 pci_set_power_state(pdev, PCI_D3hot);
9526 }
9527}
9528
9529#ifdef CONFIG_PM
9530/**
9531 * i40e_suspend - PCI callback for moving to D3
9532 * @pdev: PCI device information struct
9533 **/
9534static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9535{
9536 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9537 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9538
9539 set_bit(__I40E_SUSPENDED, &pf->state);
9540 set_bit(__I40E_DOWN, &pf->state);
9541 rtnl_lock();
9542 i40e_prep_for_reset(pf);
9543 rtnl_unlock();
9544
8e2773ae
SN		 9545 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9546 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9547
9548 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9549 pci_set_power_state(pdev, PCI_D3hot);
9550
9551 return 0;
41c445ff
JB		 9552}
9553
9007bccd
SN		 9554/**
9555 * i40e_resume - PCI callback for waking up from D3
9556 * @pdev: PCI device information struct
9557 **/
9558static int i40e_resume(struct pci_dev *pdev)
9559{
9560 struct i40e_pf *pf = pci_get_drvdata(pdev);
9561 u32 err;
9562
9563 pci_set_power_state(pdev, PCI_D0);
9564 pci_restore_state(pdev);
9565 /* pci_restore_state() clears dev->state_saves, so
9566 * call pci_save_state() again to restore it.
9567 */
9568 pci_save_state(pdev);
9569
9570 err = pci_enable_device_mem(pdev);
9571 if (err) {
9572 dev_err(&pdev->dev,
9573 "%s: Cannot enable PCI device from suspend\n",
9574 __func__);
9575 return err;
9576 }
9577 pci_set_master(pdev);
9578
9579 /* no wakeup events while running */
9580 pci_wake_from_d3(pdev, false);
9581
9582 /* handling the reset will rebuild the device state */
9583 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9584 clear_bit(__I40E_DOWN, &pf->state);
9585 rtnl_lock();
9586 i40e_reset_and_rebuild(pf, false);
9587 rtnl_unlock();
9588 }
9589
9590 return 0;
9591}
9592
9593#endif
41c445ff
JB		 9594static const struct pci_error_handlers i40e_err_handler = {
9595 .error_detected = i40e_pci_error_detected,
9596 .slot_reset = i40e_pci_error_slot_reset,
9597 .resume = i40e_pci_error_resume,
9598};
9599
9600static struct pci_driver i40e_driver = {
9601 .name = i40e_driver_name,
9602 .id_table = i40e_pci_tbl,
9603 .probe = i40e_probe,
9604 .remove = i40e_remove,
9007bccd
SN		 9605#ifdef CONFIG_PM
9606 .suspend = i40e_suspend,
9607 .resume = i40e_resume,
9608#endif
9609 .shutdown = i40e_shutdown,
41c445ff
JB		 9610 .err_handler = &i40e_err_handler,
9611 .sriov_configure = i40e_pci_sriov_configure,
9612};
9613
9614/**
9615 * i40e_init_module - Driver registration routine
9616 *
9617 * i40e_init_module is the first routine called when the driver is
9618 * loaded. All it does is register with the PCI subsystem.
9619 **/
9620static int __init i40e_init_module(void)
9621{
9622 pr_info("%s: %s - version %s\n", i40e_driver_name,
9623 i40e_driver_string, i40e_driver_version_str);
9624 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9625 i40e_dbg_init();
9626 return pci_register_driver(&i40e_driver);
9627}
9628module_init(i40e_init_module);
9629
9630/**
9631 * i40e_exit_module - Driver exit cleanup routine
9632 *
9633 * i40e_exit_module is called just before the driver is removed
9634 * from memory.
9635 **/
9636static void __exit i40e_exit_module(void)
9637{
9638 pci_unregister_driver(&i40e_driver);
9639 i40e_dbg_exit();
9640}
9641module_exit(i40e_exit_module);
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