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41c445ff JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
4fc8c676 | 4 | * Copyright(c) 2013 - 2017 Intel Corporation. |
41c445ff JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
41c445ff JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
b499ffb0 SV |
27 | #include <linux/etherdevice.h> |
28 | #include <linux/of_net.h> | |
29 | #include <linux/pci.h> | |
0c8493d9 | 30 | #include <linux/bpf.h> |
b499ffb0 | 31 | |
41c445ff JB |
32 | /* Local includes */ |
33 | #include "i40e.h" | |
4eb3f768 | 34 | #include "i40e_diag.h" |
06a5f7f1 | 35 | #include <net/udp_tunnel.h> |
ed0980c4 SP |
36 | /* All i40e tracepoints are defined by the include below, which |
37 | * must be included exactly once across the whole kernel with | |
38 | * CREATE_TRACE_POINTS defined | |
39 | */ | |
40 | #define CREATE_TRACE_POINTS | |
41 | #include "i40e_trace.h" | |
41c445ff JB |
42 | |
43 | const char i40e_driver_name[] = "i40e"; | |
44 | static const char i40e_driver_string[] = | |
45 | "Intel(R) Ethernet Connection XL710 Network Driver"; | |
46 | ||
47 | #define DRV_KERN "-k" | |
48 | ||
15990832 BP |
49 | #define DRV_VERSION_MAJOR 2 |
50 | #define DRV_VERSION_MINOR 1 | |
2318b401 | 51 | #define DRV_VERSION_BUILD 14 |
41c445ff JB |
52 | #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ |
53 | __stringify(DRV_VERSION_MINOR) "." \ | |
54 | __stringify(DRV_VERSION_BUILD) DRV_KERN | |
55 | const char i40e_driver_version_str[] = DRV_VERSION; | |
8fb905b3 | 56 | static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation."; |
41c445ff JB |
57 | |
58 | /* a bit of forward declarations */ | |
59 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi); | |
373149fc | 60 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired); |
41c445ff JB |
61 | static int i40e_add_vsi(struct i40e_vsi *vsi); |
62 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi); | |
bc7d338f | 63 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit); |
41c445ff JB |
64 | static int i40e_setup_misc_vector(struct i40e_pf *pf); |
65 | static void i40e_determine_queue_usage(struct i40e_pf *pf); | |
66 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf); | |
373149fc MS |
67 | static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired); |
68 | static int i40e_reset(struct i40e_pf *pf); | |
69 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired); | |
cbf61325 | 70 | static void i40e_fdir_sb_setup(struct i40e_pf *pf); |
4e3b35b0 | 71 | static int i40e_veb_get_bw_info(struct i40e_veb *veb); |
2f4b411a AN |
72 | static int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, |
73 | struct i40e_cloud_filter *filter, | |
74 | bool add); | |
75 | static int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, | |
76 | struct i40e_cloud_filter *filter, | |
77 | bool add); | |
78 | static int i40e_get_capabilities(struct i40e_pf *pf, | |
79 | enum i40e_admin_queue_opc list_type); | |
80 | ||
41c445ff JB |
81 | |
82 | /* i40e_pci_tbl - PCI Device ID Table | |
83 | * | |
84 | * Last entry must be all 0s | |
85 | * | |
86 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
87 | * Class, Class Mask, private data (not used) } | |
88 | */ | |
9baa3c34 | 89 | static const struct pci_device_id i40e_pci_tbl[] = { |
ab60085e | 90 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0}, |
ab60085e | 91 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0}, |
ab60085e SN |
92 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0}, |
93 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0}, | |
ab60085e SN |
94 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, |
95 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, | |
96 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, | |
5960d33f | 97 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, |
bc5166b9 | 98 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, |
35dae51d ASJ |
99 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0}, |
100 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0}, | |
87e6c1d7 ASJ |
101 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0}, |
102 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0}, | |
103 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0}, | |
d6bf58c2 | 104 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0}, |
48a3b512 SN |
105 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
106 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0}, | |
3123237a CW |
107 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0}, |
108 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0}, | |
41c445ff JB |
109 | /* required last entry */ |
110 | {0, } | |
111 | }; | |
112 | MODULE_DEVICE_TABLE(pci, i40e_pci_tbl); | |
113 | ||
114 | #define I40E_MAX_VF_COUNT 128 | |
115 | static int debug = -1; | |
5d4ca23e AD |
116 | module_param(debug, uint, 0); |
117 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX)"); | |
41c445ff JB |
118 | |
119 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
120 | MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); | |
121 | MODULE_LICENSE("GPL"); | |
122 | MODULE_VERSION(DRV_VERSION); | |
123 | ||
2803b16c JB |
124 | static struct workqueue_struct *i40e_wq; |
125 | ||
41c445ff JB |
126 | /** |
127 | * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code | |
128 | * @hw: pointer to the HW structure | |
129 | * @mem: ptr to mem struct to fill out | |
130 | * @size: size of memory requested | |
131 | * @alignment: what to align the allocation to | |
132 | **/ | |
133 | int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem, | |
134 | u64 size, u32 alignment) | |
135 | { | |
136 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
137 | ||
138 | mem->size = ALIGN(size, alignment); | |
139 | mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size, | |
140 | &mem->pa, GFP_KERNEL); | |
93bc73b8 JB |
141 | if (!mem->va) |
142 | return -ENOMEM; | |
41c445ff | 143 | |
93bc73b8 | 144 | return 0; |
41c445ff JB |
145 | } |
146 | ||
147 | /** | |
148 | * i40e_free_dma_mem_d - OS specific memory free for shared code | |
149 | * @hw: pointer to the HW structure | |
150 | * @mem: ptr to mem struct to free | |
151 | **/ | |
152 | int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem) | |
153 | { | |
154 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
155 | ||
156 | dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa); | |
157 | mem->va = NULL; | |
158 | mem->pa = 0; | |
159 | mem->size = 0; | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | /** | |
165 | * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code | |
166 | * @hw: pointer to the HW structure | |
167 | * @mem: ptr to mem struct to fill out | |
168 | * @size: size of memory requested | |
169 | **/ | |
170 | int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem, | |
171 | u32 size) | |
172 | { | |
173 | mem->size = size; | |
174 | mem->va = kzalloc(size, GFP_KERNEL); | |
175 | ||
93bc73b8 JB |
176 | if (!mem->va) |
177 | return -ENOMEM; | |
41c445ff | 178 | |
93bc73b8 | 179 | return 0; |
41c445ff JB |
180 | } |
181 | ||
182 | /** | |
183 | * i40e_free_virt_mem_d - OS specific memory free for shared code | |
184 | * @hw: pointer to the HW structure | |
185 | * @mem: ptr to mem struct to free | |
186 | **/ | |
187 | int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem) | |
188 | { | |
189 | /* it's ok to kfree a NULL pointer */ | |
190 | kfree(mem->va); | |
191 | mem->va = NULL; | |
192 | mem->size = 0; | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * i40e_get_lump - find a lump of free generic resource | |
199 | * @pf: board private structure | |
200 | * @pile: the pile of resource to search | |
201 | * @needed: the number of items needed | |
202 | * @id: an owner id to stick on the items assigned | |
203 | * | |
204 | * Returns the base item index of the lump, or negative for error | |
205 | * | |
206 | * The search_hint trick and lack of advanced fit-finding only work | |
207 | * because we're highly likely to have all the same size lump requests. | |
208 | * Linear search time and any fragmentation should be minimal. | |
209 | **/ | |
210 | static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile, | |
211 | u16 needed, u16 id) | |
212 | { | |
213 | int ret = -ENOMEM; | |
ddf434ac | 214 | int i, j; |
41c445ff JB |
215 | |
216 | if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) { | |
217 | dev_info(&pf->pdev->dev, | |
218 | "param err: pile=%p needed=%d id=0x%04x\n", | |
219 | pile, needed, id); | |
220 | return -EINVAL; | |
221 | } | |
222 | ||
223 | /* start the linear search with an imperfect hint */ | |
224 | i = pile->search_hint; | |
ddf434ac | 225 | while (i < pile->num_entries) { |
41c445ff JB |
226 | /* skip already allocated entries */ |
227 | if (pile->list[i] & I40E_PILE_VALID_BIT) { | |
228 | i++; | |
229 | continue; | |
230 | } | |
231 | ||
232 | /* do we have enough in this lump? */ | |
233 | for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) { | |
234 | if (pile->list[i+j] & I40E_PILE_VALID_BIT) | |
235 | break; | |
236 | } | |
237 | ||
238 | if (j == needed) { | |
239 | /* there was enough, so assign it to the requestor */ | |
240 | for (j = 0; j < needed; j++) | |
241 | pile->list[i+j] = id | I40E_PILE_VALID_BIT; | |
242 | ret = i; | |
243 | pile->search_hint = i + j; | |
ddf434ac | 244 | break; |
41c445ff | 245 | } |
6995b36c JB |
246 | |
247 | /* not enough, so skip over it and continue looking */ | |
248 | i += j; | |
41c445ff JB |
249 | } |
250 | ||
251 | return ret; | |
252 | } | |
253 | ||
254 | /** | |
255 | * i40e_put_lump - return a lump of generic resource | |
256 | * @pile: the pile of resource to search | |
257 | * @index: the base item index | |
258 | * @id: the owner id of the items assigned | |
259 | * | |
260 | * Returns the count of items in the lump | |
261 | **/ | |
262 | static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id) | |
263 | { | |
264 | int valid_id = (id | I40E_PILE_VALID_BIT); | |
265 | int count = 0; | |
266 | int i; | |
267 | ||
268 | if (!pile || index >= pile->num_entries) | |
269 | return -EINVAL; | |
270 | ||
271 | for (i = index; | |
272 | i < pile->num_entries && pile->list[i] == valid_id; | |
273 | i++) { | |
274 | pile->list[i] = 0; | |
275 | count++; | |
276 | } | |
277 | ||
278 | if (count && index < pile->search_hint) | |
279 | pile->search_hint = index; | |
280 | ||
281 | return count; | |
282 | } | |
283 | ||
fdf0e0bf ASJ |
284 | /** |
285 | * i40e_find_vsi_from_id - searches for the vsi with the given id | |
286 | * @pf - the pf structure to search for the vsi | |
287 | * @id - id of the vsi it is searching for | |
288 | **/ | |
289 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id) | |
290 | { | |
291 | int i; | |
292 | ||
293 | for (i = 0; i < pf->num_alloc_vsi; i++) | |
294 | if (pf->vsi[i] && (pf->vsi[i]->id == id)) | |
295 | return pf->vsi[i]; | |
296 | ||
297 | return NULL; | |
298 | } | |
299 | ||
41c445ff JB |
300 | /** |
301 | * i40e_service_event_schedule - Schedule the service task to wake up | |
302 | * @pf: board private structure | |
303 | * | |
304 | * If not already scheduled, this puts the task into the work queue | |
305 | **/ | |
e3219ce6 | 306 | void i40e_service_event_schedule(struct i40e_pf *pf) |
41c445ff | 307 | { |
9e6c9c0f | 308 | if (!test_bit(__I40E_DOWN, pf->state) && |
0da36b97 | 309 | !test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
2803b16c | 310 | queue_work(i40e_wq, &pf->service_task); |
41c445ff JB |
311 | } |
312 | ||
313 | /** | |
314 | * i40e_tx_timeout - Respond to a Tx Hang | |
315 | * @netdev: network interface device structure | |
316 | * | |
317 | * If any port has noticed a Tx timeout, it is likely that the whole | |
318 | * device is munged, not just the one netdev port, so go for the full | |
319 | * reset. | |
320 | **/ | |
321 | static void i40e_tx_timeout(struct net_device *netdev) | |
322 | { | |
323 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
324 | struct i40e_vsi *vsi = np->vsi; | |
325 | struct i40e_pf *pf = vsi->back; | |
b03a8c1f KP |
326 | struct i40e_ring *tx_ring = NULL; |
327 | unsigned int i, hung_queue = 0; | |
328 | u32 head, val; | |
41c445ff JB |
329 | |
330 | pf->tx_timeout_count++; | |
331 | ||
b03a8c1f KP |
332 | /* find the stopped queue the same way the stack does */ |
333 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
334 | struct netdev_queue *q; | |
335 | unsigned long trans_start; | |
336 | ||
337 | q = netdev_get_tx_queue(netdev, i); | |
9b36627a | 338 | trans_start = q->trans_start; |
b03a8c1f KP |
339 | if (netif_xmit_stopped(q) && |
340 | time_after(jiffies, | |
341 | (trans_start + netdev->watchdog_timeo))) { | |
342 | hung_queue = i; | |
343 | break; | |
344 | } | |
345 | } | |
346 | ||
347 | if (i == netdev->num_tx_queues) { | |
348 | netdev_info(netdev, "tx_timeout: no netdev hung queue found\n"); | |
349 | } else { | |
350 | /* now that we have an index, find the tx_ring struct */ | |
351 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
352 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
353 | if (hung_queue == | |
354 | vsi->tx_rings[i]->queue_index) { | |
355 | tx_ring = vsi->tx_rings[i]; | |
356 | break; | |
357 | } | |
358 | } | |
359 | } | |
360 | } | |
361 | ||
41c445ff | 362 | if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20))) |
b03a8c1f KP |
363 | pf->tx_timeout_recovery_level = 1; /* reset after some time */ |
364 | else if (time_before(jiffies, | |
365 | (pf->tx_timeout_last_recovery + netdev->watchdog_timeo))) | |
366 | return; /* don't do any new action before the next timeout */ | |
367 | ||
368 | if (tx_ring) { | |
369 | head = i40e_get_head(tx_ring); | |
370 | /* Read interrupt register */ | |
371 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
372 | val = rd32(&pf->hw, | |
373 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
374 | tx_ring->vsi->base_vector - 1)); | |
375 | else | |
376 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
377 | ||
378 | netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n", | |
379 | vsi->seid, hung_queue, tx_ring->next_to_clean, | |
380 | head, tx_ring->next_to_use, | |
381 | readl(tx_ring->tail), val); | |
382 | } | |
383 | ||
41c445ff | 384 | pf->tx_timeout_last_recovery = jiffies; |
b03a8c1f KP |
385 | netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n", |
386 | pf->tx_timeout_recovery_level, hung_queue); | |
41c445ff JB |
387 | |
388 | switch (pf->tx_timeout_recovery_level) { | |
41c445ff | 389 | case 1: |
0da36b97 | 390 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff JB |
391 | break; |
392 | case 2: | |
0da36b97 | 393 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff JB |
394 | break; |
395 | case 3: | |
0da36b97 | 396 | set_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff JB |
397 | break; |
398 | default: | |
399 | netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); | |
41c445ff JB |
400 | break; |
401 | } | |
b03a8c1f | 402 | |
41c445ff JB |
403 | i40e_service_event_schedule(pf); |
404 | pf->tx_timeout_recovery_level++; | |
405 | } | |
406 | ||
41c445ff JB |
407 | /** |
408 | * i40e_get_vsi_stats_struct - Get System Network Statistics | |
409 | * @vsi: the VSI we care about | |
410 | * | |
411 | * Returns the address of the device statistics structure. | |
412 | * The statistics are actually updated from the service task. | |
413 | **/ | |
414 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi) | |
415 | { | |
416 | return &vsi->net_stats; | |
417 | } | |
418 | ||
74608d17 BT |
419 | /** |
420 | * i40e_get_netdev_stats_struct_tx - populate stats from a Tx ring | |
421 | * @ring: Tx ring to get statistics from | |
422 | * @stats: statistics entry to be updated | |
423 | **/ | |
424 | static void i40e_get_netdev_stats_struct_tx(struct i40e_ring *ring, | |
425 | struct rtnl_link_stats64 *stats) | |
426 | { | |
427 | u64 bytes, packets; | |
428 | unsigned int start; | |
429 | ||
430 | do { | |
431 | start = u64_stats_fetch_begin_irq(&ring->syncp); | |
432 | packets = ring->stats.packets; | |
433 | bytes = ring->stats.bytes; | |
434 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); | |
435 | ||
436 | stats->tx_packets += packets; | |
437 | stats->tx_bytes += bytes; | |
438 | } | |
439 | ||
41c445ff JB |
440 | /** |
441 | * i40e_get_netdev_stats_struct - Get statistics for netdev interface | |
442 | * @netdev: network interface device structure | |
443 | * | |
444 | * Returns the address of the device statistics structure. | |
445 | * The statistics are actually updated from the service task. | |
446 | **/ | |
9eed69a9 | 447 | static void i40e_get_netdev_stats_struct(struct net_device *netdev, |
bc1f4470 | 448 | struct rtnl_link_stats64 *stats) |
41c445ff JB |
449 | { |
450 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
e7046ee1 | 451 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff | 452 | struct i40e_vsi *vsi = np->vsi; |
980e9b11 AD |
453 | struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi); |
454 | int i; | |
455 | ||
0da36b97 | 456 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
bc1f4470 | 457 | return; |
bc7d338f | 458 | |
3c325ced | 459 | if (!vsi->tx_rings) |
bc1f4470 | 460 | return; |
3c325ced | 461 | |
980e9b11 AD |
462 | rcu_read_lock(); |
463 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
980e9b11 AD |
464 | u64 bytes, packets; |
465 | unsigned int start; | |
466 | ||
6aa7de05 | 467 | tx_ring = READ_ONCE(vsi->tx_rings[i]); |
980e9b11 AD |
468 | if (!tx_ring) |
469 | continue; | |
74608d17 | 470 | i40e_get_netdev_stats_struct_tx(tx_ring, stats); |
980e9b11 | 471 | |
980e9b11 AD |
472 | rx_ring = &tx_ring[1]; |
473 | ||
474 | do { | |
57a7744e | 475 | start = u64_stats_fetch_begin_irq(&rx_ring->syncp); |
980e9b11 AD |
476 | packets = rx_ring->stats.packets; |
477 | bytes = rx_ring->stats.bytes; | |
57a7744e | 478 | } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start)); |
41c445ff | 479 | |
980e9b11 AD |
480 | stats->rx_packets += packets; |
481 | stats->rx_bytes += bytes; | |
74608d17 BT |
482 | |
483 | if (i40e_enabled_xdp_vsi(vsi)) | |
484 | i40e_get_netdev_stats_struct_tx(&rx_ring[1], stats); | |
980e9b11 AD |
485 | } |
486 | rcu_read_unlock(); | |
487 | ||
a5282f44 | 488 | /* following stats updated by i40e_watchdog_subtask() */ |
980e9b11 AD |
489 | stats->multicast = vsi_stats->multicast; |
490 | stats->tx_errors = vsi_stats->tx_errors; | |
491 | stats->tx_dropped = vsi_stats->tx_dropped; | |
492 | stats->rx_errors = vsi_stats->rx_errors; | |
d8201e20 | 493 | stats->rx_dropped = vsi_stats->rx_dropped; |
980e9b11 AD |
494 | stats->rx_crc_errors = vsi_stats->rx_crc_errors; |
495 | stats->rx_length_errors = vsi_stats->rx_length_errors; | |
41c445ff JB |
496 | } |
497 | ||
498 | /** | |
499 | * i40e_vsi_reset_stats - Resets all stats of the given vsi | |
500 | * @vsi: the VSI to have its stats reset | |
501 | **/ | |
502 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi) | |
503 | { | |
504 | struct rtnl_link_stats64 *ns; | |
505 | int i; | |
506 | ||
507 | if (!vsi) | |
508 | return; | |
509 | ||
510 | ns = i40e_get_vsi_stats_struct(vsi); | |
511 | memset(ns, 0, sizeof(*ns)); | |
512 | memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets)); | |
513 | memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats)); | |
514 | memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets)); | |
8e9dca53 | 515 | if (vsi->rx_rings && vsi->rx_rings[0]) { |
41c445ff | 516 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
6995b36c | 517 | memset(&vsi->rx_rings[i]->stats, 0, |
9f65e15b | 518 | sizeof(vsi->rx_rings[i]->stats)); |
6995b36c | 519 | memset(&vsi->rx_rings[i]->rx_stats, 0, |
9f65e15b | 520 | sizeof(vsi->rx_rings[i]->rx_stats)); |
6995b36c | 521 | memset(&vsi->tx_rings[i]->stats, 0, |
9f65e15b AD |
522 | sizeof(vsi->tx_rings[i]->stats)); |
523 | memset(&vsi->tx_rings[i]->tx_stats, 0, | |
524 | sizeof(vsi->tx_rings[i]->tx_stats)); | |
41c445ff | 525 | } |
8e9dca53 | 526 | } |
41c445ff JB |
527 | vsi->stat_offsets_loaded = false; |
528 | } | |
529 | ||
530 | /** | |
b40c82e6 | 531 | * i40e_pf_reset_stats - Reset all of the stats for the given PF |
41c445ff JB |
532 | * @pf: the PF to be reset |
533 | **/ | |
534 | void i40e_pf_reset_stats(struct i40e_pf *pf) | |
535 | { | |
e91fdf76 SN |
536 | int i; |
537 | ||
41c445ff JB |
538 | memset(&pf->stats, 0, sizeof(pf->stats)); |
539 | memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); | |
540 | pf->stat_offsets_loaded = false; | |
e91fdf76 SN |
541 | |
542 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
543 | if (pf->veb[i]) { | |
544 | memset(&pf->veb[i]->stats, 0, | |
545 | sizeof(pf->veb[i]->stats)); | |
546 | memset(&pf->veb[i]->stats_offsets, 0, | |
547 | sizeof(pf->veb[i]->stats_offsets)); | |
548 | pf->veb[i]->stat_offsets_loaded = false; | |
549 | } | |
550 | } | |
42bce04e | 551 | pf->hw_csum_rx_error = 0; |
41c445ff JB |
552 | } |
553 | ||
554 | /** | |
555 | * i40e_stat_update48 - read and update a 48 bit stat from the chip | |
556 | * @hw: ptr to the hardware info | |
557 | * @hireg: the high 32 bit reg to read | |
558 | * @loreg: the low 32 bit reg to read | |
559 | * @offset_loaded: has the initial offset been loaded yet | |
560 | * @offset: ptr to current offset value | |
561 | * @stat: ptr to the stat | |
562 | * | |
563 | * Since the device stats are not reset at PFReset, they likely will not | |
564 | * be zeroed when the driver starts. We'll save the first values read | |
565 | * and use them as offsets to be subtracted from the raw values in order | |
566 | * to report stats that count from zero. In the process, we also manage | |
567 | * the potential roll-over. | |
568 | **/ | |
569 | static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, | |
570 | bool offset_loaded, u64 *offset, u64 *stat) | |
571 | { | |
572 | u64 new_data; | |
573 | ||
ab60085e | 574 | if (hw->device_id == I40E_DEV_ID_QEMU) { |
41c445ff JB |
575 | new_data = rd32(hw, loreg); |
576 | new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; | |
577 | } else { | |
578 | new_data = rd64(hw, loreg); | |
579 | } | |
580 | if (!offset_loaded) | |
581 | *offset = new_data; | |
582 | if (likely(new_data >= *offset)) | |
583 | *stat = new_data - *offset; | |
584 | else | |
41a1d04b | 585 | *stat = (new_data + BIT_ULL(48)) - *offset; |
41c445ff JB |
586 | *stat &= 0xFFFFFFFFFFFFULL; |
587 | } | |
588 | ||
589 | /** | |
590 | * i40e_stat_update32 - read and update a 32 bit stat from the chip | |
591 | * @hw: ptr to the hardware info | |
592 | * @reg: the hw reg to read | |
593 | * @offset_loaded: has the initial offset been loaded yet | |
594 | * @offset: ptr to current offset value | |
595 | * @stat: ptr to the stat | |
596 | **/ | |
597 | static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, | |
598 | bool offset_loaded, u64 *offset, u64 *stat) | |
599 | { | |
600 | u32 new_data; | |
601 | ||
602 | new_data = rd32(hw, reg); | |
603 | if (!offset_loaded) | |
604 | *offset = new_data; | |
605 | if (likely(new_data >= *offset)) | |
606 | *stat = (u32)(new_data - *offset); | |
607 | else | |
41a1d04b | 608 | *stat = (u32)((new_data + BIT_ULL(32)) - *offset); |
41c445ff JB |
609 | } |
610 | ||
0dc8692e MS |
611 | /** |
612 | * i40e_stat_update_and_clear32 - read and clear hw reg, update a 32 bit stat | |
613 | * @hw: ptr to the hardware info | |
614 | * @reg: the hw reg to read and clear | |
615 | * @stat: ptr to the stat | |
616 | **/ | |
617 | static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat) | |
618 | { | |
619 | u32 new_data = rd32(hw, reg); | |
620 | ||
621 | wr32(hw, reg, 1); /* must write a nonzero value to clear register */ | |
622 | *stat += new_data; | |
623 | } | |
624 | ||
41c445ff JB |
625 | /** |
626 | * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. | |
627 | * @vsi: the VSI to be updated | |
628 | **/ | |
629 | void i40e_update_eth_stats(struct i40e_vsi *vsi) | |
630 | { | |
631 | int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx); | |
632 | struct i40e_pf *pf = vsi->back; | |
633 | struct i40e_hw *hw = &pf->hw; | |
634 | struct i40e_eth_stats *oes; | |
635 | struct i40e_eth_stats *es; /* device's eth stats */ | |
636 | ||
637 | es = &vsi->eth_stats; | |
638 | oes = &vsi->eth_stats_offsets; | |
639 | ||
640 | /* Gather up the stats that the hw collects */ | |
641 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
642 | vsi->stat_offsets_loaded, | |
643 | &oes->tx_errors, &es->tx_errors); | |
644 | i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), | |
645 | vsi->stat_offsets_loaded, | |
646 | &oes->rx_discards, &es->rx_discards); | |
41a9e55c SN |
647 | i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx), |
648 | vsi->stat_offsets_loaded, | |
649 | &oes->rx_unknown_protocol, &es->rx_unknown_protocol); | |
650 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
651 | vsi->stat_offsets_loaded, | |
652 | &oes->tx_errors, &es->tx_errors); | |
41c445ff JB |
653 | |
654 | i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx), | |
655 | I40E_GLV_GORCL(stat_idx), | |
656 | vsi->stat_offsets_loaded, | |
657 | &oes->rx_bytes, &es->rx_bytes); | |
658 | i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), | |
659 | I40E_GLV_UPRCL(stat_idx), | |
660 | vsi->stat_offsets_loaded, | |
661 | &oes->rx_unicast, &es->rx_unicast); | |
662 | i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), | |
663 | I40E_GLV_MPRCL(stat_idx), | |
664 | vsi->stat_offsets_loaded, | |
665 | &oes->rx_multicast, &es->rx_multicast); | |
666 | i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), | |
667 | I40E_GLV_BPRCL(stat_idx), | |
668 | vsi->stat_offsets_loaded, | |
669 | &oes->rx_broadcast, &es->rx_broadcast); | |
670 | ||
671 | i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), | |
672 | I40E_GLV_GOTCL(stat_idx), | |
673 | vsi->stat_offsets_loaded, | |
674 | &oes->tx_bytes, &es->tx_bytes); | |
675 | i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), | |
676 | I40E_GLV_UPTCL(stat_idx), | |
677 | vsi->stat_offsets_loaded, | |
678 | &oes->tx_unicast, &es->tx_unicast); | |
679 | i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), | |
680 | I40E_GLV_MPTCL(stat_idx), | |
681 | vsi->stat_offsets_loaded, | |
682 | &oes->tx_multicast, &es->tx_multicast); | |
683 | i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), | |
684 | I40E_GLV_BPTCL(stat_idx), | |
685 | vsi->stat_offsets_loaded, | |
686 | &oes->tx_broadcast, &es->tx_broadcast); | |
687 | vsi->stat_offsets_loaded = true; | |
688 | } | |
689 | ||
690 | /** | |
691 | * i40e_update_veb_stats - Update Switch component statistics | |
692 | * @veb: the VEB being updated | |
693 | **/ | |
694 | static void i40e_update_veb_stats(struct i40e_veb *veb) | |
695 | { | |
696 | struct i40e_pf *pf = veb->pf; | |
697 | struct i40e_hw *hw = &pf->hw; | |
698 | struct i40e_eth_stats *oes; | |
699 | struct i40e_eth_stats *es; /* device's eth stats */ | |
fe860afb NP |
700 | struct i40e_veb_tc_stats *veb_oes; |
701 | struct i40e_veb_tc_stats *veb_es; | |
702 | int i, idx = 0; | |
41c445ff JB |
703 | |
704 | idx = veb->stats_idx; | |
705 | es = &veb->stats; | |
706 | oes = &veb->stats_offsets; | |
fe860afb NP |
707 | veb_es = &veb->tc_stats; |
708 | veb_oes = &veb->tc_stats_offsets; | |
41c445ff JB |
709 | |
710 | /* Gather up the stats that the hw collects */ | |
711 | i40e_stat_update32(hw, I40E_GLSW_TDPC(idx), | |
712 | veb->stat_offsets_loaded, | |
713 | &oes->tx_discards, &es->tx_discards); | |
7134f9ce JB |
714 | if (hw->revision_id > 0) |
715 | i40e_stat_update32(hw, I40E_GLSW_RUPP(idx), | |
716 | veb->stat_offsets_loaded, | |
717 | &oes->rx_unknown_protocol, | |
718 | &es->rx_unknown_protocol); | |
41c445ff JB |
719 | i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx), |
720 | veb->stat_offsets_loaded, | |
721 | &oes->rx_bytes, &es->rx_bytes); | |
722 | i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx), | |
723 | veb->stat_offsets_loaded, | |
724 | &oes->rx_unicast, &es->rx_unicast); | |
725 | i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx), | |
726 | veb->stat_offsets_loaded, | |
727 | &oes->rx_multicast, &es->rx_multicast); | |
728 | i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx), | |
729 | veb->stat_offsets_loaded, | |
730 | &oes->rx_broadcast, &es->rx_broadcast); | |
731 | ||
732 | i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx), | |
733 | veb->stat_offsets_loaded, | |
734 | &oes->tx_bytes, &es->tx_bytes); | |
735 | i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx), | |
736 | veb->stat_offsets_loaded, | |
737 | &oes->tx_unicast, &es->tx_unicast); | |
738 | i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx), | |
739 | veb->stat_offsets_loaded, | |
740 | &oes->tx_multicast, &es->tx_multicast); | |
741 | i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx), | |
742 | veb->stat_offsets_loaded, | |
743 | &oes->tx_broadcast, &es->tx_broadcast); | |
fe860afb NP |
744 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
745 | i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx), | |
746 | I40E_GLVEBTC_RPCL(i, idx), | |
747 | veb->stat_offsets_loaded, | |
748 | &veb_oes->tc_rx_packets[i], | |
749 | &veb_es->tc_rx_packets[i]); | |
750 | i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx), | |
751 | I40E_GLVEBTC_RBCL(i, idx), | |
752 | veb->stat_offsets_loaded, | |
753 | &veb_oes->tc_rx_bytes[i], | |
754 | &veb_es->tc_rx_bytes[i]); | |
755 | i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx), | |
756 | I40E_GLVEBTC_TPCL(i, idx), | |
757 | veb->stat_offsets_loaded, | |
758 | &veb_oes->tc_tx_packets[i], | |
759 | &veb_es->tc_tx_packets[i]); | |
760 | i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx), | |
761 | I40E_GLVEBTC_TBCL(i, idx), | |
762 | veb->stat_offsets_loaded, | |
763 | &veb_oes->tc_tx_bytes[i], | |
764 | &veb_es->tc_tx_bytes[i]); | |
765 | } | |
41c445ff JB |
766 | veb->stat_offsets_loaded = true; |
767 | } | |
768 | ||
41c445ff | 769 | /** |
7812fddc | 770 | * i40e_update_vsi_stats - Update the vsi statistics counters. |
41c445ff JB |
771 | * @vsi: the VSI to be updated |
772 | * | |
773 | * There are a few instances where we store the same stat in a | |
774 | * couple of different structs. This is partly because we have | |
775 | * the netdev stats that need to be filled out, which is slightly | |
776 | * different from the "eth_stats" defined by the chip and used in | |
7812fddc | 777 | * VF communications. We sort it out here. |
41c445ff | 778 | **/ |
7812fddc | 779 | static void i40e_update_vsi_stats(struct i40e_vsi *vsi) |
41c445ff JB |
780 | { |
781 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
782 | struct rtnl_link_stats64 *ons; |
783 | struct rtnl_link_stats64 *ns; /* netdev stats */ | |
784 | struct i40e_eth_stats *oes; | |
785 | struct i40e_eth_stats *es; /* device's eth stats */ | |
786 | u32 tx_restart, tx_busy; | |
bf00b376 | 787 | struct i40e_ring *p; |
41c445ff | 788 | u32 rx_page, rx_buf; |
bf00b376 AA |
789 | u64 bytes, packets; |
790 | unsigned int start; | |
2fc3d715 | 791 | u64 tx_linearize; |
164c9f54 | 792 | u64 tx_force_wb; |
41c445ff JB |
793 | u64 rx_p, rx_b; |
794 | u64 tx_p, tx_b; | |
41c445ff JB |
795 | u16 q; |
796 | ||
0da36b97 JK |
797 | if (test_bit(__I40E_VSI_DOWN, vsi->state) || |
798 | test_bit(__I40E_CONFIG_BUSY, pf->state)) | |
41c445ff JB |
799 | return; |
800 | ||
801 | ns = i40e_get_vsi_stats_struct(vsi); | |
802 | ons = &vsi->net_stats_offsets; | |
803 | es = &vsi->eth_stats; | |
804 | oes = &vsi->eth_stats_offsets; | |
805 | ||
806 | /* Gather up the netdev and vsi stats that the driver collects | |
807 | * on the fly during packet processing | |
808 | */ | |
809 | rx_b = rx_p = 0; | |
810 | tx_b = tx_p = 0; | |
164c9f54 | 811 | tx_restart = tx_busy = tx_linearize = tx_force_wb = 0; |
41c445ff JB |
812 | rx_page = 0; |
813 | rx_buf = 0; | |
980e9b11 | 814 | rcu_read_lock(); |
41c445ff | 815 | for (q = 0; q < vsi->num_queue_pairs; q++) { |
980e9b11 | 816 | /* locate Tx ring */ |
6aa7de05 | 817 | p = READ_ONCE(vsi->tx_rings[q]); |
980e9b11 AD |
818 | |
819 | do { | |
57a7744e | 820 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
821 | packets = p->stats.packets; |
822 | bytes = p->stats.bytes; | |
57a7744e | 823 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
824 | tx_b += bytes; |
825 | tx_p += packets; | |
826 | tx_restart += p->tx_stats.restart_queue; | |
827 | tx_busy += p->tx_stats.tx_busy; | |
2fc3d715 | 828 | tx_linearize += p->tx_stats.tx_linearize; |
164c9f54 | 829 | tx_force_wb += p->tx_stats.tx_force_wb; |
41c445ff | 830 | |
980e9b11 AD |
831 | /* Rx queue is part of the same block as Tx queue */ |
832 | p = &p[1]; | |
833 | do { | |
57a7744e | 834 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
835 | packets = p->stats.packets; |
836 | bytes = p->stats.bytes; | |
57a7744e | 837 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
838 | rx_b += bytes; |
839 | rx_p += packets; | |
420136cc MW |
840 | rx_buf += p->rx_stats.alloc_buff_failed; |
841 | rx_page += p->rx_stats.alloc_page_failed; | |
41c445ff | 842 | } |
980e9b11 | 843 | rcu_read_unlock(); |
41c445ff JB |
844 | vsi->tx_restart = tx_restart; |
845 | vsi->tx_busy = tx_busy; | |
2fc3d715 | 846 | vsi->tx_linearize = tx_linearize; |
164c9f54 | 847 | vsi->tx_force_wb = tx_force_wb; |
41c445ff JB |
848 | vsi->rx_page_failed = rx_page; |
849 | vsi->rx_buf_failed = rx_buf; | |
850 | ||
851 | ns->rx_packets = rx_p; | |
852 | ns->rx_bytes = rx_b; | |
853 | ns->tx_packets = tx_p; | |
854 | ns->tx_bytes = tx_b; | |
855 | ||
41c445ff | 856 | /* update netdev stats from eth stats */ |
7812fddc | 857 | i40e_update_eth_stats(vsi); |
41c445ff JB |
858 | ons->tx_errors = oes->tx_errors; |
859 | ns->tx_errors = es->tx_errors; | |
860 | ons->multicast = oes->rx_multicast; | |
861 | ns->multicast = es->rx_multicast; | |
41a9e55c SN |
862 | ons->rx_dropped = oes->rx_discards; |
863 | ns->rx_dropped = es->rx_discards; | |
41c445ff JB |
864 | ons->tx_dropped = oes->tx_discards; |
865 | ns->tx_dropped = es->tx_discards; | |
866 | ||
7812fddc | 867 | /* pull in a couple PF stats if this is the main vsi */ |
41c445ff | 868 | if (vsi == pf->vsi[pf->lan_vsi]) { |
7812fddc SN |
869 | ns->rx_crc_errors = pf->stats.crc_errors; |
870 | ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes; | |
871 | ns->rx_length_errors = pf->stats.rx_length_errors; | |
872 | } | |
873 | } | |
41c445ff | 874 | |
7812fddc | 875 | /** |
b40c82e6 | 876 | * i40e_update_pf_stats - Update the PF statistics counters. |
7812fddc SN |
877 | * @pf: the PF to be updated |
878 | **/ | |
879 | static void i40e_update_pf_stats(struct i40e_pf *pf) | |
880 | { | |
881 | struct i40e_hw_port_stats *osd = &pf->stats_offsets; | |
882 | struct i40e_hw_port_stats *nsd = &pf->stats; | |
883 | struct i40e_hw *hw = &pf->hw; | |
884 | u32 val; | |
885 | int i; | |
41c445ff | 886 | |
7812fddc SN |
887 | i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), |
888 | I40E_GLPRT_GORCL(hw->port), | |
889 | pf->stat_offsets_loaded, | |
890 | &osd->eth.rx_bytes, &nsd->eth.rx_bytes); | |
891 | i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), | |
892 | I40E_GLPRT_GOTCL(hw->port), | |
893 | pf->stat_offsets_loaded, | |
894 | &osd->eth.tx_bytes, &nsd->eth.tx_bytes); | |
895 | i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), | |
896 | pf->stat_offsets_loaded, | |
897 | &osd->eth.rx_discards, | |
898 | &nsd->eth.rx_discards); | |
532d283d SN |
899 | i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), |
900 | I40E_GLPRT_UPRCL(hw->port), | |
901 | pf->stat_offsets_loaded, | |
902 | &osd->eth.rx_unicast, | |
903 | &nsd->eth.rx_unicast); | |
7812fddc SN |
904 | i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), |
905 | I40E_GLPRT_MPRCL(hw->port), | |
906 | pf->stat_offsets_loaded, | |
907 | &osd->eth.rx_multicast, | |
908 | &nsd->eth.rx_multicast); | |
532d283d SN |
909 | i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), |
910 | I40E_GLPRT_BPRCL(hw->port), | |
911 | pf->stat_offsets_loaded, | |
912 | &osd->eth.rx_broadcast, | |
913 | &nsd->eth.rx_broadcast); | |
914 | i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), | |
915 | I40E_GLPRT_UPTCL(hw->port), | |
916 | pf->stat_offsets_loaded, | |
917 | &osd->eth.tx_unicast, | |
918 | &nsd->eth.tx_unicast); | |
919 | i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), | |
920 | I40E_GLPRT_MPTCL(hw->port), | |
921 | pf->stat_offsets_loaded, | |
922 | &osd->eth.tx_multicast, | |
923 | &nsd->eth.tx_multicast); | |
924 | i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), | |
925 | I40E_GLPRT_BPTCL(hw->port), | |
926 | pf->stat_offsets_loaded, | |
927 | &osd->eth.tx_broadcast, | |
928 | &nsd->eth.tx_broadcast); | |
41c445ff | 929 | |
7812fddc SN |
930 | i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), |
931 | pf->stat_offsets_loaded, | |
932 | &osd->tx_dropped_link_down, | |
933 | &nsd->tx_dropped_link_down); | |
41c445ff | 934 | |
7812fddc SN |
935 | i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), |
936 | pf->stat_offsets_loaded, | |
937 | &osd->crc_errors, &nsd->crc_errors); | |
41c445ff | 938 | |
7812fddc SN |
939 | i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), |
940 | pf->stat_offsets_loaded, | |
941 | &osd->illegal_bytes, &nsd->illegal_bytes); | |
41c445ff | 942 | |
7812fddc SN |
943 | i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), |
944 | pf->stat_offsets_loaded, | |
945 | &osd->mac_local_faults, | |
946 | &nsd->mac_local_faults); | |
947 | i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), | |
948 | pf->stat_offsets_loaded, | |
949 | &osd->mac_remote_faults, | |
950 | &nsd->mac_remote_faults); | |
41c445ff | 951 | |
7812fddc SN |
952 | i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), |
953 | pf->stat_offsets_loaded, | |
954 | &osd->rx_length_errors, | |
955 | &nsd->rx_length_errors); | |
41c445ff | 956 | |
7812fddc SN |
957 | i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), |
958 | pf->stat_offsets_loaded, | |
959 | &osd->link_xon_rx, &nsd->link_xon_rx); | |
960 | i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), | |
961 | pf->stat_offsets_loaded, | |
962 | &osd->link_xon_tx, &nsd->link_xon_tx); | |
95db239f NP |
963 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), |
964 | pf->stat_offsets_loaded, | |
965 | &osd->link_xoff_rx, &nsd->link_xoff_rx); | |
7812fddc SN |
966 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), |
967 | pf->stat_offsets_loaded, | |
968 | &osd->link_xoff_tx, &nsd->link_xoff_tx); | |
41c445ff | 969 | |
7812fddc | 970 | for (i = 0; i < 8; i++) { |
95db239f NP |
971 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), |
972 | pf->stat_offsets_loaded, | |
973 | &osd->priority_xoff_rx[i], | |
974 | &nsd->priority_xoff_rx[i]); | |
7812fddc | 975 | i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i), |
41c445ff | 976 | pf->stat_offsets_loaded, |
7812fddc SN |
977 | &osd->priority_xon_rx[i], |
978 | &nsd->priority_xon_rx[i]); | |
979 | i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i), | |
41c445ff | 980 | pf->stat_offsets_loaded, |
7812fddc SN |
981 | &osd->priority_xon_tx[i], |
982 | &nsd->priority_xon_tx[i]); | |
983 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), | |
41c445ff | 984 | pf->stat_offsets_loaded, |
7812fddc SN |
985 | &osd->priority_xoff_tx[i], |
986 | &nsd->priority_xoff_tx[i]); | |
987 | i40e_stat_update32(hw, | |
988 | I40E_GLPRT_RXON2OFFCNT(hw->port, i), | |
bee5af7e | 989 | pf->stat_offsets_loaded, |
7812fddc SN |
990 | &osd->priority_xon_2_xoff[i], |
991 | &nsd->priority_xon_2_xoff[i]); | |
41c445ff JB |
992 | } |
993 | ||
7812fddc SN |
994 | i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), |
995 | I40E_GLPRT_PRC64L(hw->port), | |
996 | pf->stat_offsets_loaded, | |
997 | &osd->rx_size_64, &nsd->rx_size_64); | |
998 | i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), | |
999 | I40E_GLPRT_PRC127L(hw->port), | |
1000 | pf->stat_offsets_loaded, | |
1001 | &osd->rx_size_127, &nsd->rx_size_127); | |
1002 | i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), | |
1003 | I40E_GLPRT_PRC255L(hw->port), | |
1004 | pf->stat_offsets_loaded, | |
1005 | &osd->rx_size_255, &nsd->rx_size_255); | |
1006 | i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), | |
1007 | I40E_GLPRT_PRC511L(hw->port), | |
1008 | pf->stat_offsets_loaded, | |
1009 | &osd->rx_size_511, &nsd->rx_size_511); | |
1010 | i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), | |
1011 | I40E_GLPRT_PRC1023L(hw->port), | |
1012 | pf->stat_offsets_loaded, | |
1013 | &osd->rx_size_1023, &nsd->rx_size_1023); | |
1014 | i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), | |
1015 | I40E_GLPRT_PRC1522L(hw->port), | |
1016 | pf->stat_offsets_loaded, | |
1017 | &osd->rx_size_1522, &nsd->rx_size_1522); | |
1018 | i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), | |
1019 | I40E_GLPRT_PRC9522L(hw->port), | |
1020 | pf->stat_offsets_loaded, | |
1021 | &osd->rx_size_big, &nsd->rx_size_big); | |
1022 | ||
1023 | i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), | |
1024 | I40E_GLPRT_PTC64L(hw->port), | |
1025 | pf->stat_offsets_loaded, | |
1026 | &osd->tx_size_64, &nsd->tx_size_64); | |
1027 | i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), | |
1028 | I40E_GLPRT_PTC127L(hw->port), | |
1029 | pf->stat_offsets_loaded, | |
1030 | &osd->tx_size_127, &nsd->tx_size_127); | |
1031 | i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), | |
1032 | I40E_GLPRT_PTC255L(hw->port), | |
1033 | pf->stat_offsets_loaded, | |
1034 | &osd->tx_size_255, &nsd->tx_size_255); | |
1035 | i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), | |
1036 | I40E_GLPRT_PTC511L(hw->port), | |
1037 | pf->stat_offsets_loaded, | |
1038 | &osd->tx_size_511, &nsd->tx_size_511); | |
1039 | i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), | |
1040 | I40E_GLPRT_PTC1023L(hw->port), | |
1041 | pf->stat_offsets_loaded, | |
1042 | &osd->tx_size_1023, &nsd->tx_size_1023); | |
1043 | i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), | |
1044 | I40E_GLPRT_PTC1522L(hw->port), | |
1045 | pf->stat_offsets_loaded, | |
1046 | &osd->tx_size_1522, &nsd->tx_size_1522); | |
1047 | i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), | |
1048 | I40E_GLPRT_PTC9522L(hw->port), | |
1049 | pf->stat_offsets_loaded, | |
1050 | &osd->tx_size_big, &nsd->tx_size_big); | |
1051 | ||
1052 | i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port), | |
1053 | pf->stat_offsets_loaded, | |
1054 | &osd->rx_undersize, &nsd->rx_undersize); | |
1055 | i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port), | |
1056 | pf->stat_offsets_loaded, | |
1057 | &osd->rx_fragments, &nsd->rx_fragments); | |
1058 | i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port), | |
1059 | pf->stat_offsets_loaded, | |
1060 | &osd->rx_oversize, &nsd->rx_oversize); | |
1061 | i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port), | |
1062 | pf->stat_offsets_loaded, | |
1063 | &osd->rx_jabber, &nsd->rx_jabber); | |
1064 | ||
433c47de | 1065 | /* FDIR stats */ |
0dc8692e MS |
1066 | i40e_stat_update_and_clear32(hw, |
1067 | I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(hw->pf_id)), | |
1068 | &nsd->fd_atr_match); | |
1069 | i40e_stat_update_and_clear32(hw, | |
1070 | I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(hw->pf_id)), | |
1071 | &nsd->fd_sb_match); | |
1072 | i40e_stat_update_and_clear32(hw, | |
1073 | I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(hw->pf_id)), | |
1074 | &nsd->fd_atr_tunnel_match); | |
433c47de | 1075 | |
7812fddc SN |
1076 | val = rd32(hw, I40E_PRTPM_EEE_STAT); |
1077 | nsd->tx_lpi_status = | |
1078 | (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> | |
1079 | I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; | |
1080 | nsd->rx_lpi_status = | |
1081 | (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> | |
1082 | I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; | |
1083 | i40e_stat_update32(hw, I40E_PRTPM_TLPIC, | |
1084 | pf->stat_offsets_loaded, | |
1085 | &osd->tx_lpi_count, &nsd->tx_lpi_count); | |
1086 | i40e_stat_update32(hw, I40E_PRTPM_RLPIC, | |
1087 | pf->stat_offsets_loaded, | |
1088 | &osd->rx_lpi_count, &nsd->rx_lpi_count); | |
1089 | ||
d0389e51 | 1090 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED && |
47994c11 | 1091 | !(pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED)) |
d0389e51 ASJ |
1092 | nsd->fd_sb_status = true; |
1093 | else | |
1094 | nsd->fd_sb_status = false; | |
1095 | ||
1096 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED && | |
47994c11 | 1097 | !(pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED)) |
d0389e51 ASJ |
1098 | nsd->fd_atr_status = true; |
1099 | else | |
1100 | nsd->fd_atr_status = false; | |
1101 | ||
41c445ff JB |
1102 | pf->stat_offsets_loaded = true; |
1103 | } | |
1104 | ||
7812fddc SN |
1105 | /** |
1106 | * i40e_update_stats - Update the various statistics counters. | |
1107 | * @vsi: the VSI to be updated | |
1108 | * | |
1109 | * Update the various stats for this VSI and its related entities. | |
1110 | **/ | |
1111 | void i40e_update_stats(struct i40e_vsi *vsi) | |
1112 | { | |
1113 | struct i40e_pf *pf = vsi->back; | |
1114 | ||
1115 | if (vsi == pf->vsi[pf->lan_vsi]) | |
1116 | i40e_update_pf_stats(pf); | |
1117 | ||
1118 | i40e_update_vsi_stats(vsi); | |
1119 | } | |
1120 | ||
41c445ff JB |
1121 | /** |
1122 | * i40e_find_filter - Search VSI filter list for specific mac/vlan filter | |
1123 | * @vsi: the VSI to be searched | |
1124 | * @macaddr: the MAC address | |
1125 | * @vlan: the vlan | |
41c445ff JB |
1126 | * |
1127 | * Returns ptr to the filter object or NULL | |
1128 | **/ | |
1129 | static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1130 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1131 | { |
1132 | struct i40e_mac_filter *f; | |
278e7d0b | 1133 | u64 key; |
41c445ff JB |
1134 | |
1135 | if (!vsi || !macaddr) | |
1136 | return NULL; | |
1137 | ||
278e7d0b JK |
1138 | key = i40e_addr_to_hkey(macaddr); |
1139 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
41c445ff | 1140 | if ((ether_addr_equal(macaddr, f->macaddr)) && |
1bc87e80 | 1141 | (vlan == f->vlan)) |
41c445ff JB |
1142 | return f; |
1143 | } | |
1144 | return NULL; | |
1145 | } | |
1146 | ||
1147 | /** | |
1148 | * i40e_find_mac - Find a mac addr in the macvlan filters list | |
1149 | * @vsi: the VSI to be searched | |
1150 | * @macaddr: the MAC address we are searching for | |
41c445ff JB |
1151 | * |
1152 | * Returns the first filter with the provided MAC address or NULL if | |
1153 | * MAC address was not found | |
1154 | **/ | |
6622f5cd | 1155 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr) |
41c445ff JB |
1156 | { |
1157 | struct i40e_mac_filter *f; | |
278e7d0b | 1158 | u64 key; |
41c445ff JB |
1159 | |
1160 | if (!vsi || !macaddr) | |
1161 | return NULL; | |
1162 | ||
278e7d0b JK |
1163 | key = i40e_addr_to_hkey(macaddr); |
1164 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
1bc87e80 | 1165 | if ((ether_addr_equal(macaddr, f->macaddr))) |
41c445ff JB |
1166 | return f; |
1167 | } | |
1168 | return NULL; | |
1169 | } | |
1170 | ||
1171 | /** | |
1172 | * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode | |
1173 | * @vsi: the VSI to be searched | |
1174 | * | |
1175 | * Returns true if VSI is in vlan mode or false otherwise | |
1176 | **/ | |
1177 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi) | |
1178 | { | |
cbebb85f JK |
1179 | /* If we have a PVID, always operate in VLAN mode */ |
1180 | if (vsi->info.pvid) | |
1181 | return true; | |
1182 | ||
1183 | /* We need to operate in VLAN mode whenever we have any filters with | |
1184 | * a VLAN other than I40E_VLAN_ALL. We could check the table each | |
1185 | * time, incurring search cost repeatedly. However, we can notice two | |
1186 | * things: | |
1187 | * | |
1188 | * 1) the only place where we can gain a VLAN filter is in | |
1189 | * i40e_add_filter. | |
1190 | * | |
1191 | * 2) the only place where filters are actually removed is in | |
0b7c8b5d | 1192 | * i40e_sync_filters_subtask. |
cbebb85f JK |
1193 | * |
1194 | * Thus, we can simply use a boolean value, has_vlan_filters which we | |
1195 | * will set to true when we add a VLAN filter in i40e_add_filter. Then | |
1196 | * we have to perform the full search after deleting filters in | |
0b7c8b5d | 1197 | * i40e_sync_filters_subtask, but we already have to search |
cbebb85f JK |
1198 | * filters here and can perform the check at the same time. This |
1199 | * results in avoiding embedding a loop for VLAN mode inside another | |
1200 | * loop over all the filters, and should maintain correctness as noted | |
1201 | * above. | |
41c445ff | 1202 | */ |
cbebb85f | 1203 | return vsi->has_vlan_filter; |
41c445ff JB |
1204 | } |
1205 | ||
489a3265 JK |
1206 | /** |
1207 | * i40e_correct_mac_vlan_filters - Correct non-VLAN filters if necessary | |
1208 | * @vsi: the VSI to configure | |
1209 | * @tmp_add_list: list of filters ready to be added | |
1210 | * @tmp_del_list: list of filters ready to be deleted | |
1211 | * @vlan_filters: the number of active VLAN filters | |
1212 | * | |
1213 | * Update VLAN=0 and VLAN=-1 (I40E_VLAN_ANY) filters properly so that they | |
1214 | * behave as expected. If we have any active VLAN filters remaining or about | |
1215 | * to be added then we need to update non-VLAN filters to be marked as VLAN=0 | |
1216 | * so that they only match against untagged traffic. If we no longer have any | |
1217 | * active VLAN filters, we need to make all non-VLAN filters marked as VLAN=-1 | |
1218 | * so that they match against both tagged and untagged traffic. In this way, | |
1219 | * we ensure that we correctly receive the desired traffic. This ensures that | |
1220 | * when we have an active VLAN we will receive only untagged traffic and | |
1221 | * traffic matching active VLANs. If we have no active VLANs then we will | |
1222 | * operate in non-VLAN mode and receive all traffic, tagged or untagged. | |
1223 | * | |
1224 | * Finally, in a similar fashion, this function also corrects filters when | |
1225 | * there is an active PVID assigned to this VSI. | |
1226 | * | |
1227 | * In case of memory allocation failure return -ENOMEM. Otherwise, return 0. | |
1228 | * | |
1229 | * This function is only expected to be called from within | |
1230 | * i40e_sync_vsi_filters. | |
1231 | * | |
1232 | * NOTE: This function expects to be called while under the | |
1233 | * mac_filter_hash_lock | |
1234 | */ | |
1235 | static int i40e_correct_mac_vlan_filters(struct i40e_vsi *vsi, | |
1236 | struct hlist_head *tmp_add_list, | |
1237 | struct hlist_head *tmp_del_list, | |
1238 | int vlan_filters) | |
1239 | { | |
5cb25901 | 1240 | s16 pvid = le16_to_cpu(vsi->info.pvid); |
489a3265 | 1241 | struct i40e_mac_filter *f, *add_head; |
671889e6 | 1242 | struct i40e_new_mac_filter *new; |
489a3265 JK |
1243 | struct hlist_node *h; |
1244 | int bkt, new_vlan; | |
1245 | ||
1246 | /* To determine if a particular filter needs to be replaced we | |
1247 | * have the three following conditions: | |
1248 | * | |
1249 | * a) if we have a PVID assigned, then all filters which are | |
1250 | * not marked as VLAN=PVID must be replaced with filters that | |
1251 | * are. | |
1252 | * b) otherwise, if we have any active VLANS, all filters | |
1253 | * which are marked as VLAN=-1 must be replaced with | |
1254 | * filters marked as VLAN=0 | |
1255 | * c) finally, if we do not have any active VLANS, all filters | |
1256 | * which are marked as VLAN=0 must be replaced with filters | |
1257 | * marked as VLAN=-1 | |
1258 | */ | |
1259 | ||
1260 | /* Update the filters about to be added in place */ | |
671889e6 | 1261 | hlist_for_each_entry(new, tmp_add_list, hlist) { |
5cb25901 JK |
1262 | if (pvid && new->f->vlan != pvid) |
1263 | new->f->vlan = pvid; | |
671889e6 JK |
1264 | else if (vlan_filters && new->f->vlan == I40E_VLAN_ANY) |
1265 | new->f->vlan = 0; | |
1266 | else if (!vlan_filters && new->f->vlan == 0) | |
1267 | new->f->vlan = I40E_VLAN_ANY; | |
489a3265 JK |
1268 | } |
1269 | ||
1270 | /* Update the remaining active filters */ | |
1271 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { | |
1272 | /* Combine the checks for whether a filter needs to be changed | |
1273 | * and then determine the new VLAN inside the if block, in | |
1274 | * order to avoid duplicating code for adding the new filter | |
1275 | * then deleting the old filter. | |
1276 | */ | |
5cb25901 | 1277 | if ((pvid && f->vlan != pvid) || |
489a3265 JK |
1278 | (vlan_filters && f->vlan == I40E_VLAN_ANY) || |
1279 | (!vlan_filters && f->vlan == 0)) { | |
1280 | /* Determine the new vlan we will be adding */ | |
5cb25901 JK |
1281 | if (pvid) |
1282 | new_vlan = pvid; | |
489a3265 JK |
1283 | else if (vlan_filters) |
1284 | new_vlan = 0; | |
1285 | else | |
1286 | new_vlan = I40E_VLAN_ANY; | |
1287 | ||
1288 | /* Create the new filter */ | |
1289 | add_head = i40e_add_filter(vsi, f->macaddr, new_vlan); | |
1290 | if (!add_head) | |
1291 | return -ENOMEM; | |
1292 | ||
671889e6 JK |
1293 | /* Create a temporary i40e_new_mac_filter */ |
1294 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
1295 | if (!new) | |
1296 | return -ENOMEM; | |
1297 | ||
1298 | new->f = add_head; | |
1299 | new->state = add_head->state; | |
1300 | ||
1301 | /* Add the new filter to the tmp list */ | |
1302 | hlist_add_head(&new->hlist, tmp_add_list); | |
489a3265 JK |
1303 | |
1304 | /* Put the original filter into the delete list */ | |
1305 | f->state = I40E_FILTER_REMOVE; | |
1306 | hash_del(&f->hlist); | |
1307 | hlist_add_head(&f->hlist, tmp_del_list); | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | vsi->has_vlan_filter = !!vlan_filters; | |
1312 | ||
1313 | return 0; | |
1314 | } | |
1315 | ||
1596b5dd JK |
1316 | /** |
1317 | * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM | |
1318 | * @vsi: the PF Main VSI - inappropriate for any other VSI | |
1319 | * @macaddr: the MAC address | |
1320 | * | |
1321 | * Remove whatever filter the firmware set up so the driver can manage | |
1322 | * its own filtering intelligently. | |
1323 | **/ | |
1324 | static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr) | |
1325 | { | |
1326 | struct i40e_aqc_remove_macvlan_element_data element; | |
1327 | struct i40e_pf *pf = vsi->back; | |
1328 | ||
1329 | /* Only appropriate for the PF main VSI */ | |
1330 | if (vsi->type != I40E_VSI_MAIN) | |
1331 | return; | |
1332 | ||
1333 | memset(&element, 0, sizeof(element)); | |
1334 | ether_addr_copy(element.mac_addr, macaddr); | |
1335 | element.vlan_tag = 0; | |
1336 | /* Ignore error returns, some firmware does it this way... */ | |
1337 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; | |
1338 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1339 | ||
1340 | memset(&element, 0, sizeof(element)); | |
1341 | ether_addr_copy(element.mac_addr, macaddr); | |
1342 | element.vlan_tag = 0; | |
1343 | /* ...and some firmware does it this way. */ | |
1344 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | | |
1345 | I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; | |
1346 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1347 | } | |
1348 | ||
41c445ff JB |
1349 | /** |
1350 | * i40e_add_filter - Add a mac/vlan filter to the VSI | |
1351 | * @vsi: the VSI to be searched | |
1352 | * @macaddr: the MAC address | |
1353 | * @vlan: the vlan | |
41c445ff JB |
1354 | * |
1355 | * Returns ptr to the filter object or NULL when no memory available. | |
21659035 | 1356 | * |
278e7d0b | 1357 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1358 | * being held. |
41c445ff JB |
1359 | **/ |
1360 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1361 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1362 | { |
1363 | struct i40e_mac_filter *f; | |
278e7d0b | 1364 | u64 key; |
41c445ff JB |
1365 | |
1366 | if (!vsi || !macaddr) | |
1367 | return NULL; | |
1368 | ||
1bc87e80 | 1369 | f = i40e_find_filter(vsi, macaddr, vlan); |
41c445ff JB |
1370 | if (!f) { |
1371 | f = kzalloc(sizeof(*f), GFP_ATOMIC); | |
1372 | if (!f) | |
1bc87e80 | 1373 | return NULL; |
41c445ff | 1374 | |
cbebb85f JK |
1375 | /* Update the boolean indicating if we need to function in |
1376 | * VLAN mode. | |
1377 | */ | |
1378 | if (vlan >= 0) | |
1379 | vsi->has_vlan_filter = true; | |
1380 | ||
9a173901 | 1381 | ether_addr_copy(f->macaddr, macaddr); |
41c445ff | 1382 | f->vlan = vlan; |
c3c7ea27 MW |
1383 | /* If we're in overflow promisc mode, set the state directly |
1384 | * to failed, so we don't bother to try sending the filter | |
1385 | * to the hardware. | |
1386 | */ | |
0da36b97 | 1387 | if (test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state)) |
c3c7ea27 MW |
1388 | f->state = I40E_FILTER_FAILED; |
1389 | else | |
1390 | f->state = I40E_FILTER_NEW; | |
278e7d0b JK |
1391 | INIT_HLIST_NODE(&f->hlist); |
1392 | ||
1393 | key = i40e_addr_to_hkey(macaddr); | |
1394 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
41c445ff | 1395 | |
41c445ff JB |
1396 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; |
1397 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1398 | } | |
1399 | ||
1bc87e80 JK |
1400 | /* If we're asked to add a filter that has been marked for removal, it |
1401 | * is safe to simply restore it to active state. __i40e_del_filter | |
1402 | * will have simply deleted any filters which were previously marked | |
1403 | * NEW or FAILED, so if it is currently marked REMOVE it must have | |
1404 | * previously been ACTIVE. Since we haven't yet run the sync filters | |
1405 | * task, just restore this filter to the ACTIVE state so that the | |
1406 | * sync task leaves it in place | |
1407 | */ | |
1408 | if (f->state == I40E_FILTER_REMOVE) | |
1409 | f->state = I40E_FILTER_ACTIVE; | |
1410 | ||
41c445ff JB |
1411 | return f; |
1412 | } | |
1413 | ||
1414 | /** | |
290d2557 JK |
1415 | * __i40e_del_filter - Remove a specific filter from the VSI |
1416 | * @vsi: VSI to remove from | |
1417 | * @f: the filter to remove from the list | |
1418 | * | |
1419 | * This function should be called instead of i40e_del_filter only if you know | |
1420 | * the exact filter you will remove already, such as via i40e_find_filter or | |
1421 | * i40e_find_mac. | |
21659035 | 1422 | * |
278e7d0b | 1423 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1424 | * being held. |
c3c7ea27 MW |
1425 | * ANOTHER NOTE: This function MUST be called from within the context of |
1426 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1427 | * instead of list_for_each_entry(). | |
41c445ff | 1428 | **/ |
148141bb | 1429 | void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f) |
41c445ff | 1430 | { |
1bc87e80 | 1431 | if (!f) |
41c445ff JB |
1432 | return; |
1433 | ||
a410c821 AB |
1434 | /* If the filter was never added to firmware then we can just delete it |
1435 | * directly and we don't want to set the status to remove or else an | |
1436 | * admin queue command will unnecessarily fire. | |
1437 | */ | |
1bc87e80 JK |
1438 | if ((f->state == I40E_FILTER_FAILED) || |
1439 | (f->state == I40E_FILTER_NEW)) { | |
278e7d0b | 1440 | hash_del(&f->hlist); |
1bc87e80 | 1441 | kfree(f); |
41c445ff | 1442 | } else { |
1bc87e80 | 1443 | f->state = I40E_FILTER_REMOVE; |
41c445ff | 1444 | } |
a410c821 AB |
1445 | |
1446 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1447 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
41c445ff JB |
1448 | } |
1449 | ||
290d2557 JK |
1450 | /** |
1451 | * i40e_del_filter - Remove a MAC/VLAN filter from the VSI | |
1452 | * @vsi: the VSI to be searched | |
1453 | * @macaddr: the MAC address | |
1454 | * @vlan: the VLAN | |
1455 | * | |
278e7d0b | 1456 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
290d2557 JK |
1457 | * being held. |
1458 | * ANOTHER NOTE: This function MUST be called from within the context of | |
1459 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1460 | * instead of list_for_each_entry(). | |
1461 | **/ | |
1462 | void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan) | |
1463 | { | |
1464 | struct i40e_mac_filter *f; | |
1465 | ||
1466 | if (!vsi || !macaddr) | |
1467 | return; | |
1468 | ||
1469 | f = i40e_find_filter(vsi, macaddr, vlan); | |
1470 | __i40e_del_filter(vsi, f); | |
1471 | } | |
1472 | ||
35ec2ff3 | 1473 | /** |
feffdbe4 | 1474 | * i40e_add_mac_filter - Add a MAC filter for all active VLANs |
35ec2ff3 JK |
1475 | * @vsi: the VSI to be searched |
1476 | * @macaddr: the mac address to be filtered | |
1477 | * | |
feffdbe4 JK |
1478 | * If we're not in VLAN mode, just add the filter to I40E_VLAN_ANY. Otherwise, |
1479 | * go through all the macvlan filters and add a macvlan filter for each | |
5feb3d7b JK |
1480 | * unique vlan that already exists. If a PVID has been assigned, instead only |
1481 | * add the macaddr to that VLAN. | |
35ec2ff3 | 1482 | * |
5feb3d7b | 1483 | * Returns last filter added on success, else NULL |
35ec2ff3 | 1484 | **/ |
feffdbe4 JK |
1485 | struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, |
1486 | const u8 *macaddr) | |
35ec2ff3 | 1487 | { |
5feb3d7b | 1488 | struct i40e_mac_filter *f, *add = NULL; |
278e7d0b JK |
1489 | struct hlist_node *h; |
1490 | int bkt; | |
5feb3d7b JK |
1491 | |
1492 | if (vsi->info.pvid) | |
1493 | return i40e_add_filter(vsi, macaddr, | |
1494 | le16_to_cpu(vsi->info.pvid)); | |
35ec2ff3 | 1495 | |
7aaf9536 JK |
1496 | if (!i40e_is_vsi_in_vlan(vsi)) |
1497 | return i40e_add_filter(vsi, macaddr, I40E_VLAN_ANY); | |
1498 | ||
278e7d0b | 1499 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
1500 | if (f->state == I40E_FILTER_REMOVE) |
1501 | continue; | |
5feb3d7b JK |
1502 | add = i40e_add_filter(vsi, macaddr, f->vlan); |
1503 | if (!add) | |
1504 | return NULL; | |
35ec2ff3 JK |
1505 | } |
1506 | ||
5feb3d7b | 1507 | return add; |
35ec2ff3 JK |
1508 | } |
1509 | ||
1510 | /** | |
feffdbe4 | 1511 | * i40e_del_mac_filter - Remove a MAC filter from all VLANs |
35ec2ff3 JK |
1512 | * @vsi: the VSI to be searched |
1513 | * @macaddr: the mac address to be removed | |
1514 | * | |
feffdbe4 JK |
1515 | * Removes a given MAC address from a VSI regardless of what VLAN it has been |
1516 | * associated with. | |
35ec2ff3 JK |
1517 | * |
1518 | * Returns 0 for success, or error | |
1519 | **/ | |
feffdbe4 | 1520 | int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr) |
35ec2ff3 | 1521 | { |
278e7d0b JK |
1522 | struct i40e_mac_filter *f; |
1523 | struct hlist_node *h; | |
290d2557 | 1524 | bool found = false; |
278e7d0b | 1525 | int bkt; |
35ec2ff3 | 1526 | |
278e7d0b JK |
1527 | WARN(!spin_is_locked(&vsi->mac_filter_hash_lock), |
1528 | "Missing mac_filter_hash_lock\n"); | |
1529 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { | |
290d2557 JK |
1530 | if (ether_addr_equal(macaddr, f->macaddr)) { |
1531 | __i40e_del_filter(vsi, f); | |
1532 | found = true; | |
1533 | } | |
35ec2ff3 | 1534 | } |
290d2557 JK |
1535 | |
1536 | if (found) | |
35ec2ff3 | 1537 | return 0; |
290d2557 JK |
1538 | else |
1539 | return -ENOENT; | |
35ec2ff3 JK |
1540 | } |
1541 | ||
41c445ff JB |
1542 | /** |
1543 | * i40e_set_mac - NDO callback to set mac address | |
1544 | * @netdev: network interface device structure | |
1545 | * @p: pointer to an address structure | |
1546 | * | |
1547 | * Returns 0 on success, negative on failure | |
1548 | **/ | |
1549 | static int i40e_set_mac(struct net_device *netdev, void *p) | |
1550 | { | |
1551 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1552 | struct i40e_vsi *vsi = np->vsi; | |
30650cc5 SN |
1553 | struct i40e_pf *pf = vsi->back; |
1554 | struct i40e_hw *hw = &pf->hw; | |
41c445ff | 1555 | struct sockaddr *addr = p; |
41c445ff JB |
1556 | |
1557 | if (!is_valid_ether_addr(addr->sa_data)) | |
1558 | return -EADDRNOTAVAIL; | |
1559 | ||
30650cc5 SN |
1560 | if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) { |
1561 | netdev_info(netdev, "already using mac address %pM\n", | |
1562 | addr->sa_data); | |
1563 | return 0; | |
1564 | } | |
41c445ff | 1565 | |
0da36b97 JK |
1566 | if (test_bit(__I40E_VSI_DOWN, vsi->back->state) || |
1567 | test_bit(__I40E_RESET_RECOVERY_PENDING, vsi->back->state)) | |
80f6428f ASJ |
1568 | return -EADDRNOTAVAIL; |
1569 | ||
30650cc5 SN |
1570 | if (ether_addr_equal(hw->mac.addr, addr->sa_data)) |
1571 | netdev_info(netdev, "returning to hw mac address %pM\n", | |
1572 | hw->mac.addr); | |
1573 | else | |
1574 | netdev_info(netdev, "set new mac address %pM\n", addr->sa_data); | |
1575 | ||
458867b2 JK |
1576 | /* Copy the address first, so that we avoid a possible race with |
1577 | * .set_rx_mode(). If we copy after changing the address in the filter | |
1578 | * list, we might open ourselves to a narrow race window where | |
1579 | * .set_rx_mode could delete our dev_addr filter and prevent traffic | |
1580 | * from passing. | |
1581 | */ | |
1582 | ether_addr_copy(netdev->dev_addr, addr->sa_data); | |
1583 | ||
278e7d0b | 1584 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
feffdbe4 JK |
1585 | i40e_del_mac_filter(vsi, netdev->dev_addr); |
1586 | i40e_add_mac_filter(vsi, addr->sa_data); | |
278e7d0b | 1587 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
1588 | if (vsi->type == I40E_VSI_MAIN) { |
1589 | i40e_status ret; | |
6995b36c | 1590 | |
41c445ff | 1591 | ret = i40e_aq_mac_address_write(&vsi->back->hw, |
cc41222c | 1592 | I40E_AQC_WRITE_TYPE_LAA_WOL, |
41c445ff | 1593 | addr->sa_data, NULL); |
c3c7ea27 MW |
1594 | if (ret) |
1595 | netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n", | |
1596 | i40e_stat_str(hw, ret), | |
1597 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
30650cc5 SN |
1598 | } |
1599 | ||
c53934c6 JB |
1600 | /* schedule our worker thread which will take care of |
1601 | * applying the new filter changes | |
1602 | */ | |
1603 | i40e_service_event_schedule(vsi->back); | |
1604 | return 0; | |
41c445ff JB |
1605 | } |
1606 | ||
a9ce82f7 AN |
1607 | /** |
1608 | * i40e_config_rss_aq - Prepare for RSS using AQ commands | |
1609 | * @vsi: vsi structure | |
1610 | * @seed: RSS hash seed | |
1611 | **/ | |
1612 | static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
1613 | u8 *lut, u16 lut_size) | |
1614 | { | |
1615 | struct i40e_pf *pf = vsi->back; | |
1616 | struct i40e_hw *hw = &pf->hw; | |
1617 | int ret = 0; | |
1618 | ||
1619 | if (seed) { | |
1620 | struct i40e_aqc_get_set_rss_key_data *seed_dw = | |
1621 | (struct i40e_aqc_get_set_rss_key_data *)seed; | |
1622 | ret = i40e_aq_set_rss_key(hw, vsi->id, seed_dw); | |
1623 | if (ret) { | |
1624 | dev_info(&pf->pdev->dev, | |
1625 | "Cannot set RSS key, err %s aq_err %s\n", | |
1626 | i40e_stat_str(hw, ret), | |
1627 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
1628 | return ret; | |
1629 | } | |
1630 | } | |
1631 | if (lut) { | |
1632 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
1633 | ||
1634 | ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
1635 | if (ret) { | |
1636 | dev_info(&pf->pdev->dev, | |
1637 | "Cannot set RSS lut, err %s aq_err %s\n", | |
1638 | i40e_stat_str(hw, ret), | |
1639 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
1640 | return ret; | |
1641 | } | |
1642 | } | |
1643 | return ret; | |
1644 | } | |
1645 | ||
1646 | /** | |
1647 | * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used | |
1648 | * @vsi: VSI structure | |
1649 | **/ | |
1650 | static int i40e_vsi_config_rss(struct i40e_vsi *vsi) | |
1651 | { | |
1652 | struct i40e_pf *pf = vsi->back; | |
1653 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
1654 | u8 *lut; | |
1655 | int ret; | |
1656 | ||
1657 | if (!(pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)) | |
1658 | return 0; | |
1659 | if (!vsi->rss_size) | |
1660 | vsi->rss_size = min_t(int, pf->alloc_rss_size, | |
1661 | vsi->num_queue_pairs); | |
1662 | if (!vsi->rss_size) | |
1663 | return -EINVAL; | |
1664 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); | |
1665 | if (!lut) | |
1666 | return -ENOMEM; | |
1667 | ||
1668 | /* Use the user configured hash keys and lookup table if there is one, | |
1669 | * otherwise use default | |
1670 | */ | |
1671 | if (vsi->rss_lut_user) | |
1672 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
1673 | else | |
1674 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
1675 | if (vsi->rss_hkey_user) | |
1676 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
1677 | else | |
1678 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
1679 | ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size); | |
1680 | kfree(lut); | |
1681 | return ret; | |
1682 | } | |
1683 | ||
1684 | /** | |
1685 | * i40e_vsi_setup_queue_map_mqprio - Prepares mqprio based tc_config | |
1686 | * @vsi: the VSI being configured, | |
1687 | * @ctxt: VSI context structure | |
1688 | * @enabled_tc: number of traffic classes to enable | |
1689 | * | |
1690 | * Prepares VSI tc_config to have queue configurations based on MQPRIO options. | |
1691 | **/ | |
1692 | static int i40e_vsi_setup_queue_map_mqprio(struct i40e_vsi *vsi, | |
1693 | struct i40e_vsi_context *ctxt, | |
1694 | u8 enabled_tc) | |
1695 | { | |
1696 | u16 qcount = 0, max_qcount, qmap, sections = 0; | |
1697 | int i, override_q, pow, num_qps, ret; | |
1698 | u8 netdev_tc = 0, offset = 0; | |
1699 | ||
1700 | if (vsi->type != I40E_VSI_MAIN) | |
1701 | return -EINVAL; | |
1702 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1703 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1704 | vsi->tc_config.numtc = vsi->mqprio_qopt.qopt.num_tc; | |
1705 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
1706 | num_qps = vsi->mqprio_qopt.qopt.count[0]; | |
1707 | ||
1708 | /* find the next higher power-of-2 of num queue pairs */ | |
1709 | pow = ilog2(num_qps); | |
1710 | if (!is_power_of_2(num_qps)) | |
1711 | pow++; | |
1712 | qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1713 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1714 | ||
1715 | /* Setup queue offset/count for all TCs for given VSI */ | |
1716 | max_qcount = vsi->mqprio_qopt.qopt.count[0]; | |
1717 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1718 | /* See if the given TC is enabled for the given VSI */ | |
1719 | if (vsi->tc_config.enabled_tc & BIT(i)) { | |
1720 | offset = vsi->mqprio_qopt.qopt.offset[i]; | |
1721 | qcount = vsi->mqprio_qopt.qopt.count[i]; | |
1722 | if (qcount > max_qcount) | |
1723 | max_qcount = qcount; | |
1724 | vsi->tc_config.tc_info[i].qoffset = offset; | |
1725 | vsi->tc_config.tc_info[i].qcount = qcount; | |
1726 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1727 | } else { | |
1728 | /* TC is not enabled so set the offset to | |
1729 | * default queue and allocate one queue | |
1730 | * for the given TC. | |
1731 | */ | |
1732 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1733 | vsi->tc_config.tc_info[i].qcount = 1; | |
1734 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1735 | } | |
1736 | } | |
1737 | ||
1738 | /* Set actual Tx/Rx queue pairs */ | |
1739 | vsi->num_queue_pairs = offset + qcount; | |
1740 | ||
1741 | /* Setup queue TC[0].qmap for given VSI context */ | |
1742 | ctxt->info.tc_mapping[0] = cpu_to_le16(qmap); | |
1743 | ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1744 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1745 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1746 | ||
1747 | /* Reconfigure RSS for main VSI with max queue count */ | |
1748 | vsi->rss_size = max_qcount; | |
1749 | ret = i40e_vsi_config_rss(vsi); | |
1750 | if (ret) { | |
1751 | dev_info(&vsi->back->pdev->dev, | |
1752 | "Failed to reconfig rss for num_queues (%u)\n", | |
1753 | max_qcount); | |
1754 | return ret; | |
1755 | } | |
1756 | vsi->reconfig_rss = true; | |
1757 | dev_dbg(&vsi->back->pdev->dev, | |
1758 | "Reconfigured rss with num_queues (%u)\n", max_qcount); | |
1759 | ||
1760 | /* Find queue count available for channel VSIs and starting offset | |
1761 | * for channel VSIs | |
1762 | */ | |
1763 | override_q = vsi->mqprio_qopt.qopt.count[0]; | |
1764 | if (override_q && override_q < vsi->num_queue_pairs) { | |
1765 | vsi->cnt_q_avail = vsi->num_queue_pairs - override_q; | |
1766 | vsi->next_base_queue = override_q; | |
1767 | } | |
1768 | return 0; | |
1769 | } | |
1770 | ||
41c445ff JB |
1771 | /** |
1772 | * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc | |
1773 | * @vsi: the VSI being setup | |
1774 | * @ctxt: VSI context structure | |
1775 | * @enabled_tc: Enabled TCs bitmap | |
1776 | * @is_add: True if called before Add VSI | |
1777 | * | |
1778 | * Setup VSI queue mapping for enabled traffic classes. | |
1779 | **/ | |
1780 | static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, | |
1781 | struct i40e_vsi_context *ctxt, | |
1782 | u8 enabled_tc, | |
1783 | bool is_add) | |
1784 | { | |
1785 | struct i40e_pf *pf = vsi->back; | |
1786 | u16 sections = 0; | |
1787 | u8 netdev_tc = 0; | |
1788 | u16 numtc = 0; | |
1789 | u16 qcount; | |
1790 | u8 offset; | |
1791 | u16 qmap; | |
1792 | int i; | |
4e3b35b0 | 1793 | u16 num_tc_qps = 0; |
41c445ff JB |
1794 | |
1795 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1796 | offset = 0; | |
1797 | ||
1798 | if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { | |
1799 | /* Find numtc from enabled TC bitmap */ | |
1800 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 1801 | if (enabled_tc & BIT(i)) /* TC is enabled */ |
41c445ff JB |
1802 | numtc++; |
1803 | } | |
1804 | if (!numtc) { | |
1805 | dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n"); | |
1806 | numtc = 1; | |
1807 | } | |
1808 | } else { | |
a9ce82f7 | 1809 | /* At least TC0 is enabled in non-DCB, non-MQPRIO case */ |
41c445ff JB |
1810 | numtc = 1; |
1811 | } | |
1812 | ||
1813 | vsi->tc_config.numtc = numtc; | |
1814 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
4e3b35b0 | 1815 | /* Number of queues per enabled TC */ |
7d64402f CS |
1816 | qcount = vsi->alloc_queue_pairs; |
1817 | ||
7f9ff476 | 1818 | num_tc_qps = qcount / numtc; |
e25d00b8 | 1819 | num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf)); |
41c445ff JB |
1820 | |
1821 | /* Setup queue offset/count for all TCs for given VSI */ | |
1822 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1823 | /* See if the given TC is enabled for the given VSI */ | |
75f5cea9 | 1824 | if (vsi->tc_config.enabled_tc & BIT(i)) { |
41a1d04b | 1825 | /* TC is enabled */ |
41c445ff JB |
1826 | int pow, num_qps; |
1827 | ||
41c445ff JB |
1828 | switch (vsi->type) { |
1829 | case I40E_VSI_MAIN: | |
acd65448 HZ |
1830 | qcount = min_t(int, pf->alloc_rss_size, |
1831 | num_tc_qps); | |
41c445ff JB |
1832 | break; |
1833 | case I40E_VSI_FDIR: | |
1834 | case I40E_VSI_SRIOV: | |
1835 | case I40E_VSI_VMDQ2: | |
1836 | default: | |
4e3b35b0 | 1837 | qcount = num_tc_qps; |
41c445ff JB |
1838 | WARN_ON(i != 0); |
1839 | break; | |
1840 | } | |
4e3b35b0 NP |
1841 | vsi->tc_config.tc_info[i].qoffset = offset; |
1842 | vsi->tc_config.tc_info[i].qcount = qcount; | |
41c445ff | 1843 | |
1e200e4a | 1844 | /* find the next higher power-of-2 of num queue pairs */ |
4e3b35b0 | 1845 | num_qps = qcount; |
41c445ff | 1846 | pow = 0; |
41a1d04b | 1847 | while (num_qps && (BIT_ULL(pow) < qcount)) { |
41c445ff JB |
1848 | pow++; |
1849 | num_qps >>= 1; | |
1850 | } | |
1851 | ||
1852 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1853 | qmap = | |
1854 | (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1855 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1856 | ||
4e3b35b0 | 1857 | offset += qcount; |
41c445ff JB |
1858 | } else { |
1859 | /* TC is not enabled so set the offset to | |
1860 | * default queue and allocate one queue | |
1861 | * for the given TC. | |
1862 | */ | |
1863 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1864 | vsi->tc_config.tc_info[i].qcount = 1; | |
1865 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1866 | ||
1867 | qmap = 0; | |
1868 | } | |
1869 | ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); | |
1870 | } | |
1871 | ||
1872 | /* Set actual Tx/Rx queue pairs */ | |
1873 | vsi->num_queue_pairs = offset; | |
9a3bd2f1 ASJ |
1874 | if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) { |
1875 | if (vsi->req_queue_pairs > 0) | |
1876 | vsi->num_queue_pairs = vsi->req_queue_pairs; | |
26cdc443 | 1877 | else if (pf->flags & I40E_FLAG_MSIX_ENABLED) |
9a3bd2f1 ASJ |
1878 | vsi->num_queue_pairs = pf->num_lan_msix; |
1879 | } | |
41c445ff JB |
1880 | |
1881 | /* Scheduler section valid can only be set for ADD VSI */ | |
1882 | if (is_add) { | |
1883 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1884 | ||
1885 | ctxt->info.up_enable_bits = enabled_tc; | |
1886 | } | |
1887 | if (vsi->type == I40E_VSI_SRIOV) { | |
1888 | ctxt->info.mapping_flags |= | |
1889 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); | |
1890 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
1891 | ctxt->info.queue_mapping[i] = | |
1892 | cpu_to_le16(vsi->base_queue + i); | |
1893 | } else { | |
1894 | ctxt->info.mapping_flags |= | |
1895 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1896 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1897 | } | |
1898 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1899 | } | |
1900 | ||
6622f5cd JK |
1901 | /** |
1902 | * i40e_addr_sync - Callback for dev_(mc|uc)_sync to add address | |
1903 | * @netdev: the netdevice | |
1904 | * @addr: address to add | |
1905 | * | |
1906 | * Called by __dev_(mc|uc)_sync when an address needs to be added. We call | |
1907 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1908 | */ | |
1909 | static int i40e_addr_sync(struct net_device *netdev, const u8 *addr) | |
1910 | { | |
1911 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1912 | struct i40e_vsi *vsi = np->vsi; | |
6622f5cd | 1913 | |
feffdbe4 | 1914 | if (i40e_add_mac_filter(vsi, addr)) |
6622f5cd JK |
1915 | return 0; |
1916 | else | |
1917 | return -ENOMEM; | |
1918 | } | |
1919 | ||
1920 | /** | |
1921 | * i40e_addr_unsync - Callback for dev_(mc|uc)_sync to remove address | |
1922 | * @netdev: the netdevice | |
1923 | * @addr: address to add | |
1924 | * | |
1925 | * Called by __dev_(mc|uc)_sync when an address needs to be removed. We call | |
1926 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1927 | */ | |
1928 | static int i40e_addr_unsync(struct net_device *netdev, const u8 *addr) | |
1929 | { | |
1930 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1931 | struct i40e_vsi *vsi = np->vsi; | |
1932 | ||
458867b2 JK |
1933 | /* Under some circumstances, we might receive a request to delete |
1934 | * our own device address from our uc list. Because we store the | |
1935 | * device address in the VSI's MAC/VLAN filter list, we need to ignore | |
1936 | * such requests and not delete our device address from this list. | |
1937 | */ | |
1938 | if (ether_addr_equal(addr, netdev->dev_addr)) | |
1939 | return 0; | |
1940 | ||
feffdbe4 | 1941 | i40e_del_mac_filter(vsi, addr); |
6622f5cd JK |
1942 | |
1943 | return 0; | |
1944 | } | |
1945 | ||
41c445ff JB |
1946 | /** |
1947 | * i40e_set_rx_mode - NDO callback to set the netdev filters | |
1948 | * @netdev: network interface device structure | |
1949 | **/ | |
1950 | static void i40e_set_rx_mode(struct net_device *netdev) | |
1951 | { | |
1952 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 1953 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 1954 | |
278e7d0b | 1955 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 1956 | |
6622f5cd JK |
1957 | __dev_uc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); |
1958 | __dev_mc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); | |
41c445ff | 1959 | |
278e7d0b | 1960 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
1961 | |
1962 | /* check for other flag changes */ | |
1963 | if (vsi->current_netdev_flags != vsi->netdev->flags) { | |
1964 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1965 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1966 | } | |
1967 | } | |
1968 | ||
21659035 | 1969 | /** |
671889e6 | 1970 | * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries |
4a2ce27b | 1971 | * @vsi: Pointer to VSI struct |
21659035 KP |
1972 | * @from: Pointer to list which contains MAC filter entries - changes to |
1973 | * those entries needs to be undone. | |
1974 | * | |
671889e6 | 1975 | * MAC filter entries from this list were slated for deletion. |
21659035 | 1976 | **/ |
671889e6 JK |
1977 | static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi, |
1978 | struct hlist_head *from) | |
21659035 | 1979 | { |
278e7d0b JK |
1980 | struct i40e_mac_filter *f; |
1981 | struct hlist_node *h; | |
1982 | ||
1983 | hlist_for_each_entry_safe(f, h, from, hlist) { | |
1984 | u64 key = i40e_addr_to_hkey(f->macaddr); | |
21659035 | 1985 | |
21659035 | 1986 | /* Move the element back into MAC filter list*/ |
278e7d0b JK |
1987 | hlist_del(&f->hlist); |
1988 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
21659035 KP |
1989 | } |
1990 | } | |
1991 | ||
671889e6 JK |
1992 | /** |
1993 | * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries | |
1994 | * @vsi: Pointer to vsi struct | |
1995 | * @from: Pointer to list which contains MAC filter entries - changes to | |
1996 | * those entries needs to be undone. | |
1997 | * | |
1998 | * MAC filter entries from this list were slated for addition. | |
1999 | **/ | |
2000 | static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi, | |
2001 | struct hlist_head *from) | |
2002 | { | |
2003 | struct i40e_new_mac_filter *new; | |
2004 | struct hlist_node *h; | |
2005 | ||
2006 | hlist_for_each_entry_safe(new, h, from, hlist) { | |
2007 | /* We can simply free the wrapper structure */ | |
2008 | hlist_del(&new->hlist); | |
2009 | kfree(new); | |
2010 | } | |
2011 | } | |
2012 | ||
d88d40b0 JK |
2013 | /** |
2014 | * i40e_next_entry - Get the next non-broadcast filter from a list | |
671889e6 | 2015 | * @next: pointer to filter in list |
d88d40b0 JK |
2016 | * |
2017 | * Returns the next non-broadcast filter in the list. Required so that we | |
2018 | * ignore broadcast filters within the list, since these are not handled via | |
2019 | * the normal firmware update path. | |
2020 | */ | |
671889e6 JK |
2021 | static |
2022 | struct i40e_new_mac_filter *i40e_next_filter(struct i40e_new_mac_filter *next) | |
d88d40b0 | 2023 | { |
584a8870 JK |
2024 | hlist_for_each_entry_continue(next, hlist) { |
2025 | if (!is_broadcast_ether_addr(next->f->macaddr)) | |
2026 | return next; | |
d88d40b0 JK |
2027 | } |
2028 | ||
584a8870 | 2029 | return NULL; |
d88d40b0 JK |
2030 | } |
2031 | ||
21659035 | 2032 | /** |
c3c7ea27 MW |
2033 | * i40e_update_filter_state - Update filter state based on return data |
2034 | * from firmware | |
2035 | * @count: Number of filters added | |
2036 | * @add_list: return data from fw | |
2037 | * @head: pointer to first filter in current batch | |
21659035 | 2038 | * |
c3c7ea27 MW |
2039 | * MAC filter entries from list were slated to be added to device. Returns |
2040 | * number of successful filters. Note that 0 does NOT mean success! | |
21659035 | 2041 | **/ |
c3c7ea27 MW |
2042 | static int |
2043 | i40e_update_filter_state(int count, | |
2044 | struct i40e_aqc_add_macvlan_element_data *add_list, | |
671889e6 | 2045 | struct i40e_new_mac_filter *add_head) |
21659035 | 2046 | { |
c3c7ea27 MW |
2047 | int retval = 0; |
2048 | int i; | |
21659035 | 2049 | |
ac9e2390 JK |
2050 | for (i = 0; i < count; i++) { |
2051 | /* Always check status of each filter. We don't need to check | |
2052 | * the firmware return status because we pre-set the filter | |
2053 | * status to I40E_AQC_MM_ERR_NO_RES when sending the filter | |
2054 | * request to the adminq. Thus, if it no longer matches then | |
2055 | * we know the filter is active. | |
c3c7ea27 | 2056 | */ |
ac9e2390 | 2057 | if (add_list[i].match_method == I40E_AQC_MM_ERR_NO_RES) { |
c3c7ea27 | 2058 | add_head->state = I40E_FILTER_FAILED; |
ac9e2390 JK |
2059 | } else { |
2060 | add_head->state = I40E_FILTER_ACTIVE; | |
2061 | retval++; | |
c3c7ea27 | 2062 | } |
ac9e2390 | 2063 | |
d88d40b0 JK |
2064 | add_head = i40e_next_filter(add_head); |
2065 | if (!add_head) | |
2066 | break; | |
21659035 | 2067 | } |
ac9e2390 | 2068 | |
c3c7ea27 | 2069 | return retval; |
21659035 KP |
2070 | } |
2071 | ||
00936319 JK |
2072 | /** |
2073 | * i40e_aqc_del_filters - Request firmware to delete a set of filters | |
2074 | * @vsi: ptr to the VSI | |
2075 | * @vsi_name: name to display in messages | |
2076 | * @list: the list of filters to send to firmware | |
2077 | * @num_del: the number of filters to delete | |
2078 | * @retval: Set to -EIO on failure to delete | |
2079 | * | |
2080 | * Send a request to firmware via AdminQ to delete a set of filters. Uses | |
2081 | * *retval instead of a return value so that success does not force ret_val to | |
2082 | * be set to 0. This ensures that a sequence of calls to this function | |
2083 | * preserve the previous value of *retval on successful delete. | |
2084 | */ | |
2085 | static | |
2086 | void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
2087 | struct i40e_aqc_remove_macvlan_element_data *list, | |
2088 | int num_del, int *retval) | |
2089 | { | |
2090 | struct i40e_hw *hw = &vsi->back->hw; | |
2091 | i40e_status aq_ret; | |
2092 | int aq_err; | |
2093 | ||
2094 | aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, list, num_del, NULL); | |
2095 | aq_err = hw->aq.asq_last_status; | |
2096 | ||
2097 | /* Explicitly ignore and do not report when firmware returns ENOENT */ | |
2098 | if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { | |
2099 | *retval = -EIO; | |
2100 | dev_info(&vsi->back->pdev->dev, | |
2101 | "ignoring delete macvlan error on %s, err %s, aq_err %s\n", | |
2102 | vsi_name, i40e_stat_str(hw, aq_ret), | |
2103 | i40e_aq_str(hw, aq_err)); | |
2104 | } | |
2105 | } | |
2106 | ||
2107 | /** | |
2108 | * i40e_aqc_add_filters - Request firmware to add a set of filters | |
2109 | * @vsi: ptr to the VSI | |
2110 | * @vsi_name: name to display in messages | |
2111 | * @list: the list of filters to send to firmware | |
2112 | * @add_head: Position in the add hlist | |
2113 | * @num_add: the number of filters to add | |
2114 | * @promisc_change: set to true on exit if promiscuous mode was forced on | |
2115 | * | |
2116 | * Send a request to firmware via AdminQ to add a chunk of filters. Will set | |
2117 | * promisc_changed to true if the firmware has run out of space for more | |
2118 | * filters. | |
2119 | */ | |
2120 | static | |
2121 | void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
2122 | struct i40e_aqc_add_macvlan_element_data *list, | |
671889e6 | 2123 | struct i40e_new_mac_filter *add_head, |
00936319 JK |
2124 | int num_add, bool *promisc_changed) |
2125 | { | |
2126 | struct i40e_hw *hw = &vsi->back->hw; | |
00936319 JK |
2127 | int aq_err, fcnt; |
2128 | ||
ac9e2390 | 2129 | i40e_aq_add_macvlan(hw, vsi->seid, list, num_add, NULL); |
00936319 | 2130 | aq_err = hw->aq.asq_last_status; |
ac9e2390 | 2131 | fcnt = i40e_update_filter_state(num_add, list, add_head); |
00936319 JK |
2132 | |
2133 | if (fcnt != num_add) { | |
2134 | *promisc_changed = true; | |
0da36b97 | 2135 | set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
00936319 JK |
2136 | dev_warn(&vsi->back->pdev->dev, |
2137 | "Error %s adding RX filters on %s, promiscuous mode forced on\n", | |
2138 | i40e_aq_str(hw, aq_err), | |
2139 | vsi_name); | |
2140 | } | |
2141 | } | |
2142 | ||
435c084a JK |
2143 | /** |
2144 | * i40e_aqc_broadcast_filter - Set promiscuous broadcast flags | |
2145 | * @vsi: pointer to the VSI | |
2146 | * @f: filter data | |
2147 | * | |
2148 | * This function sets or clears the promiscuous broadcast flags for VLAN | |
2149 | * filters in order to properly receive broadcast frames. Assumes that only | |
2150 | * broadcast filters are passed. | |
671889e6 JK |
2151 | * |
2152 | * Returns status indicating success or failure; | |
435c084a | 2153 | **/ |
671889e6 JK |
2154 | static i40e_status |
2155 | i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name, | |
2156 | struct i40e_mac_filter *f) | |
435c084a JK |
2157 | { |
2158 | bool enable = f->state == I40E_FILTER_NEW; | |
2159 | struct i40e_hw *hw = &vsi->back->hw; | |
2160 | i40e_status aq_ret; | |
2161 | ||
2162 | if (f->vlan == I40E_VLAN_ANY) { | |
2163 | aq_ret = i40e_aq_set_vsi_broadcast(hw, | |
2164 | vsi->seid, | |
2165 | enable, | |
2166 | NULL); | |
2167 | } else { | |
2168 | aq_ret = i40e_aq_set_vsi_bc_promisc_on_vlan(hw, | |
2169 | vsi->seid, | |
2170 | enable, | |
2171 | f->vlan, | |
2172 | NULL); | |
2173 | } | |
2174 | ||
671889e6 | 2175 | if (aq_ret) |
435c084a JK |
2176 | dev_warn(&vsi->back->pdev->dev, |
2177 | "Error %s setting broadcast promiscuous mode on %s\n", | |
2178 | i40e_aq_str(hw, hw->aq.asq_last_status), | |
2179 | vsi_name); | |
671889e6 JK |
2180 | |
2181 | return aq_ret; | |
435c084a JK |
2182 | } |
2183 | ||
bd5608b3 AB |
2184 | /** |
2185 | * i40e_set_promiscuous - set promiscuous mode | |
2186 | * @pf: board private structure | |
2187 | * @promisc: promisc on or off | |
2188 | * | |
2189 | * There are different ways of setting promiscuous mode on a PF depending on | |
2190 | * what state/environment we're in. This identifies and sets it appropriately. | |
2191 | * Returns 0 on success. | |
2192 | **/ | |
2193 | static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc) | |
2194 | { | |
2195 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
2196 | struct i40e_hw *hw = &pf->hw; | |
2197 | i40e_status aq_ret; | |
2198 | ||
2199 | if (vsi->type == I40E_VSI_MAIN && | |
2200 | pf->lan_veb != I40E_NO_VEB && | |
2201 | !(pf->flags & I40E_FLAG_MFP_ENABLED)) { | |
2202 | /* set defport ON for Main VSI instead of true promisc | |
2203 | * this way we will get all unicast/multicast and VLAN | |
2204 | * promisc behavior but will not get VF or VMDq traffic | |
2205 | * replicated on the Main VSI. | |
2206 | */ | |
2207 | if (promisc) | |
2208 | aq_ret = i40e_aq_set_default_vsi(hw, | |
2209 | vsi->seid, | |
2210 | NULL); | |
2211 | else | |
2212 | aq_ret = i40e_aq_clear_default_vsi(hw, | |
2213 | vsi->seid, | |
2214 | NULL); | |
2215 | if (aq_ret) { | |
2216 | dev_info(&pf->pdev->dev, | |
2217 | "Set default VSI failed, err %s, aq_err %s\n", | |
2218 | i40e_stat_str(hw, aq_ret), | |
2219 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2220 | } | |
2221 | } else { | |
2222 | aq_ret = i40e_aq_set_vsi_unicast_promiscuous( | |
2223 | hw, | |
2224 | vsi->seid, | |
2225 | promisc, NULL, | |
2226 | true); | |
2227 | if (aq_ret) { | |
2228 | dev_info(&pf->pdev->dev, | |
2229 | "set unicast promisc failed, err %s, aq_err %s\n", | |
2230 | i40e_stat_str(hw, aq_ret), | |
2231 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2232 | } | |
2233 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous( | |
2234 | hw, | |
2235 | vsi->seid, | |
2236 | promisc, NULL); | |
2237 | if (aq_ret) { | |
2238 | dev_info(&pf->pdev->dev, | |
2239 | "set multicast promisc failed, err %s, aq_err %s\n", | |
2240 | i40e_stat_str(hw, aq_ret), | |
2241 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2242 | } | |
2243 | } | |
2244 | ||
2245 | if (!aq_ret) | |
2246 | pf->cur_promisc = promisc; | |
2247 | ||
2248 | return aq_ret; | |
2249 | } | |
2250 | ||
41c445ff JB |
2251 | /** |
2252 | * i40e_sync_vsi_filters - Update the VSI filter list to the HW | |
2253 | * @vsi: ptr to the VSI | |
2254 | * | |
2255 | * Push any outstanding VSI filter changes through the AdminQ. | |
2256 | * | |
2257 | * Returns 0 or error value | |
2258 | **/ | |
17652c63 | 2259 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi) |
41c445ff | 2260 | { |
278e7d0b | 2261 | struct hlist_head tmp_add_list, tmp_del_list; |
671889e6 JK |
2262 | struct i40e_mac_filter *f; |
2263 | struct i40e_new_mac_filter *new, *add_head = NULL; | |
3e25a8f3 | 2264 | struct i40e_hw *hw = &vsi->back->hw; |
38326218 | 2265 | unsigned int failed_filters = 0; |
84f5ca6c | 2266 | unsigned int vlan_filters = 0; |
c3c7ea27 | 2267 | bool promisc_changed = false; |
2d1de828 | 2268 | char vsi_name[16] = "PF"; |
41c445ff | 2269 | int filter_list_len = 0; |
ea02e90b | 2270 | i40e_status aq_ret = 0; |
84f5ca6c | 2271 | u32 changed_flags = 0; |
278e7d0b | 2272 | struct hlist_node *h; |
41c445ff JB |
2273 | struct i40e_pf *pf; |
2274 | int num_add = 0; | |
2275 | int num_del = 0; | |
84f5ca6c | 2276 | int retval = 0; |
41c445ff | 2277 | u16 cmd_flags; |
c3c7ea27 | 2278 | int list_size; |
278e7d0b | 2279 | int bkt; |
41c445ff JB |
2280 | |
2281 | /* empty array typed pointers, kcalloc later */ | |
2282 | struct i40e_aqc_add_macvlan_element_data *add_list; | |
2283 | struct i40e_aqc_remove_macvlan_element_data *del_list; | |
2284 | ||
0da36b97 | 2285 | while (test_and_set_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state)) |
41c445ff JB |
2286 | usleep_range(1000, 2000); |
2287 | pf = vsi->back; | |
2288 | ||
2289 | if (vsi->netdev) { | |
2290 | changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags; | |
2291 | vsi->current_netdev_flags = vsi->netdev->flags; | |
2292 | } | |
2293 | ||
278e7d0b JK |
2294 | INIT_HLIST_HEAD(&tmp_add_list); |
2295 | INIT_HLIST_HEAD(&tmp_del_list); | |
21659035 | 2296 | |
2d1de828 SN |
2297 | if (vsi->type == I40E_VSI_SRIOV) |
2298 | snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id); | |
2299 | else if (vsi->type != I40E_VSI_MAIN) | |
2300 | snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid); | |
2301 | ||
41c445ff JB |
2302 | if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) { |
2303 | vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED; | |
2304 | ||
278e7d0b | 2305 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 2306 | /* Create a list of filters to delete. */ |
278e7d0b | 2307 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 2308 | if (f->state == I40E_FILTER_REMOVE) { |
c3c7ea27 | 2309 | /* Move the element into temporary del_list */ |
278e7d0b JK |
2310 | hash_del(&f->hlist); |
2311 | hlist_add_head(&f->hlist, &tmp_del_list); | |
84f5ca6c AB |
2312 | |
2313 | /* Avoid counting removed filters */ | |
2314 | continue; | |
c3c7ea27 MW |
2315 | } |
2316 | if (f->state == I40E_FILTER_NEW) { | |
671889e6 JK |
2317 | /* Create a temporary i40e_new_mac_filter */ |
2318 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
2319 | if (!new) | |
2320 | goto err_no_memory_locked; | |
2321 | ||
2322 | /* Store pointer to the real filter */ | |
2323 | new->f = f; | |
2324 | new->state = f->state; | |
2325 | ||
2326 | /* Add it to the hash list */ | |
2327 | hlist_add_head(&new->hlist, &tmp_add_list); | |
21659035 | 2328 | } |
84f5ca6c | 2329 | |
489a3265 JK |
2330 | /* Count the number of active (current and new) VLAN |
2331 | * filters we have now. Does not count filters which | |
2332 | * are marked for deletion. | |
84f5ca6c AB |
2333 | */ |
2334 | if (f->vlan > 0) | |
2335 | vlan_filters++; | |
84f5ca6c AB |
2336 | } |
2337 | ||
489a3265 JK |
2338 | retval = i40e_correct_mac_vlan_filters(vsi, |
2339 | &tmp_add_list, | |
2340 | &tmp_del_list, | |
2341 | vlan_filters); | |
2342 | if (retval) | |
2343 | goto err_no_memory_locked; | |
84f5ca6c | 2344 | |
278e7d0b | 2345 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 KP |
2346 | } |
2347 | ||
2348 | /* Now process 'del_list' outside the lock */ | |
278e7d0b | 2349 | if (!hlist_empty(&tmp_del_list)) { |
3e25a8f3 | 2350 | filter_list_len = hw->aq.asq_buf_size / |
21659035 | 2351 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2352 | list_size = filter_list_len * |
f1199998 | 2353 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2354 | del_list = kzalloc(list_size, GFP_ATOMIC); |
4a2ce27b JK |
2355 | if (!del_list) |
2356 | goto err_no_memory; | |
21659035 | 2357 | |
278e7d0b | 2358 | hlist_for_each_entry_safe(f, h, &tmp_del_list, hlist) { |
41c445ff JB |
2359 | cmd_flags = 0; |
2360 | ||
435c084a | 2361 | /* handle broadcast filters by updating the broadcast |
d88d40b0 | 2362 | * promiscuous flag and release filter list. |
435c084a JK |
2363 | */ |
2364 | if (is_broadcast_ether_addr(f->macaddr)) { | |
2365 | i40e_aqc_broadcast_filter(vsi, vsi_name, f); | |
2366 | ||
2367 | hlist_del(&f->hlist); | |
2368 | kfree(f); | |
2369 | continue; | |
2370 | } | |
2371 | ||
41c445ff | 2372 | /* add to delete list */ |
9a173901 | 2373 | ether_addr_copy(del_list[num_del].mac_addr, f->macaddr); |
c3c7ea27 MW |
2374 | if (f->vlan == I40E_VLAN_ANY) { |
2375 | del_list[num_del].vlan_tag = 0; | |
a6cb9146 | 2376 | cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; |
c3c7ea27 MW |
2377 | } else { |
2378 | del_list[num_del].vlan_tag = | |
2379 | cpu_to_le16((u16)(f->vlan)); | |
2380 | } | |
41c445ff | 2381 | |
41c445ff JB |
2382 | cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; |
2383 | del_list[num_del].flags = cmd_flags; | |
2384 | num_del++; | |
2385 | ||
41c445ff JB |
2386 | /* flush a full buffer */ |
2387 | if (num_del == filter_list_len) { | |
00936319 JK |
2388 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2389 | num_del, &retval); | |
c3c7ea27 | 2390 | memset(del_list, 0, list_size); |
00936319 | 2391 | num_del = 0; |
41c445ff | 2392 | } |
21659035 KP |
2393 | /* Release memory for MAC filter entries which were |
2394 | * synced up with HW. | |
2395 | */ | |
278e7d0b | 2396 | hlist_del(&f->hlist); |
21659035 | 2397 | kfree(f); |
41c445ff | 2398 | } |
21659035 | 2399 | |
41c445ff | 2400 | if (num_del) { |
00936319 JK |
2401 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2402 | num_del, &retval); | |
41c445ff JB |
2403 | } |
2404 | ||
2405 | kfree(del_list); | |
2406 | del_list = NULL; | |
21659035 KP |
2407 | } |
2408 | ||
278e7d0b | 2409 | if (!hlist_empty(&tmp_add_list)) { |
c3c7ea27 | 2410 | /* Do all the adds now. */ |
3e25a8f3 | 2411 | filter_list_len = hw->aq.asq_buf_size / |
f1199998 | 2412 | sizeof(struct i40e_aqc_add_macvlan_element_data); |
c3c7ea27 MW |
2413 | list_size = filter_list_len * |
2414 | sizeof(struct i40e_aqc_add_macvlan_element_data); | |
2415 | add_list = kzalloc(list_size, GFP_ATOMIC); | |
4a2ce27b JK |
2416 | if (!add_list) |
2417 | goto err_no_memory; | |
2418 | ||
c3c7ea27 | 2419 | num_add = 0; |
671889e6 | 2420 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
d19cb64b | 2421 | if (test_bit(__I40E_VSI_OVERFLOW_PROMISC, |
0da36b97 | 2422 | vsi->state)) { |
671889e6 | 2423 | new->state = I40E_FILTER_FAILED; |
c3c7ea27 MW |
2424 | continue; |
2425 | } | |
435c084a JK |
2426 | |
2427 | /* handle broadcast filters by updating the broadcast | |
2428 | * promiscuous flag instead of adding a MAC filter. | |
2429 | */ | |
671889e6 JK |
2430 | if (is_broadcast_ether_addr(new->f->macaddr)) { |
2431 | if (i40e_aqc_broadcast_filter(vsi, vsi_name, | |
2432 | new->f)) | |
2433 | new->state = I40E_FILTER_FAILED; | |
2434 | else | |
2435 | new->state = I40E_FILTER_ACTIVE; | |
435c084a JK |
2436 | continue; |
2437 | } | |
2438 | ||
41c445ff | 2439 | /* add to add array */ |
c3c7ea27 | 2440 | if (num_add == 0) |
671889e6 | 2441 | add_head = new; |
c3c7ea27 | 2442 | cmd_flags = 0; |
671889e6 JK |
2443 | ether_addr_copy(add_list[num_add].mac_addr, |
2444 | new->f->macaddr); | |
2445 | if (new->f->vlan == I40E_VLAN_ANY) { | |
c3c7ea27 MW |
2446 | add_list[num_add].vlan_tag = 0; |
2447 | cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
2448 | } else { | |
2449 | add_list[num_add].vlan_tag = | |
671889e6 | 2450 | cpu_to_le16((u16)(new->f->vlan)); |
c3c7ea27 | 2451 | } |
41c445ff | 2452 | add_list[num_add].queue_number = 0; |
ac9e2390 | 2453 | /* set invalid match method for later detection */ |
0266ac45 | 2454 | add_list[num_add].match_method = I40E_AQC_MM_ERR_NO_RES; |
41c445ff | 2455 | cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; |
41c445ff JB |
2456 | add_list[num_add].flags = cpu_to_le16(cmd_flags); |
2457 | num_add++; | |
2458 | ||
2459 | /* flush a full buffer */ | |
2460 | if (num_add == filter_list_len) { | |
00936319 JK |
2461 | i40e_aqc_add_filters(vsi, vsi_name, add_list, |
2462 | add_head, num_add, | |
2463 | &promisc_changed); | |
c3c7ea27 | 2464 | memset(add_list, 0, list_size); |
41c445ff | 2465 | num_add = 0; |
41c445ff JB |
2466 | } |
2467 | } | |
2468 | if (num_add) { | |
00936319 JK |
2469 | i40e_aqc_add_filters(vsi, vsi_name, add_list, add_head, |
2470 | num_add, &promisc_changed); | |
41c445ff | 2471 | } |
c3c7ea27 MW |
2472 | /* Now move all of the filters from the temp add list back to |
2473 | * the VSI's list. | |
2474 | */ | |
278e7d0b | 2475 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
671889e6 JK |
2476 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
2477 | /* Only update the state if we're still NEW */ | |
2478 | if (new->f->state == I40E_FILTER_NEW) | |
2479 | new->f->state = new->state; | |
2480 | hlist_del(&new->hlist); | |
2481 | kfree(new); | |
c3c7ea27 | 2482 | } |
278e7d0b | 2483 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
2484 | kfree(add_list); |
2485 | add_list = NULL; | |
c3c7ea27 | 2486 | } |
41c445ff | 2487 | |
38326218 JK |
2488 | /* Determine the number of active and failed filters. */ |
2489 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
2490 | vsi->active_filters = 0; | |
2491 | hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) { | |
2492 | if (f->state == I40E_FILTER_ACTIVE) | |
2493 | vsi->active_filters++; | |
2494 | else if (f->state == I40E_FILTER_FAILED) | |
2495 | failed_filters++; | |
2496 | } | |
2497 | spin_unlock_bh(&vsi->mac_filter_hash_lock); | |
2498 | ||
2499 | /* If promiscuous mode has changed, we need to calculate a new | |
2500 | * threshold for when we are safe to exit | |
2501 | */ | |
2502 | if (promisc_changed) | |
2503 | vsi->promisc_threshold = (vsi->active_filters * 3) / 4; | |
2504 | ||
2505 | /* Check if we are able to exit overflow promiscuous mode. We can | |
2506 | * safely exit if we didn't just enter, we no longer have any failed | |
2507 | * filters, and we have reduced filters below the threshold value. | |
2508 | */ | |
0da36b97 | 2509 | if (test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state) && |
38326218 | 2510 | !promisc_changed && !failed_filters && |
c3c7ea27 | 2511 | (vsi->active_filters < vsi->promisc_threshold)) { |
38326218 JK |
2512 | dev_info(&pf->pdev->dev, |
2513 | "filter logjam cleared on %s, leaving overflow promiscuous mode\n", | |
2514 | vsi_name); | |
0da36b97 | 2515 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
38326218 JK |
2516 | promisc_changed = true; |
2517 | vsi->promisc_threshold = 0; | |
41c445ff JB |
2518 | } |
2519 | ||
a856b5cb ASJ |
2520 | /* if the VF is not trusted do not do promisc */ |
2521 | if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) { | |
0da36b97 | 2522 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
a856b5cb ASJ |
2523 | goto out; |
2524 | } | |
2525 | ||
41c445ff JB |
2526 | /* check for changes in promiscuous modes */ |
2527 | if (changed_flags & IFF_ALLMULTI) { | |
2528 | bool cur_multipromisc; | |
6995b36c | 2529 | |
41c445ff | 2530 | cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI); |
ea02e90b MW |
2531 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw, |
2532 | vsi->seid, | |
2533 | cur_multipromisc, | |
2534 | NULL); | |
2535 | if (aq_ret) { | |
2536 | retval = i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2537 | hw->aq.asq_last_status); |
41c445ff | 2538 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2539 | "set multi promisc failed on %s, err %s aq_err %s\n", |
2540 | vsi_name, | |
3e25a8f3 MW |
2541 | i40e_stat_str(hw, aq_ret), |
2542 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2543 | } |
41c445ff | 2544 | } |
e5887239 AB |
2545 | |
2546 | if ((changed_flags & IFF_PROMISC) || promisc_changed) { | |
41c445ff | 2547 | bool cur_promisc; |
6995b36c | 2548 | |
41c445ff | 2549 | cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) || |
d19cb64b | 2550 | test_bit(__I40E_VSI_OVERFLOW_PROMISC, |
0da36b97 | 2551 | vsi->state)); |
bd5608b3 | 2552 | aq_ret = i40e_set_promiscuous(pf, cur_promisc); |
ea02e90b MW |
2553 | if (aq_ret) { |
2554 | retval = i40e_aq_rc_to_posix(aq_ret, | |
bd5608b3 | 2555 | hw->aq.asq_last_status); |
1a10370a | 2556 | dev_info(&pf->pdev->dev, |
bd5608b3 AB |
2557 | "Setting promiscuous %s failed on %s, err %s aq_err %s\n", |
2558 | cur_promisc ? "on" : "off", | |
2559 | vsi_name, | |
2560 | i40e_stat_str(hw, aq_ret), | |
2561 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2562 | } |
41c445ff | 2563 | } |
ea02e90b | 2564 | out: |
2818ccd9 JB |
2565 | /* if something went wrong then set the changed flag so we try again */ |
2566 | if (retval) | |
2567 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
2568 | ||
0da36b97 | 2569 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
ea02e90b | 2570 | return retval; |
4a2ce27b JK |
2571 | |
2572 | err_no_memory: | |
2573 | /* Restore elements on the temporary add and delete lists */ | |
2574 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
84f5ca6c | 2575 | err_no_memory_locked: |
671889e6 JK |
2576 | i40e_undo_del_filter_entries(vsi, &tmp_del_list); |
2577 | i40e_undo_add_filter_entries(vsi, &tmp_add_list); | |
4a2ce27b JK |
2578 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
2579 | ||
2580 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
0da36b97 | 2581 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
4a2ce27b | 2582 | return -ENOMEM; |
41c445ff JB |
2583 | } |
2584 | ||
2585 | /** | |
2586 | * i40e_sync_filters_subtask - Sync the VSI filter list with HW | |
2587 | * @pf: board private structure | |
2588 | **/ | |
2589 | static void i40e_sync_filters_subtask(struct i40e_pf *pf) | |
2590 | { | |
2591 | int v; | |
2592 | ||
2593 | if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC)) | |
2594 | return; | |
2595 | pf->flags &= ~I40E_FLAG_FILTER_SYNC; | |
2596 | ||
505682cd | 2597 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 2598 | if (pf->vsi[v] && |
17652c63 JB |
2599 | (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) { |
2600 | int ret = i40e_sync_vsi_filters(pf->vsi[v]); | |
2601 | ||
2602 | if (ret) { | |
2603 | /* come back and try again later */ | |
2604 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
2605 | break; | |
2606 | } | |
2607 | } | |
41c445ff JB |
2608 | } |
2609 | } | |
2610 | ||
0c8493d9 BT |
2611 | /** |
2612 | * i40e_max_xdp_frame_size - returns the maximum allowed frame size for XDP | |
2613 | * @vsi: the vsi | |
2614 | **/ | |
2615 | static int i40e_max_xdp_frame_size(struct i40e_vsi *vsi) | |
2616 | { | |
2617 | if (PAGE_SIZE >= 8192 || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
2618 | return I40E_RXBUFFER_2048; | |
2619 | else | |
2620 | return I40E_RXBUFFER_3072; | |
2621 | } | |
2622 | ||
41c445ff JB |
2623 | /** |
2624 | * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit | |
2625 | * @netdev: network interface device structure | |
2626 | * @new_mtu: new value for maximum frame size | |
2627 | * | |
2628 | * Returns 0 on success, negative on failure | |
2629 | **/ | |
2630 | static int i40e_change_mtu(struct net_device *netdev, int new_mtu) | |
2631 | { | |
2632 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 2633 | struct i40e_vsi *vsi = np->vsi; |
0ef2d5af | 2634 | struct i40e_pf *pf = vsi->back; |
41c445ff | 2635 | |
0c8493d9 BT |
2636 | if (i40e_enabled_xdp_vsi(vsi)) { |
2637 | int frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
2638 | ||
2639 | if (frame_size > i40e_max_xdp_frame_size(vsi)) | |
2640 | return -EINVAL; | |
2641 | } | |
2642 | ||
41c445ff JB |
2643 | netdev_info(netdev, "changing MTU from %d to %d\n", |
2644 | netdev->mtu, new_mtu); | |
2645 | netdev->mtu = new_mtu; | |
2646 | if (netif_running(netdev)) | |
2647 | i40e_vsi_reinit_locked(vsi); | |
0ef2d5af MW |
2648 | pf->flags |= (I40E_FLAG_SERVICE_CLIENT_REQUESTED | |
2649 | I40E_FLAG_CLIENT_L2_CHANGE); | |
41c445ff JB |
2650 | return 0; |
2651 | } | |
2652 | ||
beb0dff1 JK |
2653 | /** |
2654 | * i40e_ioctl - Access the hwtstamp interface | |
2655 | * @netdev: network interface device structure | |
2656 | * @ifr: interface request data | |
2657 | * @cmd: ioctl command | |
2658 | **/ | |
2659 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
2660 | { | |
2661 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2662 | struct i40e_pf *pf = np->vsi->back; | |
2663 | ||
2664 | switch (cmd) { | |
2665 | case SIOCGHWTSTAMP: | |
2666 | return i40e_ptp_get_ts_config(pf, ifr); | |
2667 | case SIOCSHWTSTAMP: | |
2668 | return i40e_ptp_set_ts_config(pf, ifr); | |
2669 | default: | |
2670 | return -EOPNOTSUPP; | |
2671 | } | |
2672 | } | |
2673 | ||
41c445ff JB |
2674 | /** |
2675 | * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI | |
2676 | * @vsi: the vsi being adjusted | |
2677 | **/ | |
2678 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi) | |
2679 | { | |
2680 | struct i40e_vsi_context ctxt; | |
2681 | i40e_status ret; | |
2682 | ||
2683 | if ((vsi->info.valid_sections & | |
2684 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2685 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0)) | |
2686 | return; /* already enabled */ | |
2687 | ||
2688 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2689 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2690 | I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; | |
2691 | ||
2692 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2693 | ctxt.info = vsi->info; |
41c445ff JB |
2694 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2695 | if (ret) { | |
2696 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2697 | "update vlan stripping failed, err %s aq_err %s\n", |
2698 | i40e_stat_str(&vsi->back->hw, ret), | |
2699 | i40e_aq_str(&vsi->back->hw, | |
2700 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2701 | } |
2702 | } | |
2703 | ||
2704 | /** | |
2705 | * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI | |
2706 | * @vsi: the vsi being adjusted | |
2707 | **/ | |
2708 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi) | |
2709 | { | |
2710 | struct i40e_vsi_context ctxt; | |
2711 | i40e_status ret; | |
2712 | ||
2713 | if ((vsi->info.valid_sections & | |
2714 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2715 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) == | |
2716 | I40E_AQ_VSI_PVLAN_EMOD_MASK)) | |
2717 | return; /* already disabled */ | |
2718 | ||
2719 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2720 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2721 | I40E_AQ_VSI_PVLAN_EMOD_NOTHING; | |
2722 | ||
2723 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2724 | ctxt.info = vsi->info; |
41c445ff JB |
2725 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2726 | if (ret) { | |
2727 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2728 | "update vlan stripping failed, err %s aq_err %s\n", |
2729 | i40e_stat_str(&vsi->back->hw, ret), | |
2730 | i40e_aq_str(&vsi->back->hw, | |
2731 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2732 | } |
2733 | } | |
2734 | ||
2735 | /** | |
2736 | * i40e_vlan_rx_register - Setup or shutdown vlan offload | |
2737 | * @netdev: network interface to be adjusted | |
2738 | * @features: netdev features to test if VLAN offload is enabled or not | |
2739 | **/ | |
2740 | static void i40e_vlan_rx_register(struct net_device *netdev, u32 features) | |
2741 | { | |
2742 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2743 | struct i40e_vsi *vsi = np->vsi; | |
2744 | ||
2745 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2746 | i40e_vlan_stripping_enable(vsi); | |
2747 | else | |
2748 | i40e_vlan_stripping_disable(vsi); | |
2749 | } | |
2750 | ||
2751 | /** | |
490a4ad3 | 2752 | * i40e_add_vlan_all_mac - Add a MAC/VLAN filter for each existing MAC address |
41c445ff JB |
2753 | * @vsi: the vsi being configured |
2754 | * @vid: vlan id to be added (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2755 | * |
2756 | * This is a helper function for adding a new MAC/VLAN filter with the | |
2757 | * specified VLAN for each existing MAC address already in the hash table. | |
2758 | * This function does *not* perform any accounting to update filters based on | |
2759 | * VLAN mode. | |
2760 | * | |
2761 | * NOTE: this function expects to be called while under the | |
2762 | * mac_filter_hash_lock | |
41c445ff | 2763 | **/ |
9af52f60 | 2764 | int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2765 | { |
490a4ad3 | 2766 | struct i40e_mac_filter *f, *add_f; |
278e7d0b JK |
2767 | struct hlist_node *h; |
2768 | int bkt; | |
41c445ff | 2769 | |
278e7d0b | 2770 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
2771 | if (f->state == I40E_FILTER_REMOVE) |
2772 | continue; | |
1bc87e80 | 2773 | add_f = i40e_add_filter(vsi, f->macaddr, vid); |
41c445ff JB |
2774 | if (!add_f) { |
2775 | dev_info(&vsi->back->pdev->dev, | |
2776 | "Could not add vlan filter %d for %pM\n", | |
2777 | vid, f->macaddr); | |
2778 | return -ENOMEM; | |
2779 | } | |
2780 | } | |
2781 | ||
490a4ad3 JK |
2782 | return 0; |
2783 | } | |
2784 | ||
2785 | /** | |
2786 | * i40e_vsi_add_vlan - Add VSI membership for given VLAN | |
2787 | * @vsi: the VSI being configured | |
f94484b7 | 2788 | * @vid: VLAN id to be added |
490a4ad3 | 2789 | **/ |
f94484b7 | 2790 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2791 | { |
489a3265 | 2792 | int err; |
490a4ad3 | 2793 | |
fcf6cfc8 | 2794 | if (vsi->info.pvid) |
f94484b7 JK |
2795 | return -EINVAL; |
2796 | ||
fcf6cfc8 JK |
2797 | /* The network stack will attempt to add VID=0, with the intention to |
2798 | * receive priority tagged packets with a VLAN of 0. Our HW receives | |
2799 | * these packets by default when configured to receive untagged | |
2800 | * packets, so we don't need to add a filter for this case. | |
2801 | * Additionally, HW interprets adding a VID=0 filter as meaning to | |
2802 | * receive *only* tagged traffic and stops receiving untagged traffic. | |
2803 | * Thus, we do not want to actually add a filter for VID=0 | |
2804 | */ | |
2805 | if (!vid) | |
2806 | return 0; | |
2807 | ||
490a4ad3 JK |
2808 | /* Locked once because all functions invoked below iterates list*/ |
2809 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
490a4ad3 | 2810 | err = i40e_add_vlan_all_mac(vsi, vid); |
278e7d0b | 2811 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
489a3265 JK |
2812 | if (err) |
2813 | return err; | |
21659035 | 2814 | |
0e4425ed JB |
2815 | /* schedule our worker thread which will take care of |
2816 | * applying the new filter changes | |
2817 | */ | |
2818 | i40e_service_event_schedule(vsi->back); | |
2819 | return 0; | |
41c445ff JB |
2820 | } |
2821 | ||
2822 | /** | |
490a4ad3 | 2823 | * i40e_rm_vlan_all_mac - Remove MAC/VLAN pair for all MAC with the given VLAN |
41c445ff JB |
2824 | * @vsi: the vsi being configured |
2825 | * @vid: vlan id to be removed (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2826 | * |
2827 | * This function should be used to remove all VLAN filters which match the | |
2828 | * given VID. It does not schedule the service event and does not take the | |
2829 | * mac_filter_hash_lock so it may be combined with other operations under | |
2830 | * a single invocation of the mac_filter_hash_lock. | |
2831 | * | |
2832 | * NOTE: this function expects to be called while under the | |
2833 | * mac_filter_hash_lock | |
2834 | */ | |
9af52f60 | 2835 | void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2836 | { |
84f5ca6c | 2837 | struct i40e_mac_filter *f; |
278e7d0b | 2838 | struct hlist_node *h; |
278e7d0b | 2839 | int bkt; |
41c445ff | 2840 | |
278e7d0b | 2841 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
290d2557 JK |
2842 | if (f->vlan == vid) |
2843 | __i40e_del_filter(vsi, f); | |
2844 | } | |
490a4ad3 | 2845 | } |
41c445ff | 2846 | |
490a4ad3 JK |
2847 | /** |
2848 | * i40e_vsi_kill_vlan - Remove VSI membership for given VLAN | |
2849 | * @vsi: the VSI being configured | |
f94484b7 | 2850 | * @vid: VLAN id to be removed |
490a4ad3 | 2851 | **/ |
f94484b7 | 2852 | void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2853 | { |
f94484b7 JK |
2854 | if (!vid || vsi->info.pvid) |
2855 | return; | |
2856 | ||
490a4ad3 JK |
2857 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
2858 | i40e_rm_vlan_all_mac(vsi, vid); | |
278e7d0b | 2859 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2860 | |
0e4425ed JB |
2861 | /* schedule our worker thread which will take care of |
2862 | * applying the new filter changes | |
2863 | */ | |
2864 | i40e_service_event_schedule(vsi->back); | |
41c445ff JB |
2865 | } |
2866 | ||
2867 | /** | |
2868 | * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload | |
2869 | * @netdev: network interface to be adjusted | |
2870 | * @vid: vlan id to be added | |
078b5876 JB |
2871 | * |
2872 | * net_device_ops implementation for adding vlan ids | |
41c445ff JB |
2873 | **/ |
2874 | static int i40e_vlan_rx_add_vid(struct net_device *netdev, | |
2875 | __always_unused __be16 proto, u16 vid) | |
2876 | { | |
2877 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2878 | struct i40e_vsi *vsi = np->vsi; | |
078b5876 | 2879 | int ret = 0; |
41c445ff | 2880 | |
6a112785 | 2881 | if (vid >= VLAN_N_VID) |
078b5876 JB |
2882 | return -EINVAL; |
2883 | ||
fcf6cfc8 | 2884 | ret = i40e_vsi_add_vlan(vsi, vid); |
6a112785 | 2885 | if (!ret) |
078b5876 | 2886 | set_bit(vid, vsi->active_vlans); |
41c445ff | 2887 | |
078b5876 | 2888 | return ret; |
41c445ff JB |
2889 | } |
2890 | ||
2891 | /** | |
2892 | * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload | |
2893 | * @netdev: network interface to be adjusted | |
2894 | * @vid: vlan id to be removed | |
078b5876 | 2895 | * |
fdfd943e | 2896 | * net_device_ops implementation for removing vlan ids |
41c445ff JB |
2897 | **/ |
2898 | static int i40e_vlan_rx_kill_vid(struct net_device *netdev, | |
2899 | __always_unused __be16 proto, u16 vid) | |
2900 | { | |
2901 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2902 | struct i40e_vsi *vsi = np->vsi; | |
2903 | ||
41c445ff JB |
2904 | /* return code is ignored as there is nothing a user |
2905 | * can do about failure to remove and a log message was | |
078b5876 | 2906 | * already printed from the other function |
41c445ff JB |
2907 | */ |
2908 | i40e_vsi_kill_vlan(vsi, vid); | |
2909 | ||
2910 | clear_bit(vid, vsi->active_vlans); | |
078b5876 | 2911 | |
41c445ff JB |
2912 | return 0; |
2913 | } | |
2914 | ||
2915 | /** | |
2916 | * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up | |
2917 | * @vsi: the vsi being brought back up | |
2918 | **/ | |
2919 | static void i40e_restore_vlan(struct i40e_vsi *vsi) | |
2920 | { | |
2921 | u16 vid; | |
2922 | ||
2923 | if (!vsi->netdev) | |
2924 | return; | |
2925 | ||
2926 | i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features); | |
2927 | ||
2928 | for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID) | |
2929 | i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q), | |
2930 | vid); | |
2931 | } | |
2932 | ||
2933 | /** | |
2934 | * i40e_vsi_add_pvid - Add pvid for the VSI | |
2935 | * @vsi: the vsi being adjusted | |
2936 | * @vid: the vlan id to set as a PVID | |
2937 | **/ | |
dcae29be | 2938 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) |
41c445ff JB |
2939 | { |
2940 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 2941 | i40e_status ret; |
41c445ff JB |
2942 | |
2943 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2944 | vsi->info.pvid = cpu_to_le16(vid); | |
6c12fcbf GR |
2945 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED | |
2946 | I40E_AQ_VSI_PVLAN_INSERT_PVID | | |
b774c7dd | 2947 | I40E_AQ_VSI_PVLAN_EMOD_STR; |
41c445ff JB |
2948 | |
2949 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2950 | ctxt.info = vsi->info; |
f1c7e72e SN |
2951 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2952 | if (ret) { | |
41c445ff | 2953 | dev_info(&vsi->back->pdev->dev, |
f1c7e72e SN |
2954 | "add pvid failed, err %s aq_err %s\n", |
2955 | i40e_stat_str(&vsi->back->hw, ret), | |
2956 | i40e_aq_str(&vsi->back->hw, | |
2957 | vsi->back->hw.aq.asq_last_status)); | |
dcae29be | 2958 | return -ENOENT; |
41c445ff JB |
2959 | } |
2960 | ||
dcae29be | 2961 | return 0; |
41c445ff JB |
2962 | } |
2963 | ||
2964 | /** | |
2965 | * i40e_vsi_remove_pvid - Remove the pvid from the VSI | |
2966 | * @vsi: the vsi being adjusted | |
2967 | * | |
2968 | * Just use the vlan_rx_register() service to put it back to normal | |
2969 | **/ | |
2970 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi) | |
2971 | { | |
6c12fcbf GR |
2972 | i40e_vlan_stripping_disable(vsi); |
2973 | ||
41c445ff | 2974 | vsi->info.pvid = 0; |
41c445ff JB |
2975 | } |
2976 | ||
2977 | /** | |
2978 | * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources | |
2979 | * @vsi: ptr to the VSI | |
2980 | * | |
2981 | * If this function returns with an error, then it's possible one or | |
2982 | * more of the rings is populated (while the rest are not). It is the | |
2983 | * callers duty to clean those orphaned rings. | |
2984 | * | |
2985 | * Return 0 on success, negative on failure | |
2986 | **/ | |
2987 | static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi) | |
2988 | { | |
2989 | int i, err = 0; | |
2990 | ||
2991 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2992 | err = i40e_setup_tx_descriptors(vsi->tx_rings[i]); |
41c445ff | 2993 | |
74608d17 BT |
2994 | if (!i40e_enabled_xdp_vsi(vsi)) |
2995 | return err; | |
2996 | ||
2997 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
2998 | err = i40e_setup_tx_descriptors(vsi->xdp_rings[i]); | |
2999 | ||
41c445ff JB |
3000 | return err; |
3001 | } | |
3002 | ||
3003 | /** | |
3004 | * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues | |
3005 | * @vsi: ptr to the VSI | |
3006 | * | |
3007 | * Free VSI's transmit software resources | |
3008 | **/ | |
3009 | static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi) | |
3010 | { | |
3011 | int i; | |
3012 | ||
74608d17 BT |
3013 | if (vsi->tx_rings) { |
3014 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
3015 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) | |
3016 | i40e_free_tx_resources(vsi->tx_rings[i]); | |
3017 | } | |
8e9dca53 | 3018 | |
74608d17 BT |
3019 | if (vsi->xdp_rings) { |
3020 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
3021 | if (vsi->xdp_rings[i] && vsi->xdp_rings[i]->desc) | |
3022 | i40e_free_tx_resources(vsi->xdp_rings[i]); | |
3023 | } | |
41c445ff JB |
3024 | } |
3025 | ||
3026 | /** | |
3027 | * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources | |
3028 | * @vsi: ptr to the VSI | |
3029 | * | |
3030 | * If this function returns with an error, then it's possible one or | |
3031 | * more of the rings is populated (while the rest are not). It is the | |
3032 | * callers duty to clean those orphaned rings. | |
3033 | * | |
3034 | * Return 0 on success, negative on failure | |
3035 | **/ | |
3036 | static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi) | |
3037 | { | |
3038 | int i, err = 0; | |
3039 | ||
3040 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3041 | err = i40e_setup_rx_descriptors(vsi->rx_rings[i]); |
41c445ff JB |
3042 | return err; |
3043 | } | |
3044 | ||
3045 | /** | |
3046 | * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues | |
3047 | * @vsi: ptr to the VSI | |
3048 | * | |
3049 | * Free all receive software resources | |
3050 | **/ | |
3051 | static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) | |
3052 | { | |
3053 | int i; | |
3054 | ||
8e9dca53 GR |
3055 | if (!vsi->rx_rings) |
3056 | return; | |
3057 | ||
41c445ff | 3058 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 3059 | if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc) |
9f65e15b | 3060 | i40e_free_rx_resources(vsi->rx_rings[i]); |
41c445ff JB |
3061 | } |
3062 | ||
3ffa037d NP |
3063 | /** |
3064 | * i40e_config_xps_tx_ring - Configure XPS for a Tx ring | |
3065 | * @ring: The Tx ring to configure | |
3066 | * | |
3067 | * This enables/disables XPS for a given Tx descriptor ring | |
3068 | * based on the TCs enabled for the VSI that ring belongs to. | |
3069 | **/ | |
3070 | static void i40e_config_xps_tx_ring(struct i40e_ring *ring) | |
3071 | { | |
be664cbe | 3072 | int cpu; |
3ffa037d | 3073 | |
8f88b303 | 3074 | if (!ring->q_vector || !ring->netdev || ring->ch) |
9a660eea JB |
3075 | return; |
3076 | ||
6f853d4f JK |
3077 | /* We only initialize XPS once, so as not to overwrite user settings */ |
3078 | if (test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state)) | |
3079 | return; | |
0e4425ed | 3080 | |
6f853d4f JK |
3081 | cpu = cpumask_local_spread(ring->q_vector->v_idx, -1); |
3082 | netif_set_xps_queue(ring->netdev, get_cpu_mask(cpu), | |
3083 | ring->queue_index); | |
3ffa037d NP |
3084 | } |
3085 | ||
41c445ff JB |
3086 | /** |
3087 | * i40e_configure_tx_ring - Configure a transmit ring context and rest | |
3088 | * @ring: The Tx ring to configure | |
3089 | * | |
3090 | * Configure the Tx descriptor ring in the HMC context. | |
3091 | **/ | |
3092 | static int i40e_configure_tx_ring(struct i40e_ring *ring) | |
3093 | { | |
3094 | struct i40e_vsi *vsi = ring->vsi; | |
3095 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
3096 | struct i40e_hw *hw = &vsi->back->hw; | |
3097 | struct i40e_hmc_obj_txq tx_ctx; | |
3098 | i40e_status err = 0; | |
3099 | u32 qtx_ctl = 0; | |
3100 | ||
3101 | /* some ATR related tx ring init */ | |
60ea5f83 | 3102 | if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) { |
41c445ff JB |
3103 | ring->atr_sample_rate = vsi->back->atr_sample_rate; |
3104 | ring->atr_count = 0; | |
3105 | } else { | |
3106 | ring->atr_sample_rate = 0; | |
3107 | } | |
3108 | ||
3ffa037d NP |
3109 | /* configure XPS */ |
3110 | i40e_config_xps_tx_ring(ring); | |
41c445ff JB |
3111 | |
3112 | /* clear the context structure first */ | |
3113 | memset(&tx_ctx, 0, sizeof(tx_ctx)); | |
3114 | ||
3115 | tx_ctx.new_context = 1; | |
3116 | tx_ctx.base = (ring->dma / 128); | |
3117 | tx_ctx.qlen = ring->count; | |
60ea5f83 JB |
3118 | tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED | |
3119 | I40E_FLAG_FD_ATR_ENABLED)); | |
beb0dff1 | 3120 | tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP); |
1943d8ba JB |
3121 | /* FDIR VSI tx ring can still use RS bit and writebacks */ |
3122 | if (vsi->type != I40E_VSI_FDIR) | |
3123 | tx_ctx.head_wb_ena = 1; | |
3124 | tx_ctx.head_wb_addr = ring->dma + | |
3125 | (ring->count * sizeof(struct i40e_tx_desc)); | |
41c445ff JB |
3126 | |
3127 | /* As part of VSI creation/update, FW allocates certain | |
3128 | * Tx arbitration queue sets for each TC enabled for | |
3129 | * the VSI. The FW returns the handles to these queue | |
3130 | * sets as part of the response buffer to Add VSI, | |
3131 | * Update VSI, etc. AQ commands. It is expected that | |
3132 | * these queue set handles be associated with the Tx | |
3133 | * queues by the driver as part of the TX queue context | |
3134 | * initialization. This has to be done regardless of | |
3135 | * DCB as by default everything is mapped to TC0. | |
3136 | */ | |
8f88b303 AN |
3137 | |
3138 | if (ring->ch) | |
3139 | tx_ctx.rdylist = | |
3140 | le16_to_cpu(ring->ch->info.qs_handle[ring->dcb_tc]); | |
3141 | ||
3142 | else | |
3143 | tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]); | |
3144 | ||
41c445ff JB |
3145 | tx_ctx.rdylist_act = 0; |
3146 | ||
3147 | /* clear the context in the HMC */ | |
3148 | err = i40e_clear_lan_tx_queue_context(hw, pf_q); | |
3149 | if (err) { | |
3150 | dev_info(&vsi->back->pdev->dev, | |
3151 | "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n", | |
3152 | ring->queue_index, pf_q, err); | |
3153 | return -ENOMEM; | |
3154 | } | |
3155 | ||
3156 | /* set the context in the HMC */ | |
3157 | err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); | |
3158 | if (err) { | |
3159 | dev_info(&vsi->back->pdev->dev, | |
3160 | "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n", | |
3161 | ring->queue_index, pf_q, err); | |
3162 | return -ENOMEM; | |
3163 | } | |
3164 | ||
3165 | /* Now associate this queue with this PCI function */ | |
8f88b303 AN |
3166 | if (ring->ch) { |
3167 | if (ring->ch->type == I40E_VSI_VMDQ2) | |
3168 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; | |
3169 | else | |
3170 | return -EINVAL; | |
3171 | ||
3172 | qtx_ctl |= (ring->ch->vsi_number << | |
3173 | I40E_QTX_CTL_VFVM_INDX_SHIFT) & | |
3174 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
7a28d885 | 3175 | } else { |
8f88b303 AN |
3176 | if (vsi->type == I40E_VSI_VMDQ2) { |
3177 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; | |
3178 | qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & | |
3179 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
3180 | } else { | |
3181 | qtx_ctl = I40E_QTX_CTL_PF_QUEUE; | |
3182 | } | |
7a28d885 MW |
3183 | } |
3184 | ||
13fd9774 SN |
3185 | qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & |
3186 | I40E_QTX_CTL_PF_INDX_MASK); | |
41c445ff JB |
3187 | wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); |
3188 | i40e_flush(hw); | |
3189 | ||
41c445ff JB |
3190 | /* cache tail off for easier writes later */ |
3191 | ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); | |
3192 | ||
3193 | return 0; | |
3194 | } | |
3195 | ||
3196 | /** | |
3197 | * i40e_configure_rx_ring - Configure a receive ring context | |
3198 | * @ring: The Rx ring to configure | |
3199 | * | |
3200 | * Configure the Rx descriptor ring in the HMC context. | |
3201 | **/ | |
3202 | static int i40e_configure_rx_ring(struct i40e_ring *ring) | |
3203 | { | |
3204 | struct i40e_vsi *vsi = ring->vsi; | |
3205 | u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len; | |
3206 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
3207 | struct i40e_hw *hw = &vsi->back->hw; | |
3208 | struct i40e_hmc_obj_rxq rx_ctx; | |
3209 | i40e_status err = 0; | |
3210 | ||
bd6cd4e6 | 3211 | bitmap_zero(ring->state, __I40E_RING_STATE_NBITS); |
41c445ff JB |
3212 | |
3213 | /* clear the context structure first */ | |
3214 | memset(&rx_ctx, 0, sizeof(rx_ctx)); | |
3215 | ||
3216 | ring->rx_buf_len = vsi->rx_buf_len; | |
41c445ff | 3217 | |
dab86afd AD |
3218 | rx_ctx.dbuff = DIV_ROUND_UP(ring->rx_buf_len, |
3219 | BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); | |
41c445ff JB |
3220 | |
3221 | rx_ctx.base = (ring->dma / 128); | |
3222 | rx_ctx.qlen = ring->count; | |
3223 | ||
bec60fc4 JB |
3224 | /* use 32 byte descriptors */ |
3225 | rx_ctx.dsize = 1; | |
41c445ff | 3226 | |
bec60fc4 JB |
3227 | /* descriptor type is always zero |
3228 | * rx_ctx.dtype = 0; | |
3229 | */ | |
b32bfa17 | 3230 | rx_ctx.hsplit_0 = 0; |
41c445ff | 3231 | |
b32bfa17 | 3232 | rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len); |
7134f9ce JB |
3233 | if (hw->revision_id == 0) |
3234 | rx_ctx.lrxqthresh = 0; | |
3235 | else | |
7362be9e | 3236 | rx_ctx.lrxqthresh = 1; |
41c445ff JB |
3237 | rx_ctx.crcstrip = 1; |
3238 | rx_ctx.l2tsel = 1; | |
c4bbac39 JB |
3239 | /* this controls whether VLAN is stripped from inner headers */ |
3240 | rx_ctx.showiv = 0; | |
acb3676b CS |
3241 | /* set the prefena field to 1 because the manual says to */ |
3242 | rx_ctx.prefena = 1; | |
41c445ff JB |
3243 | |
3244 | /* clear the context in the HMC */ | |
3245 | err = i40e_clear_lan_rx_queue_context(hw, pf_q); | |
3246 | if (err) { | |
3247 | dev_info(&vsi->back->pdev->dev, | |
3248 | "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3249 | ring->queue_index, pf_q, err); | |
3250 | return -ENOMEM; | |
3251 | } | |
3252 | ||
3253 | /* set the context in the HMC */ | |
3254 | err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx); | |
3255 | if (err) { | |
3256 | dev_info(&vsi->back->pdev->dev, | |
3257 | "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3258 | ring->queue_index, pf_q, err); | |
3259 | return -ENOMEM; | |
3260 | } | |
3261 | ||
ca9ec088 AD |
3262 | /* configure Rx buffer alignment */ |
3263 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
3264 | clear_ring_build_skb_enabled(ring); | |
3265 | else | |
3266 | set_ring_build_skb_enabled(ring); | |
3267 | ||
41c445ff JB |
3268 | /* cache tail for quicker writes, and clear the reg before use */ |
3269 | ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q); | |
3270 | writel(0, ring->tail); | |
3271 | ||
1a557afc | 3272 | i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring)); |
41c445ff JB |
3273 | |
3274 | return 0; | |
3275 | } | |
3276 | ||
3277 | /** | |
3278 | * i40e_vsi_configure_tx - Configure the VSI for Tx | |
3279 | * @vsi: VSI structure describing this set of rings and resources | |
3280 | * | |
3281 | * Configure the Tx VSI for operation. | |
3282 | **/ | |
3283 | static int i40e_vsi_configure_tx(struct i40e_vsi *vsi) | |
3284 | { | |
3285 | int err = 0; | |
3286 | u16 i; | |
3287 | ||
9f65e15b AD |
3288 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) |
3289 | err = i40e_configure_tx_ring(vsi->tx_rings[i]); | |
41c445ff | 3290 | |
74608d17 BT |
3291 | if (!i40e_enabled_xdp_vsi(vsi)) |
3292 | return err; | |
3293 | ||
3294 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) | |
3295 | err = i40e_configure_tx_ring(vsi->xdp_rings[i]); | |
3296 | ||
41c445ff JB |
3297 | return err; |
3298 | } | |
3299 | ||
3300 | /** | |
3301 | * i40e_vsi_configure_rx - Configure the VSI for Rx | |
3302 | * @vsi: the VSI being configured | |
3303 | * | |
3304 | * Configure the Rx VSI for operation. | |
3305 | **/ | |
3306 | static int i40e_vsi_configure_rx(struct i40e_vsi *vsi) | |
3307 | { | |
3308 | int err = 0; | |
3309 | u16 i; | |
3310 | ||
dab86afd AD |
3311 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) { |
3312 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
3313 | vsi->rx_buf_len = I40E_RXBUFFER_2048; | |
3314 | #if (PAGE_SIZE < 8192) | |
ca9ec088 AD |
3315 | } else if (!I40E_2K_TOO_SMALL_WITH_PADDING && |
3316 | (vsi->netdev->mtu <= ETH_DATA_LEN)) { | |
dab86afd AD |
3317 | vsi->max_frame = I40E_RXBUFFER_1536 - NET_IP_ALIGN; |
3318 | vsi->rx_buf_len = I40E_RXBUFFER_1536 - NET_IP_ALIGN; | |
3319 | #endif | |
3320 | } else { | |
3321 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
98efd694 AD |
3322 | vsi->rx_buf_len = (PAGE_SIZE < 8192) ? I40E_RXBUFFER_3072 : |
3323 | I40E_RXBUFFER_2048; | |
dab86afd | 3324 | } |
41c445ff JB |
3325 | |
3326 | /* set up individual rings */ | |
3327 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3328 | err = i40e_configure_rx_ring(vsi->rx_rings[i]); |
41c445ff JB |
3329 | |
3330 | return err; | |
3331 | } | |
3332 | ||
3333 | /** | |
3334 | * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC | |
3335 | * @vsi: ptr to the VSI | |
3336 | **/ | |
3337 | static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi) | |
3338 | { | |
e7046ee1 | 3339 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff JB |
3340 | u16 qoffset, qcount; |
3341 | int i, n; | |
3342 | ||
cd238a3e PN |
3343 | if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
3344 | /* Reset the TC information */ | |
3345 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
3346 | rx_ring = vsi->rx_rings[i]; | |
3347 | tx_ring = vsi->tx_rings[i]; | |
3348 | rx_ring->dcb_tc = 0; | |
3349 | tx_ring->dcb_tc = 0; | |
3350 | } | |
a9ce82f7 | 3351 | return; |
cd238a3e | 3352 | } |
41c445ff JB |
3353 | |
3354 | for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) { | |
41a1d04b | 3355 | if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) |
41c445ff JB |
3356 | continue; |
3357 | ||
3358 | qoffset = vsi->tc_config.tc_info[n].qoffset; | |
3359 | qcount = vsi->tc_config.tc_info[n].qcount; | |
3360 | for (i = qoffset; i < (qoffset + qcount); i++) { | |
e7046ee1 AA |
3361 | rx_ring = vsi->rx_rings[i]; |
3362 | tx_ring = vsi->tx_rings[i]; | |
41c445ff JB |
3363 | rx_ring->dcb_tc = n; |
3364 | tx_ring->dcb_tc = n; | |
3365 | } | |
3366 | } | |
3367 | } | |
3368 | ||
3369 | /** | |
3370 | * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI | |
3371 | * @vsi: ptr to the VSI | |
3372 | **/ | |
3373 | static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi) | |
3374 | { | |
3375 | if (vsi->netdev) | |
3376 | i40e_set_rx_mode(vsi->netdev); | |
3377 | } | |
3378 | ||
17a73f6b JG |
3379 | /** |
3380 | * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters | |
3381 | * @vsi: Pointer to the targeted VSI | |
3382 | * | |
3383 | * This function replays the hlist on the hw where all the SB Flow Director | |
3384 | * filters were saved. | |
3385 | **/ | |
3386 | static void i40e_fdir_filter_restore(struct i40e_vsi *vsi) | |
3387 | { | |
3388 | struct i40e_fdir_filter *filter; | |
3389 | struct i40e_pf *pf = vsi->back; | |
3390 | struct hlist_node *node; | |
3391 | ||
55a5e60b ASJ |
3392 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
3393 | return; | |
3394 | ||
6d069425 | 3395 | /* Reset FDir counters as we're replaying all existing filters */ |
097dbf52 JK |
3396 | pf->fd_tcp4_filter_cnt = 0; |
3397 | pf->fd_udp4_filter_cnt = 0; | |
f223c875 | 3398 | pf->fd_sctp4_filter_cnt = 0; |
097dbf52 | 3399 | pf->fd_ip4_filter_cnt = 0; |
6d069425 | 3400 | |
17a73f6b JG |
3401 | hlist_for_each_entry_safe(filter, node, |
3402 | &pf->fdir_filter_list, fdir_node) { | |
3403 | i40e_add_del_fdir(vsi, filter, true); | |
3404 | } | |
3405 | } | |
3406 | ||
41c445ff JB |
3407 | /** |
3408 | * i40e_vsi_configure - Set up the VSI for action | |
3409 | * @vsi: the VSI being configured | |
3410 | **/ | |
3411 | static int i40e_vsi_configure(struct i40e_vsi *vsi) | |
3412 | { | |
3413 | int err; | |
3414 | ||
3415 | i40e_set_vsi_rx_mode(vsi); | |
3416 | i40e_restore_vlan(vsi); | |
3417 | i40e_vsi_config_dcb_rings(vsi); | |
3418 | err = i40e_vsi_configure_tx(vsi); | |
3419 | if (!err) | |
3420 | err = i40e_vsi_configure_rx(vsi); | |
3421 | ||
3422 | return err; | |
3423 | } | |
3424 | ||
3425 | /** | |
3426 | * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW | |
3427 | * @vsi: the VSI being configured | |
3428 | **/ | |
3429 | static void i40e_vsi_configure_msix(struct i40e_vsi *vsi) | |
3430 | { | |
74608d17 | 3431 | bool has_xdp = i40e_enabled_xdp_vsi(vsi); |
41c445ff | 3432 | struct i40e_pf *pf = vsi->back; |
41c445ff JB |
3433 | struct i40e_hw *hw = &pf->hw; |
3434 | u16 vector; | |
3435 | int i, q; | |
41c445ff JB |
3436 | u32 qp; |
3437 | ||
3438 | /* The interrupt indexing is offset by 1 in the PFINT_ITRn | |
3439 | * and PFINT_LNKLSTn registers, e.g.: | |
3440 | * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts) | |
3441 | */ | |
3442 | qp = vsi->base_queue; | |
3443 | vector = vsi->base_vector; | |
493fb300 | 3444 | for (i = 0; i < vsi->num_q_vectors; i++, vector++) { |
ac26fc13 JB |
3445 | struct i40e_q_vector *q_vector = vsi->q_vectors[i]; |
3446 | ||
ee2319cf | 3447 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3448 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting); |
41c445ff JB |
3449 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3450 | wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), | |
3451 | q_vector->rx.itr); | |
a75e8005 | 3452 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting); |
41c445ff JB |
3453 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3454 | wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), | |
3455 | q_vector->tx.itr); | |
ac26fc13 | 3456 | wr32(hw, I40E_PFINT_RATEN(vector - 1), |
1c0e6a36 | 3457 | i40e_intrl_usec_to_reg(vsi->int_rate_limit)); |
41c445ff JB |
3458 | |
3459 | /* Linked list for the queuepairs assigned to this vector */ | |
3460 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); | |
3461 | for (q = 0; q < q_vector->num_ringpairs; q++) { | |
74608d17 | 3462 | u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp; |
ac26fc13 JB |
3463 | u32 val; |
3464 | ||
41c445ff | 3465 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3466 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | |
3467 | (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | |
3468 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | | |
3469 | (I40E_QUEUE_TYPE_TX << | |
3470 | I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3471 | |
3472 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
3473 | ||
74608d17 BT |
3474 | if (has_xdp) { |
3475 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3476 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3477 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3478 | (qp << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3479 | (I40E_QUEUE_TYPE_TX << | |
3480 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3481 | ||
3482 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); | |
3483 | } | |
3484 | ||
41c445ff | 3485 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3486 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | |
3487 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3488 | ((qp + 1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3489 | (I40E_QUEUE_TYPE_RX << | |
3490 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3491 | |
3492 | /* Terminate the linked list */ | |
3493 | if (q == (q_vector->num_ringpairs - 1)) | |
74608d17 BT |
3494 | val |= (I40E_QUEUE_END_OF_LIST << |
3495 | I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
41c445ff JB |
3496 | |
3497 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
3498 | qp++; | |
3499 | } | |
3500 | } | |
3501 | ||
3502 | i40e_flush(hw); | |
3503 | } | |
3504 | ||
3505 | /** | |
3506 | * i40e_enable_misc_int_causes - enable the non-queue interrupts | |
3507 | * @hw: ptr to the hardware info | |
3508 | **/ | |
ab437b5a | 3509 | static void i40e_enable_misc_int_causes(struct i40e_pf *pf) |
41c445ff | 3510 | { |
ab437b5a | 3511 | struct i40e_hw *hw = &pf->hw; |
41c445ff JB |
3512 | u32 val; |
3513 | ||
3514 | /* clear things first */ | |
3515 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ | |
3516 | rd32(hw, I40E_PFINT_ICR0); /* read to clear */ | |
3517 | ||
3518 | val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | | |
3519 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | | |
3520 | I40E_PFINT_ICR0_ENA_GRST_MASK | | |
3521 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | | |
3522 | I40E_PFINT_ICR0_ENA_GPIO_MASK | | |
41c445ff JB |
3523 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | |
3524 | I40E_PFINT_ICR0_ENA_VFLR_MASK | | |
3525 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3526 | ||
0d8e1439 ASJ |
3527 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
3528 | val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3529 | ||
ab437b5a JK |
3530 | if (pf->flags & I40E_FLAG_PTP) |
3531 | val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; | |
3532 | ||
41c445ff JB |
3533 | wr32(hw, I40E_PFINT_ICR0_ENA, val); |
3534 | ||
3535 | /* SW_ITR_IDX = 0, but don't change INTENA */ | |
84ed40e7 ASJ |
3536 | wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | |
3537 | I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | |
41c445ff JB |
3538 | |
3539 | /* OTHER_ITR_IDX = 0 */ | |
3540 | wr32(hw, I40E_PFINT_STAT_CTL0, 0); | |
3541 | } | |
3542 | ||
3543 | /** | |
3544 | * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW | |
3545 | * @vsi: the VSI being configured | |
3546 | **/ | |
3547 | static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi) | |
3548 | { | |
74608d17 | 3549 | u32 nextqp = i40e_enabled_xdp_vsi(vsi) ? vsi->alloc_queue_pairs : 0; |
493fb300 | 3550 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; |
41c445ff JB |
3551 | struct i40e_pf *pf = vsi->back; |
3552 | struct i40e_hw *hw = &pf->hw; | |
3553 | u32 val; | |
3554 | ||
3555 | /* set the ITR configuration */ | |
ee2319cf | 3556 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3557 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting); |
41c445ff JB |
3558 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3559 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr); | |
a75e8005 | 3560 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting); |
41c445ff JB |
3561 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3562 | wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr); | |
3563 | ||
ab437b5a | 3564 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
3565 | |
3566 | /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ | |
3567 | wr32(hw, I40E_PFINT_LNKLST0, 0); | |
3568 | ||
f29eaa3d | 3569 | /* Associate the queue pair to the vector and enable the queue int */ |
74608d17 BT |
3570 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3571 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3572 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)| | |
41c445ff JB |
3573 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); |
3574 | ||
3575 | wr32(hw, I40E_QINT_RQCTL(0), val); | |
3576 | ||
74608d17 BT |
3577 | if (i40e_enabled_xdp_vsi(vsi)) { |
3578 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3579 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)| | |
3580 | (I40E_QUEUE_TYPE_TX | |
3581 | << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3582 | ||
3583 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); | |
3584 | } | |
3585 | ||
41c445ff JB |
3586 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
3587 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3588 | (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3589 | ||
3590 | wr32(hw, I40E_QINT_TQCTL(0), val); | |
3591 | i40e_flush(hw); | |
3592 | } | |
3593 | ||
2ef28cfb MW |
3594 | /** |
3595 | * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0 | |
3596 | * @pf: board private structure | |
3597 | **/ | |
3598 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) | |
3599 | { | |
3600 | struct i40e_hw *hw = &pf->hw; | |
3601 | ||
3602 | wr32(hw, I40E_PFINT_DYN_CTL0, | |
3603 | I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
3604 | i40e_flush(hw); | |
3605 | } | |
3606 | ||
41c445ff JB |
3607 | /** |
3608 | * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 | |
3609 | * @pf: board private structure | |
3610 | **/ | |
dbadbbe2 | 3611 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf) |
41c445ff JB |
3612 | { |
3613 | struct i40e_hw *hw = &pf->hw; | |
3614 | u32 val; | |
3615 | ||
3616 | val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
dbadbbe2 | 3617 | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | |
41c445ff JB |
3618 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); |
3619 | ||
3620 | wr32(hw, I40E_PFINT_DYN_CTL0, val); | |
3621 | i40e_flush(hw); | |
3622 | } | |
3623 | ||
41c445ff JB |
3624 | /** |
3625 | * i40e_msix_clean_rings - MSIX mode Interrupt Handler | |
3626 | * @irq: interrupt number | |
3627 | * @data: pointer to a q_vector | |
3628 | **/ | |
3629 | static irqreturn_t i40e_msix_clean_rings(int irq, void *data) | |
3630 | { | |
3631 | struct i40e_q_vector *q_vector = data; | |
3632 | ||
cd0b6fa6 | 3633 | if (!q_vector->tx.ring && !q_vector->rx.ring) |
41c445ff JB |
3634 | return IRQ_HANDLED; |
3635 | ||
5d3465a1 | 3636 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3637 | |
3638 | return IRQ_HANDLED; | |
3639 | } | |
3640 | ||
96db776a AB |
3641 | /** |
3642 | * i40e_irq_affinity_notify - Callback for affinity changes | |
3643 | * @notify: context as to what irq was changed | |
3644 | * @mask: the new affinity mask | |
3645 | * | |
3646 | * This is a callback function used by the irq_set_affinity_notifier function | |
3647 | * so that we may register to receive changes to the irq affinity masks. | |
3648 | **/ | |
3649 | static void i40e_irq_affinity_notify(struct irq_affinity_notify *notify, | |
3650 | const cpumask_t *mask) | |
3651 | { | |
3652 | struct i40e_q_vector *q_vector = | |
3653 | container_of(notify, struct i40e_q_vector, affinity_notify); | |
3654 | ||
7e4d01e7 | 3655 | cpumask_copy(&q_vector->affinity_mask, mask); |
96db776a AB |
3656 | } |
3657 | ||
3658 | /** | |
3659 | * i40e_irq_affinity_release - Callback for affinity notifier release | |
3660 | * @ref: internal core kernel usage | |
3661 | * | |
3662 | * This is a callback function used by the irq_set_affinity_notifier function | |
3663 | * to inform the current notification subscriber that they will no longer | |
3664 | * receive notifications. | |
3665 | **/ | |
3666 | static void i40e_irq_affinity_release(struct kref *ref) {} | |
3667 | ||
41c445ff JB |
3668 | /** |
3669 | * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts | |
3670 | * @vsi: the VSI being configured | |
3671 | * @basename: name for the vector | |
3672 | * | |
3673 | * Allocates MSI-X vectors and requests interrupts from the kernel. | |
3674 | **/ | |
3675 | static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename) | |
3676 | { | |
3677 | int q_vectors = vsi->num_q_vectors; | |
3678 | struct i40e_pf *pf = vsi->back; | |
3679 | int base = vsi->base_vector; | |
3680 | int rx_int_idx = 0; | |
3681 | int tx_int_idx = 0; | |
3682 | int vector, err; | |
96db776a | 3683 | int irq_num; |
be664cbe | 3684 | int cpu; |
41c445ff JB |
3685 | |
3686 | for (vector = 0; vector < q_vectors; vector++) { | |
493fb300 | 3687 | struct i40e_q_vector *q_vector = vsi->q_vectors[vector]; |
41c445ff | 3688 | |
96db776a AB |
3689 | irq_num = pf->msix_entries[base + vector].vector; |
3690 | ||
cd0b6fa6 | 3691 | if (q_vector->tx.ring && q_vector->rx.ring) { |
41c445ff JB |
3692 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3693 | "%s-%s-%d", basename, "TxRx", rx_int_idx++); | |
3694 | tx_int_idx++; | |
cd0b6fa6 | 3695 | } else if (q_vector->rx.ring) { |
41c445ff JB |
3696 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3697 | "%s-%s-%d", basename, "rx", rx_int_idx++); | |
cd0b6fa6 | 3698 | } else if (q_vector->tx.ring) { |
41c445ff JB |
3699 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3700 | "%s-%s-%d", basename, "tx", tx_int_idx++); | |
3701 | } else { | |
3702 | /* skip this unused q_vector */ | |
3703 | continue; | |
3704 | } | |
96db776a | 3705 | err = request_irq(irq_num, |
41c445ff JB |
3706 | vsi->irq_handler, |
3707 | 0, | |
3708 | q_vector->name, | |
3709 | q_vector); | |
3710 | if (err) { | |
3711 | dev_info(&pf->pdev->dev, | |
fb43201f | 3712 | "MSIX request_irq failed, error: %d\n", err); |
41c445ff JB |
3713 | goto free_queue_irqs; |
3714 | } | |
96db776a AB |
3715 | |
3716 | /* register for affinity change notifications */ | |
3717 | q_vector->affinity_notify.notify = i40e_irq_affinity_notify; | |
3718 | q_vector->affinity_notify.release = i40e_irq_affinity_release; | |
3719 | irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify); | |
be664cbe JK |
3720 | /* Spread affinity hints out across online CPUs. |
3721 | * | |
3722 | * get_cpu_mask returns a static constant mask with | |
3723 | * a permanent lifetime so it's ok to pass to | |
3724 | * irq_set_affinity_hint without making a copy. | |
759dc4a7 | 3725 | */ |
be664cbe JK |
3726 | cpu = cpumask_local_spread(q_vector->v_idx, -1); |
3727 | irq_set_affinity_hint(irq_num, get_cpu_mask(cpu)); | |
41c445ff JB |
3728 | } |
3729 | ||
63741846 | 3730 | vsi->irqs_ready = true; |
41c445ff JB |
3731 | return 0; |
3732 | ||
3733 | free_queue_irqs: | |
3734 | while (vector) { | |
3735 | vector--; | |
96db776a AB |
3736 | irq_num = pf->msix_entries[base + vector].vector; |
3737 | irq_set_affinity_notifier(irq_num, NULL); | |
3738 | irq_set_affinity_hint(irq_num, NULL); | |
3739 | free_irq(irq_num, &vsi->q_vectors[vector]); | |
41c445ff JB |
3740 | } |
3741 | return err; | |
3742 | } | |
3743 | ||
3744 | /** | |
3745 | * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI | |
3746 | * @vsi: the VSI being un-configured | |
3747 | **/ | |
3748 | static void i40e_vsi_disable_irq(struct i40e_vsi *vsi) | |
3749 | { | |
3750 | struct i40e_pf *pf = vsi->back; | |
3751 | struct i40e_hw *hw = &pf->hw; | |
3752 | int base = vsi->base_vector; | |
3753 | int i; | |
3754 | ||
2e5c26ea | 3755 | /* disable interrupt causation from each queue */ |
41c445ff | 3756 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
2e5c26ea SN |
3757 | u32 val; |
3758 | ||
3759 | val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx)); | |
3760 | val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK; | |
3761 | wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val); | |
3762 | ||
3763 | val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx)); | |
3764 | val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK; | |
3765 | wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val); | |
3766 | ||
74608d17 BT |
3767 | if (!i40e_enabled_xdp_vsi(vsi)) |
3768 | continue; | |
3769 | wr32(hw, I40E_QINT_TQCTL(vsi->xdp_rings[i]->reg_idx), 0); | |
41c445ff JB |
3770 | } |
3771 | ||
2e5c26ea | 3772 | /* disable each interrupt */ |
41c445ff JB |
3773 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
3774 | for (i = vsi->base_vector; | |
3775 | i < (vsi->num_q_vectors + vsi->base_vector); i++) | |
3776 | wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0); | |
3777 | ||
3778 | i40e_flush(hw); | |
3779 | for (i = 0; i < vsi->num_q_vectors; i++) | |
3780 | synchronize_irq(pf->msix_entries[i + base].vector); | |
3781 | } else { | |
3782 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
3783 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
3784 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
3785 | i40e_flush(hw); | |
3786 | synchronize_irq(pf->pdev->irq); | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | /** | |
3791 | * i40e_vsi_enable_irq - Enable IRQ for the given VSI | |
3792 | * @vsi: the VSI being configured | |
3793 | **/ | |
3794 | static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) | |
3795 | { | |
3796 | struct i40e_pf *pf = vsi->back; | |
3797 | int i; | |
3798 | ||
3799 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
7845548d | 3800 | for (i = 0; i < vsi->num_q_vectors; i++) |
41c445ff JB |
3801 | i40e_irq_dynamic_enable(vsi, i); |
3802 | } else { | |
dbadbbe2 | 3803 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
3804 | } |
3805 | ||
1022cb6c | 3806 | i40e_flush(&pf->hw); |
41c445ff JB |
3807 | return 0; |
3808 | } | |
3809 | ||
3810 | /** | |
c17401a1 | 3811 | * i40e_free_misc_vector - Free the vector that handles non-queue events |
41c445ff JB |
3812 | * @pf: board private structure |
3813 | **/ | |
c17401a1 | 3814 | static void i40e_free_misc_vector(struct i40e_pf *pf) |
41c445ff JB |
3815 | { |
3816 | /* Disable ICR 0 */ | |
3817 | wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0); | |
3818 | i40e_flush(&pf->hw); | |
c17401a1 JK |
3819 | |
3820 | if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) { | |
3821 | synchronize_irq(pf->msix_entries[0].vector); | |
3822 | free_irq(pf->msix_entries[0].vector, pf); | |
3823 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); | |
3824 | } | |
41c445ff JB |
3825 | } |
3826 | ||
3827 | /** | |
3828 | * i40e_intr - MSI/Legacy and non-queue interrupt handler | |
3829 | * @irq: interrupt number | |
3830 | * @data: pointer to a q_vector | |
3831 | * | |
3832 | * This is the handler used for all MSI/Legacy interrupts, and deals | |
3833 | * with both queue and non-queue interrupts. This is also used in | |
3834 | * MSIX mode to handle the non-queue interrupts. | |
3835 | **/ | |
3836 | static irqreturn_t i40e_intr(int irq, void *data) | |
3837 | { | |
3838 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
3839 | struct i40e_hw *hw = &pf->hw; | |
5e823066 | 3840 | irqreturn_t ret = IRQ_NONE; |
41c445ff JB |
3841 | u32 icr0, icr0_remaining; |
3842 | u32 val, ena_mask; | |
3843 | ||
3844 | icr0 = rd32(hw, I40E_PFINT_ICR0); | |
5e823066 | 3845 | ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); |
41c445ff | 3846 | |
116a57d4 SN |
3847 | /* if sharing a legacy IRQ, we might get called w/o an intr pending */ |
3848 | if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0) | |
5e823066 | 3849 | goto enable_intr; |
41c445ff | 3850 | |
cd92e72f SN |
3851 | /* if interrupt but no bits showing, must be SWINT */ |
3852 | if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) || | |
3853 | (icr0 & I40E_PFINT_ICR0_SWINT_MASK)) | |
3854 | pf->sw_int_count++; | |
3855 | ||
0d8e1439 | 3856 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && |
7642984b | 3857 | (icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) { |
0d8e1439 | 3858 | ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; |
23bb6dc3 | 3859 | dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n"); |
7642984b | 3860 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
0d8e1439 ASJ |
3861 | } |
3862 | ||
41c445ff JB |
3863 | /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */ |
3864 | if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) { | |
5d3465a1 AD |
3865 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
3866 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; | |
41c445ff | 3867 | |
a16ae2d5 ASJ |
3868 | /* We do not have a way to disarm Queue causes while leaving |
3869 | * interrupt enabled for all other causes, ideally | |
3870 | * interrupt should be disabled while we are in NAPI but | |
3871 | * this is not a performance path and napi_schedule() | |
3872 | * can deal with rescheduling. | |
3873 | */ | |
9e6c9c0f | 3874 | if (!test_bit(__I40E_DOWN, pf->state)) |
5d3465a1 | 3875 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3876 | } |
3877 | ||
3878 | if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { | |
3879 | ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
0da36b97 | 3880 | set_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
6e93d0c9 | 3881 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n"); |
41c445ff JB |
3882 | } |
3883 | ||
3884 | if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { | |
3885 | ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
0da36b97 | 3886 | set_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
3887 | } |
3888 | ||
3889 | if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { | |
3890 | ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; | |
0da36b97 | 3891 | set_bit(__I40E_VFLR_EVENT_PENDING, pf->state); |
41c445ff JB |
3892 | } |
3893 | ||
3894 | if (icr0 & I40E_PFINT_ICR0_GRST_MASK) { | |
0da36b97 JK |
3895 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
3896 | set_bit(__I40E_RESET_INTR_RECEIVED, pf->state); | |
41c445ff JB |
3897 | ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; |
3898 | val = rd32(hw, I40E_GLGEN_RSTAT); | |
3899 | val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) | |
3900 | >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; | |
4eb3f768 | 3901 | if (val == I40E_RESET_CORER) { |
41c445ff | 3902 | pf->corer_count++; |
4eb3f768 | 3903 | } else if (val == I40E_RESET_GLOBR) { |
41c445ff | 3904 | pf->globr_count++; |
4eb3f768 | 3905 | } else if (val == I40E_RESET_EMPR) { |
41c445ff | 3906 | pf->empr_count++; |
0da36b97 | 3907 | set_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state); |
4eb3f768 | 3908 | } |
41c445ff JB |
3909 | } |
3910 | ||
9c010ee0 ASJ |
3911 | if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) { |
3912 | icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK; | |
3913 | dev_info(&pf->pdev->dev, "HMC error interrupt\n"); | |
25fc0e65 ASJ |
3914 | dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n", |
3915 | rd32(hw, I40E_PFHMC_ERRORINFO), | |
3916 | rd32(hw, I40E_PFHMC_ERRORDATA)); | |
9c010ee0 ASJ |
3917 | } |
3918 | ||
beb0dff1 JK |
3919 | if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) { |
3920 | u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0); | |
3921 | ||
3922 | if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) { | |
cafa1fca | 3923 | icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; |
beb0dff1 | 3924 | i40e_ptp_tx_hwtstamp(pf); |
beb0dff1 | 3925 | } |
beb0dff1 JK |
3926 | } |
3927 | ||
41c445ff JB |
3928 | /* If a critical error is pending we have no choice but to reset the |
3929 | * device. | |
3930 | * Report and mask out any remaining unexpected interrupts. | |
3931 | */ | |
3932 | icr0_remaining = icr0 & ena_mask; | |
3933 | if (icr0_remaining) { | |
3934 | dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n", | |
3935 | icr0_remaining); | |
9c010ee0 | 3936 | if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) || |
41c445ff | 3937 | (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) || |
c0c28975 | 3938 | (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) { |
9c010ee0 | 3939 | dev_info(&pf->pdev->dev, "device will be reset\n"); |
0da36b97 | 3940 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
9c010ee0 | 3941 | i40e_service_event_schedule(pf); |
41c445ff JB |
3942 | } |
3943 | ena_mask &= ~icr0_remaining; | |
3944 | } | |
5e823066 | 3945 | ret = IRQ_HANDLED; |
41c445ff | 3946 | |
5e823066 | 3947 | enable_intr: |
41c445ff JB |
3948 | /* re-enable interrupt causes */ |
3949 | wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); | |
9e6c9c0f | 3950 | if (!test_bit(__I40E_DOWN, pf->state)) { |
41c445ff | 3951 | i40e_service_event_schedule(pf); |
dbadbbe2 | 3952 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
3953 | } |
3954 | ||
5e823066 | 3955 | return ret; |
41c445ff JB |
3956 | } |
3957 | ||
cbf61325 ASJ |
3958 | /** |
3959 | * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes | |
3960 | * @tx_ring: tx ring to clean | |
3961 | * @budget: how many cleans we're allowed | |
3962 | * | |
3963 | * Returns true if there's any budget left (e.g. the clean is finished) | |
3964 | **/ | |
3965 | static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget) | |
3966 | { | |
3967 | struct i40e_vsi *vsi = tx_ring->vsi; | |
3968 | u16 i = tx_ring->next_to_clean; | |
3969 | struct i40e_tx_buffer *tx_buf; | |
3970 | struct i40e_tx_desc *tx_desc; | |
3971 | ||
3972 | tx_buf = &tx_ring->tx_bi[i]; | |
3973 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
3974 | i -= tx_ring->count; | |
3975 | ||
3976 | do { | |
3977 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
3978 | ||
3979 | /* if next_to_watch is not set then there is no work pending */ | |
3980 | if (!eop_desc) | |
3981 | break; | |
3982 | ||
3983 | /* prevent any other reads prior to eop_desc */ | |
52c6912f | 3984 | smp_rmb(); |
cbf61325 ASJ |
3985 | |
3986 | /* if the descriptor isn't done, no work yet to do */ | |
3987 | if (!(eop_desc->cmd_type_offset_bsz & | |
3988 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
3989 | break; | |
3990 | ||
3991 | /* clear next_to_watch to prevent false hangs */ | |
3992 | tx_buf->next_to_watch = NULL; | |
3993 | ||
49d7d933 ASJ |
3994 | tx_desc->buffer_addr = 0; |
3995 | tx_desc->cmd_type_offset_bsz = 0; | |
3996 | /* move past filter desc */ | |
3997 | tx_buf++; | |
3998 | tx_desc++; | |
3999 | i++; | |
4000 | if (unlikely(!i)) { | |
4001 | i -= tx_ring->count; | |
4002 | tx_buf = tx_ring->tx_bi; | |
4003 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
4004 | } | |
cbf61325 ASJ |
4005 | /* unmap skb header data */ |
4006 | dma_unmap_single(tx_ring->dev, | |
4007 | dma_unmap_addr(tx_buf, dma), | |
4008 | dma_unmap_len(tx_buf, len), | |
4009 | DMA_TO_DEVICE); | |
49d7d933 ASJ |
4010 | if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB) |
4011 | kfree(tx_buf->raw_buf); | |
cbf61325 | 4012 | |
49d7d933 ASJ |
4013 | tx_buf->raw_buf = NULL; |
4014 | tx_buf->tx_flags = 0; | |
4015 | tx_buf->next_to_watch = NULL; | |
cbf61325 | 4016 | dma_unmap_len_set(tx_buf, len, 0); |
49d7d933 ASJ |
4017 | tx_desc->buffer_addr = 0; |
4018 | tx_desc->cmd_type_offset_bsz = 0; | |
cbf61325 | 4019 | |
49d7d933 | 4020 | /* move us past the eop_desc for start of next FD desc */ |
cbf61325 ASJ |
4021 | tx_buf++; |
4022 | tx_desc++; | |
4023 | i++; | |
4024 | if (unlikely(!i)) { | |
4025 | i -= tx_ring->count; | |
4026 | tx_buf = tx_ring->tx_bi; | |
4027 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
4028 | } | |
4029 | ||
4030 | /* update budget accounting */ | |
4031 | budget--; | |
4032 | } while (likely(budget)); | |
4033 | ||
4034 | i += tx_ring->count; | |
4035 | tx_ring->next_to_clean = i; | |
4036 | ||
6995b36c | 4037 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) |
7845548d | 4038 | i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx); |
6995b36c | 4039 | |
cbf61325 ASJ |
4040 | return budget > 0; |
4041 | } | |
4042 | ||
4043 | /** | |
4044 | * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring | |
4045 | * @irq: interrupt number | |
4046 | * @data: pointer to a q_vector | |
4047 | **/ | |
4048 | static irqreturn_t i40e_fdir_clean_ring(int irq, void *data) | |
4049 | { | |
4050 | struct i40e_q_vector *q_vector = data; | |
4051 | struct i40e_vsi *vsi; | |
4052 | ||
4053 | if (!q_vector->tx.ring) | |
4054 | return IRQ_HANDLED; | |
4055 | ||
4056 | vsi = q_vector->tx.ring->vsi; | |
4057 | i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit); | |
4058 | ||
4059 | return IRQ_HANDLED; | |
4060 | } | |
4061 | ||
41c445ff | 4062 | /** |
cd0b6fa6 | 4063 | * i40e_map_vector_to_qp - Assigns the queue pair to the vector |
41c445ff JB |
4064 | * @vsi: the VSI being configured |
4065 | * @v_idx: vector index | |
cd0b6fa6 | 4066 | * @qp_idx: queue pair index |
41c445ff | 4067 | **/ |
26cdc443 | 4068 | static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx) |
41c445ff | 4069 | { |
493fb300 | 4070 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; |
9f65e15b AD |
4071 | struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx]; |
4072 | struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx]; | |
41c445ff JB |
4073 | |
4074 | tx_ring->q_vector = q_vector; | |
cd0b6fa6 AD |
4075 | tx_ring->next = q_vector->tx.ring; |
4076 | q_vector->tx.ring = tx_ring; | |
41c445ff | 4077 | q_vector->tx.count++; |
cd0b6fa6 | 4078 | |
74608d17 BT |
4079 | /* Place XDP Tx ring in the same q_vector ring list as regular Tx */ |
4080 | if (i40e_enabled_xdp_vsi(vsi)) { | |
4081 | struct i40e_ring *xdp_ring = vsi->xdp_rings[qp_idx]; | |
4082 | ||
4083 | xdp_ring->q_vector = q_vector; | |
4084 | xdp_ring->next = q_vector->tx.ring; | |
4085 | q_vector->tx.ring = xdp_ring; | |
4086 | q_vector->tx.count++; | |
4087 | } | |
4088 | ||
cd0b6fa6 AD |
4089 | rx_ring->q_vector = q_vector; |
4090 | rx_ring->next = q_vector->rx.ring; | |
4091 | q_vector->rx.ring = rx_ring; | |
4092 | q_vector->rx.count++; | |
41c445ff JB |
4093 | } |
4094 | ||
4095 | /** | |
4096 | * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors | |
4097 | * @vsi: the VSI being configured | |
4098 | * | |
4099 | * This function maps descriptor rings to the queue-specific vectors | |
4100 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
4101 | * one vector per queue pair, but on a constrained vector budget, we | |
4102 | * group the queue pairs as "efficiently" as possible. | |
4103 | **/ | |
4104 | static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi) | |
4105 | { | |
4106 | int qp_remaining = vsi->num_queue_pairs; | |
4107 | int q_vectors = vsi->num_q_vectors; | |
cd0b6fa6 | 4108 | int num_ringpairs; |
41c445ff JB |
4109 | int v_start = 0; |
4110 | int qp_idx = 0; | |
4111 | ||
4112 | /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to | |
4113 | * group them so there are multiple queues per vector. | |
70114ec4 ASJ |
4114 | * It is also important to go through all the vectors available to be |
4115 | * sure that if we don't use all the vectors, that the remaining vectors | |
4116 | * are cleared. This is especially important when decreasing the | |
4117 | * number of queues in use. | |
41c445ff | 4118 | */ |
70114ec4 | 4119 | for (; v_start < q_vectors; v_start++) { |
cd0b6fa6 AD |
4120 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; |
4121 | ||
4122 | num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); | |
4123 | ||
4124 | q_vector->num_ringpairs = num_ringpairs; | |
4125 | ||
4126 | q_vector->rx.count = 0; | |
4127 | q_vector->tx.count = 0; | |
4128 | q_vector->rx.ring = NULL; | |
4129 | q_vector->tx.ring = NULL; | |
4130 | ||
4131 | while (num_ringpairs--) { | |
26cdc443 | 4132 | i40e_map_vector_to_qp(vsi, v_start, qp_idx); |
cd0b6fa6 AD |
4133 | qp_idx++; |
4134 | qp_remaining--; | |
41c445ff JB |
4135 | } |
4136 | } | |
4137 | } | |
4138 | ||
4139 | /** | |
4140 | * i40e_vsi_request_irq - Request IRQ from the OS | |
4141 | * @vsi: the VSI being configured | |
4142 | * @basename: name for the vector | |
4143 | **/ | |
4144 | static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename) | |
4145 | { | |
4146 | struct i40e_pf *pf = vsi->back; | |
4147 | int err; | |
4148 | ||
4149 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
4150 | err = i40e_vsi_request_irq_msix(vsi, basename); | |
4151 | else if (pf->flags & I40E_FLAG_MSI_ENABLED) | |
4152 | err = request_irq(pf->pdev->irq, i40e_intr, 0, | |
b294ac70 | 4153 | pf->int_name, pf); |
41c445ff JB |
4154 | else |
4155 | err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED, | |
b294ac70 | 4156 | pf->int_name, pf); |
41c445ff JB |
4157 | |
4158 | if (err) | |
4159 | dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err); | |
4160 | ||
4161 | return err; | |
4162 | } | |
4163 | ||
4164 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4165 | /** | |
d89d967f | 4166 | * i40e_netpoll - A Polling 'interrupt' handler |
41c445ff JB |
4167 | * @netdev: network interface device structure |
4168 | * | |
4169 | * This is used by netconsole to send skbs without having to re-enable | |
4170 | * interrupts. It's not called while the normal interrupt routine is executing. | |
4171 | **/ | |
4172 | static void i40e_netpoll(struct net_device *netdev) | |
4173 | { | |
4174 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
4175 | struct i40e_vsi *vsi = np->vsi; | |
4176 | struct i40e_pf *pf = vsi->back; | |
4177 | int i; | |
4178 | ||
4179 | /* if interface is down do nothing */ | |
0da36b97 | 4180 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
4181 | return; |
4182 | ||
41c445ff JB |
4183 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
4184 | for (i = 0; i < vsi->num_q_vectors; i++) | |
493fb300 | 4185 | i40e_msix_clean_rings(0, vsi->q_vectors[i]); |
41c445ff JB |
4186 | } else { |
4187 | i40e_intr(pf->pdev->irq, netdev); | |
4188 | } | |
41c445ff JB |
4189 | } |
4190 | #endif | |
4191 | ||
c768e490 JK |
4192 | #define I40E_QTX_ENA_WAIT_COUNT 50 |
4193 | ||
23527308 NP |
4194 | /** |
4195 | * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled | |
4196 | * @pf: the PF being configured | |
4197 | * @pf_q: the PF queue | |
4198 | * @enable: enable or disable state of the queue | |
4199 | * | |
4200 | * This routine will wait for the given Tx queue of the PF to reach the | |
4201 | * enabled or disabled state. | |
4202 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4203 | * multiple retries; else will return 0 in case of success. | |
4204 | **/ | |
4205 | static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4206 | { | |
4207 | int i; | |
4208 | u32 tx_reg; | |
4209 | ||
4210 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4211 | tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); | |
4212 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4213 | break; | |
4214 | ||
f98a2006 | 4215 | usleep_range(10, 20); |
23527308 NP |
4216 | } |
4217 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4218 | return -ETIMEDOUT; | |
4219 | ||
4220 | return 0; | |
4221 | } | |
4222 | ||
c768e490 JK |
4223 | /** |
4224 | * i40e_control_tx_q - Start or stop a particular Tx queue | |
4225 | * @pf: the PF structure | |
4226 | * @pf_q: the PF queue to configure | |
4227 | * @enable: start or stop the queue | |
4228 | * | |
4229 | * This function enables or disables a single queue. Note that any delay | |
4230 | * required after the operation is expected to be handled by the caller of | |
4231 | * this function. | |
4232 | **/ | |
4233 | static void i40e_control_tx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4234 | { | |
4235 | struct i40e_hw *hw = &pf->hw; | |
4236 | u32 tx_reg; | |
4237 | int i; | |
4238 | ||
4239 | /* warn the TX unit of coming changes */ | |
4240 | i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable); | |
4241 | if (!enable) | |
4242 | usleep_range(10, 20); | |
4243 | ||
4244 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4245 | tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); | |
4246 | if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == | |
4247 | ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) | |
4248 | break; | |
4249 | usleep_range(1000, 2000); | |
4250 | } | |
4251 | ||
4252 | /* Skip if the queue is already in the requested state */ | |
4253 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4254 | return; | |
4255 | ||
4256 | /* turn on/off the queue */ | |
4257 | if (enable) { | |
4258 | wr32(hw, I40E_QTX_HEAD(pf_q), 0); | |
4259 | tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; | |
4260 | } else { | |
4261 | tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; | |
4262 | } | |
4263 | ||
4264 | wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); | |
4265 | } | |
4266 | ||
74608d17 BT |
4267 | /** |
4268 | * i40e_control_wait_tx_q - Start/stop Tx queue and wait for completion | |
4269 | * @seid: VSI SEID | |
4270 | * @pf: the PF structure | |
4271 | * @pf_q: the PF queue to configure | |
4272 | * @is_xdp: true if the queue is used for XDP | |
4273 | * @enable: start or stop the queue | |
4274 | **/ | |
4275 | static int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, | |
4276 | bool is_xdp, bool enable) | |
4277 | { | |
4278 | int ret; | |
4279 | ||
4280 | i40e_control_tx_q(pf, pf_q, enable); | |
4281 | ||
4282 | /* wait for the change to finish */ | |
4283 | ret = i40e_pf_txq_wait(pf, pf_q, enable); | |
4284 | if (ret) { | |
4285 | dev_info(&pf->pdev->dev, | |
4286 | "VSI seid %d %sTx ring %d %sable timeout\n", | |
4287 | seid, (is_xdp ? "XDP " : ""), pf_q, | |
4288 | (enable ? "en" : "dis")); | |
4289 | } | |
4290 | ||
4291 | return ret; | |
4292 | } | |
4293 | ||
41c445ff JB |
4294 | /** |
4295 | * i40e_vsi_control_tx - Start or stop a VSI's rings | |
4296 | * @vsi: the VSI being configured | |
4297 | * @enable: start or stop the rings | |
4298 | **/ | |
4299 | static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) | |
4300 | { | |
4301 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4302 | int i, pf_q, ret = 0; |
41c445ff JB |
4303 | |
4304 | pf_q = vsi->base_queue; | |
4305 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
74608d17 BT |
4306 | ret = i40e_control_wait_tx_q(vsi->seid, pf, |
4307 | pf_q, | |
4308 | false /*is xdp*/, enable); | |
4309 | if (ret) | |
4310 | break; | |
351499ab | 4311 | |
74608d17 BT |
4312 | if (!i40e_enabled_xdp_vsi(vsi)) |
4313 | continue; | |
4314 | ||
4315 | ret = i40e_control_wait_tx_q(vsi->seid, pf, | |
4316 | pf_q + vsi->alloc_queue_pairs, | |
4317 | true /*is xdp*/, enable); | |
4318 | if (ret) | |
23527308 | 4319 | break; |
41c445ff JB |
4320 | } |
4321 | ||
23527308 NP |
4322 | return ret; |
4323 | } | |
4324 | ||
4325 | /** | |
4326 | * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled | |
4327 | * @pf: the PF being configured | |
4328 | * @pf_q: the PF queue | |
4329 | * @enable: enable or disable state of the queue | |
4330 | * | |
4331 | * This routine will wait for the given Rx queue of the PF to reach the | |
4332 | * enabled or disabled state. | |
4333 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4334 | * multiple retries; else will return 0 in case of success. | |
4335 | **/ | |
4336 | static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4337 | { | |
4338 | int i; | |
4339 | u32 rx_reg; | |
4340 | ||
4341 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4342 | rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); | |
4343 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4344 | break; | |
4345 | ||
f98a2006 | 4346 | usleep_range(10, 20); |
23527308 NP |
4347 | } |
4348 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4349 | return -ETIMEDOUT; | |
7134f9ce | 4350 | |
41c445ff JB |
4351 | return 0; |
4352 | } | |
4353 | ||
c768e490 JK |
4354 | /** |
4355 | * i40e_control_rx_q - Start or stop a particular Rx queue | |
4356 | * @pf: the PF structure | |
4357 | * @pf_q: the PF queue to configure | |
4358 | * @enable: start or stop the queue | |
4359 | * | |
4360 | * This function enables or disables a single queue. Note that any delay | |
4361 | * required after the operation is expected to be handled by the caller of | |
4362 | * this function. | |
4363 | **/ | |
4364 | static void i40e_control_rx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4365 | { | |
4366 | struct i40e_hw *hw = &pf->hw; | |
4367 | u32 rx_reg; | |
4368 | int i; | |
4369 | ||
4370 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4371 | rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); | |
4372 | if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == | |
4373 | ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) | |
4374 | break; | |
4375 | usleep_range(1000, 2000); | |
4376 | } | |
4377 | ||
4378 | /* Skip if the queue is already in the requested state */ | |
4379 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4380 | return; | |
4381 | ||
4382 | /* turn on/off the queue */ | |
4383 | if (enable) | |
4384 | rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; | |
4385 | else | |
4386 | rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; | |
4387 | ||
4388 | wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); | |
4389 | } | |
4390 | ||
41c445ff JB |
4391 | /** |
4392 | * i40e_vsi_control_rx - Start or stop a VSI's rings | |
4393 | * @vsi: the VSI being configured | |
4394 | * @enable: start or stop the rings | |
4395 | **/ | |
4396 | static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) | |
4397 | { | |
4398 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4399 | int i, pf_q, ret = 0; |
41c445ff JB |
4400 | |
4401 | pf_q = vsi->base_queue; | |
4402 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
c768e490 | 4403 | i40e_control_rx_q(pf, pf_q, enable); |
41c445ff | 4404 | |
41c445ff | 4405 | /* wait for the change to finish */ |
23527308 NP |
4406 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); |
4407 | if (ret) { | |
4408 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4409 | "VSI seid %d Rx ring %d %sable timeout\n", |
4410 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
23527308 | 4411 | break; |
41c445ff JB |
4412 | } |
4413 | } | |
4414 | ||
d08a9f6c WC |
4415 | /* Due to HW errata, on Rx disable only, the register can indicate done |
4416 | * before it really is. Needs 50ms to be sure | |
4417 | */ | |
4418 | if (!enable) | |
4419 | mdelay(50); | |
4420 | ||
23527308 | 4421 | return ret; |
41c445ff JB |
4422 | } |
4423 | ||
4424 | /** | |
3aa7b74d | 4425 | * i40e_vsi_start_rings - Start a VSI's rings |
41c445ff | 4426 | * @vsi: the VSI being configured |
41c445ff | 4427 | **/ |
3aa7b74d | 4428 | int i40e_vsi_start_rings(struct i40e_vsi *vsi) |
41c445ff | 4429 | { |
3b867b28 | 4430 | int ret = 0; |
41c445ff JB |
4431 | |
4432 | /* do rx first for enable and last for disable */ | |
3aa7b74d FS |
4433 | ret = i40e_vsi_control_rx(vsi, true); |
4434 | if (ret) | |
4435 | return ret; | |
4436 | ret = i40e_vsi_control_tx(vsi, true); | |
41c445ff JB |
4437 | |
4438 | return ret; | |
4439 | } | |
4440 | ||
3aa7b74d FS |
4441 | /** |
4442 | * i40e_vsi_stop_rings - Stop a VSI's rings | |
4443 | * @vsi: the VSI being configured | |
4444 | **/ | |
4445 | void i40e_vsi_stop_rings(struct i40e_vsi *vsi) | |
4446 | { | |
3480756f | 4447 | /* When port TX is suspended, don't wait */ |
0da36b97 | 4448 | if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state)) |
3480756f JK |
4449 | return i40e_vsi_stop_rings_no_wait(vsi); |
4450 | ||
3aa7b74d FS |
4451 | /* do rx first for enable and last for disable |
4452 | * Ignore return value, we need to shutdown whatever we can | |
4453 | */ | |
4454 | i40e_vsi_control_tx(vsi, false); | |
4455 | i40e_vsi_control_rx(vsi, false); | |
4456 | } | |
4457 | ||
e4b433f4 JK |
4458 | /** |
4459 | * i40e_vsi_stop_rings_no_wait - Stop a VSI's rings and do not delay | |
4460 | * @vsi: the VSI being shutdown | |
4461 | * | |
4462 | * This function stops all the rings for a VSI but does not delay to verify | |
4463 | * that rings have been disabled. It is expected that the caller is shutting | |
4464 | * down multiple VSIs at once and will delay together for all the VSIs after | |
4465 | * initiating the shutdown. This is particularly useful for shutting down lots | |
4466 | * of VFs together. Otherwise, a large delay can be incurred while configuring | |
4467 | * each VSI in serial. | |
4468 | **/ | |
4469 | void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi) | |
4470 | { | |
4471 | struct i40e_pf *pf = vsi->back; | |
4472 | int i, pf_q; | |
4473 | ||
4474 | pf_q = vsi->base_queue; | |
4475 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4476 | i40e_control_tx_q(pf, pf_q, false); | |
4477 | i40e_control_rx_q(pf, pf_q, false); | |
4478 | } | |
4479 | } | |
4480 | ||
41c445ff JB |
4481 | /** |
4482 | * i40e_vsi_free_irq - Free the irq association with the OS | |
4483 | * @vsi: the VSI being configured | |
4484 | **/ | |
4485 | static void i40e_vsi_free_irq(struct i40e_vsi *vsi) | |
4486 | { | |
4487 | struct i40e_pf *pf = vsi->back; | |
4488 | struct i40e_hw *hw = &pf->hw; | |
4489 | int base = vsi->base_vector; | |
4490 | u32 val, qp; | |
4491 | int i; | |
4492 | ||
4493 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4494 | if (!vsi->q_vectors) | |
4495 | return; | |
4496 | ||
63741846 SN |
4497 | if (!vsi->irqs_ready) |
4498 | return; | |
4499 | ||
4500 | vsi->irqs_ready = false; | |
41c445ff | 4501 | for (i = 0; i < vsi->num_q_vectors; i++) { |
96db776a AB |
4502 | int irq_num; |
4503 | u16 vector; | |
4504 | ||
4505 | vector = i + base; | |
4506 | irq_num = pf->msix_entries[vector].vector; | |
41c445ff JB |
4507 | |
4508 | /* free only the irqs that were actually requested */ | |
78681b1f SN |
4509 | if (!vsi->q_vectors[i] || |
4510 | !vsi->q_vectors[i]->num_ringpairs) | |
41c445ff JB |
4511 | continue; |
4512 | ||
96db776a AB |
4513 | /* clear the affinity notifier in the IRQ descriptor */ |
4514 | irq_set_affinity_notifier(irq_num, NULL); | |
759dc4a7 | 4515 | /* remove our suggested affinity mask for this IRQ */ |
96db776a AB |
4516 | irq_set_affinity_hint(irq_num, NULL); |
4517 | synchronize_irq(irq_num); | |
4518 | free_irq(irq_num, vsi->q_vectors[i]); | |
41c445ff JB |
4519 | |
4520 | /* Tear down the interrupt queue link list | |
4521 | * | |
4522 | * We know that they come in pairs and always | |
4523 | * the Rx first, then the Tx. To clear the | |
4524 | * link list, stick the EOL value into the | |
4525 | * next_q field of the registers. | |
4526 | */ | |
4527 | val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); | |
4528 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4529 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4530 | val |= I40E_QUEUE_END_OF_LIST | |
4531 | << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4532 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); | |
4533 | ||
4534 | while (qp != I40E_QUEUE_END_OF_LIST) { | |
4535 | u32 next; | |
4536 | ||
4537 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4538 | ||
4539 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4540 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4541 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4542 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4543 | ||
4544 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4545 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4546 | ||
4547 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4548 | ||
4549 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4550 | ||
4551 | next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) | |
4552 | >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; | |
4553 | ||
4554 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4555 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4556 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4557 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4558 | ||
4559 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4560 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4561 | ||
4562 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4563 | qp = next; | |
4564 | } | |
4565 | } | |
4566 | } else { | |
4567 | free_irq(pf->pdev->irq, pf); | |
4568 | ||
4569 | val = rd32(hw, I40E_PFINT_LNKLST0); | |
4570 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4571 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4572 | val |= I40E_QUEUE_END_OF_LIST | |
4573 | << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
4574 | wr32(hw, I40E_PFINT_LNKLST0, val); | |
4575 | ||
4576 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4577 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4578 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4579 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4580 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4581 | ||
4582 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4583 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4584 | ||
4585 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4586 | ||
4587 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4588 | ||
4589 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4590 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4591 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4592 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4593 | ||
4594 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4595 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4596 | ||
4597 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4598 | } | |
4599 | } | |
4600 | ||
493fb300 AD |
4601 | /** |
4602 | * i40e_free_q_vector - Free memory allocated for specific interrupt vector | |
4603 | * @vsi: the VSI being configured | |
4604 | * @v_idx: Index of vector to be freed | |
4605 | * | |
4606 | * This function frees the memory allocated to the q_vector. In addition if | |
4607 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4608 | * to freeing the q_vector. | |
4609 | **/ | |
4610 | static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx) | |
4611 | { | |
4612 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; | |
cd0b6fa6 | 4613 | struct i40e_ring *ring; |
493fb300 AD |
4614 | |
4615 | if (!q_vector) | |
4616 | return; | |
4617 | ||
4618 | /* disassociate q_vector from rings */ | |
cd0b6fa6 AD |
4619 | i40e_for_each_ring(ring, q_vector->tx) |
4620 | ring->q_vector = NULL; | |
4621 | ||
4622 | i40e_for_each_ring(ring, q_vector->rx) | |
4623 | ring->q_vector = NULL; | |
493fb300 AD |
4624 | |
4625 | /* only VSI w/ an associated netdev is set up w/ NAPI */ | |
4626 | if (vsi->netdev) | |
4627 | netif_napi_del(&q_vector->napi); | |
4628 | ||
4629 | vsi->q_vectors[v_idx] = NULL; | |
4630 | ||
4631 | kfree_rcu(q_vector, rcu); | |
4632 | } | |
4633 | ||
41c445ff JB |
4634 | /** |
4635 | * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors | |
4636 | * @vsi: the VSI being un-configured | |
4637 | * | |
4638 | * This frees the memory allocated to the q_vectors and | |
4639 | * deletes references to the NAPI struct. | |
4640 | **/ | |
4641 | static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi) | |
4642 | { | |
4643 | int v_idx; | |
4644 | ||
493fb300 AD |
4645 | for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) |
4646 | i40e_free_q_vector(vsi, v_idx); | |
41c445ff JB |
4647 | } |
4648 | ||
4649 | /** | |
4650 | * i40e_reset_interrupt_capability - Disable interrupt setup in OS | |
4651 | * @pf: board private structure | |
4652 | **/ | |
4653 | static void i40e_reset_interrupt_capability(struct i40e_pf *pf) | |
4654 | { | |
4655 | /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */ | |
4656 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4657 | pci_disable_msix(pf->pdev); | |
4658 | kfree(pf->msix_entries); | |
4659 | pf->msix_entries = NULL; | |
3b444399 SN |
4660 | kfree(pf->irq_pile); |
4661 | pf->irq_pile = NULL; | |
41c445ff JB |
4662 | } else if (pf->flags & I40E_FLAG_MSI_ENABLED) { |
4663 | pci_disable_msi(pf->pdev); | |
4664 | } | |
4665 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
4666 | } | |
4667 | ||
4668 | /** | |
4669 | * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4670 | * @pf: board private structure | |
4671 | * | |
4672 | * We go through and clear interrupt specific resources and reset the structure | |
4673 | * to pre-load conditions | |
4674 | **/ | |
4675 | static void i40e_clear_interrupt_scheme(struct i40e_pf *pf) | |
4676 | { | |
4677 | int i; | |
4678 | ||
c17401a1 | 4679 | i40e_free_misc_vector(pf); |
e147758d | 4680 | |
e3219ce6 ASJ |
4681 | i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector, |
4682 | I40E_IWARP_IRQ_PILE_ID); | |
4683 | ||
41c445ff | 4684 | i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1); |
505682cd | 4685 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
4686 | if (pf->vsi[i]) |
4687 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
4688 | i40e_reset_interrupt_capability(pf); | |
4689 | } | |
4690 | ||
4691 | /** | |
4692 | * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI | |
4693 | * @vsi: the VSI being configured | |
4694 | **/ | |
4695 | static void i40e_napi_enable_all(struct i40e_vsi *vsi) | |
4696 | { | |
4697 | int q_idx; | |
4698 | ||
4699 | if (!vsi->netdev) | |
4700 | return; | |
4701 | ||
13a8cd19 AD |
4702 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4703 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4704 | ||
4705 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4706 | napi_enable(&q_vector->napi); | |
4707 | } | |
41c445ff JB |
4708 | } |
4709 | ||
4710 | /** | |
4711 | * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI | |
4712 | * @vsi: the VSI being configured | |
4713 | **/ | |
4714 | static void i40e_napi_disable_all(struct i40e_vsi *vsi) | |
4715 | { | |
4716 | int q_idx; | |
4717 | ||
4718 | if (!vsi->netdev) | |
4719 | return; | |
4720 | ||
13a8cd19 AD |
4721 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4722 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4723 | ||
4724 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4725 | napi_disable(&q_vector->napi); | |
4726 | } | |
41c445ff JB |
4727 | } |
4728 | ||
90ef8d47 SN |
4729 | /** |
4730 | * i40e_vsi_close - Shut down a VSI | |
4731 | * @vsi: the vsi to be quelled | |
4732 | **/ | |
4733 | static void i40e_vsi_close(struct i40e_vsi *vsi) | |
4734 | { | |
0ef2d5af | 4735 | struct i40e_pf *pf = vsi->back; |
0da36b97 | 4736 | if (!test_and_set_bit(__I40E_VSI_DOWN, vsi->state)) |
90ef8d47 SN |
4737 | i40e_down(vsi); |
4738 | i40e_vsi_free_irq(vsi); | |
4739 | i40e_vsi_free_tx_resources(vsi); | |
4740 | i40e_vsi_free_rx_resources(vsi); | |
92faef85 | 4741 | vsi->current_netdev_flags = 0; |
0ef2d5af | 4742 | pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED; |
0da36b97 | 4743 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
0ef2d5af | 4744 | pf->flags |= I40E_FLAG_CLIENT_RESET; |
90ef8d47 SN |
4745 | } |
4746 | ||
41c445ff JB |
4747 | /** |
4748 | * i40e_quiesce_vsi - Pause a given VSI | |
4749 | * @vsi: the VSI being paused | |
4750 | **/ | |
4751 | static void i40e_quiesce_vsi(struct i40e_vsi *vsi) | |
4752 | { | |
0da36b97 | 4753 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
4754 | return; |
4755 | ||
0da36b97 | 4756 | set_bit(__I40E_VSI_NEEDS_RESTART, vsi->state); |
6995b36c | 4757 | if (vsi->netdev && netif_running(vsi->netdev)) |
41c445ff | 4758 | vsi->netdev->netdev_ops->ndo_stop(vsi->netdev); |
6995b36c | 4759 | else |
90ef8d47 | 4760 | i40e_vsi_close(vsi); |
41c445ff JB |
4761 | } |
4762 | ||
4763 | /** | |
4764 | * i40e_unquiesce_vsi - Resume a given VSI | |
4765 | * @vsi: the VSI being resumed | |
4766 | **/ | |
4767 | static void i40e_unquiesce_vsi(struct i40e_vsi *vsi) | |
4768 | { | |
0da36b97 | 4769 | if (!test_and_clear_bit(__I40E_VSI_NEEDS_RESTART, vsi->state)) |
41c445ff JB |
4770 | return; |
4771 | ||
41c445ff JB |
4772 | if (vsi->netdev && netif_running(vsi->netdev)) |
4773 | vsi->netdev->netdev_ops->ndo_open(vsi->netdev); | |
4774 | else | |
8276f757 | 4775 | i40e_vsi_open(vsi); /* this clears the DOWN bit */ |
41c445ff JB |
4776 | } |
4777 | ||
4778 | /** | |
4779 | * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF | |
4780 | * @pf: the PF | |
4781 | **/ | |
4782 | static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf) | |
4783 | { | |
4784 | int v; | |
4785 | ||
505682cd | 4786 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4787 | if (pf->vsi[v]) |
4788 | i40e_quiesce_vsi(pf->vsi[v]); | |
4789 | } | |
4790 | } | |
4791 | ||
4792 | /** | |
4793 | * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF | |
4794 | * @pf: the PF | |
4795 | **/ | |
4796 | static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) | |
4797 | { | |
4798 | int v; | |
4799 | ||
505682cd | 4800 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4801 | if (pf->vsi[v]) |
4802 | i40e_unquiesce_vsi(pf->vsi[v]); | |
4803 | } | |
4804 | } | |
4805 | ||
69129dc3 | 4806 | /** |
3fe06f41 | 4807 | * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled |
69129dc3 NP |
4808 | * @vsi: the VSI being configured |
4809 | * | |
af26ce2d | 4810 | * Wait until all queues on a given VSI have been disabled. |
69129dc3 | 4811 | **/ |
e4b433f4 | 4812 | int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi) |
69129dc3 NP |
4813 | { |
4814 | struct i40e_pf *pf = vsi->back; | |
4815 | int i, pf_q, ret; | |
4816 | ||
4817 | pf_q = vsi->base_queue; | |
4818 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
af26ce2d | 4819 | /* Check and wait for the Tx queue */ |
69129dc3 NP |
4820 | ret = i40e_pf_txq_wait(pf, pf_q, false); |
4821 | if (ret) { | |
4822 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4823 | "VSI seid %d Tx ring %d disable timeout\n", |
4824 | vsi->seid, pf_q); | |
69129dc3 NP |
4825 | return ret; |
4826 | } | |
74608d17 BT |
4827 | |
4828 | if (!i40e_enabled_xdp_vsi(vsi)) | |
4829 | goto wait_rx; | |
4830 | ||
4831 | /* Check and wait for the XDP Tx queue */ | |
4832 | ret = i40e_pf_txq_wait(pf, pf_q + vsi->alloc_queue_pairs, | |
4833 | false); | |
4834 | if (ret) { | |
4835 | dev_info(&pf->pdev->dev, | |
4836 | "VSI seid %d XDP Tx ring %d disable timeout\n", | |
4837 | vsi->seid, pf_q); | |
4838 | return ret; | |
4839 | } | |
4840 | wait_rx: | |
4841 | /* Check and wait for the Rx queue */ | |
3fe06f41 NP |
4842 | ret = i40e_pf_rxq_wait(pf, pf_q, false); |
4843 | if (ret) { | |
4844 | dev_info(&pf->pdev->dev, | |
4845 | "VSI seid %d Rx ring %d disable timeout\n", | |
4846 | vsi->seid, pf_q); | |
4847 | return ret; | |
4848 | } | |
4849 | } | |
4850 | ||
69129dc3 NP |
4851 | return 0; |
4852 | } | |
4853 | ||
e4b433f4 | 4854 | #ifdef CONFIG_I40E_DCB |
69129dc3 | 4855 | /** |
3fe06f41 | 4856 | * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled |
69129dc3 NP |
4857 | * @pf: the PF |
4858 | * | |
3fe06f41 | 4859 | * This function waits for the queues to be in disabled state for all the |
69129dc3 NP |
4860 | * VSIs that are managed by this PF. |
4861 | **/ | |
3fe06f41 | 4862 | static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf) |
69129dc3 NP |
4863 | { |
4864 | int v, ret = 0; | |
4865 | ||
4866 | for (v = 0; v < pf->hw.func_caps.num_vsis; v++) { | |
c76cb6ed | 4867 | if (pf->vsi[v]) { |
3fe06f41 | 4868 | ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]); |
69129dc3 NP |
4869 | if (ret) |
4870 | break; | |
4871 | } | |
4872 | } | |
4873 | ||
4874 | return ret; | |
4875 | } | |
4876 | ||
4877 | #endif | |
b03a8c1f KP |
4878 | |
4879 | /** | |
4880 | * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue | |
4881 | * @q_idx: TX queue number | |
4882 | * @vsi: Pointer to VSI struct | |
4883 | * | |
4884 | * This function checks specified queue for given VSI. Detects hung condition. | |
17daabb5 AB |
4885 | * We proactively detect hung TX queues by checking if interrupts are disabled |
4886 | * but there are pending descriptors. If it appears hung, attempt to recover | |
4887 | * by triggering a SW interrupt. | |
b03a8c1f KP |
4888 | **/ |
4889 | static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi) | |
4890 | { | |
4891 | struct i40e_ring *tx_ring = NULL; | |
4892 | struct i40e_pf *pf; | |
17daabb5 | 4893 | u32 val, tx_pending; |
b03a8c1f KP |
4894 | int i; |
4895 | ||
4896 | pf = vsi->back; | |
4897 | ||
4898 | /* now that we have an index, find the tx_ring struct */ | |
4899 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
4900 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
4901 | if (q_idx == vsi->tx_rings[i]->queue_index) { | |
4902 | tx_ring = vsi->tx_rings[i]; | |
4903 | break; | |
4904 | } | |
4905 | } | |
4906 | } | |
4907 | ||
4908 | if (!tx_ring) | |
4909 | return; | |
4910 | ||
4911 | /* Read interrupt register */ | |
4912 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
4913 | val = rd32(&pf->hw, | |
4914 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
4915 | tx_ring->vsi->base_vector - 1)); | |
4916 | else | |
4917 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
4918 | ||
17daabb5 | 4919 | tx_pending = i40e_get_tx_pending(tx_ring); |
b03a8c1f | 4920 | |
17daabb5 AB |
4921 | /* Interrupts are disabled and TX pending is non-zero, |
4922 | * trigger the SW interrupt (don't wait). Worst case | |
4923 | * there will be one extra interrupt which may result | |
4924 | * into not cleaning any queues because queues are cleaned. | |
b03a8c1f | 4925 | */ |
17daabb5 AB |
4926 | if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) |
4927 | i40e_force_wb(vsi, tx_ring->q_vector); | |
b03a8c1f KP |
4928 | } |
4929 | ||
4930 | /** | |
4931 | * i40e_detect_recover_hung - Function to detect and recover hung_queues | |
4932 | * @pf: pointer to PF struct | |
4933 | * | |
4934 | * LAN VSI has netdev and netdev has TX queues. This function is to check | |
4935 | * each of those TX queues if they are hung, trigger recovery by issuing | |
4936 | * SW interrupt. | |
4937 | **/ | |
4938 | static void i40e_detect_recover_hung(struct i40e_pf *pf) | |
4939 | { | |
4940 | struct net_device *netdev; | |
4941 | struct i40e_vsi *vsi; | |
b85c94b6 | 4942 | unsigned int i; |
b03a8c1f KP |
4943 | |
4944 | /* Only for LAN VSI */ | |
4945 | vsi = pf->vsi[pf->lan_vsi]; | |
4946 | ||
4947 | if (!vsi) | |
4948 | return; | |
4949 | ||
4950 | /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */ | |
0da36b97 JK |
4951 | if (test_bit(__I40E_VSI_DOWN, vsi->back->state) || |
4952 | test_bit(__I40E_RESET_RECOVERY_PENDING, vsi->back->state)) | |
b03a8c1f KP |
4953 | return; |
4954 | ||
4955 | /* Make sure type is MAIN VSI */ | |
4956 | if (vsi->type != I40E_VSI_MAIN) | |
4957 | return; | |
4958 | ||
4959 | netdev = vsi->netdev; | |
4960 | if (!netdev) | |
4961 | return; | |
4962 | ||
4963 | /* Bail out if netif_carrier is not OK */ | |
4964 | if (!netif_carrier_ok(netdev)) | |
4965 | return; | |
4966 | ||
4967 | /* Go thru' TX queues for netdev */ | |
4968 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
4969 | struct netdev_queue *q; | |
4970 | ||
4971 | q = netdev_get_tx_queue(netdev, i); | |
4972 | if (q) | |
4973 | i40e_detect_recover_hung_queue(i, vsi); | |
4974 | } | |
4975 | } | |
4976 | ||
63d7e5a4 NP |
4977 | /** |
4978 | * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP | |
b40c82e6 | 4979 | * @pf: pointer to PF |
63d7e5a4 NP |
4980 | * |
4981 | * Get TC map for ISCSI PF type that will include iSCSI TC | |
4982 | * and LAN TC. | |
4983 | **/ | |
4984 | static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf) | |
4985 | { | |
4986 | struct i40e_dcb_app_priority_table app; | |
4987 | struct i40e_hw *hw = &pf->hw; | |
4988 | u8 enabled_tc = 1; /* TC0 is always enabled */ | |
4989 | u8 tc, i; | |
4990 | /* Get the iSCSI APP TLV */ | |
4991 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4992 | ||
4993 | for (i = 0; i < dcbcfg->numapps; i++) { | |
4994 | app = dcbcfg->app[i]; | |
4995 | if (app.selector == I40E_APP_SEL_TCPIP && | |
4996 | app.protocolid == I40E_APP_PROTOID_ISCSI) { | |
4997 | tc = dcbcfg->etscfg.prioritytable[app.priority]; | |
75f5cea9 | 4998 | enabled_tc |= BIT(tc); |
63d7e5a4 NP |
4999 | break; |
5000 | } | |
5001 | } | |
5002 | ||
5003 | return enabled_tc; | |
5004 | } | |
5005 | ||
41c445ff JB |
5006 | /** |
5007 | * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config | |
5008 | * @dcbcfg: the corresponding DCBx configuration structure | |
5009 | * | |
5010 | * Return the number of TCs from given DCBx configuration | |
5011 | **/ | |
5012 | static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) | |
5013 | { | |
fbfe12c6 | 5014 | int i, tc_unused = 0; |
078b5876 | 5015 | u8 num_tc = 0; |
fbfe12c6 | 5016 | u8 ret = 0; |
41c445ff JB |
5017 | |
5018 | /* Scan the ETS Config Priority Table to find | |
5019 | * traffic class enabled for a given priority | |
fbfe12c6 | 5020 | * and create a bitmask of enabled TCs |
41c445ff | 5021 | */ |
fbfe12c6 DE |
5022 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) |
5023 | num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]); | |
41c445ff | 5024 | |
fbfe12c6 DE |
5025 | /* Now scan the bitmask to check for |
5026 | * contiguous TCs starting with TC0 | |
41c445ff | 5027 | */ |
fbfe12c6 DE |
5028 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
5029 | if (num_tc & BIT(i)) { | |
5030 | if (!tc_unused) { | |
5031 | ret++; | |
5032 | } else { | |
5033 | pr_err("Non-contiguous TC - Disabling DCB\n"); | |
5034 | return 1; | |
5035 | } | |
5036 | } else { | |
5037 | tc_unused = 1; | |
5038 | } | |
5039 | } | |
5040 | ||
5041 | /* There is always at least TC0 */ | |
5042 | if (!ret) | |
5043 | ret = 1; | |
5044 | ||
5045 | return ret; | |
41c445ff JB |
5046 | } |
5047 | ||
5048 | /** | |
5049 | * i40e_dcb_get_enabled_tc - Get enabled traffic classes | |
5050 | * @dcbcfg: the corresponding DCBx configuration structure | |
5051 | * | |
5052 | * Query the current DCB configuration and return the number of | |
5053 | * traffic classes enabled from the given DCBX config | |
5054 | **/ | |
5055 | static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg) | |
5056 | { | |
5057 | u8 num_tc = i40e_dcb_get_num_tc(dcbcfg); | |
5058 | u8 enabled_tc = 1; | |
5059 | u8 i; | |
5060 | ||
5061 | for (i = 0; i < num_tc; i++) | |
41a1d04b | 5062 | enabled_tc |= BIT(i); |
41c445ff JB |
5063 | |
5064 | return enabled_tc; | |
5065 | } | |
5066 | ||
a9ce82f7 AN |
5067 | /** |
5068 | * i40e_mqprio_get_enabled_tc - Get enabled traffic classes | |
5069 | * @pf: PF being queried | |
5070 | * | |
5071 | * Query the current MQPRIO configuration and return the number of | |
5072 | * traffic classes enabled. | |
5073 | **/ | |
5074 | static u8 i40e_mqprio_get_enabled_tc(struct i40e_pf *pf) | |
5075 | { | |
5076 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
5077 | u8 num_tc = vsi->mqprio_qopt.qopt.num_tc; | |
5078 | u8 enabled_tc = 1, i; | |
5079 | ||
5080 | for (i = 1; i < num_tc; i++) | |
5081 | enabled_tc |= BIT(i); | |
5082 | return enabled_tc; | |
5083 | } | |
5084 | ||
41c445ff JB |
5085 | /** |
5086 | * i40e_pf_get_num_tc - Get enabled traffic classes for PF | |
5087 | * @pf: PF being queried | |
5088 | * | |
5089 | * Return number of traffic classes enabled for the given PF | |
5090 | **/ | |
5091 | static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) | |
5092 | { | |
5093 | struct i40e_hw *hw = &pf->hw; | |
52a08caa | 5094 | u8 i, enabled_tc = 1; |
41c445ff JB |
5095 | u8 num_tc = 0; |
5096 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5097 | ||
a9ce82f7 AN |
5098 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5099 | return pf->vsi[pf->lan_vsi]->mqprio_qopt.qopt.num_tc; | |
5100 | ||
5101 | /* If neither MQPRIO nor DCB is enabled, then always use single TC */ | |
41c445ff JB |
5102 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) |
5103 | return 1; | |
5104 | ||
63d7e5a4 NP |
5105 | /* SFP mode will be enabled for all TCs on port */ |
5106 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) | |
5107 | return i40e_dcb_get_num_tc(dcbcfg); | |
5108 | ||
41c445ff | 5109 | /* MFP mode return count of enabled TCs for this PF */ |
63d7e5a4 NP |
5110 | if (pf->hw.func_caps.iscsi) |
5111 | enabled_tc = i40e_get_iscsi_tc_map(pf); | |
5112 | else | |
fc51de96 | 5113 | return 1; /* Only TC0 */ |
41c445ff | 5114 | |
63d7e5a4 | 5115 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
75f5cea9 | 5116 | if (enabled_tc & BIT(i)) |
63d7e5a4 NP |
5117 | num_tc++; |
5118 | } | |
5119 | return num_tc; | |
41c445ff JB |
5120 | } |
5121 | ||
41c445ff JB |
5122 | /** |
5123 | * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes | |
5124 | * @pf: PF being queried | |
5125 | * | |
5126 | * Return a bitmap for enabled traffic classes for this PF. | |
5127 | **/ | |
5128 | static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) | |
5129 | { | |
a9ce82f7 AN |
5130 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5131 | return i40e_mqprio_get_enabled_tc(pf); | |
5132 | ||
5133 | /* If neither MQPRIO nor DCB is enabled for this PF then just return | |
5134 | * default TC | |
5135 | */ | |
41c445ff | 5136 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) |
ea6acb7e | 5137 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff | 5138 | |
41c445ff | 5139 | /* SFP mode we want PF to be enabled for all TCs */ |
63d7e5a4 NP |
5140 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
5141 | return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config); | |
5142 | ||
fc51de96 | 5143 | /* MFP enabled and iSCSI PF type */ |
63d7e5a4 NP |
5144 | if (pf->hw.func_caps.iscsi) |
5145 | return i40e_get_iscsi_tc_map(pf); | |
5146 | else | |
ea6acb7e | 5147 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff JB |
5148 | } |
5149 | ||
5150 | /** | |
5151 | * i40e_vsi_get_bw_info - Query VSI BW Information | |
5152 | * @vsi: the VSI being queried | |
5153 | * | |
5154 | * Returns 0 on success, negative value on failure | |
5155 | **/ | |
5156 | static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) | |
5157 | { | |
5158 | struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0}; | |
5159 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; | |
5160 | struct i40e_pf *pf = vsi->back; | |
5161 | struct i40e_hw *hw = &pf->hw; | |
f1c7e72e | 5162 | i40e_status ret; |
41c445ff | 5163 | u32 tc_bw_max; |
41c445ff JB |
5164 | int i; |
5165 | ||
5166 | /* Get the VSI level BW configuration */ | |
f1c7e72e SN |
5167 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); |
5168 | if (ret) { | |
41c445ff | 5169 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5170 | "couldn't get PF vsi bw config, err %s aq_err %s\n", |
5171 | i40e_stat_str(&pf->hw, ret), | |
5172 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 5173 | return -EINVAL; |
41c445ff JB |
5174 | } |
5175 | ||
5176 | /* Get the VSI level BW configuration per TC */ | |
f1c7e72e SN |
5177 | ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config, |
5178 | NULL); | |
5179 | if (ret) { | |
41c445ff | 5180 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5181 | "couldn't get PF vsi ets bw config, err %s aq_err %s\n", |
5182 | i40e_stat_str(&pf->hw, ret), | |
5183 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 5184 | return -EINVAL; |
41c445ff JB |
5185 | } |
5186 | ||
5187 | if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) { | |
5188 | dev_info(&pf->pdev->dev, | |
5189 | "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n", | |
5190 | bw_config.tc_valid_bits, | |
5191 | bw_ets_config.tc_valid_bits); | |
5192 | /* Still continuing */ | |
5193 | } | |
5194 | ||
5195 | vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit); | |
5196 | vsi->bw_max_quanta = bw_config.max_bw; | |
5197 | tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) | | |
5198 | (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16); | |
5199 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5200 | vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i]; | |
5201 | vsi->bw_ets_limit_credits[i] = | |
5202 | le16_to_cpu(bw_ets_config.credits[i]); | |
5203 | /* 3 bits out of 4 for each TC */ | |
5204 | vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7); | |
5205 | } | |
078b5876 | 5206 | |
dcae29be | 5207 | return 0; |
41c445ff JB |
5208 | } |
5209 | ||
5210 | /** | |
5211 | * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC | |
5212 | * @vsi: the VSI being configured | |
5213 | * @enabled_tc: TC bitmap | |
5214 | * @bw_credits: BW shared credits per TC | |
5215 | * | |
5216 | * Returns 0 on success, negative value on failure | |
5217 | **/ | |
dcae29be | 5218 | static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, |
41c445ff JB |
5219 | u8 *bw_share) |
5220 | { | |
5221 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
f1c7e72e | 5222 | i40e_status ret; |
dcae29be | 5223 | int i; |
41c445ff | 5224 | |
2027d4de | 5225 | if (vsi->back->flags & I40E_FLAG_TC_MQPRIO) |
a9ce82f7 | 5226 | return 0; |
2027d4de AN |
5227 | if (!vsi->mqprio_qopt.qopt.hw) { |
5228 | ret = i40e_set_bw_limit(vsi, vsi->seid, 0); | |
5229 | if (ret) | |
5230 | dev_info(&vsi->back->pdev->dev, | |
5231 | "Failed to reset tx rate for vsi->seid %u\n", | |
5232 | vsi->seid); | |
5233 | return ret; | |
5234 | } | |
41c445ff JB |
5235 | bw_data.tc_valid_bits = enabled_tc; |
5236 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5237 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
5238 | ||
f1c7e72e SN |
5239 | ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data, |
5240 | NULL); | |
5241 | if (ret) { | |
41c445ff | 5242 | dev_info(&vsi->back->pdev->dev, |
69bfb110 JB |
5243 | "AQ command Config VSI BW allocation per TC failed = %d\n", |
5244 | vsi->back->hw.aq.asq_last_status); | |
dcae29be | 5245 | return -EINVAL; |
41c445ff JB |
5246 | } |
5247 | ||
5248 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5249 | vsi->info.qs_handle[i] = bw_data.qs_handles[i]; | |
5250 | ||
dcae29be | 5251 | return 0; |
41c445ff JB |
5252 | } |
5253 | ||
5254 | /** | |
5255 | * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration | |
5256 | * @vsi: the VSI being configured | |
5257 | * @enabled_tc: TC map to be enabled | |
5258 | * | |
5259 | **/ | |
5260 | static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5261 | { | |
5262 | struct net_device *netdev = vsi->netdev; | |
5263 | struct i40e_pf *pf = vsi->back; | |
5264 | struct i40e_hw *hw = &pf->hw; | |
5265 | u8 netdev_tc = 0; | |
5266 | int i; | |
5267 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5268 | ||
5269 | if (!netdev) | |
5270 | return; | |
5271 | ||
5272 | if (!enabled_tc) { | |
5273 | netdev_reset_tc(netdev); | |
5274 | return; | |
5275 | } | |
5276 | ||
5277 | /* Set up actual enabled TCs on the VSI */ | |
5278 | if (netdev_set_num_tc(netdev, vsi->tc_config.numtc)) | |
5279 | return; | |
5280 | ||
5281 | /* set per TC queues for the VSI */ | |
5282 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5283 | /* Only set TC queues for enabled tcs | |
5284 | * | |
5285 | * e.g. For a VSI that has TC0 and TC3 enabled the | |
5286 | * enabled_tc bitmap would be 0x00001001; the driver | |
5287 | * will set the numtc for netdev as 2 that will be | |
5288 | * referenced by the netdev layer as TC 0 and 1. | |
5289 | */ | |
75f5cea9 | 5290 | if (vsi->tc_config.enabled_tc & BIT(i)) |
41c445ff JB |
5291 | netdev_set_tc_queue(netdev, |
5292 | vsi->tc_config.tc_info[i].netdev_tc, | |
5293 | vsi->tc_config.tc_info[i].qcount, | |
5294 | vsi->tc_config.tc_info[i].qoffset); | |
5295 | } | |
5296 | ||
a9ce82f7 AN |
5297 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5298 | return; | |
5299 | ||
41c445ff JB |
5300 | /* Assign UP2TC map for the VSI */ |
5301 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { | |
5302 | /* Get the actual TC# for the UP */ | |
5303 | u8 ets_tc = dcbcfg->etscfg.prioritytable[i]; | |
5304 | /* Get the mapped netdev TC# for the UP */ | |
5305 | netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc; | |
5306 | netdev_set_prio_tc_map(netdev, i, netdev_tc); | |
5307 | } | |
5308 | } | |
5309 | ||
5310 | /** | |
5311 | * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map | |
5312 | * @vsi: the VSI being configured | |
5313 | * @ctxt: the ctxt buffer returned from AQ VSI update param command | |
5314 | **/ | |
5315 | static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi, | |
5316 | struct i40e_vsi_context *ctxt) | |
5317 | { | |
5318 | /* copy just the sections touched not the entire info | |
5319 | * since not all sections are valid as returned by | |
5320 | * update vsi params | |
5321 | */ | |
5322 | vsi->info.mapping_flags = ctxt->info.mapping_flags; | |
5323 | memcpy(&vsi->info.queue_mapping, | |
5324 | &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping)); | |
5325 | memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping, | |
5326 | sizeof(vsi->info.tc_mapping)); | |
5327 | } | |
5328 | ||
5329 | /** | |
5330 | * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map | |
5331 | * @vsi: VSI to be configured | |
5332 | * @enabled_tc: TC bitmap | |
5333 | * | |
5334 | * This configures a particular VSI for TCs that are mapped to the | |
5335 | * given TC bitmap. It uses default bandwidth share for TCs across | |
5336 | * VSIs to configure TC for a particular VSI. | |
5337 | * | |
5338 | * NOTE: | |
5339 | * It is expected that the VSI queues have been quisced before calling | |
5340 | * this function. | |
5341 | **/ | |
5342 | static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5343 | { | |
5344 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
5345 | struct i40e_vsi_context ctxt; | |
5346 | int ret = 0; | |
5347 | int i; | |
5348 | ||
5349 | /* Check if enabled_tc is same as existing or new TCs */ | |
a9ce82f7 AN |
5350 | if (vsi->tc_config.enabled_tc == enabled_tc && |
5351 | vsi->mqprio_qopt.mode != TC_MQPRIO_MODE_CHANNEL) | |
41c445ff JB |
5352 | return ret; |
5353 | ||
5354 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
5355 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 5356 | if (enabled_tc & BIT(i)) |
41c445ff JB |
5357 | bw_share[i] = 1; |
5358 | } | |
5359 | ||
5360 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
5361 | if (ret) { | |
5362 | dev_info(&vsi->back->pdev->dev, | |
5363 | "Failed configuring TC map %d for VSI %d\n", | |
5364 | enabled_tc, vsi->seid); | |
5365 | goto out; | |
5366 | } | |
5367 | ||
5368 | /* Update Queue Pairs Mapping for currently enabled UPs */ | |
5369 | ctxt.seid = vsi->seid; | |
5370 | ctxt.pf_num = vsi->back->hw.pf_id; | |
5371 | ctxt.vf_num = 0; | |
5372 | ctxt.uplink_seid = vsi->uplink_seid; | |
1a2f6248 | 5373 | ctxt.info = vsi->info; |
a9ce82f7 AN |
5374 | if (vsi->back->flags & I40E_FLAG_TC_MQPRIO) { |
5375 | ret = i40e_vsi_setup_queue_map_mqprio(vsi, &ctxt, enabled_tc); | |
5376 | if (ret) | |
5377 | goto out; | |
5378 | } else { | |
5379 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
5380 | } | |
41c445ff | 5381 | |
a9ce82f7 AN |
5382 | /* On destroying the qdisc, reset vsi->rss_size, as number of enabled |
5383 | * queues changed. | |
5384 | */ | |
5385 | if (!vsi->mqprio_qopt.qopt.hw && vsi->reconfig_rss) { | |
5386 | vsi->rss_size = min_t(int, vsi->back->alloc_rss_size, | |
5387 | vsi->num_queue_pairs); | |
5388 | ret = i40e_vsi_config_rss(vsi); | |
5389 | if (ret) { | |
5390 | dev_info(&vsi->back->pdev->dev, | |
5391 | "Failed to reconfig rss for num_queues\n"); | |
5392 | return ret; | |
5393 | } | |
5394 | vsi->reconfig_rss = false; | |
5395 | } | |
e3219ce6 ASJ |
5396 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
5397 | ctxt.info.valid_sections |= | |
5398 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
5399 | ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA; | |
5400 | } | |
5401 | ||
a9ce82f7 AN |
5402 | /* Update the VSI after updating the VSI queue-mapping |
5403 | * information | |
5404 | */ | |
41c445ff JB |
5405 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
5406 | if (ret) { | |
5407 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
5408 | "Update vsi tc config failed, err %s aq_err %s\n", |
5409 | i40e_stat_str(&vsi->back->hw, ret), | |
5410 | i40e_aq_str(&vsi->back->hw, | |
5411 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
5412 | goto out; |
5413 | } | |
5414 | /* update the local VSI info with updated queue map */ | |
5415 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
5416 | vsi->info.valid_sections = 0; | |
5417 | ||
5418 | /* Update current VSI BW information */ | |
5419 | ret = i40e_vsi_get_bw_info(vsi); | |
5420 | if (ret) { | |
5421 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
5422 | "Failed updating vsi bw info, err %s aq_err %s\n", |
5423 | i40e_stat_str(&vsi->back->hw, ret), | |
5424 | i40e_aq_str(&vsi->back->hw, | |
5425 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
5426 | goto out; |
5427 | } | |
5428 | ||
5429 | /* Update the netdev TC setup */ | |
5430 | i40e_vsi_config_netdev_tc(vsi, enabled_tc); | |
5431 | out: | |
5432 | return ret; | |
5433 | } | |
5434 | ||
4e3b35b0 | 5435 | /** |
5ecae412 AN |
5436 | * i40e_get_link_speed - Returns link speed for the interface |
5437 | * @vsi: VSI to be configured | |
4e3b35b0 | 5438 | * |
4e3b35b0 | 5439 | **/ |
5ecae412 | 5440 | int i40e_get_link_speed(struct i40e_vsi *vsi) |
4e3b35b0 | 5441 | { |
5ecae412 | 5442 | struct i40e_pf *pf = vsi->back; |
4e3b35b0 | 5443 | |
5ecae412 AN |
5444 | switch (pf->hw.phy.link_info.link_speed) { |
5445 | case I40E_LINK_SPEED_40GB: | |
5446 | return 40000; | |
5447 | case I40E_LINK_SPEED_25GB: | |
5448 | return 25000; | |
5449 | case I40E_LINK_SPEED_20GB: | |
5450 | return 20000; | |
5451 | case I40E_LINK_SPEED_10GB: | |
5452 | return 10000; | |
5453 | case I40E_LINK_SPEED_1GB: | |
5454 | return 1000; | |
5455 | default: | |
5456 | return -EINVAL; | |
4e3b35b0 | 5457 | } |
4e3b35b0 NP |
5458 | } |
5459 | ||
4e3b35b0 | 5460 | /** |
5ecae412 AN |
5461 | * i40e_set_bw_limit - setup BW limit for Tx traffic based on max_tx_rate |
5462 | * @vsi: VSI to be configured | |
5463 | * @seid: seid of the channel/VSI | |
5464 | * @max_tx_rate: max TX rate to be configured as BW limit | |
4e3b35b0 | 5465 | * |
5ecae412 | 5466 | * Helper function to set BW limit for a given VSI |
4e3b35b0 | 5467 | **/ |
5ecae412 | 5468 | int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate) |
4e3b35b0 | 5469 | { |
5ecae412 | 5470 | struct i40e_pf *pf = vsi->back; |
6c32e0d9 | 5471 | u64 credits = 0; |
5ecae412 AN |
5472 | int speed = 0; |
5473 | int ret = 0; | |
4e3b35b0 | 5474 | |
5ecae412 AN |
5475 | speed = i40e_get_link_speed(vsi); |
5476 | if (max_tx_rate > speed) { | |
5477 | dev_err(&pf->pdev->dev, | |
5478 | "Invalid max tx rate %llu specified for VSI seid %d.", | |
5479 | max_tx_rate, seid); | |
5480 | return -EINVAL; | |
5481 | } | |
5482 | if (max_tx_rate && max_tx_rate < 50) { | |
5483 | dev_warn(&pf->pdev->dev, | |
5484 | "Setting max tx rate to minimum usable value of 50Mbps.\n"); | |
5485 | max_tx_rate = 50; | |
5486 | } | |
5487 | ||
5488 | /* Tx rate credits are in values of 50Mbps, 0 is disabled */ | |
6c32e0d9 AB |
5489 | credits = max_tx_rate; |
5490 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
5491 | ret = i40e_aq_config_vsi_bw_limit(&pf->hw, seid, credits, | |
5ecae412 AN |
5492 | I40E_MAX_BW_INACTIVE_ACCUM, NULL); |
5493 | if (ret) | |
5494 | dev_err(&pf->pdev->dev, | |
5495 | "Failed set tx rate (%llu Mbps) for vsi->seid %u, err %s aq_err %s\n", | |
5496 | max_tx_rate, seid, i40e_stat_str(&pf->hw, ret), | |
5497 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
5498 | return ret; | |
5499 | } | |
5500 | ||
8f88b303 AN |
5501 | /** |
5502 | * i40e_remove_queue_channels - Remove queue channels for the TCs | |
5503 | * @vsi: VSI to be configured | |
5504 | * | |
5505 | * Remove queue channels for the TCs | |
5506 | **/ | |
5507 | static void i40e_remove_queue_channels(struct i40e_vsi *vsi) | |
5508 | { | |
2f4b411a AN |
5509 | enum i40e_admin_queue_err last_aq_status; |
5510 | struct i40e_cloud_filter *cfilter; | |
8f88b303 | 5511 | struct i40e_channel *ch, *ch_tmp; |
2f4b411a AN |
5512 | struct i40e_pf *pf = vsi->back; |
5513 | struct hlist_node *node; | |
8f88b303 AN |
5514 | int ret, i; |
5515 | ||
5516 | /* Reset rss size that was stored when reconfiguring rss for | |
5517 | * channel VSIs with non-power-of-2 queue count. | |
5518 | */ | |
5519 | vsi->current_rss_size = 0; | |
5520 | ||
5521 | /* perform cleanup for channels if they exist */ | |
5522 | if (list_empty(&vsi->ch_list)) | |
5523 | return; | |
5524 | ||
5525 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5526 | struct i40e_vsi *p_vsi; | |
5527 | ||
5528 | list_del(&ch->list); | |
5529 | p_vsi = ch->parent_vsi; | |
5530 | if (!p_vsi || !ch->initialized) { | |
5531 | kfree(ch); | |
4e3b35b0 | 5532 | continue; |
8f88b303 AN |
5533 | } |
5534 | /* Reset queue contexts */ | |
5535 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
5536 | struct i40e_ring *tx_ring, *rx_ring; | |
5537 | u16 pf_q; | |
5538 | ||
5539 | pf_q = ch->base_queue + i; | |
5540 | tx_ring = vsi->tx_rings[pf_q]; | |
5541 | tx_ring->ch = NULL; | |
5542 | ||
5543 | rx_ring = vsi->rx_rings[pf_q]; | |
5544 | rx_ring->ch = NULL; | |
5545 | } | |
5546 | ||
2027d4de AN |
5547 | /* Reset BW configured for this VSI via mqprio */ |
5548 | ret = i40e_set_bw_limit(vsi, ch->seid, 0); | |
5549 | if (ret) | |
5550 | dev_info(&vsi->back->pdev->dev, | |
5551 | "Failed to reset tx rate for ch->seid %u\n", | |
5552 | ch->seid); | |
5553 | ||
2f4b411a AN |
5554 | /* delete cloud filters associated with this channel */ |
5555 | hlist_for_each_entry_safe(cfilter, node, | |
5556 | &pf->cloud_filter_list, cloud_node) { | |
5557 | if (cfilter->seid != ch->seid) | |
5558 | continue; | |
5559 | ||
5560 | hash_del(&cfilter->cloud_node); | |
5561 | if (cfilter->dst_port) | |
5562 | ret = i40e_add_del_cloud_filter_big_buf(vsi, | |
5563 | cfilter, | |
5564 | false); | |
5565 | else | |
5566 | ret = i40e_add_del_cloud_filter(vsi, cfilter, | |
5567 | false); | |
5568 | last_aq_status = pf->hw.aq.asq_last_status; | |
5569 | if (ret) | |
5570 | dev_info(&pf->pdev->dev, | |
5571 | "Failed to delete cloud filter, err %s aq_err %s\n", | |
5572 | i40e_stat_str(&pf->hw, ret), | |
5573 | i40e_aq_str(&pf->hw, last_aq_status)); | |
5574 | kfree(cfilter); | |
5575 | } | |
5576 | ||
8f88b303 AN |
5577 | /* delete VSI from FW */ |
5578 | ret = i40e_aq_delete_element(&vsi->back->hw, ch->seid, | |
5579 | NULL); | |
5580 | if (ret) | |
5581 | dev_err(&vsi->back->pdev->dev, | |
5582 | "unable to remove channel (%d) for parent VSI(%d)\n", | |
5583 | ch->seid, p_vsi->seid); | |
5584 | kfree(ch); | |
5585 | } | |
5586 | INIT_LIST_HEAD(&vsi->ch_list); | |
5587 | } | |
5588 | ||
5589 | /** | |
5590 | * i40e_is_any_channel - channel exist or not | |
5591 | * @vsi: ptr to VSI to which channels are associated with | |
5592 | * | |
5593 | * Returns true or false if channel(s) exist for associated VSI or not | |
5594 | **/ | |
5595 | static bool i40e_is_any_channel(struct i40e_vsi *vsi) | |
5596 | { | |
5597 | struct i40e_channel *ch, *ch_tmp; | |
5598 | ||
5599 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5600 | if (ch->initialized) | |
5601 | return true; | |
5602 | } | |
5603 | ||
5604 | return false; | |
5605 | } | |
5606 | ||
5607 | /** | |
5608 | * i40e_get_max_queues_for_channel | |
5609 | * @vsi: ptr to VSI to which channels are associated with | |
5610 | * | |
5611 | * Helper function which returns max value among the queue counts set on the | |
5612 | * channels/TCs created. | |
5613 | **/ | |
5614 | static int i40e_get_max_queues_for_channel(struct i40e_vsi *vsi) | |
5615 | { | |
5616 | struct i40e_channel *ch, *ch_tmp; | |
5617 | int max = 0; | |
5618 | ||
5619 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5620 | if (!ch->initialized) | |
5621 | continue; | |
5622 | if (ch->num_queue_pairs > max) | |
5623 | max = ch->num_queue_pairs; | |
5624 | } | |
5625 | ||
5626 | return max; | |
5627 | } | |
5628 | ||
5629 | /** | |
5630 | * i40e_validate_num_queues - validate num_queues w.r.t channel | |
5631 | * @pf: ptr to PF device | |
5632 | * @num_queues: number of queues | |
5633 | * @vsi: the parent VSI | |
5634 | * @reconfig_rss: indicates should the RSS be reconfigured or not | |
5635 | * | |
5636 | * This function validates number of queues in the context of new channel | |
5637 | * which is being established and determines if RSS should be reconfigured | |
5638 | * or not for parent VSI. | |
5639 | **/ | |
5640 | static int i40e_validate_num_queues(struct i40e_pf *pf, int num_queues, | |
5641 | struct i40e_vsi *vsi, bool *reconfig_rss) | |
5642 | { | |
5643 | int max_ch_queues; | |
5644 | ||
5645 | if (!reconfig_rss) | |
5646 | return -EINVAL; | |
5647 | ||
5648 | *reconfig_rss = false; | |
8f88b303 AN |
5649 | if (vsi->current_rss_size) { |
5650 | if (num_queues > vsi->current_rss_size) { | |
5651 | dev_dbg(&pf->pdev->dev, | |
5652 | "Error: num_queues (%d) > vsi's current_size(%d)\n", | |
5653 | num_queues, vsi->current_rss_size); | |
5654 | return -EINVAL; | |
5655 | } else if ((num_queues < vsi->current_rss_size) && | |
5656 | (!is_power_of_2(num_queues))) { | |
5657 | dev_dbg(&pf->pdev->dev, | |
5658 | "Error: num_queues (%d) < vsi's current_size(%d), but not power of 2\n", | |
5659 | num_queues, vsi->current_rss_size); | |
5660 | return -EINVAL; | |
5661 | } | |
5662 | } | |
5663 | ||
5664 | if (!is_power_of_2(num_queues)) { | |
5665 | /* Find the max num_queues configured for channel if channel | |
5666 | * exist. | |
5667 | * if channel exist, then enforce 'num_queues' to be more than | |
5668 | * max ever queues configured for channel. | |
5669 | */ | |
5670 | max_ch_queues = i40e_get_max_queues_for_channel(vsi); | |
5671 | if (num_queues < max_ch_queues) { | |
5672 | dev_dbg(&pf->pdev->dev, | |
5673 | "Error: num_queues (%d) < max queues configured for channel(%d)\n", | |
5674 | num_queues, max_ch_queues); | |
5675 | return -EINVAL; | |
5676 | } | |
5677 | *reconfig_rss = true; | |
5678 | } | |
5679 | ||
5680 | return 0; | |
5681 | } | |
5682 | ||
5683 | /** | |
5684 | * i40e_vsi_reconfig_rss - reconfig RSS based on specified rss_size | |
5685 | * @vsi: the VSI being setup | |
5686 | * @rss_size: size of RSS, accordingly LUT gets reprogrammed | |
5687 | * | |
5688 | * This function reconfigures RSS by reprogramming LUTs using 'rss_size' | |
5689 | **/ | |
5690 | static int i40e_vsi_reconfig_rss(struct i40e_vsi *vsi, u16 rss_size) | |
5691 | { | |
5692 | struct i40e_pf *pf = vsi->back; | |
5693 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
5694 | struct i40e_hw *hw = &pf->hw; | |
5695 | int local_rss_size; | |
5696 | u8 *lut; | |
5697 | int ret; | |
5698 | ||
5699 | if (!vsi->rss_size) | |
5700 | return -EINVAL; | |
5701 | ||
5702 | if (rss_size > vsi->rss_size) | |
5703 | return -EINVAL; | |
5704 | ||
5705 | local_rss_size = min_t(int, vsi->rss_size, rss_size); | |
5706 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); | |
5707 | if (!lut) | |
5708 | return -ENOMEM; | |
5709 | ||
5710 | /* Ignoring user configured lut if there is one */ | |
5711 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, local_rss_size); | |
5712 | ||
5713 | /* Use user configured hash key if there is one, otherwise | |
5714 | * use default. | |
5715 | */ | |
5716 | if (vsi->rss_hkey_user) | |
5717 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
5718 | else | |
5719 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
5720 | ||
5721 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); | |
5722 | if (ret) { | |
5723 | dev_info(&pf->pdev->dev, | |
5724 | "Cannot set RSS lut, err %s aq_err %s\n", | |
5725 | i40e_stat_str(hw, ret), | |
5726 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
5727 | kfree(lut); | |
5728 | return ret; | |
5729 | } | |
5730 | kfree(lut); | |
5731 | ||
5732 | /* Do the update w.r.t. storing rss_size */ | |
5733 | if (!vsi->orig_rss_size) | |
5734 | vsi->orig_rss_size = vsi->rss_size; | |
5735 | vsi->current_rss_size = local_rss_size; | |
5736 | ||
5737 | return ret; | |
5738 | } | |
5739 | ||
5740 | /** | |
5741 | * i40e_channel_setup_queue_map - Setup a channel queue map | |
5742 | * @pf: ptr to PF device | |
5743 | * @vsi: the VSI being setup | |
5744 | * @ctxt: VSI context structure | |
5745 | * @ch: ptr to channel structure | |
5746 | * | |
5747 | * Setup queue map for a specific channel | |
5748 | **/ | |
5749 | static void i40e_channel_setup_queue_map(struct i40e_pf *pf, | |
5750 | struct i40e_vsi_context *ctxt, | |
5751 | struct i40e_channel *ch) | |
5752 | { | |
5753 | u16 qcount, qmap, sections = 0; | |
5754 | u8 offset = 0; | |
5755 | int pow; | |
5756 | ||
5757 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
5758 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
5759 | ||
5760 | qcount = min_t(int, ch->num_queue_pairs, pf->num_lan_msix); | |
5761 | ch->num_queue_pairs = qcount; | |
5762 | ||
5763 | /* find the next higher power-of-2 of num queue pairs */ | |
5764 | pow = ilog2(qcount); | |
5765 | if (!is_power_of_2(qcount)) | |
5766 | pow++; | |
5767 | ||
5768 | qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
5769 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
5770 | ||
5771 | /* Setup queue TC[0].qmap for given VSI context */ | |
5772 | ctxt->info.tc_mapping[0] = cpu_to_le16(qmap); | |
5773 | ||
5774 | ctxt->info.up_enable_bits = 0x1; /* TC0 enabled */ | |
5775 | ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
5776 | ctxt->info.queue_mapping[0] = cpu_to_le16(ch->base_queue); | |
5777 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
5778 | } | |
5779 | ||
5780 | /** | |
5781 | * i40e_add_channel - add a channel by adding VSI | |
5782 | * @pf: ptr to PF device | |
5783 | * @uplink_seid: underlying HW switching element (VEB) ID | |
5784 | * @ch: ptr to channel structure | |
5785 | * | |
5786 | * Add a channel (VSI) using add_vsi and queue_map | |
5787 | **/ | |
5788 | static int i40e_add_channel(struct i40e_pf *pf, u16 uplink_seid, | |
5789 | struct i40e_channel *ch) | |
5790 | { | |
5791 | struct i40e_hw *hw = &pf->hw; | |
5792 | struct i40e_vsi_context ctxt; | |
5793 | u8 enabled_tc = 0x1; /* TC0 enabled */ | |
5794 | int ret; | |
5795 | ||
5796 | if (ch->type != I40E_VSI_VMDQ2) { | |
5797 | dev_info(&pf->pdev->dev, | |
5798 | "add new vsi failed, ch->type %d\n", ch->type); | |
5799 | return -EINVAL; | |
5800 | } | |
5801 | ||
5802 | memset(&ctxt, 0, sizeof(ctxt)); | |
5803 | ctxt.pf_num = hw->pf_id; | |
5804 | ctxt.vf_num = 0; | |
5805 | ctxt.uplink_seid = uplink_seid; | |
5806 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; | |
5807 | if (ch->type == I40E_VSI_VMDQ2) | |
5808 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; | |
5809 | ||
5810 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) { | |
5811 | ctxt.info.valid_sections |= | |
5812 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
5813 | ctxt.info.switch_id = | |
5814 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
5815 | } | |
5816 | ||
5817 | /* Set queue map for a given VSI context */ | |
5818 | i40e_channel_setup_queue_map(pf, &ctxt, ch); | |
5819 | ||
5820 | /* Now time to create VSI */ | |
5821 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
5822 | if (ret) { | |
5823 | dev_info(&pf->pdev->dev, | |
5824 | "add new vsi failed, err %s aq_err %s\n", | |
5825 | i40e_stat_str(&pf->hw, ret), | |
5826 | i40e_aq_str(&pf->hw, | |
5827 | pf->hw.aq.asq_last_status)); | |
5828 | return -ENOENT; | |
5829 | } | |
5830 | ||
5831 | /* Success, update channel */ | |
5832 | ch->enabled_tc = enabled_tc; | |
5833 | ch->seid = ctxt.seid; | |
5834 | ch->vsi_number = ctxt.vsi_number; | |
5835 | ch->stat_counter_idx = cpu_to_le16(ctxt.info.stat_counter_idx); | |
5836 | ||
5837 | /* copy just the sections touched not the entire info | |
5838 | * since not all sections are valid as returned by | |
5839 | * update vsi params | |
5840 | */ | |
5841 | ch->info.mapping_flags = ctxt.info.mapping_flags; | |
5842 | memcpy(&ch->info.queue_mapping, | |
5843 | &ctxt.info.queue_mapping, sizeof(ctxt.info.queue_mapping)); | |
5844 | memcpy(&ch->info.tc_mapping, ctxt.info.tc_mapping, | |
5845 | sizeof(ctxt.info.tc_mapping)); | |
5846 | ||
5847 | return 0; | |
5848 | } | |
5849 | ||
5850 | static int i40e_channel_config_bw(struct i40e_vsi *vsi, struct i40e_channel *ch, | |
5851 | u8 *bw_share) | |
5852 | { | |
5853 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
5854 | i40e_status ret; | |
5855 | int i; | |
5856 | ||
5857 | bw_data.tc_valid_bits = ch->enabled_tc; | |
5858 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5859 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
5860 | ||
5861 | ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, ch->seid, | |
5862 | &bw_data, NULL); | |
5863 | if (ret) { | |
5864 | dev_info(&vsi->back->pdev->dev, | |
5865 | "Config VSI BW allocation per TC failed, aq_err: %d for new_vsi->seid %u\n", | |
5866 | vsi->back->hw.aq.asq_last_status, ch->seid); | |
5867 | return -EINVAL; | |
5868 | } | |
5869 | ||
5870 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5871 | ch->info.qs_handle[i] = bw_data.qs_handles[i]; | |
5872 | ||
5873 | return 0; | |
5874 | } | |
5875 | ||
5876 | /** | |
5877 | * i40e_channel_config_tx_ring - config TX ring associated with new channel | |
5878 | * @pf: ptr to PF device | |
5879 | * @vsi: the VSI being setup | |
5880 | * @ch: ptr to channel structure | |
5881 | * | |
5882 | * Configure TX rings associated with channel (VSI) since queues are being | |
5883 | * from parent VSI. | |
5884 | **/ | |
5885 | static int i40e_channel_config_tx_ring(struct i40e_pf *pf, | |
5886 | struct i40e_vsi *vsi, | |
5887 | struct i40e_channel *ch) | |
5888 | { | |
5889 | i40e_status ret; | |
5890 | int i; | |
5891 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
5892 | ||
5893 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
5894 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5895 | if (ch->enabled_tc & BIT(i)) | |
5896 | bw_share[i] = 1; | |
5897 | } | |
5898 | ||
5899 | /* configure BW for new VSI */ | |
5900 | ret = i40e_channel_config_bw(vsi, ch, bw_share); | |
5901 | if (ret) { | |
5902 | dev_info(&vsi->back->pdev->dev, | |
5903 | "Failed configuring TC map %d for channel (seid %u)\n", | |
5904 | ch->enabled_tc, ch->seid); | |
5905 | return ret; | |
5906 | } | |
5907 | ||
5908 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
5909 | struct i40e_ring *tx_ring, *rx_ring; | |
5910 | u16 pf_q; | |
5911 | ||
5912 | pf_q = ch->base_queue + i; | |
5913 | ||
5914 | /* Get to TX ring ptr of main VSI, for re-setup TX queue | |
5915 | * context | |
5916 | */ | |
5917 | tx_ring = vsi->tx_rings[pf_q]; | |
5918 | tx_ring->ch = ch; | |
5919 | ||
5920 | /* Get the RX ring ptr */ | |
5921 | rx_ring = vsi->rx_rings[pf_q]; | |
5922 | rx_ring->ch = ch; | |
5923 | } | |
5924 | ||
5925 | return 0; | |
5926 | } | |
5927 | ||
5928 | /** | |
5929 | * i40e_setup_hw_channel - setup new channel | |
5930 | * @pf: ptr to PF device | |
5931 | * @vsi: the VSI being setup | |
5932 | * @ch: ptr to channel structure | |
5933 | * @uplink_seid: underlying HW switching element (VEB) ID | |
5934 | * @type: type of channel to be created (VMDq2/VF) | |
5935 | * | |
5936 | * Setup new channel (VSI) based on specified type (VMDq2/VF) | |
5937 | * and configures TX rings accordingly | |
5938 | **/ | |
5939 | static inline int i40e_setup_hw_channel(struct i40e_pf *pf, | |
5940 | struct i40e_vsi *vsi, | |
5941 | struct i40e_channel *ch, | |
5942 | u16 uplink_seid, u8 type) | |
5943 | { | |
5944 | int ret; | |
5945 | ||
5946 | ch->initialized = false; | |
5947 | ch->base_queue = vsi->next_base_queue; | |
5948 | ch->type = type; | |
5949 | ||
5950 | /* Proceed with creation of channel (VMDq2) VSI */ | |
5951 | ret = i40e_add_channel(pf, uplink_seid, ch); | |
5952 | if (ret) { | |
5953 | dev_info(&pf->pdev->dev, | |
5954 | "failed to add_channel using uplink_seid %u\n", | |
5955 | uplink_seid); | |
5956 | return ret; | |
5957 | } | |
5958 | ||
5959 | /* Mark the successful creation of channel */ | |
5960 | ch->initialized = true; | |
5961 | ||
5962 | /* Reconfigure TX queues using QTX_CTL register */ | |
5963 | ret = i40e_channel_config_tx_ring(pf, vsi, ch); | |
5964 | if (ret) { | |
5965 | dev_info(&pf->pdev->dev, | |
5966 | "failed to configure TX rings for channel %u\n", | |
5967 | ch->seid); | |
5968 | return ret; | |
5969 | } | |
5970 | ||
5971 | /* update 'next_base_queue' */ | |
5972 | vsi->next_base_queue = vsi->next_base_queue + ch->num_queue_pairs; | |
5973 | dev_dbg(&pf->pdev->dev, | |
5974 | "Added channel: vsi_seid %u, vsi_number %u, stat_counter_idx %u, num_queue_pairs %u, pf->next_base_queue %d\n", | |
5975 | ch->seid, ch->vsi_number, ch->stat_counter_idx, | |
5976 | ch->num_queue_pairs, | |
5977 | vsi->next_base_queue); | |
5978 | return ret; | |
5979 | } | |
5980 | ||
5981 | /** | |
5982 | * i40e_setup_channel - setup new channel using uplink element | |
5983 | * @pf: ptr to PF device | |
5984 | * @type: type of channel to be created (VMDq2/VF) | |
5985 | * @uplink_seid: underlying HW switching element (VEB) ID | |
5986 | * @ch: ptr to channel structure | |
5987 | * | |
5988 | * Setup new channel (VSI) based on specified type (VMDq2/VF) | |
5989 | * and uplink switching element (uplink_seid) | |
5990 | **/ | |
5991 | static bool i40e_setup_channel(struct i40e_pf *pf, struct i40e_vsi *vsi, | |
5992 | struct i40e_channel *ch) | |
5993 | { | |
5994 | u8 vsi_type; | |
5995 | u16 seid; | |
5996 | int ret; | |
5997 | ||
5998 | if (vsi->type == I40E_VSI_MAIN) { | |
5999 | vsi_type = I40E_VSI_VMDQ2; | |
6000 | } else { | |
6001 | dev_err(&pf->pdev->dev, "unsupported parent vsi type(%d)\n", | |
6002 | vsi->type); | |
6003 | return false; | |
6004 | } | |
6005 | ||
6006 | /* underlying switching element */ | |
6007 | seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
6008 | ||
6009 | /* create channel (VSI), configure TX rings */ | |
6010 | ret = i40e_setup_hw_channel(pf, vsi, ch, seid, vsi_type); | |
6011 | if (ret) { | |
6012 | dev_err(&pf->pdev->dev, "failed to setup hw_channel\n"); | |
6013 | return false; | |
6014 | } | |
6015 | ||
6016 | return ch->initialized ? true : false; | |
6017 | } | |
6018 | ||
2f4b411a AN |
6019 | /** |
6020 | * i40e_validate_and_set_switch_mode - sets up switch mode correctly | |
6021 | * @vsi: ptr to VSI which has PF backing | |
6022 | * | |
6023 | * Sets up switch mode correctly if it needs to be changed and perform | |
6024 | * what are allowed modes. | |
6025 | **/ | |
6026 | static int i40e_validate_and_set_switch_mode(struct i40e_vsi *vsi) | |
6027 | { | |
6028 | u8 mode; | |
6029 | struct i40e_pf *pf = vsi->back; | |
6030 | struct i40e_hw *hw = &pf->hw; | |
6031 | int ret; | |
6032 | ||
6033 | ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_dev_capabilities); | |
6034 | if (ret) | |
6035 | return -EINVAL; | |
6036 | ||
6037 | if (hw->dev_caps.switch_mode) { | |
6038 | /* if switch mode is set, support mode2 (non-tunneled for | |
6039 | * cloud filter) for now | |
6040 | */ | |
6041 | u32 switch_mode = hw->dev_caps.switch_mode & | |
6042 | I40E_SWITCH_MODE_MASK; | |
6043 | if (switch_mode >= I40E_CLOUD_FILTER_MODE1) { | |
6044 | if (switch_mode == I40E_CLOUD_FILTER_MODE2) | |
6045 | return 0; | |
6046 | dev_err(&pf->pdev->dev, | |
6047 | "Invalid switch_mode (%d), only non-tunneled mode for cloud filter is supported\n", | |
6048 | hw->dev_caps.switch_mode); | |
6049 | return -EINVAL; | |
6050 | } | |
6051 | } | |
6052 | ||
6053 | /* Set Bit 7 to be valid */ | |
6054 | mode = I40E_AQ_SET_SWITCH_BIT7_VALID; | |
6055 | ||
64e711ca AN |
6056 | /* Set L4type for TCP support */ |
6057 | mode |= I40E_AQ_SET_SWITCH_L4_TYPE_TCP; | |
2f4b411a AN |
6058 | |
6059 | /* Set cloud filter mode */ | |
6060 | mode |= I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL; | |
6061 | ||
6062 | /* Prep mode field for set_switch_config */ | |
6063 | ret = i40e_aq_set_switch_config(hw, pf->last_sw_conf_flags, | |
6064 | pf->last_sw_conf_valid_flags, | |
6065 | mode, NULL); | |
6066 | if (ret && hw->aq.asq_last_status != I40E_AQ_RC_ESRCH) | |
6067 | dev_err(&pf->pdev->dev, | |
6068 | "couldn't set switch config bits, err %s aq_err %s\n", | |
6069 | i40e_stat_str(hw, ret), | |
6070 | i40e_aq_str(hw, | |
6071 | hw->aq.asq_last_status)); | |
6072 | ||
6073 | return ret; | |
6074 | } | |
6075 | ||
8f88b303 AN |
6076 | /** |
6077 | * i40e_create_queue_channel - function to create channel | |
6078 | * @vsi: VSI to be configured | |
6079 | * @ch: ptr to channel (it contains channel specific params) | |
6080 | * | |
6081 | * This function creates channel (VSI) using num_queues specified by user, | |
6082 | * reconfigs RSS if needed. | |
6083 | **/ | |
6084 | int i40e_create_queue_channel(struct i40e_vsi *vsi, | |
6085 | struct i40e_channel *ch) | |
6086 | { | |
6087 | struct i40e_pf *pf = vsi->back; | |
6088 | bool reconfig_rss; | |
6089 | int err; | |
6090 | ||
6091 | if (!ch) | |
6092 | return -EINVAL; | |
6093 | ||
6094 | if (!ch->num_queue_pairs) { | |
6095 | dev_err(&pf->pdev->dev, "Invalid num_queues requested: %d\n", | |
6096 | ch->num_queue_pairs); | |
6097 | return -EINVAL; | |
6098 | } | |
6099 | ||
6100 | /* validate user requested num_queues for channel */ | |
6101 | err = i40e_validate_num_queues(pf, ch->num_queue_pairs, vsi, | |
6102 | &reconfig_rss); | |
6103 | if (err) { | |
6104 | dev_info(&pf->pdev->dev, "Failed to validate num_queues (%d)\n", | |
6105 | ch->num_queue_pairs); | |
6106 | return -EINVAL; | |
6107 | } | |
6108 | ||
6109 | /* By default we are in VEPA mode, if this is the first VF/VMDq | |
6110 | * VSI to be added switch to VEB mode. | |
6111 | */ | |
6112 | if ((!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) || | |
6113 | (!i40e_is_any_channel(vsi))) { | |
6114 | if (!is_power_of_2(vsi->tc_config.tc_info[0].qcount)) { | |
6115 | dev_dbg(&pf->pdev->dev, | |
6116 | "Failed to create channel. Override queues (%u) not power of 2\n", | |
6117 | vsi->tc_config.tc_info[0].qcount); | |
6118 | return -EINVAL; | |
6119 | } | |
6120 | ||
6121 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
6122 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
6123 | ||
6124 | if (vsi->type == I40E_VSI_MAIN) { | |
6125 | if (pf->flags & I40E_FLAG_TC_MQPRIO) | |
6126 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, | |
6127 | true); | |
6128 | else | |
6129 | i40e_do_reset_safe(pf, | |
6130 | I40E_PF_RESET_FLAG); | |
6131 | } | |
6132 | } | |
6133 | /* now onwards for main VSI, number of queues will be value | |
6134 | * of TC0's queue count | |
6135 | */ | |
6136 | } | |
6137 | ||
6138 | /* By this time, vsi->cnt_q_avail shall be set to non-zero and | |
6139 | * it should be more than num_queues | |
6140 | */ | |
6141 | if (!vsi->cnt_q_avail || vsi->cnt_q_avail < ch->num_queue_pairs) { | |
6142 | dev_dbg(&pf->pdev->dev, | |
6143 | "Error: cnt_q_avail (%u) less than num_queues %d\n", | |
6144 | vsi->cnt_q_avail, ch->num_queue_pairs); | |
6145 | return -EINVAL; | |
6146 | } | |
6147 | ||
6148 | /* reconfig_rss only if vsi type is MAIN_VSI */ | |
6149 | if (reconfig_rss && (vsi->type == I40E_VSI_MAIN)) { | |
6150 | err = i40e_vsi_reconfig_rss(vsi, ch->num_queue_pairs); | |
6151 | if (err) { | |
6152 | dev_info(&pf->pdev->dev, | |
6153 | "Error: unable to reconfig rss for num_queues (%u)\n", | |
6154 | ch->num_queue_pairs); | |
6155 | return -EINVAL; | |
6156 | } | |
6157 | } | |
6158 | ||
6159 | if (!i40e_setup_channel(pf, vsi, ch)) { | |
6160 | dev_info(&pf->pdev->dev, "Failed to setup channel\n"); | |
6161 | return -EINVAL; | |
6162 | } | |
6163 | ||
6164 | dev_info(&pf->pdev->dev, | |
6165 | "Setup channel (id:%u) utilizing num_queues %d\n", | |
6166 | ch->seid, ch->num_queue_pairs); | |
6167 | ||
2027d4de AN |
6168 | /* configure VSI for BW limit */ |
6169 | if (ch->max_tx_rate) { | |
6c32e0d9 AB |
6170 | u64 credits = ch->max_tx_rate; |
6171 | ||
2027d4de AN |
6172 | if (i40e_set_bw_limit(vsi, ch->seid, ch->max_tx_rate)) |
6173 | return -EINVAL; | |
6174 | ||
6c32e0d9 | 6175 | do_div(credits, I40E_BW_CREDIT_DIVISOR); |
2027d4de AN |
6176 | dev_dbg(&pf->pdev->dev, |
6177 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
6178 | ch->max_tx_rate, | |
6c32e0d9 AB |
6179 | credits, |
6180 | ch->seid); | |
2027d4de AN |
6181 | } |
6182 | ||
8f88b303 AN |
6183 | /* in case of VF, this will be main SRIOV VSI */ |
6184 | ch->parent_vsi = vsi; | |
6185 | ||
6186 | /* and update main_vsi's count for queue_available to use */ | |
6187 | vsi->cnt_q_avail -= ch->num_queue_pairs; | |
6188 | ||
6189 | return 0; | |
6190 | } | |
6191 | ||
6192 | /** | |
6193 | * i40e_configure_queue_channels - Add queue channel for the given TCs | |
6194 | * @vsi: VSI to be configured | |
6195 | * | |
6196 | * Configures queue channel mapping to the given TCs | |
6197 | **/ | |
6198 | static int i40e_configure_queue_channels(struct i40e_vsi *vsi) | |
6199 | { | |
6200 | struct i40e_channel *ch; | |
6c32e0d9 | 6201 | u64 max_rate = 0; |
8f88b303 AN |
6202 | int ret = 0, i; |
6203 | ||
6204 | /* Create app vsi with the TCs. Main VSI with TC0 is already set up */ | |
aa5cb02a | 6205 | vsi->tc_seid_map[0] = vsi->seid; |
8f88b303 AN |
6206 | for (i = 1; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
6207 | if (vsi->tc_config.enabled_tc & BIT(i)) { | |
6208 | ch = kzalloc(sizeof(*ch), GFP_KERNEL); | |
6209 | if (!ch) { | |
6210 | ret = -ENOMEM; | |
6211 | goto err_free; | |
6212 | } | |
6213 | ||
6214 | INIT_LIST_HEAD(&ch->list); | |
6215 | ch->num_queue_pairs = | |
6216 | vsi->tc_config.tc_info[i].qcount; | |
6217 | ch->base_queue = | |
6218 | vsi->tc_config.tc_info[i].qoffset; | |
6219 | ||
2027d4de AN |
6220 | /* Bandwidth limit through tc interface is in bytes/s, |
6221 | * change to Mbit/s | |
6222 | */ | |
6c32e0d9 AB |
6223 | max_rate = vsi->mqprio_qopt.max_rate[i]; |
6224 | do_div(max_rate, I40E_BW_MBPS_DIVISOR); | |
6225 | ch->max_tx_rate = max_rate; | |
2027d4de | 6226 | |
8f88b303 AN |
6227 | list_add_tail(&ch->list, &vsi->ch_list); |
6228 | ||
6229 | ret = i40e_create_queue_channel(vsi, ch); | |
6230 | if (ret) { | |
6231 | dev_err(&vsi->back->pdev->dev, | |
6232 | "Failed creating queue channel with TC%d: queues %d\n", | |
6233 | i, ch->num_queue_pairs); | |
6234 | goto err_free; | |
6235 | } | |
aa5cb02a | 6236 | vsi->tc_seid_map[i] = ch->seid; |
8f88b303 AN |
6237 | } |
6238 | } | |
6239 | return ret; | |
6240 | ||
6241 | err_free: | |
6242 | i40e_remove_queue_channels(vsi); | |
6243 | return ret; | |
6244 | } | |
6245 | ||
4e3b35b0 NP |
6246 | /** |
6247 | * i40e_veb_config_tc - Configure TCs for given VEB | |
6248 | * @veb: given VEB | |
6249 | * @enabled_tc: TC bitmap | |
6250 | * | |
6251 | * Configures given TC bitmap for VEB (switching) element | |
6252 | **/ | |
6253 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc) | |
6254 | { | |
6255 | struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0}; | |
6256 | struct i40e_pf *pf = veb->pf; | |
6257 | int ret = 0; | |
6258 | int i; | |
6259 | ||
6260 | /* No TCs or already enabled TCs just return */ | |
6261 | if (!enabled_tc || veb->enabled_tc == enabled_tc) | |
6262 | return ret; | |
6263 | ||
6264 | bw_data.tc_valid_bits = enabled_tc; | |
6265 | /* bw_data.absolute_credits is not set (relative) */ | |
6266 | ||
6267 | /* Enable ETS TCs with equal BW Share for now */ | |
6268 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 6269 | if (enabled_tc & BIT(i)) |
4e3b35b0 NP |
6270 | bw_data.tc_bw_share_credits[i] = 1; |
6271 | } | |
6272 | ||
6273 | ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid, | |
6274 | &bw_data, NULL); | |
6275 | if (ret) { | |
6276 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6277 | "VEB bw config failed, err %s aq_err %s\n", |
6278 | i40e_stat_str(&pf->hw, ret), | |
6279 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6280 | goto out; |
6281 | } | |
6282 | ||
6283 | /* Update the BW information */ | |
6284 | ret = i40e_veb_get_bw_info(veb); | |
6285 | if (ret) { | |
6286 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6287 | "Failed getting veb bw config, err %s aq_err %s\n", |
6288 | i40e_stat_str(&pf->hw, ret), | |
6289 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6290 | } |
6291 | ||
6292 | out: | |
6293 | return ret; | |
6294 | } | |
6295 | ||
6296 | #ifdef CONFIG_I40E_DCB | |
6297 | /** | |
6298 | * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs | |
6299 | * @pf: PF struct | |
6300 | * | |
6301 | * Reconfigure VEB/VSIs on a given PF; it is assumed that | |
6302 | * the caller would've quiesce all the VSIs before calling | |
6303 | * this function | |
6304 | **/ | |
6305 | static void i40e_dcb_reconfigure(struct i40e_pf *pf) | |
6306 | { | |
6307 | u8 tc_map = 0; | |
6308 | int ret; | |
6309 | u8 v; | |
6310 | ||
6311 | /* Enable the TCs available on PF to all VEBs */ | |
6312 | tc_map = i40e_pf_get_tc_map(pf); | |
6313 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
6314 | if (!pf->veb[v]) | |
6315 | continue; | |
6316 | ret = i40e_veb_config_tc(pf->veb[v], tc_map); | |
6317 | if (ret) { | |
6318 | dev_info(&pf->pdev->dev, | |
6319 | "Failed configuring TC for VEB seid=%d\n", | |
6320 | pf->veb[v]->seid); | |
6321 | /* Will try to configure as many components */ | |
6322 | } | |
6323 | } | |
6324 | ||
6325 | /* Update each VSI */ | |
505682cd | 6326 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
4e3b35b0 NP |
6327 | if (!pf->vsi[v]) |
6328 | continue; | |
6329 | ||
6330 | /* - Enable all TCs for the LAN VSI | |
6331 | * - For all others keep them at TC0 for now | |
6332 | */ | |
6333 | if (v == pf->lan_vsi) | |
6334 | tc_map = i40e_pf_get_tc_map(pf); | |
6335 | else | |
ea6acb7e | 6336 | tc_map = I40E_DEFAULT_TRAFFIC_CLASS; |
4e3b35b0 NP |
6337 | |
6338 | ret = i40e_vsi_config_tc(pf->vsi[v], tc_map); | |
6339 | if (ret) { | |
6340 | dev_info(&pf->pdev->dev, | |
6341 | "Failed configuring TC for VSI seid=%d\n", | |
6342 | pf->vsi[v]->seid); | |
6343 | /* Will try to configure as many components */ | |
6344 | } else { | |
0672a091 NP |
6345 | /* Re-configure VSI vectors based on updated TC map */ |
6346 | i40e_vsi_map_rings_to_vectors(pf->vsi[v]); | |
4e3b35b0 NP |
6347 | if (pf->vsi[v]->netdev) |
6348 | i40e_dcbnl_set_all(pf->vsi[v]); | |
6349 | } | |
6350 | } | |
6351 | } | |
6352 | ||
2fd75f31 NP |
6353 | /** |
6354 | * i40e_resume_port_tx - Resume port Tx | |
6355 | * @pf: PF struct | |
6356 | * | |
6357 | * Resume a port's Tx and issue a PF reset in case of failure to | |
6358 | * resume. | |
6359 | **/ | |
6360 | static int i40e_resume_port_tx(struct i40e_pf *pf) | |
6361 | { | |
6362 | struct i40e_hw *hw = &pf->hw; | |
6363 | int ret; | |
6364 | ||
6365 | ret = i40e_aq_resume_port_tx(hw, NULL); | |
6366 | if (ret) { | |
6367 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6368 | "Resume Port Tx failed, err %s aq_err %s\n", |
6369 | i40e_stat_str(&pf->hw, ret), | |
6370 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
2fd75f31 | 6371 | /* Schedule PF reset to recover */ |
0da36b97 | 6372 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
2fd75f31 NP |
6373 | i40e_service_event_schedule(pf); |
6374 | } | |
6375 | ||
6376 | return ret; | |
6377 | } | |
6378 | ||
4e3b35b0 NP |
6379 | /** |
6380 | * i40e_init_pf_dcb - Initialize DCB configuration | |
6381 | * @pf: PF being configured | |
6382 | * | |
6383 | * Query the current DCB configuration and cache it | |
6384 | * in the hardware structure | |
6385 | **/ | |
6386 | static int i40e_init_pf_dcb(struct i40e_pf *pf) | |
6387 | { | |
6388 | struct i40e_hw *hw = &pf->hw; | |
6389 | int err = 0; | |
6390 | ||
025b4a54 | 6391 | /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */ |
d36e41dc | 6392 | if (pf->hw_features & I40E_HW_NO_DCB_SUPPORT) |
025b4a54 ASJ |
6393 | goto out; |
6394 | ||
4e3b35b0 NP |
6395 | /* Get the initial DCB configuration */ |
6396 | err = i40e_init_dcb(hw); | |
6397 | if (!err) { | |
6398 | /* Device/Function is not DCBX capable */ | |
6399 | if ((!hw->func_caps.dcb) || | |
6400 | (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) { | |
6401 | dev_info(&pf->pdev->dev, | |
6402 | "DCBX offload is not supported or is disabled for this PF.\n"); | |
4e3b35b0 NP |
6403 | } else { |
6404 | /* When status is not DISABLED then DCBX in FW */ | |
6405 | pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | | |
6406 | DCB_CAP_DCBX_VER_IEEE; | |
4d9b6043 NP |
6407 | |
6408 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
a036244c DE |
6409 | /* Enable DCB tagging only when more than one TC |
6410 | * or explicitly disable if only one TC | |
6411 | */ | |
4d9b6043 NP |
6412 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
6413 | pf->flags |= I40E_FLAG_DCB_ENABLED; | |
a036244c DE |
6414 | else |
6415 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
9fa61dd2 NP |
6416 | dev_dbg(&pf->pdev->dev, |
6417 | "DCBX offload is supported for this PF.\n"); | |
4e3b35b0 | 6418 | } |
014269ff | 6419 | } else { |
aebfc816 | 6420 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6421 | "Query for DCB configuration failed, err %s aq_err %s\n", |
6422 | i40e_stat_str(&pf->hw, err), | |
6423 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6424 | } |
6425 | ||
6426 | out: | |
6427 | return err; | |
6428 | } | |
6429 | #endif /* CONFIG_I40E_DCB */ | |
cf05ed08 JB |
6430 | #define SPEED_SIZE 14 |
6431 | #define FC_SIZE 8 | |
6432 | /** | |
6433 | * i40e_print_link_message - print link up or down | |
6434 | * @vsi: the VSI for which link needs a message | |
6435 | */ | |
c156f856 | 6436 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup) |
cf05ed08 | 6437 | { |
7ec9ba11 | 6438 | enum i40e_aq_link_speed new_speed; |
3fded466 | 6439 | struct i40e_pf *pf = vsi->back; |
a9165490 SN |
6440 | char *speed = "Unknown"; |
6441 | char *fc = "Unknown"; | |
3e03d7cc | 6442 | char *fec = ""; |
68e49702 | 6443 | char *req_fec = ""; |
3e03d7cc | 6444 | char *an = ""; |
cf05ed08 | 6445 | |
3fded466 | 6446 | new_speed = pf->hw.phy.link_info.link_speed; |
7ec9ba11 FS |
6447 | |
6448 | if ((vsi->current_isup == isup) && (vsi->current_speed == new_speed)) | |
c156f856 MJ |
6449 | return; |
6450 | vsi->current_isup = isup; | |
7ec9ba11 | 6451 | vsi->current_speed = new_speed; |
cf05ed08 JB |
6452 | if (!isup) { |
6453 | netdev_info(vsi->netdev, "NIC Link is Down\n"); | |
6454 | return; | |
6455 | } | |
6456 | ||
148c2d80 GR |
6457 | /* Warn user if link speed on NPAR enabled partition is not at |
6458 | * least 10GB | |
6459 | */ | |
3fded466 SM |
6460 | if (pf->hw.func_caps.npar_enable && |
6461 | (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB || | |
6462 | pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) | |
148c2d80 GR |
6463 | netdev_warn(vsi->netdev, |
6464 | "The partition detected link speed that is less than 10Gbps\n"); | |
6465 | ||
3fded466 | 6466 | switch (pf->hw.phy.link_info.link_speed) { |
cf05ed08 | 6467 | case I40E_LINK_SPEED_40GB: |
a9165490 | 6468 | speed = "40 G"; |
cf05ed08 | 6469 | break; |
ae24b409 | 6470 | case I40E_LINK_SPEED_20GB: |
a9165490 | 6471 | speed = "20 G"; |
ae24b409 | 6472 | break; |
3123237a CW |
6473 | case I40E_LINK_SPEED_25GB: |
6474 | speed = "25 G"; | |
6475 | break; | |
cf05ed08 | 6476 | case I40E_LINK_SPEED_10GB: |
a9165490 | 6477 | speed = "10 G"; |
cf05ed08 JB |
6478 | break; |
6479 | case I40E_LINK_SPEED_1GB: | |
a9165490 | 6480 | speed = "1000 M"; |
cf05ed08 | 6481 | break; |
5960d33f | 6482 | case I40E_LINK_SPEED_100MB: |
a9165490 | 6483 | speed = "100 M"; |
5960d33f | 6484 | break; |
cf05ed08 JB |
6485 | default: |
6486 | break; | |
6487 | } | |
6488 | ||
3fded466 | 6489 | switch (pf->hw.fc.current_mode) { |
cf05ed08 | 6490 | case I40E_FC_FULL: |
a9165490 | 6491 | fc = "RX/TX"; |
cf05ed08 JB |
6492 | break; |
6493 | case I40E_FC_TX_PAUSE: | |
a9165490 | 6494 | fc = "TX"; |
cf05ed08 JB |
6495 | break; |
6496 | case I40E_FC_RX_PAUSE: | |
a9165490 | 6497 | fc = "RX"; |
cf05ed08 JB |
6498 | break; |
6499 | default: | |
a9165490 | 6500 | fc = "None"; |
cf05ed08 JB |
6501 | break; |
6502 | } | |
6503 | ||
3fded466 | 6504 | if (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_25GB) { |
68e49702 | 6505 | req_fec = ", Requested FEC: None"; |
3e03d7cc HT |
6506 | fec = ", FEC: None"; |
6507 | an = ", Autoneg: False"; | |
6508 | ||
3fded466 | 6509 | if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED) |
3e03d7cc HT |
6510 | an = ", Autoneg: True"; |
6511 | ||
3fded466 | 6512 | if (pf->hw.phy.link_info.fec_info & |
3e03d7cc HT |
6513 | I40E_AQ_CONFIG_FEC_KR_ENA) |
6514 | fec = ", FEC: CL74 FC-FEC/BASE-R"; | |
3fded466 | 6515 | else if (pf->hw.phy.link_info.fec_info & |
3e03d7cc HT |
6516 | I40E_AQ_CONFIG_FEC_RS_ENA) |
6517 | fec = ", FEC: CL108 RS-FEC"; | |
68e49702 MS |
6518 | |
6519 | /* 'CL108 RS-FEC' should be displayed when RS is requested, or | |
6520 | * both RS and FC are requested | |
6521 | */ | |
6522 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
6523 | (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS)) { | |
6524 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
6525 | I40E_AQ_REQUEST_FEC_RS) | |
6526 | req_fec = ", Requested FEC: CL108 RS-FEC"; | |
6527 | else | |
6528 | req_fec = ", Requested FEC: CL74 FC-FEC/BASE-R"; | |
6529 | } | |
3e03d7cc HT |
6530 | } |
6531 | ||
68e49702 MS |
6532 | netdev_info(vsi->netdev, "NIC Link is Up, %sbps Full Duplex%s%s%s, Flow Control: %s\n", |
6533 | speed, req_fec, fec, an, fc); | |
cf05ed08 | 6534 | } |
4e3b35b0 | 6535 | |
41c445ff JB |
6536 | /** |
6537 | * i40e_up_complete - Finish the last steps of bringing up a connection | |
6538 | * @vsi: the VSI being configured | |
6539 | **/ | |
6540 | static int i40e_up_complete(struct i40e_vsi *vsi) | |
6541 | { | |
6542 | struct i40e_pf *pf = vsi->back; | |
6543 | int err; | |
6544 | ||
6545 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
6546 | i40e_vsi_configure_msix(vsi); | |
6547 | else | |
6548 | i40e_configure_msi_and_legacy(vsi); | |
6549 | ||
6550 | /* start rings */ | |
3aa7b74d | 6551 | err = i40e_vsi_start_rings(vsi); |
41c445ff JB |
6552 | if (err) |
6553 | return err; | |
6554 | ||
0da36b97 | 6555 | clear_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
6556 | i40e_napi_enable_all(vsi); |
6557 | i40e_vsi_enable_irq(vsi); | |
6558 | ||
6559 | if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) && | |
6560 | (vsi->netdev)) { | |
cf05ed08 | 6561 | i40e_print_link_message(vsi, true); |
41c445ff JB |
6562 | netif_tx_start_all_queues(vsi->netdev); |
6563 | netif_carrier_on(vsi->netdev); | |
6564 | } | |
ca64fa4e ASJ |
6565 | |
6566 | /* replay FDIR SB filters */ | |
1e1be8f6 ASJ |
6567 | if (vsi->type == I40E_VSI_FDIR) { |
6568 | /* reset fd counters */ | |
097dbf52 JK |
6569 | pf->fd_add_err = 0; |
6570 | pf->fd_atr_cnt = 0; | |
ca64fa4e | 6571 | i40e_fdir_filter_restore(vsi); |
1e1be8f6 | 6572 | } |
e3219ce6 ASJ |
6573 | |
6574 | /* On the next run of the service_task, notify any clients of the new | |
6575 | * opened netdev | |
6576 | */ | |
6577 | pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED; | |
41c445ff JB |
6578 | i40e_service_event_schedule(pf); |
6579 | ||
6580 | return 0; | |
6581 | } | |
6582 | ||
6583 | /** | |
6584 | * i40e_vsi_reinit_locked - Reset the VSI | |
6585 | * @vsi: the VSI being configured | |
6586 | * | |
6587 | * Rebuild the ring structs after some configuration | |
6588 | * has changed, e.g. MTU size. | |
6589 | **/ | |
6590 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi) | |
6591 | { | |
6592 | struct i40e_pf *pf = vsi->back; | |
6593 | ||
6594 | WARN_ON(in_interrupt()); | |
0da36b97 | 6595 | while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
6596 | usleep_range(1000, 2000); |
6597 | i40e_down(vsi); | |
6598 | ||
41c445ff | 6599 | i40e_up(vsi); |
0da36b97 | 6600 | clear_bit(__I40E_CONFIG_BUSY, pf->state); |
41c445ff JB |
6601 | } |
6602 | ||
6603 | /** | |
6604 | * i40e_up - Bring the connection back up after being down | |
6605 | * @vsi: the VSI being configured | |
6606 | **/ | |
6607 | int i40e_up(struct i40e_vsi *vsi) | |
6608 | { | |
6609 | int err; | |
6610 | ||
6611 | err = i40e_vsi_configure(vsi); | |
6612 | if (!err) | |
6613 | err = i40e_up_complete(vsi); | |
6614 | ||
6615 | return err; | |
6616 | } | |
6617 | ||
6618 | /** | |
6619 | * i40e_down - Shutdown the connection processing | |
6620 | * @vsi: the VSI being stopped | |
6621 | **/ | |
6622 | void i40e_down(struct i40e_vsi *vsi) | |
6623 | { | |
6624 | int i; | |
6625 | ||
6626 | /* It is assumed that the caller of this function | |
d19cb64b | 6627 | * sets the vsi->state __I40E_VSI_DOWN bit. |
41c445ff JB |
6628 | */ |
6629 | if (vsi->netdev) { | |
6630 | netif_carrier_off(vsi->netdev); | |
6631 | netif_tx_disable(vsi->netdev); | |
6632 | } | |
6633 | i40e_vsi_disable_irq(vsi); | |
3aa7b74d | 6634 | i40e_vsi_stop_rings(vsi); |
41c445ff JB |
6635 | i40e_napi_disable_all(vsi); |
6636 | ||
6637 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b | 6638 | i40e_clean_tx_ring(vsi->tx_rings[i]); |
74608d17 BT |
6639 | if (i40e_enabled_xdp_vsi(vsi)) |
6640 | i40e_clean_tx_ring(vsi->xdp_rings[i]); | |
9f65e15b | 6641 | i40e_clean_rx_ring(vsi->rx_rings[i]); |
41c445ff | 6642 | } |
f980d445 | 6643 | |
41c445ff JB |
6644 | } |
6645 | ||
a9ce82f7 AN |
6646 | /** |
6647 | * i40e_validate_mqprio_qopt- validate queue mapping info | |
6648 | * @vsi: the VSI being configured | |
6649 | * @mqprio_qopt: queue parametrs | |
6650 | **/ | |
6651 | static int i40e_validate_mqprio_qopt(struct i40e_vsi *vsi, | |
6652 | struct tc_mqprio_qopt_offload *mqprio_qopt) | |
6653 | { | |
2027d4de | 6654 | u64 sum_max_rate = 0; |
6c32e0d9 | 6655 | u64 max_rate = 0; |
a9ce82f7 AN |
6656 | int i; |
6657 | ||
6658 | if (mqprio_qopt->qopt.offset[0] != 0 || | |
6659 | mqprio_qopt->qopt.num_tc < 1 || | |
6660 | mqprio_qopt->qopt.num_tc > I40E_MAX_TRAFFIC_CLASS) | |
6661 | return -EINVAL; | |
6662 | for (i = 0; ; i++) { | |
6663 | if (!mqprio_qopt->qopt.count[i]) | |
6664 | return -EINVAL; | |
2027d4de AN |
6665 | if (mqprio_qopt->min_rate[i]) { |
6666 | dev_err(&vsi->back->pdev->dev, | |
6667 | "Invalid min tx rate (greater than 0) specified\n"); | |
a9ce82f7 | 6668 | return -EINVAL; |
2027d4de | 6669 | } |
6c32e0d9 AB |
6670 | max_rate = mqprio_qopt->max_rate[i]; |
6671 | do_div(max_rate, I40E_BW_MBPS_DIVISOR); | |
6672 | sum_max_rate += max_rate; | |
2027d4de | 6673 | |
a9ce82f7 AN |
6674 | if (i >= mqprio_qopt->qopt.num_tc - 1) |
6675 | break; | |
6676 | if (mqprio_qopt->qopt.offset[i + 1] != | |
6677 | (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) | |
6678 | return -EINVAL; | |
6679 | } | |
6680 | if (vsi->num_queue_pairs < | |
6681 | (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) { | |
6682 | return -EINVAL; | |
6683 | } | |
2027d4de AN |
6684 | if (sum_max_rate > i40e_get_link_speed(vsi)) { |
6685 | dev_err(&vsi->back->pdev->dev, | |
6686 | "Invalid max tx rate specified\n"); | |
6687 | return -EINVAL; | |
6688 | } | |
a9ce82f7 AN |
6689 | return 0; |
6690 | } | |
6691 | ||
6692 | /** | |
6693 | * i40e_vsi_set_default_tc_config - set default values for tc configuration | |
6694 | * @vsi: the VSI being configured | |
6695 | **/ | |
6696 | static void i40e_vsi_set_default_tc_config(struct i40e_vsi *vsi) | |
6697 | { | |
6698 | u16 qcount; | |
6699 | int i; | |
6700 | ||
6701 | /* Only TC0 is enabled */ | |
6702 | vsi->tc_config.numtc = 1; | |
6703 | vsi->tc_config.enabled_tc = 1; | |
6704 | qcount = min_t(int, vsi->alloc_queue_pairs, | |
6705 | i40e_pf_get_max_q_per_tc(vsi->back)); | |
6706 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
6707 | /* For the TC that is not enabled set the offset to to default | |
6708 | * queue and allocate one queue for the given TC. | |
6709 | */ | |
6710 | vsi->tc_config.tc_info[i].qoffset = 0; | |
6711 | if (i == 0) | |
6712 | vsi->tc_config.tc_info[i].qcount = qcount; | |
6713 | else | |
6714 | vsi->tc_config.tc_info[i].qcount = 1; | |
6715 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
6716 | } | |
6717 | } | |
6718 | ||
41c445ff JB |
6719 | /** |
6720 | * i40e_setup_tc - configure multiple traffic classes | |
6721 | * @netdev: net device to configure | |
a9ce82f7 | 6722 | * @type_data: tc offload data |
41c445ff | 6723 | **/ |
a9ce82f7 | 6724 | static int i40e_setup_tc(struct net_device *netdev, void *type_data) |
41c445ff | 6725 | { |
a9ce82f7 | 6726 | struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; |
41c445ff JB |
6727 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
6728 | struct i40e_vsi *vsi = np->vsi; | |
6729 | struct i40e_pf *pf = vsi->back; | |
a9ce82f7 AN |
6730 | u8 enabled_tc = 0, num_tc, hw; |
6731 | bool need_reset = false; | |
41c445ff | 6732 | int ret = -EINVAL; |
a9ce82f7 | 6733 | u16 mode; |
41c445ff JB |
6734 | int i; |
6735 | ||
a9ce82f7 AN |
6736 | num_tc = mqprio_qopt->qopt.num_tc; |
6737 | hw = mqprio_qopt->qopt.hw; | |
6738 | mode = mqprio_qopt->mode; | |
6739 | if (!hw) { | |
6740 | pf->flags &= ~I40E_FLAG_TC_MQPRIO; | |
6741 | memcpy(&vsi->mqprio_qopt, mqprio_qopt, sizeof(*mqprio_qopt)); | |
6742 | goto config_tc; | |
41c445ff JB |
6743 | } |
6744 | ||
6745 | /* Check if MFP enabled */ | |
6746 | if (pf->flags & I40E_FLAG_MFP_ENABLED) { | |
a9ce82f7 AN |
6747 | netdev_info(netdev, |
6748 | "Configuring TC not supported in MFP mode\n"); | |
6749 | return ret; | |
41c445ff | 6750 | } |
a9ce82f7 AN |
6751 | switch (mode) { |
6752 | case TC_MQPRIO_MODE_DCB: | |
6753 | pf->flags &= ~I40E_FLAG_TC_MQPRIO; | |
41c445ff | 6754 | |
a9ce82f7 AN |
6755 | /* Check if DCB enabled to continue */ |
6756 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) { | |
6757 | netdev_info(netdev, | |
6758 | "DCB is not enabled for adapter\n"); | |
6759 | return ret; | |
6760 | } | |
6761 | ||
6762 | /* Check whether tc count is within enabled limit */ | |
6763 | if (num_tc > i40e_pf_get_num_tc(pf)) { | |
6764 | netdev_info(netdev, | |
6765 | "TC count greater than enabled on link for adapter\n"); | |
6766 | return ret; | |
6767 | } | |
6768 | break; | |
6769 | case TC_MQPRIO_MODE_CHANNEL: | |
6770 | if (pf->flags & I40E_FLAG_DCB_ENABLED) { | |
6771 | netdev_info(netdev, | |
6772 | "Full offload of TC Mqprio options is not supported when DCB is enabled\n"); | |
6773 | return ret; | |
6774 | } | |
6775 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
6776 | return ret; | |
6777 | ret = i40e_validate_mqprio_qopt(vsi, mqprio_qopt); | |
6778 | if (ret) | |
6779 | return ret; | |
6780 | memcpy(&vsi->mqprio_qopt, mqprio_qopt, | |
6781 | sizeof(*mqprio_qopt)); | |
6782 | pf->flags |= I40E_FLAG_TC_MQPRIO; | |
6783 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
6784 | break; | |
6785 | default: | |
6786 | return -EINVAL; | |
41c445ff JB |
6787 | } |
6788 | ||
a9ce82f7 | 6789 | config_tc: |
41c445ff | 6790 | /* Generate TC map for number of tc requested */ |
a9ce82f7 | 6791 | for (i = 0; i < num_tc; i++) |
75f5cea9 | 6792 | enabled_tc |= BIT(i); |
41c445ff JB |
6793 | |
6794 | /* Requesting same TC configuration as already enabled */ | |
a9ce82f7 AN |
6795 | if (enabled_tc == vsi->tc_config.enabled_tc && |
6796 | mode != TC_MQPRIO_MODE_CHANNEL) | |
41c445ff JB |
6797 | return 0; |
6798 | ||
6799 | /* Quiesce VSI queues */ | |
6800 | i40e_quiesce_vsi(vsi); | |
6801 | ||
a9ce82f7 AN |
6802 | if (!hw && !(pf->flags & I40E_FLAG_TC_MQPRIO)) |
6803 | i40e_remove_queue_channels(vsi); | |
6804 | ||
41c445ff JB |
6805 | /* Configure VSI for enabled TCs */ |
6806 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
6807 | if (ret) { | |
6808 | netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n", | |
6809 | vsi->seid); | |
a9ce82f7 | 6810 | need_reset = true; |
41c445ff JB |
6811 | goto exit; |
6812 | } | |
6813 | ||
8f88b303 | 6814 | if (pf->flags & I40E_FLAG_TC_MQPRIO) { |
2027d4de | 6815 | if (vsi->mqprio_qopt.max_rate[0]) { |
6c32e0d9 AB |
6816 | u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0]; |
6817 | ||
6818 | do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR); | |
2027d4de AN |
6819 | ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate); |
6820 | if (!ret) { | |
6c32e0d9 AB |
6821 | u64 credits = max_tx_rate; |
6822 | ||
6823 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
2027d4de AN |
6824 | dev_dbg(&vsi->back->pdev->dev, |
6825 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
6826 | max_tx_rate, | |
6c32e0d9 | 6827 | credits, |
2027d4de AN |
6828 | vsi->seid); |
6829 | } else { | |
6830 | need_reset = true; | |
6831 | goto exit; | |
6832 | } | |
6833 | } | |
8f88b303 | 6834 | ret = i40e_configure_queue_channels(vsi); |
4e3b35b0 | 6835 | if (ret) { |
8f88b303 AN |
6836 | netdev_info(netdev, |
6837 | "Failed configuring queue channels\n"); | |
a9ce82f7 | 6838 | need_reset = true; |
8f88b303 | 6839 | goto exit; |
4e3b35b0 NP |
6840 | } |
6841 | } | |
6842 | ||
41c445ff | 6843 | exit: |
a9ce82f7 AN |
6844 | /* Reset the configuration data to defaults, only TC0 is enabled */ |
6845 | if (need_reset) { | |
6846 | i40e_vsi_set_default_tc_config(vsi); | |
6847 | need_reset = false; | |
6848 | } | |
4e3b35b0 | 6849 | |
8f88b303 AN |
6850 | /* Unquiesce VSI */ |
6851 | i40e_unquiesce_vsi(vsi); | |
41c445ff JB |
6852 | return ret; |
6853 | } | |
4e3b35b0 | 6854 | |
2f4b411a AN |
6855 | /** |
6856 | * i40e_set_cld_element - sets cloud filter element data | |
6857 | * @filter: cloud filter rule | |
6858 | * @cld: ptr to cloud filter element data | |
6859 | * | |
6860 | * This is helper function to copy data into cloud filter element | |
6861 | **/ | |
6862 | static inline void | |
6863 | i40e_set_cld_element(struct i40e_cloud_filter *filter, | |
6864 | struct i40e_aqc_cloud_filters_element_data *cld) | |
6865 | { | |
6866 | int i, j; | |
6867 | u32 ipa; | |
6868 | ||
6869 | memset(cld, 0, sizeof(*cld)); | |
6870 | ether_addr_copy(cld->outer_mac, filter->dst_mac); | |
6871 | ether_addr_copy(cld->inner_mac, filter->src_mac); | |
6872 | ||
6873 | if (filter->n_proto != ETH_P_IP && filter->n_proto != ETH_P_IPV6) | |
6874 | return; | |
6875 | ||
6876 | if (filter->n_proto == ETH_P_IPV6) { | |
6877 | #define IPV6_MAX_INDEX (ARRAY_SIZE(filter->dst_ipv6) - 1) | |
6878 | for (i = 0, j = 0; i < ARRAY_SIZE(filter->dst_ipv6); | |
6879 | i++, j += 2) { | |
6880 | ipa = be32_to_cpu(filter->dst_ipv6[IPV6_MAX_INDEX - i]); | |
6881 | ipa = cpu_to_le32(ipa); | |
6882 | memcpy(&cld->ipaddr.raw_v6.data[j], &ipa, sizeof(ipa)); | |
4e3b35b0 | 6883 | } |
2f4b411a AN |
6884 | } else { |
6885 | ipa = be32_to_cpu(filter->dst_ipv4); | |
6886 | memcpy(&cld->ipaddr.v4.data, &ipa, sizeof(ipa)); | |
4e3b35b0 | 6887 | } |
2f4b411a AN |
6888 | |
6889 | cld->inner_vlan = cpu_to_le16(ntohs(filter->vlan_id)); | |
6890 | ||
6891 | /* tenant_id is not supported by FW now, once the support is enabled | |
6892 | * fill the cld->tenant_id with cpu_to_le32(filter->tenant_id) | |
6893 | */ | |
6894 | if (filter->tenant_id) | |
6895 | return; | |
4e3b35b0 NP |
6896 | } |
6897 | ||
2fd75f31 | 6898 | /** |
2f4b411a AN |
6899 | * i40e_add_del_cloud_filter - Add/del cloud filter |
6900 | * @vsi: pointer to VSI | |
6901 | * @filter: cloud filter rule | |
6902 | * @add: if true, add, if false, delete | |
2fd75f31 | 6903 | * |
2f4b411a AN |
6904 | * Add or delete a cloud filter for a specific flow spec. |
6905 | * Returns 0 if the filter were successfully added. | |
2fd75f31 | 6906 | **/ |
2f4b411a AN |
6907 | static int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, |
6908 | struct i40e_cloud_filter *filter, bool add) | |
2fd75f31 | 6909 | { |
2f4b411a AN |
6910 | struct i40e_aqc_cloud_filters_element_data cld_filter; |
6911 | struct i40e_pf *pf = vsi->back; | |
2fd75f31 | 6912 | int ret; |
2f4b411a AN |
6913 | static const u16 flag_table[128] = { |
6914 | [I40E_CLOUD_FILTER_FLAGS_OMAC] = | |
6915 | I40E_AQC_ADD_CLOUD_FILTER_OMAC, | |
6916 | [I40E_CLOUD_FILTER_FLAGS_IMAC] = | |
6917 | I40E_AQC_ADD_CLOUD_FILTER_IMAC, | |
6918 | [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN] = | |
6919 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN, | |
6920 | [I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID] = | |
6921 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID, | |
6922 | [I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC] = | |
6923 | I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC, | |
6924 | [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID] = | |
6925 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID, | |
6926 | [I40E_CLOUD_FILTER_FLAGS_IIP] = | |
6927 | I40E_AQC_ADD_CLOUD_FILTER_IIP, | |
6928 | }; | |
6929 | ||
6930 | if (filter->flags >= ARRAY_SIZE(flag_table)) | |
6931 | return I40E_ERR_CONFIG; | |
6932 | ||
6933 | /* copy element needed to add cloud filter from filter */ | |
6934 | i40e_set_cld_element(filter, &cld_filter); | |
6935 | ||
6936 | if (filter->tunnel_type != I40E_CLOUD_TNL_TYPE_NONE) | |
6937 | cld_filter.flags = cpu_to_le16(filter->tunnel_type << | |
6938 | I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT); | |
6939 | ||
6940 | if (filter->n_proto == ETH_P_IPV6) | |
6941 | cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] | | |
6942 | I40E_AQC_ADD_CLOUD_FLAGS_IPV6); | |
6943 | else | |
6944 | cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] | | |
6945 | I40E_AQC_ADD_CLOUD_FLAGS_IPV4); | |
2fd75f31 | 6946 | |
2f4b411a AN |
6947 | if (add) |
6948 | ret = i40e_aq_add_cloud_filters(&pf->hw, filter->seid, | |
6949 | &cld_filter, 1); | |
6950 | else | |
6951 | ret = i40e_aq_rem_cloud_filters(&pf->hw, filter->seid, | |
6952 | &cld_filter, 1); | |
6953 | if (ret) | |
6954 | dev_dbg(&pf->pdev->dev, | |
6955 | "Failed to %s cloud filter using l4 port %u, err %d aq_err %d\n", | |
6956 | add ? "add" : "delete", filter->dst_port, ret, | |
6957 | pf->hw.aq.asq_last_status); | |
6958 | else | |
2fd75f31 | 6959 | dev_info(&pf->pdev->dev, |
2f4b411a AN |
6960 | "%s cloud filter for VSI: %d\n", |
6961 | add ? "Added" : "Deleted", filter->seid); | |
2fd75f31 NP |
6962 | return ret; |
6963 | } | |
6964 | ||
4e3b35b0 | 6965 | /** |
2f4b411a AN |
6966 | * i40e_add_del_cloud_filter_big_buf - Add/del cloud filter using big_buf |
6967 | * @vsi: pointer to VSI | |
6968 | * @filter: cloud filter rule | |
6969 | * @add: if true, add, if false, delete | |
4e3b35b0 | 6970 | * |
2f4b411a AN |
6971 | * Add or delete a cloud filter for a specific flow spec using big buffer. |
6972 | * Returns 0 if the filter were successfully added. | |
4e3b35b0 | 6973 | **/ |
2f4b411a AN |
6974 | static int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, |
6975 | struct i40e_cloud_filter *filter, | |
6976 | bool add) | |
4e3b35b0 | 6977 | { |
2f4b411a AN |
6978 | struct i40e_aqc_cloud_filters_element_bb cld_filter; |
6979 | struct i40e_pf *pf = vsi->back; | |
6980 | int ret; | |
4e3b35b0 | 6981 | |
2f4b411a AN |
6982 | /* Both (src/dst) valid mac_addr are not supported */ |
6983 | if ((is_valid_ether_addr(filter->dst_mac) && | |
6984 | is_valid_ether_addr(filter->src_mac)) || | |
6985 | (is_multicast_ether_addr(filter->dst_mac) && | |
6986 | is_multicast_ether_addr(filter->src_mac))) | |
64e711ca | 6987 | return -EOPNOTSUPP; |
025b4a54 | 6988 | |
64e711ca AN |
6989 | /* Big buffer cloud filter needs 'L4 port' to be non-zero. Also, UDP |
6990 | * ports are not supported via big buffer now. | |
2f4b411a | 6991 | */ |
64e711ca AN |
6992 | if (!filter->dst_port || filter->ip_proto == IPPROTO_UDP) |
6993 | return -EOPNOTSUPP; | |
4d9b6043 | 6994 | |
2f4b411a AN |
6995 | /* adding filter using src_port/src_ip is not supported at this stage */ |
6996 | if (filter->src_port || filter->src_ipv4 || | |
6997 | !ipv6_addr_any(&filter->ip.v6.src_ip6)) | |
64e711ca | 6998 | return -EOPNOTSUPP; |
2f4b411a AN |
6999 | |
7000 | /* copy element needed to add cloud filter from filter */ | |
7001 | i40e_set_cld_element(filter, &cld_filter.element); | |
7002 | ||
7003 | if (is_valid_ether_addr(filter->dst_mac) || | |
7004 | is_valid_ether_addr(filter->src_mac) || | |
7005 | is_multicast_ether_addr(filter->dst_mac) || | |
7006 | is_multicast_ether_addr(filter->src_mac)) { | |
7007 | /* MAC + IP : unsupported mode */ | |
7008 | if (filter->dst_ipv4) | |
64e711ca | 7009 | return -EOPNOTSUPP; |
2f4b411a AN |
7010 | |
7011 | /* since we validated that L4 port must be valid before | |
7012 | * we get here, start with respective "flags" value | |
7013 | * and update if vlan is present or not | |
7014 | */ | |
7015 | cld_filter.element.flags = | |
7016 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT); | |
7017 | ||
7018 | if (filter->vlan_id) { | |
7019 | cld_filter.element.flags = | |
7020 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT); | |
4e3b35b0 | 7021 | } |
2f4b411a AN |
7022 | |
7023 | } else if (filter->dst_ipv4 || | |
7024 | !ipv6_addr_any(&filter->ip.v6.dst_ip6)) { | |
7025 | cld_filter.element.flags = | |
7026 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_IP_PORT); | |
7027 | if (filter->n_proto == ETH_P_IPV6) | |
7028 | cld_filter.element.flags |= | |
7029 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV6); | |
7030 | else | |
7031 | cld_filter.element.flags |= | |
7032 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV4); | |
014269ff | 7033 | } else { |
2f4b411a AN |
7034 | dev_err(&pf->pdev->dev, |
7035 | "either mac or ip has to be valid for cloud filter\n"); | |
7036 | return -EINVAL; | |
4e3b35b0 NP |
7037 | } |
7038 | ||
2f4b411a AN |
7039 | /* Now copy L4 port in Byte 6..7 in general fields */ |
7040 | cld_filter.general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0] = | |
7041 | be16_to_cpu(filter->dst_port); | |
7042 | ||
7043 | if (add) { | |
7044 | /* Validate current device switch mode, change if necessary */ | |
7045 | ret = i40e_validate_and_set_switch_mode(vsi); | |
7046 | if (ret) { | |
7047 | dev_err(&pf->pdev->dev, | |
7048 | "failed to set switch mode, ret %d\n", | |
7049 | ret); | |
7050 | return ret; | |
7051 | } | |
7052 | ||
7053 | ret = i40e_aq_add_cloud_filters_bb(&pf->hw, filter->seid, | |
7054 | &cld_filter, 1); | |
7055 | } else { | |
7056 | ret = i40e_aq_rem_cloud_filters_bb(&pf->hw, filter->seid, | |
7057 | &cld_filter, 1); | |
7058 | } | |
7059 | ||
7060 | if (ret) | |
7061 | dev_dbg(&pf->pdev->dev, | |
7062 | "Failed to %s cloud filter(big buffer) err %d aq_err %d\n", | |
7063 | add ? "add" : "delete", ret, pf->hw.aq.asq_last_status); | |
7064 | else | |
7065 | dev_info(&pf->pdev->dev, | |
7066 | "%s cloud filter for VSI: %d, L4 port: %d\n", | |
7067 | add ? "add" : "delete", filter->seid, | |
7068 | ntohs(filter->dst_port)); | |
7069 | return ret; | |
4e3b35b0 | 7070 | } |
2f4b411a | 7071 | |
cf05ed08 | 7072 | /** |
2f4b411a AN |
7073 | * i40e_parse_cls_flower - Parse tc flower filters provided by kernel |
7074 | * @vsi: Pointer to VSI | |
7075 | * @cls_flower: Pointer to struct tc_cls_flower_offload | |
7076 | * @filter: Pointer to cloud filter structure | |
7077 | * | |
7078 | **/ | |
7079 | static int i40e_parse_cls_flower(struct i40e_vsi *vsi, | |
7080 | struct tc_cls_flower_offload *f, | |
7081 | struct i40e_cloud_filter *filter) | |
cf05ed08 | 7082 | { |
2f4b411a AN |
7083 | u16 n_proto_mask = 0, n_proto_key = 0, addr_type = 0; |
7084 | struct i40e_pf *pf = vsi->back; | |
7085 | u8 field_flags = 0; | |
7086 | ||
7087 | if (f->dissector->used_keys & | |
7088 | ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | | |
7089 | BIT(FLOW_DISSECTOR_KEY_BASIC) | | |
7090 | BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | | |
7091 | BIT(FLOW_DISSECTOR_KEY_VLAN) | | |
7092 | BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | | |
7093 | BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | | |
7094 | BIT(FLOW_DISSECTOR_KEY_PORTS) | | |
7095 | BIT(FLOW_DISSECTOR_KEY_ENC_KEYID))) { | |
7096 | dev_err(&pf->pdev->dev, "Unsupported key used: 0x%x\n", | |
7097 | f->dissector->used_keys); | |
7098 | return -EOPNOTSUPP; | |
7099 | } | |
cf05ed08 | 7100 | |
2f4b411a AN |
7101 | if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) { |
7102 | struct flow_dissector_key_keyid *key = | |
7103 | skb_flow_dissector_target(f->dissector, | |
7104 | FLOW_DISSECTOR_KEY_ENC_KEYID, | |
7105 | f->key); | |
7ec9ba11 | 7106 | |
2f4b411a AN |
7107 | struct flow_dissector_key_keyid *mask = |
7108 | skb_flow_dissector_target(f->dissector, | |
7109 | FLOW_DISSECTOR_KEY_ENC_KEYID, | |
7110 | f->mask); | |
7111 | ||
7112 | if (mask->keyid != 0) | |
7113 | field_flags |= I40E_CLOUD_FIELD_TEN_ID; | |
7114 | ||
7115 | filter->tenant_id = be32_to_cpu(key->keyid); | |
cf05ed08 JB |
7116 | } |
7117 | ||
2f4b411a AN |
7118 | if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) { |
7119 | struct flow_dissector_key_basic *key = | |
7120 | skb_flow_dissector_target(f->dissector, | |
7121 | FLOW_DISSECTOR_KEY_BASIC, | |
7122 | f->key); | |
148c2d80 | 7123 | |
2f4b411a AN |
7124 | struct flow_dissector_key_basic *mask = |
7125 | skb_flow_dissector_target(f->dissector, | |
7126 | FLOW_DISSECTOR_KEY_BASIC, | |
7127 | f->mask); | |
7128 | ||
7129 | n_proto_key = ntohs(key->n_proto); | |
7130 | n_proto_mask = ntohs(mask->n_proto); | |
7131 | ||
7132 | if (n_proto_key == ETH_P_ALL) { | |
7133 | n_proto_key = 0; | |
7134 | n_proto_mask = 0; | |
7135 | } | |
7136 | filter->n_proto = n_proto_key & n_proto_mask; | |
7137 | filter->ip_proto = key->ip_proto; | |
cf05ed08 JB |
7138 | } |
7139 | ||
2f4b411a AN |
7140 | if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { |
7141 | struct flow_dissector_key_eth_addrs *key = | |
7142 | skb_flow_dissector_target(f->dissector, | |
7143 | FLOW_DISSECTOR_KEY_ETH_ADDRS, | |
7144 | f->key); | |
7145 | ||
7146 | struct flow_dissector_key_eth_addrs *mask = | |
7147 | skb_flow_dissector_target(f->dissector, | |
7148 | FLOW_DISSECTOR_KEY_ETH_ADDRS, | |
7149 | f->mask); | |
7150 | ||
7151 | /* use is_broadcast and is_zero to check for all 0xf or 0 */ | |
7152 | if (!is_zero_ether_addr(mask->dst)) { | |
7153 | if (is_broadcast_ether_addr(mask->dst)) { | |
7154 | field_flags |= I40E_CLOUD_FIELD_OMAC; | |
7155 | } else { | |
7156 | dev_err(&pf->pdev->dev, "Bad ether dest mask %pM\n", | |
7157 | mask->dst); | |
7158 | return I40E_ERR_CONFIG; | |
7159 | } | |
7160 | } | |
7161 | ||
7162 | if (!is_zero_ether_addr(mask->src)) { | |
7163 | if (is_broadcast_ether_addr(mask->src)) { | |
7164 | field_flags |= I40E_CLOUD_FIELD_IMAC; | |
7165 | } else { | |
7166 | dev_err(&pf->pdev->dev, "Bad ether src mask %pM\n", | |
7167 | mask->src); | |
7168 | return I40E_ERR_CONFIG; | |
7169 | } | |
7170 | } | |
7171 | ether_addr_copy(filter->dst_mac, key->dst); | |
7172 | ether_addr_copy(filter->src_mac, key->src); | |
cf05ed08 JB |
7173 | } |
7174 | ||
2f4b411a AN |
7175 | if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) { |
7176 | struct flow_dissector_key_vlan *key = | |
7177 | skb_flow_dissector_target(f->dissector, | |
7178 | FLOW_DISSECTOR_KEY_VLAN, | |
7179 | f->key); | |
7180 | struct flow_dissector_key_vlan *mask = | |
7181 | skb_flow_dissector_target(f->dissector, | |
7182 | FLOW_DISSECTOR_KEY_VLAN, | |
7183 | f->mask); | |
3e03d7cc | 7184 | |
2f4b411a AN |
7185 | if (mask->vlan_id) { |
7186 | if (mask->vlan_id == VLAN_VID_MASK) { | |
7187 | field_flags |= I40E_CLOUD_FIELD_IVLAN; | |
3e03d7cc | 7188 | |
2f4b411a AN |
7189 | } else { |
7190 | dev_err(&pf->pdev->dev, "Bad vlan mask 0x%04x\n", | |
7191 | mask->vlan_id); | |
7192 | return I40E_ERR_CONFIG; | |
7193 | } | |
7194 | } | |
68e49702 | 7195 | |
2f4b411a AN |
7196 | filter->vlan_id = cpu_to_be16(key->vlan_id); |
7197 | } | |
7198 | ||
7199 | if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) { | |
7200 | struct flow_dissector_key_control *key = | |
7201 | skb_flow_dissector_target(f->dissector, | |
7202 | FLOW_DISSECTOR_KEY_CONTROL, | |
7203 | f->key); | |
7204 | ||
7205 | addr_type = key->addr_type; | |
7206 | } | |
7207 | ||
7208 | if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { | |
7209 | struct flow_dissector_key_ipv4_addrs *key = | |
7210 | skb_flow_dissector_target(f->dissector, | |
7211 | FLOW_DISSECTOR_KEY_IPV4_ADDRS, | |
7212 | f->key); | |
7213 | struct flow_dissector_key_ipv4_addrs *mask = | |
7214 | skb_flow_dissector_target(f->dissector, | |
7215 | FLOW_DISSECTOR_KEY_IPV4_ADDRS, | |
7216 | f->mask); | |
7217 | ||
7218 | if (mask->dst) { | |
7219 | if (mask->dst == cpu_to_be32(0xffffffff)) { | |
7220 | field_flags |= I40E_CLOUD_FIELD_IIP; | |
7221 | } else { | |
7222 | mask->dst = be32_to_cpu(mask->dst); | |
7223 | dev_err(&pf->pdev->dev, "Bad ip dst mask %pI4\n", | |
7224 | &mask->dst); | |
7225 | return I40E_ERR_CONFIG; | |
7226 | } | |
7227 | } | |
7228 | ||
7229 | if (mask->src) { | |
7230 | if (mask->src == cpu_to_be32(0xffffffff)) { | |
7231 | field_flags |= I40E_CLOUD_FIELD_IIP; | |
7232 | } else { | |
7233 | mask->src = be32_to_cpu(mask->src); | |
7234 | dev_err(&pf->pdev->dev, "Bad ip src mask %pI4\n", | |
7235 | &mask->src); | |
7236 | return I40E_ERR_CONFIG; | |
7237 | } | |
7238 | } | |
7239 | ||
7240 | if (field_flags & I40E_CLOUD_FIELD_TEN_ID) { | |
7241 | dev_err(&pf->pdev->dev, "Tenant id not allowed for ip filter\n"); | |
7242 | return I40E_ERR_CONFIG; | |
7243 | } | |
7244 | filter->dst_ipv4 = key->dst; | |
7245 | filter->src_ipv4 = key->src; | |
7246 | } | |
7247 | ||
7248 | if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { | |
7249 | struct flow_dissector_key_ipv6_addrs *key = | |
7250 | skb_flow_dissector_target(f->dissector, | |
7251 | FLOW_DISSECTOR_KEY_IPV6_ADDRS, | |
7252 | f->key); | |
7253 | struct flow_dissector_key_ipv6_addrs *mask = | |
7254 | skb_flow_dissector_target(f->dissector, | |
7255 | FLOW_DISSECTOR_KEY_IPV6_ADDRS, | |
7256 | f->mask); | |
7257 | ||
7258 | /* src and dest IPV6 address should not be LOOPBACK | |
7259 | * (0:0:0:0:0:0:0:1), which can be represented as ::1 | |
68e49702 | 7260 | */ |
2f4b411a AN |
7261 | if (ipv6_addr_loopback(&key->dst) || |
7262 | ipv6_addr_loopback(&key->src)) { | |
7263 | dev_err(&pf->pdev->dev, | |
7264 | "Bad ipv6, addr is LOOPBACK\n"); | |
7265 | return I40E_ERR_CONFIG; | |
7266 | } | |
7267 | if (!ipv6_addr_any(&mask->dst) || !ipv6_addr_any(&mask->src)) | |
7268 | field_flags |= I40E_CLOUD_FIELD_IIP; | |
7269 | ||
7270 | memcpy(&filter->src_ipv6, &key->src.s6_addr32, | |
7271 | sizeof(filter->src_ipv6)); | |
7272 | memcpy(&filter->dst_ipv6, &key->dst.s6_addr32, | |
7273 | sizeof(filter->dst_ipv6)); | |
7274 | } | |
7275 | ||
7276 | if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) { | |
7277 | struct flow_dissector_key_ports *key = | |
7278 | skb_flow_dissector_target(f->dissector, | |
7279 | FLOW_DISSECTOR_KEY_PORTS, | |
7280 | f->key); | |
7281 | struct flow_dissector_key_ports *mask = | |
7282 | skb_flow_dissector_target(f->dissector, | |
7283 | FLOW_DISSECTOR_KEY_PORTS, | |
7284 | f->mask); | |
7285 | ||
7286 | if (mask->src) { | |
7287 | if (mask->src == cpu_to_be16(0xffff)) { | |
7288 | field_flags |= I40E_CLOUD_FIELD_IIP; | |
7289 | } else { | |
7290 | dev_err(&pf->pdev->dev, "Bad src port mask 0x%04x\n", | |
7291 | be16_to_cpu(mask->src)); | |
7292 | return I40E_ERR_CONFIG; | |
7293 | } | |
7294 | } | |
7295 | ||
7296 | if (mask->dst) { | |
7297 | if (mask->dst == cpu_to_be16(0xffff)) { | |
7298 | field_flags |= I40E_CLOUD_FIELD_IIP; | |
7299 | } else { | |
7300 | dev_err(&pf->pdev->dev, "Bad dst port mask 0x%04x\n", | |
7301 | be16_to_cpu(mask->dst)); | |
7302 | return I40E_ERR_CONFIG; | |
7303 | } | |
7304 | } | |
7305 | ||
7306 | filter->dst_port = key->dst; | |
7307 | filter->src_port = key->src; | |
7308 | ||
7309 | switch (filter->ip_proto) { | |
7310 | case IPPROTO_TCP: | |
7311 | case IPPROTO_UDP: | |
7312 | break; | |
7313 | default: | |
7314 | dev_err(&pf->pdev->dev, | |
7315 | "Only UDP and TCP transport are supported\n"); | |
7316 | return -EINVAL; | |
68e49702 | 7317 | } |
3e03d7cc | 7318 | } |
2f4b411a AN |
7319 | filter->flags = field_flags; |
7320 | return 0; | |
7321 | } | |
3e03d7cc | 7322 | |
2f4b411a AN |
7323 | /** |
7324 | * i40e_handle_tclass: Forward to a traffic class on the device | |
7325 | * @vsi: Pointer to VSI | |
7326 | * @tc: traffic class index on the device | |
7327 | * @filter: Pointer to cloud filter structure | |
7328 | * | |
7329 | **/ | |
7330 | static int i40e_handle_tclass(struct i40e_vsi *vsi, u32 tc, | |
7331 | struct i40e_cloud_filter *filter) | |
7332 | { | |
7333 | struct i40e_channel *ch, *ch_tmp; | |
7334 | ||
7335 | /* direct to a traffic class on the same device */ | |
7336 | if (tc == 0) { | |
7337 | filter->seid = vsi->seid; | |
7338 | return 0; | |
7339 | } else if (vsi->tc_config.enabled_tc & BIT(tc)) { | |
7340 | if (!filter->dst_port) { | |
7341 | dev_err(&vsi->back->pdev->dev, | |
7342 | "Specify destination port to direct to traffic class that is not default\n"); | |
7343 | return -EINVAL; | |
7344 | } | |
7345 | if (list_empty(&vsi->ch_list)) | |
7346 | return -EINVAL; | |
7347 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, | |
7348 | list) { | |
7349 | if (ch->seid == vsi->tc_seid_map[tc]) | |
7350 | filter->seid = ch->seid; | |
7351 | } | |
7352 | return 0; | |
7353 | } | |
7354 | dev_err(&vsi->back->pdev->dev, "TC is not enabled\n"); | |
7355 | return -EINVAL; | |
cf05ed08 | 7356 | } |
4e3b35b0 | 7357 | |
41c445ff | 7358 | /** |
2f4b411a AN |
7359 | * i40e_configure_clsflower - Configure tc flower filters |
7360 | * @vsi: Pointer to VSI | |
7361 | * @cls_flower: Pointer to struct tc_cls_flower_offload | |
7362 | * | |
41c445ff | 7363 | **/ |
2f4b411a AN |
7364 | static int i40e_configure_clsflower(struct i40e_vsi *vsi, |
7365 | struct tc_cls_flower_offload *cls_flower) | |
41c445ff | 7366 | { |
2f4b411a AN |
7367 | int tc = tc_classid_to_hwtc(vsi->netdev, cls_flower->classid); |
7368 | struct i40e_cloud_filter *filter = NULL; | |
41c445ff | 7369 | struct i40e_pf *pf = vsi->back; |
2f4b411a | 7370 | int err = 0; |
41c445ff | 7371 | |
2f4b411a AN |
7372 | if (tc < 0) { |
7373 | dev_err(&vsi->back->pdev->dev, "Invalid traffic class\n"); | |
bc4244c6 | 7374 | return -EOPNOTSUPP; |
2f4b411a | 7375 | } |
41c445ff | 7376 | |
2f4b411a AN |
7377 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) || |
7378 | test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) | |
7379 | return -EBUSY; | |
41c445ff | 7380 | |
2f4b411a AN |
7381 | if (pf->fdir_pf_active_filters || |
7382 | (!hlist_empty(&pf->fdir_filter_list))) { | |
7383 | dev_err(&vsi->back->pdev->dev, | |
7384 | "Flow Director Sideband filters exists, turn ntuple off to configure cloud filters\n"); | |
7385 | return -EINVAL; | |
7386 | } | |
41c445ff | 7387 | |
2f4b411a AN |
7388 | if (vsi->back->flags & I40E_FLAG_FD_SB_ENABLED) { |
7389 | dev_err(&vsi->back->pdev->dev, | |
7390 | "Disable Flow Director Sideband, configuring Cloud filters via tc-flower\n"); | |
7391 | vsi->back->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
7392 | vsi->back->flags |= I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
41c445ff | 7393 | } |
ca64fa4e | 7394 | |
2f4b411a AN |
7395 | filter = kzalloc(sizeof(*filter), GFP_KERNEL); |
7396 | if (!filter) | |
7397 | return -ENOMEM; | |
7398 | ||
7399 | filter->cookie = cls_flower->cookie; | |
7400 | ||
7401 | err = i40e_parse_cls_flower(vsi, cls_flower, filter); | |
7402 | if (err < 0) | |
7403 | goto err; | |
7404 | ||
7405 | err = i40e_handle_tclass(vsi, tc, filter); | |
7406 | if (err < 0) | |
7407 | goto err; | |
7408 | ||
7409 | /* Add cloud filter */ | |
7410 | if (filter->dst_port) | |
7411 | err = i40e_add_del_cloud_filter_big_buf(vsi, filter, true); | |
7412 | else | |
7413 | err = i40e_add_del_cloud_filter(vsi, filter, true); | |
7414 | ||
7415 | if (err) { | |
7416 | dev_err(&pf->pdev->dev, | |
7417 | "Failed to add cloud filter, err %s\n", | |
7418 | i40e_stat_str(&pf->hw, err)); | |
2f4b411a | 7419 | goto err; |
1e1be8f6 | 7420 | } |
e3219ce6 | 7421 | |
2f4b411a AN |
7422 | /* add filter to the ordered list */ |
7423 | INIT_HLIST_NODE(&filter->cloud_node); | |
41c445ff | 7424 | |
2f4b411a AN |
7425 | hlist_add_head(&filter->cloud_node, &pf->cloud_filter_list); |
7426 | ||
7427 | pf->num_cloud_filters++; | |
7428 | ||
7429 | return err; | |
7430 | err: | |
7431 | kfree(filter); | |
7432 | return err; | |
41c445ff JB |
7433 | } |
7434 | ||
7435 | /** | |
2f4b411a AN |
7436 | * i40e_find_cloud_filter - Find the could filter in the list |
7437 | * @vsi: Pointer to VSI | |
7438 | * @cookie: filter specific cookie | |
41c445ff | 7439 | * |
41c445ff | 7440 | **/ |
2f4b411a AN |
7441 | static struct i40e_cloud_filter *i40e_find_cloud_filter(struct i40e_vsi *vsi, |
7442 | unsigned long *cookie) | |
41c445ff | 7443 | { |
2f4b411a AN |
7444 | struct i40e_cloud_filter *filter = NULL; |
7445 | struct hlist_node *node2; | |
41c445ff | 7446 | |
2f4b411a AN |
7447 | hlist_for_each_entry_safe(filter, node2, |
7448 | &vsi->back->cloud_filter_list, cloud_node) | |
7449 | if (!memcmp(cookie, &filter->cookie, sizeof(filter->cookie))) | |
7450 | return filter; | |
7451 | return NULL; | |
41c445ff JB |
7452 | } |
7453 | ||
7454 | /** | |
2f4b411a AN |
7455 | * i40e_delete_clsflower - Remove tc flower filters |
7456 | * @vsi: Pointer to VSI | |
7457 | * @cls_flower: Pointer to struct tc_cls_flower_offload | |
7458 | * | |
41c445ff | 7459 | **/ |
2f4b411a AN |
7460 | static int i40e_delete_clsflower(struct i40e_vsi *vsi, |
7461 | struct tc_cls_flower_offload *cls_flower) | |
41c445ff | 7462 | { |
2f4b411a AN |
7463 | struct i40e_cloud_filter *filter = NULL; |
7464 | struct i40e_pf *pf = vsi->back; | |
7465 | int err = 0; | |
41c445ff | 7466 | |
2f4b411a | 7467 | filter = i40e_find_cloud_filter(vsi, &cls_flower->cookie); |
41c445ff | 7468 | |
2f4b411a AN |
7469 | if (!filter) |
7470 | return -EINVAL; | |
41c445ff | 7471 | |
2f4b411a | 7472 | hash_del(&filter->cloud_node); |
41c445ff | 7473 | |
2f4b411a AN |
7474 | if (filter->dst_port) |
7475 | err = i40e_add_del_cloud_filter_big_buf(vsi, filter, false); | |
7476 | else | |
7477 | err = i40e_add_del_cloud_filter(vsi, filter, false); | |
41c445ff | 7478 | |
2f4b411a AN |
7479 | kfree(filter); |
7480 | if (err) { | |
7481 | dev_err(&pf->pdev->dev, | |
7482 | "Failed to delete cloud filter, err %s\n", | |
7483 | i40e_stat_str(&pf->hw, err)); | |
7484 | return i40e_aq_rc_to_posix(err, pf->hw.aq.asq_last_status); | |
41c445ff | 7485 | } |
f980d445 | 7486 | |
2f4b411a AN |
7487 | pf->num_cloud_filters--; |
7488 | if (!pf->num_cloud_filters) | |
7489 | if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) && | |
7490 | !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) { | |
7491 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
7492 | pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
7493 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; | |
7494 | } | |
7495 | return 0; | |
41c445ff JB |
7496 | } |
7497 | ||
7498 | /** | |
2f4b411a | 7499 | * i40e_setup_tc_cls_flower - flower classifier offloads |
41c445ff | 7500 | * @netdev: net device to configure |
2f4b411a | 7501 | * @type_data: offload data |
41c445ff | 7502 | **/ |
2f4b411a AN |
7503 | static int i40e_setup_tc_cls_flower(struct i40e_netdev_priv *np, |
7504 | struct tc_cls_flower_offload *cls_flower) | |
41c445ff | 7505 | { |
41c445ff | 7506 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 7507 | |
2f4b411a AN |
7508 | if (cls_flower->common.chain_index) |
7509 | return -EOPNOTSUPP; | |
41c445ff | 7510 | |
2f4b411a AN |
7511 | switch (cls_flower->command) { |
7512 | case TC_CLSFLOWER_REPLACE: | |
7513 | return i40e_configure_clsflower(vsi, cls_flower); | |
7514 | case TC_CLSFLOWER_DESTROY: | |
7515 | return i40e_delete_clsflower(vsi, cls_flower); | |
7516 | case TC_CLSFLOWER_STATS: | |
7517 | return -EOPNOTSUPP; | |
7518 | default: | |
7519 | return -EINVAL; | |
41c445ff | 7520 | } |
2f4b411a | 7521 | } |
41c445ff | 7522 | |
2f4b411a AN |
7523 | static int i40e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
7524 | void *cb_priv) | |
7525 | { | |
7526 | struct i40e_netdev_priv *np = cb_priv; | |
41c445ff | 7527 | |
2f4b411a AN |
7528 | switch (type) { |
7529 | case TC_SETUP_CLSFLOWER: | |
7530 | return i40e_setup_tc_cls_flower(np, type_data); | |
41c445ff | 7531 | |
2f4b411a AN |
7532 | default: |
7533 | return -EOPNOTSUPP; | |
41c445ff | 7534 | } |
2f4b411a | 7535 | } |
41c445ff | 7536 | |
2f4b411a AN |
7537 | static int i40e_setup_tc_block(struct net_device *dev, |
7538 | struct tc_block_offload *f) | |
7539 | { | |
7540 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
41c445ff | 7541 | |
2f4b411a AN |
7542 | if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) |
7543 | return -EOPNOTSUPP; | |
7544 | ||
7545 | switch (f->command) { | |
7546 | case TC_BLOCK_BIND: | |
7547 | return tcf_block_cb_register(f->block, i40e_setup_tc_block_cb, | |
7548 | np, np); | |
7549 | case TC_BLOCK_UNBIND: | |
7550 | tcf_block_cb_unregister(f->block, i40e_setup_tc_block_cb, np); | |
7551 | return 0; | |
7552 | default: | |
7553 | return -EOPNOTSUPP; | |
7554 | } | |
41c445ff JB |
7555 | } |
7556 | ||
2572ac53 | 7557 | static int __i40e_setup_tc(struct net_device *netdev, enum tc_setup_type type, |
de4784ca | 7558 | void *type_data) |
e4c6734e | 7559 | { |
2f4b411a | 7560 | switch (type) { |
575ed7d3 | 7561 | case TC_SETUP_QDISC_MQPRIO: |
2f4b411a AN |
7562 | return i40e_setup_tc(netdev, type_data); |
7563 | case TC_SETUP_BLOCK: | |
7564 | return i40e_setup_tc_block(netdev, type_data); | |
7565 | default: | |
38cf0426 | 7566 | return -EOPNOTSUPP; |
2f4b411a | 7567 | } |
e4c6734e JF |
7568 | } |
7569 | ||
41c445ff JB |
7570 | /** |
7571 | * i40e_open - Called when a network interface is made active | |
7572 | * @netdev: network interface device structure | |
7573 | * | |
7574 | * The open entry point is called when a network interface is made | |
7575 | * active by the system (IFF_UP). At this point all resources needed | |
7576 | * for transmit and receive operations are allocated, the interrupt | |
7577 | * handler is registered with the OS, the netdev watchdog subtask is | |
7578 | * enabled, and the stack is notified that the interface is ready. | |
7579 | * | |
7580 | * Returns 0 on success, negative value on failure | |
7581 | **/ | |
38e00438 | 7582 | int i40e_open(struct net_device *netdev) |
41c445ff JB |
7583 | { |
7584 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
7585 | struct i40e_vsi *vsi = np->vsi; | |
7586 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
7587 | int err; |
7588 | ||
4eb3f768 | 7589 | /* disallow open during test or if eeprom is broken */ |
0da36b97 JK |
7590 | if (test_bit(__I40E_TESTING, pf->state) || |
7591 | test_bit(__I40E_BAD_EEPROM, pf->state)) | |
41c445ff JB |
7592 | return -EBUSY; |
7593 | ||
7594 | netif_carrier_off(netdev); | |
7595 | ||
6c167f58 EK |
7596 | err = i40e_vsi_open(vsi); |
7597 | if (err) | |
7598 | return err; | |
7599 | ||
059dab69 JB |
7600 | /* configure global TSO hardware offload settings */ |
7601 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH | | |
7602 | TCP_FLAG_FIN) >> 16); | |
7603 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH | | |
7604 | TCP_FLAG_FIN | | |
7605 | TCP_FLAG_CWR) >> 16); | |
7606 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16); | |
7607 | ||
06a5f7f1 | 7608 | udp_tunnel_get_rx_info(netdev); |
e3219ce6 | 7609 | |
6c167f58 EK |
7610 | return 0; |
7611 | } | |
7612 | ||
7613 | /** | |
7614 | * i40e_vsi_open - | |
7615 | * @vsi: the VSI to open | |
7616 | * | |
7617 | * Finish initialization of the VSI. | |
7618 | * | |
7619 | * Returns 0 on success, negative value on failure | |
373149fc MS |
7620 | * |
7621 | * Note: expects to be called while under rtnl_lock() | |
6c167f58 EK |
7622 | **/ |
7623 | int i40e_vsi_open(struct i40e_vsi *vsi) | |
7624 | { | |
7625 | struct i40e_pf *pf = vsi->back; | |
b294ac70 | 7626 | char int_name[I40E_INT_NAME_STR_LEN]; |
6c167f58 EK |
7627 | int err; |
7628 | ||
41c445ff JB |
7629 | /* allocate descriptors */ |
7630 | err = i40e_vsi_setup_tx_resources(vsi); | |
7631 | if (err) | |
7632 | goto err_setup_tx; | |
7633 | err = i40e_vsi_setup_rx_resources(vsi); | |
7634 | if (err) | |
7635 | goto err_setup_rx; | |
7636 | ||
7637 | err = i40e_vsi_configure(vsi); | |
7638 | if (err) | |
7639 | goto err_setup_rx; | |
7640 | ||
c22e3c6c SN |
7641 | if (vsi->netdev) { |
7642 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s", | |
7643 | dev_driver_string(&pf->pdev->dev), vsi->netdev->name); | |
7644 | err = i40e_vsi_request_irq(vsi, int_name); | |
7645 | if (err) | |
7646 | goto err_setup_rx; | |
41c445ff | 7647 | |
c22e3c6c SN |
7648 | /* Notify the stack of the actual queue counts. */ |
7649 | err = netif_set_real_num_tx_queues(vsi->netdev, | |
7650 | vsi->num_queue_pairs); | |
7651 | if (err) | |
7652 | goto err_set_queues; | |
25946ddb | 7653 | |
c22e3c6c SN |
7654 | err = netif_set_real_num_rx_queues(vsi->netdev, |
7655 | vsi->num_queue_pairs); | |
7656 | if (err) | |
7657 | goto err_set_queues; | |
8a9eb7d3 SN |
7658 | |
7659 | } else if (vsi->type == I40E_VSI_FDIR) { | |
e240f674 | 7660 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir", |
b2008cbf CW |
7661 | dev_driver_string(&pf->pdev->dev), |
7662 | dev_name(&pf->pdev->dev)); | |
8a9eb7d3 | 7663 | err = i40e_vsi_request_irq(vsi, int_name); |
b2008cbf | 7664 | |
c22e3c6c | 7665 | } else { |
ce9ccb17 | 7666 | err = -EINVAL; |
6c167f58 EK |
7667 | goto err_setup_rx; |
7668 | } | |
25946ddb | 7669 | |
41c445ff JB |
7670 | err = i40e_up_complete(vsi); |
7671 | if (err) | |
7672 | goto err_up_complete; | |
7673 | ||
41c445ff JB |
7674 | return 0; |
7675 | ||
7676 | err_up_complete: | |
7677 | i40e_down(vsi); | |
25946ddb | 7678 | err_set_queues: |
41c445ff JB |
7679 | i40e_vsi_free_irq(vsi); |
7680 | err_setup_rx: | |
7681 | i40e_vsi_free_rx_resources(vsi); | |
7682 | err_setup_tx: | |
7683 | i40e_vsi_free_tx_resources(vsi); | |
7684 | if (vsi == pf->vsi[pf->lan_vsi]) | |
ff424188 | 7685 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
41c445ff JB |
7686 | |
7687 | return err; | |
7688 | } | |
7689 | ||
17a73f6b JG |
7690 | /** |
7691 | * i40e_fdir_filter_exit - Cleans up the Flow Director accounting | |
b40c82e6 | 7692 | * @pf: Pointer to PF |
17a73f6b JG |
7693 | * |
7694 | * This function destroys the hlist where all the Flow Director | |
7695 | * filters were saved. | |
7696 | **/ | |
7697 | static void i40e_fdir_filter_exit(struct i40e_pf *pf) | |
7698 | { | |
7699 | struct i40e_fdir_filter *filter; | |
0e588de1 | 7700 | struct i40e_flex_pit *pit_entry, *tmp; |
17a73f6b JG |
7701 | struct hlist_node *node2; |
7702 | ||
7703 | hlist_for_each_entry_safe(filter, node2, | |
7704 | &pf->fdir_filter_list, fdir_node) { | |
7705 | hlist_del(&filter->fdir_node); | |
7706 | kfree(filter); | |
7707 | } | |
097dbf52 | 7708 | |
0e588de1 JK |
7709 | list_for_each_entry_safe(pit_entry, tmp, &pf->l3_flex_pit_list, list) { |
7710 | list_del(&pit_entry->list); | |
7711 | kfree(pit_entry); | |
7712 | } | |
7713 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); | |
7714 | ||
7715 | list_for_each_entry_safe(pit_entry, tmp, &pf->l4_flex_pit_list, list) { | |
7716 | list_del(&pit_entry->list); | |
7717 | kfree(pit_entry); | |
7718 | } | |
7719 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
7720 | ||
17a73f6b | 7721 | pf->fdir_pf_active_filters = 0; |
097dbf52 JK |
7722 | pf->fd_tcp4_filter_cnt = 0; |
7723 | pf->fd_udp4_filter_cnt = 0; | |
f223c875 | 7724 | pf->fd_sctp4_filter_cnt = 0; |
097dbf52 | 7725 | pf->fd_ip4_filter_cnt = 0; |
3bcee1e6 JK |
7726 | |
7727 | /* Reprogram the default input set for TCP/IPv4 */ | |
7728 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP, | |
7729 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
7730 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
7731 | ||
7732 | /* Reprogram the default input set for UDP/IPv4 */ | |
7733 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_UDP, | |
7734 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
7735 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
7736 | ||
7737 | /* Reprogram the default input set for SCTP/IPv4 */ | |
7738 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, | |
7739 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
7740 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
7741 | ||
7742 | /* Reprogram the default input set for Other/IPv4 */ | |
7743 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, | |
7744 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
17a73f6b JG |
7745 | } |
7746 | ||
aaf66502 AN |
7747 | /** |
7748 | * i40e_cloud_filter_exit - Cleans up the cloud filters | |
7749 | * @pf: Pointer to PF | |
7750 | * | |
7751 | * This function destroys the hlist where all the cloud filters | |
7752 | * were saved. | |
7753 | **/ | |
7754 | static void i40e_cloud_filter_exit(struct i40e_pf *pf) | |
7755 | { | |
7756 | struct i40e_cloud_filter *cfilter; | |
7757 | struct hlist_node *node; | |
7758 | ||
7759 | hlist_for_each_entry_safe(cfilter, node, | |
7760 | &pf->cloud_filter_list, cloud_node) { | |
7761 | hlist_del(&cfilter->cloud_node); | |
7762 | kfree(cfilter); | |
7763 | } | |
7764 | pf->num_cloud_filters = 0; | |
2f4b411a AN |
7765 | |
7766 | if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) && | |
7767 | !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) { | |
7768 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
7769 | pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
7770 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; | |
7771 | } | |
aaf66502 AN |
7772 | } |
7773 | ||
41c445ff JB |
7774 | /** |
7775 | * i40e_close - Disables a network interface | |
7776 | * @netdev: network interface device structure | |
7777 | * | |
7778 | * The close entry point is called when an interface is de-activated | |
7779 | * by the OS. The hardware is still under the driver's control, but | |
7780 | * this netdev interface is disabled. | |
7781 | * | |
7782 | * Returns 0, this is not allowed to fail | |
7783 | **/ | |
38e00438 | 7784 | int i40e_close(struct net_device *netdev) |
41c445ff JB |
7785 | { |
7786 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
7787 | struct i40e_vsi *vsi = np->vsi; | |
7788 | ||
90ef8d47 | 7789 | i40e_vsi_close(vsi); |
41c445ff JB |
7790 | |
7791 | return 0; | |
7792 | } | |
7793 | ||
7794 | /** | |
7795 | * i40e_do_reset - Start a PF or Core Reset sequence | |
7796 | * @pf: board private structure | |
7797 | * @reset_flags: which reset is requested | |
373149fc MS |
7798 | * @lock_acquired: indicates whether or not the lock has been acquired |
7799 | * before this function was called. | |
41c445ff JB |
7800 | * |
7801 | * The essential difference in resets is that the PF Reset | |
7802 | * doesn't clear the packet buffers, doesn't reset the PE | |
7803 | * firmware, and doesn't bother the other PFs on the chip. | |
7804 | **/ | |
373149fc | 7805 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired) |
41c445ff JB |
7806 | { |
7807 | u32 val; | |
7808 | ||
7809 | WARN_ON(in_interrupt()); | |
7810 | ||
263fc48f | 7811 | |
41c445ff | 7812 | /* do the biggest reset indicated */ |
41a1d04b | 7813 | if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { |
41c445ff JB |
7814 | |
7815 | /* Request a Global Reset | |
7816 | * | |
7817 | * This will start the chip's countdown to the actual full | |
7818 | * chip reset event, and a warning interrupt to be sent | |
7819 | * to all PFs, including the requestor. Our handler | |
7820 | * for the warning interrupt will deal with the shutdown | |
7821 | * and recovery of the switch setup. | |
7822 | */ | |
69bfb110 | 7823 | dev_dbg(&pf->pdev->dev, "GlobalR requested\n"); |
41c445ff JB |
7824 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
7825 | val |= I40E_GLGEN_RTRIG_GLOBR_MASK; | |
7826 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
7827 | ||
41a1d04b | 7828 | } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) { |
41c445ff JB |
7829 | |
7830 | /* Request a Core Reset | |
7831 | * | |
7832 | * Same as Global Reset, except does *not* include the MAC/PHY | |
7833 | */ | |
69bfb110 | 7834 | dev_dbg(&pf->pdev->dev, "CoreR requested\n"); |
41c445ff JB |
7835 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
7836 | val |= I40E_GLGEN_RTRIG_CORER_MASK; | |
7837 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
7838 | i40e_flush(&pf->hw); | |
7839 | ||
ff424188 | 7840 | } else if (reset_flags & I40E_PF_RESET_FLAG) { |
41c445ff JB |
7841 | |
7842 | /* Request a PF Reset | |
7843 | * | |
7844 | * Resets only the PF-specific registers | |
7845 | * | |
7846 | * This goes directly to the tear-down and rebuild of | |
7847 | * the switch, since we need to do all the recovery as | |
7848 | * for the Core Reset. | |
7849 | */ | |
69bfb110 | 7850 | dev_dbg(&pf->pdev->dev, "PFR requested\n"); |
373149fc | 7851 | i40e_handle_reset_warning(pf, lock_acquired); |
41c445ff | 7852 | |
41a1d04b | 7853 | } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) { |
41c445ff JB |
7854 | int v; |
7855 | ||
7856 | /* Find the VSI(s) that requested a re-init */ | |
7857 | dev_info(&pf->pdev->dev, | |
7858 | "VSI reinit requested\n"); | |
505682cd | 7859 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 7860 | struct i40e_vsi *vsi = pf->vsi[v]; |
6995b36c | 7861 | |
41c445ff | 7862 | if (vsi != NULL && |
d19cb64b | 7863 | test_and_clear_bit(__I40E_VSI_REINIT_REQUESTED, |
0da36b97 | 7864 | vsi->state)) |
41c445ff | 7865 | i40e_vsi_reinit_locked(pf->vsi[v]); |
41c445ff | 7866 | } |
41a1d04b | 7867 | } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) { |
b5d06f05 NP |
7868 | int v; |
7869 | ||
7870 | /* Find the VSI(s) that needs to be brought down */ | |
7871 | dev_info(&pf->pdev->dev, "VSI down requested\n"); | |
7872 | for (v = 0; v < pf->num_alloc_vsi; v++) { | |
7873 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 7874 | |
b5d06f05 | 7875 | if (vsi != NULL && |
d19cb64b | 7876 | test_and_clear_bit(__I40E_VSI_DOWN_REQUESTED, |
0da36b97 JK |
7877 | vsi->state)) { |
7878 | set_bit(__I40E_VSI_DOWN, vsi->state); | |
b5d06f05 | 7879 | i40e_down(vsi); |
b5d06f05 NP |
7880 | } |
7881 | } | |
41c445ff JB |
7882 | } else { |
7883 | dev_info(&pf->pdev->dev, | |
7884 | "bad reset request 0x%08x\n", reset_flags); | |
41c445ff JB |
7885 | } |
7886 | } | |
7887 | ||
4e3b35b0 NP |
7888 | #ifdef CONFIG_I40E_DCB |
7889 | /** | |
7890 | * i40e_dcb_need_reconfig - Check if DCB needs reconfig | |
7891 | * @pf: board private structure | |
7892 | * @old_cfg: current DCB config | |
7893 | * @new_cfg: new DCB config | |
7894 | **/ | |
7895 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
7896 | struct i40e_dcbx_config *old_cfg, | |
7897 | struct i40e_dcbx_config *new_cfg) | |
7898 | { | |
7899 | bool need_reconfig = false; | |
7900 | ||
7901 | /* Check if ETS configuration has changed */ | |
7902 | if (memcmp(&new_cfg->etscfg, | |
7903 | &old_cfg->etscfg, | |
7904 | sizeof(new_cfg->etscfg))) { | |
7905 | /* If Priority Table has changed reconfig is needed */ | |
7906 | if (memcmp(&new_cfg->etscfg.prioritytable, | |
7907 | &old_cfg->etscfg.prioritytable, | |
7908 | sizeof(new_cfg->etscfg.prioritytable))) { | |
7909 | need_reconfig = true; | |
69bfb110 | 7910 | dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n"); |
4e3b35b0 NP |
7911 | } |
7912 | ||
7913 | if (memcmp(&new_cfg->etscfg.tcbwtable, | |
7914 | &old_cfg->etscfg.tcbwtable, | |
7915 | sizeof(new_cfg->etscfg.tcbwtable))) | |
69bfb110 | 7916 | dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n"); |
4e3b35b0 NP |
7917 | |
7918 | if (memcmp(&new_cfg->etscfg.tsatable, | |
7919 | &old_cfg->etscfg.tsatable, | |
7920 | sizeof(new_cfg->etscfg.tsatable))) | |
69bfb110 | 7921 | dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n"); |
4e3b35b0 NP |
7922 | } |
7923 | ||
7924 | /* Check if PFC configuration has changed */ | |
7925 | if (memcmp(&new_cfg->pfc, | |
7926 | &old_cfg->pfc, | |
7927 | sizeof(new_cfg->pfc))) { | |
7928 | need_reconfig = true; | |
69bfb110 | 7929 | dev_dbg(&pf->pdev->dev, "PFC config change detected.\n"); |
4e3b35b0 NP |
7930 | } |
7931 | ||
7932 | /* Check if APP Table has changed */ | |
7933 | if (memcmp(&new_cfg->app, | |
7934 | &old_cfg->app, | |
3d9667a9 | 7935 | sizeof(new_cfg->app))) { |
4e3b35b0 | 7936 | need_reconfig = true; |
69bfb110 | 7937 | dev_dbg(&pf->pdev->dev, "APP Table change detected.\n"); |
3d9667a9 | 7938 | } |
4e3b35b0 | 7939 | |
fb43201f | 7940 | dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig); |
4e3b35b0 NP |
7941 | return need_reconfig; |
7942 | } | |
7943 | ||
7944 | /** | |
7945 | * i40e_handle_lldp_event - Handle LLDP Change MIB event | |
7946 | * @pf: board private structure | |
7947 | * @e: event info posted on ARQ | |
7948 | **/ | |
7949 | static int i40e_handle_lldp_event(struct i40e_pf *pf, | |
7950 | struct i40e_arq_event_info *e) | |
7951 | { | |
7952 | struct i40e_aqc_lldp_get_mib *mib = | |
7953 | (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; | |
7954 | struct i40e_hw *hw = &pf->hw; | |
4e3b35b0 NP |
7955 | struct i40e_dcbx_config tmp_dcbx_cfg; |
7956 | bool need_reconfig = false; | |
7957 | int ret = 0; | |
7958 | u8 type; | |
7959 | ||
4d9b6043 | 7960 | /* Not DCB capable or capability disabled */ |
ea6acb7e | 7961 | if (!(pf->flags & I40E_FLAG_DCB_CAPABLE)) |
4d9b6043 NP |
7962 | return ret; |
7963 | ||
4e3b35b0 NP |
7964 | /* Ignore if event is not for Nearest Bridge */ |
7965 | type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) | |
7966 | & I40E_AQ_LLDP_BRIDGE_TYPE_MASK); | |
fb43201f | 7967 | dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type); |
4e3b35b0 NP |
7968 | if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE) |
7969 | return ret; | |
7970 | ||
7971 | /* Check MIB Type and return if event for Remote MIB update */ | |
7972 | type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK; | |
9fa61dd2 | 7973 | dev_dbg(&pf->pdev->dev, |
fb43201f | 7974 | "LLDP event mib type %s\n", type ? "remote" : "local"); |
4e3b35b0 NP |
7975 | if (type == I40E_AQ_LLDP_MIB_REMOTE) { |
7976 | /* Update the remote cached instance and return */ | |
7977 | ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, | |
7978 | I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, | |
7979 | &hw->remote_dcbx_config); | |
7980 | goto exit; | |
7981 | } | |
7982 | ||
9fa61dd2 | 7983 | /* Store the old configuration */ |
1a2f6248 | 7984 | tmp_dcbx_cfg = hw->local_dcbx_config; |
9fa61dd2 | 7985 | |
750fcbcf NP |
7986 | /* Reset the old DCBx configuration data */ |
7987 | memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config)); | |
9fa61dd2 NP |
7988 | /* Get updated DCBX data from firmware */ |
7989 | ret = i40e_get_dcb_config(&pf->hw); | |
4e3b35b0 | 7990 | if (ret) { |
f1c7e72e SN |
7991 | dev_info(&pf->pdev->dev, |
7992 | "Failed querying DCB configuration data from firmware, err %s aq_err %s\n", | |
7993 | i40e_stat_str(&pf->hw, ret), | |
7994 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
7995 | goto exit; |
7996 | } | |
7997 | ||
7998 | /* No change detected in DCBX configs */ | |
750fcbcf NP |
7999 | if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config, |
8000 | sizeof(tmp_dcbx_cfg))) { | |
69bfb110 | 8001 | dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n"); |
4e3b35b0 NP |
8002 | goto exit; |
8003 | } | |
8004 | ||
750fcbcf NP |
8005 | need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, |
8006 | &hw->local_dcbx_config); | |
4e3b35b0 | 8007 | |
750fcbcf | 8008 | i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config); |
4e3b35b0 NP |
8009 | |
8010 | if (!need_reconfig) | |
8011 | goto exit; | |
8012 | ||
4d9b6043 | 8013 | /* Enable DCB tagging only when more than one TC */ |
750fcbcf | 8014 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
4d9b6043 NP |
8015 | pf->flags |= I40E_FLAG_DCB_ENABLED; |
8016 | else | |
8017 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
8018 | ||
0da36b97 | 8019 | set_bit(__I40E_PORT_SUSPENDED, pf->state); |
4e3b35b0 NP |
8020 | /* Reconfiguration needed quiesce all VSIs */ |
8021 | i40e_pf_quiesce_all_vsi(pf); | |
8022 | ||
8023 | /* Changes in configuration update VEB/VSI */ | |
8024 | i40e_dcb_reconfigure(pf); | |
8025 | ||
2fd75f31 NP |
8026 | ret = i40e_resume_port_tx(pf); |
8027 | ||
0da36b97 | 8028 | clear_bit(__I40E_PORT_SUSPENDED, pf->state); |
2fd75f31 | 8029 | /* In case of error no point in resuming VSIs */ |
69129dc3 NP |
8030 | if (ret) |
8031 | goto exit; | |
8032 | ||
3fe06f41 NP |
8033 | /* Wait for the PF's queues to be disabled */ |
8034 | ret = i40e_pf_wait_queues_disabled(pf); | |
11e47708 PN |
8035 | if (ret) { |
8036 | /* Schedule PF reset to recover */ | |
0da36b97 | 8037 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
11e47708 PN |
8038 | i40e_service_event_schedule(pf); |
8039 | } else { | |
2fd75f31 | 8040 | i40e_pf_unquiesce_all_vsi(pf); |
0ef2d5af MW |
8041 | pf->flags |= (I40E_FLAG_SERVICE_CLIENT_REQUESTED | |
8042 | I40E_FLAG_CLIENT_L2_CHANGE); | |
11e47708 PN |
8043 | } |
8044 | ||
4e3b35b0 NP |
8045 | exit: |
8046 | return ret; | |
8047 | } | |
8048 | #endif /* CONFIG_I40E_DCB */ | |
8049 | ||
23326186 ASJ |
8050 | /** |
8051 | * i40e_do_reset_safe - Protected reset path for userland calls. | |
8052 | * @pf: board private structure | |
8053 | * @reset_flags: which reset is requested | |
8054 | * | |
8055 | **/ | |
8056 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags) | |
8057 | { | |
8058 | rtnl_lock(); | |
373149fc | 8059 | i40e_do_reset(pf, reset_flags, true); |
23326186 ASJ |
8060 | rtnl_unlock(); |
8061 | } | |
8062 | ||
41c445ff JB |
8063 | /** |
8064 | * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event | |
8065 | * @pf: board private structure | |
8066 | * @e: event info posted on ARQ | |
8067 | * | |
8068 | * Handler for LAN Queue Overflow Event generated by the firmware for PF | |
8069 | * and VF queues | |
8070 | **/ | |
8071 | static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, | |
8072 | struct i40e_arq_event_info *e) | |
8073 | { | |
8074 | struct i40e_aqc_lan_overflow *data = | |
8075 | (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; | |
8076 | u32 queue = le32_to_cpu(data->prtdcb_rupto); | |
8077 | u32 qtx_ctl = le32_to_cpu(data->otx_ctl); | |
8078 | struct i40e_hw *hw = &pf->hw; | |
8079 | struct i40e_vf *vf; | |
8080 | u16 vf_id; | |
8081 | ||
69bfb110 JB |
8082 | dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", |
8083 | queue, qtx_ctl); | |
41c445ff JB |
8084 | |
8085 | /* Queue belongs to VF, find the VF and issue VF reset */ | |
8086 | if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) | |
8087 | >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { | |
8088 | vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) | |
8089 | >> I40E_QTX_CTL_VFVM_INDX_SHIFT); | |
8090 | vf_id -= hw->func_caps.vf_base_id; | |
8091 | vf = &pf->vf[vf_id]; | |
8092 | i40e_vc_notify_vf_reset(vf); | |
8093 | /* Allow VF to process pending reset notification */ | |
8094 | msleep(20); | |
8095 | i40e_reset_vf(vf, false); | |
8096 | } | |
8097 | } | |
8098 | ||
55a5e60b | 8099 | /** |
12957388 ASJ |
8100 | * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters |
8101 | * @pf: board private structure | |
8102 | **/ | |
04294e38 | 8103 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf) |
12957388 | 8104 | { |
04294e38 | 8105 | u32 val, fcnt_prog; |
12957388 ASJ |
8106 | |
8107 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); | |
8108 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); | |
8109 | return fcnt_prog; | |
8110 | } | |
8111 | ||
8112 | /** | |
04294e38 | 8113 | * i40e_get_current_fd_count - Get total FD filters programmed for this PF |
55a5e60b ASJ |
8114 | * @pf: board private structure |
8115 | **/ | |
04294e38 | 8116 | u32 i40e_get_current_fd_count(struct i40e_pf *pf) |
55a5e60b | 8117 | { |
04294e38 ASJ |
8118 | u32 val, fcnt_prog; |
8119 | ||
55a5e60b ASJ |
8120 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); |
8121 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + | |
8122 | ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> | |
8123 | I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); | |
8124 | return fcnt_prog; | |
8125 | } | |
1e1be8f6 | 8126 | |
04294e38 ASJ |
8127 | /** |
8128 | * i40e_get_global_fd_count - Get total FD filters programmed on device | |
8129 | * @pf: board private structure | |
8130 | **/ | |
8131 | u32 i40e_get_global_fd_count(struct i40e_pf *pf) | |
8132 | { | |
8133 | u32 val, fcnt_prog; | |
8134 | ||
8135 | val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); | |
8136 | fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + | |
8137 | ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> | |
8138 | I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); | |
8139 | return fcnt_prog; | |
8140 | } | |
8141 | ||
55a5e60b ASJ |
8142 | /** |
8143 | * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled | |
8144 | * @pf: board private structure | |
8145 | **/ | |
8146 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf) | |
8147 | { | |
3487b6c3 | 8148 | struct i40e_fdir_filter *filter; |
55a5e60b | 8149 | u32 fcnt_prog, fcnt_avail; |
3487b6c3 | 8150 | struct hlist_node *node; |
55a5e60b | 8151 | |
0da36b97 | 8152 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
8153 | return; |
8154 | ||
47994c11 | 8155 | /* Check if we have enough room to re-enable FDir SB capability. */ |
04294e38 | 8156 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 8157 | fcnt_avail = pf->fdir_pf_filter_count; |
1e1be8f6 ASJ |
8158 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) || |
8159 | (pf->fd_add_err == 0) || | |
8160 | (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) { | |
47994c11 JK |
8161 | if (pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED) { |
8162 | pf->flags &= ~I40E_FLAG_FD_SB_AUTO_DISABLED; | |
8163 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && | |
8164 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
2e4875e3 | 8165 | dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n"); |
55a5e60b ASJ |
8166 | } |
8167 | } | |
a3417d28 | 8168 | |
47994c11 JK |
8169 | /* We should wait for even more space before re-enabling ATR. |
8170 | * Additionally, we cannot enable ATR as long as we still have TCP SB | |
8171 | * rules active. | |
a3417d28 | 8172 | */ |
47994c11 JK |
8173 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) && |
8174 | (pf->fd_tcp4_filter_cnt == 0)) { | |
8175 | if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED) { | |
8176 | pf->flags &= ~I40E_FLAG_FD_ATR_AUTO_DISABLED; | |
8177 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
8178 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
a3417d28 | 8179 | dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n"); |
55a5e60b ASJ |
8180 | } |
8181 | } | |
3487b6c3 CW |
8182 | |
8183 | /* if hw had a problem adding a filter, delete it */ | |
8184 | if (pf->fd_inv > 0) { | |
8185 | hlist_for_each_entry_safe(filter, node, | |
8186 | &pf->fdir_filter_list, fdir_node) { | |
8187 | if (filter->fd_id == pf->fd_inv) { | |
8188 | hlist_del(&filter->fdir_node); | |
8189 | kfree(filter); | |
8190 | pf->fdir_pf_active_filters--; | |
013df598 | 8191 | pf->fd_inv = 0; |
3487b6c3 CW |
8192 | } |
8193 | } | |
8194 | } | |
55a5e60b ASJ |
8195 | } |
8196 | ||
1e1be8f6 | 8197 | #define I40E_MIN_FD_FLUSH_INTERVAL 10 |
04294e38 | 8198 | #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30 |
1e1be8f6 ASJ |
8199 | /** |
8200 | * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB | |
8201 | * @pf: board private structure | |
8202 | **/ | |
8203 | static void i40e_fdir_flush_and_replay(struct i40e_pf *pf) | |
8204 | { | |
04294e38 | 8205 | unsigned long min_flush_time; |
1e1be8f6 | 8206 | int flush_wait_retry = 50; |
04294e38 ASJ |
8207 | bool disable_atr = false; |
8208 | int fd_room; | |
1e1be8f6 ASJ |
8209 | int reg; |
8210 | ||
a5fdaf34 JB |
8211 | if (!time_after(jiffies, pf->fd_flush_timestamp + |
8212 | (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) | |
8213 | return; | |
04294e38 | 8214 | |
a5fdaf34 JB |
8215 | /* If the flush is happening too quick and we have mostly SB rules we |
8216 | * should not re-enable ATR for some time. | |
8217 | */ | |
8218 | min_flush_time = pf->fd_flush_timestamp + | |
8219 | (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ); | |
8220 | fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters; | |
8221 | ||
8222 | if (!(time_after(jiffies, min_flush_time)) && | |
8223 | (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) { | |
8224 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
8225 | dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n"); | |
8226 | disable_atr = true; | |
8227 | } | |
8228 | ||
8229 | pf->fd_flush_timestamp = jiffies; | |
47994c11 | 8230 | pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; |
a5fdaf34 JB |
8231 | /* flush all filters */ |
8232 | wr32(&pf->hw, I40E_PFQF_CTL_1, | |
8233 | I40E_PFQF_CTL_1_CLEARFDTABLE_MASK); | |
8234 | i40e_flush(&pf->hw); | |
8235 | pf->fd_flush_cnt++; | |
8236 | pf->fd_add_err = 0; | |
8237 | do { | |
8238 | /* Check FD flush status every 5-6msec */ | |
8239 | usleep_range(5000, 6000); | |
8240 | reg = rd32(&pf->hw, I40E_PFQF_CTL_1); | |
8241 | if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) | |
8242 | break; | |
8243 | } while (flush_wait_retry--); | |
8244 | if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { | |
8245 | dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n"); | |
8246 | } else { | |
8247 | /* replay sideband filters */ | |
8248 | i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]); | |
097dbf52 | 8249 | if (!disable_atr && !pf->fd_tcp4_filter_cnt) |
47994c11 | 8250 | pf->flags &= ~I40E_FLAG_FD_ATR_AUTO_DISABLED; |
0da36b97 | 8251 | clear_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); |
a5fdaf34 JB |
8252 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
8253 | dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n"); | |
1e1be8f6 ASJ |
8254 | } |
8255 | } | |
8256 | ||
8257 | /** | |
8258 | * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed | |
8259 | * @pf: board private structure | |
8260 | **/ | |
04294e38 | 8261 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf) |
1e1be8f6 ASJ |
8262 | { |
8263 | return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; | |
8264 | } | |
8265 | ||
8266 | /* We can see up to 256 filter programming desc in transit if the filters are | |
8267 | * being applied really fast; before we see the first | |
8268 | * filter miss error on Rx queue 0. Accumulating enough error messages before | |
8269 | * reacting will make sure we don't cause flush too often. | |
8270 | */ | |
8271 | #define I40E_MAX_FD_PROGRAM_ERROR 256 | |
8272 | ||
41c445ff JB |
8273 | /** |
8274 | * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table | |
8275 | * @pf: board private structure | |
8276 | **/ | |
8277 | static void i40e_fdir_reinit_subtask(struct i40e_pf *pf) | |
8278 | { | |
41c445ff | 8279 | |
41c445ff | 8280 | /* if interface is down do nothing */ |
9e6c9c0f | 8281 | if (test_bit(__I40E_DOWN, pf->state)) |
41c445ff | 8282 | return; |
1e1be8f6 | 8283 | |
0da36b97 | 8284 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
8285 | i40e_fdir_flush_and_replay(pf); |
8286 | ||
55a5e60b ASJ |
8287 | i40e_fdir_check_and_reenable(pf); |
8288 | ||
41c445ff JB |
8289 | } |
8290 | ||
8291 | /** | |
8292 | * i40e_vsi_link_event - notify VSI of a link event | |
8293 | * @vsi: vsi to be notified | |
8294 | * @link_up: link up or down | |
8295 | **/ | |
8296 | static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up) | |
8297 | { | |
0da36b97 | 8298 | if (!vsi || test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
8299 | return; |
8300 | ||
8301 | switch (vsi->type) { | |
8302 | case I40E_VSI_MAIN: | |
8303 | if (!vsi->netdev || !vsi->netdev_registered) | |
8304 | break; | |
8305 | ||
8306 | if (link_up) { | |
8307 | netif_carrier_on(vsi->netdev); | |
8308 | netif_tx_wake_all_queues(vsi->netdev); | |
8309 | } else { | |
8310 | netif_carrier_off(vsi->netdev); | |
8311 | netif_tx_stop_all_queues(vsi->netdev); | |
8312 | } | |
8313 | break; | |
8314 | ||
8315 | case I40E_VSI_SRIOV: | |
41c445ff JB |
8316 | case I40E_VSI_VMDQ2: |
8317 | case I40E_VSI_CTRL: | |
e3219ce6 | 8318 | case I40E_VSI_IWARP: |
41c445ff JB |
8319 | case I40E_VSI_MIRROR: |
8320 | default: | |
8321 | /* there is no notification for other VSIs */ | |
8322 | break; | |
8323 | } | |
8324 | } | |
8325 | ||
8326 | /** | |
8327 | * i40e_veb_link_event - notify elements on the veb of a link event | |
8328 | * @veb: veb to be notified | |
8329 | * @link_up: link up or down | |
8330 | **/ | |
8331 | static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up) | |
8332 | { | |
8333 | struct i40e_pf *pf; | |
8334 | int i; | |
8335 | ||
8336 | if (!veb || !veb->pf) | |
8337 | return; | |
8338 | pf = veb->pf; | |
8339 | ||
8340 | /* depth first... */ | |
8341 | for (i = 0; i < I40E_MAX_VEB; i++) | |
8342 | if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid)) | |
8343 | i40e_veb_link_event(pf->veb[i], link_up); | |
8344 | ||
8345 | /* ... now the local VSIs */ | |
505682cd | 8346 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
8347 | if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid)) |
8348 | i40e_vsi_link_event(pf->vsi[i], link_up); | |
8349 | } | |
8350 | ||
8351 | /** | |
8352 | * i40e_link_event - Update netif_carrier status | |
8353 | * @pf: board private structure | |
8354 | **/ | |
8355 | static void i40e_link_event(struct i40e_pf *pf) | |
8356 | { | |
320684cd | 8357 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
fef59ddf | 8358 | u8 new_link_speed, old_link_speed; |
a72a5abc JB |
8359 | i40e_status status; |
8360 | bool new_link, old_link; | |
41c445ff | 8361 | |
1f9610e4 CS |
8362 | /* save off old link status information */ |
8363 | pf->hw.phy.link_info_old = pf->hw.phy.link_info; | |
8364 | ||
1e701e09 JB |
8365 | /* set this to force the get_link_status call to refresh state */ |
8366 | pf->hw.phy.get_link_info = true; | |
8367 | ||
41c445ff | 8368 | old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP); |
a72a5abc JB |
8369 | |
8370 | status = i40e_get_link_status(&pf->hw, &new_link); | |
ae136708 HR |
8371 | |
8372 | /* On success, disable temp link polling */ | |
8373 | if (status == I40E_SUCCESS) { | |
8374 | if (pf->flags & I40E_FLAG_TEMP_LINK_POLLING) | |
8375 | pf->flags &= ~I40E_FLAG_TEMP_LINK_POLLING; | |
8376 | } else { | |
8377 | /* Enable link polling temporarily until i40e_get_link_status | |
8378 | * returns I40E_SUCCESS | |
8379 | */ | |
8380 | pf->flags |= I40E_FLAG_TEMP_LINK_POLLING; | |
a72a5abc JB |
8381 | dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n", |
8382 | status); | |
8383 | return; | |
8384 | } | |
8385 | ||
fef59ddf CS |
8386 | old_link_speed = pf->hw.phy.link_info_old.link_speed; |
8387 | new_link_speed = pf->hw.phy.link_info.link_speed; | |
41c445ff | 8388 | |
1e701e09 | 8389 | if (new_link == old_link && |
fef59ddf | 8390 | new_link_speed == old_link_speed && |
0da36b97 | 8391 | (test_bit(__I40E_VSI_DOWN, vsi->state) || |
320684cd | 8392 | new_link == netif_carrier_ok(vsi->netdev))) |
41c445ff | 8393 | return; |
320684cd | 8394 | |
9a03449d | 8395 | i40e_print_link_message(vsi, new_link); |
41c445ff JB |
8396 | |
8397 | /* Notify the base of the switch tree connected to | |
8398 | * the link. Floating VEBs are not notified. | |
8399 | */ | |
8400 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
8401 | i40e_veb_link_event(pf->veb[pf->lan_veb], new_link); | |
8402 | else | |
320684cd | 8403 | i40e_vsi_link_event(vsi, new_link); |
41c445ff JB |
8404 | |
8405 | if (pf->vf) | |
8406 | i40e_vc_notify_link_state(pf); | |
beb0dff1 JK |
8407 | |
8408 | if (pf->flags & I40E_FLAG_PTP) | |
8409 | i40e_ptp_set_increment(pf); | |
41c445ff JB |
8410 | } |
8411 | ||
41c445ff | 8412 | /** |
21536717 | 8413 | * i40e_watchdog_subtask - periodic checks not using event driven response |
41c445ff JB |
8414 | * @pf: board private structure |
8415 | **/ | |
8416 | static void i40e_watchdog_subtask(struct i40e_pf *pf) | |
8417 | { | |
8418 | int i; | |
8419 | ||
8420 | /* if interface is down do nothing */ | |
9e6c9c0f | 8421 | if (test_bit(__I40E_DOWN, pf->state) || |
0da36b97 | 8422 | test_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
8423 | return; |
8424 | ||
21536717 SN |
8425 | /* make sure we don't do these things too often */ |
8426 | if (time_before(jiffies, (pf->service_timer_previous + | |
8427 | pf->service_timer_period))) | |
8428 | return; | |
8429 | pf->service_timer_previous = jiffies; | |
8430 | ||
ae136708 HR |
8431 | if ((pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) || |
8432 | (pf->flags & I40E_FLAG_TEMP_LINK_POLLING)) | |
9ac77266 | 8433 | i40e_link_event(pf); |
21536717 | 8434 | |
41c445ff JB |
8435 | /* Update the stats for active netdevs so the network stack |
8436 | * can look at updated numbers whenever it cares to | |
8437 | */ | |
505682cd | 8438 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
8439 | if (pf->vsi[i] && pf->vsi[i]->netdev) |
8440 | i40e_update_stats(pf->vsi[i]); | |
8441 | ||
d1a8d275 ASJ |
8442 | if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) { |
8443 | /* Update the stats for the active switching components */ | |
8444 | for (i = 0; i < I40E_MAX_VEB; i++) | |
8445 | if (pf->veb[i]) | |
8446 | i40e_update_veb_stats(pf->veb[i]); | |
8447 | } | |
beb0dff1 | 8448 | |
61189556 | 8449 | i40e_ptp_rx_hang(pf); |
0bc0706b | 8450 | i40e_ptp_tx_hang(pf); |
41c445ff JB |
8451 | } |
8452 | ||
8453 | /** | |
8454 | * i40e_reset_subtask - Set up for resetting the device and driver | |
8455 | * @pf: board private structure | |
8456 | **/ | |
8457 | static void i40e_reset_subtask(struct i40e_pf *pf) | |
8458 | { | |
8459 | u32 reset_flags = 0; | |
8460 | ||
0da36b97 | 8461 | if (test_bit(__I40E_REINIT_REQUESTED, pf->state)) { |
75f5cea9 | 8462 | reset_flags |= BIT(__I40E_REINIT_REQUESTED); |
0da36b97 | 8463 | clear_bit(__I40E_REINIT_REQUESTED, pf->state); |
41c445ff | 8464 | } |
0da36b97 | 8465 | if (test_bit(__I40E_PF_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 8466 | reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); |
0da36b97 | 8467 | clear_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff | 8468 | } |
0da36b97 | 8469 | if (test_bit(__I40E_CORE_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 8470 | reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); |
0da36b97 | 8471 | clear_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff | 8472 | } |
0da36b97 | 8473 | if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 8474 | reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); |
0da36b97 | 8475 | clear_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff | 8476 | } |
9e6c9c0f MR |
8477 | if (test_bit(__I40E_DOWN_REQUESTED, pf->state)) { |
8478 | reset_flags |= BIT(__I40E_DOWN_REQUESTED); | |
8479 | clear_bit(__I40E_DOWN_REQUESTED, pf->state); | |
b5d06f05 | 8480 | } |
41c445ff JB |
8481 | |
8482 | /* If there's a recovery already waiting, it takes | |
8483 | * precedence before starting a new reset sequence. | |
8484 | */ | |
0da36b97 | 8485 | if (test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) { |
373149fc MS |
8486 | i40e_prep_for_reset(pf, false); |
8487 | i40e_reset(pf); | |
8488 | i40e_rebuild(pf, false, false); | |
41c445ff JB |
8489 | } |
8490 | ||
8491 | /* If we're already down or resetting, just bail */ | |
8492 | if (reset_flags && | |
9e6c9c0f | 8493 | !test_bit(__I40E_DOWN, pf->state) && |
0da36b97 | 8494 | !test_bit(__I40E_CONFIG_BUSY, pf->state)) { |
dfc4ff64 | 8495 | i40e_do_reset(pf, reset_flags, false); |
373149fc | 8496 | } |
41c445ff JB |
8497 | } |
8498 | ||
8499 | /** | |
8500 | * i40e_handle_link_event - Handle link event | |
8501 | * @pf: board private structure | |
8502 | * @e: event info posted on ARQ | |
8503 | **/ | |
8504 | static void i40e_handle_link_event(struct i40e_pf *pf, | |
8505 | struct i40e_arq_event_info *e) | |
8506 | { | |
41c445ff JB |
8507 | struct i40e_aqc_get_link_status *status = |
8508 | (struct i40e_aqc_get_link_status *)&e->desc.params.raw; | |
41c445ff | 8509 | |
1e701e09 JB |
8510 | /* Do a new status request to re-enable LSE reporting |
8511 | * and load new status information into the hw struct | |
8512 | * This completely ignores any state information | |
8513 | * in the ARQ event info, instead choosing to always | |
8514 | * issue the AQ update link status command. | |
8515 | */ | |
8516 | i40e_link_event(pf); | |
8517 | ||
9a858178 FS |
8518 | /* Check if module meets thermal requirements */ |
8519 | if (status->phy_type == I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP) { | |
7b592f61 | 8520 | dev_err(&pf->pdev->dev, |
9a858178 FS |
8521 | "Rx/Tx is disabled on this device because the module does not meet thermal requirements.\n"); |
8522 | dev_err(&pf->pdev->dev, | |
8523 | "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n"); | |
8524 | } else { | |
8525 | /* check for unqualified module, if link is down, suppress | |
8526 | * the message if link was forced to be down. | |
8527 | */ | |
8528 | if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && | |
8529 | (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && | |
8530 | (!(status->link_info & I40E_AQ_LINK_UP)) && | |
8531 | (!(pf->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED))) { | |
8532 | dev_err(&pf->pdev->dev, | |
8533 | "Rx/Tx is disabled on this device because an unsupported SFP module type was detected.\n"); | |
8534 | dev_err(&pf->pdev->dev, | |
8535 | "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n"); | |
8536 | } | |
8537 | } | |
41c445ff JB |
8538 | } |
8539 | ||
8540 | /** | |
8541 | * i40e_clean_adminq_subtask - Clean the AdminQ rings | |
8542 | * @pf: board private structure | |
8543 | **/ | |
8544 | static void i40e_clean_adminq_subtask(struct i40e_pf *pf) | |
8545 | { | |
8546 | struct i40e_arq_event_info event; | |
8547 | struct i40e_hw *hw = &pf->hw; | |
8548 | u16 pending, i = 0; | |
8549 | i40e_status ret; | |
8550 | u16 opcode; | |
86df242b | 8551 | u32 oldval; |
41c445ff JB |
8552 | u32 val; |
8553 | ||
a316f651 | 8554 | /* Do not run clean AQ when PF reset fails */ |
0da36b97 | 8555 | if (test_bit(__I40E_RESET_FAILED, pf->state)) |
a316f651 ASJ |
8556 | return; |
8557 | ||
86df242b SN |
8558 | /* check for error indications */ |
8559 | val = rd32(&pf->hw, pf->hw.aq.arq.len); | |
8560 | oldval = val; | |
8561 | if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { | |
75eb73c1 MW |
8562 | if (hw->debug_mask & I40E_DEBUG_AQ) |
8563 | dev_info(&pf->pdev->dev, "ARQ VF Error detected\n"); | |
86df242b SN |
8564 | val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; |
8565 | } | |
8566 | if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { | |
75eb73c1 MW |
8567 | if (hw->debug_mask & I40E_DEBUG_AQ) |
8568 | dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n"); | |
86df242b | 8569 | val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; |
1d0a4ada | 8570 | pf->arq_overflows++; |
86df242b SN |
8571 | } |
8572 | if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { | |
75eb73c1 MW |
8573 | if (hw->debug_mask & I40E_DEBUG_AQ) |
8574 | dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n"); | |
86df242b SN |
8575 | val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; |
8576 | } | |
8577 | if (oldval != val) | |
8578 | wr32(&pf->hw, pf->hw.aq.arq.len, val); | |
8579 | ||
8580 | val = rd32(&pf->hw, pf->hw.aq.asq.len); | |
8581 | oldval = val; | |
8582 | if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { | |
75eb73c1 MW |
8583 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
8584 | dev_info(&pf->pdev->dev, "ASQ VF Error detected\n"); | |
86df242b SN |
8585 | val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; |
8586 | } | |
8587 | if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { | |
75eb73c1 MW |
8588 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
8589 | dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n"); | |
86df242b SN |
8590 | val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; |
8591 | } | |
8592 | if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { | |
75eb73c1 MW |
8593 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
8594 | dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n"); | |
86df242b SN |
8595 | val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; |
8596 | } | |
8597 | if (oldval != val) | |
8598 | wr32(&pf->hw, pf->hw.aq.asq.len, val); | |
8599 | ||
1001dc37 MW |
8600 | event.buf_len = I40E_MAX_AQ_BUF_SIZE; |
8601 | event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); | |
41c445ff JB |
8602 | if (!event.msg_buf) |
8603 | return; | |
8604 | ||
8605 | do { | |
8606 | ret = i40e_clean_arq_element(hw, &event, &pending); | |
56497978 | 8607 | if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) |
41c445ff | 8608 | break; |
56497978 | 8609 | else if (ret) { |
41c445ff JB |
8610 | dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret); |
8611 | break; | |
8612 | } | |
8613 | ||
8614 | opcode = le16_to_cpu(event.desc.opcode); | |
8615 | switch (opcode) { | |
8616 | ||
8617 | case i40e_aqc_opc_get_link_status: | |
8618 | i40e_handle_link_event(pf, &event); | |
8619 | break; | |
8620 | case i40e_aqc_opc_send_msg_to_pf: | |
8621 | ret = i40e_vc_process_vf_msg(pf, | |
8622 | le16_to_cpu(event.desc.retval), | |
8623 | le32_to_cpu(event.desc.cookie_high), | |
8624 | le32_to_cpu(event.desc.cookie_low), | |
8625 | event.msg_buf, | |
1001dc37 | 8626 | event.msg_len); |
41c445ff JB |
8627 | break; |
8628 | case i40e_aqc_opc_lldp_update_mib: | |
69bfb110 | 8629 | dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n"); |
4e3b35b0 NP |
8630 | #ifdef CONFIG_I40E_DCB |
8631 | rtnl_lock(); | |
8632 | ret = i40e_handle_lldp_event(pf, &event); | |
8633 | rtnl_unlock(); | |
8634 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
8635 | break; |
8636 | case i40e_aqc_opc_event_lan_overflow: | |
69bfb110 | 8637 | dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n"); |
41c445ff JB |
8638 | i40e_handle_lan_overflow_event(pf, &event); |
8639 | break; | |
0467bc91 SN |
8640 | case i40e_aqc_opc_send_msg_to_peer: |
8641 | dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n"); | |
8642 | break; | |
91a0f930 SN |
8643 | case i40e_aqc_opc_nvm_erase: |
8644 | case i40e_aqc_opc_nvm_update: | |
00ada50d | 8645 | case i40e_aqc_opc_oem_post_update: |
6e93d0c9 SN |
8646 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, |
8647 | "ARQ NVM operation 0x%04x completed\n", | |
8648 | opcode); | |
91a0f930 | 8649 | break; |
41c445ff JB |
8650 | default: |
8651 | dev_info(&pf->pdev->dev, | |
56e5ca68 | 8652 | "ARQ: Unknown event 0x%04x ignored\n", |
0467bc91 | 8653 | opcode); |
41c445ff JB |
8654 | break; |
8655 | } | |
1fca3265 CB |
8656 | } while (i++ < pf->adminq_work_limit); |
8657 | ||
8658 | if (i < pf->adminq_work_limit) | |
0da36b97 | 8659 | clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
41c445ff | 8660 | |
41c445ff JB |
8661 | /* re-enable Admin queue interrupt cause */ |
8662 | val = rd32(hw, I40E_PFINT_ICR0_ENA); | |
8663 | val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
8664 | wr32(hw, I40E_PFINT_ICR0_ENA, val); | |
8665 | i40e_flush(hw); | |
8666 | ||
8667 | kfree(event.msg_buf); | |
8668 | } | |
8669 | ||
4eb3f768 SN |
8670 | /** |
8671 | * i40e_verify_eeprom - make sure eeprom is good to use | |
8672 | * @pf: board private structure | |
8673 | **/ | |
8674 | static void i40e_verify_eeprom(struct i40e_pf *pf) | |
8675 | { | |
8676 | int err; | |
8677 | ||
8678 | err = i40e_diag_eeprom_test(&pf->hw); | |
8679 | if (err) { | |
8680 | /* retry in case of garbage read */ | |
8681 | err = i40e_diag_eeprom_test(&pf->hw); | |
8682 | if (err) { | |
8683 | dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n", | |
8684 | err); | |
0da36b97 | 8685 | set_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
8686 | } |
8687 | } | |
8688 | ||
0da36b97 | 8689 | if (!err && test_bit(__I40E_BAD_EEPROM, pf->state)) { |
4eb3f768 | 8690 | dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n"); |
0da36b97 | 8691 | clear_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
8692 | } |
8693 | } | |
8694 | ||
386a0afa AA |
8695 | /** |
8696 | * i40e_enable_pf_switch_lb | |
b40c82e6 | 8697 | * @pf: pointer to the PF structure |
386a0afa AA |
8698 | * |
8699 | * enable switch loop back or die - no point in a return value | |
8700 | **/ | |
8701 | static void i40e_enable_pf_switch_lb(struct i40e_pf *pf) | |
8702 | { | |
8703 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
8704 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 8705 | int ret; |
386a0afa AA |
8706 | |
8707 | ctxt.seid = pf->main_vsi_seid; | |
8708 | ctxt.pf_num = pf->hw.pf_id; | |
8709 | ctxt.vf_num = 0; | |
f1c7e72e SN |
8710 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
8711 | if (ret) { | |
386a0afa | 8712 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8713 | "couldn't get PF vsi config, err %s aq_err %s\n", |
8714 | i40e_stat_str(&pf->hw, ret), | |
8715 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8716 | return; |
8717 | } | |
8718 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
8719 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
8720 | ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
8721 | ||
f1c7e72e SN |
8722 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
8723 | if (ret) { | |
386a0afa | 8724 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8725 | "update vsi switch failed, err %s aq_err %s\n", |
8726 | i40e_stat_str(&pf->hw, ret), | |
8727 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8728 | } |
8729 | } | |
8730 | ||
8731 | /** | |
8732 | * i40e_disable_pf_switch_lb | |
b40c82e6 | 8733 | * @pf: pointer to the PF structure |
386a0afa AA |
8734 | * |
8735 | * disable switch loop back or die - no point in a return value | |
8736 | **/ | |
8737 | static void i40e_disable_pf_switch_lb(struct i40e_pf *pf) | |
8738 | { | |
8739 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
8740 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 8741 | int ret; |
386a0afa AA |
8742 | |
8743 | ctxt.seid = pf->main_vsi_seid; | |
8744 | ctxt.pf_num = pf->hw.pf_id; | |
8745 | ctxt.vf_num = 0; | |
f1c7e72e SN |
8746 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
8747 | if (ret) { | |
386a0afa | 8748 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8749 | "couldn't get PF vsi config, err %s aq_err %s\n", |
8750 | i40e_stat_str(&pf->hw, ret), | |
8751 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8752 | return; |
8753 | } | |
8754 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
8755 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
8756 | ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
8757 | ||
f1c7e72e SN |
8758 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
8759 | if (ret) { | |
386a0afa | 8760 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8761 | "update vsi switch failed, err %s aq_err %s\n", |
8762 | i40e_stat_str(&pf->hw, ret), | |
8763 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8764 | } |
8765 | } | |
8766 | ||
51616018 NP |
8767 | /** |
8768 | * i40e_config_bridge_mode - Configure the HW bridge mode | |
8769 | * @veb: pointer to the bridge instance | |
8770 | * | |
8771 | * Configure the loop back mode for the LAN VSI that is downlink to the | |
8772 | * specified HW bridge instance. It is expected this function is called | |
8773 | * when a new HW bridge is instantiated. | |
8774 | **/ | |
8775 | static void i40e_config_bridge_mode(struct i40e_veb *veb) | |
8776 | { | |
8777 | struct i40e_pf *pf = veb->pf; | |
8778 | ||
6dec1017 SN |
8779 | if (pf->hw.debug_mask & I40E_DEBUG_LAN) |
8780 | dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n", | |
8781 | veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
51616018 NP |
8782 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) |
8783 | i40e_disable_pf_switch_lb(pf); | |
8784 | else | |
8785 | i40e_enable_pf_switch_lb(pf); | |
8786 | } | |
8787 | ||
41c445ff JB |
8788 | /** |
8789 | * i40e_reconstitute_veb - rebuild the VEB and anything connected to it | |
8790 | * @veb: pointer to the VEB instance | |
8791 | * | |
8792 | * This is a recursive function that first builds the attached VSIs then | |
8793 | * recurses in to build the next layer of VEB. We track the connections | |
8794 | * through our own index numbers because the seid's from the HW could | |
8795 | * change across the reset. | |
8796 | **/ | |
8797 | static int i40e_reconstitute_veb(struct i40e_veb *veb) | |
8798 | { | |
8799 | struct i40e_vsi *ctl_vsi = NULL; | |
8800 | struct i40e_pf *pf = veb->pf; | |
8801 | int v, veb_idx; | |
8802 | int ret; | |
8803 | ||
8804 | /* build VSI that owns this VEB, temporarily attached to base VEB */ | |
505682cd | 8805 | for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) { |
41c445ff JB |
8806 | if (pf->vsi[v] && |
8807 | pf->vsi[v]->veb_idx == veb->idx && | |
8808 | pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
8809 | ctl_vsi = pf->vsi[v]; | |
8810 | break; | |
8811 | } | |
8812 | } | |
8813 | if (!ctl_vsi) { | |
8814 | dev_info(&pf->pdev->dev, | |
8815 | "missing owner VSI for veb_idx %d\n", veb->idx); | |
8816 | ret = -ENOENT; | |
8817 | goto end_reconstitute; | |
8818 | } | |
8819 | if (ctl_vsi != pf->vsi[pf->lan_vsi]) | |
8820 | ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
8821 | ret = i40e_add_vsi(ctl_vsi); | |
8822 | if (ret) { | |
8823 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8824 | "rebuild of veb_idx %d owner VSI failed: %d\n", |
8825 | veb->idx, ret); | |
41c445ff JB |
8826 | goto end_reconstitute; |
8827 | } | |
8828 | i40e_vsi_reset_stats(ctl_vsi); | |
8829 | ||
8830 | /* create the VEB in the switch and move the VSI onto the VEB */ | |
8831 | ret = i40e_add_veb(veb, ctl_vsi); | |
8832 | if (ret) | |
8833 | goto end_reconstitute; | |
8834 | ||
fc60861e ASJ |
8835 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
8836 | veb->bridge_mode = BRIDGE_MODE_VEB; | |
8837 | else | |
8838 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
51616018 | 8839 | i40e_config_bridge_mode(veb); |
b64ba084 | 8840 | |
41c445ff | 8841 | /* create the remaining VSIs attached to this VEB */ |
505682cd | 8842 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
8843 | if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi) |
8844 | continue; | |
8845 | ||
8846 | if (pf->vsi[v]->veb_idx == veb->idx) { | |
8847 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 8848 | |
41c445ff JB |
8849 | vsi->uplink_seid = veb->seid; |
8850 | ret = i40e_add_vsi(vsi); | |
8851 | if (ret) { | |
8852 | dev_info(&pf->pdev->dev, | |
8853 | "rebuild of vsi_idx %d failed: %d\n", | |
8854 | v, ret); | |
8855 | goto end_reconstitute; | |
8856 | } | |
8857 | i40e_vsi_reset_stats(vsi); | |
8858 | } | |
8859 | } | |
8860 | ||
8861 | /* create any VEBs attached to this VEB - RECURSION */ | |
8862 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
8863 | if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) { | |
8864 | pf->veb[veb_idx]->uplink_seid = veb->seid; | |
8865 | ret = i40e_reconstitute_veb(pf->veb[veb_idx]); | |
8866 | if (ret) | |
8867 | break; | |
8868 | } | |
8869 | } | |
8870 | ||
8871 | end_reconstitute: | |
8872 | return ret; | |
8873 | } | |
8874 | ||
8875 | /** | |
8876 | * i40e_get_capabilities - get info about the HW | |
8877 | * @pf: the PF struct | |
8878 | **/ | |
2f4b411a AN |
8879 | static int i40e_get_capabilities(struct i40e_pf *pf, |
8880 | enum i40e_admin_queue_opc list_type) | |
41c445ff JB |
8881 | { |
8882 | struct i40e_aqc_list_capabilities_element_resp *cap_buf; | |
8883 | u16 data_size; | |
8884 | int buf_len; | |
8885 | int err; | |
8886 | ||
8887 | buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); | |
8888 | do { | |
8889 | cap_buf = kzalloc(buf_len, GFP_KERNEL); | |
8890 | if (!cap_buf) | |
8891 | return -ENOMEM; | |
8892 | ||
8893 | /* this loads the data into the hw struct for us */ | |
8894 | err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len, | |
2f4b411a AN |
8895 | &data_size, list_type, |
8896 | NULL); | |
41c445ff JB |
8897 | /* data loaded, buffer no longer needed */ |
8898 | kfree(cap_buf); | |
8899 | ||
8900 | if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { | |
8901 | /* retry with a larger buffer */ | |
8902 | buf_len = data_size; | |
8903 | } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { | |
8904 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8905 | "capability discovery failed, err %s aq_err %s\n", |
8906 | i40e_stat_str(&pf->hw, err), | |
8907 | i40e_aq_str(&pf->hw, | |
8908 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
8909 | return -ENODEV; |
8910 | } | |
8911 | } while (err); | |
8912 | ||
2f4b411a AN |
8913 | if (pf->hw.debug_mask & I40E_DEBUG_USER) { |
8914 | if (list_type == i40e_aqc_opc_list_func_capabilities) { | |
8915 | dev_info(&pf->pdev->dev, | |
8916 | "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n", | |
8917 | pf->hw.pf_id, pf->hw.func_caps.num_vfs, | |
8918 | pf->hw.func_caps.num_msix_vectors, | |
8919 | pf->hw.func_caps.num_msix_vectors_vf, | |
8920 | pf->hw.func_caps.fd_filters_guaranteed, | |
8921 | pf->hw.func_caps.fd_filters_best_effort, | |
8922 | pf->hw.func_caps.num_tx_qp, | |
8923 | pf->hw.func_caps.num_vsis); | |
8924 | } else if (list_type == i40e_aqc_opc_list_dev_capabilities) { | |
8925 | dev_info(&pf->pdev->dev, | |
8926 | "switch_mode=0x%04x, function_valid=0x%08x\n", | |
8927 | pf->hw.dev_caps.switch_mode, | |
8928 | pf->hw.dev_caps.valid_functions); | |
8929 | dev_info(&pf->pdev->dev, | |
8930 | "SR-IOV=%d, num_vfs for all function=%u\n", | |
8931 | pf->hw.dev_caps.sr_iov_1_1, | |
8932 | pf->hw.dev_caps.num_vfs); | |
8933 | dev_info(&pf->pdev->dev, | |
8934 | "num_vsis=%u, num_rx:%u, num_tx=%u\n", | |
8935 | pf->hw.dev_caps.num_vsis, | |
8936 | pf->hw.dev_caps.num_rx_qp, | |
8937 | pf->hw.dev_caps.num_tx_qp); | |
8938 | } | |
8939 | } | |
8940 | if (list_type == i40e_aqc_opc_list_func_capabilities) { | |
7134f9ce JB |
8941 | #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \ |
8942 | + pf->hw.func_caps.num_vfs) | |
2f4b411a AN |
8943 | if (pf->hw.revision_id == 0 && |
8944 | pf->hw.func_caps.num_vsis < DEF_NUM_VSI) { | |
8945 | dev_info(&pf->pdev->dev, | |
8946 | "got num_vsis %d, setting num_vsis to %d\n", | |
8947 | pf->hw.func_caps.num_vsis, DEF_NUM_VSI); | |
8948 | pf->hw.func_caps.num_vsis = DEF_NUM_VSI; | |
8949 | } | |
7134f9ce | 8950 | } |
41c445ff JB |
8951 | return 0; |
8952 | } | |
8953 | ||
cbf61325 ASJ |
8954 | static int i40e_vsi_clear(struct i40e_vsi *vsi); |
8955 | ||
41c445ff | 8956 | /** |
cbf61325 | 8957 | * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband |
41c445ff JB |
8958 | * @pf: board private structure |
8959 | **/ | |
cbf61325 | 8960 | static void i40e_fdir_sb_setup(struct i40e_pf *pf) |
41c445ff JB |
8961 | { |
8962 | struct i40e_vsi *vsi; | |
41c445ff | 8963 | |
407e063c JB |
8964 | /* quick workaround for an NVM issue that leaves a critical register |
8965 | * uninitialized | |
8966 | */ | |
8967 | if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) { | |
8968 | static const u32 hkey[] = { | |
8969 | 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36, | |
8970 | 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb, | |
8971 | 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21, | |
8972 | 0x95b3a76d}; | |
4b816446 | 8973 | int i; |
407e063c JB |
8974 | |
8975 | for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++) | |
8976 | wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]); | |
8977 | } | |
8978 | ||
cbf61325 | 8979 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
41c445ff JB |
8980 | return; |
8981 | ||
cbf61325 | 8982 | /* find existing VSI and see if it needs configuring */ |
4b816446 | 8983 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
cbf61325 ASJ |
8984 | |
8985 | /* create a new VSI if none exists */ | |
41c445ff | 8986 | if (!vsi) { |
cbf61325 ASJ |
8987 | vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, |
8988 | pf->vsi[pf->lan_vsi]->seid, 0); | |
41c445ff JB |
8989 | if (!vsi) { |
8990 | dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n"); | |
8a9eb7d3 | 8991 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
2f4b411a | 8992 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
8a9eb7d3 | 8993 | return; |
41c445ff | 8994 | } |
cbf61325 | 8995 | } |
41c445ff | 8996 | |
8a9eb7d3 | 8997 | i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring); |
41c445ff JB |
8998 | } |
8999 | ||
9000 | /** | |
9001 | * i40e_fdir_teardown - release the Flow Director resources | |
9002 | * @pf: board private structure | |
9003 | **/ | |
9004 | static void i40e_fdir_teardown(struct i40e_pf *pf) | |
9005 | { | |
4b816446 | 9006 | struct i40e_vsi *vsi; |
41c445ff | 9007 | |
17a73f6b | 9008 | i40e_fdir_filter_exit(pf); |
4b816446 AD |
9009 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
9010 | if (vsi) | |
9011 | i40e_vsi_release(vsi); | |
41c445ff JB |
9012 | } |
9013 | ||
2f4b411a AN |
9014 | /** |
9015 | * i40e_rebuild_cloud_filters - Rebuilds cloud filters for VSIs | |
9016 | * @vsi: PF main vsi | |
9017 | * @seid: seid of main or channel VSIs | |
9018 | * | |
9019 | * Rebuilds cloud filters associated with main VSI and channel VSIs if they | |
9020 | * existed before reset | |
9021 | **/ | |
9022 | static int i40e_rebuild_cloud_filters(struct i40e_vsi *vsi, u16 seid) | |
9023 | { | |
9024 | struct i40e_cloud_filter *cfilter; | |
9025 | struct i40e_pf *pf = vsi->back; | |
9026 | struct hlist_node *node; | |
9027 | i40e_status ret; | |
9028 | ||
9029 | /* Add cloud filters back if they exist */ | |
9030 | hlist_for_each_entry_safe(cfilter, node, &pf->cloud_filter_list, | |
9031 | cloud_node) { | |
9032 | if (cfilter->seid != seid) | |
9033 | continue; | |
9034 | ||
9035 | if (cfilter->dst_port) | |
9036 | ret = i40e_add_del_cloud_filter_big_buf(vsi, cfilter, | |
9037 | true); | |
9038 | else | |
9039 | ret = i40e_add_del_cloud_filter(vsi, cfilter, true); | |
cbf61325 | 9040 | |
2f4b411a AN |
9041 | if (ret) { |
9042 | dev_dbg(&pf->pdev->dev, | |
9043 | "Failed to rebuild cloud filter, err %s aq_err %s\n", | |
9044 | i40e_stat_str(&pf->hw, ret), | |
9045 | i40e_aq_str(&pf->hw, | |
9046 | pf->hw.aq.asq_last_status)); | |
9047 | return ret; | |
41c445ff | 9048 | } |
cbf61325 | 9049 | } |
2f4b411a | 9050 | return 0; |
41c445ff JB |
9051 | } |
9052 | ||
9053 | /** | |
8f88b303 AN |
9054 | * i40e_rebuild_channels - Rebuilds channel VSIs if they existed before reset |
9055 | * @vsi: PF main vsi | |
9056 | * | |
9057 | * Rebuilds channel VSIs if they existed before reset | |
41c445ff | 9058 | **/ |
8f88b303 | 9059 | static int i40e_rebuild_channels(struct i40e_vsi *vsi) |
41c445ff | 9060 | { |
8f88b303 AN |
9061 | struct i40e_channel *ch, *ch_tmp; |
9062 | i40e_status ret; | |
41c445ff | 9063 | |
8f88b303 AN |
9064 | if (list_empty(&vsi->ch_list)) |
9065 | return 0; | |
9066 | ||
9067 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
9068 | if (!ch->initialized) | |
9069 | break; | |
9070 | /* Proceed with creation of channel (VMDq2) VSI */ | |
9071 | ret = i40e_add_channel(vsi->back, vsi->uplink_seid, ch); | |
9072 | if (ret) { | |
9073 | dev_info(&vsi->back->pdev->dev, | |
9074 | "failed to rebuild channels using uplink_seid %u\n", | |
9075 | vsi->uplink_seid); | |
9076 | return ret; | |
9077 | } | |
2027d4de | 9078 | if (ch->max_tx_rate) { |
6c32e0d9 AB |
9079 | u64 credits = ch->max_tx_rate; |
9080 | ||
2027d4de AN |
9081 | if (i40e_set_bw_limit(vsi, ch->seid, |
9082 | ch->max_tx_rate)) | |
9083 | return -EINVAL; | |
9084 | ||
6c32e0d9 | 9085 | do_div(credits, I40E_BW_CREDIT_DIVISOR); |
2027d4de AN |
9086 | dev_dbg(&vsi->back->pdev->dev, |
9087 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
9088 | ch->max_tx_rate, | |
6c32e0d9 | 9089 | credits, |
2027d4de AN |
9090 | ch->seid); |
9091 | } | |
2f4b411a AN |
9092 | ret = i40e_rebuild_cloud_filters(vsi, ch->seid); |
9093 | if (ret) { | |
9094 | dev_dbg(&vsi->back->pdev->dev, | |
9095 | "Failed to rebuild cloud filters for channel VSI %u\n", | |
9096 | ch->seid); | |
9097 | return ret; | |
9098 | } | |
8f88b303 AN |
9099 | } |
9100 | return 0; | |
41c445ff JB |
9101 | } |
9102 | ||
9103 | /** | |
f650a38b | 9104 | * i40e_prep_for_reset - prep for the core to reset |
41c445ff | 9105 | * @pf: board private structure |
373149fc MS |
9106 | * @lock_acquired: indicates whether or not the lock has been acquired |
9107 | * before this function was called. | |
41c445ff | 9108 | * |
b40c82e6 | 9109 | * Close up the VFs and other things in prep for PF Reset. |
f650a38b | 9110 | **/ |
373149fc | 9111 | static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired) |
41c445ff | 9112 | { |
41c445ff | 9113 | struct i40e_hw *hw = &pf->hw; |
60442dea | 9114 | i40e_status ret = 0; |
41c445ff JB |
9115 | u32 v; |
9116 | ||
0da36b97 JK |
9117 | clear_bit(__I40E_RESET_INTR_RECEIVED, pf->state); |
9118 | if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) | |
23cfbe07 | 9119 | return; |
d3ce5734 MW |
9120 | if (i40e_check_asq_alive(&pf->hw)) |
9121 | i40e_vc_notify_reset(pf); | |
41c445ff | 9122 | |
69bfb110 | 9123 | dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n"); |
41c445ff | 9124 | |
41c445ff | 9125 | /* quiesce the VSIs and their queues that are not already DOWN */ |
373149fc MS |
9126 | /* pf_quiesce_all_vsi modifies netdev structures -rtnl_lock needed */ |
9127 | if (!lock_acquired) | |
9128 | rtnl_lock(); | |
41c445ff | 9129 | i40e_pf_quiesce_all_vsi(pf); |
373149fc MS |
9130 | if (!lock_acquired) |
9131 | rtnl_unlock(); | |
41c445ff | 9132 | |
505682cd | 9133 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
9134 | if (pf->vsi[v]) |
9135 | pf->vsi[v]->seid = 0; | |
9136 | } | |
9137 | ||
9138 | i40e_shutdown_adminq(&pf->hw); | |
9139 | ||
f650a38b | 9140 | /* call shutdown HMC */ |
60442dea SN |
9141 | if (hw->hmc.hmc_obj) { |
9142 | ret = i40e_shutdown_lan_hmc(hw); | |
23cfbe07 | 9143 | if (ret) |
60442dea SN |
9144 | dev_warn(&pf->pdev->dev, |
9145 | "shutdown_lan_hmc failed: %d\n", ret); | |
f650a38b | 9146 | } |
f650a38b ASJ |
9147 | } |
9148 | ||
44033fac JB |
9149 | /** |
9150 | * i40e_send_version - update firmware with driver version | |
9151 | * @pf: PF struct | |
9152 | */ | |
9153 | static void i40e_send_version(struct i40e_pf *pf) | |
9154 | { | |
9155 | struct i40e_driver_version dv; | |
9156 | ||
9157 | dv.major_version = DRV_VERSION_MAJOR; | |
9158 | dv.minor_version = DRV_VERSION_MINOR; | |
9159 | dv.build_version = DRV_VERSION_BUILD; | |
9160 | dv.subbuild_version = 0; | |
35a7d804 | 9161 | strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string)); |
44033fac JB |
9162 | i40e_aq_send_driver_version(&pf->hw, &dv, NULL); |
9163 | } | |
9164 | ||
5bbb2e20 FS |
9165 | /** |
9166 | * i40e_get_oem_version - get OEM specific version information | |
9167 | * @hw: pointer to the hardware structure | |
9168 | **/ | |
9169 | static void i40e_get_oem_version(struct i40e_hw *hw) | |
9170 | { | |
9171 | u16 block_offset = 0xffff; | |
9172 | u16 block_length = 0; | |
9173 | u16 capabilities = 0; | |
9174 | u16 gen_snap = 0; | |
9175 | u16 release = 0; | |
9176 | ||
9177 | #define I40E_SR_NVM_OEM_VERSION_PTR 0x1B | |
9178 | #define I40E_NVM_OEM_LENGTH_OFFSET 0x00 | |
9179 | #define I40E_NVM_OEM_CAPABILITIES_OFFSET 0x01 | |
9180 | #define I40E_NVM_OEM_GEN_OFFSET 0x02 | |
9181 | #define I40E_NVM_OEM_RELEASE_OFFSET 0x03 | |
9182 | #define I40E_NVM_OEM_CAPABILITIES_MASK 0x000F | |
9183 | #define I40E_NVM_OEM_LENGTH 3 | |
9184 | ||
9185 | /* Check if pointer to OEM version block is valid. */ | |
9186 | i40e_read_nvm_word(hw, I40E_SR_NVM_OEM_VERSION_PTR, &block_offset); | |
9187 | if (block_offset == 0xffff) | |
9188 | return; | |
9189 | ||
9190 | /* Check if OEM version block has correct length. */ | |
9191 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_LENGTH_OFFSET, | |
9192 | &block_length); | |
9193 | if (block_length < I40E_NVM_OEM_LENGTH) | |
9194 | return; | |
9195 | ||
9196 | /* Check if OEM version format is as expected. */ | |
9197 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_CAPABILITIES_OFFSET, | |
9198 | &capabilities); | |
9199 | if ((capabilities & I40E_NVM_OEM_CAPABILITIES_MASK) != 0) | |
9200 | return; | |
9201 | ||
9202 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_GEN_OFFSET, | |
9203 | &gen_snap); | |
9204 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_RELEASE_OFFSET, | |
9205 | &release); | |
9206 | hw->nvm.oem_ver = (gen_snap << I40E_OEM_SNAP_SHIFT) | release; | |
9207 | hw->nvm.eetrack = I40E_OEM_EETRACK_ID; | |
9208 | } | |
9209 | ||
f650a38b | 9210 | /** |
373149fc | 9211 | * i40e_reset - wait for core reset to finish reset, reset pf if corer not seen |
f650a38b ASJ |
9212 | * @pf: board private structure |
9213 | **/ | |
373149fc | 9214 | static int i40e_reset(struct i40e_pf *pf) |
f650a38b | 9215 | { |
f650a38b ASJ |
9216 | struct i40e_hw *hw = &pf->hw; |
9217 | i40e_status ret; | |
f650a38b | 9218 | |
41c445ff | 9219 | ret = i40e_pf_reset(hw); |
b5565400 | 9220 | if (ret) { |
41c445ff | 9221 | dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret); |
0da36b97 JK |
9222 | set_bit(__I40E_RESET_FAILED, pf->state); |
9223 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); | |
373149fc MS |
9224 | } else { |
9225 | pf->pfr_count++; | |
b5565400 | 9226 | } |
373149fc MS |
9227 | return ret; |
9228 | } | |
9229 | ||
9230 | /** | |
9231 | * i40e_rebuild - rebuild using a saved config | |
9232 | * @pf: board private structure | |
9233 | * @reinit: if the Main VSI needs to re-initialized. | |
9234 | * @lock_acquired: indicates whether or not the lock has been acquired | |
9235 | * before this function was called. | |
9236 | **/ | |
9237 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired) | |
9238 | { | |
2027d4de | 9239 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
373149fc MS |
9240 | struct i40e_hw *hw = &pf->hw; |
9241 | u8 set_fc_aq_fail = 0; | |
9242 | i40e_status ret; | |
9243 | u32 val; | |
9244 | int v; | |
41c445ff | 9245 | |
9e6c9c0f | 9246 | if (test_bit(__I40E_DOWN, pf->state)) |
a316f651 | 9247 | goto clear_recovery; |
69bfb110 | 9248 | dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n"); |
41c445ff JB |
9249 | |
9250 | /* rebuild the basics for the AdminQ, HMC, and initial HW switch */ | |
9251 | ret = i40e_init_adminq(&pf->hw); | |
9252 | if (ret) { | |
f1c7e72e SN |
9253 | dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n", |
9254 | i40e_stat_str(&pf->hw, ret), | |
9255 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
a316f651 | 9256 | goto clear_recovery; |
41c445ff | 9257 | } |
5bbb2e20 | 9258 | i40e_get_oem_version(&pf->hw); |
41c445ff | 9259 | |
4eb3f768 | 9260 | /* re-verify the eeprom if we just had an EMP reset */ |
0da36b97 | 9261 | if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state)) |
4eb3f768 | 9262 | i40e_verify_eeprom(pf); |
4eb3f768 | 9263 | |
e78ac4bf | 9264 | i40e_clear_pxe_mode(hw); |
2f4b411a | 9265 | ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities); |
f1c7e72e | 9266 | if (ret) |
41c445ff | 9267 | goto end_core_reset; |
41c445ff | 9268 | |
41c445ff | 9269 | ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
c76cb6ed | 9270 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
9271 | if (ret) { |
9272 | dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret); | |
9273 | goto end_core_reset; | |
9274 | } | |
9275 | ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
9276 | if (ret) { | |
9277 | dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret); | |
9278 | goto end_core_reset; | |
9279 | } | |
9280 | ||
4e3b35b0 NP |
9281 | #ifdef CONFIG_I40E_DCB |
9282 | ret = i40e_init_pf_dcb(pf); | |
9283 | if (ret) { | |
aebfc816 SN |
9284 | dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret); |
9285 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; | |
9286 | /* Continue without DCB enabled */ | |
4e3b35b0 NP |
9287 | } |
9288 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff | 9289 | /* do basic switch setup */ |
373149fc MS |
9290 | if (!lock_acquired) |
9291 | rtnl_lock(); | |
bc7d338f | 9292 | ret = i40e_setup_pf_switch(pf, reinit); |
41c445ff | 9293 | if (ret) |
373149fc | 9294 | goto end_unlock; |
41c445ff | 9295 | |
2f0aff41 SN |
9296 | /* The driver only wants link up/down and module qualification |
9297 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
9298 | */ |
9299 | ret = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 9300 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 9301 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 9302 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 9303 | if (ret) |
f1c7e72e SN |
9304 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
9305 | i40e_stat_str(&pf->hw, ret), | |
9306 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 9307 | |
cafa2ee6 ASJ |
9308 | /* make sure our flow control settings are restored */ |
9309 | ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true); | |
9310 | if (ret) | |
8279e495 NP |
9311 | dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n", |
9312 | i40e_stat_str(&pf->hw, ret), | |
9313 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 9314 | |
41c445ff JB |
9315 | /* Rebuild the VSIs and VEBs that existed before reset. |
9316 | * They are still in our local switch element arrays, so only | |
9317 | * need to rebuild the switch model in the HW. | |
9318 | * | |
9319 | * If there were VEBs but the reconstitution failed, we'll try | |
9320 | * try to recover minimal use by getting the basic PF VSI working. | |
9321 | */ | |
2027d4de | 9322 | if (vsi->uplink_seid != pf->mac_seid) { |
69bfb110 | 9323 | dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n"); |
41c445ff JB |
9324 | /* find the one VEB connected to the MAC, and find orphans */ |
9325 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
9326 | if (!pf->veb[v]) | |
9327 | continue; | |
9328 | ||
9329 | if (pf->veb[v]->uplink_seid == pf->mac_seid || | |
9330 | pf->veb[v]->uplink_seid == 0) { | |
9331 | ret = i40e_reconstitute_veb(pf->veb[v]); | |
9332 | ||
9333 | if (!ret) | |
9334 | continue; | |
9335 | ||
9336 | /* If Main VEB failed, we're in deep doodoo, | |
9337 | * so give up rebuilding the switch and set up | |
9338 | * for minimal rebuild of PF VSI. | |
9339 | * If orphan failed, we'll report the error | |
9340 | * but try to keep going. | |
9341 | */ | |
9342 | if (pf->veb[v]->uplink_seid == pf->mac_seid) { | |
9343 | dev_info(&pf->pdev->dev, | |
9344 | "rebuild of switch failed: %d, will try to set up simple PF connection\n", | |
9345 | ret); | |
2027d4de | 9346 | vsi->uplink_seid = pf->mac_seid; |
41c445ff JB |
9347 | break; |
9348 | } else if (pf->veb[v]->uplink_seid == 0) { | |
9349 | dev_info(&pf->pdev->dev, | |
9350 | "rebuild of orphan VEB failed: %d\n", | |
9351 | ret); | |
9352 | } | |
9353 | } | |
9354 | } | |
9355 | } | |
9356 | ||
2027d4de | 9357 | if (vsi->uplink_seid == pf->mac_seid) { |
cde4cbc7 | 9358 | dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n"); |
41c445ff | 9359 | /* no VEB, so rebuild only the Main VSI */ |
2027d4de | 9360 | ret = i40e_add_vsi(vsi); |
41c445ff JB |
9361 | if (ret) { |
9362 | dev_info(&pf->pdev->dev, | |
9363 | "rebuild of Main VSI failed: %d\n", ret); | |
373149fc | 9364 | goto end_unlock; |
41c445ff JB |
9365 | } |
9366 | } | |
9367 | ||
2027d4de | 9368 | if (vsi->mqprio_qopt.max_rate[0]) { |
6c32e0d9 AB |
9369 | u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0]; |
9370 | u64 credits = 0; | |
2027d4de | 9371 | |
6c32e0d9 | 9372 | do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR); |
2027d4de | 9373 | ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate); |
6c32e0d9 | 9374 | if (ret) |
2027d4de | 9375 | goto end_unlock; |
6c32e0d9 AB |
9376 | |
9377 | credits = max_tx_rate; | |
9378 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
9379 | dev_dbg(&vsi->back->pdev->dev, | |
9380 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
9381 | max_tx_rate, | |
9382 | credits, | |
9383 | vsi->seid); | |
2027d4de AN |
9384 | } |
9385 | ||
2f4b411a AN |
9386 | ret = i40e_rebuild_cloud_filters(vsi, vsi->seid); |
9387 | if (ret) | |
9388 | goto end_unlock; | |
9389 | ||
8f88b303 AN |
9390 | /* PF Main VSI is rebuild by now, go ahead and rebuild channel VSIs |
9391 | * for this main VSI if they exist | |
9392 | */ | |
2027d4de | 9393 | ret = i40e_rebuild_channels(vsi); |
8f88b303 AN |
9394 | if (ret) |
9395 | goto end_unlock; | |
9396 | ||
4f2f017c ASJ |
9397 | /* Reconfigure hardware for allowing smaller MSS in the case |
9398 | * of TSO, so that we avoid the MDD being fired and causing | |
9399 | * a reset in the case of small MSS+TSO. | |
9400 | */ | |
9401 | #define I40E_REG_MSS 0x000E64DC | |
9402 | #define I40E_REG_MSS_MIN_MASK 0x3FF0000 | |
9403 | #define I40E_64BYTE_MSS 0x400000 | |
9404 | val = rd32(hw, I40E_REG_MSS); | |
9405 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
9406 | val &= ~I40E_REG_MSS_MIN_MASK; | |
9407 | val |= I40E_64BYTE_MSS; | |
9408 | wr32(hw, I40E_REG_MSS, val); | |
9409 | } | |
9410 | ||
d36e41dc | 9411 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
9412 | msleep(75); |
9413 | ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
9414 | if (ret) | |
f1c7e72e SN |
9415 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
9416 | i40e_stat_str(&pf->hw, ret), | |
9417 | i40e_aq_str(&pf->hw, | |
9418 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 9419 | } |
41c445ff JB |
9420 | /* reinit the misc interrupt */ |
9421 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
9422 | ret = i40e_setup_misc_vector(pf); | |
9423 | ||
e7358f54 ASJ |
9424 | /* Add a filter to drop all Flow control frames from any VSI from being |
9425 | * transmitted. By doing so we stop a malicious VF from sending out | |
9426 | * PAUSE or PFC frames and potentially controlling traffic for other | |
9427 | * PF/VF VSIs. | |
9428 | * The FW can still send Flow control frames if enabled. | |
9429 | */ | |
9430 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
9431 | pf->main_vsi_seid); | |
9432 | ||
41c445ff JB |
9433 | /* restart the VSIs that were rebuilt and running before the reset */ |
9434 | i40e_pf_unquiesce_all_vsi(pf); | |
9435 | ||
024b05f4 JK |
9436 | /* Release the RTNL lock before we start resetting VFs */ |
9437 | if (!lock_acquired) | |
9438 | rtnl_unlock(); | |
9439 | ||
bd5608b3 AB |
9440 | /* Restore promiscuous settings */ |
9441 | ret = i40e_set_promiscuous(pf, pf->cur_promisc); | |
9442 | if (ret) | |
9443 | dev_warn(&pf->pdev->dev, | |
9444 | "Failed to restore promiscuous setting: %s, err %s aq_err %s\n", | |
9445 | pf->cur_promisc ? "on" : "off", | |
9446 | i40e_stat_str(&pf->hw, ret), | |
9447 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
9448 | ||
e4b433f4 | 9449 | i40e_reset_all_vfs(pf, true); |
69f64b2b | 9450 | |
41c445ff | 9451 | /* tell the firmware that we're starting */ |
44033fac | 9452 | i40e_send_version(pf); |
41c445ff | 9453 | |
024b05f4 JK |
9454 | /* We've already released the lock, so don't do it again */ |
9455 | goto end_core_reset; | |
9456 | ||
373149fc | 9457 | end_unlock: |
024b05f4 JK |
9458 | if (!lock_acquired) |
9459 | rtnl_unlock(); | |
41c445ff | 9460 | end_core_reset: |
0da36b97 | 9461 | clear_bit(__I40E_RESET_FAILED, pf->state); |
a316f651 | 9462 | clear_recovery: |
0da36b97 | 9463 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); |
41c445ff JB |
9464 | } |
9465 | ||
373149fc MS |
9466 | /** |
9467 | * i40e_reset_and_rebuild - reset and rebuild using a saved config | |
9468 | * @pf: board private structure | |
9469 | * @reinit: if the Main VSI needs to re-initialized. | |
9470 | * @lock_acquired: indicates whether or not the lock has been acquired | |
9471 | * before this function was called. | |
9472 | **/ | |
9473 | static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit, | |
9474 | bool lock_acquired) | |
9475 | { | |
9476 | int ret; | |
9477 | /* Now we wait for GRST to settle out. | |
9478 | * We don't have to delete the VEBs or VSIs from the hw switch | |
9479 | * because the reset will make them disappear. | |
9480 | */ | |
9481 | ret = i40e_reset(pf); | |
9482 | if (!ret) | |
9483 | i40e_rebuild(pf, reinit, lock_acquired); | |
9484 | } | |
9485 | ||
f650a38b | 9486 | /** |
b40c82e6 | 9487 | * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild |
f650a38b ASJ |
9488 | * @pf: board private structure |
9489 | * | |
9490 | * Close up the VFs and other things in prep for a Core Reset, | |
9491 | * then get ready to rebuild the world. | |
373149fc MS |
9492 | * @lock_acquired: indicates whether or not the lock has been acquired |
9493 | * before this function was called. | |
f650a38b | 9494 | **/ |
373149fc | 9495 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired) |
f650a38b | 9496 | { |
373149fc MS |
9497 | i40e_prep_for_reset(pf, lock_acquired); |
9498 | i40e_reset_and_rebuild(pf, false, lock_acquired); | |
f650a38b ASJ |
9499 | } |
9500 | ||
41c445ff JB |
9501 | /** |
9502 | * i40e_handle_mdd_event | |
b40c82e6 | 9503 | * @pf: pointer to the PF structure |
41c445ff JB |
9504 | * |
9505 | * Called from the MDD irq handler to identify possibly malicious vfs | |
9506 | **/ | |
9507 | static void i40e_handle_mdd_event(struct i40e_pf *pf) | |
9508 | { | |
9509 | struct i40e_hw *hw = &pf->hw; | |
9510 | bool mdd_detected = false; | |
df430b12 | 9511 | bool pf_mdd_detected = false; |
41c445ff JB |
9512 | struct i40e_vf *vf; |
9513 | u32 reg; | |
9514 | int i; | |
9515 | ||
0da36b97 | 9516 | if (!test_bit(__I40E_MDD_EVENT_PENDING, pf->state)) |
41c445ff JB |
9517 | return; |
9518 | ||
9519 | /* find what triggered the MDD event */ | |
9520 | reg = rd32(hw, I40E_GL_MDET_TX); | |
9521 | if (reg & I40E_GL_MDET_TX_VALID_MASK) { | |
4c33f83a ASJ |
9522 | u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> |
9523 | I40E_GL_MDET_TX_PF_NUM_SHIFT; | |
2089ad03 | 9524 | u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> |
4c33f83a | 9525 | I40E_GL_MDET_TX_VF_NUM_SHIFT; |
013f6579 | 9526 | u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> |
4c33f83a | 9527 | I40E_GL_MDET_TX_EVENT_SHIFT; |
2089ad03 MW |
9528 | u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> |
9529 | I40E_GL_MDET_TX_QUEUE_SHIFT) - | |
9530 | pf->hw.func_caps.base_queue; | |
faf32978 | 9531 | if (netif_msg_tx_err(pf)) |
b40c82e6 | 9532 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", |
faf32978 | 9533 | event, queue, pf_num, vf_num); |
41c445ff JB |
9534 | wr32(hw, I40E_GL_MDET_TX, 0xffffffff); |
9535 | mdd_detected = true; | |
9536 | } | |
9537 | reg = rd32(hw, I40E_GL_MDET_RX); | |
9538 | if (reg & I40E_GL_MDET_RX_VALID_MASK) { | |
4c33f83a ASJ |
9539 | u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> |
9540 | I40E_GL_MDET_RX_FUNCTION_SHIFT; | |
013f6579 | 9541 | u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> |
4c33f83a | 9542 | I40E_GL_MDET_RX_EVENT_SHIFT; |
2089ad03 MW |
9543 | u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> |
9544 | I40E_GL_MDET_RX_QUEUE_SHIFT) - | |
9545 | pf->hw.func_caps.base_queue; | |
faf32978 JB |
9546 | if (netif_msg_rx_err(pf)) |
9547 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", | |
9548 | event, queue, func); | |
41c445ff JB |
9549 | wr32(hw, I40E_GL_MDET_RX, 0xffffffff); |
9550 | mdd_detected = true; | |
9551 | } | |
9552 | ||
df430b12 NP |
9553 | if (mdd_detected) { |
9554 | reg = rd32(hw, I40E_PF_MDET_TX); | |
9555 | if (reg & I40E_PF_MDET_TX_VALID_MASK) { | |
9556 | wr32(hw, I40E_PF_MDET_TX, 0xFFFF); | |
faf32978 | 9557 | dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n"); |
df430b12 NP |
9558 | pf_mdd_detected = true; |
9559 | } | |
9560 | reg = rd32(hw, I40E_PF_MDET_RX); | |
9561 | if (reg & I40E_PF_MDET_RX_VALID_MASK) { | |
9562 | wr32(hw, I40E_PF_MDET_RX, 0xFFFF); | |
faf32978 | 9563 | dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n"); |
df430b12 NP |
9564 | pf_mdd_detected = true; |
9565 | } | |
9566 | /* Queue belongs to the PF, initiate a reset */ | |
9567 | if (pf_mdd_detected) { | |
0da36b97 | 9568 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
df430b12 NP |
9569 | i40e_service_event_schedule(pf); |
9570 | } | |
9571 | } | |
9572 | ||
41c445ff JB |
9573 | /* see if one of the VFs needs its hand slapped */ |
9574 | for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) { | |
9575 | vf = &(pf->vf[i]); | |
9576 | reg = rd32(hw, I40E_VP_MDET_TX(i)); | |
9577 | if (reg & I40E_VP_MDET_TX_VALID_MASK) { | |
9578 | wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF); | |
9579 | vf->num_mdd_events++; | |
faf32978 JB |
9580 | dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n", |
9581 | i); | |
41c445ff JB |
9582 | } |
9583 | ||
9584 | reg = rd32(hw, I40E_VP_MDET_RX(i)); | |
9585 | if (reg & I40E_VP_MDET_RX_VALID_MASK) { | |
9586 | wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF); | |
9587 | vf->num_mdd_events++; | |
faf32978 JB |
9588 | dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n", |
9589 | i); | |
41c445ff JB |
9590 | } |
9591 | ||
9592 | if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) { | |
9593 | dev_info(&pf->pdev->dev, | |
9594 | "Too many MDD events on VF %d, disabled\n", i); | |
9595 | dev_info(&pf->pdev->dev, | |
9596 | "Use PF Control I/F to re-enable the VF\n"); | |
6322e63c | 9597 | set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states); |
41c445ff JB |
9598 | } |
9599 | } | |
9600 | ||
9601 | /* re-enable mdd interrupt cause */ | |
0da36b97 | 9602 | clear_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
9603 | reg = rd32(hw, I40E_PFINT_ICR0_ENA); |
9604 | reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
9605 | wr32(hw, I40E_PFINT_ICR0_ENA, reg); | |
9606 | i40e_flush(hw); | |
9607 | } | |
9608 | ||
d8b2c700 JK |
9609 | static const char *i40e_tunnel_name(struct i40e_udp_port_config *port) |
9610 | { | |
9611 | switch (port->type) { | |
9612 | case UDP_TUNNEL_TYPE_VXLAN: | |
9613 | return "vxlan"; | |
9614 | case UDP_TUNNEL_TYPE_GENEVE: | |
9615 | return "geneve"; | |
9616 | default: | |
9617 | return "unknown"; | |
9618 | } | |
9619 | } | |
9620 | ||
1f190d93 AD |
9621 | /** |
9622 | * i40e_sync_udp_filters - Trigger a sync event for existing UDP filters | |
9623 | * @pf: board private structure | |
9624 | **/ | |
9625 | static void i40e_sync_udp_filters(struct i40e_pf *pf) | |
9626 | { | |
9627 | int i; | |
9628 | ||
9629 | /* loop through and set pending bit for all active UDP filters */ | |
9630 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
9631 | if (pf->udp_ports[i].port) | |
9632 | pf->pending_udp_bitmap |= BIT_ULL(i); | |
9633 | } | |
9634 | ||
9635 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
9636 | } | |
9637 | ||
a1c9a9d9 | 9638 | /** |
6a899024 | 9639 | * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW |
a1c9a9d9 JK |
9640 | * @pf: board private structure |
9641 | **/ | |
6a899024 | 9642 | static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf) |
a1c9a9d9 | 9643 | { |
a1c9a9d9 JK |
9644 | struct i40e_hw *hw = &pf->hw; |
9645 | i40e_status ret; | |
fe0b0cd9 | 9646 | u16 port; |
a1c9a9d9 JK |
9647 | int i; |
9648 | ||
6a899024 | 9649 | if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC)) |
a1c9a9d9 JK |
9650 | return; |
9651 | ||
6a899024 | 9652 | pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC; |
a1c9a9d9 JK |
9653 | |
9654 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
6a899024 SA |
9655 | if (pf->pending_udp_bitmap & BIT_ULL(i)) { |
9656 | pf->pending_udp_bitmap &= ~BIT_ULL(i); | |
27826fd5 | 9657 | port = pf->udp_ports[i].port; |
c22c06c8 | 9658 | if (port) |
b3f5c7bc CW |
9659 | ret = i40e_aq_add_udp_tunnel(hw, port, |
9660 | pf->udp_ports[i].type, | |
9661 | NULL, NULL); | |
c22c06c8 SN |
9662 | else |
9663 | ret = i40e_aq_del_udp_tunnel(hw, i, NULL); | |
a1c9a9d9 JK |
9664 | |
9665 | if (ret) { | |
d8b2c700 JK |
9666 | dev_info(&pf->pdev->dev, |
9667 | "%s %s port %d, index %d failed, err %s aq_err %s\n", | |
9668 | i40e_tunnel_name(&pf->udp_ports[i]), | |
9669 | port ? "add" : "delete", | |
9670 | port, i, | |
9671 | i40e_stat_str(&pf->hw, ret), | |
9672 | i40e_aq_str(&pf->hw, | |
9673 | pf->hw.aq.asq_last_status)); | |
27826fd5 | 9674 | pf->udp_ports[i].port = 0; |
a1c9a9d9 JK |
9675 | } |
9676 | } | |
9677 | } | |
9678 | } | |
9679 | ||
41c445ff JB |
9680 | /** |
9681 | * i40e_service_task - Run the driver's async subtasks | |
9682 | * @work: pointer to work_struct containing our data | |
9683 | **/ | |
9684 | static void i40e_service_task(struct work_struct *work) | |
9685 | { | |
9686 | struct i40e_pf *pf = container_of(work, | |
9687 | struct i40e_pf, | |
9688 | service_task); | |
9689 | unsigned long start_time = jiffies; | |
9690 | ||
e57a2fea | 9691 | /* don't bother with service tasks if a reset is in progress */ |
0da36b97 | 9692 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
e57a2fea | 9693 | return; |
e57a2fea | 9694 | |
0da36b97 | 9695 | if (test_and_set_bit(__I40E_SERVICE_SCHED, pf->state)) |
91089033 MW |
9696 | return; |
9697 | ||
b03a8c1f | 9698 | i40e_detect_recover_hung(pf); |
2818ccd9 | 9699 | i40e_sync_filters_subtask(pf); |
41c445ff JB |
9700 | i40e_reset_subtask(pf); |
9701 | i40e_handle_mdd_event(pf); | |
9702 | i40e_vc_process_vflr_event(pf); | |
9703 | i40e_watchdog_subtask(pf); | |
9704 | i40e_fdir_reinit_subtask(pf); | |
0ef2d5af MW |
9705 | if (pf->flags & I40E_FLAG_CLIENT_RESET) { |
9706 | /* Client subtask will reopen next time through. */ | |
9707 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], true); | |
9708 | pf->flags &= ~I40E_FLAG_CLIENT_RESET; | |
9709 | } else { | |
9710 | i40e_client_subtask(pf); | |
9711 | if (pf->flags & I40E_FLAG_CLIENT_L2_CHANGE) { | |
9712 | i40e_notify_client_of_l2_param_changes( | |
9713 | pf->vsi[pf->lan_vsi]); | |
9714 | pf->flags &= ~I40E_FLAG_CLIENT_L2_CHANGE; | |
9715 | } | |
9716 | } | |
41c445ff | 9717 | i40e_sync_filters_subtask(pf); |
6a899024 | 9718 | i40e_sync_udp_filters_subtask(pf); |
41c445ff JB |
9719 | i40e_clean_adminq_subtask(pf); |
9720 | ||
91089033 MW |
9721 | /* flush memory to make sure state is correct before next watchdog */ |
9722 | smp_mb__before_atomic(); | |
0da36b97 | 9723 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff JB |
9724 | |
9725 | /* If the tasks have taken longer than one timer cycle or there | |
9726 | * is more work to be done, reschedule the service task now | |
9727 | * rather than wait for the timer to tick again. | |
9728 | */ | |
9729 | if (time_after(jiffies, (start_time + pf->service_timer_period)) || | |
0da36b97 JK |
9730 | test_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state) || |
9731 | test_bit(__I40E_MDD_EVENT_PENDING, pf->state) || | |
9732 | test_bit(__I40E_VFLR_EVENT_PENDING, pf->state)) | |
41c445ff JB |
9733 | i40e_service_event_schedule(pf); |
9734 | } | |
9735 | ||
9736 | /** | |
9737 | * i40e_service_timer - timer callback | |
9738 | * @data: pointer to PF struct | |
9739 | **/ | |
26566eae | 9740 | static void i40e_service_timer(struct timer_list *t) |
41c445ff | 9741 | { |
26566eae | 9742 | struct i40e_pf *pf = from_timer(pf, t, service_timer); |
41c445ff JB |
9743 | |
9744 | mod_timer(&pf->service_timer, | |
9745 | round_jiffies(jiffies + pf->service_timer_period)); | |
9746 | i40e_service_event_schedule(pf); | |
9747 | } | |
9748 | ||
9749 | /** | |
9750 | * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI | |
9751 | * @vsi: the VSI being configured | |
9752 | **/ | |
9753 | static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) | |
9754 | { | |
9755 | struct i40e_pf *pf = vsi->back; | |
9756 | ||
9757 | switch (vsi->type) { | |
9758 | case I40E_VSI_MAIN: | |
9759 | vsi->alloc_queue_pairs = pf->num_lan_qps; | |
9760 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
9761 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
9762 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
9763 | vsi->num_q_vectors = pf->num_lan_msix; | |
9764 | else | |
9765 | vsi->num_q_vectors = 1; | |
9766 | ||
9767 | break; | |
9768 | ||
9769 | case I40E_VSI_FDIR: | |
9770 | vsi->alloc_queue_pairs = 1; | |
9771 | vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT, | |
9772 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
a70e407f | 9773 | vsi->num_q_vectors = pf->num_fdsb_msix; |
41c445ff JB |
9774 | break; |
9775 | ||
9776 | case I40E_VSI_VMDQ2: | |
9777 | vsi->alloc_queue_pairs = pf->num_vmdq_qps; | |
9778 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
9779 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
9780 | vsi->num_q_vectors = pf->num_vmdq_msix; | |
9781 | break; | |
9782 | ||
9783 | case I40E_VSI_SRIOV: | |
9784 | vsi->alloc_queue_pairs = pf->num_vf_qps; | |
9785 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
9786 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
9787 | break; | |
9788 | ||
9789 | default: | |
9790 | WARN_ON(1); | |
9791 | return -ENODATA; | |
9792 | } | |
9793 | ||
9794 | return 0; | |
9795 | } | |
9796 | ||
f650a38b ASJ |
9797 | /** |
9798 | * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi | |
3d7d7a86 | 9799 | * @vsi: VSI pointer |
bc7d338f | 9800 | * @alloc_qvectors: a bool to specify if q_vectors need to be allocated. |
f650a38b ASJ |
9801 | * |
9802 | * On error: returns error code (negative) | |
9803 | * On success: returns 0 | |
9804 | **/ | |
bc7d338f | 9805 | static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors) |
f650a38b | 9806 | { |
74608d17 | 9807 | struct i40e_ring **next_rings; |
f650a38b ASJ |
9808 | int size; |
9809 | int ret = 0; | |
9810 | ||
74608d17 BT |
9811 | /* allocate memory for both Tx, XDP Tx and Rx ring pointers */ |
9812 | size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * | |
9813 | (i40e_enabled_xdp_vsi(vsi) ? 3 : 2); | |
f650a38b ASJ |
9814 | vsi->tx_rings = kzalloc(size, GFP_KERNEL); |
9815 | if (!vsi->tx_rings) | |
9816 | return -ENOMEM; | |
74608d17 BT |
9817 | next_rings = vsi->tx_rings + vsi->alloc_queue_pairs; |
9818 | if (i40e_enabled_xdp_vsi(vsi)) { | |
9819 | vsi->xdp_rings = next_rings; | |
9820 | next_rings += vsi->alloc_queue_pairs; | |
9821 | } | |
9822 | vsi->rx_rings = next_rings; | |
f650a38b | 9823 | |
bc7d338f ASJ |
9824 | if (alloc_qvectors) { |
9825 | /* allocate memory for q_vector pointers */ | |
f57e4fbd | 9826 | size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors; |
bc7d338f ASJ |
9827 | vsi->q_vectors = kzalloc(size, GFP_KERNEL); |
9828 | if (!vsi->q_vectors) { | |
9829 | ret = -ENOMEM; | |
9830 | goto err_vectors; | |
9831 | } | |
f650a38b ASJ |
9832 | } |
9833 | return ret; | |
9834 | ||
9835 | err_vectors: | |
9836 | kfree(vsi->tx_rings); | |
9837 | return ret; | |
9838 | } | |
9839 | ||
41c445ff JB |
9840 | /** |
9841 | * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF | |
9842 | * @pf: board private structure | |
9843 | * @type: type of VSI | |
9844 | * | |
9845 | * On error: returns error code (negative) | |
9846 | * On success: returns vsi index in PF (positive) | |
9847 | **/ | |
9848 | static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type) | |
9849 | { | |
9850 | int ret = -ENODEV; | |
9851 | struct i40e_vsi *vsi; | |
9852 | int vsi_idx; | |
9853 | int i; | |
9854 | ||
9855 | /* Need to protect the allocation of the VSIs at the PF level */ | |
9856 | mutex_lock(&pf->switch_mutex); | |
9857 | ||
9858 | /* VSI list may be fragmented if VSI creation/destruction has | |
9859 | * been happening. We can afford to do a quick scan to look | |
9860 | * for any free VSIs in the list. | |
9861 | * | |
9862 | * find next empty vsi slot, looping back around if necessary | |
9863 | */ | |
9864 | i = pf->next_vsi; | |
505682cd | 9865 | while (i < pf->num_alloc_vsi && pf->vsi[i]) |
41c445ff | 9866 | i++; |
505682cd | 9867 | if (i >= pf->num_alloc_vsi) { |
41c445ff JB |
9868 | i = 0; |
9869 | while (i < pf->next_vsi && pf->vsi[i]) | |
9870 | i++; | |
9871 | } | |
9872 | ||
505682cd | 9873 | if (i < pf->num_alloc_vsi && !pf->vsi[i]) { |
41c445ff JB |
9874 | vsi_idx = i; /* Found one! */ |
9875 | } else { | |
9876 | ret = -ENODEV; | |
493fb300 | 9877 | goto unlock_pf; /* out of VSI slots! */ |
41c445ff JB |
9878 | } |
9879 | pf->next_vsi = ++i; | |
9880 | ||
9881 | vsi = kzalloc(sizeof(*vsi), GFP_KERNEL); | |
9882 | if (!vsi) { | |
9883 | ret = -ENOMEM; | |
493fb300 | 9884 | goto unlock_pf; |
41c445ff JB |
9885 | } |
9886 | vsi->type = type; | |
9887 | vsi->back = pf; | |
0da36b97 | 9888 | set_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
9889 | vsi->flags = 0; |
9890 | vsi->idx = vsi_idx; | |
ac26fc13 | 9891 | vsi->int_rate_limit = 0; |
5db4cb59 ASJ |
9892 | vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ? |
9893 | pf->rss_table_size : 64; | |
41c445ff JB |
9894 | vsi->netdev_registered = false; |
9895 | vsi->work_limit = I40E_DEFAULT_IRQ_WORK; | |
278e7d0b | 9896 | hash_init(vsi->mac_filter_hash); |
63741846 | 9897 | vsi->irqs_ready = false; |
41c445ff | 9898 | |
9f65e15b AD |
9899 | ret = i40e_set_num_rings_in_vsi(vsi); |
9900 | if (ret) | |
9901 | goto err_rings; | |
9902 | ||
bc7d338f | 9903 | ret = i40e_vsi_alloc_arrays(vsi, true); |
f650a38b | 9904 | if (ret) |
9f65e15b | 9905 | goto err_rings; |
493fb300 | 9906 | |
41c445ff JB |
9907 | /* Setup default MSIX irq handler for VSI */ |
9908 | i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings); | |
9909 | ||
21659035 | 9910 | /* Initialize VSI lock */ |
278e7d0b | 9911 | spin_lock_init(&vsi->mac_filter_hash_lock); |
41c445ff JB |
9912 | pf->vsi[vsi_idx] = vsi; |
9913 | ret = vsi_idx; | |
493fb300 AD |
9914 | goto unlock_pf; |
9915 | ||
9f65e15b | 9916 | err_rings: |
493fb300 AD |
9917 | pf->next_vsi = i - 1; |
9918 | kfree(vsi); | |
9919 | unlock_pf: | |
41c445ff JB |
9920 | mutex_unlock(&pf->switch_mutex); |
9921 | return ret; | |
9922 | } | |
9923 | ||
f650a38b ASJ |
9924 | /** |
9925 | * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI | |
9926 | * @type: VSI pointer | |
bc7d338f | 9927 | * @free_qvectors: a bool to specify if q_vectors need to be freed. |
f650a38b ASJ |
9928 | * |
9929 | * On error: returns error code (negative) | |
9930 | * On success: returns 0 | |
9931 | **/ | |
bc7d338f | 9932 | static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors) |
f650a38b ASJ |
9933 | { |
9934 | /* free the ring and vector containers */ | |
bc7d338f ASJ |
9935 | if (free_qvectors) { |
9936 | kfree(vsi->q_vectors); | |
9937 | vsi->q_vectors = NULL; | |
9938 | } | |
f650a38b ASJ |
9939 | kfree(vsi->tx_rings); |
9940 | vsi->tx_rings = NULL; | |
9941 | vsi->rx_rings = NULL; | |
74608d17 | 9942 | vsi->xdp_rings = NULL; |
f650a38b ASJ |
9943 | } |
9944 | ||
28c5869f HZ |
9945 | /** |
9946 | * i40e_clear_rss_config_user - clear the user configured RSS hash keys | |
9947 | * and lookup table | |
9948 | * @vsi: Pointer to VSI structure | |
9949 | */ | |
9950 | static void i40e_clear_rss_config_user(struct i40e_vsi *vsi) | |
9951 | { | |
9952 | if (!vsi) | |
9953 | return; | |
9954 | ||
9955 | kfree(vsi->rss_hkey_user); | |
9956 | vsi->rss_hkey_user = NULL; | |
9957 | ||
9958 | kfree(vsi->rss_lut_user); | |
9959 | vsi->rss_lut_user = NULL; | |
9960 | } | |
9961 | ||
41c445ff JB |
9962 | /** |
9963 | * i40e_vsi_clear - Deallocate the VSI provided | |
9964 | * @vsi: the VSI being un-configured | |
9965 | **/ | |
9966 | static int i40e_vsi_clear(struct i40e_vsi *vsi) | |
9967 | { | |
9968 | struct i40e_pf *pf; | |
9969 | ||
9970 | if (!vsi) | |
9971 | return 0; | |
9972 | ||
9973 | if (!vsi->back) | |
9974 | goto free_vsi; | |
9975 | pf = vsi->back; | |
9976 | ||
9977 | mutex_lock(&pf->switch_mutex); | |
9978 | if (!pf->vsi[vsi->idx]) { | |
9979 | dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n", | |
9980 | vsi->idx, vsi->idx, vsi, vsi->type); | |
9981 | goto unlock_vsi; | |
9982 | } | |
9983 | ||
9984 | if (pf->vsi[vsi->idx] != vsi) { | |
9985 | dev_err(&pf->pdev->dev, | |
9986 | "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n", | |
9987 | pf->vsi[vsi->idx]->idx, | |
9988 | pf->vsi[vsi->idx], | |
9989 | pf->vsi[vsi->idx]->type, | |
9990 | vsi->idx, vsi, vsi->type); | |
9991 | goto unlock_vsi; | |
9992 | } | |
9993 | ||
b40c82e6 | 9994 | /* updates the PF for this cleared vsi */ |
41c445ff JB |
9995 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
9996 | i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx); | |
9997 | ||
bc7d338f | 9998 | i40e_vsi_free_arrays(vsi, true); |
28c5869f | 9999 | i40e_clear_rss_config_user(vsi); |
493fb300 | 10000 | |
41c445ff JB |
10001 | pf->vsi[vsi->idx] = NULL; |
10002 | if (vsi->idx < pf->next_vsi) | |
10003 | pf->next_vsi = vsi->idx; | |
10004 | ||
10005 | unlock_vsi: | |
10006 | mutex_unlock(&pf->switch_mutex); | |
10007 | free_vsi: | |
10008 | kfree(vsi); | |
10009 | ||
10010 | return 0; | |
10011 | } | |
10012 | ||
9f65e15b AD |
10013 | /** |
10014 | * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI | |
10015 | * @vsi: the VSI being cleaned | |
10016 | **/ | |
be1d5eea | 10017 | static void i40e_vsi_clear_rings(struct i40e_vsi *vsi) |
9f65e15b AD |
10018 | { |
10019 | int i; | |
10020 | ||
8e9dca53 | 10021 | if (vsi->tx_rings && vsi->tx_rings[0]) { |
d7397644 | 10022 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
00403f04 MW |
10023 | kfree_rcu(vsi->tx_rings[i], rcu); |
10024 | vsi->tx_rings[i] = NULL; | |
10025 | vsi->rx_rings[i] = NULL; | |
74608d17 BT |
10026 | if (vsi->xdp_rings) |
10027 | vsi->xdp_rings[i] = NULL; | |
00403f04 | 10028 | } |
be1d5eea | 10029 | } |
9f65e15b AD |
10030 | } |
10031 | ||
41c445ff JB |
10032 | /** |
10033 | * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI | |
10034 | * @vsi: the VSI being configured | |
10035 | **/ | |
10036 | static int i40e_alloc_rings(struct i40e_vsi *vsi) | |
10037 | { | |
74608d17 | 10038 | int i, qpv = i40e_enabled_xdp_vsi(vsi) ? 3 : 2; |
41c445ff | 10039 | struct i40e_pf *pf = vsi->back; |
74608d17 | 10040 | struct i40e_ring *ring; |
41c445ff | 10041 | |
41c445ff | 10042 | /* Set basic values in the rings to be used later during open() */ |
d7397644 | 10043 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
ac6c5e3d | 10044 | /* allocate space for both Tx and Rx in one shot */ |
74608d17 BT |
10045 | ring = kcalloc(qpv, sizeof(struct i40e_ring), GFP_KERNEL); |
10046 | if (!ring) | |
9f65e15b | 10047 | goto err_out; |
41c445ff | 10048 | |
74608d17 BT |
10049 | ring->queue_index = i; |
10050 | ring->reg_idx = vsi->base_queue + i; | |
10051 | ring->ring_active = false; | |
10052 | ring->vsi = vsi; | |
10053 | ring->netdev = vsi->netdev; | |
10054 | ring->dev = &pf->pdev->dev; | |
10055 | ring->count = vsi->num_desc; | |
10056 | ring->size = 0; | |
10057 | ring->dcb_tc = 0; | |
d36e41dc | 10058 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 BT |
10059 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
10060 | ring->tx_itr_setting = pf->tx_itr_default; | |
10061 | vsi->tx_rings[i] = ring++; | |
10062 | ||
10063 | if (!i40e_enabled_xdp_vsi(vsi)) | |
10064 | goto setup_rx; | |
10065 | ||
10066 | ring->queue_index = vsi->alloc_queue_pairs + i; | |
10067 | ring->reg_idx = vsi->base_queue + ring->queue_index; | |
10068 | ring->ring_active = false; | |
10069 | ring->vsi = vsi; | |
10070 | ring->netdev = NULL; | |
10071 | ring->dev = &pf->pdev->dev; | |
10072 | ring->count = vsi->num_desc; | |
10073 | ring->size = 0; | |
10074 | ring->dcb_tc = 0; | |
d36e41dc | 10075 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 BT |
10076 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
10077 | set_ring_xdp(ring); | |
10078 | ring->tx_itr_setting = pf->tx_itr_default; | |
10079 | vsi->xdp_rings[i] = ring++; | |
10080 | ||
10081 | setup_rx: | |
10082 | ring->queue_index = i; | |
10083 | ring->reg_idx = vsi->base_queue + i; | |
10084 | ring->ring_active = false; | |
10085 | ring->vsi = vsi; | |
10086 | ring->netdev = vsi->netdev; | |
10087 | ring->dev = &pf->pdev->dev; | |
10088 | ring->count = vsi->num_desc; | |
10089 | ring->size = 0; | |
10090 | ring->dcb_tc = 0; | |
10091 | ring->rx_itr_setting = pf->rx_itr_default; | |
10092 | vsi->rx_rings[i] = ring; | |
41c445ff JB |
10093 | } |
10094 | ||
10095 | return 0; | |
9f65e15b AD |
10096 | |
10097 | err_out: | |
10098 | i40e_vsi_clear_rings(vsi); | |
10099 | return -ENOMEM; | |
41c445ff JB |
10100 | } |
10101 | ||
10102 | /** | |
10103 | * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel | |
10104 | * @pf: board private structure | |
10105 | * @vectors: the number of MSI-X vectors to request | |
10106 | * | |
10107 | * Returns the number of vectors reserved, or error | |
10108 | **/ | |
10109 | static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors) | |
10110 | { | |
7b37f376 AG |
10111 | vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries, |
10112 | I40E_MIN_MSIX, vectors); | |
10113 | if (vectors < 0) { | |
41c445ff | 10114 | dev_info(&pf->pdev->dev, |
7b37f376 | 10115 | "MSI-X vector reservation failed: %d\n", vectors); |
41c445ff JB |
10116 | vectors = 0; |
10117 | } | |
10118 | ||
10119 | return vectors; | |
10120 | } | |
10121 | ||
10122 | /** | |
10123 | * i40e_init_msix - Setup the MSIX capability | |
10124 | * @pf: board private structure | |
10125 | * | |
10126 | * Work with the OS to set up the MSIX vectors needed. | |
10127 | * | |
3b444399 | 10128 | * Returns the number of vectors reserved or negative on failure |
41c445ff JB |
10129 | **/ |
10130 | static int i40e_init_msix(struct i40e_pf *pf) | |
10131 | { | |
41c445ff | 10132 | struct i40e_hw *hw = &pf->hw; |
c0cf70a6 | 10133 | int cpus, extra_vectors; |
1e200e4a | 10134 | int vectors_left; |
41c445ff | 10135 | int v_budget, i; |
3b444399 | 10136 | int v_actual; |
e3219ce6 | 10137 | int iwarp_requested = 0; |
41c445ff JB |
10138 | |
10139 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
10140 | return -ENODEV; | |
10141 | ||
10142 | /* The number of vectors we'll request will be comprised of: | |
10143 | * - Add 1 for "other" cause for Admin Queue events, etc. | |
10144 | * - The number of LAN queue pairs | |
f8ff1464 ASJ |
10145 | * - Queues being used for RSS. |
10146 | * We don't need as many as max_rss_size vectors. | |
10147 | * use rss_size instead in the calculation since that | |
10148 | * is governed by number of cpus in the system. | |
10149 | * - assumes symmetric Tx/Rx pairing | |
41c445ff | 10150 | * - The number of VMDq pairs |
e3219ce6 | 10151 | * - The CPU count within the NUMA node if iWARP is enabled |
41c445ff JB |
10152 | * Once we count this up, try the request. |
10153 | * | |
10154 | * If we can't get what we want, we'll simplify to nearly nothing | |
10155 | * and try again. If that still fails, we punt. | |
10156 | */ | |
1e200e4a SN |
10157 | vectors_left = hw->func_caps.num_msix_vectors; |
10158 | v_budget = 0; | |
10159 | ||
10160 | /* reserve one vector for miscellaneous handler */ | |
10161 | if (vectors_left) { | |
10162 | v_budget++; | |
10163 | vectors_left--; | |
10164 | } | |
10165 | ||
c0cf70a6 JK |
10166 | /* reserve some vectors for the main PF traffic queues. Initially we |
10167 | * only reserve at most 50% of the available vectors, in the case that | |
10168 | * the number of online CPUs is large. This ensures that we can enable | |
10169 | * extra features as well. Once we've enabled the other features, we | |
10170 | * will use any remaining vectors to reach as close as we can to the | |
10171 | * number of online CPUs. | |
10172 | */ | |
10173 | cpus = num_online_cpus(); | |
10174 | pf->num_lan_msix = min_t(int, cpus, vectors_left / 2); | |
1e200e4a | 10175 | vectors_left -= pf->num_lan_msix; |
1e200e4a SN |
10176 | |
10177 | /* reserve one vector for sideband flow director */ | |
10178 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
10179 | if (vectors_left) { | |
a70e407f | 10180 | pf->num_fdsb_msix = 1; |
1e200e4a SN |
10181 | v_budget++; |
10182 | vectors_left--; | |
10183 | } else { | |
a70e407f | 10184 | pf->num_fdsb_msix = 0; |
1e200e4a SN |
10185 | } |
10186 | } | |
83840e4b | 10187 | |
e3219ce6 ASJ |
10188 | /* can we reserve enough for iWARP? */ |
10189 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { | |
4ce20abc SA |
10190 | iwarp_requested = pf->num_iwarp_msix; |
10191 | ||
e3219ce6 ASJ |
10192 | if (!vectors_left) |
10193 | pf->num_iwarp_msix = 0; | |
10194 | else if (vectors_left < pf->num_iwarp_msix) | |
10195 | pf->num_iwarp_msix = 1; | |
10196 | v_budget += pf->num_iwarp_msix; | |
10197 | vectors_left -= pf->num_iwarp_msix; | |
10198 | } | |
10199 | ||
1e200e4a SN |
10200 | /* any vectors left over go for VMDq support */ |
10201 | if (pf->flags & I40E_FLAG_VMDQ_ENABLED) { | |
10202 | int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps; | |
10203 | int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted); | |
10204 | ||
9ca57e97 SA |
10205 | if (!vectors_left) { |
10206 | pf->num_vmdq_msix = 0; | |
10207 | pf->num_vmdq_qps = 0; | |
10208 | } else { | |
10209 | /* if we're short on vectors for what's desired, we limit | |
10210 | * the queues per vmdq. If this is still more than are | |
10211 | * available, the user will need to change the number of | |
10212 | * queues/vectors used by the PF later with the ethtool | |
10213 | * channels command | |
10214 | */ | |
10215 | if (vmdq_vecs < vmdq_vecs_wanted) | |
10216 | pf->num_vmdq_qps = 1; | |
10217 | pf->num_vmdq_msix = pf->num_vmdq_qps; | |
1e200e4a | 10218 | |
9ca57e97 SA |
10219 | v_budget += vmdq_vecs; |
10220 | vectors_left -= vmdq_vecs; | |
10221 | } | |
1e200e4a | 10222 | } |
41c445ff | 10223 | |
c0cf70a6 JK |
10224 | /* On systems with a large number of SMP cores, we previously limited |
10225 | * the number of vectors for num_lan_msix to be at most 50% of the | |
10226 | * available vectors, to allow for other features. Now, we add back | |
10227 | * the remaining vectors. However, we ensure that the total | |
10228 | * num_lan_msix will not exceed num_online_cpus(). To do this, we | |
10229 | * calculate the number of vectors we can add without going over the | |
10230 | * cap of CPUs. For systems with a small number of CPUs this will be | |
10231 | * zero. | |
10232 | */ | |
10233 | extra_vectors = min_t(int, cpus - pf->num_lan_msix, vectors_left); | |
10234 | pf->num_lan_msix += extra_vectors; | |
10235 | vectors_left -= extra_vectors; | |
10236 | ||
10237 | WARN(vectors_left < 0, | |
10238 | "Calculation of remaining vectors underflowed. This is an accounting bug when determining total MSI-X vectors.\n"); | |
10239 | ||
10240 | v_budget += pf->num_lan_msix; | |
41c445ff JB |
10241 | pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), |
10242 | GFP_KERNEL); | |
10243 | if (!pf->msix_entries) | |
10244 | return -ENOMEM; | |
10245 | ||
10246 | for (i = 0; i < v_budget; i++) | |
10247 | pf->msix_entries[i].entry = i; | |
3b444399 | 10248 | v_actual = i40e_reserve_msix_vectors(pf, v_budget); |
a34977ba | 10249 | |
3b444399 | 10250 | if (v_actual < I40E_MIN_MSIX) { |
41c445ff JB |
10251 | pf->flags &= ~I40E_FLAG_MSIX_ENABLED; |
10252 | kfree(pf->msix_entries); | |
10253 | pf->msix_entries = NULL; | |
4c95aa5d | 10254 | pci_disable_msix(pf->pdev); |
41c445ff JB |
10255 | return -ENODEV; |
10256 | ||
3b444399 | 10257 | } else if (v_actual == I40E_MIN_MSIX) { |
41c445ff | 10258 | /* Adjust for minimal MSIX use */ |
41c445ff JB |
10259 | pf->num_vmdq_vsis = 0; |
10260 | pf->num_vmdq_qps = 0; | |
41c445ff JB |
10261 | pf->num_lan_qps = 1; |
10262 | pf->num_lan_msix = 1; | |
10263 | ||
3e6b1cf7 | 10264 | } else if (v_actual != v_budget) { |
4ce20abc SA |
10265 | /* If we have limited resources, we will start with no vectors |
10266 | * for the special features and then allocate vectors to some | |
10267 | * of these features based on the policy and at the end disable | |
10268 | * the features that did not get any vectors. | |
10269 | */ | |
3b444399 SN |
10270 | int vec; |
10271 | ||
4ce20abc | 10272 | dev_info(&pf->pdev->dev, |
3e6b1cf7 SN |
10273 | "MSI-X vector limit reached with %d, wanted %d, attempting to redistribute vectors\n", |
10274 | v_actual, v_budget); | |
a34977ba | 10275 | /* reserve the misc vector */ |
3b444399 | 10276 | vec = v_actual - 1; |
a34977ba | 10277 | |
41c445ff JB |
10278 | /* Scale vector usage down */ |
10279 | pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */ | |
a34977ba | 10280 | pf->num_vmdq_vsis = 1; |
1e200e4a | 10281 | pf->num_vmdq_qps = 1; |
41c445ff JB |
10282 | |
10283 | /* partition out the remaining vectors */ | |
10284 | switch (vec) { | |
10285 | case 2: | |
41c445ff JB |
10286 | pf->num_lan_msix = 1; |
10287 | break; | |
10288 | case 3: | |
e3219ce6 ASJ |
10289 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
10290 | pf->num_lan_msix = 1; | |
10291 | pf->num_iwarp_msix = 1; | |
10292 | } else { | |
10293 | pf->num_lan_msix = 2; | |
10294 | } | |
41c445ff JB |
10295 | break; |
10296 | default: | |
e3219ce6 ASJ |
10297 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
10298 | pf->num_iwarp_msix = min_t(int, (vec / 3), | |
10299 | iwarp_requested); | |
10300 | pf->num_vmdq_vsis = min_t(int, (vec / 3), | |
10301 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
10302 | } else { | |
10303 | pf->num_vmdq_vsis = min_t(int, (vec / 2), | |
10304 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
10305 | } | |
abd97a94 SA |
10306 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
10307 | pf->num_fdsb_msix = 1; | |
10308 | vec--; | |
10309 | } | |
e3219ce6 ASJ |
10310 | pf->num_lan_msix = min_t(int, |
10311 | (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)), | |
10312 | pf->num_lan_msix); | |
4ce20abc | 10313 | pf->num_lan_qps = pf->num_lan_msix; |
41c445ff JB |
10314 | break; |
10315 | } | |
10316 | } | |
10317 | ||
abd97a94 SA |
10318 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
10319 | (pf->num_fdsb_msix == 0)) { | |
10320 | dev_info(&pf->pdev->dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n"); | |
10321 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2f4b411a | 10322 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
abd97a94 | 10323 | } |
a34977ba ASJ |
10324 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && |
10325 | (pf->num_vmdq_msix == 0)) { | |
10326 | dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n"); | |
10327 | pf->flags &= ~I40E_FLAG_VMDQ_ENABLED; | |
10328 | } | |
e3219ce6 ASJ |
10329 | |
10330 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && | |
10331 | (pf->num_iwarp_msix == 0)) { | |
10332 | dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n"); | |
10333 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
10334 | } | |
4ce20abc SA |
10335 | i40e_debug(&pf->hw, I40E_DEBUG_INIT, |
10336 | "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n", | |
10337 | pf->num_lan_msix, | |
10338 | pf->num_vmdq_msix * pf->num_vmdq_vsis, | |
10339 | pf->num_fdsb_msix, | |
10340 | pf->num_iwarp_msix); | |
10341 | ||
3b444399 | 10342 | return v_actual; |
41c445ff JB |
10343 | } |
10344 | ||
493fb300 | 10345 | /** |
90e04070 | 10346 | * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector |
493fb300 AD |
10347 | * @vsi: the VSI being configured |
10348 | * @v_idx: index of the vector in the vsi struct | |
7f6c5539 | 10349 | * @cpu: cpu to be used on affinity_mask |
493fb300 AD |
10350 | * |
10351 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
10352 | **/ | |
7f6c5539 | 10353 | static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu) |
493fb300 AD |
10354 | { |
10355 | struct i40e_q_vector *q_vector; | |
10356 | ||
10357 | /* allocate q_vector */ | |
10358 | q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL); | |
10359 | if (!q_vector) | |
10360 | return -ENOMEM; | |
10361 | ||
10362 | q_vector->vsi = vsi; | |
10363 | q_vector->v_idx = v_idx; | |
759dc4a7 | 10364 | cpumask_copy(&q_vector->affinity_mask, cpu_possible_mask); |
7f6c5539 | 10365 | |
493fb300 AD |
10366 | if (vsi->netdev) |
10367 | netif_napi_add(vsi->netdev, &q_vector->napi, | |
eefeacee | 10368 | i40e_napi_poll, NAPI_POLL_WEIGHT); |
493fb300 | 10369 | |
cd0b6fa6 AD |
10370 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
10371 | q_vector->tx.latency_range = I40E_LOW_LATENCY; | |
10372 | ||
493fb300 AD |
10373 | /* tie q_vector and vsi together */ |
10374 | vsi->q_vectors[v_idx] = q_vector; | |
10375 | ||
10376 | return 0; | |
10377 | } | |
10378 | ||
41c445ff | 10379 | /** |
90e04070 | 10380 | * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors |
41c445ff JB |
10381 | * @vsi: the VSI being configured |
10382 | * | |
10383 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
10384 | * return -ENOMEM. | |
10385 | **/ | |
90e04070 | 10386 | static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi) |
41c445ff JB |
10387 | { |
10388 | struct i40e_pf *pf = vsi->back; | |
7f6c5539 | 10389 | int err, v_idx, num_q_vectors, current_cpu; |
41c445ff JB |
10390 | |
10391 | /* if not MSIX, give the one vector only to the LAN VSI */ | |
10392 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
10393 | num_q_vectors = vsi->num_q_vectors; | |
10394 | else if (vsi == pf->vsi[pf->lan_vsi]) | |
10395 | num_q_vectors = 1; | |
10396 | else | |
10397 | return -EINVAL; | |
10398 | ||
7f6c5539 GP |
10399 | current_cpu = cpumask_first(cpu_online_mask); |
10400 | ||
41c445ff | 10401 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
7f6c5539 | 10402 | err = i40e_vsi_alloc_q_vector(vsi, v_idx, current_cpu); |
493fb300 AD |
10403 | if (err) |
10404 | goto err_out; | |
7f6c5539 GP |
10405 | current_cpu = cpumask_next(current_cpu, cpu_online_mask); |
10406 | if (unlikely(current_cpu >= nr_cpu_ids)) | |
10407 | current_cpu = cpumask_first(cpu_online_mask); | |
41c445ff JB |
10408 | } |
10409 | ||
10410 | return 0; | |
493fb300 AD |
10411 | |
10412 | err_out: | |
10413 | while (v_idx--) | |
10414 | i40e_free_q_vector(vsi, v_idx); | |
10415 | ||
10416 | return err; | |
41c445ff JB |
10417 | } |
10418 | ||
10419 | /** | |
10420 | * i40e_init_interrupt_scheme - Determine proper interrupt scheme | |
10421 | * @pf: board private structure to initialize | |
10422 | **/ | |
c1147280 | 10423 | static int i40e_init_interrupt_scheme(struct i40e_pf *pf) |
41c445ff | 10424 | { |
3b444399 SN |
10425 | int vectors = 0; |
10426 | ssize_t size; | |
41c445ff JB |
10427 | |
10428 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3b444399 SN |
10429 | vectors = i40e_init_msix(pf); |
10430 | if (vectors < 0) { | |
60ea5f83 | 10431 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | |
e3219ce6 | 10432 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 | 10433 | I40E_FLAG_RSS_ENABLED | |
4d9b6043 | 10434 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 10435 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
10436 | I40E_FLAG_SRIOV_ENABLED | |
10437 | I40E_FLAG_FD_SB_ENABLED | | |
10438 | I40E_FLAG_FD_ATR_ENABLED | | |
10439 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 10440 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
41c445ff JB |
10441 | |
10442 | /* rework the queue expectations without MSIX */ | |
10443 | i40e_determine_queue_usage(pf); | |
10444 | } | |
10445 | } | |
10446 | ||
10447 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
10448 | (pf->flags & I40E_FLAG_MSI_ENABLED)) { | |
77fa28be | 10449 | dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n"); |
3b444399 SN |
10450 | vectors = pci_enable_msi(pf->pdev); |
10451 | if (vectors < 0) { | |
10452 | dev_info(&pf->pdev->dev, "MSI init failed - %d\n", | |
10453 | vectors); | |
41c445ff JB |
10454 | pf->flags &= ~I40E_FLAG_MSI_ENABLED; |
10455 | } | |
3b444399 | 10456 | vectors = 1; /* one MSI or Legacy vector */ |
41c445ff JB |
10457 | } |
10458 | ||
958a3e3b | 10459 | if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) |
77fa28be | 10460 | dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n"); |
958a3e3b | 10461 | |
3b444399 SN |
10462 | /* set up vector assignment tracking */ |
10463 | size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors); | |
10464 | pf->irq_pile = kzalloc(size, GFP_KERNEL); | |
c1147280 JB |
10465 | if (!pf->irq_pile) { |
10466 | dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n"); | |
10467 | return -ENOMEM; | |
10468 | } | |
3b444399 SN |
10469 | pf->irq_pile->num_entries = vectors; |
10470 | pf->irq_pile->search_hint = 0; | |
10471 | ||
c1147280 | 10472 | /* track first vector for misc interrupts, ignore return */ |
3b444399 | 10473 | (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1); |
c1147280 JB |
10474 | |
10475 | return 0; | |
41c445ff JB |
10476 | } |
10477 | ||
b980c063 JK |
10478 | /** |
10479 | * i40e_restore_interrupt_scheme - Restore the interrupt scheme | |
10480 | * @pf: private board data structure | |
10481 | * | |
10482 | * Restore the interrupt scheme that was cleared when we suspended the | |
10483 | * device. This should be called during resume to re-allocate the q_vectors | |
10484 | * and reacquire IRQs. | |
10485 | */ | |
10486 | static int i40e_restore_interrupt_scheme(struct i40e_pf *pf) | |
10487 | { | |
10488 | int err, i; | |
10489 | ||
10490 | /* We cleared the MSI and MSI-X flags when disabling the old interrupt | |
10491 | * scheme. We need to re-enabled them here in order to attempt to | |
10492 | * re-acquire the MSI or MSI-X vectors | |
10493 | */ | |
10494 | pf->flags |= (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
10495 | ||
10496 | err = i40e_init_interrupt_scheme(pf); | |
10497 | if (err) | |
10498 | return err; | |
10499 | ||
10500 | /* Now that we've re-acquired IRQs, we need to remap the vectors and | |
10501 | * rings together again. | |
10502 | */ | |
10503 | for (i = 0; i < pf->num_alloc_vsi; i++) { | |
10504 | if (pf->vsi[i]) { | |
10505 | err = i40e_vsi_alloc_q_vectors(pf->vsi[i]); | |
10506 | if (err) | |
10507 | goto err_unwind; | |
10508 | i40e_vsi_map_rings_to_vectors(pf->vsi[i]); | |
10509 | } | |
10510 | } | |
10511 | ||
10512 | err = i40e_setup_misc_vector(pf); | |
10513 | if (err) | |
10514 | goto err_unwind; | |
10515 | ||
10516 | return 0; | |
10517 | ||
10518 | err_unwind: | |
10519 | while (i--) { | |
10520 | if (pf->vsi[i]) | |
10521 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
10522 | } | |
10523 | ||
10524 | return err; | |
10525 | } | |
b980c063 | 10526 | |
41c445ff JB |
10527 | /** |
10528 | * i40e_setup_misc_vector - Setup the misc vector to handle non queue events | |
10529 | * @pf: board private structure | |
10530 | * | |
10531 | * This sets up the handler for MSIX 0, which is used to manage the | |
10532 | * non-queue interrupts, e.g. AdminQ and errors. This is not used | |
10533 | * when in MSI or Legacy interrupt mode. | |
10534 | **/ | |
10535 | static int i40e_setup_misc_vector(struct i40e_pf *pf) | |
10536 | { | |
10537 | struct i40e_hw *hw = &pf->hw; | |
10538 | int err = 0; | |
10539 | ||
c17401a1 JK |
10540 | /* Only request the IRQ once, the first time through. */ |
10541 | if (!test_and_set_bit(__I40E_MISC_IRQ_REQUESTED, pf->state)) { | |
41c445ff | 10542 | err = request_irq(pf->msix_entries[0].vector, |
b294ac70 | 10543 | i40e_intr, 0, pf->int_name, pf); |
41c445ff | 10544 | if (err) { |
c17401a1 | 10545 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); |
41c445ff | 10546 | dev_info(&pf->pdev->dev, |
77fa28be | 10547 | "request_irq for %s failed: %d\n", |
b294ac70 | 10548 | pf->int_name, err); |
41c445ff JB |
10549 | return -EFAULT; |
10550 | } | |
10551 | } | |
10552 | ||
ab437b5a | 10553 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
10554 | |
10555 | /* associate no queues to the misc vector */ | |
10556 | wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST); | |
10557 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K); | |
10558 | ||
10559 | i40e_flush(hw); | |
10560 | ||
dbadbbe2 | 10561 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
10562 | |
10563 | return err; | |
10564 | } | |
10565 | ||
95a73780 ASJ |
10566 | /** |
10567 | * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands | |
10568 | * @vsi: Pointer to vsi structure | |
10569 | * @seed: Buffter to store the hash keys | |
10570 | * @lut: Buffer to store the lookup table entries | |
10571 | * @lut_size: Size of buffer to store the lookup table entries | |
10572 | * | |
10573 | * Return 0 on success, negative on failure | |
10574 | */ | |
10575 | static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
10576 | u8 *lut, u16 lut_size) | |
10577 | { | |
10578 | struct i40e_pf *pf = vsi->back; | |
10579 | struct i40e_hw *hw = &pf->hw; | |
10580 | int ret = 0; | |
10581 | ||
10582 | if (seed) { | |
10583 | ret = i40e_aq_get_rss_key(hw, vsi->id, | |
10584 | (struct i40e_aqc_get_set_rss_key_data *)seed); | |
10585 | if (ret) { | |
10586 | dev_info(&pf->pdev->dev, | |
10587 | "Cannot get RSS key, err %s aq_err %s\n", | |
10588 | i40e_stat_str(&pf->hw, ret), | |
10589 | i40e_aq_str(&pf->hw, | |
10590 | pf->hw.aq.asq_last_status)); | |
10591 | return ret; | |
10592 | } | |
10593 | } | |
10594 | ||
10595 | if (lut) { | |
10596 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
10597 | ||
10598 | ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
10599 | if (ret) { | |
10600 | dev_info(&pf->pdev->dev, | |
10601 | "Cannot get RSS lut, err %s aq_err %s\n", | |
10602 | i40e_stat_str(&pf->hw, ret), | |
10603 | i40e_aq_str(&pf->hw, | |
10604 | pf->hw.aq.asq_last_status)); | |
10605 | return ret; | |
10606 | } | |
10607 | } | |
10608 | ||
10609 | return ret; | |
10610 | } | |
10611 | ||
e25d00b8 | 10612 | /** |
043dd650 | 10613 | * i40e_config_rss_reg - Configure RSS keys and lut by writing registers |
e69ff813 | 10614 | * @vsi: Pointer to vsi structure |
e25d00b8 | 10615 | * @seed: RSS hash seed |
e69ff813 HZ |
10616 | * @lut: Lookup table |
10617 | * @lut_size: Lookup table size | |
10618 | * | |
10619 | * Returns 0 on success, negative on failure | |
41c445ff | 10620 | **/ |
e69ff813 HZ |
10621 | static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed, |
10622 | const u8 *lut, u16 lut_size) | |
41c445ff | 10623 | { |
e69ff813 | 10624 | struct i40e_pf *pf = vsi->back; |
4617e8c0 | 10625 | struct i40e_hw *hw = &pf->hw; |
c4e1868c | 10626 | u16 vf_id = vsi->vf_id; |
e69ff813 | 10627 | u8 i; |
41c445ff | 10628 | |
e25d00b8 | 10629 | /* Fill out hash function seed */ |
e69ff813 HZ |
10630 | if (seed) { |
10631 | u32 *seed_dw = (u32 *)seed; | |
10632 | ||
c4e1868c MW |
10633 | if (vsi->type == I40E_VSI_MAIN) { |
10634 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
26f77e53 | 10635 | wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]); |
c4e1868c MW |
10636 | } else if (vsi->type == I40E_VSI_SRIOV) { |
10637 | for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++) | |
26f77e53 | 10638 | wr32(hw, I40E_VFQF_HKEY1(i, vf_id), seed_dw[i]); |
c4e1868c MW |
10639 | } else { |
10640 | dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n"); | |
10641 | } | |
e69ff813 HZ |
10642 | } |
10643 | ||
10644 | if (lut) { | |
10645 | u32 *lut_dw = (u32 *)lut; | |
10646 | ||
c4e1868c MW |
10647 | if (vsi->type == I40E_VSI_MAIN) { |
10648 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
10649 | return -EINVAL; | |
10650 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
10651 | wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]); | |
10652 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
10653 | if (lut_size != I40E_VF_HLUT_ARRAY_SIZE) | |
10654 | return -EINVAL; | |
10655 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
26f77e53 | 10656 | wr32(hw, I40E_VFQF_HLUT1(i, vf_id), lut_dw[i]); |
c4e1868c MW |
10657 | } else { |
10658 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
10659 | } | |
e25d00b8 ASJ |
10660 | } |
10661 | i40e_flush(hw); | |
10662 | ||
10663 | return 0; | |
10664 | } | |
10665 | ||
043dd650 HZ |
10666 | /** |
10667 | * i40e_get_rss_reg - Get the RSS keys and lut by reading registers | |
10668 | * @vsi: Pointer to VSI structure | |
10669 | * @seed: Buffer to store the keys | |
10670 | * @lut: Buffer to store the lookup table entries | |
10671 | * @lut_size: Size of buffer to store the lookup table entries | |
10672 | * | |
10673 | * Returns 0 on success, negative on failure | |
10674 | */ | |
10675 | static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed, | |
10676 | u8 *lut, u16 lut_size) | |
10677 | { | |
10678 | struct i40e_pf *pf = vsi->back; | |
10679 | struct i40e_hw *hw = &pf->hw; | |
10680 | u16 i; | |
10681 | ||
10682 | if (seed) { | |
10683 | u32 *seed_dw = (u32 *)seed; | |
10684 | ||
10685 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
272cdaf2 | 10686 | seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); |
043dd650 HZ |
10687 | } |
10688 | if (lut) { | |
10689 | u32 *lut_dw = (u32 *)lut; | |
10690 | ||
10691 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
10692 | return -EINVAL; | |
10693 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
10694 | lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i)); | |
10695 | } | |
10696 | ||
10697 | return 0; | |
10698 | } | |
10699 | ||
10700 | /** | |
10701 | * i40e_config_rss - Configure RSS keys and lut | |
10702 | * @vsi: Pointer to VSI structure | |
10703 | * @seed: RSS hash seed | |
10704 | * @lut: Lookup table | |
10705 | * @lut_size: Lookup table size | |
10706 | * | |
10707 | * Returns 0 on success, negative on failure | |
10708 | */ | |
10709 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
10710 | { | |
10711 | struct i40e_pf *pf = vsi->back; | |
10712 | ||
d36e41dc | 10713 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
043dd650 HZ |
10714 | return i40e_config_rss_aq(vsi, seed, lut, lut_size); |
10715 | else | |
10716 | return i40e_config_rss_reg(vsi, seed, lut, lut_size); | |
10717 | } | |
10718 | ||
10719 | /** | |
10720 | * i40e_get_rss - Get RSS keys and lut | |
10721 | * @vsi: Pointer to VSI structure | |
10722 | * @seed: Buffer to store the keys | |
10723 | * @lut: Buffer to store the lookup table entries | |
10724 | * lut_size: Size of buffer to store the lookup table entries | |
10725 | * | |
10726 | * Returns 0 on success, negative on failure | |
10727 | */ | |
10728 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
10729 | { | |
95a73780 ASJ |
10730 | struct i40e_pf *pf = vsi->back; |
10731 | ||
d36e41dc | 10732 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
95a73780 ASJ |
10733 | return i40e_get_rss_aq(vsi, seed, lut, lut_size); |
10734 | else | |
10735 | return i40e_get_rss_reg(vsi, seed, lut, lut_size); | |
043dd650 HZ |
10736 | } |
10737 | ||
e69ff813 HZ |
10738 | /** |
10739 | * i40e_fill_rss_lut - Fill the RSS lookup table with default values | |
10740 | * @pf: Pointer to board private structure | |
10741 | * @lut: Lookup table | |
10742 | * @rss_table_size: Lookup table size | |
10743 | * @rss_size: Range of queue number for hashing | |
10744 | */ | |
f1582351 AB |
10745 | void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, |
10746 | u16 rss_table_size, u16 rss_size) | |
e69ff813 HZ |
10747 | { |
10748 | u16 i; | |
10749 | ||
10750 | for (i = 0; i < rss_table_size; i++) | |
10751 | lut[i] = i % rss_size; | |
10752 | } | |
10753 | ||
e25d00b8 | 10754 | /** |
043dd650 | 10755 | * i40e_pf_config_rss - Prepare for RSS if used |
e25d00b8 ASJ |
10756 | * @pf: board private structure |
10757 | **/ | |
043dd650 | 10758 | static int i40e_pf_config_rss(struct i40e_pf *pf) |
e25d00b8 ASJ |
10759 | { |
10760 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
10761 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
e69ff813 | 10762 | u8 *lut; |
e25d00b8 ASJ |
10763 | struct i40e_hw *hw = &pf->hw; |
10764 | u32 reg_val; | |
10765 | u64 hena; | |
e69ff813 | 10766 | int ret; |
e25d00b8 | 10767 | |
41c445ff | 10768 | /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */ |
272cdaf2 SN |
10769 | hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) | |
10770 | ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32); | |
e25d00b8 ASJ |
10771 | hena |= i40e_pf_get_default_rss_hena(pf); |
10772 | ||
272cdaf2 SN |
10773 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena); |
10774 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); | |
41c445ff | 10775 | |
e25d00b8 | 10776 | /* Determine the RSS table size based on the hardware capabilities */ |
272cdaf2 | 10777 | reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); |
e25d00b8 ASJ |
10778 | reg_val = (pf->rss_table_size == 512) ? |
10779 | (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : | |
10780 | (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); | |
272cdaf2 | 10781 | i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); |
e157ea30 | 10782 | |
28c5869f | 10783 | /* Determine the RSS size of the VSI */ |
f25571b5 HR |
10784 | if (!vsi->rss_size) { |
10785 | u16 qcount; | |
10786 | ||
10787 | qcount = vsi->num_queue_pairs / vsi->tc_config.numtc; | |
10788 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); | |
10789 | } | |
a4fa59cc MW |
10790 | if (!vsi->rss_size) |
10791 | return -EINVAL; | |
28c5869f | 10792 | |
e69ff813 HZ |
10793 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
10794 | if (!lut) | |
10795 | return -ENOMEM; | |
10796 | ||
28c5869f HZ |
10797 | /* Use user configured lut if there is one, otherwise use default */ |
10798 | if (vsi->rss_lut_user) | |
10799 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
10800 | else | |
10801 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
e69ff813 | 10802 | |
28c5869f HZ |
10803 | /* Use user configured hash key if there is one, otherwise |
10804 | * use default. | |
10805 | */ | |
10806 | if (vsi->rss_hkey_user) | |
10807 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
10808 | else | |
10809 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
043dd650 | 10810 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); |
e69ff813 HZ |
10811 | kfree(lut); |
10812 | ||
10813 | return ret; | |
41c445ff JB |
10814 | } |
10815 | ||
f8ff1464 ASJ |
10816 | /** |
10817 | * i40e_reconfig_rss_queues - change number of queues for rss and rebuild | |
10818 | * @pf: board private structure | |
10819 | * @queue_count: the requested queue count for rss. | |
10820 | * | |
10821 | * returns 0 if rss is not enabled, if enabled returns the final rss queue | |
10822 | * count which may be different from the requested queue count. | |
373149fc | 10823 | * Note: expects to be called while under rtnl_lock() |
f8ff1464 ASJ |
10824 | **/ |
10825 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count) | |
10826 | { | |
9a3bd2f1 ASJ |
10827 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
10828 | int new_rss_size; | |
10829 | ||
f8ff1464 ASJ |
10830 | if (!(pf->flags & I40E_FLAG_RSS_ENABLED)) |
10831 | return 0; | |
10832 | ||
9a3bd2f1 | 10833 | new_rss_size = min_t(int, queue_count, pf->rss_size_max); |
f8ff1464 | 10834 | |
9a3bd2f1 | 10835 | if (queue_count != vsi->num_queue_pairs) { |
f25571b5 HR |
10836 | u16 qcount; |
10837 | ||
9a3bd2f1 | 10838 | vsi->req_queue_pairs = queue_count; |
373149fc | 10839 | i40e_prep_for_reset(pf, true); |
f8ff1464 | 10840 | |
acd65448 | 10841 | pf->alloc_rss_size = new_rss_size; |
f8ff1464 | 10842 | |
373149fc | 10843 | i40e_reset_and_rebuild(pf, true, true); |
28c5869f HZ |
10844 | |
10845 | /* Discard the user configured hash keys and lut, if less | |
10846 | * queues are enabled. | |
10847 | */ | |
10848 | if (queue_count < vsi->rss_size) { | |
10849 | i40e_clear_rss_config_user(vsi); | |
10850 | dev_dbg(&pf->pdev->dev, | |
10851 | "discard user configured hash keys and lut\n"); | |
10852 | } | |
10853 | ||
10854 | /* Reset vsi->rss_size, as number of enabled queues changed */ | |
f25571b5 HR |
10855 | qcount = vsi->num_queue_pairs / vsi->tc_config.numtc; |
10856 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); | |
28c5869f | 10857 | |
043dd650 | 10858 | i40e_pf_config_rss(pf); |
f8ff1464 | 10859 | } |
12815057 LY |
10860 | dev_info(&pf->pdev->dev, "User requested queue count/HW max RSS count: %d/%d\n", |
10861 | vsi->req_queue_pairs, pf->rss_size_max); | |
acd65448 | 10862 | return pf->alloc_rss_size; |
f8ff1464 ASJ |
10863 | } |
10864 | ||
f4492db1 | 10865 | /** |
4fc8c676 | 10866 | * i40e_get_partition_bw_setting - Retrieve BW settings for this PF partition |
f4492db1 GR |
10867 | * @pf: board private structure |
10868 | **/ | |
4fc8c676 | 10869 | i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
10870 | { |
10871 | i40e_status status; | |
10872 | bool min_valid, max_valid; | |
10873 | u32 max_bw, min_bw; | |
10874 | ||
10875 | status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw, | |
10876 | &min_valid, &max_valid); | |
10877 | ||
10878 | if (!status) { | |
10879 | if (min_valid) | |
4fc8c676 | 10880 | pf->min_bw = min_bw; |
f4492db1 | 10881 | if (max_valid) |
4fc8c676 | 10882 | pf->max_bw = max_bw; |
f4492db1 GR |
10883 | } |
10884 | ||
10885 | return status; | |
10886 | } | |
10887 | ||
10888 | /** | |
4fc8c676 | 10889 | * i40e_set_partition_bw_setting - Set BW settings for this PF partition |
f4492db1 GR |
10890 | * @pf: board private structure |
10891 | **/ | |
4fc8c676 | 10892 | i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
10893 | { |
10894 | struct i40e_aqc_configure_partition_bw_data bw_data; | |
10895 | i40e_status status; | |
10896 | ||
b40c82e6 | 10897 | /* Set the valid bit for this PF */ |
41a1d04b | 10898 | bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); |
4fc8c676 SN |
10899 | bw_data.max_bw[pf->hw.pf_id] = pf->max_bw & I40E_ALT_BW_VALUE_MASK; |
10900 | bw_data.min_bw[pf->hw.pf_id] = pf->min_bw & I40E_ALT_BW_VALUE_MASK; | |
f4492db1 GR |
10901 | |
10902 | /* Set the new bandwidths */ | |
10903 | status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL); | |
10904 | ||
10905 | return status; | |
10906 | } | |
10907 | ||
10908 | /** | |
4fc8c676 | 10909 | * i40e_commit_partition_bw_setting - Commit BW settings for this PF partition |
f4492db1 GR |
10910 | * @pf: board private structure |
10911 | **/ | |
4fc8c676 | 10912 | i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
10913 | { |
10914 | /* Commit temporary BW setting to permanent NVM image */ | |
10915 | enum i40e_admin_queue_err last_aq_status; | |
10916 | i40e_status ret; | |
10917 | u16 nvm_word; | |
10918 | ||
10919 | if (pf->hw.partition_id != 1) { | |
10920 | dev_info(&pf->pdev->dev, | |
10921 | "Commit BW only works on partition 1! This is partition %d", | |
10922 | pf->hw.partition_id); | |
10923 | ret = I40E_NOT_SUPPORTED; | |
10924 | goto bw_commit_out; | |
10925 | } | |
10926 | ||
10927 | /* Acquire NVM for read access */ | |
10928 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ); | |
10929 | last_aq_status = pf->hw.aq.asq_last_status; | |
10930 | if (ret) { | |
10931 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10932 | "Cannot acquire NVM for read access, err %s aq_err %s\n", |
10933 | i40e_stat_str(&pf->hw, ret), | |
10934 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
10935 | goto bw_commit_out; |
10936 | } | |
10937 | ||
10938 | /* Read word 0x10 of NVM - SW compatibility word 1 */ | |
10939 | ret = i40e_aq_read_nvm(&pf->hw, | |
10940 | I40E_SR_NVM_CONTROL_WORD, | |
10941 | 0x10, sizeof(nvm_word), &nvm_word, | |
10942 | false, NULL); | |
10943 | /* Save off last admin queue command status before releasing | |
10944 | * the NVM | |
10945 | */ | |
10946 | last_aq_status = pf->hw.aq.asq_last_status; | |
10947 | i40e_release_nvm(&pf->hw); | |
10948 | if (ret) { | |
f1c7e72e SN |
10949 | dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n", |
10950 | i40e_stat_str(&pf->hw, ret), | |
10951 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
10952 | goto bw_commit_out; |
10953 | } | |
10954 | ||
10955 | /* Wait a bit for NVM release to complete */ | |
10956 | msleep(50); | |
10957 | ||
10958 | /* Acquire NVM for write access */ | |
10959 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE); | |
10960 | last_aq_status = pf->hw.aq.asq_last_status; | |
10961 | if (ret) { | |
10962 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10963 | "Cannot acquire NVM for write access, err %s aq_err %s\n", |
10964 | i40e_stat_str(&pf->hw, ret), | |
10965 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
10966 | goto bw_commit_out; |
10967 | } | |
10968 | /* Write it back out unchanged to initiate update NVM, | |
10969 | * which will force a write of the shadow (alt) RAM to | |
10970 | * the NVM - thus storing the bandwidth values permanently. | |
10971 | */ | |
10972 | ret = i40e_aq_update_nvm(&pf->hw, | |
10973 | I40E_SR_NVM_CONTROL_WORD, | |
10974 | 0x10, sizeof(nvm_word), | |
10975 | &nvm_word, true, NULL); | |
10976 | /* Save off last admin queue command status before releasing | |
10977 | * the NVM | |
10978 | */ | |
10979 | last_aq_status = pf->hw.aq.asq_last_status; | |
10980 | i40e_release_nvm(&pf->hw); | |
10981 | if (ret) | |
10982 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10983 | "BW settings NOT SAVED, err %s aq_err %s\n", |
10984 | i40e_stat_str(&pf->hw, ret), | |
10985 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
10986 | bw_commit_out: |
10987 | ||
10988 | return ret; | |
10989 | } | |
10990 | ||
41c445ff JB |
10991 | /** |
10992 | * i40e_sw_init - Initialize general software structures (struct i40e_pf) | |
10993 | * @pf: board private structure to initialize | |
10994 | * | |
10995 | * i40e_sw_init initializes the Adapter private data structure. | |
10996 | * Fields are initialized based on PCI device information and | |
10997 | * OS network device settings (MTU size). | |
10998 | **/ | |
10999 | static int i40e_sw_init(struct i40e_pf *pf) | |
11000 | { | |
11001 | int err = 0; | |
11002 | int size; | |
11003 | ||
41c445ff JB |
11004 | /* Set default capability flags */ |
11005 | pf->flags = I40E_FLAG_RX_CSUM_ENABLED | | |
11006 | I40E_FLAG_MSI_ENABLED | | |
2bc7ee8a MW |
11007 | I40E_FLAG_MSIX_ENABLED; |
11008 | ||
ca99eb99 | 11009 | /* Set default ITR */ |
42702559 JK |
11010 | pf->rx_itr_default = I40E_ITR_RX_DEF; |
11011 | pf->tx_itr_default = I40E_ITR_TX_DEF; | |
ca99eb99 | 11012 | |
7134f9ce JB |
11013 | /* Depending on PF configurations, it is possible that the RSS |
11014 | * maximum might end up larger than the available queues | |
11015 | */ | |
41a1d04b | 11016 | pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); |
acd65448 | 11017 | pf->alloc_rss_size = 1; |
5db4cb59 | 11018 | pf->rss_table_size = pf->hw.func_caps.rss_table_size; |
7134f9ce JB |
11019 | pf->rss_size_max = min_t(int, pf->rss_size_max, |
11020 | pf->hw.func_caps.num_tx_qp); | |
41c445ff JB |
11021 | if (pf->hw.func_caps.rss) { |
11022 | pf->flags |= I40E_FLAG_RSS_ENABLED; | |
acd65448 HZ |
11023 | pf->alloc_rss_size = min_t(int, pf->rss_size_max, |
11024 | num_online_cpus()); | |
41c445ff JB |
11025 | } |
11026 | ||
2050bc65 | 11027 | /* MFP mode enabled */ |
c78b953e | 11028 | if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) { |
2050bc65 CS |
11029 | pf->flags |= I40E_FLAG_MFP_ENABLED; |
11030 | dev_info(&pf->pdev->dev, "MFP mode Enabled\n"); | |
4fc8c676 | 11031 | if (i40e_get_partition_bw_setting(pf)) { |
f4492db1 | 11032 | dev_warn(&pf->pdev->dev, |
4fc8c676 SN |
11033 | "Could not get partition bw settings\n"); |
11034 | } else { | |
f4492db1 | 11035 | dev_info(&pf->pdev->dev, |
4fc8c676 SN |
11036 | "Partition BW Min = %8.8x, Max = %8.8x\n", |
11037 | pf->min_bw, pf->max_bw); | |
11038 | ||
11039 | /* nudge the Tx scheduler */ | |
11040 | i40e_set_partition_bw_setting(pf); | |
11041 | } | |
2050bc65 CS |
11042 | } |
11043 | ||
cbf61325 ASJ |
11044 | if ((pf->hw.func_caps.fd_filters_guaranteed > 0) || |
11045 | (pf->hw.func_caps.fd_filters_best_effort > 0)) { | |
11046 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
11047 | pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE; | |
6eae9c6a SN |
11048 | if (pf->flags & I40E_FLAG_MFP_ENABLED && |
11049 | pf->hw.num_partitions > 1) | |
cbf61325 | 11050 | dev_info(&pf->pdev->dev, |
0b67584f | 11051 | "Flow Director Sideband mode Disabled in MFP mode\n"); |
6eae9c6a SN |
11052 | else |
11053 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
cbf61325 ASJ |
11054 | pf->fdir_pf_filter_count = |
11055 | pf->hw.func_caps.fd_filters_guaranteed; | |
11056 | pf->hw.fdir_shared_filter_count = | |
11057 | pf->hw.func_caps.fd_filters_best_effort; | |
41c445ff JB |
11058 | } |
11059 | ||
5a433199 | 11060 | if (pf->hw.mac.type == I40E_MAC_X722) { |
d36e41dc JK |
11061 | pf->hw_features |= (I40E_HW_RSS_AQ_CAPABLE | |
11062 | I40E_HW_128_QP_RSS_CAPABLE | | |
11063 | I40E_HW_ATR_EVICT_CAPABLE | | |
11064 | I40E_HW_WB_ON_ITR_CAPABLE | | |
11065 | I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE | | |
11066 | I40E_HW_NO_PCI_LINK_CHECK | | |
11067 | I40E_HW_USE_SET_LLDP_MIB | | |
11068 | I40E_HW_GENEVE_OFFLOAD_CAPABLE | | |
11069 | I40E_HW_PTP_L4_CAPABLE | | |
11070 | I40E_HW_WOL_MC_MAGIC_PKT_WAKE | | |
11071 | I40E_HW_OUTER_UDP_CSUM_CAPABLE); | |
10a955ff ASJ |
11072 | |
11073 | #define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03 | |
11074 | if (rd32(&pf->hw, I40E_GLQF_FDEVICTENA(1)) != | |
11075 | I40E_FDEVICT_PCTYPE_DEFAULT) { | |
11076 | dev_warn(&pf->pdev->dev, | |
11077 | "FD EVICT PCTYPES are not right, disable FD HW EVICT\n"); | |
11078 | pf->hw_features &= ~I40E_HW_ATR_EVICT_CAPABLE; | |
11079 | } | |
5a433199 ASJ |
11080 | } else if ((pf->hw.aq.api_maj_ver > 1) || |
11081 | ((pf->hw.aq.api_maj_ver == 1) && | |
11082 | (pf->hw.aq.api_min_ver > 4))) { | |
11083 | /* Supported in FW API version higher than 1.4 */ | |
d36e41dc | 11084 | pf->hw_features |= I40E_HW_GENEVE_OFFLOAD_CAPABLE; |
5a433199 ASJ |
11085 | } |
11086 | ||
11087 | /* Enable HW ATR eviction if possible */ | |
d36e41dc | 11088 | if (pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE) |
5a433199 ASJ |
11089 | pf->flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED; |
11090 | ||
6de432c5 | 11091 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
8eed76fa | 11092 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) || |
f1bbad33 | 11093 | (pf->hw.aq.fw_maj_ver < 4))) { |
d36e41dc | 11094 | pf->hw_features |= I40E_HW_RESTART_AUTONEG; |
f1bbad33 | 11095 | /* No DCB support for FW < v4.33 */ |
d36e41dc | 11096 | pf->hw_features |= I40E_HW_NO_DCB_SUPPORT; |
f1bbad33 NP |
11097 | } |
11098 | ||
11099 | /* Disable FW LLDP if FW < v4.3 */ | |
6de432c5 | 11100 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
11101 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) || |
11102 | (pf->hw.aq.fw_maj_ver < 4))) | |
d36e41dc | 11103 | pf->hw_features |= I40E_HW_STOP_FW_LLDP; |
f1bbad33 NP |
11104 | |
11105 | /* Use the FW Set LLDP MIB API if FW > v4.40 */ | |
6de432c5 | 11106 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
11107 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) || |
11108 | (pf->hw.aq.fw_maj_ver >= 5))) | |
d36e41dc | 11109 | pf->hw_features |= I40E_HW_USE_SET_LLDP_MIB; |
8eed76fa | 11110 | |
c3d26b75 AB |
11111 | /* Enable PTP L4 if FW > v6.0 */ |
11112 | if (pf->hw.mac.type == I40E_MAC_XL710 && | |
11113 | pf->hw.aq.fw_maj_ver >= 6) | |
11114 | pf->hw_features |= I40E_HW_PTP_L4_CAPABLE; | |
11115 | ||
41c445ff | 11116 | if (pf->hw.func_caps.vmdq) { |
41c445ff | 11117 | pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI; |
e25d00b8 | 11118 | pf->flags |= I40E_FLAG_VMDQ_ENABLED; |
e9e53662 | 11119 | pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf); |
41c445ff JB |
11120 | } |
11121 | ||
e3219ce6 ASJ |
11122 | if (pf->hw.func_caps.iwarp) { |
11123 | pf->flags |= I40E_FLAG_IWARP_ENABLED; | |
11124 | /* IWARP needs one extra vector for CQP just like MISC.*/ | |
11125 | pf->num_iwarp_msix = (int)num_online_cpus() + 1; | |
11126 | } | |
11127 | ||
41c445ff | 11128 | #ifdef CONFIG_PCI_IOV |
ba252f13 | 11129 | if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) { |
41c445ff JB |
11130 | pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF; |
11131 | pf->flags |= I40E_FLAG_SRIOV_ENABLED; | |
11132 | pf->num_req_vfs = min_t(int, | |
11133 | pf->hw.func_caps.num_vfs, | |
11134 | I40E_MAX_VF_COUNT); | |
11135 | } | |
11136 | #endif /* CONFIG_PCI_IOV */ | |
11137 | pf->eeprom_version = 0xDEAD; | |
11138 | pf->lan_veb = I40E_NO_VEB; | |
11139 | pf->lan_vsi = I40E_NO_VSI; | |
11140 | ||
d1a8d275 ASJ |
11141 | /* By default FW has this off for performance reasons */ |
11142 | pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED; | |
11143 | ||
41c445ff JB |
11144 | /* set up queue assignment tracking */ |
11145 | size = sizeof(struct i40e_lump_tracking) | |
11146 | + (sizeof(u16) * pf->hw.func_caps.num_tx_qp); | |
11147 | pf->qp_pile = kzalloc(size, GFP_KERNEL); | |
11148 | if (!pf->qp_pile) { | |
11149 | err = -ENOMEM; | |
11150 | goto sw_init_done; | |
11151 | } | |
11152 | pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp; | |
11153 | pf->qp_pile->search_hint = 0; | |
11154 | ||
327fe04b ASJ |
11155 | pf->tx_timeout_recovery_level = 1; |
11156 | ||
41c445ff JB |
11157 | mutex_init(&pf->switch_mutex); |
11158 | ||
11159 | sw_init_done: | |
11160 | return err; | |
11161 | } | |
11162 | ||
7c3c288b ASJ |
11163 | /** |
11164 | * i40e_set_ntuple - set the ntuple feature flag and take action | |
11165 | * @pf: board private structure to initialize | |
11166 | * @features: the feature set that the stack is suggesting | |
11167 | * | |
11168 | * returns a bool to indicate if reset needs to happen | |
11169 | **/ | |
11170 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features) | |
11171 | { | |
11172 | bool need_reset = false; | |
11173 | ||
11174 | /* Check if Flow Director n-tuple support was enabled or disabled. If | |
11175 | * the state changed, we need to reset. | |
11176 | */ | |
11177 | if (features & NETIF_F_NTUPLE) { | |
11178 | /* Enable filters and mark for reset */ | |
11179 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) | |
11180 | need_reset = true; | |
2f4b411a AN |
11181 | /* enable FD_SB only if there is MSI-X vector and no cloud |
11182 | * filters exist | |
11183 | */ | |
11184 | if (pf->num_fdsb_msix > 0 && !pf->num_cloud_filters) { | |
a70e407f | 11185 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; |
2f4b411a AN |
11186 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; |
11187 | } | |
7c3c288b ASJ |
11188 | } else { |
11189 | /* turn off filters, mark for reset and clear SW filter list */ | |
11190 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
11191 | need_reset = true; | |
11192 | i40e_fdir_filter_exit(pf); | |
11193 | } | |
47994c11 JK |
11194 | pf->flags &= ~(I40E_FLAG_FD_SB_ENABLED | |
11195 | I40E_FLAG_FD_SB_AUTO_DISABLED); | |
2f4b411a AN |
11196 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
11197 | ||
1e1be8f6 | 11198 | /* reset fd counters */ |
097dbf52 JK |
11199 | pf->fd_add_err = 0; |
11200 | pf->fd_atr_cnt = 0; | |
8a4f34fb | 11201 | /* if ATR was auto disabled it can be re-enabled. */ |
47994c11 JK |
11202 | if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED) { |
11203 | pf->flags &= ~I40E_FLAG_FD_ATR_AUTO_DISABLED; | |
11204 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
11205 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
234dc4e6 JK |
11206 | dev_info(&pf->pdev->dev, "ATR re-enabled.\n"); |
11207 | } | |
7c3c288b ASJ |
11208 | } |
11209 | return need_reset; | |
11210 | } | |
11211 | ||
d8ec9864 AB |
11212 | /** |
11213 | * i40e_clear_rss_lut - clear the rx hash lookup table | |
11214 | * @vsi: the VSI being configured | |
11215 | **/ | |
11216 | static void i40e_clear_rss_lut(struct i40e_vsi *vsi) | |
11217 | { | |
11218 | struct i40e_pf *pf = vsi->back; | |
11219 | struct i40e_hw *hw = &pf->hw; | |
11220 | u16 vf_id = vsi->vf_id; | |
11221 | u8 i; | |
11222 | ||
11223 | if (vsi->type == I40E_VSI_MAIN) { | |
11224 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
11225 | wr32(hw, I40E_PFQF_HLUT(i), 0); | |
11226 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
11227 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
11228 | i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0); | |
11229 | } else { | |
11230 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
11231 | } | |
11232 | } | |
11233 | ||
41c445ff JB |
11234 | /** |
11235 | * i40e_set_features - set the netdev feature flags | |
11236 | * @netdev: ptr to the netdev being adjusted | |
11237 | * @features: the feature set that the stack is suggesting | |
373149fc | 11238 | * Note: expects to be called while under rtnl_lock() |
41c445ff JB |
11239 | **/ |
11240 | static int i40e_set_features(struct net_device *netdev, | |
11241 | netdev_features_t features) | |
11242 | { | |
11243 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
11244 | struct i40e_vsi *vsi = np->vsi; | |
7c3c288b ASJ |
11245 | struct i40e_pf *pf = vsi->back; |
11246 | bool need_reset; | |
41c445ff | 11247 | |
d8ec9864 AB |
11248 | if (features & NETIF_F_RXHASH && !(netdev->features & NETIF_F_RXHASH)) |
11249 | i40e_pf_config_rss(pf); | |
11250 | else if (!(features & NETIF_F_RXHASH) && | |
11251 | netdev->features & NETIF_F_RXHASH) | |
11252 | i40e_clear_rss_lut(vsi); | |
11253 | ||
41c445ff JB |
11254 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
11255 | i40e_vlan_stripping_enable(vsi); | |
11256 | else | |
11257 | i40e_vlan_stripping_disable(vsi); | |
11258 | ||
2f4b411a AN |
11259 | if (!(features & NETIF_F_HW_TC) && pf->num_cloud_filters) { |
11260 | dev_err(&pf->pdev->dev, | |
11261 | "Offloaded tc filters active, can't turn hw_tc_offload off"); | |
11262 | return -EINVAL; | |
11263 | } | |
11264 | ||
7c3c288b ASJ |
11265 | need_reset = i40e_set_ntuple(pf, features); |
11266 | ||
11267 | if (need_reset) | |
ff424188 | 11268 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
7c3c288b | 11269 | |
41c445ff JB |
11270 | return 0; |
11271 | } | |
11272 | ||
a1c9a9d9 | 11273 | /** |
6a899024 | 11274 | * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port |
a1c9a9d9 JK |
11275 | * @pf: board private structure |
11276 | * @port: The UDP port to look up | |
11277 | * | |
11278 | * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found | |
11279 | **/ | |
fe0b0cd9 | 11280 | static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, u16 port) |
a1c9a9d9 JK |
11281 | { |
11282 | u8 i; | |
11283 | ||
11284 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
27826fd5 | 11285 | if (pf->udp_ports[i].port == port) |
a1c9a9d9 JK |
11286 | return i; |
11287 | } | |
11288 | ||
11289 | return i; | |
11290 | } | |
11291 | ||
11292 | /** | |
06a5f7f1 | 11293 | * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up |
a1c9a9d9 | 11294 | * @netdev: This physical port's netdev |
06a5f7f1 | 11295 | * @ti: Tunnel endpoint information |
a1c9a9d9 | 11296 | **/ |
06a5f7f1 AD |
11297 | static void i40e_udp_tunnel_add(struct net_device *netdev, |
11298 | struct udp_tunnel_info *ti) | |
a1c9a9d9 JK |
11299 | { |
11300 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
11301 | struct i40e_vsi *vsi = np->vsi; | |
11302 | struct i40e_pf *pf = vsi->back; | |
fe0b0cd9 | 11303 | u16 port = ntohs(ti->port); |
a1c9a9d9 JK |
11304 | u8 next_idx; |
11305 | u8 idx; | |
11306 | ||
6a899024 | 11307 | idx = i40e_get_udp_port_idx(pf, port); |
a1c9a9d9 JK |
11308 | |
11309 | /* Check if port already exists */ | |
11310 | if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
fe0b0cd9 | 11311 | netdev_info(netdev, "port %d already offloaded\n", port); |
a1c9a9d9 JK |
11312 | return; |
11313 | } | |
11314 | ||
11315 | /* Now check if there is space to add the new port */ | |
6a899024 | 11316 | next_idx = i40e_get_udp_port_idx(pf, 0); |
a1c9a9d9 JK |
11317 | |
11318 | if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
06a5f7f1 | 11319 | netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n", |
fe0b0cd9 | 11320 | port); |
6a899024 SA |
11321 | return; |
11322 | } | |
11323 | ||
06a5f7f1 AD |
11324 | switch (ti->type) { |
11325 | case UDP_TUNNEL_TYPE_VXLAN: | |
11326 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN; | |
11327 | break; | |
11328 | case UDP_TUNNEL_TYPE_GENEVE: | |
d36e41dc | 11329 | if (!(pf->hw_features & I40E_HW_GENEVE_OFFLOAD_CAPABLE)) |
06a5f7f1 AD |
11330 | return; |
11331 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE; | |
11332 | break; | |
11333 | default: | |
6a899024 SA |
11334 | return; |
11335 | } | |
11336 | ||
11337 | /* New port: add it and mark its index in the bitmap */ | |
27826fd5 | 11338 | pf->udp_ports[next_idx].port = port; |
6a899024 SA |
11339 | pf->pending_udp_bitmap |= BIT_ULL(next_idx); |
11340 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
a1c9a9d9 JK |
11341 | } |
11342 | ||
6a899024 | 11343 | /** |
06a5f7f1 | 11344 | * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away |
6a899024 | 11345 | * @netdev: This physical port's netdev |
06a5f7f1 | 11346 | * @ti: Tunnel endpoint information |
6a899024 | 11347 | **/ |
06a5f7f1 AD |
11348 | static void i40e_udp_tunnel_del(struct net_device *netdev, |
11349 | struct udp_tunnel_info *ti) | |
6a899024 | 11350 | { |
6a899024 SA |
11351 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
11352 | struct i40e_vsi *vsi = np->vsi; | |
11353 | struct i40e_pf *pf = vsi->back; | |
fe0b0cd9 | 11354 | u16 port = ntohs(ti->port); |
6a899024 SA |
11355 | u8 idx; |
11356 | ||
6a899024 SA |
11357 | idx = i40e_get_udp_port_idx(pf, port); |
11358 | ||
11359 | /* Check if port already exists */ | |
06a5f7f1 AD |
11360 | if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS) |
11361 | goto not_found; | |
6a899024 | 11362 | |
06a5f7f1 AD |
11363 | switch (ti->type) { |
11364 | case UDP_TUNNEL_TYPE_VXLAN: | |
11365 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN) | |
11366 | goto not_found; | |
11367 | break; | |
11368 | case UDP_TUNNEL_TYPE_GENEVE: | |
11369 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE) | |
11370 | goto not_found; | |
11371 | break; | |
11372 | default: | |
11373 | goto not_found; | |
6a899024 | 11374 | } |
06a5f7f1 AD |
11375 | |
11376 | /* if port exists, set it to 0 (mark for deletion) | |
11377 | * and make it pending | |
11378 | */ | |
27826fd5 | 11379 | pf->udp_ports[idx].port = 0; |
06a5f7f1 AD |
11380 | pf->pending_udp_bitmap |= BIT_ULL(idx); |
11381 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
11382 | ||
11383 | return; | |
11384 | not_found: | |
11385 | netdev_warn(netdev, "UDP port %d was not found, not deleting\n", | |
fe0b0cd9 | 11386 | port); |
6a899024 SA |
11387 | } |
11388 | ||
1f224ad2 | 11389 | static int i40e_get_phys_port_id(struct net_device *netdev, |
02637fce | 11390 | struct netdev_phys_item_id *ppid) |
1f224ad2 NP |
11391 | { |
11392 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
11393 | struct i40e_pf *pf = np->vsi->back; | |
11394 | struct i40e_hw *hw = &pf->hw; | |
11395 | ||
d36e41dc | 11396 | if (!(pf->hw_features & I40E_HW_PORT_ID_VALID)) |
1f224ad2 NP |
11397 | return -EOPNOTSUPP; |
11398 | ||
11399 | ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id)); | |
11400 | memcpy(ppid->id, hw->mac.port_addr, ppid->id_len); | |
11401 | ||
11402 | return 0; | |
11403 | } | |
11404 | ||
2f90ade6 JB |
11405 | /** |
11406 | * i40e_ndo_fdb_add - add an entry to the hardware database | |
11407 | * @ndm: the input from the stack | |
11408 | * @tb: pointer to array of nladdr (unused) | |
11409 | * @dev: the net device pointer | |
11410 | * @addr: the MAC address entry being added | |
11411 | * @flags: instructions from stack about fdb operation | |
11412 | */ | |
4ba0dea5 GR |
11413 | static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
11414 | struct net_device *dev, | |
f6f6424b | 11415 | const unsigned char *addr, u16 vid, |
4ba0dea5 | 11416 | u16 flags) |
4ba0dea5 GR |
11417 | { |
11418 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
11419 | struct i40e_pf *pf = np->vsi->back; | |
11420 | int err = 0; | |
11421 | ||
11422 | if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED)) | |
11423 | return -EOPNOTSUPP; | |
11424 | ||
65891fea OG |
11425 | if (vid) { |
11426 | pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name); | |
11427 | return -EINVAL; | |
11428 | } | |
11429 | ||
4ba0dea5 GR |
11430 | /* Hardware does not support aging addresses so if a |
11431 | * ndm_state is given only allow permanent addresses | |
11432 | */ | |
11433 | if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { | |
11434 | netdev_info(dev, "FDB only supports static addresses\n"); | |
11435 | return -EINVAL; | |
11436 | } | |
11437 | ||
11438 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) | |
11439 | err = dev_uc_add_excl(dev, addr); | |
11440 | else if (is_multicast_ether_addr(addr)) | |
11441 | err = dev_mc_add_excl(dev, addr); | |
11442 | else | |
11443 | err = -EINVAL; | |
11444 | ||
11445 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
11446 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
11447 | err = 0; | |
11448 | ||
11449 | return err; | |
11450 | } | |
11451 | ||
51616018 NP |
11452 | /** |
11453 | * i40e_ndo_bridge_setlink - Set the hardware bridge mode | |
11454 | * @dev: the netdev being configured | |
11455 | * @nlh: RTNL message | |
11456 | * | |
11457 | * Inserts a new hardware bridge if not already created and | |
11458 | * enables the bridging mode requested (VEB or VEPA). If the | |
11459 | * hardware bridge has already been inserted and the request | |
11460 | * is to change the mode then that requires a PF reset to | |
11461 | * allow rebuild of the components with required hardware | |
11462 | * bridge mode enabled. | |
373149fc MS |
11463 | * |
11464 | * Note: expects to be called while under rtnl_lock() | |
51616018 NP |
11465 | **/ |
11466 | static int i40e_ndo_bridge_setlink(struct net_device *dev, | |
9df70b66 CW |
11467 | struct nlmsghdr *nlh, |
11468 | u16 flags) | |
51616018 NP |
11469 | { |
11470 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
11471 | struct i40e_vsi *vsi = np->vsi; | |
11472 | struct i40e_pf *pf = vsi->back; | |
11473 | struct i40e_veb *veb = NULL; | |
11474 | struct nlattr *attr, *br_spec; | |
11475 | int i, rem; | |
11476 | ||
11477 | /* Only for PF VSI for now */ | |
11478 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
11479 | return -EOPNOTSUPP; | |
11480 | ||
11481 | /* Find the HW bridge for PF VSI */ | |
11482 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
11483 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
11484 | veb = pf->veb[i]; | |
11485 | } | |
11486 | ||
11487 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
11488 | ||
11489 | nla_for_each_nested(attr, br_spec, rem) { | |
11490 | __u16 mode; | |
11491 | ||
11492 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
11493 | continue; | |
11494 | ||
11495 | mode = nla_get_u16(attr); | |
11496 | if ((mode != BRIDGE_MODE_VEPA) && | |
11497 | (mode != BRIDGE_MODE_VEB)) | |
11498 | return -EINVAL; | |
11499 | ||
11500 | /* Insert a new HW bridge */ | |
11501 | if (!veb) { | |
11502 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
11503 | vsi->tc_config.enabled_tc); | |
11504 | if (veb) { | |
11505 | veb->bridge_mode = mode; | |
11506 | i40e_config_bridge_mode(veb); | |
11507 | } else { | |
11508 | /* No Bridge HW offload available */ | |
11509 | return -ENOENT; | |
11510 | } | |
11511 | break; | |
11512 | } else if (mode != veb->bridge_mode) { | |
11513 | /* Existing HW bridge but different mode needs reset */ | |
11514 | veb->bridge_mode = mode; | |
fc60861e ASJ |
11515 | /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */ |
11516 | if (mode == BRIDGE_MODE_VEB) | |
11517 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
11518 | else | |
11519 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
ff424188 | 11520 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
51616018 NP |
11521 | break; |
11522 | } | |
11523 | } | |
11524 | ||
11525 | return 0; | |
11526 | } | |
11527 | ||
11528 | /** | |
11529 | * i40e_ndo_bridge_getlink - Get the hardware bridge mode | |
11530 | * @skb: skb buff | |
11531 | * @pid: process id | |
11532 | * @seq: RTNL message seq # | |
11533 | * @dev: the netdev being configured | |
11534 | * @filter_mask: unused | |
d4b2f9fe | 11535 | * @nlflags: netlink flags passed in |
51616018 NP |
11536 | * |
11537 | * Return the mode in which the hardware bridge is operating in | |
11538 | * i.e VEB or VEPA. | |
11539 | **/ | |
51616018 NP |
11540 | static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
11541 | struct net_device *dev, | |
9f4ffc44 CW |
11542 | u32 __always_unused filter_mask, |
11543 | int nlflags) | |
51616018 NP |
11544 | { |
11545 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
11546 | struct i40e_vsi *vsi = np->vsi; | |
11547 | struct i40e_pf *pf = vsi->back; | |
11548 | struct i40e_veb *veb = NULL; | |
11549 | int i; | |
11550 | ||
11551 | /* Only for PF VSI for now */ | |
11552 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
11553 | return -EOPNOTSUPP; | |
11554 | ||
11555 | /* Find the HW bridge for the PF VSI */ | |
11556 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
11557 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
11558 | veb = pf->veb[i]; | |
11559 | } | |
11560 | ||
11561 | if (!veb) | |
11562 | return 0; | |
11563 | ||
46c264da | 11564 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode, |
599b076d | 11565 | 0, 0, nlflags, filter_mask, NULL); |
51616018 | 11566 | } |
51616018 | 11567 | |
f44a75e2 JS |
11568 | /** |
11569 | * i40e_features_check - Validate encapsulated packet conforms to limits | |
11570 | * @skb: skb buff | |
2bc11c63 | 11571 | * @dev: This physical port's netdev |
f44a75e2 JS |
11572 | * @features: Offload features that the stack believes apply |
11573 | **/ | |
11574 | static netdev_features_t i40e_features_check(struct sk_buff *skb, | |
11575 | struct net_device *dev, | |
11576 | netdev_features_t features) | |
11577 | { | |
f114dca2 AD |
11578 | size_t len; |
11579 | ||
11580 | /* No point in doing any of this if neither checksum nor GSO are | |
11581 | * being requested for this frame. We can rule out both by just | |
11582 | * checking for CHECKSUM_PARTIAL | |
11583 | */ | |
11584 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
11585 | return features; | |
11586 | ||
11587 | /* We cannot support GSO if the MSS is going to be less than | |
11588 | * 64 bytes. If it is then we need to drop support for GSO. | |
11589 | */ | |
11590 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_size < 64)) | |
11591 | features &= ~NETIF_F_GSO_MASK; | |
11592 | ||
11593 | /* MACLEN can support at most 63 words */ | |
11594 | len = skb_network_header(skb) - skb->data; | |
11595 | if (len & ~(63 * 2)) | |
11596 | goto out_err; | |
11597 | ||
11598 | /* IPLEN and EIPLEN can support at most 127 dwords */ | |
11599 | len = skb_transport_header(skb) - skb_network_header(skb); | |
11600 | if (len & ~(127 * 4)) | |
11601 | goto out_err; | |
11602 | ||
11603 | if (skb->encapsulation) { | |
11604 | /* L4TUNLEN can support 127 words */ | |
11605 | len = skb_inner_network_header(skb) - skb_transport_header(skb); | |
11606 | if (len & ~(127 * 2)) | |
11607 | goto out_err; | |
11608 | ||
11609 | /* IPLEN can support at most 127 dwords */ | |
11610 | len = skb_inner_transport_header(skb) - | |
11611 | skb_inner_network_header(skb); | |
11612 | if (len & ~(127 * 4)) | |
11613 | goto out_err; | |
11614 | } | |
11615 | ||
11616 | /* No need to validate L4LEN as TCP is the only protocol with a | |
11617 | * a flexible value and we support all possible values supported | |
11618 | * by TCP, which is at most 15 dwords | |
11619 | */ | |
f44a75e2 JS |
11620 | |
11621 | return features; | |
f114dca2 AD |
11622 | out_err: |
11623 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
f44a75e2 JS |
11624 | } |
11625 | ||
0c8493d9 BT |
11626 | /** |
11627 | * i40e_xdp_setup - add/remove an XDP program | |
11628 | * @vsi: VSI to changed | |
11629 | * @prog: XDP program | |
11630 | **/ | |
11631 | static int i40e_xdp_setup(struct i40e_vsi *vsi, | |
11632 | struct bpf_prog *prog) | |
11633 | { | |
11634 | int frame_size = vsi->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
11635 | struct i40e_pf *pf = vsi->back; | |
11636 | struct bpf_prog *old_prog; | |
11637 | bool need_reset; | |
11638 | int i; | |
11639 | ||
11640 | /* Don't allow frames that span over multiple buffers */ | |
11641 | if (frame_size > vsi->rx_buf_len) | |
11642 | return -EINVAL; | |
11643 | ||
11644 | if (!i40e_enabled_xdp_vsi(vsi) && !prog) | |
11645 | return 0; | |
11646 | ||
11647 | /* When turning XDP on->off/off->on we reset and rebuild the rings. */ | |
11648 | need_reset = (i40e_enabled_xdp_vsi(vsi) != !!prog); | |
11649 | ||
11650 | if (need_reset) | |
11651 | i40e_prep_for_reset(pf, true); | |
11652 | ||
11653 | old_prog = xchg(&vsi->xdp_prog, prog); | |
11654 | ||
11655 | if (need_reset) | |
11656 | i40e_reset_and_rebuild(pf, true, true); | |
11657 | ||
11658 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
11659 | WRITE_ONCE(vsi->rx_rings[i]->xdp_prog, vsi->xdp_prog); | |
11660 | ||
11661 | if (old_prog) | |
11662 | bpf_prog_put(old_prog); | |
11663 | ||
11664 | return 0; | |
11665 | } | |
11666 | ||
11667 | /** | |
f4e63525 | 11668 | * i40e_xdp - implements ndo_bpf for i40e |
0c8493d9 BT |
11669 | * @dev: netdevice |
11670 | * @xdp: XDP command | |
11671 | **/ | |
11672 | static int i40e_xdp(struct net_device *dev, | |
f4e63525 | 11673 | struct netdev_bpf *xdp) |
0c8493d9 BT |
11674 | { |
11675 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
11676 | struct i40e_vsi *vsi = np->vsi; | |
11677 | ||
11678 | if (vsi->type != I40E_VSI_MAIN) | |
11679 | return -EINVAL; | |
11680 | ||
11681 | switch (xdp->command) { | |
11682 | case XDP_SETUP_PROG: | |
11683 | return i40e_xdp_setup(vsi, xdp->prog); | |
11684 | case XDP_QUERY_PROG: | |
11685 | xdp->prog_attached = i40e_enabled_xdp_vsi(vsi); | |
eb23039f | 11686 | xdp->prog_id = vsi->xdp_prog ? vsi->xdp_prog->aux->id : 0; |
0c8493d9 BT |
11687 | return 0; |
11688 | default: | |
11689 | return -EINVAL; | |
11690 | } | |
11691 | } | |
11692 | ||
37a2973a | 11693 | static const struct net_device_ops i40e_netdev_ops = { |
41c445ff JB |
11694 | .ndo_open = i40e_open, |
11695 | .ndo_stop = i40e_close, | |
11696 | .ndo_start_xmit = i40e_lan_xmit_frame, | |
11697 | .ndo_get_stats64 = i40e_get_netdev_stats_struct, | |
11698 | .ndo_set_rx_mode = i40e_set_rx_mode, | |
11699 | .ndo_validate_addr = eth_validate_addr, | |
11700 | .ndo_set_mac_address = i40e_set_mac, | |
11701 | .ndo_change_mtu = i40e_change_mtu, | |
beb0dff1 | 11702 | .ndo_do_ioctl = i40e_ioctl, |
41c445ff JB |
11703 | .ndo_tx_timeout = i40e_tx_timeout, |
11704 | .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid, | |
11705 | .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid, | |
11706 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
11707 | .ndo_poll_controller = i40e_netpoll, | |
11708 | #endif | |
e4c6734e | 11709 | .ndo_setup_tc = __i40e_setup_tc, |
41c445ff JB |
11710 | .ndo_set_features = i40e_set_features, |
11711 | .ndo_set_vf_mac = i40e_ndo_set_vf_mac, | |
11712 | .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan, | |
ed616689 | 11713 | .ndo_set_vf_rate = i40e_ndo_set_vf_bw, |
41c445ff | 11714 | .ndo_get_vf_config = i40e_ndo_get_vf_config, |
588aefa0 | 11715 | .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state, |
e6d9004d | 11716 | .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk, |
c3bbbd20 | 11717 | .ndo_set_vf_trust = i40e_ndo_set_vf_trust, |
06a5f7f1 AD |
11718 | .ndo_udp_tunnel_add = i40e_udp_tunnel_add, |
11719 | .ndo_udp_tunnel_del = i40e_udp_tunnel_del, | |
1f224ad2 | 11720 | .ndo_get_phys_port_id = i40e_get_phys_port_id, |
4ba0dea5 | 11721 | .ndo_fdb_add = i40e_ndo_fdb_add, |
f44a75e2 | 11722 | .ndo_features_check = i40e_features_check, |
51616018 NP |
11723 | .ndo_bridge_getlink = i40e_ndo_bridge_getlink, |
11724 | .ndo_bridge_setlink = i40e_ndo_bridge_setlink, | |
f4e63525 | 11725 | .ndo_bpf = i40e_xdp, |
41c445ff JB |
11726 | }; |
11727 | ||
11728 | /** | |
11729 | * i40e_config_netdev - Setup the netdev flags | |
11730 | * @vsi: the VSI being configured | |
11731 | * | |
11732 | * Returns 0 on success, negative value on failure | |
11733 | **/ | |
11734 | static int i40e_config_netdev(struct i40e_vsi *vsi) | |
11735 | { | |
11736 | struct i40e_pf *pf = vsi->back; | |
11737 | struct i40e_hw *hw = &pf->hw; | |
11738 | struct i40e_netdev_priv *np; | |
11739 | struct net_device *netdev; | |
435c084a | 11740 | u8 broadcast[ETH_ALEN]; |
41c445ff JB |
11741 | u8 mac_addr[ETH_ALEN]; |
11742 | int etherdev_size; | |
bacd75cf PB |
11743 | netdev_features_t hw_enc_features; |
11744 | netdev_features_t hw_features; | |
41c445ff JB |
11745 | |
11746 | etherdev_size = sizeof(struct i40e_netdev_priv); | |
f8ff1464 | 11747 | netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs); |
41c445ff JB |
11748 | if (!netdev) |
11749 | return -ENOMEM; | |
11750 | ||
11751 | vsi->netdev = netdev; | |
11752 | np = netdev_priv(netdev); | |
11753 | np->vsi = vsi; | |
11754 | ||
bacd75cf PB |
11755 | hw_enc_features = NETIF_F_SG | |
11756 | NETIF_F_IP_CSUM | | |
11757 | NETIF_F_IPV6_CSUM | | |
11758 | NETIF_F_HIGHDMA | | |
11759 | NETIF_F_SOFT_FEATURES | | |
11760 | NETIF_F_TSO | | |
11761 | NETIF_F_TSO_ECN | | |
11762 | NETIF_F_TSO6 | | |
11763 | NETIF_F_GSO_GRE | | |
11764 | NETIF_F_GSO_GRE_CSUM | | |
11765 | NETIF_F_GSO_PARTIAL | | |
11766 | NETIF_F_GSO_UDP_TUNNEL | | |
11767 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
11768 | NETIF_F_SCTP_CRC | | |
11769 | NETIF_F_RXHASH | | |
11770 | NETIF_F_RXCSUM | | |
11771 | 0; | |
41c445ff | 11772 | |
d36e41dc | 11773 | if (!(pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE)) |
1c7b4a23 AD |
11774 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; |
11775 | ||
11776 | netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; | |
b0fe3306 | 11777 | |
bacd75cf PB |
11778 | netdev->hw_enc_features |= hw_enc_features; |
11779 | ||
b0fe3306 | 11780 | /* record features VLANs can make use of */ |
bacd75cf | 11781 | netdev->vlan_features |= hw_enc_features | NETIF_F_TSO_MANGLEID; |
41c445ff | 11782 | |
2e86a0b6 | 11783 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
2f4b411a AN |
11784 | netdev->hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC; |
11785 | ||
bacd75cf PB |
11786 | hw_features = hw_enc_features | |
11787 | NETIF_F_HW_VLAN_CTAG_TX | | |
11788 | NETIF_F_HW_VLAN_CTAG_RX; | |
b0fe3306 | 11789 | |
bacd75cf | 11790 | netdev->hw_features |= hw_features; |
2e86a0b6 | 11791 | |
bacd75cf | 11792 | netdev->features |= hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; |
1c7b4a23 | 11793 | netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; |
41c445ff JB |
11794 | |
11795 | if (vsi->type == I40E_VSI_MAIN) { | |
11796 | SET_NETDEV_DEV(netdev, &pf->pdev->dev); | |
9a173901 | 11797 | ether_addr_copy(mac_addr, hw->mac.perm_addr); |
41c4c2b5 JK |
11798 | /* The following steps are necessary for two reasons. First, |
11799 | * some older NVM configurations load a default MAC-VLAN | |
11800 | * filter that will accept any tagged packet, and we want to | |
11801 | * replace this with a normal filter. Additionally, it is | |
11802 | * possible our MAC address was provided by the platform using | |
11803 | * Open Firmware or similar. | |
11804 | * | |
11805 | * Thus, we need to remove the default filter and install one | |
11806 | * specific to the MAC address. | |
1596b5dd JK |
11807 | */ |
11808 | i40e_rm_default_mac_filter(vsi, mac_addr); | |
278e7d0b | 11809 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 11810 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 11811 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 11812 | } else { |
8c9eb350 JK |
11813 | /* Relate the VSI_VMDQ name to the VSI_MAIN name. Note that we |
11814 | * are still limited by IFNAMSIZ, but we're adding 'v%d\0' to | |
11815 | * the end, which is 4 bytes long, so force truncation of the | |
11816 | * original name by IFNAMSIZ - 4 | |
11817 | */ | |
11818 | snprintf(netdev->name, IFNAMSIZ, "%.*sv%%d", | |
11819 | IFNAMSIZ - 4, | |
41c445ff JB |
11820 | pf->vsi[pf->lan_vsi]->netdev->name); |
11821 | random_ether_addr(mac_addr); | |
21659035 | 11822 | |
278e7d0b | 11823 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 11824 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 11825 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 11826 | } |
21659035 | 11827 | |
435c084a JK |
11828 | /* Add the broadcast filter so that we initially will receive |
11829 | * broadcast packets. Note that when a new VLAN is first added the | |
11830 | * driver will convert all filters marked I40E_VLAN_ANY into VLAN | |
11831 | * specific filters as part of transitioning into "vlan" operation. | |
11832 | * When more VLANs are added, the driver will copy each existing MAC | |
11833 | * filter and add it for the new VLAN. | |
11834 | * | |
11835 | * Broadcast filters are handled specially by | |
11836 | * i40e_sync_filters_subtask, as the driver must to set the broadcast | |
11837 | * promiscuous bit instead of adding this directly as a MAC/VLAN | |
11838 | * filter. The subtask will update the correct broadcast promiscuous | |
11839 | * bits as VLANs become active or inactive. | |
11840 | */ | |
11841 | eth_broadcast_addr(broadcast); | |
11842 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
9569a9a4 | 11843 | i40e_add_mac_filter(vsi, broadcast); |
435c084a JK |
11844 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
11845 | ||
9a173901 GR |
11846 | ether_addr_copy(netdev->dev_addr, mac_addr); |
11847 | ether_addr_copy(netdev->perm_addr, mac_addr); | |
b0fe3306 | 11848 | |
41c445ff JB |
11849 | netdev->priv_flags |= IFF_UNICAST_FLT; |
11850 | netdev->priv_flags |= IFF_SUPP_NOFCS; | |
11851 | /* Setup netdev TC information */ | |
11852 | i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc); | |
11853 | ||
11854 | netdev->netdev_ops = &i40e_netdev_ops; | |
11855 | netdev->watchdog_timeo = 5 * HZ; | |
11856 | i40e_set_ethtool_ops(netdev); | |
11857 | ||
91c527a5 JW |
11858 | /* MTU range: 68 - 9706 */ |
11859 | netdev->min_mtu = ETH_MIN_MTU; | |
1e3a5fd5 | 11860 | netdev->max_mtu = I40E_MAX_RXBUFFER - I40E_PACKET_HDR_PAD; |
91c527a5 | 11861 | |
41c445ff JB |
11862 | return 0; |
11863 | } | |
11864 | ||
11865 | /** | |
11866 | * i40e_vsi_delete - Delete a VSI from the switch | |
11867 | * @vsi: the VSI being removed | |
11868 | * | |
11869 | * Returns 0 on success, negative value on failure | |
11870 | **/ | |
11871 | static void i40e_vsi_delete(struct i40e_vsi *vsi) | |
11872 | { | |
11873 | /* remove default VSI is not allowed */ | |
11874 | if (vsi == vsi->back->vsi[vsi->back->lan_vsi]) | |
11875 | return; | |
11876 | ||
41c445ff | 11877 | i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL); |
41c445ff JB |
11878 | } |
11879 | ||
51616018 NP |
11880 | /** |
11881 | * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB | |
11882 | * @vsi: the VSI being queried | |
11883 | * | |
11884 | * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode | |
11885 | **/ | |
11886 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi) | |
11887 | { | |
11888 | struct i40e_veb *veb; | |
11889 | struct i40e_pf *pf = vsi->back; | |
11890 | ||
11891 | /* Uplink is not a bridge so default to VEB */ | |
11892 | if (vsi->veb_idx == I40E_NO_VEB) | |
11893 | return 1; | |
11894 | ||
11895 | veb = pf->veb[vsi->veb_idx]; | |
09603eaa AA |
11896 | if (!veb) { |
11897 | dev_info(&pf->pdev->dev, | |
11898 | "There is no veb associated with the bridge\n"); | |
11899 | return -ENOENT; | |
11900 | } | |
11901 | ||
51616018 | 11902 | /* Uplink is a bridge in VEPA mode */ |
09603eaa | 11903 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) { |
51616018 | 11904 | return 0; |
09603eaa AA |
11905 | } else { |
11906 | /* Uplink is a bridge in VEB mode */ | |
11907 | return 1; | |
11908 | } | |
51616018 | 11909 | |
09603eaa AA |
11910 | /* VEPA is now default bridge, so return 0 */ |
11911 | return 0; | |
51616018 NP |
11912 | } |
11913 | ||
41c445ff JB |
11914 | /** |
11915 | * i40e_add_vsi - Add a VSI to the switch | |
11916 | * @vsi: the VSI being configured | |
11917 | * | |
11918 | * This initializes a VSI context depending on the VSI type to be added and | |
11919 | * passes it down to the add_vsi aq command. | |
11920 | **/ | |
11921 | static int i40e_add_vsi(struct i40e_vsi *vsi) | |
11922 | { | |
11923 | int ret = -ENODEV; | |
41c445ff JB |
11924 | struct i40e_pf *pf = vsi->back; |
11925 | struct i40e_hw *hw = &pf->hw; | |
11926 | struct i40e_vsi_context ctxt; | |
278e7d0b JK |
11927 | struct i40e_mac_filter *f; |
11928 | struct hlist_node *h; | |
11929 | int bkt; | |
21659035 | 11930 | |
41c445ff JB |
11931 | u8 enabled_tc = 0x1; /* TC0 enabled */ |
11932 | int f_count = 0; | |
11933 | ||
11934 | memset(&ctxt, 0, sizeof(ctxt)); | |
11935 | switch (vsi->type) { | |
11936 | case I40E_VSI_MAIN: | |
11937 | /* The PF's main VSI is already setup as part of the | |
11938 | * device initialization, so we'll not bother with | |
11939 | * the add_vsi call, but we will retrieve the current | |
11940 | * VSI context. | |
11941 | */ | |
11942 | ctxt.seid = pf->main_vsi_seid; | |
11943 | ctxt.pf_num = pf->hw.pf_id; | |
11944 | ctxt.vf_num = 0; | |
11945 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); | |
11946 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
11947 | if (ret) { | |
11948 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
11949 | "couldn't get PF vsi config, err %s aq_err %s\n", |
11950 | i40e_stat_str(&pf->hw, ret), | |
11951 | i40e_aq_str(&pf->hw, | |
11952 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
11953 | return -ENOENT; |
11954 | } | |
1a2f6248 | 11955 | vsi->info = ctxt.info; |
41c445ff JB |
11956 | vsi->info.valid_sections = 0; |
11957 | ||
11958 | vsi->seid = ctxt.seid; | |
11959 | vsi->id = ctxt.vsi_number; | |
11960 | ||
11961 | enabled_tc = i40e_pf_get_tc_map(pf); | |
11962 | ||
64615b54 MW |
11963 | /* Source pruning is enabled by default, so the flag is |
11964 | * negative logic - if it's set, we need to fiddle with | |
11965 | * the VSI to disable source pruning. | |
11966 | */ | |
11967 | if (pf->flags & I40E_FLAG_SOURCE_PRUNING_DISABLED) { | |
11968 | memset(&ctxt, 0, sizeof(ctxt)); | |
11969 | ctxt.seid = pf->main_vsi_seid; | |
11970 | ctxt.pf_num = pf->hw.pf_id; | |
11971 | ctxt.vf_num = 0; | |
11972 | ctxt.info.valid_sections |= | |
11973 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
11974 | ctxt.info.switch_id = | |
11975 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); | |
11976 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
11977 | if (ret) { | |
11978 | dev_info(&pf->pdev->dev, | |
11979 | "update vsi failed, err %s aq_err %s\n", | |
11980 | i40e_stat_str(&pf->hw, ret), | |
11981 | i40e_aq_str(&pf->hw, | |
11982 | pf->hw.aq.asq_last_status)); | |
11983 | ret = -ENOENT; | |
11984 | goto err; | |
11985 | } | |
11986 | } | |
11987 | ||
41c445ff | 11988 | /* MFP mode setup queue map and update VSI */ |
63d7e5a4 NP |
11989 | if ((pf->flags & I40E_FLAG_MFP_ENABLED) && |
11990 | !(pf->hw.func_caps.iscsi)) { /* NIC type PF */ | |
41c445ff JB |
11991 | memset(&ctxt, 0, sizeof(ctxt)); |
11992 | ctxt.seid = pf->main_vsi_seid; | |
11993 | ctxt.pf_num = pf->hw.pf_id; | |
11994 | ctxt.vf_num = 0; | |
11995 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
11996 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
11997 | if (ret) { | |
11998 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
11999 | "update vsi failed, err %s aq_err %s\n", |
12000 | i40e_stat_str(&pf->hw, ret), | |
12001 | i40e_aq_str(&pf->hw, | |
12002 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12003 | ret = -ENOENT; |
12004 | goto err; | |
12005 | } | |
12006 | /* update the local VSI info queue map */ | |
12007 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
12008 | vsi->info.valid_sections = 0; | |
12009 | } else { | |
12010 | /* Default/Main VSI is only enabled for TC0 | |
12011 | * reconfigure it to enable all TCs that are | |
12012 | * available on the port in SFP mode. | |
63d7e5a4 NP |
12013 | * For MFP case the iSCSI PF would use this |
12014 | * flow to enable LAN+iSCSI TC. | |
41c445ff JB |
12015 | */ |
12016 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
12017 | if (ret) { | |
19279235 CW |
12018 | /* Single TC condition is not fatal, |
12019 | * message and continue | |
12020 | */ | |
41c445ff | 12021 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
12022 | "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n", |
12023 | enabled_tc, | |
12024 | i40e_stat_str(&pf->hw, ret), | |
12025 | i40e_aq_str(&pf->hw, | |
12026 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12027 | } |
12028 | } | |
12029 | break; | |
12030 | ||
12031 | case I40E_VSI_FDIR: | |
cbf61325 ASJ |
12032 | ctxt.pf_num = hw->pf_id; |
12033 | ctxt.vf_num = 0; | |
12034 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 12035 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
cbf61325 | 12036 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; |
fc60861e ASJ |
12037 | if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) && |
12038 | (i40e_is_vsi_uplink_mode_veb(vsi))) { | |
51616018 | 12039 | ctxt.info.valid_sections |= |
fc60861e | 12040 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); |
51616018 | 12041 | ctxt.info.switch_id = |
fc60861e | 12042 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); |
51616018 | 12043 | } |
41c445ff | 12044 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); |
41c445ff JB |
12045 | break; |
12046 | ||
12047 | case I40E_VSI_VMDQ2: | |
12048 | ctxt.pf_num = hw->pf_id; | |
12049 | ctxt.vf_num = 0; | |
12050 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 12051 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
12052 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; |
12053 | ||
41c445ff JB |
12054 | /* This VSI is connected to VEB so the switch_id |
12055 | * should be set to zero by default. | |
12056 | */ | |
51616018 NP |
12057 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
12058 | ctxt.info.valid_sections |= | |
12059 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
12060 | ctxt.info.switch_id = | |
12061 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
12062 | } | |
41c445ff JB |
12063 | |
12064 | /* Setup the VSI tx/rx queue map for TC0 only for now */ | |
12065 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
12066 | break; | |
12067 | ||
12068 | case I40E_VSI_SRIOV: | |
12069 | ctxt.pf_num = hw->pf_id; | |
12070 | ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id; | |
12071 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 12072 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
12073 | ctxt.flags = I40E_AQ_VSI_TYPE_VF; |
12074 | ||
41c445ff JB |
12075 | /* This VSI is connected to VEB so the switch_id |
12076 | * should be set to zero by default. | |
12077 | */ | |
51616018 NP |
12078 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
12079 | ctxt.info.valid_sections |= | |
12080 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
12081 | ctxt.info.switch_id = | |
12082 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
12083 | } | |
41c445ff | 12084 | |
e3219ce6 ASJ |
12085 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
12086 | ctxt.info.valid_sections |= | |
12087 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
12088 | ctxt.info.queueing_opt_flags |= | |
4b28cdba AS |
12089 | (I40E_AQ_VSI_QUE_OPT_TCP_ENA | |
12090 | I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI); | |
e3219ce6 ASJ |
12091 | } |
12092 | ||
41c445ff JB |
12093 | ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); |
12094 | ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; | |
c674d125 MW |
12095 | if (pf->vf[vsi->vf_id].spoofchk) { |
12096 | ctxt.info.valid_sections |= | |
12097 | cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID); | |
12098 | ctxt.info.sec_flags |= | |
12099 | (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK | | |
12100 | I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK); | |
12101 | } | |
41c445ff JB |
12102 | /* Setup the VSI tx/rx queue map for TC0 only for now */ |
12103 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
12104 | break; | |
12105 | ||
e3219ce6 ASJ |
12106 | case I40E_VSI_IWARP: |
12107 | /* send down message to iWARP */ | |
12108 | break; | |
12109 | ||
41c445ff JB |
12110 | default: |
12111 | return -ENODEV; | |
12112 | } | |
12113 | ||
12114 | if (vsi->type != I40E_VSI_MAIN) { | |
12115 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
12116 | if (ret) { | |
12117 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
12118 | "add vsi failed, err %s aq_err %s\n", |
12119 | i40e_stat_str(&pf->hw, ret), | |
12120 | i40e_aq_str(&pf->hw, | |
12121 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12122 | ret = -ENOENT; |
12123 | goto err; | |
12124 | } | |
1a2f6248 | 12125 | vsi->info = ctxt.info; |
41c445ff JB |
12126 | vsi->info.valid_sections = 0; |
12127 | vsi->seid = ctxt.seid; | |
12128 | vsi->id = ctxt.vsi_number; | |
12129 | } | |
12130 | ||
c3c7ea27 | 12131 | vsi->active_filters = 0; |
0da36b97 | 12132 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
278e7d0b | 12133 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 12134 | /* If macvlan filters already exist, force them to get loaded */ |
278e7d0b | 12135 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 12136 | f->state = I40E_FILTER_NEW; |
41c445ff | 12137 | f_count++; |
21659035 | 12138 | } |
278e7d0b | 12139 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
30650cc5 | 12140 | |
41c445ff JB |
12141 | if (f_count) { |
12142 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
12143 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
12144 | } | |
12145 | ||
12146 | /* Update VSI BW information */ | |
12147 | ret = i40e_vsi_get_bw_info(vsi); | |
12148 | if (ret) { | |
12149 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12150 | "couldn't get vsi bw info, err %s aq_err %s\n", |
12151 | i40e_stat_str(&pf->hw, ret), | |
12152 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12153 | /* VSI is already added so not tearing that up */ |
12154 | ret = 0; | |
12155 | } | |
12156 | ||
12157 | err: | |
12158 | return ret; | |
12159 | } | |
12160 | ||
12161 | /** | |
12162 | * i40e_vsi_release - Delete a VSI and free its resources | |
12163 | * @vsi: the VSI being removed | |
12164 | * | |
12165 | * Returns 0 on success or < 0 on error | |
12166 | **/ | |
12167 | int i40e_vsi_release(struct i40e_vsi *vsi) | |
12168 | { | |
278e7d0b JK |
12169 | struct i40e_mac_filter *f; |
12170 | struct hlist_node *h; | |
41c445ff JB |
12171 | struct i40e_veb *veb = NULL; |
12172 | struct i40e_pf *pf; | |
12173 | u16 uplink_seid; | |
278e7d0b | 12174 | int i, n, bkt; |
41c445ff JB |
12175 | |
12176 | pf = vsi->back; | |
12177 | ||
12178 | /* release of a VEB-owner or last VSI is not allowed */ | |
12179 | if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
12180 | dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n", | |
12181 | vsi->seid, vsi->uplink_seid); | |
12182 | return -ENODEV; | |
12183 | } | |
12184 | if (vsi == pf->vsi[pf->lan_vsi] && | |
9e6c9c0f | 12185 | !test_bit(__I40E_DOWN, pf->state)) { |
41c445ff JB |
12186 | dev_info(&pf->pdev->dev, "Can't remove PF VSI\n"); |
12187 | return -ENODEV; | |
12188 | } | |
12189 | ||
12190 | uplink_seid = vsi->uplink_seid; | |
12191 | if (vsi->type != I40E_VSI_SRIOV) { | |
12192 | if (vsi->netdev_registered) { | |
12193 | vsi->netdev_registered = false; | |
12194 | if (vsi->netdev) { | |
12195 | /* results in a call to i40e_close() */ | |
12196 | unregister_netdev(vsi->netdev); | |
41c445ff JB |
12197 | } |
12198 | } else { | |
90ef8d47 | 12199 | i40e_vsi_close(vsi); |
41c445ff JB |
12200 | } |
12201 | i40e_vsi_disable_irq(vsi); | |
12202 | } | |
12203 | ||
278e7d0b | 12204 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
6622f5cd JK |
12205 | |
12206 | /* clear the sync flag on all filters */ | |
12207 | if (vsi->netdev) { | |
12208 | __dev_uc_unsync(vsi->netdev, NULL); | |
12209 | __dev_mc_unsync(vsi->netdev, NULL); | |
12210 | } | |
12211 | ||
12212 | /* make sure any remaining filters are marked for deletion */ | |
278e7d0b | 12213 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) |
290d2557 | 12214 | __i40e_del_filter(vsi, f); |
6622f5cd | 12215 | |
278e7d0b | 12216 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 12217 | |
17652c63 | 12218 | i40e_sync_vsi_filters(vsi); |
41c445ff JB |
12219 | |
12220 | i40e_vsi_delete(vsi); | |
12221 | i40e_vsi_free_q_vectors(vsi); | |
a4866597 SN |
12222 | if (vsi->netdev) { |
12223 | free_netdev(vsi->netdev); | |
12224 | vsi->netdev = NULL; | |
12225 | } | |
41c445ff JB |
12226 | i40e_vsi_clear_rings(vsi); |
12227 | i40e_vsi_clear(vsi); | |
12228 | ||
12229 | /* If this was the last thing on the VEB, except for the | |
12230 | * controlling VSI, remove the VEB, which puts the controlling | |
12231 | * VSI onto the next level down in the switch. | |
12232 | * | |
12233 | * Well, okay, there's one more exception here: don't remove | |
12234 | * the orphan VEBs yet. We'll wait for an explicit remove request | |
12235 | * from up the network stack. | |
12236 | */ | |
505682cd | 12237 | for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
12238 | if (pf->vsi[i] && |
12239 | pf->vsi[i]->uplink_seid == uplink_seid && | |
12240 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
12241 | n++; /* count the VSIs */ | |
12242 | } | |
12243 | } | |
12244 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
12245 | if (!pf->veb[i]) | |
12246 | continue; | |
12247 | if (pf->veb[i]->uplink_seid == uplink_seid) | |
12248 | n++; /* count the VEBs */ | |
12249 | if (pf->veb[i]->seid == uplink_seid) | |
12250 | veb = pf->veb[i]; | |
12251 | } | |
12252 | if (n == 0 && veb && veb->uplink_seid != 0) | |
12253 | i40e_veb_release(veb); | |
12254 | ||
12255 | return 0; | |
12256 | } | |
12257 | ||
12258 | /** | |
12259 | * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI | |
12260 | * @vsi: ptr to the VSI | |
12261 | * | |
12262 | * This should only be called after i40e_vsi_mem_alloc() which allocates the | |
12263 | * corresponding SW VSI structure and initializes num_queue_pairs for the | |
12264 | * newly allocated VSI. | |
12265 | * | |
12266 | * Returns 0 on success or negative on failure | |
12267 | **/ | |
12268 | static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi) | |
12269 | { | |
12270 | int ret = -ENOENT; | |
12271 | struct i40e_pf *pf = vsi->back; | |
12272 | ||
493fb300 | 12273 | if (vsi->q_vectors[0]) { |
41c445ff JB |
12274 | dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n", |
12275 | vsi->seid); | |
12276 | return -EEXIST; | |
12277 | } | |
12278 | ||
12279 | if (vsi->base_vector) { | |
f29eaa3d | 12280 | dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n", |
41c445ff JB |
12281 | vsi->seid, vsi->base_vector); |
12282 | return -EEXIST; | |
12283 | } | |
12284 | ||
90e04070 | 12285 | ret = i40e_vsi_alloc_q_vectors(vsi); |
41c445ff JB |
12286 | if (ret) { |
12287 | dev_info(&pf->pdev->dev, | |
12288 | "failed to allocate %d q_vector for VSI %d, ret=%d\n", | |
12289 | vsi->num_q_vectors, vsi->seid, ret); | |
12290 | vsi->num_q_vectors = 0; | |
12291 | goto vector_setup_out; | |
12292 | } | |
12293 | ||
26cdc443 ASJ |
12294 | /* In Legacy mode, we do not have to get any other vector since we |
12295 | * piggyback on the misc/ICR0 for queue interrupts. | |
12296 | */ | |
12297 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
12298 | return ret; | |
958a3e3b SN |
12299 | if (vsi->num_q_vectors) |
12300 | vsi->base_vector = i40e_get_lump(pf, pf->irq_pile, | |
12301 | vsi->num_q_vectors, vsi->idx); | |
41c445ff JB |
12302 | if (vsi->base_vector < 0) { |
12303 | dev_info(&pf->pdev->dev, | |
049a2be8 SN |
12304 | "failed to get tracking for %d vectors for VSI %d, err=%d\n", |
12305 | vsi->num_q_vectors, vsi->seid, vsi->base_vector); | |
41c445ff JB |
12306 | i40e_vsi_free_q_vectors(vsi); |
12307 | ret = -ENOENT; | |
12308 | goto vector_setup_out; | |
12309 | } | |
12310 | ||
12311 | vector_setup_out: | |
12312 | return ret; | |
12313 | } | |
12314 | ||
bc7d338f ASJ |
12315 | /** |
12316 | * i40e_vsi_reinit_setup - return and reallocate resources for a VSI | |
12317 | * @vsi: pointer to the vsi. | |
12318 | * | |
12319 | * This re-allocates a vsi's queue resources. | |
12320 | * | |
12321 | * Returns pointer to the successfully allocated and configured VSI sw struct | |
12322 | * on success, otherwise returns NULL on failure. | |
12323 | **/ | |
12324 | static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi) | |
12325 | { | |
74608d17 | 12326 | u16 alloc_queue_pairs; |
f534039d | 12327 | struct i40e_pf *pf; |
bc7d338f ASJ |
12328 | u8 enabled_tc; |
12329 | int ret; | |
12330 | ||
f534039d JU |
12331 | if (!vsi) |
12332 | return NULL; | |
12333 | ||
12334 | pf = vsi->back; | |
12335 | ||
bc7d338f ASJ |
12336 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
12337 | i40e_vsi_clear_rings(vsi); | |
12338 | ||
12339 | i40e_vsi_free_arrays(vsi, false); | |
12340 | i40e_set_num_rings_in_vsi(vsi); | |
12341 | ret = i40e_vsi_alloc_arrays(vsi, false); | |
12342 | if (ret) | |
12343 | goto err_vsi; | |
12344 | ||
74608d17 BT |
12345 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
12346 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
12347 | ||
12348 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
bc7d338f | 12349 | if (ret < 0) { |
049a2be8 | 12350 | dev_info(&pf->pdev->dev, |
f1c7e72e | 12351 | "failed to get tracking for %d queues for VSI %d err %d\n", |
74608d17 | 12352 | alloc_queue_pairs, vsi->seid, ret); |
bc7d338f ASJ |
12353 | goto err_vsi; |
12354 | } | |
12355 | vsi->base_queue = ret; | |
12356 | ||
12357 | /* Update the FW view of the VSI. Force a reset of TC and queue | |
12358 | * layout configurations. | |
12359 | */ | |
12360 | enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
12361 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; | |
12362 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
12363 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
1596b5dd JK |
12364 | if (vsi->type == I40E_VSI_MAIN) |
12365 | i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr); | |
bc7d338f ASJ |
12366 | |
12367 | /* assign it some queues */ | |
12368 | ret = i40e_alloc_rings(vsi); | |
12369 | if (ret) | |
12370 | goto err_rings; | |
12371 | ||
12372 | /* map all of the rings to the q_vectors */ | |
12373 | i40e_vsi_map_rings_to_vectors(vsi); | |
12374 | return vsi; | |
12375 | ||
12376 | err_rings: | |
12377 | i40e_vsi_free_q_vectors(vsi); | |
12378 | if (vsi->netdev_registered) { | |
12379 | vsi->netdev_registered = false; | |
12380 | unregister_netdev(vsi->netdev); | |
12381 | free_netdev(vsi->netdev); | |
12382 | vsi->netdev = NULL; | |
12383 | } | |
12384 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
12385 | err_vsi: | |
12386 | i40e_vsi_clear(vsi); | |
12387 | return NULL; | |
12388 | } | |
12389 | ||
41c445ff JB |
12390 | /** |
12391 | * i40e_vsi_setup - Set up a VSI by a given type | |
12392 | * @pf: board private structure | |
12393 | * @type: VSI type | |
12394 | * @uplink_seid: the switch element to link to | |
12395 | * @param1: usage depends upon VSI type. For VF types, indicates VF id | |
12396 | * | |
12397 | * This allocates the sw VSI structure and its queue resources, then add a VSI | |
12398 | * to the identified VEB. | |
12399 | * | |
12400 | * Returns pointer to the successfully allocated and configure VSI sw struct on | |
12401 | * success, otherwise returns NULL on failure. | |
12402 | **/ | |
12403 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, | |
12404 | u16 uplink_seid, u32 param1) | |
12405 | { | |
12406 | struct i40e_vsi *vsi = NULL; | |
12407 | struct i40e_veb *veb = NULL; | |
74608d17 | 12408 | u16 alloc_queue_pairs; |
41c445ff JB |
12409 | int ret, i; |
12410 | int v_idx; | |
12411 | ||
12412 | /* The requested uplink_seid must be either | |
12413 | * - the PF's port seid | |
12414 | * no VEB is needed because this is the PF | |
12415 | * or this is a Flow Director special case VSI | |
12416 | * - seid of an existing VEB | |
12417 | * - seid of a VSI that owns an existing VEB | |
12418 | * - seid of a VSI that doesn't own a VEB | |
12419 | * a new VEB is created and the VSI becomes the owner | |
12420 | * - seid of the PF VSI, which is what creates the first VEB | |
12421 | * this is a special case of the previous | |
12422 | * | |
12423 | * Find which uplink_seid we were given and create a new VEB if needed | |
12424 | */ | |
12425 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
12426 | if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) { | |
12427 | veb = pf->veb[i]; | |
12428 | break; | |
12429 | } | |
12430 | } | |
12431 | ||
12432 | if (!veb && uplink_seid != pf->mac_seid) { | |
12433 | ||
505682cd | 12434 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
12435 | if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) { |
12436 | vsi = pf->vsi[i]; | |
12437 | break; | |
12438 | } | |
12439 | } | |
12440 | if (!vsi) { | |
12441 | dev_info(&pf->pdev->dev, "no such uplink_seid %d\n", | |
12442 | uplink_seid); | |
12443 | return NULL; | |
12444 | } | |
12445 | ||
12446 | if (vsi->uplink_seid == pf->mac_seid) | |
12447 | veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid, | |
12448 | vsi->tc_config.enabled_tc); | |
12449 | else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) | |
12450 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
12451 | vsi->tc_config.enabled_tc); | |
79c21a82 ASJ |
12452 | if (veb) { |
12453 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) { | |
12454 | dev_info(&vsi->back->pdev->dev, | |
fb43201f | 12455 | "New VSI creation error, uplink seid of LAN VSI expected.\n"); |
79c21a82 ASJ |
12456 | return NULL; |
12457 | } | |
fa11cb3d ASJ |
12458 | /* We come up by default in VEPA mode if SRIOV is not |
12459 | * already enabled, in which case we can't force VEPA | |
12460 | * mode. | |
12461 | */ | |
12462 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
12463 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
12464 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
12465 | } | |
51616018 | 12466 | i40e_config_bridge_mode(veb); |
79c21a82 | 12467 | } |
41c445ff JB |
12468 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { |
12469 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
12470 | veb = pf->veb[i]; | |
12471 | } | |
12472 | if (!veb) { | |
12473 | dev_info(&pf->pdev->dev, "couldn't add VEB\n"); | |
12474 | return NULL; | |
12475 | } | |
12476 | ||
12477 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
12478 | uplink_seid = veb->seid; | |
12479 | } | |
12480 | ||
12481 | /* get vsi sw struct */ | |
12482 | v_idx = i40e_vsi_mem_alloc(pf, type); | |
12483 | if (v_idx < 0) | |
12484 | goto err_alloc; | |
12485 | vsi = pf->vsi[v_idx]; | |
cbf61325 ASJ |
12486 | if (!vsi) |
12487 | goto err_alloc; | |
41c445ff JB |
12488 | vsi->type = type; |
12489 | vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB); | |
12490 | ||
12491 | if (type == I40E_VSI_MAIN) | |
12492 | pf->lan_vsi = v_idx; | |
12493 | else if (type == I40E_VSI_SRIOV) | |
12494 | vsi->vf_id = param1; | |
12495 | /* assign it some queues */ | |
74608d17 BT |
12496 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
12497 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
12498 | ||
12499 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
41c445ff | 12500 | if (ret < 0) { |
049a2be8 SN |
12501 | dev_info(&pf->pdev->dev, |
12502 | "failed to get tracking for %d queues for VSI %d err=%d\n", | |
74608d17 | 12503 | alloc_queue_pairs, vsi->seid, ret); |
41c445ff JB |
12504 | goto err_vsi; |
12505 | } | |
12506 | vsi->base_queue = ret; | |
12507 | ||
12508 | /* get a VSI from the hardware */ | |
12509 | vsi->uplink_seid = uplink_seid; | |
12510 | ret = i40e_add_vsi(vsi); | |
12511 | if (ret) | |
12512 | goto err_vsi; | |
12513 | ||
12514 | switch (vsi->type) { | |
12515 | /* setup the netdev if needed */ | |
12516 | case I40E_VSI_MAIN: | |
12517 | case I40E_VSI_VMDQ2: | |
12518 | ret = i40e_config_netdev(vsi); | |
12519 | if (ret) | |
12520 | goto err_netdev; | |
12521 | ret = register_netdev(vsi->netdev); | |
12522 | if (ret) | |
12523 | goto err_netdev; | |
12524 | vsi->netdev_registered = true; | |
12525 | netif_carrier_off(vsi->netdev); | |
4e3b35b0 NP |
12526 | #ifdef CONFIG_I40E_DCB |
12527 | /* Setup DCB netlink interface */ | |
12528 | i40e_dcbnl_setup(vsi); | |
12529 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
12530 | /* fall through */ |
12531 | ||
12532 | case I40E_VSI_FDIR: | |
12533 | /* set up vectors and rings if needed */ | |
12534 | ret = i40e_vsi_setup_vectors(vsi); | |
12535 | if (ret) | |
12536 | goto err_msix; | |
12537 | ||
12538 | ret = i40e_alloc_rings(vsi); | |
12539 | if (ret) | |
12540 | goto err_rings; | |
12541 | ||
12542 | /* map all of the rings to the q_vectors */ | |
12543 | i40e_vsi_map_rings_to_vectors(vsi); | |
12544 | ||
12545 | i40e_vsi_reset_stats(vsi); | |
12546 | break; | |
12547 | ||
12548 | default: | |
12549 | /* no netdev or rings for the other VSI types */ | |
12550 | break; | |
12551 | } | |
12552 | ||
d36e41dc | 12553 | if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) && |
e25d00b8 ASJ |
12554 | (vsi->type == I40E_VSI_VMDQ2)) { |
12555 | ret = i40e_vsi_config_rss(vsi); | |
12556 | } | |
41c445ff JB |
12557 | return vsi; |
12558 | ||
12559 | err_rings: | |
12560 | i40e_vsi_free_q_vectors(vsi); | |
12561 | err_msix: | |
12562 | if (vsi->netdev_registered) { | |
12563 | vsi->netdev_registered = false; | |
12564 | unregister_netdev(vsi->netdev); | |
12565 | free_netdev(vsi->netdev); | |
12566 | vsi->netdev = NULL; | |
12567 | } | |
12568 | err_netdev: | |
12569 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
12570 | err_vsi: | |
12571 | i40e_vsi_clear(vsi); | |
12572 | err_alloc: | |
12573 | return NULL; | |
12574 | } | |
12575 | ||
12576 | /** | |
12577 | * i40e_veb_get_bw_info - Query VEB BW information | |
12578 | * @veb: the veb to query | |
12579 | * | |
12580 | * Query the Tx scheduler BW configuration data for given VEB | |
12581 | **/ | |
12582 | static int i40e_veb_get_bw_info(struct i40e_veb *veb) | |
12583 | { | |
12584 | struct i40e_aqc_query_switching_comp_ets_config_resp ets_data; | |
12585 | struct i40e_aqc_query_switching_comp_bw_config_resp bw_data; | |
12586 | struct i40e_pf *pf = veb->pf; | |
12587 | struct i40e_hw *hw = &pf->hw; | |
12588 | u32 tc_bw_max; | |
12589 | int ret = 0; | |
12590 | int i; | |
12591 | ||
12592 | ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, | |
12593 | &bw_data, NULL); | |
12594 | if (ret) { | |
12595 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12596 | "query veb bw config failed, err %s aq_err %s\n", |
12597 | i40e_stat_str(&pf->hw, ret), | |
12598 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
12599 | goto out; |
12600 | } | |
12601 | ||
12602 | ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, | |
12603 | &ets_data, NULL); | |
12604 | if (ret) { | |
12605 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12606 | "query veb bw ets config failed, err %s aq_err %s\n", |
12607 | i40e_stat_str(&pf->hw, ret), | |
12608 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
12609 | goto out; |
12610 | } | |
12611 | ||
12612 | veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit); | |
12613 | veb->bw_max_quanta = ets_data.tc_bw_max; | |
12614 | veb->is_abs_credits = bw_data.absolute_credits_enable; | |
23cd1f09 | 12615 | veb->enabled_tc = ets_data.tc_valid_bits; |
41c445ff JB |
12616 | tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) | |
12617 | (le16_to_cpu(bw_data.tc_bw_max[1]) << 16); | |
12618 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
12619 | veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i]; | |
12620 | veb->bw_tc_limit_credits[i] = | |
12621 | le16_to_cpu(bw_data.tc_bw_limits[i]); | |
12622 | veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7); | |
12623 | } | |
12624 | ||
12625 | out: | |
12626 | return ret; | |
12627 | } | |
12628 | ||
12629 | /** | |
12630 | * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF | |
12631 | * @pf: board private structure | |
12632 | * | |
12633 | * On error: returns error code (negative) | |
12634 | * On success: returns vsi index in PF (positive) | |
12635 | **/ | |
12636 | static int i40e_veb_mem_alloc(struct i40e_pf *pf) | |
12637 | { | |
12638 | int ret = -ENOENT; | |
12639 | struct i40e_veb *veb; | |
12640 | int i; | |
12641 | ||
12642 | /* Need to protect the allocation of switch elements at the PF level */ | |
12643 | mutex_lock(&pf->switch_mutex); | |
12644 | ||
12645 | /* VEB list may be fragmented if VEB creation/destruction has | |
12646 | * been happening. We can afford to do a quick scan to look | |
12647 | * for any free slots in the list. | |
12648 | * | |
12649 | * find next empty veb slot, looping back around if necessary | |
12650 | */ | |
12651 | i = 0; | |
12652 | while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL)) | |
12653 | i++; | |
12654 | if (i >= I40E_MAX_VEB) { | |
12655 | ret = -ENOMEM; | |
12656 | goto err_alloc_veb; /* out of VEB slots! */ | |
12657 | } | |
12658 | ||
12659 | veb = kzalloc(sizeof(*veb), GFP_KERNEL); | |
12660 | if (!veb) { | |
12661 | ret = -ENOMEM; | |
12662 | goto err_alloc_veb; | |
12663 | } | |
12664 | veb->pf = pf; | |
12665 | veb->idx = i; | |
12666 | veb->enabled_tc = 1; | |
12667 | ||
12668 | pf->veb[i] = veb; | |
12669 | ret = i; | |
12670 | err_alloc_veb: | |
12671 | mutex_unlock(&pf->switch_mutex); | |
12672 | return ret; | |
12673 | } | |
12674 | ||
12675 | /** | |
12676 | * i40e_switch_branch_release - Delete a branch of the switch tree | |
12677 | * @branch: where to start deleting | |
12678 | * | |
12679 | * This uses recursion to find the tips of the branch to be | |
12680 | * removed, deleting until we get back to and can delete this VEB. | |
12681 | **/ | |
12682 | static void i40e_switch_branch_release(struct i40e_veb *branch) | |
12683 | { | |
12684 | struct i40e_pf *pf = branch->pf; | |
12685 | u16 branch_seid = branch->seid; | |
12686 | u16 veb_idx = branch->idx; | |
12687 | int i; | |
12688 | ||
12689 | /* release any VEBs on this VEB - RECURSION */ | |
12690 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
12691 | if (!pf->veb[i]) | |
12692 | continue; | |
12693 | if (pf->veb[i]->uplink_seid == branch->seid) | |
12694 | i40e_switch_branch_release(pf->veb[i]); | |
12695 | } | |
12696 | ||
12697 | /* Release the VSIs on this VEB, but not the owner VSI. | |
12698 | * | |
12699 | * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing | |
12700 | * the VEB itself, so don't use (*branch) after this loop. | |
12701 | */ | |
505682cd | 12702 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
12703 | if (!pf->vsi[i]) |
12704 | continue; | |
12705 | if (pf->vsi[i]->uplink_seid == branch_seid && | |
12706 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
12707 | i40e_vsi_release(pf->vsi[i]); | |
12708 | } | |
12709 | } | |
12710 | ||
12711 | /* There's one corner case where the VEB might not have been | |
12712 | * removed, so double check it here and remove it if needed. | |
12713 | * This case happens if the veb was created from the debugfs | |
12714 | * commands and no VSIs were added to it. | |
12715 | */ | |
12716 | if (pf->veb[veb_idx]) | |
12717 | i40e_veb_release(pf->veb[veb_idx]); | |
12718 | } | |
12719 | ||
12720 | /** | |
12721 | * i40e_veb_clear - remove veb struct | |
12722 | * @veb: the veb to remove | |
12723 | **/ | |
12724 | static void i40e_veb_clear(struct i40e_veb *veb) | |
12725 | { | |
12726 | if (!veb) | |
12727 | return; | |
12728 | ||
12729 | if (veb->pf) { | |
12730 | struct i40e_pf *pf = veb->pf; | |
12731 | ||
12732 | mutex_lock(&pf->switch_mutex); | |
12733 | if (pf->veb[veb->idx] == veb) | |
12734 | pf->veb[veb->idx] = NULL; | |
12735 | mutex_unlock(&pf->switch_mutex); | |
12736 | } | |
12737 | ||
12738 | kfree(veb); | |
12739 | } | |
12740 | ||
12741 | /** | |
12742 | * i40e_veb_release - Delete a VEB and free its resources | |
12743 | * @veb: the VEB being removed | |
12744 | **/ | |
12745 | void i40e_veb_release(struct i40e_veb *veb) | |
12746 | { | |
12747 | struct i40e_vsi *vsi = NULL; | |
12748 | struct i40e_pf *pf; | |
12749 | int i, n = 0; | |
12750 | ||
12751 | pf = veb->pf; | |
12752 | ||
12753 | /* find the remaining VSI and check for extras */ | |
505682cd | 12754 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
12755 | if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) { |
12756 | n++; | |
12757 | vsi = pf->vsi[i]; | |
12758 | } | |
12759 | } | |
12760 | if (n != 1) { | |
12761 | dev_info(&pf->pdev->dev, | |
12762 | "can't remove VEB %d with %d VSIs left\n", | |
12763 | veb->seid, n); | |
12764 | return; | |
12765 | } | |
12766 | ||
12767 | /* move the remaining VSI to uplink veb */ | |
12768 | vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER; | |
12769 | if (veb->uplink_seid) { | |
12770 | vsi->uplink_seid = veb->uplink_seid; | |
12771 | if (veb->uplink_seid == pf->mac_seid) | |
12772 | vsi->veb_idx = I40E_NO_VEB; | |
12773 | else | |
12774 | vsi->veb_idx = veb->veb_idx; | |
12775 | } else { | |
12776 | /* floating VEB */ | |
12777 | vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
12778 | vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx; | |
12779 | } | |
12780 | ||
12781 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
12782 | i40e_veb_clear(veb); | |
41c445ff JB |
12783 | } |
12784 | ||
12785 | /** | |
12786 | * i40e_add_veb - create the VEB in the switch | |
12787 | * @veb: the VEB to be instantiated | |
12788 | * @vsi: the controlling VSI | |
12789 | **/ | |
12790 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi) | |
12791 | { | |
f1c7e72e | 12792 | struct i40e_pf *pf = veb->pf; |
66fc360a | 12793 | bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED); |
41c445ff JB |
12794 | int ret; |
12795 | ||
f1c7e72e | 12796 | ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid, |
5bc16031 | 12797 | veb->enabled_tc, false, |
66fc360a | 12798 | &veb->seid, enable_stats, NULL); |
5bc16031 MW |
12799 | |
12800 | /* get a VEB from the hardware */ | |
41c445ff | 12801 | if (ret) { |
f1c7e72e SN |
12802 | dev_info(&pf->pdev->dev, |
12803 | "couldn't add VEB, err %s aq_err %s\n", | |
12804 | i40e_stat_str(&pf->hw, ret), | |
12805 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12806 | return -EPERM; |
12807 | } | |
12808 | ||
12809 | /* get statistics counter */ | |
f1c7e72e | 12810 | ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL, |
41c445ff JB |
12811 | &veb->stats_idx, NULL, NULL, NULL); |
12812 | if (ret) { | |
f1c7e72e SN |
12813 | dev_info(&pf->pdev->dev, |
12814 | "couldn't get VEB statistics idx, err %s aq_err %s\n", | |
12815 | i40e_stat_str(&pf->hw, ret), | |
12816 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12817 | return -EPERM; |
12818 | } | |
12819 | ret = i40e_veb_get_bw_info(veb); | |
12820 | if (ret) { | |
f1c7e72e SN |
12821 | dev_info(&pf->pdev->dev, |
12822 | "couldn't get VEB bw info, err %s aq_err %s\n", | |
12823 | i40e_stat_str(&pf->hw, ret), | |
12824 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
12825 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
41c445ff JB |
12826 | return -ENOENT; |
12827 | } | |
12828 | ||
12829 | vsi->uplink_seid = veb->seid; | |
12830 | vsi->veb_idx = veb->idx; | |
12831 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
12832 | ||
12833 | return 0; | |
12834 | } | |
12835 | ||
12836 | /** | |
12837 | * i40e_veb_setup - Set up a VEB | |
12838 | * @pf: board private structure | |
12839 | * @flags: VEB setup flags | |
12840 | * @uplink_seid: the switch element to link to | |
12841 | * @vsi_seid: the initial VSI seid | |
12842 | * @enabled_tc: Enabled TC bit-map | |
12843 | * | |
12844 | * This allocates the sw VEB structure and links it into the switch | |
12845 | * It is possible and legal for this to be a duplicate of an already | |
12846 | * existing VEB. It is also possible for both uplink and vsi seids | |
12847 | * to be zero, in order to create a floating VEB. | |
12848 | * | |
12849 | * Returns pointer to the successfully allocated VEB sw struct on | |
12850 | * success, otherwise returns NULL on failure. | |
12851 | **/ | |
12852 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, | |
12853 | u16 uplink_seid, u16 vsi_seid, | |
12854 | u8 enabled_tc) | |
12855 | { | |
12856 | struct i40e_veb *veb, *uplink_veb = NULL; | |
12857 | int vsi_idx, veb_idx; | |
12858 | int ret; | |
12859 | ||
12860 | /* if one seid is 0, the other must be 0 to create a floating relay */ | |
12861 | if ((uplink_seid == 0 || vsi_seid == 0) && | |
12862 | (uplink_seid + vsi_seid != 0)) { | |
12863 | dev_info(&pf->pdev->dev, | |
12864 | "one, not both seid's are 0: uplink=%d vsi=%d\n", | |
12865 | uplink_seid, vsi_seid); | |
12866 | return NULL; | |
12867 | } | |
12868 | ||
12869 | /* make sure there is such a vsi and uplink */ | |
505682cd | 12870 | for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++) |
41c445ff JB |
12871 | if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid) |
12872 | break; | |
505682cd | 12873 | if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) { |
41c445ff JB |
12874 | dev_info(&pf->pdev->dev, "vsi seid %d not found\n", |
12875 | vsi_seid); | |
12876 | return NULL; | |
12877 | } | |
12878 | ||
12879 | if (uplink_seid && uplink_seid != pf->mac_seid) { | |
12880 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
12881 | if (pf->veb[veb_idx] && | |
12882 | pf->veb[veb_idx]->seid == uplink_seid) { | |
12883 | uplink_veb = pf->veb[veb_idx]; | |
12884 | break; | |
12885 | } | |
12886 | } | |
12887 | if (!uplink_veb) { | |
12888 | dev_info(&pf->pdev->dev, | |
12889 | "uplink seid %d not found\n", uplink_seid); | |
12890 | return NULL; | |
12891 | } | |
12892 | } | |
12893 | ||
12894 | /* get veb sw struct */ | |
12895 | veb_idx = i40e_veb_mem_alloc(pf); | |
12896 | if (veb_idx < 0) | |
12897 | goto err_alloc; | |
12898 | veb = pf->veb[veb_idx]; | |
12899 | veb->flags = flags; | |
12900 | veb->uplink_seid = uplink_seid; | |
12901 | veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB); | |
12902 | veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1); | |
12903 | ||
12904 | /* create the VEB in the switch */ | |
12905 | ret = i40e_add_veb(veb, pf->vsi[vsi_idx]); | |
12906 | if (ret) | |
12907 | goto err_veb; | |
1bb8b935 SN |
12908 | if (vsi_idx == pf->lan_vsi) |
12909 | pf->lan_veb = veb->idx; | |
41c445ff JB |
12910 | |
12911 | return veb; | |
12912 | ||
12913 | err_veb: | |
12914 | i40e_veb_clear(veb); | |
12915 | err_alloc: | |
12916 | return NULL; | |
12917 | } | |
12918 | ||
12919 | /** | |
b40c82e6 | 12920 | * i40e_setup_pf_switch_element - set PF vars based on switch type |
41c445ff JB |
12921 | * @pf: board private structure |
12922 | * @ele: element we are building info from | |
12923 | * @num_reported: total number of elements | |
12924 | * @printconfig: should we print the contents | |
12925 | * | |
12926 | * helper function to assist in extracting a few useful SEID values. | |
12927 | **/ | |
12928 | static void i40e_setup_pf_switch_element(struct i40e_pf *pf, | |
12929 | struct i40e_aqc_switch_config_element_resp *ele, | |
12930 | u16 num_reported, bool printconfig) | |
12931 | { | |
12932 | u16 downlink_seid = le16_to_cpu(ele->downlink_seid); | |
12933 | u16 uplink_seid = le16_to_cpu(ele->uplink_seid); | |
12934 | u8 element_type = ele->element_type; | |
12935 | u16 seid = le16_to_cpu(ele->seid); | |
12936 | ||
12937 | if (printconfig) | |
12938 | dev_info(&pf->pdev->dev, | |
12939 | "type=%d seid=%d uplink=%d downlink=%d\n", | |
12940 | element_type, seid, uplink_seid, downlink_seid); | |
12941 | ||
12942 | switch (element_type) { | |
12943 | case I40E_SWITCH_ELEMENT_TYPE_MAC: | |
12944 | pf->mac_seid = seid; | |
12945 | break; | |
12946 | case I40E_SWITCH_ELEMENT_TYPE_VEB: | |
12947 | /* Main VEB? */ | |
12948 | if (uplink_seid != pf->mac_seid) | |
12949 | break; | |
12950 | if (pf->lan_veb == I40E_NO_VEB) { | |
12951 | int v; | |
12952 | ||
12953 | /* find existing or else empty VEB */ | |
12954 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
12955 | if (pf->veb[v] && (pf->veb[v]->seid == seid)) { | |
12956 | pf->lan_veb = v; | |
12957 | break; | |
12958 | } | |
12959 | } | |
12960 | if (pf->lan_veb == I40E_NO_VEB) { | |
12961 | v = i40e_veb_mem_alloc(pf); | |
12962 | if (v < 0) | |
12963 | break; | |
12964 | pf->lan_veb = v; | |
12965 | } | |
12966 | } | |
12967 | ||
12968 | pf->veb[pf->lan_veb]->seid = seid; | |
12969 | pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid; | |
12970 | pf->veb[pf->lan_veb]->pf = pf; | |
12971 | pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB; | |
12972 | break; | |
12973 | case I40E_SWITCH_ELEMENT_TYPE_VSI: | |
12974 | if (num_reported != 1) | |
12975 | break; | |
12976 | /* This is immediately after a reset so we can assume this is | |
12977 | * the PF's VSI | |
12978 | */ | |
12979 | pf->mac_seid = uplink_seid; | |
12980 | pf->pf_seid = downlink_seid; | |
12981 | pf->main_vsi_seid = seid; | |
12982 | if (printconfig) | |
12983 | dev_info(&pf->pdev->dev, | |
12984 | "pf_seid=%d main_vsi_seid=%d\n", | |
12985 | pf->pf_seid, pf->main_vsi_seid); | |
12986 | break; | |
12987 | case I40E_SWITCH_ELEMENT_TYPE_PF: | |
12988 | case I40E_SWITCH_ELEMENT_TYPE_VF: | |
12989 | case I40E_SWITCH_ELEMENT_TYPE_EMP: | |
12990 | case I40E_SWITCH_ELEMENT_TYPE_BMC: | |
12991 | case I40E_SWITCH_ELEMENT_TYPE_PE: | |
12992 | case I40E_SWITCH_ELEMENT_TYPE_PA: | |
12993 | /* ignore these for now */ | |
12994 | break; | |
12995 | default: | |
12996 | dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n", | |
12997 | element_type, seid); | |
12998 | break; | |
12999 | } | |
13000 | } | |
13001 | ||
13002 | /** | |
13003 | * i40e_fetch_switch_configuration - Get switch config from firmware | |
13004 | * @pf: board private structure | |
13005 | * @printconfig: should we print the contents | |
13006 | * | |
13007 | * Get the current switch configuration from the device and | |
13008 | * extract a few useful SEID values. | |
13009 | **/ | |
13010 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig) | |
13011 | { | |
13012 | struct i40e_aqc_get_switch_config_resp *sw_config; | |
13013 | u16 next_seid = 0; | |
13014 | int ret = 0; | |
13015 | u8 *aq_buf; | |
13016 | int i; | |
13017 | ||
13018 | aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL); | |
13019 | if (!aq_buf) | |
13020 | return -ENOMEM; | |
13021 | ||
13022 | sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; | |
13023 | do { | |
13024 | u16 num_reported, num_total; | |
13025 | ||
13026 | ret = i40e_aq_get_switch_config(&pf->hw, sw_config, | |
13027 | I40E_AQ_LARGE_BUF, | |
13028 | &next_seid, NULL); | |
13029 | if (ret) { | |
13030 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13031 | "get switch config failed err %s aq_err %s\n", |
13032 | i40e_stat_str(&pf->hw, ret), | |
13033 | i40e_aq_str(&pf->hw, | |
13034 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13035 | kfree(aq_buf); |
13036 | return -ENOENT; | |
13037 | } | |
13038 | ||
13039 | num_reported = le16_to_cpu(sw_config->header.num_reported); | |
13040 | num_total = le16_to_cpu(sw_config->header.num_total); | |
13041 | ||
13042 | if (printconfig) | |
13043 | dev_info(&pf->pdev->dev, | |
13044 | "header: %d reported %d total\n", | |
13045 | num_reported, num_total); | |
13046 | ||
41c445ff JB |
13047 | for (i = 0; i < num_reported; i++) { |
13048 | struct i40e_aqc_switch_config_element_resp *ele = | |
13049 | &sw_config->element[i]; | |
13050 | ||
13051 | i40e_setup_pf_switch_element(pf, ele, num_reported, | |
13052 | printconfig); | |
13053 | } | |
13054 | } while (next_seid != 0); | |
13055 | ||
13056 | kfree(aq_buf); | |
13057 | return ret; | |
13058 | } | |
13059 | ||
13060 | /** | |
13061 | * i40e_setup_pf_switch - Setup the HW switch on startup or after reset | |
13062 | * @pf: board private structure | |
bc7d338f | 13063 | * @reinit: if the Main VSI needs to re-initialized. |
41c445ff JB |
13064 | * |
13065 | * Returns 0 on success, negative value on failure | |
13066 | **/ | |
bc7d338f | 13067 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit) |
41c445ff | 13068 | { |
b5569892 | 13069 | u16 flags = 0; |
41c445ff JB |
13070 | int ret; |
13071 | ||
13072 | /* find out what's out there already */ | |
13073 | ret = i40e_fetch_switch_configuration(pf, false); | |
13074 | if (ret) { | |
13075 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13076 | "couldn't fetch switch config, err %s aq_err %s\n", |
13077 | i40e_stat_str(&pf->hw, ret), | |
13078 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13079 | return ret; |
13080 | } | |
13081 | i40e_pf_reset_stats(pf); | |
13082 | ||
b5569892 ASJ |
13083 | /* set the switch config bit for the whole device to |
13084 | * support limited promisc or true promisc | |
13085 | * when user requests promisc. The default is limited | |
13086 | * promisc. | |
13087 | */ | |
13088 | ||
13089 | if ((pf->hw.pf_id == 0) && | |
2f4b411a | 13090 | !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) { |
b5569892 | 13091 | flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; |
2f4b411a AN |
13092 | pf->last_sw_conf_flags = flags; |
13093 | } | |
b5569892 ASJ |
13094 | |
13095 | if (pf->hw.pf_id == 0) { | |
13096 | u16 valid_flags; | |
13097 | ||
13098 | valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
5efe0c6c | 13099 | ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 0, |
b5569892 ASJ |
13100 | NULL); |
13101 | if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { | |
13102 | dev_info(&pf->pdev->dev, | |
13103 | "couldn't set switch config bits, err %s aq_err %s\n", | |
13104 | i40e_stat_str(&pf->hw, ret), | |
13105 | i40e_aq_str(&pf->hw, | |
13106 | pf->hw.aq.asq_last_status)); | |
13107 | /* not a fatal problem, just keep going */ | |
13108 | } | |
2f4b411a | 13109 | pf->last_sw_conf_valid_flags = valid_flags; |
b5569892 ASJ |
13110 | } |
13111 | ||
41c445ff | 13112 | /* first time setup */ |
bc7d338f | 13113 | if (pf->lan_vsi == I40E_NO_VSI || reinit) { |
41c445ff JB |
13114 | struct i40e_vsi *vsi = NULL; |
13115 | u16 uplink_seid; | |
13116 | ||
13117 | /* Set up the PF VSI associated with the PF's main VSI | |
13118 | * that is already in the HW switch | |
13119 | */ | |
13120 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
13121 | uplink_seid = pf->veb[pf->lan_veb]->seid; | |
13122 | else | |
13123 | uplink_seid = pf->mac_seid; | |
bc7d338f ASJ |
13124 | if (pf->lan_vsi == I40E_NO_VSI) |
13125 | vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0); | |
13126 | else if (reinit) | |
13127 | vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
13128 | if (!vsi) { |
13129 | dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n"); | |
aaf66502 | 13130 | i40e_cloud_filter_exit(pf); |
41c445ff JB |
13131 | i40e_fdir_teardown(pf); |
13132 | return -EAGAIN; | |
13133 | } | |
41c445ff JB |
13134 | } else { |
13135 | /* force a reset of TC and queue layout configurations */ | |
13136 | u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
6995b36c | 13137 | |
41c445ff JB |
13138 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; |
13139 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
13140 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
13141 | } | |
13142 | i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]); | |
13143 | ||
cbf61325 ASJ |
13144 | i40e_fdir_sb_setup(pf); |
13145 | ||
41c445ff JB |
13146 | /* Setup static PF queue filter control settings */ |
13147 | ret = i40e_setup_pf_filter_control(pf); | |
13148 | if (ret) { | |
13149 | dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n", | |
13150 | ret); | |
13151 | /* Failure here should not stop continuing other steps */ | |
13152 | } | |
13153 | ||
13154 | /* enable RSS in the HW, even for only one queue, as the stack can use | |
13155 | * the hash | |
13156 | */ | |
13157 | if ((pf->flags & I40E_FLAG_RSS_ENABLED)) | |
043dd650 | 13158 | i40e_pf_config_rss(pf); |
41c445ff JB |
13159 | |
13160 | /* fill in link information and enable LSE reporting */ | |
a34a6711 MW |
13161 | i40e_link_event(pf); |
13162 | ||
d52c20b7 | 13163 | /* Initialize user-specific link properties */ |
41c445ff JB |
13164 | pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info & |
13165 | I40E_AQ_AN_COMPLETED) ? true : false); | |
d52c20b7 | 13166 | |
beb0dff1 JK |
13167 | i40e_ptp_init(pf); |
13168 | ||
1f190d93 AD |
13169 | /* repopulate tunnel port filters */ |
13170 | i40e_sync_udp_filters(pf); | |
13171 | ||
41c445ff JB |
13172 | return ret; |
13173 | } | |
13174 | ||
41c445ff JB |
13175 | /** |
13176 | * i40e_determine_queue_usage - Work out queue distribution | |
13177 | * @pf: board private structure | |
13178 | **/ | |
13179 | static void i40e_determine_queue_usage(struct i40e_pf *pf) | |
13180 | { | |
41c445ff | 13181 | int queues_left; |
e50d5751 | 13182 | int q_max; |
41c445ff JB |
13183 | |
13184 | pf->num_lan_qps = 0; | |
41c445ff JB |
13185 | |
13186 | /* Find the max queues to be put into basic use. We'll always be | |
13187 | * using TC0, whether or not DCB is running, and TC0 will get the | |
13188 | * big RSS set. | |
13189 | */ | |
13190 | queues_left = pf->hw.func_caps.num_tx_qp; | |
13191 | ||
cbf61325 | 13192 | if ((queues_left == 1) || |
9aa7e935 | 13193 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) { |
41c445ff JB |
13194 | /* one qp for PF, no queues for anything else */ |
13195 | queues_left = 0; | |
acd65448 | 13196 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
41c445ff JB |
13197 | |
13198 | /* make sure all the fancies are disabled */ | |
60ea5f83 | 13199 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | |
e3219ce6 | 13200 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 JB |
13201 | I40E_FLAG_FD_SB_ENABLED | |
13202 | I40E_FLAG_FD_ATR_ENABLED | | |
4d9b6043 | 13203 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 13204 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
13205 | I40E_FLAG_SRIOV_ENABLED | |
13206 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 13207 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
9aa7e935 FZ |
13208 | } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED | |
13209 | I40E_FLAG_FD_SB_ENABLED | | |
bbe7d0e0 | 13210 | I40E_FLAG_FD_ATR_ENABLED | |
4d9b6043 | 13211 | I40E_FLAG_DCB_CAPABLE))) { |
9aa7e935 | 13212 | /* one qp for PF */ |
acd65448 | 13213 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
9aa7e935 FZ |
13214 | queues_left -= pf->num_lan_qps; |
13215 | ||
13216 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | | |
e3219ce6 | 13217 | I40E_FLAG_IWARP_ENABLED | |
9aa7e935 FZ |
13218 | I40E_FLAG_FD_SB_ENABLED | |
13219 | I40E_FLAG_FD_ATR_ENABLED | | |
13220 | I40E_FLAG_DCB_ENABLED | | |
13221 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 13222 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
41c445ff | 13223 | } else { |
cbf61325 | 13224 | /* Not enough queues for all TCs */ |
4d9b6043 | 13225 | if ((pf->flags & I40E_FLAG_DCB_CAPABLE) && |
cbf61325 | 13226 | (queues_left < I40E_MAX_TRAFFIC_CLASS)) { |
a036244c DE |
13227 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | |
13228 | I40E_FLAG_DCB_ENABLED); | |
cbf61325 ASJ |
13229 | dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n"); |
13230 | } | |
e50d5751 SN |
13231 | |
13232 | /* limit lan qps to the smaller of qps, cpus or msix */ | |
13233 | q_max = max_t(int, pf->rss_size_max, num_online_cpus()); | |
13234 | q_max = min_t(int, q_max, pf->hw.func_caps.num_tx_qp); | |
13235 | q_max = min_t(int, q_max, pf->hw.func_caps.num_msix_vectors); | |
13236 | pf->num_lan_qps = q_max; | |
9a3bd2f1 | 13237 | |
cbf61325 ASJ |
13238 | queues_left -= pf->num_lan_qps; |
13239 | } | |
13240 | ||
13241 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
13242 | if (queues_left > 1) { | |
13243 | queues_left -= 1; /* save 1 queue for FD */ | |
13244 | } else { | |
13245 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2f4b411a | 13246 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
cbf61325 ASJ |
13247 | dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n"); |
13248 | } | |
41c445ff JB |
13249 | } |
13250 | ||
13251 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
13252 | pf->num_vf_qps && pf->num_req_vfs && queues_left) { | |
cbf61325 ASJ |
13253 | pf->num_req_vfs = min_t(int, pf->num_req_vfs, |
13254 | (queues_left / pf->num_vf_qps)); | |
41c445ff JB |
13255 | queues_left -= (pf->num_req_vfs * pf->num_vf_qps); |
13256 | } | |
13257 | ||
13258 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && | |
13259 | pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) { | |
13260 | pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis, | |
13261 | (queues_left / pf->num_vmdq_qps)); | |
13262 | queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps); | |
13263 | } | |
13264 | ||
f8ff1464 | 13265 | pf->queues_left = queues_left; |
8279e495 NP |
13266 | dev_dbg(&pf->pdev->dev, |
13267 | "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n", | |
13268 | pf->hw.func_caps.num_tx_qp, | |
13269 | !!(pf->flags & I40E_FLAG_FD_SB_ENABLED), | |
acd65448 HZ |
13270 | pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs, |
13271 | pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps, | |
13272 | queues_left); | |
41c445ff JB |
13273 | } |
13274 | ||
13275 | /** | |
13276 | * i40e_setup_pf_filter_control - Setup PF static filter control | |
13277 | * @pf: PF to be setup | |
13278 | * | |
b40c82e6 | 13279 | * i40e_setup_pf_filter_control sets up a PF's initial filter control |
41c445ff JB |
13280 | * settings. If PE/FCoE are enabled then it will also set the per PF |
13281 | * based filter sizes required for them. It also enables Flow director, | |
13282 | * ethertype and macvlan type filter settings for the pf. | |
13283 | * | |
13284 | * Returns 0 on success, negative on failure | |
13285 | **/ | |
13286 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf) | |
13287 | { | |
13288 | struct i40e_filter_control_settings *settings = &pf->filter_settings; | |
13289 | ||
13290 | settings->hash_lut_size = I40E_HASH_LUT_SIZE_128; | |
13291 | ||
13292 | /* Flow Director is enabled */ | |
60ea5f83 | 13293 | if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)) |
41c445ff JB |
13294 | settings->enable_fdir = true; |
13295 | ||
13296 | /* Ethtype and MACVLAN filters enabled for PF */ | |
13297 | settings->enable_ethtype = true; | |
13298 | settings->enable_macvlan = true; | |
13299 | ||
13300 | if (i40e_set_filter_control(&pf->hw, settings)) | |
13301 | return -ENOENT; | |
13302 | ||
13303 | return 0; | |
13304 | } | |
13305 | ||
0c22b3dd | 13306 | #define INFO_STRING_LEN 255 |
7fd89545 | 13307 | #define REMAIN(__x) (INFO_STRING_LEN - (__x)) |
0c22b3dd JB |
13308 | static void i40e_print_features(struct i40e_pf *pf) |
13309 | { | |
13310 | struct i40e_hw *hw = &pf->hw; | |
3b195843 JP |
13311 | char *buf; |
13312 | int i; | |
0c22b3dd | 13313 | |
3b195843 JP |
13314 | buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL); |
13315 | if (!buf) | |
0c22b3dd | 13316 | return; |
0c22b3dd | 13317 | |
3b195843 | 13318 | i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id); |
0c22b3dd | 13319 | #ifdef CONFIG_PCI_IOV |
3b195843 | 13320 | i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs); |
0c22b3dd | 13321 | #endif |
1a557afc | 13322 | i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d", |
7fd89545 | 13323 | pf->hw.func_caps.num_vsis, |
1a557afc | 13324 | pf->vsi[pf->lan_vsi]->num_queue_pairs); |
0c22b3dd | 13325 | if (pf->flags & I40E_FLAG_RSS_ENABLED) |
3b195843 | 13326 | i += snprintf(&buf[i], REMAIN(i), " RSS"); |
0c22b3dd | 13327 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) |
3b195843 | 13328 | i += snprintf(&buf[i], REMAIN(i), " FD_ATR"); |
c6423ff1 | 13329 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
3b195843 JP |
13330 | i += snprintf(&buf[i], REMAIN(i), " FD_SB"); |
13331 | i += snprintf(&buf[i], REMAIN(i), " NTUPLE"); | |
c6423ff1 | 13332 | } |
4d9b6043 | 13333 | if (pf->flags & I40E_FLAG_DCB_CAPABLE) |
3b195843 | 13334 | i += snprintf(&buf[i], REMAIN(i), " DCB"); |
3b195843 | 13335 | i += snprintf(&buf[i], REMAIN(i), " VxLAN"); |
6a899024 | 13336 | i += snprintf(&buf[i], REMAIN(i), " Geneve"); |
0c22b3dd | 13337 | if (pf->flags & I40E_FLAG_PTP) |
3b195843 | 13338 | i += snprintf(&buf[i], REMAIN(i), " PTP"); |
6dec1017 | 13339 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
3b195843 | 13340 | i += snprintf(&buf[i], REMAIN(i), " VEB"); |
6dec1017 | 13341 | else |
3b195843 | 13342 | i += snprintf(&buf[i], REMAIN(i), " VEPA"); |
0c22b3dd | 13343 | |
3b195843 JP |
13344 | dev_info(&pf->pdev->dev, "%s\n", buf); |
13345 | kfree(buf); | |
7fd89545 | 13346 | WARN_ON(i > INFO_STRING_LEN); |
0c22b3dd JB |
13347 | } |
13348 | ||
b499ffb0 SV |
13349 | /** |
13350 | * i40e_get_platform_mac_addr - get platform-specific MAC address | |
b499ffb0 SV |
13351 | * @pdev: PCI device information struct |
13352 | * @pf: board private structure | |
13353 | * | |
41c4c2b5 JK |
13354 | * Look up the MAC address for the device. First we'll try |
13355 | * eth_platform_get_mac_address, which will check Open Firmware, or arch | |
13356 | * specific fallback. Otherwise, we'll default to the stored value in | |
13357 | * firmware. | |
b499ffb0 SV |
13358 | **/ |
13359 | static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf) | |
13360 | { | |
41c4c2b5 JK |
13361 | if (eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr)) |
13362 | i40e_get_mac_addr(&pf->hw, pf->hw.mac.addr); | |
b499ffb0 SV |
13363 | } |
13364 | ||
41c445ff JB |
13365 | /** |
13366 | * i40e_probe - Device initialization routine | |
13367 | * @pdev: PCI device information struct | |
13368 | * @ent: entry in i40e_pci_tbl | |
13369 | * | |
b40c82e6 JK |
13370 | * i40e_probe initializes a PF identified by a pci_dev structure. |
13371 | * The OS initialization, configuring of the PF private structure, | |
41c445ff JB |
13372 | * and a hardware reset occur. |
13373 | * | |
13374 | * Returns 0 on success, negative on failure | |
13375 | **/ | |
13376 | static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
13377 | { | |
e827845c | 13378 | struct i40e_aq_get_phy_abilities_resp abilities; |
41c445ff JB |
13379 | struct i40e_pf *pf; |
13380 | struct i40e_hw *hw; | |
93cd765b | 13381 | static u16 pfs_found; |
1d5109d1 | 13382 | u16 wol_nvm_bits; |
d4dfb81a | 13383 | u16 link_status; |
6f66a484 | 13384 | int err; |
4f2f017c | 13385 | u32 val; |
8a9eb7d3 | 13386 | u32 i; |
58fc3267 | 13387 | u8 set_fc_aq_fail; |
41c445ff JB |
13388 | |
13389 | err = pci_enable_device_mem(pdev); | |
13390 | if (err) | |
13391 | return err; | |
13392 | ||
13393 | /* set up for high or low dma */ | |
6494294f | 13394 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
6494294f | 13395 | if (err) { |
e3e3bfdd JS |
13396 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
13397 | if (err) { | |
13398 | dev_err(&pdev->dev, | |
13399 | "DMA configuration failed: 0x%x\n", err); | |
13400 | goto err_dma; | |
13401 | } | |
41c445ff JB |
13402 | } |
13403 | ||
13404 | /* set up pci connections */ | |
56d766d6 | 13405 | err = pci_request_mem_regions(pdev, i40e_driver_name); |
41c445ff JB |
13406 | if (err) { |
13407 | dev_info(&pdev->dev, | |
13408 | "pci_request_selected_regions failed %d\n", err); | |
13409 | goto err_pci_reg; | |
13410 | } | |
13411 | ||
13412 | pci_enable_pcie_error_reporting(pdev); | |
13413 | pci_set_master(pdev); | |
13414 | ||
13415 | /* Now that we have a PCI connection, we need to do the | |
13416 | * low level device setup. This is primarily setting up | |
13417 | * the Admin Queue structures and then querying for the | |
13418 | * device's current profile information. | |
13419 | */ | |
13420 | pf = kzalloc(sizeof(*pf), GFP_KERNEL); | |
13421 | if (!pf) { | |
13422 | err = -ENOMEM; | |
13423 | goto err_pf_alloc; | |
13424 | } | |
13425 | pf->next_vsi = 0; | |
13426 | pf->pdev = pdev; | |
9e6c9c0f | 13427 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
13428 | |
13429 | hw = &pf->hw; | |
13430 | hw->back = pf; | |
232f4706 | 13431 | |
2ac8b675 SN |
13432 | pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0), |
13433 | I40E_MAX_CSR_SPACE); | |
232f4706 | 13434 | |
2ac8b675 | 13435 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len); |
41c445ff JB |
13436 | if (!hw->hw_addr) { |
13437 | err = -EIO; | |
13438 | dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n", | |
13439 | (unsigned int)pci_resource_start(pdev, 0), | |
2ac8b675 | 13440 | pf->ioremap_len, err); |
41c445ff JB |
13441 | goto err_ioremap; |
13442 | } | |
13443 | hw->vendor_id = pdev->vendor; | |
13444 | hw->device_id = pdev->device; | |
13445 | pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | |
13446 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
13447 | hw->subsystem_device_id = pdev->subsystem_device; | |
13448 | hw->bus.device = PCI_SLOT(pdev->devfn); | |
13449 | hw->bus.func = PCI_FUNC(pdev->devfn); | |
b3f028fc | 13450 | hw->bus.bus_id = pdev->bus->number; |
93cd765b | 13451 | pf->instance = pfs_found; |
41c445ff | 13452 | |
ab243ec9 SP |
13453 | /* Select something other than the 802.1ad ethertype for the |
13454 | * switch to use internally and drop on ingress. | |
13455 | */ | |
13456 | hw->switch_tag = 0xffff; | |
13457 | hw->first_tag = ETH_P_8021AD; | |
13458 | hw->second_tag = ETH_P_8021Q; | |
13459 | ||
0e588de1 JK |
13460 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); |
13461 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
13462 | ||
de03d2b0 SN |
13463 | /* set up the locks for the AQ, do this only once in probe |
13464 | * and destroy them only once in remove | |
13465 | */ | |
13466 | mutex_init(&hw->aq.asq_mutex); | |
13467 | mutex_init(&hw->aq.arq_mutex); | |
13468 | ||
5d4ca23e AD |
13469 | pf->msg_enable = netif_msg_init(debug, |
13470 | NETIF_MSG_DRV | | |
13471 | NETIF_MSG_PROBE | | |
13472 | NETIF_MSG_LINK); | |
13473 | if (debug < -1) | |
13474 | pf->hw.debug_mask = debug; | |
5b5faa43 | 13475 | |
7134f9ce JB |
13476 | /* do a special CORER for clearing PXE mode once at init */ |
13477 | if (hw->revision_id == 0 && | |
13478 | (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) { | |
13479 | wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK); | |
13480 | i40e_flush(hw); | |
13481 | msleep(200); | |
13482 | pf->corer_count++; | |
13483 | ||
13484 | i40e_clear_pxe_mode(hw); | |
13485 | } | |
13486 | ||
41c445ff | 13487 | /* Reset here to make sure all is clean and to define PF 'n' */ |
838d41d9 | 13488 | i40e_clear_hw(hw); |
41c445ff JB |
13489 | err = i40e_pf_reset(hw); |
13490 | if (err) { | |
13491 | dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err); | |
13492 | goto err_pf_reset; | |
13493 | } | |
13494 | pf->pfr_count++; | |
13495 | ||
13496 | hw->aq.num_arq_entries = I40E_AQ_LEN; | |
13497 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
13498 | hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
13499 | hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
13500 | pf->adminq_work_limit = I40E_AQ_WORK_LIMIT; | |
b2008cbf | 13501 | |
b294ac70 | 13502 | snprintf(pf->int_name, sizeof(pf->int_name) - 1, |
b2008cbf CW |
13503 | "%s-%s:misc", |
13504 | dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev)); | |
41c445ff JB |
13505 | |
13506 | err = i40e_init_shared_code(hw); | |
13507 | if (err) { | |
b2a75c58 ASJ |
13508 | dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", |
13509 | err); | |
41c445ff JB |
13510 | goto err_pf_reset; |
13511 | } | |
13512 | ||
d52c20b7 JB |
13513 | /* set up a default setting for link flow control */ |
13514 | pf->hw.fc.requested_mode = I40E_FC_NONE; | |
13515 | ||
41c445ff | 13516 | err = i40e_init_adminq(hw); |
2b2426a7 CW |
13517 | if (err) { |
13518 | if (err == I40E_ERR_FIRMWARE_API_VERSION) | |
13519 | dev_info(&pdev->dev, | |
13520 | "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n"); | |
13521 | else | |
13522 | dev_info(&pdev->dev, | |
13523 | "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n"); | |
13524 | ||
13525 | goto err_pf_reset; | |
13526 | } | |
5bbb2e20 | 13527 | i40e_get_oem_version(hw); |
f0b44440 | 13528 | |
6dec1017 SN |
13529 | /* provide nvm, fw, api versions */ |
13530 | dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n", | |
13531 | hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build, | |
13532 | hw->aq.api_maj_ver, hw->aq.api_min_ver, | |
13533 | i40e_nvm_version_str(hw)); | |
f0b44440 | 13534 | |
7aa67613 | 13535 | if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && |
22b96551 | 13536 | hw->aq.api_min_ver > I40E_FW_MINOR_VERSION(hw)) |
278b6f62 | 13537 | dev_info(&pdev->dev, |
7aa67613 | 13538 | "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n"); |
e04ea002 | 13539 | else if (hw->aq.api_maj_ver == 1 && hw->aq.api_min_ver < 4) |
278b6f62 | 13540 | dev_info(&pdev->dev, |
7aa67613 | 13541 | "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n"); |
278b6f62 | 13542 | |
4eb3f768 SN |
13543 | i40e_verify_eeprom(pf); |
13544 | ||
2c5fe33b JB |
13545 | /* Rev 0 hardware was never productized */ |
13546 | if (hw->revision_id < 1) | |
13547 | dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); | |
13548 | ||
6ff4ef86 | 13549 | i40e_clear_pxe_mode(hw); |
2f4b411a | 13550 | err = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities); |
41c445ff JB |
13551 | if (err) |
13552 | goto err_adminq_setup; | |
13553 | ||
13554 | err = i40e_sw_init(pf); | |
13555 | if (err) { | |
13556 | dev_info(&pdev->dev, "sw_init failed: %d\n", err); | |
13557 | goto err_sw_init; | |
13558 | } | |
13559 | ||
13560 | err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, | |
c76cb6ed | 13561 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
13562 | if (err) { |
13563 | dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err); | |
13564 | goto err_init_lan_hmc; | |
13565 | } | |
13566 | ||
13567 | err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
13568 | if (err) { | |
13569 | dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err); | |
13570 | err = -ENOENT; | |
13571 | goto err_configure_lan_hmc; | |
13572 | } | |
13573 | ||
b686ece5 NP |
13574 | /* Disable LLDP for NICs that have firmware versions lower than v4.3. |
13575 | * Ignore error return codes because if it was already disabled via | |
13576 | * hardware settings this will fail | |
13577 | */ | |
d36e41dc | 13578 | if (pf->hw_features & I40E_HW_STOP_FW_LLDP) { |
b686ece5 NP |
13579 | dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n"); |
13580 | i40e_aq_stop_lldp(hw, true, NULL); | |
13581 | } | |
13582 | ||
b499ffb0 SV |
13583 | /* allow a platform config to override the HW addr */ |
13584 | i40e_get_platform_mac_addr(pdev, pf); | |
41c4c2b5 | 13585 | |
f62b5060 | 13586 | if (!is_valid_ether_addr(hw->mac.addr)) { |
41c445ff JB |
13587 | dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr); |
13588 | err = -EIO; | |
13589 | goto err_mac_addr; | |
13590 | } | |
13591 | dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr); | |
9a173901 | 13592 | ether_addr_copy(hw->mac.perm_addr, hw->mac.addr); |
1f224ad2 NP |
13593 | i40e_get_port_mac_addr(hw, hw->mac.port_addr); |
13594 | if (is_valid_ether_addr(hw->mac.port_addr)) | |
d36e41dc | 13595 | pf->hw_features |= I40E_HW_PORT_ID_VALID; |
41c445ff JB |
13596 | |
13597 | pci_set_drvdata(pdev, pf); | |
13598 | pci_save_state(pdev); | |
4e3b35b0 NP |
13599 | #ifdef CONFIG_I40E_DCB |
13600 | err = i40e_init_pf_dcb(pf); | |
13601 | if (err) { | |
aebfc816 | 13602 | dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err); |
c17ef430 | 13603 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED); |
014269ff | 13604 | /* Continue without DCB enabled */ |
4e3b35b0 NP |
13605 | } |
13606 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
13607 | |
13608 | /* set up periodic task facility */ | |
26566eae | 13609 | timer_setup(&pf->service_timer, i40e_service_timer, 0); |
41c445ff JB |
13610 | pf->service_timer_period = HZ; |
13611 | ||
13612 | INIT_WORK(&pf->service_task, i40e_service_task); | |
0da36b97 | 13613 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff | 13614 | |
1d5109d1 SN |
13615 | /* NVM bit on means WoL disabled for the port */ |
13616 | i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits); | |
75f5cea9 | 13617 | if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) |
1d5109d1 SN |
13618 | pf->wol_en = false; |
13619 | else | |
13620 | pf->wol_en = true; | |
8e2773ae SN |
13621 | device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en); |
13622 | ||
41c445ff JB |
13623 | /* set up the main switch operations */ |
13624 | i40e_determine_queue_usage(pf); | |
c1147280 JB |
13625 | err = i40e_init_interrupt_scheme(pf); |
13626 | if (err) | |
13627 | goto err_switch_setup; | |
41c445ff | 13628 | |
505682cd MW |
13629 | /* The number of VSIs reported by the FW is the minimum guaranteed |
13630 | * to us; HW supports far more and we share the remaining pool with | |
13631 | * the other PFs. We allocate space for more than the guarantee with | |
13632 | * the understanding that we might not get them all later. | |
41c445ff | 13633 | */ |
505682cd MW |
13634 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) |
13635 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
13636 | else | |
13637 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
13638 | ||
13639 | /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */ | |
d17038d6 JB |
13640 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), |
13641 | GFP_KERNEL); | |
ed87ac09 WY |
13642 | if (!pf->vsi) { |
13643 | err = -ENOMEM; | |
41c445ff | 13644 | goto err_switch_setup; |
ed87ac09 | 13645 | } |
41c445ff | 13646 | |
fa11cb3d ASJ |
13647 | #ifdef CONFIG_PCI_IOV |
13648 | /* prep for VF support */ | |
13649 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
13650 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
0da36b97 | 13651 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
fa11cb3d ASJ |
13652 | if (pci_num_vf(pdev)) |
13653 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
13654 | } | |
13655 | #endif | |
bc7d338f | 13656 | err = i40e_setup_pf_switch(pf, false); |
41c445ff JB |
13657 | if (err) { |
13658 | dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err); | |
13659 | goto err_vsis; | |
13660 | } | |
8f88b303 | 13661 | INIT_LIST_HEAD(&pf->vsi[pf->lan_vsi]->ch_list); |
58fc3267 HZ |
13662 | |
13663 | /* Make sure flow control is set according to current settings */ | |
13664 | err = i40e_set_fc(hw, &set_fc_aq_fail, true); | |
13665 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET) | |
13666 | dev_dbg(&pf->pdev->dev, | |
13667 | "Set fc with err %s aq_err %s on get_phy_cap\n", | |
13668 | i40e_stat_str(hw, err), | |
13669 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
13670 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET) | |
13671 | dev_dbg(&pf->pdev->dev, | |
13672 | "Set fc with err %s aq_err %s on set_phy_config\n", | |
13673 | i40e_stat_str(hw, err), | |
13674 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
13675 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE) | |
13676 | dev_dbg(&pf->pdev->dev, | |
13677 | "Set fc with err %s aq_err %s on get_link_info\n", | |
13678 | i40e_stat_str(hw, err), | |
13679 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
13680 | ||
8a9eb7d3 | 13681 | /* if FDIR VSI was set up, start it now */ |
505682cd | 13682 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
8a9eb7d3 SN |
13683 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
13684 | i40e_vsi_open(pf->vsi[i]); | |
13685 | break; | |
13686 | } | |
13687 | } | |
41c445ff | 13688 | |
2f0aff41 SN |
13689 | /* The driver only wants link up/down and module qualification |
13690 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
13691 | */ |
13692 | err = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 13693 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 13694 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 13695 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 13696 | if (err) |
f1c7e72e SN |
13697 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
13698 | i40e_stat_str(&pf->hw, err), | |
13699 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 13700 | |
4f2f017c ASJ |
13701 | /* Reconfigure hardware for allowing smaller MSS in the case |
13702 | * of TSO, so that we avoid the MDD being fired and causing | |
13703 | * a reset in the case of small MSS+TSO. | |
13704 | */ | |
13705 | val = rd32(hw, I40E_REG_MSS); | |
13706 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
13707 | val &= ~I40E_REG_MSS_MIN_MASK; | |
13708 | val |= I40E_64BYTE_MSS; | |
13709 | wr32(hw, I40E_REG_MSS, val); | |
13710 | } | |
13711 | ||
d36e41dc | 13712 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
13713 | msleep(75); |
13714 | err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
13715 | if (err) | |
f1c7e72e SN |
13716 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
13717 | i40e_stat_str(&pf->hw, err), | |
13718 | i40e_aq_str(&pf->hw, | |
13719 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 13720 | } |
41c445ff JB |
13721 | /* The main driver is (mostly) up and happy. We need to set this state |
13722 | * before setting up the misc vector or we get a race and the vector | |
13723 | * ends up disabled forever. | |
13724 | */ | |
9e6c9c0f | 13725 | clear_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
13726 | |
13727 | /* In case of MSIX we are going to setup the misc vector right here | |
13728 | * to handle admin queue events etc. In case of legacy and MSI | |
13729 | * the misc functionality and queue processing is combined in | |
13730 | * the same vector and that gets setup at open. | |
13731 | */ | |
13732 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
13733 | err = i40e_setup_misc_vector(pf); | |
13734 | if (err) { | |
13735 | dev_info(&pdev->dev, | |
13736 | "setup of misc vector failed: %d\n", err); | |
13737 | goto err_vsis; | |
13738 | } | |
13739 | } | |
13740 | ||
df805f62 | 13741 | #ifdef CONFIG_PCI_IOV |
41c445ff JB |
13742 | /* prep for VF support */ |
13743 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
4eb3f768 | 13744 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && |
0da36b97 | 13745 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
41c445ff JB |
13746 | /* disable link interrupts for VFs */ |
13747 | val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); | |
13748 | val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; | |
13749 | wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); | |
13750 | i40e_flush(hw); | |
4aeec010 MW |
13751 | |
13752 | if (pci_num_vf(pdev)) { | |
13753 | dev_info(&pdev->dev, | |
13754 | "Active VFs found, allocating resources.\n"); | |
13755 | err = i40e_alloc_vfs(pf, pci_num_vf(pdev)); | |
13756 | if (err) | |
13757 | dev_info(&pdev->dev, | |
13758 | "Error %d allocating resources for existing VFs\n", | |
13759 | err); | |
13760 | } | |
41c445ff | 13761 | } |
df805f62 | 13762 | #endif /* CONFIG_PCI_IOV */ |
41c445ff | 13763 | |
e3219ce6 ASJ |
13764 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
13765 | pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile, | |
13766 | pf->num_iwarp_msix, | |
13767 | I40E_IWARP_IRQ_PILE_ID); | |
13768 | if (pf->iwarp_base_vector < 0) { | |
13769 | dev_info(&pdev->dev, | |
13770 | "failed to get tracking for %d vectors for IWARP err=%d\n", | |
13771 | pf->num_iwarp_msix, pf->iwarp_base_vector); | |
13772 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
13773 | } | |
13774 | } | |
93cd765b | 13775 | |
41c445ff JB |
13776 | i40e_dbg_pf_init(pf); |
13777 | ||
13778 | /* tell the firmware that we're starting */ | |
44033fac | 13779 | i40e_send_version(pf); |
41c445ff JB |
13780 | |
13781 | /* since everything's happy, start the service_task timer */ | |
13782 | mod_timer(&pf->service_timer, | |
13783 | round_jiffies(jiffies + pf->service_timer_period)); | |
13784 | ||
e3219ce6 | 13785 | /* add this PF to client device list and launch a client service task */ |
004eb614 MW |
13786 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
13787 | err = i40e_lan_add_device(pf); | |
13788 | if (err) | |
13789 | dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n", | |
13790 | err); | |
13791 | } | |
e3219ce6 | 13792 | |
3fced535 ASJ |
13793 | #define PCI_SPEED_SIZE 8 |
13794 | #define PCI_WIDTH_SIZE 8 | |
13795 | /* Devices on the IOSF bus do not have this information | |
13796 | * and will report PCI Gen 1 x 1 by default so don't bother | |
13797 | * checking them. | |
13798 | */ | |
d36e41dc | 13799 | if (!(pf->hw_features & I40E_HW_NO_PCI_LINK_CHECK)) { |
3fced535 ASJ |
13800 | char speed[PCI_SPEED_SIZE] = "Unknown"; |
13801 | char width[PCI_WIDTH_SIZE] = "Unknown"; | |
13802 | ||
13803 | /* Get the negotiated link width and speed from PCI config | |
13804 | * space | |
13805 | */ | |
13806 | pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, | |
13807 | &link_status); | |
13808 | ||
13809 | i40e_set_pci_config_data(hw, link_status); | |
13810 | ||
13811 | switch (hw->bus.speed) { | |
13812 | case i40e_bus_speed_8000: | |
13813 | strncpy(speed, "8.0", PCI_SPEED_SIZE); break; | |
13814 | case i40e_bus_speed_5000: | |
13815 | strncpy(speed, "5.0", PCI_SPEED_SIZE); break; | |
13816 | case i40e_bus_speed_2500: | |
13817 | strncpy(speed, "2.5", PCI_SPEED_SIZE); break; | |
13818 | default: | |
13819 | break; | |
13820 | } | |
13821 | switch (hw->bus.width) { | |
13822 | case i40e_bus_width_pcie_x8: | |
13823 | strncpy(width, "8", PCI_WIDTH_SIZE); break; | |
13824 | case i40e_bus_width_pcie_x4: | |
13825 | strncpy(width, "4", PCI_WIDTH_SIZE); break; | |
13826 | case i40e_bus_width_pcie_x2: | |
13827 | strncpy(width, "2", PCI_WIDTH_SIZE); break; | |
13828 | case i40e_bus_width_pcie_x1: | |
13829 | strncpy(width, "1", PCI_WIDTH_SIZE); break; | |
13830 | default: | |
13831 | break; | |
13832 | } | |
13833 | ||
13834 | dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n", | |
13835 | speed, width); | |
13836 | ||
13837 | if (hw->bus.width < i40e_bus_width_pcie_x8 || | |
13838 | hw->bus.speed < i40e_bus_speed_8000) { | |
13839 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n"); | |
13840 | dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n"); | |
13841 | } | |
d4dfb81a CS |
13842 | } |
13843 | ||
e827845c CS |
13844 | /* get the requested speeds from the fw */ |
13845 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); | |
13846 | if (err) | |
8279e495 NP |
13847 | dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n", |
13848 | i40e_stat_str(&pf->hw, err), | |
13849 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
e827845c CS |
13850 | pf->hw.phy.link_info.requested_speeds = abilities.link_speed; |
13851 | ||
fc72dbce CS |
13852 | /* get the supported phy types from the fw */ |
13853 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); | |
13854 | if (err) | |
13855 | dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n", | |
13856 | i40e_stat_str(&pf->hw, err), | |
13857 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
fc72dbce | 13858 | |
e7358f54 ASJ |
13859 | /* Add a filter to drop all Flow control frames from any VSI from being |
13860 | * transmitted. By doing so we stop a malicious VF from sending out | |
13861 | * PAUSE or PFC frames and potentially controlling traffic for other | |
13862 | * PF/VF VSIs. | |
13863 | * The FW can still send Flow control frames if enabled. | |
13864 | */ | |
13865 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
13866 | pf->main_vsi_seid); | |
13867 | ||
31b606d0 | 13868 | if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) || |
4f9b4307 | 13869 | (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4)) |
d36e41dc | 13870 | pf->hw_features |= I40E_HW_PHY_CONTROLS_LEDS; |
4ad9f4f9 | 13871 | if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722) |
d36e41dc | 13872 | pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER; |
0c22b3dd JB |
13873 | /* print a string summarizing features */ |
13874 | i40e_print_features(pf); | |
13875 | ||
41c445ff JB |
13876 | return 0; |
13877 | ||
13878 | /* Unwind what we've done if something failed in the setup */ | |
13879 | err_vsis: | |
9e6c9c0f | 13880 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
13881 | i40e_clear_interrupt_scheme(pf); |
13882 | kfree(pf->vsi); | |
04b03013 SN |
13883 | err_switch_setup: |
13884 | i40e_reset_interrupt_capability(pf); | |
41c445ff JB |
13885 | del_timer_sync(&pf->service_timer); |
13886 | err_mac_addr: | |
13887 | err_configure_lan_hmc: | |
13888 | (void)i40e_shutdown_lan_hmc(hw); | |
13889 | err_init_lan_hmc: | |
13890 | kfree(pf->qp_pile); | |
41c445ff JB |
13891 | err_sw_init: |
13892 | err_adminq_setup: | |
41c445ff JB |
13893 | err_pf_reset: |
13894 | iounmap(hw->hw_addr); | |
13895 | err_ioremap: | |
13896 | kfree(pf); | |
13897 | err_pf_alloc: | |
13898 | pci_disable_pcie_error_reporting(pdev); | |
56d766d6 | 13899 | pci_release_mem_regions(pdev); |
41c445ff JB |
13900 | err_pci_reg: |
13901 | err_dma: | |
13902 | pci_disable_device(pdev); | |
13903 | return err; | |
13904 | } | |
13905 | ||
13906 | /** | |
13907 | * i40e_remove - Device removal routine | |
13908 | * @pdev: PCI device information struct | |
13909 | * | |
13910 | * i40e_remove is called by the PCI subsystem to alert the driver | |
13911 | * that is should release a PCI device. This could be caused by a | |
13912 | * Hot-Plug event, or because the driver is going to be removed from | |
13913 | * memory. | |
13914 | **/ | |
13915 | static void i40e_remove(struct pci_dev *pdev) | |
13916 | { | |
13917 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
bcab2db9 | 13918 | struct i40e_hw *hw = &pf->hw; |
41c445ff | 13919 | i40e_status ret_code; |
41c445ff JB |
13920 | int i; |
13921 | ||
13922 | i40e_dbg_pf_exit(pf); | |
13923 | ||
beb0dff1 JK |
13924 | i40e_ptp_stop(pf); |
13925 | ||
bcab2db9 | 13926 | /* Disable RSS in hw */ |
272cdaf2 SN |
13927 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); |
13928 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); | |
bcab2db9 | 13929 | |
41c445ff | 13930 | /* no more scheduling of any task */ |
0da36b97 | 13931 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 13932 | set_bit(__I40E_DOWN, pf->state); |
26566eae | 13933 | if (pf->service_timer.function) |
c99abb4c SN |
13934 | del_timer_sync(&pf->service_timer); |
13935 | if (pf->service_task.func) | |
13936 | cancel_work_sync(&pf->service_task); | |
41c445ff | 13937 | |
921c467c MW |
13938 | /* Client close must be called explicitly here because the timer |
13939 | * has been stopped. | |
13940 | */ | |
13941 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
13942 | ||
eb2d80bc MW |
13943 | if (pf->flags & I40E_FLAG_SRIOV_ENABLED) { |
13944 | i40e_free_vfs(pf); | |
13945 | pf->flags &= ~I40E_FLAG_SRIOV_ENABLED; | |
13946 | } | |
13947 | ||
41c445ff JB |
13948 | i40e_fdir_teardown(pf); |
13949 | ||
13950 | /* If there is a switch structure or any orphans, remove them. | |
13951 | * This will leave only the PF's VSI remaining. | |
13952 | */ | |
13953 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
13954 | if (!pf->veb[i]) | |
13955 | continue; | |
13956 | ||
13957 | if (pf->veb[i]->uplink_seid == pf->mac_seid || | |
13958 | pf->veb[i]->uplink_seid == 0) | |
13959 | i40e_switch_branch_release(pf->veb[i]); | |
13960 | } | |
13961 | ||
13962 | /* Now we can shutdown the PF's VSI, just before we kill | |
13963 | * adminq and hmc. | |
13964 | */ | |
13965 | if (pf->vsi[pf->lan_vsi]) | |
13966 | i40e_vsi_release(pf->vsi[pf->lan_vsi]); | |
13967 | ||
aaf66502 AN |
13968 | i40e_cloud_filter_exit(pf); |
13969 | ||
e3219ce6 | 13970 | /* remove attached clients */ |
004eb614 MW |
13971 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
13972 | ret_code = i40e_lan_del_device(pf); | |
13973 | if (ret_code) | |
13974 | dev_warn(&pdev->dev, "Failed to delete client device: %d\n", | |
13975 | ret_code); | |
e3219ce6 ASJ |
13976 | } |
13977 | ||
41c445ff | 13978 | /* shutdown and destroy the HMC */ |
f734dfff JB |
13979 | if (hw->hmc.hmc_obj) { |
13980 | ret_code = i40e_shutdown_lan_hmc(hw); | |
60442dea SN |
13981 | if (ret_code) |
13982 | dev_warn(&pdev->dev, | |
13983 | "Failed to destroy the HMC resources: %d\n", | |
13984 | ret_code); | |
13985 | } | |
41c445ff JB |
13986 | |
13987 | /* shutdown the adminq */ | |
ac9c5c6d | 13988 | i40e_shutdown_adminq(hw); |
41c445ff | 13989 | |
8ddb3326 JB |
13990 | /* destroy the locks only once, here */ |
13991 | mutex_destroy(&hw->aq.arq_mutex); | |
13992 | mutex_destroy(&hw->aq.asq_mutex); | |
13993 | ||
41c445ff JB |
13994 | /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */ |
13995 | i40e_clear_interrupt_scheme(pf); | |
505682cd | 13996 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
13997 | if (pf->vsi[i]) { |
13998 | i40e_vsi_clear_rings(pf->vsi[i]); | |
13999 | i40e_vsi_clear(pf->vsi[i]); | |
14000 | pf->vsi[i] = NULL; | |
14001 | } | |
14002 | } | |
14003 | ||
14004 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
14005 | kfree(pf->veb[i]); | |
14006 | pf->veb[i] = NULL; | |
14007 | } | |
14008 | ||
14009 | kfree(pf->qp_pile); | |
41c445ff JB |
14010 | kfree(pf->vsi); |
14011 | ||
f734dfff | 14012 | iounmap(hw->hw_addr); |
41c445ff | 14013 | kfree(pf); |
56d766d6 | 14014 | pci_release_mem_regions(pdev); |
41c445ff JB |
14015 | |
14016 | pci_disable_pcie_error_reporting(pdev); | |
14017 | pci_disable_device(pdev); | |
14018 | } | |
14019 | ||
14020 | /** | |
14021 | * i40e_pci_error_detected - warning that something funky happened in PCI land | |
14022 | * @pdev: PCI device information struct | |
14023 | * | |
14024 | * Called to warn that something happened and the error handling steps | |
14025 | * are in progress. Allows the driver to quiesce things, be ready for | |
14026 | * remediation. | |
14027 | **/ | |
14028 | static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev, | |
14029 | enum pci_channel_state error) | |
14030 | { | |
14031 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14032 | ||
14033 | dev_info(&pdev->dev, "%s: error %d\n", __func__, error); | |
14034 | ||
edfc23ee GP |
14035 | if (!pf) { |
14036 | dev_info(&pdev->dev, | |
14037 | "Cannot recover - error happened during device probe\n"); | |
14038 | return PCI_ERS_RESULT_DISCONNECT; | |
14039 | } | |
14040 | ||
41c445ff | 14041 | /* shutdown all operations */ |
dfc4ff64 JK |
14042 | if (!test_bit(__I40E_SUSPENDED, pf->state)) |
14043 | i40e_prep_for_reset(pf, false); | |
41c445ff JB |
14044 | |
14045 | /* Request a slot reset */ | |
14046 | return PCI_ERS_RESULT_NEED_RESET; | |
14047 | } | |
14048 | ||
14049 | /** | |
14050 | * i40e_pci_error_slot_reset - a PCI slot reset just happened | |
14051 | * @pdev: PCI device information struct | |
14052 | * | |
14053 | * Called to find if the driver can work with the device now that | |
14054 | * the pci slot has been reset. If a basic connection seems good | |
14055 | * (registers are readable and have sane content) then return a | |
14056 | * happy little PCI_ERS_RESULT_xxx. | |
14057 | **/ | |
14058 | static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev) | |
14059 | { | |
14060 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14061 | pci_ers_result_t result; | |
14062 | int err; | |
14063 | u32 reg; | |
14064 | ||
fb43201f | 14065 | dev_dbg(&pdev->dev, "%s\n", __func__); |
41c445ff JB |
14066 | if (pci_enable_device_mem(pdev)) { |
14067 | dev_info(&pdev->dev, | |
14068 | "Cannot re-enable PCI device after reset.\n"); | |
14069 | result = PCI_ERS_RESULT_DISCONNECT; | |
14070 | } else { | |
14071 | pci_set_master(pdev); | |
14072 | pci_restore_state(pdev); | |
14073 | pci_save_state(pdev); | |
14074 | pci_wake_from_d3(pdev, false); | |
14075 | ||
14076 | reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); | |
14077 | if (reg == 0) | |
14078 | result = PCI_ERS_RESULT_RECOVERED; | |
14079 | else | |
14080 | result = PCI_ERS_RESULT_DISCONNECT; | |
14081 | } | |
14082 | ||
14083 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
14084 | if (err) { | |
14085 | dev_info(&pdev->dev, | |
14086 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
14087 | err); | |
14088 | /* non-fatal, continue */ | |
14089 | } | |
14090 | ||
14091 | return result; | |
14092 | } | |
14093 | ||
19b7960b AB |
14094 | /** |
14095 | * i40e_pci_error_reset_prepare - prepare device driver for pci reset | |
14096 | * @pdev: PCI device information struct | |
14097 | */ | |
14098 | static void i40e_pci_error_reset_prepare(struct pci_dev *pdev) | |
14099 | { | |
14100 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14101 | ||
14102 | i40e_prep_for_reset(pf, false); | |
14103 | } | |
14104 | ||
14105 | /** | |
14106 | * i40e_pci_error_reset_done - pci reset done, device driver reset can begin | |
14107 | * @pdev: PCI device information struct | |
14108 | */ | |
14109 | static void i40e_pci_error_reset_done(struct pci_dev *pdev) | |
14110 | { | |
14111 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14112 | ||
14113 | i40e_reset_and_rebuild(pf, false, false); | |
14114 | } | |
14115 | ||
41c445ff JB |
14116 | /** |
14117 | * i40e_pci_error_resume - restart operations after PCI error recovery | |
14118 | * @pdev: PCI device information struct | |
14119 | * | |
14120 | * Called to allow the driver to bring things back up after PCI error | |
14121 | * and/or reset recovery has finished. | |
14122 | **/ | |
14123 | static void i40e_pci_error_resume(struct pci_dev *pdev) | |
14124 | { | |
14125 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14126 | ||
fb43201f | 14127 | dev_dbg(&pdev->dev, "%s\n", __func__); |
0da36b97 | 14128 | if (test_bit(__I40E_SUSPENDED, pf->state)) |
9007bccd SN |
14129 | return; |
14130 | ||
dfc4ff64 | 14131 | i40e_handle_reset_warning(pf, false); |
9007bccd SN |
14132 | } |
14133 | ||
1d68005d JH |
14134 | /** |
14135 | * i40e_enable_mc_magic_wake - enable multicast magic packet wake up | |
14136 | * using the mac_address_write admin q function | |
14137 | * @pf: pointer to i40e_pf struct | |
14138 | **/ | |
14139 | static void i40e_enable_mc_magic_wake(struct i40e_pf *pf) | |
14140 | { | |
14141 | struct i40e_hw *hw = &pf->hw; | |
14142 | i40e_status ret; | |
14143 | u8 mac_addr[6]; | |
14144 | u16 flags = 0; | |
14145 | ||
14146 | /* Get current MAC address in case it's an LAA */ | |
14147 | if (pf->vsi[pf->lan_vsi] && pf->vsi[pf->lan_vsi]->netdev) { | |
14148 | ether_addr_copy(mac_addr, | |
14149 | pf->vsi[pf->lan_vsi]->netdev->dev_addr); | |
14150 | } else { | |
14151 | dev_err(&pf->pdev->dev, | |
14152 | "Failed to retrieve MAC address; using default\n"); | |
14153 | ether_addr_copy(mac_addr, hw->mac.addr); | |
14154 | } | |
14155 | ||
14156 | /* The FW expects the mac address write cmd to first be called with | |
14157 | * one of these flags before calling it again with the multicast | |
14158 | * enable flags. | |
14159 | */ | |
14160 | flags = I40E_AQC_WRITE_TYPE_LAA_WOL; | |
14161 | ||
14162 | if (hw->func_caps.flex10_enable && hw->partition_id != 1) | |
14163 | flags = I40E_AQC_WRITE_TYPE_LAA_ONLY; | |
14164 | ||
14165 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
14166 | if (ret) { | |
14167 | dev_err(&pf->pdev->dev, | |
14168 | "Failed to update MAC address registers; cannot enable Multicast Magic packet wake up"); | |
14169 | return; | |
14170 | } | |
14171 | ||
14172 | flags = I40E_AQC_MC_MAG_EN | |
14173 | | I40E_AQC_WOL_PRESERVE_ON_PFR | |
14174 | | I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG; | |
14175 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
14176 | if (ret) | |
14177 | dev_err(&pf->pdev->dev, | |
14178 | "Failed to enable Multicast Magic Packet wake up\n"); | |
14179 | } | |
14180 | ||
9007bccd SN |
14181 | /** |
14182 | * i40e_shutdown - PCI callback for shutting down | |
14183 | * @pdev: PCI device information struct | |
14184 | **/ | |
14185 | static void i40e_shutdown(struct pci_dev *pdev) | |
14186 | { | |
14187 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 14188 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 14189 | |
0da36b97 | 14190 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 14191 | set_bit(__I40E_DOWN, pf->state); |
9007bccd | 14192 | rtnl_lock(); |
373149fc | 14193 | i40e_prep_for_reset(pf, true); |
9007bccd SN |
14194 | rtnl_unlock(); |
14195 | ||
8e2773ae SN |
14196 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
14197 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
14198 | ||
02b42498 CS |
14199 | del_timer_sync(&pf->service_timer); |
14200 | cancel_work_sync(&pf->service_task); | |
aaf66502 | 14201 | i40e_cloud_filter_exit(pf); |
02b42498 CS |
14202 | i40e_fdir_teardown(pf); |
14203 | ||
921c467c MW |
14204 | /* Client close must be called explicitly here because the timer |
14205 | * has been stopped. | |
14206 | */ | |
14207 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
14208 | ||
d36e41dc | 14209 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
14210 | i40e_enable_mc_magic_wake(pf); |
14211 | ||
dfc4ff64 | 14212 | i40e_prep_for_reset(pf, false); |
02b42498 CS |
14213 | |
14214 | wr32(hw, I40E_PFPM_APM, | |
14215 | (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); | |
14216 | wr32(hw, I40E_PFPM_WUFC, | |
14217 | (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
14218 | ||
e147758d SN |
14219 | i40e_clear_interrupt_scheme(pf); |
14220 | ||
9007bccd | 14221 | if (system_state == SYSTEM_POWER_OFF) { |
8e2773ae | 14222 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
14223 | pci_set_power_state(pdev, PCI_D3hot); |
14224 | } | |
14225 | } | |
14226 | ||
9007bccd | 14227 | /** |
0e5d3da4 JK |
14228 | * i40e_suspend - PM callback for moving to D3 |
14229 | * @dev: generic device information structure | |
9007bccd | 14230 | **/ |
254d152a | 14231 | static int __maybe_unused i40e_suspend(struct device *dev) |
9007bccd | 14232 | { |
0e5d3da4 | 14233 | struct pci_dev *pdev = to_pci_dev(dev); |
9007bccd | 14234 | struct i40e_pf *pf = pci_get_drvdata(pdev); |
8e2773ae | 14235 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 14236 | |
401586c2 JK |
14237 | /* If we're already suspended, then there is nothing to do */ |
14238 | if (test_and_set_bit(__I40E_SUSPENDED, pf->state)) | |
14239 | return 0; | |
14240 | ||
9e6c9c0f | 14241 | set_bit(__I40E_DOWN, pf->state); |
3932dbfe | 14242 | |
5c499228 JK |
14243 | /* Ensure service task will not be running */ |
14244 | del_timer_sync(&pf->service_timer); | |
14245 | cancel_work_sync(&pf->service_task); | |
14246 | ||
d36e41dc | 14247 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
14248 | i40e_enable_mc_magic_wake(pf); |
14249 | ||
dfc4ff64 | 14250 | i40e_prep_for_reset(pf, false); |
9007bccd | 14251 | |
8e2773ae SN |
14252 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
14253 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
14254 | ||
b980c063 JK |
14255 | /* Clear the interrupt scheme and release our IRQs so that the system |
14256 | * can safely hibernate even when there are a large number of CPUs. | |
14257 | * Otherwise hibernation might fail when mapping all the vectors back | |
14258 | * to CPU0. | |
14259 | */ | |
14260 | i40e_clear_interrupt_scheme(pf); | |
9007bccd | 14261 | |
0e5d3da4 | 14262 | return 0; |
41c445ff JB |
14263 | } |
14264 | ||
9007bccd | 14265 | /** |
0e5d3da4 JK |
14266 | * i40e_resume - PM callback for waking up from D3 |
14267 | * @dev: generic device information structure | |
9007bccd | 14268 | **/ |
254d152a | 14269 | static int __maybe_unused i40e_resume(struct device *dev) |
9007bccd | 14270 | { |
0e5d3da4 | 14271 | struct pci_dev *pdev = to_pci_dev(dev); |
9007bccd | 14272 | struct i40e_pf *pf = pci_get_drvdata(pdev); |
b980c063 | 14273 | int err; |
9007bccd | 14274 | |
401586c2 JK |
14275 | /* If we're not suspended, then there is nothing to do */ |
14276 | if (!test_bit(__I40E_SUSPENDED, pf->state)) | |
14277 | return 0; | |
9007bccd | 14278 | |
b980c063 JK |
14279 | /* We cleared the interrupt scheme when we suspended, so we need to |
14280 | * restore it now to resume device functionality. | |
14281 | */ | |
14282 | err = i40e_restore_interrupt_scheme(pf); | |
9007bccd | 14283 | if (err) { |
b980c063 JK |
14284 | dev_err(&pdev->dev, "Cannot restore interrupt scheme: %d\n", |
14285 | err); | |
9007bccd | 14286 | } |
9007bccd | 14287 | |
401586c2 JK |
14288 | clear_bit(__I40E_DOWN, pf->state); |
14289 | i40e_reset_and_rebuild(pf, false, false); | |
14290 | ||
14291 | /* Clear suspended state last after everything is recovered */ | |
14292 | clear_bit(__I40E_SUSPENDED, pf->state); | |
9007bccd | 14293 | |
5c499228 JK |
14294 | /* Restart the service task */ |
14295 | mod_timer(&pf->service_timer, | |
14296 | round_jiffies(jiffies + pf->service_timer_period)); | |
9007bccd SN |
14297 | |
14298 | return 0; | |
14299 | } | |
14300 | ||
41c445ff JB |
14301 | static const struct pci_error_handlers i40e_err_handler = { |
14302 | .error_detected = i40e_pci_error_detected, | |
14303 | .slot_reset = i40e_pci_error_slot_reset, | |
19b7960b AB |
14304 | .reset_prepare = i40e_pci_error_reset_prepare, |
14305 | .reset_done = i40e_pci_error_reset_done, | |
41c445ff JB |
14306 | .resume = i40e_pci_error_resume, |
14307 | }; | |
14308 | ||
0e5d3da4 JK |
14309 | static SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume); |
14310 | ||
41c445ff JB |
14311 | static struct pci_driver i40e_driver = { |
14312 | .name = i40e_driver_name, | |
14313 | .id_table = i40e_pci_tbl, | |
14314 | .probe = i40e_probe, | |
14315 | .remove = i40e_remove, | |
0e5d3da4 JK |
14316 | .driver = { |
14317 | .pm = &i40e_pm_ops, | |
14318 | }, | |
9007bccd | 14319 | .shutdown = i40e_shutdown, |
41c445ff JB |
14320 | .err_handler = &i40e_err_handler, |
14321 | .sriov_configure = i40e_pci_sriov_configure, | |
14322 | }; | |
14323 | ||
14324 | /** | |
14325 | * i40e_init_module - Driver registration routine | |
14326 | * | |
14327 | * i40e_init_module is the first routine called when the driver is | |
14328 | * loaded. All it does is register with the PCI subsystem. | |
14329 | **/ | |
14330 | static int __init i40e_init_module(void) | |
14331 | { | |
14332 | pr_info("%s: %s - version %s\n", i40e_driver_name, | |
14333 | i40e_driver_string, i40e_driver_version_str); | |
14334 | pr_info("%s: %s\n", i40e_driver_name, i40e_copyright); | |
96664483 | 14335 | |
4d5957cb JK |
14336 | /* There is no need to throttle the number of active tasks because |
14337 | * each device limits its own task using a state bit for scheduling | |
14338 | * the service task, and the device tasks do not interfere with each | |
14339 | * other, so we don't set a max task limit. We must set WQ_MEM_RECLAIM | |
14340 | * since we need to be able to guarantee forward progress even under | |
14341 | * memory pressure. | |
2803b16c | 14342 | */ |
4d5957cb | 14343 | i40e_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, i40e_driver_name); |
2803b16c JB |
14344 | if (!i40e_wq) { |
14345 | pr_err("%s: Failed to create workqueue\n", i40e_driver_name); | |
14346 | return -ENOMEM; | |
14347 | } | |
14348 | ||
41c445ff JB |
14349 | i40e_dbg_init(); |
14350 | return pci_register_driver(&i40e_driver); | |
14351 | } | |
14352 | module_init(i40e_init_module); | |
14353 | ||
14354 | /** | |
14355 | * i40e_exit_module - Driver exit cleanup routine | |
14356 | * | |
14357 | * i40e_exit_module is called just before the driver is removed | |
14358 | * from memory. | |
14359 | **/ | |
14360 | static void __exit i40e_exit_module(void) | |
14361 | { | |
14362 | pci_unregister_driver(&i40e_driver); | |
2803b16c | 14363 | destroy_workqueue(i40e_wq); |
41c445ff JB |
14364 | i40e_dbg_exit(); |
14365 | } | |
14366 | module_exit(i40e_exit_module); |