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i40e/i40evf: Update register.h file for X722
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
42d255ce 41#define DRV_VERSION_MINOR 3
76945bf9 42#define DRV_VERSION_BUILD 6
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
ae24b409 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
41c445ff
JB		 82 /* required last entry */
83 {0, }
84};
85MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
86
87#define I40E_MAX_VF_COUNT 128
88static int debug = -1;
89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
93MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
94MODULE_LICENSE("GPL");
95MODULE_VERSION(DRV_VERSION);
96
97/**
98 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
99 * @hw: pointer to the HW structure
100 * @mem: ptr to mem struct to fill out
101 * @size: size of memory requested
102 * @alignment: what to align the allocation to
103 **/
104int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
105 u64 size, u32 alignment)
106{
107 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
108
109 mem->size = ALIGN(size, alignment);
110 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
111 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 112 if (!mem->va)
113 return -ENOMEM;
41c445ff 114
93bc73b8 115 return 0;
41c445ff
JB		 116}
117
118/**
119 * i40e_free_dma_mem_d - OS specific memory free for shared code
120 * @hw: pointer to the HW structure
121 * @mem: ptr to mem struct to free
122 **/
123int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
124{
125 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
126
127 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
128 mem->va = NULL;
129 mem->pa = 0;
130 mem->size = 0;
131
132 return 0;
133}
134
135/**
136 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
137 * @hw: pointer to the HW structure
138 * @mem: ptr to mem struct to fill out
139 * @size: size of memory requested
140 **/
141int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
142 u32 size)
143{
144 mem->size = size;
145 mem->va = kzalloc(size, GFP_KERNEL);
146
93bc73b8
JB		 147 if (!mem->va)
148 return -ENOMEM;
41c445ff 149
93bc73b8 150 return 0;
41c445ff
JB		 151}
152
153/**
154 * i40e_free_virt_mem_d - OS specific memory free for shared code
155 * @hw: pointer to the HW structure
156 * @mem: ptr to mem struct to free
157 **/
158int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
159{
160 /* it's ok to kfree a NULL pointer */
161 kfree(mem->va);
162 mem->va = NULL;
163 mem->size = 0;
164
165 return 0;
166}
167
168/**
169 * i40e_get_lump - find a lump of free generic resource
170 * @pf: board private structure
171 * @pile: the pile of resource to search
172 * @needed: the number of items needed
173 * @id: an owner id to stick on the items assigned
174 *
175 * Returns the base item index of the lump, or negative for error
176 *
177 * The search_hint trick and lack of advanced fit-finding only work
178 * because we're highly likely to have all the same size lump requests.
179 * Linear search time and any fragmentation should be minimal.
180 **/
181static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
182 u16 needed, u16 id)
183{
184 int ret = -ENOMEM;
ddf434ac 185 int i, j;
41c445ff
JB		 186
187 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
188 dev_info(&pf->pdev->dev,
189 "param err: pile=%p needed=%d id=0x%04x\n",
190 pile, needed, id);
191 return -EINVAL;
192 }
193
194 /* start the linear search with an imperfect hint */
195 i = pile->search_hint;
ddf434ac 196 while (i < pile->num_entries) {
41c445ff
JB		 197 /* skip already allocated entries */
198 if (pile->list[i] & I40E_PILE_VALID_BIT) {
199 i++;
200 continue;
201 }
202
203 /* do we have enough in this lump? */
204 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
205 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
206 break;
207 }
208
209 if (j == needed) {
210 /* there was enough, so assign it to the requestor */
211 for (j = 0; j < needed; j++)
212 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
213 ret = i;
214 pile->search_hint = i + j;
ddf434ac 215 break;
41c445ff
JB		 216 } else {
217 /* not enough, so skip over it and continue looking */
218 i += j;
219 }
220 }
221
222 return ret;
223}
224
225/**
226 * i40e_put_lump - return a lump of generic resource
227 * @pile: the pile of resource to search
228 * @index: the base item index
229 * @id: the owner id of the items assigned
230 *
231 * Returns the count of items in the lump
232 **/
233static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
234{
235 int valid_id = (id | I40E_PILE_VALID_BIT);
236 int count = 0;
237 int i;
238
239 if (!pile || index >= pile->num_entries)
240 return -EINVAL;
241
242 for (i = index;
243 i < pile->num_entries && pile->list[i] == valid_id;
244 i++) {
245 pile->list[i] = 0;
246 count++;
247 }
248
249 if (count && index < pile->search_hint)
250 pile->search_hint = index;
251
252 return count;
253}
254
fdf0e0bf
ASJ		 255/**
256 * i40e_find_vsi_from_id - searches for the vsi with the given id
257 * @pf - the pf structure to search for the vsi
258 * @id - id of the vsi it is searching for
259 **/
260struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
261{
262 int i;
263
264 for (i = 0; i < pf->num_alloc_vsi; i++)
265 if (pf->vsi[i] && (pf->vsi[i]->id == id))
266 return pf->vsi[i];
267
268 return NULL;
269}
270
41c445ff
JB		 271/**
272 * i40e_service_event_schedule - Schedule the service task to wake up
273 * @pf: board private structure
274 *
275 * If not already scheduled, this puts the task into the work queue
276 **/
277static void i40e_service_event_schedule(struct i40e_pf *pf)
278{
279 if (!test_bit(__I40E_DOWN, &pf->state) &&
280 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
281 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
282 schedule_work(&pf->service_task);
283}
284
285/**
286 * i40e_tx_timeout - Respond to a Tx Hang
287 * @netdev: network interface device structure
288 *
289 * If any port has noticed a Tx timeout, it is likely that the whole
290 * device is munged, not just the one netdev port, so go for the full
291 * reset.
292 **/
38e00438
VD		 293#ifdef I40E_FCOE
294void i40e_tx_timeout(struct net_device *netdev)
295#else
41c445ff 296static void i40e_tx_timeout(struct net_device *netdev)
38e00438 297#endif
41c445ff
JB		 298{
299 struct i40e_netdev_priv *np = netdev_priv(netdev);
300 struct i40e_vsi *vsi = np->vsi;
301 struct i40e_pf *pf = vsi->back;
302
303 pf->tx_timeout_count++;
304
305 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 306 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 307 pf->tx_timeout_last_recovery = jiffies;
308 netdev_info(netdev, "tx_timeout recovery level %d\n",
309 pf->tx_timeout_recovery_level);
310
311 switch (pf->tx_timeout_recovery_level) {
312 case 0:
313 /* disable and re-enable queues for the VSI */
314 if (in_interrupt()) {
315 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
316 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
317 } else {
318 i40e_vsi_reinit_locked(vsi);
319 }
320 break;
321 case 1:
322 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
323 break;
324 case 2:
325 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
326 break;
327 case 3:
328 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
329 break;
330 default:
331 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 332 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
333 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 334 break;
335 }
336 i40e_service_event_schedule(pf);
337 pf->tx_timeout_recovery_level++;
338}
339
340/**
341 * i40e_release_rx_desc - Store the new tail and head values
342 * @rx_ring: ring to bump
343 * @val: new head index
344 **/
345static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
346{
347 rx_ring->next_to_use = val;
348
349 /* Force memory writes to complete before letting h/w
350 * know there are new descriptors to fetch. (Only
351 * applicable for weak-ordered memory model archs,
352 * such as IA-64).
353 */
354 wmb();
355 writel(val, rx_ring->tail);
356}
357
358/**
359 * i40e_get_vsi_stats_struct - Get System Network Statistics
360 * @vsi: the VSI we care about
361 *
362 * Returns the address of the device statistics structure.
363 * The statistics are actually updated from the service task.
364 **/
365struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
366{
367 return &vsi->net_stats;
368}
369
370/**
371 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
372 * @netdev: network interface device structure
373 *
374 * Returns the address of the device statistics structure.
375 * The statistics are actually updated from the service task.
376 **/
38e00438
VD		 377#ifdef I40E_FCOE
378struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
379 struct net_device *netdev,
380 struct rtnl_link_stats64 *stats)
381#else
41c445ff
JB		 382static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
383 struct net_device *netdev,
980e9b11 384 struct rtnl_link_stats64 *stats)
38e00438 385#endif
41c445ff
JB		 386{
387 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 388 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 389 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 390 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
391 int i;
392
bc7d338f
ASJ		 393 if (test_bit(__I40E_DOWN, &vsi->state))
394 return stats;
395
3c325ced
JB		 396 if (!vsi->tx_rings)
397 return stats;
398
980e9b11
AD		 399 rcu_read_lock();
400 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 401 u64 bytes, packets;
402 unsigned int start;
403
404 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
405 if (!tx_ring)
406 continue;
407
408 do {
57a7744e 409 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 410 packets = tx_ring->stats.packets;
411 bytes = tx_ring->stats.bytes;
57a7744e 412 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 413
414 stats->tx_packets += packets;
415 stats->tx_bytes += bytes;
416 rx_ring = &tx_ring[1];
417
418 do {
57a7744e 419 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 420 packets = rx_ring->stats.packets;
421 bytes = rx_ring->stats.bytes;
57a7744e 422 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 423
980e9b11
AD		 424 stats->rx_packets += packets;
425 stats->rx_bytes += bytes;
426 }
427 rcu_read_unlock();
428
a5282f44 429 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 430 stats->multicast = vsi_stats->multicast;
431 stats->tx_errors = vsi_stats->tx_errors;
432 stats->tx_dropped = vsi_stats->tx_dropped;
433 stats->rx_errors = vsi_stats->rx_errors;
434 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
435 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 436
980e9b11 437 return stats;
41c445ff
JB		 438}
439
440/**
441 * i40e_vsi_reset_stats - Resets all stats of the given vsi
442 * @vsi: the VSI to have its stats reset
443 **/
444void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
445{
446 struct rtnl_link_stats64 *ns;
447 int i;
448
449 if (!vsi)
450 return;
451
452 ns = i40e_get_vsi_stats_struct(vsi);
453 memset(ns, 0, sizeof(*ns));
454 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
455 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
456 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 457 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 458 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 459 memset(&vsi->rx_rings[i]->stats, 0 ,
460 sizeof(vsi->rx_rings[i]->stats));
461 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
462 sizeof(vsi->rx_rings[i]->rx_stats));
463 memset(&vsi->tx_rings[i]->stats, 0 ,
464 sizeof(vsi->tx_rings[i]->stats));
465 memset(&vsi->tx_rings[i]->tx_stats, 0,
466 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 467 }
8e9dca53 468 }
41c445ff
JB		 469 vsi->stat_offsets_loaded = false;
470}
471
472/**
b40c82e6 473 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 474 * @pf: the PF to be reset
475 **/
476void i40e_pf_reset_stats(struct i40e_pf *pf)
477{
e91fdf76
SN		 478 int i;
479
41c445ff
JB		 480 memset(&pf->stats, 0, sizeof(pf->stats));
481 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
482 pf->stat_offsets_loaded = false;
e91fdf76
SN		 483
484 for (i = 0; i < I40E_MAX_VEB; i++) {
485 if (pf->veb[i]) {
486 memset(&pf->veb[i]->stats, 0,
487 sizeof(pf->veb[i]->stats));
488 memset(&pf->veb[i]->stats_offsets, 0,
489 sizeof(pf->veb[i]->stats_offsets));
490 pf->veb[i]->stat_offsets_loaded = false;
491 }
492 }
41c445ff
JB		 493}
494
495/**
496 * i40e_stat_update48 - read and update a 48 bit stat from the chip
497 * @hw: ptr to the hardware info
498 * @hireg: the high 32 bit reg to read
499 * @loreg: the low 32 bit reg to read
500 * @offset_loaded: has the initial offset been loaded yet
501 * @offset: ptr to current offset value
502 * @stat: ptr to the stat
503 *
504 * Since the device stats are not reset at PFReset, they likely will not
505 * be zeroed when the driver starts. We'll save the first values read
506 * and use them as offsets to be subtracted from the raw values in order
507 * to report stats that count from zero. In the process, we also manage
508 * the potential roll-over.
509 **/
510static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
511 bool offset_loaded, u64 *offset, u64 *stat)
512{
513 u64 new_data;
514
ab60085e 515 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 516 new_data = rd32(hw, loreg);
517 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
518 } else {
519 new_data = rd64(hw, loreg);
520 }
521 if (!offset_loaded)
522 *offset = new_data;
523 if (likely(new_data >= *offset))
524 *stat = new_data - *offset;
525 else
41a1d04b 526 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 527 *stat &= 0xFFFFFFFFFFFFULL;
528}
529
530/**
531 * i40e_stat_update32 - read and update a 32 bit stat from the chip
532 * @hw: ptr to the hardware info
533 * @reg: the hw reg to read
534 * @offset_loaded: has the initial offset been loaded yet
535 * @offset: ptr to current offset value
536 * @stat: ptr to the stat
537 **/
538static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
539 bool offset_loaded, u64 *offset, u64 *stat)
540{
541 u32 new_data;
542
543 new_data = rd32(hw, reg);
544 if (!offset_loaded)
545 *offset = new_data;
546 if (likely(new_data >= *offset))
547 *stat = (u32)(new_data - *offset);
548 else
41a1d04b 549 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 550}
551
552/**
553 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
554 * @vsi: the VSI to be updated
555 **/
556void i40e_update_eth_stats(struct i40e_vsi *vsi)
557{
558 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
559 struct i40e_pf *pf = vsi->back;
560 struct i40e_hw *hw = &pf->hw;
561 struct i40e_eth_stats *oes;
562 struct i40e_eth_stats *es; /* device's eth stats */
563
564 es = &vsi->eth_stats;
565 oes = &vsi->eth_stats_offsets;
566
567 /* Gather up the stats that the hw collects */
568 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
569 vsi->stat_offsets_loaded,
570 &oes->tx_errors, &es->tx_errors);
571 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
572 vsi->stat_offsets_loaded,
573 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 574 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
577 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
578 vsi->stat_offsets_loaded,
579 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 580
581 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
582 I40E_GLV_GORCL(stat_idx),
583 vsi->stat_offsets_loaded,
584 &oes->rx_bytes, &es->rx_bytes);
585 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
586 I40E_GLV_UPRCL(stat_idx),
587 vsi->stat_offsets_loaded,
588 &oes->rx_unicast, &es->rx_unicast);
589 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
590 I40E_GLV_MPRCL(stat_idx),
591 vsi->stat_offsets_loaded,
592 &oes->rx_multicast, &es->rx_multicast);
593 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
594 I40E_GLV_BPRCL(stat_idx),
595 vsi->stat_offsets_loaded,
596 &oes->rx_broadcast, &es->rx_broadcast);
597
598 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
599 I40E_GLV_GOTCL(stat_idx),
600 vsi->stat_offsets_loaded,
601 &oes->tx_bytes, &es->tx_bytes);
602 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
603 I40E_GLV_UPTCL(stat_idx),
604 vsi->stat_offsets_loaded,
605 &oes->tx_unicast, &es->tx_unicast);
606 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
607 I40E_GLV_MPTCL(stat_idx),
608 vsi->stat_offsets_loaded,
609 &oes->tx_multicast, &es->tx_multicast);
610 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
611 I40E_GLV_BPTCL(stat_idx),
612 vsi->stat_offsets_loaded,
613 &oes->tx_broadcast, &es->tx_broadcast);
614 vsi->stat_offsets_loaded = true;
615}
616
617/**
618 * i40e_update_veb_stats - Update Switch component statistics
619 * @veb: the VEB being updated
620 **/
621static void i40e_update_veb_stats(struct i40e_veb *veb)
622{
623 struct i40e_pf *pf = veb->pf;
624 struct i40e_hw *hw = &pf->hw;
625 struct i40e_eth_stats *oes;
626 struct i40e_eth_stats *es; /* device's eth stats */
627 int idx = 0;
628
629 idx = veb->stats_idx;
630 es = &veb->stats;
631 oes = &veb->stats_offsets;
632
633 /* Gather up the stats that the hw collects */
634 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
635 veb->stat_offsets_loaded,
636 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 637 if (hw->revision_id > 0)
638 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
639 veb->stat_offsets_loaded,
640 &oes->rx_unknown_protocol,
641 &es->rx_unknown_protocol);
41c445ff
JB		 642 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
643 veb->stat_offsets_loaded,
644 &oes->rx_bytes, &es->rx_bytes);
645 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
646 veb->stat_offsets_loaded,
647 &oes->rx_unicast, &es->rx_unicast);
648 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
649 veb->stat_offsets_loaded,
650 &oes->rx_multicast, &es->rx_multicast);
651 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
652 veb->stat_offsets_loaded,
653 &oes->rx_broadcast, &es->rx_broadcast);
654
655 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
656 veb->stat_offsets_loaded,
657 &oes->tx_bytes, &es->tx_bytes);
658 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
659 veb->stat_offsets_loaded,
660 &oes->tx_unicast, &es->tx_unicast);
661 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
662 veb->stat_offsets_loaded,
663 &oes->tx_multicast, &es->tx_multicast);
664 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
665 veb->stat_offsets_loaded,
666 &oes->tx_broadcast, &es->tx_broadcast);
667 veb->stat_offsets_loaded = true;
668}
669
38e00438
VD		 670#ifdef I40E_FCOE
671/**
672 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
673 * @vsi: the VSI that is capable of doing FCoE
674 **/
675static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
676{
677 struct i40e_pf *pf = vsi->back;
678 struct i40e_hw *hw = &pf->hw;
679 struct i40e_fcoe_stats *ofs;
680 struct i40e_fcoe_stats *fs; /* device's eth stats */
681 int idx;
682
683 if (vsi->type != I40E_VSI_FCOE)
684 return;
685
686 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
687 fs = &vsi->fcoe_stats;
688 ofs = &vsi->fcoe_stats_offsets;
689
690 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
691 vsi->fcoe_stat_offsets_loaded,
692 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
693 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
694 vsi->fcoe_stat_offsets_loaded,
695 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
696 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
697 vsi->fcoe_stat_offsets_loaded,
698 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
699 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
700 vsi->fcoe_stat_offsets_loaded,
701 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
702 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
703 vsi->fcoe_stat_offsets_loaded,
704 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
705 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
706 vsi->fcoe_stat_offsets_loaded,
707 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
708 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
709 vsi->fcoe_stat_offsets_loaded,
710 &ofs->fcoe_last_error, &fs->fcoe_last_error);
711 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
712 vsi->fcoe_stat_offsets_loaded,
713 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
714
715 vsi->fcoe_stat_offsets_loaded = true;
716}
717
718#endif
41c445ff
JB		 719/**
720 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
721 * @pf: the corresponding PF
722 *
723 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
724 **/
725static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
726{
727 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
728 struct i40e_hw_port_stats *nsd = &pf->stats;
729 struct i40e_hw *hw = &pf->hw;
730 u64 xoff = 0;
731 u16 i, v;
732
733 if ((hw->fc.current_mode != I40E_FC_FULL) &&
734 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
735 return;
736
737 xoff = nsd->link_xoff_rx;
738 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
739 pf->stat_offsets_loaded,
740 &osd->link_xoff_rx, &nsd->link_xoff_rx);
741
742 /* No new LFC xoff rx */
743 if (!(nsd->link_xoff_rx - xoff))
744 return;
745
746 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 747 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 748 struct i40e_vsi *vsi = pf->vsi[v];
749
ddfda80f 750 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 751 continue;
752
753 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 754 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 755 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
756 }
757 }
758}
759
760/**
761 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
762 * @pf: the corresponding PF
763 *
764 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
765 **/
766static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
767{
768 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
769 struct i40e_hw_port_stats *nsd = &pf->stats;
770 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
771 struct i40e_dcbx_config *dcb_cfg;
772 struct i40e_hw *hw = &pf->hw;
773 u16 i, v;
774 u8 tc;
775
776 dcb_cfg = &hw->local_dcbx_config;
777
e120814d
NP		 778 /* Collect Link XOFF stats when PFC is disabled */
779 if (!dcb_cfg->pfc.pfcenable) {
41c445ff
JB		 780 i40e_update_link_xoff_rx(pf);
781 return;
782 }
783
784 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
785 u64 prio_xoff = nsd->priority_xoff_rx[i];
786 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
787 pf->stat_offsets_loaded,
788 &osd->priority_xoff_rx[i],
789 &nsd->priority_xoff_rx[i]);
790
791 /* No new PFC xoff rx */
792 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
793 continue;
794 /* Get the TC for given priority */
795 tc = dcb_cfg->etscfg.prioritytable[i];
796 xoff[tc] = true;
797 }
798
799 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 800 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 801 struct i40e_vsi *vsi = pf->vsi[v];
802
ddfda80f 803 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 804 continue;
805
806 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 807 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 808
809 tc = ring->dcb_tc;
810 if (xoff[tc])
811 clear_bit(__I40E_HANG_CHECK_ARMED,
812 &ring->state);
813 }
814 }
815}
816
817/**
7812fddc 818 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 819 * @vsi: the VSI to be updated
820 *
821 * There are a few instances where we store the same stat in a
822 * couple of different structs. This is partly because we have
823 * the netdev stats that need to be filled out, which is slightly
824 * different from the "eth_stats" defined by the chip and used in
7812fddc 825 * VF communications. We sort it out here.
41c445ff 826 **/
7812fddc 827static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 828{
829 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 830 struct rtnl_link_stats64 *ons;
831 struct rtnl_link_stats64 *ns; /* netdev stats */
832 struct i40e_eth_stats *oes;
833 struct i40e_eth_stats *es; /* device's eth stats */
834 u32 tx_restart, tx_busy;
bf00b376 835 struct i40e_ring *p;
41c445ff 836 u32 rx_page, rx_buf;
bf00b376
AA		 837 u64 bytes, packets;
838 unsigned int start;
41c445ff
JB		 839 u64 rx_p, rx_b;
840 u64 tx_p, tx_b;
41c445ff
JB		 841 u16 q;
842
843 if (test_bit(__I40E_DOWN, &vsi->state) ||
844 test_bit(__I40E_CONFIG_BUSY, &pf->state))
845 return;
846
847 ns = i40e_get_vsi_stats_struct(vsi);
848 ons = &vsi->net_stats_offsets;
849 es = &vsi->eth_stats;
850 oes = &vsi->eth_stats_offsets;
851
852 /* Gather up the netdev and vsi stats that the driver collects
853 * on the fly during packet processing
854 */
855 rx_b = rx_p = 0;
856 tx_b = tx_p = 0;
857 tx_restart = tx_busy = 0;
858 rx_page = 0;
859 rx_buf = 0;
980e9b11 860 rcu_read_lock();
41c445ff 861 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 862 /* locate Tx ring */
863 p = ACCESS_ONCE(vsi->tx_rings[q]);
864
865 do {
57a7744e 866 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 867 packets = p->stats.packets;
868 bytes = p->stats.bytes;
57a7744e 869 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 870 tx_b += bytes;
871 tx_p += packets;
872 tx_restart += p->tx_stats.restart_queue;
873 tx_busy += p->tx_stats.tx_busy;
41c445ff 874
980e9b11
AD		 875 /* Rx queue is part of the same block as Tx queue */
876 p = &p[1];
877 do {
57a7744e 878 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 879 packets = p->stats.packets;
880 bytes = p->stats.bytes;
57a7744e 881 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 882 rx_b += bytes;
883 rx_p += packets;
420136cc
MW		 884 rx_buf += p->rx_stats.alloc_buff_failed;
885 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 886 }
980e9b11 887 rcu_read_unlock();
41c445ff
JB		 888 vsi->tx_restart = tx_restart;
889 vsi->tx_busy = tx_busy;
890 vsi->rx_page_failed = rx_page;
891 vsi->rx_buf_failed = rx_buf;
892
893 ns->rx_packets = rx_p;
894 ns->rx_bytes = rx_b;
895 ns->tx_packets = tx_p;
896 ns->tx_bytes = tx_b;
897
41c445ff 898 /* update netdev stats from eth stats */
7812fddc 899 i40e_update_eth_stats(vsi);
41c445ff
JB		 900 ons->tx_errors = oes->tx_errors;
901 ns->tx_errors = es->tx_errors;
902 ons->multicast = oes->rx_multicast;
903 ns->multicast = es->rx_multicast;
41a9e55c
SN		 904 ons->rx_dropped = oes->rx_discards;
905 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 906 ons->tx_dropped = oes->tx_discards;
907 ns->tx_dropped = es->tx_discards;
908
7812fddc 909 /* pull in a couple PF stats if this is the main vsi */
41c445ff 910 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 911 ns->rx_crc_errors = pf->stats.crc_errors;
912 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
913 ns->rx_length_errors = pf->stats.rx_length_errors;
914 }
915}
41c445ff 916
7812fddc 917/**
b40c82e6 918 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 919 * @pf: the PF to be updated
920 **/
921static void i40e_update_pf_stats(struct i40e_pf *pf)
922{
923 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
924 struct i40e_hw_port_stats *nsd = &pf->stats;
925 struct i40e_hw *hw = &pf->hw;
926 u32 val;
927 int i;
41c445ff 928
7812fddc
SN		 929 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
930 I40E_GLPRT_GORCL(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
933 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
934 I40E_GLPRT_GOTCL(hw->port),
935 pf->stat_offsets_loaded,
936 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
937 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->eth.rx_discards,
940 &nsd->eth.rx_discards);
532d283d
SN		 941 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
942 I40E_GLPRT_UPRCL(hw->port),
943 pf->stat_offsets_loaded,
944 &osd->eth.rx_unicast,
945 &nsd->eth.rx_unicast);
7812fddc
SN		 946 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
947 I40E_GLPRT_MPRCL(hw->port),
948 pf->stat_offsets_loaded,
949 &osd->eth.rx_multicast,
950 &nsd->eth.rx_multicast);
532d283d
SN		 951 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
952 I40E_GLPRT_BPRCL(hw->port),
953 pf->stat_offsets_loaded,
954 &osd->eth.rx_broadcast,
955 &nsd->eth.rx_broadcast);
956 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
957 I40E_GLPRT_UPTCL(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->eth.tx_unicast,
960 &nsd->eth.tx_unicast);
961 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
962 I40E_GLPRT_MPTCL(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->eth.tx_multicast,
965 &nsd->eth.tx_multicast);
966 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
967 I40E_GLPRT_BPTCL(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->eth.tx_broadcast,
970 &nsd->eth.tx_broadcast);
41c445ff 971
7812fddc
SN		 972 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
973 pf->stat_offsets_loaded,
974 &osd->tx_dropped_link_down,
975 &nsd->tx_dropped_link_down);
41c445ff 976
7812fddc
SN		 977 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->crc_errors, &nsd->crc_errors);
41c445ff 980
7812fddc
SN		 981 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->mac_local_faults,
988 &nsd->mac_local_faults);
989 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
990 pf->stat_offsets_loaded,
991 &osd->mac_remote_faults,
992 &nsd->mac_remote_faults);
41c445ff 993
7812fddc
SN		 994 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->rx_length_errors,
997 &nsd->rx_length_errors);
41c445ff 998
7812fddc
SN		 999 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->link_xon_rx, &nsd->link_xon_rx);
1002 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
1003 pf->stat_offsets_loaded,
1004 &osd->link_xon_tx, &nsd->link_xon_tx);
1005 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
1006 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 1009
7812fddc
SN		 1010 for (i = 0; i < 8; i++) {
1011 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1012 pf->stat_offsets_loaded,
7812fddc
SN		 1013 &osd->priority_xon_rx[i],
1014 &nsd->priority_xon_rx[i]);
1015 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1016 pf->stat_offsets_loaded,
7812fddc
SN		 1017 &osd->priority_xon_tx[i],
1018 &nsd->priority_xon_tx[i]);
1019 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1020 pf->stat_offsets_loaded,
7812fddc
SN		 1021 &osd->priority_xoff_tx[i],
1022 &nsd->priority_xoff_tx[i]);
1023 i40e_stat_update32(hw,
1024 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1025 pf->stat_offsets_loaded,
7812fddc
SN		 1026 &osd->priority_xon_2_xoff[i],
1027 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1028 }
1029
7812fddc
SN		 1030 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1031 I40E_GLPRT_PRC64L(hw->port),
1032 pf->stat_offsets_loaded,
1033 &osd->rx_size_64, &nsd->rx_size_64);
1034 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1035 I40E_GLPRT_PRC127L(hw->port),
1036 pf->stat_offsets_loaded,
1037 &osd->rx_size_127, &nsd->rx_size_127);
1038 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1039 I40E_GLPRT_PRC255L(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->rx_size_255, &nsd->rx_size_255);
1042 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1043 I40E_GLPRT_PRC511L(hw->port),
1044 pf->stat_offsets_loaded,
1045 &osd->rx_size_511, &nsd->rx_size_511);
1046 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1047 I40E_GLPRT_PRC1023L(hw->port),
1048 pf->stat_offsets_loaded,
1049 &osd->rx_size_1023, &nsd->rx_size_1023);
1050 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1051 I40E_GLPRT_PRC1522L(hw->port),
1052 pf->stat_offsets_loaded,
1053 &osd->rx_size_1522, &nsd->rx_size_1522);
1054 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1055 I40E_GLPRT_PRC9522L(hw->port),
1056 pf->stat_offsets_loaded,
1057 &osd->rx_size_big, &nsd->rx_size_big);
1058
1059 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1060 I40E_GLPRT_PTC64L(hw->port),
1061 pf->stat_offsets_loaded,
1062 &osd->tx_size_64, &nsd->tx_size_64);
1063 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1064 I40E_GLPRT_PTC127L(hw->port),
1065 pf->stat_offsets_loaded,
1066 &osd->tx_size_127, &nsd->tx_size_127);
1067 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1068 I40E_GLPRT_PTC255L(hw->port),
1069 pf->stat_offsets_loaded,
1070 &osd->tx_size_255, &nsd->tx_size_255);
1071 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1072 I40E_GLPRT_PTC511L(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->tx_size_511, &nsd->tx_size_511);
1075 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1076 I40E_GLPRT_PTC1023L(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->tx_size_1023, &nsd->tx_size_1023);
1079 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1080 I40E_GLPRT_PTC1522L(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->tx_size_1522, &nsd->tx_size_1522);
1083 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1084 I40E_GLPRT_PTC9522L(hw->port),
1085 pf->stat_offsets_loaded,
1086 &osd->tx_size_big, &nsd->tx_size_big);
1087
1088 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1089 pf->stat_offsets_loaded,
1090 &osd->rx_undersize, &nsd->rx_undersize);
1091 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1092 pf->stat_offsets_loaded,
1093 &osd->rx_fragments, &nsd->rx_fragments);
1094 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1095 pf->stat_offsets_loaded,
1096 &osd->rx_oversize, &nsd->rx_oversize);
1097 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1098 pf->stat_offsets_loaded,
1099 &osd->rx_jabber, &nsd->rx_jabber);
1100
433c47de 1101 /* FDIR stats */
0bf4b1b0
ASJ		 1102 i40e_stat_update32(hw,
1103 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1104 pf->stat_offsets_loaded,
1105 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1106 i40e_stat_update32(hw,
1107 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1108 pf->stat_offsets_loaded,
1109 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1110 i40e_stat_update32(hw,
1111 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1112 pf->stat_offsets_loaded,
1113 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1114
7812fddc
SN		 1115 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1116 nsd->tx_lpi_status =
1117 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1118 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1119 nsd->rx_lpi_status =
1120 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1121 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1122 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1123 pf->stat_offsets_loaded,
1124 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1125 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1126 pf->stat_offsets_loaded,
1127 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1128
d0389e51
ASJ		 1129 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1130 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1131 nsd->fd_sb_status = true;
1132 else
1133 nsd->fd_sb_status = false;
1134
1135 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1136 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1137 nsd->fd_atr_status = true;
1138 else
1139 nsd->fd_atr_status = false;
1140
41c445ff
JB		 1141 pf->stat_offsets_loaded = true;
1142}
1143
7812fddc
SN		 1144/**
1145 * i40e_update_stats - Update the various statistics counters.
1146 * @vsi: the VSI to be updated
1147 *
1148 * Update the various stats for this VSI and its related entities.
1149 **/
1150void i40e_update_stats(struct i40e_vsi *vsi)
1151{
1152 struct i40e_pf *pf = vsi->back;
1153
1154 if (vsi == pf->vsi[pf->lan_vsi])
1155 i40e_update_pf_stats(pf);
1156
1157 i40e_update_vsi_stats(vsi);
38e00438
VD		 1158#ifdef I40E_FCOE
1159 i40e_update_fcoe_stats(vsi);
1160#endif
7812fddc
SN		 1161}
1162
41c445ff
JB		 1163/**
1164 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1165 * @vsi: the VSI to be searched
1166 * @macaddr: the MAC address
1167 * @vlan: the vlan
b40c82e6 1168 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1169 * @is_netdev: make sure its a netdev filter, else doesn't matter
1170 *
1171 * Returns ptr to the filter object or NULL
1172 **/
1173static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1174 u8 *macaddr, s16 vlan,
1175 bool is_vf, bool is_netdev)
1176{
1177 struct i40e_mac_filter *f;
1178
1179 if (!vsi || !macaddr)
1180 return NULL;
1181
1182 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1183 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1184 (vlan == f->vlan) &&
1185 (!is_vf || f->is_vf) &&
1186 (!is_netdev || f->is_netdev))
1187 return f;
1188 }
1189 return NULL;
1190}
1191
1192/**
1193 * i40e_find_mac - Find a mac addr in the macvlan filters list
1194 * @vsi: the VSI to be searched
1195 * @macaddr: the MAC address we are searching for
b40c82e6 1196 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1197 * @is_netdev: make sure its a netdev filter, else doesn't matter
1198 *
1199 * Returns the first filter with the provided MAC address or NULL if
1200 * MAC address was not found
1201 **/
1202struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1203 bool is_vf, bool is_netdev)
1204{
1205 struct i40e_mac_filter *f;
1206
1207 if (!vsi || !macaddr)
1208 return NULL;
1209
1210 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1211 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1212 (!is_vf || f->is_vf) &&
1213 (!is_netdev || f->is_netdev))
1214 return f;
1215 }
1216 return NULL;
1217}
1218
1219/**
1220 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1221 * @vsi: the VSI to be searched
1222 *
1223 * Returns true if VSI is in vlan mode or false otherwise
1224 **/
1225bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1226{
1227 struct i40e_mac_filter *f;
1228
1229 /* Only -1 for all the filters denotes not in vlan mode
1230 * so we have to go through all the list in order to make sure
1231 */
1232 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1233 if (f->vlan >= 0)
1234 return true;
1235 }
1236
1237 return false;
1238}
1239
1240/**
1241 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1242 * @vsi: the VSI to be searched
1243 * @macaddr: the mac address to be filtered
b40c82e6 1244 * @is_vf: true if it is a VF
41c445ff
JB		 1245 * @is_netdev: true if it is a netdev
1246 *
1247 * Goes through all the macvlan filters and adds a
1248 * macvlan filter for each unique vlan that already exists
1249 *
1250 * Returns first filter found on success, else NULL
1251 **/
1252struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1253 bool is_vf, bool is_netdev)
1254{
1255 struct i40e_mac_filter *f;
1256
1257 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1258 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1259 is_vf, is_netdev)) {
1260 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1261 is_vf, is_netdev))
41c445ff
JB		 1262 return NULL;
1263 }
1264 }
1265
1266 return list_first_entry_or_null(&vsi->mac_filter_list,
1267 struct i40e_mac_filter, list);
1268}
1269
8c27d42e
GR		 1270/**
1271 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1272 * @vsi: the PF Main VSI - inappropriate for any other VSI
1273 * @macaddr: the MAC address
30650cc5
SN		 1274 *
1275 * Some older firmware configurations set up a default promiscuous VLAN
1276 * filter that needs to be removed.
8c27d42e 1277 **/
30650cc5 1278static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1279{
1280 struct i40e_aqc_remove_macvlan_element_data element;
1281 struct i40e_pf *pf = vsi->back;
f1c7e72e 1282 i40e_status ret;
8c27d42e
GR		 1283
1284 /* Only appropriate for the PF main VSI */
1285 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1286 return -EINVAL;
8c27d42e 1287
30650cc5 1288 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1289 ether_addr_copy(element.mac_addr, macaddr);
1290 element.vlan_tag = 0;
1291 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1292 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1293 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1294 if (ret)
30650cc5
SN		 1295 return -ENOENT;
1296
1297 return 0;
8c27d42e
GR		 1298}
1299
41c445ff
JB		 1300/**
1301 * i40e_add_filter - Add a mac/vlan filter to the VSI
1302 * @vsi: the VSI to be searched
1303 * @macaddr: the MAC address
1304 * @vlan: the vlan
b40c82e6 1305 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1306 * @is_netdev: make sure its a netdev filter, else doesn't matter
1307 *
1308 * Returns ptr to the filter object or NULL when no memory available.
1309 **/
1310struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1311 u8 *macaddr, s16 vlan,
1312 bool is_vf, bool is_netdev)
1313{
1314 struct i40e_mac_filter *f;
1315
1316 if (!vsi || !macaddr)
1317 return NULL;
1318
1319 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1320 if (!f) {
1321 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1322 if (!f)
1323 goto add_filter_out;
1324
9a173901 1325 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1326 f->vlan = vlan;
1327 f->changed = true;
1328
1329 INIT_LIST_HEAD(&f->list);
1330 list_add(&f->list, &vsi->mac_filter_list);
1331 }
1332
1333 /* increment counter and add a new flag if needed */
1334 if (is_vf) {
1335 if (!f->is_vf) {
1336 f->is_vf = true;
1337 f->counter++;
1338 }
1339 } else if (is_netdev) {
1340 if (!f->is_netdev) {
1341 f->is_netdev = true;
1342 f->counter++;
1343 }
1344 } else {
1345 f->counter++;
1346 }
1347
1348 /* changed tells sync_filters_subtask to
1349 * push the filter down to the firmware
1350 */
1351 if (f->changed) {
1352 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1353 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1354 }
1355
1356add_filter_out:
1357 return f;
1358}
1359
1360/**
1361 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1362 * @vsi: the VSI to be searched
1363 * @macaddr: the MAC address
1364 * @vlan: the vlan
b40c82e6 1365 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1366 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1367 **/
1368void i40e_del_filter(struct i40e_vsi *vsi,
1369 u8 *macaddr, s16 vlan,
1370 bool is_vf, bool is_netdev)
1371{
1372 struct i40e_mac_filter *f;
1373
1374 if (!vsi || !macaddr)
1375 return;
1376
1377 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1378 if (!f || f->counter == 0)
1379 return;
1380
1381 if (is_vf) {
1382 if (f->is_vf) {
1383 f->is_vf = false;
1384 f->counter--;
1385 }
1386 } else if (is_netdev) {
1387 if (f->is_netdev) {
1388 f->is_netdev = false;
1389 f->counter--;
1390 }
1391 } else {
b40c82e6 1392 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff
JB		 1393 int min_f = 0;
1394 min_f += (f->is_vf ? 1 : 0);
1395 min_f += (f->is_netdev ? 1 : 0);
1396
1397 if (f->counter > min_f)
1398 f->counter--;
1399 }
1400
1401 /* counter == 0 tells sync_filters_subtask to
1402 * remove the filter from the firmware's list
1403 */
1404 if (f->counter == 0) {
1405 f->changed = true;
1406 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1407 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1408 }
1409}
1410
1411/**
1412 * i40e_set_mac - NDO callback to set mac address
1413 * @netdev: network interface device structure
1414 * @p: pointer to an address structure
1415 *
1416 * Returns 0 on success, negative on failure
1417 **/
38e00438
VD		 1418#ifdef I40E_FCOE
1419int i40e_set_mac(struct net_device *netdev, void *p)
1420#else
41c445ff 1421static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1422#endif
41c445ff
JB		 1423{
1424 struct i40e_netdev_priv *np = netdev_priv(netdev);
1425 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1426 struct i40e_pf *pf = vsi->back;
1427 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1428 struct sockaddr *addr = p;
1429 struct i40e_mac_filter *f;
1430
1431 if (!is_valid_ether_addr(addr->sa_data))
1432 return -EADDRNOTAVAIL;
1433
30650cc5
SN		 1434 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1435 netdev_info(netdev, "already using mac address %pM\n",
1436 addr->sa_data);
1437 return 0;
1438 }
41c445ff 1439
80f6428f
ASJ		 1440 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1441 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1442 return -EADDRNOTAVAIL;
1443
30650cc5
SN		 1444 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1445 netdev_info(netdev, "returning to hw mac address %pM\n",
1446 hw->mac.addr);
1447 else
1448 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1449
41c445ff
JB		 1450 if (vsi->type == I40E_VSI_MAIN) {
1451 i40e_status ret;
1452 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1453 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1454 addr->sa_data, NULL);
1455 if (ret) {
1456 netdev_info(netdev,
1457 "Addr change for Main VSI failed: %d\n",
1458 ret);
1459 return -EADDRNOTAVAIL;
1460 }
41c445ff
JB		 1461 }
1462
30650cc5
SN		 1463 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1464 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1465
30650cc5
SN		 1466 memset(&element, 0, sizeof(element));
1467 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1468 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1469 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1470 } else {
6c8ad1ba
SN		 1471 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1472 false, false);
6c8ad1ba 1473 }
41c445ff 1474
30650cc5
SN		 1475 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1476 struct i40e_aqc_add_macvlan_element_data element;
1477
1478 memset(&element, 0, sizeof(element));
1479 ether_addr_copy(element.mac_addr, hw->mac.addr);
1480 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1481 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1482 } else {
1483 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1484 false, false);
1485 if (f)
1486 f->is_laa = true;
1487 }
1488
1489 i40e_sync_vsi_filters(vsi);
1490 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1491
1492 return 0;
1493}
1494
1495/**
1496 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1497 * @vsi: the VSI being setup
1498 * @ctxt: VSI context structure
1499 * @enabled_tc: Enabled TCs bitmap
1500 * @is_add: True if called before Add VSI
1501 *
1502 * Setup VSI queue mapping for enabled traffic classes.
1503 **/
38e00438
VD		 1504#ifdef I40E_FCOE
1505void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1506 struct i40e_vsi_context *ctxt,
1507 u8 enabled_tc,
1508 bool is_add)
1509#else
41c445ff
JB		 1510static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1511 struct i40e_vsi_context *ctxt,
1512 u8 enabled_tc,
1513 bool is_add)
38e00438 1514#endif
41c445ff
JB		 1515{
1516 struct i40e_pf *pf = vsi->back;
1517 u16 sections = 0;
1518 u8 netdev_tc = 0;
1519 u16 numtc = 0;
1520 u16 qcount;
1521 u8 offset;
1522 u16 qmap;
1523 int i;
4e3b35b0 1524 u16 num_tc_qps = 0;
41c445ff
JB		 1525
1526 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1527 offset = 0;
1528
1529 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1530 /* Find numtc from enabled TC bitmap */
1531 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1532 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1533 numtc++;
1534 }
1535 if (!numtc) {
1536 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1537 numtc = 1;
1538 }
1539 } else {
1540 /* At least TC0 is enabled in case of non-DCB case */
1541 numtc = 1;
1542 }
1543
1544 vsi->tc_config.numtc = numtc;
1545 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1546 /* Number of queues per enabled TC */
7f9ff476
AS		 1547 /* In MFP case we can have a much lower count of MSIx
1548 * vectors available and so we need to lower the used
1549 * q count.
1550 */
1551 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1552 num_tc_qps = qcount / numtc;
4e3b35b0 1553 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1554
1555 /* Setup queue offset/count for all TCs for given VSI */
1556 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1557 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1558 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1559 /* TC is enabled */
41c445ff
JB		 1560 int pow, num_qps;
1561
41c445ff
JB		 1562 switch (vsi->type) {
1563 case I40E_VSI_MAIN:
4e3b35b0 1564 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1565 break;
38e00438
VD		 1566#ifdef I40E_FCOE
1567 case I40E_VSI_FCOE:
1568 qcount = num_tc_qps;
1569 break;
1570#endif
41c445ff
JB		 1571 case I40E_VSI_FDIR:
1572 case I40E_VSI_SRIOV:
1573 case I40E_VSI_VMDQ2:
1574 default:
4e3b35b0 1575 qcount = num_tc_qps;
41c445ff
JB		 1576 WARN_ON(i != 0);
1577 break;
1578 }
4e3b35b0
NP		 1579 vsi->tc_config.tc_info[i].qoffset = offset;
1580 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1581
1e200e4a 1582 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1583 num_qps = qcount;
41c445ff 1584 pow = 0;
41a1d04b 1585 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1586 pow++;
1587 num_qps >>= 1;
1588 }
1589
1590 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1591 qmap =
1592 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1593 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1594
4e3b35b0 1595 offset += qcount;
41c445ff
JB		 1596 } else {
1597 /* TC is not enabled so set the offset to
1598 * default queue and allocate one queue
1599 * for the given TC.
1600 */
1601 vsi->tc_config.tc_info[i].qoffset = 0;
1602 vsi->tc_config.tc_info[i].qcount = 1;
1603 vsi->tc_config.tc_info[i].netdev_tc = 0;
1604
1605 qmap = 0;
1606 }
1607 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1608 }
1609
1610 /* Set actual Tx/Rx queue pairs */
1611 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1612 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1613 if (vsi->req_queue_pairs > 0)
1614 vsi->num_queue_pairs = vsi->req_queue_pairs;
1615 else
1616 vsi->num_queue_pairs = pf->num_lan_msix;
1617 }
41c445ff
JB		 1618
1619 /* Scheduler section valid can only be set for ADD VSI */
1620 if (is_add) {
1621 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1622
1623 ctxt->info.up_enable_bits = enabled_tc;
1624 }
1625 if (vsi->type == I40E_VSI_SRIOV) {
1626 ctxt->info.mapping_flags |=
1627 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1628 for (i = 0; i < vsi->num_queue_pairs; i++)
1629 ctxt->info.queue_mapping[i] =
1630 cpu_to_le16(vsi->base_queue + i);
1631 } else {
1632 ctxt->info.mapping_flags |=
1633 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1634 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1635 }
1636 ctxt->info.valid_sections |= cpu_to_le16(sections);
1637}
1638
1639/**
1640 * i40e_set_rx_mode - NDO callback to set the netdev filters
1641 * @netdev: network interface device structure
1642 **/
38e00438
VD		 1643#ifdef I40E_FCOE
1644void i40e_set_rx_mode(struct net_device *netdev)
1645#else
41c445ff 1646static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1647#endif
41c445ff
JB		 1648{
1649 struct i40e_netdev_priv *np = netdev_priv(netdev);
1650 struct i40e_mac_filter *f, *ftmp;
1651 struct i40e_vsi *vsi = np->vsi;
1652 struct netdev_hw_addr *uca;
1653 struct netdev_hw_addr *mca;
1654 struct netdev_hw_addr *ha;
1655
1656 /* add addr if not already in the filter list */
1657 netdev_for_each_uc_addr(uca, netdev) {
1658 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1659 if (i40e_is_vsi_in_vlan(vsi))
1660 i40e_put_mac_in_vlan(vsi, uca->addr,
1661 false, true);
1662 else
1663 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1664 false, true);
1665 }
1666 }
1667
1668 netdev_for_each_mc_addr(mca, netdev) {
1669 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1670 if (i40e_is_vsi_in_vlan(vsi))
1671 i40e_put_mac_in_vlan(vsi, mca->addr,
1672 false, true);
1673 else
1674 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1675 false, true);
1676 }
1677 }
1678
1679 /* remove filter if not in netdev list */
1680 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1681 bool found = false;
1682
1683 if (!f->is_netdev)
1684 continue;
1685
1686 if (is_multicast_ether_addr(f->macaddr)) {
1687 netdev_for_each_mc_addr(mca, netdev) {
1688 if (ether_addr_equal(mca->addr, f->macaddr)) {
1689 found = true;
1690 break;
1691 }
1692 }
1693 } else {
1694 netdev_for_each_uc_addr(uca, netdev) {
1695 if (ether_addr_equal(uca->addr, f->macaddr)) {
1696 found = true;
1697 break;
1698 }
1699 }
1700
1701 for_each_dev_addr(netdev, ha) {
1702 if (ether_addr_equal(ha->addr, f->macaddr)) {
1703 found = true;
1704 break;
1705 }
1706 }
1707 }
1708 if (!found)
1709 i40e_del_filter(
1710 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1711 }
1712
1713 /* check for other flag changes */
1714 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1715 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1716 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1717 }
1718}
1719
1720/**
1721 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1722 * @vsi: ptr to the VSI
1723 *
1724 * Push any outstanding VSI filter changes through the AdminQ.
1725 *
1726 * Returns 0 or error value
1727 **/
1728int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1729{
1730 struct i40e_mac_filter *f, *ftmp;
1731 bool promisc_forced_on = false;
1732 bool add_happened = false;
1733 int filter_list_len = 0;
1734 u32 changed_flags = 0;
f1c7e72e 1735 i40e_status ret = 0;
41c445ff
JB		 1736 struct i40e_pf *pf;
1737 int num_add = 0;
1738 int num_del = 0;
f1c7e72e 1739 int aq_err = 0;
41c445ff
JB		 1740 u16 cmd_flags;
1741
1742 /* empty array typed pointers, kcalloc later */
1743 struct i40e_aqc_add_macvlan_element_data *add_list;
1744 struct i40e_aqc_remove_macvlan_element_data *del_list;
1745
1746 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1747 usleep_range(1000, 2000);
1748 pf = vsi->back;
1749
1750 if (vsi->netdev) {
1751 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1752 vsi->current_netdev_flags = vsi->netdev->flags;
1753 }
1754
1755 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1756 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1757
1758 filter_list_len = pf->hw.aq.asq_buf_size /
1759 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1760 del_list = kcalloc(filter_list_len,
1761 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1762 GFP_KERNEL);
1763 if (!del_list)
1764 return -ENOMEM;
1765
1766 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1767 if (!f->changed)
1768 continue;
1769
1770 if (f->counter != 0)
1771 continue;
1772 f->changed = false;
1773 cmd_flags = 0;
1774
1775 /* add to delete list */
9a173901 1776 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1777 del_list[num_del].vlan_tag =
1778 cpu_to_le16((u16)(f->vlan ==
1779 I40E_VLAN_ANY ? 0 : f->vlan));
1780
41c445ff
JB		 1781 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1782 del_list[num_del].flags = cmd_flags;
1783 num_del++;
1784
1785 /* unlink from filter list */
1786 list_del(&f->list);
1787 kfree(f);
1788
1789 /* flush a full buffer */
1790 if (num_del == filter_list_len) {
f1c7e72e
SN		 1791 ret = i40e_aq_remove_macvlan(&pf->hw,
1792 vsi->seid, del_list, num_del,
1793 NULL);
1794 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1795 num_del = 0;
1796 memset(del_list, 0, sizeof(*del_list));
1797
f1c7e72e 1798 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1799 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1800 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
1801 i40e_stat_str(&pf->hw, ret),
1802 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1803 }
1804 }
1805 if (num_del) {
f1c7e72e 1806 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff 1807 del_list, num_del, NULL);
f1c7e72e 1808 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1809 num_del = 0;
1810
f1c7e72e 1811 if (ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1812 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1813 "ignoring delete macvlan error, err %s aq_err %s\n",
1814 i40e_stat_str(&pf->hw, ret),
1815 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1816 }
1817
1818 kfree(del_list);
1819 del_list = NULL;
1820
1821 /* do all the adds now */
1822 filter_list_len = pf->hw.aq.asq_buf_size /
1823 sizeof(struct i40e_aqc_add_macvlan_element_data),
1824 add_list = kcalloc(filter_list_len,
1825 sizeof(struct i40e_aqc_add_macvlan_element_data),
1826 GFP_KERNEL);
1827 if (!add_list)
1828 return -ENOMEM;
1829
1830 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1831 if (!f->changed)
1832 continue;
1833
1834 if (f->counter == 0)
1835 continue;
1836 f->changed = false;
1837 add_happened = true;
1838 cmd_flags = 0;
1839
1840 /* add to add array */
9a173901 1841 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1842 add_list[num_add].vlan_tag =
1843 cpu_to_le16(
1844 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1845 add_list[num_add].queue_number = 0;
1846
1847 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1848 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1849 num_add++;
1850
1851 /* flush a full buffer */
1852 if (num_add == filter_list_len) {
f1c7e72e
SN		 1853 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1854 add_list, num_add,
1855 NULL);
1856 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1857 num_add = 0;
1858
f1c7e72e 1859 if (ret)
41c445ff
JB		 1860 break;
1861 memset(add_list, 0, sizeof(*add_list));
1862 }
1863 }
1864 if (num_add) {
f1c7e72e
SN		 1865 ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1866 add_list, num_add, NULL);
1867 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1868 num_add = 0;
1869 }
1870 kfree(add_list);
1871 add_list = NULL;
1872
f1c7e72e 1873 if (add_happened && ret && aq_err != I40E_AQ_RC_EINVAL) {
41c445ff 1874 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1875 "add filter failed, err %s aq_err %s\n",
1876 i40e_stat_str(&pf->hw, ret),
1877 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1878 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1879 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1880 &vsi->state)) {
1881 promisc_forced_on = true;
1882 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1883 &vsi->state);
1884 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1885 }
1886 }
1887 }
1888
1889 /* check for changes in promiscuous modes */
1890 if (changed_flags & IFF_ALLMULTI) {
1891 bool cur_multipromisc;
1892 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
f1c7e72e
SN		 1893 ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1894 vsi->seid,
1895 cur_multipromisc,
1896 NULL);
1897 if (ret)
41c445ff 1898 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1899 "set multi promisc failed, err %s aq_err %s\n",
1900 i40e_stat_str(&pf->hw, ret),
1901 i40e_aq_str(&pf->hw,
1902 pf->hw.aq.asq_last_status));
41c445ff
JB		 1903 }
1904 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1905 bool cur_promisc;
1906 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1907 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1908 &vsi->state));
f1c7e72e
SN		 1909 ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1910 vsi->seid,
1911 cur_promisc, NULL);
1912 if (ret)
41c445ff 1913 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1914 "set uni promisc failed, err %s, aq_err %s\n",
1915 i40e_stat_str(&pf->hw, ret),
1916 i40e_aq_str(&pf->hw,
1917 pf->hw.aq.asq_last_status));
1918 ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1919 vsi->seid,
1920 cur_promisc, NULL);
1921 if (ret)
1a10370a 1922 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 1923 "set brdcast promisc failed, err %s, aq_err %s\n",
1924 i40e_stat_str(&pf->hw, ret),
1925 i40e_aq_str(&pf->hw,
1926 pf->hw.aq.asq_last_status));
41c445ff
JB		 1927 }
1928
1929 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1930 return 0;
1931}
1932
1933/**
1934 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1935 * @pf: board private structure
1936 **/
1937static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1938{
1939 int v;
1940
1941 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1942 return;
1943 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1944
505682cd 1945 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1946 if (pf->vsi[v] &&
1947 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1948 i40e_sync_vsi_filters(pf->vsi[v]);
1949 }
1950}
1951
1952/**
1953 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1954 * @netdev: network interface device structure
1955 * @new_mtu: new value for maximum frame size
1956 *
1957 * Returns 0 on success, negative on failure
1958 **/
1959static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1960{
1961 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1962 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1963 struct i40e_vsi *vsi = np->vsi;
1964
1965 /* MTU < 68 is an error and causes problems on some kernels */
1966 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1967 return -EINVAL;
1968
1969 netdev_info(netdev, "changing MTU from %d to %d\n",
1970 netdev->mtu, new_mtu);
1971 netdev->mtu = new_mtu;
1972 if (netif_running(netdev))
1973 i40e_vsi_reinit_locked(vsi);
1974
1975 return 0;
1976}
1977
beb0dff1
JK		 1978/**
1979 * i40e_ioctl - Access the hwtstamp interface
1980 * @netdev: network interface device structure
1981 * @ifr: interface request data
1982 * @cmd: ioctl command
1983 **/
1984int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1985{
1986 struct i40e_netdev_priv *np = netdev_priv(netdev);
1987 struct i40e_pf *pf = np->vsi->back;
1988
1989 switch (cmd) {
1990 case SIOCGHWTSTAMP:
1991 return i40e_ptp_get_ts_config(pf, ifr);
1992 case SIOCSHWTSTAMP:
1993 return i40e_ptp_set_ts_config(pf, ifr);
1994 default:
1995 return -EOPNOTSUPP;
1996 }
1997}
1998
41c445ff
JB		 1999/**
2000 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2001 * @vsi: the vsi being adjusted
2002 **/
2003void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2004{
2005 struct i40e_vsi_context ctxt;
2006 i40e_status ret;
2007
2008 if ((vsi->info.valid_sections &
2009 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2010 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2011 return; /* already enabled */
2012
2013 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2014 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2015 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2016
2017 ctxt.seid = vsi->seid;
1a2f6248 2018 ctxt.info = vsi->info;
41c445ff
JB		 2019 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2020 if (ret) {
2021 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2022 "update vlan stripping failed, err %s aq_err %s\n",
2023 i40e_stat_str(&vsi->back->hw, ret),
2024 i40e_aq_str(&vsi->back->hw,
2025 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2026 }
2027}
2028
2029/**
2030 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2031 * @vsi: the vsi being adjusted
2032 **/
2033void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2034{
2035 struct i40e_vsi_context ctxt;
2036 i40e_status ret;
2037
2038 if ((vsi->info.valid_sections &
2039 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2040 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2041 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2042 return; /* already disabled */
2043
2044 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2045 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2046 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2047
2048 ctxt.seid = vsi->seid;
1a2f6248 2049 ctxt.info = vsi->info;
41c445ff
JB		 2050 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2051 if (ret) {
2052 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2053 "update vlan stripping failed, err %s aq_err %s\n",
2054 i40e_stat_str(&vsi->back->hw, ret),
2055 i40e_aq_str(&vsi->back->hw,
2056 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2057 }
2058}
2059
2060/**
2061 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2062 * @netdev: network interface to be adjusted
2063 * @features: netdev features to test if VLAN offload is enabled or not
2064 **/
2065static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2066{
2067 struct i40e_netdev_priv *np = netdev_priv(netdev);
2068 struct i40e_vsi *vsi = np->vsi;
2069
2070 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2071 i40e_vlan_stripping_enable(vsi);
2072 else
2073 i40e_vlan_stripping_disable(vsi);
2074}
2075
2076/**
2077 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2078 * @vsi: the vsi being configured
2079 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2080 **/
2081int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2082{
2083 struct i40e_mac_filter *f, *add_f;
2084 bool is_netdev, is_vf;
41c445ff
JB		 2085
2086 is_vf = (vsi->type == I40E_VSI_SRIOV);
2087 is_netdev = !!(vsi->netdev);
2088
2089 if (is_netdev) {
2090 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2091 is_vf, is_netdev);
2092 if (!add_f) {
2093 dev_info(&vsi->back->pdev->dev,
2094 "Could not add vlan filter %d for %pM\n",
2095 vid, vsi->netdev->dev_addr);
2096 return -ENOMEM;
2097 }
2098 }
2099
2100 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2101 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2102 if (!add_f) {
2103 dev_info(&vsi->back->pdev->dev,
2104 "Could not add vlan filter %d for %pM\n",
2105 vid, f->macaddr);
2106 return -ENOMEM;
2107 }
2108 }
2109
41c445ff
JB		 2110 /* Now if we add a vlan tag, make sure to check if it is the first
2111 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2112 * with 0, so we now accept untagged and specified tagged traffic
2113 * (and not any taged and untagged)
2114 */
2115 if (vid > 0) {
2116 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2117 I40E_VLAN_ANY,
2118 is_vf, is_netdev)) {
2119 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2120 I40E_VLAN_ANY, is_vf, is_netdev);
2121 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2122 is_vf, is_netdev);
2123 if (!add_f) {
2124 dev_info(&vsi->back->pdev->dev,
2125 "Could not add filter 0 for %pM\n",
2126 vsi->netdev->dev_addr);
2127 return -ENOMEM;
2128 }
2129 }
8d82a7c5 2130 }
41c445ff 2131
8d82a7c5
GR		 2132 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2133 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2134 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2135 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2136 is_vf, is_netdev)) {
2137 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2138 is_vf, is_netdev);
2139 add_f = i40e_add_filter(vsi, f->macaddr,
2140 0, is_vf, is_netdev);
2141 if (!add_f) {
2142 dev_info(&vsi->back->pdev->dev,
2143 "Could not add filter 0 for %pM\n",
2144 f->macaddr);
2145 return -ENOMEM;
2146 }
2147 }
2148 }
41c445ff
JB		 2149 }
2150
80f6428f
ASJ		 2151 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2152 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2153 return 0;
2154
2155 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2156}
2157
2158/**
2159 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2160 * @vsi: the vsi being configured
2161 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2162 *
2163 * Return: 0 on success or negative otherwise
41c445ff
JB		 2164 **/
2165int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2166{
2167 struct net_device *netdev = vsi->netdev;
2168 struct i40e_mac_filter *f, *add_f;
2169 bool is_vf, is_netdev;
2170 int filter_count = 0;
41c445ff
JB		 2171
2172 is_vf = (vsi->type == I40E_VSI_SRIOV);
2173 is_netdev = !!(netdev);
2174
2175 if (is_netdev)
2176 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2177
2178 list_for_each_entry(f, &vsi->mac_filter_list, list)
2179 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2180
41c445ff
JB		 2181 /* go through all the filters for this VSI and if there is only
2182 * vid == 0 it means there are no other filters, so vid 0 must
2183 * be replaced with -1. This signifies that we should from now
2184 * on accept any traffic (with any tag present, or untagged)
2185 */
2186 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2187 if (is_netdev) {
2188 if (f->vlan &&
2189 ether_addr_equal(netdev->dev_addr, f->macaddr))
2190 filter_count++;
2191 }
2192
2193 if (f->vlan)
2194 filter_count++;
2195 }
2196
2197 if (!filter_count && is_netdev) {
2198 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2199 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2200 is_vf, is_netdev);
2201 if (!f) {
2202 dev_info(&vsi->back->pdev->dev,
2203 "Could not add filter %d for %pM\n",
2204 I40E_VLAN_ANY, netdev->dev_addr);
2205 return -ENOMEM;
2206 }
2207 }
2208
2209 if (!filter_count) {
2210 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2211 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2212 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2213 is_vf, is_netdev);
2214 if (!add_f) {
2215 dev_info(&vsi->back->pdev->dev,
2216 "Could not add filter %d for %pM\n",
2217 I40E_VLAN_ANY, f->macaddr);
2218 return -ENOMEM;
2219 }
2220 }
2221 }
2222
80f6428f
ASJ		 2223 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2224 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2225 return 0;
2226
41c445ff
JB		 2227 return i40e_sync_vsi_filters(vsi);
2228}
2229
2230/**
2231 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2232 * @netdev: network interface to be adjusted
2233 * @vid: vlan id to be added
078b5876
JB		 2234 *
2235 * net_device_ops implementation for adding vlan ids
41c445ff 2236 **/
38e00438
VD		 2237#ifdef I40E_FCOE
2238int i40e_vlan_rx_add_vid(struct net_device *netdev,
2239 __always_unused __be16 proto, u16 vid)
2240#else
41c445ff
JB		 2241static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2242 __always_unused __be16 proto, u16 vid)
38e00438 2243#endif
41c445ff
JB		 2244{
2245 struct i40e_netdev_priv *np = netdev_priv(netdev);
2246 struct i40e_vsi *vsi = np->vsi;
078b5876 2247 int ret = 0;
41c445ff
JB		 2248
2249 if (vid > 4095)
078b5876
JB		 2250 return -EINVAL;
2251
2252 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2253
6982d429
ASJ		 2254 /* If the network stack called us with vid = 0 then
2255 * it is asking to receive priority tagged packets with
2256 * vlan id 0. Our HW receives them by default when configured
2257 * to receive untagged packets so there is no need to add an
2258 * extra filter for vlan 0 tagged packets.
41c445ff 2259 */
6982d429
ASJ		 2260 if (vid)
2261 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2262
078b5876
JB		 2263 if (!ret && (vid < VLAN_N_VID))
2264 set_bit(vid, vsi->active_vlans);
41c445ff 2265
078b5876 2266 return ret;
41c445ff
JB		 2267}
2268
2269/**
2270 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2271 * @netdev: network interface to be adjusted
2272 * @vid: vlan id to be removed
078b5876 2273 *
fdfd943e 2274 * net_device_ops implementation for removing vlan ids
41c445ff 2275 **/
38e00438
VD		 2276#ifdef I40E_FCOE
2277int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2278 __always_unused __be16 proto, u16 vid)
2279#else
41c445ff
JB		 2280static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2281 __always_unused __be16 proto, u16 vid)
38e00438 2282#endif
41c445ff
JB		 2283{
2284 struct i40e_netdev_priv *np = netdev_priv(netdev);
2285 struct i40e_vsi *vsi = np->vsi;
2286
078b5876
JB		 2287 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2288
41c445ff
JB		 2289 /* return code is ignored as there is nothing a user
2290 * can do about failure to remove and a log message was
078b5876 2291 * already printed from the other function
41c445ff
JB		 2292 */
2293 i40e_vsi_kill_vlan(vsi, vid);
2294
2295 clear_bit(vid, vsi->active_vlans);
078b5876 2296
41c445ff
JB		 2297 return 0;
2298}
2299
2300/**
2301 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2302 * @vsi: the vsi being brought back up
2303 **/
2304static void i40e_restore_vlan(struct i40e_vsi *vsi)
2305{
2306 u16 vid;
2307
2308 if (!vsi->netdev)
2309 return;
2310
2311 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2312
2313 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2314 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2315 vid);
2316}
2317
2318/**
2319 * i40e_vsi_add_pvid - Add pvid for the VSI
2320 * @vsi: the vsi being adjusted
2321 * @vid: the vlan id to set as a PVID
2322 **/
dcae29be 2323int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2324{
2325 struct i40e_vsi_context ctxt;
f1c7e72e 2326 i40e_status ret;
41c445ff
JB		 2327
2328 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2329 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2330 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2331 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2332 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2333
2334 ctxt.seid = vsi->seid;
1a2f6248 2335 ctxt.info = vsi->info;
f1c7e72e
SN		 2336 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2337 if (ret) {
41c445ff 2338 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2339 "add pvid failed, err %s aq_err %s\n",
2340 i40e_stat_str(&vsi->back->hw, ret),
2341 i40e_aq_str(&vsi->back->hw,
2342 vsi->back->hw.aq.asq_last_status));
dcae29be 2343 return -ENOENT;
41c445ff
JB		 2344 }
2345
dcae29be 2346 return 0;
41c445ff
JB		 2347}
2348
2349/**
2350 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2351 * @vsi: the vsi being adjusted
2352 *
2353 * Just use the vlan_rx_register() service to put it back to normal
2354 **/
2355void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2356{
6c12fcbf
GR		 2357 i40e_vlan_stripping_disable(vsi);
2358
41c445ff 2359 vsi->info.pvid = 0;
41c445ff
JB		 2360}
2361
2362/**
2363 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2364 * @vsi: ptr to the VSI
2365 *
2366 * If this function returns with an error, then it's possible one or
2367 * more of the rings is populated (while the rest are not). It is the
2368 * callers duty to clean those orphaned rings.
2369 *
2370 * Return 0 on success, negative on failure
2371 **/
2372static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2373{
2374 int i, err = 0;
2375
2376 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2377 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2378
2379 return err;
2380}
2381
2382/**
2383 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2384 * @vsi: ptr to the VSI
2385 *
2386 * Free VSI's transmit software resources
2387 **/
2388static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2389{
2390 int i;
2391
8e9dca53
GR		 2392 if (!vsi->tx_rings)
2393 return;
2394
41c445ff 2395 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2396 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2397 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2398}
2399
2400/**
2401 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2402 * @vsi: ptr to the VSI
2403 *
2404 * If this function returns with an error, then it's possible one or
2405 * more of the rings is populated (while the rest are not). It is the
2406 * callers duty to clean those orphaned rings.
2407 *
2408 * Return 0 on success, negative on failure
2409 **/
2410static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2411{
2412 int i, err = 0;
2413
2414 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2415 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2416#ifdef I40E_FCOE
2417 i40e_fcoe_setup_ddp_resources(vsi);
2418#endif
41c445ff
JB		 2419 return err;
2420}
2421
2422/**
2423 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2424 * @vsi: ptr to the VSI
2425 *
2426 * Free all receive software resources
2427 **/
2428static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2429{
2430 int i;
2431
8e9dca53
GR		 2432 if (!vsi->rx_rings)
2433 return;
2434
41c445ff 2435 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2436 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2437 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2438#ifdef I40E_FCOE
2439 i40e_fcoe_free_ddp_resources(vsi);
2440#endif
41c445ff
JB		 2441}
2442
3ffa037d
NP		 2443/**
2444 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2445 * @ring: The Tx ring to configure
2446 *
2447 * This enables/disables XPS for a given Tx descriptor ring
2448 * based on the TCs enabled for the VSI that ring belongs to.
2449 **/
2450static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2451{
2452 struct i40e_vsi *vsi = ring->vsi;
2453 cpumask_var_t mask;
2454
9a660eea
JB		 2455 if (!ring->q_vector || !ring->netdev)
2456 return;
2457
2458 /* Single TC mode enable XPS */
2459 if (vsi->tc_config.numtc <= 1) {
2460 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2461 netif_set_xps_queue(ring->netdev,
2462 &ring->q_vector->affinity_mask,
2463 ring->queue_index);
9a660eea
JB		 2464 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2465 /* Disable XPS to allow selection based on TC */
2466 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2467 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2468 free_cpumask_var(mask);
3ffa037d
NP		 2469 }
2470}
2471
41c445ff
JB		 2472/**
2473 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2474 * @ring: The Tx ring to configure
2475 *
2476 * Configure the Tx descriptor ring in the HMC context.
2477 **/
2478static int i40e_configure_tx_ring(struct i40e_ring *ring)
2479{
2480 struct i40e_vsi *vsi = ring->vsi;
2481 u16 pf_q = vsi->base_queue + ring->queue_index;
2482 struct i40e_hw *hw = &vsi->back->hw;
2483 struct i40e_hmc_obj_txq tx_ctx;
2484 i40e_status err = 0;
2485 u32 qtx_ctl = 0;
2486
2487 /* some ATR related tx ring init */
60ea5f83 2488 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2489 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2490 ring->atr_count = 0;
2491 } else {
2492 ring->atr_sample_rate = 0;
2493 }
2494
3ffa037d
NP		 2495 /* configure XPS */
2496 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2497
2498 /* clear the context structure first */
2499 memset(&tx_ctx, 0, sizeof(tx_ctx));
2500
2501 tx_ctx.new_context = 1;
2502 tx_ctx.base = (ring->dma / 128);
2503 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2504 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2505 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2506#ifdef I40E_FCOE
2507 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2508#endif
beb0dff1 2509 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2510 /* FDIR VSI tx ring can still use RS bit and writebacks */
2511 if (vsi->type != I40E_VSI_FDIR)
2512 tx_ctx.head_wb_ena = 1;
2513 tx_ctx.head_wb_addr = ring->dma +
2514 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2515
2516 /* As part of VSI creation/update, FW allocates certain
2517 * Tx arbitration queue sets for each TC enabled for
2518 * the VSI. The FW returns the handles to these queue
2519 * sets as part of the response buffer to Add VSI,
2520 * Update VSI, etc. AQ commands. It is expected that
2521 * these queue set handles be associated with the Tx
2522 * queues by the driver as part of the TX queue context
2523 * initialization. This has to be done regardless of
2524 * DCB as by default everything is mapped to TC0.
2525 */
2526 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2527 tx_ctx.rdylist_act = 0;
2528
2529 /* clear the context in the HMC */
2530 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2531 if (err) {
2532 dev_info(&vsi->back->pdev->dev,
2533 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2534 ring->queue_index, pf_q, err);
2535 return -ENOMEM;
2536 }
2537
2538 /* set the context in the HMC */
2539 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2540 if (err) {
2541 dev_info(&vsi->back->pdev->dev,
2542 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2543 ring->queue_index, pf_q, err);
2544 return -ENOMEM;
2545 }
2546
2547 /* Now associate this queue with this PCI function */
7a28d885 2548 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2549 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2550 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2551 I40E_QTX_CTL_VFVM_INDX_MASK;
2552 } else {
9d8bf547 2553 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2554 }
2555
13fd9774
SN		 2556 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2557 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2558 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2559 i40e_flush(hw);
2560
2561 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2562
2563 /* cache tail off for easier writes later */
2564 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2565
2566 return 0;
2567}
2568
2569/**
2570 * i40e_configure_rx_ring - Configure a receive ring context
2571 * @ring: The Rx ring to configure
2572 *
2573 * Configure the Rx descriptor ring in the HMC context.
2574 **/
2575static int i40e_configure_rx_ring(struct i40e_ring *ring)
2576{
2577 struct i40e_vsi *vsi = ring->vsi;
2578 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2579 u16 pf_q = vsi->base_queue + ring->queue_index;
2580 struct i40e_hw *hw = &vsi->back->hw;
2581 struct i40e_hmc_obj_rxq rx_ctx;
2582 i40e_status err = 0;
2583
2584 ring->state = 0;
2585
2586 /* clear the context structure first */
2587 memset(&rx_ctx, 0, sizeof(rx_ctx));
2588
2589 ring->rx_buf_len = vsi->rx_buf_len;
2590 ring->rx_hdr_len = vsi->rx_hdr_len;
2591
2592 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2593 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2594
2595 rx_ctx.base = (ring->dma / 128);
2596 rx_ctx.qlen = ring->count;
2597
2598 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2599 set_ring_16byte_desc_enabled(ring);
2600 rx_ctx.dsize = 0;
2601 } else {
2602 rx_ctx.dsize = 1;
2603 }
2604
2605 rx_ctx.dtype = vsi->dtype;
2606 if (vsi->dtype) {
2607 set_ring_ps_enabled(ring);
2608 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2609 I40E_RX_SPLIT_IP |
2610 I40E_RX_SPLIT_TCP_UDP |
2611 I40E_RX_SPLIT_SCTP;
2612 } else {
2613 rx_ctx.hsplit_0 = 0;
2614 }
2615
2616 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2617 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2618 if (hw->revision_id == 0)
2619 rx_ctx.lrxqthresh = 0;
2620 else
2621 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2622 rx_ctx.crcstrip = 1;
2623 rx_ctx.l2tsel = 1;
2624 rx_ctx.showiv = 1;
38e00438
VD		 2625#ifdef I40E_FCOE
2626 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2627#endif
acb3676b
CS		 2628 /* set the prefena field to 1 because the manual says to */
2629 rx_ctx.prefena = 1;
41c445ff
JB		 2630
2631 /* clear the context in the HMC */
2632 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2633 if (err) {
2634 dev_info(&vsi->back->pdev->dev,
2635 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2636 ring->queue_index, pf_q, err);
2637 return -ENOMEM;
2638 }
2639
2640 /* set the context in the HMC */
2641 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2642 if (err) {
2643 dev_info(&vsi->back->pdev->dev,
2644 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2645 ring->queue_index, pf_q, err);
2646 return -ENOMEM;
2647 }
2648
2649 /* cache tail for quicker writes, and clear the reg before use */
2650 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2651 writel(0, ring->tail);
2652
a132af24
MW		 2653 if (ring_is_ps_enabled(ring)) {
2654 i40e_alloc_rx_headers(ring);
2655 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2656 } else {
2657 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2658 }
41c445ff
JB		 2659
2660 return 0;
2661}
2662
2663/**
2664 * i40e_vsi_configure_tx - Configure the VSI for Tx
2665 * @vsi: VSI structure describing this set of rings and resources
2666 *
2667 * Configure the Tx VSI for operation.
2668 **/
2669static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2670{
2671 int err = 0;
2672 u16 i;
2673
9f65e15b
AD		 2674 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2675 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2676
2677 return err;
2678}
2679
2680/**
2681 * i40e_vsi_configure_rx - Configure the VSI for Rx
2682 * @vsi: the VSI being configured
2683 *
2684 * Configure the Rx VSI for operation.
2685 **/
2686static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2687{
2688 int err = 0;
2689 u16 i;
2690
2691 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2692 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2693 + ETH_FCS_LEN + VLAN_HLEN;
2694 else
2695 vsi->max_frame = I40E_RXBUFFER_2048;
2696
2697 /* figure out correct receive buffer length */
2698 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2699 I40E_FLAG_RX_PS_ENABLED)) {
2700 case I40E_FLAG_RX_1BUF_ENABLED:
2701 vsi->rx_hdr_len = 0;
2702 vsi->rx_buf_len = vsi->max_frame;
2703 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2704 break;
2705 case I40E_FLAG_RX_PS_ENABLED:
2706 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2707 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2708 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2709 break;
2710 default:
2711 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2712 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2713 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2714 break;
2715 }
2716
38e00438
VD		 2717#ifdef I40E_FCOE
2718 /* setup rx buffer for FCoE */
2719 if ((vsi->type == I40E_VSI_FCOE) &&
2720 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2721 vsi->rx_hdr_len = 0;
2722 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2723 vsi->max_frame = I40E_RXBUFFER_3072;
2724 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2725 }
2726
2727#endif /* I40E_FCOE */
41c445ff
JB		 2728 /* round up for the chip's needs */
2729 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2730 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2731 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2732 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2733
2734 /* set up individual rings */
2735 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2736 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2737
2738 return err;
2739}
2740
2741/**
2742 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2743 * @vsi: ptr to the VSI
2744 **/
2745static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2746{
e7046ee1 2747 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2748 u16 qoffset, qcount;
2749 int i, n;
2750
cd238a3e
PN		 2751 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2752 /* Reset the TC information */
2753 for (i = 0; i < vsi->num_queue_pairs; i++) {
2754 rx_ring = vsi->rx_rings[i];
2755 tx_ring = vsi->tx_rings[i];
2756 rx_ring->dcb_tc = 0;
2757 tx_ring->dcb_tc = 0;
2758 }
2759 }
41c445ff
JB		 2760
2761 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2762 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2763 continue;
2764
2765 qoffset = vsi->tc_config.tc_info[n].qoffset;
2766 qcount = vsi->tc_config.tc_info[n].qcount;
2767 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2768 rx_ring = vsi->rx_rings[i];
2769 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2770 rx_ring->dcb_tc = n;
2771 tx_ring->dcb_tc = n;
2772 }
2773 }
2774}
2775
2776/**
2777 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2778 * @vsi: ptr to the VSI
2779 **/
2780static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2781{
2782 if (vsi->netdev)
2783 i40e_set_rx_mode(vsi->netdev);
2784}
2785
17a73f6b
JG		 2786/**
2787 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2788 * @vsi: Pointer to the targeted VSI
2789 *
2790 * This function replays the hlist on the hw where all the SB Flow Director
2791 * filters were saved.
2792 **/
2793static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2794{
2795 struct i40e_fdir_filter *filter;
2796 struct i40e_pf *pf = vsi->back;
2797 struct hlist_node *node;
2798
55a5e60b
ASJ		 2799 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2800 return;
2801
17a73f6b
JG		 2802 hlist_for_each_entry_safe(filter, node,
2803 &pf->fdir_filter_list, fdir_node) {
2804 i40e_add_del_fdir(vsi, filter, true);
2805 }
2806}
2807
41c445ff
JB		 2808/**
2809 * i40e_vsi_configure - Set up the VSI for action
2810 * @vsi: the VSI being configured
2811 **/
2812static int i40e_vsi_configure(struct i40e_vsi *vsi)
2813{
2814 int err;
2815
2816 i40e_set_vsi_rx_mode(vsi);
2817 i40e_restore_vlan(vsi);
2818 i40e_vsi_config_dcb_rings(vsi);
2819 err = i40e_vsi_configure_tx(vsi);
2820 if (!err)
2821 err = i40e_vsi_configure_rx(vsi);
2822
2823 return err;
2824}
2825
2826/**
2827 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2828 * @vsi: the VSI being configured
2829 **/
2830static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2831{
2832 struct i40e_pf *pf = vsi->back;
2833 struct i40e_q_vector *q_vector;
2834 struct i40e_hw *hw = &pf->hw;
2835 u16 vector;
2836 int i, q;
2837 u32 val;
2838 u32 qp;
2839
2840 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2841 * and PFINT_LNKLSTn registers, e.g.:
2842 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2843 */
2844 qp = vsi->base_queue;
2845 vector = vsi->base_vector;
493fb300
AD		 2846 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2847 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2848 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2849 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2850 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2851 q_vector->rx.itr);
2852 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2853 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2854 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2855 q_vector->tx.itr);
2856
2857 /* Linked list for the queuepairs assigned to this vector */
2858 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2859 for (q = 0; q < q_vector->num_ringpairs; q++) {
2860 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2861 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2862 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2863 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2864 (I40E_QUEUE_TYPE_TX
2865 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2866
2867 wr32(hw, I40E_QINT_RQCTL(qp), val);
2868
2869 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2870 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2871 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2872 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2873 (I40E_QUEUE_TYPE_RX
2874 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2875
2876 /* Terminate the linked list */
2877 if (q == (q_vector->num_ringpairs - 1))
2878 val |= (I40E_QUEUE_END_OF_LIST
2879 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2880
2881 wr32(hw, I40E_QINT_TQCTL(qp), val);
2882 qp++;
2883 }
2884 }
2885
2886 i40e_flush(hw);
2887}
2888
2889/**
2890 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2891 * @hw: ptr to the hardware info
2892 **/
ab437b5a 2893static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2894{
ab437b5a 2895 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2896 u32 val;
2897
2898 /* clear things first */
2899 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2900 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2901
2902 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2903 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2904 I40E_PFINT_ICR0_ENA_GRST_MASK |
2905 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2906 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2907 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2908 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2909 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2910
ab437b5a
JK		 2911 if (pf->flags & I40E_FLAG_PTP)
2912 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2913
41c445ff
JB		 2914 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2915
2916 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2917 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2918 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2919
2920 /* OTHER_ITR_IDX = 0 */
2921 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2922}
2923
2924/**
2925 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2926 * @vsi: the VSI being configured
2927 **/
2928static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2929{
493fb300 2930 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2931 struct i40e_pf *pf = vsi->back;
2932 struct i40e_hw *hw = &pf->hw;
2933 u32 val;
2934
2935 /* set the ITR configuration */
2936 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2937 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2938 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2939 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2940 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2941 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2942
ab437b5a 2943 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 2944
2945 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2946 wr32(hw, I40E_PFINT_LNKLST0, 0);
2947
f29eaa3d 2948 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2949 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2950 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2951 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2952
2953 wr32(hw, I40E_QINT_RQCTL(0), val);
2954
2955 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2956 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2957 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2958
2959 wr32(hw, I40E_QINT_TQCTL(0), val);
2960 i40e_flush(hw);
2961}
2962
2ef28cfb
MW		 2963/**
2964 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2965 * @pf: board private structure
2966 **/
2967void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2968{
2969 struct i40e_hw *hw = &pf->hw;
2970
2971 wr32(hw, I40E_PFINT_DYN_CTL0,
2972 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2973 i40e_flush(hw);
2974}
2975
41c445ff
JB		 2976/**
2977 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2978 * @pf: board private structure
2979 **/
116a57d4 2980void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2981{
2982 struct i40e_hw *hw = &pf->hw;
2983 u32 val;
2984
2985 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2986 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2987 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2988
2989 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2990 i40e_flush(hw);
2991}
2992
2993/**
2994 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2995 * @vsi: pointer to a vsi
2996 * @vector: enable a particular Hw Interrupt vector
2997 **/
2998void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2999{
3000 struct i40e_pf *pf = vsi->back;
3001 struct i40e_hw *hw = &pf->hw;
3002 u32 val;
3003
3004 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
3005 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
3006 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3007 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 3008 /* skip the flush */
41c445ff
JB		 3009}
3010
5c2cebda
CW		 3011/**
3012 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3013 * @vsi: pointer to a vsi
03147773 3014 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3015 **/
3016void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3017{
3018 struct i40e_pf *pf = vsi->back;
3019 struct i40e_hw *hw = &pf->hw;
3020 u32 val;
3021
3022 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3023 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3024 i40e_flush(hw);
3025}
3026
41c445ff
JB		 3027/**
3028 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3029 * @irq: interrupt number
3030 * @data: pointer to a q_vector
3031 **/
3032static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3033{
3034 struct i40e_q_vector *q_vector = data;
3035
cd0b6fa6 3036 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3037 return IRQ_HANDLED;
3038
3039 napi_schedule(&q_vector->napi);
3040
3041 return IRQ_HANDLED;
3042}
3043
41c445ff
JB		 3044/**
3045 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3046 * @vsi: the VSI being configured
3047 * @basename: name for the vector
3048 *
3049 * Allocates MSI-X vectors and requests interrupts from the kernel.
3050 **/
3051static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3052{
3053 int q_vectors = vsi->num_q_vectors;
3054 struct i40e_pf *pf = vsi->back;
3055 int base = vsi->base_vector;
3056 int rx_int_idx = 0;
3057 int tx_int_idx = 0;
3058 int vector, err;
3059
3060 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3061 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3062
cd0b6fa6 3063 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3064 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3065 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3066 tx_int_idx++;
cd0b6fa6 3067 } else if (q_vector->rx.ring) {
41c445ff
JB		 3068 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3069 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3070 } else if (q_vector->tx.ring) {
41c445ff
JB		 3071 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3072 "%s-%s-%d", basename, "tx", tx_int_idx++);
3073 } else {
3074 /* skip this unused q_vector */
3075 continue;
3076 }
3077 err = request_irq(pf->msix_entries[base + vector].vector,
3078 vsi->irq_handler,
3079 0,
3080 q_vector->name,
3081 q_vector);
3082 if (err) {
3083 dev_info(&pf->pdev->dev,
3084 "%s: request_irq failed, error: %d\n",
3085 __func__, err);
3086 goto free_queue_irqs;
3087 }
3088 /* assign the mask for this irq */
3089 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3090 &q_vector->affinity_mask);
3091 }
3092
63741846 3093 vsi->irqs_ready = true;
41c445ff
JB		 3094 return 0;
3095
3096free_queue_irqs:
3097 while (vector) {
3098 vector--;
3099 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3100 NULL);
3101 free_irq(pf->msix_entries[base + vector].vector,
3102 &(vsi->q_vectors[vector]));
3103 }
3104 return err;
3105}
3106
3107/**
3108 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3109 * @vsi: the VSI being un-configured
3110 **/
3111static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3112{
3113 struct i40e_pf *pf = vsi->back;
3114 struct i40e_hw *hw = &pf->hw;
3115 int base = vsi->base_vector;
3116 int i;
3117
3118 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3119 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3120 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3121 }
3122
3123 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3124 for (i = vsi->base_vector;
3125 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3126 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3127
3128 i40e_flush(hw);
3129 for (i = 0; i < vsi->num_q_vectors; i++)
3130 synchronize_irq(pf->msix_entries[i + base].vector);
3131 } else {
3132 /* Legacy and MSI mode - this stops all interrupt handling */
3133 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3134 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3135 i40e_flush(hw);
3136 synchronize_irq(pf->pdev->irq);
3137 }
3138}
3139
3140/**
3141 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3142 * @vsi: the VSI being configured
3143 **/
3144static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3145{
3146 struct i40e_pf *pf = vsi->back;
3147 int i;
3148
3149 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3150 for (i = vsi->base_vector;
3151 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3152 i40e_irq_dynamic_enable(vsi, i);
3153 } else {
3154 i40e_irq_dynamic_enable_icr0(pf);
3155 }
3156
1022cb6c 3157 i40e_flush(&pf->hw);
41c445ff
JB		 3158 return 0;
3159}
3160
3161/**
3162 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3163 * @pf: board private structure
3164 **/
3165static void i40e_stop_misc_vector(struct i40e_pf *pf)
3166{
3167 /* Disable ICR 0 */
3168 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3169 i40e_flush(&pf->hw);
3170}
3171
3172/**
3173 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3174 * @irq: interrupt number
3175 * @data: pointer to a q_vector
3176 *
3177 * This is the handler used for all MSI/Legacy interrupts, and deals
3178 * with both queue and non-queue interrupts. This is also used in
3179 * MSIX mode to handle the non-queue interrupts.
3180 **/
3181static irqreturn_t i40e_intr(int irq, void *data)
3182{
3183 struct i40e_pf *pf = (struct i40e_pf *)data;
3184 struct i40e_hw *hw = &pf->hw;
5e823066 3185 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3186 u32 icr0, icr0_remaining;
3187 u32 val, ena_mask;
3188
3189 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3190 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3191
116a57d4
SN		 3192 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3193 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3194 goto enable_intr;
41c445ff 3195
cd92e72f
SN		 3196 /* if interrupt but no bits showing, must be SWINT */
3197 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3198 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3199 pf->sw_int_count++;
3200
41c445ff
JB		 3201 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3202 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3203
3204 /* temporarily disable queue cause for NAPI processing */
3205 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3206 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3207 wr32(hw, I40E_QINT_RQCTL(0), qval);
3208
3209 qval = rd32(hw, I40E_QINT_TQCTL(0));
3210 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3211 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3212
3213 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3214 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3215 }
3216
3217 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3218 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3219 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3220 }
3221
3222 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3223 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3224 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3225 }
3226
3227 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3228 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3229 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3230 }
3231
3232 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3233 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3234 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3235 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3236 val = rd32(hw, I40E_GLGEN_RSTAT);
3237 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3238 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3239 if (val == I40E_RESET_CORER) {
41c445ff 3240 pf->corer_count++;
4eb3f768 3241 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3242 pf->globr_count++;
4eb3f768 3243 } else if (val == I40E_RESET_EMPR) {
41c445ff 3244 pf->empr_count++;
9df42d1a 3245 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3246 }
41c445ff
JB		 3247 }
3248
9c010ee0
ASJ		 3249 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3250 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3251 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3252 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3253 rd32(hw, I40E_PFHMC_ERRORINFO),
3254 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3255 }
3256
beb0dff1
JK		 3257 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3258 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3259
3260 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3261 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3262 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3263 }
beb0dff1
JK		 3264 }
3265
41c445ff
JB		 3266 /* If a critical error is pending we have no choice but to reset the
3267 * device.
3268 * Report and mask out any remaining unexpected interrupts.
3269 */
3270 icr0_remaining = icr0 & ena_mask;
3271 if (icr0_remaining) {
3272 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3273 icr0_remaining);
9c010ee0 3274 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3275 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3276 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3277 dev_info(&pf->pdev->dev, "device will be reset\n");
3278 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3279 i40e_service_event_schedule(pf);
41c445ff
JB		 3280 }
3281 ena_mask &= ~icr0_remaining;
3282 }
5e823066 3283 ret = IRQ_HANDLED;
41c445ff 3284
5e823066 3285enable_intr:
41c445ff
JB		 3286 /* re-enable interrupt causes */
3287 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3288 if (!test_bit(__I40E_DOWN, &pf->state)) {
3289 i40e_service_event_schedule(pf);
3290 i40e_irq_dynamic_enable_icr0(pf);
3291 }
3292
5e823066 3293 return ret;
41c445ff
JB		 3294}
3295
cbf61325
ASJ		 3296/**
3297 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3298 * @tx_ring: tx ring to clean
3299 * @budget: how many cleans we're allowed
3300 *
3301 * Returns true if there's any budget left (e.g. the clean is finished)
3302 **/
3303static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3304{
3305 struct i40e_vsi *vsi = tx_ring->vsi;
3306 u16 i = tx_ring->next_to_clean;
3307 struct i40e_tx_buffer *tx_buf;
3308 struct i40e_tx_desc *tx_desc;
3309
3310 tx_buf = &tx_ring->tx_bi[i];
3311 tx_desc = I40E_TX_DESC(tx_ring, i);
3312 i -= tx_ring->count;
3313
3314 do {
3315 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3316
3317 /* if next_to_watch is not set then there is no work pending */
3318 if (!eop_desc)
3319 break;
3320
3321 /* prevent any other reads prior to eop_desc */
3322 read_barrier_depends();
3323
3324 /* if the descriptor isn't done, no work yet to do */
3325 if (!(eop_desc->cmd_type_offset_bsz &
3326 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3327 break;
3328
3329 /* clear next_to_watch to prevent false hangs */
3330 tx_buf->next_to_watch = NULL;
3331
49d7d933
ASJ		 3332 tx_desc->buffer_addr = 0;
3333 tx_desc->cmd_type_offset_bsz = 0;
3334 /* move past filter desc */
3335 tx_buf++;
3336 tx_desc++;
3337 i++;
3338 if (unlikely(!i)) {
3339 i -= tx_ring->count;
3340 tx_buf = tx_ring->tx_bi;
3341 tx_desc = I40E_TX_DESC(tx_ring, 0);
3342 }
cbf61325
ASJ		 3343 /* unmap skb header data */
3344 dma_unmap_single(tx_ring->dev,
3345 dma_unmap_addr(tx_buf, dma),
3346 dma_unmap_len(tx_buf, len),
3347 DMA_TO_DEVICE);
49d7d933
ASJ		 3348 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3349 kfree(tx_buf->raw_buf);
cbf61325 3350
49d7d933
ASJ		 3351 tx_buf->raw_buf = NULL;
3352 tx_buf->tx_flags = 0;
3353 tx_buf->next_to_watch = NULL;
cbf61325 3354 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3355 tx_desc->buffer_addr = 0;
3356 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3357
49d7d933 3358 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3359 tx_buf++;
3360 tx_desc++;
3361 i++;
3362 if (unlikely(!i)) {
3363 i -= tx_ring->count;
3364 tx_buf = tx_ring->tx_bi;
3365 tx_desc = I40E_TX_DESC(tx_ring, 0);
3366 }
3367
3368 /* update budget accounting */
3369 budget--;
3370 } while (likely(budget));
3371
3372 i += tx_ring->count;
3373 tx_ring->next_to_clean = i;
3374
3375 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3376 i40e_irq_dynamic_enable(vsi,
3377 tx_ring->q_vector->v_idx + vsi->base_vector);
3378 }
3379 return budget > 0;
3380}
3381
3382/**
3383 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3384 * @irq: interrupt number
3385 * @data: pointer to a q_vector
3386 **/
3387static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3388{
3389 struct i40e_q_vector *q_vector = data;
3390 struct i40e_vsi *vsi;
3391
3392 if (!q_vector->tx.ring)
3393 return IRQ_HANDLED;
3394
3395 vsi = q_vector->tx.ring->vsi;
3396 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3397
3398 return IRQ_HANDLED;
3399}
3400
41c445ff 3401/**
cd0b6fa6 3402 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3403 * @vsi: the VSI being configured
3404 * @v_idx: vector index
cd0b6fa6 3405 * @qp_idx: queue pair index
41c445ff 3406 **/
cd0b6fa6 3407static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3408{
493fb300 3409 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3410 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3411 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3412
3413 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3414 tx_ring->next = q_vector->tx.ring;
3415 q_vector->tx.ring = tx_ring;
41c445ff 3416 q_vector->tx.count++;
cd0b6fa6
AD		 3417
3418 rx_ring->q_vector = q_vector;
3419 rx_ring->next = q_vector->rx.ring;
3420 q_vector->rx.ring = rx_ring;
3421 q_vector->rx.count++;
41c445ff
JB		 3422}
3423
3424/**
3425 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3426 * @vsi: the VSI being configured
3427 *
3428 * This function maps descriptor rings to the queue-specific vectors
3429 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3430 * one vector per queue pair, but on a constrained vector budget, we
3431 * group the queue pairs as "efficiently" as possible.
3432 **/
3433static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3434{
3435 int qp_remaining = vsi->num_queue_pairs;
3436 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3437 int num_ringpairs;
41c445ff
JB		 3438 int v_start = 0;
3439 int qp_idx = 0;
3440
3441 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3442 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3443 * It is also important to go through all the vectors available to be
3444 * sure that if we don't use all the vectors, that the remaining vectors
3445 * are cleared. This is especially important when decreasing the
3446 * number of queues in use.
41c445ff 3447 */
70114ec4 3448 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3449 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3450
3451 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3452
3453 q_vector->num_ringpairs = num_ringpairs;
3454
3455 q_vector->rx.count = 0;
3456 q_vector->tx.count = 0;
3457 q_vector->rx.ring = NULL;
3458 q_vector->tx.ring = NULL;
3459
3460 while (num_ringpairs--) {
3461 map_vector_to_qp(vsi, v_start, qp_idx);
3462 qp_idx++;
3463 qp_remaining--;
41c445ff
JB		 3464 }
3465 }
3466}
3467
3468/**
3469 * i40e_vsi_request_irq - Request IRQ from the OS
3470 * @vsi: the VSI being configured
3471 * @basename: name for the vector
3472 **/
3473static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3474{
3475 struct i40e_pf *pf = vsi->back;
3476 int err;
3477
3478 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3479 err = i40e_vsi_request_irq_msix(vsi, basename);
3480 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3481 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3482 pf->int_name, pf);
41c445ff
JB		 3483 else
3484 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3485 pf->int_name, pf);
41c445ff
JB		 3486
3487 if (err)
3488 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3489
3490 return err;
3491}
3492
3493#ifdef CONFIG_NET_POLL_CONTROLLER
3494/**
3495 * i40e_netpoll - A Polling 'interrupt'handler
3496 * @netdev: network interface device structure
3497 *
3498 * This is used by netconsole to send skbs without having to re-enable
3499 * interrupts. It's not called while the normal interrupt routine is executing.
3500 **/
38e00438
VD		 3501#ifdef I40E_FCOE
3502void i40e_netpoll(struct net_device *netdev)
3503#else
41c445ff 3504static void i40e_netpoll(struct net_device *netdev)
38e00438 3505#endif
41c445ff
JB		 3506{
3507 struct i40e_netdev_priv *np = netdev_priv(netdev);
3508 struct i40e_vsi *vsi = np->vsi;
3509 struct i40e_pf *pf = vsi->back;
3510 int i;
3511
3512 /* if interface is down do nothing */
3513 if (test_bit(__I40E_DOWN, &vsi->state))
3514 return;
3515
3516 pf->flags |= I40E_FLAG_IN_NETPOLL;
3517 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3518 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3519 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3520 } else {
3521 i40e_intr(pf->pdev->irq, netdev);
3522 }
3523 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3524}
3525#endif
3526
23527308
NP		 3527/**
3528 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3529 * @pf: the PF being configured
3530 * @pf_q: the PF queue
3531 * @enable: enable or disable state of the queue
3532 *
3533 * This routine will wait for the given Tx queue of the PF to reach the
3534 * enabled or disabled state.
3535 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3536 * multiple retries; else will return 0 in case of success.
3537 **/
3538static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3539{
3540 int i;
3541 u32 tx_reg;
3542
3543 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3544 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3545 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3546 break;
3547
f98a2006 3548 usleep_range(10, 20);
23527308
NP		 3549 }
3550 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3551 return -ETIMEDOUT;
3552
3553 return 0;
3554}
3555
41c445ff
JB		 3556/**
3557 * i40e_vsi_control_tx - Start or stop a VSI's rings
3558 * @vsi: the VSI being configured
3559 * @enable: start or stop the rings
3560 **/
3561static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3562{
3563 struct i40e_pf *pf = vsi->back;
3564 struct i40e_hw *hw = &pf->hw;
23527308 3565 int i, j, pf_q, ret = 0;
41c445ff
JB		 3566 u32 tx_reg;
3567
3568 pf_q = vsi->base_queue;
3569 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3570
3571 /* warn the TX unit of coming changes */
3572 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3573 if (!enable)
f98a2006 3574 usleep_range(10, 20);
351499ab 3575
6c5ef620 3576 for (j = 0; j < 50; j++) {
41c445ff 3577 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3578 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3579 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3580 break;
3581 usleep_range(1000, 2000);
3582 }
fda972f6 3583 /* Skip if the queue is already in the requested state */
7c122007 3584 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3585 continue;
41c445ff
JB		 3586
3587 /* turn on/off the queue */
c5c9eb9e
SN		 3588 if (enable) {
3589 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3590 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3591 } else {
41c445ff 3592 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3593 }
41c445ff
JB		 3594
3595 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3596 /* No waiting for the Tx queue to disable */
3597 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3598 continue;
41c445ff
JB		 3599
3600 /* wait for the change to finish */
23527308
NP		 3601 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3602 if (ret) {
3603 dev_info(&pf->pdev->dev,
3604 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3605 __func__, vsi->seid, pf_q,
3606 (enable ? "en" : "dis"));
3607 break;
41c445ff
JB		 3608 }
3609 }
3610
7134f9ce
JB		 3611 if (hw->revision_id == 0)
3612 mdelay(50);
23527308
NP		 3613 return ret;
3614}
3615
3616/**
3617 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3618 * @pf: the PF being configured
3619 * @pf_q: the PF queue
3620 * @enable: enable or disable state of the queue
3621 *
3622 * This routine will wait for the given Rx queue of the PF to reach the
3623 * enabled or disabled state.
3624 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3625 * multiple retries; else will return 0 in case of success.
3626 **/
3627static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3628{
3629 int i;
3630 u32 rx_reg;
3631
3632 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3633 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3634 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3635 break;
3636
f98a2006 3637 usleep_range(10, 20);
23527308
NP		 3638 }
3639 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3640 return -ETIMEDOUT;
7134f9ce 3641
41c445ff
JB		 3642 return 0;
3643}
3644
3645/**
3646 * i40e_vsi_control_rx - Start or stop a VSI's rings
3647 * @vsi: the VSI being configured
3648 * @enable: start or stop the rings
3649 **/
3650static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3651{
3652 struct i40e_pf *pf = vsi->back;
3653 struct i40e_hw *hw = &pf->hw;
23527308 3654 int i, j, pf_q, ret = 0;
41c445ff
JB		 3655 u32 rx_reg;
3656
3657 pf_q = vsi->base_queue;
3658 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3659 for (j = 0; j < 50; j++) {
41c445ff 3660 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3661 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3662 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3663 break;
3664 usleep_range(1000, 2000);
3665 }
41c445ff 3666
7c122007
CS		 3667 /* Skip if the queue is already in the requested state */
3668 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3669 continue;
41c445ff
JB		 3670
3671 /* turn on/off the queue */
3672 if (enable)
6c5ef620 3673 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3674 else
6c5ef620 3675 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3676 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3677
3678 /* wait for the change to finish */
23527308
NP		 3679 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3680 if (ret) {
3681 dev_info(&pf->pdev->dev,
3682 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3683 __func__, vsi->seid, pf_q,
3684 (enable ? "en" : "dis"));
3685 break;
41c445ff
JB		 3686 }
3687 }
3688
23527308 3689 return ret;
41c445ff
JB		 3690}
3691
3692/**
3693 * i40e_vsi_control_rings - Start or stop a VSI's rings
3694 * @vsi: the VSI being configured
3695 * @enable: start or stop the rings
3696 **/
fc18eaa0 3697int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3698{
3b867b28 3699 int ret = 0;
41c445ff
JB		 3700
3701 /* do rx first for enable and last for disable */
3702 if (request) {
3703 ret = i40e_vsi_control_rx(vsi, request);
3704 if (ret)
3705 return ret;
3706 ret = i40e_vsi_control_tx(vsi, request);
3707 } else {
3b867b28
ASJ		 3708 /* Ignore return value, we need to shutdown whatever we can */
3709 i40e_vsi_control_tx(vsi, request);
3710 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3711 }
3712
3713 return ret;
3714}
3715
3716/**
3717 * i40e_vsi_free_irq - Free the irq association with the OS
3718 * @vsi: the VSI being configured
3719 **/
3720static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3721{
3722 struct i40e_pf *pf = vsi->back;
3723 struct i40e_hw *hw = &pf->hw;
3724 int base = vsi->base_vector;
3725 u32 val, qp;
3726 int i;
3727
3728 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3729 if (!vsi->q_vectors)
3730 return;
3731
63741846
SN		 3732 if (!vsi->irqs_ready)
3733 return;
3734
3735 vsi->irqs_ready = false;
41c445ff
JB		 3736 for (i = 0; i < vsi->num_q_vectors; i++) {
3737 u16 vector = i + base;
3738
3739 /* free only the irqs that were actually requested */
78681b1f
SN		 3740 if (!vsi->q_vectors[i] ||
3741 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3742 continue;
3743
3744 /* clear the affinity_mask in the IRQ descriptor */
3745 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3746 NULL);
3747 free_irq(pf->msix_entries[vector].vector,
493fb300 3748 vsi->q_vectors[i]);
41c445ff
JB		 3749
3750 /* Tear down the interrupt queue link list
3751 *
3752 * We know that they come in pairs and always
3753 * the Rx first, then the Tx. To clear the
3754 * link list, stick the EOL value into the
3755 * next_q field of the registers.
3756 */
3757 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3758 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3759 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3760 val |= I40E_QUEUE_END_OF_LIST
3761 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3762 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3763
3764 while (qp != I40E_QUEUE_END_OF_LIST) {
3765 u32 next;
3766
3767 val = rd32(hw, I40E_QINT_RQCTL(qp));
3768
3769 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3770 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3771 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3772 I40E_QINT_RQCTL_INTEVENT_MASK);
3773
3774 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3775 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3776
3777 wr32(hw, I40E_QINT_RQCTL(qp), val);
3778
3779 val = rd32(hw, I40E_QINT_TQCTL(qp));
3780
3781 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3782 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3783
3784 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3785 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3786 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3787 I40E_QINT_TQCTL_INTEVENT_MASK);
3788
3789 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3790 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3791
3792 wr32(hw, I40E_QINT_TQCTL(qp), val);
3793 qp = next;
3794 }
3795 }
3796 } else {
3797 free_irq(pf->pdev->irq, pf);
3798
3799 val = rd32(hw, I40E_PFINT_LNKLST0);
3800 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3801 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3802 val |= I40E_QUEUE_END_OF_LIST
3803 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3804 wr32(hw, I40E_PFINT_LNKLST0, val);
3805
3806 val = rd32(hw, I40E_QINT_RQCTL(qp));
3807 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3808 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3809 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3810 I40E_QINT_RQCTL_INTEVENT_MASK);
3811
3812 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3813 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3814
3815 wr32(hw, I40E_QINT_RQCTL(qp), val);
3816
3817 val = rd32(hw, I40E_QINT_TQCTL(qp));
3818
3819 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3820 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3821 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3822 I40E_QINT_TQCTL_INTEVENT_MASK);
3823
3824 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3825 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3826
3827 wr32(hw, I40E_QINT_TQCTL(qp), val);
3828 }
3829}
3830
493fb300
AD		 3831/**
3832 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3833 * @vsi: the VSI being configured
3834 * @v_idx: Index of vector to be freed
3835 *
3836 * This function frees the memory allocated to the q_vector. In addition if
3837 * NAPI is enabled it will delete any references to the NAPI struct prior
3838 * to freeing the q_vector.
3839 **/
3840static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3841{
3842 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3843 struct i40e_ring *ring;
493fb300
AD		 3844
3845 if (!q_vector)
3846 return;
3847
3848 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3849 i40e_for_each_ring(ring, q_vector->tx)
3850 ring->q_vector = NULL;
3851
3852 i40e_for_each_ring(ring, q_vector->rx)
3853 ring->q_vector = NULL;
493fb300
AD		 3854
3855 /* only VSI w/ an associated netdev is set up w/ NAPI */
3856 if (vsi->netdev)
3857 netif_napi_del(&q_vector->napi);
3858
3859 vsi->q_vectors[v_idx] = NULL;
3860
3861 kfree_rcu(q_vector, rcu);
3862}
3863
41c445ff
JB		 3864/**
3865 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3866 * @vsi: the VSI being un-configured
3867 *
3868 * This frees the memory allocated to the q_vectors and
3869 * deletes references to the NAPI struct.
3870 **/
3871static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3872{
3873 int v_idx;
3874
493fb300
AD		 3875 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3876 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3877}
3878
3879/**
3880 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3881 * @pf: board private structure
3882 **/
3883static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3884{
3885 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3886 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3887 pci_disable_msix(pf->pdev);
3888 kfree(pf->msix_entries);
3889 pf->msix_entries = NULL;
3b444399
SN		 3890 kfree(pf->irq_pile);
3891 pf->irq_pile = NULL;
41c445ff
JB		 3892 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3893 pci_disable_msi(pf->pdev);
3894 }
3895 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3896}
3897
3898/**
3899 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3900 * @pf: board private structure
3901 *
3902 * We go through and clear interrupt specific resources and reset the structure
3903 * to pre-load conditions
3904 **/
3905static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3906{
3907 int i;
3908
e147758d
SN		 3909 i40e_stop_misc_vector(pf);
3910 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3911 synchronize_irq(pf->msix_entries[0].vector);
3912 free_irq(pf->msix_entries[0].vector, pf);
3913 }
3914
41c445ff 3915 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3916 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3917 if (pf->vsi[i])
3918 i40e_vsi_free_q_vectors(pf->vsi[i]);
3919 i40e_reset_interrupt_capability(pf);
3920}
3921
3922/**
3923 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3924 * @vsi: the VSI being configured
3925 **/
3926static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3927{
3928 int q_idx;
3929
3930 if (!vsi->netdev)
3931 return;
3932
3933 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3934 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3935}
3936
3937/**
3938 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3939 * @vsi: the VSI being configured
3940 **/
3941static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3942{
3943 int q_idx;
3944
3945 if (!vsi->netdev)
3946 return;
3947
3948 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3949 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3950}
3951
90ef8d47
SN		 3952/**
3953 * i40e_vsi_close - Shut down a VSI
3954 * @vsi: the vsi to be quelled
3955 **/
3956static void i40e_vsi_close(struct i40e_vsi *vsi)
3957{
3958 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3959 i40e_down(vsi);
3960 i40e_vsi_free_irq(vsi);
3961 i40e_vsi_free_tx_resources(vsi);
3962 i40e_vsi_free_rx_resources(vsi);
3963}
3964
41c445ff
JB		 3965/**
3966 * i40e_quiesce_vsi - Pause a given VSI
3967 * @vsi: the VSI being paused
3968 **/
3969static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3970{
3971 if (test_bit(__I40E_DOWN, &vsi->state))
3972 return;
3973
d341b7a5
NP		 3974 /* No need to disable FCoE VSI when Tx suspended */
3975 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
3976 vsi->type == I40E_VSI_FCOE) {
3977 dev_dbg(&vsi->back->pdev->dev,
3978 "%s: VSI seid %d skipping FCoE VSI disable\n",
3979 __func__, vsi->seid);
3980 return;
3981 }
3982
41c445ff
JB		 3983 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3984 if (vsi->netdev && netif_running(vsi->netdev)) {
3985 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3986 } else {
90ef8d47 3987 i40e_vsi_close(vsi);
41c445ff
JB		 3988 }
3989}
3990
3991/**
3992 * i40e_unquiesce_vsi - Resume a given VSI
3993 * @vsi: the VSI being resumed
3994 **/
3995static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3996{
3997 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3998 return;
3999
4000 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4001 if (vsi->netdev && netif_running(vsi->netdev))
4002 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4003 else
8276f757 4004 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4005}
4006
4007/**
4008 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4009 * @pf: the PF
4010 **/
4011static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4012{
4013 int v;
4014
505682cd 4015 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4016 if (pf->vsi[v])
4017 i40e_quiesce_vsi(pf->vsi[v]);
4018 }
4019}
4020
4021/**
4022 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4023 * @pf: the PF
4024 **/
4025static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4026{
4027 int v;
4028
505682cd 4029 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4030 if (pf->vsi[v])
4031 i40e_unquiesce_vsi(pf->vsi[v]);
4032 }
4033}
4034
69129dc3
NP		 4035#ifdef CONFIG_I40E_DCB
4036/**
4037 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4038 * @vsi: the VSI being configured
4039 *
4040 * This function waits for the given VSI's Tx queues to be disabled.
4041 **/
4042static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4043{
4044 struct i40e_pf *pf = vsi->back;
4045 int i, pf_q, ret;
4046
4047 pf_q = vsi->base_queue;
4048 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4049 /* Check and wait for the disable status of the queue */
4050 ret = i40e_pf_txq_wait(pf, pf_q, false);
4051 if (ret) {
4052 dev_info(&pf->pdev->dev,
4053 "%s: VSI seid %d Tx ring %d disable timeout\n",
4054 __func__, vsi->seid, pf_q);
4055 return ret;
4056 }
4057 }
4058
4059 return 0;
4060}
4061
4062/**
4063 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4064 * @pf: the PF
4065 *
4066 * This function waits for the Tx queues to be in disabled state for all the
4067 * VSIs that are managed by this PF.
4068 **/
4069static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4070{
4071 int v, ret = 0;
4072
4073 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4074 /* No need to wait for FCoE VSI queues */
4075 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4076 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4077 if (ret)
4078 break;
4079 }
4080 }
4081
4082 return ret;
4083}
4084
4085#endif
63d7e5a4
NP		 4086/**
4087 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4088 * @pf: pointer to PF
63d7e5a4
NP		 4089 *
4090 * Get TC map for ISCSI PF type that will include iSCSI TC
4091 * and LAN TC.
4092 **/
4093static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4094{
4095 struct i40e_dcb_app_priority_table app;
4096 struct i40e_hw *hw = &pf->hw;
4097 u8 enabled_tc = 1; /* TC0 is always enabled */
4098 u8 tc, i;
4099 /* Get the iSCSI APP TLV */
4100 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4101
4102 for (i = 0; i < dcbcfg->numapps; i++) {
4103 app = dcbcfg->app[i];
4104 if (app.selector == I40E_APP_SEL_TCPIP &&
4105 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4106 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4107 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4108 break;
4109 }
4110 }
4111
4112 return enabled_tc;
4113}
4114
41c445ff
JB		 4115/**
4116 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4117 * @dcbcfg: the corresponding DCBx configuration structure
4118 *
4119 * Return the number of TCs from given DCBx configuration
4120 **/
4121static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4122{
078b5876
JB		 4123 u8 num_tc = 0;
4124 int i;
41c445ff
JB		 4125
4126 /* Scan the ETS Config Priority Table to find
4127 * traffic class enabled for a given priority
4128 * and use the traffic class index to get the
4129 * number of traffic classes enabled
4130 */
4131 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4132 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4133 num_tc = dcbcfg->etscfg.prioritytable[i];
4134 }
4135
4136 /* Traffic class index starts from zero so
4137 * increment to return the actual count
4138 */
078b5876 4139 return num_tc + 1;
41c445ff
JB		 4140}
4141
4142/**
4143 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4144 * @dcbcfg: the corresponding DCBx configuration structure
4145 *
4146 * Query the current DCB configuration and return the number of
4147 * traffic classes enabled from the given DCBX config
4148 **/
4149static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4150{
4151 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4152 u8 enabled_tc = 1;
4153 u8 i;
4154
4155 for (i = 0; i < num_tc; i++)
41a1d04b 4156 enabled_tc |= BIT(i);
41c445ff
JB		 4157
4158 return enabled_tc;
4159}
4160
4161/**
4162 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4163 * @pf: PF being queried
4164 *
4165 * Return number of traffic classes enabled for the given PF
4166 **/
4167static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4168{
4169 struct i40e_hw *hw = &pf->hw;
4170 u8 i, enabled_tc;
4171 u8 num_tc = 0;
4172 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4173
4174 /* If DCB is not enabled then always in single TC */
4175 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4176 return 1;
4177
63d7e5a4
NP		 4178 /* SFP mode will be enabled for all TCs on port */
4179 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4180 return i40e_dcb_get_num_tc(dcbcfg);
4181
41c445ff 4182 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4183 if (pf->hw.func_caps.iscsi)
4184 enabled_tc = i40e_get_iscsi_tc_map(pf);
4185 else
fc51de96 4186 return 1; /* Only TC0 */
41c445ff 4187
63d7e5a4
NP		 4188 /* At least have TC0 */
4189 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4190 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4191 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4192 num_tc++;
4193 }
4194 return num_tc;
41c445ff
JB		 4195}
4196
4197/**
4198 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4199 * @pf: PF being queried
4200 *
4201 * Return a bitmap for first enabled traffic class for this PF.
4202 **/
4203static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4204{
4205 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4206 u8 i = 0;
4207
4208 if (!enabled_tc)
4209 return 0x1; /* TC0 */
4210
4211 /* Find the first enabled TC */
4212 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4213 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4214 break;
4215 }
4216
41a1d04b 4217 return BIT(i);
41c445ff
JB		 4218}
4219
4220/**
4221 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4222 * @pf: PF being queried
4223 *
4224 * Return a bitmap for enabled traffic classes for this PF.
4225 **/
4226static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4227{
4228 /* If DCB is not enabled for this PF then just return default TC */
4229 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4230 return i40e_pf_get_default_tc(pf);
4231
41c445ff 4232 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4233 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4234 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4235
fc51de96 4236 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4237 if (pf->hw.func_caps.iscsi)
4238 return i40e_get_iscsi_tc_map(pf);
4239 else
fc51de96 4240 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4241}
4242
4243/**
4244 * i40e_vsi_get_bw_info - Query VSI BW Information
4245 * @vsi: the VSI being queried
4246 *
4247 * Returns 0 on success, negative value on failure
4248 **/
4249static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4250{
4251 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4252 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4253 struct i40e_pf *pf = vsi->back;
4254 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4255 i40e_status ret;
41c445ff 4256 u32 tc_bw_max;
41c445ff
JB		 4257 int i;
4258
4259 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4260 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4261 if (ret) {
41c445ff 4262 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4263 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4264 i40e_stat_str(&pf->hw, ret),
4265 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4266 return -EINVAL;
41c445ff
JB		 4267 }
4268
4269 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4270 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4271 NULL);
4272 if (ret) {
41c445ff 4273 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4274 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4275 i40e_stat_str(&pf->hw, ret),
4276 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4277 return -EINVAL;
41c445ff
JB		 4278 }
4279
4280 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4281 dev_info(&pf->pdev->dev,
4282 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4283 bw_config.tc_valid_bits,
4284 bw_ets_config.tc_valid_bits);
4285 /* Still continuing */
4286 }
4287
4288 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4289 vsi->bw_max_quanta = bw_config.max_bw;
4290 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4291 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4292 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4293 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4294 vsi->bw_ets_limit_credits[i] =
4295 le16_to_cpu(bw_ets_config.credits[i]);
4296 /* 3 bits out of 4 for each TC */
4297 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4298 }
078b5876 4299
dcae29be 4300 return 0;
41c445ff
JB		 4301}
4302
4303/**
4304 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4305 * @vsi: the VSI being configured
4306 * @enabled_tc: TC bitmap
4307 * @bw_credits: BW shared credits per TC
4308 *
4309 * Returns 0 on success, negative value on failure
4310 **/
dcae29be 4311static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4312 u8 *bw_share)
4313{
4314 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4315 i40e_status ret;
dcae29be 4316 int i;
41c445ff
JB		 4317
4318 bw_data.tc_valid_bits = enabled_tc;
4319 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4320 bw_data.tc_bw_credits[i] = bw_share[i];
4321
f1c7e72e
SN		 4322 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4323 NULL);
4324 if (ret) {
41c445ff 4325 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4326 "AQ command Config VSI BW allocation per TC failed = %d\n",
4327 vsi->back->hw.aq.asq_last_status);
dcae29be 4328 return -EINVAL;
41c445ff
JB		 4329 }
4330
4331 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4332 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4333
dcae29be 4334 return 0;
41c445ff
JB		 4335}
4336
4337/**
4338 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4339 * @vsi: the VSI being configured
4340 * @enabled_tc: TC map to be enabled
4341 *
4342 **/
4343static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4344{
4345 struct net_device *netdev = vsi->netdev;
4346 struct i40e_pf *pf = vsi->back;
4347 struct i40e_hw *hw = &pf->hw;
4348 u8 netdev_tc = 0;
4349 int i;
4350 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4351
4352 if (!netdev)
4353 return;
4354
4355 if (!enabled_tc) {
4356 netdev_reset_tc(netdev);
4357 return;
4358 }
4359
4360 /* Set up actual enabled TCs on the VSI */
4361 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4362 return;
4363
4364 /* set per TC queues for the VSI */
4365 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4366 /* Only set TC queues for enabled tcs
4367 *
4368 * e.g. For a VSI that has TC0 and TC3 enabled the
4369 * enabled_tc bitmap would be 0x00001001; the driver
4370 * will set the numtc for netdev as 2 that will be
4371 * referenced by the netdev layer as TC 0 and 1.
4372 */
41a1d04b 4373 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4374 netdev_set_tc_queue(netdev,
4375 vsi->tc_config.tc_info[i].netdev_tc,
4376 vsi->tc_config.tc_info[i].qcount,
4377 vsi->tc_config.tc_info[i].qoffset);
4378 }
4379
4380 /* Assign UP2TC map for the VSI */
4381 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4382 /* Get the actual TC# for the UP */
4383 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4384 /* Get the mapped netdev TC# for the UP */
4385 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4386 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4387 }
4388}
4389
4390/**
4391 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4392 * @vsi: the VSI being configured
4393 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4394 **/
4395static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4396 struct i40e_vsi_context *ctxt)
4397{
4398 /* copy just the sections touched not the entire info
4399 * since not all sections are valid as returned by
4400 * update vsi params
4401 */
4402 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4403 memcpy(&vsi->info.queue_mapping,
4404 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4405 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4406 sizeof(vsi->info.tc_mapping));
4407}
4408
4409/**
4410 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4411 * @vsi: VSI to be configured
4412 * @enabled_tc: TC bitmap
4413 *
4414 * This configures a particular VSI for TCs that are mapped to the
4415 * given TC bitmap. It uses default bandwidth share for TCs across
4416 * VSIs to configure TC for a particular VSI.
4417 *
4418 * NOTE:
4419 * It is expected that the VSI queues have been quisced before calling
4420 * this function.
4421 **/
4422static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4423{
4424 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4425 struct i40e_vsi_context ctxt;
4426 int ret = 0;
4427 int i;
4428
4429 /* Check if enabled_tc is same as existing or new TCs */
4430 if (vsi->tc_config.enabled_tc == enabled_tc)
4431 return ret;
4432
4433 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4434 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4435 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4436 bw_share[i] = 1;
4437 }
4438
4439 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4440 if (ret) {
4441 dev_info(&vsi->back->pdev->dev,
4442 "Failed configuring TC map %d for VSI %d\n",
4443 enabled_tc, vsi->seid);
4444 goto out;
4445 }
4446
4447 /* Update Queue Pairs Mapping for currently enabled UPs */
4448 ctxt.seid = vsi->seid;
4449 ctxt.pf_num = vsi->back->hw.pf_id;
4450 ctxt.vf_num = 0;
4451 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4452 ctxt.info = vsi->info;
41c445ff
JB		 4453 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4454
4455 /* Update the VSI after updating the VSI queue-mapping information */
4456 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4457 if (ret) {
4458 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4459 "Update vsi tc config failed, err %s aq_err %s\n",
4460 i40e_stat_str(&vsi->back->hw, ret),
4461 i40e_aq_str(&vsi->back->hw,
4462 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4463 goto out;
4464 }
4465 /* update the local VSI info with updated queue map */
4466 i40e_vsi_update_queue_map(vsi, &ctxt);
4467 vsi->info.valid_sections = 0;
4468
4469 /* Update current VSI BW information */
4470 ret = i40e_vsi_get_bw_info(vsi);
4471 if (ret) {
4472 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4473 "Failed updating vsi bw info, err %s aq_err %s\n",
4474 i40e_stat_str(&vsi->back->hw, ret),
4475 i40e_aq_str(&vsi->back->hw,
4476 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4477 goto out;
4478 }
4479
4480 /* Update the netdev TC setup */
4481 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4482out:
4483 return ret;
4484}
4485
4e3b35b0
NP		 4486/**
4487 * i40e_veb_config_tc - Configure TCs for given VEB
4488 * @veb: given VEB
4489 * @enabled_tc: TC bitmap
4490 *
4491 * Configures given TC bitmap for VEB (switching) element
4492 **/
4493int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4494{
4495 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4496 struct i40e_pf *pf = veb->pf;
4497 int ret = 0;
4498 int i;
4499
4500 /* No TCs or already enabled TCs just return */
4501 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4502 return ret;
4503
4504 bw_data.tc_valid_bits = enabled_tc;
4505 /* bw_data.absolute_credits is not set (relative) */
4506
4507 /* Enable ETS TCs with equal BW Share for now */
4508 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4509 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4510 bw_data.tc_bw_share_credits[i] = 1;
4511 }
4512
4513 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4514 &bw_data, NULL);
4515 if (ret) {
4516 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4517 "VEB bw config failed, err %s aq_err %s\n",
4518 i40e_stat_str(&pf->hw, ret),
4519 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4520 goto out;
4521 }
4522
4523 /* Update the BW information */
4524 ret = i40e_veb_get_bw_info(veb);
4525 if (ret) {
4526 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4527 "Failed getting veb bw config, err %s aq_err %s\n",
4528 i40e_stat_str(&pf->hw, ret),
4529 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4530 }
4531
4532out:
4533 return ret;
4534}
4535
4536#ifdef CONFIG_I40E_DCB
4537/**
4538 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4539 * @pf: PF struct
4540 *
4541 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4542 * the caller would've quiesce all the VSIs before calling
4543 * this function
4544 **/
4545static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4546{
4547 u8 tc_map = 0;
4548 int ret;
4549 u8 v;
4550
4551 /* Enable the TCs available on PF to all VEBs */
4552 tc_map = i40e_pf_get_tc_map(pf);
4553 for (v = 0; v < I40E_MAX_VEB; v++) {
4554 if (!pf->veb[v])
4555 continue;
4556 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4557 if (ret) {
4558 dev_info(&pf->pdev->dev,
4559 "Failed configuring TC for VEB seid=%d\n",
4560 pf->veb[v]->seid);
4561 /* Will try to configure as many components */
4562 }
4563 }
4564
4565 /* Update each VSI */
505682cd 4566 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4567 if (!pf->vsi[v])
4568 continue;
4569
4570 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4571#ifdef I40E_FCOE
4572 * - For FCoE VSI only enable the TC configured
4573 * as per the APP TLV
4574#endif
4e3b35b0
NP		 4575 * - For all others keep them at TC0 for now
4576 */
4577 if (v == pf->lan_vsi)
4578 tc_map = i40e_pf_get_tc_map(pf);
4579 else
4580 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4581#ifdef I40E_FCOE
4582 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4583 tc_map = i40e_get_fcoe_tc_map(pf);
4584#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4585
4586 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4587 if (ret) {
4588 dev_info(&pf->pdev->dev,
4589 "Failed configuring TC for VSI seid=%d\n",
4590 pf->vsi[v]->seid);
4591 /* Will try to configure as many components */
4592 } else {
0672a091
NP		 4593 /* Re-configure VSI vectors based on updated TC map */
4594 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4595 if (pf->vsi[v]->netdev)
4596 i40e_dcbnl_set_all(pf->vsi[v]);
4597 }
4598 }
4599}
4600
2fd75f31
NP		 4601/**
4602 * i40e_resume_port_tx - Resume port Tx
4603 * @pf: PF struct
4604 *
4605 * Resume a port's Tx and issue a PF reset in case of failure to
4606 * resume.
4607 **/
4608static int i40e_resume_port_tx(struct i40e_pf *pf)
4609{
4610 struct i40e_hw *hw = &pf->hw;
4611 int ret;
4612
4613 ret = i40e_aq_resume_port_tx(hw, NULL);
4614 if (ret) {
4615 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4616 "Resume Port Tx failed, err %s aq_err %s\n",
4617 i40e_stat_str(&pf->hw, ret),
4618 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4619 /* Schedule PF reset to recover */
4620 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4621 i40e_service_event_schedule(pf);
4622 }
4623
4624 return ret;
4625}
4626
4e3b35b0
NP		 4627/**
4628 * i40e_init_pf_dcb - Initialize DCB configuration
4629 * @pf: PF being configured
4630 *
4631 * Query the current DCB configuration and cache it
4632 * in the hardware structure
4633 **/
4634static int i40e_init_pf_dcb(struct i40e_pf *pf)
4635{
4636 struct i40e_hw *hw = &pf->hw;
4637 int err = 0;
4638
025b4a54
ASJ		 4639 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4640 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4641 (pf->hw.aq.fw_maj_ver < 4))
4642 goto out;
4643
4e3b35b0
NP		 4644 /* Get the initial DCB configuration */
4645 err = i40e_init_dcb(hw);
4646 if (!err) {
4647 /* Device/Function is not DCBX capable */
4648 if ((!hw->func_caps.dcb) ||
4649 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4650 dev_info(&pf->pdev->dev,
4651 "DCBX offload is not supported or is disabled for this PF.\n");
4652
4653 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4654 goto out;
4655
4656 } else {
4657 /* When status is not DISABLED then DCBX in FW */
4658 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4659 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4660
4661 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4662 /* Enable DCB tagging only when more than one TC */
4663 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4664 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4665 dev_dbg(&pf->pdev->dev,
4666 "DCBX offload is supported for this PF.\n");
4e3b35b0 4667 }
014269ff 4668 } else {
aebfc816 4669 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4670 "Query for DCB configuration failed, err %s aq_err %s\n",
4671 i40e_stat_str(&pf->hw, err),
4672 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4673 }
4674
4675out:
4676 return err;
4677}
4678#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4679#define SPEED_SIZE 14
4680#define FC_SIZE 8
4681/**
4682 * i40e_print_link_message - print link up or down
4683 * @vsi: the VSI for which link needs a message
4684 */
4685static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4686{
4687 char speed[SPEED_SIZE] = "Unknown";
4688 char fc[FC_SIZE] = "RX/TX";
4689
4690 if (!isup) {
4691 netdev_info(vsi->netdev, "NIC Link is Down\n");
4692 return;
4693 }
4694
148c2d80
GR		 4695 /* Warn user if link speed on NPAR enabled partition is not at
4696 * least 10GB
4697 */
4698 if (vsi->back->hw.func_caps.npar_enable &&
4699 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4700 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4701 netdev_warn(vsi->netdev,
4702 "The partition detected link speed that is less than 10Gbps\n");
4703
cf05ed08
JB		 4704 switch (vsi->back->hw.phy.link_info.link_speed) {
4705 case I40E_LINK_SPEED_40GB:
35a7d804 4706 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08 4707 break;
ae24b409
JB		 4708 case I40E_LINK_SPEED_20GB:
4709 strncpy(speed, "20 Gbps", SPEED_SIZE);
4710 break;
cf05ed08 4711 case I40E_LINK_SPEED_10GB:
35a7d804 4712 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4713 break;
4714 case I40E_LINK_SPEED_1GB:
35a7d804 4715 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4716 break;
5960d33f
MW		 4717 case I40E_LINK_SPEED_100MB:
4718 strncpy(speed, "100 Mbps", SPEED_SIZE);
4719 break;
cf05ed08
JB		 4720 default:
4721 break;
4722 }
4723
4724 switch (vsi->back->hw.fc.current_mode) {
4725 case I40E_FC_FULL:
35a7d804 4726 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4727 break;
4728 case I40E_FC_TX_PAUSE:
35a7d804 4729 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4730 break;
4731 case I40E_FC_RX_PAUSE:
35a7d804 4732 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4733 break;
4734 default:
35a7d804 4735 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4736 break;
4737 }
4738
4739 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4740 speed, fc);
4741}
4e3b35b0 4742
41c445ff
JB		 4743/**
4744 * i40e_up_complete - Finish the last steps of bringing up a connection
4745 * @vsi: the VSI being configured
4746 **/
4747static int i40e_up_complete(struct i40e_vsi *vsi)
4748{
4749 struct i40e_pf *pf = vsi->back;
4750 int err;
4751
4752 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4753 i40e_vsi_configure_msix(vsi);
4754 else
4755 i40e_configure_msi_and_legacy(vsi);
4756
4757 /* start rings */
4758 err = i40e_vsi_control_rings(vsi, true);
4759 if (err)
4760 return err;
4761
4762 clear_bit(__I40E_DOWN, &vsi->state);
4763 i40e_napi_enable_all(vsi);
4764 i40e_vsi_enable_irq(vsi);
4765
4766 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4767 (vsi->netdev)) {
cf05ed08 4768 i40e_print_link_message(vsi, true);
41c445ff
JB		 4769 netif_tx_start_all_queues(vsi->netdev);
4770 netif_carrier_on(vsi->netdev);
6d779b41 4771 } else if (vsi->netdev) {
cf05ed08 4772 i40e_print_link_message(vsi, false);
7b592f61
CW		 4773 /* need to check for qualified module here*/
4774 if ((pf->hw.phy.link_info.link_info &
4775 I40E_AQ_MEDIA_AVAILABLE) &&
4776 (!(pf->hw.phy.link_info.an_info &
4777 I40E_AQ_QUALIFIED_MODULE)))
4778 netdev_err(vsi->netdev,
4779 "the driver failed to link because an unqualified module was detected.");
41c445ff 4780 }
ca64fa4e
ASJ		 4781
4782 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4783 if (vsi->type == I40E_VSI_FDIR) {
4784 /* reset fd counters */
4785 pf->fd_add_err = pf->fd_atr_cnt = 0;
4786 if (pf->fd_tcp_rule > 0) {
4787 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 4788 if (I40E_DEBUG_FD & pf->hw.debug_mask)
4789 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 4790 pf->fd_tcp_rule = 0;
4791 }
ca64fa4e 4792 i40e_fdir_filter_restore(vsi);
1e1be8f6 4793 }
41c445ff
JB		 4794 i40e_service_event_schedule(pf);
4795
4796 return 0;
4797}
4798
4799/**
4800 * i40e_vsi_reinit_locked - Reset the VSI
4801 * @vsi: the VSI being configured
4802 *
4803 * Rebuild the ring structs after some configuration
4804 * has changed, e.g. MTU size.
4805 **/
4806static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4807{
4808 struct i40e_pf *pf = vsi->back;
4809
4810 WARN_ON(in_interrupt());
4811 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4812 usleep_range(1000, 2000);
4813 i40e_down(vsi);
4814
4815 /* Give a VF some time to respond to the reset. The
4816 * two second wait is based upon the watchdog cycle in
4817 * the VF driver.
4818 */
4819 if (vsi->type == I40E_VSI_SRIOV)
4820 msleep(2000);
4821 i40e_up(vsi);
4822 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4823}
4824
4825/**
4826 * i40e_up - Bring the connection back up after being down
4827 * @vsi: the VSI being configured
4828 **/
4829int i40e_up(struct i40e_vsi *vsi)
4830{
4831 int err;
4832
4833 err = i40e_vsi_configure(vsi);
4834 if (!err)
4835 err = i40e_up_complete(vsi);
4836
4837 return err;
4838}
4839
4840/**
4841 * i40e_down - Shutdown the connection processing
4842 * @vsi: the VSI being stopped
4843 **/
4844void i40e_down(struct i40e_vsi *vsi)
4845{
4846 int i;
4847
4848 /* It is assumed that the caller of this function
4849 * sets the vsi->state __I40E_DOWN bit.
4850 */
4851 if (vsi->netdev) {
4852 netif_carrier_off(vsi->netdev);
4853 netif_tx_disable(vsi->netdev);
4854 }
4855 i40e_vsi_disable_irq(vsi);
4856 i40e_vsi_control_rings(vsi, false);
4857 i40e_napi_disable_all(vsi);
4858
4859 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4860 i40e_clean_tx_ring(vsi->tx_rings[i]);
4861 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4862 }
4863}
4864
4865/**
4866 * i40e_setup_tc - configure multiple traffic classes
4867 * @netdev: net device to configure
4868 * @tc: number of traffic classes to enable
4869 **/
38e00438
VD		 4870#ifdef I40E_FCOE
4871int i40e_setup_tc(struct net_device *netdev, u8 tc)
4872#else
41c445ff 4873static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4874#endif
41c445ff
JB		 4875{
4876 struct i40e_netdev_priv *np = netdev_priv(netdev);
4877 struct i40e_vsi *vsi = np->vsi;
4878 struct i40e_pf *pf = vsi->back;
4879 u8 enabled_tc = 0;
4880 int ret = -EINVAL;
4881 int i;
4882
4883 /* Check if DCB enabled to continue */
4884 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4885 netdev_info(netdev, "DCB is not enabled for adapter\n");
4886 goto exit;
4887 }
4888
4889 /* Check if MFP enabled */
4890 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4891 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4892 goto exit;
4893 }
4894
4895 /* Check whether tc count is within enabled limit */
4896 if (tc > i40e_pf_get_num_tc(pf)) {
4897 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4898 goto exit;
4899 }
4900
4901 /* Generate TC map for number of tc requested */
4902 for (i = 0; i < tc; i++)
41a1d04b 4903 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 4904
4905 /* Requesting same TC configuration as already enabled */
4906 if (enabled_tc == vsi->tc_config.enabled_tc)
4907 return 0;
4908
4909 /* Quiesce VSI queues */
4910 i40e_quiesce_vsi(vsi);
4911
4912 /* Configure VSI for enabled TCs */
4913 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4914 if (ret) {
4915 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4916 vsi->seid);
4917 goto exit;
4918 }
4919
4920 /* Unquiesce VSI */
4921 i40e_unquiesce_vsi(vsi);
4922
4923exit:
4924 return ret;
4925}
4926
4927/**
4928 * i40e_open - Called when a network interface is made active
4929 * @netdev: network interface device structure
4930 *
4931 * The open entry point is called when a network interface is made
4932 * active by the system (IFF_UP). At this point all resources needed
4933 * for transmit and receive operations are allocated, the interrupt
4934 * handler is registered with the OS, the netdev watchdog subtask is
4935 * enabled, and the stack is notified that the interface is ready.
4936 *
4937 * Returns 0 on success, negative value on failure
4938 **/
38e00438 4939int i40e_open(struct net_device *netdev)
41c445ff
JB		 4940{
4941 struct i40e_netdev_priv *np = netdev_priv(netdev);
4942 struct i40e_vsi *vsi = np->vsi;
4943 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4944 int err;
4945
4eb3f768
SN		 4946 /* disallow open during test or if eeprom is broken */
4947 if (test_bit(__I40E_TESTING, &pf->state) ||
4948 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4949 return -EBUSY;
4950
4951 netif_carrier_off(netdev);
4952
6c167f58
EK		 4953 err = i40e_vsi_open(vsi);
4954 if (err)
4955 return err;
4956
059dab69
JB		 4957 /* configure global TSO hardware offload settings */
4958 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4959 TCP_FLAG_FIN) >> 16);
4960 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4961 TCP_FLAG_FIN |
4962 TCP_FLAG_CWR) >> 16);
4963 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4964
6c167f58
EK		 4965#ifdef CONFIG_I40E_VXLAN
4966 vxlan_get_rx_port(netdev);
4967#endif
4968
4969 return 0;
4970}
4971
4972/**
4973 * i40e_vsi_open -
4974 * @vsi: the VSI to open
4975 *
4976 * Finish initialization of the VSI.
4977 *
4978 * Returns 0 on success, negative value on failure
4979 **/
4980int i40e_vsi_open(struct i40e_vsi *vsi)
4981{
4982 struct i40e_pf *pf = vsi->back;
b294ac70 4983 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 4984 int err;
4985
41c445ff
JB		 4986 /* allocate descriptors */
4987 err = i40e_vsi_setup_tx_resources(vsi);
4988 if (err)
4989 goto err_setup_tx;
4990 err = i40e_vsi_setup_rx_resources(vsi);
4991 if (err)
4992 goto err_setup_rx;
4993
4994 err = i40e_vsi_configure(vsi);
4995 if (err)
4996 goto err_setup_rx;
4997
c22e3c6c
SN		 4998 if (vsi->netdev) {
4999 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5000 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5001 err = i40e_vsi_request_irq(vsi, int_name);
5002 if (err)
5003 goto err_setup_rx;
41c445ff 5004
c22e3c6c
SN		 5005 /* Notify the stack of the actual queue counts. */
5006 err = netif_set_real_num_tx_queues(vsi->netdev,
5007 vsi->num_queue_pairs);
5008 if (err)
5009 goto err_set_queues;
25946ddb 5010
c22e3c6c
SN		 5011 err = netif_set_real_num_rx_queues(vsi->netdev,
5012 vsi->num_queue_pairs);
5013 if (err)
5014 goto err_set_queues;
8a9eb7d3
SN		 5015
5016 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5017 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5018 dev_driver_string(&pf->pdev->dev),
5019 dev_name(&pf->pdev->dev));
8a9eb7d3 5020 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5021
c22e3c6c 5022 } else {
ce9ccb17 5023 err = -EINVAL;
6c167f58
EK		 5024 goto err_setup_rx;
5025 }
25946ddb 5026
41c445ff
JB		 5027 err = i40e_up_complete(vsi);
5028 if (err)
5029 goto err_up_complete;
5030
41c445ff
JB		 5031 return 0;
5032
5033err_up_complete:
5034 i40e_down(vsi);
25946ddb 5035err_set_queues:
41c445ff
JB		 5036 i40e_vsi_free_irq(vsi);
5037err_setup_rx:
5038 i40e_vsi_free_rx_resources(vsi);
5039err_setup_tx:
5040 i40e_vsi_free_tx_resources(vsi);
5041 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5042 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5043
5044 return err;
5045}
5046
17a73f6b
JG		 5047/**
5048 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5049 * @pf: Pointer to PF
17a73f6b
JG		 5050 *
5051 * This function destroys the hlist where all the Flow Director
5052 * filters were saved.
5053 **/
5054static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5055{
5056 struct i40e_fdir_filter *filter;
5057 struct hlist_node *node2;
5058
5059 hlist_for_each_entry_safe(filter, node2,
5060 &pf->fdir_filter_list, fdir_node) {
5061 hlist_del(&filter->fdir_node);
5062 kfree(filter);
5063 }
5064 pf->fdir_pf_active_filters = 0;
5065}
5066
41c445ff
JB		 5067/**
5068 * i40e_close - Disables a network interface
5069 * @netdev: network interface device structure
5070 *
5071 * The close entry point is called when an interface is de-activated
5072 * by the OS. The hardware is still under the driver's control, but
5073 * this netdev interface is disabled.
5074 *
5075 * Returns 0, this is not allowed to fail
5076 **/
38e00438
VD		 5077#ifdef I40E_FCOE
5078int i40e_close(struct net_device *netdev)
5079#else
41c445ff 5080static int i40e_close(struct net_device *netdev)
38e00438 5081#endif
41c445ff
JB		 5082{
5083 struct i40e_netdev_priv *np = netdev_priv(netdev);
5084 struct i40e_vsi *vsi = np->vsi;
5085
90ef8d47 5086 i40e_vsi_close(vsi);
41c445ff
JB		 5087
5088 return 0;
5089}
5090
5091/**
5092 * i40e_do_reset - Start a PF or Core Reset sequence
5093 * @pf: board private structure
5094 * @reset_flags: which reset is requested
5095 *
5096 * The essential difference in resets is that the PF Reset
5097 * doesn't clear the packet buffers, doesn't reset the PE
5098 * firmware, and doesn't bother the other PFs on the chip.
5099 **/
5100void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5101{
5102 u32 val;
5103
5104 WARN_ON(in_interrupt());
5105
263fc48f
MW		 5106 if (i40e_check_asq_alive(&pf->hw))
5107 i40e_vc_notify_reset(pf);
5108
41c445ff 5109 /* do the biggest reset indicated */
41a1d04b 5110 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5111
5112 /* Request a Global Reset
5113 *
5114 * This will start the chip's countdown to the actual full
5115 * chip reset event, and a warning interrupt to be sent
5116 * to all PFs, including the requestor. Our handler
5117 * for the warning interrupt will deal with the shutdown
5118 * and recovery of the switch setup.
5119 */
69bfb110 5120 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5121 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5122 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5123 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5124
41a1d04b 5125 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5126
5127 /* Request a Core Reset
5128 *
5129 * Same as Global Reset, except does *not* include the MAC/PHY
5130 */
69bfb110 5131 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5132 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5133 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5134 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5135 i40e_flush(&pf->hw);
5136
41a1d04b 5137 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5138
5139 /* Request a PF Reset
5140 *
5141 * Resets only the PF-specific registers
5142 *
5143 * This goes directly to the tear-down and rebuild of
5144 * the switch, since we need to do all the recovery as
5145 * for the Core Reset.
5146 */
69bfb110 5147 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5148 i40e_handle_reset_warning(pf);
5149
41a1d04b 5150 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5151 int v;
5152
5153 /* Find the VSI(s) that requested a re-init */
5154 dev_info(&pf->pdev->dev,
5155 "VSI reinit requested\n");
505682cd 5156 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5157 struct i40e_vsi *vsi = pf->vsi[v];
5158 if (vsi != NULL &&
5159 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5160 i40e_vsi_reinit_locked(pf->vsi[v]);
5161 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5162 }
5163 }
5164
b5d06f05
NP		 5165 /* no further action needed, so return now */
5166 return;
41a1d04b 5167 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5168 int v;
5169
5170 /* Find the VSI(s) that needs to be brought down */
5171 dev_info(&pf->pdev->dev, "VSI down requested\n");
5172 for (v = 0; v < pf->num_alloc_vsi; v++) {
5173 struct i40e_vsi *vsi = pf->vsi[v];
5174 if (vsi != NULL &&
5175 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5176 set_bit(__I40E_DOWN, &vsi->state);
5177 i40e_down(vsi);
5178 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5179 }
5180 }
5181
41c445ff
JB		 5182 /* no further action needed, so return now */
5183 return;
5184 } else {
5185 dev_info(&pf->pdev->dev,
5186 "bad reset request 0x%08x\n", reset_flags);
5187 return;
5188 }
5189}
5190
4e3b35b0
NP		 5191#ifdef CONFIG_I40E_DCB
5192/**
5193 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5194 * @pf: board private structure
5195 * @old_cfg: current DCB config
5196 * @new_cfg: new DCB config
5197 **/
5198bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5199 struct i40e_dcbx_config *old_cfg,
5200 struct i40e_dcbx_config *new_cfg)
5201{
5202 bool need_reconfig = false;
5203
5204 /* Check if ETS configuration has changed */
5205 if (memcmp(&new_cfg->etscfg,
5206 &old_cfg->etscfg,
5207 sizeof(new_cfg->etscfg))) {
5208 /* If Priority Table has changed reconfig is needed */
5209 if (memcmp(&new_cfg->etscfg.prioritytable,
5210 &old_cfg->etscfg.prioritytable,
5211 sizeof(new_cfg->etscfg.prioritytable))) {
5212 need_reconfig = true;
69bfb110 5213 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5214 }
5215
5216 if (memcmp(&new_cfg->etscfg.tcbwtable,
5217 &old_cfg->etscfg.tcbwtable,
5218 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5219 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5220
5221 if (memcmp(&new_cfg->etscfg.tsatable,
5222 &old_cfg->etscfg.tsatable,
5223 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5224 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5225 }
5226
5227 /* Check if PFC configuration has changed */
5228 if (memcmp(&new_cfg->pfc,
5229 &old_cfg->pfc,
5230 sizeof(new_cfg->pfc))) {
5231 need_reconfig = true;
69bfb110 5232 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5233 }
5234
5235 /* Check if APP Table has changed */
5236 if (memcmp(&new_cfg->app,
5237 &old_cfg->app,
3d9667a9 5238 sizeof(new_cfg->app))) {
4e3b35b0 5239 need_reconfig = true;
69bfb110 5240 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5241 }
4e3b35b0 5242
9fa61dd2
NP		 5243 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5244 need_reconfig);
4e3b35b0
NP		 5245 return need_reconfig;
5246}
5247
5248/**
5249 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5250 * @pf: board private structure
5251 * @e: event info posted on ARQ
5252 **/
5253static int i40e_handle_lldp_event(struct i40e_pf *pf,
5254 struct i40e_arq_event_info *e)
5255{
5256 struct i40e_aqc_lldp_get_mib *mib =
5257 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5258 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5259 struct i40e_dcbx_config tmp_dcbx_cfg;
5260 bool need_reconfig = false;
5261 int ret = 0;
5262 u8 type;
5263
4d9b6043
NP		 5264 /* Not DCB capable or capability disabled */
5265 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5266 return ret;
5267
4e3b35b0
NP		 5268 /* Ignore if event is not for Nearest Bridge */
5269 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5270 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5271 dev_dbg(&pf->pdev->dev,
5272 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5273 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5274 return ret;
5275
5276 /* Check MIB Type and return if event for Remote MIB update */
5277 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5278 dev_dbg(&pf->pdev->dev,
5279 "%s: LLDP event mib type %s\n", __func__,
5280 type ? "remote" : "local");
4e3b35b0
NP		 5281 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5282 /* Update the remote cached instance and return */
5283 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5284 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5285 &hw->remote_dcbx_config);
5286 goto exit;
5287 }
5288
9fa61dd2 5289 /* Store the old configuration */
1a2f6248 5290 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5291
750fcbcf
NP		 5292 /* Reset the old DCBx configuration data */
5293 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5294 /* Get updated DCBX data from firmware */
5295 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5296 if (ret) {
f1c7e72e
SN		 5297 dev_info(&pf->pdev->dev,
5298 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5299 i40e_stat_str(&pf->hw, ret),
5300 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5301 goto exit;
5302 }
5303
5304 /* No change detected in DCBX configs */
750fcbcf
NP		 5305 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5306 sizeof(tmp_dcbx_cfg))) {
69bfb110 5307 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5308 goto exit;
5309 }
5310
750fcbcf
NP		 5311 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5312 &hw->local_dcbx_config);
4e3b35b0 5313
750fcbcf 5314 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5315
5316 if (!need_reconfig)
5317 goto exit;
5318
4d9b6043 5319 /* Enable DCB tagging only when more than one TC */
750fcbcf 5320 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5321 pf->flags |= I40E_FLAG_DCB_ENABLED;
5322 else
5323 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5324
69129dc3 5325 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5326 /* Reconfiguration needed quiesce all VSIs */
5327 i40e_pf_quiesce_all_vsi(pf);
5328
5329 /* Changes in configuration update VEB/VSI */
5330 i40e_dcb_reconfigure(pf);
5331
2fd75f31
NP		 5332 ret = i40e_resume_port_tx(pf);
5333
69129dc3 5334 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5335 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5336 if (ret)
5337 goto exit;
5338
5339 /* Wait for the PF's Tx queues to be disabled */
5340 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5341 if (ret) {
5342 /* Schedule PF reset to recover */
5343 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5344 i40e_service_event_schedule(pf);
5345 } else {
2fd75f31 5346 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5347 }
5348
4e3b35b0
NP		 5349exit:
5350 return ret;
5351}
5352#endif /* CONFIG_I40E_DCB */
5353
23326186
ASJ		 5354/**
5355 * i40e_do_reset_safe - Protected reset path for userland calls.
5356 * @pf: board private structure
5357 * @reset_flags: which reset is requested
5358 *
5359 **/
5360void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5361{
5362 rtnl_lock();
5363 i40e_do_reset(pf, reset_flags);
5364 rtnl_unlock();
5365}
5366
41c445ff
JB		 5367/**
5368 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5369 * @pf: board private structure
5370 * @e: event info posted on ARQ
5371 *
5372 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5373 * and VF queues
5374 **/
5375static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5376 struct i40e_arq_event_info *e)
5377{
5378 struct i40e_aqc_lan_overflow *data =
5379 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5380 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5381 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5382 struct i40e_hw *hw = &pf->hw;
5383 struct i40e_vf *vf;
5384 u16 vf_id;
5385
69bfb110
JB		 5386 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5387 queue, qtx_ctl);
41c445ff
JB		 5388
5389 /* Queue belongs to VF, find the VF and issue VF reset */
5390 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5391 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5392 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5393 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5394 vf_id -= hw->func_caps.vf_base_id;
5395 vf = &pf->vf[vf_id];
5396 i40e_vc_notify_vf_reset(vf);
5397 /* Allow VF to process pending reset notification */
5398 msleep(20);
5399 i40e_reset_vf(vf, false);
5400 }
5401}
5402
5403/**
5404 * i40e_service_event_complete - Finish up the service event
5405 * @pf: board private structure
5406 **/
5407static void i40e_service_event_complete(struct i40e_pf *pf)
5408{
5409 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5410
5411 /* flush memory to make sure state is correct before next watchog */
4e857c58 5412 smp_mb__before_atomic();
41c445ff
JB		 5413 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5414}
5415
55a5e60b 5416/**
12957388
ASJ		 5417 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5418 * @pf: board private structure
5419 **/
04294e38 5420u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5421{
04294e38 5422 u32 val, fcnt_prog;
12957388
ASJ		 5423
5424 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5425 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5426 return fcnt_prog;
5427}
5428
5429/**
04294e38 5430 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5431 * @pf: board private structure
5432 **/
04294e38 5433u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5434{
04294e38
ASJ		 5435 u32 val, fcnt_prog;
5436
55a5e60b
ASJ		 5437 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5438 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5439 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5440 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5441 return fcnt_prog;
5442}
1e1be8f6 5443
04294e38
ASJ		 5444/**
5445 * i40e_get_global_fd_count - Get total FD filters programmed on device
5446 * @pf: board private structure
5447 **/
5448u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5449{
5450 u32 val, fcnt_prog;
5451
5452 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5453 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5454 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5455 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5456 return fcnt_prog;
5457}
5458
55a5e60b
ASJ		 5459/**
5460 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5461 * @pf: board private structure
5462 **/
5463void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5464{
5465 u32 fcnt_prog, fcnt_avail;
5466
1e1be8f6
ASJ		 5467 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5468 return;
5469
55a5e60b
ASJ		 5470 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5471 * to re-enable
5472 */
04294e38 5473 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5474 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5475 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5476 (pf->fd_add_err == 0) ||
5477 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5478 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5479 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5480 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5481 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5482 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5483 }
5484 }
5485 /* Wait for some more space to be available to turn on ATR */
5486 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5487 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5488 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5489 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5490 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5491 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5492 }
5493 }
5494}
5495
1e1be8f6 5496#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5497#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5498/**
5499 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5500 * @pf: board private structure
5501 **/
5502static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5503{
04294e38 5504 unsigned long min_flush_time;
1e1be8f6 5505 int flush_wait_retry = 50;
04294e38
ASJ		 5506 bool disable_atr = false;
5507 int fd_room;
1e1be8f6
ASJ		 5508 int reg;
5509
1790ed0c
AA		 5510 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5511 return;
5512
1e1be8f6
ASJ		 5513 if (time_after(jiffies, pf->fd_flush_timestamp +
5514 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
04294e38
ASJ		 5515 /* If the flush is happening too quick and we have mostly
5516 * SB rules we should not re-enable ATR for some time.
5517 */
5518 min_flush_time = pf->fd_flush_timestamp
5519 + (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5520 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5521
5522 if (!(time_after(jiffies, min_flush_time)) &&
5523 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
2e4875e3
ASJ		 5524 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5525 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
04294e38
ASJ		 5526 disable_atr = true;
5527 }
5528
1e1be8f6 5529 pf->fd_flush_timestamp = jiffies;
1e1be8f6
ASJ		 5530 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5531 /* flush all filters */
5532 wr32(&pf->hw, I40E_PFQF_CTL_1,
5533 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5534 i40e_flush(&pf->hw);
60793f4a 5535 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5536 pf->fd_add_err = 0;
5537 do {
5538 /* Check FD flush status every 5-6msec */
5539 usleep_range(5000, 6000);
5540 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5541 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5542 break;
5543 } while (flush_wait_retry--);
5544 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5545 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5546 } else {
5547 /* replay sideband filters */
5548 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
04294e38
ASJ		 5549 if (!disable_atr)
5550 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
1e1be8f6 5551 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
2e4875e3
ASJ		 5552 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5553 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 5554 }
5555 }
5556}
5557
5558/**
5559 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5560 * @pf: board private structure
5561 **/
04294e38 5562u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5563{
5564 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5565}
5566
5567/* We can see up to 256 filter programming desc in transit if the filters are
5568 * being applied really fast; before we see the first
5569 * filter miss error on Rx queue 0. Accumulating enough error messages before
5570 * reacting will make sure we don't cause flush too often.
5571 */
5572#define I40E_MAX_FD_PROGRAM_ERROR 256
5573
41c445ff
JB		 5574/**
5575 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5576 * @pf: board private structure
5577 **/
5578static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5579{
41c445ff 5580
41c445ff
JB		 5581 /* if interface is down do nothing */
5582 if (test_bit(__I40E_DOWN, &pf->state))
5583 return;
1e1be8f6 5584
1790ed0c
AA		 5585 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5586 return;
5587
04294e38 5588 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5589 i40e_fdir_flush_and_replay(pf);
5590
55a5e60b
ASJ		 5591 i40e_fdir_check_and_reenable(pf);
5592
41c445ff
JB		 5593}
5594
5595/**
5596 * i40e_vsi_link_event - notify VSI of a link event
5597 * @vsi: vsi to be notified
5598 * @link_up: link up or down
5599 **/
5600static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5601{
32b5b811 5602 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5603 return;
5604
5605 switch (vsi->type) {
5606 case I40E_VSI_MAIN:
38e00438
VD		 5607#ifdef I40E_FCOE
5608 case I40E_VSI_FCOE:
5609#endif
41c445ff
JB		 5610 if (!vsi->netdev || !vsi->netdev_registered)
5611 break;
5612
5613 if (link_up) {
5614 netif_carrier_on(vsi->netdev);
5615 netif_tx_wake_all_queues(vsi->netdev);
5616 } else {
5617 netif_carrier_off(vsi->netdev);
5618 netif_tx_stop_all_queues(vsi->netdev);
5619 }
5620 break;
5621
5622 case I40E_VSI_SRIOV:
41c445ff
JB		 5623 case I40E_VSI_VMDQ2:
5624 case I40E_VSI_CTRL:
5625 case I40E_VSI_MIRROR:
5626 default:
5627 /* there is no notification for other VSIs */
5628 break;
5629 }
5630}
5631
5632/**
5633 * i40e_veb_link_event - notify elements on the veb of a link event
5634 * @veb: veb to be notified
5635 * @link_up: link up or down
5636 **/
5637static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5638{
5639 struct i40e_pf *pf;
5640 int i;
5641
5642 if (!veb || !veb->pf)
5643 return;
5644 pf = veb->pf;
5645
5646 /* depth first... */
5647 for (i = 0; i < I40E_MAX_VEB; i++)
5648 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5649 i40e_veb_link_event(pf->veb[i], link_up);
5650
5651 /* ... now the local VSIs */
505682cd 5652 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5653 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5654 i40e_vsi_link_event(pf->vsi[i], link_up);
5655}
5656
5657/**
5658 * i40e_link_event - Update netif_carrier status
5659 * @pf: board private structure
5660 **/
5661static void i40e_link_event(struct i40e_pf *pf)
5662{
5663 bool new_link, old_link;
320684cd 5664 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5665 u8 new_link_speed, old_link_speed;
41c445ff 5666
1e701e09
JB		 5667 /* set this to force the get_link_status call to refresh state */
5668 pf->hw.phy.get_link_info = true;
5669
41c445ff 5670 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5671 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5672 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5673 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5674
1e701e09 5675 if (new_link == old_link &&
fef59ddf 5676 new_link_speed == old_link_speed &&
320684cd
MW		 5677 (test_bit(__I40E_DOWN, &vsi->state) ||
5678 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5679 return;
320684cd
MW		 5680
5681 if (!test_bit(__I40E_DOWN, &vsi->state))
5682 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5683
5684 /* Notify the base of the switch tree connected to
5685 * the link. Floating VEBs are not notified.
5686 */
5687 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5688 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5689 else
320684cd 5690 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5691
5692 if (pf->vf)
5693 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5694
5695 if (pf->flags & I40E_FLAG_PTP)
5696 i40e_ptp_set_increment(pf);
41c445ff
JB		 5697}
5698
5699/**
5700 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5701 * @pf: board private structure
5702 *
5703 * Set the per-queue flags to request a check for stuck queues in the irq
5704 * clean functions, then force interrupts to be sure the irq clean is called.
5705 **/
5706static void i40e_check_hang_subtask(struct i40e_pf *pf)
5707{
5708 int i, v;
5709
5710 /* If we're down or resetting, just bail */
b67a0335
AA		 5711 if (test_bit(__I40E_DOWN, &pf->state) ||
5712 test_bit(__I40E_CONFIG_BUSY, &pf->state))
41c445ff
JB		 5713 return;
5714
5715 /* for each VSI/netdev
5716 * for each Tx queue
5717 * set the check flag
5718 * for each q_vector
5719 * force an interrupt
5720 */
505682cd 5721 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5722 struct i40e_vsi *vsi = pf->vsi[v];
5723 int armed = 0;
5724
5725 if (!pf->vsi[v] ||
5726 test_bit(__I40E_DOWN, &vsi->state) ||
5727 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5728 continue;
5729
5730 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5731 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5732 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5733 &vsi->tx_rings[i]->state))
41c445ff
JB		 5734 armed++;
5735 }
5736
5737 if (armed) {
5738 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5739 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5740 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5d1ff106
SN		 5741 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
5742 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
5743 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
5744 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
41c445ff
JB		 5745 } else {
5746 u16 vec = vsi->base_vector - 1;
5747 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5d1ff106
SN		 5748 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
5749 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
5750 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
5751 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
41c445ff
JB		 5752 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5753 wr32(&vsi->back->hw,
5754 I40E_PFINT_DYN_CTLN(vec), val);
5755 }
5756 i40e_flush(&vsi->back->hw);
5757 }
5758 }
5759}
5760
5761/**
21536717 5762 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5763 * @pf: board private structure
5764 **/
5765static void i40e_watchdog_subtask(struct i40e_pf *pf)
5766{
5767 int i;
5768
5769 /* if interface is down do nothing */
5770 if (test_bit(__I40E_DOWN, &pf->state) ||
5771 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5772 return;
5773
21536717
SN		 5774 /* make sure we don't do these things too often */
5775 if (time_before(jiffies, (pf->service_timer_previous +
5776 pf->service_timer_period)))
5777 return;
5778 pf->service_timer_previous = jiffies;
5779
5780 i40e_check_hang_subtask(pf);
5781 i40e_link_event(pf);
5782
41c445ff
JB		 5783 /* Update the stats for active netdevs so the network stack
5784 * can look at updated numbers whenever it cares to
5785 */
505682cd 5786 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5787 if (pf->vsi[i] && pf->vsi[i]->netdev)
5788 i40e_update_stats(pf->vsi[i]);
5789
5790 /* Update the stats for the active switching components */
5791 for (i = 0; i < I40E_MAX_VEB; i++)
5792 if (pf->veb[i])
5793 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5794
5795 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5796}
5797
5798/**
5799 * i40e_reset_subtask - Set up for resetting the device and driver
5800 * @pf: board private structure
5801 **/
5802static void i40e_reset_subtask(struct i40e_pf *pf)
5803{
5804 u32 reset_flags = 0;
5805
23326186 5806 rtnl_lock();
41c445ff 5807 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 5808 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 5809 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5810 }
5811 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 5812 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 5813 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5814 }
5815 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 5816 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 5817 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5818 }
5819 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 5820 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 5821 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5822 }
b5d06f05 5823 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 5824 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 5825 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5826 }
41c445ff
JB		 5827
5828 /* If there's a recovery already waiting, it takes
5829 * precedence before starting a new reset sequence.
5830 */
5831 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5832 i40e_handle_reset_warning(pf);
23326186 5833 goto unlock;
41c445ff
JB		 5834 }
5835
5836 /* If we're already down or resetting, just bail */
5837 if (reset_flags &&
5838 !test_bit(__I40E_DOWN, &pf->state) &&
5839 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5840 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5841
5842unlock:
5843 rtnl_unlock();
41c445ff
JB		 5844}
5845
5846/**
5847 * i40e_handle_link_event - Handle link event
5848 * @pf: board private structure
5849 * @e: event info posted on ARQ
5850 **/
5851static void i40e_handle_link_event(struct i40e_pf *pf,
5852 struct i40e_arq_event_info *e)
5853{
5854 struct i40e_hw *hw = &pf->hw;
5855 struct i40e_aqc_get_link_status *status =
5856 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff
JB		 5857
5858 /* save off old link status information */
1a2f6248 5859 hw->phy.link_info_old = hw->phy.link_info;
41c445ff 5860
1e701e09
JB		 5861 /* Do a new status request to re-enable LSE reporting
5862 * and load new status information into the hw struct
5863 * This completely ignores any state information
5864 * in the ARQ event info, instead choosing to always
5865 * issue the AQ update link status command.
5866 */
5867 i40e_link_event(pf);
5868
7b592f61
CW		 5869 /* check for unqualified module, if link is down */
5870 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5871 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5872 (!(status->link_info & I40E_AQ_LINK_UP)))
5873 dev_err(&pf->pdev->dev,
5874 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5875}
5876
5877/**
5878 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5879 * @pf: board private structure
5880 **/
5881static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5882{
5883 struct i40e_arq_event_info event;
5884 struct i40e_hw *hw = &pf->hw;
5885 u16 pending, i = 0;
5886 i40e_status ret;
5887 u16 opcode;
86df242b 5888 u32 oldval;
41c445ff
JB		 5889 u32 val;
5890
a316f651
ASJ		 5891 /* Do not run clean AQ when PF reset fails */
5892 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5893 return;
5894
86df242b
SN		 5895 /* check for error indications */
5896 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5897 oldval = val;
5898 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5899 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5900 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5901 }
5902 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5903 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5904 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5905 }
5906 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5907 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5908 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5909 }
5910 if (oldval != val)
5911 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5912
5913 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5914 oldval = val;
5915 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5916 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5917 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5918 }
5919 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5920 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5921 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5922 }
5923 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5924 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5925 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5926 }
5927 if (oldval != val)
5928 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5929
1001dc37
MW		 5930 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
5931 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 5932 if (!event.msg_buf)
5933 return;
5934
5935 do {
5936 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5937 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5938 break;
56497978 5939 else if (ret) {
41c445ff
JB		 5940 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5941 break;
5942 }
5943
5944 opcode = le16_to_cpu(event.desc.opcode);
5945 switch (opcode) {
5946
5947 case i40e_aqc_opc_get_link_status:
5948 i40e_handle_link_event(pf, &event);
5949 break;
5950 case i40e_aqc_opc_send_msg_to_pf:
5951 ret = i40e_vc_process_vf_msg(pf,
5952 le16_to_cpu(event.desc.retval),
5953 le32_to_cpu(event.desc.cookie_high),
5954 le32_to_cpu(event.desc.cookie_low),
5955 event.msg_buf,
1001dc37 5956 event.msg_len);
41c445ff
JB		 5957 break;
5958 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5959 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5960#ifdef CONFIG_I40E_DCB
5961 rtnl_lock();
5962 ret = i40e_handle_lldp_event(pf, &event);
5963 rtnl_unlock();
5964#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5965 break;
5966 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5967 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5968 i40e_handle_lan_overflow_event(pf, &event);
5969 break;
0467bc91
SN		 5970 case i40e_aqc_opc_send_msg_to_peer:
5971 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5972 break;
91a0f930
SN		 5973 case i40e_aqc_opc_nvm_erase:
5974 case i40e_aqc_opc_nvm_update:
5975 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
5976 break;
41c445ff
JB		 5977 default:
5978 dev_info(&pf->pdev->dev,
0467bc91
SN		 5979 "ARQ Error: Unknown event 0x%04x received\n",
5980 opcode);
41c445ff
JB		 5981 break;
5982 }
5983 } while (pending && (i++ < pf->adminq_work_limit));
5984
5985 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5986 /* re-enable Admin queue interrupt cause */
5987 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5988 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5989 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5990 i40e_flush(hw);
5991
5992 kfree(event.msg_buf);
5993}
5994
4eb3f768
SN		 5995/**
5996 * i40e_verify_eeprom - make sure eeprom is good to use
5997 * @pf: board private structure
5998 **/
5999static void i40e_verify_eeprom(struct i40e_pf *pf)
6000{
6001 int err;
6002
6003 err = i40e_diag_eeprom_test(&pf->hw);
6004 if (err) {
6005 /* retry in case of garbage read */
6006 err = i40e_diag_eeprom_test(&pf->hw);
6007 if (err) {
6008 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6009 err);
6010 set_bit(__I40E_BAD_EEPROM, &pf->state);
6011 }
6012 }
6013
6014 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6015 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6016 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6017 }
6018}
6019
386a0afa
AA		 6020/**
6021 * i40e_enable_pf_switch_lb
b40c82e6 6022 * @pf: pointer to the PF structure
386a0afa
AA		 6023 *
6024 * enable switch loop back or die - no point in a return value
6025 **/
6026static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6027{
6028 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6029 struct i40e_vsi_context ctxt;
f1c7e72e 6030 int ret;
386a0afa
AA		 6031
6032 ctxt.seid = pf->main_vsi_seid;
6033 ctxt.pf_num = pf->hw.pf_id;
6034 ctxt.vf_num = 0;
f1c7e72e
SN		 6035 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6036 if (ret) {
386a0afa 6037 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6038 "couldn't get PF vsi config, err %s aq_err %s\n",
6039 i40e_stat_str(&pf->hw, ret),
6040 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6041 return;
6042 }
6043 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6044 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6045 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6046
f1c7e72e
SN		 6047 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6048 if (ret) {
386a0afa 6049 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6050 "update vsi switch failed, err %s aq_err %s\n",
6051 i40e_stat_str(&pf->hw, ret),
6052 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6053 }
6054}
6055
6056/**
6057 * i40e_disable_pf_switch_lb
b40c82e6 6058 * @pf: pointer to the PF structure
386a0afa
AA		 6059 *
6060 * disable switch loop back or die - no point in a return value
6061 **/
6062static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6063{
6064 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6065 struct i40e_vsi_context ctxt;
f1c7e72e 6066 int ret;
386a0afa
AA		 6067
6068 ctxt.seid = pf->main_vsi_seid;
6069 ctxt.pf_num = pf->hw.pf_id;
6070 ctxt.vf_num = 0;
f1c7e72e
SN		 6071 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6072 if (ret) {
386a0afa 6073 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6074 "couldn't get PF vsi config, err %s aq_err %s\n",
6075 i40e_stat_str(&pf->hw, ret),
6076 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6077 return;
6078 }
6079 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6080 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6081 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6082
f1c7e72e
SN		 6083 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6084 if (ret) {
386a0afa 6085 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6086 "update vsi switch failed, err %s aq_err %s\n",
6087 i40e_stat_str(&pf->hw, ret),
6088 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6089 }
6090}
6091
51616018
NP		 6092/**
6093 * i40e_config_bridge_mode - Configure the HW bridge mode
6094 * @veb: pointer to the bridge instance
6095 *
6096 * Configure the loop back mode for the LAN VSI that is downlink to the
6097 * specified HW bridge instance. It is expected this function is called
6098 * when a new HW bridge is instantiated.
6099 **/
6100static void i40e_config_bridge_mode(struct i40e_veb *veb)
6101{
6102 struct i40e_pf *pf = veb->pf;
6103
6104 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6105 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
6106 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6107 i40e_disable_pf_switch_lb(pf);
6108 else
6109 i40e_enable_pf_switch_lb(pf);
6110}
6111
41c445ff
JB		 6112/**
6113 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6114 * @veb: pointer to the VEB instance
6115 *
6116 * This is a recursive function that first builds the attached VSIs then
6117 * recurses in to build the next layer of VEB. We track the connections
6118 * through our own index numbers because the seid's from the HW could
6119 * change across the reset.
6120 **/
6121static int i40e_reconstitute_veb(struct i40e_veb *veb)
6122{
6123 struct i40e_vsi *ctl_vsi = NULL;
6124 struct i40e_pf *pf = veb->pf;
6125 int v, veb_idx;
6126 int ret;
6127
6128 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6129 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6130 if (pf->vsi[v] &&
6131 pf->vsi[v]->veb_idx == veb->idx &&
6132 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6133 ctl_vsi = pf->vsi[v];
6134 break;
6135 }
6136 }
6137 if (!ctl_vsi) {
6138 dev_info(&pf->pdev->dev,
6139 "missing owner VSI for veb_idx %d\n", veb->idx);
6140 ret = -ENOENT;
6141 goto end_reconstitute;
6142 }
6143 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6144 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6145 ret = i40e_add_vsi(ctl_vsi);
6146 if (ret) {
6147 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6148 "rebuild of veb_idx %d owner VSI failed: %d\n",
6149 veb->idx, ret);
41c445ff
JB		 6150 goto end_reconstitute;
6151 }
6152 i40e_vsi_reset_stats(ctl_vsi);
6153
6154 /* create the VEB in the switch and move the VSI onto the VEB */
6155 ret = i40e_add_veb(veb, ctl_vsi);
6156 if (ret)
6157 goto end_reconstitute;
6158
fc60861e
ASJ		 6159 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6160 veb->bridge_mode = BRIDGE_MODE_VEB;
6161 else
6162 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6163 i40e_config_bridge_mode(veb);
b64ba084 6164
41c445ff 6165 /* create the remaining VSIs attached to this VEB */
505682cd 6166 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6167 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6168 continue;
6169
6170 if (pf->vsi[v]->veb_idx == veb->idx) {
6171 struct i40e_vsi *vsi = pf->vsi[v];
6172 vsi->uplink_seid = veb->seid;
6173 ret = i40e_add_vsi(vsi);
6174 if (ret) {
6175 dev_info(&pf->pdev->dev,
6176 "rebuild of vsi_idx %d failed: %d\n",
6177 v, ret);
6178 goto end_reconstitute;
6179 }
6180 i40e_vsi_reset_stats(vsi);
6181 }
6182 }
6183
6184 /* create any VEBs attached to this VEB - RECURSION */
6185 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6186 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6187 pf->veb[veb_idx]->uplink_seid = veb->seid;
6188 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6189 if (ret)
6190 break;
6191 }
6192 }
6193
6194end_reconstitute:
6195 return ret;
6196}
6197
6198/**
6199 * i40e_get_capabilities - get info about the HW
6200 * @pf: the PF struct
6201 **/
6202static int i40e_get_capabilities(struct i40e_pf *pf)
6203{
6204 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6205 u16 data_size;
6206 int buf_len;
6207 int err;
6208
6209 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6210 do {
6211 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6212 if (!cap_buf)
6213 return -ENOMEM;
6214
6215 /* this loads the data into the hw struct for us */
6216 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6217 &data_size,
6218 i40e_aqc_opc_list_func_capabilities,
6219 NULL);
6220 /* data loaded, buffer no longer needed */
6221 kfree(cap_buf);
6222
6223 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6224 /* retry with a larger buffer */
6225 buf_len = data_size;
6226 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6227 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6228 "capability discovery failed, err %s aq_err %s\n",
6229 i40e_stat_str(&pf->hw, err),
6230 i40e_aq_str(&pf->hw,
6231 pf->hw.aq.asq_last_status));
41c445ff
JB		 6232 return -ENODEV;
6233 }
6234 } while (err);
6235
ac71b7ba
ASJ		 6236 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6237 (pf->hw.aq.fw_maj_ver < 2)) {
6238 pf->hw.func_caps.num_msix_vectors++;
6239 pf->hw.func_caps.num_msix_vectors_vf++;
6240 }
6241
41c445ff
JB		 6242 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6243 dev_info(&pf->pdev->dev,
6244 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6245 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6246 pf->hw.func_caps.num_msix_vectors,
6247 pf->hw.func_caps.num_msix_vectors_vf,
6248 pf->hw.func_caps.fd_filters_guaranteed,
6249 pf->hw.func_caps.fd_filters_best_effort,
6250 pf->hw.func_caps.num_tx_qp,
6251 pf->hw.func_caps.num_vsis);
6252
7134f9ce
JB		 6253#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6254 + pf->hw.func_caps.num_vfs)
6255 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6256 dev_info(&pf->pdev->dev,
6257 "got num_vsis %d, setting num_vsis to %d\n",
6258 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6259 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6260 }
6261
41c445ff
JB		 6262 return 0;
6263}
6264
cbf61325
ASJ		 6265static int i40e_vsi_clear(struct i40e_vsi *vsi);
6266
41c445ff 6267/**
cbf61325 6268 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6269 * @pf: board private structure
6270 **/
cbf61325 6271static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6272{
6273 struct i40e_vsi *vsi;
8a9eb7d3 6274 int i;
41c445ff 6275
407e063c
JB		 6276 /* quick workaround for an NVM issue that leaves a critical register
6277 * uninitialized
6278 */
6279 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6280 static const u32 hkey[] = {
6281 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6282 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6283 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6284 0x95b3a76d};
6285
6286 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6287 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6288 }
6289
cbf61325 6290 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6291 return;
6292
cbf61325 6293 /* find existing VSI and see if it needs configuring */
41c445ff 6294 vsi = NULL;
505682cd 6295 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6296 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6297 vsi = pf->vsi[i];
cbf61325
ASJ		 6298 break;
6299 }
6300 }
6301
6302 /* create a new VSI if none exists */
41c445ff 6303 if (!vsi) {
cbf61325
ASJ		 6304 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6305 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6306 if (!vsi) {
6307 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6308 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6309 return;
41c445ff 6310 }
cbf61325 6311 }
41c445ff 6312
8a9eb7d3 6313 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6314}
6315
6316/**
6317 * i40e_fdir_teardown - release the Flow Director resources
6318 * @pf: board private structure
6319 **/
6320static void i40e_fdir_teardown(struct i40e_pf *pf)
6321{
6322 int i;
6323
17a73f6b 6324 i40e_fdir_filter_exit(pf);
505682cd 6325 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6326 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6327 i40e_vsi_release(pf->vsi[i]);
6328 break;
6329 }
6330 }
6331}
6332
6333/**
f650a38b 6334 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6335 * @pf: board private structure
6336 *
b40c82e6 6337 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6338 **/
23cfbe07 6339static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6340{
41c445ff 6341 struct i40e_hw *hw = &pf->hw;
60442dea 6342 i40e_status ret = 0;
41c445ff
JB		 6343 u32 v;
6344
6345 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6346 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6347 return;
41c445ff 6348
69bfb110 6349 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6350
41c445ff
JB		 6351 /* quiesce the VSIs and their queues that are not already DOWN */
6352 i40e_pf_quiesce_all_vsi(pf);
6353
505682cd 6354 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6355 if (pf->vsi[v])
6356 pf->vsi[v]->seid = 0;
6357 }
6358
6359 i40e_shutdown_adminq(&pf->hw);
6360
f650a38b 6361 /* call shutdown HMC */
60442dea
SN		 6362 if (hw->hmc.hmc_obj) {
6363 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6364 if (ret)
60442dea
SN		 6365 dev_warn(&pf->pdev->dev,
6366 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6367 }
f650a38b
ASJ		 6368}
6369
44033fac
JB		 6370/**
6371 * i40e_send_version - update firmware with driver version
6372 * @pf: PF struct
6373 */
6374static void i40e_send_version(struct i40e_pf *pf)
6375{
6376 struct i40e_driver_version dv;
6377
6378 dv.major_version = DRV_VERSION_MAJOR;
6379 dv.minor_version = DRV_VERSION_MINOR;
6380 dv.build_version = DRV_VERSION_BUILD;
6381 dv.subbuild_version = 0;
35a7d804 6382 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6383 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6384}
6385
f650a38b 6386/**
4dda12e6 6387 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6388 * @pf: board private structure
bc7d338f 6389 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6390 **/
bc7d338f 6391static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6392{
f650a38b 6393 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6394 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6395 i40e_status ret;
6396 u32 v;
6397
41c445ff
JB		 6398 /* Now we wait for GRST to settle out.
6399 * We don't have to delete the VEBs or VSIs from the hw switch
6400 * because the reset will make them disappear.
6401 */
6402 ret = i40e_pf_reset(hw);
b5565400 6403 if (ret) {
41c445ff 6404 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6405 set_bit(__I40E_RESET_FAILED, &pf->state);
6406 goto clear_recovery;
b5565400 6407 }
41c445ff
JB		 6408 pf->pfr_count++;
6409
6410 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6411 goto clear_recovery;
69bfb110 6412 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6413
6414 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6415 ret = i40e_init_adminq(&pf->hw);
6416 if (ret) {
f1c7e72e
SN		 6417 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6418 i40e_stat_str(&pf->hw, ret),
6419 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6420 goto clear_recovery;
41c445ff
JB		 6421 }
6422
4eb3f768 6423 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6424 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6425 i40e_verify_eeprom(pf);
4eb3f768 6426
e78ac4bf 6427 i40e_clear_pxe_mode(hw);
41c445ff 6428 ret = i40e_get_capabilities(pf);
f1c7e72e 6429 if (ret)
41c445ff 6430 goto end_core_reset;
41c445ff 6431
41c445ff
JB		 6432 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6433 hw->func_caps.num_rx_qp,
6434 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6435 if (ret) {
6436 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6437 goto end_core_reset;
6438 }
6439 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6440 if (ret) {
6441 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6442 goto end_core_reset;
6443 }
6444
4e3b35b0
NP		 6445#ifdef CONFIG_I40E_DCB
6446 ret = i40e_init_pf_dcb(pf);
6447 if (ret) {
aebfc816
SN		 6448 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6449 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6450 /* Continue without DCB enabled */
4e3b35b0
NP		 6451 }
6452#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6453#ifdef I40E_FCOE
6454 ret = i40e_init_pf_fcoe(pf);
6455 if (ret)
6456 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6457
38e00438 6458#endif
41c445ff 6459 /* do basic switch setup */
bc7d338f 6460 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6461 if (ret)
6462 goto end_core_reset;
6463
7e2453fe
JB		 6464 /* driver is only interested in link up/down and module qualification
6465 * reports from firmware
6466 */
6467 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6468 I40E_AQ_EVENT_LINK_UPDOWN |
6469 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6470 if (ret)
f1c7e72e
SN		 6471 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6472 i40e_stat_str(&pf->hw, ret),
6473 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6474
cafa2ee6
ASJ		 6475 /* make sure our flow control settings are restored */
6476 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6477 if (ret)
f1c7e72e
SN		 6478 dev_info(&pf->pdev->dev, "set fc fail, err %s aq_err %s\n",
6479 i40e_stat_str(&pf->hw, ret),
6480 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6481
41c445ff
JB		 6482 /* Rebuild the VSIs and VEBs that existed before reset.
6483 * They are still in our local switch element arrays, so only
6484 * need to rebuild the switch model in the HW.
6485 *
6486 * If there were VEBs but the reconstitution failed, we'll try
6487 * try to recover minimal use by getting the basic PF VSI working.
6488 */
6489 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6490 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6491 /* find the one VEB connected to the MAC, and find orphans */
6492 for (v = 0; v < I40E_MAX_VEB; v++) {
6493 if (!pf->veb[v])
6494 continue;
6495
6496 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6497 pf->veb[v]->uplink_seid == 0) {
6498 ret = i40e_reconstitute_veb(pf->veb[v]);
6499
6500 if (!ret)
6501 continue;
6502
6503 /* If Main VEB failed, we're in deep doodoo,
6504 * so give up rebuilding the switch and set up
6505 * for minimal rebuild of PF VSI.
6506 * If orphan failed, we'll report the error
6507 * but try to keep going.
6508 */
6509 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6510 dev_info(&pf->pdev->dev,
6511 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6512 ret);
6513 pf->vsi[pf->lan_vsi]->uplink_seid
6514 = pf->mac_seid;
6515 break;
6516 } else if (pf->veb[v]->uplink_seid == 0) {
6517 dev_info(&pf->pdev->dev,
6518 "rebuild of orphan VEB failed: %d\n",
6519 ret);
6520 }
6521 }
6522 }
6523 }
6524
6525 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6526 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6527 /* no VEB, so rebuild only the Main VSI */
6528 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6529 if (ret) {
6530 dev_info(&pf->pdev->dev,
6531 "rebuild of Main VSI failed: %d\n", ret);
6532 goto end_core_reset;
6533 }
6534 }
6535
025b4a54
ASJ		 6536 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6537 (pf->hw.aq.fw_maj_ver < 4)) {
6538 msleep(75);
6539 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6540 if (ret)
f1c7e72e
SN		 6541 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6542 i40e_stat_str(&pf->hw, ret),
6543 i40e_aq_str(&pf->hw,
6544 pf->hw.aq.asq_last_status));
cafa2ee6 6545 }
41c445ff
JB		 6546 /* reinit the misc interrupt */
6547 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6548 ret = i40e_setup_misc_vector(pf);
6549
6550 /* restart the VSIs that were rebuilt and running before the reset */
6551 i40e_pf_unquiesce_all_vsi(pf);
6552
69f64b2b
MW		 6553 if (pf->num_alloc_vfs) {
6554 for (v = 0; v < pf->num_alloc_vfs; v++)
6555 i40e_reset_vf(&pf->vf[v], true);
6556 }
6557
41c445ff 6558 /* tell the firmware that we're starting */
44033fac 6559 i40e_send_version(pf);
41c445ff
JB		 6560
6561end_core_reset:
a316f651
ASJ		 6562 clear_bit(__I40E_RESET_FAILED, &pf->state);
6563clear_recovery:
41c445ff
JB		 6564 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6565}
6566
f650a38b 6567/**
b40c82e6 6568 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6569 * @pf: board private structure
6570 *
6571 * Close up the VFs and other things in prep for a Core Reset,
6572 * then get ready to rebuild the world.
6573 **/
6574static void i40e_handle_reset_warning(struct i40e_pf *pf)
6575{
23cfbe07
SN		 6576 i40e_prep_for_reset(pf);
6577 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6578}
6579
41c445ff
JB		 6580/**
6581 * i40e_handle_mdd_event
b40c82e6 6582 * @pf: pointer to the PF structure
41c445ff
JB		 6583 *
6584 * Called from the MDD irq handler to identify possibly malicious vfs
6585 **/
6586static void i40e_handle_mdd_event(struct i40e_pf *pf)
6587{
6588 struct i40e_hw *hw = &pf->hw;
6589 bool mdd_detected = false;
df430b12 6590 bool pf_mdd_detected = false;
41c445ff
JB		 6591 struct i40e_vf *vf;
6592 u32 reg;
6593 int i;
6594
6595 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6596 return;
6597
6598 /* find what triggered the MDD event */
6599 reg = rd32(hw, I40E_GL_MDET_TX);
6600 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6601 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6602 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6603 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6604 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6605 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6606 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6607 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6608 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6609 pf->hw.func_caps.base_queue;
faf32978 6610 if (netif_msg_tx_err(pf))
b40c82e6 6611 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6612 event, queue, pf_num, vf_num);
41c445ff
JB		 6613 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6614 mdd_detected = true;
6615 }
6616 reg = rd32(hw, I40E_GL_MDET_RX);
6617 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6618 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6619 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6620 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6621 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6622 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6623 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6624 pf->hw.func_caps.base_queue;
faf32978
JB		 6625 if (netif_msg_rx_err(pf))
6626 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6627 event, queue, func);
41c445ff
JB		 6628 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6629 mdd_detected = true;
6630 }
6631
df430b12
NP		 6632 if (mdd_detected) {
6633 reg = rd32(hw, I40E_PF_MDET_TX);
6634 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6635 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6636 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6637 pf_mdd_detected = true;
6638 }
6639 reg = rd32(hw, I40E_PF_MDET_RX);
6640 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6641 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6642 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6643 pf_mdd_detected = true;
6644 }
6645 /* Queue belongs to the PF, initiate a reset */
6646 if (pf_mdd_detected) {
6647 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6648 i40e_service_event_schedule(pf);
6649 }
6650 }
6651
41c445ff
JB		 6652 /* see if one of the VFs needs its hand slapped */
6653 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6654 vf = &(pf->vf[i]);
6655 reg = rd32(hw, I40E_VP_MDET_TX(i));
6656 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6657 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6658 vf->num_mdd_events++;
faf32978
JB		 6659 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6660 i);
41c445ff
JB		 6661 }
6662
6663 reg = rd32(hw, I40E_VP_MDET_RX(i));
6664 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6665 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6666 vf->num_mdd_events++;
faf32978
JB		 6667 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6668 i);
41c445ff
JB		 6669 }
6670
6671 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6672 dev_info(&pf->pdev->dev,
6673 "Too many MDD events on VF %d, disabled\n", i);
6674 dev_info(&pf->pdev->dev,
6675 "Use PF Control I/F to re-enable the VF\n");
6676 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6677 }
6678 }
6679
6680 /* re-enable mdd interrupt cause */
6681 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6682 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6683 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6684 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6685 i40e_flush(hw);
6686}
6687
a1c9a9d9
JK		 6688#ifdef CONFIG_I40E_VXLAN
6689/**
6690 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6691 * @pf: board private structure
6692 **/
6693static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6694{
a1c9a9d9
JK		 6695 struct i40e_hw *hw = &pf->hw;
6696 i40e_status ret;
a1c9a9d9
JK		 6697 __be16 port;
6698 int i;
6699
6700 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6701 return;
6702
6703 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6704
6705 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 6706 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
6707 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 6708 port = pf->vxlan_ports[i];
c22c06c8
SN		 6709 if (port)
6710 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 6711 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 6712 NULL, NULL);
6713 else
6714 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 6715
6716 if (ret) {
c22c06c8 6717 dev_info(&pf->pdev->dev,
f1c7e72e 6718 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 6719 port ? "add" : "delete",
f1c7e72e
SN		 6720 ntohs(port), i,
6721 i40e_stat_str(&pf->hw, ret),
6722 i40e_aq_str(&pf->hw,
6723 pf->hw.aq.asq_last_status));
a1c9a9d9 6724 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 6725 }
6726 }
6727 }
6728}
6729
6730#endif
41c445ff
JB		 6731/**
6732 * i40e_service_task - Run the driver's async subtasks
6733 * @work: pointer to work_struct containing our data
6734 **/
6735static void i40e_service_task(struct work_struct *work)
6736{
6737 struct i40e_pf *pf = container_of(work,
6738 struct i40e_pf,
6739 service_task);
6740 unsigned long start_time = jiffies;
6741
e57a2fea
SN		 6742 /* don't bother with service tasks if a reset is in progress */
6743 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6744 i40e_service_event_complete(pf);
6745 return;
6746 }
6747
41c445ff
JB		 6748 i40e_reset_subtask(pf);
6749 i40e_handle_mdd_event(pf);
6750 i40e_vc_process_vflr_event(pf);
6751 i40e_watchdog_subtask(pf);
6752 i40e_fdir_reinit_subtask(pf);
41c445ff 6753 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6754#ifdef CONFIG_I40E_VXLAN
6755 i40e_sync_vxlan_filters_subtask(pf);
6756#endif
41c445ff
JB		 6757 i40e_clean_adminq_subtask(pf);
6758
6759 i40e_service_event_complete(pf);
6760
6761 /* If the tasks have taken longer than one timer cycle or there
6762 * is more work to be done, reschedule the service task now
6763 * rather than wait for the timer to tick again.
6764 */
6765 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6766 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6767 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6768 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6769 i40e_service_event_schedule(pf);
6770}
6771
6772/**
6773 * i40e_service_timer - timer callback
6774 * @data: pointer to PF struct
6775 **/
6776static void i40e_service_timer(unsigned long data)
6777{
6778 struct i40e_pf *pf = (struct i40e_pf *)data;
6779
6780 mod_timer(&pf->service_timer,
6781 round_jiffies(jiffies + pf->service_timer_period));
6782 i40e_service_event_schedule(pf);
6783}
6784
6785/**
6786 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6787 * @vsi: the VSI being configured
6788 **/
6789static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6790{
6791 struct i40e_pf *pf = vsi->back;
6792
6793 switch (vsi->type) {
6794 case I40E_VSI_MAIN:
6795 vsi->alloc_queue_pairs = pf->num_lan_qps;
6796 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6797 I40E_REQ_DESCRIPTOR_MULTIPLE);
6798 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6799 vsi->num_q_vectors = pf->num_lan_msix;
6800 else
6801 vsi->num_q_vectors = 1;
6802
6803 break;
6804
6805 case I40E_VSI_FDIR:
6806 vsi->alloc_queue_pairs = 1;
6807 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6808 I40E_REQ_DESCRIPTOR_MULTIPLE);
6809 vsi->num_q_vectors = 1;
6810 break;
6811
6812 case I40E_VSI_VMDQ2:
6813 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6814 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6815 I40E_REQ_DESCRIPTOR_MULTIPLE);
6816 vsi->num_q_vectors = pf->num_vmdq_msix;
6817 break;
6818
6819 case I40E_VSI_SRIOV:
6820 vsi->alloc_queue_pairs = pf->num_vf_qps;
6821 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6822 I40E_REQ_DESCRIPTOR_MULTIPLE);
6823 break;
6824
38e00438
VD		 6825#ifdef I40E_FCOE
6826 case I40E_VSI_FCOE:
6827 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6828 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6829 I40E_REQ_DESCRIPTOR_MULTIPLE);
6830 vsi->num_q_vectors = pf->num_fcoe_msix;
6831 break;
6832
6833#endif /* I40E_FCOE */
41c445ff
JB		 6834 default:
6835 WARN_ON(1);
6836 return -ENODATA;
6837 }
6838
6839 return 0;
6840}
6841
f650a38b
ASJ		 6842/**
6843 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6844 * @type: VSI pointer
bc7d338f 6845 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6846 *
6847 * On error: returns error code (negative)
6848 * On success: returns 0
6849 **/
bc7d338f 6850static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6851{
6852 int size;
6853 int ret = 0;
6854
ac6c5e3d 6855 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6856 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6857 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6858 if (!vsi->tx_rings)
6859 return -ENOMEM;
f650a38b
ASJ		 6860 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6861
bc7d338f
ASJ		 6862 if (alloc_qvectors) {
6863 /* allocate memory for q_vector pointers */
f57e4fbd 6864 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6865 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6866 if (!vsi->q_vectors) {
6867 ret = -ENOMEM;
6868 goto err_vectors;
6869 }
f650a38b
ASJ		 6870 }
6871 return ret;
6872
6873err_vectors:
6874 kfree(vsi->tx_rings);
6875 return ret;
6876}
6877
41c445ff
JB		 6878/**
6879 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6880 * @pf: board private structure
6881 * @type: type of VSI
6882 *
6883 * On error: returns error code (negative)
6884 * On success: returns vsi index in PF (positive)
6885 **/
6886static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6887{
6888 int ret = -ENODEV;
6889 struct i40e_vsi *vsi;
6890 int vsi_idx;
6891 int i;
6892
6893 /* Need to protect the allocation of the VSIs at the PF level */
6894 mutex_lock(&pf->switch_mutex);
6895
6896 /* VSI list may be fragmented if VSI creation/destruction has
6897 * been happening. We can afford to do a quick scan to look
6898 * for any free VSIs in the list.
6899 *
6900 * find next empty vsi slot, looping back around if necessary
6901 */
6902 i = pf->next_vsi;
505682cd 6903 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6904 i++;
505682cd 6905 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6906 i = 0;
6907 while (i < pf->next_vsi && pf->vsi[i])
6908 i++;
6909 }
6910
505682cd 6911 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6912 vsi_idx = i; /* Found one! */
6913 } else {
6914 ret = -ENODEV;
493fb300 6915 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6916 }
6917 pf->next_vsi = ++i;
6918
6919 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6920 if (!vsi) {
6921 ret = -ENOMEM;
493fb300 6922 goto unlock_pf;
41c445ff
JB		 6923 }
6924 vsi->type = type;
6925 vsi->back = pf;
6926 set_bit(__I40E_DOWN, &vsi->state);
6927 vsi->flags = 0;
6928 vsi->idx = vsi_idx;
6929 vsi->rx_itr_setting = pf->rx_itr_default;
6930 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 6931 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
6932 pf->rss_table_size : 64;
41c445ff
JB		 6933 vsi->netdev_registered = false;
6934 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6935 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6936 vsi->irqs_ready = false;
41c445ff 6937
9f65e15b
AD		 6938 ret = i40e_set_num_rings_in_vsi(vsi);
6939 if (ret)
6940 goto err_rings;
6941
bc7d338f 6942 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6943 if (ret)
9f65e15b 6944 goto err_rings;
493fb300 6945
41c445ff
JB		 6946 /* Setup default MSIX irq handler for VSI */
6947 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6948
6949 pf->vsi[vsi_idx] = vsi;
6950 ret = vsi_idx;
493fb300
AD		 6951 goto unlock_pf;
6952
9f65e15b 6953err_rings:
493fb300
AD		 6954 pf->next_vsi = i - 1;
6955 kfree(vsi);
6956unlock_pf:
41c445ff
JB		 6957 mutex_unlock(&pf->switch_mutex);
6958 return ret;
6959}
6960
f650a38b
ASJ		 6961/**
6962 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6963 * @type: VSI pointer
bc7d338f 6964 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6965 *
6966 * On error: returns error code (negative)
6967 * On success: returns 0
6968 **/
bc7d338f 6969static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6970{
6971 /* free the ring and vector containers */
bc7d338f
ASJ		 6972 if (free_qvectors) {
6973 kfree(vsi->q_vectors);
6974 vsi->q_vectors = NULL;
6975 }
f650a38b
ASJ		 6976 kfree(vsi->tx_rings);
6977 vsi->tx_rings = NULL;
6978 vsi->rx_rings = NULL;
6979}
6980
41c445ff
JB		 6981/**
6982 * i40e_vsi_clear - Deallocate the VSI provided
6983 * @vsi: the VSI being un-configured
6984 **/
6985static int i40e_vsi_clear(struct i40e_vsi *vsi)
6986{
6987 struct i40e_pf *pf;
6988
6989 if (!vsi)
6990 return 0;
6991
6992 if (!vsi->back)
6993 goto free_vsi;
6994 pf = vsi->back;
6995
6996 mutex_lock(&pf->switch_mutex);
6997 if (!pf->vsi[vsi->idx]) {
6998 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6999 vsi->idx, vsi->idx, vsi, vsi->type);
7000 goto unlock_vsi;
7001 }
7002
7003 if (pf->vsi[vsi->idx] != vsi) {
7004 dev_err(&pf->pdev->dev,
7005 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7006 pf->vsi[vsi->idx]->idx,
7007 pf->vsi[vsi->idx],
7008 pf->vsi[vsi->idx]->type,
7009 vsi->idx, vsi, vsi->type);
7010 goto unlock_vsi;
7011 }
7012
b40c82e6 7013 /* updates the PF for this cleared vsi */
41c445ff
JB		 7014 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7015 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7016
bc7d338f 7017 i40e_vsi_free_arrays(vsi, true);
493fb300 7018
41c445ff
JB		 7019 pf->vsi[vsi->idx] = NULL;
7020 if (vsi->idx < pf->next_vsi)
7021 pf->next_vsi = vsi->idx;
7022
7023unlock_vsi:
7024 mutex_unlock(&pf->switch_mutex);
7025free_vsi:
7026 kfree(vsi);
7027
7028 return 0;
7029}
7030
9f65e15b
AD		 7031/**
7032 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7033 * @vsi: the VSI being cleaned
7034 **/
be1d5eea 7035static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7036{
7037 int i;
7038
8e9dca53 7039 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7040 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7041 kfree_rcu(vsi->tx_rings[i], rcu);
7042 vsi->tx_rings[i] = NULL;
7043 vsi->rx_rings[i] = NULL;
7044 }
be1d5eea 7045 }
9f65e15b
AD		 7046}
7047
41c445ff
JB		 7048/**
7049 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7050 * @vsi: the VSI being configured
7051 **/
7052static int i40e_alloc_rings(struct i40e_vsi *vsi)
7053{
e7046ee1 7054 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7055 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7056 int i;
7057
41c445ff 7058 /* Set basic values in the rings to be used later during open() */
d7397644 7059 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7060 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7061 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7062 if (!tx_ring)
7063 goto err_out;
41c445ff
JB		 7064
7065 tx_ring->queue_index = i;
7066 tx_ring->reg_idx = vsi->base_queue + i;
7067 tx_ring->ring_active = false;
7068 tx_ring->vsi = vsi;
7069 tx_ring->netdev = vsi->netdev;
7070 tx_ring->dev = &pf->pdev->dev;
7071 tx_ring->count = vsi->num_desc;
7072 tx_ring->size = 0;
7073 tx_ring->dcb_tc = 0;
9f65e15b 7074 vsi->tx_rings[i] = tx_ring;
41c445ff 7075
9f65e15b 7076 rx_ring = &tx_ring[1];
41c445ff
JB		 7077 rx_ring->queue_index = i;
7078 rx_ring->reg_idx = vsi->base_queue + i;
7079 rx_ring->ring_active = false;
7080 rx_ring->vsi = vsi;
7081 rx_ring->netdev = vsi->netdev;
7082 rx_ring->dev = &pf->pdev->dev;
7083 rx_ring->count = vsi->num_desc;
7084 rx_ring->size = 0;
7085 rx_ring->dcb_tc = 0;
7086 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7087 set_ring_16byte_desc_enabled(rx_ring);
7088 else
7089 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7090 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7091 }
7092
7093 return 0;
9f65e15b
AD		 7094
7095err_out:
7096 i40e_vsi_clear_rings(vsi);
7097 return -ENOMEM;
41c445ff
JB		 7098}
7099
7100/**
7101 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7102 * @pf: board private structure
7103 * @vectors: the number of MSI-X vectors to request
7104 *
7105 * Returns the number of vectors reserved, or error
7106 **/
7107static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7108{
7b37f376
AG		 7109 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7110 I40E_MIN_MSIX, vectors);
7111 if (vectors < 0) {
41c445ff 7112 dev_info(&pf->pdev->dev,
7b37f376 7113 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7114 vectors = 0;
7115 }
7116
7117 return vectors;
7118}
7119
7120/**
7121 * i40e_init_msix - Setup the MSIX capability
7122 * @pf: board private structure
7123 *
7124 * Work with the OS to set up the MSIX vectors needed.
7125 *
3b444399 7126 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7127 **/
7128static int i40e_init_msix(struct i40e_pf *pf)
7129{
41c445ff 7130 struct i40e_hw *hw = &pf->hw;
1e200e4a 7131 int vectors_left;
41c445ff 7132 int v_budget, i;
3b444399 7133 int v_actual;
41c445ff
JB		 7134
7135 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7136 return -ENODEV;
7137
7138 /* The number of vectors we'll request will be comprised of:
7139 * - Add 1 for "other" cause for Admin Queue events, etc.
7140 * - The number of LAN queue pairs
f8ff1464
ASJ		 7141 * - Queues being used for RSS.
7142 * We don't need as many as max_rss_size vectors.
7143 * use rss_size instead in the calculation since that
7144 * is governed by number of cpus in the system.
7145 * - assumes symmetric Tx/Rx pairing
41c445ff 7146 * - The number of VMDq pairs
38e00438
VD		 7147#ifdef I40E_FCOE
7148 * - The number of FCOE qps.
7149#endif
41c445ff
JB		 7150 * Once we count this up, try the request.
7151 *
7152 * If we can't get what we want, we'll simplify to nearly nothing
7153 * and try again. If that still fails, we punt.
7154 */
1e200e4a
SN		 7155 vectors_left = hw->func_caps.num_msix_vectors;
7156 v_budget = 0;
7157
7158 /* reserve one vector for miscellaneous handler */
7159 if (vectors_left) {
7160 v_budget++;
7161 vectors_left--;
7162 }
7163
7164 /* reserve vectors for the main PF traffic queues */
7165 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7166 vectors_left -= pf->num_lan_msix;
7167 v_budget += pf->num_lan_msix;
7168
7169 /* reserve one vector for sideband flow director */
7170 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7171 if (vectors_left) {
7172 v_budget++;
7173 vectors_left--;
7174 } else {
7175 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7176 }
7177 }
83840e4b 7178
38e00438 7179#ifdef I40E_FCOE
1e200e4a 7180 /* can we reserve enough for FCoE? */
38e00438 7181 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7182 if (!vectors_left)
7183 pf->num_fcoe_msix = 0;
7184 else if (vectors_left >= pf->num_fcoe_qps)
7185 pf->num_fcoe_msix = pf->num_fcoe_qps;
7186 else
7187 pf->num_fcoe_msix = 1;
38e00438 7188 v_budget += pf->num_fcoe_msix;
1e200e4a 7189 vectors_left -= pf->num_fcoe_msix;
38e00438 7190 }
1e200e4a 7191
38e00438 7192#endif
1e200e4a
SN		 7193 /* any vectors left over go for VMDq support */
7194 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7195 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7196 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7197
7198 /* if we're short on vectors for what's desired, we limit
7199 * the queues per vmdq. If this is still more than are
7200 * available, the user will need to change the number of
7201 * queues/vectors used by the PF later with the ethtool
7202 * channels command
7203 */
7204 if (vmdq_vecs < vmdq_vecs_wanted)
7205 pf->num_vmdq_qps = 1;
7206 pf->num_vmdq_msix = pf->num_vmdq_qps;
7207
7208 v_budget += vmdq_vecs;
7209 vectors_left -= vmdq_vecs;
7210 }
41c445ff
JB		 7211
7212 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7213 GFP_KERNEL);
7214 if (!pf->msix_entries)
7215 return -ENOMEM;
7216
7217 for (i = 0; i < v_budget; i++)
7218 pf->msix_entries[i].entry = i;
3b444399 7219 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7220
3b444399 7221 if (v_actual != v_budget) {
a34977ba
ASJ		 7222 /* If we have limited resources, we will start with no vectors
7223 * for the special features and then allocate vectors to some
7224 * of these features based on the policy and at the end disable
7225 * the features that did not get any vectors.
7226 */
38e00438
VD		 7227#ifdef I40E_FCOE
7228 pf->num_fcoe_qps = 0;
7229 pf->num_fcoe_msix = 0;
7230#endif
a34977ba
ASJ		 7231 pf->num_vmdq_msix = 0;
7232 }
7233
3b444399 7234 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7235 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7236 kfree(pf->msix_entries);
7237 pf->msix_entries = NULL;
7238 return -ENODEV;
7239
3b444399 7240 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7241 /* Adjust for minimal MSIX use */
41c445ff
JB		 7242 pf->num_vmdq_vsis = 0;
7243 pf->num_vmdq_qps = 0;
41c445ff
JB		 7244 pf->num_lan_qps = 1;
7245 pf->num_lan_msix = 1;
7246
3b444399
SN		 7247 } else if (v_actual != v_budget) {
7248 int vec;
7249
a34977ba 7250 /* reserve the misc vector */
3b444399 7251 vec = v_actual - 1;
a34977ba 7252
41c445ff
JB		 7253 /* Scale vector usage down */
7254 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7255 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7256 pf->num_vmdq_qps = 1;
7257 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7258
7259 /* partition out the remaining vectors */
7260 switch (vec) {
7261 case 2:
41c445ff
JB		 7262 pf->num_lan_msix = 1;
7263 break;
7264 case 3:
38e00438
VD		 7265#ifdef I40E_FCOE
7266 /* give one vector to FCoE */
7267 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7268 pf->num_lan_msix = 1;
7269 pf->num_fcoe_msix = 1;
7270 }
7271#else
41c445ff 7272 pf->num_lan_msix = 2;
38e00438 7273#endif
41c445ff
JB		 7274 break;
7275 default:
38e00438
VD		 7276#ifdef I40E_FCOE
7277 /* give one vector to FCoE */
7278 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7279 pf->num_fcoe_msix = 1;
7280 vec--;
7281 }
7282#endif
1e200e4a
SN		 7283 /* give the rest to the PF */
7284 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7285 break;
7286 }
7287 }
7288
a34977ba
ASJ		 7289 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7290 (pf->num_vmdq_msix == 0)) {
7291 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7292 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7293 }
38e00438
VD		 7294#ifdef I40E_FCOE
7295
7296 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7297 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7298 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7299 }
7300#endif
3b444399 7301 return v_actual;
41c445ff
JB		 7302}
7303
493fb300 7304/**
90e04070 7305 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7306 * @vsi: the VSI being configured
7307 * @v_idx: index of the vector in the vsi struct
7308 *
7309 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7310 **/
90e04070 7311static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7312{
7313 struct i40e_q_vector *q_vector;
7314
7315 /* allocate q_vector */
7316 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7317 if (!q_vector)
7318 return -ENOMEM;
7319
7320 q_vector->vsi = vsi;
7321 q_vector->v_idx = v_idx;
7322 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7323 if (vsi->netdev)
7324 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7325 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7326
cd0b6fa6
AD		 7327 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7328 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7329
493fb300
AD		 7330 /* tie q_vector and vsi together */
7331 vsi->q_vectors[v_idx] = q_vector;
7332
7333 return 0;
7334}
7335
41c445ff 7336/**
90e04070 7337 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7338 * @vsi: the VSI being configured
7339 *
7340 * We allocate one q_vector per queue interrupt. If allocation fails we
7341 * return -ENOMEM.
7342 **/
90e04070 7343static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7344{
7345 struct i40e_pf *pf = vsi->back;
7346 int v_idx, num_q_vectors;
493fb300 7347 int err;
41c445ff
JB		 7348
7349 /* if not MSIX, give the one vector only to the LAN VSI */
7350 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7351 num_q_vectors = vsi->num_q_vectors;
7352 else if (vsi == pf->vsi[pf->lan_vsi])
7353 num_q_vectors = 1;
7354 else
7355 return -EINVAL;
7356
41c445ff 7357 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7358 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7359 if (err)
7360 goto err_out;
41c445ff
JB		 7361 }
7362
7363 return 0;
493fb300
AD		 7364
7365err_out:
7366 while (v_idx--)
7367 i40e_free_q_vector(vsi, v_idx);
7368
7369 return err;
41c445ff
JB		 7370}
7371
7372/**
7373 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7374 * @pf: board private structure to initialize
7375 **/
c1147280 7376static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7377{
3b444399
SN		 7378 int vectors = 0;
7379 ssize_t size;
41c445ff
JB		 7380
7381 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7382 vectors = i40e_init_msix(pf);
7383 if (vectors < 0) {
60ea5f83 7384 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7385#ifdef I40E_FCOE
7386 I40E_FLAG_FCOE_ENABLED |
7387#endif
60ea5f83 7388 I40E_FLAG_RSS_ENABLED |
4d9b6043 7389 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7390 I40E_FLAG_SRIOV_ENABLED |
7391 I40E_FLAG_FD_SB_ENABLED |
7392 I40E_FLAG_FD_ATR_ENABLED |
7393 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7394
7395 /* rework the queue expectations without MSIX */
7396 i40e_determine_queue_usage(pf);
7397 }
7398 }
7399
7400 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7401 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7402 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7403 vectors = pci_enable_msi(pf->pdev);
7404 if (vectors < 0) {
7405 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7406 vectors);
41c445ff
JB		 7407 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7408 }
3b444399 7409 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7410 }
7411
958a3e3b 7412 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7413 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7414
3b444399
SN		 7415 /* set up vector assignment tracking */
7416 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7417 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7418 if (!pf->irq_pile) {
7419 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7420 return -ENOMEM;
7421 }
3b444399
SN		 7422 pf->irq_pile->num_entries = vectors;
7423 pf->irq_pile->search_hint = 0;
7424
c1147280 7425 /* track first vector for misc interrupts, ignore return */
3b444399 7426 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7427
7428 return 0;
41c445ff
JB		 7429}
7430
7431/**
7432 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7433 * @pf: board private structure
7434 *
7435 * This sets up the handler for MSIX 0, which is used to manage the
7436 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7437 * when in MSI or Legacy interrupt mode.
7438 **/
7439static int i40e_setup_misc_vector(struct i40e_pf *pf)
7440{
7441 struct i40e_hw *hw = &pf->hw;
7442 int err = 0;
7443
7444 /* Only request the irq if this is the first time through, and
7445 * not when we're rebuilding after a Reset
7446 */
7447 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7448 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7449 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7450 if (err) {
7451 dev_info(&pf->pdev->dev,
77fa28be 7452 "request_irq for %s failed: %d\n",
b294ac70 7453 pf->int_name, err);
41c445ff
JB		 7454 return -EFAULT;
7455 }
7456 }
7457
ab437b5a 7458 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7459
7460 /* associate no queues to the misc vector */
7461 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7462 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7463
7464 i40e_flush(hw);
7465
7466 i40e_irq_dynamic_enable_icr0(pf);
7467
7468 return err;
7469}
7470
7471/**
7472 * i40e_config_rss - Prepare for RSS if used
7473 * @pf: board private structure
7474 **/
7475static int i40e_config_rss(struct i40e_pf *pf)
7476{
22f258a1 7477 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
66ddcffb 7478 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0
ASJ		 7479 struct i40e_hw *hw = &pf->hw;
7480 u32 lut = 0;
7481 int i, j;
7482 u64 hena;
e157ea30 7483 u32 reg_val;
41c445ff 7484
22f258a1 7485 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7486 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7487 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7488
7489 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7490 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7491 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7492 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7493 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7494 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7495
66ddcffb
ASJ		 7496 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7497
e157ea30
CW		 7498 /* Check capability and Set table size and register per hw expectation*/
7499 reg_val = rd32(hw, I40E_PFQF_CTL_0);
d9e894ee 7500 if (pf->rss_table_size == 512)
e157ea30 7501 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
d9e894ee 7502 else
e157ea30 7503 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
e157ea30
CW		 7504 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7505
41c445ff 7506 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7507 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7508
7509 /* The assumption is that lan qp count will be the highest
7510 * qp count for any PF VSI that needs RSS.
7511 * If multiple VSIs need RSS support, all the qp counts
7512 * for those VSIs should be a power of 2 for RSS to work.
7513 * If LAN VSI is the only consumer for RSS then this requirement
7514 * is not necessary.
7515 */
66ddcffb 7516 if (j == vsi->rss_size)
41c445ff
JB		 7517 j = 0;
7518 /* lut = 4-byte sliding window of 4 lut entries */
7519 lut = (lut << 8) | (j &
41a1d04b 7520 (BIT(pf->hw.func_caps.rss_table_entry_width) - 1));
41c445ff
JB		 7521 /* On i = 3, we have 4 entries in lut; write to the register */
7522 if ((i & 3) == 3)
7523 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7524 }
7525 i40e_flush(hw);
7526
7527 return 0;
7528}
7529
f8ff1464
ASJ		 7530/**
7531 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7532 * @pf: board private structure
7533 * @queue_count: the requested queue count for rss.
7534 *
7535 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7536 * count which may be different from the requested queue count.
7537 **/
7538int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7539{
9a3bd2f1
ASJ		 7540 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7541 int new_rss_size;
7542
f8ff1464
ASJ		 7543 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7544 return 0;
7545
9a3bd2f1 7546 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7547
9a3bd2f1
ASJ		 7548 if (queue_count != vsi->num_queue_pairs) {
7549 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7550 i40e_prep_for_reset(pf);
7551
9a3bd2f1 7552 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7553
7554 i40e_reset_and_rebuild(pf, true);
7555 i40e_config_rss(pf);
7556 }
7557 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7558 return pf->rss_size;
7559}
7560
f4492db1
GR		 7561/**
7562 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7563 * @pf: board private structure
7564 **/
7565i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7566{
7567 i40e_status status;
7568 bool min_valid, max_valid;
7569 u32 max_bw, min_bw;
7570
7571 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7572 &min_valid, &max_valid);
7573
7574 if (!status) {
7575 if (min_valid)
7576 pf->npar_min_bw = min_bw;
7577 if (max_valid)
7578 pf->npar_max_bw = max_bw;
7579 }
7580
7581 return status;
7582}
7583
7584/**
7585 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7586 * @pf: board private structure
7587 **/
7588i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7589{
7590 struct i40e_aqc_configure_partition_bw_data bw_data;
7591 i40e_status status;
7592
b40c82e6 7593 /* Set the valid bit for this PF */
41a1d04b 7594 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 7595 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7596 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7597
7598 /* Set the new bandwidths */
7599 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7600
7601 return status;
7602}
7603
7604/**
7605 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7606 * @pf: board private structure
7607 **/
7608i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7609{
7610 /* Commit temporary BW setting to permanent NVM image */
7611 enum i40e_admin_queue_err last_aq_status;
7612 i40e_status ret;
7613 u16 nvm_word;
7614
7615 if (pf->hw.partition_id != 1) {
7616 dev_info(&pf->pdev->dev,
7617 "Commit BW only works on partition 1! This is partition %d",
7618 pf->hw.partition_id);
7619 ret = I40E_NOT_SUPPORTED;
7620 goto bw_commit_out;
7621 }
7622
7623 /* Acquire NVM for read access */
7624 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7625 last_aq_status = pf->hw.aq.asq_last_status;
7626 if (ret) {
7627 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7628 "Cannot acquire NVM for read access, err %s aq_err %s\n",
7629 i40e_stat_str(&pf->hw, ret),
7630 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7631 goto bw_commit_out;
7632 }
7633
7634 /* Read word 0x10 of NVM - SW compatibility word 1 */
7635 ret = i40e_aq_read_nvm(&pf->hw,
7636 I40E_SR_NVM_CONTROL_WORD,
7637 0x10, sizeof(nvm_word), &nvm_word,
7638 false, NULL);
7639 /* Save off last admin queue command status before releasing
7640 * the NVM
7641 */
7642 last_aq_status = pf->hw.aq.asq_last_status;
7643 i40e_release_nvm(&pf->hw);
7644 if (ret) {
f1c7e72e
SN		 7645 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
7646 i40e_stat_str(&pf->hw, ret),
7647 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7648 goto bw_commit_out;
7649 }
7650
7651 /* Wait a bit for NVM release to complete */
7652 msleep(50);
7653
7654 /* Acquire NVM for write access */
7655 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7656 last_aq_status = pf->hw.aq.asq_last_status;
7657 if (ret) {
7658 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7659 "Cannot acquire NVM for write access, err %s aq_err %s\n",
7660 i40e_stat_str(&pf->hw, ret),
7661 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7662 goto bw_commit_out;
7663 }
7664 /* Write it back out unchanged to initiate update NVM,
7665 * which will force a write of the shadow (alt) RAM to
7666 * the NVM - thus storing the bandwidth values permanently.
7667 */
7668 ret = i40e_aq_update_nvm(&pf->hw,
7669 I40E_SR_NVM_CONTROL_WORD,
7670 0x10, sizeof(nvm_word),
7671 &nvm_word, true, NULL);
7672 /* Save off last admin queue command status before releasing
7673 * the NVM
7674 */
7675 last_aq_status = pf->hw.aq.asq_last_status;
7676 i40e_release_nvm(&pf->hw);
7677 if (ret)
7678 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 7679 "BW settings NOT SAVED, err %s aq_err %s\n",
7680 i40e_stat_str(&pf->hw, ret),
7681 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 7682bw_commit_out:
7683
7684 return ret;
7685}
7686
41c445ff
JB		 7687/**
7688 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7689 * @pf: board private structure to initialize
7690 *
7691 * i40e_sw_init initializes the Adapter private data structure.
7692 * Fields are initialized based on PCI device information and
7693 * OS network device settings (MTU size).
7694 **/
7695static int i40e_sw_init(struct i40e_pf *pf)
7696{
7697 int err = 0;
7698 int size;
7699
7700 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7701 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7702 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7703 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7704 if (I40E_DEBUG_USER & debug)
7705 pf->hw.debug_mask = debug;
7706 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7707 I40E_DEFAULT_MSG_ENABLE);
7708 }
7709
7710 /* Set default capability flags */
7711 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7712 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7713 I40E_FLAG_MSIX_ENABLED;
7714
7715 if (iommu_present(&pci_bus_type))
7716 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7717 else
7718 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7719
ca99eb99
MW		 7720 /* Set default ITR */
7721 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7722 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7723
7134f9ce
JB		 7724 /* Depending on PF configurations, it is possible that the RSS
7725 * maximum might end up larger than the available queues
7726 */
41a1d04b 7727 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
ec9a7db7 7728 pf->rss_size = 1;
5db4cb59 7729 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7730 pf->rss_size_max = min_t(int, pf->rss_size_max,
7731 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7732 if (pf->hw.func_caps.rss) {
7733 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7734 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7735 }
7736
2050bc65 7737 /* MFP mode enabled */
c78b953e 7738 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 7739 pf->flags |= I40E_FLAG_MFP_ENABLED;
7740 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7741 if (i40e_get_npar_bw_setting(pf))
7742 dev_warn(&pf->pdev->dev,
7743 "Could not get NPAR bw settings\n");
7744 else
7745 dev_info(&pf->pdev->dev,
7746 "Min BW = %8.8x, Max BW = %8.8x\n",
7747 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7748 }
7749
cbf61325
ASJ		 7750 /* FW/NVM is not yet fixed in this regard */
7751 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7752 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7753 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7754 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 7755 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7756 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 7757 } else {
7758 dev_info(&pf->pdev->dev,
0b67584f 7759 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7760 }
cbf61325
ASJ		 7761 pf->fdir_pf_filter_count =
7762 pf->hw.func_caps.fd_filters_guaranteed;
7763 pf->hw.fdir_shared_filter_count =
7764 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7765 }
7766
7767 if (pf->hw.func_caps.vmdq) {
7768 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7769 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7770 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7771 }
7772
38e00438
VD		 7773#ifdef I40E_FCOE
7774 err = i40e_init_pf_fcoe(pf);
7775 if (err)
7776 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7777
7778#endif /* I40E_FCOE */
41c445ff 7779#ifdef CONFIG_PCI_IOV
ba252f13 7780 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7781 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7782 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7783 pf->num_req_vfs = min_t(int,
7784 pf->hw.func_caps.num_vfs,
7785 I40E_MAX_VF_COUNT);
7786 }
7787#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 7788 if (pf->hw.mac.type == I40E_MAC_X722) {
7789 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
7790 I40E_FLAG_128_QP_RSS_CAPABLE |
7791 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
7792 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
7793 I40E_FLAG_WB_ON_ITR_CAPABLE |
7794 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
7795 }
41c445ff
JB		 7796 pf->eeprom_version = 0xDEAD;
7797 pf->lan_veb = I40E_NO_VEB;
7798 pf->lan_vsi = I40E_NO_VSI;
7799
7800 /* set up queue assignment tracking */
7801 size = sizeof(struct i40e_lump_tracking)
7802 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7803 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7804 if (!pf->qp_pile) {
7805 err = -ENOMEM;
7806 goto sw_init_done;
7807 }
7808 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7809 pf->qp_pile->search_hint = 0;
7810
327fe04b
ASJ		 7811 pf->tx_timeout_recovery_level = 1;
7812
41c445ff
JB		 7813 mutex_init(&pf->switch_mutex);
7814
c668a12c
GR		 7815 /* If NPAR is enabled nudge the Tx scheduler */
7816 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
7817 i40e_set_npar_bw_setting(pf);
7818
41c445ff
JB		 7819sw_init_done:
7820 return err;
7821}
7822
7c3c288b
ASJ		 7823/**
7824 * i40e_set_ntuple - set the ntuple feature flag and take action
7825 * @pf: board private structure to initialize
7826 * @features: the feature set that the stack is suggesting
7827 *
7828 * returns a bool to indicate if reset needs to happen
7829 **/
7830bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7831{
7832 bool need_reset = false;
7833
7834 /* Check if Flow Director n-tuple support was enabled or disabled. If
7835 * the state changed, we need to reset.
7836 */
7837 if (features & NETIF_F_NTUPLE) {
7838 /* Enable filters and mark for reset */
7839 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7840 need_reset = true;
7841 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7842 } else {
7843 /* turn off filters, mark for reset and clear SW filter list */
7844 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7845 need_reset = true;
7846 i40e_fdir_filter_exit(pf);
7847 }
7848 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7849 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7850 /* reset fd counters */
7851 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7852 pf->fdir_pf_active_filters = 0;
7853 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 7854 if (I40E_DEBUG_FD & pf->hw.debug_mask)
7855 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7856 /* if ATR was auto disabled it can be re-enabled. */
7857 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7858 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7859 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7860 }
7861 return need_reset;
7862}
7863
41c445ff
JB		 7864/**
7865 * i40e_set_features - set the netdev feature flags
7866 * @netdev: ptr to the netdev being adjusted
7867 * @features: the feature set that the stack is suggesting
7868 **/
7869static int i40e_set_features(struct net_device *netdev,
7870 netdev_features_t features)
7871{
7872 struct i40e_netdev_priv *np = netdev_priv(netdev);
7873 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7874 struct i40e_pf *pf = vsi->back;
7875 bool need_reset;
41c445ff
JB		 7876
7877 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7878 i40e_vlan_stripping_enable(vsi);
7879 else
7880 i40e_vlan_stripping_disable(vsi);
7881
7c3c288b
ASJ		 7882 need_reset = i40e_set_ntuple(pf, features);
7883
7884 if (need_reset)
41a1d04b 7885 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 7886
41c445ff
JB		 7887 return 0;
7888}
7889
a1c9a9d9
JK		 7890#ifdef CONFIG_I40E_VXLAN
7891/**
7892 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7893 * @pf: board private structure
7894 * @port: The UDP port to look up
7895 *
7896 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7897 **/
7898static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7899{
7900 u8 i;
7901
7902 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7903 if (pf->vxlan_ports[i] == port)
7904 return i;
7905 }
7906
7907 return i;
7908}
7909
7910/**
7911 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7912 * @netdev: This physical port's netdev
7913 * @sa_family: Socket Family that VXLAN is notifying us about
7914 * @port: New UDP port number that VXLAN started listening to
7915 **/
7916static void i40e_add_vxlan_port(struct net_device *netdev,
7917 sa_family_t sa_family, __be16 port)
7918{
7919 struct i40e_netdev_priv *np = netdev_priv(netdev);
7920 struct i40e_vsi *vsi = np->vsi;
7921 struct i40e_pf *pf = vsi->back;
7922 u8 next_idx;
7923 u8 idx;
7924
7925 if (sa_family == AF_INET6)
7926 return;
7927
7928 idx = i40e_get_vxlan_port_idx(pf, port);
7929
7930 /* Check if port already exists */
7931 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 7932 netdev_info(netdev, "vxlan port %d already offloaded\n",
7933 ntohs(port));
a1c9a9d9
JK		 7934 return;
7935 }
7936
7937 /* Now check if there is space to add the new port */
7938 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7939
7940 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 7941 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 7942 ntohs(port));
7943 return;
7944 }
7945
7946 /* New port: add it and mark its index in the bitmap */
7947 pf->vxlan_ports[next_idx] = port;
41a1d04b 7948 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9 7949 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
c22c06c8
SN		 7950
7951 dev_info(&pf->pdev->dev, "adding vxlan port %d\n", ntohs(port));
a1c9a9d9
JK		 7952}
7953
7954/**
7955 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7956 * @netdev: This physical port's netdev
7957 * @sa_family: Socket Family that VXLAN is notifying us about
7958 * @port: UDP port number that VXLAN stopped listening to
7959 **/
7960static void i40e_del_vxlan_port(struct net_device *netdev,
7961 sa_family_t sa_family, __be16 port)
7962{
7963 struct i40e_netdev_priv *np = netdev_priv(netdev);
7964 struct i40e_vsi *vsi = np->vsi;
7965 struct i40e_pf *pf = vsi->back;
7966 u8 idx;
7967
7968 if (sa_family == AF_INET6)
7969 return;
7970
7971 idx = i40e_get_vxlan_port_idx(pf, port);
7972
7973 /* Check if port already exists */
7974 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7975 /* if port exists, set it to 0 (mark for deletion)
7976 * and make it pending
7977 */
7978 pf->vxlan_ports[idx] = 0;
41a1d04b 7979 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9 7980 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
c22c06c8
SN		 7981
7982 dev_info(&pf->pdev->dev, "deleting vxlan port %d\n",
7983 ntohs(port));
a1c9a9d9 7984 } else {
c22c06c8 7985 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 7986 ntohs(port));
7987 }
7988}
7989
7990#endif
1f224ad2 7991static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 7992 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 7993{
7994 struct i40e_netdev_priv *np = netdev_priv(netdev);
7995 struct i40e_pf *pf = np->vsi->back;
7996 struct i40e_hw *hw = &pf->hw;
7997
7998 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7999 return -EOPNOTSUPP;
8000
8001 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8002 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8003
8004 return 0;
8005}
8006
2f90ade6
JB		 8007/**
8008 * i40e_ndo_fdb_add - add an entry to the hardware database
8009 * @ndm: the input from the stack
8010 * @tb: pointer to array of nladdr (unused)
8011 * @dev: the net device pointer
8012 * @addr: the MAC address entry being added
8013 * @flags: instructions from stack about fdb operation
8014 */
4ba0dea5
GR		 8015static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8016 struct net_device *dev,
f6f6424b 8017 const unsigned char *addr, u16 vid,
4ba0dea5 8018 u16 flags)
4ba0dea5
GR		 8019{
8020 struct i40e_netdev_priv *np = netdev_priv(dev);
8021 struct i40e_pf *pf = np->vsi->back;
8022 int err = 0;
8023
8024 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8025 return -EOPNOTSUPP;
8026
65891fea
OG		 8027 if (vid) {
8028 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8029 return -EINVAL;
8030 }
8031
4ba0dea5
GR		 8032 /* Hardware does not support aging addresses so if a
8033 * ndm_state is given only allow permanent addresses
8034 */
8035 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8036 netdev_info(dev, "FDB only supports static addresses\n");
8037 return -EINVAL;
8038 }
8039
8040 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8041 err = dev_uc_add_excl(dev, addr);
8042 else if (is_multicast_ether_addr(addr))
8043 err = dev_mc_add_excl(dev, addr);
8044 else
8045 err = -EINVAL;
8046
8047 /* Only return duplicate errors if NLM_F_EXCL is set */
8048 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8049 err = 0;
8050
8051 return err;
8052}
8053
51616018
NP		 8054/**
8055 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8056 * @dev: the netdev being configured
8057 * @nlh: RTNL message
8058 *
8059 * Inserts a new hardware bridge if not already created and
8060 * enables the bridging mode requested (VEB or VEPA). If the
8061 * hardware bridge has already been inserted and the request
8062 * is to change the mode then that requires a PF reset to
8063 * allow rebuild of the components with required hardware
8064 * bridge mode enabled.
8065 **/
8066static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8067 struct nlmsghdr *nlh,
8068 u16 flags)
51616018
NP		 8069{
8070 struct i40e_netdev_priv *np = netdev_priv(dev);
8071 struct i40e_vsi *vsi = np->vsi;
8072 struct i40e_pf *pf = vsi->back;
8073 struct i40e_veb *veb = NULL;
8074 struct nlattr *attr, *br_spec;
8075 int i, rem;
8076
8077 /* Only for PF VSI for now */
8078 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8079 return -EOPNOTSUPP;
8080
8081 /* Find the HW bridge for PF VSI */
8082 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8083 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8084 veb = pf->veb[i];
8085 }
8086
8087 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8088
8089 nla_for_each_nested(attr, br_spec, rem) {
8090 __u16 mode;
8091
8092 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8093 continue;
8094
8095 mode = nla_get_u16(attr);
8096 if ((mode != BRIDGE_MODE_VEPA) &&
8097 (mode != BRIDGE_MODE_VEB))
8098 return -EINVAL;
8099
8100 /* Insert a new HW bridge */
8101 if (!veb) {
8102 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8103 vsi->tc_config.enabled_tc);
8104 if (veb) {
8105 veb->bridge_mode = mode;
8106 i40e_config_bridge_mode(veb);
8107 } else {
8108 /* No Bridge HW offload available */
8109 return -ENOENT;
8110 }
8111 break;
8112 } else if (mode != veb->bridge_mode) {
8113 /* Existing HW bridge but different mode needs reset */
8114 veb->bridge_mode = mode;
fc60861e
ASJ		 8115 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8116 if (mode == BRIDGE_MODE_VEB)
8117 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8118 else
8119 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8120 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8121 break;
8122 }
8123 }
8124
8125 return 0;
8126}
8127
8128/**
8129 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8130 * @skb: skb buff
8131 * @pid: process id
8132 * @seq: RTNL message seq #
8133 * @dev: the netdev being configured
8134 * @filter_mask: unused
8135 *
8136 * Return the mode in which the hardware bridge is operating in
8137 * i.e VEB or VEPA.
8138 **/
51616018
NP		 8139static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8140 struct net_device *dev,
7d4f8d87 8141 u32 filter_mask, int nlflags)
51616018
NP		 8142{
8143 struct i40e_netdev_priv *np = netdev_priv(dev);
8144 struct i40e_vsi *vsi = np->vsi;
8145 struct i40e_pf *pf = vsi->back;
8146 struct i40e_veb *veb = NULL;
8147 int i;
8148
8149 /* Only for PF VSI for now */
8150 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8151 return -EOPNOTSUPP;
8152
8153 /* Find the HW bridge for the PF VSI */
8154 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8155 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8156 veb = pf->veb[i];
8157 }
8158
8159 if (!veb)
8160 return 0;
8161
46c264da 8162 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8163 nlflags, 0, 0, filter_mask, NULL);
51616018 8164}
51616018 8165
f44a75e2
JS		 8166#define I40E_MAX_TUNNEL_HDR_LEN 80
8167/**
8168 * i40e_features_check - Validate encapsulated packet conforms to limits
8169 * @skb: skb buff
8170 * @netdev: This physical port's netdev
8171 * @features: Offload features that the stack believes apply
8172 **/
8173static netdev_features_t i40e_features_check(struct sk_buff *skb,
8174 struct net_device *dev,
8175 netdev_features_t features)
8176{
8177 if (skb->encapsulation &&
8178 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8179 I40E_MAX_TUNNEL_HDR_LEN))
8180 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8181
8182 return features;
8183}
8184
37a2973a 8185static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8186 .ndo_open = i40e_open,
8187 .ndo_stop = i40e_close,
8188 .ndo_start_xmit = i40e_lan_xmit_frame,
8189 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8190 .ndo_set_rx_mode = i40e_set_rx_mode,
8191 .ndo_validate_addr = eth_validate_addr,
8192 .ndo_set_mac_address = i40e_set_mac,
8193 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8194 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8195 .ndo_tx_timeout = i40e_tx_timeout,
8196 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8197 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8198#ifdef CONFIG_NET_POLL_CONTROLLER
8199 .ndo_poll_controller = i40e_netpoll,
8200#endif
8201 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8202#ifdef I40E_FCOE
8203 .ndo_fcoe_enable = i40e_fcoe_enable,
8204 .ndo_fcoe_disable = i40e_fcoe_disable,
8205#endif
41c445ff
JB		 8206 .ndo_set_features = i40e_set_features,
8207 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8208 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8209 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8210 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8211 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8212 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8213#ifdef CONFIG_I40E_VXLAN
8214 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8215 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8216#endif
1f224ad2 8217 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8218 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8219 .ndo_features_check = i40e_features_check,
51616018
NP		 8220 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8221 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8222};
8223
8224/**
8225 * i40e_config_netdev - Setup the netdev flags
8226 * @vsi: the VSI being configured
8227 *
8228 * Returns 0 on success, negative value on failure
8229 **/
8230static int i40e_config_netdev(struct i40e_vsi *vsi)
8231{
1a10370a 8232 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8233 struct i40e_pf *pf = vsi->back;
8234 struct i40e_hw *hw = &pf->hw;
8235 struct i40e_netdev_priv *np;
8236 struct net_device *netdev;
8237 u8 mac_addr[ETH_ALEN];
8238 int etherdev_size;
8239
8240 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8241 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8242 if (!netdev)
8243 return -ENOMEM;
8244
8245 vsi->netdev = netdev;
8246 np = netdev_priv(netdev);
8247 np->vsi = vsi;
8248
d70e941b 8249 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8250 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8251 NETIF_F_TSO;
41c445ff
JB		 8252
8253 netdev->features = NETIF_F_SG |
8254 NETIF_F_IP_CSUM |
8255 NETIF_F_SCTP_CSUM |
8256 NETIF_F_HIGHDMA |
8257 NETIF_F_GSO_UDP_TUNNEL |
8258 NETIF_F_HW_VLAN_CTAG_TX |
8259 NETIF_F_HW_VLAN_CTAG_RX |
8260 NETIF_F_HW_VLAN_CTAG_FILTER |
8261 NETIF_F_IPV6_CSUM |
8262 NETIF_F_TSO |
059dab69 8263 NETIF_F_TSO_ECN |
41c445ff
JB		 8264 NETIF_F_TSO6 |
8265 NETIF_F_RXCSUM |
8266 NETIF_F_RXHASH |
8267 0;
8268
2e86a0b6
ASJ		 8269 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8270 netdev->features |= NETIF_F_NTUPLE;
8271
41c445ff
JB		 8272 /* copy netdev features into list of user selectable features */
8273 netdev->hw_features |= netdev->features;
8274
8275 if (vsi->type == I40E_VSI_MAIN) {
8276 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8277 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8278 /* The following steps are necessary to prevent reception
8279 * of tagged packets - some older NVM configurations load a
8280 * default a MAC-VLAN filter that accepts any tagged packet
8281 * which must be replaced by a normal filter.
8c27d42e 8282 */
30650cc5
SN		 8283 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8284 i40e_add_filter(vsi, mac_addr,
8285 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8286 } else {
8287 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8288 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8289 pf->vsi[pf->lan_vsi]->netdev->name);
8290 random_ether_addr(mac_addr);
8291 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8292 }
1a10370a 8293 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8294
9a173901
GR		 8295 ether_addr_copy(netdev->dev_addr, mac_addr);
8296 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8297 /* vlan gets same features (except vlan offload)
8298 * after any tweaks for specific VSI types
8299 */
8300 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8301 NETIF_F_HW_VLAN_CTAG_RX |
8302 NETIF_F_HW_VLAN_CTAG_FILTER);
8303 netdev->priv_flags |= IFF_UNICAST_FLT;
8304 netdev->priv_flags |= IFF_SUPP_NOFCS;
8305 /* Setup netdev TC information */
8306 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8307
8308 netdev->netdev_ops = &i40e_netdev_ops;
8309 netdev->watchdog_timeo = 5 * HZ;
8310 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8311#ifdef I40E_FCOE
8312 i40e_fcoe_config_netdev(netdev, vsi);
8313#endif
41c445ff
JB		 8314
8315 return 0;
8316}
8317
8318/**
8319 * i40e_vsi_delete - Delete a VSI from the switch
8320 * @vsi: the VSI being removed
8321 *
8322 * Returns 0 on success, negative value on failure
8323 **/
8324static void i40e_vsi_delete(struct i40e_vsi *vsi)
8325{
8326 /* remove default VSI is not allowed */
8327 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8328 return;
8329
41c445ff 8330 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8331}
8332
51616018
NP		 8333/**
8334 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8335 * @vsi: the VSI being queried
8336 *
8337 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8338 **/
8339int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8340{
8341 struct i40e_veb *veb;
8342 struct i40e_pf *pf = vsi->back;
8343
8344 /* Uplink is not a bridge so default to VEB */
8345 if (vsi->veb_idx == I40E_NO_VEB)
8346 return 1;
8347
8348 veb = pf->veb[vsi->veb_idx];
8349 /* Uplink is a bridge in VEPA mode */
8350 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8351 return 0;
8352
8353 /* Uplink is a bridge in VEB mode */
8354 return 1;
8355}
8356
41c445ff
JB		 8357/**
8358 * i40e_add_vsi - Add a VSI to the switch
8359 * @vsi: the VSI being configured
8360 *
8361 * This initializes a VSI context depending on the VSI type to be added and
8362 * passes it down to the add_vsi aq command.
8363 **/
8364static int i40e_add_vsi(struct i40e_vsi *vsi)
8365{
8366 int ret = -ENODEV;
8367 struct i40e_mac_filter *f, *ftmp;
8368 struct i40e_pf *pf = vsi->back;
8369 struct i40e_hw *hw = &pf->hw;
8370 struct i40e_vsi_context ctxt;
8371 u8 enabled_tc = 0x1; /* TC0 enabled */
8372 int f_count = 0;
8373
8374 memset(&ctxt, 0, sizeof(ctxt));
8375 switch (vsi->type) {
8376 case I40E_VSI_MAIN:
8377 /* The PF's main VSI is already setup as part of the
8378 * device initialization, so we'll not bother with
8379 * the add_vsi call, but we will retrieve the current
8380 * VSI context.
8381 */
8382 ctxt.seid = pf->main_vsi_seid;
8383 ctxt.pf_num = pf->hw.pf_id;
8384 ctxt.vf_num = 0;
8385 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8386 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8387 if (ret) {
8388 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8389 "couldn't get PF vsi config, err %s aq_err %s\n",
8390 i40e_stat_str(&pf->hw, ret),
8391 i40e_aq_str(&pf->hw,
8392 pf->hw.aq.asq_last_status));
41c445ff
JB		 8393 return -ENOENT;
8394 }
1a2f6248 8395 vsi->info = ctxt.info;
41c445ff
JB		 8396 vsi->info.valid_sections = 0;
8397
8398 vsi->seid = ctxt.seid;
8399 vsi->id = ctxt.vsi_number;
8400
8401 enabled_tc = i40e_pf_get_tc_map(pf);
8402
8403 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8404 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8405 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8406 memset(&ctxt, 0, sizeof(ctxt));
8407 ctxt.seid = pf->main_vsi_seid;
8408 ctxt.pf_num = pf->hw.pf_id;
8409 ctxt.vf_num = 0;
8410 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8411 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8412 if (ret) {
8413 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8414 "update vsi failed, err %s aq_err %s\n",
8415 i40e_stat_str(&pf->hw, ret),
8416 i40e_aq_str(&pf->hw,
8417 pf->hw.aq.asq_last_status));
41c445ff
JB		 8418 ret = -ENOENT;
8419 goto err;
8420 }
8421 /* update the local VSI info queue map */
8422 i40e_vsi_update_queue_map(vsi, &ctxt);
8423 vsi->info.valid_sections = 0;
8424 } else {
8425 /* Default/Main VSI is only enabled for TC0
8426 * reconfigure it to enable all TCs that are
8427 * available on the port in SFP mode.
63d7e5a4
NP		 8428 * For MFP case the iSCSI PF would use this
8429 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8430 */
8431 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8432 if (ret) {
8433 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8434 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
8435 enabled_tc,
8436 i40e_stat_str(&pf->hw, ret),
8437 i40e_aq_str(&pf->hw,
8438 pf->hw.aq.asq_last_status));
41c445ff
JB		 8439 ret = -ENOENT;
8440 }
8441 }
8442 break;
8443
8444 case I40E_VSI_FDIR:
cbf61325
ASJ		 8445 ctxt.pf_num = hw->pf_id;
8446 ctxt.vf_num = 0;
8447 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8448 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8449 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 8450 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
8451 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 8452 ctxt.info.valid_sections |=
fc60861e 8453 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8454 ctxt.info.switch_id =
fc60861e 8455 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8456 }
41c445ff 8457 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8458 break;
8459
8460 case I40E_VSI_VMDQ2:
8461 ctxt.pf_num = hw->pf_id;
8462 ctxt.vf_num = 0;
8463 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8464 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8465 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8466
41c445ff
JB		 8467 /* This VSI is connected to VEB so the switch_id
8468 * should be set to zero by default.
8469 */
51616018
NP		 8470 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8471 ctxt.info.valid_sections |=
8472 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8473 ctxt.info.switch_id =
8474 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8475 }
41c445ff
JB		 8476
8477 /* Setup the VSI tx/rx queue map for TC0 only for now */
8478 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8479 break;
8480
8481 case I40E_VSI_SRIOV:
8482 ctxt.pf_num = hw->pf_id;
8483 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8484 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8485 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8486 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8487
41c445ff
JB		 8488 /* This VSI is connected to VEB so the switch_id
8489 * should be set to zero by default.
8490 */
51616018
NP		 8491 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8492 ctxt.info.valid_sections |=
8493 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8494 ctxt.info.switch_id =
8495 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8496 }
41c445ff
JB		 8497
8498 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8499 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8500 if (pf->vf[vsi->vf_id].spoofchk) {
8501 ctxt.info.valid_sections |=
8502 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8503 ctxt.info.sec_flags |=
8504 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8505 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8506 }
41c445ff
JB		 8507 /* Setup the VSI tx/rx queue map for TC0 only for now */
8508 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8509 break;
8510
38e00438
VD		 8511#ifdef I40E_FCOE
8512 case I40E_VSI_FCOE:
8513 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8514 if (ret) {
8515 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8516 return ret;
8517 }
8518 break;
8519
8520#endif /* I40E_FCOE */
41c445ff
JB		 8521 default:
8522 return -ENODEV;
8523 }
8524
8525 if (vsi->type != I40E_VSI_MAIN) {
8526 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8527 if (ret) {
8528 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 8529 "add vsi failed, err %s aq_err %s\n",
8530 i40e_stat_str(&pf->hw, ret),
8531 i40e_aq_str(&pf->hw,
8532 pf->hw.aq.asq_last_status));
41c445ff
JB		 8533 ret = -ENOENT;
8534 goto err;
8535 }
1a2f6248 8536 vsi->info = ctxt.info;
41c445ff
JB		 8537 vsi->info.valid_sections = 0;
8538 vsi->seid = ctxt.seid;
8539 vsi->id = ctxt.vsi_number;
8540 }
8541
8542 /* If macvlan filters already exist, force them to get loaded */
8543 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8544 f->changed = true;
8545 f_count++;
6252c7e4
SN		 8546
8547 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8548 struct i40e_aqc_remove_macvlan_element_data element;
8549
8550 memset(&element, 0, sizeof(element));
8551 ether_addr_copy(element.mac_addr, f->macaddr);
8552 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8553 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8554 &element, 1, NULL);
8555 if (ret) {
8556 /* some older FW has a different default */
8557 element.flags |=
8558 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8559 i40e_aq_remove_macvlan(hw, vsi->seid,
8560 &element, 1, NULL);
8561 }
8562
8563 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8564 I40E_AQC_WRITE_TYPE_LAA_WOL,
8565 f->macaddr, NULL);
8566 }
41c445ff
JB		 8567 }
8568 if (f_count) {
8569 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8570 pf->flags |= I40E_FLAG_FILTER_SYNC;
8571 }
8572
8573 /* Update VSI BW information */
8574 ret = i40e_vsi_get_bw_info(vsi);
8575 if (ret) {
8576 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8577 "couldn't get vsi bw info, err %s aq_err %s\n",
8578 i40e_stat_str(&pf->hw, ret),
8579 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 8580 /* VSI is already added so not tearing that up */
8581 ret = 0;
8582 }
8583
8584err:
8585 return ret;
8586}
8587
8588/**
8589 * i40e_vsi_release - Delete a VSI and free its resources
8590 * @vsi: the VSI being removed
8591 *
8592 * Returns 0 on success or < 0 on error
8593 **/
8594int i40e_vsi_release(struct i40e_vsi *vsi)
8595{
8596 struct i40e_mac_filter *f, *ftmp;
8597 struct i40e_veb *veb = NULL;
8598 struct i40e_pf *pf;
8599 u16 uplink_seid;
8600 int i, n;
8601
8602 pf = vsi->back;
8603
8604 /* release of a VEB-owner or last VSI is not allowed */
8605 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8606 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8607 vsi->seid, vsi->uplink_seid);
8608 return -ENODEV;
8609 }
8610 if (vsi == pf->vsi[pf->lan_vsi] &&
8611 !test_bit(__I40E_DOWN, &pf->state)) {
8612 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8613 return -ENODEV;
8614 }
8615
8616 uplink_seid = vsi->uplink_seid;
8617 if (vsi->type != I40E_VSI_SRIOV) {
8618 if (vsi->netdev_registered) {
8619 vsi->netdev_registered = false;
8620 if (vsi->netdev) {
8621 /* results in a call to i40e_close() */
8622 unregister_netdev(vsi->netdev);
41c445ff
JB		 8623 }
8624 } else {
90ef8d47 8625 i40e_vsi_close(vsi);
41c445ff
JB		 8626 }
8627 i40e_vsi_disable_irq(vsi);
8628 }
8629
8630 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8631 i40e_del_filter(vsi, f->macaddr, f->vlan,
8632 f->is_vf, f->is_netdev);
8633 i40e_sync_vsi_filters(vsi);
8634
8635 i40e_vsi_delete(vsi);
8636 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8637 if (vsi->netdev) {
8638 free_netdev(vsi->netdev);
8639 vsi->netdev = NULL;
8640 }
41c445ff
JB		 8641 i40e_vsi_clear_rings(vsi);
8642 i40e_vsi_clear(vsi);
8643
8644 /* If this was the last thing on the VEB, except for the
8645 * controlling VSI, remove the VEB, which puts the controlling
8646 * VSI onto the next level down in the switch.
8647 *
8648 * Well, okay, there's one more exception here: don't remove
8649 * the orphan VEBs yet. We'll wait for an explicit remove request
8650 * from up the network stack.
8651 */
505682cd 8652 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8653 if (pf->vsi[i] &&
8654 pf->vsi[i]->uplink_seid == uplink_seid &&
8655 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8656 n++; /* count the VSIs */
8657 }
8658 }
8659 for (i = 0; i < I40E_MAX_VEB; i++) {
8660 if (!pf->veb[i])
8661 continue;
8662 if (pf->veb[i]->uplink_seid == uplink_seid)
8663 n++; /* count the VEBs */
8664 if (pf->veb[i]->seid == uplink_seid)
8665 veb = pf->veb[i];
8666 }
8667 if (n == 0 && veb && veb->uplink_seid != 0)
8668 i40e_veb_release(veb);
8669
8670 return 0;
8671}
8672
8673/**
8674 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8675 * @vsi: ptr to the VSI
8676 *
8677 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8678 * corresponding SW VSI structure and initializes num_queue_pairs for the
8679 * newly allocated VSI.
8680 *
8681 * Returns 0 on success or negative on failure
8682 **/
8683static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8684{
8685 int ret = -ENOENT;
8686 struct i40e_pf *pf = vsi->back;
8687
493fb300 8688 if (vsi->q_vectors[0]) {
41c445ff
JB		 8689 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8690 vsi->seid);
8691 return -EEXIST;
8692 }
8693
8694 if (vsi->base_vector) {
f29eaa3d 8695 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8696 vsi->seid, vsi->base_vector);
8697 return -EEXIST;
8698 }
8699
90e04070 8700 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8701 if (ret) {
8702 dev_info(&pf->pdev->dev,
8703 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8704 vsi->num_q_vectors, vsi->seid, ret);
8705 vsi->num_q_vectors = 0;
8706 goto vector_setup_out;
8707 }
8708
958a3e3b
SN		 8709 if (vsi->num_q_vectors)
8710 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8711 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8712 if (vsi->base_vector < 0) {
8713 dev_info(&pf->pdev->dev,
049a2be8
SN		 8714 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8715 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8716 i40e_vsi_free_q_vectors(vsi);
8717 ret = -ENOENT;
8718 goto vector_setup_out;
8719 }
8720
8721vector_setup_out:
8722 return ret;
8723}
8724
bc7d338f
ASJ		 8725/**
8726 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8727 * @vsi: pointer to the vsi.
8728 *
8729 * This re-allocates a vsi's queue resources.
8730 *
8731 * Returns pointer to the successfully allocated and configured VSI sw struct
8732 * on success, otherwise returns NULL on failure.
8733 **/
8734static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8735{
8736 struct i40e_pf *pf = vsi->back;
8737 u8 enabled_tc;
8738 int ret;
8739
8740 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8741 i40e_vsi_clear_rings(vsi);
8742
8743 i40e_vsi_free_arrays(vsi, false);
8744 i40e_set_num_rings_in_vsi(vsi);
8745 ret = i40e_vsi_alloc_arrays(vsi, false);
8746 if (ret)
8747 goto err_vsi;
8748
8749 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8750 if (ret < 0) {
049a2be8 8751 dev_info(&pf->pdev->dev,
f1c7e72e 8752 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 8753 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8754 goto err_vsi;
8755 }
8756 vsi->base_queue = ret;
8757
8758 /* Update the FW view of the VSI. Force a reset of TC and queue
8759 * layout configurations.
8760 */
8761 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8762 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8763 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8764 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8765
8766 /* assign it some queues */
8767 ret = i40e_alloc_rings(vsi);
8768 if (ret)
8769 goto err_rings;
8770
8771 /* map all of the rings to the q_vectors */
8772 i40e_vsi_map_rings_to_vectors(vsi);
8773 return vsi;
8774
8775err_rings:
8776 i40e_vsi_free_q_vectors(vsi);
8777 if (vsi->netdev_registered) {
8778 vsi->netdev_registered = false;
8779 unregister_netdev(vsi->netdev);
8780 free_netdev(vsi->netdev);
8781 vsi->netdev = NULL;
8782 }
8783 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8784err_vsi:
8785 i40e_vsi_clear(vsi);
8786 return NULL;
8787}
8788
41c445ff
JB		 8789/**
8790 * i40e_vsi_setup - Set up a VSI by a given type
8791 * @pf: board private structure
8792 * @type: VSI type
8793 * @uplink_seid: the switch element to link to
8794 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8795 *
8796 * This allocates the sw VSI structure and its queue resources, then add a VSI
8797 * to the identified VEB.
8798 *
8799 * Returns pointer to the successfully allocated and configure VSI sw struct on
8800 * success, otherwise returns NULL on failure.
8801 **/
8802struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8803 u16 uplink_seid, u32 param1)
8804{
8805 struct i40e_vsi *vsi = NULL;
8806 struct i40e_veb *veb = NULL;
8807 int ret, i;
8808 int v_idx;
8809
8810 /* The requested uplink_seid must be either
8811 * - the PF's port seid
8812 * no VEB is needed because this is the PF
8813 * or this is a Flow Director special case VSI
8814 * - seid of an existing VEB
8815 * - seid of a VSI that owns an existing VEB
8816 * - seid of a VSI that doesn't own a VEB
8817 * a new VEB is created and the VSI becomes the owner
8818 * - seid of the PF VSI, which is what creates the first VEB
8819 * this is a special case of the previous
8820 *
8821 * Find which uplink_seid we were given and create a new VEB if needed
8822 */
8823 for (i = 0; i < I40E_MAX_VEB; i++) {
8824 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8825 veb = pf->veb[i];
8826 break;
8827 }
8828 }
8829
8830 if (!veb && uplink_seid != pf->mac_seid) {
8831
505682cd 8832 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8833 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8834 vsi = pf->vsi[i];
8835 break;
8836 }
8837 }
8838 if (!vsi) {
8839 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8840 uplink_seid);
8841 return NULL;
8842 }
8843
8844 if (vsi->uplink_seid == pf->mac_seid)
8845 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8846 vsi->tc_config.enabled_tc);
8847 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8848 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8849 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 8850 if (veb) {
8851 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
8852 dev_info(&vsi->back->pdev->dev,
8853 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
8854 __func__);
8855 return NULL;
8856 }
fa11cb3d
ASJ		 8857 /* We come up by default in VEPA mode if SRIOV is not
8858 * already enabled, in which case we can't force VEPA
8859 * mode.
8860 */
8861 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
8862 veb->bridge_mode = BRIDGE_MODE_VEPA;
8863 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8864 }
51616018 8865 i40e_config_bridge_mode(veb);
79c21a82 8866 }
41c445ff
JB		 8867 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8868 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8869 veb = pf->veb[i];
8870 }
8871 if (!veb) {
8872 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8873 return NULL;
8874 }
8875
8876 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8877 uplink_seid = veb->seid;
8878 }
8879
8880 /* get vsi sw struct */
8881 v_idx = i40e_vsi_mem_alloc(pf, type);
8882 if (v_idx < 0)
8883 goto err_alloc;
8884 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8885 if (!vsi)
8886 goto err_alloc;
41c445ff
JB		 8887 vsi->type = type;
8888 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8889
8890 if (type == I40E_VSI_MAIN)
8891 pf->lan_vsi = v_idx;
8892 else if (type == I40E_VSI_SRIOV)
8893 vsi->vf_id = param1;
8894 /* assign it some queues */
cbf61325
ASJ		 8895 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8896 vsi->idx);
41c445ff 8897 if (ret < 0) {
049a2be8
SN		 8898 dev_info(&pf->pdev->dev,
8899 "failed to get tracking for %d queues for VSI %d err=%d\n",
8900 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8901 goto err_vsi;
8902 }
8903 vsi->base_queue = ret;
8904
8905 /* get a VSI from the hardware */
8906 vsi->uplink_seid = uplink_seid;
8907 ret = i40e_add_vsi(vsi);
8908 if (ret)
8909 goto err_vsi;
8910
8911 switch (vsi->type) {
8912 /* setup the netdev if needed */
8913 case I40E_VSI_MAIN:
8914 case I40E_VSI_VMDQ2:
38e00438 8915 case I40E_VSI_FCOE:
41c445ff
JB		 8916 ret = i40e_config_netdev(vsi);
8917 if (ret)
8918 goto err_netdev;
8919 ret = register_netdev(vsi->netdev);
8920 if (ret)
8921 goto err_netdev;
8922 vsi->netdev_registered = true;
8923 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8924#ifdef CONFIG_I40E_DCB
8925 /* Setup DCB netlink interface */
8926 i40e_dcbnl_setup(vsi);
8927#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8928 /* fall through */
8929
8930 case I40E_VSI_FDIR:
8931 /* set up vectors and rings if needed */
8932 ret = i40e_vsi_setup_vectors(vsi);
8933 if (ret)
8934 goto err_msix;
8935
8936 ret = i40e_alloc_rings(vsi);
8937 if (ret)
8938 goto err_rings;
8939
8940 /* map all of the rings to the q_vectors */
8941 i40e_vsi_map_rings_to_vectors(vsi);
8942
8943 i40e_vsi_reset_stats(vsi);
8944 break;
8945
8946 default:
8947 /* no netdev or rings for the other VSI types */
8948 break;
8949 }
8950
8951 return vsi;
8952
8953err_rings:
8954 i40e_vsi_free_q_vectors(vsi);
8955err_msix:
8956 if (vsi->netdev_registered) {
8957 vsi->netdev_registered = false;
8958 unregister_netdev(vsi->netdev);
8959 free_netdev(vsi->netdev);
8960 vsi->netdev = NULL;
8961 }
8962err_netdev:
8963 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8964err_vsi:
8965 i40e_vsi_clear(vsi);
8966err_alloc:
8967 return NULL;
8968}
8969
8970/**
8971 * i40e_veb_get_bw_info - Query VEB BW information
8972 * @veb: the veb to query
8973 *
8974 * Query the Tx scheduler BW configuration data for given VEB
8975 **/
8976static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8977{
8978 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8979 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8980 struct i40e_pf *pf = veb->pf;
8981 struct i40e_hw *hw = &pf->hw;
8982 u32 tc_bw_max;
8983 int ret = 0;
8984 int i;
8985
8986 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8987 &bw_data, NULL);
8988 if (ret) {
8989 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8990 "query veb bw config failed, err %s aq_err %s\n",
8991 i40e_stat_str(&pf->hw, ret),
8992 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 8993 goto out;
8994 }
8995
8996 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8997 &ets_data, NULL);
8998 if (ret) {
8999 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9000 "query veb bw ets config failed, err %s aq_err %s\n",
9001 i40e_stat_str(&pf->hw, ret),
9002 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9003 goto out;
9004 }
9005
9006 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9007 veb->bw_max_quanta = ets_data.tc_bw_max;
9008 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9009 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9010 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9011 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9012 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9013 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9014 veb->bw_tc_limit_credits[i] =
9015 le16_to_cpu(bw_data.tc_bw_limits[i]);
9016 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9017 }
9018
9019out:
9020 return ret;
9021}
9022
9023/**
9024 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9025 * @pf: board private structure
9026 *
9027 * On error: returns error code (negative)
9028 * On success: returns vsi index in PF (positive)
9029 **/
9030static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9031{
9032 int ret = -ENOENT;
9033 struct i40e_veb *veb;
9034 int i;
9035
9036 /* Need to protect the allocation of switch elements at the PF level */
9037 mutex_lock(&pf->switch_mutex);
9038
9039 /* VEB list may be fragmented if VEB creation/destruction has
9040 * been happening. We can afford to do a quick scan to look
9041 * for any free slots in the list.
9042 *
9043 * find next empty veb slot, looping back around if necessary
9044 */
9045 i = 0;
9046 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9047 i++;
9048 if (i >= I40E_MAX_VEB) {
9049 ret = -ENOMEM;
9050 goto err_alloc_veb; /* out of VEB slots! */
9051 }
9052
9053 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9054 if (!veb) {
9055 ret = -ENOMEM;
9056 goto err_alloc_veb;
9057 }
9058 veb->pf = pf;
9059 veb->idx = i;
9060 veb->enabled_tc = 1;
9061
9062 pf->veb[i] = veb;
9063 ret = i;
9064err_alloc_veb:
9065 mutex_unlock(&pf->switch_mutex);
9066 return ret;
9067}
9068
9069/**
9070 * i40e_switch_branch_release - Delete a branch of the switch tree
9071 * @branch: where to start deleting
9072 *
9073 * This uses recursion to find the tips of the branch to be
9074 * removed, deleting until we get back to and can delete this VEB.
9075 **/
9076static void i40e_switch_branch_release(struct i40e_veb *branch)
9077{
9078 struct i40e_pf *pf = branch->pf;
9079 u16 branch_seid = branch->seid;
9080 u16 veb_idx = branch->idx;
9081 int i;
9082
9083 /* release any VEBs on this VEB - RECURSION */
9084 for (i = 0; i < I40E_MAX_VEB; i++) {
9085 if (!pf->veb[i])
9086 continue;
9087 if (pf->veb[i]->uplink_seid == branch->seid)
9088 i40e_switch_branch_release(pf->veb[i]);
9089 }
9090
9091 /* Release the VSIs on this VEB, but not the owner VSI.
9092 *
9093 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9094 * the VEB itself, so don't use (*branch) after this loop.
9095 */
505682cd 9096 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9097 if (!pf->vsi[i])
9098 continue;
9099 if (pf->vsi[i]->uplink_seid == branch_seid &&
9100 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9101 i40e_vsi_release(pf->vsi[i]);
9102 }
9103 }
9104
9105 /* There's one corner case where the VEB might not have been
9106 * removed, so double check it here and remove it if needed.
9107 * This case happens if the veb was created from the debugfs
9108 * commands and no VSIs were added to it.
9109 */
9110 if (pf->veb[veb_idx])
9111 i40e_veb_release(pf->veb[veb_idx]);
9112}
9113
9114/**
9115 * i40e_veb_clear - remove veb struct
9116 * @veb: the veb to remove
9117 **/
9118static void i40e_veb_clear(struct i40e_veb *veb)
9119{
9120 if (!veb)
9121 return;
9122
9123 if (veb->pf) {
9124 struct i40e_pf *pf = veb->pf;
9125
9126 mutex_lock(&pf->switch_mutex);
9127 if (pf->veb[veb->idx] == veb)
9128 pf->veb[veb->idx] = NULL;
9129 mutex_unlock(&pf->switch_mutex);
9130 }
9131
9132 kfree(veb);
9133}
9134
9135/**
9136 * i40e_veb_release - Delete a VEB and free its resources
9137 * @veb: the VEB being removed
9138 **/
9139void i40e_veb_release(struct i40e_veb *veb)
9140{
9141 struct i40e_vsi *vsi = NULL;
9142 struct i40e_pf *pf;
9143 int i, n = 0;
9144
9145 pf = veb->pf;
9146
9147 /* find the remaining VSI and check for extras */
505682cd 9148 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9149 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9150 n++;
9151 vsi = pf->vsi[i];
9152 }
9153 }
9154 if (n != 1) {
9155 dev_info(&pf->pdev->dev,
9156 "can't remove VEB %d with %d VSIs left\n",
9157 veb->seid, n);
9158 return;
9159 }
9160
9161 /* move the remaining VSI to uplink veb */
9162 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9163 if (veb->uplink_seid) {
9164 vsi->uplink_seid = veb->uplink_seid;
9165 if (veb->uplink_seid == pf->mac_seid)
9166 vsi->veb_idx = I40E_NO_VEB;
9167 else
9168 vsi->veb_idx = veb->veb_idx;
9169 } else {
9170 /* floating VEB */
9171 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9172 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9173 }
9174
9175 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9176 i40e_veb_clear(veb);
41c445ff
JB		 9177}
9178
9179/**
9180 * i40e_add_veb - create the VEB in the switch
9181 * @veb: the VEB to be instantiated
9182 * @vsi: the controlling VSI
9183 **/
9184static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9185{
f1c7e72e 9186 struct i40e_pf *pf = veb->pf;
56747264 9187 bool is_default = false;
e1c51b95 9188 bool is_cloud = false;
41c445ff
JB		 9189 int ret;
9190
9191 /* get a VEB from the hardware */
f1c7e72e 9192 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9193 veb->enabled_tc, is_default,
9194 is_cloud, &veb->seid, NULL);
41c445ff 9195 if (ret) {
f1c7e72e
SN		 9196 dev_info(&pf->pdev->dev,
9197 "couldn't add VEB, err %s aq_err %s\n",
9198 i40e_stat_str(&pf->hw, ret),
9199 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9200 return -EPERM;
9201 }
9202
9203 /* get statistics counter */
f1c7e72e 9204 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9205 &veb->stats_idx, NULL, NULL, NULL);
9206 if (ret) {
f1c7e72e
SN		 9207 dev_info(&pf->pdev->dev,
9208 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9209 i40e_stat_str(&pf->hw, ret),
9210 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9211 return -EPERM;
9212 }
9213 ret = i40e_veb_get_bw_info(veb);
9214 if (ret) {
f1c7e72e
SN		 9215 dev_info(&pf->pdev->dev,
9216 "couldn't get VEB bw info, err %s aq_err %s\n",
9217 i40e_stat_str(&pf->hw, ret),
9218 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9219 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9220 return -ENOENT;
9221 }
9222
9223 vsi->uplink_seid = veb->seid;
9224 vsi->veb_idx = veb->idx;
9225 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9226
9227 return 0;
9228}
9229
9230/**
9231 * i40e_veb_setup - Set up a VEB
9232 * @pf: board private structure
9233 * @flags: VEB setup flags
9234 * @uplink_seid: the switch element to link to
9235 * @vsi_seid: the initial VSI seid
9236 * @enabled_tc: Enabled TC bit-map
9237 *
9238 * This allocates the sw VEB structure and links it into the switch
9239 * It is possible and legal for this to be a duplicate of an already
9240 * existing VEB. It is also possible for both uplink and vsi seids
9241 * to be zero, in order to create a floating VEB.
9242 *
9243 * Returns pointer to the successfully allocated VEB sw struct on
9244 * success, otherwise returns NULL on failure.
9245 **/
9246struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9247 u16 uplink_seid, u16 vsi_seid,
9248 u8 enabled_tc)
9249{
9250 struct i40e_veb *veb, *uplink_veb = NULL;
9251 int vsi_idx, veb_idx;
9252 int ret;
9253
9254 /* if one seid is 0, the other must be 0 to create a floating relay */
9255 if ((uplink_seid == 0 || vsi_seid == 0) &&
9256 (uplink_seid + vsi_seid != 0)) {
9257 dev_info(&pf->pdev->dev,
9258 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9259 uplink_seid, vsi_seid);
9260 return NULL;
9261 }
9262
9263 /* make sure there is such a vsi and uplink */
505682cd 9264 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9265 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9266 break;
505682cd 9267 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9268 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9269 vsi_seid);
9270 return NULL;
9271 }
9272
9273 if (uplink_seid && uplink_seid != pf->mac_seid) {
9274 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9275 if (pf->veb[veb_idx] &&
9276 pf->veb[veb_idx]->seid == uplink_seid) {
9277 uplink_veb = pf->veb[veb_idx];
9278 break;
9279 }
9280 }
9281 if (!uplink_veb) {
9282 dev_info(&pf->pdev->dev,
9283 "uplink seid %d not found\n", uplink_seid);
9284 return NULL;
9285 }
9286 }
9287
9288 /* get veb sw struct */
9289 veb_idx = i40e_veb_mem_alloc(pf);
9290 if (veb_idx < 0)
9291 goto err_alloc;
9292 veb = pf->veb[veb_idx];
9293 veb->flags = flags;
9294 veb->uplink_seid = uplink_seid;
9295 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9296 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9297
9298 /* create the VEB in the switch */
9299 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9300 if (ret)
9301 goto err_veb;
1bb8b935
SN		 9302 if (vsi_idx == pf->lan_vsi)
9303 pf->lan_veb = veb->idx;
41c445ff
JB		 9304
9305 return veb;
9306
9307err_veb:
9308 i40e_veb_clear(veb);
9309err_alloc:
9310 return NULL;
9311}
9312
9313/**
b40c82e6 9314 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9315 * @pf: board private structure
9316 * @ele: element we are building info from
9317 * @num_reported: total number of elements
9318 * @printconfig: should we print the contents
9319 *
9320 * helper function to assist in extracting a few useful SEID values.
9321 **/
9322static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9323 struct i40e_aqc_switch_config_element_resp *ele,
9324 u16 num_reported, bool printconfig)
9325{
9326 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9327 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9328 u8 element_type = ele->element_type;
9329 u16 seid = le16_to_cpu(ele->seid);
9330
9331 if (printconfig)
9332 dev_info(&pf->pdev->dev,
9333 "type=%d seid=%d uplink=%d downlink=%d\n",
9334 element_type, seid, uplink_seid, downlink_seid);
9335
9336 switch (element_type) {
9337 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9338 pf->mac_seid = seid;
9339 break;
9340 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9341 /* Main VEB? */
9342 if (uplink_seid != pf->mac_seid)
9343 break;
9344 if (pf->lan_veb == I40E_NO_VEB) {
9345 int v;
9346
9347 /* find existing or else empty VEB */
9348 for (v = 0; v < I40E_MAX_VEB; v++) {
9349 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9350 pf->lan_veb = v;
9351 break;
9352 }
9353 }
9354 if (pf->lan_veb == I40E_NO_VEB) {
9355 v = i40e_veb_mem_alloc(pf);
9356 if (v < 0)
9357 break;
9358 pf->lan_veb = v;
9359 }
9360 }
9361
9362 pf->veb[pf->lan_veb]->seid = seid;
9363 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9364 pf->veb[pf->lan_veb]->pf = pf;
9365 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9366 break;
9367 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9368 if (num_reported != 1)
9369 break;
9370 /* This is immediately after a reset so we can assume this is
9371 * the PF's VSI
9372 */
9373 pf->mac_seid = uplink_seid;
9374 pf->pf_seid = downlink_seid;
9375 pf->main_vsi_seid = seid;
9376 if (printconfig)
9377 dev_info(&pf->pdev->dev,
9378 "pf_seid=%d main_vsi_seid=%d\n",
9379 pf->pf_seid, pf->main_vsi_seid);
9380 break;
9381 case I40E_SWITCH_ELEMENT_TYPE_PF:
9382 case I40E_SWITCH_ELEMENT_TYPE_VF:
9383 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9384 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9385 case I40E_SWITCH_ELEMENT_TYPE_PE:
9386 case I40E_SWITCH_ELEMENT_TYPE_PA:
9387 /* ignore these for now */
9388 break;
9389 default:
9390 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9391 element_type, seid);
9392 break;
9393 }
9394}
9395
9396/**
9397 * i40e_fetch_switch_configuration - Get switch config from firmware
9398 * @pf: board private structure
9399 * @printconfig: should we print the contents
9400 *
9401 * Get the current switch configuration from the device and
9402 * extract a few useful SEID values.
9403 **/
9404int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9405{
9406 struct i40e_aqc_get_switch_config_resp *sw_config;
9407 u16 next_seid = 0;
9408 int ret = 0;
9409 u8 *aq_buf;
9410 int i;
9411
9412 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9413 if (!aq_buf)
9414 return -ENOMEM;
9415
9416 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9417 do {
9418 u16 num_reported, num_total;
9419
9420 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9421 I40E_AQ_LARGE_BUF,
9422 &next_seid, NULL);
9423 if (ret) {
9424 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9425 "get switch config failed err %s aq_err %s\n",
9426 i40e_stat_str(&pf->hw, ret),
9427 i40e_aq_str(&pf->hw,
9428 pf->hw.aq.asq_last_status));
41c445ff
JB		 9429 kfree(aq_buf);
9430 return -ENOENT;
9431 }
9432
9433 num_reported = le16_to_cpu(sw_config->header.num_reported);
9434 num_total = le16_to_cpu(sw_config->header.num_total);
9435
9436 if (printconfig)
9437 dev_info(&pf->pdev->dev,
9438 "header: %d reported %d total\n",
9439 num_reported, num_total);
9440
41c445ff
JB		 9441 for (i = 0; i < num_reported; i++) {
9442 struct i40e_aqc_switch_config_element_resp *ele =
9443 &sw_config->element[i];
9444
9445 i40e_setup_pf_switch_element(pf, ele, num_reported,
9446 printconfig);
9447 }
9448 } while (next_seid != 0);
9449
9450 kfree(aq_buf);
9451 return ret;
9452}
9453
9454/**
9455 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9456 * @pf: board private structure
bc7d338f 9457 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9458 *
9459 * Returns 0 on success, negative value on failure
9460 **/
bc7d338f 9461static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9462{
9463 int ret;
9464
9465 /* find out what's out there already */
9466 ret = i40e_fetch_switch_configuration(pf, false);
9467 if (ret) {
9468 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9469 "couldn't fetch switch config, err %s aq_err %s\n",
9470 i40e_stat_str(&pf->hw, ret),
9471 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9472 return ret;
9473 }
9474 i40e_pf_reset_stats(pf);
9475
41c445ff 9476 /* first time setup */
bc7d338f 9477 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9478 struct i40e_vsi *vsi = NULL;
9479 u16 uplink_seid;
9480
9481 /* Set up the PF VSI associated with the PF's main VSI
9482 * that is already in the HW switch
9483 */
9484 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9485 uplink_seid = pf->veb[pf->lan_veb]->seid;
9486 else
9487 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9488 if (pf->lan_vsi == I40E_NO_VSI)
9489 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9490 else if (reinit)
9491 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9492 if (!vsi) {
9493 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9494 i40e_fdir_teardown(pf);
9495 return -EAGAIN;
9496 }
41c445ff
JB		 9497 } else {
9498 /* force a reset of TC and queue layout configurations */
9499 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9500 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9501 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9502 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9503 }
9504 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9505
cbf61325
ASJ		 9506 i40e_fdir_sb_setup(pf);
9507
41c445ff
JB		 9508 /* Setup static PF queue filter control settings */
9509 ret = i40e_setup_pf_filter_control(pf);
9510 if (ret) {
9511 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9512 ret);
9513 /* Failure here should not stop continuing other steps */
9514 }
9515
9516 /* enable RSS in the HW, even for only one queue, as the stack can use
9517 * the hash
9518 */
9519 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9520 i40e_config_rss(pf);
9521
9522 /* fill in link information and enable LSE reporting */
21af70fb 9523 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9524 i40e_link_event(pf);
9525
d52c20b7 9526 /* Initialize user-specific link properties */
41c445ff
JB		 9527 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9528 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9529
beb0dff1
JK		 9530 i40e_ptp_init(pf);
9531
41c445ff
JB		 9532 return ret;
9533}
9534
41c445ff
JB		 9535/**
9536 * i40e_determine_queue_usage - Work out queue distribution
9537 * @pf: board private structure
9538 **/
9539static void i40e_determine_queue_usage(struct i40e_pf *pf)
9540{
41c445ff
JB		 9541 int queues_left;
9542
9543 pf->num_lan_qps = 0;
38e00438
VD		 9544#ifdef I40E_FCOE
9545 pf->num_fcoe_qps = 0;
9546#endif
41c445ff
JB		 9547
9548 /* Find the max queues to be put into basic use. We'll always be
9549 * using TC0, whether or not DCB is running, and TC0 will get the
9550 * big RSS set.
9551 */
9552 queues_left = pf->hw.func_caps.num_tx_qp;
9553
cbf61325 9554 if ((queues_left == 1) ||
9aa7e935 9555 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9556 /* one qp for PF, no queues for anything else */
9557 queues_left = 0;
9558 pf->rss_size = pf->num_lan_qps = 1;
9559
9560 /* make sure all the fancies are disabled */
60ea5f83 9561 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9562#ifdef I40E_FCOE
9563 I40E_FLAG_FCOE_ENABLED |
9564#endif
60ea5f83
JB		 9565 I40E_FLAG_FD_SB_ENABLED |
9566 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9567 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9568 I40E_FLAG_SRIOV_ENABLED |
9569 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9570 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9571 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9572 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9573 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9574 /* one qp for PF */
9575 pf->rss_size = pf->num_lan_qps = 1;
9576 queues_left -= pf->num_lan_qps;
9577
9578 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9579#ifdef I40E_FCOE
9580 I40E_FLAG_FCOE_ENABLED |
9581#endif
9aa7e935
FZ		 9582 I40E_FLAG_FD_SB_ENABLED |
9583 I40E_FLAG_FD_ATR_ENABLED |
9584 I40E_FLAG_DCB_ENABLED |
9585 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9586 } else {
cbf61325 9587 /* Not enough queues for all TCs */
4d9b6043 9588 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9589 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9590 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9591 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9592 }
9a3bd2f1
ASJ		 9593 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9594 num_online_cpus());
9595 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9596 pf->hw.func_caps.num_tx_qp);
9597
cbf61325
ASJ		 9598 queues_left -= pf->num_lan_qps;
9599 }
9600
38e00438
VD		 9601#ifdef I40E_FCOE
9602 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9603 if (I40E_DEFAULT_FCOE <= queues_left) {
9604 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9605 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9606 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9607 } else {
9608 pf->num_fcoe_qps = 0;
9609 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9610 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9611 }
9612
9613 queues_left -= pf->num_fcoe_qps;
9614 }
9615
9616#endif
cbf61325
ASJ		 9617 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9618 if (queues_left > 1) {
9619 queues_left -= 1; /* save 1 queue for FD */
9620 } else {
9621 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9622 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9623 }
41c445ff
JB		 9624 }
9625
9626 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9627 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9628 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9629 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9630 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9631 }
9632
9633 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9634 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9635 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9636 (queues_left / pf->num_vmdq_qps));
9637 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9638 }
9639
f8ff1464 9640 pf->queues_left = queues_left;
38e00438
VD		 9641#ifdef I40E_FCOE
9642 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9643#endif
41c445ff
JB		 9644}
9645
9646/**
9647 * i40e_setup_pf_filter_control - Setup PF static filter control
9648 * @pf: PF to be setup
9649 *
b40c82e6 9650 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9651 * settings. If PE/FCoE are enabled then it will also set the per PF
9652 * based filter sizes required for them. It also enables Flow director,
9653 * ethertype and macvlan type filter settings for the pf.
9654 *
9655 * Returns 0 on success, negative on failure
9656 **/
9657static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9658{
9659 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9660
9661 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9662
9663 /* Flow Director is enabled */
60ea5f83 9664 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9665 settings->enable_fdir = true;
9666
9667 /* Ethtype and MACVLAN filters enabled for PF */
9668 settings->enable_ethtype = true;
9669 settings->enable_macvlan = true;
9670
9671 if (i40e_set_filter_control(&pf->hw, settings))
9672 return -ENOENT;
9673
9674 return 0;
9675}
9676
0c22b3dd
JB		 9677#define INFO_STRING_LEN 255
9678static void i40e_print_features(struct i40e_pf *pf)
9679{
9680 struct i40e_hw *hw = &pf->hw;
9681 char *buf, *string;
9682
9683 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9684 if (!string) {
9685 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9686 return;
9687 }
9688
9689 buf = string;
9690
9691 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9692#ifdef CONFIG_PCI_IOV
9693 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9694#endif
aba237d1
MW		 9695 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9696 pf->hw.func_caps.num_vsis,
9697 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9698 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9699
9700 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9701 buf += sprintf(buf, "RSS ");
0c22b3dd 9702 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9703 buf += sprintf(buf, "FD_ATR ");
9704 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9705 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9706 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9707 }
4d9b6043 9708 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9709 buf += sprintf(buf, "DCB ");
9710 if (pf->flags & I40E_FLAG_PTP)
9711 buf += sprintf(buf, "PTP ");
38e00438
VD		 9712#ifdef I40E_FCOE
9713 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9714 buf += sprintf(buf, "FCOE ");
9715#endif
0c22b3dd
JB		 9716
9717 BUG_ON(buf > (string + INFO_STRING_LEN));
9718 dev_info(&pf->pdev->dev, "%s\n", string);
9719 kfree(string);
9720}
9721
41c445ff
JB		 9722/**
9723 * i40e_probe - Device initialization routine
9724 * @pdev: PCI device information struct
9725 * @ent: entry in i40e_pci_tbl
9726 *
b40c82e6
JK		 9727 * i40e_probe initializes a PF identified by a pci_dev structure.
9728 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9729 * and a hardware reset occur.
9730 *
9731 * Returns 0 on success, negative on failure
9732 **/
9733static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9734{
e827845c 9735 struct i40e_aq_get_phy_abilities_resp abilities;
e815665e 9736 unsigned long ioremap_len;
41c445ff
JB		 9737 struct i40e_pf *pf;
9738 struct i40e_hw *hw;
93cd765b 9739 static u16 pfs_found;
d4dfb81a 9740 u16 link_status;
41c445ff
JB		 9741 int err = 0;
9742 u32 len;
8a9eb7d3 9743 u32 i;
41c445ff
JB		 9744
9745 err = pci_enable_device_mem(pdev);
9746 if (err)
9747 return err;
9748
9749 /* set up for high or low dma */
6494294f 9750 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9751 if (err) {
e3e3bfdd
JS		 9752 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9753 if (err) {
9754 dev_err(&pdev->dev,
9755 "DMA configuration failed: 0x%x\n", err);
9756 goto err_dma;
9757 }
41c445ff
JB		 9758 }
9759
9760 /* set up pci connections */
9761 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9762 IORESOURCE_MEM), i40e_driver_name);
9763 if (err) {
9764 dev_info(&pdev->dev,
9765 "pci_request_selected_regions failed %d\n", err);
9766 goto err_pci_reg;
9767 }
9768
9769 pci_enable_pcie_error_reporting(pdev);
9770 pci_set_master(pdev);
9771
9772 /* Now that we have a PCI connection, we need to do the
9773 * low level device setup. This is primarily setting up
9774 * the Admin Queue structures and then querying for the
9775 * device's current profile information.
9776 */
9777 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9778 if (!pf) {
9779 err = -ENOMEM;
9780 goto err_pf_alloc;
9781 }
9782 pf->next_vsi = 0;
9783 pf->pdev = pdev;
9784 set_bit(__I40E_DOWN, &pf->state);
9785
9786 hw = &pf->hw;
9787 hw->back = pf;
232f4706 9788
e815665e 9789 ioremap_len = min_t(unsigned long, pci_resource_len(pdev, 0),
232f4706
AS		 9790 I40E_MAX_CSR_SPACE);
9791
9792 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), ioremap_len);
41c445ff
JB		 9793 if (!hw->hw_addr) {
9794 err = -EIO;
9795 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9796 (unsigned int)pci_resource_start(pdev, 0),
9797 (unsigned int)pci_resource_len(pdev, 0), err);
9798 goto err_ioremap;
9799 }
9800 hw->vendor_id = pdev->vendor;
9801 hw->device_id = pdev->device;
9802 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9803 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9804 hw->subsystem_device_id = pdev->subsystem_device;
9805 hw->bus.device = PCI_SLOT(pdev->devfn);
9806 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9807 pf->instance = pfs_found;
41c445ff 9808
5b5faa43
SN		 9809 if (debug != -1) {
9810 pf->msg_enable = pf->hw.debug_mask;
9811 pf->msg_enable = debug;
9812 }
9813
7134f9ce
JB		 9814 /* do a special CORER for clearing PXE mode once at init */
9815 if (hw->revision_id == 0 &&
9816 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9817 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9818 i40e_flush(hw);
9819 msleep(200);
9820 pf->corer_count++;
9821
9822 i40e_clear_pxe_mode(hw);
9823 }
9824
41c445ff 9825 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9826 i40e_clear_hw(hw);
41c445ff
JB		 9827 err = i40e_pf_reset(hw);
9828 if (err) {
9829 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9830 goto err_pf_reset;
9831 }
9832 pf->pfr_count++;
9833
9834 hw->aq.num_arq_entries = I40E_AQ_LEN;
9835 hw->aq.num_asq_entries = I40E_AQ_LEN;
9836 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9837 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9838 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 9839
b294ac70 9840 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 9841 "%s-%s:misc",
9842 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 9843
9844 err = i40e_init_shared_code(hw);
9845 if (err) {
b2a75c58
ASJ		 9846 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
9847 err);
41c445ff
JB		 9848 goto err_pf_reset;
9849 }
9850
d52c20b7
JB		 9851 /* set up a default setting for link flow control */
9852 pf->hw.fc.requested_mode = I40E_FC_NONE;
9853
41c445ff
JB		 9854 err = i40e_init_adminq(hw);
9855 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9856 if (err) {
9857 dev_info(&pdev->dev,
7aa67613 9858 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9859 goto err_pf_reset;
9860 }
9861
7aa67613
CS		 9862 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9863 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9864 dev_info(&pdev->dev,
7aa67613
CS		 9865 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9866 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9867 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9868 dev_info(&pdev->dev,
7aa67613 9869 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 9870
4eb3f768
SN		 9871 i40e_verify_eeprom(pf);
9872
2c5fe33b
JB		 9873 /* Rev 0 hardware was never productized */
9874 if (hw->revision_id < 1)
9875 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9876
6ff4ef86 9877 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9878 err = i40e_get_capabilities(pf);
9879 if (err)
9880 goto err_adminq_setup;
9881
9882 err = i40e_sw_init(pf);
9883 if (err) {
9884 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9885 goto err_sw_init;
9886 }
9887
9888 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9889 hw->func_caps.num_rx_qp,
9890 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9891 if (err) {
9892 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9893 goto err_init_lan_hmc;
9894 }
9895
9896 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9897 if (err) {
9898 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9899 err = -ENOENT;
9900 goto err_configure_lan_hmc;
9901 }
9902
b686ece5
NP		 9903 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
9904 * Ignore error return codes because if it was already disabled via
9905 * hardware settings this will fail
9906 */
9907 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
9908 (pf->hw.aq.fw_maj_ver < 4)) {
9909 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
9910 i40e_aq_stop_lldp(hw, true, NULL);
9911 }
9912
41c445ff 9913 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9914 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9915 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9916 err = -EIO;
9917 goto err_mac_addr;
9918 }
9919 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9920 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9921 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9922 if (is_valid_ether_addr(hw->mac.port_addr))
9923 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9924#ifdef I40E_FCOE
9925 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9926 if (err)
9927 dev_info(&pdev->dev,
9928 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9929 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9930 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9931 hw->mac.san_addr);
9932 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9933 }
9934 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9935#endif /* I40E_FCOE */
41c445ff
JB		 9936
9937 pci_set_drvdata(pdev, pf);
9938 pci_save_state(pdev);
4e3b35b0
NP		 9939#ifdef CONFIG_I40E_DCB
9940 err = i40e_init_pf_dcb(pf);
9941 if (err) {
aebfc816 9942 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 9943 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9944 /* Continue without DCB enabled */
4e3b35b0
NP		 9945 }
9946#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9947
9948 /* set up periodic task facility */
9949 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9950 pf->service_timer_period = HZ;
9951
9952 INIT_WORK(&pf->service_task, i40e_service_task);
9953 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9954 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9955 pf->link_check_timeout = jiffies;
9956
8e2773ae
SN		 9957 /* WoL defaults to disabled */
9958 pf->wol_en = false;
9959 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9960
41c445ff
JB		 9961 /* set up the main switch operations */
9962 i40e_determine_queue_usage(pf);
c1147280
JB		 9963 err = i40e_init_interrupt_scheme(pf);
9964 if (err)
9965 goto err_switch_setup;
41c445ff 9966
505682cd
MW		 9967 /* The number of VSIs reported by the FW is the minimum guaranteed
9968 * to us; HW supports far more and we share the remaining pool with
9969 * the other PFs. We allocate space for more than the guarantee with
9970 * the understanding that we might not get them all later.
41c445ff 9971 */
505682cd
MW		 9972 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9973 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9974 else
9975 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9976
9977 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9978 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9979 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9980 if (!pf->vsi) {
9981 err = -ENOMEM;
41c445ff 9982 goto err_switch_setup;
ed87ac09 9983 }
41c445ff 9984
fa11cb3d
ASJ		 9985#ifdef CONFIG_PCI_IOV
9986 /* prep for VF support */
9987 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9988 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9989 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
9990 if (pci_num_vf(pdev))
9991 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
9992 }
9993#endif
bc7d338f 9994 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9995 if (err) {
9996 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9997 goto err_vsis;
9998 }
8a9eb7d3 9999 /* if FDIR VSI was set up, start it now */
505682cd 10000 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10001 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10002 i40e_vsi_open(pf->vsi[i]);
10003 break;
10004 }
10005 }
41c445ff 10006
7e2453fe
JB		 10007 /* driver is only interested in link up/down and module qualification
10008 * reports from firmware
10009 */
10010 err = i40e_aq_set_phy_int_mask(&pf->hw,
10011 I40E_AQ_EVENT_LINK_UPDOWN |
10012 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10013 if (err)
f1c7e72e
SN		 10014 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10015 i40e_stat_str(&pf->hw, err),
10016 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10017
025b4a54
ASJ		 10018 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10019 (pf->hw.aq.fw_maj_ver < 4)) {
10020 msleep(75);
10021 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10022 if (err)
f1c7e72e
SN		 10023 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10024 i40e_stat_str(&pf->hw, err),
10025 i40e_aq_str(&pf->hw,
10026 pf->hw.aq.asq_last_status));
cafa2ee6 10027 }
41c445ff
JB		 10028 /* The main driver is (mostly) up and happy. We need to set this state
10029 * before setting up the misc vector or we get a race and the vector
10030 * ends up disabled forever.
10031 */
10032 clear_bit(__I40E_DOWN, &pf->state);
10033
10034 /* In case of MSIX we are going to setup the misc vector right here
10035 * to handle admin queue events etc. In case of legacy and MSI
10036 * the misc functionality and queue processing is combined in
10037 * the same vector and that gets setup at open.
10038 */
10039 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10040 err = i40e_setup_misc_vector(pf);
10041 if (err) {
10042 dev_info(&pdev->dev,
10043 "setup of misc vector failed: %d\n", err);
10044 goto err_vsis;
10045 }
10046 }
10047
df805f62 10048#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10049 /* prep for VF support */
10050 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10051 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10052 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10053 u32 val;
10054
10055 /* disable link interrupts for VFs */
10056 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10057 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10058 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10059 i40e_flush(hw);
4aeec010
MW		 10060
10061 if (pci_num_vf(pdev)) {
10062 dev_info(&pdev->dev,
10063 "Active VFs found, allocating resources.\n");
10064 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10065 if (err)
10066 dev_info(&pdev->dev,
10067 "Error %d allocating resources for existing VFs\n",
10068 err);
10069 }
41c445ff 10070 }
df805f62 10071#endif /* CONFIG_PCI_IOV */
41c445ff 10072
93cd765b
ASJ		 10073 pfs_found++;
10074
41c445ff
JB		 10075 i40e_dbg_pf_init(pf);
10076
10077 /* tell the firmware that we're starting */
44033fac 10078 i40e_send_version(pf);
41c445ff
JB		 10079
10080 /* since everything's happy, start the service_task timer */
10081 mod_timer(&pf->service_timer,
10082 round_jiffies(jiffies + pf->service_timer_period));
10083
38e00438
VD		 10084#ifdef I40E_FCOE
10085 /* create FCoE interface */
10086 i40e_fcoe_vsi_setup(pf);
10087
10088#endif
d4dfb81a
CS		 10089 /* Get the negotiated link width and speed from PCI config space */
10090 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
10091
10092 i40e_set_pci_config_data(hw, link_status);
10093
69bfb110 10094 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 10095 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
10096 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
10097 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
10098 "Unknown"),
10099 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
10100 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
10101 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
10102 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
10103 "Unknown"));
10104
10105 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10106 hw->bus.speed < i40e_bus_speed_8000) {
10107 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10108 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10109 }
10110
e827845c
CS		 10111 /* get the requested speeds from the fw */
10112 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10113 if (err)
f1c7e72e
SN		 10114 dev_info(&pf->pdev->dev,
10115 "get phy capabilities failed, err %s aq_err %s, advertised speed settings may not be correct\n",
10116 i40e_stat_str(&pf->hw, err),
10117 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10118 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10119
0c22b3dd
JB		 10120 /* print a string summarizing features */
10121 i40e_print_features(pf);
10122
41c445ff
JB		 10123 return 0;
10124
10125 /* Unwind what we've done if something failed in the setup */
10126err_vsis:
10127 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10128 i40e_clear_interrupt_scheme(pf);
10129 kfree(pf->vsi);
04b03013
SN		 10130err_switch_setup:
10131 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10132 del_timer_sync(&pf->service_timer);
10133err_mac_addr:
10134err_configure_lan_hmc:
10135 (void)i40e_shutdown_lan_hmc(hw);
10136err_init_lan_hmc:
10137 kfree(pf->qp_pile);
41c445ff
JB		 10138err_sw_init:
10139err_adminq_setup:
10140 (void)i40e_shutdown_adminq(hw);
10141err_pf_reset:
10142 iounmap(hw->hw_addr);
10143err_ioremap:
10144 kfree(pf);
10145err_pf_alloc:
10146 pci_disable_pcie_error_reporting(pdev);
10147 pci_release_selected_regions(pdev,
10148 pci_select_bars(pdev, IORESOURCE_MEM));
10149err_pci_reg:
10150err_dma:
10151 pci_disable_device(pdev);
10152 return err;
10153}
10154
10155/**
10156 * i40e_remove - Device removal routine
10157 * @pdev: PCI device information struct
10158 *
10159 * i40e_remove is called by the PCI subsystem to alert the driver
10160 * that is should release a PCI device. This could be caused by a
10161 * Hot-Plug event, or because the driver is going to be removed from
10162 * memory.
10163 **/
10164static void i40e_remove(struct pci_dev *pdev)
10165{
10166 struct i40e_pf *pf = pci_get_drvdata(pdev);
10167 i40e_status ret_code;
41c445ff
JB		 10168 int i;
10169
10170 i40e_dbg_pf_exit(pf);
10171
beb0dff1
JK		 10172 i40e_ptp_stop(pf);
10173
41c445ff
JB		 10174 /* no more scheduling of any task */
10175 set_bit(__I40E_DOWN, &pf->state);
10176 del_timer_sync(&pf->service_timer);
10177 cancel_work_sync(&pf->service_task);
33c62b34 10178 i40e_fdir_teardown(pf);
41c445ff 10179
eb2d80bc
MW		 10180 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10181 i40e_free_vfs(pf);
10182 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10183 }
10184
41c445ff
JB		 10185 i40e_fdir_teardown(pf);
10186
10187 /* If there is a switch structure or any orphans, remove them.
10188 * This will leave only the PF's VSI remaining.
10189 */
10190 for (i = 0; i < I40E_MAX_VEB; i++) {
10191 if (!pf->veb[i])
10192 continue;
10193
10194 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10195 pf->veb[i]->uplink_seid == 0)
10196 i40e_switch_branch_release(pf->veb[i]);
10197 }
10198
10199 /* Now we can shutdown the PF's VSI, just before we kill
10200 * adminq and hmc.
10201 */
10202 if (pf->vsi[pf->lan_vsi])
10203 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10204
41c445ff 10205 /* shutdown and destroy the HMC */
60442dea
SN		 10206 if (pf->hw.hmc.hmc_obj) {
10207 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10208 if (ret_code)
10209 dev_warn(&pdev->dev,
10210 "Failed to destroy the HMC resources: %d\n",
10211 ret_code);
10212 }
41c445ff
JB		 10213
10214 /* shutdown the adminq */
41c445ff
JB		 10215 ret_code = i40e_shutdown_adminq(&pf->hw);
10216 if (ret_code)
10217 dev_warn(&pdev->dev,
10218 "Failed to destroy the Admin Queue resources: %d\n",
10219 ret_code);
10220
10221 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10222 i40e_clear_interrupt_scheme(pf);
505682cd 10223 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10224 if (pf->vsi[i]) {
10225 i40e_vsi_clear_rings(pf->vsi[i]);
10226 i40e_vsi_clear(pf->vsi[i]);
10227 pf->vsi[i] = NULL;
10228 }
10229 }
10230
10231 for (i = 0; i < I40E_MAX_VEB; i++) {
10232 kfree(pf->veb[i]);
10233 pf->veb[i] = NULL;
10234 }
10235
10236 kfree(pf->qp_pile);
41c445ff
JB		 10237 kfree(pf->vsi);
10238
41c445ff
JB		 10239 iounmap(pf->hw.hw_addr);
10240 kfree(pf);
10241 pci_release_selected_regions(pdev,
10242 pci_select_bars(pdev, IORESOURCE_MEM));
10243
10244 pci_disable_pcie_error_reporting(pdev);
10245 pci_disable_device(pdev);
10246}
10247
10248/**
10249 * i40e_pci_error_detected - warning that something funky happened in PCI land
10250 * @pdev: PCI device information struct
10251 *
10252 * Called to warn that something happened and the error handling steps
10253 * are in progress. Allows the driver to quiesce things, be ready for
10254 * remediation.
10255 **/
10256static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10257 enum pci_channel_state error)
10258{
10259 struct i40e_pf *pf = pci_get_drvdata(pdev);
10260
10261 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10262
10263 /* shutdown all operations */
9007bccd
SN		 10264 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10265 rtnl_lock();
10266 i40e_prep_for_reset(pf);
10267 rtnl_unlock();
10268 }
41c445ff
JB		 10269
10270 /* Request a slot reset */
10271 return PCI_ERS_RESULT_NEED_RESET;
10272}
10273
10274/**
10275 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10276 * @pdev: PCI device information struct
10277 *
10278 * Called to find if the driver can work with the device now that
10279 * the pci slot has been reset. If a basic connection seems good
10280 * (registers are readable and have sane content) then return a
10281 * happy little PCI_ERS_RESULT_xxx.
10282 **/
10283static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10284{
10285 struct i40e_pf *pf = pci_get_drvdata(pdev);
10286 pci_ers_result_t result;
10287 int err;
10288 u32 reg;
10289
10290 dev_info(&pdev->dev, "%s\n", __func__);
10291 if (pci_enable_device_mem(pdev)) {
10292 dev_info(&pdev->dev,
10293 "Cannot re-enable PCI device after reset.\n");
10294 result = PCI_ERS_RESULT_DISCONNECT;
10295 } else {
10296 pci_set_master(pdev);
10297 pci_restore_state(pdev);
10298 pci_save_state(pdev);
10299 pci_wake_from_d3(pdev, false);
10300
10301 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10302 if (reg == 0)
10303 result = PCI_ERS_RESULT_RECOVERED;
10304 else
10305 result = PCI_ERS_RESULT_DISCONNECT;
10306 }
10307
10308 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10309 if (err) {
10310 dev_info(&pdev->dev,
10311 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10312 err);
10313 /* non-fatal, continue */
10314 }
10315
10316 return result;
10317}
10318
10319/**
10320 * i40e_pci_error_resume - restart operations after PCI error recovery
10321 * @pdev: PCI device information struct
10322 *
10323 * Called to allow the driver to bring things back up after PCI error
10324 * and/or reset recovery has finished.
10325 **/
10326static void i40e_pci_error_resume(struct pci_dev *pdev)
10327{
10328 struct i40e_pf *pf = pci_get_drvdata(pdev);
10329
10330 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10331 if (test_bit(__I40E_SUSPENDED, &pf->state))
10332 return;
10333
10334 rtnl_lock();
41c445ff 10335 i40e_handle_reset_warning(pf);
9007bccd
SN		 10336 rtnl_lock();
10337}
10338
10339/**
10340 * i40e_shutdown - PCI callback for shutting down
10341 * @pdev: PCI device information struct
10342 **/
10343static void i40e_shutdown(struct pci_dev *pdev)
10344{
10345 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10346 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10347
10348 set_bit(__I40E_SUSPENDED, &pf->state);
10349 set_bit(__I40E_DOWN, &pf->state);
10350 rtnl_lock();
10351 i40e_prep_for_reset(pf);
10352 rtnl_unlock();
10353
8e2773ae
SN		 10354 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10355 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10356
e147758d
SN		 10357 i40e_clear_interrupt_scheme(pf);
10358
9007bccd 10359 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10360 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10361 pci_set_power_state(pdev, PCI_D3hot);
10362 }
10363}
10364
10365#ifdef CONFIG_PM
10366/**
10367 * i40e_suspend - PCI callback for moving to D3
10368 * @pdev: PCI device information struct
10369 **/
10370static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10371{
10372 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10373 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10374
10375 set_bit(__I40E_SUSPENDED, &pf->state);
10376 set_bit(__I40E_DOWN, &pf->state);
88086e5d
MW		 10377 del_timer_sync(&pf->service_timer);
10378 cancel_work_sync(&pf->service_task);
3932dbfe
MW		 10379 i40e_fdir_teardown(pf);
10380
9007bccd
SN		 10381 rtnl_lock();
10382 i40e_prep_for_reset(pf);
10383 rtnl_unlock();
10384
8e2773ae
SN		 10385 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10386 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10387
10388 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10389 pci_set_power_state(pdev, PCI_D3hot);
10390
10391 return 0;
41c445ff
JB		 10392}
10393
9007bccd
SN		 10394/**
10395 * i40e_resume - PCI callback for waking up from D3
10396 * @pdev: PCI device information struct
10397 **/
10398static int i40e_resume(struct pci_dev *pdev)
10399{
10400 struct i40e_pf *pf = pci_get_drvdata(pdev);
10401 u32 err;
10402
10403 pci_set_power_state(pdev, PCI_D0);
10404 pci_restore_state(pdev);
10405 /* pci_restore_state() clears dev->state_saves, so
10406 * call pci_save_state() again to restore it.
10407 */
10408 pci_save_state(pdev);
10409
10410 err = pci_enable_device_mem(pdev);
10411 if (err) {
10412 dev_err(&pdev->dev,
10413 "%s: Cannot enable PCI device from suspend\n",
10414 __func__);
10415 return err;
10416 }
10417 pci_set_master(pdev);
10418
10419 /* no wakeup events while running */
10420 pci_wake_from_d3(pdev, false);
10421
10422 /* handling the reset will rebuild the device state */
10423 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10424 clear_bit(__I40E_DOWN, &pf->state);
10425 rtnl_lock();
10426 i40e_reset_and_rebuild(pf, false);
10427 rtnl_unlock();
10428 }
10429
10430 return 0;
10431}
10432
10433#endif
41c445ff
JB		 10434static const struct pci_error_handlers i40e_err_handler = {
10435 .error_detected = i40e_pci_error_detected,
10436 .slot_reset = i40e_pci_error_slot_reset,
10437 .resume = i40e_pci_error_resume,
10438};
10439
10440static struct pci_driver i40e_driver = {
10441 .name = i40e_driver_name,
10442 .id_table = i40e_pci_tbl,
10443 .probe = i40e_probe,
10444 .remove = i40e_remove,
9007bccd
SN		 10445#ifdef CONFIG_PM
10446 .suspend = i40e_suspend,
10447 .resume = i40e_resume,
10448#endif
10449 .shutdown = i40e_shutdown,
41c445ff
JB		 10450 .err_handler = &i40e_err_handler,
10451 .sriov_configure = i40e_pci_sriov_configure,
10452};
10453
10454/**
10455 * i40e_init_module - Driver registration routine
10456 *
10457 * i40e_init_module is the first routine called when the driver is
10458 * loaded. All it does is register with the PCI subsystem.
10459 **/
10460static int __init i40e_init_module(void)
10461{
10462 pr_info("%s: %s - version %s\n", i40e_driver_name,
10463 i40e_driver_string, i40e_driver_version_str);
10464 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10465
41c445ff
JB		 10466 i40e_dbg_init();
10467 return pci_register_driver(&i40e_driver);
10468}
10469module_init(i40e_init_module);
10470
10471/**
10472 * i40e_exit_module - Driver exit cleanup routine
10473 *
10474 * i40e_exit_module is called just before the driver is removed
10475 * from memory.
10476 **/
10477static void __exit i40e_exit_module(void)
10478{
10479 pci_unregister_driver(&i40e_driver);
10480 i40e_dbg_exit();
10481}
10482module_exit(i40e_exit_module);
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