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i40e: remove chatty log messages
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
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41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28/* Local includes */
29#include "i40e.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
582a74e5 42#define DRV_VERSION_BUILD 14
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
47static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
58
59/* i40e_pci_tbl - PCI Device ID Table
60 *
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
67 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
76 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
281 pf->tx_timeout_recovery_level = 0;
282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
307 i40e_down(vsi);
308 break;
309 }
310 i40e_service_event_schedule(pf);
311 pf->tx_timeout_recovery_level++;
312}
313
314/**
315 * i40e_release_rx_desc - Store the new tail and head values
316 * @rx_ring: ring to bump
317 * @val: new head index
318 **/
319static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
320{
321 rx_ring->next_to_use = val;
322
323 /* Force memory writes to complete before letting h/w
324 * know there are new descriptors to fetch. (Only
325 * applicable for weak-ordered memory model archs,
326 * such as IA-64).
327 */
328 wmb();
329 writel(val, rx_ring->tail);
330}
331
332/**
333 * i40e_get_vsi_stats_struct - Get System Network Statistics
334 * @vsi: the VSI we care about
335 *
336 * Returns the address of the device statistics structure.
337 * The statistics are actually updated from the service task.
338 **/
339struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
340{
341 return &vsi->net_stats;
342}
343
344/**
345 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
346 * @netdev: network interface device structure
347 *
348 * Returns the address of the device statistics structure.
349 * The statistics are actually updated from the service task.
350 **/
351static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
352 struct net_device *netdev,
980e9b11 353 struct rtnl_link_stats64 *stats)
41c445ff
JB		 354{
355 struct i40e_netdev_priv *np = netdev_priv(netdev);
356 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 357 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
358 int i;
359
143c9054 360
bc7d338f
ASJ		 361 if (test_bit(__I40E_DOWN, &vsi->state))
362 return stats;
363
3c325ced
JB		 364 if (!vsi->tx_rings)
365 return stats;
366
980e9b11
AD		 367 rcu_read_lock();
368 for (i = 0; i < vsi->num_queue_pairs; i++) {
369 struct i40e_ring *tx_ring, *rx_ring;
370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
378 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
381 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
388 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
391 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
398 /* following stats updated by ixgbe_watchdog_task() */
399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
426 if (vsi->rx_rings)
427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff
JB		 436 }
437 vsi->stat_offsets_loaded = false;
438}
439
440/**
441 * i40e_pf_reset_stats - Reset all of the stats for the given pf
442 * @pf: the PF to be reset
443 **/
444void i40e_pf_reset_stats(struct i40e_pf *pf)
445{
446 memset(&pf->stats, 0, sizeof(pf->stats));
447 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
448 pf->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_stat_update48 - read and update a 48 bit stat from the chip
453 * @hw: ptr to the hardware info
454 * @hireg: the high 32 bit reg to read
455 * @loreg: the low 32 bit reg to read
456 * @offset_loaded: has the initial offset been loaded yet
457 * @offset: ptr to current offset value
458 * @stat: ptr to the stat
459 *
460 * Since the device stats are not reset at PFReset, they likely will not
461 * be zeroed when the driver starts. We'll save the first values read
462 * and use them as offsets to be subtracted from the raw values in order
463 * to report stats that count from zero. In the process, we also manage
464 * the potential roll-over.
465 **/
466static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
467 bool offset_loaded, u64 *offset, u64 *stat)
468{
469 u64 new_data;
470
471 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
472 new_data = rd32(hw, loreg);
473 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
474 } else {
475 new_data = rd64(hw, loreg);
476 }
477 if (!offset_loaded)
478 *offset = new_data;
479 if (likely(new_data >= *offset))
480 *stat = new_data - *offset;
481 else
482 *stat = (new_data + ((u64)1 << 48)) - *offset;
483 *stat &= 0xFFFFFFFFFFFFULL;
484}
485
486/**
487 * i40e_stat_update32 - read and update a 32 bit stat from the chip
488 * @hw: ptr to the hardware info
489 * @reg: the hw reg to read
490 * @offset_loaded: has the initial offset been loaded yet
491 * @offset: ptr to current offset value
492 * @stat: ptr to the stat
493 **/
494static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
495 bool offset_loaded, u64 *offset, u64 *stat)
496{
497 u32 new_data;
498
499 new_data = rd32(hw, reg);
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = (u32)(new_data - *offset);
504 else
505 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
506}
507
508/**
509 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
510 * @vsi: the VSI to be updated
511 **/
512void i40e_update_eth_stats(struct i40e_vsi *vsi)
513{
514 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
515 struct i40e_pf *pf = vsi->back;
516 struct i40e_hw *hw = &pf->hw;
517 struct i40e_eth_stats *oes;
518 struct i40e_eth_stats *es; /* device's eth stats */
519
520 es = &vsi->eth_stats;
521 oes = &vsi->eth_stats_offsets;
522
523 /* Gather up the stats that the hw collects */
524 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
525 vsi->stat_offsets_loaded,
526 &oes->tx_errors, &es->tx_errors);
527 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->rx_discards, &es->rx_discards);
530
531 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
532 I40E_GLV_GORCL(stat_idx),
533 vsi->stat_offsets_loaded,
534 &oes->rx_bytes, &es->rx_bytes);
535 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
536 I40E_GLV_UPRCL(stat_idx),
537 vsi->stat_offsets_loaded,
538 &oes->rx_unicast, &es->rx_unicast);
539 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
540 I40E_GLV_MPRCL(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_multicast, &es->rx_multicast);
543 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
544 I40E_GLV_BPRCL(stat_idx),
545 vsi->stat_offsets_loaded,
546 &oes->rx_broadcast, &es->rx_broadcast);
547
548 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
549 I40E_GLV_GOTCL(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->tx_bytes, &es->tx_bytes);
552 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
553 I40E_GLV_UPTCL(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->tx_unicast, &es->tx_unicast);
556 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
557 I40E_GLV_MPTCL(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_multicast, &es->tx_multicast);
560 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
561 I40E_GLV_BPTCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->tx_broadcast, &es->tx_broadcast);
564 vsi->stat_offsets_loaded = true;
565}
566
567/**
568 * i40e_update_veb_stats - Update Switch component statistics
569 * @veb: the VEB being updated
570 **/
571static void i40e_update_veb_stats(struct i40e_veb *veb)
572{
573 struct i40e_pf *pf = veb->pf;
574 struct i40e_hw *hw = &pf->hw;
575 struct i40e_eth_stats *oes;
576 struct i40e_eth_stats *es; /* device's eth stats */
577 int idx = 0;
578
579 idx = veb->stats_idx;
580 es = &veb->stats;
581 oes = &veb->stats_offsets;
582
583 /* Gather up the stats that the hw collects */
584 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
585 veb->stat_offsets_loaded,
586 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 587 if (hw->revision_id > 0)
588 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
589 veb->stat_offsets_loaded,
590 &oes->rx_unknown_protocol,
591 &es->rx_unknown_protocol);
41c445ff
JB		 592 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
593 veb->stat_offsets_loaded,
594 &oes->rx_bytes, &es->rx_bytes);
595 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unicast, &es->rx_unicast);
598 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_multicast, &es->rx_multicast);
601 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_broadcast, &es->rx_broadcast);
604
605 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->tx_bytes, &es->tx_bytes);
608 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_unicast, &es->tx_unicast);
611 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_multicast, &es->tx_multicast);
614 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_broadcast, &es->tx_broadcast);
617 veb->stat_offsets_loaded = true;
618}
619
620/**
621 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
622 * @pf: the corresponding PF
623 *
624 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
625 **/
626static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
627{
628 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
629 struct i40e_hw_port_stats *nsd = &pf->stats;
630 struct i40e_hw *hw = &pf->hw;
631 u64 xoff = 0;
632 u16 i, v;
633
634 if ((hw->fc.current_mode != I40E_FC_FULL) &&
635 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
636 return;
637
638 xoff = nsd->link_xoff_rx;
639 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
640 pf->stat_offsets_loaded,
641 &osd->link_xoff_rx, &nsd->link_xoff_rx);
642
643 /* No new LFC xoff rx */
644 if (!(nsd->link_xoff_rx - xoff))
645 return;
646
647 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
648 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
649 struct i40e_vsi *vsi = pf->vsi[v];
650
651 if (!vsi)
652 continue;
653
654 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 655 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 656 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
657 }
658 }
659}
660
661/**
662 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
663 * @pf: the corresponding PF
664 *
665 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
666 **/
667static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
668{
669 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
670 struct i40e_hw_port_stats *nsd = &pf->stats;
671 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
672 struct i40e_dcbx_config *dcb_cfg;
673 struct i40e_hw *hw = &pf->hw;
674 u16 i, v;
675 u8 tc;
676
677 dcb_cfg = &hw->local_dcbx_config;
678
679 /* See if DCB enabled with PFC TC */
680 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
681 !(dcb_cfg->pfc.pfcenable)) {
682 i40e_update_link_xoff_rx(pf);
683 return;
684 }
685
686 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
687 u64 prio_xoff = nsd->priority_xoff_rx[i];
688 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
689 pf->stat_offsets_loaded,
690 &osd->priority_xoff_rx[i],
691 &nsd->priority_xoff_rx[i]);
692
693 /* No new PFC xoff rx */
694 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
695 continue;
696 /* Get the TC for given priority */
697 tc = dcb_cfg->etscfg.prioritytable[i];
698 xoff[tc] = true;
699 }
700
701 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
702 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
703 struct i40e_vsi *vsi = pf->vsi[v];
704
705 if (!vsi)
706 continue;
707
708 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 709 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 710
711 tc = ring->dcb_tc;
712 if (xoff[tc])
713 clear_bit(__I40E_HANG_CHECK_ARMED,
714 &ring->state);
715 }
716 }
717}
718
719/**
720 * i40e_update_stats - Update the board statistics counters.
721 * @vsi: the VSI to be updated
722 *
723 * There are a few instances where we store the same stat in a
724 * couple of different structs. This is partly because we have
725 * the netdev stats that need to be filled out, which is slightly
726 * different from the "eth_stats" defined by the chip and used in
727 * VF communications. We sort it all out here in a central place.
728 **/
729void i40e_update_stats(struct i40e_vsi *vsi)
730{
731 struct i40e_pf *pf = vsi->back;
732 struct i40e_hw *hw = &pf->hw;
733 struct rtnl_link_stats64 *ons;
734 struct rtnl_link_stats64 *ns; /* netdev stats */
735 struct i40e_eth_stats *oes;
736 struct i40e_eth_stats *es; /* device's eth stats */
737 u32 tx_restart, tx_busy;
738 u32 rx_page, rx_buf;
739 u64 rx_p, rx_b;
740 u64 tx_p, tx_b;
741 int i;
742 u16 q;
743
744 if (test_bit(__I40E_DOWN, &vsi->state) ||
745 test_bit(__I40E_CONFIG_BUSY, &pf->state))
746 return;
747
748 ns = i40e_get_vsi_stats_struct(vsi);
749 ons = &vsi->net_stats_offsets;
750 es = &vsi->eth_stats;
751 oes = &vsi->eth_stats_offsets;
752
753 /* Gather up the netdev and vsi stats that the driver collects
754 * on the fly during packet processing
755 */
756 rx_b = rx_p = 0;
757 tx_b = tx_p = 0;
758 tx_restart = tx_busy = 0;
759 rx_page = 0;
760 rx_buf = 0;
980e9b11 761 rcu_read_lock();
41c445ff
JB		 762 for (q = 0; q < vsi->num_queue_pairs; q++) {
763 struct i40e_ring *p;
980e9b11
AD		 764 u64 bytes, packets;
765 unsigned int start;
766
767 /* locate Tx ring */
768 p = ACCESS_ONCE(vsi->tx_rings[q]);
769
770 do {
771 start = u64_stats_fetch_begin_bh(&p->syncp);
772 packets = p->stats.packets;
773 bytes = p->stats.bytes;
774 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
775 tx_b += bytes;
776 tx_p += packets;
777 tx_restart += p->tx_stats.restart_queue;
778 tx_busy += p->tx_stats.tx_busy;
41c445ff 779
980e9b11
AD		 780 /* Rx queue is part of the same block as Tx queue */
781 p = &p[1];
782 do {
783 start = u64_stats_fetch_begin_bh(&p->syncp);
784 packets = p->stats.packets;
785 bytes = p->stats.bytes;
786 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
787 rx_b += bytes;
788 rx_p += packets;
41c445ff
JB		 789 rx_buf += p->rx_stats.alloc_rx_buff_failed;
790 rx_page += p->rx_stats.alloc_rx_page_failed;
41c445ff 791 }
980e9b11 792 rcu_read_unlock();
41c445ff
JB		 793 vsi->tx_restart = tx_restart;
794 vsi->tx_busy = tx_busy;
795 vsi->rx_page_failed = rx_page;
796 vsi->rx_buf_failed = rx_buf;
797
798 ns->rx_packets = rx_p;
799 ns->rx_bytes = rx_b;
800 ns->tx_packets = tx_p;
801 ns->tx_bytes = tx_b;
802
803 i40e_update_eth_stats(vsi);
804 /* update netdev stats from eth stats */
805 ons->rx_errors = oes->rx_errors;
806 ns->rx_errors = es->rx_errors;
807 ons->tx_errors = oes->tx_errors;
808 ns->tx_errors = es->tx_errors;
809 ons->multicast = oes->rx_multicast;
810 ns->multicast = es->rx_multicast;
811 ons->tx_dropped = oes->tx_discards;
812 ns->tx_dropped = es->tx_discards;
813
814 /* Get the port data only if this is the main PF VSI */
815 if (vsi == pf->vsi[pf->lan_vsi]) {
816 struct i40e_hw_port_stats *nsd = &pf->stats;
817 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
818
819 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
820 I40E_GLPRT_GORCL(hw->port),
821 pf->stat_offsets_loaded,
822 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
823 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
824 I40E_GLPRT_GOTCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
827 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
828 pf->stat_offsets_loaded,
829 &osd->eth.rx_discards,
830 &nsd->eth.rx_discards);
831 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.tx_discards,
834 &nsd->eth.tx_discards);
835 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
836 I40E_GLPRT_MPRCL(hw->port),
837 pf->stat_offsets_loaded,
838 &osd->eth.rx_multicast,
839 &nsd->eth.rx_multicast);
840
841 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
842 pf->stat_offsets_loaded,
843 &osd->tx_dropped_link_down,
844 &nsd->tx_dropped_link_down);
845
846 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->crc_errors, &nsd->crc_errors);
849 ns->rx_crc_errors = nsd->crc_errors;
850
851 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->illegal_bytes, &nsd->illegal_bytes);
854 ns->rx_errors = nsd->crc_errors
855 + nsd->illegal_bytes;
856
857 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->mac_local_faults,
860 &nsd->mac_local_faults);
861 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_remote_faults,
864 &nsd->mac_remote_faults);
865
866 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
867 pf->stat_offsets_loaded,
868 &osd->rx_length_errors,
869 &nsd->rx_length_errors);
870 ns->rx_length_errors = nsd->rx_length_errors;
871
872 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->link_xon_rx, &nsd->link_xon_rx);
875 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
876 pf->stat_offsets_loaded,
877 &osd->link_xon_tx, &nsd->link_xon_tx);
878 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
879 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xoff_tx, &nsd->link_xoff_tx);
882
883 for (i = 0; i < 8; i++) {
884 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
885 pf->stat_offsets_loaded,
886 &osd->priority_xon_rx[i],
887 &nsd->priority_xon_rx[i]);
888 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_tx[i],
891 &nsd->priority_xon_tx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xoff_tx[i],
895 &nsd->priority_xoff_tx[i]);
896 i40e_stat_update32(hw,
897 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
898 pf->stat_offsets_loaded,
899 &osd->priority_xon_2_xoff[i],
900 &nsd->priority_xon_2_xoff[i]);
901 }
902
903 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
904 I40E_GLPRT_PRC64L(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->rx_size_64, &nsd->rx_size_64);
907 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
908 I40E_GLPRT_PRC127L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_127, &nsd->rx_size_127);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
912 I40E_GLPRT_PRC255L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_255, &nsd->rx_size_255);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
916 I40E_GLPRT_PRC511L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_511, &nsd->rx_size_511);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
920 I40E_GLPRT_PRC1023L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_1023, &nsd->rx_size_1023);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
924 I40E_GLPRT_PRC1522L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1522, &nsd->rx_size_1522);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
928 I40E_GLPRT_PRC9522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_big, &nsd->rx_size_big);
931
932 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
933 I40E_GLPRT_PTC64L(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->tx_size_64, &nsd->tx_size_64);
936 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
937 I40E_GLPRT_PTC127L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_127, &nsd->tx_size_127);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
941 I40E_GLPRT_PTC255L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_255, &nsd->tx_size_255);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
945 I40E_GLPRT_PTC511L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_511, &nsd->tx_size_511);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
949 I40E_GLPRT_PTC1023L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_1023, &nsd->tx_size_1023);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
953 I40E_GLPRT_PTC1522L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1522, &nsd->tx_size_1522);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
957 I40E_GLPRT_PTC9522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_big, &nsd->tx_size_big);
960
961 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->rx_undersize, &nsd->rx_undersize);
964 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_fragments, &nsd->rx_fragments);
967 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->rx_oversize, &nsd->rx_oversize);
970 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_jabber, &nsd->rx_jabber);
973 }
974
975 pf->stat_offsets_loaded = true;
976}
977
978/**
979 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
980 * @vsi: the VSI to be searched
981 * @macaddr: the MAC address
982 * @vlan: the vlan
983 * @is_vf: make sure its a vf filter, else doesn't matter
984 * @is_netdev: make sure its a netdev filter, else doesn't matter
985 *
986 * Returns ptr to the filter object or NULL
987 **/
988static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
989 u8 *macaddr, s16 vlan,
990 bool is_vf, bool is_netdev)
991{
992 struct i40e_mac_filter *f;
993
994 if (!vsi || !macaddr)
995 return NULL;
996
997 list_for_each_entry(f, &vsi->mac_filter_list, list) {
998 if ((ether_addr_equal(macaddr, f->macaddr)) &&
999 (vlan == f->vlan) &&
1000 (!is_vf || f->is_vf) &&
1001 (!is_netdev || f->is_netdev))
1002 return f;
1003 }
1004 return NULL;
1005}
1006
1007/**
1008 * i40e_find_mac - Find a mac addr in the macvlan filters list
1009 * @vsi: the VSI to be searched
1010 * @macaddr: the MAC address we are searching for
1011 * @is_vf: make sure its a vf filter, else doesn't matter
1012 * @is_netdev: make sure its a netdev filter, else doesn't matter
1013 *
1014 * Returns the first filter with the provided MAC address or NULL if
1015 * MAC address was not found
1016 **/
1017struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1018 bool is_vf, bool is_netdev)
1019{
1020 struct i40e_mac_filter *f;
1021
1022 if (!vsi || !macaddr)
1023 return NULL;
1024
1025 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1026 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1027 (!is_vf || f->is_vf) &&
1028 (!is_netdev || f->is_netdev))
1029 return f;
1030 }
1031 return NULL;
1032}
1033
1034/**
1035 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1036 * @vsi: the VSI to be searched
1037 *
1038 * Returns true if VSI is in vlan mode or false otherwise
1039 **/
1040bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1041{
1042 struct i40e_mac_filter *f;
1043
1044 /* Only -1 for all the filters denotes not in vlan mode
1045 * so we have to go through all the list in order to make sure
1046 */
1047 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1048 if (f->vlan >= 0)
1049 return true;
1050 }
1051
1052 return false;
1053}
1054
1055/**
1056 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1057 * @vsi: the VSI to be searched
1058 * @macaddr: the mac address to be filtered
1059 * @is_vf: true if it is a vf
1060 * @is_netdev: true if it is a netdev
1061 *
1062 * Goes through all the macvlan filters and adds a
1063 * macvlan filter for each unique vlan that already exists
1064 *
1065 * Returns first filter found on success, else NULL
1066 **/
1067struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1068 bool is_vf, bool is_netdev)
1069{
1070 struct i40e_mac_filter *f;
1071
1072 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1073 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1074 is_vf, is_netdev)) {
1075 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev))
1077 return NULL;
1078 }
1079 }
1080
1081 return list_first_entry_or_null(&vsi->mac_filter_list,
1082 struct i40e_mac_filter, list);
1083}
1084
1085/**
1086 * i40e_add_filter - Add a mac/vlan filter to the VSI
1087 * @vsi: the VSI to be searched
1088 * @macaddr: the MAC address
1089 * @vlan: the vlan
1090 * @is_vf: make sure its a vf filter, else doesn't matter
1091 * @is_netdev: make sure its a netdev filter, else doesn't matter
1092 *
1093 * Returns ptr to the filter object or NULL when no memory available.
1094 **/
1095struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1096 u8 *macaddr, s16 vlan,
1097 bool is_vf, bool is_netdev)
1098{
1099 struct i40e_mac_filter *f;
1100
1101 if (!vsi || !macaddr)
1102 return NULL;
1103
1104 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1105 if (!f) {
1106 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1107 if (!f)
1108 goto add_filter_out;
1109
1110 memcpy(f->macaddr, macaddr, ETH_ALEN);
1111 f->vlan = vlan;
1112 f->changed = true;
1113
1114 INIT_LIST_HEAD(&f->list);
1115 list_add(&f->list, &vsi->mac_filter_list);
1116 }
1117
1118 /* increment counter and add a new flag if needed */
1119 if (is_vf) {
1120 if (!f->is_vf) {
1121 f->is_vf = true;
1122 f->counter++;
1123 }
1124 } else if (is_netdev) {
1125 if (!f->is_netdev) {
1126 f->is_netdev = true;
1127 f->counter++;
1128 }
1129 } else {
1130 f->counter++;
1131 }
1132
1133 /* changed tells sync_filters_subtask to
1134 * push the filter down to the firmware
1135 */
1136 if (f->changed) {
1137 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1138 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1139 }
1140
1141add_filter_out:
1142 return f;
1143}
1144
1145/**
1146 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
1150 * @is_vf: make sure it's a vf filter, else doesn't matter
1151 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1152 **/
1153void i40e_del_filter(struct i40e_vsi *vsi,
1154 u8 *macaddr, s16 vlan,
1155 bool is_vf, bool is_netdev)
1156{
1157 struct i40e_mac_filter *f;
1158
1159 if (!vsi || !macaddr)
1160 return;
1161
1162 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1163 if (!f || f->counter == 0)
1164 return;
1165
1166 if (is_vf) {
1167 if (f->is_vf) {
1168 f->is_vf = false;
1169 f->counter--;
1170 }
1171 } else if (is_netdev) {
1172 if (f->is_netdev) {
1173 f->is_netdev = false;
1174 f->counter--;
1175 }
1176 } else {
1177 /* make sure we don't remove a filter in use by vf or netdev */
1178 int min_f = 0;
1179 min_f += (f->is_vf ? 1 : 0);
1180 min_f += (f->is_netdev ? 1 : 0);
1181
1182 if (f->counter > min_f)
1183 f->counter--;
1184 }
1185
1186 /* counter == 0 tells sync_filters_subtask to
1187 * remove the filter from the firmware's list
1188 */
1189 if (f->counter == 0) {
1190 f->changed = true;
1191 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1192 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1193 }
1194}
1195
1196/**
1197 * i40e_set_mac - NDO callback to set mac address
1198 * @netdev: network interface device structure
1199 * @p: pointer to an address structure
1200 *
1201 * Returns 0 on success, negative on failure
1202 **/
1203static int i40e_set_mac(struct net_device *netdev, void *p)
1204{
1205 struct i40e_netdev_priv *np = netdev_priv(netdev);
1206 struct i40e_vsi *vsi = np->vsi;
1207 struct sockaddr *addr = p;
1208 struct i40e_mac_filter *f;
1209
1210 if (!is_valid_ether_addr(addr->sa_data))
1211 return -EADDRNOTAVAIL;
1212
1213 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1214
1215 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1216 return 0;
1217
1218 if (vsi->type == I40E_VSI_MAIN) {
1219 i40e_status ret;
1220 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1221 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1222 addr->sa_data, NULL);
1223 if (ret) {
1224 netdev_info(netdev,
1225 "Addr change for Main VSI failed: %d\n",
1226 ret);
1227 return -EADDRNOTAVAIL;
1228 }
1229
1230 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1231 }
1232
1233 /* In order to be sure to not drop any packets, add the new address
1234 * then delete the old one.
1235 */
1236 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1237 if (!f)
1238 return -ENOMEM;
1239
1240 i40e_sync_vsi_filters(vsi);
1241 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1242 i40e_sync_vsi_filters(vsi);
1243
1244 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1245
1246 return 0;
1247}
1248
1249/**
1250 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1251 * @vsi: the VSI being setup
1252 * @ctxt: VSI context structure
1253 * @enabled_tc: Enabled TCs bitmap
1254 * @is_add: True if called before Add VSI
1255 *
1256 * Setup VSI queue mapping for enabled traffic classes.
1257 **/
1258static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1259 struct i40e_vsi_context *ctxt,
1260 u8 enabled_tc,
1261 bool is_add)
1262{
1263 struct i40e_pf *pf = vsi->back;
1264 u16 sections = 0;
1265 u8 netdev_tc = 0;
1266 u16 numtc = 0;
1267 u16 qcount;
1268 u8 offset;
1269 u16 qmap;
1270 int i;
1271
1272 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1273 offset = 0;
1274
1275 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1276 /* Find numtc from enabled TC bitmap */
1277 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1278 if (enabled_tc & (1 << i)) /* TC is enabled */
1279 numtc++;
1280 }
1281 if (!numtc) {
1282 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1283 numtc = 1;
1284 }
1285 } else {
1286 /* At least TC0 is enabled in case of non-DCB case */
1287 numtc = 1;
1288 }
1289
1290 vsi->tc_config.numtc = numtc;
1291 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1292
1293 /* Setup queue offset/count for all TCs for given VSI */
1294 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1295 /* See if the given TC is enabled for the given VSI */
1296 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1297 int pow, num_qps;
1298
1299 vsi->tc_config.tc_info[i].qoffset = offset;
1300 switch (vsi->type) {
1301 case I40E_VSI_MAIN:
1302 if (i == 0)
1303 qcount = pf->rss_size;
1304 else
1305 qcount = pf->num_tc_qps;
1306 vsi->tc_config.tc_info[i].qcount = qcount;
1307 break;
1308 case I40E_VSI_FDIR:
1309 case I40E_VSI_SRIOV:
1310 case I40E_VSI_VMDQ2:
1311 default:
1312 qcount = vsi->alloc_queue_pairs;
1313 vsi->tc_config.tc_info[i].qcount = qcount;
1314 WARN_ON(i != 0);
1315 break;
1316 }
1317
1318 /* find the power-of-2 of the number of queue pairs */
1319 num_qps = vsi->tc_config.tc_info[i].qcount;
1320 pow = 0;
1321 while (num_qps &&
1322 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1323 pow++;
1324 num_qps >>= 1;
1325 }
1326
1327 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1328 qmap =
1329 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1330 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1331
1332 offset += vsi->tc_config.tc_info[i].qcount;
1333 } else {
1334 /* TC is not enabled so set the offset to
1335 * default queue and allocate one queue
1336 * for the given TC.
1337 */
1338 vsi->tc_config.tc_info[i].qoffset = 0;
1339 vsi->tc_config.tc_info[i].qcount = 1;
1340 vsi->tc_config.tc_info[i].netdev_tc = 0;
1341
1342 qmap = 0;
1343 }
1344 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1345 }
1346
1347 /* Set actual Tx/Rx queue pairs */
1348 vsi->num_queue_pairs = offset;
1349
1350 /* Scheduler section valid can only be set for ADD VSI */
1351 if (is_add) {
1352 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1353
1354 ctxt->info.up_enable_bits = enabled_tc;
1355 }
1356 if (vsi->type == I40E_VSI_SRIOV) {
1357 ctxt->info.mapping_flags |=
1358 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1359 for (i = 0; i < vsi->num_queue_pairs; i++)
1360 ctxt->info.queue_mapping[i] =
1361 cpu_to_le16(vsi->base_queue + i);
1362 } else {
1363 ctxt->info.mapping_flags |=
1364 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1365 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1366 }
1367 ctxt->info.valid_sections |= cpu_to_le16(sections);
1368}
1369
1370/**
1371 * i40e_set_rx_mode - NDO callback to set the netdev filters
1372 * @netdev: network interface device structure
1373 **/
1374static void i40e_set_rx_mode(struct net_device *netdev)
1375{
1376 struct i40e_netdev_priv *np = netdev_priv(netdev);
1377 struct i40e_mac_filter *f, *ftmp;
1378 struct i40e_vsi *vsi = np->vsi;
1379 struct netdev_hw_addr *uca;
1380 struct netdev_hw_addr *mca;
1381 struct netdev_hw_addr *ha;
1382
1383 /* add addr if not already in the filter list */
1384 netdev_for_each_uc_addr(uca, netdev) {
1385 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1386 if (i40e_is_vsi_in_vlan(vsi))
1387 i40e_put_mac_in_vlan(vsi, uca->addr,
1388 false, true);
1389 else
1390 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1391 false, true);
1392 }
1393 }
1394
1395 netdev_for_each_mc_addr(mca, netdev) {
1396 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1397 if (i40e_is_vsi_in_vlan(vsi))
1398 i40e_put_mac_in_vlan(vsi, mca->addr,
1399 false, true);
1400 else
1401 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1402 false, true);
1403 }
1404 }
1405
1406 /* remove filter if not in netdev list */
1407 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1408 bool found = false;
1409
1410 if (!f->is_netdev)
1411 continue;
1412
1413 if (is_multicast_ether_addr(f->macaddr)) {
1414 netdev_for_each_mc_addr(mca, netdev) {
1415 if (ether_addr_equal(mca->addr, f->macaddr)) {
1416 found = true;
1417 break;
1418 }
1419 }
1420 } else {
1421 netdev_for_each_uc_addr(uca, netdev) {
1422 if (ether_addr_equal(uca->addr, f->macaddr)) {
1423 found = true;
1424 break;
1425 }
1426 }
1427
1428 for_each_dev_addr(netdev, ha) {
1429 if (ether_addr_equal(ha->addr, f->macaddr)) {
1430 found = true;
1431 break;
1432 }
1433 }
1434 }
1435 if (!found)
1436 i40e_del_filter(
1437 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1438 }
1439
1440 /* check for other flag changes */
1441 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1442 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1443 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1444 }
1445}
1446
1447/**
1448 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1449 * @vsi: ptr to the VSI
1450 *
1451 * Push any outstanding VSI filter changes through the AdminQ.
1452 *
1453 * Returns 0 or error value
1454 **/
1455int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1456{
1457 struct i40e_mac_filter *f, *ftmp;
1458 bool promisc_forced_on = false;
1459 bool add_happened = false;
1460 int filter_list_len = 0;
1461 u32 changed_flags = 0;
dcae29be 1462 i40e_status aq_ret = 0;
41c445ff
JB		 1463 struct i40e_pf *pf;
1464 int num_add = 0;
1465 int num_del = 0;
1466 u16 cmd_flags;
1467
1468 /* empty array typed pointers, kcalloc later */
1469 struct i40e_aqc_add_macvlan_element_data *add_list;
1470 struct i40e_aqc_remove_macvlan_element_data *del_list;
1471
1472 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1473 usleep_range(1000, 2000);
1474 pf = vsi->back;
1475
1476 if (vsi->netdev) {
1477 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1478 vsi->current_netdev_flags = vsi->netdev->flags;
1479 }
1480
1481 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1482 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1483
1484 filter_list_len = pf->hw.aq.asq_buf_size /
1485 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1486 del_list = kcalloc(filter_list_len,
1487 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1488 GFP_KERNEL);
1489 if (!del_list)
1490 return -ENOMEM;
1491
1492 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1493 if (!f->changed)
1494 continue;
1495
1496 if (f->counter != 0)
1497 continue;
1498 f->changed = false;
1499 cmd_flags = 0;
1500
1501 /* add to delete list */
1502 memcpy(del_list[num_del].mac_addr,
1503 f->macaddr, ETH_ALEN);
1504 del_list[num_del].vlan_tag =
1505 cpu_to_le16((u16)(f->vlan ==
1506 I40E_VLAN_ANY ? 0 : f->vlan));
1507
1508 /* vlan0 as wild card to allow packets from all vlans */
1509 if (f->vlan == I40E_VLAN_ANY ||
1510 (vsi->netdev && !(vsi->netdev->features &
1511 NETIF_F_HW_VLAN_CTAG_FILTER)))
1512 cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1513 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1514 del_list[num_del].flags = cmd_flags;
1515 num_del++;
1516
1517 /* unlink from filter list */
1518 list_del(&f->list);
1519 kfree(f);
1520
1521 /* flush a full buffer */
1522 if (num_del == filter_list_len) {
dcae29be 1523 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1524 vsi->seid, del_list, num_del,
1525 NULL);
1526 num_del = 0;
1527 memset(del_list, 0, sizeof(*del_list));
1528
dcae29be 1529 if (aq_ret)
41c445ff
JB		 1530 dev_info(&pf->pdev->dev,
1531 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1532 aq_ret,
41c445ff
JB		 1533 pf->hw.aq.asq_last_status);
1534 }
1535 }
1536 if (num_del) {
dcae29be 1537 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1538 del_list, num_del, NULL);
1539 num_del = 0;
1540
dcae29be 1541 if (aq_ret)
41c445ff
JB		 1542 dev_info(&pf->pdev->dev,
1543 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1544 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1545 }
1546
1547 kfree(del_list);
1548 del_list = NULL;
1549
1550 /* do all the adds now */
1551 filter_list_len = pf->hw.aq.asq_buf_size /
1552 sizeof(struct i40e_aqc_add_macvlan_element_data),
1553 add_list = kcalloc(filter_list_len,
1554 sizeof(struct i40e_aqc_add_macvlan_element_data),
1555 GFP_KERNEL);
1556 if (!add_list)
1557 return -ENOMEM;
1558
1559 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1560 if (!f->changed)
1561 continue;
1562
1563 if (f->counter == 0)
1564 continue;
1565 f->changed = false;
1566 add_happened = true;
1567 cmd_flags = 0;
1568
1569 /* add to add array */
1570 memcpy(add_list[num_add].mac_addr,
1571 f->macaddr, ETH_ALEN);
1572 add_list[num_add].vlan_tag =
1573 cpu_to_le16(
1574 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1575 add_list[num_add].queue_number = 0;
1576
1577 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
1578
1579 /* vlan0 as wild card to allow packets from all vlans */
1580 if (f->vlan == I40E_VLAN_ANY || (vsi->netdev &&
1581 !(vsi->netdev->features &
1582 NETIF_F_HW_VLAN_CTAG_FILTER)))
1583 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
1584 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1585 num_add++;
1586
1587 /* flush a full buffer */
1588 if (num_add == filter_list_len) {
dcae29be
JB		 1589 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1590 add_list, num_add,
1591 NULL);
41c445ff
JB		 1592 num_add = 0;
1593
dcae29be 1594 if (aq_ret)
41c445ff
JB		 1595 break;
1596 memset(add_list, 0, sizeof(*add_list));
1597 }
1598 }
1599 if (num_add) {
dcae29be
JB		 1600 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1601 add_list, num_add, NULL);
41c445ff
JB		 1602 num_add = 0;
1603 }
1604 kfree(add_list);
1605 add_list = NULL;
1606
dcae29be 1607 if (add_happened && (!aq_ret)) {
41c445ff 1608 /* do nothing */;
dcae29be 1609 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1610 dev_info(&pf->pdev->dev,
1611 "add filter failed, err %d, aq_err %d\n",
dcae29be 1612 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1613 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1614 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1615 &vsi->state)) {
1616 promisc_forced_on = true;
1617 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1618 &vsi->state);
1619 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1620 }
1621 }
1622 }
1623
1624 /* check for changes in promiscuous modes */
1625 if (changed_flags & IFF_ALLMULTI) {
1626 bool cur_multipromisc;
1627 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1628 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1629 vsi->seid,
1630 cur_multipromisc,
1631 NULL);
1632 if (aq_ret)
41c445ff
JB		 1633 dev_info(&pf->pdev->dev,
1634 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1635 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1636 }
1637 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1638 bool cur_promisc;
1639 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1640 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1641 &vsi->state));
dcae29be
JB		 1642 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1643 vsi->seid,
1644 cur_promisc, NULL);
1645 if (aq_ret)
41c445ff
JB		 1646 dev_info(&pf->pdev->dev,
1647 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1648 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1649 }
1650
1651 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1652 return 0;
1653}
1654
1655/**
1656 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1657 * @pf: board private structure
1658 **/
1659static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1660{
1661 int v;
1662
1663 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1664 return;
1665 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1666
1667 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1668 if (pf->vsi[v] &&
1669 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1670 i40e_sync_vsi_filters(pf->vsi[v]);
1671 }
1672}
1673
1674/**
1675 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1676 * @netdev: network interface device structure
1677 * @new_mtu: new value for maximum frame size
1678 *
1679 * Returns 0 on success, negative on failure
1680 **/
1681static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1682{
1683 struct i40e_netdev_priv *np = netdev_priv(netdev);
1684 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1685 struct i40e_vsi *vsi = np->vsi;
1686
1687 /* MTU < 68 is an error and causes problems on some kernels */
1688 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1689 return -EINVAL;
1690
1691 netdev_info(netdev, "changing MTU from %d to %d\n",
1692 netdev->mtu, new_mtu);
1693 netdev->mtu = new_mtu;
1694 if (netif_running(netdev))
1695 i40e_vsi_reinit_locked(vsi);
1696
1697 return 0;
1698}
1699
1700/**
1701 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1702 * @vsi: the vsi being adjusted
1703 **/
1704void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1705{
1706 struct i40e_vsi_context ctxt;
1707 i40e_status ret;
1708
1709 if ((vsi->info.valid_sections &
1710 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1711 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1712 return; /* already enabled */
1713
1714 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1715 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1716 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1717
1718 ctxt.seid = vsi->seid;
1719 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1720 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1721 if (ret) {
1722 dev_info(&vsi->back->pdev->dev,
1723 "%s: update vsi failed, aq_err=%d\n",
1724 __func__, vsi->back->hw.aq.asq_last_status);
1725 }
1726}
1727
1728/**
1729 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1730 * @vsi: the vsi being adjusted
1731 **/
1732void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1733{
1734 struct i40e_vsi_context ctxt;
1735 i40e_status ret;
1736
1737 if ((vsi->info.valid_sections &
1738 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1739 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1740 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1741 return; /* already disabled */
1742
1743 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1744 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1745 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1746
1747 ctxt.seid = vsi->seid;
1748 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1749 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1750 if (ret) {
1751 dev_info(&vsi->back->pdev->dev,
1752 "%s: update vsi failed, aq_err=%d\n",
1753 __func__, vsi->back->hw.aq.asq_last_status);
1754 }
1755}
1756
1757/**
1758 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1759 * @netdev: network interface to be adjusted
1760 * @features: netdev features to test if VLAN offload is enabled or not
1761 **/
1762static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1763{
1764 struct i40e_netdev_priv *np = netdev_priv(netdev);
1765 struct i40e_vsi *vsi = np->vsi;
1766
1767 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1768 i40e_vlan_stripping_enable(vsi);
1769 else
1770 i40e_vlan_stripping_disable(vsi);
1771}
1772
1773/**
1774 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1775 * @vsi: the vsi being configured
1776 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1777 **/
1778int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1779{
1780 struct i40e_mac_filter *f, *add_f;
1781 bool is_netdev, is_vf;
1782 int ret;
1783
1784 is_vf = (vsi->type == I40E_VSI_SRIOV);
1785 is_netdev = !!(vsi->netdev);
1786
1787 if (is_netdev) {
1788 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1789 is_vf, is_netdev);
1790 if (!add_f) {
1791 dev_info(&vsi->back->pdev->dev,
1792 "Could not add vlan filter %d for %pM\n",
1793 vid, vsi->netdev->dev_addr);
1794 return -ENOMEM;
1795 }
1796 }
1797
1798 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1799 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1800 if (!add_f) {
1801 dev_info(&vsi->back->pdev->dev,
1802 "Could not add vlan filter %d for %pM\n",
1803 vid, f->macaddr);
1804 return -ENOMEM;
1805 }
1806 }
1807
1808 ret = i40e_sync_vsi_filters(vsi);
1809 if (ret) {
1810 dev_info(&vsi->back->pdev->dev,
1811 "Could not sync filters for vid %d\n", vid);
1812 return ret;
1813 }
1814
1815 /* Now if we add a vlan tag, make sure to check if it is the first
1816 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1817 * with 0, so we now accept untagged and specified tagged traffic
1818 * (and not any taged and untagged)
1819 */
1820 if (vid > 0) {
1821 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1822 I40E_VLAN_ANY,
1823 is_vf, is_netdev)) {
1824 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1825 I40E_VLAN_ANY, is_vf, is_netdev);
1826 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1827 is_vf, is_netdev);
1828 if (!add_f) {
1829 dev_info(&vsi->back->pdev->dev,
1830 "Could not add filter 0 for %pM\n",
1831 vsi->netdev->dev_addr);
1832 return -ENOMEM;
1833 }
1834 }
1835
1836 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1837 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1838 is_vf, is_netdev)) {
1839 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1840 is_vf, is_netdev);
1841 add_f = i40e_add_filter(vsi, f->macaddr,
1842 0, is_vf, is_netdev);
1843 if (!add_f) {
1844 dev_info(&vsi->back->pdev->dev,
1845 "Could not add filter 0 for %pM\n",
1846 f->macaddr);
1847 return -ENOMEM;
1848 }
1849 }
1850 }
1851 ret = i40e_sync_vsi_filters(vsi);
1852 }
1853
1854 return ret;
1855}
1856
1857/**
1858 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1859 * @vsi: the vsi being configured
1860 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1861 *
1862 * Return: 0 on success or negative otherwise
41c445ff
JB		 1863 **/
1864int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1865{
1866 struct net_device *netdev = vsi->netdev;
1867 struct i40e_mac_filter *f, *add_f;
1868 bool is_vf, is_netdev;
1869 int filter_count = 0;
1870 int ret;
1871
1872 is_vf = (vsi->type == I40E_VSI_SRIOV);
1873 is_netdev = !!(netdev);
1874
1875 if (is_netdev)
1876 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1877
1878 list_for_each_entry(f, &vsi->mac_filter_list, list)
1879 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1880
1881 ret = i40e_sync_vsi_filters(vsi);
1882 if (ret) {
1883 dev_info(&vsi->back->pdev->dev, "Could not sync filters\n");
1884 return ret;
1885 }
1886
1887 /* go through all the filters for this VSI and if there is only
1888 * vid == 0 it means there are no other filters, so vid 0 must
1889 * be replaced with -1. This signifies that we should from now
1890 * on accept any traffic (with any tag present, or untagged)
1891 */
1892 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1893 if (is_netdev) {
1894 if (f->vlan &&
1895 ether_addr_equal(netdev->dev_addr, f->macaddr))
1896 filter_count++;
1897 }
1898
1899 if (f->vlan)
1900 filter_count++;
1901 }
1902
1903 if (!filter_count && is_netdev) {
1904 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1905 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1906 is_vf, is_netdev);
1907 if (!f) {
1908 dev_info(&vsi->back->pdev->dev,
1909 "Could not add filter %d for %pM\n",
1910 I40E_VLAN_ANY, netdev->dev_addr);
1911 return -ENOMEM;
1912 }
1913 }
1914
1915 if (!filter_count) {
1916 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1917 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1918 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1919 is_vf, is_netdev);
1920 if (!add_f) {
1921 dev_info(&vsi->back->pdev->dev,
1922 "Could not add filter %d for %pM\n",
1923 I40E_VLAN_ANY, f->macaddr);
1924 return -ENOMEM;
1925 }
1926 }
1927 }
1928
1929 return i40e_sync_vsi_filters(vsi);
1930}
1931
1932/**
1933 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1934 * @netdev: network interface to be adjusted
1935 * @vid: vlan id to be added
078b5876
JB		 1936 *
1937 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1938 **/
1939static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1940 __always_unused __be16 proto, u16 vid)
1941{
1942 struct i40e_netdev_priv *np = netdev_priv(netdev);
1943 struct i40e_vsi *vsi = np->vsi;
078b5876 1944 int ret = 0;
41c445ff
JB		 1945
1946 if (vid > 4095)
078b5876
JB		 1947 return -EINVAL;
1948
1949 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1950
41c445ff
JB		 1951 /* If the network stack called us with vid = 0, we should
1952 * indicate to i40e_vsi_add_vlan() that we want to receive
1953 * any traffic (i.e. with any vlan tag, or untagged)
1954 */
1955 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1956
078b5876
JB		 1957 if (!ret && (vid < VLAN_N_VID))
1958 set_bit(vid, vsi->active_vlans);
41c445ff 1959
078b5876 1960 return ret;
41c445ff
JB		 1961}
1962
1963/**
1964 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1965 * @netdev: network interface to be adjusted
1966 * @vid: vlan id to be removed
078b5876
JB		 1967 *
1968 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1969 **/
1970static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1971 __always_unused __be16 proto, u16 vid)
1972{
1973 struct i40e_netdev_priv *np = netdev_priv(netdev);
1974 struct i40e_vsi *vsi = np->vsi;
1975
078b5876
JB		 1976 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1977
41c445ff
JB		 1978 /* return code is ignored as there is nothing a user
1979 * can do about failure to remove and a log message was
078b5876 1980 * already printed from the other function
41c445ff
JB		 1981 */
1982 i40e_vsi_kill_vlan(vsi, vid);
1983
1984 clear_bit(vid, vsi->active_vlans);
078b5876 1985
41c445ff
JB		 1986 return 0;
1987}
1988
1989/**
1990 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
1991 * @vsi: the vsi being brought back up
1992 **/
1993static void i40e_restore_vlan(struct i40e_vsi *vsi)
1994{
1995 u16 vid;
1996
1997 if (!vsi->netdev)
1998 return;
1999
2000 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2001
2002 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2003 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2004 vid);
2005}
2006
2007/**
2008 * i40e_vsi_add_pvid - Add pvid for the VSI
2009 * @vsi: the vsi being adjusted
2010 * @vid: the vlan id to set as a PVID
2011 **/
dcae29be 2012int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2013{
2014 struct i40e_vsi_context ctxt;
dcae29be 2015 i40e_status aq_ret;
41c445ff
JB		 2016
2017 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2018 vsi->info.pvid = cpu_to_le16(vid);
2019 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
2020 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2021
2022 ctxt.seid = vsi->seid;
2023 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2024 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2025 if (aq_ret) {
41c445ff
JB		 2026 dev_info(&vsi->back->pdev->dev,
2027 "%s: update vsi failed, aq_err=%d\n",
2028 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2029 return -ENOENT;
41c445ff
JB		 2030 }
2031
dcae29be 2032 return 0;
41c445ff
JB		 2033}
2034
2035/**
2036 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2037 * @vsi: the vsi being adjusted
2038 *
2039 * Just use the vlan_rx_register() service to put it back to normal
2040 **/
2041void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2042{
2043 vsi->info.pvid = 0;
2044 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2045}
2046
2047/**
2048 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2049 * @vsi: ptr to the VSI
2050 *
2051 * If this function returns with an error, then it's possible one or
2052 * more of the rings is populated (while the rest are not). It is the
2053 * callers duty to clean those orphaned rings.
2054 *
2055 * Return 0 on success, negative on failure
2056 **/
2057static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2058{
2059 int i, err = 0;
2060
2061 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2062 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2063
2064 return err;
2065}
2066
2067/**
2068 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2069 * @vsi: ptr to the VSI
2070 *
2071 * Free VSI's transmit software resources
2072 **/
2073static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2074{
2075 int i;
2076
2077 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2078 if (vsi->tx_rings[i]->desc)
2079 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2080}
2081
2082/**
2083 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2084 * @vsi: ptr to the VSI
2085 *
2086 * If this function returns with an error, then it's possible one or
2087 * more of the rings is populated (while the rest are not). It is the
2088 * callers duty to clean those orphaned rings.
2089 *
2090 * Return 0 on success, negative on failure
2091 **/
2092static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2093{
2094 int i, err = 0;
2095
2096 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2097 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2098 return err;
2099}
2100
2101/**
2102 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2103 * @vsi: ptr to the VSI
2104 *
2105 * Free all receive software resources
2106 **/
2107static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2108{
2109 int i;
2110
2111 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2112 if (vsi->rx_rings[i]->desc)
2113 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2114}
2115
2116/**
2117 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2118 * @ring: The Tx ring to configure
2119 *
2120 * Configure the Tx descriptor ring in the HMC context.
2121 **/
2122static int i40e_configure_tx_ring(struct i40e_ring *ring)
2123{
2124 struct i40e_vsi *vsi = ring->vsi;
2125 u16 pf_q = vsi->base_queue + ring->queue_index;
2126 struct i40e_hw *hw = &vsi->back->hw;
2127 struct i40e_hmc_obj_txq tx_ctx;
2128 i40e_status err = 0;
2129 u32 qtx_ctl = 0;
2130
2131 /* some ATR related tx ring init */
2132 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2133 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2134 ring->atr_count = 0;
2135 } else {
2136 ring->atr_sample_rate = 0;
2137 }
2138
2139 /* initialize XPS */
2140 if (ring->q_vector && ring->netdev &&
2141 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2142 netif_set_xps_queue(ring->netdev,
2143 &ring->q_vector->affinity_mask,
2144 ring->queue_index);
2145
2146 /* clear the context structure first */
2147 memset(&tx_ctx, 0, sizeof(tx_ctx));
2148
2149 tx_ctx.new_context = 1;
2150 tx_ctx.base = (ring->dma / 128);
2151 tx_ctx.qlen = ring->count;
2152 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
2153 I40E_FLAG_FDIR_ATR_ENABLED));
2154
2155 /* As part of VSI creation/update, FW allocates certain
2156 * Tx arbitration queue sets for each TC enabled for
2157 * the VSI. The FW returns the handles to these queue
2158 * sets as part of the response buffer to Add VSI,
2159 * Update VSI, etc. AQ commands. It is expected that
2160 * these queue set handles be associated with the Tx
2161 * queues by the driver as part of the TX queue context
2162 * initialization. This has to be done regardless of
2163 * DCB as by default everything is mapped to TC0.
2164 */
2165 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2166 tx_ctx.rdylist_act = 0;
2167
2168 /* clear the context in the HMC */
2169 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2170 if (err) {
2171 dev_info(&vsi->back->pdev->dev,
2172 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2173 ring->queue_index, pf_q, err);
2174 return -ENOMEM;
2175 }
2176
2177 /* set the context in the HMC */
2178 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2179 if (err) {
2180 dev_info(&vsi->back->pdev->dev,
2181 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2182 ring->queue_index, pf_q, err);
2183 return -ENOMEM;
2184 }
2185
2186 /* Now associate this queue with this PCI function */
2187 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2188 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2189 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2190 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2191 i40e_flush(hw);
2192
2193 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2194
2195 /* cache tail off for easier writes later */
2196 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2197
2198 return 0;
2199}
2200
2201/**
2202 * i40e_configure_rx_ring - Configure a receive ring context
2203 * @ring: The Rx ring to configure
2204 *
2205 * Configure the Rx descriptor ring in the HMC context.
2206 **/
2207static int i40e_configure_rx_ring(struct i40e_ring *ring)
2208{
2209 struct i40e_vsi *vsi = ring->vsi;
2210 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2211 u16 pf_q = vsi->base_queue + ring->queue_index;
2212 struct i40e_hw *hw = &vsi->back->hw;
2213 struct i40e_hmc_obj_rxq rx_ctx;
2214 i40e_status err = 0;
2215
2216 ring->state = 0;
2217
2218 /* clear the context structure first */
2219 memset(&rx_ctx, 0, sizeof(rx_ctx));
2220
2221 ring->rx_buf_len = vsi->rx_buf_len;
2222 ring->rx_hdr_len = vsi->rx_hdr_len;
2223
2224 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2225 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2226
2227 rx_ctx.base = (ring->dma / 128);
2228 rx_ctx.qlen = ring->count;
2229
2230 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2231 set_ring_16byte_desc_enabled(ring);
2232 rx_ctx.dsize = 0;
2233 } else {
2234 rx_ctx.dsize = 1;
2235 }
2236
2237 rx_ctx.dtype = vsi->dtype;
2238 if (vsi->dtype) {
2239 set_ring_ps_enabled(ring);
2240 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2241 I40E_RX_SPLIT_IP |
2242 I40E_RX_SPLIT_TCP_UDP |
2243 I40E_RX_SPLIT_SCTP;
2244 } else {
2245 rx_ctx.hsplit_0 = 0;
2246 }
2247
2248 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2249 (chain_len * ring->rx_buf_len));
2250 rx_ctx.tphrdesc_ena = 1;
2251 rx_ctx.tphwdesc_ena = 1;
2252 rx_ctx.tphdata_ena = 1;
2253 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2254 if (hw->revision_id == 0)
2255 rx_ctx.lrxqthresh = 0;
2256 else
2257 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2258 rx_ctx.crcstrip = 1;
2259 rx_ctx.l2tsel = 1;
2260 rx_ctx.showiv = 1;
2261
2262 /* clear the context in the HMC */
2263 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2264 if (err) {
2265 dev_info(&vsi->back->pdev->dev,
2266 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2267 ring->queue_index, pf_q, err);
2268 return -ENOMEM;
2269 }
2270
2271 /* set the context in the HMC */
2272 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2273 if (err) {
2274 dev_info(&vsi->back->pdev->dev,
2275 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2276 ring->queue_index, pf_q, err);
2277 return -ENOMEM;
2278 }
2279
2280 /* cache tail for quicker writes, and clear the reg before use */
2281 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2282 writel(0, ring->tail);
2283
2284 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2285
2286 return 0;
2287}
2288
2289/**
2290 * i40e_vsi_configure_tx - Configure the VSI for Tx
2291 * @vsi: VSI structure describing this set of rings and resources
2292 *
2293 * Configure the Tx VSI for operation.
2294 **/
2295static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2296{
2297 int err = 0;
2298 u16 i;
2299
9f65e15b
AD		 2300 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2301 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2302
2303 return err;
2304}
2305
2306/**
2307 * i40e_vsi_configure_rx - Configure the VSI for Rx
2308 * @vsi: the VSI being configured
2309 *
2310 * Configure the Rx VSI for operation.
2311 **/
2312static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2313{
2314 int err = 0;
2315 u16 i;
2316
2317 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2318 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2319 + ETH_FCS_LEN + VLAN_HLEN;
2320 else
2321 vsi->max_frame = I40E_RXBUFFER_2048;
2322
2323 /* figure out correct receive buffer length */
2324 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2325 I40E_FLAG_RX_PS_ENABLED)) {
2326 case I40E_FLAG_RX_1BUF_ENABLED:
2327 vsi->rx_hdr_len = 0;
2328 vsi->rx_buf_len = vsi->max_frame;
2329 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2330 break;
2331 case I40E_FLAG_RX_PS_ENABLED:
2332 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2333 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2334 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2335 break;
2336 default:
2337 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2338 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2339 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2340 break;
2341 }
2342
2343 /* round up for the chip's needs */
2344 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2345 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2346 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2347 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2348
2349 /* set up individual rings */
2350 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2351 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2352
2353 return err;
2354}
2355
2356/**
2357 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2358 * @vsi: ptr to the VSI
2359 **/
2360static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2361{
2362 u16 qoffset, qcount;
2363 int i, n;
2364
2365 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2366 return;
2367
2368 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2369 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2370 continue;
2371
2372 qoffset = vsi->tc_config.tc_info[n].qoffset;
2373 qcount = vsi->tc_config.tc_info[n].qcount;
2374 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2375 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2376 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2377 rx_ring->dcb_tc = n;
2378 tx_ring->dcb_tc = n;
2379 }
2380 }
2381}
2382
2383/**
2384 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2385 * @vsi: ptr to the VSI
2386 **/
2387static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2388{
2389 if (vsi->netdev)
2390 i40e_set_rx_mode(vsi->netdev);
2391}
2392
2393/**
2394 * i40e_vsi_configure - Set up the VSI for action
2395 * @vsi: the VSI being configured
2396 **/
2397static int i40e_vsi_configure(struct i40e_vsi *vsi)
2398{
2399 int err;
2400
2401 i40e_set_vsi_rx_mode(vsi);
2402 i40e_restore_vlan(vsi);
2403 i40e_vsi_config_dcb_rings(vsi);
2404 err = i40e_vsi_configure_tx(vsi);
2405 if (!err)
2406 err = i40e_vsi_configure_rx(vsi);
2407
2408 return err;
2409}
2410
2411/**
2412 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2413 * @vsi: the VSI being configured
2414 **/
2415static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2416{
2417 struct i40e_pf *pf = vsi->back;
2418 struct i40e_q_vector *q_vector;
2419 struct i40e_hw *hw = &pf->hw;
2420 u16 vector;
2421 int i, q;
2422 u32 val;
2423 u32 qp;
2424
2425 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2426 * and PFINT_LNKLSTn registers, e.g.:
2427 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2428 */
2429 qp = vsi->base_queue;
2430 vector = vsi->base_vector;
493fb300
AD		 2431 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2432 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2433 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2434 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2435 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2436 q_vector->rx.itr);
2437 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2438 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2439 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2440 q_vector->tx.itr);
2441
2442 /* Linked list for the queuepairs assigned to this vector */
2443 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2444 for (q = 0; q < q_vector->num_ringpairs; q++) {
2445 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2446 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2447 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2448 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2449 (I40E_QUEUE_TYPE_TX
2450 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2451
2452 wr32(hw, I40E_QINT_RQCTL(qp), val);
2453
2454 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2455 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2456 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2457 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2458 (I40E_QUEUE_TYPE_RX
2459 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2460
2461 /* Terminate the linked list */
2462 if (q == (q_vector->num_ringpairs - 1))
2463 val |= (I40E_QUEUE_END_OF_LIST
2464 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2465
2466 wr32(hw, I40E_QINT_TQCTL(qp), val);
2467 qp++;
2468 }
2469 }
2470
2471 i40e_flush(hw);
2472}
2473
2474/**
2475 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2476 * @hw: ptr to the hardware info
2477 **/
2478static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2479{
2480 u32 val;
2481
2482 /* clear things first */
2483 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2484 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2485
2486 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2487 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2488 I40E_PFINT_ICR0_ENA_GRST_MASK |
2489 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2490 I40E_PFINT_ICR0_ENA_GPIO_MASK |
2491 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2492 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2493 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2494 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2495
2496 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2497
2498 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2499 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2500 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2501
2502 /* OTHER_ITR_IDX = 0 */
2503 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2504}
2505
2506/**
2507 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2508 * @vsi: the VSI being configured
2509 **/
2510static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2511{
493fb300 2512 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2513 struct i40e_pf *pf = vsi->back;
2514 struct i40e_hw *hw = &pf->hw;
2515 u32 val;
2516
2517 /* set the ITR configuration */
2518 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2519 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2520 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2521 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2522 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2523 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2524
2525 i40e_enable_misc_int_causes(hw);
2526
2527 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2528 wr32(hw, I40E_PFINT_LNKLST0, 0);
2529
2530 /* Associate the queue pair to the vector and enable the q int */
2531 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2532 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2533 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2534
2535 wr32(hw, I40E_QINT_RQCTL(0), val);
2536
2537 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2538 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2539 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2540
2541 wr32(hw, I40E_QINT_TQCTL(0), val);
2542 i40e_flush(hw);
2543}
2544
2545/**
2546 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2547 * @pf: board private structure
2548 **/
116a57d4 2549void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2550{
2551 struct i40e_hw *hw = &pf->hw;
2552 u32 val;
2553
2554 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2555 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2556 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2557
2558 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2559 i40e_flush(hw);
2560}
2561
2562/**
2563 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2564 * @vsi: pointer to a vsi
2565 * @vector: enable a particular Hw Interrupt vector
2566 **/
2567void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2568{
2569 struct i40e_pf *pf = vsi->back;
2570 struct i40e_hw *hw = &pf->hw;
2571 u32 val;
2572
2573 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2574 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2575 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2576 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2577 /* skip the flush */
41c445ff
JB		 2578}
2579
2580/**
2581 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2582 * @irq: interrupt number
2583 * @data: pointer to a q_vector
2584 **/
2585static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2586{
2587 struct i40e_q_vector *q_vector = data;
2588
cd0b6fa6 2589 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2590 return IRQ_HANDLED;
2591
2592 napi_schedule(&q_vector->napi);
2593
2594 return IRQ_HANDLED;
2595}
2596
2597/**
2598 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2599 * @irq: interrupt number
2600 * @data: pointer to a q_vector
2601 **/
2602static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2603{
2604 struct i40e_q_vector *q_vector = data;
2605
cd0b6fa6 2606 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2607 return IRQ_HANDLED;
2608
2609 pr_info("fdir ring cleaning needed\n");
2610
2611 return IRQ_HANDLED;
2612}
2613
2614/**
2615 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2616 * @vsi: the VSI being configured
2617 * @basename: name for the vector
2618 *
2619 * Allocates MSI-X vectors and requests interrupts from the kernel.
2620 **/
2621static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2622{
2623 int q_vectors = vsi->num_q_vectors;
2624 struct i40e_pf *pf = vsi->back;
2625 int base = vsi->base_vector;
2626 int rx_int_idx = 0;
2627 int tx_int_idx = 0;
2628 int vector, err;
2629
2630 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2631 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2632
cd0b6fa6 2633 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2634 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2635 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2636 tx_int_idx++;
cd0b6fa6 2637 } else if (q_vector->rx.ring) {
41c445ff
JB		 2638 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2639 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2640 } else if (q_vector->tx.ring) {
41c445ff
JB		 2641 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2642 "%s-%s-%d", basename, "tx", tx_int_idx++);
2643 } else {
2644 /* skip this unused q_vector */
2645 continue;
2646 }
2647 err = request_irq(pf->msix_entries[base + vector].vector,
2648 vsi->irq_handler,
2649 0,
2650 q_vector->name,
2651 q_vector);
2652 if (err) {
2653 dev_info(&pf->pdev->dev,
2654 "%s: request_irq failed, error: %d\n",
2655 __func__, err);
2656 goto free_queue_irqs;
2657 }
2658 /* assign the mask for this irq */
2659 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2660 &q_vector->affinity_mask);
2661 }
2662
2663 return 0;
2664
2665free_queue_irqs:
2666 while (vector) {
2667 vector--;
2668 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2669 NULL);
2670 free_irq(pf->msix_entries[base + vector].vector,
2671 &(vsi->q_vectors[vector]));
2672 }
2673 return err;
2674}
2675
2676/**
2677 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2678 * @vsi: the VSI being un-configured
2679 **/
2680static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2681{
2682 struct i40e_pf *pf = vsi->back;
2683 struct i40e_hw *hw = &pf->hw;
2684 int base = vsi->base_vector;
2685 int i;
2686
2687 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2688 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2689 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2690 }
2691
2692 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2693 for (i = vsi->base_vector;
2694 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2695 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2696
2697 i40e_flush(hw);
2698 for (i = 0; i < vsi->num_q_vectors; i++)
2699 synchronize_irq(pf->msix_entries[i + base].vector);
2700 } else {
2701 /* Legacy and MSI mode - this stops all interrupt handling */
2702 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2703 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2704 i40e_flush(hw);
2705 synchronize_irq(pf->pdev->irq);
2706 }
2707}
2708
2709/**
2710 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2711 * @vsi: the VSI being configured
2712 **/
2713static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2714{
2715 struct i40e_pf *pf = vsi->back;
2716 int i;
2717
2718 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2719 for (i = vsi->base_vector;
2720 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2721 i40e_irq_dynamic_enable(vsi, i);
2722 } else {
2723 i40e_irq_dynamic_enable_icr0(pf);
2724 }
2725
1022cb6c 2726 i40e_flush(&pf->hw);
41c445ff
JB		 2727 return 0;
2728}
2729
2730/**
2731 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2732 * @pf: board private structure
2733 **/
2734static void i40e_stop_misc_vector(struct i40e_pf *pf)
2735{
2736 /* Disable ICR 0 */
2737 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2738 i40e_flush(&pf->hw);
2739}
2740
2741/**
2742 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2743 * @irq: interrupt number
2744 * @data: pointer to a q_vector
2745 *
2746 * This is the handler used for all MSI/Legacy interrupts, and deals
2747 * with both queue and non-queue interrupts. This is also used in
2748 * MSIX mode to handle the non-queue interrupts.
2749 **/
2750static irqreturn_t i40e_intr(int irq, void *data)
2751{
2752 struct i40e_pf *pf = (struct i40e_pf *)data;
2753 struct i40e_hw *hw = &pf->hw;
2754 u32 icr0, icr0_remaining;
2755 u32 val, ena_mask;
2756
2757 icr0 = rd32(hw, I40E_PFINT_ICR0);
2758
41c445ff
JB		 2759 val = rd32(hw, I40E_PFINT_DYN_CTL0);
2760 val = val | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK;
2761 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2762
116a57d4
SN		 2763 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2764 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
2765 return IRQ_NONE;
2766
41c445ff
JB		 2767 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
2768
cd92e72f
SN		 2769 /* if interrupt but no bits showing, must be SWINT */
2770 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2771 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2772 pf->sw_int_count++;
2773
41c445ff
JB		 2774 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2775 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2776
2777 /* temporarily disable queue cause for NAPI processing */
2778 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2779 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2780 wr32(hw, I40E_QINT_RQCTL(0), qval);
2781
2782 qval = rd32(hw, I40E_QINT_TQCTL(0));
2783 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2784 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2785
2786 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2787 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2788 }
2789
2790 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2791 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2792 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2793 }
2794
2795 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2796 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2797 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2798 }
2799
2800 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2801 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2802 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2803 }
2804
2805 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2806 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2807 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2808 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2809 val = rd32(hw, I40E_GLGEN_RSTAT);
2810 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2811 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2812 if (val == I40E_RESET_CORER)
41c445ff 2813 pf->corer_count++;
d52cf0a9 2814 else if (val == I40E_RESET_GLOBR)
41c445ff 2815 pf->globr_count++;
d52cf0a9 2816 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2817 pf->empr_count++;
2818 }
2819
9c010ee0
ASJ		 2820 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2821 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2822 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2823 }
2824
41c445ff
JB		 2825 /* If a critical error is pending we have no choice but to reset the
2826 * device.
2827 * Report and mask out any remaining unexpected interrupts.
2828 */
2829 icr0_remaining = icr0 & ena_mask;
2830 if (icr0_remaining) {
2831 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2832 icr0_remaining);
9c010ee0 2833 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2834 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2835 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2836 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2837 dev_info(&pf->pdev->dev, "device will be reset\n");
2838 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2839 i40e_service_event_schedule(pf);
41c445ff
JB		 2840 }
2841 ena_mask &= ~icr0_remaining;
2842 }
2843
2844 /* re-enable interrupt causes */
2845 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2846 if (!test_bit(__I40E_DOWN, &pf->state)) {
2847 i40e_service_event_schedule(pf);
2848 i40e_irq_dynamic_enable_icr0(pf);
2849 }
2850
2851 return IRQ_HANDLED;
2852}
2853
2854/**
cd0b6fa6 2855 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2856 * @vsi: the VSI being configured
2857 * @v_idx: vector index
cd0b6fa6 2858 * @qp_idx: queue pair index
41c445ff 2859 **/
cd0b6fa6 2860static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2861{
493fb300 2862 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2863 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2864 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2865
2866 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2867 tx_ring->next = q_vector->tx.ring;
2868 q_vector->tx.ring = tx_ring;
41c445ff 2869 q_vector->tx.count++;
cd0b6fa6
AD		 2870
2871 rx_ring->q_vector = q_vector;
2872 rx_ring->next = q_vector->rx.ring;
2873 q_vector->rx.ring = rx_ring;
2874 q_vector->rx.count++;
41c445ff
JB		 2875}
2876
2877/**
2878 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2879 * @vsi: the VSI being configured
2880 *
2881 * This function maps descriptor rings to the queue-specific vectors
2882 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2883 * one vector per queue pair, but on a constrained vector budget, we
2884 * group the queue pairs as "efficiently" as possible.
2885 **/
2886static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2887{
2888 int qp_remaining = vsi->num_queue_pairs;
2889 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2890 int num_ringpairs;
41c445ff
JB		 2891 int v_start = 0;
2892 int qp_idx = 0;
2893
2894 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2895 * group them so there are multiple queues per vector.
2896 */
2897 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2898 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2899
2900 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2901
2902 q_vector->num_ringpairs = num_ringpairs;
2903
2904 q_vector->rx.count = 0;
2905 q_vector->tx.count = 0;
2906 q_vector->rx.ring = NULL;
2907 q_vector->tx.ring = NULL;
2908
2909 while (num_ringpairs--) {
2910 map_vector_to_qp(vsi, v_start, qp_idx);
2911 qp_idx++;
2912 qp_remaining--;
41c445ff
JB		 2913 }
2914 }
2915}
2916
2917/**
2918 * i40e_vsi_request_irq - Request IRQ from the OS
2919 * @vsi: the VSI being configured
2920 * @basename: name for the vector
2921 **/
2922static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2923{
2924 struct i40e_pf *pf = vsi->back;
2925 int err;
2926
2927 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2928 err = i40e_vsi_request_irq_msix(vsi, basename);
2929 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2930 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2931 pf->misc_int_name, pf);
2932 else
2933 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2934 pf->misc_int_name, pf);
2935
2936 if (err)
2937 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2938
2939 return err;
2940}
2941
2942#ifdef CONFIG_NET_POLL_CONTROLLER
2943/**
2944 * i40e_netpoll - A Polling 'interrupt'handler
2945 * @netdev: network interface device structure
2946 *
2947 * This is used by netconsole to send skbs without having to re-enable
2948 * interrupts. It's not called while the normal interrupt routine is executing.
2949 **/
2950static void i40e_netpoll(struct net_device *netdev)
2951{
2952 struct i40e_netdev_priv *np = netdev_priv(netdev);
2953 struct i40e_vsi *vsi = np->vsi;
2954 struct i40e_pf *pf = vsi->back;
2955 int i;
2956
2957 /* if interface is down do nothing */
2958 if (test_bit(__I40E_DOWN, &vsi->state))
2959 return;
2960
2961 pf->flags |= I40E_FLAG_IN_NETPOLL;
2962 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2963 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 2964 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 2965 } else {
2966 i40e_intr(pf->pdev->irq, netdev);
2967 }
2968 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
2969}
2970#endif
2971
2972/**
2973 * i40e_vsi_control_tx - Start or stop a VSI's rings
2974 * @vsi: the VSI being configured
2975 * @enable: start or stop the rings
2976 **/
2977static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
2978{
2979 struct i40e_pf *pf = vsi->back;
2980 struct i40e_hw *hw = &pf->hw;
2981 int i, j, pf_q;
2982 u32 tx_reg;
2983
2984 pf_q = vsi->base_queue;
2985 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
2986 j = 1000;
2987 do {
2988 usleep_range(1000, 2000);
2989 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
2990 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
2991 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
2992
fda972f6
MW		 2993 /* Skip if the queue is already in the requested state */
2994 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
2995 continue;
2996 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
2997 continue;
41c445ff
JB		 2998
2999 /* turn on/off the queue */
3000 if (enable)
3001 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3002 I40E_QTX_ENA_QENA_STAT_MASK;
3003 else
3004 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3005
3006 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3007
3008 /* wait for the change to finish */
3009 for (j = 0; j < 10; j++) {
3010 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3011 if (enable) {
3012 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3013 break;
3014 } else {
3015 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3016 break;
3017 }
3018
3019 udelay(10);
3020 }
3021 if (j >= 10) {
3022 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3023 pf_q, (enable ? "en" : "dis"));
3024 return -ETIMEDOUT;
3025 }
3026 }
3027
7134f9ce
JB		 3028 if (hw->revision_id == 0)
3029 mdelay(50);
3030
41c445ff
JB		 3031 return 0;
3032}
3033
3034/**
3035 * i40e_vsi_control_rx - Start or stop a VSI's rings
3036 * @vsi: the VSI being configured
3037 * @enable: start or stop the rings
3038 **/
3039static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3040{
3041 struct i40e_pf *pf = vsi->back;
3042 struct i40e_hw *hw = &pf->hw;
3043 int i, j, pf_q;
3044 u32 rx_reg;
3045
3046 pf_q = vsi->base_queue;
3047 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3048 j = 1000;
3049 do {
3050 usleep_range(1000, 2000);
3051 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3052 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3053 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3054
3055 if (enable) {
3056 /* is STAT set ? */
3057 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3058 continue;
3059 } else {
3060 /* is !STAT set ? */
3061 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3062 continue;
3063 }
3064
3065 /* turn on/off the queue */
3066 if (enable)
3067 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3068 I40E_QRX_ENA_QENA_STAT_MASK;
3069 else
3070 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3071 I40E_QRX_ENA_QENA_STAT_MASK);
3072 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3073
3074 /* wait for the change to finish */
3075 for (j = 0; j < 10; j++) {
3076 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3077
3078 if (enable) {
3079 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3080 break;
3081 } else {
3082 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3083 break;
3084 }
3085
3086 udelay(10);
3087 }
3088 if (j >= 10) {
3089 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3090 pf_q, (enable ? "en" : "dis"));
3091 return -ETIMEDOUT;
3092 }
3093 }
3094
3095 return 0;
3096}
3097
3098/**
3099 * i40e_vsi_control_rings - Start or stop a VSI's rings
3100 * @vsi: the VSI being configured
3101 * @enable: start or stop the rings
3102 **/
fc18eaa0 3103int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff
JB		 3104{
3105 int ret;
3106
3107 /* do rx first for enable and last for disable */
3108 if (request) {
3109 ret = i40e_vsi_control_rx(vsi, request);
3110 if (ret)
3111 return ret;
3112 ret = i40e_vsi_control_tx(vsi, request);
3113 } else {
3114 ret = i40e_vsi_control_tx(vsi, request);
3115 if (ret)
3116 return ret;
3117 ret = i40e_vsi_control_rx(vsi, request);
3118 }
3119
3120 return ret;
3121}
3122
3123/**
3124 * i40e_vsi_free_irq - Free the irq association with the OS
3125 * @vsi: the VSI being configured
3126 **/
3127static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3128{
3129 struct i40e_pf *pf = vsi->back;
3130 struct i40e_hw *hw = &pf->hw;
3131 int base = vsi->base_vector;
3132 u32 val, qp;
3133 int i;
3134
3135 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3136 if (!vsi->q_vectors)
3137 return;
3138
3139 for (i = 0; i < vsi->num_q_vectors; i++) {
3140 u16 vector = i + base;
3141
3142 /* free only the irqs that were actually requested */
493fb300 3143 if (vsi->q_vectors[i]->num_ringpairs == 0)
41c445ff
JB		 3144 continue;
3145
3146 /* clear the affinity_mask in the IRQ descriptor */
3147 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3148 NULL);
3149 free_irq(pf->msix_entries[vector].vector,
493fb300 3150 vsi->q_vectors[i]);
41c445ff
JB		 3151
3152 /* Tear down the interrupt queue link list
3153 *
3154 * We know that they come in pairs and always
3155 * the Rx first, then the Tx. To clear the
3156 * link list, stick the EOL value into the
3157 * next_q field of the registers.
3158 */
3159 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3160 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3161 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3162 val |= I40E_QUEUE_END_OF_LIST
3163 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3164 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3165
3166 while (qp != I40E_QUEUE_END_OF_LIST) {
3167 u32 next;
3168
3169 val = rd32(hw, I40E_QINT_RQCTL(qp));
3170
3171 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3172 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3173 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3174 I40E_QINT_RQCTL_INTEVENT_MASK);
3175
3176 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3177 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3178
3179 wr32(hw, I40E_QINT_RQCTL(qp), val);
3180
3181 val = rd32(hw, I40E_QINT_TQCTL(qp));
3182
3183 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3184 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3185
3186 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3187 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3188 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3189 I40E_QINT_TQCTL_INTEVENT_MASK);
3190
3191 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3192 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3193
3194 wr32(hw, I40E_QINT_TQCTL(qp), val);
3195 qp = next;
3196 }
3197 }
3198 } else {
3199 free_irq(pf->pdev->irq, pf);
3200
3201 val = rd32(hw, I40E_PFINT_LNKLST0);
3202 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3203 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3204 val |= I40E_QUEUE_END_OF_LIST
3205 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3206 wr32(hw, I40E_PFINT_LNKLST0, val);
3207
3208 val = rd32(hw, I40E_QINT_RQCTL(qp));
3209 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3210 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3211 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3212 I40E_QINT_RQCTL_INTEVENT_MASK);
3213
3214 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3215 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3216
3217 wr32(hw, I40E_QINT_RQCTL(qp), val);
3218
3219 val = rd32(hw, I40E_QINT_TQCTL(qp));
3220
3221 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3222 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3223 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3224 I40E_QINT_TQCTL_INTEVENT_MASK);
3225
3226 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3227 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3228
3229 wr32(hw, I40E_QINT_TQCTL(qp), val);
3230 }
3231}
3232
493fb300
AD		 3233/**
3234 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3235 * @vsi: the VSI being configured
3236 * @v_idx: Index of vector to be freed
3237 *
3238 * This function frees the memory allocated to the q_vector. In addition if
3239 * NAPI is enabled it will delete any references to the NAPI struct prior
3240 * to freeing the q_vector.
3241 **/
3242static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3243{
3244 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3245 struct i40e_ring *ring;
493fb300
AD		 3246
3247 if (!q_vector)
3248 return;
3249
3250 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3251 i40e_for_each_ring(ring, q_vector->tx)
3252 ring->q_vector = NULL;
3253
3254 i40e_for_each_ring(ring, q_vector->rx)
3255 ring->q_vector = NULL;
493fb300
AD		 3256
3257 /* only VSI w/ an associated netdev is set up w/ NAPI */
3258 if (vsi->netdev)
3259 netif_napi_del(&q_vector->napi);
3260
3261 vsi->q_vectors[v_idx] = NULL;
3262
3263 kfree_rcu(q_vector, rcu);
3264}
3265
41c445ff
JB		 3266/**
3267 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3268 * @vsi: the VSI being un-configured
3269 *
3270 * This frees the memory allocated to the q_vectors and
3271 * deletes references to the NAPI struct.
3272 **/
3273static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3274{
3275 int v_idx;
3276
493fb300
AD		 3277 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3278 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3279}
3280
3281/**
3282 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3283 * @pf: board private structure
3284 **/
3285static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3286{
3287 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3288 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3289 pci_disable_msix(pf->pdev);
3290 kfree(pf->msix_entries);
3291 pf->msix_entries = NULL;
3292 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3293 pci_disable_msi(pf->pdev);
3294 }
3295 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3296}
3297
3298/**
3299 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3300 * @pf: board private structure
3301 *
3302 * We go through and clear interrupt specific resources and reset the structure
3303 * to pre-load conditions
3304 **/
3305static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3306{
3307 int i;
3308
3309 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3310 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3311 if (pf->vsi[i])
3312 i40e_vsi_free_q_vectors(pf->vsi[i]);
3313 i40e_reset_interrupt_capability(pf);
3314}
3315
3316/**
3317 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3318 * @vsi: the VSI being configured
3319 **/
3320static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3321{
3322 int q_idx;
3323
3324 if (!vsi->netdev)
3325 return;
3326
3327 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3328 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3329}
3330
3331/**
3332 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3333 * @vsi: the VSI being configured
3334 **/
3335static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3336{
3337 int q_idx;
3338
3339 if (!vsi->netdev)
3340 return;
3341
3342 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3343 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3344}
3345
3346/**
3347 * i40e_quiesce_vsi - Pause a given VSI
3348 * @vsi: the VSI being paused
3349 **/
3350static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3351{
3352 if (test_bit(__I40E_DOWN, &vsi->state))
3353 return;
3354
3355 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3356 if (vsi->netdev && netif_running(vsi->netdev)) {
3357 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3358 } else {
3359 set_bit(__I40E_DOWN, &vsi->state);
3360 i40e_down(vsi);
3361 }
3362}
3363
3364/**
3365 * i40e_unquiesce_vsi - Resume a given VSI
3366 * @vsi: the VSI being resumed
3367 **/
3368static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3369{
3370 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3371 return;
3372
3373 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3374 if (vsi->netdev && netif_running(vsi->netdev))
3375 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3376 else
3377 i40e_up(vsi); /* this clears the DOWN bit */
3378}
3379
3380/**
3381 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3382 * @pf: the PF
3383 **/
3384static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3385{
3386 int v;
3387
3388 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3389 if (pf->vsi[v])
3390 i40e_quiesce_vsi(pf->vsi[v]);
3391 }
3392}
3393
3394/**
3395 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3396 * @pf: the PF
3397 **/
3398static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3399{
3400 int v;
3401
3402 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3403 if (pf->vsi[v])
3404 i40e_unquiesce_vsi(pf->vsi[v]);
3405 }
3406}
3407
3408/**
3409 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3410 * @dcbcfg: the corresponding DCBx configuration structure
3411 *
3412 * Return the number of TCs from given DCBx configuration
3413 **/
3414static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3415{
078b5876
JB		 3416 u8 num_tc = 0;
3417 int i;
41c445ff
JB		 3418
3419 /* Scan the ETS Config Priority Table to find
3420 * traffic class enabled for a given priority
3421 * and use the traffic class index to get the
3422 * number of traffic classes enabled
3423 */
3424 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3425 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3426 num_tc = dcbcfg->etscfg.prioritytable[i];
3427 }
3428
3429 /* Traffic class index starts from zero so
3430 * increment to return the actual count
3431 */
078b5876 3432 return num_tc + 1;
41c445ff
JB		 3433}
3434
3435/**
3436 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3437 * @dcbcfg: the corresponding DCBx configuration structure
3438 *
3439 * Query the current DCB configuration and return the number of
3440 * traffic classes enabled from the given DCBX config
3441 **/
3442static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3443{
3444 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3445 u8 enabled_tc = 1;
3446 u8 i;
3447
3448 for (i = 0; i < num_tc; i++)
3449 enabled_tc |= 1 << i;
3450
3451 return enabled_tc;
3452}
3453
3454/**
3455 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3456 * @pf: PF being queried
3457 *
3458 * Return number of traffic classes enabled for the given PF
3459 **/
3460static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3461{
3462 struct i40e_hw *hw = &pf->hw;
3463 u8 i, enabled_tc;
3464 u8 num_tc = 0;
3465 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3466
3467 /* If DCB is not enabled then always in single TC */
3468 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3469 return 1;
3470
3471 /* MFP mode return count of enabled TCs for this PF */
3472 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3473 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3474 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3475 if (enabled_tc & (1 << i))
3476 num_tc++;
3477 }
3478 return num_tc;
3479 }
3480
3481 /* SFP mode will be enabled for all TCs on port */
3482 return i40e_dcb_get_num_tc(dcbcfg);
3483}
3484
3485/**
3486 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3487 * @pf: PF being queried
3488 *
3489 * Return a bitmap for first enabled traffic class for this PF.
3490 **/
3491static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3492{
3493 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3494 u8 i = 0;
3495
3496 if (!enabled_tc)
3497 return 0x1; /* TC0 */
3498
3499 /* Find the first enabled TC */
3500 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3501 if (enabled_tc & (1 << i))
3502 break;
3503 }
3504
3505 return 1 << i;
3506}
3507
3508/**
3509 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3510 * @pf: PF being queried
3511 *
3512 * Return a bitmap for enabled traffic classes for this PF.
3513 **/
3514static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3515{
3516 /* If DCB is not enabled for this PF then just return default TC */
3517 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3518 return i40e_pf_get_default_tc(pf);
3519
3520 /* MFP mode will have enabled TCs set by FW */
3521 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3522 return pf->hw.func_caps.enabled_tcmap;
3523
3524 /* SFP mode we want PF to be enabled for all TCs */
3525 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3526}
3527
3528/**
3529 * i40e_vsi_get_bw_info - Query VSI BW Information
3530 * @vsi: the VSI being queried
3531 *
3532 * Returns 0 on success, negative value on failure
3533 **/
3534static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3535{
3536 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3537 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3538 struct i40e_pf *pf = vsi->back;
3539 struct i40e_hw *hw = &pf->hw;
dcae29be 3540 i40e_status aq_ret;
41c445ff 3541 u32 tc_bw_max;
41c445ff
JB		 3542 int i;
3543
3544 /* Get the VSI level BW configuration */
dcae29be
JB		 3545 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3546 if (aq_ret) {
41c445ff
JB		 3547 dev_info(&pf->pdev->dev,
3548 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3549 aq_ret, pf->hw.aq.asq_last_status);
3550 return -EINVAL;
41c445ff
JB		 3551 }
3552
3553 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3554 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3555 NULL);
3556 if (aq_ret) {
41c445ff
JB		 3557 dev_info(&pf->pdev->dev,
3558 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3559 aq_ret, pf->hw.aq.asq_last_status);
3560 return -EINVAL;
41c445ff
JB		 3561 }
3562
3563 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3564 dev_info(&pf->pdev->dev,
3565 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3566 bw_config.tc_valid_bits,
3567 bw_ets_config.tc_valid_bits);
3568 /* Still continuing */
3569 }
3570
3571 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3572 vsi->bw_max_quanta = bw_config.max_bw;
3573 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3574 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3575 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3576 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3577 vsi->bw_ets_limit_credits[i] =
3578 le16_to_cpu(bw_ets_config.credits[i]);
3579 /* 3 bits out of 4 for each TC */
3580 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3581 }
078b5876 3582
dcae29be 3583 return 0;
41c445ff
JB		 3584}
3585
3586/**
3587 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3588 * @vsi: the VSI being configured
3589 * @enabled_tc: TC bitmap
3590 * @bw_credits: BW shared credits per TC
3591 *
3592 * Returns 0 on success, negative value on failure
3593 **/
dcae29be 3594static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3595 u8 *bw_share)
3596{
3597 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3598 i40e_status aq_ret;
3599 int i;
41c445ff
JB		 3600
3601 bw_data.tc_valid_bits = enabled_tc;
3602 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3603 bw_data.tc_bw_credits[i] = bw_share[i];
3604
dcae29be
JB		 3605 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3606 NULL);
3607 if (aq_ret) {
41c445ff
JB		 3608 dev_info(&vsi->back->pdev->dev,
3609 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3610 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3611 return -EINVAL;
41c445ff
JB		 3612 }
3613
3614 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3615 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3616
dcae29be 3617 return 0;
41c445ff
JB		 3618}
3619
3620/**
3621 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3622 * @vsi: the VSI being configured
3623 * @enabled_tc: TC map to be enabled
3624 *
3625 **/
3626static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3627{
3628 struct net_device *netdev = vsi->netdev;
3629 struct i40e_pf *pf = vsi->back;
3630 struct i40e_hw *hw = &pf->hw;
3631 u8 netdev_tc = 0;
3632 int i;
3633 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3634
3635 if (!netdev)
3636 return;
3637
3638 if (!enabled_tc) {
3639 netdev_reset_tc(netdev);
3640 return;
3641 }
3642
3643 /* Set up actual enabled TCs on the VSI */
3644 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3645 return;
3646
3647 /* set per TC queues for the VSI */
3648 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3649 /* Only set TC queues for enabled tcs
3650 *
3651 * e.g. For a VSI that has TC0 and TC3 enabled the
3652 * enabled_tc bitmap would be 0x00001001; the driver
3653 * will set the numtc for netdev as 2 that will be
3654 * referenced by the netdev layer as TC 0 and 1.
3655 */
3656 if (vsi->tc_config.enabled_tc & (1 << i))
3657 netdev_set_tc_queue(netdev,
3658 vsi->tc_config.tc_info[i].netdev_tc,
3659 vsi->tc_config.tc_info[i].qcount,
3660 vsi->tc_config.tc_info[i].qoffset);
3661 }
3662
3663 /* Assign UP2TC map for the VSI */
3664 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3665 /* Get the actual TC# for the UP */
3666 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3667 /* Get the mapped netdev TC# for the UP */
3668 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3669 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3670 }
3671}
3672
3673/**
3674 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3675 * @vsi: the VSI being configured
3676 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3677 **/
3678static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3679 struct i40e_vsi_context *ctxt)
3680{
3681 /* copy just the sections touched not the entire info
3682 * since not all sections are valid as returned by
3683 * update vsi params
3684 */
3685 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3686 memcpy(&vsi->info.queue_mapping,
3687 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3688 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3689 sizeof(vsi->info.tc_mapping));
3690}
3691
3692/**
3693 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3694 * @vsi: VSI to be configured
3695 * @enabled_tc: TC bitmap
3696 *
3697 * This configures a particular VSI for TCs that are mapped to the
3698 * given TC bitmap. It uses default bandwidth share for TCs across
3699 * VSIs to configure TC for a particular VSI.
3700 *
3701 * NOTE:
3702 * It is expected that the VSI queues have been quisced before calling
3703 * this function.
3704 **/
3705static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3706{
3707 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3708 struct i40e_vsi_context ctxt;
3709 int ret = 0;
3710 int i;
3711
3712 /* Check if enabled_tc is same as existing or new TCs */
3713 if (vsi->tc_config.enabled_tc == enabled_tc)
3714 return ret;
3715
3716 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3717 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3718 if (enabled_tc & (1 << i))
3719 bw_share[i] = 1;
3720 }
3721
3722 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3723 if (ret) {
3724 dev_info(&vsi->back->pdev->dev,
3725 "Failed configuring TC map %d for VSI %d\n",
3726 enabled_tc, vsi->seid);
3727 goto out;
3728 }
3729
3730 /* Update Queue Pairs Mapping for currently enabled UPs */
3731 ctxt.seid = vsi->seid;
3732 ctxt.pf_num = vsi->back->hw.pf_id;
3733 ctxt.vf_num = 0;
3734 ctxt.uplink_seid = vsi->uplink_seid;
3735 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3736 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3737
3738 /* Update the VSI after updating the VSI queue-mapping information */
3739 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3740 if (ret) {
3741 dev_info(&vsi->back->pdev->dev,
3742 "update vsi failed, aq_err=%d\n",
3743 vsi->back->hw.aq.asq_last_status);
3744 goto out;
3745 }
3746 /* update the local VSI info with updated queue map */
3747 i40e_vsi_update_queue_map(vsi, &ctxt);
3748 vsi->info.valid_sections = 0;
3749
3750 /* Update current VSI BW information */
3751 ret = i40e_vsi_get_bw_info(vsi);
3752 if (ret) {
3753 dev_info(&vsi->back->pdev->dev,
3754 "Failed updating vsi bw info, aq_err=%d\n",
3755 vsi->back->hw.aq.asq_last_status);
3756 goto out;
3757 }
3758
3759 /* Update the netdev TC setup */
3760 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3761out:
3762 return ret;
3763}
3764
3765/**
3766 * i40e_up_complete - Finish the last steps of bringing up a connection
3767 * @vsi: the VSI being configured
3768 **/
3769static int i40e_up_complete(struct i40e_vsi *vsi)
3770{
3771 struct i40e_pf *pf = vsi->back;
3772 int err;
3773
3774 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3775 i40e_vsi_configure_msix(vsi);
3776 else
3777 i40e_configure_msi_and_legacy(vsi);
3778
3779 /* start rings */
3780 err = i40e_vsi_control_rings(vsi, true);
3781 if (err)
3782 return err;
3783
3784 clear_bit(__I40E_DOWN, &vsi->state);
3785 i40e_napi_enable_all(vsi);
3786 i40e_vsi_enable_irq(vsi);
3787
3788 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3789 (vsi->netdev)) {
6d779b41 3790 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3791 netif_tx_start_all_queues(vsi->netdev);
3792 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3793 } else if (vsi->netdev) {
3794 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3795 }
3796 i40e_service_event_schedule(pf);
3797
3798 return 0;
3799}
3800
3801/**
3802 * i40e_vsi_reinit_locked - Reset the VSI
3803 * @vsi: the VSI being configured
3804 *
3805 * Rebuild the ring structs after some configuration
3806 * has changed, e.g. MTU size.
3807 **/
3808static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3809{
3810 struct i40e_pf *pf = vsi->back;
3811
3812 WARN_ON(in_interrupt());
3813 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3814 usleep_range(1000, 2000);
3815 i40e_down(vsi);
3816
3817 /* Give a VF some time to respond to the reset. The
3818 * two second wait is based upon the watchdog cycle in
3819 * the VF driver.
3820 */
3821 if (vsi->type == I40E_VSI_SRIOV)
3822 msleep(2000);
3823 i40e_up(vsi);
3824 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3825}
3826
3827/**
3828 * i40e_up - Bring the connection back up after being down
3829 * @vsi: the VSI being configured
3830 **/
3831int i40e_up(struct i40e_vsi *vsi)
3832{
3833 int err;
3834
3835 err = i40e_vsi_configure(vsi);
3836 if (!err)
3837 err = i40e_up_complete(vsi);
3838
3839 return err;
3840}
3841
3842/**
3843 * i40e_down - Shutdown the connection processing
3844 * @vsi: the VSI being stopped
3845 **/
3846void i40e_down(struct i40e_vsi *vsi)
3847{
3848 int i;
3849
3850 /* It is assumed that the caller of this function
3851 * sets the vsi->state __I40E_DOWN bit.
3852 */
3853 if (vsi->netdev) {
3854 netif_carrier_off(vsi->netdev);
3855 netif_tx_disable(vsi->netdev);
3856 }
3857 i40e_vsi_disable_irq(vsi);
3858 i40e_vsi_control_rings(vsi, false);
3859 i40e_napi_disable_all(vsi);
3860
3861 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3862 i40e_clean_tx_ring(vsi->tx_rings[i]);
3863 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3864 }
3865}
3866
3867/**
3868 * i40e_setup_tc - configure multiple traffic classes
3869 * @netdev: net device to configure
3870 * @tc: number of traffic classes to enable
3871 **/
3872static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3873{
3874 struct i40e_netdev_priv *np = netdev_priv(netdev);
3875 struct i40e_vsi *vsi = np->vsi;
3876 struct i40e_pf *pf = vsi->back;
3877 u8 enabled_tc = 0;
3878 int ret = -EINVAL;
3879 int i;
3880
3881 /* Check if DCB enabled to continue */
3882 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3883 netdev_info(netdev, "DCB is not enabled for adapter\n");
3884 goto exit;
3885 }
3886
3887 /* Check if MFP enabled */
3888 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3889 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3890 goto exit;
3891 }
3892
3893 /* Check whether tc count is within enabled limit */
3894 if (tc > i40e_pf_get_num_tc(pf)) {
3895 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3896 goto exit;
3897 }
3898
3899 /* Generate TC map for number of tc requested */
3900 for (i = 0; i < tc; i++)
3901 enabled_tc |= (1 << i);
3902
3903 /* Requesting same TC configuration as already enabled */
3904 if (enabled_tc == vsi->tc_config.enabled_tc)
3905 return 0;
3906
3907 /* Quiesce VSI queues */
3908 i40e_quiesce_vsi(vsi);
3909
3910 /* Configure VSI for enabled TCs */
3911 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3912 if (ret) {
3913 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3914 vsi->seid);
3915 goto exit;
3916 }
3917
3918 /* Unquiesce VSI */
3919 i40e_unquiesce_vsi(vsi);
3920
3921exit:
3922 return ret;
3923}
3924
3925/**
3926 * i40e_open - Called when a network interface is made active
3927 * @netdev: network interface device structure
3928 *
3929 * The open entry point is called when a network interface is made
3930 * active by the system (IFF_UP). At this point all resources needed
3931 * for transmit and receive operations are allocated, the interrupt
3932 * handler is registered with the OS, the netdev watchdog subtask is
3933 * enabled, and the stack is notified that the interface is ready.
3934 *
3935 * Returns 0 on success, negative value on failure
3936 **/
3937static int i40e_open(struct net_device *netdev)
3938{
3939 struct i40e_netdev_priv *np = netdev_priv(netdev);
3940 struct i40e_vsi *vsi = np->vsi;
3941 struct i40e_pf *pf = vsi->back;
3942 char int_name[IFNAMSIZ];
3943 int err;
3944
3945 /* disallow open during test */
3946 if (test_bit(__I40E_TESTING, &pf->state))
3947 return -EBUSY;
3948
3949 netif_carrier_off(netdev);
3950
3951 /* allocate descriptors */
3952 err = i40e_vsi_setup_tx_resources(vsi);
3953 if (err)
3954 goto err_setup_tx;
3955 err = i40e_vsi_setup_rx_resources(vsi);
3956 if (err)
3957 goto err_setup_rx;
3958
3959 err = i40e_vsi_configure(vsi);
3960 if (err)
3961 goto err_setup_rx;
3962
3963 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
3964 dev_driver_string(&pf->pdev->dev), netdev->name);
3965 err = i40e_vsi_request_irq(vsi, int_name);
3966 if (err)
3967 goto err_setup_rx;
3968
25946ddb
ASJ		 3969 /* Notify the stack of the actual queue counts. */
3970 err = netif_set_real_num_tx_queues(netdev, pf->num_tx_queues);
3971 if (err)
3972 goto err_set_queues;
3973
3974 err = netif_set_real_num_rx_queues(netdev, pf->num_rx_queues);
3975 if (err)
3976 goto err_set_queues;
3977
41c445ff
JB		 3978 err = i40e_up_complete(vsi);
3979 if (err)
3980 goto err_up_complete;
3981
3982 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
3983 err = i40e_aq_set_vsi_broadcast(&pf->hw, vsi->seid, true, NULL);
3984 if (err)
3985 netdev_info(netdev,
3986 "couldn't set broadcast err %d aq_err %d\n",
3987 err, pf->hw.aq.asq_last_status);
3988 }
a1c9a9d9
JK		 3989#ifdef CONFIG_I40E_VXLAN
3990 vxlan_get_rx_port(netdev);
3991#endif
41c445ff
JB		 3992
3993 return 0;
3994
3995err_up_complete:
3996 i40e_down(vsi);
25946ddb 3997err_set_queues:
41c445ff
JB		 3998 i40e_vsi_free_irq(vsi);
3999err_setup_rx:
4000 i40e_vsi_free_rx_resources(vsi);
4001err_setup_tx:
4002 i40e_vsi_free_tx_resources(vsi);
4003 if (vsi == pf->vsi[pf->lan_vsi])
4004 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4005
4006 return err;
4007}
4008
4009/**
4010 * i40e_close - Disables a network interface
4011 * @netdev: network interface device structure
4012 *
4013 * The close entry point is called when an interface is de-activated
4014 * by the OS. The hardware is still under the driver's control, but
4015 * this netdev interface is disabled.
4016 *
4017 * Returns 0, this is not allowed to fail
4018 **/
4019static int i40e_close(struct net_device *netdev)
4020{
4021 struct i40e_netdev_priv *np = netdev_priv(netdev);
4022 struct i40e_vsi *vsi = np->vsi;
4023
4024 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4025 return 0;
4026
4027 i40e_down(vsi);
4028 i40e_vsi_free_irq(vsi);
4029
4030 i40e_vsi_free_tx_resources(vsi);
4031 i40e_vsi_free_rx_resources(vsi);
4032
4033 return 0;
4034}
4035
4036/**
4037 * i40e_do_reset - Start a PF or Core Reset sequence
4038 * @pf: board private structure
4039 * @reset_flags: which reset is requested
4040 *
4041 * The essential difference in resets is that the PF Reset
4042 * doesn't clear the packet buffers, doesn't reset the PE
4043 * firmware, and doesn't bother the other PFs on the chip.
4044 **/
4045void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4046{
4047 u32 val;
4048
4049 WARN_ON(in_interrupt());
4050
4051 /* do the biggest reset indicated */
4052 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4053
4054 /* Request a Global Reset
4055 *
4056 * This will start the chip's countdown to the actual full
4057 * chip reset event, and a warning interrupt to be sent
4058 * to all PFs, including the requestor. Our handler
4059 * for the warning interrupt will deal with the shutdown
4060 * and recovery of the switch setup.
4061 */
4062 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4063 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4064 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4065 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4066
4067 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4068
4069 /* Request a Core Reset
4070 *
4071 * Same as Global Reset, except does *not* include the MAC/PHY
4072 */
4073 dev_info(&pf->pdev->dev, "CoreR requested\n");
4074 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4075 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4076 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4077 i40e_flush(&pf->hw);
4078
7823fe34
SN		 4079 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4080
4081 /* Request a Firmware Reset
4082 *
4083 * Same as Global reset, plus restarting the
4084 * embedded firmware engine.
4085 */
4086 /* enable EMP Reset */
4087 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4088 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4089 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4090
4091 /* force the reset */
4092 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4093 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4094 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4095 i40e_flush(&pf->hw);
4096
41c445ff
JB		 4097 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4098
4099 /* Request a PF Reset
4100 *
4101 * Resets only the PF-specific registers
4102 *
4103 * This goes directly to the tear-down and rebuild of
4104 * the switch, since we need to do all the recovery as
4105 * for the Core Reset.
4106 */
4107 dev_info(&pf->pdev->dev, "PFR requested\n");
4108 i40e_handle_reset_warning(pf);
4109
4110 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4111 int v;
4112
4113 /* Find the VSI(s) that requested a re-init */
4114 dev_info(&pf->pdev->dev,
4115 "VSI reinit requested\n");
4116 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4117 struct i40e_vsi *vsi = pf->vsi[v];
4118 if (vsi != NULL &&
4119 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4120 i40e_vsi_reinit_locked(pf->vsi[v]);
4121 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4122 }
4123 }
4124
4125 /* no further action needed, so return now */
4126 return;
4127 } else {
4128 dev_info(&pf->pdev->dev,
4129 "bad reset request 0x%08x\n", reset_flags);
4130 return;
4131 }
4132}
4133
23326186
ASJ		 4134/**
4135 * i40e_do_reset_safe - Protected reset path for userland calls.
4136 * @pf: board private structure
4137 * @reset_flags: which reset is requested
4138 *
4139 **/
4140void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4141{
4142 rtnl_lock();
4143 i40e_do_reset(pf, reset_flags);
4144 rtnl_unlock();
4145}
4146
41c445ff
JB		 4147/**
4148 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4149 * @pf: board private structure
4150 * @e: event info posted on ARQ
4151 *
4152 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4153 * and VF queues
4154 **/
4155static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4156 struct i40e_arq_event_info *e)
4157{
4158 struct i40e_aqc_lan_overflow *data =
4159 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4160 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4161 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4162 struct i40e_hw *hw = &pf->hw;
4163 struct i40e_vf *vf;
4164 u16 vf_id;
4165
4166 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4167 __func__, queue, qtx_ctl);
4168
4169 /* Queue belongs to VF, find the VF and issue VF reset */
4170 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4171 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4172 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4173 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4174 vf_id -= hw->func_caps.vf_base_id;
4175 vf = &pf->vf[vf_id];
4176 i40e_vc_notify_vf_reset(vf);
4177 /* Allow VF to process pending reset notification */
4178 msleep(20);
4179 i40e_reset_vf(vf, false);
4180 }
4181}
4182
4183/**
4184 * i40e_service_event_complete - Finish up the service event
4185 * @pf: board private structure
4186 **/
4187static void i40e_service_event_complete(struct i40e_pf *pf)
4188{
4189 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4190
4191 /* flush memory to make sure state is correct before next watchog */
4192 smp_mb__before_clear_bit();
4193 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4194}
4195
4196/**
4197 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4198 * @pf: board private structure
4199 **/
4200static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4201{
4202 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4203 return;
4204
4205 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4206
4207 /* if interface is down do nothing */
4208 if (test_bit(__I40E_DOWN, &pf->state))
4209 return;
4210}
4211
4212/**
4213 * i40e_vsi_link_event - notify VSI of a link event
4214 * @vsi: vsi to be notified
4215 * @link_up: link up or down
4216 **/
4217static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4218{
4219 if (!vsi)
4220 return;
4221
4222 switch (vsi->type) {
4223 case I40E_VSI_MAIN:
4224 if (!vsi->netdev || !vsi->netdev_registered)
4225 break;
4226
4227 if (link_up) {
4228 netif_carrier_on(vsi->netdev);
4229 netif_tx_wake_all_queues(vsi->netdev);
4230 } else {
4231 netif_carrier_off(vsi->netdev);
4232 netif_tx_stop_all_queues(vsi->netdev);
4233 }
4234 break;
4235
4236 case I40E_VSI_SRIOV:
4237 break;
4238
4239 case I40E_VSI_VMDQ2:
4240 case I40E_VSI_CTRL:
4241 case I40E_VSI_MIRROR:
4242 default:
4243 /* there is no notification for other VSIs */
4244 break;
4245 }
4246}
4247
4248/**
4249 * i40e_veb_link_event - notify elements on the veb of a link event
4250 * @veb: veb to be notified
4251 * @link_up: link up or down
4252 **/
4253static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4254{
4255 struct i40e_pf *pf;
4256 int i;
4257
4258 if (!veb || !veb->pf)
4259 return;
4260 pf = veb->pf;
4261
4262 /* depth first... */
4263 for (i = 0; i < I40E_MAX_VEB; i++)
4264 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4265 i40e_veb_link_event(pf->veb[i], link_up);
4266
4267 /* ... now the local VSIs */
4268 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4269 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4270 i40e_vsi_link_event(pf->vsi[i], link_up);
4271}
4272
4273/**
4274 * i40e_link_event - Update netif_carrier status
4275 * @pf: board private structure
4276 **/
4277static void i40e_link_event(struct i40e_pf *pf)
4278{
4279 bool new_link, old_link;
4280
4281 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4282 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4283
4284 if (new_link == old_link)
4285 return;
4286
6d779b41
AS		 4287 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4288 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4289 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4290
4291 /* Notify the base of the switch tree connected to
4292 * the link. Floating VEBs are not notified.
4293 */
4294 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4295 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4296 else
4297 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4298
4299 if (pf->vf)
4300 i40e_vc_notify_link_state(pf);
4301}
4302
4303/**
4304 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4305 * @pf: board private structure
4306 *
4307 * Set the per-queue flags to request a check for stuck queues in the irq
4308 * clean functions, then force interrupts to be sure the irq clean is called.
4309 **/
4310static void i40e_check_hang_subtask(struct i40e_pf *pf)
4311{
4312 int i, v;
4313
4314 /* If we're down or resetting, just bail */
4315 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4316 return;
4317
4318 /* for each VSI/netdev
4319 * for each Tx queue
4320 * set the check flag
4321 * for each q_vector
4322 * force an interrupt
4323 */
4324 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4325 struct i40e_vsi *vsi = pf->vsi[v];
4326 int armed = 0;
4327
4328 if (!pf->vsi[v] ||
4329 test_bit(__I40E_DOWN, &vsi->state) ||
4330 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4331 continue;
4332
4333 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4334 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4335 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4336 &vsi->tx_rings[i]->state))
41c445ff
JB		 4337 armed++;
4338 }
4339
4340 if (armed) {
4341 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4342 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4343 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4344 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4345 } else {
4346 u16 vec = vsi->base_vector - 1;
4347 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4348 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4349 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4350 wr32(&vsi->back->hw,
4351 I40E_PFINT_DYN_CTLN(vec), val);
4352 }
4353 i40e_flush(&vsi->back->hw);
4354 }
4355 }
4356}
4357
4358/**
4359 * i40e_watchdog_subtask - Check and bring link up
4360 * @pf: board private structure
4361 **/
4362static void i40e_watchdog_subtask(struct i40e_pf *pf)
4363{
4364 int i;
4365
4366 /* if interface is down do nothing */
4367 if (test_bit(__I40E_DOWN, &pf->state) ||
4368 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4369 return;
4370
4371 /* Update the stats for active netdevs so the network stack
4372 * can look at updated numbers whenever it cares to
4373 */
4374 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4375 if (pf->vsi[i] && pf->vsi[i]->netdev)
4376 i40e_update_stats(pf->vsi[i]);
4377
4378 /* Update the stats for the active switching components */
4379 for (i = 0; i < I40E_MAX_VEB; i++)
4380 if (pf->veb[i])
4381 i40e_update_veb_stats(pf->veb[i]);
4382}
4383
4384/**
4385 * i40e_reset_subtask - Set up for resetting the device and driver
4386 * @pf: board private structure
4387 **/
4388static void i40e_reset_subtask(struct i40e_pf *pf)
4389{
4390 u32 reset_flags = 0;
4391
23326186 4392 rtnl_lock();
41c445ff
JB		 4393 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4394 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4395 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4396 }
4397 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4398 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4399 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4400 }
4401 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4402 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4403 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4404 }
4405 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4406 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4407 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4408 }
4409
4410 /* If there's a recovery already waiting, it takes
4411 * precedence before starting a new reset sequence.
4412 */
4413 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4414 i40e_handle_reset_warning(pf);
23326186 4415 goto unlock;
41c445ff
JB		 4416 }
4417
4418 /* If we're already down or resetting, just bail */
4419 if (reset_flags &&
4420 !test_bit(__I40E_DOWN, &pf->state) &&
4421 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4422 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4423
4424unlock:
4425 rtnl_unlock();
41c445ff
JB		 4426}
4427
4428/**
4429 * i40e_handle_link_event - Handle link event
4430 * @pf: board private structure
4431 * @e: event info posted on ARQ
4432 **/
4433static void i40e_handle_link_event(struct i40e_pf *pf,
4434 struct i40e_arq_event_info *e)
4435{
4436 struct i40e_hw *hw = &pf->hw;
4437 struct i40e_aqc_get_link_status *status =
4438 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4439 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4440
4441 /* save off old link status information */
4442 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4443 sizeof(pf->hw.phy.link_info_old));
4444
4445 /* update link status */
4446 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4447 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4448 hw_link_info->link_info = status->link_info;
4449 hw_link_info->an_info = status->an_info;
4450 hw_link_info->ext_info = status->ext_info;
4451 hw_link_info->lse_enable =
4452 le16_to_cpu(status->command_flags) &
4453 I40E_AQ_LSE_ENABLE;
4454
4455 /* process the event */
4456 i40e_link_event(pf);
4457
4458 /* Do a new status request to re-enable LSE reporting
4459 * and load new status information into the hw struct,
4460 * then see if the status changed while processing the
4461 * initial event.
4462 */
4463 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4464 i40e_link_event(pf);
4465}
4466
4467/**
4468 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4469 * @pf: board private structure
4470 **/
4471static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4472{
4473 struct i40e_arq_event_info event;
4474 struct i40e_hw *hw = &pf->hw;
4475 u16 pending, i = 0;
4476 i40e_status ret;
4477 u16 opcode;
4478 u32 val;
4479
4480 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4481 return;
4482
4483 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
4484 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4485 if (!event.msg_buf)
4486 return;
4487
4488 do {
4489 ret = i40e_clean_arq_element(hw, &event, &pending);
4490 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4491 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4492 break;
4493 } else if (ret) {
4494 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4495 break;
4496 }
4497
4498 opcode = le16_to_cpu(event.desc.opcode);
4499 switch (opcode) {
4500
4501 case i40e_aqc_opc_get_link_status:
4502 i40e_handle_link_event(pf, &event);
4503 break;
4504 case i40e_aqc_opc_send_msg_to_pf:
4505 ret = i40e_vc_process_vf_msg(pf,
4506 le16_to_cpu(event.desc.retval),
4507 le32_to_cpu(event.desc.cookie_high),
4508 le32_to_cpu(event.desc.cookie_low),
4509 event.msg_buf,
4510 event.msg_size);
4511 break;
4512 case i40e_aqc_opc_lldp_update_mib:
4513 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4514 break;
4515 case i40e_aqc_opc_event_lan_overflow:
4516 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4517 i40e_handle_lan_overflow_event(pf, &event);
4518 break;
4519 default:
4520 dev_info(&pf->pdev->dev,
4521 "ARQ Error: Unknown event %d received\n",
4522 event.desc.opcode);
4523 break;
4524 }
4525 } while (pending && (i++ < pf->adminq_work_limit));
4526
4527 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4528 /* re-enable Admin queue interrupt cause */
4529 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4530 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4531 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4532 i40e_flush(hw);
4533
4534 kfree(event.msg_buf);
4535}
4536
4537/**
4538 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4539 * @veb: pointer to the VEB instance
4540 *
4541 * This is a recursive function that first builds the attached VSIs then
4542 * recurses in to build the next layer of VEB. We track the connections
4543 * through our own index numbers because the seid's from the HW could
4544 * change across the reset.
4545 **/
4546static int i40e_reconstitute_veb(struct i40e_veb *veb)
4547{
4548 struct i40e_vsi *ctl_vsi = NULL;
4549 struct i40e_pf *pf = veb->pf;
4550 int v, veb_idx;
4551 int ret;
4552
4553 /* build VSI that owns this VEB, temporarily attached to base VEB */
4554 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4555 if (pf->vsi[v] &&
4556 pf->vsi[v]->veb_idx == veb->idx &&
4557 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4558 ctl_vsi = pf->vsi[v];
4559 break;
4560 }
4561 }
4562 if (!ctl_vsi) {
4563 dev_info(&pf->pdev->dev,
4564 "missing owner VSI for veb_idx %d\n", veb->idx);
4565 ret = -ENOENT;
4566 goto end_reconstitute;
4567 }
4568 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4569 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4570 ret = i40e_add_vsi(ctl_vsi);
4571 if (ret) {
4572 dev_info(&pf->pdev->dev,
4573 "rebuild of owner VSI failed: %d\n", ret);
4574 goto end_reconstitute;
4575 }
4576 i40e_vsi_reset_stats(ctl_vsi);
4577
4578 /* create the VEB in the switch and move the VSI onto the VEB */
4579 ret = i40e_add_veb(veb, ctl_vsi);
4580 if (ret)
4581 goto end_reconstitute;
4582
4583 /* create the remaining VSIs attached to this VEB */
4584 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4585 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4586 continue;
4587
4588 if (pf->vsi[v]->veb_idx == veb->idx) {
4589 struct i40e_vsi *vsi = pf->vsi[v];
4590 vsi->uplink_seid = veb->seid;
4591 ret = i40e_add_vsi(vsi);
4592 if (ret) {
4593 dev_info(&pf->pdev->dev,
4594 "rebuild of vsi_idx %d failed: %d\n",
4595 v, ret);
4596 goto end_reconstitute;
4597 }
4598 i40e_vsi_reset_stats(vsi);
4599 }
4600 }
4601
4602 /* create any VEBs attached to this VEB - RECURSION */
4603 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4604 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4605 pf->veb[veb_idx]->uplink_seid = veb->seid;
4606 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4607 if (ret)
4608 break;
4609 }
4610 }
4611
4612end_reconstitute:
4613 return ret;
4614}
4615
4616/**
4617 * i40e_get_capabilities - get info about the HW
4618 * @pf: the PF struct
4619 **/
4620static int i40e_get_capabilities(struct i40e_pf *pf)
4621{
4622 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4623 u16 data_size;
4624 int buf_len;
4625 int err;
4626
4627 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4628 do {
4629 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4630 if (!cap_buf)
4631 return -ENOMEM;
4632
4633 /* this loads the data into the hw struct for us */
4634 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4635 &data_size,
4636 i40e_aqc_opc_list_func_capabilities,
4637 NULL);
4638 /* data loaded, buffer no longer needed */
4639 kfree(cap_buf);
4640
4641 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4642 /* retry with a larger buffer */
4643 buf_len = data_size;
4644 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4645 dev_info(&pf->pdev->dev,
4646 "capability discovery failed: aq=%d\n",
4647 pf->hw.aq.asq_last_status);
4648 return -ENODEV;
4649 }
4650 } while (err);
4651
7134f9ce
JB		 4652 if (pf->hw.revision_id == 0 && pf->hw.func_caps.npar_enable) {
4653 pf->hw.func_caps.num_msix_vectors += 1;
4654 pf->hw.func_caps.num_tx_qp =
4655 min_t(int, pf->hw.func_caps.num_tx_qp,
4656 I40E_MAX_NPAR_QPS);
4657 }
4658
41c445ff
JB		 4659 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4660 dev_info(&pf->pdev->dev,
4661 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4662 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4663 pf->hw.func_caps.num_msix_vectors,
4664 pf->hw.func_caps.num_msix_vectors_vf,
4665 pf->hw.func_caps.fd_filters_guaranteed,
4666 pf->hw.func_caps.fd_filters_best_effort,
4667 pf->hw.func_caps.num_tx_qp,
4668 pf->hw.func_caps.num_vsis);
4669
7134f9ce
JB		 4670#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4671 + pf->hw.func_caps.num_vfs)
4672 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4673 dev_info(&pf->pdev->dev,
4674 "got num_vsis %d, setting num_vsis to %d\n",
4675 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4676 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4677 }
4678
41c445ff
JB		 4679 return 0;
4680}
4681
4682/**
4683 * i40e_fdir_setup - initialize the Flow Director resources
4684 * @pf: board private structure
4685 **/
4686static void i40e_fdir_setup(struct i40e_pf *pf)
4687{
4688 struct i40e_vsi *vsi;
4689 bool new_vsi = false;
4690 int err, i;
4691
958a3e3b
SN		 4692 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4693 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4694 return;
4695
4696 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4697
4698 /* find existing or make new FDIR VSI */
4699 vsi = NULL;
4700 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4701 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4702 vsi = pf->vsi[i];
4703 if (!vsi) {
4704 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4705 if (!vsi) {
4706 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4707 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4708 return;
4709 }
4710 new_vsi = true;
4711 }
4712 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4713 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4714
4715 err = i40e_vsi_setup_tx_resources(vsi);
4716 if (!err)
4717 err = i40e_vsi_setup_rx_resources(vsi);
4718 if (!err)
4719 err = i40e_vsi_configure(vsi);
4720 if (!err && new_vsi) {
4721 char int_name[IFNAMSIZ + 9];
4722 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4723 dev_driver_string(&pf->pdev->dev));
4724 err = i40e_vsi_request_irq(vsi, int_name);
4725 }
4726 if (!err)
4727 err = i40e_up_complete(vsi);
4728
4729 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4730}
4731
4732/**
4733 * i40e_fdir_teardown - release the Flow Director resources
4734 * @pf: board private structure
4735 **/
4736static void i40e_fdir_teardown(struct i40e_pf *pf)
4737{
4738 int i;
4739
4740 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4741 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4742 i40e_vsi_release(pf->vsi[i]);
4743 break;
4744 }
4745 }
4746}
4747
4748/**
f650a38b 4749 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4750 * @pf: board private structure
4751 *
f650a38b
ASJ		 4752 * Close up the VFs and other things in prep for pf Reset.
4753 **/
4754static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4755{
41c445ff
JB		 4756 struct i40e_hw *hw = &pf->hw;
4757 i40e_status ret;
4758 u32 v;
4759
4760 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4761 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4762 return 0;
41c445ff
JB		 4763
4764 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4765
4766 i40e_vc_notify_reset(pf);
4767
4768 /* quiesce the VSIs and their queues that are not already DOWN */
4769 i40e_pf_quiesce_all_vsi(pf);
4770
4771 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4772 if (pf->vsi[v])
4773 pf->vsi[v]->seid = 0;
4774 }
4775
4776 i40e_shutdown_adminq(&pf->hw);
4777
f650a38b
ASJ		 4778 /* call shutdown HMC */
4779 ret = i40e_shutdown_lan_hmc(hw);
4780 if (ret) {
4781 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4782 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4783 }
4784 return ret;
4785}
4786
4787/**
4788 * i40e_reset_and_rebuild - reset and rebuid using a saved config
4789 * @pf: board private structure
bc7d338f 4790 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4791 **/
bc7d338f 4792static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4793{
4794 struct i40e_driver_version dv;
4795 struct i40e_hw *hw = &pf->hw;
4796 i40e_status ret;
4797 u32 v;
4798
41c445ff
JB		 4799 /* Now we wait for GRST to settle out.
4800 * We don't have to delete the VEBs or VSIs from the hw switch
4801 * because the reset will make them disappear.
4802 */
4803 ret = i40e_pf_reset(hw);
4804 if (ret)
4805 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4806 pf->pfr_count++;
4807
4808 if (test_bit(__I40E_DOWN, &pf->state))
4809 goto end_core_reset;
4810 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4811
4812 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4813 ret = i40e_init_adminq(&pf->hw);
4814 if (ret) {
4815 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4816 goto end_core_reset;
4817 }
4818
4819 ret = i40e_get_capabilities(pf);
4820 if (ret) {
4821 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4822 ret);
4823 goto end_core_reset;
4824 }
4825
41c445ff
JB		 4826 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4827 hw->func_caps.num_rx_qp,
4828 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4829 if (ret) {
4830 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4831 goto end_core_reset;
4832 }
4833 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4834 if (ret) {
4835 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4836 goto end_core_reset;
4837 }
4838
4839 /* do basic switch setup */
bc7d338f 4840 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4841 if (ret)
4842 goto end_core_reset;
4843
4844 /* Rebuild the VSIs and VEBs that existed before reset.
4845 * They are still in our local switch element arrays, so only
4846 * need to rebuild the switch model in the HW.
4847 *
4848 * If there were VEBs but the reconstitution failed, we'll try
4849 * try to recover minimal use by getting the basic PF VSI working.
4850 */
4851 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4852 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4853 /* find the one VEB connected to the MAC, and find orphans */
4854 for (v = 0; v < I40E_MAX_VEB; v++) {
4855 if (!pf->veb[v])
4856 continue;
4857
4858 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4859 pf->veb[v]->uplink_seid == 0) {
4860 ret = i40e_reconstitute_veb(pf->veb[v]);
4861
4862 if (!ret)
4863 continue;
4864
4865 /* If Main VEB failed, we're in deep doodoo,
4866 * so give up rebuilding the switch and set up
4867 * for minimal rebuild of PF VSI.
4868 * If orphan failed, we'll report the error
4869 * but try to keep going.
4870 */
4871 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4872 dev_info(&pf->pdev->dev,
4873 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4874 ret);
4875 pf->vsi[pf->lan_vsi]->uplink_seid
4876 = pf->mac_seid;
4877 break;
4878 } else if (pf->veb[v]->uplink_seid == 0) {
4879 dev_info(&pf->pdev->dev,
4880 "rebuild of orphan VEB failed: %d\n",
4881 ret);
4882 }
4883 }
4884 }
4885 }
4886
4887 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4888 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4889 /* no VEB, so rebuild only the Main VSI */
4890 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4891 if (ret) {
4892 dev_info(&pf->pdev->dev,
4893 "rebuild of Main VSI failed: %d\n", ret);
4894 goto end_core_reset;
4895 }
4896 }
4897
4898 /* reinit the misc interrupt */
4899 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4900 ret = i40e_setup_misc_vector(pf);
4901
4902 /* restart the VSIs that were rebuilt and running before the reset */
4903 i40e_pf_unquiesce_all_vsi(pf);
4904
4905 /* tell the firmware that we're starting */
4906 dv.major_version = DRV_VERSION_MAJOR;
4907 dv.minor_version = DRV_VERSION_MINOR;
4908 dv.build_version = DRV_VERSION_BUILD;
4909 dv.subbuild_version = 0;
4910 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4911
4912 dev_info(&pf->pdev->dev, "PF reset done\n");
4913
4914end_core_reset:
4915 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4916}
4917
f650a38b
ASJ		 4918/**
4919 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4920 * @pf: board private structure
4921 *
4922 * Close up the VFs and other things in prep for a Core Reset,
4923 * then get ready to rebuild the world.
4924 **/
4925static void i40e_handle_reset_warning(struct i40e_pf *pf)
4926{
4927 i40e_status ret;
4928
4929 ret = i40e_prep_for_reset(pf);
4930 if (!ret)
bc7d338f 4931 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4932}
4933
41c445ff
JB		 4934/**
4935 * i40e_handle_mdd_event
4936 * @pf: pointer to the pf structure
4937 *
4938 * Called from the MDD irq handler to identify possibly malicious vfs
4939 **/
4940static void i40e_handle_mdd_event(struct i40e_pf *pf)
4941{
4942 struct i40e_hw *hw = &pf->hw;
4943 bool mdd_detected = false;
4944 struct i40e_vf *vf;
4945 u32 reg;
4946 int i;
4947
4948 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
4949 return;
4950
4951 /* find what triggered the MDD event */
4952 reg = rd32(hw, I40E_GL_MDET_TX);
4953 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4954 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
4955 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
4956 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
4957 >> I40E_GL_MDET_TX_EVENT_SHIFT;
4958 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
4959 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
4960 dev_info(&pf->pdev->dev,
4961 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
4962 event, queue, func);
4963 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
4964 mdd_detected = true;
4965 }
4966 reg = rd32(hw, I40E_GL_MDET_RX);
4967 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4968 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
4969 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
4970 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
4971 >> I40E_GL_MDET_RX_EVENT_SHIFT;
4972 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
4973 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
4974 dev_info(&pf->pdev->dev,
4975 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
4976 event, queue, func);
4977 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
4978 mdd_detected = true;
4979 }
4980
4981 /* see if one of the VFs needs its hand slapped */
4982 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
4983 vf = &(pf->vf[i]);
4984 reg = rd32(hw, I40E_VP_MDET_TX(i));
4985 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
4986 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
4987 vf->num_mdd_events++;
4988 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
4989 }
4990
4991 reg = rd32(hw, I40E_VP_MDET_RX(i));
4992 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
4993 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
4994 vf->num_mdd_events++;
4995 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
4996 }
4997
4998 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
4999 dev_info(&pf->pdev->dev,
5000 "Too many MDD events on VF %d, disabled\n", i);
5001 dev_info(&pf->pdev->dev,
5002 "Use PF Control I/F to re-enable the VF\n");
5003 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5004 }
5005 }
5006
5007 /* re-enable mdd interrupt cause */
5008 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5009 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5010 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5011 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5012 i40e_flush(hw);
5013}
5014
a1c9a9d9
JK		 5015#ifdef CONFIG_I40E_VXLAN
5016/**
5017 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5018 * @pf: board private structure
5019 **/
5020static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5021{
5022 const int vxlan_hdr_qwords = 4;
5023 struct i40e_hw *hw = &pf->hw;
5024 i40e_status ret;
5025 u8 filter_index;
5026 __be16 port;
5027 int i;
5028
5029 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5030 return;
5031
5032 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5033
5034 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5035 if (pf->pending_vxlan_bitmap & (1 << i)) {
5036 pf->pending_vxlan_bitmap &= ~(1 << i);
5037 port = pf->vxlan_ports[i];
5038 ret = port ?
5039 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5040 vxlan_hdr_qwords,
5041 I40E_AQC_TUNNEL_TYPE_VXLAN,
5042 &filter_index, NULL)
5043 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5044
5045 if (ret) {
5046 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5047 port ? "adding" : "deleting",
5048 ntohs(port), port ? i : i);
5049
5050 pf->vxlan_ports[i] = 0;
5051 } else {
5052 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5053 port ? "Added" : "Deleted",
5054 ntohs(port), port ? i : filter_index);
5055 }
5056 }
5057 }
5058}
5059
5060#endif
41c445ff
JB		 5061/**
5062 * i40e_service_task - Run the driver's async subtasks
5063 * @work: pointer to work_struct containing our data
5064 **/
5065static void i40e_service_task(struct work_struct *work)
5066{
5067 struct i40e_pf *pf = container_of(work,
5068 struct i40e_pf,
5069 service_task);
5070 unsigned long start_time = jiffies;
5071
5072 i40e_reset_subtask(pf);
5073 i40e_handle_mdd_event(pf);
5074 i40e_vc_process_vflr_event(pf);
5075 i40e_watchdog_subtask(pf);
5076 i40e_fdir_reinit_subtask(pf);
5077 i40e_check_hang_subtask(pf);
5078 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5079#ifdef CONFIG_I40E_VXLAN
5080 i40e_sync_vxlan_filters_subtask(pf);
5081#endif
41c445ff
JB		 5082 i40e_clean_adminq_subtask(pf);
5083
5084 i40e_service_event_complete(pf);
5085
5086 /* If the tasks have taken longer than one timer cycle or there
5087 * is more work to be done, reschedule the service task now
5088 * rather than wait for the timer to tick again.
5089 */
5090 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5091 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5092 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5093 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5094 i40e_service_event_schedule(pf);
5095}
5096
5097/**
5098 * i40e_service_timer - timer callback
5099 * @data: pointer to PF struct
5100 **/
5101static void i40e_service_timer(unsigned long data)
5102{
5103 struct i40e_pf *pf = (struct i40e_pf *)data;
5104
5105 mod_timer(&pf->service_timer,
5106 round_jiffies(jiffies + pf->service_timer_period));
5107 i40e_service_event_schedule(pf);
5108}
5109
5110/**
5111 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5112 * @vsi: the VSI being configured
5113 **/
5114static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5115{
5116 struct i40e_pf *pf = vsi->back;
5117
5118 switch (vsi->type) {
5119 case I40E_VSI_MAIN:
5120 vsi->alloc_queue_pairs = pf->num_lan_qps;
5121 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5122 I40E_REQ_DESCRIPTOR_MULTIPLE);
5123 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5124 vsi->num_q_vectors = pf->num_lan_msix;
5125 else
5126 vsi->num_q_vectors = 1;
5127
5128 break;
5129
5130 case I40E_VSI_FDIR:
5131 vsi->alloc_queue_pairs = 1;
5132 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5133 I40E_REQ_DESCRIPTOR_MULTIPLE);
5134 vsi->num_q_vectors = 1;
5135 break;
5136
5137 case I40E_VSI_VMDQ2:
5138 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5139 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5140 I40E_REQ_DESCRIPTOR_MULTIPLE);
5141 vsi->num_q_vectors = pf->num_vmdq_msix;
5142 break;
5143
5144 case I40E_VSI_SRIOV:
5145 vsi->alloc_queue_pairs = pf->num_vf_qps;
5146 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5147 I40E_REQ_DESCRIPTOR_MULTIPLE);
5148 break;
5149
5150 default:
5151 WARN_ON(1);
5152 return -ENODATA;
5153 }
5154
5155 return 0;
5156}
5157
f650a38b
ASJ		 5158/**
5159 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5160 * @type: VSI pointer
bc7d338f 5161 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5162 *
5163 * On error: returns error code (negative)
5164 * On success: returns 0
5165 **/
bc7d338f 5166static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5167{
5168 int size;
5169 int ret = 0;
5170
ac6c5e3d 5171 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5172 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5173 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5174 if (!vsi->tx_rings)
5175 return -ENOMEM;
f650a38b
ASJ		 5176 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5177
bc7d338f
ASJ		 5178 if (alloc_qvectors) {
5179 /* allocate memory for q_vector pointers */
5180 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5181 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5182 if (!vsi->q_vectors) {
5183 ret = -ENOMEM;
5184 goto err_vectors;
5185 }
f650a38b
ASJ		 5186 }
5187 return ret;
5188
5189err_vectors:
5190 kfree(vsi->tx_rings);
5191 return ret;
5192}
5193
41c445ff
JB		 5194/**
5195 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5196 * @pf: board private structure
5197 * @type: type of VSI
5198 *
5199 * On error: returns error code (negative)
5200 * On success: returns vsi index in PF (positive)
5201 **/
5202static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5203{
5204 int ret = -ENODEV;
5205 struct i40e_vsi *vsi;
5206 int vsi_idx;
5207 int i;
5208
5209 /* Need to protect the allocation of the VSIs at the PF level */
5210 mutex_lock(&pf->switch_mutex);
5211
5212 /* VSI list may be fragmented if VSI creation/destruction has
5213 * been happening. We can afford to do a quick scan to look
5214 * for any free VSIs in the list.
5215 *
5216 * find next empty vsi slot, looping back around if necessary
5217 */
5218 i = pf->next_vsi;
5219 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5220 i++;
5221 if (i >= pf->hw.func_caps.num_vsis) {
5222 i = 0;
5223 while (i < pf->next_vsi && pf->vsi[i])
5224 i++;
5225 }
5226
5227 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5228 vsi_idx = i; /* Found one! */
5229 } else {
5230 ret = -ENODEV;
493fb300 5231 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5232 }
5233 pf->next_vsi = ++i;
5234
5235 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5236 if (!vsi) {
5237 ret = -ENOMEM;
493fb300 5238 goto unlock_pf;
41c445ff
JB		 5239 }
5240 vsi->type = type;
5241 vsi->back = pf;
5242 set_bit(__I40E_DOWN, &vsi->state);
5243 vsi->flags = 0;
5244 vsi->idx = vsi_idx;
5245 vsi->rx_itr_setting = pf->rx_itr_default;
5246 vsi->tx_itr_setting = pf->tx_itr_default;
5247 vsi->netdev_registered = false;
5248 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5249 INIT_LIST_HEAD(&vsi->mac_filter_list);
5250
9f65e15b
AD		 5251 ret = i40e_set_num_rings_in_vsi(vsi);
5252 if (ret)
5253 goto err_rings;
5254
bc7d338f 5255 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5256 if (ret)
9f65e15b 5257 goto err_rings;
493fb300 5258
41c445ff
JB		 5259 /* Setup default MSIX irq handler for VSI */
5260 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5261
5262 pf->vsi[vsi_idx] = vsi;
5263 ret = vsi_idx;
493fb300
AD		 5264 goto unlock_pf;
5265
9f65e15b 5266err_rings:
493fb300
AD		 5267 pf->next_vsi = i - 1;
5268 kfree(vsi);
5269unlock_pf:
41c445ff
JB		 5270 mutex_unlock(&pf->switch_mutex);
5271 return ret;
5272}
5273
f650a38b
ASJ		 5274/**
5275 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5276 * @type: VSI pointer
bc7d338f 5277 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5278 *
5279 * On error: returns error code (negative)
5280 * On success: returns 0
5281 **/
bc7d338f 5282static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5283{
5284 /* free the ring and vector containers */
bc7d338f
ASJ		 5285 if (free_qvectors) {
5286 kfree(vsi->q_vectors);
5287 vsi->q_vectors = NULL;
5288 }
f650a38b
ASJ		 5289 kfree(vsi->tx_rings);
5290 vsi->tx_rings = NULL;
5291 vsi->rx_rings = NULL;
5292}
5293
41c445ff
JB		 5294/**
5295 * i40e_vsi_clear - Deallocate the VSI provided
5296 * @vsi: the VSI being un-configured
5297 **/
5298static int i40e_vsi_clear(struct i40e_vsi *vsi)
5299{
5300 struct i40e_pf *pf;
5301
5302 if (!vsi)
5303 return 0;
5304
5305 if (!vsi->back)
5306 goto free_vsi;
5307 pf = vsi->back;
5308
5309 mutex_lock(&pf->switch_mutex);
5310 if (!pf->vsi[vsi->idx]) {
5311 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5312 vsi->idx, vsi->idx, vsi, vsi->type);
5313 goto unlock_vsi;
5314 }
5315
5316 if (pf->vsi[vsi->idx] != vsi) {
5317 dev_err(&pf->pdev->dev,
5318 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5319 pf->vsi[vsi->idx]->idx,
5320 pf->vsi[vsi->idx],
5321 pf->vsi[vsi->idx]->type,
5322 vsi->idx, vsi, vsi->type);
5323 goto unlock_vsi;
5324 }
5325
5326 /* updates the pf for this cleared vsi */
5327 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5328 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5329
bc7d338f 5330 i40e_vsi_free_arrays(vsi, true);
493fb300 5331
41c445ff
JB		 5332 pf->vsi[vsi->idx] = NULL;
5333 if (vsi->idx < pf->next_vsi)
5334 pf->next_vsi = vsi->idx;
5335
5336unlock_vsi:
5337 mutex_unlock(&pf->switch_mutex);
5338free_vsi:
5339 kfree(vsi);
5340
5341 return 0;
5342}
5343
9f65e15b
AD		 5344/**
5345 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5346 * @vsi: the VSI being cleaned
5347 **/
be1d5eea 5348static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5349{
5350 int i;
5351
be1d5eea 5352 if (vsi->tx_rings[0]) {
ac6c5e3d 5353 for (i = 0; i < vsi->num_queue_pairs; i++) {
00403f04
MW		 5354 kfree_rcu(vsi->tx_rings[i], rcu);
5355 vsi->tx_rings[i] = NULL;
5356 vsi->rx_rings[i] = NULL;
5357 }
be1d5eea 5358 }
9f65e15b
AD		 5359}
5360
41c445ff
JB		 5361/**
5362 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5363 * @vsi: the VSI being configured
5364 **/
5365static int i40e_alloc_rings(struct i40e_vsi *vsi)
5366{
5367 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5368 int i;
5369
41c445ff 5370 /* Set basic values in the rings to be used later during open() */
ac6c5e3d 5371 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5372 struct i40e_ring *tx_ring;
5373 struct i40e_ring *rx_ring;
5374
ac6c5e3d 5375 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5376 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5377 if (!tx_ring)
5378 goto err_out;
41c445ff
JB		 5379
5380 tx_ring->queue_index = i;
5381 tx_ring->reg_idx = vsi->base_queue + i;
5382 tx_ring->ring_active = false;
5383 tx_ring->vsi = vsi;
5384 tx_ring->netdev = vsi->netdev;
5385 tx_ring->dev = &pf->pdev->dev;
5386 tx_ring->count = vsi->num_desc;
5387 tx_ring->size = 0;
5388 tx_ring->dcb_tc = 0;
9f65e15b 5389 vsi->tx_rings[i] = tx_ring;
41c445ff 5390
9f65e15b 5391 rx_ring = &tx_ring[1];
41c445ff
JB		 5392 rx_ring->queue_index = i;
5393 rx_ring->reg_idx = vsi->base_queue + i;
5394 rx_ring->ring_active = false;
5395 rx_ring->vsi = vsi;
5396 rx_ring->netdev = vsi->netdev;
5397 rx_ring->dev = &pf->pdev->dev;
5398 rx_ring->count = vsi->num_desc;
5399 rx_ring->size = 0;
5400 rx_ring->dcb_tc = 0;
5401 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5402 set_ring_16byte_desc_enabled(rx_ring);
5403 else
5404 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5405 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5406 }
5407
5408 return 0;
9f65e15b
AD		 5409
5410err_out:
5411 i40e_vsi_clear_rings(vsi);
5412 return -ENOMEM;
41c445ff
JB		 5413}
5414
5415/**
5416 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5417 * @pf: board private structure
5418 * @vectors: the number of MSI-X vectors to request
5419 *
5420 * Returns the number of vectors reserved, or error
5421 **/
5422static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5423{
5424 int err = 0;
5425
5426 pf->num_msix_entries = 0;
5427 while (vectors >= I40E_MIN_MSIX) {
5428 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5429 if (err == 0) {
5430 /* good to go */
5431 pf->num_msix_entries = vectors;
5432 break;
5433 } else if (err < 0) {
5434 /* total failure */
5435 dev_info(&pf->pdev->dev,
5436 "MSI-X vector reservation failed: %d\n", err);
5437 vectors = 0;
5438 break;
5439 } else {
5440 /* err > 0 is the hint for retry */
5441 dev_info(&pf->pdev->dev,
5442 "MSI-X vectors wanted %d, retrying with %d\n",
5443 vectors, err);
5444 vectors = err;
5445 }
5446 }
5447
5448 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5449 dev_info(&pf->pdev->dev,
5450 "Couldn't get enough vectors, only %d available\n",
5451 vectors);
5452 vectors = 0;
5453 }
5454
5455 return vectors;
5456}
5457
5458/**
5459 * i40e_init_msix - Setup the MSIX capability
5460 * @pf: board private structure
5461 *
5462 * Work with the OS to set up the MSIX vectors needed.
5463 *
5464 * Returns 0 on success, negative on failure
5465 **/
5466static int i40e_init_msix(struct i40e_pf *pf)
5467{
5468 i40e_status err = 0;
5469 struct i40e_hw *hw = &pf->hw;
5470 int v_budget, i;
5471 int vec;
5472
5473 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5474 return -ENODEV;
5475
5476 /* The number of vectors we'll request will be comprised of:
5477 * - Add 1 for "other" cause for Admin Queue events, etc.
5478 * - The number of LAN queue pairs
f8ff1464
ASJ		 5479 * - Queues being used for RSS.
5480 * We don't need as many as max_rss_size vectors.
5481 * use rss_size instead in the calculation since that
5482 * is governed by number of cpus in the system.
5483 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5484 * - The number of VMDq pairs
5485 * Once we count this up, try the request.
5486 *
5487 * If we can't get what we want, we'll simplify to nearly nothing
5488 * and try again. If that still fails, we punt.
5489 */
f8ff1464 5490 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5491 pf->num_vmdq_msix = pf->num_vmdq_qps;
5492 v_budget = 1 + pf->num_lan_msix;
5493 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5494 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5495 v_budget++;
5496
5497 /* Scale down if necessary, and the rings will share vectors */
5498 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5499
5500 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5501 GFP_KERNEL);
5502 if (!pf->msix_entries)
5503 return -ENOMEM;
5504
5505 for (i = 0; i < v_budget; i++)
5506 pf->msix_entries[i].entry = i;
5507 vec = i40e_reserve_msix_vectors(pf, v_budget);
5508 if (vec < I40E_MIN_MSIX) {
5509 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5510 kfree(pf->msix_entries);
5511 pf->msix_entries = NULL;
5512 return -ENODEV;
5513
5514 } else if (vec == I40E_MIN_MSIX) {
5515 /* Adjust for minimal MSIX use */
5516 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5517 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5518 pf->num_vmdq_vsis = 0;
5519 pf->num_vmdq_qps = 0;
5520 pf->num_vmdq_msix = 0;
5521 pf->num_lan_qps = 1;
5522 pf->num_lan_msix = 1;
5523
5524 } else if (vec != v_budget) {
5525 /* Scale vector usage down */
5526 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5527 vec--; /* reserve the misc vector */
5528
5529 /* partition out the remaining vectors */
5530 switch (vec) {
5531 case 2:
5532 pf->num_vmdq_vsis = 1;
5533 pf->num_lan_msix = 1;
5534 break;
5535 case 3:
5536 pf->num_vmdq_vsis = 1;
5537 pf->num_lan_msix = 2;
5538 break;
5539 default:
5540 pf->num_lan_msix = min_t(int, (vec / 2),
5541 pf->num_lan_qps);
5542 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5543 I40E_DEFAULT_NUM_VMDQ_VSI);
5544 break;
5545 }
5546 }
5547
5548 return err;
5549}
5550
493fb300
AD		 5551/**
5552 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5553 * @vsi: the VSI being configured
5554 * @v_idx: index of the vector in the vsi struct
5555 *
5556 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5557 **/
5558static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5559{
5560 struct i40e_q_vector *q_vector;
5561
5562 /* allocate q_vector */
5563 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5564 if (!q_vector)
5565 return -ENOMEM;
5566
5567 q_vector->vsi = vsi;
5568 q_vector->v_idx = v_idx;
5569 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5570 if (vsi->netdev)
5571 netif_napi_add(vsi->netdev, &q_vector->napi,
5572 i40e_napi_poll, vsi->work_limit);
5573
cd0b6fa6
AD		 5574 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5575 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5576
493fb300
AD		 5577 /* tie q_vector and vsi together */
5578 vsi->q_vectors[v_idx] = q_vector;
5579
5580 return 0;
5581}
5582
41c445ff
JB		 5583/**
5584 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5585 * @vsi: the VSI being configured
5586 *
5587 * We allocate one q_vector per queue interrupt. If allocation fails we
5588 * return -ENOMEM.
5589 **/
5590static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5591{
5592 struct i40e_pf *pf = vsi->back;
5593 int v_idx, num_q_vectors;
493fb300 5594 int err;
41c445ff
JB		 5595
5596 /* if not MSIX, give the one vector only to the LAN VSI */
5597 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5598 num_q_vectors = vsi->num_q_vectors;
5599 else if (vsi == pf->vsi[pf->lan_vsi])
5600 num_q_vectors = 1;
5601 else
5602 return -EINVAL;
5603
41c445ff 5604 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5605 err = i40e_alloc_q_vector(vsi, v_idx);
5606 if (err)
5607 goto err_out;
41c445ff
JB		 5608 }
5609
5610 return 0;
493fb300
AD		 5611
5612err_out:
5613 while (v_idx--)
5614 i40e_free_q_vector(vsi, v_idx);
5615
5616 return err;
41c445ff
JB		 5617}
5618
5619/**
5620 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5621 * @pf: board private structure to initialize
5622 **/
5623static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5624{
5625 int err = 0;
5626
5627 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5628 err = i40e_init_msix(pf);
5629 if (err) {
958a3e3b
SN		 5630 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5631 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5632 I40E_FLAG_MQ_ENABLED |
5633 I40E_FLAG_DCB_ENABLED |
5634 I40E_FLAG_SRIOV_ENABLED |
5635 I40E_FLAG_FDIR_ENABLED |
5636 I40E_FLAG_FDIR_ATR_ENABLED |
5637 I40E_FLAG_VMDQ_ENABLED);
5638
5639 /* rework the queue expectations without MSIX */
5640 i40e_determine_queue_usage(pf);
5641 }
5642 }
5643
5644 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5645 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5646 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5647 err = pci_enable_msi(pf->pdev);
5648 if (err) {
958a3e3b 5649 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5650 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5651 }
5652 }
5653
958a3e3b
SN		 5654 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5655 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5656
41c445ff
JB		 5657 /* track first vector for misc interrupts */
5658 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5659}
5660
5661/**
5662 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5663 * @pf: board private structure
5664 *
5665 * This sets up the handler for MSIX 0, which is used to manage the
5666 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5667 * when in MSI or Legacy interrupt mode.
5668 **/
5669static int i40e_setup_misc_vector(struct i40e_pf *pf)
5670{
5671 struct i40e_hw *hw = &pf->hw;
5672 int err = 0;
5673
5674 /* Only request the irq if this is the first time through, and
5675 * not when we're rebuilding after a Reset
5676 */
5677 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5678 err = request_irq(pf->msix_entries[0].vector,
5679 i40e_intr, 0, pf->misc_int_name, pf);
5680 if (err) {
5681 dev_info(&pf->pdev->dev,
5682 "request_irq for msix_misc failed: %d\n", err);
5683 return -EFAULT;
5684 }
5685 }
5686
5687 i40e_enable_misc_int_causes(hw);
5688
5689 /* associate no queues to the misc vector */
5690 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5691 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5692
5693 i40e_flush(hw);
5694
5695 i40e_irq_dynamic_enable_icr0(pf);
5696
5697 return err;
5698}
5699
5700/**
5701 * i40e_config_rss - Prepare for RSS if used
5702 * @pf: board private structure
5703 **/
5704static int i40e_config_rss(struct i40e_pf *pf)
5705{
4617e8c0
ASJ		 5706 const u64 default_hena =
5707 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
5708 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |
5709 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
5710 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) |
5711 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN) |
5712 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
5713 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |
5714 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) |
5715 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
5716 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |
5717 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
5718 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN) |
5719 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
5720 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) |
5721 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
5722 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) |
5723 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD);
5724
41c445ff
JB		 5725 /* Set of random keys generated using kernel random number generator */
5726 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5727 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5728 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5729 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5730 struct i40e_hw *hw = &pf->hw;
5731 u32 lut = 0;
5732 int i, j;
5733 u64 hena;
41c445ff
JB		 5734
5735 /* Fill out hash function seed */
5736 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5737 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5738
5739 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5740 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5741 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
4617e8c0 5742 hena |= default_hena;
41c445ff
JB		 5743 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5744 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5745
5746 /* Populate the LUT with max no. of queues in round robin fashion */
5747 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5748
5749 /* The assumption is that lan qp count will be the highest
5750 * qp count for any PF VSI that needs RSS.
5751 * If multiple VSIs need RSS support, all the qp counts
5752 * for those VSIs should be a power of 2 for RSS to work.
5753 * If LAN VSI is the only consumer for RSS then this requirement
5754 * is not necessary.
5755 */
5756 if (j == pf->rss_size)
5757 j = 0;
5758 /* lut = 4-byte sliding window of 4 lut entries */
5759 lut = (lut << 8) | (j &
5760 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5761 /* On i = 3, we have 4 entries in lut; write to the register */
5762 if ((i & 3) == 3)
5763 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5764 }
5765 i40e_flush(hw);
5766
5767 return 0;
5768}
5769
f8ff1464
ASJ		 5770/**
5771 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5772 * @pf: board private structure
5773 * @queue_count: the requested queue count for rss.
5774 *
5775 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5776 * count which may be different from the requested queue count.
5777 **/
5778int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5779{
5780 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5781 return 0;
5782
5783 queue_count = min_t(int, queue_count, pf->rss_size_max);
5784 queue_count = rounddown_pow_of_two(queue_count);
5785
5786 if (queue_count != pf->rss_size) {
5787 if (pf->queues_left < (queue_count - pf->rss_size)) {
5788 dev_info(&pf->pdev->dev,
5789 "Not enough queues to do RSS on %d queues: remaining queues %d\n",
5790 queue_count, pf->queues_left);
5791 return pf->rss_size;
5792 }
5793 i40e_prep_for_reset(pf);
5794
5795 pf->num_lan_qps += (queue_count - pf->rss_size);
5796 pf->queues_left -= (queue_count - pf->rss_size);
5797 pf->rss_size = queue_count;
5798
5799 i40e_reset_and_rebuild(pf, true);
5800 i40e_config_rss(pf);
5801 }
5802 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5803 return pf->rss_size;
5804}
5805
41c445ff
JB		 5806/**
5807 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5808 * @pf: board private structure to initialize
5809 *
5810 * i40e_sw_init initializes the Adapter private data structure.
5811 * Fields are initialized based on PCI device information and
5812 * OS network device settings (MTU size).
5813 **/
5814static int i40e_sw_init(struct i40e_pf *pf)
5815{
5816 int err = 0;
5817 int size;
5818
5819 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5820 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5821 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5822 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5823 if (I40E_DEBUG_USER & debug)
5824 pf->hw.debug_mask = debug;
5825 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5826 I40E_DEFAULT_MSG_ENABLE);
5827 }
5828
5829 /* Set default capability flags */
5830 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5831 I40E_FLAG_MSI_ENABLED |
5832 I40E_FLAG_MSIX_ENABLED |
5833 I40E_FLAG_RX_PS_ENABLED |
5834 I40E_FLAG_MQ_ENABLED |
5835 I40E_FLAG_RX_1BUF_ENABLED;
5836
7134f9ce
JB		 5837 /* Depending on PF configurations, it is possible that the RSS
5838 * maximum might end up larger than the available queues
5839 */
41c445ff 5840 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5841 pf->rss_size_max = min_t(int, pf->rss_size_max,
5842 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5843 if (pf->hw.func_caps.rss) {
5844 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5845 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5846 } else {
5847 pf->rss_size = 1;
5848 }
5849
5850 if (pf->hw.func_caps.dcb)
5851 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5852 else
5853 pf->num_tc_qps = 0;
5854
5855 if (pf->hw.func_caps.fd) {
5856 /* FW/NVM is not yet fixed in this regard */
5857 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5858 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5859 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5860 dev_info(&pf->pdev->dev,
5861 "Flow Director ATR mode Enabled\n");
5862 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5863 dev_info(&pf->pdev->dev,
5864 "Flow Director Side Band mode Enabled\n");
5865 pf->fdir_pf_filter_count =
5866 pf->hw.func_caps.fd_filters_guaranteed;
5867 }
5868 } else {
5869 pf->fdir_pf_filter_count = 0;
5870 }
5871
5872 if (pf->hw.func_caps.vmdq) {
5873 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5874 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5875 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5876 }
5877
5878 /* MFP mode enabled */
5879 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5880 pf->flags |= I40E_FLAG_MFP_ENABLED;
5881 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5882 }
5883
5884#ifdef CONFIG_PCI_IOV
5885 if (pf->hw.func_caps.num_vfs) {
5886 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5887 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5888 pf->num_req_vfs = min_t(int,
5889 pf->hw.func_caps.num_vfs,
5890 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5891 dev_info(&pf->pdev->dev,
5892 "Number of VFs being requested for PF[%d] = %d\n",
5893 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5894 }
5895#endif /* CONFIG_PCI_IOV */
5896 pf->eeprom_version = 0xDEAD;
5897 pf->lan_veb = I40E_NO_VEB;
5898 pf->lan_vsi = I40E_NO_VSI;
5899
5900 /* set up queue assignment tracking */
5901 size = sizeof(struct i40e_lump_tracking)
5902 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5903 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5904 if (!pf->qp_pile) {
5905 err = -ENOMEM;
5906 goto sw_init_done;
5907 }
5908 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5909 pf->qp_pile->search_hint = 0;
5910
5911 /* set up vector assignment tracking */
5912 size = sizeof(struct i40e_lump_tracking)
5913 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5914 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5915 if (!pf->irq_pile) {
5916 kfree(pf->qp_pile);
5917 err = -ENOMEM;
5918 goto sw_init_done;
5919 }
5920 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5921 pf->irq_pile->search_hint = 0;
5922
5923 mutex_init(&pf->switch_mutex);
5924
5925sw_init_done:
5926 return err;
5927}
5928
5929/**
5930 * i40e_set_features - set the netdev feature flags
5931 * @netdev: ptr to the netdev being adjusted
5932 * @features: the feature set that the stack is suggesting
5933 **/
5934static int i40e_set_features(struct net_device *netdev,
5935 netdev_features_t features)
5936{
5937 struct i40e_netdev_priv *np = netdev_priv(netdev);
5938 struct i40e_vsi *vsi = np->vsi;
5939
5940 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5941 i40e_vlan_stripping_enable(vsi);
5942 else
5943 i40e_vlan_stripping_disable(vsi);
5944
5945 return 0;
5946}
5947
a1c9a9d9
JK		 5948#ifdef CONFIG_I40E_VXLAN
5949/**
5950 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5951 * @pf: board private structure
5952 * @port: The UDP port to look up
5953 *
5954 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5955 **/
5956static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5957{
5958 u8 i;
5959
5960 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5961 if (pf->vxlan_ports[i] == port)
5962 return i;
5963 }
5964
5965 return i;
5966}
5967
5968/**
5969 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5970 * @netdev: This physical port's netdev
5971 * @sa_family: Socket Family that VXLAN is notifying us about
5972 * @port: New UDP port number that VXLAN started listening to
5973 **/
5974static void i40e_add_vxlan_port(struct net_device *netdev,
5975 sa_family_t sa_family, __be16 port)
5976{
5977 struct i40e_netdev_priv *np = netdev_priv(netdev);
5978 struct i40e_vsi *vsi = np->vsi;
5979 struct i40e_pf *pf = vsi->back;
5980 u8 next_idx;
5981 u8 idx;
5982
5983 if (sa_family == AF_INET6)
5984 return;
5985
5986 idx = i40e_get_vxlan_port_idx(pf, port);
5987
5988 /* Check if port already exists */
5989 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5990 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
5991 return;
5992 }
5993
5994 /* Now check if there is space to add the new port */
5995 next_idx = i40e_get_vxlan_port_idx(pf, 0);
5996
5997 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5998 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
5999 ntohs(port));
6000 return;
6001 }
6002
6003 /* New port: add it and mark its index in the bitmap */
6004 pf->vxlan_ports[next_idx] = port;
6005 pf->pending_vxlan_bitmap |= (1 << next_idx);
6006
6007 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6008}
6009
6010/**
6011 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6012 * @netdev: This physical port's netdev
6013 * @sa_family: Socket Family that VXLAN is notifying us about
6014 * @port: UDP port number that VXLAN stopped listening to
6015 **/
6016static void i40e_del_vxlan_port(struct net_device *netdev,
6017 sa_family_t sa_family, __be16 port)
6018{
6019 struct i40e_netdev_priv *np = netdev_priv(netdev);
6020 struct i40e_vsi *vsi = np->vsi;
6021 struct i40e_pf *pf = vsi->back;
6022 u8 idx;
6023
6024 if (sa_family == AF_INET6)
6025 return;
6026
6027 idx = i40e_get_vxlan_port_idx(pf, port);
6028
6029 /* Check if port already exists */
6030 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6031 /* if port exists, set it to 0 (mark for deletion)
6032 * and make it pending
6033 */
6034 pf->vxlan_ports[idx] = 0;
6035
6036 pf->pending_vxlan_bitmap |= (1 << idx);
6037
6038 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6039 } else {
6040 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6041 ntohs(port));
6042 }
6043}
6044
6045#endif
41c445ff
JB		 6046static const struct net_device_ops i40e_netdev_ops = {
6047 .ndo_open = i40e_open,
6048 .ndo_stop = i40e_close,
6049 .ndo_start_xmit = i40e_lan_xmit_frame,
6050 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6051 .ndo_set_rx_mode = i40e_set_rx_mode,
6052 .ndo_validate_addr = eth_validate_addr,
6053 .ndo_set_mac_address = i40e_set_mac,
6054 .ndo_change_mtu = i40e_change_mtu,
6055 .ndo_tx_timeout = i40e_tx_timeout,
6056 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6057 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6058#ifdef CONFIG_NET_POLL_CONTROLLER
6059 .ndo_poll_controller = i40e_netpoll,
6060#endif
6061 .ndo_setup_tc = i40e_setup_tc,
6062 .ndo_set_features = i40e_set_features,
6063 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6064 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6065 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6066 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6067#ifdef CONFIG_I40E_VXLAN
6068 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6069 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6070#endif
41c445ff
JB		 6071};
6072
6073/**
6074 * i40e_config_netdev - Setup the netdev flags
6075 * @vsi: the VSI being configured
6076 *
6077 * Returns 0 on success, negative value on failure
6078 **/
6079static int i40e_config_netdev(struct i40e_vsi *vsi)
6080{
6081 struct i40e_pf *pf = vsi->back;
6082 struct i40e_hw *hw = &pf->hw;
6083 struct i40e_netdev_priv *np;
6084 struct net_device *netdev;
6085 u8 mac_addr[ETH_ALEN];
6086 int etherdev_size;
6087
6088 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6089 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6090 if (!netdev)
6091 return -ENOMEM;
6092
6093 vsi->netdev = netdev;
6094 np = netdev_priv(netdev);
6095 np->vsi = vsi;
6096
6097 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6098 NETIF_F_GSO_UDP_TUNNEL |
6099 NETIF_F_TSO |
6100 NETIF_F_SG;
6101
6102 netdev->features = NETIF_F_SG |
6103 NETIF_F_IP_CSUM |
6104 NETIF_F_SCTP_CSUM |
6105 NETIF_F_HIGHDMA |
6106 NETIF_F_GSO_UDP_TUNNEL |
6107 NETIF_F_HW_VLAN_CTAG_TX |
6108 NETIF_F_HW_VLAN_CTAG_RX |
6109 NETIF_F_HW_VLAN_CTAG_FILTER |
6110 NETIF_F_IPV6_CSUM |
6111 NETIF_F_TSO |
6112 NETIF_F_TSO6 |
6113 NETIF_F_RXCSUM |
6114 NETIF_F_RXHASH |
6115 0;
6116
6117 /* copy netdev features into list of user selectable features */
6118 netdev->hw_features |= netdev->features;
6119
6120 if (vsi->type == I40E_VSI_MAIN) {
6121 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6122 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6123 } else {
6124 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6125 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6126 pf->vsi[pf->lan_vsi]->netdev->name);
6127 random_ether_addr(mac_addr);
6128 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6129 }
6130
6131 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6132 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6133 /* vlan gets same features (except vlan offload)
6134 * after any tweaks for specific VSI types
6135 */
6136 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6137 NETIF_F_HW_VLAN_CTAG_RX |
6138 NETIF_F_HW_VLAN_CTAG_FILTER);
6139 netdev->priv_flags |= IFF_UNICAST_FLT;
6140 netdev->priv_flags |= IFF_SUPP_NOFCS;
6141 /* Setup netdev TC information */
6142 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6143
6144 netdev->netdev_ops = &i40e_netdev_ops;
6145 netdev->watchdog_timeo = 5 * HZ;
6146 i40e_set_ethtool_ops(netdev);
6147
6148 return 0;
6149}
6150
6151/**
6152 * i40e_vsi_delete - Delete a VSI from the switch
6153 * @vsi: the VSI being removed
6154 *
6155 * Returns 0 on success, negative value on failure
6156 **/
6157static void i40e_vsi_delete(struct i40e_vsi *vsi)
6158{
6159 /* remove default VSI is not allowed */
6160 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6161 return;
6162
6163 /* there is no HW VSI for FDIR */
6164 if (vsi->type == I40E_VSI_FDIR)
6165 return;
6166
6167 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6168 return;
6169}
6170
6171/**
6172 * i40e_add_vsi - Add a VSI to the switch
6173 * @vsi: the VSI being configured
6174 *
6175 * This initializes a VSI context depending on the VSI type to be added and
6176 * passes it down to the add_vsi aq command.
6177 **/
6178static int i40e_add_vsi(struct i40e_vsi *vsi)
6179{
6180 int ret = -ENODEV;
6181 struct i40e_mac_filter *f, *ftmp;
6182 struct i40e_pf *pf = vsi->back;
6183 struct i40e_hw *hw = &pf->hw;
6184 struct i40e_vsi_context ctxt;
6185 u8 enabled_tc = 0x1; /* TC0 enabled */
6186 int f_count = 0;
6187
6188 memset(&ctxt, 0, sizeof(ctxt));
6189 switch (vsi->type) {
6190 case I40E_VSI_MAIN:
6191 /* The PF's main VSI is already setup as part of the
6192 * device initialization, so we'll not bother with
6193 * the add_vsi call, but we will retrieve the current
6194 * VSI context.
6195 */
6196 ctxt.seid = pf->main_vsi_seid;
6197 ctxt.pf_num = pf->hw.pf_id;
6198 ctxt.vf_num = 0;
6199 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6200 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6201 if (ret) {
6202 dev_info(&pf->pdev->dev,
6203 "couldn't get pf vsi config, err %d, aq_err %d\n",
6204 ret, pf->hw.aq.asq_last_status);
6205 return -ENOENT;
6206 }
6207 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6208 vsi->info.valid_sections = 0;
6209
6210 vsi->seid = ctxt.seid;
6211 vsi->id = ctxt.vsi_number;
6212
6213 enabled_tc = i40e_pf_get_tc_map(pf);
6214
6215 /* MFP mode setup queue map and update VSI */
6216 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6217 memset(&ctxt, 0, sizeof(ctxt));
6218 ctxt.seid = pf->main_vsi_seid;
6219 ctxt.pf_num = pf->hw.pf_id;
6220 ctxt.vf_num = 0;
6221 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6222 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6223 if (ret) {
6224 dev_info(&pf->pdev->dev,
6225 "update vsi failed, aq_err=%d\n",
6226 pf->hw.aq.asq_last_status);
6227 ret = -ENOENT;
6228 goto err;
6229 }
6230 /* update the local VSI info queue map */
6231 i40e_vsi_update_queue_map(vsi, &ctxt);
6232 vsi->info.valid_sections = 0;
6233 } else {
6234 /* Default/Main VSI is only enabled for TC0
6235 * reconfigure it to enable all TCs that are
6236 * available on the port in SFP mode.
6237 */
6238 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6239 if (ret) {
6240 dev_info(&pf->pdev->dev,
6241 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6242 enabled_tc, ret,
6243 pf->hw.aq.asq_last_status);
6244 ret = -ENOENT;
6245 }
6246 }
6247 break;
6248
6249 case I40E_VSI_FDIR:
6250 /* no queue mapping or actual HW VSI needed */
6251 vsi->info.valid_sections = 0;
6252 vsi->seid = 0;
6253 vsi->id = 0;
6254 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6255 return 0;
6256 break;
6257
6258 case I40E_VSI_VMDQ2:
6259 ctxt.pf_num = hw->pf_id;
6260 ctxt.vf_num = 0;
6261 ctxt.uplink_seid = vsi->uplink_seid;
6262 ctxt.connection_type = 0x1; /* regular data port */
6263 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6264
6265 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6266
6267 /* This VSI is connected to VEB so the switch_id
6268 * should be set to zero by default.
6269 */
6270 ctxt.info.switch_id = 0;
6271 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6272 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6273
6274 /* Setup the VSI tx/rx queue map for TC0 only for now */
6275 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6276 break;
6277
6278 case I40E_VSI_SRIOV:
6279 ctxt.pf_num = hw->pf_id;
6280 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6281 ctxt.uplink_seid = vsi->uplink_seid;
6282 ctxt.connection_type = 0x1; /* regular data port */
6283 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6284
6285 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6286
6287 /* This VSI is connected to VEB so the switch_id
6288 * should be set to zero by default.
6289 */
6290 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6291
6292 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6293 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6294 /* Setup the VSI tx/rx queue map for TC0 only for now */
6295 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6296 break;
6297
6298 default:
6299 return -ENODEV;
6300 }
6301
6302 if (vsi->type != I40E_VSI_MAIN) {
6303 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6304 if (ret) {
6305 dev_info(&vsi->back->pdev->dev,
6306 "add vsi failed, aq_err=%d\n",
6307 vsi->back->hw.aq.asq_last_status);
6308 ret = -ENOENT;
6309 goto err;
6310 }
6311 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6312 vsi->info.valid_sections = 0;
6313 vsi->seid = ctxt.seid;
6314 vsi->id = ctxt.vsi_number;
6315 }
6316
6317 /* If macvlan filters already exist, force them to get loaded */
6318 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6319 f->changed = true;
6320 f_count++;
6321 }
6322 if (f_count) {
6323 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6324 pf->flags |= I40E_FLAG_FILTER_SYNC;
6325 }
6326
6327 /* Update VSI BW information */
6328 ret = i40e_vsi_get_bw_info(vsi);
6329 if (ret) {
6330 dev_info(&pf->pdev->dev,
6331 "couldn't get vsi bw info, err %d, aq_err %d\n",
6332 ret, pf->hw.aq.asq_last_status);
6333 /* VSI is already added so not tearing that up */
6334 ret = 0;
6335 }
6336
6337err:
6338 return ret;
6339}
6340
6341/**
6342 * i40e_vsi_release - Delete a VSI and free its resources
6343 * @vsi: the VSI being removed
6344 *
6345 * Returns 0 on success or < 0 on error
6346 **/
6347int i40e_vsi_release(struct i40e_vsi *vsi)
6348{
6349 struct i40e_mac_filter *f, *ftmp;
6350 struct i40e_veb *veb = NULL;
6351 struct i40e_pf *pf;
6352 u16 uplink_seid;
6353 int i, n;
6354
6355 pf = vsi->back;
6356
6357 /* release of a VEB-owner or last VSI is not allowed */
6358 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6359 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6360 vsi->seid, vsi->uplink_seid);
6361 return -ENODEV;
6362 }
6363 if (vsi == pf->vsi[pf->lan_vsi] &&
6364 !test_bit(__I40E_DOWN, &pf->state)) {
6365 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6366 return -ENODEV;
6367 }
6368
6369 uplink_seid = vsi->uplink_seid;
6370 if (vsi->type != I40E_VSI_SRIOV) {
6371 if (vsi->netdev_registered) {
6372 vsi->netdev_registered = false;
6373 if (vsi->netdev) {
6374 /* results in a call to i40e_close() */
6375 unregister_netdev(vsi->netdev);
6376 free_netdev(vsi->netdev);
6377 vsi->netdev = NULL;
6378 }
6379 } else {
6380 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6381 i40e_down(vsi);
6382 i40e_vsi_free_irq(vsi);
6383 i40e_vsi_free_tx_resources(vsi);
6384 i40e_vsi_free_rx_resources(vsi);
6385 }
6386 i40e_vsi_disable_irq(vsi);
6387 }
6388
6389 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6390 i40e_del_filter(vsi, f->macaddr, f->vlan,
6391 f->is_vf, f->is_netdev);
6392 i40e_sync_vsi_filters(vsi);
6393
6394 i40e_vsi_delete(vsi);
6395 i40e_vsi_free_q_vectors(vsi);
6396 i40e_vsi_clear_rings(vsi);
6397 i40e_vsi_clear(vsi);
6398
6399 /* If this was the last thing on the VEB, except for the
6400 * controlling VSI, remove the VEB, which puts the controlling
6401 * VSI onto the next level down in the switch.
6402 *
6403 * Well, okay, there's one more exception here: don't remove
6404 * the orphan VEBs yet. We'll wait for an explicit remove request
6405 * from up the network stack.
6406 */
6407 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6408 if (pf->vsi[i] &&
6409 pf->vsi[i]->uplink_seid == uplink_seid &&
6410 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6411 n++; /* count the VSIs */
6412 }
6413 }
6414 for (i = 0; i < I40E_MAX_VEB; i++) {
6415 if (!pf->veb[i])
6416 continue;
6417 if (pf->veb[i]->uplink_seid == uplink_seid)
6418 n++; /* count the VEBs */
6419 if (pf->veb[i]->seid == uplink_seid)
6420 veb = pf->veb[i];
6421 }
6422 if (n == 0 && veb && veb->uplink_seid != 0)
6423 i40e_veb_release(veb);
6424
6425 return 0;
6426}
6427
6428/**
6429 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6430 * @vsi: ptr to the VSI
6431 *
6432 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6433 * corresponding SW VSI structure and initializes num_queue_pairs for the
6434 * newly allocated VSI.
6435 *
6436 * Returns 0 on success or negative on failure
6437 **/
6438static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6439{
6440 int ret = -ENOENT;
6441 struct i40e_pf *pf = vsi->back;
6442
493fb300 6443 if (vsi->q_vectors[0]) {
41c445ff
JB		 6444 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6445 vsi->seid);
6446 return -EEXIST;
6447 }
6448
6449 if (vsi->base_vector) {
6450 dev_info(&pf->pdev->dev,
6451 "VSI %d has non-zero base vector %d\n",
6452 vsi->seid, vsi->base_vector);
6453 return -EEXIST;
6454 }
6455
6456 ret = i40e_alloc_q_vectors(vsi);
6457 if (ret) {
6458 dev_info(&pf->pdev->dev,
6459 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6460 vsi->num_q_vectors, vsi->seid, ret);
6461 vsi->num_q_vectors = 0;
6462 goto vector_setup_out;
6463 }
6464
958a3e3b
SN		 6465 if (vsi->num_q_vectors)
6466 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6467 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6468 if (vsi->base_vector < 0) {
6469 dev_info(&pf->pdev->dev,
6470 "failed to get q tracking for VSI %d, err=%d\n",
6471 vsi->seid, vsi->base_vector);
6472 i40e_vsi_free_q_vectors(vsi);
6473 ret = -ENOENT;
6474 goto vector_setup_out;
6475 }
6476
6477vector_setup_out:
6478 return ret;
6479}
6480
bc7d338f
ASJ		 6481/**
6482 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6483 * @vsi: pointer to the vsi.
6484 *
6485 * This re-allocates a vsi's queue resources.
6486 *
6487 * Returns pointer to the successfully allocated and configured VSI sw struct
6488 * on success, otherwise returns NULL on failure.
6489 **/
6490static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6491{
6492 struct i40e_pf *pf = vsi->back;
6493 u8 enabled_tc;
6494 int ret;
6495
6496 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6497 i40e_vsi_clear_rings(vsi);
6498
6499 i40e_vsi_free_arrays(vsi, false);
6500 i40e_set_num_rings_in_vsi(vsi);
6501 ret = i40e_vsi_alloc_arrays(vsi, false);
6502 if (ret)
6503 goto err_vsi;
6504
6505 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6506 if (ret < 0) {
6507 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6508 vsi->seid, ret);
6509 goto err_vsi;
6510 }
6511 vsi->base_queue = ret;
6512
6513 /* Update the FW view of the VSI. Force a reset of TC and queue
6514 * layout configurations.
6515 */
6516 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6517 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6518 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6519 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6520
6521 /* assign it some queues */
6522 ret = i40e_alloc_rings(vsi);
6523 if (ret)
6524 goto err_rings;
6525
6526 /* map all of the rings to the q_vectors */
6527 i40e_vsi_map_rings_to_vectors(vsi);
6528 return vsi;
6529
6530err_rings:
6531 i40e_vsi_free_q_vectors(vsi);
6532 if (vsi->netdev_registered) {
6533 vsi->netdev_registered = false;
6534 unregister_netdev(vsi->netdev);
6535 free_netdev(vsi->netdev);
6536 vsi->netdev = NULL;
6537 }
6538 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6539err_vsi:
6540 i40e_vsi_clear(vsi);
6541 return NULL;
6542}
6543
41c445ff
JB		 6544/**
6545 * i40e_vsi_setup - Set up a VSI by a given type
6546 * @pf: board private structure
6547 * @type: VSI type
6548 * @uplink_seid: the switch element to link to
6549 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6550 *
6551 * This allocates the sw VSI structure and its queue resources, then add a VSI
6552 * to the identified VEB.
6553 *
6554 * Returns pointer to the successfully allocated and configure VSI sw struct on
6555 * success, otherwise returns NULL on failure.
6556 **/
6557struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6558 u16 uplink_seid, u32 param1)
6559{
6560 struct i40e_vsi *vsi = NULL;
6561 struct i40e_veb *veb = NULL;
6562 int ret, i;
6563 int v_idx;
6564
6565 /* The requested uplink_seid must be either
6566 * - the PF's port seid
6567 * no VEB is needed because this is the PF
6568 * or this is a Flow Director special case VSI
6569 * - seid of an existing VEB
6570 * - seid of a VSI that owns an existing VEB
6571 * - seid of a VSI that doesn't own a VEB
6572 * a new VEB is created and the VSI becomes the owner
6573 * - seid of the PF VSI, which is what creates the first VEB
6574 * this is a special case of the previous
6575 *
6576 * Find which uplink_seid we were given and create a new VEB if needed
6577 */
6578 for (i = 0; i < I40E_MAX_VEB; i++) {
6579 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6580 veb = pf->veb[i];
6581 break;
6582 }
6583 }
6584
6585 if (!veb && uplink_seid != pf->mac_seid) {
6586
6587 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6588 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6589 vsi = pf->vsi[i];
6590 break;
6591 }
6592 }
6593 if (!vsi) {
6594 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6595 uplink_seid);
6596 return NULL;
6597 }
6598
6599 if (vsi->uplink_seid == pf->mac_seid)
6600 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6601 vsi->tc_config.enabled_tc);
6602 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6603 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6604 vsi->tc_config.enabled_tc);
6605
6606 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6607 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6608 veb = pf->veb[i];
6609 }
6610 if (!veb) {
6611 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6612 return NULL;
6613 }
6614
6615 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6616 uplink_seid = veb->seid;
6617 }
6618
6619 /* get vsi sw struct */
6620 v_idx = i40e_vsi_mem_alloc(pf, type);
6621 if (v_idx < 0)
6622 goto err_alloc;
6623 vsi = pf->vsi[v_idx];
6624 vsi->type = type;
6625 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6626
6627 if (type == I40E_VSI_MAIN)
6628 pf->lan_vsi = v_idx;
6629 else if (type == I40E_VSI_SRIOV)
6630 vsi->vf_id = param1;
6631 /* assign it some queues */
6632 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6633 if (ret < 0) {
6634 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6635 vsi->seid, ret);
6636 goto err_vsi;
6637 }
6638 vsi->base_queue = ret;
6639
6640 /* get a VSI from the hardware */
6641 vsi->uplink_seid = uplink_seid;
6642 ret = i40e_add_vsi(vsi);
6643 if (ret)
6644 goto err_vsi;
6645
6646 switch (vsi->type) {
6647 /* setup the netdev if needed */
6648 case I40E_VSI_MAIN:
6649 case I40E_VSI_VMDQ2:
6650 ret = i40e_config_netdev(vsi);
6651 if (ret)
6652 goto err_netdev;
6653 ret = register_netdev(vsi->netdev);
6654 if (ret)
6655 goto err_netdev;
6656 vsi->netdev_registered = true;
6657 netif_carrier_off(vsi->netdev);
6658 /* fall through */
6659
6660 case I40E_VSI_FDIR:
6661 /* set up vectors and rings if needed */
6662 ret = i40e_vsi_setup_vectors(vsi);
6663 if (ret)
6664 goto err_msix;
6665
6666 ret = i40e_alloc_rings(vsi);
6667 if (ret)
6668 goto err_rings;
6669
6670 /* map all of the rings to the q_vectors */
6671 i40e_vsi_map_rings_to_vectors(vsi);
6672
6673 i40e_vsi_reset_stats(vsi);
6674 break;
6675
6676 default:
6677 /* no netdev or rings for the other VSI types */
6678 break;
6679 }
6680
6681 return vsi;
6682
6683err_rings:
6684 i40e_vsi_free_q_vectors(vsi);
6685err_msix:
6686 if (vsi->netdev_registered) {
6687 vsi->netdev_registered = false;
6688 unregister_netdev(vsi->netdev);
6689 free_netdev(vsi->netdev);
6690 vsi->netdev = NULL;
6691 }
6692err_netdev:
6693 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6694err_vsi:
6695 i40e_vsi_clear(vsi);
6696err_alloc:
6697 return NULL;
6698}
6699
6700/**
6701 * i40e_veb_get_bw_info - Query VEB BW information
6702 * @veb: the veb to query
6703 *
6704 * Query the Tx scheduler BW configuration data for given VEB
6705 **/
6706static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6707{
6708 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6709 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6710 struct i40e_pf *pf = veb->pf;
6711 struct i40e_hw *hw = &pf->hw;
6712 u32 tc_bw_max;
6713 int ret = 0;
6714 int i;
6715
6716 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6717 &bw_data, NULL);
6718 if (ret) {
6719 dev_info(&pf->pdev->dev,
6720 "query veb bw config failed, aq_err=%d\n",
6721 hw->aq.asq_last_status);
6722 goto out;
6723 }
6724
6725 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6726 &ets_data, NULL);
6727 if (ret) {
6728 dev_info(&pf->pdev->dev,
6729 "query veb bw ets config failed, aq_err=%d\n",
6730 hw->aq.asq_last_status);
6731 goto out;
6732 }
6733
6734 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6735 veb->bw_max_quanta = ets_data.tc_bw_max;
6736 veb->is_abs_credits = bw_data.absolute_credits_enable;
6737 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6738 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6739 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6740 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6741 veb->bw_tc_limit_credits[i] =
6742 le16_to_cpu(bw_data.tc_bw_limits[i]);
6743 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6744 }
6745
6746out:
6747 return ret;
6748}
6749
6750/**
6751 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6752 * @pf: board private structure
6753 *
6754 * On error: returns error code (negative)
6755 * On success: returns vsi index in PF (positive)
6756 **/
6757static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6758{
6759 int ret = -ENOENT;
6760 struct i40e_veb *veb;
6761 int i;
6762
6763 /* Need to protect the allocation of switch elements at the PF level */
6764 mutex_lock(&pf->switch_mutex);
6765
6766 /* VEB list may be fragmented if VEB creation/destruction has
6767 * been happening. We can afford to do a quick scan to look
6768 * for any free slots in the list.
6769 *
6770 * find next empty veb slot, looping back around if necessary
6771 */
6772 i = 0;
6773 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6774 i++;
6775 if (i >= I40E_MAX_VEB) {
6776 ret = -ENOMEM;
6777 goto err_alloc_veb; /* out of VEB slots! */
6778 }
6779
6780 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6781 if (!veb) {
6782 ret = -ENOMEM;
6783 goto err_alloc_veb;
6784 }
6785 veb->pf = pf;
6786 veb->idx = i;
6787 veb->enabled_tc = 1;
6788
6789 pf->veb[i] = veb;
6790 ret = i;
6791err_alloc_veb:
6792 mutex_unlock(&pf->switch_mutex);
6793 return ret;
6794}
6795
6796/**
6797 * i40e_switch_branch_release - Delete a branch of the switch tree
6798 * @branch: where to start deleting
6799 *
6800 * This uses recursion to find the tips of the branch to be
6801 * removed, deleting until we get back to and can delete this VEB.
6802 **/
6803static void i40e_switch_branch_release(struct i40e_veb *branch)
6804{
6805 struct i40e_pf *pf = branch->pf;
6806 u16 branch_seid = branch->seid;
6807 u16 veb_idx = branch->idx;
6808 int i;
6809
6810 /* release any VEBs on this VEB - RECURSION */
6811 for (i = 0; i < I40E_MAX_VEB; i++) {
6812 if (!pf->veb[i])
6813 continue;
6814 if (pf->veb[i]->uplink_seid == branch->seid)
6815 i40e_switch_branch_release(pf->veb[i]);
6816 }
6817
6818 /* Release the VSIs on this VEB, but not the owner VSI.
6819 *
6820 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6821 * the VEB itself, so don't use (*branch) after this loop.
6822 */
6823 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6824 if (!pf->vsi[i])
6825 continue;
6826 if (pf->vsi[i]->uplink_seid == branch_seid &&
6827 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6828 i40e_vsi_release(pf->vsi[i]);
6829 }
6830 }
6831
6832 /* There's one corner case where the VEB might not have been
6833 * removed, so double check it here and remove it if needed.
6834 * This case happens if the veb was created from the debugfs
6835 * commands and no VSIs were added to it.
6836 */
6837 if (pf->veb[veb_idx])
6838 i40e_veb_release(pf->veb[veb_idx]);
6839}
6840
6841/**
6842 * i40e_veb_clear - remove veb struct
6843 * @veb: the veb to remove
6844 **/
6845static void i40e_veb_clear(struct i40e_veb *veb)
6846{
6847 if (!veb)
6848 return;
6849
6850 if (veb->pf) {
6851 struct i40e_pf *pf = veb->pf;
6852
6853 mutex_lock(&pf->switch_mutex);
6854 if (pf->veb[veb->idx] == veb)
6855 pf->veb[veb->idx] = NULL;
6856 mutex_unlock(&pf->switch_mutex);
6857 }
6858
6859 kfree(veb);
6860}
6861
6862/**
6863 * i40e_veb_release - Delete a VEB and free its resources
6864 * @veb: the VEB being removed
6865 **/
6866void i40e_veb_release(struct i40e_veb *veb)
6867{
6868 struct i40e_vsi *vsi = NULL;
6869 struct i40e_pf *pf;
6870 int i, n = 0;
6871
6872 pf = veb->pf;
6873
6874 /* find the remaining VSI and check for extras */
6875 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6876 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6877 n++;
6878 vsi = pf->vsi[i];
6879 }
6880 }
6881 if (n != 1) {
6882 dev_info(&pf->pdev->dev,
6883 "can't remove VEB %d with %d VSIs left\n",
6884 veb->seid, n);
6885 return;
6886 }
6887
6888 /* move the remaining VSI to uplink veb */
6889 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6890 if (veb->uplink_seid) {
6891 vsi->uplink_seid = veb->uplink_seid;
6892 if (veb->uplink_seid == pf->mac_seid)
6893 vsi->veb_idx = I40E_NO_VEB;
6894 else
6895 vsi->veb_idx = veb->veb_idx;
6896 } else {
6897 /* floating VEB */
6898 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6899 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6900 }
6901
6902 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6903 i40e_veb_clear(veb);
6904
6905 return;
6906}
6907
6908/**
6909 * i40e_add_veb - create the VEB in the switch
6910 * @veb: the VEB to be instantiated
6911 * @vsi: the controlling VSI
6912 **/
6913static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6914{
6915 bool is_default = (vsi->idx == vsi->back->lan_vsi);
e1c51b95 6916 bool is_cloud = false;
41c445ff
JB		 6917 int ret;
6918
6919 /* get a VEB from the hardware */
6920 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6921 veb->enabled_tc, is_default,
6922 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6923 if (ret) {
6924 dev_info(&veb->pf->pdev->dev,
6925 "couldn't add VEB, err %d, aq_err %d\n",
6926 ret, veb->pf->hw.aq.asq_last_status);
6927 return -EPERM;
6928 }
6929
6930 /* get statistics counter */
6931 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6932 &veb->stats_idx, NULL, NULL, NULL);
6933 if (ret) {
6934 dev_info(&veb->pf->pdev->dev,
6935 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6936 ret, veb->pf->hw.aq.asq_last_status);
6937 return -EPERM;
6938 }
6939 ret = i40e_veb_get_bw_info(veb);
6940 if (ret) {
6941 dev_info(&veb->pf->pdev->dev,
6942 "couldn't get VEB bw info, err %d, aq_err %d\n",
6943 ret, veb->pf->hw.aq.asq_last_status);
6944 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6945 return -ENOENT;
6946 }
6947
6948 vsi->uplink_seid = veb->seid;
6949 vsi->veb_idx = veb->idx;
6950 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6951
6952 return 0;
6953}
6954
6955/**
6956 * i40e_veb_setup - Set up a VEB
6957 * @pf: board private structure
6958 * @flags: VEB setup flags
6959 * @uplink_seid: the switch element to link to
6960 * @vsi_seid: the initial VSI seid
6961 * @enabled_tc: Enabled TC bit-map
6962 *
6963 * This allocates the sw VEB structure and links it into the switch
6964 * It is possible and legal for this to be a duplicate of an already
6965 * existing VEB. It is also possible for both uplink and vsi seids
6966 * to be zero, in order to create a floating VEB.
6967 *
6968 * Returns pointer to the successfully allocated VEB sw struct on
6969 * success, otherwise returns NULL on failure.
6970 **/
6971struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6972 u16 uplink_seid, u16 vsi_seid,
6973 u8 enabled_tc)
6974{
6975 struct i40e_veb *veb, *uplink_veb = NULL;
6976 int vsi_idx, veb_idx;
6977 int ret;
6978
6979 /* if one seid is 0, the other must be 0 to create a floating relay */
6980 if ((uplink_seid == 0 || vsi_seid == 0) &&
6981 (uplink_seid + vsi_seid != 0)) {
6982 dev_info(&pf->pdev->dev,
6983 "one, not both seid's are 0: uplink=%d vsi=%d\n",
6984 uplink_seid, vsi_seid);
6985 return NULL;
6986 }
6987
6988 /* make sure there is such a vsi and uplink */
6989 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
6990 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
6991 break;
6992 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
6993 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
6994 vsi_seid);
6995 return NULL;
6996 }
6997
6998 if (uplink_seid && uplink_seid != pf->mac_seid) {
6999 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7000 if (pf->veb[veb_idx] &&
7001 pf->veb[veb_idx]->seid == uplink_seid) {
7002 uplink_veb = pf->veb[veb_idx];
7003 break;
7004 }
7005 }
7006 if (!uplink_veb) {
7007 dev_info(&pf->pdev->dev,
7008 "uplink seid %d not found\n", uplink_seid);
7009 return NULL;
7010 }
7011 }
7012
7013 /* get veb sw struct */
7014 veb_idx = i40e_veb_mem_alloc(pf);
7015 if (veb_idx < 0)
7016 goto err_alloc;
7017 veb = pf->veb[veb_idx];
7018 veb->flags = flags;
7019 veb->uplink_seid = uplink_seid;
7020 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7021 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7022
7023 /* create the VEB in the switch */
7024 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7025 if (ret)
7026 goto err_veb;
7027
7028 return veb;
7029
7030err_veb:
7031 i40e_veb_clear(veb);
7032err_alloc:
7033 return NULL;
7034}
7035
7036/**
7037 * i40e_setup_pf_switch_element - set pf vars based on switch type
7038 * @pf: board private structure
7039 * @ele: element we are building info from
7040 * @num_reported: total number of elements
7041 * @printconfig: should we print the contents
7042 *
7043 * helper function to assist in extracting a few useful SEID values.
7044 **/
7045static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7046 struct i40e_aqc_switch_config_element_resp *ele,
7047 u16 num_reported, bool printconfig)
7048{
7049 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7050 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7051 u8 element_type = ele->element_type;
7052 u16 seid = le16_to_cpu(ele->seid);
7053
7054 if (printconfig)
7055 dev_info(&pf->pdev->dev,
7056 "type=%d seid=%d uplink=%d downlink=%d\n",
7057 element_type, seid, uplink_seid, downlink_seid);
7058
7059 switch (element_type) {
7060 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7061 pf->mac_seid = seid;
7062 break;
7063 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7064 /* Main VEB? */
7065 if (uplink_seid != pf->mac_seid)
7066 break;
7067 if (pf->lan_veb == I40E_NO_VEB) {
7068 int v;
7069
7070 /* find existing or else empty VEB */
7071 for (v = 0; v < I40E_MAX_VEB; v++) {
7072 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7073 pf->lan_veb = v;
7074 break;
7075 }
7076 }
7077 if (pf->lan_veb == I40E_NO_VEB) {
7078 v = i40e_veb_mem_alloc(pf);
7079 if (v < 0)
7080 break;
7081 pf->lan_veb = v;
7082 }
7083 }
7084
7085 pf->veb[pf->lan_veb]->seid = seid;
7086 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7087 pf->veb[pf->lan_veb]->pf = pf;
7088 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7089 break;
7090 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7091 if (num_reported != 1)
7092 break;
7093 /* This is immediately after a reset so we can assume this is
7094 * the PF's VSI
7095 */
7096 pf->mac_seid = uplink_seid;
7097 pf->pf_seid = downlink_seid;
7098 pf->main_vsi_seid = seid;
7099 if (printconfig)
7100 dev_info(&pf->pdev->dev,
7101 "pf_seid=%d main_vsi_seid=%d\n",
7102 pf->pf_seid, pf->main_vsi_seid);
7103 break;
7104 case I40E_SWITCH_ELEMENT_TYPE_PF:
7105 case I40E_SWITCH_ELEMENT_TYPE_VF:
7106 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7107 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7108 case I40E_SWITCH_ELEMENT_TYPE_PE:
7109 case I40E_SWITCH_ELEMENT_TYPE_PA:
7110 /* ignore these for now */
7111 break;
7112 default:
7113 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7114 element_type, seid);
7115 break;
7116 }
7117}
7118
7119/**
7120 * i40e_fetch_switch_configuration - Get switch config from firmware
7121 * @pf: board private structure
7122 * @printconfig: should we print the contents
7123 *
7124 * Get the current switch configuration from the device and
7125 * extract a few useful SEID values.
7126 **/
7127int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7128{
7129 struct i40e_aqc_get_switch_config_resp *sw_config;
7130 u16 next_seid = 0;
7131 int ret = 0;
7132 u8 *aq_buf;
7133 int i;
7134
7135 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7136 if (!aq_buf)
7137 return -ENOMEM;
7138
7139 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7140 do {
7141 u16 num_reported, num_total;
7142
7143 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7144 I40E_AQ_LARGE_BUF,
7145 &next_seid, NULL);
7146 if (ret) {
7147 dev_info(&pf->pdev->dev,
7148 "get switch config failed %d aq_err=%x\n",
7149 ret, pf->hw.aq.asq_last_status);
7150 kfree(aq_buf);
7151 return -ENOENT;
7152 }
7153
7154 num_reported = le16_to_cpu(sw_config->header.num_reported);
7155 num_total = le16_to_cpu(sw_config->header.num_total);
7156
7157 if (printconfig)
7158 dev_info(&pf->pdev->dev,
7159 "header: %d reported %d total\n",
7160 num_reported, num_total);
7161
7162 if (num_reported) {
7163 int sz = sizeof(*sw_config) * num_reported;
7164
7165 kfree(pf->sw_config);
7166 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7167 if (pf->sw_config)
7168 memcpy(pf->sw_config, sw_config, sz);
7169 }
7170
7171 for (i = 0; i < num_reported; i++) {
7172 struct i40e_aqc_switch_config_element_resp *ele =
7173 &sw_config->element[i];
7174
7175 i40e_setup_pf_switch_element(pf, ele, num_reported,
7176 printconfig);
7177 }
7178 } while (next_seid != 0);
7179
7180 kfree(aq_buf);
7181 return ret;
7182}
7183
7184/**
7185 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7186 * @pf: board private structure
bc7d338f 7187 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7188 *
7189 * Returns 0 on success, negative value on failure
7190 **/
bc7d338f 7191static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7192{
895106a5 7193 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7194 int ret;
7195
7196 /* find out what's out there already */
7197 ret = i40e_fetch_switch_configuration(pf, false);
7198 if (ret) {
7199 dev_info(&pf->pdev->dev,
7200 "couldn't fetch switch config, err %d, aq_err %d\n",
7201 ret, pf->hw.aq.asq_last_status);
7202 return ret;
7203 }
7204 i40e_pf_reset_stats(pf);
7205
7206 /* fdir VSI must happen first to be sure it gets queue 0, but only
7207 * if there is enough room for the fdir VSI
7208 */
7209 if (pf->num_lan_qps > 1)
7210 i40e_fdir_setup(pf);
7211
7212 /* first time setup */
bc7d338f 7213 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7214 struct i40e_vsi *vsi = NULL;
7215 u16 uplink_seid;
7216
7217 /* Set up the PF VSI associated with the PF's main VSI
7218 * that is already in the HW switch
7219 */
7220 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7221 uplink_seid = pf->veb[pf->lan_veb]->seid;
7222 else
7223 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7224 if (pf->lan_vsi == I40E_NO_VSI)
7225 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7226 else if (reinit)
7227 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7228 if (!vsi) {
7229 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7230 i40e_fdir_teardown(pf);
7231 return -EAGAIN;
7232 }
7233 /* accommodate kcompat by copying the main VSI queue count
7234 * into the pf, since this newer code pushes the pf queue
7235 * info down a level into a VSI
7236 */
ac6c5e3d
SN		 7237 pf->num_rx_queues = vsi->num_queue_pairs;
7238 pf->num_tx_queues = vsi->num_queue_pairs;
41c445ff
JB		 7239 } else {
7240 /* force a reset of TC and queue layout configurations */
7241 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7242 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7243 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7244 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7245 }
7246 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7247
7248 /* Setup static PF queue filter control settings */
7249 ret = i40e_setup_pf_filter_control(pf);
7250 if (ret) {
7251 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7252 ret);
7253 /* Failure here should not stop continuing other steps */
7254 }
7255
7256 /* enable RSS in the HW, even for only one queue, as the stack can use
7257 * the hash
7258 */
7259 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7260 i40e_config_rss(pf);
7261
7262 /* fill in link information and enable LSE reporting */
7263 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7264 i40e_link_event(pf);
7265
d52c20b7 7266 /* Initialize user-specific link properties */
41c445ff
JB		 7267 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7268 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7269 /* requested_mode is set in probe or by ethtool */
7270 if (!pf->fc_autoneg_status)
7271 goto no_autoneg;
7272
7273 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7274 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7275 pf->hw.fc.current_mode = I40E_FC_FULL;
7276 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7277 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7278 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7279 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7280 else
d52c20b7
JB		 7281 pf->hw.fc.current_mode = I40E_FC_NONE;
7282
7283 /* sync the flow control settings with the auto-neg values */
7284 switch (pf->hw.fc.current_mode) {
7285 case I40E_FC_FULL:
7286 txfc = 1;
7287 rxfc = 1;
7288 break;
7289 case I40E_FC_TX_PAUSE:
7290 txfc = 1;
7291 rxfc = 0;
7292 break;
7293 case I40E_FC_RX_PAUSE:
7294 txfc = 0;
7295 rxfc = 1;
7296 break;
7297 case I40E_FC_NONE:
7298 case I40E_FC_DEFAULT:
7299 txfc = 0;
7300 rxfc = 0;
7301 break;
7302 case I40E_FC_PFC:
7303 /* TBD */
7304 break;
7305 /* no default case, we have to handle all possibilities here */
7306 }
7307
7308 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7309
7310 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7311 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7312 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7313
7314 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7315
d52c20b7
JB		 7316 goto fc_complete;
7317
7318no_autoneg:
7319 /* disable L2 flow control, user can turn it on if they wish */
7320 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7321 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7322 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7323
7324fc_complete:
41c445ff
JB		 7325 return ret;
7326}
7327
7328/**
7329 * i40e_set_rss_size - helper to set rss_size
7330 * @pf: board private structure
7331 * @queues_left: how many queues
7332 */
7333static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7334{
7335 int num_tc0;
7336
7337 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7338 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7339 num_tc0 = rounddown_pow_of_two(num_tc0);
7340
7341 return num_tc0;
7342}
7343
7344/**
7345 * i40e_determine_queue_usage - Work out queue distribution
7346 * @pf: board private structure
7347 **/
7348static void i40e_determine_queue_usage(struct i40e_pf *pf)
7349{
7350 int accum_tc_size;
7351 int queues_left;
7352
7353 pf->num_lan_qps = 0;
7354 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7355 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7356
7357 /* Find the max queues to be put into basic use. We'll always be
7358 * using TC0, whether or not DCB is running, and TC0 will get the
7359 * big RSS set.
7360 */
7361 queues_left = pf->hw.func_caps.num_tx_qp;
7362
7363 if (!((pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7364 (pf->flags & I40E_FLAG_MQ_ENABLED)) ||
7365 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7366 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7367 (queues_left == 1)) {
7368
7369 /* one qp for PF, no queues for anything else */
7370 queues_left = 0;
7371 pf->rss_size = pf->num_lan_qps = 1;
7372
7373 /* make sure all the fancies are disabled */
7374 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
7375 I40E_FLAG_MQ_ENABLED |
7376 I40E_FLAG_FDIR_ENABLED |
7377 I40E_FLAG_FDIR_ATR_ENABLED |
7378 I40E_FLAG_DCB_ENABLED |
7379 I40E_FLAG_SRIOV_ENABLED |
7380 I40E_FLAG_VMDQ_ENABLED);
7381
7382 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7383 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7384 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7385
7386 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7387
7388 queues_left -= pf->rss_size;
f8ff1464 7389 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7390
7391 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7392 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7393 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7394
7395 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7396 * are set up for RSS in TC0
7397 */
7398 queues_left -= accum_tc_size;
7399
7400 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7401
7402 queues_left -= pf->rss_size;
7403 if (queues_left < 0) {
7404 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7405 return;
7406 }
7407
f8ff1464 7408 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7409
7410 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7411 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7412 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7413
7414 queues_left -= 1; /* save 1 queue for FD */
7415
7416 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7417
7418 queues_left -= pf->rss_size;
7419 if (queues_left < 0) {
7420 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7421 return;
7422 }
7423
f8ff1464 7424 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7425
7426 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7427 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7428 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7429
7430 /* save 1 queue for TCs 1 thru 7,
7431 * 1 queue for flow director,
7432 * and the rest are set up for RSS in TC0
7433 */
7434 queues_left -= 1;
7435 queues_left -= accum_tc_size;
7436
7437 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7438 queues_left -= pf->rss_size;
7439 if (queues_left < 0) {
7440 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7441 return;
7442 }
7443
f8ff1464 7444 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7445
7446 } else {
7447 dev_info(&pf->pdev->dev,
7448 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7449 return;
7450 }
7451
7452 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7453 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7454 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7455 pf->num_vf_qps));
7456 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7457 }
7458
7459 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7460 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7461 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7462 (queues_left / pf->num_vmdq_qps));
7463 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7464 }
7465
f8ff1464 7466 pf->queues_left = queues_left;
41c445ff
JB		 7467 return;
7468}
7469
7470/**
7471 * i40e_setup_pf_filter_control - Setup PF static filter control
7472 * @pf: PF to be setup
7473 *
7474 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7475 * settings. If PE/FCoE are enabled then it will also set the per PF
7476 * based filter sizes required for them. It also enables Flow director,
7477 * ethertype and macvlan type filter settings for the pf.
7478 *
7479 * Returns 0 on success, negative on failure
7480 **/
7481static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7482{
7483 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7484
7485 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7486
7487 /* Flow Director is enabled */
7488 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7489 settings->enable_fdir = true;
7490
7491 /* Ethtype and MACVLAN filters enabled for PF */
7492 settings->enable_ethtype = true;
7493 settings->enable_macvlan = true;
7494
7495 if (i40e_set_filter_control(&pf->hw, settings))
7496 return -ENOENT;
7497
7498 return 0;
7499}
7500
7501/**
7502 * i40e_probe - Device initialization routine
7503 * @pdev: PCI device information struct
7504 * @ent: entry in i40e_pci_tbl
7505 *
7506 * i40e_probe initializes a pf identified by a pci_dev structure.
7507 * The OS initialization, configuring of the pf private structure,
7508 * and a hardware reset occur.
7509 *
7510 * Returns 0 on success, negative on failure
7511 **/
7512static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7513{
7514 struct i40e_driver_version dv;
7515 struct i40e_pf *pf;
7516 struct i40e_hw *hw;
93cd765b 7517 static u16 pfs_found;
d4dfb81a 7518 u16 link_status;
41c445ff
JB		 7519 int err = 0;
7520 u32 len;
7521
7522 err = pci_enable_device_mem(pdev);
7523 if (err)
7524 return err;
7525
7526 /* set up for high or low dma */
7527 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7528 /* coherent mask for the same size will always succeed if
7529 * dma_set_mask does
7530 */
7531 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7532 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7533 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7534 } else {
7535 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7536 err = -EIO;
7537 goto err_dma;
7538 }
7539
7540 /* set up pci connections */
7541 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7542 IORESOURCE_MEM), i40e_driver_name);
7543 if (err) {
7544 dev_info(&pdev->dev,
7545 "pci_request_selected_regions failed %d\n", err);
7546 goto err_pci_reg;
7547 }
7548
7549 pci_enable_pcie_error_reporting(pdev);
7550 pci_set_master(pdev);
7551
7552 /* Now that we have a PCI connection, we need to do the
7553 * low level device setup. This is primarily setting up
7554 * the Admin Queue structures and then querying for the
7555 * device's current profile information.
7556 */
7557 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7558 if (!pf) {
7559 err = -ENOMEM;
7560 goto err_pf_alloc;
7561 }
7562 pf->next_vsi = 0;
7563 pf->pdev = pdev;
7564 set_bit(__I40E_DOWN, &pf->state);
7565
7566 hw = &pf->hw;
7567 hw->back = pf;
7568 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7569 pci_resource_len(pdev, 0));
7570 if (!hw->hw_addr) {
7571 err = -EIO;
7572 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7573 (unsigned int)pci_resource_start(pdev, 0),
7574 (unsigned int)pci_resource_len(pdev, 0), err);
7575 goto err_ioremap;
7576 }
7577 hw->vendor_id = pdev->vendor;
7578 hw->device_id = pdev->device;
7579 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7580 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7581 hw->subsystem_device_id = pdev->subsystem_device;
7582 hw->bus.device = PCI_SLOT(pdev->devfn);
7583 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7584 pf->instance = pfs_found;
41c445ff 7585
7134f9ce
JB		 7586 /* do a special CORER for clearing PXE mode once at init */
7587 if (hw->revision_id == 0 &&
7588 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7589 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7590 i40e_flush(hw);
7591 msleep(200);
7592 pf->corer_count++;
7593
7594 i40e_clear_pxe_mode(hw);
7595 }
7596
41c445ff
JB		 7597 /* Reset here to make sure all is clean and to define PF 'n' */
7598 err = i40e_pf_reset(hw);
7599 if (err) {
7600 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7601 goto err_pf_reset;
7602 }
7603 pf->pfr_count++;
7604
7605 hw->aq.num_arq_entries = I40E_AQ_LEN;
7606 hw->aq.num_asq_entries = I40E_AQ_LEN;
7607 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7608 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7609 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7610 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7611 "%s-pf%d:misc",
7612 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7613
7614 err = i40e_init_shared_code(hw);
7615 if (err) {
7616 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7617 goto err_pf_reset;
7618 }
7619
d52c20b7
JB		 7620 /* set up a default setting for link flow control */
7621 pf->hw.fc.requested_mode = I40E_FC_NONE;
7622
41c445ff
JB		 7623 err = i40e_init_adminq(hw);
7624 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7625 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7626 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7627 dev_info(&pdev->dev,
7628 "warning: NVM version not supported, supported version: %02x.%02x\n",
7629 I40E_CURRENT_NVM_VERSION_HI,
7630 I40E_CURRENT_NVM_VERSION_LO);
7631 }
41c445ff
JB		 7632 if (err) {
7633 dev_info(&pdev->dev,
7634 "init_adminq failed: %d expecting API %02x.%02x\n",
7635 err,
7636 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7637 goto err_pf_reset;
7638 }
7639
7640 err = i40e_get_capabilities(pf);
7641 if (err)
7642 goto err_adminq_setup;
7643
7644 err = i40e_sw_init(pf);
7645 if (err) {
7646 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7647 goto err_sw_init;
7648 }
7649
7650 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7651 hw->func_caps.num_rx_qp,
7652 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7653 if (err) {
7654 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7655 goto err_init_lan_hmc;
7656 }
7657
7658 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7659 if (err) {
7660 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7661 err = -ENOENT;
7662 goto err_configure_lan_hmc;
7663 }
7664
7665 i40e_get_mac_addr(hw, hw->mac.addr);
7666 if (i40e_validate_mac_addr(hw->mac.addr)) {
7667 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7668 err = -EIO;
7669 goto err_mac_addr;
7670 }
7671 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7672 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7673
7674 pci_set_drvdata(pdev, pf);
7675 pci_save_state(pdev);
7676
7677 /* set up periodic task facility */
7678 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7679 pf->service_timer_period = HZ;
7680
7681 INIT_WORK(&pf->service_task, i40e_service_task);
7682 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7683 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7684 pf->link_check_timeout = jiffies;
7685
8e2773ae
SN		 7686 /* WoL defaults to disabled */
7687 pf->wol_en = false;
7688 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7689
41c445ff
JB		 7690 /* set up the main switch operations */
7691 i40e_determine_queue_usage(pf);
7692 i40e_init_interrupt_scheme(pf);
7693
7694 /* Set up the *vsi struct based on the number of VSIs in the HW,
7695 * and set up our local tracking of the MAIN PF vsi.
7696 */
7697 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7698 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7699 if (!pf->vsi) {
7700 err = -ENOMEM;
41c445ff 7701 goto err_switch_setup;
ed87ac09 7702 }
41c445ff 7703
bc7d338f 7704 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7705 if (err) {
7706 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7707 goto err_vsis;
7708 }
7709
7710 /* The main driver is (mostly) up and happy. We need to set this state
7711 * before setting up the misc vector or we get a race and the vector
7712 * ends up disabled forever.
7713 */
7714 clear_bit(__I40E_DOWN, &pf->state);
7715
7716 /* In case of MSIX we are going to setup the misc vector right here
7717 * to handle admin queue events etc. In case of legacy and MSI
7718 * the misc functionality and queue processing is combined in
7719 * the same vector and that gets setup at open.
7720 */
7721 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7722 err = i40e_setup_misc_vector(pf);
7723 if (err) {
7724 dev_info(&pdev->dev,
7725 "setup of misc vector failed: %d\n", err);
7726 goto err_vsis;
7727 }
7728 }
7729
7730 /* prep for VF support */
7731 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7732 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7733 u32 val;
7734
7735 /* disable link interrupts for VFs */
7736 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7737 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7738 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7739 i40e_flush(hw);
7740 }
7741
93cd765b
ASJ		 7742 pfs_found++;
7743
41c445ff
JB		 7744 i40e_dbg_pf_init(pf);
7745
7746 /* tell the firmware that we're starting */
7747 dv.major_version = DRV_VERSION_MAJOR;
7748 dv.minor_version = DRV_VERSION_MINOR;
7749 dv.build_version = DRV_VERSION_BUILD;
7750 dv.subbuild_version = 0;
7751 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7752
7753 /* since everything's happy, start the service_task timer */
7754 mod_timer(&pf->service_timer,
7755 round_jiffies(jiffies + pf->service_timer_period));
7756
d4dfb81a
CS		 7757 /* Get the negotiated link width and speed from PCI config space */
7758 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7759
7760 i40e_set_pci_config_data(hw, link_status);
7761
7762 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7763 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7764 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7765 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7766 "Unknown"),
7767 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7768 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7769 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7770 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7771 "Unknown"));
7772
7773 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7774 hw->bus.speed < i40e_bus_speed_8000) {
7775 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7776 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7777 }
7778
41c445ff
JB		 7779 return 0;
7780
7781 /* Unwind what we've done if something failed in the setup */
7782err_vsis:
7783 set_bit(__I40E_DOWN, &pf->state);
7784err_switch_setup:
7785 i40e_clear_interrupt_scheme(pf);
7786 kfree(pf->vsi);
7787 del_timer_sync(&pf->service_timer);
7788err_mac_addr:
7789err_configure_lan_hmc:
7790 (void)i40e_shutdown_lan_hmc(hw);
7791err_init_lan_hmc:
7792 kfree(pf->qp_pile);
7793 kfree(pf->irq_pile);
7794err_sw_init:
7795err_adminq_setup:
7796 (void)i40e_shutdown_adminq(hw);
7797err_pf_reset:
7798 iounmap(hw->hw_addr);
7799err_ioremap:
7800 kfree(pf);
7801err_pf_alloc:
7802 pci_disable_pcie_error_reporting(pdev);
7803 pci_release_selected_regions(pdev,
7804 pci_select_bars(pdev, IORESOURCE_MEM));
7805err_pci_reg:
7806err_dma:
7807 pci_disable_device(pdev);
7808 return err;
7809}
7810
7811/**
7812 * i40e_remove - Device removal routine
7813 * @pdev: PCI device information struct
7814 *
7815 * i40e_remove is called by the PCI subsystem to alert the driver
7816 * that is should release a PCI device. This could be caused by a
7817 * Hot-Plug event, or because the driver is going to be removed from
7818 * memory.
7819 **/
7820static void i40e_remove(struct pci_dev *pdev)
7821{
7822 struct i40e_pf *pf = pci_get_drvdata(pdev);
7823 i40e_status ret_code;
7824 u32 reg;
7825 int i;
7826
7827 i40e_dbg_pf_exit(pf);
7828
7829 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7830 i40e_free_vfs(pf);
7831 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7832 }
7833
7834 /* no more scheduling of any task */
7835 set_bit(__I40E_DOWN, &pf->state);
7836 del_timer_sync(&pf->service_timer);
7837 cancel_work_sync(&pf->service_task);
7838
7839 i40e_fdir_teardown(pf);
7840
7841 /* If there is a switch structure or any orphans, remove them.
7842 * This will leave only the PF's VSI remaining.
7843 */
7844 for (i = 0; i < I40E_MAX_VEB; i++) {
7845 if (!pf->veb[i])
7846 continue;
7847
7848 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7849 pf->veb[i]->uplink_seid == 0)
7850 i40e_switch_branch_release(pf->veb[i]);
7851 }
7852
7853 /* Now we can shutdown the PF's VSI, just before we kill
7854 * adminq and hmc.
7855 */
7856 if (pf->vsi[pf->lan_vsi])
7857 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7858
7859 i40e_stop_misc_vector(pf);
7860 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7861 synchronize_irq(pf->msix_entries[0].vector);
7862 free_irq(pf->msix_entries[0].vector, pf);
7863 }
7864
7865 /* shutdown and destroy the HMC */
7866 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7867 if (ret_code)
7868 dev_warn(&pdev->dev,
7869 "Failed to destroy the HMC resources: %d\n", ret_code);
7870
7871 /* shutdown the adminq */
7872 i40e_aq_queue_shutdown(&pf->hw, true);
7873 ret_code = i40e_shutdown_adminq(&pf->hw);
7874 if (ret_code)
7875 dev_warn(&pdev->dev,
7876 "Failed to destroy the Admin Queue resources: %d\n",
7877 ret_code);
7878
7879 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7880 i40e_clear_interrupt_scheme(pf);
7881 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7882 if (pf->vsi[i]) {
7883 i40e_vsi_clear_rings(pf->vsi[i]);
7884 i40e_vsi_clear(pf->vsi[i]);
7885 pf->vsi[i] = NULL;
7886 }
7887 }
7888
7889 for (i = 0; i < I40E_MAX_VEB; i++) {
7890 kfree(pf->veb[i]);
7891 pf->veb[i] = NULL;
7892 }
7893
7894 kfree(pf->qp_pile);
7895 kfree(pf->irq_pile);
7896 kfree(pf->sw_config);
7897 kfree(pf->vsi);
7898
7899 /* force a PF reset to clean anything leftover */
7900 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7901 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7902 i40e_flush(&pf->hw);
7903
7904 iounmap(pf->hw.hw_addr);
7905 kfree(pf);
7906 pci_release_selected_regions(pdev,
7907 pci_select_bars(pdev, IORESOURCE_MEM));
7908
7909 pci_disable_pcie_error_reporting(pdev);
7910 pci_disable_device(pdev);
7911}
7912
7913/**
7914 * i40e_pci_error_detected - warning that something funky happened in PCI land
7915 * @pdev: PCI device information struct
7916 *
7917 * Called to warn that something happened and the error handling steps
7918 * are in progress. Allows the driver to quiesce things, be ready for
7919 * remediation.
7920 **/
7921static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7922 enum pci_channel_state error)
7923{
7924 struct i40e_pf *pf = pci_get_drvdata(pdev);
7925
7926 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7927
7928 /* shutdown all operations */
9007bccd
SN		 7929 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7930 rtnl_lock();
7931 i40e_prep_for_reset(pf);
7932 rtnl_unlock();
7933 }
41c445ff
JB		 7934
7935 /* Request a slot reset */
7936 return PCI_ERS_RESULT_NEED_RESET;
7937}
7938
7939/**
7940 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7941 * @pdev: PCI device information struct
7942 *
7943 * Called to find if the driver can work with the device now that
7944 * the pci slot has been reset. If a basic connection seems good
7945 * (registers are readable and have sane content) then return a
7946 * happy little PCI_ERS_RESULT_xxx.
7947 **/
7948static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7949{
7950 struct i40e_pf *pf = pci_get_drvdata(pdev);
7951 pci_ers_result_t result;
7952 int err;
7953 u32 reg;
7954
7955 dev_info(&pdev->dev, "%s\n", __func__);
7956 if (pci_enable_device_mem(pdev)) {
7957 dev_info(&pdev->dev,
7958 "Cannot re-enable PCI device after reset.\n");
7959 result = PCI_ERS_RESULT_DISCONNECT;
7960 } else {
7961 pci_set_master(pdev);
7962 pci_restore_state(pdev);
7963 pci_save_state(pdev);
7964 pci_wake_from_d3(pdev, false);
7965
7966 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7967 if (reg == 0)
7968 result = PCI_ERS_RESULT_RECOVERED;
7969 else
7970 result = PCI_ERS_RESULT_DISCONNECT;
7971 }
7972
7973 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7974 if (err) {
7975 dev_info(&pdev->dev,
7976 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7977 err);
7978 /* non-fatal, continue */
7979 }
7980
7981 return result;
7982}
7983
7984/**
7985 * i40e_pci_error_resume - restart operations after PCI error recovery
7986 * @pdev: PCI device information struct
7987 *
7988 * Called to allow the driver to bring things back up after PCI error
7989 * and/or reset recovery has finished.
7990 **/
7991static void i40e_pci_error_resume(struct pci_dev *pdev)
7992{
7993 struct i40e_pf *pf = pci_get_drvdata(pdev);
7994
7995 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 7996 if (test_bit(__I40E_SUSPENDED, &pf->state))
7997 return;
7998
7999 rtnl_lock();
41c445ff 8000 i40e_handle_reset_warning(pf);
9007bccd
SN		 8001 rtnl_lock();
8002}
8003
8004/**
8005 * i40e_shutdown - PCI callback for shutting down
8006 * @pdev: PCI device information struct
8007 **/
8008static void i40e_shutdown(struct pci_dev *pdev)
8009{
8010 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8011 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8012
8013 set_bit(__I40E_SUSPENDED, &pf->state);
8014 set_bit(__I40E_DOWN, &pf->state);
8015 rtnl_lock();
8016 i40e_prep_for_reset(pf);
8017 rtnl_unlock();
8018
8e2773ae
SN		 8019 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8020 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8021
9007bccd 8022 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8023 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8024 pci_set_power_state(pdev, PCI_D3hot);
8025 }
8026}
8027
8028#ifdef CONFIG_PM
8029/**
8030 * i40e_suspend - PCI callback for moving to D3
8031 * @pdev: PCI device information struct
8032 **/
8033static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8034{
8035 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8036 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8037
8038 set_bit(__I40E_SUSPENDED, &pf->state);
8039 set_bit(__I40E_DOWN, &pf->state);
8040 rtnl_lock();
8041 i40e_prep_for_reset(pf);
8042 rtnl_unlock();
8043
8e2773ae
SN		 8044 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8045 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8046
8047 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8048 pci_set_power_state(pdev, PCI_D3hot);
8049
8050 return 0;
41c445ff
JB		 8051}
8052
9007bccd
SN		 8053/**
8054 * i40e_resume - PCI callback for waking up from D3
8055 * @pdev: PCI device information struct
8056 **/
8057static int i40e_resume(struct pci_dev *pdev)
8058{
8059 struct i40e_pf *pf = pci_get_drvdata(pdev);
8060 u32 err;
8061
8062 pci_set_power_state(pdev, PCI_D0);
8063 pci_restore_state(pdev);
8064 /* pci_restore_state() clears dev->state_saves, so
8065 * call pci_save_state() again to restore it.
8066 */
8067 pci_save_state(pdev);
8068
8069 err = pci_enable_device_mem(pdev);
8070 if (err) {
8071 dev_err(&pdev->dev,
8072 "%s: Cannot enable PCI device from suspend\n",
8073 __func__);
8074 return err;
8075 }
8076 pci_set_master(pdev);
8077
8078 /* no wakeup events while running */
8079 pci_wake_from_d3(pdev, false);
8080
8081 /* handling the reset will rebuild the device state */
8082 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8083 clear_bit(__I40E_DOWN, &pf->state);
8084 rtnl_lock();
8085 i40e_reset_and_rebuild(pf, false);
8086 rtnl_unlock();
8087 }
8088
8089 return 0;
8090}
8091
8092#endif
41c445ff
JB		 8093static const struct pci_error_handlers i40e_err_handler = {
8094 .error_detected = i40e_pci_error_detected,
8095 .slot_reset = i40e_pci_error_slot_reset,
8096 .resume = i40e_pci_error_resume,
8097};
8098
8099static struct pci_driver i40e_driver = {
8100 .name = i40e_driver_name,
8101 .id_table = i40e_pci_tbl,
8102 .probe = i40e_probe,
8103 .remove = i40e_remove,
9007bccd
SN		 8104#ifdef CONFIG_PM
8105 .suspend = i40e_suspend,
8106 .resume = i40e_resume,
8107#endif
8108 .shutdown = i40e_shutdown,
41c445ff
JB		 8109 .err_handler = &i40e_err_handler,
8110 .sriov_configure = i40e_pci_sriov_configure,
8111};
8112
8113/**
8114 * i40e_init_module - Driver registration routine
8115 *
8116 * i40e_init_module is the first routine called when the driver is
8117 * loaded. All it does is register with the PCI subsystem.
8118 **/
8119static int __init i40e_init_module(void)
8120{
8121 pr_info("%s: %s - version %s\n", i40e_driver_name,
8122 i40e_driver_string, i40e_driver_version_str);
8123 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8124 i40e_dbg_init();
8125 return pci_register_driver(&i40e_driver);
8126}
8127module_init(i40e_init_module);
8128
8129/**
8130 * i40e_exit_module - Driver exit cleanup routine
8131 *
8132 * i40e_exit_module is called just before the driver is removed
8133 * from memory.
8134 **/
8135static void __exit i40e_exit_module(void)
8136{
8137 pci_unregister_driver(&i40e_driver);
8138 i40e_dbg_exit();
8139}
8140module_exit(i40e_exit_module);
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