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fd0a05ce JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
dc641b73 | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
fd0a05ce JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
fd0a05ce JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
1c112a64 | 27 | #include <linux/prefetch.h> |
fd0a05ce | 28 | #include "i40e.h" |
206812b5 | 29 | #include "i40e_prototype.h" |
fd0a05ce JB |
30 | |
31 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
32 | u32 td_tag) | |
33 | { | |
34 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
35 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
36 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
37 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
38 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
39 | } | |
40 | ||
eaefbd06 | 41 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) |
49d7d933 | 42 | #define I40E_FD_CLEAN_DELAY 10 |
fd0a05ce JB |
43 | /** |
44 | * i40e_program_fdir_filter - Program a Flow Director filter | |
17a73f6b JG |
45 | * @fdir_data: Packet data that will be filter parameters |
46 | * @raw_packet: the pre-allocated packet buffer for FDir | |
fd0a05ce JB |
47 | * @pf: The pf pointer |
48 | * @add: True for add/update, False for remove | |
49 | **/ | |
17a73f6b | 50 | int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet, |
fd0a05ce JB |
51 | struct i40e_pf *pf, bool add) |
52 | { | |
53 | struct i40e_filter_program_desc *fdir_desc; | |
49d7d933 | 54 | struct i40e_tx_buffer *tx_buf, *first; |
fd0a05ce JB |
55 | struct i40e_tx_desc *tx_desc; |
56 | struct i40e_ring *tx_ring; | |
eaefbd06 | 57 | unsigned int fpt, dcc; |
fd0a05ce JB |
58 | struct i40e_vsi *vsi; |
59 | struct device *dev; | |
60 | dma_addr_t dma; | |
61 | u32 td_cmd = 0; | |
49d7d933 | 62 | u16 delay = 0; |
fd0a05ce JB |
63 | u16 i; |
64 | ||
65 | /* find existing FDIR VSI */ | |
66 | vsi = NULL; | |
505682cd | 67 | for (i = 0; i < pf->num_alloc_vsi; i++) |
fd0a05ce JB |
68 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) |
69 | vsi = pf->vsi[i]; | |
70 | if (!vsi) | |
71 | return -ENOENT; | |
72 | ||
9f65e15b | 73 | tx_ring = vsi->tx_rings[0]; |
fd0a05ce JB |
74 | dev = tx_ring->dev; |
75 | ||
49d7d933 ASJ |
76 | /* we need two descriptors to add/del a filter and we can wait */ |
77 | do { | |
78 | if (I40E_DESC_UNUSED(tx_ring) > 1) | |
79 | break; | |
80 | msleep_interruptible(1); | |
81 | delay++; | |
82 | } while (delay < I40E_FD_CLEAN_DELAY); | |
83 | ||
84 | if (!(I40E_DESC_UNUSED(tx_ring) > 1)) | |
85 | return -EAGAIN; | |
86 | ||
17a73f6b JG |
87 | dma = dma_map_single(dev, raw_packet, |
88 | I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); | |
fd0a05ce JB |
89 | if (dma_mapping_error(dev, dma)) |
90 | goto dma_fail; | |
91 | ||
92 | /* grab the next descriptor */ | |
fc4ac67b AD |
93 | i = tx_ring->next_to_use; |
94 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
49d7d933 ASJ |
95 | first = &tx_ring->tx_bi[i]; |
96 | memset(first, 0, sizeof(struct i40e_tx_buffer)); | |
fc4ac67b | 97 | |
49d7d933 | 98 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
fd0a05ce | 99 | |
eaefbd06 JB |
100 | fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & |
101 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
fd0a05ce | 102 | |
eaefbd06 JB |
103 | fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) & |
104 | I40E_TXD_FLTR_QW0_FLEXOFF_MASK; | |
fd0a05ce | 105 | |
eaefbd06 JB |
106 | fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) & |
107 | I40E_TXD_FLTR_QW0_PCTYPE_MASK; | |
fd0a05ce JB |
108 | |
109 | /* Use LAN VSI Id if not programmed by user */ | |
110 | if (fdir_data->dest_vsi == 0) | |
eaefbd06 JB |
111 | fpt |= (pf->vsi[pf->lan_vsi]->id) << |
112 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
fd0a05ce | 113 | else |
eaefbd06 JB |
114 | fpt |= ((u32)fdir_data->dest_vsi << |
115 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) & | |
116 | I40E_TXD_FLTR_QW0_DEST_VSI_MASK; | |
117 | ||
eaefbd06 | 118 | dcc = I40E_TX_DESC_DTYPE_FILTER_PROG; |
fd0a05ce JB |
119 | |
120 | if (add) | |
eaefbd06 JB |
121 | dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << |
122 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
fd0a05ce | 123 | else |
eaefbd06 JB |
124 | dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
125 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
fd0a05ce | 126 | |
eaefbd06 JB |
127 | dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) & |
128 | I40E_TXD_FLTR_QW1_DEST_MASK; | |
fd0a05ce | 129 | |
eaefbd06 JB |
130 | dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) & |
131 | I40E_TXD_FLTR_QW1_FD_STATUS_MASK; | |
fd0a05ce JB |
132 | |
133 | if (fdir_data->cnt_index != 0) { | |
eaefbd06 JB |
134 | dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
135 | dcc |= ((u32)fdir_data->cnt_index << | |
136 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
433c47de | 137 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; |
fd0a05ce JB |
138 | } |
139 | ||
99753ea6 JB |
140 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt); |
141 | fdir_desc->rsvd = cpu_to_le32(0); | |
eaefbd06 | 142 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc); |
fd0a05ce JB |
143 | fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id); |
144 | ||
145 | /* Now program a dummy descriptor */ | |
fc4ac67b AD |
146 | i = tx_ring->next_to_use; |
147 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
298deef1 | 148 | tx_buf = &tx_ring->tx_bi[i]; |
fc4ac67b | 149 | |
49d7d933 ASJ |
150 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
151 | ||
152 | memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); | |
fd0a05ce | 153 | |
298deef1 | 154 | /* record length, and DMA address */ |
17a73f6b | 155 | dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); |
298deef1 ASJ |
156 | dma_unmap_addr_set(tx_buf, dma, dma); |
157 | ||
fd0a05ce | 158 | tx_desc->buffer_addr = cpu_to_le64(dma); |
eaefbd06 | 159 | td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; |
fd0a05ce | 160 | |
49d7d933 ASJ |
161 | tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; |
162 | tx_buf->raw_buf = (void *)raw_packet; | |
163 | ||
fd0a05ce | 164 | tx_desc->cmd_type_offset_bsz = |
17a73f6b | 165 | build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); |
fd0a05ce | 166 | |
298deef1 ASJ |
167 | /* set the timestamp */ |
168 | tx_buf->time_stamp = jiffies; | |
169 | ||
fd0a05ce | 170 | /* Force memory writes to complete before letting h/w |
49d7d933 | 171 | * know there are new descriptors to fetch. |
fd0a05ce JB |
172 | */ |
173 | wmb(); | |
174 | ||
fc4ac67b | 175 | /* Mark the data descriptor to be watched */ |
49d7d933 | 176 | first->next_to_watch = tx_desc; |
fc4ac67b | 177 | |
fd0a05ce JB |
178 | writel(tx_ring->next_to_use, tx_ring->tail); |
179 | return 0; | |
180 | ||
181 | dma_fail: | |
182 | return -1; | |
183 | } | |
184 | ||
17a73f6b JG |
185 | #define IP_HEADER_OFFSET 14 |
186 | #define I40E_UDPIP_DUMMY_PACKET_LEN 42 | |
187 | /** | |
188 | * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters | |
189 | * @vsi: pointer to the targeted VSI | |
190 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
191 | * @add: true adds a filter, false removes it |
192 | * | |
193 | * Returns 0 if the filters were successfully added or removed | |
194 | **/ | |
195 | static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, | |
196 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 197 | bool add) |
17a73f6b JG |
198 | { |
199 | struct i40e_pf *pf = vsi->back; | |
200 | struct udphdr *udp; | |
201 | struct iphdr *ip; | |
202 | bool err = false; | |
49d7d933 | 203 | u8 *raw_packet; |
17a73f6b | 204 | int ret; |
17a73f6b JG |
205 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, |
206 | 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, | |
207 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
208 | ||
49d7d933 ASJ |
209 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
210 | if (!raw_packet) | |
211 | return -ENOMEM; | |
17a73f6b JG |
212 | memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); |
213 | ||
214 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
215 | udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET | |
216 | + sizeof(struct iphdr)); | |
217 | ||
218 | ip->daddr = fd_data->dst_ip[0]; | |
219 | udp->dest = fd_data->dst_port; | |
220 | ip->saddr = fd_data->src_ip[0]; | |
221 | udp->source = fd_data->src_port; | |
222 | ||
b2d36c03 KS |
223 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; |
224 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
225 | if (ret) { | |
226 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
227 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
228 | fd_data->pctype, fd_data->fd_id, ret); | |
b2d36c03 KS |
229 | err = true; |
230 | } else { | |
f7233c54 ASJ |
231 | if (add) |
232 | dev_info(&pf->pdev->dev, | |
233 | "Filter OK for PCTYPE %d loc = %d\n", | |
234 | fd_data->pctype, fd_data->fd_id); | |
235 | else | |
236 | dev_info(&pf->pdev->dev, | |
237 | "Filter deleted for PCTYPE %d loc = %d\n", | |
238 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b | 239 | } |
17a73f6b JG |
240 | return err ? -EOPNOTSUPP : 0; |
241 | } | |
242 | ||
243 | #define I40E_TCPIP_DUMMY_PACKET_LEN 54 | |
244 | /** | |
245 | * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters | |
246 | * @vsi: pointer to the targeted VSI | |
247 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
248 | * @add: true adds a filter, false removes it |
249 | * | |
250 | * Returns 0 if the filters were successfully added or removed | |
251 | **/ | |
252 | static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, | |
253 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 254 | bool add) |
17a73f6b JG |
255 | { |
256 | struct i40e_pf *pf = vsi->back; | |
257 | struct tcphdr *tcp; | |
258 | struct iphdr *ip; | |
259 | bool err = false; | |
49d7d933 | 260 | u8 *raw_packet; |
17a73f6b JG |
261 | int ret; |
262 | /* Dummy packet */ | |
263 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
264 | 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, | |
265 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, | |
266 | 0x0, 0x72, 0, 0, 0, 0}; | |
267 | ||
49d7d933 ASJ |
268 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
269 | if (!raw_packet) | |
270 | return -ENOMEM; | |
17a73f6b JG |
271 | memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); |
272 | ||
273 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
274 | tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET | |
275 | + sizeof(struct iphdr)); | |
276 | ||
277 | ip->daddr = fd_data->dst_ip[0]; | |
278 | tcp->dest = fd_data->dst_port; | |
279 | ip->saddr = fd_data->src_ip[0]; | |
280 | tcp->source = fd_data->src_port; | |
281 | ||
282 | if (add) { | |
1e1be8f6 | 283 | pf->fd_tcp_rule++; |
17a73f6b JG |
284 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) { |
285 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); | |
286 | pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; | |
287 | } | |
1e1be8f6 ASJ |
288 | } else { |
289 | pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ? | |
290 | (pf->fd_tcp_rule - 1) : 0; | |
291 | if (pf->fd_tcp_rule == 0) { | |
292 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
293 | dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); | |
294 | } | |
17a73f6b JG |
295 | } |
296 | ||
b2d36c03 | 297 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; |
17a73f6b JG |
298 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); |
299 | ||
300 | if (ret) { | |
301 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
302 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
303 | fd_data->pctype, fd_data->fd_id, ret); | |
17a73f6b JG |
304 | err = true; |
305 | } else { | |
f7233c54 ASJ |
306 | if (add) |
307 | dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", | |
308 | fd_data->pctype, fd_data->fd_id); | |
309 | else | |
310 | dev_info(&pf->pdev->dev, | |
311 | "Filter deleted for PCTYPE %d loc = %d\n", | |
312 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
313 | } |
314 | ||
17a73f6b JG |
315 | return err ? -EOPNOTSUPP : 0; |
316 | } | |
317 | ||
318 | /** | |
319 | * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for | |
320 | * a specific flow spec | |
321 | * @vsi: pointer to the targeted VSI | |
322 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
323 | * @add: true adds a filter, false removes it |
324 | * | |
21d3efdc | 325 | * Always returns -EOPNOTSUPP |
17a73f6b JG |
326 | **/ |
327 | static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, | |
328 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 329 | bool add) |
17a73f6b JG |
330 | { |
331 | return -EOPNOTSUPP; | |
332 | } | |
333 | ||
334 | #define I40E_IP_DUMMY_PACKET_LEN 34 | |
335 | /** | |
336 | * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for | |
337 | * a specific flow spec | |
338 | * @vsi: pointer to the targeted VSI | |
339 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
340 | * @add: true adds a filter, false removes it |
341 | * | |
342 | * Returns 0 if the filters were successfully added or removed | |
343 | **/ | |
344 | static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, | |
345 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 346 | bool add) |
17a73f6b JG |
347 | { |
348 | struct i40e_pf *pf = vsi->back; | |
349 | struct iphdr *ip; | |
350 | bool err = false; | |
49d7d933 | 351 | u8 *raw_packet; |
17a73f6b JG |
352 | int ret; |
353 | int i; | |
354 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
355 | 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, | |
356 | 0, 0, 0, 0}; | |
357 | ||
17a73f6b JG |
358 | for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; |
359 | i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { | |
49d7d933 ASJ |
360 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
361 | if (!raw_packet) | |
362 | return -ENOMEM; | |
363 | memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); | |
364 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
365 | ||
366 | ip->saddr = fd_data->src_ip[0]; | |
367 | ip->daddr = fd_data->dst_ip[0]; | |
368 | ip->protocol = 0; | |
369 | ||
17a73f6b JG |
370 | fd_data->pctype = i; |
371 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
372 | ||
373 | if (ret) { | |
374 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
375 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
376 | fd_data->pctype, fd_data->fd_id, ret); | |
17a73f6b JG |
377 | err = true; |
378 | } else { | |
f7233c54 ASJ |
379 | if (add) |
380 | dev_info(&pf->pdev->dev, | |
381 | "Filter OK for PCTYPE %d loc = %d\n", | |
382 | fd_data->pctype, fd_data->fd_id); | |
383 | else | |
384 | dev_info(&pf->pdev->dev, | |
385 | "Filter deleted for PCTYPE %d loc = %d\n", | |
386 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
387 | } |
388 | } | |
389 | ||
390 | return err ? -EOPNOTSUPP : 0; | |
391 | } | |
392 | ||
393 | /** | |
394 | * i40e_add_del_fdir - Build raw packets to add/del fdir filter | |
395 | * @vsi: pointer to the targeted VSI | |
396 | * @cmd: command to get or set RX flow classification rules | |
397 | * @add: true adds a filter, false removes it | |
398 | * | |
399 | **/ | |
400 | int i40e_add_del_fdir(struct i40e_vsi *vsi, | |
401 | struct i40e_fdir_filter *input, bool add) | |
402 | { | |
403 | struct i40e_pf *pf = vsi->back; | |
17a73f6b JG |
404 | int ret; |
405 | ||
17a73f6b JG |
406 | switch (input->flow_type & ~FLOW_EXT) { |
407 | case TCP_V4_FLOW: | |
49d7d933 | 408 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
409 | break; |
410 | case UDP_V4_FLOW: | |
49d7d933 | 411 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b JG |
412 | break; |
413 | case SCTP_V4_FLOW: | |
49d7d933 | 414 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); |
17a73f6b JG |
415 | break; |
416 | case IPV4_FLOW: | |
49d7d933 | 417 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b JG |
418 | break; |
419 | case IP_USER_FLOW: | |
420 | switch (input->ip4_proto) { | |
421 | case IPPROTO_TCP: | |
49d7d933 | 422 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
423 | break; |
424 | case IPPROTO_UDP: | |
49d7d933 | 425 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b JG |
426 | break; |
427 | case IPPROTO_SCTP: | |
49d7d933 | 428 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); |
17a73f6b JG |
429 | break; |
430 | default: | |
49d7d933 | 431 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b JG |
432 | break; |
433 | } | |
434 | break; | |
435 | default: | |
c5ffe7e1 | 436 | dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", |
17a73f6b JG |
437 | input->flow_type); |
438 | ret = -EINVAL; | |
439 | } | |
440 | ||
49d7d933 | 441 | /* The buffer allocated here is freed by the i40e_clean_tx_ring() */ |
17a73f6b JG |
442 | return ret; |
443 | } | |
444 | ||
fd0a05ce JB |
445 | /** |
446 | * i40e_fd_handle_status - check the Programming Status for FD | |
447 | * @rx_ring: the Rx ring for this descriptor | |
55a5e60b | 448 | * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. |
fd0a05ce JB |
449 | * @prog_id: the id originally used for programming |
450 | * | |
451 | * This is used to verify if the FD programming or invalidation | |
452 | * requested by SW to the HW is successful or not and take actions accordingly. | |
453 | **/ | |
55a5e60b ASJ |
454 | static void i40e_fd_handle_status(struct i40e_ring *rx_ring, |
455 | union i40e_rx_desc *rx_desc, u8 prog_id) | |
fd0a05ce | 456 | { |
55a5e60b ASJ |
457 | struct i40e_pf *pf = rx_ring->vsi->back; |
458 | struct pci_dev *pdev = pf->pdev; | |
459 | u32 fcnt_prog, fcnt_avail; | |
fd0a05ce | 460 | u32 error; |
55a5e60b | 461 | u64 qw; |
fd0a05ce | 462 | |
55a5e60b | 463 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
fd0a05ce JB |
464 | error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> |
465 | I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; | |
466 | ||
55a5e60b | 467 | if (error == (0x1 << I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { |
f7233c54 ASJ |
468 | if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || |
469 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
470 | dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", | |
471 | rx_desc->wb.qword0.hi_dword.fd_id); | |
55a5e60b | 472 | |
1e1be8f6 ASJ |
473 | pf->fd_add_err++; |
474 | /* store the current atr filter count */ | |
475 | pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); | |
476 | ||
55a5e60b | 477 | /* filter programming failed most likely due to table full */ |
12957388 ASJ |
478 | fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf); |
479 | fcnt_avail = pf->fdir_pf_filter_count; | |
55a5e60b ASJ |
480 | /* If ATR is running fcnt_prog can quickly change, |
481 | * if we are very close to full, it makes sense to disable | |
482 | * FD ATR/SB and then re-enable it when there is room. | |
483 | */ | |
484 | if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { | |
1e1be8f6 | 485 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
b814ba65 | 486 | !(pf->auto_disable_flags & |
b814ba65 | 487 | I40E_FLAG_FD_SB_ENABLED)) { |
55a5e60b ASJ |
488 | dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); |
489 | pf->auto_disable_flags |= | |
490 | I40E_FLAG_FD_SB_ENABLED; | |
55a5e60b ASJ |
491 | } |
492 | } else { | |
e99bdd39 | 493 | dev_info(&pdev->dev, |
f7233c54 | 494 | "FD filter programming failed due to incorrect filter parameters\n"); |
55a5e60b ASJ |
495 | } |
496 | } else if (error == | |
497 | (0x1 << I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { | |
13c2884f | 498 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
e99bdd39 | 499 | dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", |
13c2884f | 500 | rx_desc->wb.qword0.hi_dword.fd_id); |
55a5e60b | 501 | } |
fd0a05ce JB |
502 | } |
503 | ||
504 | /** | |
a5e9c572 | 505 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer |
fd0a05ce JB |
506 | * @ring: the ring that owns the buffer |
507 | * @tx_buffer: the buffer to free | |
508 | **/ | |
a5e9c572 AD |
509 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, |
510 | struct i40e_tx_buffer *tx_buffer) | |
fd0a05ce | 511 | { |
a5e9c572 | 512 | if (tx_buffer->skb) { |
49d7d933 ASJ |
513 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
514 | kfree(tx_buffer->raw_buf); | |
515 | else | |
516 | dev_kfree_skb_any(tx_buffer->skb); | |
517 | ||
a5e9c572 | 518 | if (dma_unmap_len(tx_buffer, len)) |
fd0a05ce | 519 | dma_unmap_single(ring->dev, |
35a1e2ad AD |
520 | dma_unmap_addr(tx_buffer, dma), |
521 | dma_unmap_len(tx_buffer, len), | |
fd0a05ce | 522 | DMA_TO_DEVICE); |
a5e9c572 AD |
523 | } else if (dma_unmap_len(tx_buffer, len)) { |
524 | dma_unmap_page(ring->dev, | |
525 | dma_unmap_addr(tx_buffer, dma), | |
526 | dma_unmap_len(tx_buffer, len), | |
527 | DMA_TO_DEVICE); | |
fd0a05ce | 528 | } |
a5e9c572 AD |
529 | tx_buffer->next_to_watch = NULL; |
530 | tx_buffer->skb = NULL; | |
35a1e2ad | 531 | dma_unmap_len_set(tx_buffer, len, 0); |
a5e9c572 | 532 | /* tx_buffer must be completely set up in the transmit path */ |
fd0a05ce JB |
533 | } |
534 | ||
535 | /** | |
536 | * i40e_clean_tx_ring - Free any empty Tx buffers | |
537 | * @tx_ring: ring to be cleaned | |
538 | **/ | |
539 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring) | |
540 | { | |
fd0a05ce JB |
541 | unsigned long bi_size; |
542 | u16 i; | |
543 | ||
544 | /* ring already cleared, nothing to do */ | |
545 | if (!tx_ring->tx_bi) | |
546 | return; | |
547 | ||
548 | /* Free all the Tx ring sk_buffs */ | |
a5e9c572 AD |
549 | for (i = 0; i < tx_ring->count; i++) |
550 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
fd0a05ce JB |
551 | |
552 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
553 | memset(tx_ring->tx_bi, 0, bi_size); | |
554 | ||
555 | /* Zero out the descriptor ring */ | |
556 | memset(tx_ring->desc, 0, tx_ring->size); | |
557 | ||
558 | tx_ring->next_to_use = 0; | |
559 | tx_ring->next_to_clean = 0; | |
7070ce0a AD |
560 | |
561 | if (!tx_ring->netdev) | |
562 | return; | |
563 | ||
564 | /* cleanup Tx queue statistics */ | |
565 | netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, | |
566 | tx_ring->queue_index)); | |
fd0a05ce JB |
567 | } |
568 | ||
569 | /** | |
570 | * i40e_free_tx_resources - Free Tx resources per queue | |
571 | * @tx_ring: Tx descriptor ring for a specific queue | |
572 | * | |
573 | * Free all transmit software resources | |
574 | **/ | |
575 | void i40e_free_tx_resources(struct i40e_ring *tx_ring) | |
576 | { | |
577 | i40e_clean_tx_ring(tx_ring); | |
578 | kfree(tx_ring->tx_bi); | |
579 | tx_ring->tx_bi = NULL; | |
580 | ||
581 | if (tx_ring->desc) { | |
582 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
583 | tx_ring->desc, tx_ring->dma); | |
584 | tx_ring->desc = NULL; | |
585 | } | |
586 | } | |
587 | ||
588 | /** | |
589 | * i40e_get_tx_pending - how many tx descriptors not processed | |
590 | * @tx_ring: the ring of descriptors | |
591 | * | |
592 | * Since there is no access to the ring head register | |
593 | * in XL710, we need to use our local copies | |
594 | **/ | |
595 | static u32 i40e_get_tx_pending(struct i40e_ring *ring) | |
596 | { | |
597 | u32 ntu = ((ring->next_to_clean <= ring->next_to_use) | |
598 | ? ring->next_to_use | |
599 | : ring->next_to_use + ring->count); | |
600 | return ntu - ring->next_to_clean; | |
601 | } | |
602 | ||
603 | /** | |
604 | * i40e_check_tx_hang - Is there a hang in the Tx queue | |
605 | * @tx_ring: the ring of descriptors | |
606 | **/ | |
607 | static bool i40e_check_tx_hang(struct i40e_ring *tx_ring) | |
608 | { | |
609 | u32 tx_pending = i40e_get_tx_pending(tx_ring); | |
810b3ae4 | 610 | struct i40e_pf *pf = tx_ring->vsi->back; |
fd0a05ce JB |
611 | bool ret = false; |
612 | ||
613 | clear_check_for_tx_hang(tx_ring); | |
614 | ||
615 | /* Check for a hung queue, but be thorough. This verifies | |
616 | * that a transmit has been completed since the previous | |
617 | * check AND there is at least one packet pending. The | |
618 | * ARMED bit is set to indicate a potential hang. The | |
619 | * bit is cleared if a pause frame is received to remove | |
620 | * false hang detection due to PFC or 802.3x frames. By | |
621 | * requiring this to fail twice we avoid races with | |
622 | * PFC clearing the ARMED bit and conditions where we | |
623 | * run the check_tx_hang logic with a transmit completion | |
624 | * pending but without time to complete it yet. | |
625 | */ | |
a114d0a6 | 626 | if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) && |
810b3ae4 | 627 | (tx_pending >= I40E_MIN_DESC_PENDING)) { |
fd0a05ce JB |
628 | /* make sure it is true for two checks in a row */ |
629 | ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED, | |
630 | &tx_ring->state); | |
810b3ae4 ASJ |
631 | } else if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) && |
632 | (tx_pending < I40E_MIN_DESC_PENDING) && | |
633 | (tx_pending > 0)) { | |
634 | if (I40E_DEBUG_FLOW & pf->hw.debug_mask) | |
635 | dev_info(tx_ring->dev, "HW needs some more descs to do a cacheline flush. tx_pending %d, queue %d", | |
636 | tx_pending, tx_ring->queue_index); | |
637 | pf->tx_sluggish_count++; | |
fd0a05ce JB |
638 | } else { |
639 | /* update completed stats and disarm the hang check */ | |
a114d0a6 | 640 | tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets; |
fd0a05ce JB |
641 | clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state); |
642 | } | |
643 | ||
644 | return ret; | |
645 | } | |
646 | ||
1943d8ba JB |
647 | /** |
648 | * i40e_get_head - Retrieve head from head writeback | |
649 | * @tx_ring: tx ring to fetch head of | |
650 | * | |
651 | * Returns value of Tx ring head based on value stored | |
652 | * in head write-back location | |
653 | **/ | |
654 | static inline u32 i40e_get_head(struct i40e_ring *tx_ring) | |
655 | { | |
656 | void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; | |
657 | ||
658 | return le32_to_cpu(*(volatile __le32 *)head); | |
659 | } | |
660 | ||
d91649f5 JB |
661 | #define WB_STRIDE 0x3 |
662 | ||
fd0a05ce JB |
663 | /** |
664 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
665 | * @tx_ring: tx ring to clean | |
666 | * @budget: how many cleans we're allowed | |
667 | * | |
668 | * Returns true if there's any budget left (e.g. the clean is finished) | |
669 | **/ | |
670 | static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) | |
671 | { | |
672 | u16 i = tx_ring->next_to_clean; | |
673 | struct i40e_tx_buffer *tx_buf; | |
1943d8ba | 674 | struct i40e_tx_desc *tx_head; |
fd0a05ce JB |
675 | struct i40e_tx_desc *tx_desc; |
676 | unsigned int total_packets = 0; | |
677 | unsigned int total_bytes = 0; | |
678 | ||
679 | tx_buf = &tx_ring->tx_bi[i]; | |
680 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
a5e9c572 | 681 | i -= tx_ring->count; |
fd0a05ce | 682 | |
1943d8ba JB |
683 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
684 | ||
a5e9c572 AD |
685 | do { |
686 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
fd0a05ce JB |
687 | |
688 | /* if next_to_watch is not set then there is no work pending */ | |
689 | if (!eop_desc) | |
690 | break; | |
691 | ||
a5e9c572 AD |
692 | /* prevent any other reads prior to eop_desc */ |
693 | read_barrier_depends(); | |
694 | ||
1943d8ba JB |
695 | /* we have caught up to head, no work left to do */ |
696 | if (tx_head == tx_desc) | |
fd0a05ce JB |
697 | break; |
698 | ||
c304fdac | 699 | /* clear next_to_watch to prevent false hangs */ |
fd0a05ce | 700 | tx_buf->next_to_watch = NULL; |
fd0a05ce | 701 | |
a5e9c572 AD |
702 | /* update the statistics for this packet */ |
703 | total_bytes += tx_buf->bytecount; | |
704 | total_packets += tx_buf->gso_segs; | |
fd0a05ce | 705 | |
a5e9c572 | 706 | /* free the skb */ |
a81fb049 | 707 | dev_consume_skb_any(tx_buf->skb); |
fd0a05ce | 708 | |
a5e9c572 AD |
709 | /* unmap skb header data */ |
710 | dma_unmap_single(tx_ring->dev, | |
711 | dma_unmap_addr(tx_buf, dma), | |
712 | dma_unmap_len(tx_buf, len), | |
713 | DMA_TO_DEVICE); | |
fd0a05ce | 714 | |
a5e9c572 AD |
715 | /* clear tx_buffer data */ |
716 | tx_buf->skb = NULL; | |
717 | dma_unmap_len_set(tx_buf, len, 0); | |
fd0a05ce | 718 | |
a5e9c572 AD |
719 | /* unmap remaining buffers */ |
720 | while (tx_desc != eop_desc) { | |
fd0a05ce JB |
721 | |
722 | tx_buf++; | |
723 | tx_desc++; | |
724 | i++; | |
a5e9c572 AD |
725 | if (unlikely(!i)) { |
726 | i -= tx_ring->count; | |
fd0a05ce JB |
727 | tx_buf = tx_ring->tx_bi; |
728 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
729 | } | |
fd0a05ce | 730 | |
a5e9c572 AD |
731 | /* unmap any remaining paged data */ |
732 | if (dma_unmap_len(tx_buf, len)) { | |
733 | dma_unmap_page(tx_ring->dev, | |
734 | dma_unmap_addr(tx_buf, dma), | |
735 | dma_unmap_len(tx_buf, len), | |
736 | DMA_TO_DEVICE); | |
737 | dma_unmap_len_set(tx_buf, len, 0); | |
738 | } | |
739 | } | |
740 | ||
741 | /* move us one more past the eop_desc for start of next pkt */ | |
742 | tx_buf++; | |
743 | tx_desc++; | |
744 | i++; | |
745 | if (unlikely(!i)) { | |
746 | i -= tx_ring->count; | |
747 | tx_buf = tx_ring->tx_bi; | |
748 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
749 | } | |
750 | ||
751 | /* update budget accounting */ | |
752 | budget--; | |
753 | } while (likely(budget)); | |
754 | ||
755 | i += tx_ring->count; | |
fd0a05ce | 756 | tx_ring->next_to_clean = i; |
980e9b11 | 757 | u64_stats_update_begin(&tx_ring->syncp); |
a114d0a6 AD |
758 | tx_ring->stats.bytes += total_bytes; |
759 | tx_ring->stats.packets += total_packets; | |
980e9b11 | 760 | u64_stats_update_end(&tx_ring->syncp); |
fd0a05ce JB |
761 | tx_ring->q_vector->tx.total_bytes += total_bytes; |
762 | tx_ring->q_vector->tx.total_packets += total_packets; | |
a5e9c572 | 763 | |
d91649f5 JB |
764 | /* check to see if there are any non-cache aligned descriptors |
765 | * waiting to be written back, and kick the hardware to force | |
766 | * them to be written back in case of napi polling | |
767 | */ | |
768 | if (budget && | |
769 | !((i & WB_STRIDE) == WB_STRIDE) && | |
770 | !test_bit(__I40E_DOWN, &tx_ring->vsi->state) && | |
771 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) | |
772 | tx_ring->arm_wb = true; | |
773 | else | |
774 | tx_ring->arm_wb = false; | |
775 | ||
fd0a05ce JB |
776 | if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) { |
777 | /* schedule immediate reset if we believe we hung */ | |
778 | dev_info(tx_ring->dev, "Detected Tx Unit Hang\n" | |
779 | " VSI <%d>\n" | |
780 | " Tx Queue <%d>\n" | |
781 | " next_to_use <%x>\n" | |
782 | " next_to_clean <%x>\n", | |
783 | tx_ring->vsi->seid, | |
784 | tx_ring->queue_index, | |
785 | tx_ring->next_to_use, i); | |
786 | dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n" | |
787 | " time_stamp <%lx>\n" | |
788 | " jiffies <%lx>\n", | |
789 | tx_ring->tx_bi[i].time_stamp, jiffies); | |
790 | ||
791 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
792 | ||
793 | dev_info(tx_ring->dev, | |
d91649f5 | 794 | "tx hang detected on queue %d, reset requested\n", |
fd0a05ce JB |
795 | tx_ring->queue_index); |
796 | ||
d91649f5 JB |
797 | /* do not fire the reset immediately, wait for the stack to |
798 | * decide we are truly stuck, also prevents every queue from | |
799 | * simultaneously requesting a reset | |
800 | */ | |
fd0a05ce | 801 | |
d91649f5 JB |
802 | /* the adapter is about to reset, no point in enabling polling */ |
803 | budget = 1; | |
fd0a05ce JB |
804 | } |
805 | ||
7070ce0a AD |
806 | netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, |
807 | tx_ring->queue_index), | |
808 | total_packets, total_bytes); | |
809 | ||
fd0a05ce JB |
810 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
811 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
812 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
813 | /* Make sure that anybody stopping the queue after this | |
814 | * sees the new next_to_clean. | |
815 | */ | |
816 | smp_mb(); | |
817 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
818 | tx_ring->queue_index) && | |
819 | !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) { | |
820 | netif_wake_subqueue(tx_ring->netdev, | |
821 | tx_ring->queue_index); | |
822 | ++tx_ring->tx_stats.restart_queue; | |
823 | } | |
824 | } | |
825 | ||
d91649f5 JB |
826 | return !!budget; |
827 | } | |
828 | ||
829 | /** | |
830 | * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors | |
831 | * @vsi: the VSI we care about | |
832 | * @q_vector: the vector on which to force writeback | |
833 | * | |
834 | **/ | |
835 | static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
836 | { | |
837 | u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | | |
838 | I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | | |
c29af37f ASJ |
839 | I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; |
840 | /* allow 00 to be written to the index */ | |
d91649f5 JB |
841 | |
842 | wr32(&vsi->back->hw, | |
843 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), | |
844 | val); | |
fd0a05ce JB |
845 | } |
846 | ||
847 | /** | |
848 | * i40e_set_new_dynamic_itr - Find new ITR level | |
849 | * @rc: structure containing ring performance data | |
850 | * | |
851 | * Stores a new ITR value based on packets and byte counts during | |
852 | * the last interrupt. The advantage of per interrupt computation | |
853 | * is faster updates and more accurate ITR for the current traffic | |
854 | * pattern. Constants in this function were computed based on | |
855 | * theoretical maximum wire speed and thresholds were set based on | |
856 | * testing data as well as attempting to minimize response time | |
857 | * while increasing bulk throughput. | |
858 | **/ | |
859 | static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) | |
860 | { | |
861 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
862 | u32 new_itr = rc->itr; | |
863 | int bytes_per_int; | |
864 | ||
865 | if (rc->total_packets == 0 || !rc->itr) | |
866 | return; | |
867 | ||
868 | /* simple throttlerate management | |
869 | * 0-10MB/s lowest (100000 ints/s) | |
870 | * 10-20MB/s low (20000 ints/s) | |
871 | * 20-1249MB/s bulk (8000 ints/s) | |
872 | */ | |
873 | bytes_per_int = rc->total_bytes / rc->itr; | |
874 | switch (rc->itr) { | |
875 | case I40E_LOWEST_LATENCY: | |
876 | if (bytes_per_int > 10) | |
877 | new_latency_range = I40E_LOW_LATENCY; | |
878 | break; | |
879 | case I40E_LOW_LATENCY: | |
880 | if (bytes_per_int > 20) | |
881 | new_latency_range = I40E_BULK_LATENCY; | |
882 | else if (bytes_per_int <= 10) | |
883 | new_latency_range = I40E_LOWEST_LATENCY; | |
884 | break; | |
885 | case I40E_BULK_LATENCY: | |
886 | if (bytes_per_int <= 20) | |
887 | rc->latency_range = I40E_LOW_LATENCY; | |
888 | break; | |
889 | } | |
890 | ||
891 | switch (new_latency_range) { | |
892 | case I40E_LOWEST_LATENCY: | |
893 | new_itr = I40E_ITR_100K; | |
894 | break; | |
895 | case I40E_LOW_LATENCY: | |
896 | new_itr = I40E_ITR_20K; | |
897 | break; | |
898 | case I40E_BULK_LATENCY: | |
899 | new_itr = I40E_ITR_8K; | |
900 | break; | |
901 | default: | |
902 | break; | |
903 | } | |
904 | ||
905 | if (new_itr != rc->itr) { | |
906 | /* do an exponential smoothing */ | |
907 | new_itr = (10 * new_itr * rc->itr) / | |
908 | ((9 * new_itr) + rc->itr); | |
909 | rc->itr = new_itr & I40E_MAX_ITR; | |
910 | } | |
911 | ||
912 | rc->total_bytes = 0; | |
913 | rc->total_packets = 0; | |
914 | } | |
915 | ||
916 | /** | |
917 | * i40e_update_dynamic_itr - Adjust ITR based on bytes per int | |
918 | * @q_vector: the vector to adjust | |
919 | **/ | |
920 | static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector) | |
921 | { | |
922 | u16 vector = q_vector->vsi->base_vector + q_vector->v_idx; | |
923 | struct i40e_hw *hw = &q_vector->vsi->back->hw; | |
924 | u32 reg_addr; | |
925 | u16 old_itr; | |
926 | ||
927 | reg_addr = I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1); | |
928 | old_itr = q_vector->rx.itr; | |
929 | i40e_set_new_dynamic_itr(&q_vector->rx); | |
930 | if (old_itr != q_vector->rx.itr) | |
931 | wr32(hw, reg_addr, q_vector->rx.itr); | |
932 | ||
933 | reg_addr = I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1); | |
934 | old_itr = q_vector->tx.itr; | |
935 | i40e_set_new_dynamic_itr(&q_vector->tx); | |
936 | if (old_itr != q_vector->tx.itr) | |
937 | wr32(hw, reg_addr, q_vector->tx.itr); | |
fd0a05ce JB |
938 | } |
939 | ||
940 | /** | |
941 | * i40e_clean_programming_status - clean the programming status descriptor | |
942 | * @rx_ring: the rx ring that has this descriptor | |
943 | * @rx_desc: the rx descriptor written back by HW | |
944 | * | |
945 | * Flow director should handle FD_FILTER_STATUS to check its filter programming | |
946 | * status being successful or not and take actions accordingly. FCoE should | |
947 | * handle its context/filter programming/invalidation status and take actions. | |
948 | * | |
949 | **/ | |
950 | static void i40e_clean_programming_status(struct i40e_ring *rx_ring, | |
951 | union i40e_rx_desc *rx_desc) | |
952 | { | |
953 | u64 qw; | |
954 | u8 id; | |
955 | ||
956 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
957 | id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> | |
958 | I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; | |
959 | ||
960 | if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) | |
55a5e60b | 961 | i40e_fd_handle_status(rx_ring, rx_desc, id); |
38e00438 VD |
962 | #ifdef I40E_FCOE |
963 | else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || | |
964 | (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) | |
965 | i40e_fcoe_handle_status(rx_ring, rx_desc, id); | |
966 | #endif | |
fd0a05ce JB |
967 | } |
968 | ||
969 | /** | |
970 | * i40e_setup_tx_descriptors - Allocate the Tx descriptors | |
971 | * @tx_ring: the tx ring to set up | |
972 | * | |
973 | * Return 0 on success, negative on error | |
974 | **/ | |
975 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
976 | { | |
977 | struct device *dev = tx_ring->dev; | |
978 | int bi_size; | |
979 | ||
980 | if (!dev) | |
981 | return -ENOMEM; | |
982 | ||
983 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
984 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
985 | if (!tx_ring->tx_bi) | |
986 | goto err; | |
987 | ||
988 | /* round up to nearest 4K */ | |
989 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
990 | /* add u32 for head writeback, align after this takes care of |
991 | * guaranteeing this is at least one cache line in size | |
992 | */ | |
993 | tx_ring->size += sizeof(u32); | |
fd0a05ce JB |
994 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
995 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
996 | &tx_ring->dma, GFP_KERNEL); | |
997 | if (!tx_ring->desc) { | |
998 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
999 | tx_ring->size); | |
1000 | goto err; | |
1001 | } | |
1002 | ||
1003 | tx_ring->next_to_use = 0; | |
1004 | tx_ring->next_to_clean = 0; | |
1005 | return 0; | |
1006 | ||
1007 | err: | |
1008 | kfree(tx_ring->tx_bi); | |
1009 | tx_ring->tx_bi = NULL; | |
1010 | return -ENOMEM; | |
1011 | } | |
1012 | ||
1013 | /** | |
1014 | * i40e_clean_rx_ring - Free Rx buffers | |
1015 | * @rx_ring: ring to be cleaned | |
1016 | **/ | |
1017 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring) | |
1018 | { | |
1019 | struct device *dev = rx_ring->dev; | |
1020 | struct i40e_rx_buffer *rx_bi; | |
1021 | unsigned long bi_size; | |
1022 | u16 i; | |
1023 | ||
1024 | /* ring already cleared, nothing to do */ | |
1025 | if (!rx_ring->rx_bi) | |
1026 | return; | |
1027 | ||
1028 | /* Free all the Rx ring sk_buffs */ | |
1029 | for (i = 0; i < rx_ring->count; i++) { | |
1030 | rx_bi = &rx_ring->rx_bi[i]; | |
1031 | if (rx_bi->dma) { | |
1032 | dma_unmap_single(dev, | |
1033 | rx_bi->dma, | |
1034 | rx_ring->rx_buf_len, | |
1035 | DMA_FROM_DEVICE); | |
1036 | rx_bi->dma = 0; | |
1037 | } | |
1038 | if (rx_bi->skb) { | |
1039 | dev_kfree_skb(rx_bi->skb); | |
1040 | rx_bi->skb = NULL; | |
1041 | } | |
1042 | if (rx_bi->page) { | |
1043 | if (rx_bi->page_dma) { | |
1044 | dma_unmap_page(dev, | |
1045 | rx_bi->page_dma, | |
1046 | PAGE_SIZE / 2, | |
1047 | DMA_FROM_DEVICE); | |
1048 | rx_bi->page_dma = 0; | |
1049 | } | |
1050 | __free_page(rx_bi->page); | |
1051 | rx_bi->page = NULL; | |
1052 | rx_bi->page_offset = 0; | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
1057 | memset(rx_ring->rx_bi, 0, bi_size); | |
1058 | ||
1059 | /* Zero out the descriptor ring */ | |
1060 | memset(rx_ring->desc, 0, rx_ring->size); | |
1061 | ||
1062 | rx_ring->next_to_clean = 0; | |
1063 | rx_ring->next_to_use = 0; | |
1064 | } | |
1065 | ||
1066 | /** | |
1067 | * i40e_free_rx_resources - Free Rx resources | |
1068 | * @rx_ring: ring to clean the resources from | |
1069 | * | |
1070 | * Free all receive software resources | |
1071 | **/ | |
1072 | void i40e_free_rx_resources(struct i40e_ring *rx_ring) | |
1073 | { | |
1074 | i40e_clean_rx_ring(rx_ring); | |
1075 | kfree(rx_ring->rx_bi); | |
1076 | rx_ring->rx_bi = NULL; | |
1077 | ||
1078 | if (rx_ring->desc) { | |
1079 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
1080 | rx_ring->desc, rx_ring->dma); | |
1081 | rx_ring->desc = NULL; | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * i40e_setup_rx_descriptors - Allocate Rx descriptors | |
1087 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
1088 | * | |
1089 | * Returns 0 on success, negative on failure | |
1090 | **/ | |
1091 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
1092 | { | |
1093 | struct device *dev = rx_ring->dev; | |
1094 | int bi_size; | |
1095 | ||
1096 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
1097 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1098 | if (!rx_ring->rx_bi) | |
1099 | goto err; | |
1100 | ||
638702bd CW |
1101 | u64_stats_init(rx_ring->syncp); |
1102 | ||
fd0a05ce JB |
1103 | /* Round up to nearest 4K */ |
1104 | rx_ring->size = ring_is_16byte_desc_enabled(rx_ring) | |
1105 | ? rx_ring->count * sizeof(union i40e_16byte_rx_desc) | |
1106 | : rx_ring->count * sizeof(union i40e_32byte_rx_desc); | |
1107 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
1108 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
1109 | &rx_ring->dma, GFP_KERNEL); | |
1110 | ||
1111 | if (!rx_ring->desc) { | |
1112 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
1113 | rx_ring->size); | |
1114 | goto err; | |
1115 | } | |
1116 | ||
1117 | rx_ring->next_to_clean = 0; | |
1118 | rx_ring->next_to_use = 0; | |
1119 | ||
1120 | return 0; | |
1121 | err: | |
1122 | kfree(rx_ring->rx_bi); | |
1123 | rx_ring->rx_bi = NULL; | |
1124 | return -ENOMEM; | |
1125 | } | |
1126 | ||
1127 | /** | |
1128 | * i40e_release_rx_desc - Store the new tail and head values | |
1129 | * @rx_ring: ring to bump | |
1130 | * @val: new head index | |
1131 | **/ | |
1132 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
1133 | { | |
1134 | rx_ring->next_to_use = val; | |
1135 | /* Force memory writes to complete before letting h/w | |
1136 | * know there are new descriptors to fetch. (Only | |
1137 | * applicable for weak-ordered memory model archs, | |
1138 | * such as IA-64). | |
1139 | */ | |
1140 | wmb(); | |
1141 | writel(val, rx_ring->tail); | |
1142 | } | |
1143 | ||
1144 | /** | |
1145 | * i40e_alloc_rx_buffers - Replace used receive buffers; packet split | |
1146 | * @rx_ring: ring to place buffers on | |
1147 | * @cleaned_count: number of buffers to replace | |
1148 | **/ | |
1149 | void i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) | |
1150 | { | |
1151 | u16 i = rx_ring->next_to_use; | |
1152 | union i40e_rx_desc *rx_desc; | |
1153 | struct i40e_rx_buffer *bi; | |
1154 | struct sk_buff *skb; | |
1155 | ||
1156 | /* do nothing if no valid netdev defined */ | |
1157 | if (!rx_ring->netdev || !cleaned_count) | |
1158 | return; | |
1159 | ||
1160 | while (cleaned_count--) { | |
1161 | rx_desc = I40E_RX_DESC(rx_ring, i); | |
1162 | bi = &rx_ring->rx_bi[i]; | |
1163 | skb = bi->skb; | |
1164 | ||
1165 | if (!skb) { | |
1166 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1167 | rx_ring->rx_buf_len); | |
1168 | if (!skb) { | |
420136cc | 1169 | rx_ring->rx_stats.alloc_buff_failed++; |
fd0a05ce JB |
1170 | goto no_buffers; |
1171 | } | |
1172 | /* initialize queue mapping */ | |
1173 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
1174 | bi->skb = skb; | |
1175 | } | |
1176 | ||
1177 | if (!bi->dma) { | |
1178 | bi->dma = dma_map_single(rx_ring->dev, | |
1179 | skb->data, | |
1180 | rx_ring->rx_buf_len, | |
1181 | DMA_FROM_DEVICE); | |
1182 | if (dma_mapping_error(rx_ring->dev, bi->dma)) { | |
420136cc | 1183 | rx_ring->rx_stats.alloc_buff_failed++; |
fd0a05ce JB |
1184 | bi->dma = 0; |
1185 | goto no_buffers; | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | if (ring_is_ps_enabled(rx_ring)) { | |
1190 | if (!bi->page) { | |
1191 | bi->page = alloc_page(GFP_ATOMIC); | |
1192 | if (!bi->page) { | |
420136cc | 1193 | rx_ring->rx_stats.alloc_page_failed++; |
fd0a05ce JB |
1194 | goto no_buffers; |
1195 | } | |
1196 | } | |
1197 | ||
1198 | if (!bi->page_dma) { | |
1199 | /* use a half page if we're re-using */ | |
1200 | bi->page_offset ^= PAGE_SIZE / 2; | |
1201 | bi->page_dma = dma_map_page(rx_ring->dev, | |
1202 | bi->page, | |
1203 | bi->page_offset, | |
1204 | PAGE_SIZE / 2, | |
1205 | DMA_FROM_DEVICE); | |
1206 | if (dma_mapping_error(rx_ring->dev, | |
1207 | bi->page_dma)) { | |
420136cc | 1208 | rx_ring->rx_stats.alloc_page_failed++; |
fd0a05ce JB |
1209 | bi->page_dma = 0; |
1210 | goto no_buffers; | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | /* Refresh the desc even if buffer_addrs didn't change | |
1215 | * because each write-back erases this info. | |
1216 | */ | |
1217 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); | |
1218 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
1219 | } else { | |
1220 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); | |
1221 | rx_desc->read.hdr_addr = 0; | |
1222 | } | |
1223 | i++; | |
1224 | if (i == rx_ring->count) | |
1225 | i = 0; | |
1226 | } | |
1227 | ||
1228 | no_buffers: | |
1229 | if (rx_ring->next_to_use != i) | |
1230 | i40e_release_rx_desc(rx_ring, i); | |
1231 | } | |
1232 | ||
1233 | /** | |
1234 | * i40e_receive_skb - Send a completed packet up the stack | |
1235 | * @rx_ring: rx ring in play | |
1236 | * @skb: packet to send up | |
1237 | * @vlan_tag: vlan tag for packet | |
1238 | **/ | |
1239 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
1240 | struct sk_buff *skb, u16 vlan_tag) | |
1241 | { | |
1242 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
1243 | struct i40e_vsi *vsi = rx_ring->vsi; | |
1244 | u64 flags = vsi->back->flags; | |
1245 | ||
1246 | if (vlan_tag & VLAN_VID_MASK) | |
1247 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
1248 | ||
1249 | if (flags & I40E_FLAG_IN_NETPOLL) | |
1250 | netif_rx(skb); | |
1251 | else | |
1252 | napi_gro_receive(&q_vector->napi, skb); | |
1253 | } | |
1254 | ||
1255 | /** | |
1256 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
1257 | * @vsi: the VSI we care about | |
1258 | * @skb: skb currently being received and modified | |
1259 | * @rx_status: status value of last descriptor in packet | |
1260 | * @rx_error: error value of last descriptor in packet | |
8144f0f7 | 1261 | * @rx_ptype: ptype value of last descriptor in packet |
fd0a05ce JB |
1262 | **/ |
1263 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
1264 | struct sk_buff *skb, | |
1265 | u32 rx_status, | |
8144f0f7 JG |
1266 | u32 rx_error, |
1267 | u16 rx_ptype) | |
fd0a05ce | 1268 | { |
8a3c91cc JB |
1269 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype); |
1270 | bool ipv4 = false, ipv6 = false; | |
8144f0f7 JG |
1271 | bool ipv4_tunnel, ipv6_tunnel; |
1272 | __wsum rx_udp_csum; | |
8144f0f7 | 1273 | struct iphdr *iph; |
8a3c91cc | 1274 | __sum16 csum; |
8144f0f7 JG |
1275 | |
1276 | ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) && | |
1277 | (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4); | |
1278 | ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) && | |
1279 | (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4); | |
1280 | ||
fd0a05ce JB |
1281 | skb->ip_summed = CHECKSUM_NONE; |
1282 | ||
1283 | /* Rx csum enabled and ip headers found? */ | |
8a3c91cc JB |
1284 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
1285 | return; | |
1286 | ||
1287 | /* did the hardware decode the packet and checksum? */ | |
1288 | if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT))) | |
1289 | return; | |
1290 | ||
1291 | /* both known and outer_ip must be set for the below code to work */ | |
1292 | if (!(decoded.known && decoded.outer_ip)) | |
fd0a05ce JB |
1293 | return; |
1294 | ||
8a3c91cc JB |
1295 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && |
1296 | decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4) | |
1297 | ipv4 = true; | |
1298 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1299 | decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6) | |
1300 | ipv6 = true; | |
1301 | ||
1302 | if (ipv4 && | |
1303 | (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) | | |
1304 | (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
1305 | goto checksum_fail; | |
1306 | ||
ddf1d0d7 | 1307 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 1308 | if (ipv6 && |
8a3c91cc JB |
1309 | rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
1310 | /* don't increment checksum err here, non-fatal err */ | |
8ee75a8e SN |
1311 | return; |
1312 | ||
8a3c91cc JB |
1313 | /* there was some L4 error, count error and punt packet to the stack */ |
1314 | if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)) | |
1315 | goto checksum_fail; | |
1316 | ||
1317 | /* handle packets that were not able to be checksummed due | |
1318 | * to arrival speed, in this case the stack can compute | |
1319 | * the csum. | |
1320 | */ | |
1321 | if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT)) | |
fd0a05ce | 1322 | return; |
fd0a05ce | 1323 | |
8a3c91cc JB |
1324 | /* If VXLAN traffic has an outer UDPv4 checksum we need to check |
1325 | * it in the driver, hardware does not do it for us. | |
1326 | * Since L3L4P bit was set we assume a valid IHL value (>=5) | |
1327 | * so the total length of IPv4 header is IHL*4 bytes | |
1328 | * The UDP_0 bit *may* bet set if the *inner* header is UDP | |
1329 | */ | |
f6385979 | 1330 | if (ipv4_tunnel) { |
8144f0f7 JG |
1331 | skb->transport_header = skb->mac_header + |
1332 | sizeof(struct ethhdr) + | |
1333 | (ip_hdr(skb)->ihl * 4); | |
1334 | ||
1335 | /* Add 4 bytes for VLAN tagged packets */ | |
1336 | skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) || | |
1337 | skb->protocol == htons(ETH_P_8021AD)) | |
1338 | ? VLAN_HLEN : 0; | |
1339 | ||
f6385979 AS |
1340 | if ((ip_hdr(skb)->protocol == IPPROTO_UDP) && |
1341 | (udp_hdr(skb)->check != 0)) { | |
1342 | rx_udp_csum = udp_csum(skb); | |
1343 | iph = ip_hdr(skb); | |
1344 | csum = csum_tcpudp_magic( | |
1345 | iph->saddr, iph->daddr, | |
1346 | (skb->len - skb_transport_offset(skb)), | |
1347 | IPPROTO_UDP, rx_udp_csum); | |
8144f0f7 | 1348 | |
f6385979 AS |
1349 | if (udp_hdr(skb)->check != csum) |
1350 | goto checksum_fail; | |
1351 | ||
1352 | } /* else its GRE and so no outer UDP header */ | |
8144f0f7 JG |
1353 | } |
1354 | ||
fd0a05ce | 1355 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
fa4ba69b | 1356 | skb->csum_level = ipv4_tunnel || ipv6_tunnel; |
8a3c91cc JB |
1357 | |
1358 | return; | |
1359 | ||
1360 | checksum_fail: | |
1361 | vsi->back->hw_csum_rx_error++; | |
fd0a05ce JB |
1362 | } |
1363 | ||
1364 | /** | |
1365 | * i40e_rx_hash - returns the hash value from the Rx descriptor | |
1366 | * @ring: descriptor ring | |
1367 | * @rx_desc: specific descriptor | |
1368 | **/ | |
1369 | static inline u32 i40e_rx_hash(struct i40e_ring *ring, | |
1370 | union i40e_rx_desc *rx_desc) | |
1371 | { | |
8a494920 JB |
1372 | const __le64 rss_mask = |
1373 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << | |
1374 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
1375 | ||
1376 | if ((ring->netdev->features & NETIF_F_RXHASH) && | |
1377 | (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) | |
1378 | return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
1379 | else | |
1380 | return 0; | |
fd0a05ce JB |
1381 | } |
1382 | ||
206812b5 JB |
1383 | /** |
1384 | * i40e_ptype_to_hash - get a hash type | |
1385 | * @ptype: the ptype value from the descriptor | |
1386 | * | |
1387 | * Returns a hash type to be used by skb_set_hash | |
1388 | **/ | |
1389 | static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype) | |
1390 | { | |
1391 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
1392 | ||
1393 | if (!decoded.known) | |
1394 | return PKT_HASH_TYPE_NONE; | |
1395 | ||
1396 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1397 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
1398 | return PKT_HASH_TYPE_L4; | |
1399 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1400 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
1401 | return PKT_HASH_TYPE_L3; | |
1402 | else | |
1403 | return PKT_HASH_TYPE_L2; | |
1404 | } | |
1405 | ||
fd0a05ce JB |
1406 | /** |
1407 | * i40e_clean_rx_irq - Reclaim resources after receive completes | |
1408 | * @rx_ring: rx ring to clean | |
1409 | * @budget: how many cleans we're allowed | |
1410 | * | |
1411 | * Returns true if there's any budget left (e.g. the clean is finished) | |
1412 | **/ | |
1413 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) | |
1414 | { | |
1415 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
1416 | u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo; | |
1417 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); | |
1418 | const int current_node = numa_node_id(); | |
1419 | struct i40e_vsi *vsi = rx_ring->vsi; | |
1420 | u16 i = rx_ring->next_to_clean; | |
1421 | union i40e_rx_desc *rx_desc; | |
1422 | u32 rx_error, rx_status; | |
206812b5 | 1423 | u8 rx_ptype; |
fd0a05ce JB |
1424 | u64 qword; |
1425 | ||
390f86df EB |
1426 | if (budget <= 0) |
1427 | return 0; | |
1428 | ||
fd0a05ce JB |
1429 | rx_desc = I40E_RX_DESC(rx_ring, i); |
1430 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
6838b535 JB |
1431 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> |
1432 | I40E_RXD_QW1_STATUS_SHIFT; | |
fd0a05ce JB |
1433 | |
1434 | while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) { | |
1435 | union i40e_rx_desc *next_rxd; | |
1436 | struct i40e_rx_buffer *rx_bi; | |
1437 | struct sk_buff *skb; | |
1438 | u16 vlan_tag; | |
1439 | if (i40e_rx_is_programming_status(qword)) { | |
1440 | i40e_clean_programming_status(rx_ring, rx_desc); | |
1441 | I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd); | |
1442 | goto next_desc; | |
1443 | } | |
1444 | rx_bi = &rx_ring->rx_bi[i]; | |
1445 | skb = rx_bi->skb; | |
1446 | prefetch(skb->data); | |
1447 | ||
829af3ac MW |
1448 | rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> |
1449 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1450 | rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >> | |
1451 | I40E_RXD_QW1_LENGTH_HBUF_SHIFT; | |
1452 | rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >> | |
1453 | I40E_RXD_QW1_LENGTH_SPH_SHIFT; | |
1454 | ||
1455 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
1456 | I40E_RXD_QW1_ERROR_SHIFT; | |
fd0a05ce JB |
1457 | rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT); |
1458 | rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT); | |
1459 | ||
8144f0f7 JG |
1460 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> |
1461 | I40E_RXD_QW1_PTYPE_SHIFT; | |
fd0a05ce JB |
1462 | rx_bi->skb = NULL; |
1463 | ||
1464 | /* This memory barrier is needed to keep us from reading | |
1465 | * any other fields out of the rx_desc until we know the | |
1466 | * STATUS_DD bit is set | |
1467 | */ | |
1468 | rmb(); | |
1469 | ||
1470 | /* Get the header and possibly the whole packet | |
1471 | * If this is an skb from previous receive dma will be 0 | |
1472 | */ | |
1473 | if (rx_bi->dma) { | |
1474 | u16 len; | |
1475 | ||
1476 | if (rx_hbo) | |
1477 | len = I40E_RX_HDR_SIZE; | |
1478 | else if (rx_sph) | |
1479 | len = rx_header_len; | |
1480 | else if (rx_packet_len) | |
1481 | len = rx_packet_len; /* 1buf/no split found */ | |
1482 | else | |
1483 | len = rx_header_len; /* split always mode */ | |
1484 | ||
1485 | skb_put(skb, len); | |
1486 | dma_unmap_single(rx_ring->dev, | |
1487 | rx_bi->dma, | |
1488 | rx_ring->rx_buf_len, | |
1489 | DMA_FROM_DEVICE); | |
1490 | rx_bi->dma = 0; | |
1491 | } | |
1492 | ||
1493 | /* Get the rest of the data if this was a header split */ | |
1494 | if (ring_is_ps_enabled(rx_ring) && rx_packet_len) { | |
1495 | ||
1496 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1497 | rx_bi->page, | |
1498 | rx_bi->page_offset, | |
1499 | rx_packet_len); | |
1500 | ||
1501 | skb->len += rx_packet_len; | |
1502 | skb->data_len += rx_packet_len; | |
1503 | skb->truesize += rx_packet_len; | |
1504 | ||
1505 | if ((page_count(rx_bi->page) == 1) && | |
1506 | (page_to_nid(rx_bi->page) == current_node)) | |
1507 | get_page(rx_bi->page); | |
1508 | else | |
1509 | rx_bi->page = NULL; | |
1510 | ||
1511 | dma_unmap_page(rx_ring->dev, | |
1512 | rx_bi->page_dma, | |
1513 | PAGE_SIZE / 2, | |
1514 | DMA_FROM_DEVICE); | |
1515 | rx_bi->page_dma = 0; | |
1516 | } | |
1517 | I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd); | |
1518 | ||
1519 | if (unlikely( | |
1520 | !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) { | |
1521 | struct i40e_rx_buffer *next_buffer; | |
1522 | ||
1523 | next_buffer = &rx_ring->rx_bi[i]; | |
1524 | ||
1525 | if (ring_is_ps_enabled(rx_ring)) { | |
1526 | rx_bi->skb = next_buffer->skb; | |
1527 | rx_bi->dma = next_buffer->dma; | |
1528 | next_buffer->skb = skb; | |
1529 | next_buffer->dma = 0; | |
1530 | } | |
1531 | rx_ring->rx_stats.non_eop_descs++; | |
1532 | goto next_desc; | |
1533 | } | |
1534 | ||
1535 | /* ERR_MASK will only have valid bits if EOP set */ | |
1536 | if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) { | |
1537 | dev_kfree_skb_any(skb); | |
8a3c91cc JB |
1538 | /* TODO: shouldn't we increment a counter indicating the |
1539 | * drop? | |
1540 | */ | |
fd0a05ce JB |
1541 | goto next_desc; |
1542 | } | |
1543 | ||
206812b5 JB |
1544 | skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc), |
1545 | i40e_ptype_to_hash(rx_ptype)); | |
beb0dff1 JK |
1546 | if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) { |
1547 | i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status & | |
1548 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> | |
1549 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT); | |
1550 | rx_ring->last_rx_timestamp = jiffies; | |
1551 | } | |
1552 | ||
fd0a05ce JB |
1553 | /* probably a little skewed due to removing CRC */ |
1554 | total_rx_bytes += skb->len; | |
1555 | total_rx_packets++; | |
1556 | ||
1557 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
8144f0f7 JG |
1558 | |
1559 | i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype); | |
1560 | ||
fd0a05ce JB |
1561 | vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) |
1562 | ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) | |
1563 | : 0; | |
38e00438 VD |
1564 | #ifdef I40E_FCOE |
1565 | if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) { | |
1566 | dev_kfree_skb_any(skb); | |
1567 | goto next_desc; | |
1568 | } | |
1569 | #endif | |
fd0a05ce JB |
1570 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
1571 | ||
1572 | rx_ring->netdev->last_rx = jiffies; | |
1573 | budget--; | |
1574 | next_desc: | |
1575 | rx_desc->wb.qword1.status_error_len = 0; | |
1576 | if (!budget) | |
1577 | break; | |
1578 | ||
1579 | cleaned_count++; | |
1580 | /* return some buffers to hardware, one at a time is too slow */ | |
1581 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
1582 | i40e_alloc_rx_buffers(rx_ring, cleaned_count); | |
1583 | cleaned_count = 0; | |
1584 | } | |
1585 | ||
1586 | /* use prefetched values */ | |
1587 | rx_desc = next_rxd; | |
1588 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
829af3ac MW |
1589 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> |
1590 | I40E_RXD_QW1_STATUS_SHIFT; | |
fd0a05ce JB |
1591 | } |
1592 | ||
1593 | rx_ring->next_to_clean = i; | |
980e9b11 | 1594 | u64_stats_update_begin(&rx_ring->syncp); |
a114d0a6 AD |
1595 | rx_ring->stats.packets += total_rx_packets; |
1596 | rx_ring->stats.bytes += total_rx_bytes; | |
980e9b11 | 1597 | u64_stats_update_end(&rx_ring->syncp); |
fd0a05ce JB |
1598 | rx_ring->q_vector->rx.total_packets += total_rx_packets; |
1599 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1600 | ||
1601 | if (cleaned_count) | |
1602 | i40e_alloc_rx_buffers(rx_ring, cleaned_count); | |
1603 | ||
1604 | return budget > 0; | |
1605 | } | |
1606 | ||
1607 | /** | |
1608 | * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1609 | * @napi: napi struct with our devices info in it | |
1610 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1611 | * | |
1612 | * This function will clean all queues associated with a q_vector. | |
1613 | * | |
1614 | * Returns the amount of work done | |
1615 | **/ | |
1616 | int i40e_napi_poll(struct napi_struct *napi, int budget) | |
1617 | { | |
1618 | struct i40e_q_vector *q_vector = | |
1619 | container_of(napi, struct i40e_q_vector, napi); | |
1620 | struct i40e_vsi *vsi = q_vector->vsi; | |
cd0b6fa6 | 1621 | struct i40e_ring *ring; |
fd0a05ce | 1622 | bool clean_complete = true; |
d91649f5 | 1623 | bool arm_wb = false; |
fd0a05ce | 1624 | int budget_per_ring; |
fd0a05ce JB |
1625 | |
1626 | if (test_bit(__I40E_DOWN, &vsi->state)) { | |
1627 | napi_complete(napi); | |
1628 | return 0; | |
1629 | } | |
1630 | ||
cd0b6fa6 AD |
1631 | /* Since the actual Tx work is minimal, we can give the Tx a larger |
1632 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1633 | */ | |
d91649f5 | 1634 | i40e_for_each_ring(ring, q_vector->tx) { |
cd0b6fa6 | 1635 | clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit); |
d91649f5 JB |
1636 | arm_wb |= ring->arm_wb; |
1637 | } | |
cd0b6fa6 | 1638 | |
fd0a05ce JB |
1639 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
1640 | * allow the budget to go below 1 because that would exit polling early. | |
fd0a05ce JB |
1641 | */ |
1642 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
cd0b6fa6 AD |
1643 | |
1644 | i40e_for_each_ring(ring, q_vector->rx) | |
1645 | clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring); | |
fd0a05ce JB |
1646 | |
1647 | /* If work not completed, return budget and polling will return */ | |
d91649f5 JB |
1648 | if (!clean_complete) { |
1649 | if (arm_wb) | |
1650 | i40e_force_wb(vsi, q_vector); | |
fd0a05ce | 1651 | return budget; |
d91649f5 | 1652 | } |
fd0a05ce JB |
1653 | |
1654 | /* Work is done so exit the polling mode and re-enable the interrupt */ | |
1655 | napi_complete(napi); | |
1656 | if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) || | |
1657 | ITR_IS_DYNAMIC(vsi->tx_itr_setting)) | |
1658 | i40e_update_dynamic_itr(q_vector); | |
1659 | ||
1660 | if (!test_bit(__I40E_DOWN, &vsi->state)) { | |
1661 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { | |
1662 | i40e_irq_dynamic_enable(vsi, | |
1663 | q_vector->v_idx + vsi->base_vector); | |
1664 | } else { | |
1665 | struct i40e_hw *hw = &vsi->back->hw; | |
1666 | /* We re-enable the queue 0 cause, but | |
1667 | * don't worry about dynamic_enable | |
1668 | * because we left it on for the other | |
1669 | * possible interrupts during napi | |
1670 | */ | |
1671 | u32 qval = rd32(hw, I40E_QINT_RQCTL(0)); | |
1672 | qval |= I40E_QINT_RQCTL_CAUSE_ENA_MASK; | |
1673 | wr32(hw, I40E_QINT_RQCTL(0), qval); | |
1674 | ||
1675 | qval = rd32(hw, I40E_QINT_TQCTL(0)); | |
1676 | qval |= I40E_QINT_TQCTL_CAUSE_ENA_MASK; | |
1677 | wr32(hw, I40E_QINT_TQCTL(0), qval); | |
116a57d4 SN |
1678 | |
1679 | i40e_irq_dynamic_enable_icr0(vsi->back); | |
fd0a05ce JB |
1680 | } |
1681 | } | |
1682 | ||
1683 | return 0; | |
1684 | } | |
1685 | ||
1686 | /** | |
1687 | * i40e_atr - Add a Flow Director ATR filter | |
1688 | * @tx_ring: ring to add programming descriptor to | |
1689 | * @skb: send buffer | |
1690 | * @flags: send flags | |
1691 | * @protocol: wire protocol | |
1692 | **/ | |
1693 | static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
1694 | u32 flags, __be16 protocol) | |
1695 | { | |
1696 | struct i40e_filter_program_desc *fdir_desc; | |
1697 | struct i40e_pf *pf = tx_ring->vsi->back; | |
1698 | union { | |
1699 | unsigned char *network; | |
1700 | struct iphdr *ipv4; | |
1701 | struct ipv6hdr *ipv6; | |
1702 | } hdr; | |
1703 | struct tcphdr *th; | |
1704 | unsigned int hlen; | |
1705 | u32 flex_ptype, dtype_cmd; | |
fc4ac67b | 1706 | u16 i; |
fd0a05ce JB |
1707 | |
1708 | /* make sure ATR is enabled */ | |
60ea5f83 | 1709 | if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) |
fd0a05ce JB |
1710 | return; |
1711 | ||
1712 | /* if sampling is disabled do nothing */ | |
1713 | if (!tx_ring->atr_sample_rate) | |
1714 | return; | |
1715 | ||
fd0a05ce JB |
1716 | /* snag network header to get L4 type and address */ |
1717 | hdr.network = skb_network_header(skb); | |
1718 | ||
1719 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
1720 | if (protocol == htons(ETH_P_IP)) { | |
1721 | if (hdr.ipv4->protocol != IPPROTO_TCP) | |
1722 | return; | |
1723 | ||
1724 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1725 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1726 | } else if (protocol == htons(ETH_P_IPV6)) { | |
1727 | if (hdr.ipv6->nexthdr != IPPROTO_TCP) | |
1728 | return; | |
1729 | ||
1730 | hlen = sizeof(struct ipv6hdr); | |
1731 | } else { | |
1732 | return; | |
1733 | } | |
1734 | ||
1735 | th = (struct tcphdr *)(hdr.network + hlen); | |
1736 | ||
55a5e60b ASJ |
1737 | /* Due to lack of space, no more new filters can be programmed */ |
1738 | if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) | |
1739 | return; | |
1740 | ||
1741 | tx_ring->atr_count++; | |
1742 | ||
ce806783 ASJ |
1743 | /* sample on all syn/fin/rst packets or once every atr sample rate */ |
1744 | if (!th->fin && | |
1745 | !th->syn && | |
1746 | !th->rst && | |
1747 | (tx_ring->atr_count < tx_ring->atr_sample_rate)) | |
fd0a05ce JB |
1748 | return; |
1749 | ||
1750 | tx_ring->atr_count = 0; | |
1751 | ||
1752 | /* grab the next descriptor */ | |
fc4ac67b AD |
1753 | i = tx_ring->next_to_use; |
1754 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
1755 | ||
1756 | i++; | |
1757 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
1758 | |
1759 | flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & | |
1760 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
1761 | flex_ptype |= (protocol == htons(ETH_P_IP)) ? | |
1762 | (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << | |
1763 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : | |
1764 | (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << | |
1765 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
1766 | ||
1767 | flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
1768 | ||
1769 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
1770 | ||
ce806783 | 1771 | dtype_cmd |= (th->fin || th->rst) ? |
fd0a05ce JB |
1772 | (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
1773 | I40E_TXD_FLTR_QW1_PCMD_SHIFT) : | |
1774 | (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
1775 | I40E_TXD_FLTR_QW1_PCMD_SHIFT); | |
1776 | ||
1777 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << | |
1778 | I40E_TXD_FLTR_QW1_DEST_SHIFT; | |
1779 | ||
1780 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << | |
1781 | I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; | |
1782 | ||
433c47de ASJ |
1783 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
1784 | dtype_cmd |= | |
1785 | ((u32)pf->fd_atr_cnt_idx << I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
1786 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
1787 | ||
fd0a05ce | 1788 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); |
99753ea6 | 1789 | fdir_desc->rsvd = cpu_to_le32(0); |
fd0a05ce | 1790 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); |
99753ea6 | 1791 | fdir_desc->fd_id = cpu_to_le32(0); |
fd0a05ce JB |
1792 | } |
1793 | ||
fd0a05ce JB |
1794 | /** |
1795 | * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW | |
1796 | * @skb: send buffer | |
1797 | * @tx_ring: ring to send buffer on | |
1798 | * @flags: the tx flags to be set | |
1799 | * | |
1800 | * Checks the skb and set up correspondingly several generic transmit flags | |
1801 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
1802 | * | |
1803 | * Returns error code indicate the frame should be dropped upon error and the | |
1804 | * otherwise returns 0 to indicate the flags has been set properly. | |
1805 | **/ | |
38e00438 VD |
1806 | #ifdef I40E_FCOE |
1807 | int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, | |
1808 | struct i40e_ring *tx_ring, | |
1809 | u32 *flags) | |
1810 | #else | |
fd0a05ce JB |
1811 | static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, |
1812 | struct i40e_ring *tx_ring, | |
1813 | u32 *flags) | |
38e00438 | 1814 | #endif |
fd0a05ce JB |
1815 | { |
1816 | __be16 protocol = skb->protocol; | |
1817 | u32 tx_flags = 0; | |
1818 | ||
1819 | /* if we have a HW VLAN tag being added, default to the HW one */ | |
df8a39de JP |
1820 | if (skb_vlan_tag_present(skb)) { |
1821 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
fd0a05ce JB |
1822 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
1823 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
0e2fe46c | 1824 | } else if (protocol == htons(ETH_P_8021Q)) { |
fd0a05ce JB |
1825 | struct vlan_hdr *vhdr, _vhdr; |
1826 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
1827 | if (!vhdr) | |
1828 | return -EINVAL; | |
1829 | ||
1830 | protocol = vhdr->h_vlan_encapsulated_proto; | |
1831 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
1832 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
1833 | } | |
1834 | ||
1835 | /* Insert 802.1p priority into VLAN header */ | |
38e00438 VD |
1836 | if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || |
1837 | (skb->priority != TC_PRIO_CONTROL)) { | |
fd0a05ce JB |
1838 | tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; |
1839 | tx_flags |= (skb->priority & 0x7) << | |
1840 | I40E_TX_FLAGS_VLAN_PRIO_SHIFT; | |
1841 | if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { | |
1842 | struct vlan_ethhdr *vhdr; | |
dd225bc6 FR |
1843 | int rc; |
1844 | ||
1845 | rc = skb_cow_head(skb, 0); | |
1846 | if (rc < 0) | |
1847 | return rc; | |
fd0a05ce JB |
1848 | vhdr = (struct vlan_ethhdr *)skb->data; |
1849 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
1850 | I40E_TX_FLAGS_VLAN_SHIFT); | |
1851 | } else { | |
1852 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; | |
1853 | } | |
1854 | } | |
1855 | *flags = tx_flags; | |
1856 | return 0; | |
1857 | } | |
1858 | ||
fd0a05ce JB |
1859 | /** |
1860 | * i40e_tso - set up the tso context descriptor | |
1861 | * @tx_ring: ptr to the ring to send | |
1862 | * @skb: ptr to the skb we're sending | |
1863 | * @tx_flags: the collected send information | |
1864 | * @protocol: the send protocol | |
1865 | * @hdr_len: ptr to the size of the packet header | |
1866 | * @cd_tunneling: ptr to context descriptor bits | |
1867 | * | |
1868 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
1869 | **/ | |
1870 | static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
1871 | u32 tx_flags, __be16 protocol, u8 *hdr_len, | |
1872 | u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling) | |
1873 | { | |
1874 | u32 cd_cmd, cd_tso_len, cd_mss; | |
dd225bc6 | 1875 | struct ipv6hdr *ipv6h; |
fd0a05ce JB |
1876 | struct tcphdr *tcph; |
1877 | struct iphdr *iph; | |
1878 | u32 l4len; | |
1879 | int err; | |
fd0a05ce JB |
1880 | |
1881 | if (!skb_is_gso(skb)) | |
1882 | return 0; | |
1883 | ||
dd225bc6 FR |
1884 | err = skb_cow_head(skb, 0); |
1885 | if (err < 0) | |
1886 | return err; | |
fd0a05ce | 1887 | |
df23075f AS |
1888 | iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb); |
1889 | ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); | |
1890 | ||
1891 | if (iph->version == 4) { | |
fd0a05ce JB |
1892 | tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); |
1893 | iph->tot_len = 0; | |
1894 | iph->check = 0; | |
1895 | tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, | |
1896 | 0, IPPROTO_TCP, 0); | |
df23075f | 1897 | } else if (ipv6h->version == 6) { |
fd0a05ce JB |
1898 | tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); |
1899 | ipv6h->payload_len = 0; | |
1900 | tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, | |
1901 | 0, IPPROTO_TCP, 0); | |
1902 | } | |
1903 | ||
1904 | l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); | |
1905 | *hdr_len = (skb->encapsulation | |
1906 | ? (skb_inner_transport_header(skb) - skb->data) | |
1907 | : skb_transport_offset(skb)) + l4len; | |
1908 | ||
1909 | /* find the field values */ | |
1910 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
1911 | cd_tso_len = skb->len - *hdr_len; | |
1912 | cd_mss = skb_shinfo(skb)->gso_size; | |
829af3ac MW |
1913 | *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
1914 | ((u64)cd_tso_len << | |
1915 | I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
1916 | ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
fd0a05ce JB |
1917 | return 1; |
1918 | } | |
1919 | ||
beb0dff1 JK |
1920 | /** |
1921 | * i40e_tsyn - set up the tsyn context descriptor | |
1922 | * @tx_ring: ptr to the ring to send | |
1923 | * @skb: ptr to the skb we're sending | |
1924 | * @tx_flags: the collected send information | |
1925 | * | |
1926 | * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen | |
1927 | **/ | |
1928 | static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
1929 | u32 tx_flags, u64 *cd_type_cmd_tso_mss) | |
1930 | { | |
1931 | struct i40e_pf *pf; | |
1932 | ||
1933 | if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) | |
1934 | return 0; | |
1935 | ||
1936 | /* Tx timestamps cannot be sampled when doing TSO */ | |
1937 | if (tx_flags & I40E_TX_FLAGS_TSO) | |
1938 | return 0; | |
1939 | ||
1940 | /* only timestamp the outbound packet if the user has requested it and | |
1941 | * we are not already transmitting a packet to be timestamped | |
1942 | */ | |
1943 | pf = i40e_netdev_to_pf(tx_ring->netdev); | |
22b4777d JK |
1944 | if (!(pf->flags & I40E_FLAG_PTP)) |
1945 | return 0; | |
1946 | ||
9ce34f02 JK |
1947 | if (pf->ptp_tx && |
1948 | !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { | |
beb0dff1 JK |
1949 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
1950 | pf->ptp_tx_skb = skb_get(skb); | |
1951 | } else { | |
1952 | return 0; | |
1953 | } | |
1954 | ||
1955 | *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << | |
1956 | I40E_TXD_CTX_QW1_CMD_SHIFT; | |
1957 | ||
beb0dff1 JK |
1958 | return 1; |
1959 | } | |
1960 | ||
fd0a05ce JB |
1961 | /** |
1962 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
1963 | * @skb: send buffer | |
1964 | * @tx_flags: Tx flags currently set | |
1965 | * @td_cmd: Tx descriptor command bits to set | |
1966 | * @td_offset: Tx descriptor header offsets to set | |
1967 | * @cd_tunneling: ptr to context desc bits | |
1968 | **/ | |
1969 | static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags, | |
1970 | u32 *td_cmd, u32 *td_offset, | |
1971 | struct i40e_ring *tx_ring, | |
1972 | u32 *cd_tunneling) | |
1973 | { | |
1974 | struct ipv6hdr *this_ipv6_hdr; | |
1975 | unsigned int this_tcp_hdrlen; | |
1976 | struct iphdr *this_ip_hdr; | |
1977 | u32 network_hdr_len; | |
1978 | u8 l4_hdr = 0; | |
1979 | ||
1980 | if (skb->encapsulation) { | |
1981 | network_hdr_len = skb_inner_network_header_len(skb); | |
1982 | this_ip_hdr = inner_ip_hdr(skb); | |
1983 | this_ipv6_hdr = inner_ipv6_hdr(skb); | |
1984 | this_tcp_hdrlen = inner_tcp_hdrlen(skb); | |
1985 | ||
1986 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
1987 | ||
1988 | if (tx_flags & I40E_TX_FLAGS_TSO) { | |
1989 | *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4; | |
1990 | ip_hdr(skb)->check = 0; | |
1991 | } else { | |
1992 | *cd_tunneling |= | |
1993 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
1994 | } | |
1995 | } else if (tx_flags & I40E_TX_FLAGS_IPV6) { | |
df23075f AS |
1996 | *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6; |
1997 | if (tx_flags & I40E_TX_FLAGS_TSO) | |
fd0a05ce | 1998 | ip_hdr(skb)->check = 0; |
fd0a05ce JB |
1999 | } |
2000 | ||
2001 | /* Now set the ctx descriptor fields */ | |
2002 | *cd_tunneling |= (skb_network_header_len(skb) >> 2) << | |
2003 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT | | |
2004 | I40E_TXD_CTX_UDP_TUNNELING | | |
2005 | ((skb_inner_network_offset(skb) - | |
2006 | skb_transport_offset(skb)) >> 1) << | |
2007 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
df23075f AS |
2008 | if (this_ip_hdr->version == 6) { |
2009 | tx_flags &= ~I40E_TX_FLAGS_IPV4; | |
2010 | tx_flags |= I40E_TX_FLAGS_IPV6; | |
2011 | } | |
fd0a05ce JB |
2012 | } else { |
2013 | network_hdr_len = skb_network_header_len(skb); | |
2014 | this_ip_hdr = ip_hdr(skb); | |
2015 | this_ipv6_hdr = ipv6_hdr(skb); | |
2016 | this_tcp_hdrlen = tcp_hdrlen(skb); | |
2017 | } | |
2018 | ||
2019 | /* Enable IP checksum offloads */ | |
2020 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
2021 | l4_hdr = this_ip_hdr->protocol; | |
2022 | /* the stack computes the IP header already, the only time we | |
2023 | * need the hardware to recompute it is in the case of TSO. | |
2024 | */ | |
2025 | if (tx_flags & I40E_TX_FLAGS_TSO) { | |
2026 | *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM; | |
2027 | this_ip_hdr->check = 0; | |
2028 | } else { | |
2029 | *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4; | |
2030 | } | |
2031 | /* Now set the td_offset for IP header length */ | |
2032 | *td_offset = (network_hdr_len >> 2) << | |
2033 | I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
2034 | } else if (tx_flags & I40E_TX_FLAGS_IPV6) { | |
2035 | l4_hdr = this_ipv6_hdr->nexthdr; | |
2036 | *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; | |
2037 | /* Now set the td_offset for IP header length */ | |
2038 | *td_offset = (network_hdr_len >> 2) << | |
2039 | I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
2040 | } | |
2041 | /* words in MACLEN + dwords in IPLEN + dwords in L4Len */ | |
2042 | *td_offset |= (skb_network_offset(skb) >> 1) << | |
2043 | I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
2044 | ||
2045 | /* Enable L4 checksum offloads */ | |
2046 | switch (l4_hdr) { | |
2047 | case IPPROTO_TCP: | |
2048 | /* enable checksum offloads */ | |
2049 | *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; | |
2050 | *td_offset |= (this_tcp_hdrlen >> 2) << | |
2051 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
2052 | break; | |
2053 | case IPPROTO_SCTP: | |
2054 | /* enable SCTP checksum offload */ | |
2055 | *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; | |
2056 | *td_offset |= (sizeof(struct sctphdr) >> 2) << | |
2057 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
2058 | break; | |
2059 | case IPPROTO_UDP: | |
2060 | /* enable UDP checksum offload */ | |
2061 | *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; | |
2062 | *td_offset |= (sizeof(struct udphdr) >> 2) << | |
2063 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
2064 | break; | |
2065 | default: | |
2066 | break; | |
2067 | } | |
2068 | } | |
2069 | ||
2070 | /** | |
2071 | * i40e_create_tx_ctx Build the Tx context descriptor | |
2072 | * @tx_ring: ring to create the descriptor on | |
2073 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
2074 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
2075 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
2076 | **/ | |
2077 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
2078 | const u64 cd_type_cmd_tso_mss, | |
2079 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
2080 | { | |
2081 | struct i40e_tx_context_desc *context_desc; | |
fc4ac67b | 2082 | int i = tx_ring->next_to_use; |
fd0a05ce | 2083 | |
ff40dd5d JB |
2084 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
2085 | !cd_tunneling && !cd_l2tag2) | |
fd0a05ce JB |
2086 | return; |
2087 | ||
2088 | /* grab the next descriptor */ | |
fc4ac67b AD |
2089 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); |
2090 | ||
2091 | i++; | |
2092 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2093 | |
2094 | /* cpu_to_le32 and assign to struct fields */ | |
2095 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
2096 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 2097 | context_desc->rsvd = cpu_to_le16(0); |
fd0a05ce JB |
2098 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
2099 | } | |
2100 | ||
4567dc10 ED |
2101 | /** |
2102 | * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions | |
2103 | * @tx_ring: the ring to be checked | |
2104 | * @size: the size buffer we want to assure is available | |
2105 | * | |
2106 | * Returns -EBUSY if a stop is needed, else 0 | |
2107 | **/ | |
2108 | static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) | |
2109 | { | |
2110 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2111 | /* Memory barrier before checking head and tail */ | |
2112 | smp_mb(); | |
2113 | ||
2114 | /* Check again in a case another CPU has just made room available. */ | |
2115 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
2116 | return -EBUSY; | |
2117 | ||
2118 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
2119 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2120 | ++tx_ring->tx_stats.restart_queue; | |
2121 | return 0; | |
2122 | } | |
2123 | ||
2124 | /** | |
2125 | * i40e_maybe_stop_tx - 1st level check for tx stop conditions | |
2126 | * @tx_ring: the ring to be checked | |
2127 | * @size: the size buffer we want to assure is available | |
2128 | * | |
2129 | * Returns 0 if stop is not needed | |
2130 | **/ | |
2131 | #ifdef I40E_FCOE | |
2132 | int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) | |
2133 | #else | |
2134 | static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) | |
2135 | #endif | |
2136 | { | |
2137 | if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) | |
2138 | return 0; | |
2139 | return __i40e_maybe_stop_tx(tx_ring, size); | |
2140 | } | |
2141 | ||
fd0a05ce JB |
2142 | /** |
2143 | * i40e_tx_map - Build the Tx descriptor | |
2144 | * @tx_ring: ring to send buffer on | |
2145 | * @skb: send buffer | |
2146 | * @first: first buffer info buffer to use | |
2147 | * @tx_flags: collected send information | |
2148 | * @hdr_len: size of the packet header | |
2149 | * @td_cmd: the command field in the descriptor | |
2150 | * @td_offset: offset for checksum or crc | |
2151 | **/ | |
38e00438 VD |
2152 | #ifdef I40E_FCOE |
2153 | void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2154 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2155 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
2156 | #else | |
fd0a05ce JB |
2157 | static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
2158 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2159 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
38e00438 | 2160 | #endif |
fd0a05ce | 2161 | { |
fd0a05ce JB |
2162 | unsigned int data_len = skb->data_len; |
2163 | unsigned int size = skb_headlen(skb); | |
a5e9c572 | 2164 | struct skb_frag_struct *frag; |
fd0a05ce JB |
2165 | struct i40e_tx_buffer *tx_bi; |
2166 | struct i40e_tx_desc *tx_desc; | |
a5e9c572 | 2167 | u16 i = tx_ring->next_to_use; |
fd0a05ce JB |
2168 | u32 td_tag = 0; |
2169 | dma_addr_t dma; | |
2170 | u16 gso_segs; | |
2171 | ||
fd0a05ce JB |
2172 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { |
2173 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2174 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2175 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2176 | } | |
2177 | ||
a5e9c572 AD |
2178 | if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) |
2179 | gso_segs = skb_shinfo(skb)->gso_segs; | |
2180 | else | |
2181 | gso_segs = 1; | |
2182 | ||
2183 | /* multiply data chunks by size of headers */ | |
2184 | first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); | |
2185 | first->gso_segs = gso_segs; | |
2186 | first->skb = skb; | |
2187 | first->tx_flags = tx_flags; | |
2188 | ||
2189 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2190 | ||
fd0a05ce | 2191 | tx_desc = I40E_TX_DESC(tx_ring, i); |
a5e9c572 AD |
2192 | tx_bi = first; |
2193 | ||
2194 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
2195 | if (dma_mapping_error(tx_ring->dev, dma)) | |
2196 | goto dma_error; | |
2197 | ||
2198 | /* record length, and DMA address */ | |
2199 | dma_unmap_len_set(tx_bi, len, size); | |
2200 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2201 | ||
2202 | tx_desc->buffer_addr = cpu_to_le64(dma); | |
2203 | ||
2204 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
fd0a05ce JB |
2205 | tx_desc->cmd_type_offset_bsz = |
2206 | build_ctob(td_cmd, td_offset, | |
2207 | I40E_MAX_DATA_PER_TXD, td_tag); | |
2208 | ||
fd0a05ce JB |
2209 | tx_desc++; |
2210 | i++; | |
2211 | if (i == tx_ring->count) { | |
2212 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2213 | i = 0; | |
2214 | } | |
fd0a05ce | 2215 | |
a5e9c572 AD |
2216 | dma += I40E_MAX_DATA_PER_TXD; |
2217 | size -= I40E_MAX_DATA_PER_TXD; | |
fd0a05ce | 2218 | |
a5e9c572 AD |
2219 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2220 | } | |
fd0a05ce JB |
2221 | |
2222 | if (likely(!data_len)) | |
2223 | break; | |
2224 | ||
a5e9c572 AD |
2225 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, |
2226 | size, td_tag); | |
fd0a05ce JB |
2227 | |
2228 | tx_desc++; | |
2229 | i++; | |
2230 | if (i == tx_ring->count) { | |
2231 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2232 | i = 0; | |
2233 | } | |
2234 | ||
a5e9c572 AD |
2235 | size = skb_frag_size(frag); |
2236 | data_len -= size; | |
fd0a05ce | 2237 | |
a5e9c572 AD |
2238 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
2239 | DMA_TO_DEVICE); | |
fd0a05ce | 2240 | |
a5e9c572 AD |
2241 | tx_bi = &tx_ring->tx_bi[i]; |
2242 | } | |
fd0a05ce | 2243 | |
1943d8ba JB |
2244 | /* Place RS bit on last descriptor of any packet that spans across the |
2245 | * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline. | |
2246 | */ | |
1943d8ba JB |
2247 | if (((i & WB_STRIDE) != WB_STRIDE) && |
2248 | (first <= &tx_ring->tx_bi[i]) && | |
2249 | (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) { | |
2250 | tx_desc->cmd_type_offset_bsz = | |
2251 | build_ctob(td_cmd, td_offset, size, td_tag) | | |
2252 | cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP << | |
2253 | I40E_TXD_QW1_CMD_SHIFT); | |
2254 | } else { | |
2255 | tx_desc->cmd_type_offset_bsz = | |
2256 | build_ctob(td_cmd, td_offset, size, td_tag) | | |
2257 | cpu_to_le64((u64)I40E_TXD_CMD << | |
2258 | I40E_TXD_QW1_CMD_SHIFT); | |
2259 | } | |
fd0a05ce | 2260 | |
7070ce0a AD |
2261 | netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, |
2262 | tx_ring->queue_index), | |
2263 | first->bytecount); | |
2264 | ||
a5e9c572 | 2265 | /* set the timestamp */ |
fd0a05ce | 2266 | first->time_stamp = jiffies; |
fd0a05ce JB |
2267 | |
2268 | /* Force memory writes to complete before letting h/w | |
2269 | * know there are new descriptors to fetch. (Only | |
2270 | * applicable for weak-ordered memory model archs, | |
2271 | * such as IA-64). | |
2272 | */ | |
2273 | wmb(); | |
2274 | ||
a5e9c572 AD |
2275 | /* set next_to_watch value indicating a packet is present */ |
2276 | first->next_to_watch = tx_desc; | |
2277 | ||
2278 | i++; | |
2279 | if (i == tx_ring->count) | |
2280 | i = 0; | |
2281 | ||
2282 | tx_ring->next_to_use = i; | |
2283 | ||
4567dc10 | 2284 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
a5e9c572 | 2285 | /* notify HW of packet */ |
4567dc10 ED |
2286 | if (!skb->xmit_more || |
2287 | netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, | |
2288 | tx_ring->queue_index))) | |
2289 | writel(i, tx_ring->tail); | |
a5e9c572 | 2290 | |
fd0a05ce JB |
2291 | return; |
2292 | ||
2293 | dma_error: | |
a5e9c572 | 2294 | dev_info(tx_ring->dev, "TX DMA map failed\n"); |
fd0a05ce JB |
2295 | |
2296 | /* clear dma mappings for failed tx_bi map */ | |
2297 | for (;;) { | |
2298 | tx_bi = &tx_ring->tx_bi[i]; | |
a5e9c572 | 2299 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); |
fd0a05ce JB |
2300 | if (tx_bi == first) |
2301 | break; | |
2302 | if (i == 0) | |
2303 | i = tx_ring->count; | |
2304 | i--; | |
2305 | } | |
2306 | ||
fd0a05ce JB |
2307 | tx_ring->next_to_use = i; |
2308 | } | |
2309 | ||
fd0a05ce JB |
2310 | /** |
2311 | * i40e_xmit_descriptor_count - calculate number of tx descriptors needed | |
2312 | * @skb: send buffer | |
2313 | * @tx_ring: ring to send buffer on | |
2314 | * | |
2315 | * Returns number of data descriptors needed for this skb. Returns 0 to indicate | |
2316 | * there is not enough descriptors available in this ring since we need at least | |
2317 | * one descriptor. | |
2318 | **/ | |
38e00438 VD |
2319 | #ifdef I40E_FCOE |
2320 | int i40e_xmit_descriptor_count(struct sk_buff *skb, | |
2321 | struct i40e_ring *tx_ring) | |
2322 | #else | |
fd0a05ce JB |
2323 | static int i40e_xmit_descriptor_count(struct sk_buff *skb, |
2324 | struct i40e_ring *tx_ring) | |
38e00438 | 2325 | #endif |
fd0a05ce | 2326 | { |
fd0a05ce | 2327 | unsigned int f; |
fd0a05ce JB |
2328 | int count = 0; |
2329 | ||
2330 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
2331 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
be560521 | 2332 | * + 4 desc gap to avoid the cache line where head is, |
fd0a05ce JB |
2333 | * + 1 desc for context descriptor, |
2334 | * otherwise try next time | |
2335 | */ | |
fd0a05ce JB |
2336 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
2337 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
980093eb | 2338 | |
fd0a05ce | 2339 | count += TXD_USE_COUNT(skb_headlen(skb)); |
be560521 | 2340 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { |
fd0a05ce JB |
2341 | tx_ring->tx_stats.tx_busy++; |
2342 | return 0; | |
2343 | } | |
2344 | return count; | |
2345 | } | |
2346 | ||
2347 | /** | |
2348 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
2349 | * @skb: send buffer | |
2350 | * @tx_ring: ring to send buffer on | |
2351 | * | |
2352 | * Returns NETDEV_TX_OK if sent, else an error code | |
2353 | **/ | |
2354 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
2355 | struct i40e_ring *tx_ring) | |
2356 | { | |
2357 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
2358 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
2359 | struct i40e_tx_buffer *first; | |
2360 | u32 td_offset = 0; | |
2361 | u32 tx_flags = 0; | |
2362 | __be16 protocol; | |
2363 | u32 td_cmd = 0; | |
2364 | u8 hdr_len = 0; | |
beb0dff1 | 2365 | int tsyn; |
fd0a05ce JB |
2366 | int tso; |
2367 | if (0 == i40e_xmit_descriptor_count(skb, tx_ring)) | |
2368 | return NETDEV_TX_BUSY; | |
2369 | ||
2370 | /* prepare the xmit flags */ | |
2371 | if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) | |
2372 | goto out_drop; | |
2373 | ||
2374 | /* obtain protocol of skb */ | |
3d34dd03 | 2375 | protocol = vlan_get_protocol(skb); |
fd0a05ce JB |
2376 | |
2377 | /* record the location of the first descriptor for this packet */ | |
2378 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
2379 | ||
2380 | /* setup IPv4/IPv6 offloads */ | |
0e2fe46c | 2381 | if (protocol == htons(ETH_P_IP)) |
fd0a05ce | 2382 | tx_flags |= I40E_TX_FLAGS_IPV4; |
0e2fe46c | 2383 | else if (protocol == htons(ETH_P_IPV6)) |
fd0a05ce JB |
2384 | tx_flags |= I40E_TX_FLAGS_IPV6; |
2385 | ||
2386 | tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len, | |
2387 | &cd_type_cmd_tso_mss, &cd_tunneling); | |
2388 | ||
2389 | if (tso < 0) | |
2390 | goto out_drop; | |
2391 | else if (tso) | |
2392 | tx_flags |= I40E_TX_FLAGS_TSO; | |
2393 | ||
beb0dff1 JK |
2394 | tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); |
2395 | ||
2396 | if (tsyn) | |
2397 | tx_flags |= I40E_TX_FLAGS_TSYN; | |
2398 | ||
259afec7 JK |
2399 | skb_tx_timestamp(skb); |
2400 | ||
b1941306 AD |
2401 | /* always enable CRC insertion offload */ |
2402 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
2403 | ||
fd0a05ce | 2404 | /* Always offload the checksum, since it's in the data descriptor */ |
b1941306 | 2405 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
fd0a05ce JB |
2406 | tx_flags |= I40E_TX_FLAGS_CSUM; |
2407 | ||
fd0a05ce JB |
2408 | i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset, |
2409 | tx_ring, &cd_tunneling); | |
b1941306 | 2410 | } |
fd0a05ce JB |
2411 | |
2412 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, | |
2413 | cd_tunneling, cd_l2tag2); | |
2414 | ||
2415 | /* Add Flow Director ATR if it's enabled. | |
2416 | * | |
2417 | * NOTE: this must always be directly before the data descriptor. | |
2418 | */ | |
2419 | i40e_atr(tx_ring, skb, tx_flags, protocol); | |
2420 | ||
2421 | i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, | |
2422 | td_cmd, td_offset); | |
2423 | ||
fd0a05ce JB |
2424 | return NETDEV_TX_OK; |
2425 | ||
2426 | out_drop: | |
2427 | dev_kfree_skb_any(skb); | |
2428 | return NETDEV_TX_OK; | |
2429 | } | |
2430 | ||
2431 | /** | |
2432 | * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
2433 | * @skb: send buffer | |
2434 | * @netdev: network interface device structure | |
2435 | * | |
2436 | * Returns NETDEV_TX_OK if sent, else an error code | |
2437 | **/ | |
2438 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2439 | { | |
2440 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2441 | struct i40e_vsi *vsi = np->vsi; | |
9f65e15b | 2442 | struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; |
fd0a05ce JB |
2443 | |
2444 | /* hardware can't handle really short frames, hardware padding works | |
2445 | * beyond this point | |
2446 | */ | |
a94d9e22 AD |
2447 | if (skb_put_padto(skb, I40E_MIN_TX_LEN)) |
2448 | return NETDEV_TX_OK; | |
fd0a05ce JB |
2449 | |
2450 | return i40e_xmit_frame_ring(skb, tx_ring); | |
2451 | } |