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fd0a05ce JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
fd0a05ce JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
fd0a05ce JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
1c112a64 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
fd0a05ce | 29 | #include "i40e.h" |
206812b5 | 30 | #include "i40e_prototype.h" |
fd0a05ce JB |
31 | |
32 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
33 | u32 td_tag) | |
34 | { | |
35 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
36 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
37 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
38 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
39 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
40 | } | |
41 | ||
eaefbd06 | 42 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) |
5e02f283 AD |
43 | /** |
44 | * i40e_fdir - Generate a Flow Director descriptor based on fdata | |
45 | * @tx_ring: Tx ring to send buffer on | |
46 | * @fdata: Flow director filter data | |
47 | * @add: Indicate if we are adding a rule or deleting one | |
48 | * | |
49 | **/ | |
50 | static void i40e_fdir(struct i40e_ring *tx_ring, | |
51 | struct i40e_fdir_filter *fdata, bool add) | |
52 | { | |
53 | struct i40e_filter_program_desc *fdir_desc; | |
54 | struct i40e_pf *pf = tx_ring->vsi->back; | |
55 | u32 flex_ptype, dtype_cmd; | |
56 | u16 i; | |
57 | ||
58 | /* grab the next descriptor */ | |
59 | i = tx_ring->next_to_use; | |
60 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
61 | ||
62 | i++; | |
63 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
64 | ||
65 | flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & | |
66 | (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); | |
67 | ||
68 | flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & | |
69 | (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); | |
70 | ||
71 | flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & | |
72 | (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
73 | ||
0e588de1 JK |
74 | flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & |
75 | (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); | |
76 | ||
5e02f283 AD |
77 | /* Use LAN VSI Id if not programmed by user */ |
78 | flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & | |
79 | ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << | |
80 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); | |
81 | ||
82 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
83 | ||
84 | dtype_cmd |= add ? | |
85 | I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
86 | I40E_TXD_FLTR_QW1_PCMD_SHIFT : | |
87 | I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << | |
88 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
89 | ||
90 | dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & | |
91 | (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); | |
92 | ||
93 | dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & | |
94 | (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); | |
95 | ||
96 | if (fdata->cnt_index) { | |
97 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; | |
98 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & | |
99 | ((u32)fdata->cnt_index << | |
100 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); | |
101 | } | |
102 | ||
103 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); | |
104 | fdir_desc->rsvd = cpu_to_le32(0); | |
105 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); | |
106 | fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); | |
107 | } | |
108 | ||
49d7d933 | 109 | #define I40E_FD_CLEAN_DELAY 10 |
fd0a05ce JB |
110 | /** |
111 | * i40e_program_fdir_filter - Program a Flow Director filter | |
17a73f6b JG |
112 | * @fdir_data: Packet data that will be filter parameters |
113 | * @raw_packet: the pre-allocated packet buffer for FDir | |
b40c82e6 | 114 | * @pf: The PF pointer |
fd0a05ce JB |
115 | * @add: True for add/update, False for remove |
116 | **/ | |
1eb846ac AD |
117 | static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, |
118 | u8 *raw_packet, struct i40e_pf *pf, | |
119 | bool add) | |
fd0a05ce | 120 | { |
49d7d933 | 121 | struct i40e_tx_buffer *tx_buf, *first; |
fd0a05ce JB |
122 | struct i40e_tx_desc *tx_desc; |
123 | struct i40e_ring *tx_ring; | |
124 | struct i40e_vsi *vsi; | |
125 | struct device *dev; | |
126 | dma_addr_t dma; | |
127 | u32 td_cmd = 0; | |
128 | u16 i; | |
129 | ||
130 | /* find existing FDIR VSI */ | |
4b816446 | 131 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
fd0a05ce JB |
132 | if (!vsi) |
133 | return -ENOENT; | |
134 | ||
9f65e15b | 135 | tx_ring = vsi->tx_rings[0]; |
fd0a05ce JB |
136 | dev = tx_ring->dev; |
137 | ||
49d7d933 | 138 | /* we need two descriptors to add/del a filter and we can wait */ |
ed245406 AD |
139 | for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { |
140 | if (!i) | |
141 | return -EAGAIN; | |
49d7d933 | 142 | msleep_interruptible(1); |
ed245406 | 143 | } |
49d7d933 | 144 | |
17a73f6b JG |
145 | dma = dma_map_single(dev, raw_packet, |
146 | I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); | |
fd0a05ce JB |
147 | if (dma_mapping_error(dev, dma)) |
148 | goto dma_fail; | |
149 | ||
150 | /* grab the next descriptor */ | |
fc4ac67b | 151 | i = tx_ring->next_to_use; |
49d7d933 | 152 | first = &tx_ring->tx_bi[i]; |
5e02f283 | 153 | i40e_fdir(tx_ring, fdir_data, add); |
fd0a05ce JB |
154 | |
155 | /* Now program a dummy descriptor */ | |
fc4ac67b AD |
156 | i = tx_ring->next_to_use; |
157 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
298deef1 | 158 | tx_buf = &tx_ring->tx_bi[i]; |
fc4ac67b | 159 | |
49d7d933 ASJ |
160 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
161 | ||
162 | memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); | |
fd0a05ce | 163 | |
298deef1 | 164 | /* record length, and DMA address */ |
17a73f6b | 165 | dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); |
298deef1 ASJ |
166 | dma_unmap_addr_set(tx_buf, dma, dma); |
167 | ||
fd0a05ce | 168 | tx_desc->buffer_addr = cpu_to_le64(dma); |
eaefbd06 | 169 | td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; |
fd0a05ce | 170 | |
49d7d933 ASJ |
171 | tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; |
172 | tx_buf->raw_buf = (void *)raw_packet; | |
173 | ||
fd0a05ce | 174 | tx_desc->cmd_type_offset_bsz = |
17a73f6b | 175 | build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); |
fd0a05ce | 176 | |
fd0a05ce | 177 | /* Force memory writes to complete before letting h/w |
49d7d933 | 178 | * know there are new descriptors to fetch. |
fd0a05ce JB |
179 | */ |
180 | wmb(); | |
181 | ||
fc4ac67b | 182 | /* Mark the data descriptor to be watched */ |
49d7d933 | 183 | first->next_to_watch = tx_desc; |
fc4ac67b | 184 | |
fd0a05ce JB |
185 | writel(tx_ring->next_to_use, tx_ring->tail); |
186 | return 0; | |
187 | ||
188 | dma_fail: | |
189 | return -1; | |
190 | } | |
191 | ||
17a73f6b JG |
192 | #define IP_HEADER_OFFSET 14 |
193 | #define I40E_UDPIP_DUMMY_PACKET_LEN 42 | |
194 | /** | |
195 | * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters | |
196 | * @vsi: pointer to the targeted VSI | |
197 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
198 | * @add: true adds a filter, false removes it |
199 | * | |
200 | * Returns 0 if the filters were successfully added or removed | |
201 | **/ | |
202 | static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, | |
203 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 204 | bool add) |
17a73f6b JG |
205 | { |
206 | struct i40e_pf *pf = vsi->back; | |
207 | struct udphdr *udp; | |
208 | struct iphdr *ip; | |
49d7d933 | 209 | u8 *raw_packet; |
17a73f6b | 210 | int ret; |
17a73f6b JG |
211 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, |
212 | 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, | |
213 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
214 | ||
49d7d933 ASJ |
215 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
216 | if (!raw_packet) | |
217 | return -ENOMEM; | |
17a73f6b JG |
218 | memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); |
219 | ||
220 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
221 | udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET | |
222 | + sizeof(struct iphdr)); | |
223 | ||
8ce43dce | 224 | ip->daddr = fd_data->dst_ip; |
17a73f6b | 225 | udp->dest = fd_data->dst_port; |
8ce43dce | 226 | ip->saddr = fd_data->src_ip; |
17a73f6b JG |
227 | udp->source = fd_data->src_port; |
228 | ||
0e588de1 JK |
229 | if (fd_data->flex_filter) { |
230 | u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN; | |
231 | __be16 pattern = fd_data->flex_word; | |
232 | u16 off = fd_data->flex_offset; | |
233 | ||
234 | *((__force __be16 *)(payload + off)) = pattern; | |
235 | } | |
236 | ||
b2d36c03 KS |
237 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; |
238 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
239 | if (ret) { | |
240 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
241 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
242 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
243 | /* Free the packet buffer since it wasn't added to the ring */ |
244 | kfree(raw_packet); | |
245 | return -EOPNOTSUPP; | |
4205d379 | 246 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
247 | if (add) |
248 | dev_info(&pf->pdev->dev, | |
249 | "Filter OK for PCTYPE %d loc = %d\n", | |
250 | fd_data->pctype, fd_data->fd_id); | |
251 | else | |
252 | dev_info(&pf->pdev->dev, | |
253 | "Filter deleted for PCTYPE %d loc = %d\n", | |
254 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b | 255 | } |
a42e7a36 | 256 | |
097dbf52 JK |
257 | if (add) |
258 | pf->fd_udp4_filter_cnt++; | |
259 | else | |
260 | pf->fd_udp4_filter_cnt--; | |
261 | ||
e5187ee3 | 262 | return 0; |
17a73f6b JG |
263 | } |
264 | ||
265 | #define I40E_TCPIP_DUMMY_PACKET_LEN 54 | |
266 | /** | |
267 | * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters | |
268 | * @vsi: pointer to the targeted VSI | |
269 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
270 | * @add: true adds a filter, false removes it |
271 | * | |
272 | * Returns 0 if the filters were successfully added or removed | |
273 | **/ | |
274 | static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, | |
275 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 276 | bool add) |
17a73f6b JG |
277 | { |
278 | struct i40e_pf *pf = vsi->back; | |
279 | struct tcphdr *tcp; | |
280 | struct iphdr *ip; | |
49d7d933 | 281 | u8 *raw_packet; |
17a73f6b JG |
282 | int ret; |
283 | /* Dummy packet */ | |
284 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
285 | 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, | |
286 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, | |
287 | 0x0, 0x72, 0, 0, 0, 0}; | |
288 | ||
49d7d933 ASJ |
289 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
290 | if (!raw_packet) | |
291 | return -ENOMEM; | |
17a73f6b JG |
292 | memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); |
293 | ||
294 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
295 | tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET | |
296 | + sizeof(struct iphdr)); | |
297 | ||
8ce43dce | 298 | ip->daddr = fd_data->dst_ip; |
17a73f6b | 299 | tcp->dest = fd_data->dst_port; |
8ce43dce | 300 | ip->saddr = fd_data->src_ip; |
17a73f6b JG |
301 | tcp->source = fd_data->src_port; |
302 | ||
0e588de1 JK |
303 | if (fd_data->flex_filter) { |
304 | u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN; | |
305 | __be16 pattern = fd_data->flex_word; | |
306 | u16 off = fd_data->flex_offset; | |
307 | ||
308 | *((__force __be16 *)(payload + off)) = pattern; | |
309 | } | |
310 | ||
b2d36c03 | 311 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; |
17a73f6b | 312 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); |
17a73f6b JG |
313 | if (ret) { |
314 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
315 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
316 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
317 | /* Free the packet buffer since it wasn't added to the ring */ |
318 | kfree(raw_packet); | |
319 | return -EOPNOTSUPP; | |
4205d379 | 320 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
321 | if (add) |
322 | dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", | |
323 | fd_data->pctype, fd_data->fd_id); | |
324 | else | |
325 | dev_info(&pf->pdev->dev, | |
326 | "Filter deleted for PCTYPE %d loc = %d\n", | |
327 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
328 | } |
329 | ||
377cc249 | 330 | if (add) { |
097dbf52 | 331 | pf->fd_tcp4_filter_cnt++; |
377cc249 JK |
332 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
333 | I40E_DEBUG_FD & pf->hw.debug_mask) | |
334 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); | |
335 | pf->hw_disabled_flags |= I40E_FLAG_FD_ATR_ENABLED; | |
336 | } else { | |
097dbf52 JK |
337 | pf->fd_tcp4_filter_cnt--; |
338 | if (pf->fd_tcp4_filter_cnt == 0) { | |
377cc249 JK |
339 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
340 | I40E_DEBUG_FD & pf->hw.debug_mask) | |
341 | dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); | |
342 | pf->hw_disabled_flags &= ~I40E_FLAG_FD_ATR_ENABLED; | |
343 | } | |
344 | } | |
345 | ||
e5187ee3 | 346 | return 0; |
17a73f6b JG |
347 | } |
348 | ||
f223c875 JK |
349 | #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 |
350 | /** | |
351 | * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for | |
352 | * a specific flow spec | |
353 | * @vsi: pointer to the targeted VSI | |
354 | * @fd_data: the flow director data required for the FDir descriptor | |
355 | * @add: true adds a filter, false removes it | |
356 | * | |
357 | * Returns 0 if the filters were successfully added or removed | |
358 | **/ | |
359 | static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, | |
360 | struct i40e_fdir_filter *fd_data, | |
361 | bool add) | |
362 | { | |
363 | struct i40e_pf *pf = vsi->back; | |
364 | struct sctphdr *sctp; | |
365 | struct iphdr *ip; | |
366 | u8 *raw_packet; | |
367 | int ret; | |
368 | /* Dummy packet */ | |
369 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
370 | 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0, | |
371 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
372 | ||
373 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); | |
374 | if (!raw_packet) | |
375 | return -ENOMEM; | |
376 | memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN); | |
377 | ||
378 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
379 | sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET | |
380 | + sizeof(struct iphdr)); | |
381 | ||
382 | ip->daddr = fd_data->dst_ip; | |
383 | sctp->dest = fd_data->dst_port; | |
384 | ip->saddr = fd_data->src_ip; | |
385 | sctp->source = fd_data->src_port; | |
386 | ||
387 | if (fd_data->flex_filter) { | |
388 | u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN; | |
389 | __be16 pattern = fd_data->flex_word; | |
390 | u16 off = fd_data->flex_offset; | |
391 | ||
392 | *((__force __be16 *)(payload + off)) = pattern; | |
393 | } | |
394 | ||
395 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; | |
396 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
397 | if (ret) { | |
398 | dev_info(&pf->pdev->dev, | |
399 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", | |
400 | fd_data->pctype, fd_data->fd_id, ret); | |
401 | /* Free the packet buffer since it wasn't added to the ring */ | |
402 | kfree(raw_packet); | |
403 | return -EOPNOTSUPP; | |
404 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { | |
405 | if (add) | |
406 | dev_info(&pf->pdev->dev, | |
407 | "Filter OK for PCTYPE %d loc = %d\n", | |
408 | fd_data->pctype, fd_data->fd_id); | |
409 | else | |
410 | dev_info(&pf->pdev->dev, | |
411 | "Filter deleted for PCTYPE %d loc = %d\n", | |
412 | fd_data->pctype, fd_data->fd_id); | |
413 | } | |
414 | ||
415 | if (add) | |
416 | pf->fd_sctp4_filter_cnt++; | |
417 | else | |
418 | pf->fd_sctp4_filter_cnt--; | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
17a73f6b JG |
423 | #define I40E_IP_DUMMY_PACKET_LEN 34 |
424 | /** | |
425 | * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for | |
426 | * a specific flow spec | |
427 | * @vsi: pointer to the targeted VSI | |
428 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
429 | * @add: true adds a filter, false removes it |
430 | * | |
431 | * Returns 0 if the filters were successfully added or removed | |
432 | **/ | |
433 | static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, | |
434 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 435 | bool add) |
17a73f6b JG |
436 | { |
437 | struct i40e_pf *pf = vsi->back; | |
438 | struct iphdr *ip; | |
49d7d933 | 439 | u8 *raw_packet; |
17a73f6b JG |
440 | int ret; |
441 | int i; | |
442 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
443 | 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, | |
444 | 0, 0, 0, 0}; | |
445 | ||
17a73f6b JG |
446 | for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; |
447 | i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { | |
49d7d933 ASJ |
448 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
449 | if (!raw_packet) | |
450 | return -ENOMEM; | |
451 | memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); | |
452 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
453 | ||
8ce43dce JK |
454 | ip->saddr = fd_data->src_ip; |
455 | ip->daddr = fd_data->dst_ip; | |
49d7d933 ASJ |
456 | ip->protocol = 0; |
457 | ||
0e588de1 JK |
458 | if (fd_data->flex_filter) { |
459 | u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN; | |
460 | __be16 pattern = fd_data->flex_word; | |
461 | u16 off = fd_data->flex_offset; | |
462 | ||
463 | *((__force __be16 *)(payload + off)) = pattern; | |
464 | } | |
465 | ||
17a73f6b JG |
466 | fd_data->pctype = i; |
467 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
17a73f6b JG |
468 | if (ret) { |
469 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
470 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
471 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
472 | /* The packet buffer wasn't added to the ring so we |
473 | * need to free it now. | |
474 | */ | |
475 | kfree(raw_packet); | |
476 | return -EOPNOTSUPP; | |
4205d379 | 477 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
478 | if (add) |
479 | dev_info(&pf->pdev->dev, | |
480 | "Filter OK for PCTYPE %d loc = %d\n", | |
481 | fd_data->pctype, fd_data->fd_id); | |
482 | else | |
483 | dev_info(&pf->pdev->dev, | |
484 | "Filter deleted for PCTYPE %d loc = %d\n", | |
485 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
486 | } |
487 | } | |
488 | ||
097dbf52 JK |
489 | if (add) |
490 | pf->fd_ip4_filter_cnt++; | |
491 | else | |
492 | pf->fd_ip4_filter_cnt--; | |
493 | ||
e5187ee3 | 494 | return 0; |
17a73f6b JG |
495 | } |
496 | ||
497 | /** | |
498 | * i40e_add_del_fdir - Build raw packets to add/del fdir filter | |
499 | * @vsi: pointer to the targeted VSI | |
500 | * @cmd: command to get or set RX flow classification rules | |
501 | * @add: true adds a filter, false removes it | |
502 | * | |
503 | **/ | |
504 | int i40e_add_del_fdir(struct i40e_vsi *vsi, | |
505 | struct i40e_fdir_filter *input, bool add) | |
506 | { | |
507 | struct i40e_pf *pf = vsi->back; | |
17a73f6b JG |
508 | int ret; |
509 | ||
17a73f6b JG |
510 | switch (input->flow_type & ~FLOW_EXT) { |
511 | case TCP_V4_FLOW: | |
49d7d933 | 512 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
513 | break; |
514 | case UDP_V4_FLOW: | |
49d7d933 | 515 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 516 | break; |
f223c875 JK |
517 | case SCTP_V4_FLOW: |
518 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); | |
519 | break; | |
17a73f6b JG |
520 | case IP_USER_FLOW: |
521 | switch (input->ip4_proto) { | |
522 | case IPPROTO_TCP: | |
49d7d933 | 523 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
524 | break; |
525 | case IPPROTO_UDP: | |
49d7d933 | 526 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 527 | break; |
f223c875 JK |
528 | case IPPROTO_SCTP: |
529 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); | |
530 | break; | |
e1da71ca | 531 | case IPPROTO_IP: |
49d7d933 | 532 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b | 533 | break; |
e1da71ca AD |
534 | default: |
535 | /* We cannot support masking based on protocol */ | |
536 | goto unsupported_flow; | |
17a73f6b JG |
537 | } |
538 | break; | |
539 | default: | |
e1da71ca | 540 | unsupported_flow: |
c5ffe7e1 | 541 | dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", |
17a73f6b JG |
542 | input->flow_type); |
543 | ret = -EINVAL; | |
544 | } | |
545 | ||
a158aeaf JK |
546 | /* The buffer allocated here will be normally be freed by |
547 | * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit | |
548 | * completion. In the event of an error adding the buffer to the FDIR | |
549 | * ring, it will immediately be freed. It may also be freed by | |
550 | * i40e_clean_tx_ring() when closing the VSI. | |
551 | */ | |
17a73f6b JG |
552 | return ret; |
553 | } | |
554 | ||
fd0a05ce JB |
555 | /** |
556 | * i40e_fd_handle_status - check the Programming Status for FD | |
557 | * @rx_ring: the Rx ring for this descriptor | |
55a5e60b | 558 | * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. |
fd0a05ce JB |
559 | * @prog_id: the id originally used for programming |
560 | * | |
561 | * This is used to verify if the FD programming or invalidation | |
562 | * requested by SW to the HW is successful or not and take actions accordingly. | |
563 | **/ | |
55a5e60b ASJ |
564 | static void i40e_fd_handle_status(struct i40e_ring *rx_ring, |
565 | union i40e_rx_desc *rx_desc, u8 prog_id) | |
fd0a05ce | 566 | { |
55a5e60b ASJ |
567 | struct i40e_pf *pf = rx_ring->vsi->back; |
568 | struct pci_dev *pdev = pf->pdev; | |
569 | u32 fcnt_prog, fcnt_avail; | |
fd0a05ce | 570 | u32 error; |
55a5e60b | 571 | u64 qw; |
fd0a05ce | 572 | |
55a5e60b | 573 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
fd0a05ce JB |
574 | error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> |
575 | I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; | |
576 | ||
41a1d04b | 577 | if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { |
3487b6c3 | 578 | pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); |
f7233c54 ASJ |
579 | if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || |
580 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
581 | dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", | |
3487b6c3 | 582 | pf->fd_inv); |
55a5e60b | 583 | |
04294e38 ASJ |
584 | /* Check if the programming error is for ATR. |
585 | * If so, auto disable ATR and set a state for | |
586 | * flush in progress. Next time we come here if flush is in | |
587 | * progress do nothing, once flush is complete the state will | |
588 | * be cleared. | |
589 | */ | |
590 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) | |
591 | return; | |
592 | ||
1e1be8f6 ASJ |
593 | pf->fd_add_err++; |
594 | /* store the current atr filter count */ | |
595 | pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); | |
596 | ||
04294e38 | 597 | if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && |
b77ac975 HR |
598 | (pf->hw_disabled_flags & I40E_FLAG_FD_SB_ENABLED)) { |
599 | pf->hw_disabled_flags |= I40E_FLAG_FD_ATR_ENABLED; | |
04294e38 ASJ |
600 | set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); |
601 | } | |
602 | ||
55a5e60b | 603 | /* filter programming failed most likely due to table full */ |
04294e38 | 604 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 605 | fcnt_avail = pf->fdir_pf_filter_count; |
55a5e60b ASJ |
606 | /* If ATR is running fcnt_prog can quickly change, |
607 | * if we are very close to full, it makes sense to disable | |
608 | * FD ATR/SB and then re-enable it when there is room. | |
609 | */ | |
610 | if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { | |
1e1be8f6 | 611 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
b77ac975 | 612 | !(pf->hw_disabled_flags & |
b814ba65 | 613 | I40E_FLAG_FD_SB_ENABLED)) { |
2e4875e3 ASJ |
614 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
615 | dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); | |
b77ac975 | 616 | pf->hw_disabled_flags |= |
55a5e60b | 617 | I40E_FLAG_FD_SB_ENABLED; |
55a5e60b | 618 | } |
55a5e60b | 619 | } |
41a1d04b | 620 | } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { |
13c2884f | 621 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
e99bdd39 | 622 | dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", |
13c2884f | 623 | rx_desc->wb.qword0.hi_dword.fd_id); |
55a5e60b | 624 | } |
fd0a05ce JB |
625 | } |
626 | ||
627 | /** | |
a5e9c572 | 628 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer |
fd0a05ce JB |
629 | * @ring: the ring that owns the buffer |
630 | * @tx_buffer: the buffer to free | |
631 | **/ | |
a5e9c572 AD |
632 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, |
633 | struct i40e_tx_buffer *tx_buffer) | |
fd0a05ce | 634 | { |
a5e9c572 | 635 | if (tx_buffer->skb) { |
64bfd68e AD |
636 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
637 | kfree(tx_buffer->raw_buf); | |
638 | else | |
639 | dev_kfree_skb_any(tx_buffer->skb); | |
a5e9c572 | 640 | if (dma_unmap_len(tx_buffer, len)) |
fd0a05ce | 641 | dma_unmap_single(ring->dev, |
35a1e2ad AD |
642 | dma_unmap_addr(tx_buffer, dma), |
643 | dma_unmap_len(tx_buffer, len), | |
fd0a05ce | 644 | DMA_TO_DEVICE); |
a5e9c572 AD |
645 | } else if (dma_unmap_len(tx_buffer, len)) { |
646 | dma_unmap_page(ring->dev, | |
647 | dma_unmap_addr(tx_buffer, dma), | |
648 | dma_unmap_len(tx_buffer, len), | |
649 | DMA_TO_DEVICE); | |
fd0a05ce | 650 | } |
a42e7a36 | 651 | |
a5e9c572 AD |
652 | tx_buffer->next_to_watch = NULL; |
653 | tx_buffer->skb = NULL; | |
35a1e2ad | 654 | dma_unmap_len_set(tx_buffer, len, 0); |
a5e9c572 | 655 | /* tx_buffer must be completely set up in the transmit path */ |
fd0a05ce JB |
656 | } |
657 | ||
658 | /** | |
659 | * i40e_clean_tx_ring - Free any empty Tx buffers | |
660 | * @tx_ring: ring to be cleaned | |
661 | **/ | |
662 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring) | |
663 | { | |
fd0a05ce JB |
664 | unsigned long bi_size; |
665 | u16 i; | |
666 | ||
667 | /* ring already cleared, nothing to do */ | |
668 | if (!tx_ring->tx_bi) | |
669 | return; | |
670 | ||
671 | /* Free all the Tx ring sk_buffs */ | |
a5e9c572 AD |
672 | for (i = 0; i < tx_ring->count; i++) |
673 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
fd0a05ce JB |
674 | |
675 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
676 | memset(tx_ring->tx_bi, 0, bi_size); | |
677 | ||
678 | /* Zero out the descriptor ring */ | |
679 | memset(tx_ring->desc, 0, tx_ring->size); | |
680 | ||
681 | tx_ring->next_to_use = 0; | |
682 | tx_ring->next_to_clean = 0; | |
7070ce0a AD |
683 | |
684 | if (!tx_ring->netdev) | |
685 | return; | |
686 | ||
687 | /* cleanup Tx queue statistics */ | |
e486bdfd | 688 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
fd0a05ce JB |
689 | } |
690 | ||
691 | /** | |
692 | * i40e_free_tx_resources - Free Tx resources per queue | |
693 | * @tx_ring: Tx descriptor ring for a specific queue | |
694 | * | |
695 | * Free all transmit software resources | |
696 | **/ | |
697 | void i40e_free_tx_resources(struct i40e_ring *tx_ring) | |
698 | { | |
699 | i40e_clean_tx_ring(tx_ring); | |
700 | kfree(tx_ring->tx_bi); | |
701 | tx_ring->tx_bi = NULL; | |
702 | ||
703 | if (tx_ring->desc) { | |
704 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
705 | tx_ring->desc, tx_ring->dma); | |
706 | tx_ring->desc = NULL; | |
707 | } | |
708 | } | |
709 | ||
710 | /** | |
711 | * i40e_get_tx_pending - how many tx descriptors not processed | |
712 | * @tx_ring: the ring of descriptors | |
dd353109 | 713 | * @in_sw: is tx_pending being checked in SW or HW |
fd0a05ce JB |
714 | * |
715 | * Since there is no access to the ring head register | |
716 | * in XL710, we need to use our local copies | |
717 | **/ | |
dd353109 | 718 | u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
fd0a05ce | 719 | { |
a68de58d JB |
720 | u32 head, tail; |
721 | ||
dd353109 ASJ |
722 | if (!in_sw) |
723 | head = i40e_get_head(ring); | |
724 | else | |
725 | head = ring->next_to_clean; | |
a68de58d JB |
726 | tail = readl(ring->tail); |
727 | ||
728 | if (head != tail) | |
729 | return (head < tail) ? | |
730 | tail - head : (tail + ring->count - head); | |
731 | ||
732 | return 0; | |
fd0a05ce JB |
733 | } |
734 | ||
1dc8b538 | 735 | #define WB_STRIDE 4 |
d91649f5 | 736 | |
fd0a05ce JB |
737 | /** |
738 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
739 | * @vsi: the VSI we care about |
740 | * @tx_ring: Tx ring to clean | |
741 | * @napi_budget: Used to determine if we are in netpoll | |
fd0a05ce JB |
742 | * |
743 | * Returns true if there's any budget left (e.g. the clean is finished) | |
744 | **/ | |
a619afe8 AD |
745 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
746 | struct i40e_ring *tx_ring, int napi_budget) | |
fd0a05ce JB |
747 | { |
748 | u16 i = tx_ring->next_to_clean; | |
749 | struct i40e_tx_buffer *tx_buf; | |
1943d8ba | 750 | struct i40e_tx_desc *tx_head; |
fd0a05ce | 751 | struct i40e_tx_desc *tx_desc; |
a619afe8 AD |
752 | unsigned int total_bytes = 0, total_packets = 0; |
753 | unsigned int budget = vsi->work_limit; | |
fd0a05ce JB |
754 | |
755 | tx_buf = &tx_ring->tx_bi[i]; | |
756 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
a5e9c572 | 757 | i -= tx_ring->count; |
fd0a05ce | 758 | |
1943d8ba JB |
759 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
760 | ||
a5e9c572 AD |
761 | do { |
762 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
fd0a05ce JB |
763 | |
764 | /* if next_to_watch is not set then there is no work pending */ | |
765 | if (!eop_desc) | |
766 | break; | |
767 | ||
a5e9c572 AD |
768 | /* prevent any other reads prior to eop_desc */ |
769 | read_barrier_depends(); | |
770 | ||
1943d8ba JB |
771 | /* we have caught up to head, no work left to do */ |
772 | if (tx_head == tx_desc) | |
fd0a05ce JB |
773 | break; |
774 | ||
c304fdac | 775 | /* clear next_to_watch to prevent false hangs */ |
fd0a05ce | 776 | tx_buf->next_to_watch = NULL; |
fd0a05ce | 777 | |
a5e9c572 AD |
778 | /* update the statistics for this packet */ |
779 | total_bytes += tx_buf->bytecount; | |
780 | total_packets += tx_buf->gso_segs; | |
fd0a05ce | 781 | |
a5e9c572 | 782 | /* free the skb */ |
a619afe8 | 783 | napi_consume_skb(tx_buf->skb, napi_budget); |
fd0a05ce | 784 | |
a5e9c572 AD |
785 | /* unmap skb header data */ |
786 | dma_unmap_single(tx_ring->dev, | |
787 | dma_unmap_addr(tx_buf, dma), | |
788 | dma_unmap_len(tx_buf, len), | |
789 | DMA_TO_DEVICE); | |
fd0a05ce | 790 | |
a5e9c572 AD |
791 | /* clear tx_buffer data */ |
792 | tx_buf->skb = NULL; | |
793 | dma_unmap_len_set(tx_buf, len, 0); | |
fd0a05ce | 794 | |
a5e9c572 AD |
795 | /* unmap remaining buffers */ |
796 | while (tx_desc != eop_desc) { | |
fd0a05ce JB |
797 | |
798 | tx_buf++; | |
799 | tx_desc++; | |
800 | i++; | |
a5e9c572 AD |
801 | if (unlikely(!i)) { |
802 | i -= tx_ring->count; | |
fd0a05ce JB |
803 | tx_buf = tx_ring->tx_bi; |
804 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
805 | } | |
fd0a05ce | 806 | |
a5e9c572 AD |
807 | /* unmap any remaining paged data */ |
808 | if (dma_unmap_len(tx_buf, len)) { | |
809 | dma_unmap_page(tx_ring->dev, | |
810 | dma_unmap_addr(tx_buf, dma), | |
811 | dma_unmap_len(tx_buf, len), | |
812 | DMA_TO_DEVICE); | |
813 | dma_unmap_len_set(tx_buf, len, 0); | |
814 | } | |
815 | } | |
816 | ||
817 | /* move us one more past the eop_desc for start of next pkt */ | |
818 | tx_buf++; | |
819 | tx_desc++; | |
820 | i++; | |
821 | if (unlikely(!i)) { | |
822 | i -= tx_ring->count; | |
823 | tx_buf = tx_ring->tx_bi; | |
824 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
825 | } | |
826 | ||
016890b9 JB |
827 | prefetch(tx_desc); |
828 | ||
a5e9c572 AD |
829 | /* update budget accounting */ |
830 | budget--; | |
831 | } while (likely(budget)); | |
832 | ||
833 | i += tx_ring->count; | |
fd0a05ce | 834 | tx_ring->next_to_clean = i; |
980e9b11 | 835 | u64_stats_update_begin(&tx_ring->syncp); |
a114d0a6 AD |
836 | tx_ring->stats.bytes += total_bytes; |
837 | tx_ring->stats.packets += total_packets; | |
980e9b11 | 838 | u64_stats_update_end(&tx_ring->syncp); |
fd0a05ce JB |
839 | tx_ring->q_vector->tx.total_bytes += total_bytes; |
840 | tx_ring->q_vector->tx.total_packets += total_packets; | |
a5e9c572 | 841 | |
58044743 | 842 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
58044743 AS |
843 | /* check to see if there are < 4 descriptors |
844 | * waiting to be written back, then kick the hardware to force | |
845 | * them to be written back in case we stay in NAPI. | |
846 | * In this mode on X722 we do not enable Interrupt. | |
847 | */ | |
88dc9e6f | 848 | unsigned int j = i40e_get_tx_pending(tx_ring, false); |
58044743 AS |
849 | |
850 | if (budget && | |
1dc8b538 | 851 | ((j / WB_STRIDE) == 0) && (j > 0) && |
a619afe8 | 852 | !test_bit(__I40E_DOWN, &vsi->state) && |
58044743 AS |
853 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) |
854 | tx_ring->arm_wb = true; | |
855 | } | |
d91649f5 | 856 | |
e486bdfd AD |
857 | /* notify netdev of completed buffers */ |
858 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
7070ce0a AD |
859 | total_packets, total_bytes); |
860 | ||
fd0a05ce JB |
861 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
862 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
863 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
864 | /* Make sure that anybody stopping the queue after this | |
865 | * sees the new next_to_clean. | |
866 | */ | |
867 | smp_mb(); | |
868 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
869 | tx_ring->queue_index) && | |
a619afe8 | 870 | !test_bit(__I40E_DOWN, &vsi->state)) { |
fd0a05ce JB |
871 | netif_wake_subqueue(tx_ring->netdev, |
872 | tx_ring->queue_index); | |
873 | ++tx_ring->tx_stats.restart_queue; | |
874 | } | |
875 | } | |
876 | ||
d91649f5 JB |
877 | return !!budget; |
878 | } | |
879 | ||
880 | /** | |
ecc6a239 | 881 | * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
d91649f5 | 882 | * @vsi: the VSI we care about |
ecc6a239 | 883 | * @q_vector: the vector on which to enable writeback |
d91649f5 JB |
884 | * |
885 | **/ | |
ecc6a239 ASJ |
886 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
887 | struct i40e_q_vector *q_vector) | |
d91649f5 | 888 | { |
8e0764b4 | 889 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 890 | u32 val; |
8e0764b4 | 891 | |
ecc6a239 ASJ |
892 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
893 | return; | |
8e0764b4 | 894 | |
ecc6a239 ASJ |
895 | if (q_vector->arm_wb_state) |
896 | return; | |
8e0764b4 | 897 | |
ecc6a239 ASJ |
898 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { |
899 | val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | | |
900 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 901 | |
ecc6a239 ASJ |
902 | wr32(&vsi->back->hw, |
903 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), | |
904 | val); | |
905 | } else { | |
906 | val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | | |
907 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 908 | |
ecc6a239 ASJ |
909 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); |
910 | } | |
911 | q_vector->arm_wb_state = true; | |
912 | } | |
913 | ||
914 | /** | |
915 | * i40e_force_wb - Issue SW Interrupt so HW does a wb | |
916 | * @vsi: the VSI we care about | |
917 | * @q_vector: the vector on which to force writeback | |
918 | * | |
919 | **/ | |
920 | void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
921 | { | |
922 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { | |
8e0764b4 ASJ |
923 | u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | |
924 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ | |
925 | I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | | |
926 | I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; | |
927 | /* allow 00 to be written to the index */ | |
928 | ||
929 | wr32(&vsi->back->hw, | |
930 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + | |
931 | vsi->base_vector - 1), val); | |
932 | } else { | |
933 | u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
934 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ | |
935 | I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | | |
936 | I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; | |
937 | /* allow 00 to be written to the index */ | |
938 | ||
939 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); | |
940 | } | |
fd0a05ce JB |
941 | } |
942 | ||
943 | /** | |
944 | * i40e_set_new_dynamic_itr - Find new ITR level | |
945 | * @rc: structure containing ring performance data | |
946 | * | |
8f5e39ce JB |
947 | * Returns true if ITR changed, false if not |
948 | * | |
fd0a05ce JB |
949 | * Stores a new ITR value based on packets and byte counts during |
950 | * the last interrupt. The advantage of per interrupt computation | |
951 | * is faster updates and more accurate ITR for the current traffic | |
952 | * pattern. Constants in this function were computed based on | |
953 | * theoretical maximum wire speed and thresholds were set based on | |
954 | * testing data as well as attempting to minimize response time | |
955 | * while increasing bulk throughput. | |
956 | **/ | |
8f5e39ce | 957 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
fd0a05ce JB |
958 | { |
959 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
c56625d5 | 960 | struct i40e_q_vector *qv = rc->ring->q_vector; |
fd0a05ce JB |
961 | u32 new_itr = rc->itr; |
962 | int bytes_per_int; | |
51cc6d9f | 963 | int usecs; |
fd0a05ce JB |
964 | |
965 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 966 | return false; |
fd0a05ce JB |
967 | |
968 | /* simple throttlerate management | |
c56625d5 | 969 | * 0-10MB/s lowest (50000 ints/s) |
fd0a05ce | 970 | * 10-20MB/s low (20000 ints/s) |
c56625d5 JB |
971 | * 20-1249MB/s bulk (18000 ints/s) |
972 | * > 40000 Rx packets per second (8000 ints/s) | |
51cc6d9f JB |
973 | * |
974 | * The math works out because the divisor is in 10^(-6) which | |
975 | * turns the bytes/us input value into MB/s values, but | |
976 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
977 | * are in 2 usec increments in the ITR registers, and make sure |
978 | * to use the smoothed values that the countdown timer gives us. | |
fd0a05ce | 979 | */ |
ee2319cf | 980 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
51cc6d9f | 981 | bytes_per_int = rc->total_bytes / usecs; |
ee2319cf | 982 | |
de32e3ef | 983 | switch (new_latency_range) { |
fd0a05ce JB |
984 | case I40E_LOWEST_LATENCY: |
985 | if (bytes_per_int > 10) | |
986 | new_latency_range = I40E_LOW_LATENCY; | |
987 | break; | |
988 | case I40E_LOW_LATENCY: | |
989 | if (bytes_per_int > 20) | |
990 | new_latency_range = I40E_BULK_LATENCY; | |
991 | else if (bytes_per_int <= 10) | |
992 | new_latency_range = I40E_LOWEST_LATENCY; | |
993 | break; | |
994 | case I40E_BULK_LATENCY: | |
c56625d5 | 995 | case I40E_ULTRA_LATENCY: |
de32e3ef CW |
996 | default: |
997 | if (bytes_per_int <= 20) | |
998 | new_latency_range = I40E_LOW_LATENCY; | |
fd0a05ce JB |
999 | break; |
1000 | } | |
c56625d5 JB |
1001 | |
1002 | /* this is to adjust RX more aggressively when streaming small | |
1003 | * packets. The value of 40000 was picked as it is just beyond | |
1004 | * what the hardware can receive per second if in low latency | |
1005 | * mode. | |
1006 | */ | |
1007 | #define RX_ULTRA_PACKET_RATE 40000 | |
1008 | ||
1009 | if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && | |
1010 | (&qv->rx == rc)) | |
1011 | new_latency_range = I40E_ULTRA_LATENCY; | |
1012 | ||
de32e3ef | 1013 | rc->latency_range = new_latency_range; |
fd0a05ce JB |
1014 | |
1015 | switch (new_latency_range) { | |
1016 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 1017 | new_itr = I40E_ITR_50K; |
fd0a05ce JB |
1018 | break; |
1019 | case I40E_LOW_LATENCY: | |
1020 | new_itr = I40E_ITR_20K; | |
1021 | break; | |
1022 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
1023 | new_itr = I40E_ITR_18K; |
1024 | break; | |
1025 | case I40E_ULTRA_LATENCY: | |
fd0a05ce JB |
1026 | new_itr = I40E_ITR_8K; |
1027 | break; | |
1028 | default: | |
1029 | break; | |
1030 | } | |
1031 | ||
fd0a05ce JB |
1032 | rc->total_bytes = 0; |
1033 | rc->total_packets = 0; | |
8f5e39ce JB |
1034 | |
1035 | if (new_itr != rc->itr) { | |
1036 | rc->itr = new_itr; | |
1037 | return true; | |
1038 | } | |
1039 | ||
1040 | return false; | |
fd0a05ce JB |
1041 | } |
1042 | ||
fd0a05ce JB |
1043 | /** |
1044 | * i40e_clean_programming_status - clean the programming status descriptor | |
1045 | * @rx_ring: the rx ring that has this descriptor | |
1046 | * @rx_desc: the rx descriptor written back by HW | |
1047 | * | |
1048 | * Flow director should handle FD_FILTER_STATUS to check its filter programming | |
1049 | * status being successful or not and take actions accordingly. FCoE should | |
1050 | * handle its context/filter programming/invalidation status and take actions. | |
1051 | * | |
1052 | **/ | |
1053 | static void i40e_clean_programming_status(struct i40e_ring *rx_ring, | |
1054 | union i40e_rx_desc *rx_desc) | |
1055 | { | |
1056 | u64 qw; | |
1057 | u8 id; | |
1058 | ||
1059 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1060 | id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> | |
1061 | I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; | |
1062 | ||
1063 | if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) | |
55a5e60b | 1064 | i40e_fd_handle_status(rx_ring, rx_desc, id); |
38e00438 VD |
1065 | #ifdef I40E_FCOE |
1066 | else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || | |
1067 | (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) | |
1068 | i40e_fcoe_handle_status(rx_ring, rx_desc, id); | |
1069 | #endif | |
fd0a05ce JB |
1070 | } |
1071 | ||
1072 | /** | |
1073 | * i40e_setup_tx_descriptors - Allocate the Tx descriptors | |
1074 | * @tx_ring: the tx ring to set up | |
1075 | * | |
1076 | * Return 0 on success, negative on error | |
1077 | **/ | |
1078 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
1079 | { | |
1080 | struct device *dev = tx_ring->dev; | |
1081 | int bi_size; | |
1082 | ||
1083 | if (!dev) | |
1084 | return -ENOMEM; | |
1085 | ||
e908f815 JB |
1086 | /* warn if we are about to overwrite the pointer */ |
1087 | WARN_ON(tx_ring->tx_bi); | |
fd0a05ce JB |
1088 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
1089 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1090 | if (!tx_ring->tx_bi) | |
1091 | goto err; | |
1092 | ||
1093 | /* round up to nearest 4K */ | |
1094 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
1095 | /* add u32 for head writeback, align after this takes care of |
1096 | * guaranteeing this is at least one cache line in size | |
1097 | */ | |
1098 | tx_ring->size += sizeof(u32); | |
fd0a05ce JB |
1099 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1100 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
1101 | &tx_ring->dma, GFP_KERNEL); | |
1102 | if (!tx_ring->desc) { | |
1103 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
1104 | tx_ring->size); | |
1105 | goto err; | |
1106 | } | |
1107 | ||
1108 | tx_ring->next_to_use = 0; | |
1109 | tx_ring->next_to_clean = 0; | |
1110 | return 0; | |
1111 | ||
1112 | err: | |
1113 | kfree(tx_ring->tx_bi); | |
1114 | tx_ring->tx_bi = NULL; | |
1115 | return -ENOMEM; | |
1116 | } | |
1117 | ||
1118 | /** | |
1119 | * i40e_clean_rx_ring - Free Rx buffers | |
1120 | * @rx_ring: ring to be cleaned | |
1121 | **/ | |
1122 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring) | |
1123 | { | |
fd0a05ce JB |
1124 | unsigned long bi_size; |
1125 | u16 i; | |
1126 | ||
1127 | /* ring already cleared, nothing to do */ | |
1128 | if (!rx_ring->rx_bi) | |
1129 | return; | |
1130 | ||
e72e5659 SP |
1131 | if (rx_ring->skb) { |
1132 | dev_kfree_skb(rx_ring->skb); | |
1133 | rx_ring->skb = NULL; | |
1134 | } | |
1135 | ||
fd0a05ce JB |
1136 | /* Free all the Rx ring sk_buffs */ |
1137 | for (i = 0; i < rx_ring->count; i++) { | |
1a557afc JB |
1138 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
1139 | ||
1a557afc JB |
1140 | if (!rx_bi->page) |
1141 | continue; | |
1142 | ||
59605bc0 AD |
1143 | /* Invalidate cache lines that may have been written to by |
1144 | * device so that we avoid corrupting memory. | |
1145 | */ | |
1146 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1147 | rx_bi->dma, | |
1148 | rx_bi->page_offset, | |
1149 | I40E_RXBUFFER_2048, | |
1150 | DMA_FROM_DEVICE); | |
1151 | ||
1152 | /* free resources associated with mapping */ | |
1153 | dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, | |
1154 | PAGE_SIZE, | |
1155 | DMA_FROM_DEVICE, | |
1156 | I40E_RX_DMA_ATTR); | |
1a557afc JB |
1157 | __free_pages(rx_bi->page, 0); |
1158 | ||
1159 | rx_bi->page = NULL; | |
1160 | rx_bi->page_offset = 0; | |
fd0a05ce JB |
1161 | } |
1162 | ||
1163 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
1164 | memset(rx_ring->rx_bi, 0, bi_size); | |
1165 | ||
1166 | /* Zero out the descriptor ring */ | |
1167 | memset(rx_ring->desc, 0, rx_ring->size); | |
1168 | ||
1a557afc | 1169 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1170 | rx_ring->next_to_clean = 0; |
1171 | rx_ring->next_to_use = 0; | |
1172 | } | |
1173 | ||
1174 | /** | |
1175 | * i40e_free_rx_resources - Free Rx resources | |
1176 | * @rx_ring: ring to clean the resources from | |
1177 | * | |
1178 | * Free all receive software resources | |
1179 | **/ | |
1180 | void i40e_free_rx_resources(struct i40e_ring *rx_ring) | |
1181 | { | |
1182 | i40e_clean_rx_ring(rx_ring); | |
1183 | kfree(rx_ring->rx_bi); | |
1184 | rx_ring->rx_bi = NULL; | |
1185 | ||
1186 | if (rx_ring->desc) { | |
1187 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
1188 | rx_ring->desc, rx_ring->dma); | |
1189 | rx_ring->desc = NULL; | |
1190 | } | |
1191 | } | |
1192 | ||
1193 | /** | |
1194 | * i40e_setup_rx_descriptors - Allocate Rx descriptors | |
1195 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
1196 | * | |
1197 | * Returns 0 on success, negative on failure | |
1198 | **/ | |
1199 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
1200 | { | |
1201 | struct device *dev = rx_ring->dev; | |
1202 | int bi_size; | |
1203 | ||
e908f815 JB |
1204 | /* warn if we are about to overwrite the pointer */ |
1205 | WARN_ON(rx_ring->rx_bi); | |
fd0a05ce JB |
1206 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
1207 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1208 | if (!rx_ring->rx_bi) | |
1209 | goto err; | |
1210 | ||
f217d6ca | 1211 | u64_stats_init(&rx_ring->syncp); |
638702bd | 1212 | |
fd0a05ce | 1213 | /* Round up to nearest 4K */ |
1a557afc | 1214 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
fd0a05ce JB |
1215 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
1216 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
1217 | &rx_ring->dma, GFP_KERNEL); | |
1218 | ||
1219 | if (!rx_ring->desc) { | |
1220 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
1221 | rx_ring->size); | |
1222 | goto err; | |
1223 | } | |
1224 | ||
1a557afc | 1225 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1226 | rx_ring->next_to_clean = 0; |
1227 | rx_ring->next_to_use = 0; | |
1228 | ||
1229 | return 0; | |
1230 | err: | |
1231 | kfree(rx_ring->rx_bi); | |
1232 | rx_ring->rx_bi = NULL; | |
1233 | return -ENOMEM; | |
1234 | } | |
1235 | ||
1236 | /** | |
1237 | * i40e_release_rx_desc - Store the new tail and head values | |
1238 | * @rx_ring: ring to bump | |
1239 | * @val: new head index | |
1240 | **/ | |
1241 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
1242 | { | |
1243 | rx_ring->next_to_use = val; | |
1a557afc JB |
1244 | |
1245 | /* update next to alloc since we have filled the ring */ | |
1246 | rx_ring->next_to_alloc = val; | |
1247 | ||
fd0a05ce JB |
1248 | /* Force memory writes to complete before letting h/w |
1249 | * know there are new descriptors to fetch. (Only | |
1250 | * applicable for weak-ordered memory model archs, | |
1251 | * such as IA-64). | |
1252 | */ | |
1253 | wmb(); | |
1254 | writel(val, rx_ring->tail); | |
1255 | } | |
1256 | ||
1257 | /** | |
1a557afc JB |
1258 | * i40e_alloc_mapped_page - recycle or make a new page |
1259 | * @rx_ring: ring to use | |
1260 | * @bi: rx_buffer struct to modify | |
c2e245ab | 1261 | * |
1a557afc JB |
1262 | * Returns true if the page was successfully allocated or |
1263 | * reused. | |
fd0a05ce | 1264 | **/ |
1a557afc JB |
1265 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
1266 | struct i40e_rx_buffer *bi) | |
a132af24 | 1267 | { |
1a557afc JB |
1268 | struct page *page = bi->page; |
1269 | dma_addr_t dma; | |
a132af24 | 1270 | |
1a557afc JB |
1271 | /* since we are recycling buffers we should seldom need to alloc */ |
1272 | if (likely(page)) { | |
1273 | rx_ring->rx_stats.page_reuse_count++; | |
1274 | return true; | |
1275 | } | |
a132af24 | 1276 | |
1a557afc JB |
1277 | /* alloc new page for storage */ |
1278 | page = dev_alloc_page(); | |
1279 | if (unlikely(!page)) { | |
1280 | rx_ring->rx_stats.alloc_page_failed++; | |
1281 | return false; | |
1282 | } | |
a132af24 | 1283 | |
1a557afc | 1284 | /* map page for use */ |
59605bc0 AD |
1285 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
1286 | PAGE_SIZE, | |
1287 | DMA_FROM_DEVICE, | |
1288 | I40E_RX_DMA_ATTR); | |
f16704e5 | 1289 | |
1a557afc JB |
1290 | /* if mapping failed free memory back to system since |
1291 | * there isn't much point in holding memory we can't use | |
f16704e5 | 1292 | */ |
1a557afc JB |
1293 | if (dma_mapping_error(rx_ring->dev, dma)) { |
1294 | __free_pages(page, 0); | |
1295 | rx_ring->rx_stats.alloc_page_failed++; | |
1296 | return false; | |
a132af24 MW |
1297 | } |
1298 | ||
1a557afc JB |
1299 | bi->dma = dma; |
1300 | bi->page = page; | |
1301 | bi->page_offset = 0; | |
c2e245ab | 1302 | |
1a557afc JB |
1303 | return true; |
1304 | } | |
c2e245ab | 1305 | |
1a557afc JB |
1306 | /** |
1307 | * i40e_receive_skb - Send a completed packet up the stack | |
1308 | * @rx_ring: rx ring in play | |
1309 | * @skb: packet to send up | |
1310 | * @vlan_tag: vlan tag for packet | |
1311 | **/ | |
1312 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
1313 | struct sk_buff *skb, u16 vlan_tag) | |
1314 | { | |
1315 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
c2e245ab | 1316 | |
1a557afc JB |
1317 | if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
1318 | (vlan_tag & VLAN_VID_MASK)) | |
1319 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
1320 | ||
1321 | napi_gro_receive(&q_vector->napi, skb); | |
a132af24 MW |
1322 | } |
1323 | ||
1324 | /** | |
1a557afc | 1325 | * i40e_alloc_rx_buffers - Replace used receive buffers |
a132af24 MW |
1326 | * @rx_ring: ring to place buffers on |
1327 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 1328 | * |
1a557afc | 1329 | * Returns false if all allocations were successful, true if any fail |
a132af24 | 1330 | **/ |
1a557afc | 1331 | bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
fd0a05ce | 1332 | { |
1a557afc | 1333 | u16 ntu = rx_ring->next_to_use; |
fd0a05ce JB |
1334 | union i40e_rx_desc *rx_desc; |
1335 | struct i40e_rx_buffer *bi; | |
fd0a05ce JB |
1336 | |
1337 | /* do nothing if no valid netdev defined */ | |
1338 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 1339 | return false; |
fd0a05ce | 1340 | |
1a557afc JB |
1341 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
1342 | bi = &rx_ring->rx_bi[ntu]; | |
fd0a05ce | 1343 | |
1a557afc JB |
1344 | do { |
1345 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
1346 | goto no_buffers; | |
fd0a05ce | 1347 | |
59605bc0 AD |
1348 | /* sync the buffer for use by the device */ |
1349 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
1350 | bi->page_offset, | |
1351 | I40E_RXBUFFER_2048, | |
1352 | DMA_FROM_DEVICE); | |
1353 | ||
1a557afc JB |
1354 | /* Refresh the desc even if buffer_addrs didn't change |
1355 | * because each write-back erases this info. | |
1356 | */ | |
1357 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
fd0a05ce | 1358 | |
1a557afc JB |
1359 | rx_desc++; |
1360 | bi++; | |
1361 | ntu++; | |
1362 | if (unlikely(ntu == rx_ring->count)) { | |
1363 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
1364 | bi = rx_ring->rx_bi; | |
1365 | ntu = 0; | |
1366 | } | |
1367 | ||
1368 | /* clear the status bits for the next_to_use descriptor */ | |
1369 | rx_desc->wb.qword1.status_error_len = 0; | |
1370 | ||
1371 | cleaned_count--; | |
1372 | } while (cleaned_count); | |
1373 | ||
1374 | if (rx_ring->next_to_use != ntu) | |
1375 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1376 | |
1377 | return false; | |
1378 | ||
fd0a05ce | 1379 | no_buffers: |
1a557afc JB |
1380 | if (rx_ring->next_to_use != ntu) |
1381 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1382 | |
1383 | /* make sure to come back via polling to try again after | |
1384 | * allocation failure | |
1385 | */ | |
1386 | return true; | |
fd0a05ce JB |
1387 | } |
1388 | ||
fd0a05ce JB |
1389 | /** |
1390 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
1391 | * @vsi: the VSI we care about | |
1392 | * @skb: skb currently being received and modified | |
1a557afc JB |
1393 | * @rx_desc: the receive descriptor |
1394 | * | |
1395 | * skb->protocol must be set before this function is called | |
fd0a05ce JB |
1396 | **/ |
1397 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
1398 | struct sk_buff *skb, | |
1a557afc | 1399 | union i40e_rx_desc *rx_desc) |
fd0a05ce | 1400 | { |
1a557afc | 1401 | struct i40e_rx_ptype_decoded decoded; |
1a557afc | 1402 | u32 rx_error, rx_status; |
858296c8 | 1403 | bool ipv4, ipv6; |
1a557afc JB |
1404 | u8 ptype; |
1405 | u64 qword; | |
1406 | ||
1407 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1408 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
1409 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
1410 | I40E_RXD_QW1_ERROR_SHIFT; | |
1411 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1412 | I40E_RXD_QW1_STATUS_SHIFT; | |
1413 | decoded = decode_rx_desc_ptype(ptype); | |
8144f0f7 | 1414 | |
fd0a05ce JB |
1415 | skb->ip_summed = CHECKSUM_NONE; |
1416 | ||
1a557afc JB |
1417 | skb_checksum_none_assert(skb); |
1418 | ||
fd0a05ce | 1419 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
1420 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
1421 | return; | |
1422 | ||
1423 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 1424 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
1425 | return; |
1426 | ||
1427 | /* both known and outer_ip must be set for the below code to work */ | |
1428 | if (!(decoded.known && decoded.outer_ip)) | |
fd0a05ce JB |
1429 | return; |
1430 | ||
fad57330 AD |
1431 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
1432 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
1433 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
1434 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
1435 | |
1436 | if (ipv4 && | |
41a1d04b JB |
1437 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
1438 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
1439 | goto checksum_fail; |
1440 | ||
ddf1d0d7 | 1441 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 1442 | if (ipv6 && |
41a1d04b | 1443 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 1444 | /* don't increment checksum err here, non-fatal err */ |
8ee75a8e SN |
1445 | return; |
1446 | ||
8a3c91cc | 1447 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 1448 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
1449 | goto checksum_fail; |
1450 | ||
1451 | /* handle packets that were not able to be checksummed due | |
1452 | * to arrival speed, in this case the stack can compute | |
1453 | * the csum. | |
1454 | */ | |
41a1d04b | 1455 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
fd0a05ce | 1456 | return; |
fd0a05ce | 1457 | |
858296c8 AD |
1458 | /* If there is an outer header present that might contain a checksum |
1459 | * we need to bump the checksum level by 1 to reflect the fact that | |
1460 | * we are indicating we validated the inner checksum. | |
8a3c91cc | 1461 | */ |
858296c8 AD |
1462 | if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) |
1463 | skb->csum_level = 1; | |
1464 | ||
1465 | /* Only report checksum unnecessary for TCP, UDP, or SCTP */ | |
1466 | switch (decoded.inner_prot) { | |
1467 | case I40E_RX_PTYPE_INNER_PROT_TCP: | |
1468 | case I40E_RX_PTYPE_INNER_PROT_UDP: | |
1469 | case I40E_RX_PTYPE_INNER_PROT_SCTP: | |
1470 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1471 | /* fall though */ | |
1472 | default: | |
1473 | break; | |
1474 | } | |
8a3c91cc JB |
1475 | |
1476 | return; | |
1477 | ||
1478 | checksum_fail: | |
1479 | vsi->back->hw_csum_rx_error++; | |
fd0a05ce JB |
1480 | } |
1481 | ||
1482 | /** | |
857942fd | 1483 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
1484 | * @ptype: the ptype value from the descriptor |
1485 | * | |
1486 | * Returns a hash type to be used by skb_set_hash | |
1487 | **/ | |
1a557afc | 1488 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
1489 | { |
1490 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
1491 | ||
1492 | if (!decoded.known) | |
1493 | return PKT_HASH_TYPE_NONE; | |
1494 | ||
1495 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1496 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
1497 | return PKT_HASH_TYPE_L4; | |
1498 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1499 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
1500 | return PKT_HASH_TYPE_L3; | |
1501 | else | |
1502 | return PKT_HASH_TYPE_L2; | |
1503 | } | |
1504 | ||
857942fd ASJ |
1505 | /** |
1506 | * i40e_rx_hash - set the hash value in the skb | |
1507 | * @ring: descriptor ring | |
1508 | * @rx_desc: specific descriptor | |
1509 | **/ | |
1510 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
1511 | union i40e_rx_desc *rx_desc, | |
1512 | struct sk_buff *skb, | |
1513 | u8 rx_ptype) | |
1514 | { | |
1515 | u32 hash; | |
1a557afc | 1516 | const __le64 rss_mask = |
857942fd ASJ |
1517 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
1518 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
1519 | ||
a876c3ba | 1520 | if (!(ring->netdev->features & NETIF_F_RXHASH)) |
857942fd ASJ |
1521 | return; |
1522 | ||
1523 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
1524 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
1525 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
1526 | } | |
1527 | } | |
1528 | ||
a132af24 | 1529 | /** |
1a557afc JB |
1530 | * i40e_process_skb_fields - Populate skb header fields from Rx descriptor |
1531 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1532 | * @rx_desc: pointer to the EOP Rx descriptor | |
1533 | * @skb: pointer to current skb being populated | |
1534 | * @rx_ptype: the packet type decoded by hardware | |
1535 | * | |
1536 | * This function checks the ring, descriptor, and packet information in | |
1537 | * order to populate the hash, checksum, VLAN, protocol, and | |
1538 | * other fields within the skb. | |
1539 | **/ | |
1540 | static inline | |
1541 | void i40e_process_skb_fields(struct i40e_ring *rx_ring, | |
1542 | union i40e_rx_desc *rx_desc, struct sk_buff *skb, | |
1543 | u8 rx_ptype) | |
1544 | { | |
1545 | u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1546 | u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1547 | I40E_RXD_QW1_STATUS_SHIFT; | |
144ed176 JK |
1548 | u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; |
1549 | u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> | |
1a557afc JB |
1550 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; |
1551 | ||
12490501 | 1552 | if (unlikely(tsynvalid)) |
144ed176 | 1553 | i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); |
1a557afc JB |
1554 | |
1555 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); | |
1556 | ||
1557 | /* modifies the skb - consumes the enet header */ | |
1558 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
1559 | ||
1560 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); | |
1561 | ||
1562 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
1563 | } | |
1564 | ||
1a557afc JB |
1565 | /** |
1566 | * i40e_cleanup_headers - Correct empty headers | |
1567 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1568 | * @skb: pointer to current skb being fixed | |
1569 | * | |
1570 | * Also address the case where we are pulling data in on pages only | |
1571 | * and as such no data is present in the skb header. | |
1572 | * | |
1573 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1574 | * it is large enough to qualify as a valid Ethernet frame. | |
1575 | * | |
1576 | * Returns true if an error was encountered and skb was freed. | |
1577 | **/ | |
1578 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
1579 | { | |
1a557afc JB |
1580 | /* if eth_skb_pad returns an error the skb was freed */ |
1581 | if (eth_skb_pad(skb)) | |
1582 | return true; | |
1583 | ||
1584 | return false; | |
1585 | } | |
1586 | ||
1587 | /** | |
1588 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
1589 | * @rx_ring: rx descriptor ring to store buffers on | |
1590 | * @old_buff: donor buffer to have page reused | |
1591 | * | |
1592 | * Synchronizes page for reuse by the adapter | |
1593 | **/ | |
1594 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
1595 | struct i40e_rx_buffer *old_buff) | |
1596 | { | |
1597 | struct i40e_rx_buffer *new_buff; | |
1598 | u16 nta = rx_ring->next_to_alloc; | |
1599 | ||
1600 | new_buff = &rx_ring->rx_bi[nta]; | |
1601 | ||
1602 | /* update, and store next to alloc */ | |
1603 | nta++; | |
1604 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1605 | ||
1606 | /* transfer page from old buffer to new buffer */ | |
1607 | *new_buff = *old_buff; | |
1608 | } | |
1609 | ||
1610 | /** | |
9b37c937 | 1611 | * i40e_page_is_reusable - check if any reuse is possible |
1a557afc | 1612 | * @page: page struct to check |
9b37c937 SP |
1613 | * |
1614 | * A page is not reusable if it was allocated under low memory | |
1615 | * conditions, or it's not in the same NUMA node as this CPU. | |
1a557afc | 1616 | */ |
9b37c937 | 1617 | static inline bool i40e_page_is_reusable(struct page *page) |
1a557afc | 1618 | { |
9b37c937 SP |
1619 | return (page_to_nid(page) == numa_mem_id()) && |
1620 | !page_is_pfmemalloc(page); | |
1621 | } | |
1622 | ||
1623 | /** | |
1624 | * i40e_can_reuse_rx_page - Determine if this page can be reused by | |
1625 | * the adapter for another receive | |
1626 | * | |
1627 | * @rx_buffer: buffer containing the page | |
1628 | * @page: page address from rx_buffer | |
1629 | * @truesize: actual size of the buffer in this page | |
1630 | * | |
1631 | * If page is reusable, rx_buffer->page_offset is adjusted to point to | |
1632 | * an unused region in the page. | |
1633 | * | |
1634 | * For small pages, @truesize will be a constant value, half the size | |
1635 | * of the memory at page. We'll attempt to alternate between high and | |
1636 | * low halves of the page, with one half ready for use by the hardware | |
1637 | * and the other half being consumed by the stack. We use the page | |
1638 | * ref count to determine whether the stack has finished consuming the | |
1639 | * portion of this page that was passed up with a previous packet. If | |
1640 | * the page ref count is >1, we'll assume the "other" half page is | |
1641 | * still busy, and this page cannot be reused. | |
1642 | * | |
1643 | * For larger pages, @truesize will be the actual space used by the | |
1644 | * received packet (adjusted upward to an even multiple of the cache | |
1645 | * line size). This will advance through the page by the amount | |
1646 | * actually consumed by the received packets while there is still | |
1647 | * space for a buffer. Each region of larger pages will be used at | |
1648 | * most once, after which the page will not be reused. | |
1649 | * | |
1650 | * In either case, if the page is reusable its refcount is increased. | |
1651 | **/ | |
1652 | static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer, | |
1653 | struct page *page, | |
1654 | const unsigned int truesize) | |
1655 | { | |
1656 | #if (PAGE_SIZE >= 8192) | |
1657 | unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048; | |
1658 | #endif | |
1659 | ||
1660 | /* Is any reuse possible? */ | |
1661 | if (unlikely(!i40e_page_is_reusable(page))) | |
1662 | return false; | |
1663 | ||
1664 | #if (PAGE_SIZE < 8192) | |
1665 | /* if we are only owner of page we can reuse it */ | |
1666 | if (unlikely(page_count(page) != 1)) | |
1667 | return false; | |
1668 | ||
1669 | /* flip page offset to other buffer */ | |
1670 | rx_buffer->page_offset ^= truesize; | |
1671 | #else | |
1672 | /* move offset up to the next cache line */ | |
1673 | rx_buffer->page_offset += truesize; | |
1674 | ||
1675 | if (rx_buffer->page_offset > last_offset) | |
1676 | return false; | |
1677 | #endif | |
1678 | ||
1679 | /* Inc ref count on page before passing it up to the stack */ | |
1680 | get_page(page); | |
1681 | ||
1682 | return true; | |
1a557afc JB |
1683 | } |
1684 | ||
1685 | /** | |
1686 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1687 | * @rx_ring: rx descriptor ring to transact packets on | |
1688 | * @rx_buffer: buffer containing page to add | |
7987dcd7 | 1689 | * @size: packet length from rx_desc |
1a557afc JB |
1690 | * @skb: sk_buff to place the data into |
1691 | * | |
1692 | * This function will add the data contained in rx_buffer->page to the skb. | |
1693 | * This is done either through a direct copy if the data in the buffer is | |
1694 | * less than the skb header size, otherwise it will just attach the page as | |
1695 | * a frag to the skb. | |
1696 | * | |
1697 | * The function will then update the page offset if necessary and return | |
1698 | * true if the buffer can be reused by the adapter. | |
1699 | **/ | |
1700 | static bool i40e_add_rx_frag(struct i40e_ring *rx_ring, | |
1701 | struct i40e_rx_buffer *rx_buffer, | |
7987dcd7 | 1702 | unsigned int size, |
1a557afc JB |
1703 | struct sk_buff *skb) |
1704 | { | |
1705 | struct page *page = rx_buffer->page; | |
9b37c937 | 1706 | unsigned char *va = page_address(page) + rx_buffer->page_offset; |
1a557afc JB |
1707 | #if (PAGE_SIZE < 8192) |
1708 | unsigned int truesize = I40E_RXBUFFER_2048; | |
1709 | #else | |
1710 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
1a557afc | 1711 | #endif |
9b37c937 SP |
1712 | unsigned int pull_len; |
1713 | ||
1714 | if (unlikely(skb_is_nonlinear(skb))) | |
1715 | goto add_tail_frag; | |
1a557afc JB |
1716 | |
1717 | /* will the data fit in the skb we allocated? if so, just | |
1718 | * copy it as it is pretty small anyway | |
1719 | */ | |
9b37c937 | 1720 | if (size <= I40E_RX_HDR_SIZE) { |
1a557afc JB |
1721 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
1722 | ||
9b37c937 SP |
1723 | /* page is reusable, we can reuse buffer as-is */ |
1724 | if (likely(i40e_page_is_reusable(page))) | |
1a557afc JB |
1725 | return true; |
1726 | ||
1727 | /* this page cannot be reused so discard it */ | |
1728 | __free_pages(page, 0); | |
1729 | return false; | |
1730 | } | |
1731 | ||
9b37c937 SP |
1732 | /* we need the header to contain the greater of either |
1733 | * ETH_HLEN or 60 bytes if the skb->len is less than | |
1734 | * 60 for skb_pad. | |
1735 | */ | |
1736 | pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE); | |
1a557afc | 1737 | |
9b37c937 SP |
1738 | /* align pull length to size of long to optimize |
1739 | * memcpy performance | |
1740 | */ | |
1741 | memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); | |
1a557afc | 1742 | |
9b37c937 SP |
1743 | /* update all of the pointers */ |
1744 | va += pull_len; | |
1745 | size -= pull_len; | |
1a557afc | 1746 | |
9b37c937 SP |
1747 | add_tail_frag: |
1748 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, | |
1749 | (unsigned long)va & ~PAGE_MASK, size, truesize); | |
1a557afc | 1750 | |
9b37c937 | 1751 | return i40e_can_reuse_rx_page(rx_buffer, page, truesize); |
1a557afc JB |
1752 | } |
1753 | ||
1754 | /** | |
1755 | * i40e_fetch_rx_buffer - Allocate skb and populate it | |
1756 | * @rx_ring: rx descriptor ring to transact packets on | |
1757 | * @rx_desc: descriptor containing info written by hardware | |
a132af24 | 1758 | * |
1a557afc JB |
1759 | * This function allocates an skb on the fly, and populates it with the page |
1760 | * data from the current receive descriptor, taking care to set up the skb | |
1761 | * correctly, as well as handling calling the page recycle function if | |
1762 | * necessary. | |
1763 | */ | |
1764 | static inline | |
1765 | struct sk_buff *i40e_fetch_rx_buffer(struct i40e_ring *rx_ring, | |
e72e5659 SP |
1766 | union i40e_rx_desc *rx_desc, |
1767 | struct sk_buff *skb) | |
1a557afc | 1768 | { |
7987dcd7 SP |
1769 | u64 local_status_error_len = |
1770 | le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1771 | unsigned int size = | |
1772 | (local_status_error_len & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> | |
1773 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1a557afc | 1774 | struct i40e_rx_buffer *rx_buffer; |
1a557afc JB |
1775 | struct page *page; |
1776 | ||
1777 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1778 | page = rx_buffer->page; | |
1779 | prefetchw(page); | |
1780 | ||
1a557afc JB |
1781 | if (likely(!skb)) { |
1782 | void *page_addr = page_address(page) + rx_buffer->page_offset; | |
1783 | ||
1784 | /* prefetch first cache line of first page */ | |
1785 | prefetch(page_addr); | |
1786 | #if L1_CACHE_BYTES < 128 | |
1787 | prefetch(page_addr + L1_CACHE_BYTES); | |
1788 | #endif | |
1789 | ||
1790 | /* allocate a skb to store the frags */ | |
1791 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
1792 | I40E_RX_HDR_SIZE, | |
1793 | GFP_ATOMIC | __GFP_NOWARN); | |
1794 | if (unlikely(!skb)) { | |
1795 | rx_ring->rx_stats.alloc_buff_failed++; | |
1796 | return NULL; | |
1797 | } | |
1798 | ||
1799 | /* we will be copying header into skb->data in | |
1800 | * pskb_may_pull so it is in our interest to prefetch | |
1801 | * it now to avoid a possible cache miss | |
1802 | */ | |
1803 | prefetchw(skb->data); | |
1a557afc JB |
1804 | } |
1805 | ||
1806 | /* we are reusing so sync this buffer for CPU use */ | |
1807 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1808 | rx_buffer->dma, | |
1809 | rx_buffer->page_offset, | |
7987dcd7 | 1810 | size, |
1a557afc JB |
1811 | DMA_FROM_DEVICE); |
1812 | ||
1813 | /* pull page into skb */ | |
7987dcd7 | 1814 | if (i40e_add_rx_frag(rx_ring, rx_buffer, size, skb)) { |
1a557afc JB |
1815 | /* hand second half of page back to the ring */ |
1816 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1817 | rx_ring->rx_stats.page_reuse_count++; | |
1818 | } else { | |
1819 | /* we are not reusing the buffer so unmap it */ | |
59605bc0 AD |
1820 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, PAGE_SIZE, |
1821 | DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); | |
1a557afc JB |
1822 | } |
1823 | ||
1824 | /* clear contents of buffer_info */ | |
1825 | rx_buffer->page = NULL; | |
1826 | ||
1827 | return skb; | |
1828 | } | |
1829 | ||
1830 | /** | |
1831 | * i40e_is_non_eop - process handling of non-EOP buffers | |
1832 | * @rx_ring: Rx ring being processed | |
1833 | * @rx_desc: Rx descriptor for current buffer | |
1834 | * @skb: Current socket buffer containing buffer in progress | |
1835 | * | |
1836 | * This function updates next to clean. If the buffer is an EOP buffer | |
1837 | * this function exits returning false, otherwise it will place the | |
1838 | * sk_buff in the next buffer to be chained and return true indicating | |
1839 | * that this is in fact a non-EOP buffer. | |
a132af24 | 1840 | **/ |
1a557afc JB |
1841 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, |
1842 | union i40e_rx_desc *rx_desc, | |
1843 | struct sk_buff *skb) | |
1844 | { | |
1845 | u32 ntc = rx_ring->next_to_clean + 1; | |
1846 | ||
1847 | /* fetch, update, and store next to clean */ | |
1848 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1849 | rx_ring->next_to_clean = ntc; | |
1850 | ||
1851 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1852 | ||
1853 | #define staterrlen rx_desc->wb.qword1.status_error_len | |
1854 | if (unlikely(i40e_rx_is_programming_status(le64_to_cpu(staterrlen)))) { | |
1855 | i40e_clean_programming_status(rx_ring, rx_desc); | |
1a557afc JB |
1856 | return true; |
1857 | } | |
1858 | /* if we are the last buffer then there is nothing else to do */ | |
1859 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
1860 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
1861 | return false; | |
1862 | ||
1a557afc JB |
1863 | rx_ring->rx_stats.non_eop_descs++; |
1864 | ||
1865 | return true; | |
1866 | } | |
1867 | ||
1868 | /** | |
1869 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1870 | * @rx_ring: rx descriptor ring to transact packets on | |
1871 | * @budget: Total limit on number of packets to process | |
1872 | * | |
1873 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1874 | * processing. The advantage to this is that on systems that have | |
1875 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1876 | * it by maintaining the mapping of the page to the system. | |
1877 | * | |
1878 | * Returns amount of work completed | |
1879 | **/ | |
1880 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) | |
a132af24 MW |
1881 | { |
1882 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
e72e5659 | 1883 | struct sk_buff *skb = rx_ring->skb; |
a132af24 | 1884 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); |
c2e245ab | 1885 | bool failure = false; |
a132af24 | 1886 | |
1a557afc JB |
1887 | while (likely(total_rx_packets < budget)) { |
1888 | union i40e_rx_desc *rx_desc; | |
a132af24 | 1889 | u16 vlan_tag; |
1a557afc JB |
1890 | u8 rx_ptype; |
1891 | u64 qword; | |
1892 | ||
fd0a05ce JB |
1893 | /* return some buffers to hardware, one at a time is too slow */ |
1894 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 1895 | failure = failure || |
1a557afc | 1896 | i40e_alloc_rx_buffers(rx_ring, cleaned_count); |
fd0a05ce JB |
1897 | cleaned_count = 0; |
1898 | } | |
1899 | ||
1a557afc JB |
1900 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
1901 | ||
1a557afc JB |
1902 | /* status_error_len will always be zero for unused descriptors |
1903 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
1904 | * which is always zero because packet split isn't used, if the | |
1905 | * hardware wrote DD then it will be non-zero | |
1906 | */ | |
99dad8b3 AD |
1907 | if (!i40e_test_staterr(rx_desc, |
1908 | BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) | |
1a557afc JB |
1909 | break; |
1910 | ||
a132af24 MW |
1911 | /* This memory barrier is needed to keep us from reading |
1912 | * any other fields out of the rx_desc until we know the | |
1913 | * DD bit is set. | |
1914 | */ | |
67317166 | 1915 | dma_rmb(); |
a132af24 | 1916 | |
e72e5659 | 1917 | skb = i40e_fetch_rx_buffer(rx_ring, rx_desc, skb); |
1a557afc JB |
1918 | if (!skb) |
1919 | break; | |
a132af24 | 1920 | |
a132af24 MW |
1921 | cleaned_count++; |
1922 | ||
1a557afc | 1923 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 1924 | continue; |
a132af24 | 1925 | |
1a557afc JB |
1926 | /* ERR_MASK will only have valid bits if EOP set, and |
1927 | * what we are doing here is actually checking | |
1928 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
1929 | * the error field | |
1930 | */ | |
1931 | if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
a132af24 | 1932 | dev_kfree_skb_any(skb); |
a132af24 MW |
1933 | continue; |
1934 | } | |
1935 | ||
e72e5659 SP |
1936 | if (i40e_cleanup_headers(rx_ring, skb)) { |
1937 | skb = NULL; | |
1a557afc | 1938 | continue; |
e72e5659 | 1939 | } |
a132af24 MW |
1940 | |
1941 | /* probably a little skewed due to removing CRC */ | |
1942 | total_rx_bytes += skb->len; | |
a132af24 | 1943 | |
99dad8b3 AD |
1944 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1945 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> | |
1946 | I40E_RXD_QW1_PTYPE_SHIFT; | |
1947 | ||
1a557afc JB |
1948 | /* populate checksum, VLAN, and protocol */ |
1949 | i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); | |
a132af24 | 1950 | |
a132af24 | 1951 | #ifdef I40E_FCOE |
1f15d667 JB |
1952 | if (unlikely( |
1953 | i40e_rx_is_fcoe(rx_ptype) && | |
1954 | !i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) { | |
a132af24 MW |
1955 | dev_kfree_skb_any(skb); |
1956 | continue; | |
1957 | } | |
1958 | #endif | |
1a557afc JB |
1959 | |
1960 | vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? | |
1961 | le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; | |
1962 | ||
a132af24 | 1963 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
e72e5659 | 1964 | skb = NULL; |
a132af24 | 1965 | |
1a557afc JB |
1966 | /* update budget accounting */ |
1967 | total_rx_packets++; | |
1968 | } | |
fd0a05ce | 1969 | |
e72e5659 SP |
1970 | rx_ring->skb = skb; |
1971 | ||
980e9b11 | 1972 | u64_stats_update_begin(&rx_ring->syncp); |
a114d0a6 AD |
1973 | rx_ring->stats.packets += total_rx_packets; |
1974 | rx_ring->stats.bytes += total_rx_bytes; | |
980e9b11 | 1975 | u64_stats_update_end(&rx_ring->syncp); |
fd0a05ce JB |
1976 | rx_ring->q_vector->rx.total_packets += total_rx_packets; |
1977 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1978 | ||
1a557afc | 1979 | /* guarantee a trip back through this routine if there was a failure */ |
c2e245ab | 1980 | return failure ? budget : total_rx_packets; |
fd0a05ce JB |
1981 | } |
1982 | ||
8f5e39ce JB |
1983 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
1984 | { | |
1985 | u32 val; | |
1986 | ||
1987 | val = I40E_PFINT_DYN_CTLN_INTENA_MASK | | |
40d72a50 JB |
1988 | /* Don't clear PBA because that can cause lost interrupts that |
1989 | * came in while we were cleaning/polling | |
1990 | */ | |
8f5e39ce JB |
1991 | (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | |
1992 | (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); | |
1993 | ||
1994 | return val; | |
1995 | } | |
1996 | ||
1997 | /* a small macro to shorten up some long lines */ | |
1998 | #define INTREG I40E_PFINT_DYN_CTLN | |
3c234c47 | 1999 | static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 | 2000 | { |
3c234c47 | 2001 | return vsi->rx_rings[idx]->rx_itr_setting; |
65e87c03 JK |
2002 | } |
2003 | ||
3c234c47 | 2004 | static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 | 2005 | { |
3c234c47 | 2006 | return vsi->tx_rings[idx]->tx_itr_setting; |
65e87c03 | 2007 | } |
8f5e39ce | 2008 | |
de32e3ef CW |
2009 | /** |
2010 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
2011 | * @vsi: the VSI we care about | |
2012 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
2013 | * | |
2014 | **/ | |
2015 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
2016 | struct i40e_q_vector *q_vector) | |
2017 | { | |
2018 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
2019 | bool rx = false, tx = false; |
2020 | u32 rxval, txval; | |
de32e3ef | 2021 | int vector; |
a75e8005 | 2022 | int idx = q_vector->v_idx; |
65e87c03 | 2023 | int rx_itr_setting, tx_itr_setting; |
de32e3ef CW |
2024 | |
2025 | vector = (q_vector->v_idx + vsi->base_vector); | |
8f5e39ce | 2026 | |
ee2319cf JB |
2027 | /* avoid dynamic calculation if in countdown mode OR if |
2028 | * all dynamic is disabled | |
2029 | */ | |
8f5e39ce JB |
2030 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
2031 | ||
3c234c47 CW |
2032 | rx_itr_setting = get_rx_itr(vsi, idx); |
2033 | tx_itr_setting = get_tx_itr(vsi, idx); | |
65e87c03 | 2034 | |
ee2319cf | 2035 | if (q_vector->itr_countdown > 0 || |
65e87c03 JK |
2036 | (!ITR_IS_DYNAMIC(rx_itr_setting) && |
2037 | !ITR_IS_DYNAMIC(tx_itr_setting))) { | |
ee2319cf JB |
2038 | goto enable_int; |
2039 | } | |
2040 | ||
65e87c03 | 2041 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
2042 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
2043 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 2044 | } |
8f5e39ce | 2045 | |
65e87c03 | 2046 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
2047 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
2048 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
de32e3ef | 2049 | } |
8f5e39ce JB |
2050 | |
2051 | if (rx || tx) { | |
2052 | /* get the higher of the two ITR adjustments and | |
2053 | * use the same value for both ITR registers | |
2054 | * when in adaptive mode (Rx and/or Tx) | |
2055 | */ | |
2056 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
2057 | ||
2058 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
2059 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
2060 | tx = true; | |
2061 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
2062 | rx = true; | |
2063 | } | |
2064 | ||
2065 | /* only need to enable the interrupt once, but need | |
2066 | * to possibly update both ITR values | |
2067 | */ | |
2068 | if (rx) { | |
2069 | /* set the INTENA_MSK_MASK so that this first write | |
2070 | * won't actually enable the interrupt, instead just | |
2071 | * updating the ITR (it's bit 31 PF and VF) | |
2072 | */ | |
2073 | rxval |= BIT(31); | |
2074 | /* don't check _DOWN because interrupt isn't being enabled */ | |
2075 | wr32(hw, INTREG(vector - 1), rxval); | |
2076 | } | |
2077 | ||
ee2319cf | 2078 | enable_int: |
8f5e39ce JB |
2079 | if (!test_bit(__I40E_DOWN, &vsi->state)) |
2080 | wr32(hw, INTREG(vector - 1), txval); | |
ee2319cf JB |
2081 | |
2082 | if (q_vector->itr_countdown) | |
2083 | q_vector->itr_countdown--; | |
2084 | else | |
2085 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
2086 | } |
2087 | ||
fd0a05ce JB |
2088 | /** |
2089 | * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine | |
2090 | * @napi: napi struct with our devices info in it | |
2091 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2092 | * | |
2093 | * This function will clean all queues associated with a q_vector. | |
2094 | * | |
2095 | * Returns the amount of work done | |
2096 | **/ | |
2097 | int i40e_napi_poll(struct napi_struct *napi, int budget) | |
2098 | { | |
2099 | struct i40e_q_vector *q_vector = | |
2100 | container_of(napi, struct i40e_q_vector, napi); | |
2101 | struct i40e_vsi *vsi = q_vector->vsi; | |
cd0b6fa6 | 2102 | struct i40e_ring *ring; |
fd0a05ce | 2103 | bool clean_complete = true; |
d91649f5 | 2104 | bool arm_wb = false; |
fd0a05ce | 2105 | int budget_per_ring; |
32b3e08f | 2106 | int work_done = 0; |
fd0a05ce JB |
2107 | |
2108 | if (test_bit(__I40E_DOWN, &vsi->state)) { | |
2109 | napi_complete(napi); | |
2110 | return 0; | |
2111 | } | |
2112 | ||
9c6c1259 KP |
2113 | /* Clear hung_detected bit */ |
2114 | clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected); | |
cd0b6fa6 AD |
2115 | /* Since the actual Tx work is minimal, we can give the Tx a larger |
2116 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
2117 | */ | |
d91649f5 | 2118 | i40e_for_each_ring(ring, q_vector->tx) { |
a619afe8 | 2119 | if (!i40e_clean_tx_irq(vsi, ring, budget)) { |
f2edaaaa AD |
2120 | clean_complete = false; |
2121 | continue; | |
2122 | } | |
2123 | arm_wb |= ring->arm_wb; | |
0deda868 | 2124 | ring->arm_wb = false; |
d91649f5 | 2125 | } |
cd0b6fa6 | 2126 | |
c67caceb AD |
2127 | /* Handle case where we are called by netpoll with a budget of 0 */ |
2128 | if (budget <= 0) | |
2129 | goto tx_only; | |
2130 | ||
fd0a05ce JB |
2131 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
2132 | * allow the budget to go below 1 because that would exit polling early. | |
fd0a05ce JB |
2133 | */ |
2134 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
cd0b6fa6 | 2135 | |
a132af24 | 2136 | i40e_for_each_ring(ring, q_vector->rx) { |
1a557afc | 2137 | int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); |
32b3e08f JB |
2138 | |
2139 | work_done += cleaned; | |
f2edaaaa AD |
2140 | /* if we clean as many as budgeted, we must not be done */ |
2141 | if (cleaned >= budget_per_ring) | |
2142 | clean_complete = false; | |
a132af24 | 2143 | } |
fd0a05ce JB |
2144 | |
2145 | /* If work not completed, return budget and polling will return */ | |
d91649f5 | 2146 | if (!clean_complete) { |
96db776a AB |
2147 | const cpumask_t *aff_mask = &q_vector->affinity_mask; |
2148 | int cpu_id = smp_processor_id(); | |
2149 | ||
2150 | /* It is possible that the interrupt affinity has changed but, | |
2151 | * if the cpu is pegged at 100%, polling will never exit while | |
2152 | * traffic continues and the interrupt will be stuck on this | |
2153 | * cpu. We check to make sure affinity is correct before we | |
2154 | * continue to poll, otherwise we must stop polling so the | |
2155 | * interrupt can move to the correct cpu. | |
2156 | */ | |
2157 | if (likely(cpumask_test_cpu(cpu_id, aff_mask) || | |
2158 | !(vsi->back->flags & I40E_FLAG_MSIX_ENABLED))) { | |
c67caceb | 2159 | tx_only: |
96db776a AB |
2160 | if (arm_wb) { |
2161 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
2162 | i40e_enable_wb_on_itr(vsi, q_vector); | |
2163 | } | |
2164 | return budget; | |
164c9f54 | 2165 | } |
d91649f5 | 2166 | } |
fd0a05ce | 2167 | |
8e0764b4 ASJ |
2168 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
2169 | q_vector->arm_wb_state = false; | |
2170 | ||
fd0a05ce | 2171 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 2172 | napi_complete_done(napi, work_done); |
96db776a AB |
2173 | |
2174 | /* If we're prematurely stopping polling to fix the interrupt | |
2175 | * affinity we want to make sure polling starts back up so we | |
2176 | * issue a call to i40e_force_wb which triggers a SW interrupt. | |
2177 | */ | |
2178 | if (!clean_complete) | |
2179 | i40e_force_wb(vsi, q_vector); | |
2180 | else if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) | |
40d72a50 | 2181 | i40e_irq_dynamic_enable_icr0(vsi->back, false); |
96db776a AB |
2182 | else |
2183 | i40e_update_enable_itr(vsi, q_vector); | |
2184 | ||
6beb84a7 | 2185 | return min(work_done, budget - 1); |
fd0a05ce JB |
2186 | } |
2187 | ||
2188 | /** | |
2189 | * i40e_atr - Add a Flow Director ATR filter | |
2190 | * @tx_ring: ring to add programming descriptor to | |
2191 | * @skb: send buffer | |
89232c3b | 2192 | * @tx_flags: send tx flags |
fd0a05ce JB |
2193 | **/ |
2194 | static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
6b037cd4 | 2195 | u32 tx_flags) |
fd0a05ce JB |
2196 | { |
2197 | struct i40e_filter_program_desc *fdir_desc; | |
2198 | struct i40e_pf *pf = tx_ring->vsi->back; | |
2199 | union { | |
2200 | unsigned char *network; | |
2201 | struct iphdr *ipv4; | |
2202 | struct ipv6hdr *ipv6; | |
2203 | } hdr; | |
2204 | struct tcphdr *th; | |
2205 | unsigned int hlen; | |
2206 | u32 flex_ptype, dtype_cmd; | |
ffcc55c0 | 2207 | int l4_proto; |
fc4ac67b | 2208 | u16 i; |
fd0a05ce JB |
2209 | |
2210 | /* make sure ATR is enabled */ | |
60ea5f83 | 2211 | if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) |
fd0a05ce JB |
2212 | return; |
2213 | ||
b77ac975 | 2214 | if ((pf->hw_disabled_flags & I40E_FLAG_FD_ATR_ENABLED)) |
04294e38 ASJ |
2215 | return; |
2216 | ||
fd0a05ce JB |
2217 | /* if sampling is disabled do nothing */ |
2218 | if (!tx_ring->atr_sample_rate) | |
2219 | return; | |
2220 | ||
6b037cd4 | 2221 | /* Currently only IPv4/IPv6 with TCP is supported */ |
89232c3b ASJ |
2222 | if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) |
2223 | return; | |
fd0a05ce | 2224 | |
ffcc55c0 AD |
2225 | /* snag network header to get L4 type and address */ |
2226 | hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? | |
2227 | skb_inner_network_header(skb) : skb_network_header(skb); | |
fd0a05ce | 2228 | |
ffcc55c0 AD |
2229 | /* Note: tx_flags gets modified to reflect inner protocols in |
2230 | * tx_enable_csum function if encap is enabled. | |
2231 | */ | |
2232 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
6b037cd4 | 2233 | /* access ihl as u8 to avoid unaligned access on ia64 */ |
ffcc55c0 AD |
2234 | hlen = (hdr.network[0] & 0x0F) << 2; |
2235 | l4_proto = hdr.ipv4->protocol; | |
fd0a05ce | 2236 | } else { |
ffcc55c0 AD |
2237 | hlen = hdr.network - skb->data; |
2238 | l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); | |
2239 | hlen -= hdr.network - skb->data; | |
fd0a05ce JB |
2240 | } |
2241 | ||
6b037cd4 | 2242 | if (l4_proto != IPPROTO_TCP) |
89232c3b ASJ |
2243 | return; |
2244 | ||
fd0a05ce JB |
2245 | th = (struct tcphdr *)(hdr.network + hlen); |
2246 | ||
55a5e60b | 2247 | /* Due to lack of space, no more new filters can be programmed */ |
b77ac975 | 2248 | if (th->syn && (pf->hw_disabled_flags & I40E_FLAG_FD_ATR_ENABLED)) |
55a5e60b | 2249 | return; |
72b74869 | 2250 | if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && |
b77ac975 | 2251 | (!(pf->hw_disabled_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) { |
52eb95ef ASJ |
2252 | /* HW ATR eviction will take care of removing filters on FIN |
2253 | * and RST packets. | |
2254 | */ | |
2255 | if (th->fin || th->rst) | |
2256 | return; | |
2257 | } | |
55a5e60b ASJ |
2258 | |
2259 | tx_ring->atr_count++; | |
2260 | ||
ce806783 ASJ |
2261 | /* sample on all syn/fin/rst packets or once every atr sample rate */ |
2262 | if (!th->fin && | |
2263 | !th->syn && | |
2264 | !th->rst && | |
2265 | (tx_ring->atr_count < tx_ring->atr_sample_rate)) | |
fd0a05ce JB |
2266 | return; |
2267 | ||
2268 | tx_ring->atr_count = 0; | |
2269 | ||
2270 | /* grab the next descriptor */ | |
fc4ac67b AD |
2271 | i = tx_ring->next_to_use; |
2272 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
2273 | ||
2274 | i++; | |
2275 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2276 | |
2277 | flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & | |
2278 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
6b037cd4 | 2279 | flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? |
fd0a05ce JB |
2280 | (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << |
2281 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : | |
2282 | (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << | |
2283 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
2284 | ||
2285 | flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
2286 | ||
2287 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
2288 | ||
ce806783 | 2289 | dtype_cmd |= (th->fin || th->rst) ? |
fd0a05ce JB |
2290 | (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
2291 | I40E_TXD_FLTR_QW1_PCMD_SHIFT) : | |
2292 | (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
2293 | I40E_TXD_FLTR_QW1_PCMD_SHIFT); | |
2294 | ||
2295 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << | |
2296 | I40E_TXD_FLTR_QW1_DEST_SHIFT; | |
2297 | ||
2298 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << | |
2299 | I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; | |
2300 | ||
433c47de | 2301 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
6a899024 | 2302 | if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) |
60ccd45c ASJ |
2303 | dtype_cmd |= |
2304 | ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << | |
2305 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2306 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
2307 | else | |
2308 | dtype_cmd |= | |
2309 | ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << | |
2310 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2311 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
433c47de | 2312 | |
72b74869 | 2313 | if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && |
b77ac975 | 2314 | (!(pf->hw_disabled_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) |
52eb95ef ASJ |
2315 | dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; |
2316 | ||
fd0a05ce | 2317 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); |
99753ea6 | 2318 | fdir_desc->rsvd = cpu_to_le32(0); |
fd0a05ce | 2319 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); |
99753ea6 | 2320 | fdir_desc->fd_id = cpu_to_le32(0); |
fd0a05ce JB |
2321 | } |
2322 | ||
fd0a05ce JB |
2323 | /** |
2324 | * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW | |
2325 | * @skb: send buffer | |
2326 | * @tx_ring: ring to send buffer on | |
2327 | * @flags: the tx flags to be set | |
2328 | * | |
2329 | * Checks the skb and set up correspondingly several generic transmit flags | |
2330 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
2331 | * | |
2332 | * Returns error code indicate the frame should be dropped upon error and the | |
2333 | * otherwise returns 0 to indicate the flags has been set properly. | |
2334 | **/ | |
38e00438 | 2335 | #ifdef I40E_FCOE |
3e587cf3 | 2336 | inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, |
fd0a05ce JB |
2337 | struct i40e_ring *tx_ring, |
2338 | u32 *flags) | |
3e587cf3 JB |
2339 | #else |
2340 | static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, | |
2341 | struct i40e_ring *tx_ring, | |
2342 | u32 *flags) | |
38e00438 | 2343 | #endif |
fd0a05ce JB |
2344 | { |
2345 | __be16 protocol = skb->protocol; | |
2346 | u32 tx_flags = 0; | |
2347 | ||
31eaaccf GR |
2348 | if (protocol == htons(ETH_P_8021Q) && |
2349 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
2350 | /* When HW VLAN acceleration is turned off by the user the | |
2351 | * stack sets the protocol to 8021q so that the driver | |
2352 | * can take any steps required to support the SW only | |
2353 | * VLAN handling. In our case the driver doesn't need | |
2354 | * to take any further steps so just set the protocol | |
2355 | * to the encapsulated ethertype. | |
2356 | */ | |
2357 | skb->protocol = vlan_get_protocol(skb); | |
2358 | goto out; | |
2359 | } | |
2360 | ||
fd0a05ce | 2361 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
2362 | if (skb_vlan_tag_present(skb)) { |
2363 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
fd0a05ce JB |
2364 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
2365 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
0e2fe46c | 2366 | } else if (protocol == htons(ETH_P_8021Q)) { |
fd0a05ce | 2367 | struct vlan_hdr *vhdr, _vhdr; |
6995b36c | 2368 | |
fd0a05ce JB |
2369 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
2370 | if (!vhdr) | |
2371 | return -EINVAL; | |
2372 | ||
2373 | protocol = vhdr->h_vlan_encapsulated_proto; | |
2374 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
2375 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
2376 | } | |
2377 | ||
d40d00b1 NP |
2378 | if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) |
2379 | goto out; | |
2380 | ||
fd0a05ce | 2381 | /* Insert 802.1p priority into VLAN header */ |
38e00438 VD |
2382 | if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || |
2383 | (skb->priority != TC_PRIO_CONTROL)) { | |
fd0a05ce JB |
2384 | tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; |
2385 | tx_flags |= (skb->priority & 0x7) << | |
2386 | I40E_TX_FLAGS_VLAN_PRIO_SHIFT; | |
2387 | if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { | |
2388 | struct vlan_ethhdr *vhdr; | |
dd225bc6 FR |
2389 | int rc; |
2390 | ||
2391 | rc = skb_cow_head(skb, 0); | |
2392 | if (rc < 0) | |
2393 | return rc; | |
fd0a05ce JB |
2394 | vhdr = (struct vlan_ethhdr *)skb->data; |
2395 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
2396 | I40E_TX_FLAGS_VLAN_SHIFT); | |
2397 | } else { | |
2398 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; | |
2399 | } | |
2400 | } | |
d40d00b1 NP |
2401 | |
2402 | out: | |
fd0a05ce JB |
2403 | *flags = tx_flags; |
2404 | return 0; | |
2405 | } | |
2406 | ||
fd0a05ce JB |
2407 | /** |
2408 | * i40e_tso - set up the tso context descriptor | |
52ea3e80 | 2409 | * @first: pointer to first Tx buffer for xmit |
fd0a05ce | 2410 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 2411 | * @cd_type_cmd_tso_mss: Quad Word 1 |
fd0a05ce JB |
2412 | * |
2413 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
2414 | **/ | |
52ea3e80 AD |
2415 | static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, |
2416 | u64 *cd_type_cmd_tso_mss) | |
fd0a05ce | 2417 | { |
52ea3e80 | 2418 | struct sk_buff *skb = first->skb; |
03f9d6a5 | 2419 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
2420 | union { |
2421 | struct iphdr *v4; | |
2422 | struct ipv6hdr *v6; | |
2423 | unsigned char *hdr; | |
2424 | } ip; | |
c49a7bc3 AD |
2425 | union { |
2426 | struct tcphdr *tcp; | |
5453205c | 2427 | struct udphdr *udp; |
c49a7bc3 AD |
2428 | unsigned char *hdr; |
2429 | } l4; | |
2430 | u32 paylen, l4_offset; | |
52ea3e80 | 2431 | u16 gso_segs, gso_size; |
fd0a05ce | 2432 | int err; |
fd0a05ce | 2433 | |
e9f6563d SN |
2434 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2435 | return 0; | |
2436 | ||
fd0a05ce JB |
2437 | if (!skb_is_gso(skb)) |
2438 | return 0; | |
2439 | ||
dd225bc6 FR |
2440 | err = skb_cow_head(skb, 0); |
2441 | if (err < 0) | |
2442 | return err; | |
fd0a05ce | 2443 | |
c777019a AD |
2444 | ip.hdr = skb_network_header(skb); |
2445 | l4.hdr = skb_transport_header(skb); | |
df23075f | 2446 | |
c777019a AD |
2447 | /* initialize outer IP header fields */ |
2448 | if (ip.v4->version == 4) { | |
2449 | ip.v4->tot_len = 0; | |
2450 | ip.v4->check = 0; | |
c49a7bc3 | 2451 | } else { |
c777019a AD |
2452 | ip.v6->payload_len = 0; |
2453 | } | |
2454 | ||
577389a5 | 2455 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 2456 | SKB_GSO_GRE_CSUM | |
7e13318d | 2457 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 2458 | SKB_GSO_IPXIP6 | |
577389a5 | 2459 | SKB_GSO_UDP_TUNNEL | |
5453205c | 2460 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
2461 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
2462 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
2463 | l4.udp->len = 0; | |
2464 | ||
5453205c AD |
2465 | /* determine offset of outer transport header */ |
2466 | l4_offset = l4.hdr - skb->data; | |
2467 | ||
2468 | /* remove payload length from outer checksum */ | |
24d41e5e | 2469 | paylen = skb->len - l4_offset; |
b9c015d4 JK |
2470 | csum_replace_by_diff(&l4.udp->check, |
2471 | (__force __wsum)htonl(paylen)); | |
5453205c AD |
2472 | } |
2473 | ||
c777019a AD |
2474 | /* reset pointers to inner headers */ |
2475 | ip.hdr = skb_inner_network_header(skb); | |
2476 | l4.hdr = skb_inner_transport_header(skb); | |
2477 | ||
2478 | /* initialize inner IP header fields */ | |
2479 | if (ip.v4->version == 4) { | |
2480 | ip.v4->tot_len = 0; | |
2481 | ip.v4->check = 0; | |
2482 | } else { | |
2483 | ip.v6->payload_len = 0; | |
2484 | } | |
fd0a05ce JB |
2485 | } |
2486 | ||
c49a7bc3 AD |
2487 | /* determine offset of inner transport header */ |
2488 | l4_offset = l4.hdr - skb->data; | |
2489 | ||
2490 | /* remove payload length from inner checksum */ | |
24d41e5e | 2491 | paylen = skb->len - l4_offset; |
b9c015d4 | 2492 | csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); |
c49a7bc3 AD |
2493 | |
2494 | /* compute length of segmentation header */ | |
2495 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
fd0a05ce | 2496 | |
52ea3e80 AD |
2497 | /* pull values out of skb_shinfo */ |
2498 | gso_size = skb_shinfo(skb)->gso_size; | |
2499 | gso_segs = skb_shinfo(skb)->gso_segs; | |
2500 | ||
2501 | /* update GSO size and bytecount with header size */ | |
2502 | first->gso_segs = gso_segs; | |
2503 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
2504 | ||
fd0a05ce JB |
2505 | /* find the field values */ |
2506 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
2507 | cd_tso_len = skb->len - *hdr_len; | |
52ea3e80 | 2508 | cd_mss = gso_size; |
03f9d6a5 AD |
2509 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
2510 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
2511 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
fd0a05ce JB |
2512 | return 1; |
2513 | } | |
2514 | ||
beb0dff1 JK |
2515 | /** |
2516 | * i40e_tsyn - set up the tsyn context descriptor | |
2517 | * @tx_ring: ptr to the ring to send | |
2518 | * @skb: ptr to the skb we're sending | |
2519 | * @tx_flags: the collected send information | |
9c883bd3 | 2520 | * @cd_type_cmd_tso_mss: Quad Word 1 |
beb0dff1 JK |
2521 | * |
2522 | * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen | |
2523 | **/ | |
2524 | static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2525 | u32 tx_flags, u64 *cd_type_cmd_tso_mss) | |
2526 | { | |
2527 | struct i40e_pf *pf; | |
2528 | ||
2529 | if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) | |
2530 | return 0; | |
2531 | ||
2532 | /* Tx timestamps cannot be sampled when doing TSO */ | |
2533 | if (tx_flags & I40E_TX_FLAGS_TSO) | |
2534 | return 0; | |
2535 | ||
2536 | /* only timestamp the outbound packet if the user has requested it and | |
2537 | * we are not already transmitting a packet to be timestamped | |
2538 | */ | |
2539 | pf = i40e_netdev_to_pf(tx_ring->netdev); | |
22b4777d JK |
2540 | if (!(pf->flags & I40E_FLAG_PTP)) |
2541 | return 0; | |
2542 | ||
9ce34f02 JK |
2543 | if (pf->ptp_tx && |
2544 | !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { | |
beb0dff1 JK |
2545 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
2546 | pf->ptp_tx_skb = skb_get(skb); | |
2547 | } else { | |
2548 | return 0; | |
2549 | } | |
2550 | ||
2551 | *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << | |
2552 | I40E_TXD_CTX_QW1_CMD_SHIFT; | |
2553 | ||
beb0dff1 JK |
2554 | return 1; |
2555 | } | |
2556 | ||
fd0a05ce JB |
2557 | /** |
2558 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
2559 | * @skb: send buffer | |
89232c3b | 2560 | * @tx_flags: pointer to Tx flags currently set |
fd0a05ce JB |
2561 | * @td_cmd: Tx descriptor command bits to set |
2562 | * @td_offset: Tx descriptor header offsets to set | |
554f4544 | 2563 | * @tx_ring: Tx descriptor ring |
fd0a05ce JB |
2564 | * @cd_tunneling: ptr to context desc bits |
2565 | **/ | |
529f1f65 AD |
2566 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
2567 | u32 *td_cmd, u32 *td_offset, | |
2568 | struct i40e_ring *tx_ring, | |
2569 | u32 *cd_tunneling) | |
fd0a05ce | 2570 | { |
b96b78f2 AD |
2571 | union { |
2572 | struct iphdr *v4; | |
2573 | struct ipv6hdr *v6; | |
2574 | unsigned char *hdr; | |
2575 | } ip; | |
2576 | union { | |
2577 | struct tcphdr *tcp; | |
2578 | struct udphdr *udp; | |
2579 | unsigned char *hdr; | |
2580 | } l4; | |
a3fd9d88 | 2581 | unsigned char *exthdr; |
d1bd743b | 2582 | u32 offset, cmd = 0; |
a3fd9d88 | 2583 | __be16 frag_off; |
b96b78f2 AD |
2584 | u8 l4_proto = 0; |
2585 | ||
529f1f65 AD |
2586 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2587 | return 0; | |
2588 | ||
b96b78f2 AD |
2589 | ip.hdr = skb_network_header(skb); |
2590 | l4.hdr = skb_transport_header(skb); | |
fd0a05ce | 2591 | |
475b4205 AD |
2592 | /* compute outer L2 header size */ |
2593 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
2594 | ||
fd0a05ce | 2595 | if (skb->encapsulation) { |
d1bd743b | 2596 | u32 tunnel = 0; |
a0064728 AD |
2597 | /* define outer network header type */ |
2598 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
2599 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2600 | I40E_TX_CTX_EXT_IP_IPV4 : | |
2601 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
2602 | ||
a0064728 AD |
2603 | l4_proto = ip.v4->protocol; |
2604 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 2605 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
2606 | |
2607 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 2608 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
2609 | if (l4.hdr != exthdr) |
2610 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2611 | &l4_proto, &frag_off); | |
a0064728 AD |
2612 | } |
2613 | ||
2614 | /* define outer transport */ | |
2615 | switch (l4_proto) { | |
45991204 | 2616 | case IPPROTO_UDP: |
475b4205 | 2617 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
6a899024 | 2618 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
45991204 | 2619 | break; |
c1d1791d | 2620 | case IPPROTO_GRE: |
475b4205 | 2621 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 | 2622 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
c1d1791d | 2623 | break; |
577389a5 AD |
2624 | case IPPROTO_IPIP: |
2625 | case IPPROTO_IPV6: | |
2626 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; | |
2627 | l4.hdr = skb_inner_network_header(skb); | |
2628 | break; | |
45991204 | 2629 | default: |
529f1f65 AD |
2630 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2631 | return -1; | |
2632 | ||
2633 | skb_checksum_help(skb); | |
2634 | return 0; | |
45991204 | 2635 | } |
b96b78f2 | 2636 | |
577389a5 AD |
2637 | /* compute outer L3 header size */ |
2638 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
2639 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
2640 | ||
2641 | /* switch IP header pointer from outer to inner header */ | |
2642 | ip.hdr = skb_inner_network_header(skb); | |
2643 | ||
475b4205 AD |
2644 | /* compute tunnel header size */ |
2645 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
2646 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
2647 | ||
5453205c AD |
2648 | /* indicate if we need to offload outer UDP header */ |
2649 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 2650 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
2651 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
2652 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
2653 | ||
475b4205 AD |
2654 | /* record tunnel offload values */ |
2655 | *cd_tunneling |= tunnel; | |
2656 | ||
b96b78f2 | 2657 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 2658 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 2659 | l4_proto = 0; |
fd0a05ce | 2660 | |
a0064728 AD |
2661 | /* reset type as we transition from outer to inner headers */ |
2662 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
2663 | if (ip.v4->version == 4) | |
2664 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
2665 | if (ip.v6->version == 6) | |
89232c3b | 2666 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
fd0a05ce JB |
2667 | } |
2668 | ||
2669 | /* Enable IP checksum offloads */ | |
89232c3b | 2670 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 2671 | l4_proto = ip.v4->protocol; |
fd0a05ce JB |
2672 | /* the stack computes the IP header already, the only time we |
2673 | * need the hardware to recompute it is in the case of TSO. | |
2674 | */ | |
475b4205 AD |
2675 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2676 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
2677 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 2678 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 2679 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
2680 | |
2681 | exthdr = ip.hdr + sizeof(*ip.v6); | |
2682 | l4_proto = ip.v6->nexthdr; | |
2683 | if (l4.hdr != exthdr) | |
2684 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2685 | &l4_proto, &frag_off); | |
fd0a05ce | 2686 | } |
b96b78f2 | 2687 | |
475b4205 AD |
2688 | /* compute inner L3 header size */ |
2689 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
fd0a05ce JB |
2690 | |
2691 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 2692 | switch (l4_proto) { |
fd0a05ce JB |
2693 | case IPPROTO_TCP: |
2694 | /* enable checksum offloads */ | |
475b4205 AD |
2695 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
2696 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2697 | break; |
2698 | case IPPROTO_SCTP: | |
2699 | /* enable SCTP checksum offload */ | |
475b4205 AD |
2700 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
2701 | offset |= (sizeof(struct sctphdr) >> 2) << | |
2702 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2703 | break; |
2704 | case IPPROTO_UDP: | |
2705 | /* enable UDP checksum offload */ | |
475b4205 AD |
2706 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
2707 | offset |= (sizeof(struct udphdr) >> 2) << | |
2708 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2709 | break; |
2710 | default: | |
529f1f65 AD |
2711 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2712 | return -1; | |
2713 | skb_checksum_help(skb); | |
2714 | return 0; | |
fd0a05ce | 2715 | } |
475b4205 AD |
2716 | |
2717 | *td_cmd |= cmd; | |
2718 | *td_offset |= offset; | |
529f1f65 AD |
2719 | |
2720 | return 1; | |
fd0a05ce JB |
2721 | } |
2722 | ||
2723 | /** | |
2724 | * i40e_create_tx_ctx Build the Tx context descriptor | |
2725 | * @tx_ring: ring to create the descriptor on | |
2726 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
2727 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
2728 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
2729 | **/ | |
2730 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
2731 | const u64 cd_type_cmd_tso_mss, | |
2732 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
2733 | { | |
2734 | struct i40e_tx_context_desc *context_desc; | |
fc4ac67b | 2735 | int i = tx_ring->next_to_use; |
fd0a05ce | 2736 | |
ff40dd5d JB |
2737 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
2738 | !cd_tunneling && !cd_l2tag2) | |
fd0a05ce JB |
2739 | return; |
2740 | ||
2741 | /* grab the next descriptor */ | |
fc4ac67b AD |
2742 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); |
2743 | ||
2744 | i++; | |
2745 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2746 | |
2747 | /* cpu_to_le32 and assign to struct fields */ | |
2748 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
2749 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 2750 | context_desc->rsvd = cpu_to_le16(0); |
fd0a05ce JB |
2751 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
2752 | } | |
2753 | ||
4567dc10 ED |
2754 | /** |
2755 | * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions | |
2756 | * @tx_ring: the ring to be checked | |
2757 | * @size: the size buffer we want to assure is available | |
2758 | * | |
2759 | * Returns -EBUSY if a stop is needed, else 0 | |
2760 | **/ | |
4ec441df | 2761 | int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
4567dc10 ED |
2762 | { |
2763 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2764 | /* Memory barrier before checking head and tail */ | |
2765 | smp_mb(); | |
2766 | ||
2767 | /* Check again in a case another CPU has just made room available. */ | |
2768 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
2769 | return -EBUSY; | |
2770 | ||
2771 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
2772 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2773 | ++tx_ring->tx_stats.restart_queue; | |
2774 | return 0; | |
2775 | } | |
2776 | ||
71da6197 | 2777 | /** |
3f3f7cb8 | 2778 | * __i40e_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 2779 | * @skb: send buffer |
71da6197 | 2780 | * |
3f3f7cb8 AD |
2781 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
2782 | * and so we need to figure out the cases where we need to linearize the skb. | |
2783 | * | |
2784 | * For TSO we need to count the TSO header and segment payload separately. | |
2785 | * As such we need to check cases where we have 7 fragments or more as we | |
2786 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
2787 | * the segment payload in the first descriptor, and another 7 for the | |
2788 | * fragments. | |
71da6197 | 2789 | **/ |
2d37490b | 2790 | bool __i40e_chk_linearize(struct sk_buff *skb) |
71da6197 | 2791 | { |
2d37490b | 2792 | const struct skb_frag_struct *frag, *stale; |
3f3f7cb8 | 2793 | int nr_frags, sum; |
71da6197 | 2794 | |
3f3f7cb8 | 2795 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 2796 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 2797 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 2798 | return false; |
71da6197 | 2799 | |
2d37490b | 2800 | /* We need to walk through the list and validate that each group |
841493a3 | 2801 | * of 6 fragments totals at least gso_size. |
2d37490b | 2802 | */ |
3f3f7cb8 | 2803 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
2804 | frag = &skb_shinfo(skb)->frags[0]; |
2805 | ||
2806 | /* Initialize size to the negative value of gso_size minus 1. We | |
2807 | * use this as the worst case scenerio in which the frag ahead | |
2808 | * of us only provides one byte which is why we are limited to 6 | |
2809 | * descriptors for a single transmit as the header and previous | |
2810 | * fragment are already consuming 2 descriptors. | |
2811 | */ | |
3f3f7cb8 | 2812 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 2813 | |
3f3f7cb8 AD |
2814 | /* Add size of frags 0 through 4 to create our initial sum */ |
2815 | sum += skb_frag_size(frag++); | |
2816 | sum += skb_frag_size(frag++); | |
2817 | sum += skb_frag_size(frag++); | |
2818 | sum += skb_frag_size(frag++); | |
2819 | sum += skb_frag_size(frag++); | |
2d37490b AD |
2820 | |
2821 | /* Walk through fragments adding latest fragment, testing it, and | |
2822 | * then removing stale fragments from the sum. | |
2823 | */ | |
2824 | stale = &skb_shinfo(skb)->frags[0]; | |
2825 | for (;;) { | |
3f3f7cb8 | 2826 | sum += skb_frag_size(frag++); |
2d37490b AD |
2827 | |
2828 | /* if sum is negative we failed to make sufficient progress */ | |
2829 | if (sum < 0) | |
2830 | return true; | |
2831 | ||
841493a3 | 2832 | if (!nr_frags--) |
2d37490b AD |
2833 | break; |
2834 | ||
3f3f7cb8 | 2835 | sum -= skb_frag_size(stale++); |
71da6197 AS |
2836 | } |
2837 | ||
2d37490b | 2838 | return false; |
71da6197 AS |
2839 | } |
2840 | ||
fd0a05ce JB |
2841 | /** |
2842 | * i40e_tx_map - Build the Tx descriptor | |
2843 | * @tx_ring: ring to send buffer on | |
2844 | * @skb: send buffer | |
2845 | * @first: first buffer info buffer to use | |
2846 | * @tx_flags: collected send information | |
2847 | * @hdr_len: size of the packet header | |
2848 | * @td_cmd: the command field in the descriptor | |
2849 | * @td_offset: offset for checksum or crc | |
2850 | **/ | |
38e00438 | 2851 | #ifdef I40E_FCOE |
3e587cf3 | 2852 | inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
fd0a05ce JB |
2853 | struct i40e_tx_buffer *first, u32 tx_flags, |
2854 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
3e587cf3 JB |
2855 | #else |
2856 | static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2857 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2858 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
38e00438 | 2859 | #endif |
fd0a05ce | 2860 | { |
fd0a05ce JB |
2861 | unsigned int data_len = skb->data_len; |
2862 | unsigned int size = skb_headlen(skb); | |
a5e9c572 | 2863 | struct skb_frag_struct *frag; |
fd0a05ce JB |
2864 | struct i40e_tx_buffer *tx_bi; |
2865 | struct i40e_tx_desc *tx_desc; | |
a5e9c572 | 2866 | u16 i = tx_ring->next_to_use; |
fd0a05ce JB |
2867 | u32 td_tag = 0; |
2868 | dma_addr_t dma; | |
1dc8b538 | 2869 | u16 desc_count = 1; |
fd0a05ce | 2870 | |
fd0a05ce JB |
2871 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { |
2872 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2873 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2874 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2875 | } | |
2876 | ||
a5e9c572 AD |
2877 | first->tx_flags = tx_flags; |
2878 | ||
2879 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2880 | ||
fd0a05ce | 2881 | tx_desc = I40E_TX_DESC(tx_ring, i); |
a5e9c572 AD |
2882 | tx_bi = first; |
2883 | ||
2884 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
2885 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
2886 | ||
a5e9c572 AD |
2887 | if (dma_mapping_error(tx_ring->dev, dma)) |
2888 | goto dma_error; | |
2889 | ||
2890 | /* record length, and DMA address */ | |
2891 | dma_unmap_len_set(tx_bi, len, size); | |
2892 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2893 | ||
5c4654da AD |
2894 | /* align size to end of page */ |
2895 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
a5e9c572 AD |
2896 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2897 | ||
2898 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
fd0a05ce JB |
2899 | tx_desc->cmd_type_offset_bsz = |
2900 | build_ctob(td_cmd, td_offset, | |
5c4654da | 2901 | max_data, td_tag); |
fd0a05ce | 2902 | |
fd0a05ce JB |
2903 | tx_desc++; |
2904 | i++; | |
58044743 AS |
2905 | desc_count++; |
2906 | ||
fd0a05ce JB |
2907 | if (i == tx_ring->count) { |
2908 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2909 | i = 0; | |
2910 | } | |
fd0a05ce | 2911 | |
5c4654da AD |
2912 | dma += max_data; |
2913 | size -= max_data; | |
fd0a05ce | 2914 | |
5c4654da | 2915 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
a5e9c572 AD |
2916 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2917 | } | |
fd0a05ce JB |
2918 | |
2919 | if (likely(!data_len)) | |
2920 | break; | |
2921 | ||
a5e9c572 AD |
2922 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, |
2923 | size, td_tag); | |
fd0a05ce JB |
2924 | |
2925 | tx_desc++; | |
2926 | i++; | |
58044743 AS |
2927 | desc_count++; |
2928 | ||
fd0a05ce JB |
2929 | if (i == tx_ring->count) { |
2930 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2931 | i = 0; | |
2932 | } | |
2933 | ||
a5e9c572 AD |
2934 | size = skb_frag_size(frag); |
2935 | data_len -= size; | |
fd0a05ce | 2936 | |
a5e9c572 AD |
2937 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
2938 | DMA_TO_DEVICE); | |
fd0a05ce | 2939 | |
a5e9c572 AD |
2940 | tx_bi = &tx_ring->tx_bi[i]; |
2941 | } | |
fd0a05ce | 2942 | |
1dc8b538 | 2943 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
a5e9c572 AD |
2944 | |
2945 | i++; | |
2946 | if (i == tx_ring->count) | |
2947 | i = 0; | |
2948 | ||
2949 | tx_ring->next_to_use = i; | |
2950 | ||
4567dc10 | 2951 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
58044743 | 2952 | |
1dc8b538 AD |
2953 | /* write last descriptor with EOP bit */ |
2954 | td_cmd |= I40E_TX_DESC_CMD_EOP; | |
2955 | ||
2956 | /* We can OR these values together as they both are checked against | |
2957 | * 4 below and at this point desc_count will be used as a boolean value | |
2958 | * after this if/else block. | |
2959 | */ | |
2960 | desc_count |= ++tx_ring->packet_stride; | |
2961 | ||
58044743 | 2962 | /* Algorithm to optimize tail and RS bit setting: |
1dc8b538 AD |
2963 | * if queue is stopped |
2964 | * mark RS bit | |
2965 | * reset packet counter | |
2966 | * else if xmit_more is supported and is true | |
2967 | * advance packet counter to 4 | |
2968 | * reset desc_count to 0 | |
58044743 | 2969 | * |
1dc8b538 AD |
2970 | * if desc_count >= 4 |
2971 | * mark RS bit | |
2972 | * reset packet counter | |
2973 | * if desc_count > 0 | |
2974 | * update tail | |
58044743 | 2975 | * |
1dc8b538 | 2976 | * Note: If there are less than 4 descriptors |
58044743 AS |
2977 | * pending and interrupts were disabled the service task will |
2978 | * trigger a force WB. | |
2979 | */ | |
1dc8b538 AD |
2980 | if (netif_xmit_stopped(txring_txq(tx_ring))) { |
2981 | goto do_rs; | |
2982 | } else if (skb->xmit_more) { | |
2983 | /* set stride to arm on next packet and reset desc_count */ | |
2984 | tx_ring->packet_stride = WB_STRIDE; | |
2985 | desc_count = 0; | |
2986 | } else if (desc_count >= WB_STRIDE) { | |
2987 | do_rs: | |
2988 | /* write last descriptor with RS bit set */ | |
2989 | td_cmd |= I40E_TX_DESC_CMD_RS; | |
58044743 | 2990 | tx_ring->packet_stride = 0; |
58044743 | 2991 | } |
58044743 AS |
2992 | |
2993 | tx_desc->cmd_type_offset_bsz = | |
1dc8b538 AD |
2994 | build_ctob(td_cmd, td_offset, size, td_tag); |
2995 | ||
2996 | /* Force memory writes to complete before letting h/w know there | |
2997 | * are new descriptors to fetch. | |
2998 | * | |
2999 | * We also use this memory barrier to make certain all of the | |
3000 | * status bits have been updated before next_to_watch is written. | |
3001 | */ | |
3002 | wmb(); | |
3003 | ||
3004 | /* set next_to_watch value indicating a packet is present */ | |
3005 | first->next_to_watch = tx_desc; | |
58044743 | 3006 | |
a5e9c572 | 3007 | /* notify HW of packet */ |
1dc8b538 | 3008 | if (desc_count) { |
58044743 | 3009 | writel(i, tx_ring->tail); |
1dc8b538 AD |
3010 | |
3011 | /* we need this if more than one processor can write to our tail | |
3012 | * at a time, it synchronizes IO on IA64/Altix systems | |
3013 | */ | |
3014 | mmiowb(); | |
58044743 | 3015 | } |
1dc8b538 | 3016 | |
fd0a05ce JB |
3017 | return; |
3018 | ||
3019 | dma_error: | |
a5e9c572 | 3020 | dev_info(tx_ring->dev, "TX DMA map failed\n"); |
fd0a05ce JB |
3021 | |
3022 | /* clear dma mappings for failed tx_bi map */ | |
3023 | for (;;) { | |
3024 | tx_bi = &tx_ring->tx_bi[i]; | |
a5e9c572 | 3025 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); |
fd0a05ce JB |
3026 | if (tx_bi == first) |
3027 | break; | |
3028 | if (i == 0) | |
3029 | i = tx_ring->count; | |
3030 | i--; | |
3031 | } | |
3032 | ||
fd0a05ce JB |
3033 | tx_ring->next_to_use = i; |
3034 | } | |
3035 | ||
fd0a05ce JB |
3036 | /** |
3037 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
3038 | * @skb: send buffer | |
3039 | * @tx_ring: ring to send buffer on | |
3040 | * | |
3041 | * Returns NETDEV_TX_OK if sent, else an error code | |
3042 | **/ | |
3043 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
3044 | struct i40e_ring *tx_ring) | |
3045 | { | |
3046 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
3047 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
3048 | struct i40e_tx_buffer *first; | |
3049 | u32 td_offset = 0; | |
3050 | u32 tx_flags = 0; | |
3051 | __be16 protocol; | |
3052 | u32 td_cmd = 0; | |
3053 | u8 hdr_len = 0; | |
4ec441df | 3054 | int tso, count; |
beb0dff1 | 3055 | int tsyn; |
6995b36c | 3056 | |
b74118f0 JB |
3057 | /* prefetch the data, we'll need it later */ |
3058 | prefetch(skb->data); | |
3059 | ||
4ec441df | 3060 | count = i40e_xmit_descriptor_count(skb); |
2d37490b | 3061 | if (i40e_chk_linearize(skb, count)) { |
52ea3e80 AD |
3062 | if (__skb_linearize(skb)) { |
3063 | dev_kfree_skb_any(skb); | |
3064 | return NETDEV_TX_OK; | |
3065 | } | |
5c4654da | 3066 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
3067 | tx_ring->tx_stats.tx_linearize++; |
3068 | } | |
4ec441df AD |
3069 | |
3070 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
3071 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
3072 | * + 4 desc gap to avoid the cache line where head is, | |
3073 | * + 1 desc for context descriptor, | |
3074 | * otherwise try next time | |
3075 | */ | |
3076 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
3077 | tx_ring->tx_stats.tx_busy++; | |
fd0a05ce | 3078 | return NETDEV_TX_BUSY; |
4ec441df | 3079 | } |
fd0a05ce | 3080 | |
52ea3e80 AD |
3081 | /* record the location of the first descriptor for this packet */ |
3082 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
3083 | first->skb = skb; | |
3084 | first->bytecount = skb->len; | |
3085 | first->gso_segs = 1; | |
3086 | ||
fd0a05ce JB |
3087 | /* prepare the xmit flags */ |
3088 | if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) | |
3089 | goto out_drop; | |
3090 | ||
3091 | /* obtain protocol of skb */ | |
3d34dd03 | 3092 | protocol = vlan_get_protocol(skb); |
fd0a05ce | 3093 | |
fd0a05ce | 3094 | /* setup IPv4/IPv6 offloads */ |
0e2fe46c | 3095 | if (protocol == htons(ETH_P_IP)) |
fd0a05ce | 3096 | tx_flags |= I40E_TX_FLAGS_IPV4; |
0e2fe46c | 3097 | else if (protocol == htons(ETH_P_IPV6)) |
fd0a05ce JB |
3098 | tx_flags |= I40E_TX_FLAGS_IPV6; |
3099 | ||
52ea3e80 | 3100 | tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); |
fd0a05ce JB |
3101 | |
3102 | if (tso < 0) | |
3103 | goto out_drop; | |
3104 | else if (tso) | |
3105 | tx_flags |= I40E_TX_FLAGS_TSO; | |
3106 | ||
3bc67973 AD |
3107 | /* Always offload the checksum, since it's in the data descriptor */ |
3108 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, | |
3109 | tx_ring, &cd_tunneling); | |
3110 | if (tso < 0) | |
3111 | goto out_drop; | |
3112 | ||
beb0dff1 JK |
3113 | tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); |
3114 | ||
3115 | if (tsyn) | |
3116 | tx_flags |= I40E_TX_FLAGS_TSYN; | |
3117 | ||
259afec7 JK |
3118 | skb_tx_timestamp(skb); |
3119 | ||
b1941306 AD |
3120 | /* always enable CRC insertion offload */ |
3121 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
3122 | ||
fd0a05ce JB |
3123 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
3124 | cd_tunneling, cd_l2tag2); | |
3125 | ||
3126 | /* Add Flow Director ATR if it's enabled. | |
3127 | * | |
3128 | * NOTE: this must always be directly before the data descriptor. | |
3129 | */ | |
6b037cd4 | 3130 | i40e_atr(tx_ring, skb, tx_flags); |
fd0a05ce JB |
3131 | |
3132 | i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, | |
3133 | td_cmd, td_offset); | |
3134 | ||
fd0a05ce JB |
3135 | return NETDEV_TX_OK; |
3136 | ||
3137 | out_drop: | |
52ea3e80 AD |
3138 | dev_kfree_skb_any(first->skb); |
3139 | first->skb = NULL; | |
fd0a05ce JB |
3140 | return NETDEV_TX_OK; |
3141 | } | |
3142 | ||
3143 | /** | |
3144 | * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
3145 | * @skb: send buffer | |
3146 | * @netdev: network interface device structure | |
3147 | * | |
3148 | * Returns NETDEV_TX_OK if sent, else an error code | |
3149 | **/ | |
3150 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
3151 | { | |
3152 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
3153 | struct i40e_vsi *vsi = np->vsi; | |
9f65e15b | 3154 | struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; |
fd0a05ce JB |
3155 | |
3156 | /* hardware can't handle really short frames, hardware padding works | |
3157 | * beyond this point | |
3158 | */ | |
a94d9e22 AD |
3159 | if (skb_put_padto(skb, I40E_MIN_TX_LEN)) |
3160 | return NETDEV_TX_OK; | |
fd0a05ce JB |
3161 | |
3162 | return i40e_xmit_frame_ring(skb, tx_ring); | |
3163 | } |