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ae06c70b | 1 | // SPDX-License-Identifier: GPL-2.0 |
51dce24b | 2 | /* Copyright(c) 2013 - 2018 Intel Corporation. */ |
fd0a05ce | 3 | |
1c112a64 | 4 | #include <linux/prefetch.h> |
0c8493d9 | 5 | #include <linux/bpf_trace.h> |
87128824 | 6 | #include <net/xdp.h> |
fd0a05ce | 7 | #include "i40e.h" |
ed0980c4 | 8 | #include "i40e_trace.h" |
206812b5 | 9 | #include "i40e_prototype.h" |
20a739db | 10 | #include "i40e_txrx_common.h" |
0a714186 | 11 | #include "i40e_xsk.h" |
fd0a05ce | 12 | |
eaefbd06 | 13 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) |
5e02f283 AD |
14 | /** |
15 | * i40e_fdir - Generate a Flow Director descriptor based on fdata | |
16 | * @tx_ring: Tx ring to send buffer on | |
17 | * @fdata: Flow director filter data | |
18 | * @add: Indicate if we are adding a rule or deleting one | |
19 | * | |
20 | **/ | |
21 | static void i40e_fdir(struct i40e_ring *tx_ring, | |
22 | struct i40e_fdir_filter *fdata, bool add) | |
23 | { | |
24 | struct i40e_filter_program_desc *fdir_desc; | |
25 | struct i40e_pf *pf = tx_ring->vsi->back; | |
26 | u32 flex_ptype, dtype_cmd; | |
27 | u16 i; | |
28 | ||
29 | /* grab the next descriptor */ | |
30 | i = tx_ring->next_to_use; | |
31 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
32 | ||
33 | i++; | |
34 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
35 | ||
36 | flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & | |
37 | (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); | |
38 | ||
39 | flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & | |
40 | (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); | |
41 | ||
42 | flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & | |
43 | (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
44 | ||
0e588de1 JK |
45 | flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & |
46 | (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); | |
47 | ||
5e02f283 AD |
48 | /* Use LAN VSI Id if not programmed by user */ |
49 | flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & | |
50 | ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << | |
51 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); | |
52 | ||
53 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
54 | ||
55 | dtype_cmd |= add ? | |
56 | I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
57 | I40E_TXD_FLTR_QW1_PCMD_SHIFT : | |
58 | I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << | |
59 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
60 | ||
61 | dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & | |
62 | (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); | |
63 | ||
64 | dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & | |
65 | (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); | |
66 | ||
67 | if (fdata->cnt_index) { | |
68 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; | |
69 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & | |
70 | ((u32)fdata->cnt_index << | |
71 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); | |
72 | } | |
73 | ||
74 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); | |
75 | fdir_desc->rsvd = cpu_to_le32(0); | |
76 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); | |
77 | fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); | |
78 | } | |
79 | ||
49d7d933 | 80 | #define I40E_FD_CLEAN_DELAY 10 |
fd0a05ce JB |
81 | /** |
82 | * i40e_program_fdir_filter - Program a Flow Director filter | |
17a73f6b JG |
83 | * @fdir_data: Packet data that will be filter parameters |
84 | * @raw_packet: the pre-allocated packet buffer for FDir | |
b40c82e6 | 85 | * @pf: The PF pointer |
fd0a05ce JB |
86 | * @add: True for add/update, False for remove |
87 | **/ | |
1eb846ac AD |
88 | static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, |
89 | u8 *raw_packet, struct i40e_pf *pf, | |
90 | bool add) | |
fd0a05ce | 91 | { |
49d7d933 | 92 | struct i40e_tx_buffer *tx_buf, *first; |
fd0a05ce JB |
93 | struct i40e_tx_desc *tx_desc; |
94 | struct i40e_ring *tx_ring; | |
95 | struct i40e_vsi *vsi; | |
96 | struct device *dev; | |
97 | dma_addr_t dma; | |
98 | u32 td_cmd = 0; | |
99 | u16 i; | |
100 | ||
101 | /* find existing FDIR VSI */ | |
4b816446 | 102 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
fd0a05ce JB |
103 | if (!vsi) |
104 | return -ENOENT; | |
105 | ||
9f65e15b | 106 | tx_ring = vsi->tx_rings[0]; |
fd0a05ce JB |
107 | dev = tx_ring->dev; |
108 | ||
49d7d933 | 109 | /* we need two descriptors to add/del a filter and we can wait */ |
ed245406 AD |
110 | for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { |
111 | if (!i) | |
112 | return -EAGAIN; | |
49d7d933 | 113 | msleep_interruptible(1); |
ed245406 | 114 | } |
49d7d933 | 115 | |
17a73f6b JG |
116 | dma = dma_map_single(dev, raw_packet, |
117 | I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); | |
fd0a05ce JB |
118 | if (dma_mapping_error(dev, dma)) |
119 | goto dma_fail; | |
120 | ||
121 | /* grab the next descriptor */ | |
fc4ac67b | 122 | i = tx_ring->next_to_use; |
49d7d933 | 123 | first = &tx_ring->tx_bi[i]; |
5e02f283 | 124 | i40e_fdir(tx_ring, fdir_data, add); |
fd0a05ce JB |
125 | |
126 | /* Now program a dummy descriptor */ | |
fc4ac67b AD |
127 | i = tx_ring->next_to_use; |
128 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
298deef1 | 129 | tx_buf = &tx_ring->tx_bi[i]; |
fc4ac67b | 130 | |
49d7d933 ASJ |
131 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
132 | ||
133 | memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); | |
fd0a05ce | 134 | |
298deef1 | 135 | /* record length, and DMA address */ |
17a73f6b | 136 | dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); |
298deef1 ASJ |
137 | dma_unmap_addr_set(tx_buf, dma, dma); |
138 | ||
fd0a05ce | 139 | tx_desc->buffer_addr = cpu_to_le64(dma); |
eaefbd06 | 140 | td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; |
fd0a05ce | 141 | |
49d7d933 ASJ |
142 | tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; |
143 | tx_buf->raw_buf = (void *)raw_packet; | |
144 | ||
fd0a05ce | 145 | tx_desc->cmd_type_offset_bsz = |
17a73f6b | 146 | build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); |
fd0a05ce | 147 | |
fd0a05ce | 148 | /* Force memory writes to complete before letting h/w |
49d7d933 | 149 | * know there are new descriptors to fetch. |
fd0a05ce JB |
150 | */ |
151 | wmb(); | |
152 | ||
fc4ac67b | 153 | /* Mark the data descriptor to be watched */ |
49d7d933 | 154 | first->next_to_watch = tx_desc; |
fc4ac67b | 155 | |
fd0a05ce JB |
156 | writel(tx_ring->next_to_use, tx_ring->tail); |
157 | return 0; | |
158 | ||
159 | dma_fail: | |
160 | return -1; | |
161 | } | |
162 | ||
17a73f6b JG |
163 | #define IP_HEADER_OFFSET 14 |
164 | #define I40E_UDPIP_DUMMY_PACKET_LEN 42 | |
165 | /** | |
166 | * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters | |
167 | * @vsi: pointer to the targeted VSI | |
168 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
169 | * @add: true adds a filter, false removes it |
170 | * | |
171 | * Returns 0 if the filters were successfully added or removed | |
172 | **/ | |
173 | static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, | |
174 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 175 | bool add) |
17a73f6b JG |
176 | { |
177 | struct i40e_pf *pf = vsi->back; | |
178 | struct udphdr *udp; | |
179 | struct iphdr *ip; | |
49d7d933 | 180 | u8 *raw_packet; |
17a73f6b | 181 | int ret; |
17a73f6b JG |
182 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, |
183 | 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, | |
184 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
185 | ||
49d7d933 ASJ |
186 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
187 | if (!raw_packet) | |
188 | return -ENOMEM; | |
17a73f6b JG |
189 | memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); |
190 | ||
191 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
192 | udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET | |
193 | + sizeof(struct iphdr)); | |
194 | ||
8ce43dce | 195 | ip->daddr = fd_data->dst_ip; |
17a73f6b | 196 | udp->dest = fd_data->dst_port; |
8ce43dce | 197 | ip->saddr = fd_data->src_ip; |
17a73f6b JG |
198 | udp->source = fd_data->src_port; |
199 | ||
0e588de1 JK |
200 | if (fd_data->flex_filter) { |
201 | u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN; | |
202 | __be16 pattern = fd_data->flex_word; | |
203 | u16 off = fd_data->flex_offset; | |
204 | ||
205 | *((__force __be16 *)(payload + off)) = pattern; | |
206 | } | |
207 | ||
b2d36c03 KS |
208 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; |
209 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
210 | if (ret) { | |
211 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
212 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
213 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
214 | /* Free the packet buffer since it wasn't added to the ring */ |
215 | kfree(raw_packet); | |
216 | return -EOPNOTSUPP; | |
4205d379 | 217 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
218 | if (add) |
219 | dev_info(&pf->pdev->dev, | |
220 | "Filter OK for PCTYPE %d loc = %d\n", | |
221 | fd_data->pctype, fd_data->fd_id); | |
222 | else | |
223 | dev_info(&pf->pdev->dev, | |
224 | "Filter deleted for PCTYPE %d loc = %d\n", | |
225 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b | 226 | } |
a42e7a36 | 227 | |
097dbf52 JK |
228 | if (add) |
229 | pf->fd_udp4_filter_cnt++; | |
230 | else | |
231 | pf->fd_udp4_filter_cnt--; | |
232 | ||
e5187ee3 | 233 | return 0; |
17a73f6b JG |
234 | } |
235 | ||
236 | #define I40E_TCPIP_DUMMY_PACKET_LEN 54 | |
237 | /** | |
238 | * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters | |
239 | * @vsi: pointer to the targeted VSI | |
240 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
241 | * @add: true adds a filter, false removes it |
242 | * | |
243 | * Returns 0 if the filters were successfully added or removed | |
244 | **/ | |
245 | static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, | |
246 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 247 | bool add) |
17a73f6b JG |
248 | { |
249 | struct i40e_pf *pf = vsi->back; | |
250 | struct tcphdr *tcp; | |
251 | struct iphdr *ip; | |
49d7d933 | 252 | u8 *raw_packet; |
17a73f6b JG |
253 | int ret; |
254 | /* Dummy packet */ | |
255 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
256 | 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, | |
257 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, | |
258 | 0x0, 0x72, 0, 0, 0, 0}; | |
259 | ||
49d7d933 ASJ |
260 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
261 | if (!raw_packet) | |
262 | return -ENOMEM; | |
17a73f6b JG |
263 | memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); |
264 | ||
265 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
266 | tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET | |
267 | + sizeof(struct iphdr)); | |
268 | ||
8ce43dce | 269 | ip->daddr = fd_data->dst_ip; |
17a73f6b | 270 | tcp->dest = fd_data->dst_port; |
8ce43dce | 271 | ip->saddr = fd_data->src_ip; |
17a73f6b JG |
272 | tcp->source = fd_data->src_port; |
273 | ||
0e588de1 JK |
274 | if (fd_data->flex_filter) { |
275 | u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN; | |
276 | __be16 pattern = fd_data->flex_word; | |
277 | u16 off = fd_data->flex_offset; | |
278 | ||
279 | *((__force __be16 *)(payload + off)) = pattern; | |
280 | } | |
281 | ||
b2d36c03 | 282 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; |
17a73f6b | 283 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); |
17a73f6b JG |
284 | if (ret) { |
285 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
286 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
287 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
288 | /* Free the packet buffer since it wasn't added to the ring */ |
289 | kfree(raw_packet); | |
290 | return -EOPNOTSUPP; | |
4205d379 | 291 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
292 | if (add) |
293 | dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", | |
294 | fd_data->pctype, fd_data->fd_id); | |
295 | else | |
296 | dev_info(&pf->pdev->dev, | |
297 | "Filter deleted for PCTYPE %d loc = %d\n", | |
298 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
299 | } |
300 | ||
377cc249 | 301 | if (add) { |
097dbf52 | 302 | pf->fd_tcp4_filter_cnt++; |
377cc249 JK |
303 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
304 | I40E_DEBUG_FD & pf->hw.debug_mask) | |
305 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); | |
134201ae | 306 | set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); |
377cc249 | 307 | } else { |
097dbf52 | 308 | pf->fd_tcp4_filter_cnt--; |
377cc249 JK |
309 | } |
310 | ||
e5187ee3 | 311 | return 0; |
17a73f6b JG |
312 | } |
313 | ||
f223c875 JK |
314 | #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 |
315 | /** | |
316 | * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for | |
317 | * a specific flow spec | |
318 | * @vsi: pointer to the targeted VSI | |
319 | * @fd_data: the flow director data required for the FDir descriptor | |
320 | * @add: true adds a filter, false removes it | |
321 | * | |
322 | * Returns 0 if the filters were successfully added or removed | |
323 | **/ | |
324 | static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, | |
325 | struct i40e_fdir_filter *fd_data, | |
326 | bool add) | |
327 | { | |
328 | struct i40e_pf *pf = vsi->back; | |
329 | struct sctphdr *sctp; | |
330 | struct iphdr *ip; | |
331 | u8 *raw_packet; | |
332 | int ret; | |
333 | /* Dummy packet */ | |
334 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
335 | 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0, | |
336 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
337 | ||
338 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); | |
339 | if (!raw_packet) | |
340 | return -ENOMEM; | |
341 | memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN); | |
342 | ||
343 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
344 | sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET | |
345 | + sizeof(struct iphdr)); | |
346 | ||
347 | ip->daddr = fd_data->dst_ip; | |
348 | sctp->dest = fd_data->dst_port; | |
349 | ip->saddr = fd_data->src_ip; | |
350 | sctp->source = fd_data->src_port; | |
351 | ||
352 | if (fd_data->flex_filter) { | |
353 | u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN; | |
354 | __be16 pattern = fd_data->flex_word; | |
355 | u16 off = fd_data->flex_offset; | |
356 | ||
357 | *((__force __be16 *)(payload + off)) = pattern; | |
358 | } | |
359 | ||
360 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; | |
361 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
362 | if (ret) { | |
363 | dev_info(&pf->pdev->dev, | |
364 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", | |
365 | fd_data->pctype, fd_data->fd_id, ret); | |
366 | /* Free the packet buffer since it wasn't added to the ring */ | |
367 | kfree(raw_packet); | |
368 | return -EOPNOTSUPP; | |
369 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { | |
370 | if (add) | |
371 | dev_info(&pf->pdev->dev, | |
372 | "Filter OK for PCTYPE %d loc = %d\n", | |
373 | fd_data->pctype, fd_data->fd_id); | |
374 | else | |
375 | dev_info(&pf->pdev->dev, | |
376 | "Filter deleted for PCTYPE %d loc = %d\n", | |
377 | fd_data->pctype, fd_data->fd_id); | |
378 | } | |
379 | ||
380 | if (add) | |
381 | pf->fd_sctp4_filter_cnt++; | |
382 | else | |
383 | pf->fd_sctp4_filter_cnt--; | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
17a73f6b JG |
388 | #define I40E_IP_DUMMY_PACKET_LEN 34 |
389 | /** | |
390 | * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for | |
391 | * a specific flow spec | |
392 | * @vsi: pointer to the targeted VSI | |
393 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
394 | * @add: true adds a filter, false removes it |
395 | * | |
396 | * Returns 0 if the filters were successfully added or removed | |
397 | **/ | |
398 | static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, | |
399 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 400 | bool add) |
17a73f6b JG |
401 | { |
402 | struct i40e_pf *pf = vsi->back; | |
403 | struct iphdr *ip; | |
49d7d933 | 404 | u8 *raw_packet; |
17a73f6b JG |
405 | int ret; |
406 | int i; | |
407 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
408 | 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, | |
409 | 0, 0, 0, 0}; | |
410 | ||
17a73f6b JG |
411 | for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; |
412 | i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { | |
49d7d933 ASJ |
413 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
414 | if (!raw_packet) | |
415 | return -ENOMEM; | |
416 | memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); | |
417 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
418 | ||
8ce43dce JK |
419 | ip->saddr = fd_data->src_ip; |
420 | ip->daddr = fd_data->dst_ip; | |
49d7d933 ASJ |
421 | ip->protocol = 0; |
422 | ||
0e588de1 JK |
423 | if (fd_data->flex_filter) { |
424 | u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN; | |
425 | __be16 pattern = fd_data->flex_word; | |
426 | u16 off = fd_data->flex_offset; | |
427 | ||
428 | *((__force __be16 *)(payload + off)) = pattern; | |
429 | } | |
430 | ||
17a73f6b JG |
431 | fd_data->pctype = i; |
432 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
17a73f6b JG |
433 | if (ret) { |
434 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
435 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
436 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
437 | /* The packet buffer wasn't added to the ring so we |
438 | * need to free it now. | |
439 | */ | |
440 | kfree(raw_packet); | |
441 | return -EOPNOTSUPP; | |
4205d379 | 442 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
443 | if (add) |
444 | dev_info(&pf->pdev->dev, | |
445 | "Filter OK for PCTYPE %d loc = %d\n", | |
446 | fd_data->pctype, fd_data->fd_id); | |
447 | else | |
448 | dev_info(&pf->pdev->dev, | |
449 | "Filter deleted for PCTYPE %d loc = %d\n", | |
450 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
451 | } |
452 | } | |
453 | ||
097dbf52 JK |
454 | if (add) |
455 | pf->fd_ip4_filter_cnt++; | |
456 | else | |
457 | pf->fd_ip4_filter_cnt--; | |
458 | ||
e5187ee3 | 459 | return 0; |
17a73f6b JG |
460 | } |
461 | ||
462 | /** | |
463 | * i40e_add_del_fdir - Build raw packets to add/del fdir filter | |
464 | * @vsi: pointer to the targeted VSI | |
f5254429 | 465 | * @input: filter to add or delete |
17a73f6b JG |
466 | * @add: true adds a filter, false removes it |
467 | * | |
468 | **/ | |
469 | int i40e_add_del_fdir(struct i40e_vsi *vsi, | |
470 | struct i40e_fdir_filter *input, bool add) | |
471 | { | |
472 | struct i40e_pf *pf = vsi->back; | |
17a73f6b JG |
473 | int ret; |
474 | ||
17a73f6b JG |
475 | switch (input->flow_type & ~FLOW_EXT) { |
476 | case TCP_V4_FLOW: | |
49d7d933 | 477 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
478 | break; |
479 | case UDP_V4_FLOW: | |
49d7d933 | 480 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 481 | break; |
f223c875 JK |
482 | case SCTP_V4_FLOW: |
483 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); | |
484 | break; | |
17a73f6b JG |
485 | case IP_USER_FLOW: |
486 | switch (input->ip4_proto) { | |
487 | case IPPROTO_TCP: | |
49d7d933 | 488 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
489 | break; |
490 | case IPPROTO_UDP: | |
49d7d933 | 491 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 492 | break; |
f223c875 JK |
493 | case IPPROTO_SCTP: |
494 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); | |
495 | break; | |
e1da71ca | 496 | case IPPROTO_IP: |
49d7d933 | 497 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b | 498 | break; |
e1da71ca AD |
499 | default: |
500 | /* We cannot support masking based on protocol */ | |
a346fb83 JK |
501 | dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n", |
502 | input->ip4_proto); | |
503 | return -EINVAL; | |
17a73f6b JG |
504 | } |
505 | break; | |
506 | default: | |
a346fb83 | 507 | dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n", |
17a73f6b | 508 | input->flow_type); |
a346fb83 | 509 | return -EINVAL; |
17a73f6b JG |
510 | } |
511 | ||
a158aeaf JK |
512 | /* The buffer allocated here will be normally be freed by |
513 | * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit | |
514 | * completion. In the event of an error adding the buffer to the FDIR | |
515 | * ring, it will immediately be freed. It may also be freed by | |
516 | * i40e_clean_tx_ring() when closing the VSI. | |
517 | */ | |
17a73f6b JG |
518 | return ret; |
519 | } | |
520 | ||
fd0a05ce JB |
521 | /** |
522 | * i40e_fd_handle_status - check the Programming Status for FD | |
523 | * @rx_ring: the Rx ring for this descriptor | |
55a5e60b | 524 | * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. |
fd0a05ce JB |
525 | * @prog_id: the id originally used for programming |
526 | * | |
527 | * This is used to verify if the FD programming or invalidation | |
528 | * requested by SW to the HW is successful or not and take actions accordingly. | |
529 | **/ | |
20a739db BT |
530 | void i40e_fd_handle_status(struct i40e_ring *rx_ring, |
531 | union i40e_rx_desc *rx_desc, u8 prog_id) | |
fd0a05ce | 532 | { |
55a5e60b ASJ |
533 | struct i40e_pf *pf = rx_ring->vsi->back; |
534 | struct pci_dev *pdev = pf->pdev; | |
535 | u32 fcnt_prog, fcnt_avail; | |
fd0a05ce | 536 | u32 error; |
55a5e60b | 537 | u64 qw; |
fd0a05ce | 538 | |
55a5e60b | 539 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
fd0a05ce JB |
540 | error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> |
541 | I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; | |
542 | ||
41a1d04b | 543 | if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { |
3487b6c3 | 544 | pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); |
f7233c54 ASJ |
545 | if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || |
546 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
547 | dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", | |
3487b6c3 | 548 | pf->fd_inv); |
55a5e60b | 549 | |
04294e38 ASJ |
550 | /* Check if the programming error is for ATR. |
551 | * If so, auto disable ATR and set a state for | |
552 | * flush in progress. Next time we come here if flush is in | |
553 | * progress do nothing, once flush is complete the state will | |
554 | * be cleared. | |
555 | */ | |
0da36b97 | 556 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
04294e38 ASJ |
557 | return; |
558 | ||
1e1be8f6 ASJ |
559 | pf->fd_add_err++; |
560 | /* store the current atr filter count */ | |
561 | pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); | |
562 | ||
04294e38 | 563 | if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && |
134201ae JK |
564 | test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) { |
565 | /* These set_bit() calls aren't atomic with the | |
566 | * test_bit() here, but worse case we potentially | |
567 | * disable ATR and queue a flush right after SB | |
568 | * support is re-enabled. That shouldn't cause an | |
569 | * issue in practice | |
570 | */ | |
571 | set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); | |
0da36b97 | 572 | set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); |
04294e38 ASJ |
573 | } |
574 | ||
55a5e60b | 575 | /* filter programming failed most likely due to table full */ |
04294e38 | 576 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 577 | fcnt_avail = pf->fdir_pf_filter_count; |
55a5e60b ASJ |
578 | /* If ATR is running fcnt_prog can quickly change, |
579 | * if we are very close to full, it makes sense to disable | |
580 | * FD ATR/SB and then re-enable it when there is room. | |
581 | */ | |
582 | if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { | |
1e1be8f6 | 583 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
134201ae JK |
584 | !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED, |
585 | pf->state)) | |
2e4875e3 ASJ |
586 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
587 | dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); | |
55a5e60b | 588 | } |
41a1d04b | 589 | } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { |
13c2884f | 590 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
e99bdd39 | 591 | dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", |
13c2884f | 592 | rx_desc->wb.qword0.hi_dword.fd_id); |
55a5e60b | 593 | } |
fd0a05ce JB |
594 | } |
595 | ||
596 | /** | |
a5e9c572 | 597 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer |
fd0a05ce JB |
598 | * @ring: the ring that owns the buffer |
599 | * @tx_buffer: the buffer to free | |
600 | **/ | |
a5e9c572 AD |
601 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, |
602 | struct i40e_tx_buffer *tx_buffer) | |
fd0a05ce | 603 | { |
a5e9c572 | 604 | if (tx_buffer->skb) { |
64bfd68e AD |
605 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
606 | kfree(tx_buffer->raw_buf); | |
74608d17 | 607 | else if (ring_is_xdp(ring)) |
03993094 | 608 | xdp_return_frame(tx_buffer->xdpf); |
64bfd68e AD |
609 | else |
610 | dev_kfree_skb_any(tx_buffer->skb); | |
a5e9c572 | 611 | if (dma_unmap_len(tx_buffer, len)) |
fd0a05ce | 612 | dma_unmap_single(ring->dev, |
35a1e2ad AD |
613 | dma_unmap_addr(tx_buffer, dma), |
614 | dma_unmap_len(tx_buffer, len), | |
fd0a05ce | 615 | DMA_TO_DEVICE); |
a5e9c572 AD |
616 | } else if (dma_unmap_len(tx_buffer, len)) { |
617 | dma_unmap_page(ring->dev, | |
618 | dma_unmap_addr(tx_buffer, dma), | |
619 | dma_unmap_len(tx_buffer, len), | |
620 | DMA_TO_DEVICE); | |
fd0a05ce | 621 | } |
a42e7a36 | 622 | |
a5e9c572 AD |
623 | tx_buffer->next_to_watch = NULL; |
624 | tx_buffer->skb = NULL; | |
35a1e2ad | 625 | dma_unmap_len_set(tx_buffer, len, 0); |
a5e9c572 | 626 | /* tx_buffer must be completely set up in the transmit path */ |
fd0a05ce JB |
627 | } |
628 | ||
629 | /** | |
630 | * i40e_clean_tx_ring - Free any empty Tx buffers | |
631 | * @tx_ring: ring to be cleaned | |
632 | **/ | |
633 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring) | |
634 | { | |
fd0a05ce JB |
635 | unsigned long bi_size; |
636 | u16 i; | |
637 | ||
9dbb1370 BT |
638 | if (ring_is_xdp(tx_ring) && tx_ring->xsk_umem) { |
639 | i40e_xsk_clean_tx_ring(tx_ring); | |
640 | } else { | |
641 | /* ring already cleared, nothing to do */ | |
642 | if (!tx_ring->tx_bi) | |
643 | return; | |
fd0a05ce | 644 | |
9dbb1370 BT |
645 | /* Free all the Tx ring sk_buffs */ |
646 | for (i = 0; i < tx_ring->count; i++) | |
647 | i40e_unmap_and_free_tx_resource(tx_ring, | |
648 | &tx_ring->tx_bi[i]); | |
649 | } | |
fd0a05ce JB |
650 | |
651 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
652 | memset(tx_ring->tx_bi, 0, bi_size); | |
653 | ||
654 | /* Zero out the descriptor ring */ | |
655 | memset(tx_ring->desc, 0, tx_ring->size); | |
656 | ||
657 | tx_ring->next_to_use = 0; | |
658 | tx_ring->next_to_clean = 0; | |
7070ce0a AD |
659 | |
660 | if (!tx_ring->netdev) | |
661 | return; | |
662 | ||
663 | /* cleanup Tx queue statistics */ | |
e486bdfd | 664 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
fd0a05ce JB |
665 | } |
666 | ||
667 | /** | |
668 | * i40e_free_tx_resources - Free Tx resources per queue | |
669 | * @tx_ring: Tx descriptor ring for a specific queue | |
670 | * | |
671 | * Free all transmit software resources | |
672 | **/ | |
673 | void i40e_free_tx_resources(struct i40e_ring *tx_ring) | |
674 | { | |
675 | i40e_clean_tx_ring(tx_ring); | |
676 | kfree(tx_ring->tx_bi); | |
677 | tx_ring->tx_bi = NULL; | |
678 | ||
679 | if (tx_ring->desc) { | |
680 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
681 | tx_ring->desc, tx_ring->dma); | |
682 | tx_ring->desc = NULL; | |
683 | } | |
684 | } | |
685 | ||
686 | /** | |
687 | * i40e_get_tx_pending - how many tx descriptors not processed | |
f5254429 | 688 | * @ring: the ring of descriptors |
04d41051 | 689 | * @in_sw: use SW variables |
fd0a05ce JB |
690 | * |
691 | * Since there is no access to the ring head register | |
692 | * in XL710, we need to use our local copies | |
693 | **/ | |
04d41051 | 694 | u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
fd0a05ce | 695 | { |
a68de58d JB |
696 | u32 head, tail; |
697 | ||
04d41051 AB |
698 | if (!in_sw) { |
699 | head = i40e_get_head(ring); | |
700 | tail = readl(ring->tail); | |
701 | } else { | |
702 | head = ring->next_to_clean; | |
703 | tail = ring->next_to_use; | |
704 | } | |
a68de58d JB |
705 | |
706 | if (head != tail) | |
707 | return (head < tail) ? | |
708 | tail - head : (tail + ring->count - head); | |
709 | ||
710 | return 0; | |
fd0a05ce JB |
711 | } |
712 | ||
07d44190 SM |
713 | /** |
714 | * i40e_detect_recover_hung - Function to detect and recover hung_queues | |
715 | * @vsi: pointer to vsi struct with tx queues | |
716 | * | |
717 | * VSI has netdev and netdev has TX queues. This function is to check each of | |
718 | * those TX queues if they are hung, trigger recovery by issuing SW interrupt. | |
719 | **/ | |
720 | void i40e_detect_recover_hung(struct i40e_vsi *vsi) | |
721 | { | |
722 | struct i40e_ring *tx_ring = NULL; | |
723 | struct net_device *netdev; | |
724 | unsigned int i; | |
725 | int packets; | |
726 | ||
727 | if (!vsi) | |
728 | return; | |
729 | ||
730 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) | |
731 | return; | |
732 | ||
733 | netdev = vsi->netdev; | |
734 | if (!netdev) | |
735 | return; | |
736 | ||
737 | if (!netif_carrier_ok(netdev)) | |
738 | return; | |
739 | ||
740 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
741 | tx_ring = vsi->tx_rings[i]; | |
742 | if (tx_ring && tx_ring->desc) { | |
743 | /* If packet counter has not changed the queue is | |
744 | * likely stalled, so force an interrupt for this | |
745 | * queue. | |
746 | * | |
747 | * prev_pkt_ctr would be negative if there was no | |
748 | * pending work. | |
749 | */ | |
750 | packets = tx_ring->stats.packets & INT_MAX; | |
751 | if (tx_ring->tx_stats.prev_pkt_ctr == packets) { | |
752 | i40e_force_wb(vsi, tx_ring->q_vector); | |
753 | continue; | |
754 | } | |
755 | ||
756 | /* Memory barrier between read of packet count and call | |
757 | * to i40e_get_tx_pending() | |
758 | */ | |
759 | smp_rmb(); | |
760 | tx_ring->tx_stats.prev_pkt_ctr = | |
04d41051 | 761 | i40e_get_tx_pending(tx_ring, true) ? packets : -1; |
07d44190 SM |
762 | } |
763 | } | |
764 | } | |
765 | ||
fd0a05ce JB |
766 | /** |
767 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
768 | * @vsi: the VSI we care about |
769 | * @tx_ring: Tx ring to clean | |
770 | * @napi_budget: Used to determine if we are in netpoll | |
fd0a05ce JB |
771 | * |
772 | * Returns true if there's any budget left (e.g. the clean is finished) | |
773 | **/ | |
a619afe8 AD |
774 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
775 | struct i40e_ring *tx_ring, int napi_budget) | |
fd0a05ce | 776 | { |
97e42ef4 | 777 | int i = tx_ring->next_to_clean; |
fd0a05ce | 778 | struct i40e_tx_buffer *tx_buf; |
1943d8ba | 779 | struct i40e_tx_desc *tx_head; |
fd0a05ce | 780 | struct i40e_tx_desc *tx_desc; |
a619afe8 AD |
781 | unsigned int total_bytes = 0, total_packets = 0; |
782 | unsigned int budget = vsi->work_limit; | |
fd0a05ce JB |
783 | |
784 | tx_buf = &tx_ring->tx_bi[i]; | |
785 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
a5e9c572 | 786 | i -= tx_ring->count; |
fd0a05ce | 787 | |
1943d8ba JB |
788 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
789 | ||
a5e9c572 AD |
790 | do { |
791 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
fd0a05ce JB |
792 | |
793 | /* if next_to_watch is not set then there is no work pending */ | |
794 | if (!eop_desc) | |
795 | break; | |
796 | ||
a5e9c572 | 797 | /* prevent any other reads prior to eop_desc */ |
52c6912f | 798 | smp_rmb(); |
a5e9c572 | 799 | |
ed0980c4 | 800 | i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); |
1943d8ba JB |
801 | /* we have caught up to head, no work left to do */ |
802 | if (tx_head == tx_desc) | |
fd0a05ce JB |
803 | break; |
804 | ||
c304fdac | 805 | /* clear next_to_watch to prevent false hangs */ |
fd0a05ce | 806 | tx_buf->next_to_watch = NULL; |
fd0a05ce | 807 | |
a5e9c572 AD |
808 | /* update the statistics for this packet */ |
809 | total_bytes += tx_buf->bytecount; | |
810 | total_packets += tx_buf->gso_segs; | |
fd0a05ce | 811 | |
74608d17 BT |
812 | /* free the skb/XDP data */ |
813 | if (ring_is_xdp(tx_ring)) | |
03993094 | 814 | xdp_return_frame(tx_buf->xdpf); |
74608d17 BT |
815 | else |
816 | napi_consume_skb(tx_buf->skb, napi_budget); | |
fd0a05ce | 817 | |
a5e9c572 AD |
818 | /* unmap skb header data */ |
819 | dma_unmap_single(tx_ring->dev, | |
820 | dma_unmap_addr(tx_buf, dma), | |
821 | dma_unmap_len(tx_buf, len), | |
822 | DMA_TO_DEVICE); | |
fd0a05ce | 823 | |
a5e9c572 AD |
824 | /* clear tx_buffer data */ |
825 | tx_buf->skb = NULL; | |
826 | dma_unmap_len_set(tx_buf, len, 0); | |
fd0a05ce | 827 | |
a5e9c572 AD |
828 | /* unmap remaining buffers */ |
829 | while (tx_desc != eop_desc) { | |
ed0980c4 SP |
830 | i40e_trace(clean_tx_irq_unmap, |
831 | tx_ring, tx_desc, tx_buf); | |
fd0a05ce JB |
832 | |
833 | tx_buf++; | |
834 | tx_desc++; | |
835 | i++; | |
a5e9c572 AD |
836 | if (unlikely(!i)) { |
837 | i -= tx_ring->count; | |
fd0a05ce JB |
838 | tx_buf = tx_ring->tx_bi; |
839 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
840 | } | |
fd0a05ce | 841 | |
a5e9c572 AD |
842 | /* unmap any remaining paged data */ |
843 | if (dma_unmap_len(tx_buf, len)) { | |
844 | dma_unmap_page(tx_ring->dev, | |
845 | dma_unmap_addr(tx_buf, dma), | |
846 | dma_unmap_len(tx_buf, len), | |
847 | DMA_TO_DEVICE); | |
848 | dma_unmap_len_set(tx_buf, len, 0); | |
849 | } | |
850 | } | |
851 | ||
852 | /* move us one more past the eop_desc for start of next pkt */ | |
853 | tx_buf++; | |
854 | tx_desc++; | |
855 | i++; | |
856 | if (unlikely(!i)) { | |
857 | i -= tx_ring->count; | |
858 | tx_buf = tx_ring->tx_bi; | |
859 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
860 | } | |
861 | ||
016890b9 JB |
862 | prefetch(tx_desc); |
863 | ||
a5e9c572 AD |
864 | /* update budget accounting */ |
865 | budget--; | |
866 | } while (likely(budget)); | |
867 | ||
868 | i += tx_ring->count; | |
fd0a05ce | 869 | tx_ring->next_to_clean = i; |
a96e7472 MK |
870 | i40e_update_tx_stats(tx_ring, total_packets, total_bytes); |
871 | i40e_arm_wb(tx_ring, vsi, budget); | |
d91649f5 | 872 | |
74608d17 BT |
873 | if (ring_is_xdp(tx_ring)) |
874 | return !!budget; | |
875 | ||
e486bdfd AD |
876 | /* notify netdev of completed buffers */ |
877 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
7070ce0a AD |
878 | total_packets, total_bytes); |
879 | ||
b85c94b6 | 880 | #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) |
fd0a05ce JB |
881 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
882 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
883 | /* Make sure that anybody stopping the queue after this | |
884 | * sees the new next_to_clean. | |
885 | */ | |
886 | smp_mb(); | |
887 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
888 | tx_ring->queue_index) && | |
0da36b97 | 889 | !test_bit(__I40E_VSI_DOWN, vsi->state)) { |
fd0a05ce JB |
890 | netif_wake_subqueue(tx_ring->netdev, |
891 | tx_ring->queue_index); | |
892 | ++tx_ring->tx_stats.restart_queue; | |
893 | } | |
894 | } | |
895 | ||
d91649f5 JB |
896 | return !!budget; |
897 | } | |
898 | ||
899 | /** | |
ecc6a239 | 900 | * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
d91649f5 | 901 | * @vsi: the VSI we care about |
ecc6a239 | 902 | * @q_vector: the vector on which to enable writeback |
d91649f5 JB |
903 | * |
904 | **/ | |
ecc6a239 ASJ |
905 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
906 | struct i40e_q_vector *q_vector) | |
d91649f5 | 907 | { |
8e0764b4 | 908 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 909 | u32 val; |
8e0764b4 | 910 | |
ecc6a239 ASJ |
911 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
912 | return; | |
8e0764b4 | 913 | |
ecc6a239 ASJ |
914 | if (q_vector->arm_wb_state) |
915 | return; | |
8e0764b4 | 916 | |
ecc6a239 ASJ |
917 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { |
918 | val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | | |
919 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 920 | |
ecc6a239 | 921 | wr32(&vsi->back->hw, |
a3f9fb5e | 922 | I40E_PFINT_DYN_CTLN(q_vector->reg_idx), |
ecc6a239 ASJ |
923 | val); |
924 | } else { | |
925 | val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | | |
926 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 927 | |
ecc6a239 ASJ |
928 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); |
929 | } | |
930 | q_vector->arm_wb_state = true; | |
931 | } | |
932 | ||
933 | /** | |
934 | * i40e_force_wb - Issue SW Interrupt so HW does a wb | |
935 | * @vsi: the VSI we care about | |
936 | * @q_vector: the vector on which to force writeback | |
937 | * | |
938 | **/ | |
939 | void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
940 | { | |
941 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { | |
8e0764b4 ASJ |
942 | u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | |
943 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ | |
944 | I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | | |
945 | I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; | |
946 | /* allow 00 to be written to the index */ | |
947 | ||
948 | wr32(&vsi->back->hw, | |
a3f9fb5e | 949 | I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val); |
8e0764b4 ASJ |
950 | } else { |
951 | u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
952 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ | |
953 | I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | | |
954 | I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; | |
955 | /* allow 00 to be written to the index */ | |
956 | ||
957 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); | |
958 | } | |
fd0a05ce JB |
959 | } |
960 | ||
a0073a4b AD |
961 | static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector, |
962 | struct i40e_ring_container *rc) | |
963 | { | |
964 | return &q_vector->rx == rc; | |
965 | } | |
966 | ||
967 | static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector) | |
968 | { | |
969 | unsigned int divisor; | |
970 | ||
971 | switch (q_vector->vsi->back->hw.phy.link_info.link_speed) { | |
972 | case I40E_LINK_SPEED_40GB: | |
973 | divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024; | |
974 | break; | |
975 | case I40E_LINK_SPEED_25GB: | |
976 | case I40E_LINK_SPEED_20GB: | |
977 | divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512; | |
978 | break; | |
979 | default: | |
980 | case I40E_LINK_SPEED_10GB: | |
981 | divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256; | |
982 | break; | |
983 | case I40E_LINK_SPEED_1GB: | |
984 | case I40E_LINK_SPEED_100MB: | |
985 | divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32; | |
986 | break; | |
987 | } | |
988 | ||
989 | return divisor; | |
990 | } | |
991 | ||
fd0a05ce | 992 | /** |
a0073a4b AD |
993 | * i40e_update_itr - update the dynamic ITR value based on statistics |
994 | * @q_vector: structure containing interrupt and ring information | |
fd0a05ce JB |
995 | * @rc: structure containing ring performance data |
996 | * | |
a0073a4b AD |
997 | * Stores a new ITR value based on packets and byte |
998 | * counts during the last interrupt. The advantage of per interrupt | |
999 | * computation is faster updates and more accurate ITR for the current | |
1000 | * traffic pattern. Constants in this function were computed | |
1001 | * based on theoretical maximum wire speed and thresholds were set based | |
1002 | * on testing data as well as attempting to minimize response time | |
fd0a05ce JB |
1003 | * while increasing bulk throughput. |
1004 | **/ | |
a0073a4b AD |
1005 | static void i40e_update_itr(struct i40e_q_vector *q_vector, |
1006 | struct i40e_ring_container *rc) | |
fd0a05ce | 1007 | { |
a0073a4b AD |
1008 | unsigned int avg_wire_size, packets, bytes, itr; |
1009 | unsigned long next_update = jiffies; | |
fd0a05ce | 1010 | |
a0073a4b AD |
1011 | /* If we don't have any rings just leave ourselves set for maximum |
1012 | * possible latency so we take ourselves out of the equation. | |
1013 | */ | |
71dc3719 | 1014 | if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting)) |
a0073a4b | 1015 | return; |
71dc3719 | 1016 | |
a0073a4b AD |
1017 | /* For Rx we want to push the delay up and default to low latency. |
1018 | * for Tx we want to pull the delay down and default to high latency. | |
1019 | */ | |
1020 | itr = i40e_container_is_rx(q_vector, rc) ? | |
1021 | I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY : | |
1022 | I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY; | |
1023 | ||
1024 | /* If we didn't update within up to 1 - 2 jiffies we can assume | |
1025 | * that either packets are coming in so slow there hasn't been | |
1026 | * any work, or that there is so much work that NAPI is dealing | |
1027 | * with interrupt moderation and we don't need to do anything. | |
1028 | */ | |
1029 | if (time_after(next_update, rc->next_update)) | |
1030 | goto clear_counts; | |
1031 | ||
1032 | /* If itr_countdown is set it means we programmed an ITR within | |
1033 | * the last 4 interrupt cycles. This has a side effect of us | |
1034 | * potentially firing an early interrupt. In order to work around | |
1035 | * this we need to throw out any data received for a few | |
1036 | * interrupts following the update. | |
1037 | */ | |
1038 | if (q_vector->itr_countdown) { | |
1039 | itr = rc->target_itr; | |
1040 | goto clear_counts; | |
1041 | } | |
fd0a05ce | 1042 | |
a0073a4b AD |
1043 | packets = rc->total_packets; |
1044 | bytes = rc->total_bytes; | |
742c9875 | 1045 | |
a0073a4b AD |
1046 | if (i40e_container_is_rx(q_vector, rc)) { |
1047 | /* If Rx there are 1 to 4 packets and bytes are less than | |
1048 | * 9000 assume insufficient data to use bulk rate limiting | |
1049 | * approach unless Tx is already in bulk rate limiting. We | |
1050 | * are likely latency driven. | |
1051 | */ | |
1052 | if (packets && packets < 4 && bytes < 9000 && | |
1053 | (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) { | |
1054 | itr = I40E_ITR_ADAPTIVE_LATENCY; | |
1055 | goto adjust_by_size; | |
1056 | } | |
1057 | } else if (packets < 4) { | |
1058 | /* If we have Tx and Rx ITR maxed and Tx ITR is running in | |
1059 | * bulk mode and we are receiving 4 or fewer packets just | |
1060 | * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so | |
1061 | * that the Rx can relax. | |
1062 | */ | |
1063 | if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS && | |
1064 | (q_vector->rx.target_itr & I40E_ITR_MASK) == | |
1065 | I40E_ITR_ADAPTIVE_MAX_USECS) | |
1066 | goto clear_counts; | |
1067 | } else if (packets > 32) { | |
1068 | /* If we have processed over 32 packets in a single interrupt | |
1069 | * for Tx assume we need to switch over to "bulk" mode. | |
1070 | */ | |
1071 | rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY; | |
1072 | } | |
1073 | ||
1074 | /* We have no packets to actually measure against. This means | |
1075 | * either one of the other queues on this vector is active or | |
1076 | * we are a Tx queue doing TSO with too high of an interrupt rate. | |
1077 | * | |
1078 | * Between 4 and 56 we can assume that our current interrupt delay | |
1079 | * is only slightly too low. As such we should increase it by a small | |
1080 | * fixed amount. | |
742c9875 | 1081 | */ |
a0073a4b AD |
1082 | if (packets < 56) { |
1083 | itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC; | |
1084 | if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { | |
1085 | itr &= I40E_ITR_ADAPTIVE_LATENCY; | |
1086 | itr += I40E_ITR_ADAPTIVE_MAX_USECS; | |
1087 | } | |
1088 | goto clear_counts; | |
742c9875 JK |
1089 | } |
1090 | ||
a0073a4b AD |
1091 | if (packets <= 256) { |
1092 | itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr); | |
1093 | itr &= I40E_ITR_MASK; | |
1094 | ||
1095 | /* Between 56 and 112 is our "goldilocks" zone where we are | |
1096 | * working out "just right". Just report that our current | |
1097 | * ITR is good for us. | |
1098 | */ | |
1099 | if (packets <= 112) | |
1100 | goto clear_counts; | |
1101 | ||
1102 | /* If packet count is 128 or greater we are likely looking | |
1103 | * at a slight overrun of the delay we want. Try halving | |
1104 | * our delay to see if that will cut the number of packets | |
1105 | * in half per interrupt. | |
1106 | */ | |
1107 | itr /= 2; | |
1108 | itr &= I40E_ITR_MASK; | |
1109 | if (itr < I40E_ITR_ADAPTIVE_MIN_USECS) | |
1110 | itr = I40E_ITR_ADAPTIVE_MIN_USECS; | |
1111 | ||
1112 | goto clear_counts; | |
1113 | } | |
1114 | ||
1115 | /* The paths below assume we are dealing with a bulk ITR since | |
1116 | * number of packets is greater than 256. We are just going to have | |
1117 | * to compute a value and try to bring the count under control, | |
1118 | * though for smaller packet sizes there isn't much we can do as | |
1119 | * NAPI polling will likely be kicking in sooner rather than later. | |
1120 | */ | |
1121 | itr = I40E_ITR_ADAPTIVE_BULK; | |
1122 | ||
1123 | adjust_by_size: | |
1124 | /* If packet counts are 256 or greater we can assume we have a gross | |
1125 | * overestimation of what the rate should be. Instead of trying to fine | |
1126 | * tune it just use the formula below to try and dial in an exact value | |
1127 | * give the current packet size of the frame. | |
1128 | */ | |
1129 | avg_wire_size = bytes / packets; | |
1130 | ||
1131 | /* The following is a crude approximation of: | |
1132 | * wmem_default / (size + overhead) = desired_pkts_per_int | |
1133 | * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate | |
1134 | * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value | |
51cc6d9f | 1135 | * |
a0073a4b AD |
1136 | * Assuming wmem_default is 212992 and overhead is 640 bytes per |
1137 | * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the | |
1138 | * formula down to | |
1139 | * | |
1140 | * (170 * (size + 24)) / (size + 640) = ITR | |
1141 | * | |
1142 | * We first do some math on the packet size and then finally bitshift | |
1143 | * by 8 after rounding up. We also have to account for PCIe link speed | |
1144 | * difference as ITR scales based on this. | |
fd0a05ce | 1145 | */ |
a0073a4b AD |
1146 | if (avg_wire_size <= 60) { |
1147 | /* Start at 250k ints/sec */ | |
1148 | avg_wire_size = 4096; | |
1149 | } else if (avg_wire_size <= 380) { | |
1150 | /* 250K ints/sec to 60K ints/sec */ | |
1151 | avg_wire_size *= 40; | |
1152 | avg_wire_size += 1696; | |
1153 | } else if (avg_wire_size <= 1084) { | |
1154 | /* 60K ints/sec to 36K ints/sec */ | |
1155 | avg_wire_size *= 15; | |
1156 | avg_wire_size += 11452; | |
1157 | } else if (avg_wire_size <= 1980) { | |
1158 | /* 36K ints/sec to 30K ints/sec */ | |
1159 | avg_wire_size *= 5; | |
1160 | avg_wire_size += 22420; | |
1161 | } else { | |
1162 | /* plateau at a limit of 30K ints/sec */ | |
1163 | avg_wire_size = 32256; | |
fd0a05ce | 1164 | } |
c56625d5 | 1165 | |
a0073a4b AD |
1166 | /* If we are in low latency mode halve our delay which doubles the |
1167 | * rate to somewhere between 100K to 16K ints/sec | |
1168 | */ | |
1169 | if (itr & I40E_ITR_ADAPTIVE_LATENCY) | |
1170 | avg_wire_size /= 2; | |
fd0a05ce | 1171 | |
a0073a4b AD |
1172 | /* Resultant value is 256 times larger than it needs to be. This |
1173 | * gives us room to adjust the value as needed to either increase | |
1174 | * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. | |
1175 | * | |
1176 | * Use addition as we have already recorded the new latency flag | |
1177 | * for the ITR value. | |
1178 | */ | |
1179 | itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) * | |
1180 | I40E_ITR_ADAPTIVE_MIN_INC; | |
1181 | ||
1182 | if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { | |
1183 | itr &= I40E_ITR_ADAPTIVE_LATENCY; | |
1184 | itr += I40E_ITR_ADAPTIVE_MAX_USECS; | |
fd0a05ce JB |
1185 | } |
1186 | ||
a0073a4b AD |
1187 | clear_counts: |
1188 | /* write back value */ | |
1189 | rc->target_itr = itr; | |
1190 | ||
1191 | /* next update should occur within next jiffy */ | |
1192 | rc->next_update = next_update + 1; | |
1193 | ||
fd0a05ce JB |
1194 | rc->total_bytes = 0; |
1195 | rc->total_packets = 0; | |
1196 | } | |
1197 | ||
2b9478ff AD |
1198 | /** |
1199 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
1200 | * @rx_ring: rx descriptor ring to store buffers on | |
1201 | * @old_buff: donor buffer to have page reused | |
1202 | * | |
1203 | * Synchronizes page for reuse by the adapter | |
1204 | **/ | |
1205 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
1206 | struct i40e_rx_buffer *old_buff) | |
1207 | { | |
1208 | struct i40e_rx_buffer *new_buff; | |
1209 | u16 nta = rx_ring->next_to_alloc; | |
1210 | ||
1211 | new_buff = &rx_ring->rx_bi[nta]; | |
1212 | ||
1213 | /* update, and store next to alloc */ | |
1214 | nta++; | |
1215 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1216 | ||
1217 | /* transfer page from old buffer to new buffer */ | |
1218 | new_buff->dma = old_buff->dma; | |
1219 | new_buff->page = old_buff->page; | |
1220 | new_buff->page_offset = old_buff->page_offset; | |
1221 | new_buff->pagecnt_bias = old_buff->pagecnt_bias; | |
6d7aad1d BT |
1222 | |
1223 | rx_ring->rx_stats.page_reuse_count++; | |
1224 | ||
1225 | /* clear contents of buffer_info */ | |
1226 | old_buff->page = NULL; | |
2b9478ff AD |
1227 | } |
1228 | ||
0e626ff7 AD |
1229 | /** |
1230 | * i40e_rx_is_programming_status - check for programming status descriptor | |
1231 | * @qw: qword representing status_error_len in CPU ordering | |
1232 | * | |
1233 | * The value of in the descriptor length field indicate if this | |
1234 | * is a programming status descriptor for flow director or FCoE | |
1235 | * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise | |
1236 | * it is a packet descriptor. | |
1237 | **/ | |
1238 | static inline bool i40e_rx_is_programming_status(u64 qw) | |
1239 | { | |
1240 | /* The Rx filter programming status and SPH bit occupy the same | |
1241 | * spot in the descriptor. Since we don't support packet split we | |
1242 | * can just reuse the bit as an indication that this is a | |
1243 | * programming status descriptor. | |
1244 | */ | |
1245 | return qw & I40E_RXD_QW1_LENGTH_SPH_MASK; | |
1246 | } | |
1247 | ||
fd0a05ce | 1248 | /** |
6d7aad1d | 1249 | * i40e_clean_programming_status - try clean the programming status descriptor |
fd0a05ce JB |
1250 | * @rx_ring: the rx ring that has this descriptor |
1251 | * @rx_desc: the rx descriptor written back by HW | |
0e626ff7 | 1252 | * @qw: qword representing status_error_len in CPU ordering |
fd0a05ce JB |
1253 | * |
1254 | * Flow director should handle FD_FILTER_STATUS to check its filter programming | |
1255 | * status being successful or not and take actions accordingly. FCoE should | |
1256 | * handle its context/filter programming/invalidation status and take actions. | |
1257 | * | |
6d7aad1d | 1258 | * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL. |
fd0a05ce | 1259 | **/ |
20a739db | 1260 | struct i40e_rx_buffer *i40e_clean_programming_status( |
6d7aad1d BT |
1261 | struct i40e_ring *rx_ring, |
1262 | union i40e_rx_desc *rx_desc, | |
1263 | u64 qw) | |
fd0a05ce | 1264 | { |
2b9478ff | 1265 | struct i40e_rx_buffer *rx_buffer; |
6d7aad1d | 1266 | u32 ntc; |
fd0a05ce JB |
1267 | u8 id; |
1268 | ||
6d7aad1d BT |
1269 | if (!i40e_rx_is_programming_status(qw)) |
1270 | return NULL; | |
1271 | ||
1272 | ntc = rx_ring->next_to_clean; | |
1273 | ||
0e626ff7 | 1274 | /* fetch, update, and store next to clean */ |
2b9478ff | 1275 | rx_buffer = &rx_ring->rx_bi[ntc++]; |
0e626ff7 AD |
1276 | ntc = (ntc < rx_ring->count) ? ntc : 0; |
1277 | rx_ring->next_to_clean = ntc; | |
1278 | ||
1279 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1280 | ||
fd0a05ce JB |
1281 | id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> |
1282 | I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; | |
1283 | ||
1284 | if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) | |
55a5e60b | 1285 | i40e_fd_handle_status(rx_ring, rx_desc, id); |
6d7aad1d BT |
1286 | |
1287 | return rx_buffer; | |
fd0a05ce JB |
1288 | } |
1289 | ||
1290 | /** | |
1291 | * i40e_setup_tx_descriptors - Allocate the Tx descriptors | |
1292 | * @tx_ring: the tx ring to set up | |
1293 | * | |
1294 | * Return 0 on success, negative on error | |
1295 | **/ | |
1296 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
1297 | { | |
1298 | struct device *dev = tx_ring->dev; | |
1299 | int bi_size; | |
1300 | ||
1301 | if (!dev) | |
1302 | return -ENOMEM; | |
1303 | ||
e908f815 JB |
1304 | /* warn if we are about to overwrite the pointer */ |
1305 | WARN_ON(tx_ring->tx_bi); | |
fd0a05ce JB |
1306 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
1307 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1308 | if (!tx_ring->tx_bi) | |
1309 | goto err; | |
1310 | ||
7d6d0677 FF |
1311 | u64_stats_init(&tx_ring->syncp); |
1312 | ||
fd0a05ce JB |
1313 | /* round up to nearest 4K */ |
1314 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
1315 | /* add u32 for head writeback, align after this takes care of |
1316 | * guaranteeing this is at least one cache line in size | |
1317 | */ | |
1318 | tx_ring->size += sizeof(u32); | |
fd0a05ce JB |
1319 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1320 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
1321 | &tx_ring->dma, GFP_KERNEL); | |
1322 | if (!tx_ring->desc) { | |
1323 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
1324 | tx_ring->size); | |
1325 | goto err; | |
1326 | } | |
1327 | ||
1328 | tx_ring->next_to_use = 0; | |
1329 | tx_ring->next_to_clean = 0; | |
07d44190 | 1330 | tx_ring->tx_stats.prev_pkt_ctr = -1; |
fd0a05ce JB |
1331 | return 0; |
1332 | ||
1333 | err: | |
1334 | kfree(tx_ring->tx_bi); | |
1335 | tx_ring->tx_bi = NULL; | |
1336 | return -ENOMEM; | |
1337 | } | |
1338 | ||
1339 | /** | |
1340 | * i40e_clean_rx_ring - Free Rx buffers | |
1341 | * @rx_ring: ring to be cleaned | |
1342 | **/ | |
1343 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring) | |
1344 | { | |
fd0a05ce JB |
1345 | unsigned long bi_size; |
1346 | u16 i; | |
1347 | ||
1348 | /* ring already cleared, nothing to do */ | |
1349 | if (!rx_ring->rx_bi) | |
1350 | return; | |
1351 | ||
e72e5659 SP |
1352 | if (rx_ring->skb) { |
1353 | dev_kfree_skb(rx_ring->skb); | |
1354 | rx_ring->skb = NULL; | |
1355 | } | |
1356 | ||
411dc16f BT |
1357 | if (rx_ring->xsk_umem) { |
1358 | i40e_xsk_clean_rx_ring(rx_ring); | |
0a714186 | 1359 | goto skip_free; |
411dc16f | 1360 | } |
0a714186 | 1361 | |
fd0a05ce JB |
1362 | /* Free all the Rx ring sk_buffs */ |
1363 | for (i = 0; i < rx_ring->count; i++) { | |
1a557afc JB |
1364 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
1365 | ||
1a557afc JB |
1366 | if (!rx_bi->page) |
1367 | continue; | |
1368 | ||
59605bc0 AD |
1369 | /* Invalidate cache lines that may have been written to by |
1370 | * device so that we avoid corrupting memory. | |
1371 | */ | |
1372 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1373 | rx_bi->dma, | |
1374 | rx_bi->page_offset, | |
98efd694 | 1375 | rx_ring->rx_buf_len, |
59605bc0 AD |
1376 | DMA_FROM_DEVICE); |
1377 | ||
1378 | /* free resources associated with mapping */ | |
1379 | dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, | |
98efd694 | 1380 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
1381 | DMA_FROM_DEVICE, |
1382 | I40E_RX_DMA_ATTR); | |
98efd694 | 1383 | |
1793668c | 1384 | __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); |
1a557afc JB |
1385 | |
1386 | rx_bi->page = NULL; | |
1387 | rx_bi->page_offset = 0; | |
fd0a05ce JB |
1388 | } |
1389 | ||
0a714186 | 1390 | skip_free: |
fd0a05ce JB |
1391 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
1392 | memset(rx_ring->rx_bi, 0, bi_size); | |
1393 | ||
1394 | /* Zero out the descriptor ring */ | |
1395 | memset(rx_ring->desc, 0, rx_ring->size); | |
1396 | ||
1a557afc | 1397 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1398 | rx_ring->next_to_clean = 0; |
1399 | rx_ring->next_to_use = 0; | |
1400 | } | |
1401 | ||
1402 | /** | |
1403 | * i40e_free_rx_resources - Free Rx resources | |
1404 | * @rx_ring: ring to clean the resources from | |
1405 | * | |
1406 | * Free all receive software resources | |
1407 | **/ | |
1408 | void i40e_free_rx_resources(struct i40e_ring *rx_ring) | |
1409 | { | |
1410 | i40e_clean_rx_ring(rx_ring); | |
87128824 JDB |
1411 | if (rx_ring->vsi->type == I40E_VSI_MAIN) |
1412 | xdp_rxq_info_unreg(&rx_ring->xdp_rxq); | |
0c8493d9 | 1413 | rx_ring->xdp_prog = NULL; |
fd0a05ce JB |
1414 | kfree(rx_ring->rx_bi); |
1415 | rx_ring->rx_bi = NULL; | |
1416 | ||
1417 | if (rx_ring->desc) { | |
1418 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
1419 | rx_ring->desc, rx_ring->dma); | |
1420 | rx_ring->desc = NULL; | |
1421 | } | |
1422 | } | |
1423 | ||
1424 | /** | |
1425 | * i40e_setup_rx_descriptors - Allocate Rx descriptors | |
1426 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
1427 | * | |
1428 | * Returns 0 on success, negative on failure | |
1429 | **/ | |
1430 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
1431 | { | |
1432 | struct device *dev = rx_ring->dev; | |
87128824 | 1433 | int err = -ENOMEM; |
fd0a05ce JB |
1434 | int bi_size; |
1435 | ||
e908f815 JB |
1436 | /* warn if we are about to overwrite the pointer */ |
1437 | WARN_ON(rx_ring->rx_bi); | |
fd0a05ce JB |
1438 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
1439 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1440 | if (!rx_ring->rx_bi) | |
1441 | goto err; | |
1442 | ||
f217d6ca | 1443 | u64_stats_init(&rx_ring->syncp); |
638702bd | 1444 | |
fd0a05ce | 1445 | /* Round up to nearest 4K */ |
1a557afc | 1446 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
fd0a05ce JB |
1447 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
1448 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
1449 | &rx_ring->dma, GFP_KERNEL); | |
1450 | ||
1451 | if (!rx_ring->desc) { | |
1452 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
1453 | rx_ring->size); | |
1454 | goto err; | |
1455 | } | |
1456 | ||
1a557afc | 1457 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1458 | rx_ring->next_to_clean = 0; |
1459 | rx_ring->next_to_use = 0; | |
1460 | ||
87128824 JDB |
1461 | /* XDP RX-queue info only needed for RX rings exposed to XDP */ |
1462 | if (rx_ring->vsi->type == I40E_VSI_MAIN) { | |
1463 | err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, | |
1464 | rx_ring->queue_index); | |
1465 | if (err < 0) | |
1466 | goto err; | |
1467 | } | |
1468 | ||
0c8493d9 BT |
1469 | rx_ring->xdp_prog = rx_ring->vsi->xdp_prog; |
1470 | ||
fd0a05ce JB |
1471 | return 0; |
1472 | err: | |
1473 | kfree(rx_ring->rx_bi); | |
1474 | rx_ring->rx_bi = NULL; | |
87128824 | 1475 | return err; |
fd0a05ce JB |
1476 | } |
1477 | ||
1478 | /** | |
1479 | * i40e_release_rx_desc - Store the new tail and head values | |
1480 | * @rx_ring: ring to bump | |
1481 | * @val: new head index | |
1482 | **/ | |
20a739db | 1483 | void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) |
fd0a05ce JB |
1484 | { |
1485 | rx_ring->next_to_use = val; | |
1a557afc JB |
1486 | |
1487 | /* update next to alloc since we have filled the ring */ | |
1488 | rx_ring->next_to_alloc = val; | |
1489 | ||
fd0a05ce JB |
1490 | /* Force memory writes to complete before letting h/w |
1491 | * know there are new descriptors to fetch. (Only | |
1492 | * applicable for weak-ordered memory model archs, | |
1493 | * such as IA-64). | |
1494 | */ | |
1495 | wmb(); | |
1496 | writel(val, rx_ring->tail); | |
1497 | } | |
1498 | ||
ca9ec088 AD |
1499 | /** |
1500 | * i40e_rx_offset - Return expected offset into page to access data | |
1501 | * @rx_ring: Ring we are requesting offset of | |
1502 | * | |
1503 | * Returns the offset value for ring into the data buffer. | |
1504 | */ | |
1505 | static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring) | |
1506 | { | |
1507 | return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0; | |
1508 | } | |
1509 | ||
fd0a05ce | 1510 | /** |
1a557afc JB |
1511 | * i40e_alloc_mapped_page - recycle or make a new page |
1512 | * @rx_ring: ring to use | |
1513 | * @bi: rx_buffer struct to modify | |
c2e245ab | 1514 | * |
1a557afc JB |
1515 | * Returns true if the page was successfully allocated or |
1516 | * reused. | |
fd0a05ce | 1517 | **/ |
1a557afc JB |
1518 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
1519 | struct i40e_rx_buffer *bi) | |
a132af24 | 1520 | { |
1a557afc JB |
1521 | struct page *page = bi->page; |
1522 | dma_addr_t dma; | |
a132af24 | 1523 | |
1a557afc JB |
1524 | /* since we are recycling buffers we should seldom need to alloc */ |
1525 | if (likely(page)) { | |
1526 | rx_ring->rx_stats.page_reuse_count++; | |
1527 | return true; | |
1528 | } | |
a132af24 | 1529 | |
1a557afc | 1530 | /* alloc new page for storage */ |
98efd694 | 1531 | page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); |
1a557afc JB |
1532 | if (unlikely(!page)) { |
1533 | rx_ring->rx_stats.alloc_page_failed++; | |
1534 | return false; | |
1535 | } | |
a132af24 | 1536 | |
1a557afc | 1537 | /* map page for use */ |
59605bc0 | 1538 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
98efd694 | 1539 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
1540 | DMA_FROM_DEVICE, |
1541 | I40E_RX_DMA_ATTR); | |
f16704e5 | 1542 | |
1a557afc JB |
1543 | /* if mapping failed free memory back to system since |
1544 | * there isn't much point in holding memory we can't use | |
f16704e5 | 1545 | */ |
1a557afc | 1546 | if (dma_mapping_error(rx_ring->dev, dma)) { |
98efd694 | 1547 | __free_pages(page, i40e_rx_pg_order(rx_ring)); |
1a557afc JB |
1548 | rx_ring->rx_stats.alloc_page_failed++; |
1549 | return false; | |
a132af24 MW |
1550 | } |
1551 | ||
1a557afc JB |
1552 | bi->dma = dma; |
1553 | bi->page = page; | |
ca9ec088 | 1554 | bi->page_offset = i40e_rx_offset(rx_ring); |
8ce29c67 BT |
1555 | page_ref_add(page, USHRT_MAX - 1); |
1556 | bi->pagecnt_bias = USHRT_MAX; | |
c2e245ab | 1557 | |
1a557afc JB |
1558 | return true; |
1559 | } | |
c2e245ab | 1560 | |
a132af24 | 1561 | /** |
1a557afc | 1562 | * i40e_alloc_rx_buffers - Replace used receive buffers |
a132af24 MW |
1563 | * @rx_ring: ring to place buffers on |
1564 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 1565 | * |
1a557afc | 1566 | * Returns false if all allocations were successful, true if any fail |
a132af24 | 1567 | **/ |
1a557afc | 1568 | bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
fd0a05ce | 1569 | { |
1a557afc | 1570 | u16 ntu = rx_ring->next_to_use; |
fd0a05ce JB |
1571 | union i40e_rx_desc *rx_desc; |
1572 | struct i40e_rx_buffer *bi; | |
fd0a05ce JB |
1573 | |
1574 | /* do nothing if no valid netdev defined */ | |
1575 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 1576 | return false; |
fd0a05ce | 1577 | |
1a557afc JB |
1578 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
1579 | bi = &rx_ring->rx_bi[ntu]; | |
fd0a05ce | 1580 | |
1a557afc JB |
1581 | do { |
1582 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
1583 | goto no_buffers; | |
fd0a05ce | 1584 | |
59605bc0 AD |
1585 | /* sync the buffer for use by the device */ |
1586 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
1587 | bi->page_offset, | |
98efd694 | 1588 | rx_ring->rx_buf_len, |
59605bc0 AD |
1589 | DMA_FROM_DEVICE); |
1590 | ||
1a557afc JB |
1591 | /* Refresh the desc even if buffer_addrs didn't change |
1592 | * because each write-back erases this info. | |
1593 | */ | |
1594 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
fd0a05ce | 1595 | |
1a557afc JB |
1596 | rx_desc++; |
1597 | bi++; | |
1598 | ntu++; | |
1599 | if (unlikely(ntu == rx_ring->count)) { | |
1600 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
1601 | bi = rx_ring->rx_bi; | |
1602 | ntu = 0; | |
1603 | } | |
1604 | ||
1605 | /* clear the status bits for the next_to_use descriptor */ | |
1606 | rx_desc->wb.qword1.status_error_len = 0; | |
1607 | ||
1608 | cleaned_count--; | |
1609 | } while (cleaned_count); | |
1610 | ||
1611 | if (rx_ring->next_to_use != ntu) | |
1612 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1613 | |
1614 | return false; | |
1615 | ||
fd0a05ce | 1616 | no_buffers: |
1a557afc JB |
1617 | if (rx_ring->next_to_use != ntu) |
1618 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1619 | |
1620 | /* make sure to come back via polling to try again after | |
1621 | * allocation failure | |
1622 | */ | |
1623 | return true; | |
fd0a05ce JB |
1624 | } |
1625 | ||
fd0a05ce JB |
1626 | /** |
1627 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
1628 | * @vsi: the VSI we care about | |
1629 | * @skb: skb currently being received and modified | |
1a557afc | 1630 | * @rx_desc: the receive descriptor |
fd0a05ce JB |
1631 | **/ |
1632 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
1633 | struct sk_buff *skb, | |
1a557afc | 1634 | union i40e_rx_desc *rx_desc) |
fd0a05ce | 1635 | { |
1a557afc | 1636 | struct i40e_rx_ptype_decoded decoded; |
1a557afc | 1637 | u32 rx_error, rx_status; |
858296c8 | 1638 | bool ipv4, ipv6; |
1a557afc JB |
1639 | u8 ptype; |
1640 | u64 qword; | |
1641 | ||
1642 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1643 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
1644 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
1645 | I40E_RXD_QW1_ERROR_SHIFT; | |
1646 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1647 | I40E_RXD_QW1_STATUS_SHIFT; | |
1648 | decoded = decode_rx_desc_ptype(ptype); | |
8144f0f7 | 1649 | |
fd0a05ce JB |
1650 | skb->ip_summed = CHECKSUM_NONE; |
1651 | ||
1a557afc JB |
1652 | skb_checksum_none_assert(skb); |
1653 | ||
fd0a05ce | 1654 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
1655 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
1656 | return; | |
1657 | ||
1658 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 1659 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
1660 | return; |
1661 | ||
1662 | /* both known and outer_ip must be set for the below code to work */ | |
1663 | if (!(decoded.known && decoded.outer_ip)) | |
fd0a05ce JB |
1664 | return; |
1665 | ||
fad57330 AD |
1666 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
1667 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
1668 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
1669 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
1670 | |
1671 | if (ipv4 && | |
41a1d04b JB |
1672 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
1673 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
1674 | goto checksum_fail; |
1675 | ||
ddf1d0d7 | 1676 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 1677 | if (ipv6 && |
41a1d04b | 1678 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 1679 | /* don't increment checksum err here, non-fatal err */ |
8ee75a8e SN |
1680 | return; |
1681 | ||
8a3c91cc | 1682 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 1683 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
1684 | goto checksum_fail; |
1685 | ||
1686 | /* handle packets that were not able to be checksummed due | |
1687 | * to arrival speed, in this case the stack can compute | |
1688 | * the csum. | |
1689 | */ | |
41a1d04b | 1690 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
fd0a05ce | 1691 | return; |
fd0a05ce | 1692 | |
858296c8 AD |
1693 | /* If there is an outer header present that might contain a checksum |
1694 | * we need to bump the checksum level by 1 to reflect the fact that | |
1695 | * we are indicating we validated the inner checksum. | |
8a3c91cc | 1696 | */ |
858296c8 AD |
1697 | if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) |
1698 | skb->csum_level = 1; | |
1699 | ||
1700 | /* Only report checksum unnecessary for TCP, UDP, or SCTP */ | |
1701 | switch (decoded.inner_prot) { | |
1702 | case I40E_RX_PTYPE_INNER_PROT_TCP: | |
1703 | case I40E_RX_PTYPE_INNER_PROT_UDP: | |
1704 | case I40E_RX_PTYPE_INNER_PROT_SCTP: | |
1705 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1706 | /* fall though */ | |
1707 | default: | |
1708 | break; | |
1709 | } | |
8a3c91cc JB |
1710 | |
1711 | return; | |
1712 | ||
1713 | checksum_fail: | |
1714 | vsi->back->hw_csum_rx_error++; | |
fd0a05ce JB |
1715 | } |
1716 | ||
1717 | /** | |
857942fd | 1718 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
1719 | * @ptype: the ptype value from the descriptor |
1720 | * | |
1721 | * Returns a hash type to be used by skb_set_hash | |
1722 | **/ | |
1a557afc | 1723 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
1724 | { |
1725 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
1726 | ||
1727 | if (!decoded.known) | |
1728 | return PKT_HASH_TYPE_NONE; | |
1729 | ||
1730 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1731 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
1732 | return PKT_HASH_TYPE_L4; | |
1733 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1734 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
1735 | return PKT_HASH_TYPE_L3; | |
1736 | else | |
1737 | return PKT_HASH_TYPE_L2; | |
1738 | } | |
1739 | ||
857942fd ASJ |
1740 | /** |
1741 | * i40e_rx_hash - set the hash value in the skb | |
1742 | * @ring: descriptor ring | |
1743 | * @rx_desc: specific descriptor | |
f5254429 JK |
1744 | * @skb: skb currently being received and modified |
1745 | * @rx_ptype: Rx packet type | |
857942fd ASJ |
1746 | **/ |
1747 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
1748 | union i40e_rx_desc *rx_desc, | |
1749 | struct sk_buff *skb, | |
1750 | u8 rx_ptype) | |
1751 | { | |
1752 | u32 hash; | |
1a557afc | 1753 | const __le64 rss_mask = |
857942fd ASJ |
1754 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
1755 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
1756 | ||
a876c3ba | 1757 | if (!(ring->netdev->features & NETIF_F_RXHASH)) |
857942fd ASJ |
1758 | return; |
1759 | ||
1760 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
1761 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
1762 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
1763 | } | |
1764 | } | |
1765 | ||
a132af24 | 1766 | /** |
1a557afc JB |
1767 | * i40e_process_skb_fields - Populate skb header fields from Rx descriptor |
1768 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1769 | * @rx_desc: pointer to the EOP Rx descriptor | |
1770 | * @skb: pointer to current skb being populated | |
1771 | * @rx_ptype: the packet type decoded by hardware | |
1772 | * | |
1773 | * This function checks the ring, descriptor, and packet information in | |
1774 | * order to populate the hash, checksum, VLAN, protocol, and | |
1775 | * other fields within the skb. | |
1776 | **/ | |
1a557afc | 1777 | void i40e_process_skb_fields(struct i40e_ring *rx_ring, |
800b8f63 | 1778 | union i40e_rx_desc *rx_desc, struct sk_buff *skb) |
1a557afc JB |
1779 | { |
1780 | u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1781 | u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1782 | I40E_RXD_QW1_STATUS_SHIFT; | |
144ed176 JK |
1783 | u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; |
1784 | u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> | |
1a557afc | 1785 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; |
800b8f63 MM |
1786 | u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> |
1787 | I40E_RXD_QW1_PTYPE_SHIFT; | |
1a557afc | 1788 | |
12490501 | 1789 | if (unlikely(tsynvalid)) |
144ed176 | 1790 | i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); |
1a557afc JB |
1791 | |
1792 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); | |
1793 | ||
1a557afc JB |
1794 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); |
1795 | ||
1796 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
a5b268e4 | 1797 | |
2a508c64 MM |
1798 | if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) { |
1799 | u16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1; | |
1800 | ||
1801 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1802 | le16_to_cpu(vlan_tag)); | |
1803 | } | |
1804 | ||
a5b268e4 AD |
1805 | /* modifies the skb - consumes the enet header */ |
1806 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
1a557afc JB |
1807 | } |
1808 | ||
1a557afc JB |
1809 | /** |
1810 | * i40e_cleanup_headers - Correct empty headers | |
1811 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1812 | * @skb: pointer to current skb being fixed | |
0c8493d9 | 1813 | * @rx_desc: pointer to the EOP Rx descriptor |
1a557afc JB |
1814 | * |
1815 | * Also address the case where we are pulling data in on pages only | |
1816 | * and as such no data is present in the skb header. | |
1817 | * | |
1818 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1819 | * it is large enough to qualify as a valid Ethernet frame. | |
1820 | * | |
1821 | * Returns true if an error was encountered and skb was freed. | |
1822 | **/ | |
0c8493d9 BT |
1823 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb, |
1824 | union i40e_rx_desc *rx_desc) | |
1825 | ||
1a557afc | 1826 | { |
0c8493d9 BT |
1827 | /* XDP packets use error pointer so abort at this point */ |
1828 | if (IS_ERR(skb)) | |
1829 | return true; | |
1830 | ||
1831 | /* ERR_MASK will only have valid bits if EOP set, and | |
1832 | * what we are doing here is actually checking | |
1833 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
1834 | * the error field | |
1835 | */ | |
1836 | if (unlikely(i40e_test_staterr(rx_desc, | |
1837 | BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
1838 | dev_kfree_skb_any(skb); | |
1839 | return true; | |
1840 | } | |
1841 | ||
1a557afc JB |
1842 | /* if eth_skb_pad returns an error the skb was freed */ |
1843 | if (eth_skb_pad(skb)) | |
1844 | return true; | |
1845 | ||
1846 | return false; | |
1847 | } | |
1848 | ||
1a557afc | 1849 | /** |
9b37c937 | 1850 | * i40e_page_is_reusable - check if any reuse is possible |
1a557afc | 1851 | * @page: page struct to check |
9b37c937 SP |
1852 | * |
1853 | * A page is not reusable if it was allocated under low memory | |
1854 | * conditions, or it's not in the same NUMA node as this CPU. | |
1a557afc | 1855 | */ |
9b37c937 | 1856 | static inline bool i40e_page_is_reusable(struct page *page) |
1a557afc | 1857 | { |
9b37c937 SP |
1858 | return (page_to_nid(page) == numa_mem_id()) && |
1859 | !page_is_pfmemalloc(page); | |
1860 | } | |
1861 | ||
1862 | /** | |
1863 | * i40e_can_reuse_rx_page - Determine if this page can be reused by | |
1864 | * the adapter for another receive | |
1865 | * | |
1866 | * @rx_buffer: buffer containing the page | |
9b37c937 SP |
1867 | * |
1868 | * If page is reusable, rx_buffer->page_offset is adjusted to point to | |
1869 | * an unused region in the page. | |
1870 | * | |
1871 | * For small pages, @truesize will be a constant value, half the size | |
1872 | * of the memory at page. We'll attempt to alternate between high and | |
1873 | * low halves of the page, with one half ready for use by the hardware | |
1874 | * and the other half being consumed by the stack. We use the page | |
1875 | * ref count to determine whether the stack has finished consuming the | |
1876 | * portion of this page that was passed up with a previous packet. If | |
1877 | * the page ref count is >1, we'll assume the "other" half page is | |
1878 | * still busy, and this page cannot be reused. | |
1879 | * | |
1880 | * For larger pages, @truesize will be the actual space used by the | |
1881 | * received packet (adjusted upward to an even multiple of the cache | |
1882 | * line size). This will advance through the page by the amount | |
1883 | * actually consumed by the received packets while there is still | |
1884 | * space for a buffer. Each region of larger pages will be used at | |
1885 | * most once, after which the page will not be reused. | |
1886 | * | |
1887 | * In either case, if the page is reusable its refcount is increased. | |
1888 | **/ | |
a0cfc313 | 1889 | static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer) |
9b37c937 | 1890 | { |
a0cfc313 AD |
1891 | unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; |
1892 | struct page *page = rx_buffer->page; | |
9b37c937 SP |
1893 | |
1894 | /* Is any reuse possible? */ | |
1895 | if (unlikely(!i40e_page_is_reusable(page))) | |
1896 | return false; | |
1897 | ||
1898 | #if (PAGE_SIZE < 8192) | |
1899 | /* if we are only owner of page we can reuse it */ | |
a0cfc313 | 1900 | if (unlikely((page_count(page) - pagecnt_bias) > 1)) |
9b37c937 | 1901 | return false; |
9b37c937 | 1902 | #else |
98efd694 AD |
1903 | #define I40E_LAST_OFFSET \ |
1904 | (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) | |
1905 | if (rx_buffer->page_offset > I40E_LAST_OFFSET) | |
9b37c937 SP |
1906 | return false; |
1907 | #endif | |
1908 | ||
1793668c AD |
1909 | /* If we have drained the page fragment pool we need to update |
1910 | * the pagecnt_bias and page count so that we fully restock the | |
1911 | * number of references the driver holds. | |
1912 | */ | |
8ce29c67 BT |
1913 | if (unlikely(pagecnt_bias == 1)) { |
1914 | page_ref_add(page, USHRT_MAX - 1); | |
1793668c AD |
1915 | rx_buffer->pagecnt_bias = USHRT_MAX; |
1916 | } | |
a0cfc313 | 1917 | |
9b37c937 | 1918 | return true; |
1a557afc JB |
1919 | } |
1920 | ||
1921 | /** | |
1922 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1923 | * @rx_ring: rx descriptor ring to transact packets on | |
1924 | * @rx_buffer: buffer containing page to add | |
1a557afc | 1925 | * @skb: sk_buff to place the data into |
a0cfc313 | 1926 | * @size: packet length from rx_desc |
1a557afc JB |
1927 | * |
1928 | * This function will add the data contained in rx_buffer->page to the skb. | |
fa2343e9 | 1929 | * It will just attach the page as a frag to the skb. |
1a557afc | 1930 | * |
fa2343e9 | 1931 | * The function will then update the page offset. |
1a557afc | 1932 | **/ |
a0cfc313 | 1933 | static void i40e_add_rx_frag(struct i40e_ring *rx_ring, |
1a557afc | 1934 | struct i40e_rx_buffer *rx_buffer, |
a0cfc313 AD |
1935 | struct sk_buff *skb, |
1936 | unsigned int size) | |
1a557afc | 1937 | { |
1a557afc | 1938 | #if (PAGE_SIZE < 8192) |
98efd694 | 1939 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
1a557afc | 1940 | #else |
ca9ec088 | 1941 | unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)); |
1a557afc | 1942 | #endif |
1a557afc | 1943 | |
fa2343e9 AD |
1944 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, |
1945 | rx_buffer->page_offset, size, truesize); | |
1a557afc | 1946 | |
a0cfc313 AD |
1947 | /* page is being used so we must update the page offset */ |
1948 | #if (PAGE_SIZE < 8192) | |
1949 | rx_buffer->page_offset ^= truesize; | |
1950 | #else | |
1951 | rx_buffer->page_offset += truesize; | |
1952 | #endif | |
1a557afc JB |
1953 | } |
1954 | ||
9a064128 AD |
1955 | /** |
1956 | * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use | |
1957 | * @rx_ring: rx descriptor ring to transact packets on | |
1958 | * @size: size of buffer to add to skb | |
1959 | * | |
1960 | * This function will pull an Rx buffer from the ring and synchronize it | |
1961 | * for use by the CPU. | |
1962 | */ | |
1963 | static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, | |
1964 | const unsigned int size) | |
1965 | { | |
1966 | struct i40e_rx_buffer *rx_buffer; | |
1967 | ||
1968 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1969 | prefetchw(rx_buffer->page); | |
1970 | ||
1971 | /* we are reusing so sync this buffer for CPU use */ | |
1972 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1973 | rx_buffer->dma, | |
1974 | rx_buffer->page_offset, | |
1975 | size, | |
1976 | DMA_FROM_DEVICE); | |
1977 | ||
a0cfc313 AD |
1978 | /* We have pulled a buffer for use, so decrement pagecnt_bias */ |
1979 | rx_buffer->pagecnt_bias--; | |
1980 | ||
9a064128 AD |
1981 | return rx_buffer; |
1982 | } | |
1983 | ||
1a557afc | 1984 | /** |
fa2343e9 | 1985 | * i40e_construct_skb - Allocate skb and populate it |
1a557afc | 1986 | * @rx_ring: rx descriptor ring to transact packets on |
9a064128 | 1987 | * @rx_buffer: rx buffer to pull data from |
0c8493d9 | 1988 | * @xdp: xdp_buff pointing to the data |
a132af24 | 1989 | * |
fa2343e9 AD |
1990 | * This function allocates an skb. It then populates it with the page |
1991 | * data from the current receive descriptor, taking care to set up the | |
1992 | * skb correctly. | |
1a557afc | 1993 | */ |
fa2343e9 AD |
1994 | static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, |
1995 | struct i40e_rx_buffer *rx_buffer, | |
0c8493d9 | 1996 | struct xdp_buff *xdp) |
1a557afc | 1997 | { |
0c8493d9 | 1998 | unsigned int size = xdp->data_end - xdp->data; |
fa2343e9 | 1999 | #if (PAGE_SIZE < 8192) |
98efd694 | 2000 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
fa2343e9 AD |
2001 | #else |
2002 | unsigned int truesize = SKB_DATA_ALIGN(size); | |
2003 | #endif | |
2004 | unsigned int headlen; | |
2005 | struct sk_buff *skb; | |
1a557afc | 2006 | |
fa2343e9 | 2007 | /* prefetch first cache line of first page */ |
0c8493d9 | 2008 | prefetch(xdp->data); |
1a557afc | 2009 | #if L1_CACHE_BYTES < 128 |
0c8493d9 | 2010 | prefetch(xdp->data + L1_CACHE_BYTES); |
1a557afc | 2011 | #endif |
cc5b114d DB |
2012 | /* Note, we get here by enabling legacy-rx via: |
2013 | * | |
2014 | * ethtool --set-priv-flags <dev> legacy-rx on | |
2015 | * | |
2016 | * In this mode, we currently get 0 extra XDP headroom as | |
2017 | * opposed to having legacy-rx off, where we process XDP | |
2018 | * packets going to stack via i40e_build_skb(). The latter | |
2019 | * provides us currently with 192 bytes of headroom. | |
2020 | * | |
2021 | * For i40e_construct_skb() mode it means that the | |
2022 | * xdp->data_meta will always point to xdp->data, since | |
2023 | * the helper cannot expand the head. Should this ever | |
2024 | * change in future for legacy-rx mode on, then lets also | |
2025 | * add xdp->data_meta handling here. | |
2026 | */ | |
1a557afc | 2027 | |
fa2343e9 AD |
2028 | /* allocate a skb to store the frags */ |
2029 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
2030 | I40E_RX_HDR_SIZE, | |
2031 | GFP_ATOMIC | __GFP_NOWARN); | |
2032 | if (unlikely(!skb)) | |
2033 | return NULL; | |
2034 | ||
2035 | /* Determine available headroom for copy */ | |
2036 | headlen = size; | |
2037 | if (headlen > I40E_RX_HDR_SIZE) | |
c43f1255 SF |
2038 | headlen = eth_get_headlen(skb->dev, xdp->data, |
2039 | I40E_RX_HDR_SIZE); | |
1a557afc | 2040 | |
fa2343e9 | 2041 | /* align pull length to size of long to optimize memcpy performance */ |
0c8493d9 BT |
2042 | memcpy(__skb_put(skb, headlen), xdp->data, |
2043 | ALIGN(headlen, sizeof(long))); | |
fa2343e9 AD |
2044 | |
2045 | /* update all of the pointers */ | |
2046 | size -= headlen; | |
2047 | if (size) { | |
2048 | skb_add_rx_frag(skb, 0, rx_buffer->page, | |
2049 | rx_buffer->page_offset + headlen, | |
2050 | size, truesize); | |
2051 | ||
2052 | /* buffer is used by skb, update page_offset */ | |
2053 | #if (PAGE_SIZE < 8192) | |
2054 | rx_buffer->page_offset ^= truesize; | |
2055 | #else | |
2056 | rx_buffer->page_offset += truesize; | |
2057 | #endif | |
2058 | } else { | |
2059 | /* buffer is unused, reset bias back to rx_buffer */ | |
2060 | rx_buffer->pagecnt_bias++; | |
2061 | } | |
a0cfc313 AD |
2062 | |
2063 | return skb; | |
2064 | } | |
2065 | ||
f8b45b74 AD |
2066 | /** |
2067 | * i40e_build_skb - Build skb around an existing buffer | |
2068 | * @rx_ring: Rx descriptor ring to transact packets on | |
2069 | * @rx_buffer: Rx buffer to pull data from | |
0c8493d9 | 2070 | * @xdp: xdp_buff pointing to the data |
f8b45b74 AD |
2071 | * |
2072 | * This function builds an skb around an existing Rx buffer, taking care | |
2073 | * to set up the skb correctly and avoid any memcpy overhead. | |
2074 | */ | |
2075 | static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, | |
2076 | struct i40e_rx_buffer *rx_buffer, | |
0c8493d9 | 2077 | struct xdp_buff *xdp) |
f8b45b74 | 2078 | { |
cc5b114d | 2079 | unsigned int metasize = xdp->data - xdp->data_meta; |
f8b45b74 AD |
2080 | #if (PAGE_SIZE < 8192) |
2081 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; | |
2082 | #else | |
2aae918c | 2083 | unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
c51818d5 DB |
2084 | SKB_DATA_ALIGN(xdp->data_end - |
2085 | xdp->data_hard_start); | |
f8b45b74 AD |
2086 | #endif |
2087 | struct sk_buff *skb; | |
2088 | ||
cc5b114d DB |
2089 | /* Prefetch first cache line of first page. If xdp->data_meta |
2090 | * is unused, this points exactly as xdp->data, otherwise we | |
2091 | * likely have a consumer accessing first few bytes of meta | |
2092 | * data, and then actual data. | |
2093 | */ | |
2094 | prefetch(xdp->data_meta); | |
f8b45b74 | 2095 | #if L1_CACHE_BYTES < 128 |
cc5b114d | 2096 | prefetch(xdp->data_meta + L1_CACHE_BYTES); |
f8b45b74 AD |
2097 | #endif |
2098 | /* build an skb around the page buffer */ | |
0c8493d9 | 2099 | skb = build_skb(xdp->data_hard_start, truesize); |
f8b45b74 AD |
2100 | if (unlikely(!skb)) |
2101 | return NULL; | |
2102 | ||
2103 | /* update pointers within the skb to store the data */ | |
c51818d5 | 2104 | skb_reserve(skb, xdp->data - xdp->data_hard_start); |
cc5b114d DB |
2105 | __skb_put(skb, xdp->data_end - xdp->data); |
2106 | if (metasize) | |
2107 | skb_metadata_set(skb, metasize); | |
f8b45b74 AD |
2108 | |
2109 | /* buffer is used by skb, update page_offset */ | |
2110 | #if (PAGE_SIZE < 8192) | |
2111 | rx_buffer->page_offset ^= truesize; | |
2112 | #else | |
2113 | rx_buffer->page_offset += truesize; | |
2114 | #endif | |
2115 | ||
2116 | return skb; | |
2117 | } | |
2118 | ||
a0cfc313 AD |
2119 | /** |
2120 | * i40e_put_rx_buffer - Clean up used buffer and either recycle or free | |
2121 | * @rx_ring: rx descriptor ring to transact packets on | |
2122 | * @rx_buffer: rx buffer to pull data from | |
2123 | * | |
2124 | * This function will clean up the contents of the rx_buffer. It will | |
11a350c9 | 2125 | * either recycle the buffer or unmap it and free the associated resources. |
a0cfc313 AD |
2126 | */ |
2127 | static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, | |
2128 | struct i40e_rx_buffer *rx_buffer) | |
2129 | { | |
2130 | if (i40e_can_reuse_rx_page(rx_buffer)) { | |
1a557afc JB |
2131 | /* hand second half of page back to the ring */ |
2132 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1a557afc JB |
2133 | } else { |
2134 | /* we are not reusing the buffer so unmap it */ | |
98efd694 AD |
2135 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, |
2136 | i40e_rx_pg_size(rx_ring), | |
59605bc0 | 2137 | DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); |
1793668c AD |
2138 | __page_frag_cache_drain(rx_buffer->page, |
2139 | rx_buffer->pagecnt_bias); | |
6d7aad1d BT |
2140 | /* clear contents of buffer_info */ |
2141 | rx_buffer->page = NULL; | |
1a557afc | 2142 | } |
1a557afc JB |
2143 | } |
2144 | ||
2145 | /** | |
2146 | * i40e_is_non_eop - process handling of non-EOP buffers | |
2147 | * @rx_ring: Rx ring being processed | |
2148 | * @rx_desc: Rx descriptor for current buffer | |
2149 | * @skb: Current socket buffer containing buffer in progress | |
2150 | * | |
2151 | * This function updates next to clean. If the buffer is an EOP buffer | |
2152 | * this function exits returning false, otherwise it will place the | |
2153 | * sk_buff in the next buffer to be chained and return true indicating | |
2154 | * that this is in fact a non-EOP buffer. | |
a132af24 | 2155 | **/ |
1a557afc JB |
2156 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, |
2157 | union i40e_rx_desc *rx_desc, | |
2158 | struct sk_buff *skb) | |
2159 | { | |
2160 | u32 ntc = rx_ring->next_to_clean + 1; | |
2161 | ||
2162 | /* fetch, update, and store next to clean */ | |
2163 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
2164 | rx_ring->next_to_clean = ntc; | |
2165 | ||
2166 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
2167 | ||
1a557afc JB |
2168 | /* if we are the last buffer then there is nothing else to do */ |
2169 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
2170 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
2171 | return false; | |
2172 | ||
1a557afc JB |
2173 | rx_ring->rx_stats.non_eop_descs++; |
2174 | ||
2175 | return true; | |
2176 | } | |
2177 | ||
44fa2dbd | 2178 | static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, |
74608d17 | 2179 | struct i40e_ring *xdp_ring); |
0c8493d9 | 2180 | |
20a739db | 2181 | int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring) |
44fa2dbd JDB |
2182 | { |
2183 | struct xdp_frame *xdpf = convert_to_xdp_frame(xdp); | |
2184 | ||
2185 | if (unlikely(!xdpf)) | |
2186 | return I40E_XDP_CONSUMED; | |
2187 | ||
2188 | return i40e_xmit_xdp_ring(xdpf, xdp_ring); | |
2189 | } | |
2190 | ||
0c8493d9 BT |
2191 | /** |
2192 | * i40e_run_xdp - run an XDP program | |
2193 | * @rx_ring: Rx ring being processed | |
2194 | * @xdp: XDP buffer containing the frame | |
2195 | **/ | |
2196 | static struct sk_buff *i40e_run_xdp(struct i40e_ring *rx_ring, | |
2197 | struct xdp_buff *xdp) | |
2198 | { | |
d9314c47 | 2199 | int err, result = I40E_XDP_PASS; |
74608d17 | 2200 | struct i40e_ring *xdp_ring; |
0c8493d9 BT |
2201 | struct bpf_prog *xdp_prog; |
2202 | u32 act; | |
2203 | ||
2204 | rcu_read_lock(); | |
2205 | xdp_prog = READ_ONCE(rx_ring->xdp_prog); | |
2206 | ||
2207 | if (!xdp_prog) | |
2208 | goto xdp_out; | |
2209 | ||
b411ef11 JDB |
2210 | prefetchw(xdp->data_hard_start); /* xdp_frame write */ |
2211 | ||
0c8493d9 BT |
2212 | act = bpf_prog_run_xdp(xdp_prog, xdp); |
2213 | switch (act) { | |
2214 | case XDP_PASS: | |
2215 | break; | |
74608d17 BT |
2216 | case XDP_TX: |
2217 | xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index]; | |
44fa2dbd | 2218 | result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring); |
74608d17 | 2219 | break; |
d9314c47 BT |
2220 | case XDP_REDIRECT: |
2221 | err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog); | |
2e689312 | 2222 | result = !err ? I40E_XDP_REDIR : I40E_XDP_CONSUMED; |
d9314c47 | 2223 | break; |
0c8493d9 BT |
2224 | default: |
2225 | bpf_warn_invalid_xdp_action(act); | |
f7c3ca2d | 2226 | /* fall through */ |
0c8493d9 BT |
2227 | case XDP_ABORTED: |
2228 | trace_xdp_exception(rx_ring->netdev, xdp_prog, act); | |
f7c3ca2d | 2229 | /* fall through -- handle aborts by dropping packet */ |
0c8493d9 BT |
2230 | case XDP_DROP: |
2231 | result = I40E_XDP_CONSUMED; | |
2232 | break; | |
2233 | } | |
2234 | xdp_out: | |
2235 | rcu_read_unlock(); | |
2236 | return ERR_PTR(-result); | |
2237 | } | |
2238 | ||
74608d17 BT |
2239 | /** |
2240 | * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region | |
2241 | * @rx_ring: Rx ring | |
2242 | * @rx_buffer: Rx buffer to adjust | |
2243 | * @size: Size of adjustment | |
2244 | **/ | |
2245 | static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring, | |
2246 | struct i40e_rx_buffer *rx_buffer, | |
2247 | unsigned int size) | |
2248 | { | |
2249 | #if (PAGE_SIZE < 8192) | |
2250 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; | |
2251 | ||
2252 | rx_buffer->page_offset ^= truesize; | |
2253 | #else | |
2254 | unsigned int truesize = SKB_DATA_ALIGN(i40e_rx_offset(rx_ring) + size); | |
2255 | ||
2256 | rx_buffer->page_offset += truesize; | |
2257 | #endif | |
2258 | } | |
2259 | ||
6d7aad1d BT |
2260 | /** |
2261 | * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register | |
2262 | * @xdp_ring: XDP Tx ring | |
2263 | * | |
2264 | * This function updates the XDP Tx ring tail register. | |
2265 | **/ | |
20a739db | 2266 | void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring) |
d9314c47 BT |
2267 | { |
2268 | /* Force memory writes to complete before letting h/w | |
2269 | * know there are new descriptors to fetch. | |
2270 | */ | |
2271 | wmb(); | |
2272 | writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail); | |
2273 | } | |
2274 | ||
6d7aad1d BT |
2275 | /** |
2276 | * i40e_update_rx_stats - Update Rx ring statistics | |
2277 | * @rx_ring: rx descriptor ring | |
2278 | * @total_rx_bytes: number of bytes received | |
2279 | * @total_rx_packets: number of packets received | |
2280 | * | |
2281 | * This function updates the Rx ring statistics. | |
2282 | **/ | |
20a739db BT |
2283 | void i40e_update_rx_stats(struct i40e_ring *rx_ring, |
2284 | unsigned int total_rx_bytes, | |
2285 | unsigned int total_rx_packets) | |
6d7aad1d BT |
2286 | { |
2287 | u64_stats_update_begin(&rx_ring->syncp); | |
2288 | rx_ring->stats.packets += total_rx_packets; | |
2289 | rx_ring->stats.bytes += total_rx_bytes; | |
2290 | u64_stats_update_end(&rx_ring->syncp); | |
2291 | rx_ring->q_vector->rx.total_packets += total_rx_packets; | |
2292 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
2293 | } | |
2294 | ||
2295 | /** | |
2296 | * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map | |
2297 | * @rx_ring: Rx ring | |
2298 | * @xdp_res: Result of the receive batch | |
2299 | * | |
2300 | * This function bumps XDP Tx tail and/or flush redirect map, and | |
2301 | * should be called when a batch of packets has been processed in the | |
2302 | * napi loop. | |
2303 | **/ | |
20a739db | 2304 | void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res) |
6d7aad1d BT |
2305 | { |
2306 | if (xdp_res & I40E_XDP_REDIR) | |
2307 | xdp_do_flush_map(); | |
2308 | ||
2309 | if (xdp_res & I40E_XDP_TX) { | |
2310 | struct i40e_ring *xdp_ring = | |
2311 | rx_ring->vsi->xdp_rings[rx_ring->queue_index]; | |
2312 | ||
2313 | i40e_xdp_ring_update_tail(xdp_ring); | |
2314 | } | |
2315 | } | |
2316 | ||
1a557afc JB |
2317 | /** |
2318 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
2319 | * @rx_ring: rx descriptor ring to transact packets on | |
2320 | * @budget: Total limit on number of packets to process | |
2321 | * | |
2322 | * This function provides a "bounce buffer" approach to Rx interrupt | |
2323 | * processing. The advantage to this is that on systems that have | |
2324 | * expensive overhead for IOMMU access this provides a means of avoiding | |
2325 | * it by maintaining the mapping of the page to the system. | |
2326 | * | |
2327 | * Returns amount of work completed | |
2328 | **/ | |
2329 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) | |
a132af24 MW |
2330 | { |
2331 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
e72e5659 | 2332 | struct sk_buff *skb = rx_ring->skb; |
a132af24 | 2333 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); |
2e689312 JDB |
2334 | unsigned int xdp_xmit = 0; |
2335 | bool failure = false; | |
87128824 JDB |
2336 | struct xdp_buff xdp; |
2337 | ||
2338 | xdp.rxq = &rx_ring->xdp_rxq; | |
a132af24 | 2339 | |
b85c94b6 | 2340 | while (likely(total_rx_packets < (unsigned int)budget)) { |
9a064128 | 2341 | struct i40e_rx_buffer *rx_buffer; |
1a557afc | 2342 | union i40e_rx_desc *rx_desc; |
d57c0e08 | 2343 | unsigned int size; |
1a557afc JB |
2344 | u64 qword; |
2345 | ||
fd0a05ce JB |
2346 | /* return some buffers to hardware, one at a time is too slow */ |
2347 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 2348 | failure = failure || |
1a557afc | 2349 | i40e_alloc_rx_buffers(rx_ring, cleaned_count); |
fd0a05ce JB |
2350 | cleaned_count = 0; |
2351 | } | |
2352 | ||
1a557afc JB |
2353 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
2354 | ||
1a557afc JB |
2355 | /* status_error_len will always be zero for unused descriptors |
2356 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
2357 | * which is always zero because packet split isn't used, if the | |
d57c0e08 | 2358 | * hardware wrote DD then the length will be non-zero |
1a557afc | 2359 | */ |
d57c0e08 | 2360 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1a557afc | 2361 | |
a132af24 | 2362 | /* This memory barrier is needed to keep us from reading |
d57c0e08 AD |
2363 | * any other fields out of the rx_desc until we have |
2364 | * verified the descriptor has been written back. | |
a132af24 | 2365 | */ |
67317166 | 2366 | dma_rmb(); |
a132af24 | 2367 | |
6d7aad1d BT |
2368 | rx_buffer = i40e_clean_programming_status(rx_ring, rx_desc, |
2369 | qword); | |
2370 | if (unlikely(rx_buffer)) { | |
2371 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
62b4c669 | 2372 | cleaned_count++; |
0e626ff7 AD |
2373 | continue; |
2374 | } | |
6d7aad1d | 2375 | |
0e626ff7 AD |
2376 | size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> |
2377 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
2378 | if (!size) | |
2379 | break; | |
2380 | ||
ed0980c4 | 2381 | i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb); |
9a064128 AD |
2382 | rx_buffer = i40e_get_rx_buffer(rx_ring, size); |
2383 | ||
fa2343e9 | 2384 | /* retrieve a buffer from the ring */ |
0c8493d9 BT |
2385 | if (!skb) { |
2386 | xdp.data = page_address(rx_buffer->page) + | |
2387 | rx_buffer->page_offset; | |
cc5b114d | 2388 | xdp.data_meta = xdp.data; |
0c8493d9 BT |
2389 | xdp.data_hard_start = xdp.data - |
2390 | i40e_rx_offset(rx_ring); | |
2391 | xdp.data_end = xdp.data + size; | |
2392 | ||
2393 | skb = i40e_run_xdp(rx_ring, &xdp); | |
2394 | } | |
2395 | ||
2396 | if (IS_ERR(skb)) { | |
2e689312 JDB |
2397 | unsigned int xdp_res = -PTR_ERR(skb); |
2398 | ||
2399 | if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) { | |
2400 | xdp_xmit |= xdp_res; | |
74608d17 BT |
2401 | i40e_rx_buffer_flip(rx_ring, rx_buffer, size); |
2402 | } else { | |
2403 | rx_buffer->pagecnt_bias++; | |
2404 | } | |
0c8493d9 BT |
2405 | total_rx_bytes += size; |
2406 | total_rx_packets++; | |
0c8493d9 | 2407 | } else if (skb) { |
fa2343e9 | 2408 | i40e_add_rx_frag(rx_ring, rx_buffer, skb, size); |
0c8493d9 BT |
2409 | } else if (ring_uses_build_skb(rx_ring)) { |
2410 | skb = i40e_build_skb(rx_ring, rx_buffer, &xdp); | |
2411 | } else { | |
2412 | skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp); | |
2413 | } | |
fa2343e9 AD |
2414 | |
2415 | /* exit if we failed to retrieve a buffer */ | |
2416 | if (!skb) { | |
2417 | rx_ring->rx_stats.alloc_buff_failed++; | |
2418 | rx_buffer->pagecnt_bias++; | |
1a557afc | 2419 | break; |
fa2343e9 | 2420 | } |
a132af24 | 2421 | |
a0cfc313 | 2422 | i40e_put_rx_buffer(rx_ring, rx_buffer); |
a132af24 MW |
2423 | cleaned_count++; |
2424 | ||
1a557afc | 2425 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 2426 | continue; |
a132af24 | 2427 | |
0c8493d9 | 2428 | if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) { |
e72e5659 | 2429 | skb = NULL; |
1a557afc | 2430 | continue; |
e72e5659 | 2431 | } |
a132af24 MW |
2432 | |
2433 | /* probably a little skewed due to removing CRC */ | |
2434 | total_rx_bytes += skb->len; | |
a132af24 | 2435 | |
1a557afc | 2436 | /* populate checksum, VLAN, and protocol */ |
800b8f63 | 2437 | i40e_process_skb_fields(rx_ring, rx_desc, skb); |
1a557afc | 2438 | |
ed0980c4 | 2439 | i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb); |
2a508c64 | 2440 | napi_gro_receive(&rx_ring->q_vector->napi, skb); |
e72e5659 | 2441 | skb = NULL; |
a132af24 | 2442 | |
1a557afc JB |
2443 | /* update budget accounting */ |
2444 | total_rx_packets++; | |
2445 | } | |
fd0a05ce | 2446 | |
6d7aad1d | 2447 | i40e_finalize_xdp_rx(rx_ring, xdp_xmit); |
e72e5659 SP |
2448 | rx_ring->skb = skb; |
2449 | ||
6d7aad1d | 2450 | i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets); |
fd0a05ce | 2451 | |
1a557afc | 2452 | /* guarantee a trip back through this routine if there was a failure */ |
b85c94b6 | 2453 | return failure ? budget : (int)total_rx_packets; |
fd0a05ce JB |
2454 | } |
2455 | ||
92418fb1 | 2456 | static inline u32 i40e_buildreg_itr(const int type, u16 itr) |
8f5e39ce JB |
2457 | { |
2458 | u32 val; | |
2459 | ||
4ff17929 AD |
2460 | /* We don't bother with setting the CLEARPBA bit as the data sheet |
2461 | * points out doing so is "meaningless since it was already | |
2462 | * auto-cleared". The auto-clearing happens when the interrupt is | |
2463 | * asserted. | |
2464 | * | |
2465 | * Hardware errata 28 for also indicates that writing to a | |
2466 | * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear | |
2467 | * an event in the PBA anyway so we need to rely on the automask | |
2468 | * to hold pending events for us until the interrupt is re-enabled | |
92418fb1 AD |
2469 | * |
2470 | * The itr value is reported in microseconds, and the register | |
2471 | * value is recorded in 2 microsecond units. For this reason we | |
2472 | * only need to shift by the interval shift - 1 instead of the | |
2473 | * full value. | |
4ff17929 | 2474 | */ |
92418fb1 AD |
2475 | itr &= I40E_ITR_MASK; |
2476 | ||
8f5e39ce | 2477 | val = I40E_PFINT_DYN_CTLN_INTENA_MASK | |
8f5e39ce | 2478 | (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | |
92418fb1 | 2479 | (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1)); |
8f5e39ce JB |
2480 | |
2481 | return val; | |
2482 | } | |
2483 | ||
2484 | /* a small macro to shorten up some long lines */ | |
2485 | #define INTREG I40E_PFINT_DYN_CTLN | |
2486 | ||
a0073a4b AD |
2487 | /* The act of updating the ITR will cause it to immediately trigger. In order |
2488 | * to prevent this from throwing off adaptive update statistics we defer the | |
2489 | * update so that it can only happen so often. So after either Tx or Rx are | |
2490 | * updated we make the adaptive scheme wait until either the ITR completely | |
2491 | * expires via the next_update expiration or we have been through at least | |
2492 | * 3 interrupts. | |
2493 | */ | |
2494 | #define ITR_COUNTDOWN_START 3 | |
2495 | ||
de32e3ef CW |
2496 | /** |
2497 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
2498 | * @vsi: the VSI we care about | |
2499 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
2500 | * | |
2501 | **/ | |
2502 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
2503 | struct i40e_q_vector *q_vector) | |
2504 | { | |
2505 | struct i40e_hw *hw = &vsi->back->hw; | |
556fdfd6 | 2506 | u32 intval; |
de32e3ef | 2507 | |
9254c0e3 JK |
2508 | /* If we don't have MSIX, then we only need to re-enable icr0 */ |
2509 | if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) { | |
dbadbbe2 | 2510 | i40e_irq_dynamic_enable_icr0(vsi->back); |
9254c0e3 JK |
2511 | return; |
2512 | } | |
2513 | ||
a0073a4b AD |
2514 | /* These will do nothing if dynamic updates are not enabled */ |
2515 | i40e_update_itr(q_vector, &q_vector->tx); | |
2516 | i40e_update_itr(q_vector, &q_vector->rx); | |
ee2319cf | 2517 | |
a0073a4b AD |
2518 | /* This block of logic allows us to get away with only updating |
2519 | * one ITR value with each interrupt. The idea is to perform a | |
2520 | * pseudo-lazy update with the following criteria. | |
2521 | * | |
2522 | * 1. Rx is given higher priority than Tx if both are in same state | |
2523 | * 2. If we must reduce an ITR that is given highest priority. | |
2524 | * 3. We then give priority to increasing ITR based on amount. | |
2525 | */ | |
2526 | if (q_vector->rx.target_itr < q_vector->rx.current_itr) { | |
2527 | /* Rx ITR needs to be reduced, this is highest priority */ | |
556fdfd6 AD |
2528 | intval = i40e_buildreg_itr(I40E_RX_ITR, |
2529 | q_vector->rx.target_itr); | |
2530 | q_vector->rx.current_itr = q_vector->rx.target_itr; | |
a0073a4b AD |
2531 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
2532 | } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) || | |
2533 | ((q_vector->rx.target_itr - q_vector->rx.current_itr) < | |
2534 | (q_vector->tx.target_itr - q_vector->tx.current_itr))) { | |
2535 | /* Tx ITR needs to be reduced, this is second priority | |
2536 | * Tx ITR needs to be increased more than Rx, fourth priority | |
2537 | */ | |
556fdfd6 AD |
2538 | intval = i40e_buildreg_itr(I40E_TX_ITR, |
2539 | q_vector->tx.target_itr); | |
2540 | q_vector->tx.current_itr = q_vector->tx.target_itr; | |
a0073a4b AD |
2541 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
2542 | } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) { | |
2543 | /* Rx ITR needs to be increased, third priority */ | |
2544 | intval = i40e_buildreg_itr(I40E_RX_ITR, | |
2545 | q_vector->rx.target_itr); | |
2546 | q_vector->rx.current_itr = q_vector->rx.target_itr; | |
2547 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
556fdfd6 | 2548 | } else { |
a0073a4b | 2549 | /* No ITR update, lowest priority */ |
556fdfd6 | 2550 | intval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
a0073a4b AD |
2551 | if (q_vector->itr_countdown) |
2552 | q_vector->itr_countdown--; | |
556fdfd6 AD |
2553 | } |
2554 | ||
0da36b97 | 2555 | if (!test_bit(__I40E_VSI_DOWN, vsi->state)) |
556fdfd6 | 2556 | wr32(hw, INTREG(q_vector->reg_idx), intval); |
de32e3ef CW |
2557 | } |
2558 | ||
fd0a05ce JB |
2559 | /** |
2560 | * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine | |
2561 | * @napi: napi struct with our devices info in it | |
2562 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2563 | * | |
2564 | * This function will clean all queues associated with a q_vector. | |
2565 | * | |
2566 | * Returns the amount of work done | |
2567 | **/ | |
2568 | int i40e_napi_poll(struct napi_struct *napi, int budget) | |
2569 | { | |
2570 | struct i40e_q_vector *q_vector = | |
2571 | container_of(napi, struct i40e_q_vector, napi); | |
2572 | struct i40e_vsi *vsi = q_vector->vsi; | |
cd0b6fa6 | 2573 | struct i40e_ring *ring; |
fd0a05ce | 2574 | bool clean_complete = true; |
d91649f5 | 2575 | bool arm_wb = false; |
fd0a05ce | 2576 | int budget_per_ring; |
32b3e08f | 2577 | int work_done = 0; |
fd0a05ce | 2578 | |
0da36b97 | 2579 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) { |
fd0a05ce JB |
2580 | napi_complete(napi); |
2581 | return 0; | |
2582 | } | |
2583 | ||
cd0b6fa6 AD |
2584 | /* Since the actual Tx work is minimal, we can give the Tx a larger |
2585 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
2586 | */ | |
d91649f5 | 2587 | i40e_for_each_ring(ring, q_vector->tx) { |
1328dcdd MK |
2588 | bool wd = ring->xsk_umem ? |
2589 | i40e_clean_xdp_tx_irq(vsi, ring, budget) : | |
2590 | i40e_clean_tx_irq(vsi, ring, budget); | |
2591 | ||
2592 | if (!wd) { | |
f2edaaaa AD |
2593 | clean_complete = false; |
2594 | continue; | |
2595 | } | |
2596 | arm_wb |= ring->arm_wb; | |
0deda868 | 2597 | ring->arm_wb = false; |
d91649f5 | 2598 | } |
cd0b6fa6 | 2599 | |
c67caceb AD |
2600 | /* Handle case where we are called by netpoll with a budget of 0 */ |
2601 | if (budget <= 0) | |
2602 | goto tx_only; | |
2603 | ||
fd0a05ce JB |
2604 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
2605 | * allow the budget to go below 1 because that would exit polling early. | |
fd0a05ce JB |
2606 | */ |
2607 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
cd0b6fa6 | 2608 | |
a132af24 | 2609 | i40e_for_each_ring(ring, q_vector->rx) { |
0a714186 BT |
2610 | int cleaned = ring->xsk_umem ? |
2611 | i40e_clean_rx_irq_zc(ring, budget_per_ring) : | |
2612 | i40e_clean_rx_irq(ring, budget_per_ring); | |
32b3e08f JB |
2613 | |
2614 | work_done += cleaned; | |
f2edaaaa AD |
2615 | /* if we clean as many as budgeted, we must not be done */ |
2616 | if (cleaned >= budget_per_ring) | |
2617 | clean_complete = false; | |
a132af24 | 2618 | } |
fd0a05ce JB |
2619 | |
2620 | /* If work not completed, return budget and polling will return */ | |
d91649f5 | 2621 | if (!clean_complete) { |
96db776a AB |
2622 | int cpu_id = smp_processor_id(); |
2623 | ||
2624 | /* It is possible that the interrupt affinity has changed but, | |
2625 | * if the cpu is pegged at 100%, polling will never exit while | |
2626 | * traffic continues and the interrupt will be stuck on this | |
2627 | * cpu. We check to make sure affinity is correct before we | |
2628 | * continue to poll, otherwise we must stop polling so the | |
2629 | * interrupt can move to the correct cpu. | |
2630 | */ | |
6d977729 JK |
2631 | if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) { |
2632 | /* Tell napi that we are done polling */ | |
2633 | napi_complete_done(napi, work_done); | |
2634 | ||
2635 | /* Force an interrupt */ | |
2636 | i40e_force_wb(vsi, q_vector); | |
2637 | ||
2638 | /* Return budget-1 so that polling stops */ | |
2639 | return budget - 1; | |
2640 | } | |
c67caceb | 2641 | tx_only: |
6d977729 JK |
2642 | if (arm_wb) { |
2643 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
2644 | i40e_enable_wb_on_itr(vsi, q_vector); | |
164c9f54 | 2645 | } |
6d977729 | 2646 | return budget; |
d91649f5 | 2647 | } |
fd0a05ce | 2648 | |
8e0764b4 ASJ |
2649 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
2650 | q_vector->arm_wb_state = false; | |
2651 | ||
0bcd952f JB |
2652 | /* Exit the polling mode, but don't re-enable interrupts if stack might |
2653 | * poll us due to busy-polling | |
2654 | */ | |
2655 | if (likely(napi_complete_done(napi, work_done))) | |
2656 | i40e_update_enable_itr(vsi, q_vector); | |
96db776a | 2657 | |
6beb84a7 | 2658 | return min(work_done, budget - 1); |
fd0a05ce JB |
2659 | } |
2660 | ||
2661 | /** | |
2662 | * i40e_atr - Add a Flow Director ATR filter | |
2663 | * @tx_ring: ring to add programming descriptor to | |
2664 | * @skb: send buffer | |
89232c3b | 2665 | * @tx_flags: send tx flags |
fd0a05ce JB |
2666 | **/ |
2667 | static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
6b037cd4 | 2668 | u32 tx_flags) |
fd0a05ce JB |
2669 | { |
2670 | struct i40e_filter_program_desc *fdir_desc; | |
2671 | struct i40e_pf *pf = tx_ring->vsi->back; | |
2672 | union { | |
2673 | unsigned char *network; | |
2674 | struct iphdr *ipv4; | |
2675 | struct ipv6hdr *ipv6; | |
2676 | } hdr; | |
2677 | struct tcphdr *th; | |
2678 | unsigned int hlen; | |
2679 | u32 flex_ptype, dtype_cmd; | |
ffcc55c0 | 2680 | int l4_proto; |
fc4ac67b | 2681 | u16 i; |
fd0a05ce JB |
2682 | |
2683 | /* make sure ATR is enabled */ | |
60ea5f83 | 2684 | if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) |
fd0a05ce JB |
2685 | return; |
2686 | ||
134201ae | 2687 | if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) |
04294e38 ASJ |
2688 | return; |
2689 | ||
fd0a05ce JB |
2690 | /* if sampling is disabled do nothing */ |
2691 | if (!tx_ring->atr_sample_rate) | |
2692 | return; | |
2693 | ||
6b037cd4 | 2694 | /* Currently only IPv4/IPv6 with TCP is supported */ |
89232c3b ASJ |
2695 | if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) |
2696 | return; | |
fd0a05ce | 2697 | |
ffcc55c0 AD |
2698 | /* snag network header to get L4 type and address */ |
2699 | hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? | |
2700 | skb_inner_network_header(skb) : skb_network_header(skb); | |
fd0a05ce | 2701 | |
ffcc55c0 AD |
2702 | /* Note: tx_flags gets modified to reflect inner protocols in |
2703 | * tx_enable_csum function if encap is enabled. | |
2704 | */ | |
2705 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
6b037cd4 | 2706 | /* access ihl as u8 to avoid unaligned access on ia64 */ |
ffcc55c0 AD |
2707 | hlen = (hdr.network[0] & 0x0F) << 2; |
2708 | l4_proto = hdr.ipv4->protocol; | |
fd0a05ce | 2709 | } else { |
601a2e7a JB |
2710 | /* find the start of the innermost ipv6 header */ |
2711 | unsigned int inner_hlen = hdr.network - skb->data; | |
2712 | unsigned int h_offset = inner_hlen; | |
2713 | ||
2714 | /* this function updates h_offset to the end of the header */ | |
2715 | l4_proto = | |
2716 | ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL); | |
2717 | /* hlen will contain our best estimate of the tcp header */ | |
2718 | hlen = h_offset - inner_hlen; | |
fd0a05ce JB |
2719 | } |
2720 | ||
6b037cd4 | 2721 | if (l4_proto != IPPROTO_TCP) |
89232c3b ASJ |
2722 | return; |
2723 | ||
fd0a05ce JB |
2724 | th = (struct tcphdr *)(hdr.network + hlen); |
2725 | ||
55a5e60b | 2726 | /* Due to lack of space, no more new filters can be programmed */ |
134201ae | 2727 | if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) |
55a5e60b | 2728 | return; |
6964e53f | 2729 | if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) { |
52eb95ef ASJ |
2730 | /* HW ATR eviction will take care of removing filters on FIN |
2731 | * and RST packets. | |
2732 | */ | |
2733 | if (th->fin || th->rst) | |
2734 | return; | |
2735 | } | |
55a5e60b ASJ |
2736 | |
2737 | tx_ring->atr_count++; | |
2738 | ||
ce806783 ASJ |
2739 | /* sample on all syn/fin/rst packets or once every atr sample rate */ |
2740 | if (!th->fin && | |
2741 | !th->syn && | |
2742 | !th->rst && | |
2743 | (tx_ring->atr_count < tx_ring->atr_sample_rate)) | |
fd0a05ce JB |
2744 | return; |
2745 | ||
2746 | tx_ring->atr_count = 0; | |
2747 | ||
2748 | /* grab the next descriptor */ | |
fc4ac67b AD |
2749 | i = tx_ring->next_to_use; |
2750 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
2751 | ||
2752 | i++; | |
2753 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2754 | |
2755 | flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & | |
2756 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
6b037cd4 | 2757 | flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? |
fd0a05ce JB |
2758 | (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << |
2759 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : | |
2760 | (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << | |
2761 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
2762 | ||
2763 | flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
2764 | ||
2765 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
2766 | ||
ce806783 | 2767 | dtype_cmd |= (th->fin || th->rst) ? |
fd0a05ce JB |
2768 | (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
2769 | I40E_TXD_FLTR_QW1_PCMD_SHIFT) : | |
2770 | (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
2771 | I40E_TXD_FLTR_QW1_PCMD_SHIFT); | |
2772 | ||
2773 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << | |
2774 | I40E_TXD_FLTR_QW1_DEST_SHIFT; | |
2775 | ||
2776 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << | |
2777 | I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; | |
2778 | ||
433c47de | 2779 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
6a899024 | 2780 | if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) |
60ccd45c ASJ |
2781 | dtype_cmd |= |
2782 | ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << | |
2783 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2784 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
2785 | else | |
2786 | dtype_cmd |= | |
2787 | ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << | |
2788 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2789 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
433c47de | 2790 | |
6964e53f | 2791 | if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) |
52eb95ef ASJ |
2792 | dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; |
2793 | ||
fd0a05ce | 2794 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); |
99753ea6 | 2795 | fdir_desc->rsvd = cpu_to_le32(0); |
fd0a05ce | 2796 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); |
99753ea6 | 2797 | fdir_desc->fd_id = cpu_to_le32(0); |
fd0a05ce JB |
2798 | } |
2799 | ||
fd0a05ce JB |
2800 | /** |
2801 | * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW | |
2802 | * @skb: send buffer | |
2803 | * @tx_ring: ring to send buffer on | |
2804 | * @flags: the tx flags to be set | |
2805 | * | |
2806 | * Checks the skb and set up correspondingly several generic transmit flags | |
2807 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
2808 | * | |
2809 | * Returns error code indicate the frame should be dropped upon error and the | |
2810 | * otherwise returns 0 to indicate the flags has been set properly. | |
2811 | **/ | |
3e587cf3 JB |
2812 | static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, |
2813 | struct i40e_ring *tx_ring, | |
2814 | u32 *flags) | |
fd0a05ce JB |
2815 | { |
2816 | __be16 protocol = skb->protocol; | |
2817 | u32 tx_flags = 0; | |
2818 | ||
31eaaccf GR |
2819 | if (protocol == htons(ETH_P_8021Q) && |
2820 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
2821 | /* When HW VLAN acceleration is turned off by the user the | |
2822 | * stack sets the protocol to 8021q so that the driver | |
2823 | * can take any steps required to support the SW only | |
2824 | * VLAN handling. In our case the driver doesn't need | |
2825 | * to take any further steps so just set the protocol | |
2826 | * to the encapsulated ethertype. | |
2827 | */ | |
2828 | skb->protocol = vlan_get_protocol(skb); | |
2829 | goto out; | |
2830 | } | |
2831 | ||
fd0a05ce | 2832 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
2833 | if (skb_vlan_tag_present(skb)) { |
2834 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
fd0a05ce JB |
2835 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
2836 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
0e2fe46c | 2837 | } else if (protocol == htons(ETH_P_8021Q)) { |
fd0a05ce | 2838 | struct vlan_hdr *vhdr, _vhdr; |
6995b36c | 2839 | |
fd0a05ce JB |
2840 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
2841 | if (!vhdr) | |
2842 | return -EINVAL; | |
2843 | ||
2844 | protocol = vhdr->h_vlan_encapsulated_proto; | |
2845 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
2846 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
2847 | } | |
2848 | ||
d40d00b1 NP |
2849 | if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) |
2850 | goto out; | |
2851 | ||
fd0a05ce | 2852 | /* Insert 802.1p priority into VLAN header */ |
38e00438 VD |
2853 | if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || |
2854 | (skb->priority != TC_PRIO_CONTROL)) { | |
fd0a05ce JB |
2855 | tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; |
2856 | tx_flags |= (skb->priority & 0x7) << | |
2857 | I40E_TX_FLAGS_VLAN_PRIO_SHIFT; | |
2858 | if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { | |
2859 | struct vlan_ethhdr *vhdr; | |
dd225bc6 FR |
2860 | int rc; |
2861 | ||
2862 | rc = skb_cow_head(skb, 0); | |
2863 | if (rc < 0) | |
2864 | return rc; | |
fd0a05ce JB |
2865 | vhdr = (struct vlan_ethhdr *)skb->data; |
2866 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
2867 | I40E_TX_FLAGS_VLAN_SHIFT); | |
2868 | } else { | |
2869 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; | |
2870 | } | |
2871 | } | |
d40d00b1 NP |
2872 | |
2873 | out: | |
fd0a05ce JB |
2874 | *flags = tx_flags; |
2875 | return 0; | |
2876 | } | |
2877 | ||
fd0a05ce JB |
2878 | /** |
2879 | * i40e_tso - set up the tso context descriptor | |
52ea3e80 | 2880 | * @first: pointer to first Tx buffer for xmit |
fd0a05ce | 2881 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 2882 | * @cd_type_cmd_tso_mss: Quad Word 1 |
fd0a05ce JB |
2883 | * |
2884 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
2885 | **/ | |
52ea3e80 AD |
2886 | static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, |
2887 | u64 *cd_type_cmd_tso_mss) | |
fd0a05ce | 2888 | { |
52ea3e80 | 2889 | struct sk_buff *skb = first->skb; |
03f9d6a5 | 2890 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
2891 | union { |
2892 | struct iphdr *v4; | |
2893 | struct ipv6hdr *v6; | |
2894 | unsigned char *hdr; | |
2895 | } ip; | |
c49a7bc3 AD |
2896 | union { |
2897 | struct tcphdr *tcp; | |
5453205c | 2898 | struct udphdr *udp; |
c49a7bc3 AD |
2899 | unsigned char *hdr; |
2900 | } l4; | |
2901 | u32 paylen, l4_offset; | |
52ea3e80 | 2902 | u16 gso_segs, gso_size; |
fd0a05ce | 2903 | int err; |
fd0a05ce | 2904 | |
e9f6563d SN |
2905 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2906 | return 0; | |
2907 | ||
fd0a05ce JB |
2908 | if (!skb_is_gso(skb)) |
2909 | return 0; | |
2910 | ||
dd225bc6 FR |
2911 | err = skb_cow_head(skb, 0); |
2912 | if (err < 0) | |
2913 | return err; | |
fd0a05ce | 2914 | |
c777019a AD |
2915 | ip.hdr = skb_network_header(skb); |
2916 | l4.hdr = skb_transport_header(skb); | |
df23075f | 2917 | |
c777019a AD |
2918 | /* initialize outer IP header fields */ |
2919 | if (ip.v4->version == 4) { | |
2920 | ip.v4->tot_len = 0; | |
2921 | ip.v4->check = 0; | |
c49a7bc3 | 2922 | } else { |
c777019a AD |
2923 | ip.v6->payload_len = 0; |
2924 | } | |
2925 | ||
577389a5 | 2926 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 2927 | SKB_GSO_GRE_CSUM | |
7e13318d | 2928 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 2929 | SKB_GSO_IPXIP6 | |
577389a5 | 2930 | SKB_GSO_UDP_TUNNEL | |
5453205c | 2931 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
2932 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
2933 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
2934 | l4.udp->len = 0; | |
2935 | ||
5453205c AD |
2936 | /* determine offset of outer transport header */ |
2937 | l4_offset = l4.hdr - skb->data; | |
2938 | ||
2939 | /* remove payload length from outer checksum */ | |
24d41e5e | 2940 | paylen = skb->len - l4_offset; |
b9c015d4 JK |
2941 | csum_replace_by_diff(&l4.udp->check, |
2942 | (__force __wsum)htonl(paylen)); | |
5453205c AD |
2943 | } |
2944 | ||
c777019a AD |
2945 | /* reset pointers to inner headers */ |
2946 | ip.hdr = skb_inner_network_header(skb); | |
2947 | l4.hdr = skb_inner_transport_header(skb); | |
2948 | ||
2949 | /* initialize inner IP header fields */ | |
2950 | if (ip.v4->version == 4) { | |
2951 | ip.v4->tot_len = 0; | |
2952 | ip.v4->check = 0; | |
2953 | } else { | |
2954 | ip.v6->payload_len = 0; | |
2955 | } | |
fd0a05ce JB |
2956 | } |
2957 | ||
c49a7bc3 AD |
2958 | /* determine offset of inner transport header */ |
2959 | l4_offset = l4.hdr - skb->data; | |
2960 | ||
2961 | /* remove payload length from inner checksum */ | |
24d41e5e | 2962 | paylen = skb->len - l4_offset; |
c49a7bc3 | 2963 | |
3fd8ed56 JH |
2964 | if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { |
2965 | csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen)); | |
2966 | /* compute length of segmentation header */ | |
2967 | *hdr_len = sizeof(*l4.udp) + l4_offset; | |
2968 | } else { | |
2969 | csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); | |
2970 | /* compute length of segmentation header */ | |
2971 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
2972 | } | |
fd0a05ce | 2973 | |
52ea3e80 AD |
2974 | /* pull values out of skb_shinfo */ |
2975 | gso_size = skb_shinfo(skb)->gso_size; | |
2976 | gso_segs = skb_shinfo(skb)->gso_segs; | |
2977 | ||
2978 | /* update GSO size and bytecount with header size */ | |
2979 | first->gso_segs = gso_segs; | |
2980 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
2981 | ||
fd0a05ce JB |
2982 | /* find the field values */ |
2983 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
2984 | cd_tso_len = skb->len - *hdr_len; | |
52ea3e80 | 2985 | cd_mss = gso_size; |
03f9d6a5 AD |
2986 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
2987 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
2988 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
fd0a05ce JB |
2989 | return 1; |
2990 | } | |
2991 | ||
beb0dff1 JK |
2992 | /** |
2993 | * i40e_tsyn - set up the tsyn context descriptor | |
2994 | * @tx_ring: ptr to the ring to send | |
2995 | * @skb: ptr to the skb we're sending | |
2996 | * @tx_flags: the collected send information | |
9c883bd3 | 2997 | * @cd_type_cmd_tso_mss: Quad Word 1 |
beb0dff1 JK |
2998 | * |
2999 | * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen | |
3000 | **/ | |
3001 | static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
3002 | u32 tx_flags, u64 *cd_type_cmd_tso_mss) | |
3003 | { | |
3004 | struct i40e_pf *pf; | |
3005 | ||
3006 | if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) | |
3007 | return 0; | |
3008 | ||
3009 | /* Tx timestamps cannot be sampled when doing TSO */ | |
3010 | if (tx_flags & I40E_TX_FLAGS_TSO) | |
3011 | return 0; | |
3012 | ||
3013 | /* only timestamp the outbound packet if the user has requested it and | |
3014 | * we are not already transmitting a packet to be timestamped | |
3015 | */ | |
3016 | pf = i40e_netdev_to_pf(tx_ring->netdev); | |
22b4777d JK |
3017 | if (!(pf->flags & I40E_FLAG_PTP)) |
3018 | return 0; | |
3019 | ||
9ce34f02 | 3020 | if (pf->ptp_tx && |
0da36b97 | 3021 | !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) { |
beb0dff1 | 3022 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
0bc0706b | 3023 | pf->ptp_tx_start = jiffies; |
beb0dff1 JK |
3024 | pf->ptp_tx_skb = skb_get(skb); |
3025 | } else { | |
2955faca | 3026 | pf->tx_hwtstamp_skipped++; |
beb0dff1 JK |
3027 | return 0; |
3028 | } | |
3029 | ||
3030 | *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << | |
3031 | I40E_TXD_CTX_QW1_CMD_SHIFT; | |
3032 | ||
beb0dff1 JK |
3033 | return 1; |
3034 | } | |
3035 | ||
fd0a05ce JB |
3036 | /** |
3037 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
3038 | * @skb: send buffer | |
89232c3b | 3039 | * @tx_flags: pointer to Tx flags currently set |
fd0a05ce JB |
3040 | * @td_cmd: Tx descriptor command bits to set |
3041 | * @td_offset: Tx descriptor header offsets to set | |
554f4544 | 3042 | * @tx_ring: Tx descriptor ring |
fd0a05ce JB |
3043 | * @cd_tunneling: ptr to context desc bits |
3044 | **/ | |
529f1f65 AD |
3045 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
3046 | u32 *td_cmd, u32 *td_offset, | |
3047 | struct i40e_ring *tx_ring, | |
3048 | u32 *cd_tunneling) | |
fd0a05ce | 3049 | { |
b96b78f2 AD |
3050 | union { |
3051 | struct iphdr *v4; | |
3052 | struct ipv6hdr *v6; | |
3053 | unsigned char *hdr; | |
3054 | } ip; | |
3055 | union { | |
3056 | struct tcphdr *tcp; | |
3057 | struct udphdr *udp; | |
3058 | unsigned char *hdr; | |
3059 | } l4; | |
a3fd9d88 | 3060 | unsigned char *exthdr; |
d1bd743b | 3061 | u32 offset, cmd = 0; |
a3fd9d88 | 3062 | __be16 frag_off; |
b96b78f2 AD |
3063 | u8 l4_proto = 0; |
3064 | ||
529f1f65 AD |
3065 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
3066 | return 0; | |
3067 | ||
b96b78f2 AD |
3068 | ip.hdr = skb_network_header(skb); |
3069 | l4.hdr = skb_transport_header(skb); | |
fd0a05ce | 3070 | |
475b4205 AD |
3071 | /* compute outer L2 header size */ |
3072 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
3073 | ||
fd0a05ce | 3074 | if (skb->encapsulation) { |
d1bd743b | 3075 | u32 tunnel = 0; |
a0064728 AD |
3076 | /* define outer network header type */ |
3077 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
3078 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
3079 | I40E_TX_CTX_EXT_IP_IPV4 : | |
3080 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
3081 | ||
a0064728 AD |
3082 | l4_proto = ip.v4->protocol; |
3083 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 3084 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
3085 | |
3086 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 3087 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
3088 | if (l4.hdr != exthdr) |
3089 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
3090 | &l4_proto, &frag_off); | |
a0064728 AD |
3091 | } |
3092 | ||
3093 | /* define outer transport */ | |
3094 | switch (l4_proto) { | |
45991204 | 3095 | case IPPROTO_UDP: |
475b4205 | 3096 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
6a899024 | 3097 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
45991204 | 3098 | break; |
c1d1791d | 3099 | case IPPROTO_GRE: |
475b4205 | 3100 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 | 3101 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
c1d1791d | 3102 | break; |
577389a5 AD |
3103 | case IPPROTO_IPIP: |
3104 | case IPPROTO_IPV6: | |
3105 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; | |
3106 | l4.hdr = skb_inner_network_header(skb); | |
3107 | break; | |
45991204 | 3108 | default: |
529f1f65 AD |
3109 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
3110 | return -1; | |
3111 | ||
3112 | skb_checksum_help(skb); | |
3113 | return 0; | |
45991204 | 3114 | } |
b96b78f2 | 3115 | |
577389a5 AD |
3116 | /* compute outer L3 header size */ |
3117 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
3118 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
3119 | ||
3120 | /* switch IP header pointer from outer to inner header */ | |
3121 | ip.hdr = skb_inner_network_header(skb); | |
3122 | ||
475b4205 AD |
3123 | /* compute tunnel header size */ |
3124 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
3125 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
3126 | ||
5453205c AD |
3127 | /* indicate if we need to offload outer UDP header */ |
3128 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 3129 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
3130 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
3131 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
3132 | ||
475b4205 AD |
3133 | /* record tunnel offload values */ |
3134 | *cd_tunneling |= tunnel; | |
3135 | ||
b96b78f2 | 3136 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 3137 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 3138 | l4_proto = 0; |
fd0a05ce | 3139 | |
a0064728 AD |
3140 | /* reset type as we transition from outer to inner headers */ |
3141 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
3142 | if (ip.v4->version == 4) | |
3143 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
3144 | if (ip.v6->version == 6) | |
89232c3b | 3145 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
fd0a05ce JB |
3146 | } |
3147 | ||
3148 | /* Enable IP checksum offloads */ | |
89232c3b | 3149 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 3150 | l4_proto = ip.v4->protocol; |
fd0a05ce JB |
3151 | /* the stack computes the IP header already, the only time we |
3152 | * need the hardware to recompute it is in the case of TSO. | |
3153 | */ | |
475b4205 AD |
3154 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
3155 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
3156 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 3157 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 3158 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
3159 | |
3160 | exthdr = ip.hdr + sizeof(*ip.v6); | |
3161 | l4_proto = ip.v6->nexthdr; | |
3162 | if (l4.hdr != exthdr) | |
3163 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
3164 | &l4_proto, &frag_off); | |
fd0a05ce | 3165 | } |
b96b78f2 | 3166 | |
475b4205 AD |
3167 | /* compute inner L3 header size */ |
3168 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
fd0a05ce JB |
3169 | |
3170 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 3171 | switch (l4_proto) { |
fd0a05ce JB |
3172 | case IPPROTO_TCP: |
3173 | /* enable checksum offloads */ | |
475b4205 AD |
3174 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
3175 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
3176 | break; |
3177 | case IPPROTO_SCTP: | |
3178 | /* enable SCTP checksum offload */ | |
475b4205 AD |
3179 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
3180 | offset |= (sizeof(struct sctphdr) >> 2) << | |
3181 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
3182 | break; |
3183 | case IPPROTO_UDP: | |
3184 | /* enable UDP checksum offload */ | |
475b4205 AD |
3185 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
3186 | offset |= (sizeof(struct udphdr) >> 2) << | |
3187 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
3188 | break; |
3189 | default: | |
529f1f65 AD |
3190 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
3191 | return -1; | |
3192 | skb_checksum_help(skb); | |
3193 | return 0; | |
fd0a05ce | 3194 | } |
475b4205 AD |
3195 | |
3196 | *td_cmd |= cmd; | |
3197 | *td_offset |= offset; | |
529f1f65 AD |
3198 | |
3199 | return 1; | |
fd0a05ce JB |
3200 | } |
3201 | ||
3202 | /** | |
3203 | * i40e_create_tx_ctx Build the Tx context descriptor | |
3204 | * @tx_ring: ring to create the descriptor on | |
3205 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
3206 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
3207 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
3208 | **/ | |
3209 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
3210 | const u64 cd_type_cmd_tso_mss, | |
3211 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
3212 | { | |
3213 | struct i40e_tx_context_desc *context_desc; | |
fc4ac67b | 3214 | int i = tx_ring->next_to_use; |
fd0a05ce | 3215 | |
ff40dd5d JB |
3216 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
3217 | !cd_tunneling && !cd_l2tag2) | |
fd0a05ce JB |
3218 | return; |
3219 | ||
3220 | /* grab the next descriptor */ | |
fc4ac67b AD |
3221 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); |
3222 | ||
3223 | i++; | |
3224 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
3225 | |
3226 | /* cpu_to_le32 and assign to struct fields */ | |
3227 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
3228 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 3229 | context_desc->rsvd = cpu_to_le16(0); |
fd0a05ce JB |
3230 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
3231 | } | |
3232 | ||
4567dc10 ED |
3233 | /** |
3234 | * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions | |
3235 | * @tx_ring: the ring to be checked | |
3236 | * @size: the size buffer we want to assure is available | |
3237 | * | |
3238 | * Returns -EBUSY if a stop is needed, else 0 | |
3239 | **/ | |
4ec441df | 3240 | int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
4567dc10 ED |
3241 | { |
3242 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
3243 | /* Memory barrier before checking head and tail */ | |
3244 | smp_mb(); | |
3245 | ||
3246 | /* Check again in a case another CPU has just made room available. */ | |
3247 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
3248 | return -EBUSY; | |
3249 | ||
3250 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
3251 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
3252 | ++tx_ring->tx_stats.restart_queue; | |
3253 | return 0; | |
3254 | } | |
3255 | ||
71da6197 | 3256 | /** |
3f3f7cb8 | 3257 | * __i40e_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 3258 | * @skb: send buffer |
71da6197 | 3259 | * |
3f3f7cb8 AD |
3260 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
3261 | * and so we need to figure out the cases where we need to linearize the skb. | |
3262 | * | |
3263 | * For TSO we need to count the TSO header and segment payload separately. | |
3264 | * As such we need to check cases where we have 7 fragments or more as we | |
3265 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
3266 | * the segment payload in the first descriptor, and another 7 for the | |
3267 | * fragments. | |
71da6197 | 3268 | **/ |
2d37490b | 3269 | bool __i40e_chk_linearize(struct sk_buff *skb) |
71da6197 | 3270 | { |
d7840976 | 3271 | const skb_frag_t *frag, *stale; |
3f3f7cb8 | 3272 | int nr_frags, sum; |
71da6197 | 3273 | |
3f3f7cb8 | 3274 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 3275 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 3276 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 3277 | return false; |
71da6197 | 3278 | |
2d37490b | 3279 | /* We need to walk through the list and validate that each group |
841493a3 | 3280 | * of 6 fragments totals at least gso_size. |
2d37490b | 3281 | */ |
3f3f7cb8 | 3282 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
3283 | frag = &skb_shinfo(skb)->frags[0]; |
3284 | ||
3285 | /* Initialize size to the negative value of gso_size minus 1. We | |
3286 | * use this as the worst case scenerio in which the frag ahead | |
3287 | * of us only provides one byte which is why we are limited to 6 | |
3288 | * descriptors for a single transmit as the header and previous | |
3289 | * fragment are already consuming 2 descriptors. | |
3290 | */ | |
3f3f7cb8 | 3291 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 3292 | |
3f3f7cb8 AD |
3293 | /* Add size of frags 0 through 4 to create our initial sum */ |
3294 | sum += skb_frag_size(frag++); | |
3295 | sum += skb_frag_size(frag++); | |
3296 | sum += skb_frag_size(frag++); | |
3297 | sum += skb_frag_size(frag++); | |
3298 | sum += skb_frag_size(frag++); | |
2d37490b AD |
3299 | |
3300 | /* Walk through fragments adding latest fragment, testing it, and | |
3301 | * then removing stale fragments from the sum. | |
3302 | */ | |
248de22e AD |
3303 | for (stale = &skb_shinfo(skb)->frags[0];; stale++) { |
3304 | int stale_size = skb_frag_size(stale); | |
3305 | ||
3f3f7cb8 | 3306 | sum += skb_frag_size(frag++); |
2d37490b | 3307 | |
248de22e AD |
3308 | /* The stale fragment may present us with a smaller |
3309 | * descriptor than the actual fragment size. To account | |
3310 | * for that we need to remove all the data on the front and | |
3311 | * figure out what the remainder would be in the last | |
3312 | * descriptor associated with the fragment. | |
3313 | */ | |
3314 | if (stale_size > I40E_MAX_DATA_PER_TXD) { | |
b54c9d5b | 3315 | int align_pad = -(skb_frag_off(stale)) & |
248de22e AD |
3316 | (I40E_MAX_READ_REQ_SIZE - 1); |
3317 | ||
3318 | sum -= align_pad; | |
3319 | stale_size -= align_pad; | |
3320 | ||
3321 | do { | |
3322 | sum -= I40E_MAX_DATA_PER_TXD_ALIGNED; | |
3323 | stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED; | |
3324 | } while (stale_size > I40E_MAX_DATA_PER_TXD); | |
3325 | } | |
3326 | ||
2d37490b AD |
3327 | /* if sum is negative we failed to make sufficient progress */ |
3328 | if (sum < 0) | |
3329 | return true; | |
3330 | ||
841493a3 | 3331 | if (!nr_frags--) |
2d37490b AD |
3332 | break; |
3333 | ||
248de22e | 3334 | sum -= stale_size; |
71da6197 AS |
3335 | } |
3336 | ||
2d37490b | 3337 | return false; |
71da6197 AS |
3338 | } |
3339 | ||
fd0a05ce JB |
3340 | /** |
3341 | * i40e_tx_map - Build the Tx descriptor | |
3342 | * @tx_ring: ring to send buffer on | |
3343 | * @skb: send buffer | |
3344 | * @first: first buffer info buffer to use | |
3345 | * @tx_flags: collected send information | |
3346 | * @hdr_len: size of the packet header | |
3347 | * @td_cmd: the command field in the descriptor | |
3348 | * @td_offset: offset for checksum or crc | |
69077577 JK |
3349 | * |
3350 | * Returns 0 on success, -1 on failure to DMA | |
fd0a05ce | 3351 | **/ |
69077577 JK |
3352 | static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
3353 | struct i40e_tx_buffer *first, u32 tx_flags, | |
3354 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
fd0a05ce | 3355 | { |
fd0a05ce JB |
3356 | unsigned int data_len = skb->data_len; |
3357 | unsigned int size = skb_headlen(skb); | |
d7840976 | 3358 | skb_frag_t *frag; |
fd0a05ce JB |
3359 | struct i40e_tx_buffer *tx_bi; |
3360 | struct i40e_tx_desc *tx_desc; | |
a5e9c572 | 3361 | u16 i = tx_ring->next_to_use; |
fd0a05ce JB |
3362 | u32 td_tag = 0; |
3363 | dma_addr_t dma; | |
1dc8b538 | 3364 | u16 desc_count = 1; |
fd0a05ce | 3365 | |
fd0a05ce JB |
3366 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { |
3367 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
3368 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
3369 | I40E_TX_FLAGS_VLAN_SHIFT; | |
3370 | } | |
3371 | ||
a5e9c572 AD |
3372 | first->tx_flags = tx_flags; |
3373 | ||
3374 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
3375 | ||
fd0a05ce | 3376 | tx_desc = I40E_TX_DESC(tx_ring, i); |
a5e9c572 AD |
3377 | tx_bi = first; |
3378 | ||
3379 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
3380 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
3381 | ||
a5e9c572 AD |
3382 | if (dma_mapping_error(tx_ring->dev, dma)) |
3383 | goto dma_error; | |
3384 | ||
3385 | /* record length, and DMA address */ | |
3386 | dma_unmap_len_set(tx_bi, len, size); | |
3387 | dma_unmap_addr_set(tx_bi, dma, dma); | |
3388 | ||
5c4654da AD |
3389 | /* align size to end of page */ |
3390 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
a5e9c572 AD |
3391 | tx_desc->buffer_addr = cpu_to_le64(dma); |
3392 | ||
3393 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
fd0a05ce JB |
3394 | tx_desc->cmd_type_offset_bsz = |
3395 | build_ctob(td_cmd, td_offset, | |
5c4654da | 3396 | max_data, td_tag); |
fd0a05ce | 3397 | |
fd0a05ce JB |
3398 | tx_desc++; |
3399 | i++; | |
58044743 AS |
3400 | desc_count++; |
3401 | ||
fd0a05ce JB |
3402 | if (i == tx_ring->count) { |
3403 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3404 | i = 0; | |
3405 | } | |
fd0a05ce | 3406 | |
5c4654da AD |
3407 | dma += max_data; |
3408 | size -= max_data; | |
fd0a05ce | 3409 | |
5c4654da | 3410 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
a5e9c572 AD |
3411 | tx_desc->buffer_addr = cpu_to_le64(dma); |
3412 | } | |
fd0a05ce JB |
3413 | |
3414 | if (likely(!data_len)) | |
3415 | break; | |
3416 | ||
a5e9c572 AD |
3417 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, |
3418 | size, td_tag); | |
fd0a05ce JB |
3419 | |
3420 | tx_desc++; | |
3421 | i++; | |
58044743 AS |
3422 | desc_count++; |
3423 | ||
fd0a05ce JB |
3424 | if (i == tx_ring->count) { |
3425 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3426 | i = 0; | |
3427 | } | |
3428 | ||
a5e9c572 AD |
3429 | size = skb_frag_size(frag); |
3430 | data_len -= size; | |
fd0a05ce | 3431 | |
a5e9c572 AD |
3432 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
3433 | DMA_TO_DEVICE); | |
fd0a05ce | 3434 | |
a5e9c572 AD |
3435 | tx_bi = &tx_ring->tx_bi[i]; |
3436 | } | |
fd0a05ce | 3437 | |
1dc8b538 | 3438 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
a5e9c572 AD |
3439 | |
3440 | i++; | |
3441 | if (i == tx_ring->count) | |
3442 | i = 0; | |
3443 | ||
3444 | tx_ring->next_to_use = i; | |
3445 | ||
4567dc10 | 3446 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
58044743 | 3447 | |
1dc8b538 AD |
3448 | /* write last descriptor with EOP bit */ |
3449 | td_cmd |= I40E_TX_DESC_CMD_EOP; | |
3450 | ||
a5340d93 JK |
3451 | /* We OR these values together to check both against 4 (WB_STRIDE) |
3452 | * below. This is safe since we don't re-use desc_count afterwards. | |
1dc8b538 AD |
3453 | */ |
3454 | desc_count |= ++tx_ring->packet_stride; | |
3455 | ||
a5340d93 | 3456 | if (desc_count >= WB_STRIDE) { |
1dc8b538 AD |
3457 | /* write last descriptor with RS bit set */ |
3458 | td_cmd |= I40E_TX_DESC_CMD_RS; | |
58044743 | 3459 | tx_ring->packet_stride = 0; |
58044743 | 3460 | } |
58044743 AS |
3461 | |
3462 | tx_desc->cmd_type_offset_bsz = | |
1dc8b538 AD |
3463 | build_ctob(td_cmd, td_offset, size, td_tag); |
3464 | ||
a9e51058 JK |
3465 | skb_tx_timestamp(skb); |
3466 | ||
1dc8b538 AD |
3467 | /* Force memory writes to complete before letting h/w know there |
3468 | * are new descriptors to fetch. | |
3469 | * | |
3470 | * We also use this memory barrier to make certain all of the | |
3471 | * status bits have been updated before next_to_watch is written. | |
3472 | */ | |
3473 | wmb(); | |
3474 | ||
3475 | /* set next_to_watch value indicating a packet is present */ | |
3476 | first->next_to_watch = tx_desc; | |
58044743 | 3477 | |
a5e9c572 | 3478 | /* notify HW of packet */ |
6b16f9ee | 3479 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { |
58044743 AS |
3480 | writel(i, tx_ring->tail); |
3481 | } | |
1dc8b538 | 3482 | |
69077577 | 3483 | return 0; |
fd0a05ce JB |
3484 | |
3485 | dma_error: | |
a5e9c572 | 3486 | dev_info(tx_ring->dev, "TX DMA map failed\n"); |
fd0a05ce JB |
3487 | |
3488 | /* clear dma mappings for failed tx_bi map */ | |
3489 | for (;;) { | |
3490 | tx_bi = &tx_ring->tx_bi[i]; | |
a5e9c572 | 3491 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); |
fd0a05ce JB |
3492 | if (tx_bi == first) |
3493 | break; | |
3494 | if (i == 0) | |
3495 | i = tx_ring->count; | |
3496 | i--; | |
3497 | } | |
3498 | ||
fd0a05ce | 3499 | tx_ring->next_to_use = i; |
69077577 JK |
3500 | |
3501 | return -1; | |
fd0a05ce JB |
3502 | } |
3503 | ||
74608d17 BT |
3504 | /** |
3505 | * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring | |
3506 | * @xdp: data to transmit | |
3507 | * @xdp_ring: XDP Tx ring | |
3508 | **/ | |
44fa2dbd | 3509 | static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, |
74608d17 BT |
3510 | struct i40e_ring *xdp_ring) |
3511 | { | |
74608d17 BT |
3512 | u16 i = xdp_ring->next_to_use; |
3513 | struct i40e_tx_buffer *tx_bi; | |
3514 | struct i40e_tx_desc *tx_desc; | |
8554768c | 3515 | void *data = xdpf->data; |
44fa2dbd | 3516 | u32 size = xdpf->len; |
74608d17 BT |
3517 | dma_addr_t dma; |
3518 | ||
3519 | if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) { | |
3520 | xdp_ring->tx_stats.tx_busy++; | |
3521 | return I40E_XDP_CONSUMED; | |
3522 | } | |
8554768c | 3523 | dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE); |
74608d17 BT |
3524 | if (dma_mapping_error(xdp_ring->dev, dma)) |
3525 | return I40E_XDP_CONSUMED; | |
3526 | ||
3527 | tx_bi = &xdp_ring->tx_bi[i]; | |
3528 | tx_bi->bytecount = size; | |
3529 | tx_bi->gso_segs = 1; | |
b411ef11 | 3530 | tx_bi->xdpf = xdpf; |
74608d17 BT |
3531 | |
3532 | /* record length, and DMA address */ | |
3533 | dma_unmap_len_set(tx_bi, len, size); | |
3534 | dma_unmap_addr_set(tx_bi, dma, dma); | |
3535 | ||
3536 | tx_desc = I40E_TX_DESC(xdp_ring, i); | |
3537 | tx_desc->buffer_addr = cpu_to_le64(dma); | |
3538 | tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC | |
3539 | | I40E_TXD_CMD, | |
3540 | 0, size, 0); | |
3541 | ||
3542 | /* Make certain all of the status bits have been updated | |
3543 | * before next_to_watch is written. | |
3544 | */ | |
3545 | smp_wmb(); | |
3546 | ||
3547 | i++; | |
3548 | if (i == xdp_ring->count) | |
3549 | i = 0; | |
3550 | ||
3551 | tx_bi->next_to_watch = tx_desc; | |
3552 | xdp_ring->next_to_use = i; | |
3553 | ||
3554 | return I40E_XDP_TX; | |
3555 | } | |
3556 | ||
fd0a05ce JB |
3557 | /** |
3558 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
3559 | * @skb: send buffer | |
3560 | * @tx_ring: ring to send buffer on | |
3561 | * | |
3562 | * Returns NETDEV_TX_OK if sent, else an error code | |
3563 | **/ | |
3564 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
3565 | struct i40e_ring *tx_ring) | |
3566 | { | |
3567 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
3568 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
3569 | struct i40e_tx_buffer *first; | |
3570 | u32 td_offset = 0; | |
3571 | u32 tx_flags = 0; | |
3572 | __be16 protocol; | |
3573 | u32 td_cmd = 0; | |
3574 | u8 hdr_len = 0; | |
4ec441df | 3575 | int tso, count; |
beb0dff1 | 3576 | int tsyn; |
6995b36c | 3577 | |
b74118f0 JB |
3578 | /* prefetch the data, we'll need it later */ |
3579 | prefetch(skb->data); | |
3580 | ||
ed0980c4 SP |
3581 | i40e_trace(xmit_frame_ring, skb, tx_ring); |
3582 | ||
4ec441df | 3583 | count = i40e_xmit_descriptor_count(skb); |
2d37490b | 3584 | if (i40e_chk_linearize(skb, count)) { |
52ea3e80 AD |
3585 | if (__skb_linearize(skb)) { |
3586 | dev_kfree_skb_any(skb); | |
3587 | return NETDEV_TX_OK; | |
3588 | } | |
5c4654da | 3589 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
3590 | tx_ring->tx_stats.tx_linearize++; |
3591 | } | |
4ec441df AD |
3592 | |
3593 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
3594 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
3595 | * + 4 desc gap to avoid the cache line where head is, | |
3596 | * + 1 desc for context descriptor, | |
3597 | * otherwise try next time | |
3598 | */ | |
3599 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
3600 | tx_ring->tx_stats.tx_busy++; | |
fd0a05ce | 3601 | return NETDEV_TX_BUSY; |
4ec441df | 3602 | } |
fd0a05ce | 3603 | |
52ea3e80 AD |
3604 | /* record the location of the first descriptor for this packet */ |
3605 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
3606 | first->skb = skb; | |
3607 | first->bytecount = skb->len; | |
3608 | first->gso_segs = 1; | |
3609 | ||
fd0a05ce JB |
3610 | /* prepare the xmit flags */ |
3611 | if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) | |
3612 | goto out_drop; | |
3613 | ||
3614 | /* obtain protocol of skb */ | |
3d34dd03 | 3615 | protocol = vlan_get_protocol(skb); |
fd0a05ce | 3616 | |
fd0a05ce | 3617 | /* setup IPv4/IPv6 offloads */ |
0e2fe46c | 3618 | if (protocol == htons(ETH_P_IP)) |
fd0a05ce | 3619 | tx_flags |= I40E_TX_FLAGS_IPV4; |
0e2fe46c | 3620 | else if (protocol == htons(ETH_P_IPV6)) |
fd0a05ce JB |
3621 | tx_flags |= I40E_TX_FLAGS_IPV6; |
3622 | ||
52ea3e80 | 3623 | tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); |
fd0a05ce JB |
3624 | |
3625 | if (tso < 0) | |
3626 | goto out_drop; | |
3627 | else if (tso) | |
3628 | tx_flags |= I40E_TX_FLAGS_TSO; | |
3629 | ||
3bc67973 AD |
3630 | /* Always offload the checksum, since it's in the data descriptor */ |
3631 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, | |
3632 | tx_ring, &cd_tunneling); | |
3633 | if (tso < 0) | |
3634 | goto out_drop; | |
3635 | ||
beb0dff1 JK |
3636 | tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); |
3637 | ||
3638 | if (tsyn) | |
3639 | tx_flags |= I40E_TX_FLAGS_TSYN; | |
3640 | ||
b1941306 AD |
3641 | /* always enable CRC insertion offload */ |
3642 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
3643 | ||
fd0a05ce JB |
3644 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
3645 | cd_tunneling, cd_l2tag2); | |
3646 | ||
3647 | /* Add Flow Director ATR if it's enabled. | |
3648 | * | |
3649 | * NOTE: this must always be directly before the data descriptor. | |
3650 | */ | |
6b037cd4 | 3651 | i40e_atr(tx_ring, skb, tx_flags); |
fd0a05ce | 3652 | |
69077577 JK |
3653 | if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, |
3654 | td_cmd, td_offset)) | |
3655 | goto cleanup_tx_tstamp; | |
fd0a05ce | 3656 | |
fd0a05ce JB |
3657 | return NETDEV_TX_OK; |
3658 | ||
3659 | out_drop: | |
ed0980c4 | 3660 | i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); |
52ea3e80 AD |
3661 | dev_kfree_skb_any(first->skb); |
3662 | first->skb = NULL; | |
69077577 JK |
3663 | cleanup_tx_tstamp: |
3664 | if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) { | |
3665 | struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev); | |
3666 | ||
3667 | dev_kfree_skb_any(pf->ptp_tx_skb); | |
3668 | pf->ptp_tx_skb = NULL; | |
3669 | clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); | |
3670 | } | |
3671 | ||
fd0a05ce JB |
3672 | return NETDEV_TX_OK; |
3673 | } | |
3674 | ||
3675 | /** | |
3676 | * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
3677 | * @skb: send buffer | |
3678 | * @netdev: network interface device structure | |
3679 | * | |
3680 | * Returns NETDEV_TX_OK if sent, else an error code | |
3681 | **/ | |
3682 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
3683 | { | |
3684 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
3685 | struct i40e_vsi *vsi = np->vsi; | |
9f65e15b | 3686 | struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; |
fd0a05ce JB |
3687 | |
3688 | /* hardware can't handle really short frames, hardware padding works | |
3689 | * beyond this point | |
3690 | */ | |
a94d9e22 AD |
3691 | if (skb_put_padto(skb, I40E_MIN_TX_LEN)) |
3692 | return NETDEV_TX_OK; | |
fd0a05ce JB |
3693 | |
3694 | return i40e_xmit_frame_ring(skb, tx_ring); | |
3695 | } | |
d9314c47 BT |
3696 | |
3697 | /** | |
3698 | * i40e_xdp_xmit - Implements ndo_xdp_xmit | |
3699 | * @dev: netdev | |
3700 | * @xdp: XDP buffer | |
3701 | * | |
735fc405 JDB |
3702 | * Returns number of frames successfully sent. Frames that fail are |
3703 | * free'ed via XDP return API. | |
3704 | * | |
3705 | * For error cases, a negative errno code is returned and no-frames | |
3706 | * are transmitted (caller must handle freeing frames). | |
d9314c47 | 3707 | **/ |
42b33468 JDB |
3708 | int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, |
3709 | u32 flags) | |
d9314c47 BT |
3710 | { |
3711 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
3712 | unsigned int queue_index = smp_processor_id(); | |
3713 | struct i40e_vsi *vsi = np->vsi; | |
59eb2a88 | 3714 | struct i40e_pf *pf = vsi->back; |
cdb57ed0 | 3715 | struct i40e_ring *xdp_ring; |
735fc405 JDB |
3716 | int drops = 0; |
3717 | int i; | |
d9314c47 BT |
3718 | |
3719 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) | |
3720 | return -ENETDOWN; | |
3721 | ||
59eb2a88 BT |
3722 | if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs || |
3723 | test_bit(__I40E_CONFIG_BUSY, pf->state)) | |
d9314c47 BT |
3724 | return -ENXIO; |
3725 | ||
cdb57ed0 | 3726 | if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) |
42b33468 JDB |
3727 | return -EINVAL; |
3728 | ||
cdb57ed0 JDB |
3729 | xdp_ring = vsi->xdp_rings[queue_index]; |
3730 | ||
735fc405 JDB |
3731 | for (i = 0; i < n; i++) { |
3732 | struct xdp_frame *xdpf = frames[i]; | |
3733 | int err; | |
d9314c47 | 3734 | |
cdb57ed0 | 3735 | err = i40e_xmit_xdp_ring(xdpf, xdp_ring); |
735fc405 JDB |
3736 | if (err != I40E_XDP_TX) { |
3737 | xdp_return_frame_rx_napi(xdpf); | |
3738 | drops++; | |
3739 | } | |
3740 | } | |
3741 | ||
cdb57ed0 JDB |
3742 | if (unlikely(flags & XDP_XMIT_FLUSH)) |
3743 | i40e_xdp_ring_update_tail(xdp_ring); | |
d9314c47 | 3744 | |
735fc405 | 3745 | return n - drops; |
d9314c47 | 3746 | } |