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fd0a05ce JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
fd0a05ce JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
fd0a05ce JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
1c112a64 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
fd0a05ce | 29 | #include "i40e.h" |
ed0980c4 | 30 | #include "i40e_trace.h" |
206812b5 | 31 | #include "i40e_prototype.h" |
fd0a05ce JB |
32 | |
33 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
34 | u32 td_tag) | |
35 | { | |
36 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
37 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
38 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
39 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
40 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
41 | } | |
42 | ||
eaefbd06 | 43 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) |
5e02f283 AD |
44 | /** |
45 | * i40e_fdir - Generate a Flow Director descriptor based on fdata | |
46 | * @tx_ring: Tx ring to send buffer on | |
47 | * @fdata: Flow director filter data | |
48 | * @add: Indicate if we are adding a rule or deleting one | |
49 | * | |
50 | **/ | |
51 | static void i40e_fdir(struct i40e_ring *tx_ring, | |
52 | struct i40e_fdir_filter *fdata, bool add) | |
53 | { | |
54 | struct i40e_filter_program_desc *fdir_desc; | |
55 | struct i40e_pf *pf = tx_ring->vsi->back; | |
56 | u32 flex_ptype, dtype_cmd; | |
57 | u16 i; | |
58 | ||
59 | /* grab the next descriptor */ | |
60 | i = tx_ring->next_to_use; | |
61 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
62 | ||
63 | i++; | |
64 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
65 | ||
66 | flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & | |
67 | (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); | |
68 | ||
69 | flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & | |
70 | (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); | |
71 | ||
72 | flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & | |
73 | (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
74 | ||
0e588de1 JK |
75 | flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & |
76 | (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); | |
77 | ||
5e02f283 AD |
78 | /* Use LAN VSI Id if not programmed by user */ |
79 | flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & | |
80 | ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << | |
81 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); | |
82 | ||
83 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
84 | ||
85 | dtype_cmd |= add ? | |
86 | I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
87 | I40E_TXD_FLTR_QW1_PCMD_SHIFT : | |
88 | I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << | |
89 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
90 | ||
91 | dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & | |
92 | (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); | |
93 | ||
94 | dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & | |
95 | (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); | |
96 | ||
97 | if (fdata->cnt_index) { | |
98 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; | |
99 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & | |
100 | ((u32)fdata->cnt_index << | |
101 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); | |
102 | } | |
103 | ||
104 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); | |
105 | fdir_desc->rsvd = cpu_to_le32(0); | |
106 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); | |
107 | fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); | |
108 | } | |
109 | ||
49d7d933 | 110 | #define I40E_FD_CLEAN_DELAY 10 |
fd0a05ce JB |
111 | /** |
112 | * i40e_program_fdir_filter - Program a Flow Director filter | |
17a73f6b JG |
113 | * @fdir_data: Packet data that will be filter parameters |
114 | * @raw_packet: the pre-allocated packet buffer for FDir | |
b40c82e6 | 115 | * @pf: The PF pointer |
fd0a05ce JB |
116 | * @add: True for add/update, False for remove |
117 | **/ | |
1eb846ac AD |
118 | static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, |
119 | u8 *raw_packet, struct i40e_pf *pf, | |
120 | bool add) | |
fd0a05ce | 121 | { |
49d7d933 | 122 | struct i40e_tx_buffer *tx_buf, *first; |
fd0a05ce JB |
123 | struct i40e_tx_desc *tx_desc; |
124 | struct i40e_ring *tx_ring; | |
125 | struct i40e_vsi *vsi; | |
126 | struct device *dev; | |
127 | dma_addr_t dma; | |
128 | u32 td_cmd = 0; | |
129 | u16 i; | |
130 | ||
131 | /* find existing FDIR VSI */ | |
4b816446 | 132 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
fd0a05ce JB |
133 | if (!vsi) |
134 | return -ENOENT; | |
135 | ||
9f65e15b | 136 | tx_ring = vsi->tx_rings[0]; |
fd0a05ce JB |
137 | dev = tx_ring->dev; |
138 | ||
49d7d933 | 139 | /* we need two descriptors to add/del a filter and we can wait */ |
ed245406 AD |
140 | for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { |
141 | if (!i) | |
142 | return -EAGAIN; | |
49d7d933 | 143 | msleep_interruptible(1); |
ed245406 | 144 | } |
49d7d933 | 145 | |
17a73f6b JG |
146 | dma = dma_map_single(dev, raw_packet, |
147 | I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); | |
fd0a05ce JB |
148 | if (dma_mapping_error(dev, dma)) |
149 | goto dma_fail; | |
150 | ||
151 | /* grab the next descriptor */ | |
fc4ac67b | 152 | i = tx_ring->next_to_use; |
49d7d933 | 153 | first = &tx_ring->tx_bi[i]; |
5e02f283 | 154 | i40e_fdir(tx_ring, fdir_data, add); |
fd0a05ce JB |
155 | |
156 | /* Now program a dummy descriptor */ | |
fc4ac67b AD |
157 | i = tx_ring->next_to_use; |
158 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
298deef1 | 159 | tx_buf = &tx_ring->tx_bi[i]; |
fc4ac67b | 160 | |
49d7d933 ASJ |
161 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
162 | ||
163 | memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); | |
fd0a05ce | 164 | |
298deef1 | 165 | /* record length, and DMA address */ |
17a73f6b | 166 | dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); |
298deef1 ASJ |
167 | dma_unmap_addr_set(tx_buf, dma, dma); |
168 | ||
fd0a05ce | 169 | tx_desc->buffer_addr = cpu_to_le64(dma); |
eaefbd06 | 170 | td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; |
fd0a05ce | 171 | |
49d7d933 ASJ |
172 | tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; |
173 | tx_buf->raw_buf = (void *)raw_packet; | |
174 | ||
fd0a05ce | 175 | tx_desc->cmd_type_offset_bsz = |
17a73f6b | 176 | build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); |
fd0a05ce | 177 | |
fd0a05ce | 178 | /* Force memory writes to complete before letting h/w |
49d7d933 | 179 | * know there are new descriptors to fetch. |
fd0a05ce JB |
180 | */ |
181 | wmb(); | |
182 | ||
fc4ac67b | 183 | /* Mark the data descriptor to be watched */ |
49d7d933 | 184 | first->next_to_watch = tx_desc; |
fc4ac67b | 185 | |
fd0a05ce JB |
186 | writel(tx_ring->next_to_use, tx_ring->tail); |
187 | return 0; | |
188 | ||
189 | dma_fail: | |
190 | return -1; | |
191 | } | |
192 | ||
17a73f6b JG |
193 | #define IP_HEADER_OFFSET 14 |
194 | #define I40E_UDPIP_DUMMY_PACKET_LEN 42 | |
195 | /** | |
196 | * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters | |
197 | * @vsi: pointer to the targeted VSI | |
198 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
199 | * @add: true adds a filter, false removes it |
200 | * | |
201 | * Returns 0 if the filters were successfully added or removed | |
202 | **/ | |
203 | static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, | |
204 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 205 | bool add) |
17a73f6b JG |
206 | { |
207 | struct i40e_pf *pf = vsi->back; | |
208 | struct udphdr *udp; | |
209 | struct iphdr *ip; | |
49d7d933 | 210 | u8 *raw_packet; |
17a73f6b | 211 | int ret; |
17a73f6b JG |
212 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, |
213 | 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, | |
214 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
215 | ||
49d7d933 ASJ |
216 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
217 | if (!raw_packet) | |
218 | return -ENOMEM; | |
17a73f6b JG |
219 | memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); |
220 | ||
221 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
222 | udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET | |
223 | + sizeof(struct iphdr)); | |
224 | ||
8ce43dce | 225 | ip->daddr = fd_data->dst_ip; |
17a73f6b | 226 | udp->dest = fd_data->dst_port; |
8ce43dce | 227 | ip->saddr = fd_data->src_ip; |
17a73f6b JG |
228 | udp->source = fd_data->src_port; |
229 | ||
0e588de1 JK |
230 | if (fd_data->flex_filter) { |
231 | u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN; | |
232 | __be16 pattern = fd_data->flex_word; | |
233 | u16 off = fd_data->flex_offset; | |
234 | ||
235 | *((__force __be16 *)(payload + off)) = pattern; | |
236 | } | |
237 | ||
b2d36c03 KS |
238 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; |
239 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
240 | if (ret) { | |
241 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
242 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
243 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
244 | /* Free the packet buffer since it wasn't added to the ring */ |
245 | kfree(raw_packet); | |
246 | return -EOPNOTSUPP; | |
4205d379 | 247 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
248 | if (add) |
249 | dev_info(&pf->pdev->dev, | |
250 | "Filter OK for PCTYPE %d loc = %d\n", | |
251 | fd_data->pctype, fd_data->fd_id); | |
252 | else | |
253 | dev_info(&pf->pdev->dev, | |
254 | "Filter deleted for PCTYPE %d loc = %d\n", | |
255 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b | 256 | } |
a42e7a36 | 257 | |
097dbf52 JK |
258 | if (add) |
259 | pf->fd_udp4_filter_cnt++; | |
260 | else | |
261 | pf->fd_udp4_filter_cnt--; | |
262 | ||
e5187ee3 | 263 | return 0; |
17a73f6b JG |
264 | } |
265 | ||
266 | #define I40E_TCPIP_DUMMY_PACKET_LEN 54 | |
267 | /** | |
268 | * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters | |
269 | * @vsi: pointer to the targeted VSI | |
270 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
271 | * @add: true adds a filter, false removes it |
272 | * | |
273 | * Returns 0 if the filters were successfully added or removed | |
274 | **/ | |
275 | static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, | |
276 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 277 | bool add) |
17a73f6b JG |
278 | { |
279 | struct i40e_pf *pf = vsi->back; | |
280 | struct tcphdr *tcp; | |
281 | struct iphdr *ip; | |
49d7d933 | 282 | u8 *raw_packet; |
17a73f6b JG |
283 | int ret; |
284 | /* Dummy packet */ | |
285 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
286 | 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, | |
287 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, | |
288 | 0x0, 0x72, 0, 0, 0, 0}; | |
289 | ||
49d7d933 ASJ |
290 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
291 | if (!raw_packet) | |
292 | return -ENOMEM; | |
17a73f6b JG |
293 | memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); |
294 | ||
295 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
296 | tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET | |
297 | + sizeof(struct iphdr)); | |
298 | ||
8ce43dce | 299 | ip->daddr = fd_data->dst_ip; |
17a73f6b | 300 | tcp->dest = fd_data->dst_port; |
8ce43dce | 301 | ip->saddr = fd_data->src_ip; |
17a73f6b JG |
302 | tcp->source = fd_data->src_port; |
303 | ||
0e588de1 JK |
304 | if (fd_data->flex_filter) { |
305 | u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN; | |
306 | __be16 pattern = fd_data->flex_word; | |
307 | u16 off = fd_data->flex_offset; | |
308 | ||
309 | *((__force __be16 *)(payload + off)) = pattern; | |
310 | } | |
311 | ||
b2d36c03 | 312 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; |
17a73f6b | 313 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); |
17a73f6b JG |
314 | if (ret) { |
315 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
316 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
317 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
318 | /* Free the packet buffer since it wasn't added to the ring */ |
319 | kfree(raw_packet); | |
320 | return -EOPNOTSUPP; | |
4205d379 | 321 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
322 | if (add) |
323 | dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", | |
324 | fd_data->pctype, fd_data->fd_id); | |
325 | else | |
326 | dev_info(&pf->pdev->dev, | |
327 | "Filter deleted for PCTYPE %d loc = %d\n", | |
328 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
329 | } |
330 | ||
377cc249 | 331 | if (add) { |
097dbf52 | 332 | pf->fd_tcp4_filter_cnt++; |
377cc249 JK |
333 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
334 | I40E_DEBUG_FD & pf->hw.debug_mask) | |
335 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); | |
47994c11 | 336 | pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; |
377cc249 | 337 | } else { |
097dbf52 | 338 | pf->fd_tcp4_filter_cnt--; |
377cc249 JK |
339 | } |
340 | ||
e5187ee3 | 341 | return 0; |
17a73f6b JG |
342 | } |
343 | ||
f223c875 JK |
344 | #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 |
345 | /** | |
346 | * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for | |
347 | * a specific flow spec | |
348 | * @vsi: pointer to the targeted VSI | |
349 | * @fd_data: the flow director data required for the FDir descriptor | |
350 | * @add: true adds a filter, false removes it | |
351 | * | |
352 | * Returns 0 if the filters were successfully added or removed | |
353 | **/ | |
354 | static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, | |
355 | struct i40e_fdir_filter *fd_data, | |
356 | bool add) | |
357 | { | |
358 | struct i40e_pf *pf = vsi->back; | |
359 | struct sctphdr *sctp; | |
360 | struct iphdr *ip; | |
361 | u8 *raw_packet; | |
362 | int ret; | |
363 | /* Dummy packet */ | |
364 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
365 | 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0, | |
366 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
367 | ||
368 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); | |
369 | if (!raw_packet) | |
370 | return -ENOMEM; | |
371 | memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN); | |
372 | ||
373 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
374 | sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET | |
375 | + sizeof(struct iphdr)); | |
376 | ||
377 | ip->daddr = fd_data->dst_ip; | |
378 | sctp->dest = fd_data->dst_port; | |
379 | ip->saddr = fd_data->src_ip; | |
380 | sctp->source = fd_data->src_port; | |
381 | ||
382 | if (fd_data->flex_filter) { | |
383 | u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN; | |
384 | __be16 pattern = fd_data->flex_word; | |
385 | u16 off = fd_data->flex_offset; | |
386 | ||
387 | *((__force __be16 *)(payload + off)) = pattern; | |
388 | } | |
389 | ||
390 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; | |
391 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
392 | if (ret) { | |
393 | dev_info(&pf->pdev->dev, | |
394 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", | |
395 | fd_data->pctype, fd_data->fd_id, ret); | |
396 | /* Free the packet buffer since it wasn't added to the ring */ | |
397 | kfree(raw_packet); | |
398 | return -EOPNOTSUPP; | |
399 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { | |
400 | if (add) | |
401 | dev_info(&pf->pdev->dev, | |
402 | "Filter OK for PCTYPE %d loc = %d\n", | |
403 | fd_data->pctype, fd_data->fd_id); | |
404 | else | |
405 | dev_info(&pf->pdev->dev, | |
406 | "Filter deleted for PCTYPE %d loc = %d\n", | |
407 | fd_data->pctype, fd_data->fd_id); | |
408 | } | |
409 | ||
410 | if (add) | |
411 | pf->fd_sctp4_filter_cnt++; | |
412 | else | |
413 | pf->fd_sctp4_filter_cnt--; | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
17a73f6b JG |
418 | #define I40E_IP_DUMMY_PACKET_LEN 34 |
419 | /** | |
420 | * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for | |
421 | * a specific flow spec | |
422 | * @vsi: pointer to the targeted VSI | |
423 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
424 | * @add: true adds a filter, false removes it |
425 | * | |
426 | * Returns 0 if the filters were successfully added or removed | |
427 | **/ | |
428 | static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, | |
429 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 430 | bool add) |
17a73f6b JG |
431 | { |
432 | struct i40e_pf *pf = vsi->back; | |
433 | struct iphdr *ip; | |
49d7d933 | 434 | u8 *raw_packet; |
17a73f6b JG |
435 | int ret; |
436 | int i; | |
437 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
438 | 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, | |
439 | 0, 0, 0, 0}; | |
440 | ||
17a73f6b JG |
441 | for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; |
442 | i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { | |
49d7d933 ASJ |
443 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
444 | if (!raw_packet) | |
445 | return -ENOMEM; | |
446 | memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); | |
447 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
448 | ||
8ce43dce JK |
449 | ip->saddr = fd_data->src_ip; |
450 | ip->daddr = fd_data->dst_ip; | |
49d7d933 ASJ |
451 | ip->protocol = 0; |
452 | ||
0e588de1 JK |
453 | if (fd_data->flex_filter) { |
454 | u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN; | |
455 | __be16 pattern = fd_data->flex_word; | |
456 | u16 off = fd_data->flex_offset; | |
457 | ||
458 | *((__force __be16 *)(payload + off)) = pattern; | |
459 | } | |
460 | ||
17a73f6b JG |
461 | fd_data->pctype = i; |
462 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
17a73f6b JG |
463 | if (ret) { |
464 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
465 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
466 | fd_data->pctype, fd_data->fd_id, ret); | |
e5187ee3 JK |
467 | /* The packet buffer wasn't added to the ring so we |
468 | * need to free it now. | |
469 | */ | |
470 | kfree(raw_packet); | |
471 | return -EOPNOTSUPP; | |
4205d379 | 472 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
473 | if (add) |
474 | dev_info(&pf->pdev->dev, | |
475 | "Filter OK for PCTYPE %d loc = %d\n", | |
476 | fd_data->pctype, fd_data->fd_id); | |
477 | else | |
478 | dev_info(&pf->pdev->dev, | |
479 | "Filter deleted for PCTYPE %d loc = %d\n", | |
480 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
481 | } |
482 | } | |
483 | ||
097dbf52 JK |
484 | if (add) |
485 | pf->fd_ip4_filter_cnt++; | |
486 | else | |
487 | pf->fd_ip4_filter_cnt--; | |
488 | ||
e5187ee3 | 489 | return 0; |
17a73f6b JG |
490 | } |
491 | ||
492 | /** | |
493 | * i40e_add_del_fdir - Build raw packets to add/del fdir filter | |
494 | * @vsi: pointer to the targeted VSI | |
495 | * @cmd: command to get or set RX flow classification rules | |
496 | * @add: true adds a filter, false removes it | |
497 | * | |
498 | **/ | |
499 | int i40e_add_del_fdir(struct i40e_vsi *vsi, | |
500 | struct i40e_fdir_filter *input, bool add) | |
501 | { | |
502 | struct i40e_pf *pf = vsi->back; | |
17a73f6b JG |
503 | int ret; |
504 | ||
17a73f6b JG |
505 | switch (input->flow_type & ~FLOW_EXT) { |
506 | case TCP_V4_FLOW: | |
49d7d933 | 507 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
508 | break; |
509 | case UDP_V4_FLOW: | |
49d7d933 | 510 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 511 | break; |
f223c875 JK |
512 | case SCTP_V4_FLOW: |
513 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); | |
514 | break; | |
17a73f6b JG |
515 | case IP_USER_FLOW: |
516 | switch (input->ip4_proto) { | |
517 | case IPPROTO_TCP: | |
49d7d933 | 518 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
519 | break; |
520 | case IPPROTO_UDP: | |
49d7d933 | 521 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 522 | break; |
f223c875 JK |
523 | case IPPROTO_SCTP: |
524 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); | |
525 | break; | |
e1da71ca | 526 | case IPPROTO_IP: |
49d7d933 | 527 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b | 528 | break; |
e1da71ca AD |
529 | default: |
530 | /* We cannot support masking based on protocol */ | |
a346fb83 JK |
531 | dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n", |
532 | input->ip4_proto); | |
533 | return -EINVAL; | |
17a73f6b JG |
534 | } |
535 | break; | |
536 | default: | |
a346fb83 | 537 | dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n", |
17a73f6b | 538 | input->flow_type); |
a346fb83 | 539 | return -EINVAL; |
17a73f6b JG |
540 | } |
541 | ||
a158aeaf JK |
542 | /* The buffer allocated here will be normally be freed by |
543 | * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit | |
544 | * completion. In the event of an error adding the buffer to the FDIR | |
545 | * ring, it will immediately be freed. It may also be freed by | |
546 | * i40e_clean_tx_ring() when closing the VSI. | |
547 | */ | |
17a73f6b JG |
548 | return ret; |
549 | } | |
550 | ||
fd0a05ce JB |
551 | /** |
552 | * i40e_fd_handle_status - check the Programming Status for FD | |
553 | * @rx_ring: the Rx ring for this descriptor | |
55a5e60b | 554 | * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. |
fd0a05ce JB |
555 | * @prog_id: the id originally used for programming |
556 | * | |
557 | * This is used to verify if the FD programming or invalidation | |
558 | * requested by SW to the HW is successful or not and take actions accordingly. | |
559 | **/ | |
55a5e60b ASJ |
560 | static void i40e_fd_handle_status(struct i40e_ring *rx_ring, |
561 | union i40e_rx_desc *rx_desc, u8 prog_id) | |
fd0a05ce | 562 | { |
55a5e60b ASJ |
563 | struct i40e_pf *pf = rx_ring->vsi->back; |
564 | struct pci_dev *pdev = pf->pdev; | |
565 | u32 fcnt_prog, fcnt_avail; | |
fd0a05ce | 566 | u32 error; |
55a5e60b | 567 | u64 qw; |
fd0a05ce | 568 | |
55a5e60b | 569 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
fd0a05ce JB |
570 | error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> |
571 | I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; | |
572 | ||
41a1d04b | 573 | if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { |
3487b6c3 | 574 | pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); |
f7233c54 ASJ |
575 | if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || |
576 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
577 | dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", | |
3487b6c3 | 578 | pf->fd_inv); |
55a5e60b | 579 | |
04294e38 ASJ |
580 | /* Check if the programming error is for ATR. |
581 | * If so, auto disable ATR and set a state for | |
582 | * flush in progress. Next time we come here if flush is in | |
583 | * progress do nothing, once flush is complete the state will | |
584 | * be cleared. | |
585 | */ | |
0da36b97 | 586 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
04294e38 ASJ |
587 | return; |
588 | ||
1e1be8f6 ASJ |
589 | pf->fd_add_err++; |
590 | /* store the current atr filter count */ | |
591 | pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); | |
592 | ||
04294e38 | 593 | if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && |
47994c11 JK |
594 | pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED) { |
595 | pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; | |
0da36b97 | 596 | set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); |
04294e38 ASJ |
597 | } |
598 | ||
55a5e60b | 599 | /* filter programming failed most likely due to table full */ |
04294e38 | 600 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 601 | fcnt_avail = pf->fdir_pf_filter_count; |
55a5e60b ASJ |
602 | /* If ATR is running fcnt_prog can quickly change, |
603 | * if we are very close to full, it makes sense to disable | |
604 | * FD ATR/SB and then re-enable it when there is room. | |
605 | */ | |
606 | if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { | |
1e1be8f6 | 607 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
47994c11 JK |
608 | !(pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED)) { |
609 | pf->flags |= I40E_FLAG_FD_SB_AUTO_DISABLED; | |
2e4875e3 ASJ |
610 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
611 | dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); | |
55a5e60b | 612 | } |
55a5e60b | 613 | } |
41a1d04b | 614 | } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { |
13c2884f | 615 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
e99bdd39 | 616 | dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", |
13c2884f | 617 | rx_desc->wb.qword0.hi_dword.fd_id); |
55a5e60b | 618 | } |
fd0a05ce JB |
619 | } |
620 | ||
621 | /** | |
a5e9c572 | 622 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer |
fd0a05ce JB |
623 | * @ring: the ring that owns the buffer |
624 | * @tx_buffer: the buffer to free | |
625 | **/ | |
a5e9c572 AD |
626 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, |
627 | struct i40e_tx_buffer *tx_buffer) | |
fd0a05ce | 628 | { |
a5e9c572 | 629 | if (tx_buffer->skb) { |
64bfd68e AD |
630 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
631 | kfree(tx_buffer->raw_buf); | |
632 | else | |
633 | dev_kfree_skb_any(tx_buffer->skb); | |
a5e9c572 | 634 | if (dma_unmap_len(tx_buffer, len)) |
fd0a05ce | 635 | dma_unmap_single(ring->dev, |
35a1e2ad AD |
636 | dma_unmap_addr(tx_buffer, dma), |
637 | dma_unmap_len(tx_buffer, len), | |
fd0a05ce | 638 | DMA_TO_DEVICE); |
a5e9c572 AD |
639 | } else if (dma_unmap_len(tx_buffer, len)) { |
640 | dma_unmap_page(ring->dev, | |
641 | dma_unmap_addr(tx_buffer, dma), | |
642 | dma_unmap_len(tx_buffer, len), | |
643 | DMA_TO_DEVICE); | |
fd0a05ce | 644 | } |
a42e7a36 | 645 | |
a5e9c572 AD |
646 | tx_buffer->next_to_watch = NULL; |
647 | tx_buffer->skb = NULL; | |
35a1e2ad | 648 | dma_unmap_len_set(tx_buffer, len, 0); |
a5e9c572 | 649 | /* tx_buffer must be completely set up in the transmit path */ |
fd0a05ce JB |
650 | } |
651 | ||
652 | /** | |
653 | * i40e_clean_tx_ring - Free any empty Tx buffers | |
654 | * @tx_ring: ring to be cleaned | |
655 | **/ | |
656 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring) | |
657 | { | |
fd0a05ce JB |
658 | unsigned long bi_size; |
659 | u16 i; | |
660 | ||
661 | /* ring already cleared, nothing to do */ | |
662 | if (!tx_ring->tx_bi) | |
663 | return; | |
664 | ||
665 | /* Free all the Tx ring sk_buffs */ | |
a5e9c572 AD |
666 | for (i = 0; i < tx_ring->count; i++) |
667 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
fd0a05ce JB |
668 | |
669 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
670 | memset(tx_ring->tx_bi, 0, bi_size); | |
671 | ||
672 | /* Zero out the descriptor ring */ | |
673 | memset(tx_ring->desc, 0, tx_ring->size); | |
674 | ||
675 | tx_ring->next_to_use = 0; | |
676 | tx_ring->next_to_clean = 0; | |
7070ce0a AD |
677 | |
678 | if (!tx_ring->netdev) | |
679 | return; | |
680 | ||
681 | /* cleanup Tx queue statistics */ | |
e486bdfd | 682 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
fd0a05ce JB |
683 | } |
684 | ||
685 | /** | |
686 | * i40e_free_tx_resources - Free Tx resources per queue | |
687 | * @tx_ring: Tx descriptor ring for a specific queue | |
688 | * | |
689 | * Free all transmit software resources | |
690 | **/ | |
691 | void i40e_free_tx_resources(struct i40e_ring *tx_ring) | |
692 | { | |
693 | i40e_clean_tx_ring(tx_ring); | |
694 | kfree(tx_ring->tx_bi); | |
695 | tx_ring->tx_bi = NULL; | |
696 | ||
697 | if (tx_ring->desc) { | |
698 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
699 | tx_ring->desc, tx_ring->dma); | |
700 | tx_ring->desc = NULL; | |
701 | } | |
702 | } | |
703 | ||
704 | /** | |
705 | * i40e_get_tx_pending - how many tx descriptors not processed | |
706 | * @tx_ring: the ring of descriptors | |
707 | * | |
708 | * Since there is no access to the ring head register | |
709 | * in XL710, we need to use our local copies | |
710 | **/ | |
17daabb5 | 711 | u32 i40e_get_tx_pending(struct i40e_ring *ring) |
fd0a05ce | 712 | { |
a68de58d JB |
713 | u32 head, tail; |
714 | ||
17daabb5 | 715 | head = i40e_get_head(ring); |
a68de58d JB |
716 | tail = readl(ring->tail); |
717 | ||
718 | if (head != tail) | |
719 | return (head < tail) ? | |
720 | tail - head : (tail + ring->count - head); | |
721 | ||
722 | return 0; | |
fd0a05ce JB |
723 | } |
724 | ||
1dc8b538 | 725 | #define WB_STRIDE 4 |
d91649f5 | 726 | |
fd0a05ce JB |
727 | /** |
728 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
729 | * @vsi: the VSI we care about |
730 | * @tx_ring: Tx ring to clean | |
731 | * @napi_budget: Used to determine if we are in netpoll | |
fd0a05ce JB |
732 | * |
733 | * Returns true if there's any budget left (e.g. the clean is finished) | |
734 | **/ | |
a619afe8 AD |
735 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
736 | struct i40e_ring *tx_ring, int napi_budget) | |
fd0a05ce JB |
737 | { |
738 | u16 i = tx_ring->next_to_clean; | |
739 | struct i40e_tx_buffer *tx_buf; | |
1943d8ba | 740 | struct i40e_tx_desc *tx_head; |
fd0a05ce | 741 | struct i40e_tx_desc *tx_desc; |
a619afe8 AD |
742 | unsigned int total_bytes = 0, total_packets = 0; |
743 | unsigned int budget = vsi->work_limit; | |
fd0a05ce JB |
744 | |
745 | tx_buf = &tx_ring->tx_bi[i]; | |
746 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
a5e9c572 | 747 | i -= tx_ring->count; |
fd0a05ce | 748 | |
1943d8ba JB |
749 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
750 | ||
a5e9c572 AD |
751 | do { |
752 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
fd0a05ce JB |
753 | |
754 | /* if next_to_watch is not set then there is no work pending */ | |
755 | if (!eop_desc) | |
756 | break; | |
757 | ||
a5e9c572 AD |
758 | /* prevent any other reads prior to eop_desc */ |
759 | read_barrier_depends(); | |
760 | ||
ed0980c4 | 761 | i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); |
1943d8ba JB |
762 | /* we have caught up to head, no work left to do */ |
763 | if (tx_head == tx_desc) | |
fd0a05ce JB |
764 | break; |
765 | ||
c304fdac | 766 | /* clear next_to_watch to prevent false hangs */ |
fd0a05ce | 767 | tx_buf->next_to_watch = NULL; |
fd0a05ce | 768 | |
a5e9c572 AD |
769 | /* update the statistics for this packet */ |
770 | total_bytes += tx_buf->bytecount; | |
771 | total_packets += tx_buf->gso_segs; | |
fd0a05ce | 772 | |
a5e9c572 | 773 | /* free the skb */ |
a619afe8 | 774 | napi_consume_skb(tx_buf->skb, napi_budget); |
fd0a05ce | 775 | |
a5e9c572 AD |
776 | /* unmap skb header data */ |
777 | dma_unmap_single(tx_ring->dev, | |
778 | dma_unmap_addr(tx_buf, dma), | |
779 | dma_unmap_len(tx_buf, len), | |
780 | DMA_TO_DEVICE); | |
fd0a05ce | 781 | |
a5e9c572 AD |
782 | /* clear tx_buffer data */ |
783 | tx_buf->skb = NULL; | |
784 | dma_unmap_len_set(tx_buf, len, 0); | |
fd0a05ce | 785 | |
a5e9c572 AD |
786 | /* unmap remaining buffers */ |
787 | while (tx_desc != eop_desc) { | |
ed0980c4 SP |
788 | i40e_trace(clean_tx_irq_unmap, |
789 | tx_ring, tx_desc, tx_buf); | |
fd0a05ce JB |
790 | |
791 | tx_buf++; | |
792 | tx_desc++; | |
793 | i++; | |
a5e9c572 AD |
794 | if (unlikely(!i)) { |
795 | i -= tx_ring->count; | |
fd0a05ce JB |
796 | tx_buf = tx_ring->tx_bi; |
797 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
798 | } | |
fd0a05ce | 799 | |
a5e9c572 AD |
800 | /* unmap any remaining paged data */ |
801 | if (dma_unmap_len(tx_buf, len)) { | |
802 | dma_unmap_page(tx_ring->dev, | |
803 | dma_unmap_addr(tx_buf, dma), | |
804 | dma_unmap_len(tx_buf, len), | |
805 | DMA_TO_DEVICE); | |
806 | dma_unmap_len_set(tx_buf, len, 0); | |
807 | } | |
808 | } | |
809 | ||
810 | /* move us one more past the eop_desc for start of next pkt */ | |
811 | tx_buf++; | |
812 | tx_desc++; | |
813 | i++; | |
814 | if (unlikely(!i)) { | |
815 | i -= tx_ring->count; | |
816 | tx_buf = tx_ring->tx_bi; | |
817 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
818 | } | |
819 | ||
016890b9 JB |
820 | prefetch(tx_desc); |
821 | ||
a5e9c572 AD |
822 | /* update budget accounting */ |
823 | budget--; | |
824 | } while (likely(budget)); | |
825 | ||
826 | i += tx_ring->count; | |
fd0a05ce | 827 | tx_ring->next_to_clean = i; |
980e9b11 | 828 | u64_stats_update_begin(&tx_ring->syncp); |
a114d0a6 AD |
829 | tx_ring->stats.bytes += total_bytes; |
830 | tx_ring->stats.packets += total_packets; | |
980e9b11 | 831 | u64_stats_update_end(&tx_ring->syncp); |
fd0a05ce JB |
832 | tx_ring->q_vector->tx.total_bytes += total_bytes; |
833 | tx_ring->q_vector->tx.total_packets += total_packets; | |
a5e9c572 | 834 | |
58044743 | 835 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
58044743 AS |
836 | /* check to see if there are < 4 descriptors |
837 | * waiting to be written back, then kick the hardware to force | |
838 | * them to be written back in case we stay in NAPI. | |
839 | * In this mode on X722 we do not enable Interrupt. | |
840 | */ | |
17daabb5 | 841 | unsigned int j = i40e_get_tx_pending(tx_ring); |
58044743 AS |
842 | |
843 | if (budget && | |
1dc8b538 | 844 | ((j / WB_STRIDE) == 0) && (j > 0) && |
0da36b97 | 845 | !test_bit(__I40E_VSI_DOWN, vsi->state) && |
58044743 AS |
846 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) |
847 | tx_ring->arm_wb = true; | |
848 | } | |
d91649f5 | 849 | |
e486bdfd AD |
850 | /* notify netdev of completed buffers */ |
851 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
7070ce0a AD |
852 | total_packets, total_bytes); |
853 | ||
fd0a05ce JB |
854 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
855 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
856 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
857 | /* Make sure that anybody stopping the queue after this | |
858 | * sees the new next_to_clean. | |
859 | */ | |
860 | smp_mb(); | |
861 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
862 | tx_ring->queue_index) && | |
0da36b97 | 863 | !test_bit(__I40E_VSI_DOWN, vsi->state)) { |
fd0a05ce JB |
864 | netif_wake_subqueue(tx_ring->netdev, |
865 | tx_ring->queue_index); | |
866 | ++tx_ring->tx_stats.restart_queue; | |
867 | } | |
868 | } | |
869 | ||
d91649f5 JB |
870 | return !!budget; |
871 | } | |
872 | ||
873 | /** | |
ecc6a239 | 874 | * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
d91649f5 | 875 | * @vsi: the VSI we care about |
ecc6a239 | 876 | * @q_vector: the vector on which to enable writeback |
d91649f5 JB |
877 | * |
878 | **/ | |
ecc6a239 ASJ |
879 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
880 | struct i40e_q_vector *q_vector) | |
d91649f5 | 881 | { |
8e0764b4 | 882 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 883 | u32 val; |
8e0764b4 | 884 | |
ecc6a239 ASJ |
885 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
886 | return; | |
8e0764b4 | 887 | |
ecc6a239 ASJ |
888 | if (q_vector->arm_wb_state) |
889 | return; | |
8e0764b4 | 890 | |
ecc6a239 ASJ |
891 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { |
892 | val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | | |
893 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 894 | |
ecc6a239 ASJ |
895 | wr32(&vsi->back->hw, |
896 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), | |
897 | val); | |
898 | } else { | |
899 | val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | | |
900 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 901 | |
ecc6a239 ASJ |
902 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); |
903 | } | |
904 | q_vector->arm_wb_state = true; | |
905 | } | |
906 | ||
907 | /** | |
908 | * i40e_force_wb - Issue SW Interrupt so HW does a wb | |
909 | * @vsi: the VSI we care about | |
910 | * @q_vector: the vector on which to force writeback | |
911 | * | |
912 | **/ | |
913 | void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
914 | { | |
915 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { | |
8e0764b4 ASJ |
916 | u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | |
917 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ | |
918 | I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | | |
919 | I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; | |
920 | /* allow 00 to be written to the index */ | |
921 | ||
922 | wr32(&vsi->back->hw, | |
923 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + | |
924 | vsi->base_vector - 1), val); | |
925 | } else { | |
926 | u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
927 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ | |
928 | I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | | |
929 | I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; | |
930 | /* allow 00 to be written to the index */ | |
931 | ||
932 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); | |
933 | } | |
fd0a05ce JB |
934 | } |
935 | ||
936 | /** | |
937 | * i40e_set_new_dynamic_itr - Find new ITR level | |
938 | * @rc: structure containing ring performance data | |
939 | * | |
8f5e39ce JB |
940 | * Returns true if ITR changed, false if not |
941 | * | |
fd0a05ce JB |
942 | * Stores a new ITR value based on packets and byte counts during |
943 | * the last interrupt. The advantage of per interrupt computation | |
944 | * is faster updates and more accurate ITR for the current traffic | |
945 | * pattern. Constants in this function were computed based on | |
946 | * theoretical maximum wire speed and thresholds were set based on | |
947 | * testing data as well as attempting to minimize response time | |
948 | * while increasing bulk throughput. | |
949 | **/ | |
8f5e39ce | 950 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
fd0a05ce JB |
951 | { |
952 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
c56625d5 | 953 | struct i40e_q_vector *qv = rc->ring->q_vector; |
fd0a05ce JB |
954 | u32 new_itr = rc->itr; |
955 | int bytes_per_int; | |
51cc6d9f | 956 | int usecs; |
fd0a05ce JB |
957 | |
958 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 959 | return false; |
fd0a05ce JB |
960 | |
961 | /* simple throttlerate management | |
c56625d5 | 962 | * 0-10MB/s lowest (50000 ints/s) |
fd0a05ce | 963 | * 10-20MB/s low (20000 ints/s) |
c56625d5 JB |
964 | * 20-1249MB/s bulk (18000 ints/s) |
965 | * > 40000 Rx packets per second (8000 ints/s) | |
51cc6d9f JB |
966 | * |
967 | * The math works out because the divisor is in 10^(-6) which | |
968 | * turns the bytes/us input value into MB/s values, but | |
969 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
970 | * are in 2 usec increments in the ITR registers, and make sure |
971 | * to use the smoothed values that the countdown timer gives us. | |
fd0a05ce | 972 | */ |
ee2319cf | 973 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
51cc6d9f | 974 | bytes_per_int = rc->total_bytes / usecs; |
ee2319cf | 975 | |
de32e3ef | 976 | switch (new_latency_range) { |
fd0a05ce JB |
977 | case I40E_LOWEST_LATENCY: |
978 | if (bytes_per_int > 10) | |
979 | new_latency_range = I40E_LOW_LATENCY; | |
980 | break; | |
981 | case I40E_LOW_LATENCY: | |
982 | if (bytes_per_int > 20) | |
983 | new_latency_range = I40E_BULK_LATENCY; | |
984 | else if (bytes_per_int <= 10) | |
985 | new_latency_range = I40E_LOWEST_LATENCY; | |
986 | break; | |
987 | case I40E_BULK_LATENCY: | |
c56625d5 | 988 | case I40E_ULTRA_LATENCY: |
de32e3ef CW |
989 | default: |
990 | if (bytes_per_int <= 20) | |
991 | new_latency_range = I40E_LOW_LATENCY; | |
fd0a05ce JB |
992 | break; |
993 | } | |
c56625d5 JB |
994 | |
995 | /* this is to adjust RX more aggressively when streaming small | |
996 | * packets. The value of 40000 was picked as it is just beyond | |
997 | * what the hardware can receive per second if in low latency | |
998 | * mode. | |
999 | */ | |
1000 | #define RX_ULTRA_PACKET_RATE 40000 | |
1001 | ||
1002 | if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && | |
1003 | (&qv->rx == rc)) | |
1004 | new_latency_range = I40E_ULTRA_LATENCY; | |
1005 | ||
de32e3ef | 1006 | rc->latency_range = new_latency_range; |
fd0a05ce JB |
1007 | |
1008 | switch (new_latency_range) { | |
1009 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 1010 | new_itr = I40E_ITR_50K; |
fd0a05ce JB |
1011 | break; |
1012 | case I40E_LOW_LATENCY: | |
1013 | new_itr = I40E_ITR_20K; | |
1014 | break; | |
1015 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
1016 | new_itr = I40E_ITR_18K; |
1017 | break; | |
1018 | case I40E_ULTRA_LATENCY: | |
fd0a05ce JB |
1019 | new_itr = I40E_ITR_8K; |
1020 | break; | |
1021 | default: | |
1022 | break; | |
1023 | } | |
1024 | ||
fd0a05ce JB |
1025 | rc->total_bytes = 0; |
1026 | rc->total_packets = 0; | |
8f5e39ce JB |
1027 | |
1028 | if (new_itr != rc->itr) { | |
1029 | rc->itr = new_itr; | |
1030 | return true; | |
1031 | } | |
1032 | ||
1033 | return false; | |
fd0a05ce JB |
1034 | } |
1035 | ||
0e626ff7 AD |
1036 | /** |
1037 | * i40e_rx_is_programming_status - check for programming status descriptor | |
1038 | * @qw: qword representing status_error_len in CPU ordering | |
1039 | * | |
1040 | * The value of in the descriptor length field indicate if this | |
1041 | * is a programming status descriptor for flow director or FCoE | |
1042 | * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise | |
1043 | * it is a packet descriptor. | |
1044 | **/ | |
1045 | static inline bool i40e_rx_is_programming_status(u64 qw) | |
1046 | { | |
1047 | /* The Rx filter programming status and SPH bit occupy the same | |
1048 | * spot in the descriptor. Since we don't support packet split we | |
1049 | * can just reuse the bit as an indication that this is a | |
1050 | * programming status descriptor. | |
1051 | */ | |
1052 | return qw & I40E_RXD_QW1_LENGTH_SPH_MASK; | |
1053 | } | |
1054 | ||
fd0a05ce JB |
1055 | /** |
1056 | * i40e_clean_programming_status - clean the programming status descriptor | |
1057 | * @rx_ring: the rx ring that has this descriptor | |
1058 | * @rx_desc: the rx descriptor written back by HW | |
0e626ff7 | 1059 | * @qw: qword representing status_error_len in CPU ordering |
fd0a05ce JB |
1060 | * |
1061 | * Flow director should handle FD_FILTER_STATUS to check its filter programming | |
1062 | * status being successful or not and take actions accordingly. FCoE should | |
1063 | * handle its context/filter programming/invalidation status and take actions. | |
1064 | * | |
1065 | **/ | |
1066 | static void i40e_clean_programming_status(struct i40e_ring *rx_ring, | |
0e626ff7 AD |
1067 | union i40e_rx_desc *rx_desc, |
1068 | u64 qw) | |
fd0a05ce | 1069 | { |
0e626ff7 | 1070 | u32 ntc = rx_ring->next_to_clean + 1; |
fd0a05ce JB |
1071 | u8 id; |
1072 | ||
0e626ff7 AD |
1073 | /* fetch, update, and store next to clean */ |
1074 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1075 | rx_ring->next_to_clean = ntc; | |
1076 | ||
1077 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1078 | ||
fd0a05ce JB |
1079 | id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> |
1080 | I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; | |
1081 | ||
1082 | if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) | |
55a5e60b | 1083 | i40e_fd_handle_status(rx_ring, rx_desc, id); |
fd0a05ce JB |
1084 | } |
1085 | ||
1086 | /** | |
1087 | * i40e_setup_tx_descriptors - Allocate the Tx descriptors | |
1088 | * @tx_ring: the tx ring to set up | |
1089 | * | |
1090 | * Return 0 on success, negative on error | |
1091 | **/ | |
1092 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
1093 | { | |
1094 | struct device *dev = tx_ring->dev; | |
1095 | int bi_size; | |
1096 | ||
1097 | if (!dev) | |
1098 | return -ENOMEM; | |
1099 | ||
e908f815 JB |
1100 | /* warn if we are about to overwrite the pointer */ |
1101 | WARN_ON(tx_ring->tx_bi); | |
fd0a05ce JB |
1102 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
1103 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1104 | if (!tx_ring->tx_bi) | |
1105 | goto err; | |
1106 | ||
1107 | /* round up to nearest 4K */ | |
1108 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
1109 | /* add u32 for head writeback, align after this takes care of |
1110 | * guaranteeing this is at least one cache line in size | |
1111 | */ | |
1112 | tx_ring->size += sizeof(u32); | |
fd0a05ce JB |
1113 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1114 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
1115 | &tx_ring->dma, GFP_KERNEL); | |
1116 | if (!tx_ring->desc) { | |
1117 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
1118 | tx_ring->size); | |
1119 | goto err; | |
1120 | } | |
1121 | ||
1122 | tx_ring->next_to_use = 0; | |
1123 | tx_ring->next_to_clean = 0; | |
1124 | return 0; | |
1125 | ||
1126 | err: | |
1127 | kfree(tx_ring->tx_bi); | |
1128 | tx_ring->tx_bi = NULL; | |
1129 | return -ENOMEM; | |
1130 | } | |
1131 | ||
1132 | /** | |
1133 | * i40e_clean_rx_ring - Free Rx buffers | |
1134 | * @rx_ring: ring to be cleaned | |
1135 | **/ | |
1136 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring) | |
1137 | { | |
fd0a05ce JB |
1138 | unsigned long bi_size; |
1139 | u16 i; | |
1140 | ||
1141 | /* ring already cleared, nothing to do */ | |
1142 | if (!rx_ring->rx_bi) | |
1143 | return; | |
1144 | ||
e72e5659 SP |
1145 | if (rx_ring->skb) { |
1146 | dev_kfree_skb(rx_ring->skb); | |
1147 | rx_ring->skb = NULL; | |
1148 | } | |
1149 | ||
fd0a05ce JB |
1150 | /* Free all the Rx ring sk_buffs */ |
1151 | for (i = 0; i < rx_ring->count; i++) { | |
1a557afc JB |
1152 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
1153 | ||
1a557afc JB |
1154 | if (!rx_bi->page) |
1155 | continue; | |
1156 | ||
59605bc0 AD |
1157 | /* Invalidate cache lines that may have been written to by |
1158 | * device so that we avoid corrupting memory. | |
1159 | */ | |
1160 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1161 | rx_bi->dma, | |
1162 | rx_bi->page_offset, | |
98efd694 | 1163 | rx_ring->rx_buf_len, |
59605bc0 AD |
1164 | DMA_FROM_DEVICE); |
1165 | ||
1166 | /* free resources associated with mapping */ | |
1167 | dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, | |
98efd694 | 1168 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
1169 | DMA_FROM_DEVICE, |
1170 | I40E_RX_DMA_ATTR); | |
98efd694 | 1171 | |
1793668c | 1172 | __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); |
1a557afc JB |
1173 | |
1174 | rx_bi->page = NULL; | |
1175 | rx_bi->page_offset = 0; | |
fd0a05ce JB |
1176 | } |
1177 | ||
1178 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
1179 | memset(rx_ring->rx_bi, 0, bi_size); | |
1180 | ||
1181 | /* Zero out the descriptor ring */ | |
1182 | memset(rx_ring->desc, 0, rx_ring->size); | |
1183 | ||
1a557afc | 1184 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1185 | rx_ring->next_to_clean = 0; |
1186 | rx_ring->next_to_use = 0; | |
1187 | } | |
1188 | ||
1189 | /** | |
1190 | * i40e_free_rx_resources - Free Rx resources | |
1191 | * @rx_ring: ring to clean the resources from | |
1192 | * | |
1193 | * Free all receive software resources | |
1194 | **/ | |
1195 | void i40e_free_rx_resources(struct i40e_ring *rx_ring) | |
1196 | { | |
1197 | i40e_clean_rx_ring(rx_ring); | |
1198 | kfree(rx_ring->rx_bi); | |
1199 | rx_ring->rx_bi = NULL; | |
1200 | ||
1201 | if (rx_ring->desc) { | |
1202 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
1203 | rx_ring->desc, rx_ring->dma); | |
1204 | rx_ring->desc = NULL; | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | /** | |
1209 | * i40e_setup_rx_descriptors - Allocate Rx descriptors | |
1210 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
1211 | * | |
1212 | * Returns 0 on success, negative on failure | |
1213 | **/ | |
1214 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
1215 | { | |
1216 | struct device *dev = rx_ring->dev; | |
1217 | int bi_size; | |
1218 | ||
e908f815 JB |
1219 | /* warn if we are about to overwrite the pointer */ |
1220 | WARN_ON(rx_ring->rx_bi); | |
fd0a05ce JB |
1221 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
1222 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1223 | if (!rx_ring->rx_bi) | |
1224 | goto err; | |
1225 | ||
f217d6ca | 1226 | u64_stats_init(&rx_ring->syncp); |
638702bd | 1227 | |
fd0a05ce | 1228 | /* Round up to nearest 4K */ |
1a557afc | 1229 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
fd0a05ce JB |
1230 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
1231 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
1232 | &rx_ring->dma, GFP_KERNEL); | |
1233 | ||
1234 | if (!rx_ring->desc) { | |
1235 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
1236 | rx_ring->size); | |
1237 | goto err; | |
1238 | } | |
1239 | ||
1a557afc | 1240 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1241 | rx_ring->next_to_clean = 0; |
1242 | rx_ring->next_to_use = 0; | |
1243 | ||
1244 | return 0; | |
1245 | err: | |
1246 | kfree(rx_ring->rx_bi); | |
1247 | rx_ring->rx_bi = NULL; | |
1248 | return -ENOMEM; | |
1249 | } | |
1250 | ||
1251 | /** | |
1252 | * i40e_release_rx_desc - Store the new tail and head values | |
1253 | * @rx_ring: ring to bump | |
1254 | * @val: new head index | |
1255 | **/ | |
1256 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
1257 | { | |
1258 | rx_ring->next_to_use = val; | |
1a557afc JB |
1259 | |
1260 | /* update next to alloc since we have filled the ring */ | |
1261 | rx_ring->next_to_alloc = val; | |
1262 | ||
fd0a05ce JB |
1263 | /* Force memory writes to complete before letting h/w |
1264 | * know there are new descriptors to fetch. (Only | |
1265 | * applicable for weak-ordered memory model archs, | |
1266 | * such as IA-64). | |
1267 | */ | |
1268 | wmb(); | |
1269 | writel(val, rx_ring->tail); | |
1270 | } | |
1271 | ||
ca9ec088 AD |
1272 | /** |
1273 | * i40e_rx_offset - Return expected offset into page to access data | |
1274 | * @rx_ring: Ring we are requesting offset of | |
1275 | * | |
1276 | * Returns the offset value for ring into the data buffer. | |
1277 | */ | |
1278 | static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring) | |
1279 | { | |
1280 | return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0; | |
1281 | } | |
1282 | ||
fd0a05ce | 1283 | /** |
1a557afc JB |
1284 | * i40e_alloc_mapped_page - recycle or make a new page |
1285 | * @rx_ring: ring to use | |
1286 | * @bi: rx_buffer struct to modify | |
c2e245ab | 1287 | * |
1a557afc JB |
1288 | * Returns true if the page was successfully allocated or |
1289 | * reused. | |
fd0a05ce | 1290 | **/ |
1a557afc JB |
1291 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
1292 | struct i40e_rx_buffer *bi) | |
a132af24 | 1293 | { |
1a557afc JB |
1294 | struct page *page = bi->page; |
1295 | dma_addr_t dma; | |
a132af24 | 1296 | |
1a557afc JB |
1297 | /* since we are recycling buffers we should seldom need to alloc */ |
1298 | if (likely(page)) { | |
1299 | rx_ring->rx_stats.page_reuse_count++; | |
1300 | return true; | |
1301 | } | |
a132af24 | 1302 | |
1a557afc | 1303 | /* alloc new page for storage */ |
98efd694 | 1304 | page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); |
1a557afc JB |
1305 | if (unlikely(!page)) { |
1306 | rx_ring->rx_stats.alloc_page_failed++; | |
1307 | return false; | |
1308 | } | |
a132af24 | 1309 | |
1a557afc | 1310 | /* map page for use */ |
59605bc0 | 1311 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
98efd694 | 1312 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
1313 | DMA_FROM_DEVICE, |
1314 | I40E_RX_DMA_ATTR); | |
f16704e5 | 1315 | |
1a557afc JB |
1316 | /* if mapping failed free memory back to system since |
1317 | * there isn't much point in holding memory we can't use | |
f16704e5 | 1318 | */ |
1a557afc | 1319 | if (dma_mapping_error(rx_ring->dev, dma)) { |
98efd694 | 1320 | __free_pages(page, i40e_rx_pg_order(rx_ring)); |
1a557afc JB |
1321 | rx_ring->rx_stats.alloc_page_failed++; |
1322 | return false; | |
a132af24 MW |
1323 | } |
1324 | ||
1a557afc JB |
1325 | bi->dma = dma; |
1326 | bi->page = page; | |
ca9ec088 | 1327 | bi->page_offset = i40e_rx_offset(rx_ring); |
a0cfc313 AD |
1328 | |
1329 | /* initialize pagecnt_bias to 1 representing we fully own page */ | |
1793668c | 1330 | bi->pagecnt_bias = 1; |
c2e245ab | 1331 | |
1a557afc JB |
1332 | return true; |
1333 | } | |
c2e245ab | 1334 | |
1a557afc JB |
1335 | /** |
1336 | * i40e_receive_skb - Send a completed packet up the stack | |
1337 | * @rx_ring: rx ring in play | |
1338 | * @skb: packet to send up | |
1339 | * @vlan_tag: vlan tag for packet | |
1340 | **/ | |
1341 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
1342 | struct sk_buff *skb, u16 vlan_tag) | |
1343 | { | |
1344 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
c2e245ab | 1345 | |
1a557afc JB |
1346 | if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
1347 | (vlan_tag & VLAN_VID_MASK)) | |
1348 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
1349 | ||
1350 | napi_gro_receive(&q_vector->napi, skb); | |
a132af24 MW |
1351 | } |
1352 | ||
1353 | /** | |
1a557afc | 1354 | * i40e_alloc_rx_buffers - Replace used receive buffers |
a132af24 MW |
1355 | * @rx_ring: ring to place buffers on |
1356 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 1357 | * |
1a557afc | 1358 | * Returns false if all allocations were successful, true if any fail |
a132af24 | 1359 | **/ |
1a557afc | 1360 | bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
fd0a05ce | 1361 | { |
1a557afc | 1362 | u16 ntu = rx_ring->next_to_use; |
fd0a05ce JB |
1363 | union i40e_rx_desc *rx_desc; |
1364 | struct i40e_rx_buffer *bi; | |
fd0a05ce JB |
1365 | |
1366 | /* do nothing if no valid netdev defined */ | |
1367 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 1368 | return false; |
fd0a05ce | 1369 | |
1a557afc JB |
1370 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
1371 | bi = &rx_ring->rx_bi[ntu]; | |
fd0a05ce | 1372 | |
1a557afc JB |
1373 | do { |
1374 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
1375 | goto no_buffers; | |
fd0a05ce | 1376 | |
59605bc0 AD |
1377 | /* sync the buffer for use by the device */ |
1378 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
1379 | bi->page_offset, | |
98efd694 | 1380 | rx_ring->rx_buf_len, |
59605bc0 AD |
1381 | DMA_FROM_DEVICE); |
1382 | ||
1a557afc JB |
1383 | /* Refresh the desc even if buffer_addrs didn't change |
1384 | * because each write-back erases this info. | |
1385 | */ | |
1386 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
fd0a05ce | 1387 | |
1a557afc JB |
1388 | rx_desc++; |
1389 | bi++; | |
1390 | ntu++; | |
1391 | if (unlikely(ntu == rx_ring->count)) { | |
1392 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
1393 | bi = rx_ring->rx_bi; | |
1394 | ntu = 0; | |
1395 | } | |
1396 | ||
1397 | /* clear the status bits for the next_to_use descriptor */ | |
1398 | rx_desc->wb.qword1.status_error_len = 0; | |
1399 | ||
1400 | cleaned_count--; | |
1401 | } while (cleaned_count); | |
1402 | ||
1403 | if (rx_ring->next_to_use != ntu) | |
1404 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1405 | |
1406 | return false; | |
1407 | ||
fd0a05ce | 1408 | no_buffers: |
1a557afc JB |
1409 | if (rx_ring->next_to_use != ntu) |
1410 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1411 | |
1412 | /* make sure to come back via polling to try again after | |
1413 | * allocation failure | |
1414 | */ | |
1415 | return true; | |
fd0a05ce JB |
1416 | } |
1417 | ||
fd0a05ce JB |
1418 | /** |
1419 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
1420 | * @vsi: the VSI we care about | |
1421 | * @skb: skb currently being received and modified | |
1a557afc | 1422 | * @rx_desc: the receive descriptor |
fd0a05ce JB |
1423 | **/ |
1424 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
1425 | struct sk_buff *skb, | |
1a557afc | 1426 | union i40e_rx_desc *rx_desc) |
fd0a05ce | 1427 | { |
1a557afc | 1428 | struct i40e_rx_ptype_decoded decoded; |
1a557afc | 1429 | u32 rx_error, rx_status; |
858296c8 | 1430 | bool ipv4, ipv6; |
1a557afc JB |
1431 | u8 ptype; |
1432 | u64 qword; | |
1433 | ||
1434 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1435 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
1436 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
1437 | I40E_RXD_QW1_ERROR_SHIFT; | |
1438 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1439 | I40E_RXD_QW1_STATUS_SHIFT; | |
1440 | decoded = decode_rx_desc_ptype(ptype); | |
8144f0f7 | 1441 | |
fd0a05ce JB |
1442 | skb->ip_summed = CHECKSUM_NONE; |
1443 | ||
1a557afc JB |
1444 | skb_checksum_none_assert(skb); |
1445 | ||
fd0a05ce | 1446 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
1447 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
1448 | return; | |
1449 | ||
1450 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 1451 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
1452 | return; |
1453 | ||
1454 | /* both known and outer_ip must be set for the below code to work */ | |
1455 | if (!(decoded.known && decoded.outer_ip)) | |
fd0a05ce JB |
1456 | return; |
1457 | ||
fad57330 AD |
1458 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
1459 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
1460 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
1461 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
1462 | |
1463 | if (ipv4 && | |
41a1d04b JB |
1464 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
1465 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
1466 | goto checksum_fail; |
1467 | ||
ddf1d0d7 | 1468 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 1469 | if (ipv6 && |
41a1d04b | 1470 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 1471 | /* don't increment checksum err here, non-fatal err */ |
8ee75a8e SN |
1472 | return; |
1473 | ||
8a3c91cc | 1474 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 1475 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
1476 | goto checksum_fail; |
1477 | ||
1478 | /* handle packets that were not able to be checksummed due | |
1479 | * to arrival speed, in this case the stack can compute | |
1480 | * the csum. | |
1481 | */ | |
41a1d04b | 1482 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
fd0a05ce | 1483 | return; |
fd0a05ce | 1484 | |
858296c8 AD |
1485 | /* If there is an outer header present that might contain a checksum |
1486 | * we need to bump the checksum level by 1 to reflect the fact that | |
1487 | * we are indicating we validated the inner checksum. | |
8a3c91cc | 1488 | */ |
858296c8 AD |
1489 | if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) |
1490 | skb->csum_level = 1; | |
1491 | ||
1492 | /* Only report checksum unnecessary for TCP, UDP, or SCTP */ | |
1493 | switch (decoded.inner_prot) { | |
1494 | case I40E_RX_PTYPE_INNER_PROT_TCP: | |
1495 | case I40E_RX_PTYPE_INNER_PROT_UDP: | |
1496 | case I40E_RX_PTYPE_INNER_PROT_SCTP: | |
1497 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1498 | /* fall though */ | |
1499 | default: | |
1500 | break; | |
1501 | } | |
8a3c91cc JB |
1502 | |
1503 | return; | |
1504 | ||
1505 | checksum_fail: | |
1506 | vsi->back->hw_csum_rx_error++; | |
fd0a05ce JB |
1507 | } |
1508 | ||
1509 | /** | |
857942fd | 1510 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
1511 | * @ptype: the ptype value from the descriptor |
1512 | * | |
1513 | * Returns a hash type to be used by skb_set_hash | |
1514 | **/ | |
1a557afc | 1515 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
1516 | { |
1517 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
1518 | ||
1519 | if (!decoded.known) | |
1520 | return PKT_HASH_TYPE_NONE; | |
1521 | ||
1522 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1523 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
1524 | return PKT_HASH_TYPE_L4; | |
1525 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1526 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
1527 | return PKT_HASH_TYPE_L3; | |
1528 | else | |
1529 | return PKT_HASH_TYPE_L2; | |
1530 | } | |
1531 | ||
857942fd ASJ |
1532 | /** |
1533 | * i40e_rx_hash - set the hash value in the skb | |
1534 | * @ring: descriptor ring | |
1535 | * @rx_desc: specific descriptor | |
1536 | **/ | |
1537 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
1538 | union i40e_rx_desc *rx_desc, | |
1539 | struct sk_buff *skb, | |
1540 | u8 rx_ptype) | |
1541 | { | |
1542 | u32 hash; | |
1a557afc | 1543 | const __le64 rss_mask = |
857942fd ASJ |
1544 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
1545 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
1546 | ||
a876c3ba | 1547 | if (!(ring->netdev->features & NETIF_F_RXHASH)) |
857942fd ASJ |
1548 | return; |
1549 | ||
1550 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
1551 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
1552 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
1553 | } | |
1554 | } | |
1555 | ||
a132af24 | 1556 | /** |
1a557afc JB |
1557 | * i40e_process_skb_fields - Populate skb header fields from Rx descriptor |
1558 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1559 | * @rx_desc: pointer to the EOP Rx descriptor | |
1560 | * @skb: pointer to current skb being populated | |
1561 | * @rx_ptype: the packet type decoded by hardware | |
1562 | * | |
1563 | * This function checks the ring, descriptor, and packet information in | |
1564 | * order to populate the hash, checksum, VLAN, protocol, and | |
1565 | * other fields within the skb. | |
1566 | **/ | |
1567 | static inline | |
1568 | void i40e_process_skb_fields(struct i40e_ring *rx_ring, | |
1569 | union i40e_rx_desc *rx_desc, struct sk_buff *skb, | |
1570 | u8 rx_ptype) | |
1571 | { | |
1572 | u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1573 | u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1574 | I40E_RXD_QW1_STATUS_SHIFT; | |
144ed176 JK |
1575 | u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; |
1576 | u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> | |
1a557afc JB |
1577 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; |
1578 | ||
12490501 | 1579 | if (unlikely(tsynvalid)) |
144ed176 | 1580 | i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); |
1a557afc JB |
1581 | |
1582 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); | |
1583 | ||
1a557afc JB |
1584 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); |
1585 | ||
1586 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
a5b268e4 AD |
1587 | |
1588 | /* modifies the skb - consumes the enet header */ | |
1589 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
1a557afc JB |
1590 | } |
1591 | ||
1a557afc JB |
1592 | /** |
1593 | * i40e_cleanup_headers - Correct empty headers | |
1594 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1595 | * @skb: pointer to current skb being fixed | |
1596 | * | |
1597 | * Also address the case where we are pulling data in on pages only | |
1598 | * and as such no data is present in the skb header. | |
1599 | * | |
1600 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1601 | * it is large enough to qualify as a valid Ethernet frame. | |
1602 | * | |
1603 | * Returns true if an error was encountered and skb was freed. | |
1604 | **/ | |
1605 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
1606 | { | |
1a557afc JB |
1607 | /* if eth_skb_pad returns an error the skb was freed */ |
1608 | if (eth_skb_pad(skb)) | |
1609 | return true; | |
1610 | ||
1611 | return false; | |
1612 | } | |
1613 | ||
1614 | /** | |
1615 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
1616 | * @rx_ring: rx descriptor ring to store buffers on | |
1617 | * @old_buff: donor buffer to have page reused | |
1618 | * | |
1619 | * Synchronizes page for reuse by the adapter | |
1620 | **/ | |
1621 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
1622 | struct i40e_rx_buffer *old_buff) | |
1623 | { | |
1624 | struct i40e_rx_buffer *new_buff; | |
1625 | u16 nta = rx_ring->next_to_alloc; | |
1626 | ||
1627 | new_buff = &rx_ring->rx_bi[nta]; | |
1628 | ||
1629 | /* update, and store next to alloc */ | |
1630 | nta++; | |
1631 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1632 | ||
1633 | /* transfer page from old buffer to new buffer */ | |
1793668c AD |
1634 | new_buff->dma = old_buff->dma; |
1635 | new_buff->page = old_buff->page; | |
1636 | new_buff->page_offset = old_buff->page_offset; | |
1637 | new_buff->pagecnt_bias = old_buff->pagecnt_bias; | |
1a557afc JB |
1638 | } |
1639 | ||
1640 | /** | |
9b37c937 | 1641 | * i40e_page_is_reusable - check if any reuse is possible |
1a557afc | 1642 | * @page: page struct to check |
9b37c937 SP |
1643 | * |
1644 | * A page is not reusable if it was allocated under low memory | |
1645 | * conditions, or it's not in the same NUMA node as this CPU. | |
1a557afc | 1646 | */ |
9b37c937 | 1647 | static inline bool i40e_page_is_reusable(struct page *page) |
1a557afc | 1648 | { |
9b37c937 SP |
1649 | return (page_to_nid(page) == numa_mem_id()) && |
1650 | !page_is_pfmemalloc(page); | |
1651 | } | |
1652 | ||
1653 | /** | |
1654 | * i40e_can_reuse_rx_page - Determine if this page can be reused by | |
1655 | * the adapter for another receive | |
1656 | * | |
1657 | * @rx_buffer: buffer containing the page | |
9b37c937 SP |
1658 | * |
1659 | * If page is reusable, rx_buffer->page_offset is adjusted to point to | |
1660 | * an unused region in the page. | |
1661 | * | |
1662 | * For small pages, @truesize will be a constant value, half the size | |
1663 | * of the memory at page. We'll attempt to alternate between high and | |
1664 | * low halves of the page, with one half ready for use by the hardware | |
1665 | * and the other half being consumed by the stack. We use the page | |
1666 | * ref count to determine whether the stack has finished consuming the | |
1667 | * portion of this page that was passed up with a previous packet. If | |
1668 | * the page ref count is >1, we'll assume the "other" half page is | |
1669 | * still busy, and this page cannot be reused. | |
1670 | * | |
1671 | * For larger pages, @truesize will be the actual space used by the | |
1672 | * received packet (adjusted upward to an even multiple of the cache | |
1673 | * line size). This will advance through the page by the amount | |
1674 | * actually consumed by the received packets while there is still | |
1675 | * space for a buffer. Each region of larger pages will be used at | |
1676 | * most once, after which the page will not be reused. | |
1677 | * | |
1678 | * In either case, if the page is reusable its refcount is increased. | |
1679 | **/ | |
a0cfc313 | 1680 | static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer) |
9b37c937 | 1681 | { |
a0cfc313 AD |
1682 | unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; |
1683 | struct page *page = rx_buffer->page; | |
9b37c937 SP |
1684 | |
1685 | /* Is any reuse possible? */ | |
1686 | if (unlikely(!i40e_page_is_reusable(page))) | |
1687 | return false; | |
1688 | ||
1689 | #if (PAGE_SIZE < 8192) | |
1690 | /* if we are only owner of page we can reuse it */ | |
a0cfc313 | 1691 | if (unlikely((page_count(page) - pagecnt_bias) > 1)) |
9b37c937 | 1692 | return false; |
9b37c937 | 1693 | #else |
98efd694 AD |
1694 | #define I40E_LAST_OFFSET \ |
1695 | (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) | |
1696 | if (rx_buffer->page_offset > I40E_LAST_OFFSET) | |
9b37c937 SP |
1697 | return false; |
1698 | #endif | |
1699 | ||
1793668c AD |
1700 | /* If we have drained the page fragment pool we need to update |
1701 | * the pagecnt_bias and page count so that we fully restock the | |
1702 | * number of references the driver holds. | |
1703 | */ | |
a0cfc313 | 1704 | if (unlikely(!pagecnt_bias)) { |
1793668c AD |
1705 | page_ref_add(page, USHRT_MAX); |
1706 | rx_buffer->pagecnt_bias = USHRT_MAX; | |
1707 | } | |
a0cfc313 | 1708 | |
9b37c937 | 1709 | return true; |
1a557afc JB |
1710 | } |
1711 | ||
1712 | /** | |
1713 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1714 | * @rx_ring: rx descriptor ring to transact packets on | |
1715 | * @rx_buffer: buffer containing page to add | |
1a557afc | 1716 | * @skb: sk_buff to place the data into |
a0cfc313 | 1717 | * @size: packet length from rx_desc |
1a557afc JB |
1718 | * |
1719 | * This function will add the data contained in rx_buffer->page to the skb. | |
fa2343e9 | 1720 | * It will just attach the page as a frag to the skb. |
1a557afc | 1721 | * |
fa2343e9 | 1722 | * The function will then update the page offset. |
1a557afc | 1723 | **/ |
a0cfc313 | 1724 | static void i40e_add_rx_frag(struct i40e_ring *rx_ring, |
1a557afc | 1725 | struct i40e_rx_buffer *rx_buffer, |
a0cfc313 AD |
1726 | struct sk_buff *skb, |
1727 | unsigned int size) | |
1a557afc | 1728 | { |
1a557afc | 1729 | #if (PAGE_SIZE < 8192) |
98efd694 | 1730 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
1a557afc | 1731 | #else |
ca9ec088 | 1732 | unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)); |
1a557afc | 1733 | #endif |
1a557afc | 1734 | |
fa2343e9 AD |
1735 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, |
1736 | rx_buffer->page_offset, size, truesize); | |
1a557afc | 1737 | |
a0cfc313 AD |
1738 | /* page is being used so we must update the page offset */ |
1739 | #if (PAGE_SIZE < 8192) | |
1740 | rx_buffer->page_offset ^= truesize; | |
1741 | #else | |
1742 | rx_buffer->page_offset += truesize; | |
1743 | #endif | |
1a557afc JB |
1744 | } |
1745 | ||
9a064128 AD |
1746 | /** |
1747 | * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use | |
1748 | * @rx_ring: rx descriptor ring to transact packets on | |
1749 | * @size: size of buffer to add to skb | |
1750 | * | |
1751 | * This function will pull an Rx buffer from the ring and synchronize it | |
1752 | * for use by the CPU. | |
1753 | */ | |
1754 | static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, | |
1755 | const unsigned int size) | |
1756 | { | |
1757 | struct i40e_rx_buffer *rx_buffer; | |
1758 | ||
1759 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1760 | prefetchw(rx_buffer->page); | |
1761 | ||
1762 | /* we are reusing so sync this buffer for CPU use */ | |
1763 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1764 | rx_buffer->dma, | |
1765 | rx_buffer->page_offset, | |
1766 | size, | |
1767 | DMA_FROM_DEVICE); | |
1768 | ||
a0cfc313 AD |
1769 | /* We have pulled a buffer for use, so decrement pagecnt_bias */ |
1770 | rx_buffer->pagecnt_bias--; | |
1771 | ||
9a064128 AD |
1772 | return rx_buffer; |
1773 | } | |
1774 | ||
1a557afc | 1775 | /** |
fa2343e9 | 1776 | * i40e_construct_skb - Allocate skb and populate it |
1a557afc | 1777 | * @rx_ring: rx descriptor ring to transact packets on |
9a064128 | 1778 | * @rx_buffer: rx buffer to pull data from |
d57c0e08 | 1779 | * @size: size of buffer to add to skb |
a132af24 | 1780 | * |
fa2343e9 AD |
1781 | * This function allocates an skb. It then populates it with the page |
1782 | * data from the current receive descriptor, taking care to set up the | |
1783 | * skb correctly. | |
1a557afc | 1784 | */ |
fa2343e9 AD |
1785 | static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, |
1786 | struct i40e_rx_buffer *rx_buffer, | |
1787 | unsigned int size) | |
1a557afc | 1788 | { |
fa2343e9 AD |
1789 | void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; |
1790 | #if (PAGE_SIZE < 8192) | |
98efd694 | 1791 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
fa2343e9 AD |
1792 | #else |
1793 | unsigned int truesize = SKB_DATA_ALIGN(size); | |
1794 | #endif | |
1795 | unsigned int headlen; | |
1796 | struct sk_buff *skb; | |
1a557afc | 1797 | |
fa2343e9 AD |
1798 | /* prefetch first cache line of first page */ |
1799 | prefetch(va); | |
1a557afc | 1800 | #if L1_CACHE_BYTES < 128 |
fa2343e9 | 1801 | prefetch(va + L1_CACHE_BYTES); |
1a557afc JB |
1802 | #endif |
1803 | ||
fa2343e9 AD |
1804 | /* allocate a skb to store the frags */ |
1805 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
1806 | I40E_RX_HDR_SIZE, | |
1807 | GFP_ATOMIC | __GFP_NOWARN); | |
1808 | if (unlikely(!skb)) | |
1809 | return NULL; | |
1810 | ||
1811 | /* Determine available headroom for copy */ | |
1812 | headlen = size; | |
1813 | if (headlen > I40E_RX_HDR_SIZE) | |
1814 | headlen = eth_get_headlen(va, I40E_RX_HDR_SIZE); | |
1a557afc | 1815 | |
fa2343e9 AD |
1816 | /* align pull length to size of long to optimize memcpy performance */ |
1817 | memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); | |
1818 | ||
1819 | /* update all of the pointers */ | |
1820 | size -= headlen; | |
1821 | if (size) { | |
1822 | skb_add_rx_frag(skb, 0, rx_buffer->page, | |
1823 | rx_buffer->page_offset + headlen, | |
1824 | size, truesize); | |
1825 | ||
1826 | /* buffer is used by skb, update page_offset */ | |
1827 | #if (PAGE_SIZE < 8192) | |
1828 | rx_buffer->page_offset ^= truesize; | |
1829 | #else | |
1830 | rx_buffer->page_offset += truesize; | |
1831 | #endif | |
1832 | } else { | |
1833 | /* buffer is unused, reset bias back to rx_buffer */ | |
1834 | rx_buffer->pagecnt_bias++; | |
1835 | } | |
a0cfc313 AD |
1836 | |
1837 | return skb; | |
1838 | } | |
1839 | ||
f8b45b74 AD |
1840 | /** |
1841 | * i40e_build_skb - Build skb around an existing buffer | |
1842 | * @rx_ring: Rx descriptor ring to transact packets on | |
1843 | * @rx_buffer: Rx buffer to pull data from | |
1844 | * @size: size of buffer to add to skb | |
1845 | * | |
1846 | * This function builds an skb around an existing Rx buffer, taking care | |
1847 | * to set up the skb correctly and avoid any memcpy overhead. | |
1848 | */ | |
1849 | static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, | |
1850 | struct i40e_rx_buffer *rx_buffer, | |
1851 | unsigned int size) | |
1852 | { | |
1853 | void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; | |
1854 | #if (PAGE_SIZE < 8192) | |
1855 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; | |
1856 | #else | |
1857 | unsigned int truesize = SKB_DATA_ALIGN(size); | |
1858 | #endif | |
1859 | struct sk_buff *skb; | |
1860 | ||
1861 | /* prefetch first cache line of first page */ | |
1862 | prefetch(va); | |
1863 | #if L1_CACHE_BYTES < 128 | |
1864 | prefetch(va + L1_CACHE_BYTES); | |
1865 | #endif | |
1866 | /* build an skb around the page buffer */ | |
1867 | skb = build_skb(va - I40E_SKB_PAD, truesize); | |
1868 | if (unlikely(!skb)) | |
1869 | return NULL; | |
1870 | ||
1871 | /* update pointers within the skb to store the data */ | |
1872 | skb_reserve(skb, I40E_SKB_PAD); | |
1873 | __skb_put(skb, size); | |
1874 | ||
1875 | /* buffer is used by skb, update page_offset */ | |
1876 | #if (PAGE_SIZE < 8192) | |
1877 | rx_buffer->page_offset ^= truesize; | |
1878 | #else | |
1879 | rx_buffer->page_offset += truesize; | |
1880 | #endif | |
1881 | ||
1882 | return skb; | |
1883 | } | |
1884 | ||
a0cfc313 AD |
1885 | /** |
1886 | * i40e_put_rx_buffer - Clean up used buffer and either recycle or free | |
1887 | * @rx_ring: rx descriptor ring to transact packets on | |
1888 | * @rx_buffer: rx buffer to pull data from | |
1889 | * | |
1890 | * This function will clean up the contents of the rx_buffer. It will | |
1891 | * either recycle the bufer or unmap it and free the associated resources. | |
1892 | */ | |
1893 | static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, | |
1894 | struct i40e_rx_buffer *rx_buffer) | |
1895 | { | |
1896 | if (i40e_can_reuse_rx_page(rx_buffer)) { | |
1a557afc JB |
1897 | /* hand second half of page back to the ring */ |
1898 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1899 | rx_ring->rx_stats.page_reuse_count++; | |
1900 | } else { | |
1901 | /* we are not reusing the buffer so unmap it */ | |
98efd694 AD |
1902 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, |
1903 | i40e_rx_pg_size(rx_ring), | |
59605bc0 | 1904 | DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); |
1793668c AD |
1905 | __page_frag_cache_drain(rx_buffer->page, |
1906 | rx_buffer->pagecnt_bias); | |
1a557afc JB |
1907 | } |
1908 | ||
1909 | /* clear contents of buffer_info */ | |
1910 | rx_buffer->page = NULL; | |
1a557afc JB |
1911 | } |
1912 | ||
1913 | /** | |
1914 | * i40e_is_non_eop - process handling of non-EOP buffers | |
1915 | * @rx_ring: Rx ring being processed | |
1916 | * @rx_desc: Rx descriptor for current buffer | |
1917 | * @skb: Current socket buffer containing buffer in progress | |
1918 | * | |
1919 | * This function updates next to clean. If the buffer is an EOP buffer | |
1920 | * this function exits returning false, otherwise it will place the | |
1921 | * sk_buff in the next buffer to be chained and return true indicating | |
1922 | * that this is in fact a non-EOP buffer. | |
a132af24 | 1923 | **/ |
1a557afc JB |
1924 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, |
1925 | union i40e_rx_desc *rx_desc, | |
1926 | struct sk_buff *skb) | |
1927 | { | |
1928 | u32 ntc = rx_ring->next_to_clean + 1; | |
1929 | ||
1930 | /* fetch, update, and store next to clean */ | |
1931 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1932 | rx_ring->next_to_clean = ntc; | |
1933 | ||
1934 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1935 | ||
1a557afc JB |
1936 | /* if we are the last buffer then there is nothing else to do */ |
1937 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
1938 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
1939 | return false; | |
1940 | ||
1a557afc JB |
1941 | rx_ring->rx_stats.non_eop_descs++; |
1942 | ||
1943 | return true; | |
1944 | } | |
1945 | ||
1946 | /** | |
1947 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1948 | * @rx_ring: rx descriptor ring to transact packets on | |
1949 | * @budget: Total limit on number of packets to process | |
1950 | * | |
1951 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1952 | * processing. The advantage to this is that on systems that have | |
1953 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1954 | * it by maintaining the mapping of the page to the system. | |
1955 | * | |
1956 | * Returns amount of work completed | |
1957 | **/ | |
1958 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) | |
a132af24 MW |
1959 | { |
1960 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
e72e5659 | 1961 | struct sk_buff *skb = rx_ring->skb; |
a132af24 | 1962 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); |
c2e245ab | 1963 | bool failure = false; |
a132af24 | 1964 | |
1a557afc | 1965 | while (likely(total_rx_packets < budget)) { |
9a064128 | 1966 | struct i40e_rx_buffer *rx_buffer; |
1a557afc | 1967 | union i40e_rx_desc *rx_desc; |
d57c0e08 | 1968 | unsigned int size; |
a132af24 | 1969 | u16 vlan_tag; |
1a557afc JB |
1970 | u8 rx_ptype; |
1971 | u64 qword; | |
1972 | ||
fd0a05ce JB |
1973 | /* return some buffers to hardware, one at a time is too slow */ |
1974 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 1975 | failure = failure || |
1a557afc | 1976 | i40e_alloc_rx_buffers(rx_ring, cleaned_count); |
fd0a05ce JB |
1977 | cleaned_count = 0; |
1978 | } | |
1979 | ||
1a557afc JB |
1980 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
1981 | ||
1a557afc JB |
1982 | /* status_error_len will always be zero for unused descriptors |
1983 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
1984 | * which is always zero because packet split isn't used, if the | |
d57c0e08 | 1985 | * hardware wrote DD then the length will be non-zero |
1a557afc | 1986 | */ |
d57c0e08 | 1987 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1a557afc | 1988 | |
a132af24 | 1989 | /* This memory barrier is needed to keep us from reading |
d57c0e08 AD |
1990 | * any other fields out of the rx_desc until we have |
1991 | * verified the descriptor has been written back. | |
a132af24 | 1992 | */ |
67317166 | 1993 | dma_rmb(); |
a132af24 | 1994 | |
0e626ff7 AD |
1995 | if (unlikely(i40e_rx_is_programming_status(qword))) { |
1996 | i40e_clean_programming_status(rx_ring, rx_desc, qword); | |
1997 | continue; | |
1998 | } | |
1999 | size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> | |
2000 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
2001 | if (!size) | |
2002 | break; | |
2003 | ||
ed0980c4 | 2004 | i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb); |
9a064128 AD |
2005 | rx_buffer = i40e_get_rx_buffer(rx_ring, size); |
2006 | ||
fa2343e9 AD |
2007 | /* retrieve a buffer from the ring */ |
2008 | if (skb) | |
2009 | i40e_add_rx_frag(rx_ring, rx_buffer, skb, size); | |
f8b45b74 AD |
2010 | else if (ring_uses_build_skb(rx_ring)) |
2011 | skb = i40e_build_skb(rx_ring, rx_buffer, size); | |
fa2343e9 AD |
2012 | else |
2013 | skb = i40e_construct_skb(rx_ring, rx_buffer, size); | |
2014 | ||
2015 | /* exit if we failed to retrieve a buffer */ | |
2016 | if (!skb) { | |
2017 | rx_ring->rx_stats.alloc_buff_failed++; | |
2018 | rx_buffer->pagecnt_bias++; | |
1a557afc | 2019 | break; |
fa2343e9 | 2020 | } |
a132af24 | 2021 | |
a0cfc313 | 2022 | i40e_put_rx_buffer(rx_ring, rx_buffer); |
a132af24 MW |
2023 | cleaned_count++; |
2024 | ||
1a557afc | 2025 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 2026 | continue; |
a132af24 | 2027 | |
1a557afc JB |
2028 | /* ERR_MASK will only have valid bits if EOP set, and |
2029 | * what we are doing here is actually checking | |
2030 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
2031 | * the error field | |
2032 | */ | |
2033 | if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
a132af24 | 2034 | dev_kfree_skb_any(skb); |
741b8b83 | 2035 | skb = NULL; |
a132af24 MW |
2036 | continue; |
2037 | } | |
2038 | ||
e72e5659 SP |
2039 | if (i40e_cleanup_headers(rx_ring, skb)) { |
2040 | skb = NULL; | |
1a557afc | 2041 | continue; |
e72e5659 | 2042 | } |
a132af24 MW |
2043 | |
2044 | /* probably a little skewed due to removing CRC */ | |
2045 | total_rx_bytes += skb->len; | |
a132af24 | 2046 | |
99dad8b3 AD |
2047 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
2048 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> | |
2049 | I40E_RXD_QW1_PTYPE_SHIFT; | |
2050 | ||
1a557afc JB |
2051 | /* populate checksum, VLAN, and protocol */ |
2052 | i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); | |
a132af24 | 2053 | |
1a557afc JB |
2054 | vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? |
2055 | le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; | |
2056 | ||
ed0980c4 | 2057 | i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb); |
a132af24 | 2058 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
e72e5659 | 2059 | skb = NULL; |
a132af24 | 2060 | |
1a557afc JB |
2061 | /* update budget accounting */ |
2062 | total_rx_packets++; | |
2063 | } | |
fd0a05ce | 2064 | |
e72e5659 SP |
2065 | rx_ring->skb = skb; |
2066 | ||
980e9b11 | 2067 | u64_stats_update_begin(&rx_ring->syncp); |
a114d0a6 AD |
2068 | rx_ring->stats.packets += total_rx_packets; |
2069 | rx_ring->stats.bytes += total_rx_bytes; | |
980e9b11 | 2070 | u64_stats_update_end(&rx_ring->syncp); |
fd0a05ce JB |
2071 | rx_ring->q_vector->rx.total_packets += total_rx_packets; |
2072 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
2073 | ||
1a557afc | 2074 | /* guarantee a trip back through this routine if there was a failure */ |
c2e245ab | 2075 | return failure ? budget : total_rx_packets; |
fd0a05ce JB |
2076 | } |
2077 | ||
8f5e39ce JB |
2078 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
2079 | { | |
2080 | u32 val; | |
2081 | ||
2082 | val = I40E_PFINT_DYN_CTLN_INTENA_MASK | | |
40d72a50 JB |
2083 | /* Don't clear PBA because that can cause lost interrupts that |
2084 | * came in while we were cleaning/polling | |
2085 | */ | |
8f5e39ce JB |
2086 | (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | |
2087 | (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); | |
2088 | ||
2089 | return val; | |
2090 | } | |
2091 | ||
2092 | /* a small macro to shorten up some long lines */ | |
2093 | #define INTREG I40E_PFINT_DYN_CTLN | |
3c234c47 | 2094 | static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 | 2095 | { |
3c234c47 | 2096 | return vsi->rx_rings[idx]->rx_itr_setting; |
65e87c03 JK |
2097 | } |
2098 | ||
3c234c47 | 2099 | static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 | 2100 | { |
3c234c47 | 2101 | return vsi->tx_rings[idx]->tx_itr_setting; |
65e87c03 | 2102 | } |
8f5e39ce | 2103 | |
de32e3ef CW |
2104 | /** |
2105 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
2106 | * @vsi: the VSI we care about | |
2107 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
2108 | * | |
2109 | **/ | |
2110 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
2111 | struct i40e_q_vector *q_vector) | |
2112 | { | |
2113 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
2114 | bool rx = false, tx = false; |
2115 | u32 rxval, txval; | |
de32e3ef | 2116 | int vector; |
a75e8005 | 2117 | int idx = q_vector->v_idx; |
65e87c03 | 2118 | int rx_itr_setting, tx_itr_setting; |
de32e3ef CW |
2119 | |
2120 | vector = (q_vector->v_idx + vsi->base_vector); | |
8f5e39ce | 2121 | |
ee2319cf JB |
2122 | /* avoid dynamic calculation if in countdown mode OR if |
2123 | * all dynamic is disabled | |
2124 | */ | |
8f5e39ce JB |
2125 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
2126 | ||
3c234c47 CW |
2127 | rx_itr_setting = get_rx_itr(vsi, idx); |
2128 | tx_itr_setting = get_tx_itr(vsi, idx); | |
65e87c03 | 2129 | |
ee2319cf | 2130 | if (q_vector->itr_countdown > 0 || |
65e87c03 JK |
2131 | (!ITR_IS_DYNAMIC(rx_itr_setting) && |
2132 | !ITR_IS_DYNAMIC(tx_itr_setting))) { | |
ee2319cf JB |
2133 | goto enable_int; |
2134 | } | |
2135 | ||
65e87c03 | 2136 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
2137 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
2138 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 2139 | } |
8f5e39ce | 2140 | |
65e87c03 | 2141 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
2142 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
2143 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
de32e3ef | 2144 | } |
8f5e39ce JB |
2145 | |
2146 | if (rx || tx) { | |
2147 | /* get the higher of the two ITR adjustments and | |
2148 | * use the same value for both ITR registers | |
2149 | * when in adaptive mode (Rx and/or Tx) | |
2150 | */ | |
2151 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
2152 | ||
2153 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
2154 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
2155 | tx = true; | |
2156 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
2157 | rx = true; | |
2158 | } | |
2159 | ||
2160 | /* only need to enable the interrupt once, but need | |
2161 | * to possibly update both ITR values | |
2162 | */ | |
2163 | if (rx) { | |
2164 | /* set the INTENA_MSK_MASK so that this first write | |
2165 | * won't actually enable the interrupt, instead just | |
2166 | * updating the ITR (it's bit 31 PF and VF) | |
2167 | */ | |
2168 | rxval |= BIT(31); | |
2169 | /* don't check _DOWN because interrupt isn't being enabled */ | |
2170 | wr32(hw, INTREG(vector - 1), rxval); | |
2171 | } | |
2172 | ||
ee2319cf | 2173 | enable_int: |
0da36b97 | 2174 | if (!test_bit(__I40E_VSI_DOWN, vsi->state)) |
8f5e39ce | 2175 | wr32(hw, INTREG(vector - 1), txval); |
ee2319cf JB |
2176 | |
2177 | if (q_vector->itr_countdown) | |
2178 | q_vector->itr_countdown--; | |
2179 | else | |
2180 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
2181 | } |
2182 | ||
fd0a05ce JB |
2183 | /** |
2184 | * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine | |
2185 | * @napi: napi struct with our devices info in it | |
2186 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2187 | * | |
2188 | * This function will clean all queues associated with a q_vector. | |
2189 | * | |
2190 | * Returns the amount of work done | |
2191 | **/ | |
2192 | int i40e_napi_poll(struct napi_struct *napi, int budget) | |
2193 | { | |
2194 | struct i40e_q_vector *q_vector = | |
2195 | container_of(napi, struct i40e_q_vector, napi); | |
2196 | struct i40e_vsi *vsi = q_vector->vsi; | |
cd0b6fa6 | 2197 | struct i40e_ring *ring; |
fd0a05ce | 2198 | bool clean_complete = true; |
d91649f5 | 2199 | bool arm_wb = false; |
fd0a05ce | 2200 | int budget_per_ring; |
32b3e08f | 2201 | int work_done = 0; |
fd0a05ce | 2202 | |
0da36b97 | 2203 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) { |
fd0a05ce JB |
2204 | napi_complete(napi); |
2205 | return 0; | |
2206 | } | |
2207 | ||
cd0b6fa6 AD |
2208 | /* Since the actual Tx work is minimal, we can give the Tx a larger |
2209 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
2210 | */ | |
d91649f5 | 2211 | i40e_for_each_ring(ring, q_vector->tx) { |
a619afe8 | 2212 | if (!i40e_clean_tx_irq(vsi, ring, budget)) { |
f2edaaaa AD |
2213 | clean_complete = false; |
2214 | continue; | |
2215 | } | |
2216 | arm_wb |= ring->arm_wb; | |
0deda868 | 2217 | ring->arm_wb = false; |
d91649f5 | 2218 | } |
cd0b6fa6 | 2219 | |
c67caceb AD |
2220 | /* Handle case where we are called by netpoll with a budget of 0 */ |
2221 | if (budget <= 0) | |
2222 | goto tx_only; | |
2223 | ||
fd0a05ce JB |
2224 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
2225 | * allow the budget to go below 1 because that would exit polling early. | |
fd0a05ce JB |
2226 | */ |
2227 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
cd0b6fa6 | 2228 | |
a132af24 | 2229 | i40e_for_each_ring(ring, q_vector->rx) { |
1a557afc | 2230 | int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); |
32b3e08f JB |
2231 | |
2232 | work_done += cleaned; | |
f2edaaaa AD |
2233 | /* if we clean as many as budgeted, we must not be done */ |
2234 | if (cleaned >= budget_per_ring) | |
2235 | clean_complete = false; | |
a132af24 | 2236 | } |
fd0a05ce JB |
2237 | |
2238 | /* If work not completed, return budget and polling will return */ | |
d91649f5 | 2239 | if (!clean_complete) { |
96db776a AB |
2240 | const cpumask_t *aff_mask = &q_vector->affinity_mask; |
2241 | int cpu_id = smp_processor_id(); | |
2242 | ||
2243 | /* It is possible that the interrupt affinity has changed but, | |
2244 | * if the cpu is pegged at 100%, polling will never exit while | |
2245 | * traffic continues and the interrupt will be stuck on this | |
2246 | * cpu. We check to make sure affinity is correct before we | |
2247 | * continue to poll, otherwise we must stop polling so the | |
2248 | * interrupt can move to the correct cpu. | |
2249 | */ | |
2250 | if (likely(cpumask_test_cpu(cpu_id, aff_mask) || | |
2251 | !(vsi->back->flags & I40E_FLAG_MSIX_ENABLED))) { | |
c67caceb | 2252 | tx_only: |
96db776a AB |
2253 | if (arm_wb) { |
2254 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
2255 | i40e_enable_wb_on_itr(vsi, q_vector); | |
2256 | } | |
2257 | return budget; | |
164c9f54 | 2258 | } |
d91649f5 | 2259 | } |
fd0a05ce | 2260 | |
8e0764b4 ASJ |
2261 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
2262 | q_vector->arm_wb_state = false; | |
2263 | ||
fd0a05ce | 2264 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 2265 | napi_complete_done(napi, work_done); |
96db776a AB |
2266 | |
2267 | /* If we're prematurely stopping polling to fix the interrupt | |
2268 | * affinity we want to make sure polling starts back up so we | |
2269 | * issue a call to i40e_force_wb which triggers a SW interrupt. | |
2270 | */ | |
2271 | if (!clean_complete) | |
2272 | i40e_force_wb(vsi, q_vector); | |
2273 | else if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) | |
40d72a50 | 2274 | i40e_irq_dynamic_enable_icr0(vsi->back, false); |
96db776a AB |
2275 | else |
2276 | i40e_update_enable_itr(vsi, q_vector); | |
2277 | ||
6beb84a7 | 2278 | return min(work_done, budget - 1); |
fd0a05ce JB |
2279 | } |
2280 | ||
2281 | /** | |
2282 | * i40e_atr - Add a Flow Director ATR filter | |
2283 | * @tx_ring: ring to add programming descriptor to | |
2284 | * @skb: send buffer | |
89232c3b | 2285 | * @tx_flags: send tx flags |
fd0a05ce JB |
2286 | **/ |
2287 | static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
6b037cd4 | 2288 | u32 tx_flags) |
fd0a05ce JB |
2289 | { |
2290 | struct i40e_filter_program_desc *fdir_desc; | |
2291 | struct i40e_pf *pf = tx_ring->vsi->back; | |
2292 | union { | |
2293 | unsigned char *network; | |
2294 | struct iphdr *ipv4; | |
2295 | struct ipv6hdr *ipv6; | |
2296 | } hdr; | |
2297 | struct tcphdr *th; | |
2298 | unsigned int hlen; | |
2299 | u32 flex_ptype, dtype_cmd; | |
ffcc55c0 | 2300 | int l4_proto; |
fc4ac67b | 2301 | u16 i; |
fd0a05ce JB |
2302 | |
2303 | /* make sure ATR is enabled */ | |
60ea5f83 | 2304 | if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) |
fd0a05ce JB |
2305 | return; |
2306 | ||
47994c11 | 2307 | if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED) |
04294e38 ASJ |
2308 | return; |
2309 | ||
fd0a05ce JB |
2310 | /* if sampling is disabled do nothing */ |
2311 | if (!tx_ring->atr_sample_rate) | |
2312 | return; | |
2313 | ||
6b037cd4 | 2314 | /* Currently only IPv4/IPv6 with TCP is supported */ |
89232c3b ASJ |
2315 | if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) |
2316 | return; | |
fd0a05ce | 2317 | |
ffcc55c0 AD |
2318 | /* snag network header to get L4 type and address */ |
2319 | hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? | |
2320 | skb_inner_network_header(skb) : skb_network_header(skb); | |
fd0a05ce | 2321 | |
ffcc55c0 AD |
2322 | /* Note: tx_flags gets modified to reflect inner protocols in |
2323 | * tx_enable_csum function if encap is enabled. | |
2324 | */ | |
2325 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
6b037cd4 | 2326 | /* access ihl as u8 to avoid unaligned access on ia64 */ |
ffcc55c0 AD |
2327 | hlen = (hdr.network[0] & 0x0F) << 2; |
2328 | l4_proto = hdr.ipv4->protocol; | |
fd0a05ce | 2329 | } else { |
ffcc55c0 AD |
2330 | hlen = hdr.network - skb->data; |
2331 | l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); | |
2332 | hlen -= hdr.network - skb->data; | |
fd0a05ce JB |
2333 | } |
2334 | ||
6b037cd4 | 2335 | if (l4_proto != IPPROTO_TCP) |
89232c3b ASJ |
2336 | return; |
2337 | ||
fd0a05ce JB |
2338 | th = (struct tcphdr *)(hdr.network + hlen); |
2339 | ||
55a5e60b | 2340 | /* Due to lack of space, no more new filters can be programmed */ |
47994c11 | 2341 | if (th->syn && (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED)) |
55a5e60b | 2342 | return; |
e8c5f723 | 2343 | if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) { |
52eb95ef ASJ |
2344 | /* HW ATR eviction will take care of removing filters on FIN |
2345 | * and RST packets. | |
2346 | */ | |
2347 | if (th->fin || th->rst) | |
2348 | return; | |
2349 | } | |
55a5e60b ASJ |
2350 | |
2351 | tx_ring->atr_count++; | |
2352 | ||
ce806783 ASJ |
2353 | /* sample on all syn/fin/rst packets or once every atr sample rate */ |
2354 | if (!th->fin && | |
2355 | !th->syn && | |
2356 | !th->rst && | |
2357 | (tx_ring->atr_count < tx_ring->atr_sample_rate)) | |
fd0a05ce JB |
2358 | return; |
2359 | ||
2360 | tx_ring->atr_count = 0; | |
2361 | ||
2362 | /* grab the next descriptor */ | |
fc4ac67b AD |
2363 | i = tx_ring->next_to_use; |
2364 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
2365 | ||
2366 | i++; | |
2367 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2368 | |
2369 | flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & | |
2370 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
6b037cd4 | 2371 | flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? |
fd0a05ce JB |
2372 | (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << |
2373 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : | |
2374 | (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << | |
2375 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
2376 | ||
2377 | flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
2378 | ||
2379 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
2380 | ||
ce806783 | 2381 | dtype_cmd |= (th->fin || th->rst) ? |
fd0a05ce JB |
2382 | (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
2383 | I40E_TXD_FLTR_QW1_PCMD_SHIFT) : | |
2384 | (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
2385 | I40E_TXD_FLTR_QW1_PCMD_SHIFT); | |
2386 | ||
2387 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << | |
2388 | I40E_TXD_FLTR_QW1_DEST_SHIFT; | |
2389 | ||
2390 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << | |
2391 | I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; | |
2392 | ||
433c47de | 2393 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
6a899024 | 2394 | if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) |
60ccd45c ASJ |
2395 | dtype_cmd |= |
2396 | ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << | |
2397 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2398 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
2399 | else | |
2400 | dtype_cmd |= | |
2401 | ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << | |
2402 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2403 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
433c47de | 2404 | |
e8c5f723 | 2405 | if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) |
52eb95ef ASJ |
2406 | dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; |
2407 | ||
fd0a05ce | 2408 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); |
99753ea6 | 2409 | fdir_desc->rsvd = cpu_to_le32(0); |
fd0a05ce | 2410 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); |
99753ea6 | 2411 | fdir_desc->fd_id = cpu_to_le32(0); |
fd0a05ce JB |
2412 | } |
2413 | ||
fd0a05ce JB |
2414 | /** |
2415 | * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW | |
2416 | * @skb: send buffer | |
2417 | * @tx_ring: ring to send buffer on | |
2418 | * @flags: the tx flags to be set | |
2419 | * | |
2420 | * Checks the skb and set up correspondingly several generic transmit flags | |
2421 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
2422 | * | |
2423 | * Returns error code indicate the frame should be dropped upon error and the | |
2424 | * otherwise returns 0 to indicate the flags has been set properly. | |
2425 | **/ | |
3e587cf3 JB |
2426 | static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, |
2427 | struct i40e_ring *tx_ring, | |
2428 | u32 *flags) | |
fd0a05ce JB |
2429 | { |
2430 | __be16 protocol = skb->protocol; | |
2431 | u32 tx_flags = 0; | |
2432 | ||
31eaaccf GR |
2433 | if (protocol == htons(ETH_P_8021Q) && |
2434 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
2435 | /* When HW VLAN acceleration is turned off by the user the | |
2436 | * stack sets the protocol to 8021q so that the driver | |
2437 | * can take any steps required to support the SW only | |
2438 | * VLAN handling. In our case the driver doesn't need | |
2439 | * to take any further steps so just set the protocol | |
2440 | * to the encapsulated ethertype. | |
2441 | */ | |
2442 | skb->protocol = vlan_get_protocol(skb); | |
2443 | goto out; | |
2444 | } | |
2445 | ||
fd0a05ce | 2446 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
2447 | if (skb_vlan_tag_present(skb)) { |
2448 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
fd0a05ce JB |
2449 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
2450 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
0e2fe46c | 2451 | } else if (protocol == htons(ETH_P_8021Q)) { |
fd0a05ce | 2452 | struct vlan_hdr *vhdr, _vhdr; |
6995b36c | 2453 | |
fd0a05ce JB |
2454 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
2455 | if (!vhdr) | |
2456 | return -EINVAL; | |
2457 | ||
2458 | protocol = vhdr->h_vlan_encapsulated_proto; | |
2459 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
2460 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
2461 | } | |
2462 | ||
d40d00b1 NP |
2463 | if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) |
2464 | goto out; | |
2465 | ||
fd0a05ce | 2466 | /* Insert 802.1p priority into VLAN header */ |
38e00438 VD |
2467 | if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || |
2468 | (skb->priority != TC_PRIO_CONTROL)) { | |
fd0a05ce JB |
2469 | tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; |
2470 | tx_flags |= (skb->priority & 0x7) << | |
2471 | I40E_TX_FLAGS_VLAN_PRIO_SHIFT; | |
2472 | if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { | |
2473 | struct vlan_ethhdr *vhdr; | |
dd225bc6 FR |
2474 | int rc; |
2475 | ||
2476 | rc = skb_cow_head(skb, 0); | |
2477 | if (rc < 0) | |
2478 | return rc; | |
fd0a05ce JB |
2479 | vhdr = (struct vlan_ethhdr *)skb->data; |
2480 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
2481 | I40E_TX_FLAGS_VLAN_SHIFT); | |
2482 | } else { | |
2483 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; | |
2484 | } | |
2485 | } | |
d40d00b1 NP |
2486 | |
2487 | out: | |
fd0a05ce JB |
2488 | *flags = tx_flags; |
2489 | return 0; | |
2490 | } | |
2491 | ||
fd0a05ce JB |
2492 | /** |
2493 | * i40e_tso - set up the tso context descriptor | |
52ea3e80 | 2494 | * @first: pointer to first Tx buffer for xmit |
fd0a05ce | 2495 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 2496 | * @cd_type_cmd_tso_mss: Quad Word 1 |
fd0a05ce JB |
2497 | * |
2498 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
2499 | **/ | |
52ea3e80 AD |
2500 | static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, |
2501 | u64 *cd_type_cmd_tso_mss) | |
fd0a05ce | 2502 | { |
52ea3e80 | 2503 | struct sk_buff *skb = first->skb; |
03f9d6a5 | 2504 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
2505 | union { |
2506 | struct iphdr *v4; | |
2507 | struct ipv6hdr *v6; | |
2508 | unsigned char *hdr; | |
2509 | } ip; | |
c49a7bc3 AD |
2510 | union { |
2511 | struct tcphdr *tcp; | |
5453205c | 2512 | struct udphdr *udp; |
c49a7bc3 AD |
2513 | unsigned char *hdr; |
2514 | } l4; | |
2515 | u32 paylen, l4_offset; | |
52ea3e80 | 2516 | u16 gso_segs, gso_size; |
fd0a05ce | 2517 | int err; |
fd0a05ce | 2518 | |
e9f6563d SN |
2519 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2520 | return 0; | |
2521 | ||
fd0a05ce JB |
2522 | if (!skb_is_gso(skb)) |
2523 | return 0; | |
2524 | ||
dd225bc6 FR |
2525 | err = skb_cow_head(skb, 0); |
2526 | if (err < 0) | |
2527 | return err; | |
fd0a05ce | 2528 | |
c777019a AD |
2529 | ip.hdr = skb_network_header(skb); |
2530 | l4.hdr = skb_transport_header(skb); | |
df23075f | 2531 | |
c777019a AD |
2532 | /* initialize outer IP header fields */ |
2533 | if (ip.v4->version == 4) { | |
2534 | ip.v4->tot_len = 0; | |
2535 | ip.v4->check = 0; | |
c49a7bc3 | 2536 | } else { |
c777019a AD |
2537 | ip.v6->payload_len = 0; |
2538 | } | |
2539 | ||
577389a5 | 2540 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 2541 | SKB_GSO_GRE_CSUM | |
7e13318d | 2542 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 2543 | SKB_GSO_IPXIP6 | |
577389a5 | 2544 | SKB_GSO_UDP_TUNNEL | |
5453205c | 2545 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
2546 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
2547 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
2548 | l4.udp->len = 0; | |
2549 | ||
5453205c AD |
2550 | /* determine offset of outer transport header */ |
2551 | l4_offset = l4.hdr - skb->data; | |
2552 | ||
2553 | /* remove payload length from outer checksum */ | |
24d41e5e | 2554 | paylen = skb->len - l4_offset; |
b9c015d4 JK |
2555 | csum_replace_by_diff(&l4.udp->check, |
2556 | (__force __wsum)htonl(paylen)); | |
5453205c AD |
2557 | } |
2558 | ||
c777019a AD |
2559 | /* reset pointers to inner headers */ |
2560 | ip.hdr = skb_inner_network_header(skb); | |
2561 | l4.hdr = skb_inner_transport_header(skb); | |
2562 | ||
2563 | /* initialize inner IP header fields */ | |
2564 | if (ip.v4->version == 4) { | |
2565 | ip.v4->tot_len = 0; | |
2566 | ip.v4->check = 0; | |
2567 | } else { | |
2568 | ip.v6->payload_len = 0; | |
2569 | } | |
fd0a05ce JB |
2570 | } |
2571 | ||
c49a7bc3 AD |
2572 | /* determine offset of inner transport header */ |
2573 | l4_offset = l4.hdr - skb->data; | |
2574 | ||
2575 | /* remove payload length from inner checksum */ | |
24d41e5e | 2576 | paylen = skb->len - l4_offset; |
b9c015d4 | 2577 | csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); |
c49a7bc3 AD |
2578 | |
2579 | /* compute length of segmentation header */ | |
2580 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
fd0a05ce | 2581 | |
52ea3e80 AD |
2582 | /* pull values out of skb_shinfo */ |
2583 | gso_size = skb_shinfo(skb)->gso_size; | |
2584 | gso_segs = skb_shinfo(skb)->gso_segs; | |
2585 | ||
2586 | /* update GSO size and bytecount with header size */ | |
2587 | first->gso_segs = gso_segs; | |
2588 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
2589 | ||
fd0a05ce JB |
2590 | /* find the field values */ |
2591 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
2592 | cd_tso_len = skb->len - *hdr_len; | |
52ea3e80 | 2593 | cd_mss = gso_size; |
03f9d6a5 AD |
2594 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
2595 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
2596 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
fd0a05ce JB |
2597 | return 1; |
2598 | } | |
2599 | ||
beb0dff1 JK |
2600 | /** |
2601 | * i40e_tsyn - set up the tsyn context descriptor | |
2602 | * @tx_ring: ptr to the ring to send | |
2603 | * @skb: ptr to the skb we're sending | |
2604 | * @tx_flags: the collected send information | |
9c883bd3 | 2605 | * @cd_type_cmd_tso_mss: Quad Word 1 |
beb0dff1 JK |
2606 | * |
2607 | * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen | |
2608 | **/ | |
2609 | static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2610 | u32 tx_flags, u64 *cd_type_cmd_tso_mss) | |
2611 | { | |
2612 | struct i40e_pf *pf; | |
2613 | ||
2614 | if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) | |
2615 | return 0; | |
2616 | ||
2617 | /* Tx timestamps cannot be sampled when doing TSO */ | |
2618 | if (tx_flags & I40E_TX_FLAGS_TSO) | |
2619 | return 0; | |
2620 | ||
2621 | /* only timestamp the outbound packet if the user has requested it and | |
2622 | * we are not already transmitting a packet to be timestamped | |
2623 | */ | |
2624 | pf = i40e_netdev_to_pf(tx_ring->netdev); | |
22b4777d JK |
2625 | if (!(pf->flags & I40E_FLAG_PTP)) |
2626 | return 0; | |
2627 | ||
9ce34f02 | 2628 | if (pf->ptp_tx && |
0da36b97 | 2629 | !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) { |
beb0dff1 JK |
2630 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
2631 | pf->ptp_tx_skb = skb_get(skb); | |
2632 | } else { | |
2633 | return 0; | |
2634 | } | |
2635 | ||
2636 | *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << | |
2637 | I40E_TXD_CTX_QW1_CMD_SHIFT; | |
2638 | ||
beb0dff1 JK |
2639 | return 1; |
2640 | } | |
2641 | ||
fd0a05ce JB |
2642 | /** |
2643 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
2644 | * @skb: send buffer | |
89232c3b | 2645 | * @tx_flags: pointer to Tx flags currently set |
fd0a05ce JB |
2646 | * @td_cmd: Tx descriptor command bits to set |
2647 | * @td_offset: Tx descriptor header offsets to set | |
554f4544 | 2648 | * @tx_ring: Tx descriptor ring |
fd0a05ce JB |
2649 | * @cd_tunneling: ptr to context desc bits |
2650 | **/ | |
529f1f65 AD |
2651 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
2652 | u32 *td_cmd, u32 *td_offset, | |
2653 | struct i40e_ring *tx_ring, | |
2654 | u32 *cd_tunneling) | |
fd0a05ce | 2655 | { |
b96b78f2 AD |
2656 | union { |
2657 | struct iphdr *v4; | |
2658 | struct ipv6hdr *v6; | |
2659 | unsigned char *hdr; | |
2660 | } ip; | |
2661 | union { | |
2662 | struct tcphdr *tcp; | |
2663 | struct udphdr *udp; | |
2664 | unsigned char *hdr; | |
2665 | } l4; | |
a3fd9d88 | 2666 | unsigned char *exthdr; |
d1bd743b | 2667 | u32 offset, cmd = 0; |
a3fd9d88 | 2668 | __be16 frag_off; |
b96b78f2 AD |
2669 | u8 l4_proto = 0; |
2670 | ||
529f1f65 AD |
2671 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2672 | return 0; | |
2673 | ||
b96b78f2 AD |
2674 | ip.hdr = skb_network_header(skb); |
2675 | l4.hdr = skb_transport_header(skb); | |
fd0a05ce | 2676 | |
475b4205 AD |
2677 | /* compute outer L2 header size */ |
2678 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
2679 | ||
fd0a05ce | 2680 | if (skb->encapsulation) { |
d1bd743b | 2681 | u32 tunnel = 0; |
a0064728 AD |
2682 | /* define outer network header type */ |
2683 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
2684 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2685 | I40E_TX_CTX_EXT_IP_IPV4 : | |
2686 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
2687 | ||
a0064728 AD |
2688 | l4_proto = ip.v4->protocol; |
2689 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 2690 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
2691 | |
2692 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 2693 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
2694 | if (l4.hdr != exthdr) |
2695 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2696 | &l4_proto, &frag_off); | |
a0064728 AD |
2697 | } |
2698 | ||
2699 | /* define outer transport */ | |
2700 | switch (l4_proto) { | |
45991204 | 2701 | case IPPROTO_UDP: |
475b4205 | 2702 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
6a899024 | 2703 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
45991204 | 2704 | break; |
c1d1791d | 2705 | case IPPROTO_GRE: |
475b4205 | 2706 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 | 2707 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
c1d1791d | 2708 | break; |
577389a5 AD |
2709 | case IPPROTO_IPIP: |
2710 | case IPPROTO_IPV6: | |
2711 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; | |
2712 | l4.hdr = skb_inner_network_header(skb); | |
2713 | break; | |
45991204 | 2714 | default: |
529f1f65 AD |
2715 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2716 | return -1; | |
2717 | ||
2718 | skb_checksum_help(skb); | |
2719 | return 0; | |
45991204 | 2720 | } |
b96b78f2 | 2721 | |
577389a5 AD |
2722 | /* compute outer L3 header size */ |
2723 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
2724 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
2725 | ||
2726 | /* switch IP header pointer from outer to inner header */ | |
2727 | ip.hdr = skb_inner_network_header(skb); | |
2728 | ||
475b4205 AD |
2729 | /* compute tunnel header size */ |
2730 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
2731 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
2732 | ||
5453205c AD |
2733 | /* indicate if we need to offload outer UDP header */ |
2734 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 2735 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
2736 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
2737 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
2738 | ||
475b4205 AD |
2739 | /* record tunnel offload values */ |
2740 | *cd_tunneling |= tunnel; | |
2741 | ||
b96b78f2 | 2742 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 2743 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 2744 | l4_proto = 0; |
fd0a05ce | 2745 | |
a0064728 AD |
2746 | /* reset type as we transition from outer to inner headers */ |
2747 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
2748 | if (ip.v4->version == 4) | |
2749 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
2750 | if (ip.v6->version == 6) | |
89232c3b | 2751 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
fd0a05ce JB |
2752 | } |
2753 | ||
2754 | /* Enable IP checksum offloads */ | |
89232c3b | 2755 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 2756 | l4_proto = ip.v4->protocol; |
fd0a05ce JB |
2757 | /* the stack computes the IP header already, the only time we |
2758 | * need the hardware to recompute it is in the case of TSO. | |
2759 | */ | |
475b4205 AD |
2760 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2761 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
2762 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 2763 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 2764 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
2765 | |
2766 | exthdr = ip.hdr + sizeof(*ip.v6); | |
2767 | l4_proto = ip.v6->nexthdr; | |
2768 | if (l4.hdr != exthdr) | |
2769 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2770 | &l4_proto, &frag_off); | |
fd0a05ce | 2771 | } |
b96b78f2 | 2772 | |
475b4205 AD |
2773 | /* compute inner L3 header size */ |
2774 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
fd0a05ce JB |
2775 | |
2776 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 2777 | switch (l4_proto) { |
fd0a05ce JB |
2778 | case IPPROTO_TCP: |
2779 | /* enable checksum offloads */ | |
475b4205 AD |
2780 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
2781 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2782 | break; |
2783 | case IPPROTO_SCTP: | |
2784 | /* enable SCTP checksum offload */ | |
475b4205 AD |
2785 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
2786 | offset |= (sizeof(struct sctphdr) >> 2) << | |
2787 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2788 | break; |
2789 | case IPPROTO_UDP: | |
2790 | /* enable UDP checksum offload */ | |
475b4205 AD |
2791 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
2792 | offset |= (sizeof(struct udphdr) >> 2) << | |
2793 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2794 | break; |
2795 | default: | |
529f1f65 AD |
2796 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2797 | return -1; | |
2798 | skb_checksum_help(skb); | |
2799 | return 0; | |
fd0a05ce | 2800 | } |
475b4205 AD |
2801 | |
2802 | *td_cmd |= cmd; | |
2803 | *td_offset |= offset; | |
529f1f65 AD |
2804 | |
2805 | return 1; | |
fd0a05ce JB |
2806 | } |
2807 | ||
2808 | /** | |
2809 | * i40e_create_tx_ctx Build the Tx context descriptor | |
2810 | * @tx_ring: ring to create the descriptor on | |
2811 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
2812 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
2813 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
2814 | **/ | |
2815 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
2816 | const u64 cd_type_cmd_tso_mss, | |
2817 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
2818 | { | |
2819 | struct i40e_tx_context_desc *context_desc; | |
fc4ac67b | 2820 | int i = tx_ring->next_to_use; |
fd0a05ce | 2821 | |
ff40dd5d JB |
2822 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
2823 | !cd_tunneling && !cd_l2tag2) | |
fd0a05ce JB |
2824 | return; |
2825 | ||
2826 | /* grab the next descriptor */ | |
fc4ac67b AD |
2827 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); |
2828 | ||
2829 | i++; | |
2830 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2831 | |
2832 | /* cpu_to_le32 and assign to struct fields */ | |
2833 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
2834 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 2835 | context_desc->rsvd = cpu_to_le16(0); |
fd0a05ce JB |
2836 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
2837 | } | |
2838 | ||
4567dc10 ED |
2839 | /** |
2840 | * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions | |
2841 | * @tx_ring: the ring to be checked | |
2842 | * @size: the size buffer we want to assure is available | |
2843 | * | |
2844 | * Returns -EBUSY if a stop is needed, else 0 | |
2845 | **/ | |
4ec441df | 2846 | int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
4567dc10 ED |
2847 | { |
2848 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2849 | /* Memory barrier before checking head and tail */ | |
2850 | smp_mb(); | |
2851 | ||
2852 | /* Check again in a case another CPU has just made room available. */ | |
2853 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
2854 | return -EBUSY; | |
2855 | ||
2856 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
2857 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2858 | ++tx_ring->tx_stats.restart_queue; | |
2859 | return 0; | |
2860 | } | |
2861 | ||
71da6197 | 2862 | /** |
3f3f7cb8 | 2863 | * __i40e_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 2864 | * @skb: send buffer |
71da6197 | 2865 | * |
3f3f7cb8 AD |
2866 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
2867 | * and so we need to figure out the cases where we need to linearize the skb. | |
2868 | * | |
2869 | * For TSO we need to count the TSO header and segment payload separately. | |
2870 | * As such we need to check cases where we have 7 fragments or more as we | |
2871 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
2872 | * the segment payload in the first descriptor, and another 7 for the | |
2873 | * fragments. | |
71da6197 | 2874 | **/ |
2d37490b | 2875 | bool __i40e_chk_linearize(struct sk_buff *skb) |
71da6197 | 2876 | { |
2d37490b | 2877 | const struct skb_frag_struct *frag, *stale; |
3f3f7cb8 | 2878 | int nr_frags, sum; |
71da6197 | 2879 | |
3f3f7cb8 | 2880 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 2881 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 2882 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 2883 | return false; |
71da6197 | 2884 | |
2d37490b | 2885 | /* We need to walk through the list and validate that each group |
841493a3 | 2886 | * of 6 fragments totals at least gso_size. |
2d37490b | 2887 | */ |
3f3f7cb8 | 2888 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
2889 | frag = &skb_shinfo(skb)->frags[0]; |
2890 | ||
2891 | /* Initialize size to the negative value of gso_size minus 1. We | |
2892 | * use this as the worst case scenerio in which the frag ahead | |
2893 | * of us only provides one byte which is why we are limited to 6 | |
2894 | * descriptors for a single transmit as the header and previous | |
2895 | * fragment are already consuming 2 descriptors. | |
2896 | */ | |
3f3f7cb8 | 2897 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 2898 | |
3f3f7cb8 AD |
2899 | /* Add size of frags 0 through 4 to create our initial sum */ |
2900 | sum += skb_frag_size(frag++); | |
2901 | sum += skb_frag_size(frag++); | |
2902 | sum += skb_frag_size(frag++); | |
2903 | sum += skb_frag_size(frag++); | |
2904 | sum += skb_frag_size(frag++); | |
2d37490b AD |
2905 | |
2906 | /* Walk through fragments adding latest fragment, testing it, and | |
2907 | * then removing stale fragments from the sum. | |
2908 | */ | |
2909 | stale = &skb_shinfo(skb)->frags[0]; | |
2910 | for (;;) { | |
3f3f7cb8 | 2911 | sum += skb_frag_size(frag++); |
2d37490b AD |
2912 | |
2913 | /* if sum is negative we failed to make sufficient progress */ | |
2914 | if (sum < 0) | |
2915 | return true; | |
2916 | ||
841493a3 | 2917 | if (!nr_frags--) |
2d37490b AD |
2918 | break; |
2919 | ||
3f3f7cb8 | 2920 | sum -= skb_frag_size(stale++); |
71da6197 AS |
2921 | } |
2922 | ||
2d37490b | 2923 | return false; |
71da6197 AS |
2924 | } |
2925 | ||
fd0a05ce JB |
2926 | /** |
2927 | * i40e_tx_map - Build the Tx descriptor | |
2928 | * @tx_ring: ring to send buffer on | |
2929 | * @skb: send buffer | |
2930 | * @first: first buffer info buffer to use | |
2931 | * @tx_flags: collected send information | |
2932 | * @hdr_len: size of the packet header | |
2933 | * @td_cmd: the command field in the descriptor | |
2934 | * @td_offset: offset for checksum or crc | |
2935 | **/ | |
3e587cf3 JB |
2936 | static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
2937 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2938 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
fd0a05ce | 2939 | { |
fd0a05ce JB |
2940 | unsigned int data_len = skb->data_len; |
2941 | unsigned int size = skb_headlen(skb); | |
a5e9c572 | 2942 | struct skb_frag_struct *frag; |
fd0a05ce JB |
2943 | struct i40e_tx_buffer *tx_bi; |
2944 | struct i40e_tx_desc *tx_desc; | |
a5e9c572 | 2945 | u16 i = tx_ring->next_to_use; |
fd0a05ce JB |
2946 | u32 td_tag = 0; |
2947 | dma_addr_t dma; | |
1dc8b538 | 2948 | u16 desc_count = 1; |
fd0a05ce | 2949 | |
fd0a05ce JB |
2950 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { |
2951 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2952 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2953 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2954 | } | |
2955 | ||
a5e9c572 AD |
2956 | first->tx_flags = tx_flags; |
2957 | ||
2958 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2959 | ||
fd0a05ce | 2960 | tx_desc = I40E_TX_DESC(tx_ring, i); |
a5e9c572 AD |
2961 | tx_bi = first; |
2962 | ||
2963 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
2964 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
2965 | ||
a5e9c572 AD |
2966 | if (dma_mapping_error(tx_ring->dev, dma)) |
2967 | goto dma_error; | |
2968 | ||
2969 | /* record length, and DMA address */ | |
2970 | dma_unmap_len_set(tx_bi, len, size); | |
2971 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2972 | ||
5c4654da AD |
2973 | /* align size to end of page */ |
2974 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
a5e9c572 AD |
2975 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2976 | ||
2977 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
fd0a05ce JB |
2978 | tx_desc->cmd_type_offset_bsz = |
2979 | build_ctob(td_cmd, td_offset, | |
5c4654da | 2980 | max_data, td_tag); |
fd0a05ce | 2981 | |
fd0a05ce JB |
2982 | tx_desc++; |
2983 | i++; | |
58044743 AS |
2984 | desc_count++; |
2985 | ||
fd0a05ce JB |
2986 | if (i == tx_ring->count) { |
2987 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2988 | i = 0; | |
2989 | } | |
fd0a05ce | 2990 | |
5c4654da AD |
2991 | dma += max_data; |
2992 | size -= max_data; | |
fd0a05ce | 2993 | |
5c4654da | 2994 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
a5e9c572 AD |
2995 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2996 | } | |
fd0a05ce JB |
2997 | |
2998 | if (likely(!data_len)) | |
2999 | break; | |
3000 | ||
a5e9c572 AD |
3001 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, |
3002 | size, td_tag); | |
fd0a05ce JB |
3003 | |
3004 | tx_desc++; | |
3005 | i++; | |
58044743 AS |
3006 | desc_count++; |
3007 | ||
fd0a05ce JB |
3008 | if (i == tx_ring->count) { |
3009 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3010 | i = 0; | |
3011 | } | |
3012 | ||
a5e9c572 AD |
3013 | size = skb_frag_size(frag); |
3014 | data_len -= size; | |
fd0a05ce | 3015 | |
a5e9c572 AD |
3016 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
3017 | DMA_TO_DEVICE); | |
fd0a05ce | 3018 | |
a5e9c572 AD |
3019 | tx_bi = &tx_ring->tx_bi[i]; |
3020 | } | |
fd0a05ce | 3021 | |
1dc8b538 | 3022 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
a5e9c572 AD |
3023 | |
3024 | i++; | |
3025 | if (i == tx_ring->count) | |
3026 | i = 0; | |
3027 | ||
3028 | tx_ring->next_to_use = i; | |
3029 | ||
4567dc10 | 3030 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
58044743 | 3031 | |
1dc8b538 AD |
3032 | /* write last descriptor with EOP bit */ |
3033 | td_cmd |= I40E_TX_DESC_CMD_EOP; | |
3034 | ||
3035 | /* We can OR these values together as they both are checked against | |
3036 | * 4 below and at this point desc_count will be used as a boolean value | |
3037 | * after this if/else block. | |
3038 | */ | |
3039 | desc_count |= ++tx_ring->packet_stride; | |
3040 | ||
58044743 | 3041 | /* Algorithm to optimize tail and RS bit setting: |
1dc8b538 AD |
3042 | * if queue is stopped |
3043 | * mark RS bit | |
3044 | * reset packet counter | |
3045 | * else if xmit_more is supported and is true | |
3046 | * advance packet counter to 4 | |
3047 | * reset desc_count to 0 | |
58044743 | 3048 | * |
1dc8b538 AD |
3049 | * if desc_count >= 4 |
3050 | * mark RS bit | |
3051 | * reset packet counter | |
3052 | * if desc_count > 0 | |
3053 | * update tail | |
58044743 | 3054 | * |
1dc8b538 | 3055 | * Note: If there are less than 4 descriptors |
58044743 AS |
3056 | * pending and interrupts were disabled the service task will |
3057 | * trigger a force WB. | |
3058 | */ | |
1dc8b538 AD |
3059 | if (netif_xmit_stopped(txring_txq(tx_ring))) { |
3060 | goto do_rs; | |
3061 | } else if (skb->xmit_more) { | |
3062 | /* set stride to arm on next packet and reset desc_count */ | |
3063 | tx_ring->packet_stride = WB_STRIDE; | |
3064 | desc_count = 0; | |
3065 | } else if (desc_count >= WB_STRIDE) { | |
3066 | do_rs: | |
3067 | /* write last descriptor with RS bit set */ | |
3068 | td_cmd |= I40E_TX_DESC_CMD_RS; | |
58044743 | 3069 | tx_ring->packet_stride = 0; |
58044743 | 3070 | } |
58044743 AS |
3071 | |
3072 | tx_desc->cmd_type_offset_bsz = | |
1dc8b538 AD |
3073 | build_ctob(td_cmd, td_offset, size, td_tag); |
3074 | ||
3075 | /* Force memory writes to complete before letting h/w know there | |
3076 | * are new descriptors to fetch. | |
3077 | * | |
3078 | * We also use this memory barrier to make certain all of the | |
3079 | * status bits have been updated before next_to_watch is written. | |
3080 | */ | |
3081 | wmb(); | |
3082 | ||
3083 | /* set next_to_watch value indicating a packet is present */ | |
3084 | first->next_to_watch = tx_desc; | |
58044743 | 3085 | |
a5e9c572 | 3086 | /* notify HW of packet */ |
1dc8b538 | 3087 | if (desc_count) { |
58044743 | 3088 | writel(i, tx_ring->tail); |
1dc8b538 AD |
3089 | |
3090 | /* we need this if more than one processor can write to our tail | |
3091 | * at a time, it synchronizes IO on IA64/Altix systems | |
3092 | */ | |
3093 | mmiowb(); | |
58044743 | 3094 | } |
1dc8b538 | 3095 | |
fd0a05ce JB |
3096 | return; |
3097 | ||
3098 | dma_error: | |
a5e9c572 | 3099 | dev_info(tx_ring->dev, "TX DMA map failed\n"); |
fd0a05ce JB |
3100 | |
3101 | /* clear dma mappings for failed tx_bi map */ | |
3102 | for (;;) { | |
3103 | tx_bi = &tx_ring->tx_bi[i]; | |
a5e9c572 | 3104 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); |
fd0a05ce JB |
3105 | if (tx_bi == first) |
3106 | break; | |
3107 | if (i == 0) | |
3108 | i = tx_ring->count; | |
3109 | i--; | |
3110 | } | |
3111 | ||
fd0a05ce JB |
3112 | tx_ring->next_to_use = i; |
3113 | } | |
3114 | ||
fd0a05ce JB |
3115 | /** |
3116 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
3117 | * @skb: send buffer | |
3118 | * @tx_ring: ring to send buffer on | |
3119 | * | |
3120 | * Returns NETDEV_TX_OK if sent, else an error code | |
3121 | **/ | |
3122 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
3123 | struct i40e_ring *tx_ring) | |
3124 | { | |
3125 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
3126 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
3127 | struct i40e_tx_buffer *first; | |
3128 | u32 td_offset = 0; | |
3129 | u32 tx_flags = 0; | |
3130 | __be16 protocol; | |
3131 | u32 td_cmd = 0; | |
3132 | u8 hdr_len = 0; | |
4ec441df | 3133 | int tso, count; |
beb0dff1 | 3134 | int tsyn; |
6995b36c | 3135 | |
b74118f0 JB |
3136 | /* prefetch the data, we'll need it later */ |
3137 | prefetch(skb->data); | |
3138 | ||
ed0980c4 SP |
3139 | i40e_trace(xmit_frame_ring, skb, tx_ring); |
3140 | ||
4ec441df | 3141 | count = i40e_xmit_descriptor_count(skb); |
2d37490b | 3142 | if (i40e_chk_linearize(skb, count)) { |
52ea3e80 AD |
3143 | if (__skb_linearize(skb)) { |
3144 | dev_kfree_skb_any(skb); | |
3145 | return NETDEV_TX_OK; | |
3146 | } | |
5c4654da | 3147 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
3148 | tx_ring->tx_stats.tx_linearize++; |
3149 | } | |
4ec441df AD |
3150 | |
3151 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
3152 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
3153 | * + 4 desc gap to avoid the cache line where head is, | |
3154 | * + 1 desc for context descriptor, | |
3155 | * otherwise try next time | |
3156 | */ | |
3157 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
3158 | tx_ring->tx_stats.tx_busy++; | |
fd0a05ce | 3159 | return NETDEV_TX_BUSY; |
4ec441df | 3160 | } |
fd0a05ce | 3161 | |
52ea3e80 AD |
3162 | /* record the location of the first descriptor for this packet */ |
3163 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
3164 | first->skb = skb; | |
3165 | first->bytecount = skb->len; | |
3166 | first->gso_segs = 1; | |
3167 | ||
fd0a05ce JB |
3168 | /* prepare the xmit flags */ |
3169 | if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) | |
3170 | goto out_drop; | |
3171 | ||
3172 | /* obtain protocol of skb */ | |
3d34dd03 | 3173 | protocol = vlan_get_protocol(skb); |
fd0a05ce | 3174 | |
fd0a05ce | 3175 | /* setup IPv4/IPv6 offloads */ |
0e2fe46c | 3176 | if (protocol == htons(ETH_P_IP)) |
fd0a05ce | 3177 | tx_flags |= I40E_TX_FLAGS_IPV4; |
0e2fe46c | 3178 | else if (protocol == htons(ETH_P_IPV6)) |
fd0a05ce JB |
3179 | tx_flags |= I40E_TX_FLAGS_IPV6; |
3180 | ||
52ea3e80 | 3181 | tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); |
fd0a05ce JB |
3182 | |
3183 | if (tso < 0) | |
3184 | goto out_drop; | |
3185 | else if (tso) | |
3186 | tx_flags |= I40E_TX_FLAGS_TSO; | |
3187 | ||
3bc67973 AD |
3188 | /* Always offload the checksum, since it's in the data descriptor */ |
3189 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, | |
3190 | tx_ring, &cd_tunneling); | |
3191 | if (tso < 0) | |
3192 | goto out_drop; | |
3193 | ||
beb0dff1 JK |
3194 | tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); |
3195 | ||
3196 | if (tsyn) | |
3197 | tx_flags |= I40E_TX_FLAGS_TSYN; | |
3198 | ||
259afec7 JK |
3199 | skb_tx_timestamp(skb); |
3200 | ||
b1941306 AD |
3201 | /* always enable CRC insertion offload */ |
3202 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
3203 | ||
fd0a05ce JB |
3204 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
3205 | cd_tunneling, cd_l2tag2); | |
3206 | ||
3207 | /* Add Flow Director ATR if it's enabled. | |
3208 | * | |
3209 | * NOTE: this must always be directly before the data descriptor. | |
3210 | */ | |
6b037cd4 | 3211 | i40e_atr(tx_ring, skb, tx_flags); |
fd0a05ce JB |
3212 | |
3213 | i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, | |
3214 | td_cmd, td_offset); | |
3215 | ||
fd0a05ce JB |
3216 | return NETDEV_TX_OK; |
3217 | ||
3218 | out_drop: | |
ed0980c4 | 3219 | i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); |
52ea3e80 AD |
3220 | dev_kfree_skb_any(first->skb); |
3221 | first->skb = NULL; | |
fd0a05ce JB |
3222 | return NETDEV_TX_OK; |
3223 | } | |
3224 | ||
3225 | /** | |
3226 | * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
3227 | * @skb: send buffer | |
3228 | * @netdev: network interface device structure | |
3229 | * | |
3230 | * Returns NETDEV_TX_OK if sent, else an error code | |
3231 | **/ | |
3232 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
3233 | { | |
3234 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
3235 | struct i40e_vsi *vsi = np->vsi; | |
9f65e15b | 3236 | struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; |
fd0a05ce JB |
3237 | |
3238 | /* hardware can't handle really short frames, hardware padding works | |
3239 | * beyond this point | |
3240 | */ | |
a94d9e22 AD |
3241 | if (skb_put_padto(skb, I40E_MIN_TX_LEN)) |
3242 | return NETDEV_TX_OK; | |
fd0a05ce JB |
3243 | |
3244 | return i40e_xmit_frame_ring(skb, tx_ring); | |
3245 | } |