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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_txrx.c
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fd0a05ce
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e.h"
29
30static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
31 u32 td_tag)
32{
33 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
34 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
35 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
36 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
37 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
38}
39
40/**
41 * i40e_program_fdir_filter - Program a Flow Director filter
42 * @fdir_input: Packet data that will be filter parameters
43 * @pf: The pf pointer
44 * @add: True for add/update, False for remove
45 **/
46int i40e_program_fdir_filter(struct i40e_fdir_data *fdir_data,
47 struct i40e_pf *pf, bool add)
48{
49 struct i40e_filter_program_desc *fdir_desc;
50 struct i40e_tx_buffer *tx_buf;
51 struct i40e_tx_desc *tx_desc;
52 struct i40e_ring *tx_ring;
53 struct i40e_vsi *vsi;
54 struct device *dev;
55 dma_addr_t dma;
56 u32 td_cmd = 0;
57 u16 i;
58
59 /* find existing FDIR VSI */
60 vsi = NULL;
61 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
62 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
63 vsi = pf->vsi[i];
64 if (!vsi)
65 return -ENOENT;
66
67 tx_ring = &vsi->tx_rings[0];
68 dev = tx_ring->dev;
69
70 dma = dma_map_single(dev, fdir_data->raw_packet,
71 I40E_FDIR_MAX_RAW_PACKET_LOOKUP, DMA_TO_DEVICE);
72 if (dma_mapping_error(dev, dma))
73 goto dma_fail;
74
75 /* grab the next descriptor */
76 fdir_desc = I40E_TX_FDIRDESC(tx_ring, tx_ring->next_to_use);
77 tx_buf = &tx_ring->tx_bi[tx_ring->next_to_use];
78 tx_ring->next_to_use++;
79 if (tx_ring->next_to_use == tx_ring->count)
80 tx_ring->next_to_use = 0;
81
82 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32((fdir_data->q_index
83 << I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
84 & I40E_TXD_FLTR_QW0_QINDEX_MASK);
85
86 fdir_desc->qindex_flex_ptype_vsi |= cpu_to_le32((fdir_data->flex_off
87 << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
88 & I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
89
90 fdir_desc->qindex_flex_ptype_vsi |= cpu_to_le32((fdir_data->pctype
91 << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
92 & I40E_TXD_FLTR_QW0_PCTYPE_MASK);
93
94 /* Use LAN VSI Id if not programmed by user */
95 if (fdir_data->dest_vsi == 0)
96 fdir_desc->qindex_flex_ptype_vsi |=
97 cpu_to_le32((pf->vsi[pf->lan_vsi]->id)
98 << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
99 else
100 fdir_desc->qindex_flex_ptype_vsi |=
101 cpu_to_le32((fdir_data->dest_vsi
102 << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
103 & I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
104
105 fdir_desc->dtype_cmd_cntindex =
106 cpu_to_le32(I40E_TX_DESC_DTYPE_FILTER_PROG);
107
108 if (add)
109 fdir_desc->dtype_cmd_cntindex |= cpu_to_le32(
110 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE
111 << I40E_TXD_FLTR_QW1_PCMD_SHIFT);
112 else
113 fdir_desc->dtype_cmd_cntindex |= cpu_to_le32(
114 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE
115 << I40E_TXD_FLTR_QW1_PCMD_SHIFT);
116
117 fdir_desc->dtype_cmd_cntindex |= cpu_to_le32((fdir_data->dest_ctl
118 << I40E_TXD_FLTR_QW1_DEST_SHIFT)
119 & I40E_TXD_FLTR_QW1_DEST_MASK);
120
121 fdir_desc->dtype_cmd_cntindex |= cpu_to_le32(
122 (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
123 & I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
124
125 if (fdir_data->cnt_index != 0) {
126 fdir_desc->dtype_cmd_cntindex |=
127 cpu_to_le32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
128 fdir_desc->dtype_cmd_cntindex |=
129 cpu_to_le32((fdir_data->cnt_index
130 << I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
131 & I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
132 }
133
134 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
135
136 /* Now program a dummy descriptor */
137 tx_desc = I40E_TX_DESC(tx_ring, tx_ring->next_to_use);
138 tx_buf = &tx_ring->tx_bi[tx_ring->next_to_use];
139 tx_ring->next_to_use++;
140 if (tx_ring->next_to_use == tx_ring->count)
141 tx_ring->next_to_use = 0;
142
143 tx_desc->buffer_addr = cpu_to_le64(dma);
144 td_cmd = I40E_TX_DESC_CMD_EOP |
145 I40E_TX_DESC_CMD_RS |
146 I40E_TX_DESC_CMD_DUMMY;
147
148 tx_desc->cmd_type_offset_bsz =
149 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_LOOKUP, 0);
150
151 /* Mark the data descriptor to be watched */
152 tx_buf->next_to_watch = tx_desc;
153
154 /* Force memory writes to complete before letting h/w
155 * know there are new descriptors to fetch. (Only
156 * applicable for weak-ordered memory model archs,
157 * such as IA-64).
158 */
159 wmb();
160
161 writel(tx_ring->next_to_use, tx_ring->tail);
162 return 0;
163
164dma_fail:
165 return -1;
166}
167
168/**
169 * i40e_fd_handle_status - check the Programming Status for FD
170 * @rx_ring: the Rx ring for this descriptor
171 * @qw: the descriptor data
172 * @prog_id: the id originally used for programming
173 *
174 * This is used to verify if the FD programming or invalidation
175 * requested by SW to the HW is successful or not and take actions accordingly.
176 **/
177static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u32 qw, u8 prog_id)
178{
179 struct pci_dev *pdev = rx_ring->vsi->back->pdev;
180 u32 error;
181
182 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
183 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
184
185 /* for now just print the Status */
186 dev_info(&pdev->dev, "FD programming id %02x, Status %08x\n",
187 prog_id, error);
188}
189
190/**
191 * i40e_unmap_tx_resource - Release a Tx buffer
192 * @ring: the ring that owns the buffer
193 * @tx_buffer: the buffer to free
194 **/
195static inline void i40e_unmap_tx_resource(struct i40e_ring *ring,
196 struct i40e_tx_buffer *tx_buffer)
197{
198 if (tx_buffer->dma) {
199 if (tx_buffer->tx_flags & I40E_TX_FLAGS_MAPPED_AS_PAGE)
200 dma_unmap_page(ring->dev,
201 tx_buffer->dma,
202 tx_buffer->length,
203 DMA_TO_DEVICE);
204 else
205 dma_unmap_single(ring->dev,
206 tx_buffer->dma,
207 tx_buffer->length,
208 DMA_TO_DEVICE);
209 }
210 tx_buffer->dma = 0;
211 tx_buffer->time_stamp = 0;
212}
213
214/**
215 * i40e_clean_tx_ring - Free any empty Tx buffers
216 * @tx_ring: ring to be cleaned
217 **/
218void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
219{
220 struct i40e_tx_buffer *tx_buffer;
221 unsigned long bi_size;
222 u16 i;
223
224 /* ring already cleared, nothing to do */
225 if (!tx_ring->tx_bi)
226 return;
227
228 /* Free all the Tx ring sk_buffs */
229 for (i = 0; i < tx_ring->count; i++) {
230 tx_buffer = &tx_ring->tx_bi[i];
231 i40e_unmap_tx_resource(tx_ring, tx_buffer);
232 if (tx_buffer->skb)
233 dev_kfree_skb_any(tx_buffer->skb);
234 tx_buffer->skb = NULL;
235 }
236
237 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
238 memset(tx_ring->tx_bi, 0, bi_size);
239
240 /* Zero out the descriptor ring */
241 memset(tx_ring->desc, 0, tx_ring->size);
242
243 tx_ring->next_to_use = 0;
244 tx_ring->next_to_clean = 0;
245}
246
247/**
248 * i40e_free_tx_resources - Free Tx resources per queue
249 * @tx_ring: Tx descriptor ring for a specific queue
250 *
251 * Free all transmit software resources
252 **/
253void i40e_free_tx_resources(struct i40e_ring *tx_ring)
254{
255 i40e_clean_tx_ring(tx_ring);
256 kfree(tx_ring->tx_bi);
257 tx_ring->tx_bi = NULL;
258
259 if (tx_ring->desc) {
260 dma_free_coherent(tx_ring->dev, tx_ring->size,
261 tx_ring->desc, tx_ring->dma);
262 tx_ring->desc = NULL;
263 }
264}
265
266/**
267 * i40e_get_tx_pending - how many tx descriptors not processed
268 * @tx_ring: the ring of descriptors
269 *
270 * Since there is no access to the ring head register
271 * in XL710, we need to use our local copies
272 **/
273static u32 i40e_get_tx_pending(struct i40e_ring *ring)
274{
275 u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
276 ? ring->next_to_use
277 : ring->next_to_use + ring->count);
278 return ntu - ring->next_to_clean;
279}
280
281/**
282 * i40e_check_tx_hang - Is there a hang in the Tx queue
283 * @tx_ring: the ring of descriptors
284 **/
285static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
286{
287 u32 tx_pending = i40e_get_tx_pending(tx_ring);
288 bool ret = false;
289
290 clear_check_for_tx_hang(tx_ring);
291
292 /* Check for a hung queue, but be thorough. This verifies
293 * that a transmit has been completed since the previous
294 * check AND there is at least one packet pending. The
295 * ARMED bit is set to indicate a potential hang. The
296 * bit is cleared if a pause frame is received to remove
297 * false hang detection due to PFC or 802.3x frames. By
298 * requiring this to fail twice we avoid races with
299 * PFC clearing the ARMED bit and conditions where we
300 * run the check_tx_hang logic with a transmit completion
301 * pending but without time to complete it yet.
302 */
303 if ((tx_ring->tx_stats.tx_done_old == tx_ring->tx_stats.packets) &&
304 tx_pending) {
305 /* make sure it is true for two checks in a row */
306 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
307 &tx_ring->state);
308 } else {
309 /* update completed stats and disarm the hang check */
310 tx_ring->tx_stats.tx_done_old = tx_ring->tx_stats.packets;
311 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
312 }
313
314 return ret;
315}
316
317/**
318 * i40e_clean_tx_irq - Reclaim resources after transmit completes
319 * @tx_ring: tx ring to clean
320 * @budget: how many cleans we're allowed
321 *
322 * Returns true if there's any budget left (e.g. the clean is finished)
323 **/
324static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
325{
326 u16 i = tx_ring->next_to_clean;
327 struct i40e_tx_buffer *tx_buf;
328 struct i40e_tx_desc *tx_desc;
329 unsigned int total_packets = 0;
330 unsigned int total_bytes = 0;
331
332 tx_buf = &tx_ring->tx_bi[i];
333 tx_desc = I40E_TX_DESC(tx_ring, i);
334
335 for (; budget; budget--) {
336 struct i40e_tx_desc *eop_desc;
337
338 eop_desc = tx_buf->next_to_watch;
339
340 /* if next_to_watch is not set then there is no work pending */
341 if (!eop_desc)
342 break;
343
344 /* if the descriptor isn't done, no work yet to do */
345 if (!(eop_desc->cmd_type_offset_bsz &
346 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
347 break;
348
c304fdac 349 /* clear next_to_watch to prevent false hangs */
fd0a05ce
JB		 350 tx_buf->next_to_watch = NULL;
351 tx_buf->time_stamp = 0;
352
353 /* set memory barrier before eop_desc is verified */
354 rmb();
355
356 do {
357 i40e_unmap_tx_resource(tx_ring, tx_buf);
358
359 /* clear dtype status */
360 tx_desc->cmd_type_offset_bsz &=
361 ~cpu_to_le64(I40E_TXD_QW1_DTYPE_MASK);
362
363 if (likely(tx_desc == eop_desc)) {
364 eop_desc = NULL;
365
366 dev_kfree_skb_any(tx_buf->skb);
367 tx_buf->skb = NULL;
368
369 total_bytes += tx_buf->bytecount;
370 total_packets += tx_buf->gso_segs;
371 }
372
373 tx_buf++;
374 tx_desc++;
375 i++;
376 if (unlikely(i == tx_ring->count)) {
377 i = 0;
378 tx_buf = tx_ring->tx_bi;
379 tx_desc = I40E_TX_DESC(tx_ring, 0);
380 }
381 } while (eop_desc);
382 }
383
384 tx_ring->next_to_clean = i;
385 tx_ring->tx_stats.bytes += total_bytes;
386 tx_ring->tx_stats.packets += total_packets;
387 tx_ring->q_vector->tx.total_bytes += total_bytes;
388 tx_ring->q_vector->tx.total_packets += total_packets;
389 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
390 /* schedule immediate reset if we believe we hung */
391 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
392 " VSI <%d>\n"
393 " Tx Queue <%d>\n"
394 " next_to_use <%x>\n"
395 " next_to_clean <%x>\n",
396 tx_ring->vsi->seid,
397 tx_ring->queue_index,
398 tx_ring->next_to_use, i);
399 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
400 " time_stamp <%lx>\n"
401 " jiffies <%lx>\n",
402 tx_ring->tx_bi[i].time_stamp, jiffies);
403
404 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
405
406 dev_info(tx_ring->dev,
407 "tx hang detected on queue %d, resetting adapter\n",
408 tx_ring->queue_index);
409
410 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
411
412 /* the adapter is about to reset, no point in enabling stuff */
413 return true;
414 }
415
416#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
417 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
418 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
419 /* Make sure that anybody stopping the queue after this
420 * sees the new next_to_clean.
421 */
422 smp_mb();
423 if (__netif_subqueue_stopped(tx_ring->netdev,
424 tx_ring->queue_index) &&
425 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
426 netif_wake_subqueue(tx_ring->netdev,
427 tx_ring->queue_index);
428 ++tx_ring->tx_stats.restart_queue;
429 }
430 }
431
432 return budget > 0;
433}
434
435/**
436 * i40e_set_new_dynamic_itr - Find new ITR level
437 * @rc: structure containing ring performance data
438 *
439 * Stores a new ITR value based on packets and byte counts during
440 * the last interrupt. The advantage of per interrupt computation
441 * is faster updates and more accurate ITR for the current traffic
442 * pattern. Constants in this function were computed based on
443 * theoretical maximum wire speed and thresholds were set based on
444 * testing data as well as attempting to minimize response time
445 * while increasing bulk throughput.
446 **/
447static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
448{
449 enum i40e_latency_range new_latency_range = rc->latency_range;
450 u32 new_itr = rc->itr;
451 int bytes_per_int;
452
453 if (rc->total_packets == 0 || !rc->itr)
454 return;
455
456 /* simple throttlerate management
457 * 0-10MB/s lowest (100000 ints/s)
458 * 10-20MB/s low (20000 ints/s)
459 * 20-1249MB/s bulk (8000 ints/s)
460 */
461 bytes_per_int = rc->total_bytes / rc->itr;
462 switch (rc->itr) {
463 case I40E_LOWEST_LATENCY:
464 if (bytes_per_int > 10)
465 new_latency_range = I40E_LOW_LATENCY;
466 break;
467 case I40E_LOW_LATENCY:
468 if (bytes_per_int > 20)
469 new_latency_range = I40E_BULK_LATENCY;
470 else if (bytes_per_int <= 10)
471 new_latency_range = I40E_LOWEST_LATENCY;
472 break;
473 case I40E_BULK_LATENCY:
474 if (bytes_per_int <= 20)
475 rc->latency_range = I40E_LOW_LATENCY;
476 break;
477 }
478
479 switch (new_latency_range) {
480 case I40E_LOWEST_LATENCY:
481 new_itr = I40E_ITR_100K;
482 break;
483 case I40E_LOW_LATENCY:
484 new_itr = I40E_ITR_20K;
485 break;
486 case I40E_BULK_LATENCY:
487 new_itr = I40E_ITR_8K;
488 break;
489 default:
490 break;
491 }
492
493 if (new_itr != rc->itr) {
494 /* do an exponential smoothing */
495 new_itr = (10 * new_itr * rc->itr) /
496 ((9 * new_itr) + rc->itr);
497 rc->itr = new_itr & I40E_MAX_ITR;
498 }
499
500 rc->total_bytes = 0;
501 rc->total_packets = 0;
502}
503
504/**
505 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
506 * @q_vector: the vector to adjust
507 **/
508static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
509{
510 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
511 struct i40e_hw *hw = &q_vector->vsi->back->hw;
512 u32 reg_addr;
513 u16 old_itr;
514
515 reg_addr = I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1);
516 old_itr = q_vector->rx.itr;
517 i40e_set_new_dynamic_itr(&q_vector->rx);
518 if (old_itr != q_vector->rx.itr)
519 wr32(hw, reg_addr, q_vector->rx.itr);
520
521 reg_addr = I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1);
522 old_itr = q_vector->tx.itr;
523 i40e_set_new_dynamic_itr(&q_vector->tx);
524 if (old_itr != q_vector->tx.itr)
525 wr32(hw, reg_addr, q_vector->tx.itr);
526
527 i40e_flush(hw);
528}
529
530/**
531 * i40e_clean_programming_status - clean the programming status descriptor
532 * @rx_ring: the rx ring that has this descriptor
533 * @rx_desc: the rx descriptor written back by HW
534 *
535 * Flow director should handle FD_FILTER_STATUS to check its filter programming
536 * status being successful or not and take actions accordingly. FCoE should
537 * handle its context/filter programming/invalidation status and take actions.
538 *
539 **/
540static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
541 union i40e_rx_desc *rx_desc)
542{
543 u64 qw;
544 u8 id;
545
546 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
547 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
548 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
549
550 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
551 i40e_fd_handle_status(rx_ring, qw, id);
552}
553
554/**
555 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
556 * @tx_ring: the tx ring to set up
557 *
558 * Return 0 on success, negative on error
559 **/
560int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
561{
562 struct device *dev = tx_ring->dev;
563 int bi_size;
564
565 if (!dev)
566 return -ENOMEM;
567
568 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
569 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
570 if (!tx_ring->tx_bi)
571 goto err;
572
573 /* round up to nearest 4K */
574 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
575 tx_ring->size = ALIGN(tx_ring->size, 4096);
576 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
577 &tx_ring->dma, GFP_KERNEL);
578 if (!tx_ring->desc) {
579 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
580 tx_ring->size);
581 goto err;
582 }
583
584 tx_ring->next_to_use = 0;
585 tx_ring->next_to_clean = 0;
586 return 0;
587
588err:
589 kfree(tx_ring->tx_bi);
590 tx_ring->tx_bi = NULL;
591 return -ENOMEM;
592}
593
594/**
595 * i40e_clean_rx_ring - Free Rx buffers
596 * @rx_ring: ring to be cleaned
597 **/
598void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
599{
600 struct device *dev = rx_ring->dev;
601 struct i40e_rx_buffer *rx_bi;
602 unsigned long bi_size;
603 u16 i;
604
605 /* ring already cleared, nothing to do */
606 if (!rx_ring->rx_bi)
607 return;
608
609 /* Free all the Rx ring sk_buffs */
610 for (i = 0; i < rx_ring->count; i++) {
611 rx_bi = &rx_ring->rx_bi[i];
612 if (rx_bi->dma) {
613 dma_unmap_single(dev,
614 rx_bi->dma,
615 rx_ring->rx_buf_len,
616 DMA_FROM_DEVICE);
617 rx_bi->dma = 0;
618 }
619 if (rx_bi->skb) {
620 dev_kfree_skb(rx_bi->skb);
621 rx_bi->skb = NULL;
622 }
623 if (rx_bi->page) {
624 if (rx_bi->page_dma) {
625 dma_unmap_page(dev,
626 rx_bi->page_dma,
627 PAGE_SIZE / 2,
628 DMA_FROM_DEVICE);
629 rx_bi->page_dma = 0;
630 }
631 __free_page(rx_bi->page);
632 rx_bi->page = NULL;
633 rx_bi->page_offset = 0;
634 }
635 }
636
637 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
638 memset(rx_ring->rx_bi, 0, bi_size);
639
640 /* Zero out the descriptor ring */
641 memset(rx_ring->desc, 0, rx_ring->size);
642
643 rx_ring->next_to_clean = 0;
644 rx_ring->next_to_use = 0;
645}
646
647/**
648 * i40e_free_rx_resources - Free Rx resources
649 * @rx_ring: ring to clean the resources from
650 *
651 * Free all receive software resources
652 **/
653void i40e_free_rx_resources(struct i40e_ring *rx_ring)
654{
655 i40e_clean_rx_ring(rx_ring);
656 kfree(rx_ring->rx_bi);
657 rx_ring->rx_bi = NULL;
658
659 if (rx_ring->desc) {
660 dma_free_coherent(rx_ring->dev, rx_ring->size,
661 rx_ring->desc, rx_ring->dma);
662 rx_ring->desc = NULL;
663 }
664}
665
666/**
667 * i40e_setup_rx_descriptors - Allocate Rx descriptors
668 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
669 *
670 * Returns 0 on success, negative on failure
671 **/
672int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
673{
674 struct device *dev = rx_ring->dev;
675 int bi_size;
676
677 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
678 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
679 if (!rx_ring->rx_bi)
680 goto err;
681
682 /* Round up to nearest 4K */
683 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
684 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
685 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
686 rx_ring->size = ALIGN(rx_ring->size, 4096);
687 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
688 &rx_ring->dma, GFP_KERNEL);
689
690 if (!rx_ring->desc) {
691 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
692 rx_ring->size);
693 goto err;
694 }
695
696 rx_ring->next_to_clean = 0;
697 rx_ring->next_to_use = 0;
698
699 return 0;
700err:
701 kfree(rx_ring->rx_bi);
702 rx_ring->rx_bi = NULL;
703 return -ENOMEM;
704}
705
706/**
707 * i40e_release_rx_desc - Store the new tail and head values
708 * @rx_ring: ring to bump
709 * @val: new head index
710 **/
711static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
712{
713 rx_ring->next_to_use = val;
714 /* Force memory writes to complete before letting h/w
715 * know there are new descriptors to fetch. (Only
716 * applicable for weak-ordered memory model archs,
717 * such as IA-64).
718 */
719 wmb();
720 writel(val, rx_ring->tail);
721}
722
723/**
724 * i40e_alloc_rx_buffers - Replace used receive buffers; packet split
725 * @rx_ring: ring to place buffers on
726 * @cleaned_count: number of buffers to replace
727 **/
728void i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
729{
730 u16 i = rx_ring->next_to_use;
731 union i40e_rx_desc *rx_desc;
732 struct i40e_rx_buffer *bi;
733 struct sk_buff *skb;
734
735 /* do nothing if no valid netdev defined */
736 if (!rx_ring->netdev || !cleaned_count)
737 return;
738
739 while (cleaned_count--) {
740 rx_desc = I40E_RX_DESC(rx_ring, i);
741 bi = &rx_ring->rx_bi[i];
742 skb = bi->skb;
743
744 if (!skb) {
745 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
746 rx_ring->rx_buf_len);
747 if (!skb) {
748 rx_ring->rx_stats.alloc_rx_buff_failed++;
749 goto no_buffers;
750 }
751 /* initialize queue mapping */
752 skb_record_rx_queue(skb, rx_ring->queue_index);
753 bi->skb = skb;
754 }
755
756 if (!bi->dma) {
757 bi->dma = dma_map_single(rx_ring->dev,
758 skb->data,
759 rx_ring->rx_buf_len,
760 DMA_FROM_DEVICE);
761 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
762 rx_ring->rx_stats.alloc_rx_buff_failed++;
763 bi->dma = 0;
764 goto no_buffers;
765 }
766 }
767
768 if (ring_is_ps_enabled(rx_ring)) {
769 if (!bi->page) {
770 bi->page = alloc_page(GFP_ATOMIC);
771 if (!bi->page) {
772 rx_ring->rx_stats.alloc_rx_page_failed++;
773 goto no_buffers;
774 }
775 }
776
777 if (!bi->page_dma) {
778 /* use a half page if we're re-using */
779 bi->page_offset ^= PAGE_SIZE / 2;
780 bi->page_dma = dma_map_page(rx_ring->dev,
781 bi->page,
782 bi->page_offset,
783 PAGE_SIZE / 2,
784 DMA_FROM_DEVICE);
785 if (dma_mapping_error(rx_ring->dev,
786 bi->page_dma)) {
787 rx_ring->rx_stats.alloc_rx_page_failed++;
788 bi->page_dma = 0;
789 goto no_buffers;
790 }
791 }
792
793 /* Refresh the desc even if buffer_addrs didn't change
794 * because each write-back erases this info.
795 */
796 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
797 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
798 } else {
799 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
800 rx_desc->read.hdr_addr = 0;
801 }
802 i++;
803 if (i == rx_ring->count)
804 i = 0;
805 }
806
807no_buffers:
808 if (rx_ring->next_to_use != i)
809 i40e_release_rx_desc(rx_ring, i);
810}
811
812/**
813 * i40e_receive_skb - Send a completed packet up the stack
814 * @rx_ring: rx ring in play
815 * @skb: packet to send up
816 * @vlan_tag: vlan tag for packet
817 **/
818static void i40e_receive_skb(struct i40e_ring *rx_ring,
819 struct sk_buff *skb, u16 vlan_tag)
820{
821 struct i40e_q_vector *q_vector = rx_ring->q_vector;
822 struct i40e_vsi *vsi = rx_ring->vsi;
823 u64 flags = vsi->back->flags;
824
825 if (vlan_tag & VLAN_VID_MASK)
826 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
827
828 if (flags & I40E_FLAG_IN_NETPOLL)
829 netif_rx(skb);
830 else
831 napi_gro_receive(&q_vector->napi, skb);
832}
833
834/**
835 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
836 * @vsi: the VSI we care about
837 * @skb: skb currently being received and modified
838 * @rx_status: status value of last descriptor in packet
839 * @rx_error: error value of last descriptor in packet
840 **/
841static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
842 struct sk_buff *skb,
843 u32 rx_status,
844 u32 rx_error)
845{
846 skb->ip_summed = CHECKSUM_NONE;
847
848 /* Rx csum enabled and ip headers found? */
849 if (!(vsi->netdev->features & NETIF_F_RXCSUM &&
850 rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
851 return;
852
853 /* IP or L4 checksum error */
854 if (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
855 (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))) {
856 vsi->back->hw_csum_rx_error++;
857 return;
858 }
859
860 skb->ip_summed = CHECKSUM_UNNECESSARY;
861}
862
863/**
864 * i40e_rx_hash - returns the hash value from the Rx descriptor
865 * @ring: descriptor ring
866 * @rx_desc: specific descriptor
867 **/
868static inline u32 i40e_rx_hash(struct i40e_ring *ring,
869 union i40e_rx_desc *rx_desc)
870{
871 if (ring->netdev->features & NETIF_F_RXHASH) {
872 if ((le64_to_cpu(rx_desc->wb.qword1.status_error_len) >>
873 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
874 I40E_RX_DESC_FLTSTAT_RSS_HASH)
875 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
876 }
877 return 0;
878}
879
880/**
881 * i40e_clean_rx_irq - Reclaim resources after receive completes
882 * @rx_ring: rx ring to clean
883 * @budget: how many cleans we're allowed
884 *
885 * Returns true if there's any budget left (e.g. the clean is finished)
886 **/
887static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
888{
889 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
890 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
891 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
892 const int current_node = numa_node_id();
893 struct i40e_vsi *vsi = rx_ring->vsi;
894 u16 i = rx_ring->next_to_clean;
895 union i40e_rx_desc *rx_desc;
896 u32 rx_error, rx_status;
897 u64 qword;
898
899 rx_desc = I40E_RX_DESC(rx_ring, i);
900 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
901 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK)
902 >> I40E_RXD_QW1_STATUS_SHIFT;
903
904 while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
905 union i40e_rx_desc *next_rxd;
906 struct i40e_rx_buffer *rx_bi;
907 struct sk_buff *skb;
908 u16 vlan_tag;
909 if (i40e_rx_is_programming_status(qword)) {
910 i40e_clean_programming_status(rx_ring, rx_desc);
911 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
912 goto next_desc;
913 }
914 rx_bi = &rx_ring->rx_bi[i];
915 skb = rx_bi->skb;
916 prefetch(skb->data);
917
918 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK)
919 >> I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
920 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK)
921 >> I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
922 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK)
923 >> I40E_RXD_QW1_LENGTH_SPH_SHIFT;
924
925 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK)
926 >> I40E_RXD_QW1_ERROR_SHIFT;
927 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
928 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
929
930 rx_bi->skb = NULL;
931
932 /* This memory barrier is needed to keep us from reading
933 * any other fields out of the rx_desc until we know the
934 * STATUS_DD bit is set
935 */
936 rmb();
937
938 /* Get the header and possibly the whole packet
939 * If this is an skb from previous receive dma will be 0
940 */
941 if (rx_bi->dma) {
942 u16 len;
943
944 if (rx_hbo)
945 len = I40E_RX_HDR_SIZE;
946 else if (rx_sph)
947 len = rx_header_len;
948 else if (rx_packet_len)
949 len = rx_packet_len; /* 1buf/no split found */
950 else
951 len = rx_header_len; /* split always mode */
952
953 skb_put(skb, len);
954 dma_unmap_single(rx_ring->dev,
955 rx_bi->dma,
956 rx_ring->rx_buf_len,
957 DMA_FROM_DEVICE);
958 rx_bi->dma = 0;
959 }
960
961 /* Get the rest of the data if this was a header split */
962 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
963
964 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
965 rx_bi->page,
966 rx_bi->page_offset,
967 rx_packet_len);
968
969 skb->len += rx_packet_len;
970 skb->data_len += rx_packet_len;
971 skb->truesize += rx_packet_len;
972
973 if ((page_count(rx_bi->page) == 1) &&
974 (page_to_nid(rx_bi->page) == current_node))
975 get_page(rx_bi->page);
976 else
977 rx_bi->page = NULL;
978
979 dma_unmap_page(rx_ring->dev,
980 rx_bi->page_dma,
981 PAGE_SIZE / 2,
982 DMA_FROM_DEVICE);
983 rx_bi->page_dma = 0;
984 }
985 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
986
987 if (unlikely(
988 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
989 struct i40e_rx_buffer *next_buffer;
990
991 next_buffer = &rx_ring->rx_bi[i];
992
993 if (ring_is_ps_enabled(rx_ring)) {
994 rx_bi->skb = next_buffer->skb;
995 rx_bi->dma = next_buffer->dma;
996 next_buffer->skb = skb;
997 next_buffer->dma = 0;
998 }
999 rx_ring->rx_stats.non_eop_descs++;
1000 goto next_desc;
1001 }
1002
1003 /* ERR_MASK will only have valid bits if EOP set */
1004 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1005 dev_kfree_skb_any(skb);
1006 goto next_desc;
1007 }
1008
1009 skb->rxhash = i40e_rx_hash(rx_ring, rx_desc);
1010 i40e_rx_checksum(vsi, skb, rx_status, rx_error);
1011
1012 /* probably a little skewed due to removing CRC */
1013 total_rx_bytes += skb->len;
1014 total_rx_packets++;
1015
1016 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1017 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1018 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1019 : 0;
1020 i40e_receive_skb(rx_ring, skb, vlan_tag);
1021
1022 rx_ring->netdev->last_rx = jiffies;
1023 budget--;
1024next_desc:
1025 rx_desc->wb.qword1.status_error_len = 0;
1026 if (!budget)
1027 break;
1028
1029 cleaned_count++;
1030 /* return some buffers to hardware, one at a time is too slow */
1031 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1032 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
1033 cleaned_count = 0;
1034 }
1035
1036 /* use prefetched values */
1037 rx_desc = next_rxd;
1038 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1039 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK)
1040 >> I40E_RXD_QW1_STATUS_SHIFT;
1041 }
1042
1043 rx_ring->next_to_clean = i;
1044 rx_ring->rx_stats.packets += total_rx_packets;
1045 rx_ring->rx_stats.bytes += total_rx_bytes;
1046 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1047 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1048
1049 if (cleaned_count)
1050 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
1051
1052 return budget > 0;
1053}
1054
1055/**
1056 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1057 * @napi: napi struct with our devices info in it
1058 * @budget: amount of work driver is allowed to do this pass, in packets
1059 *
1060 * This function will clean all queues associated with a q_vector.
1061 *
1062 * Returns the amount of work done
1063 **/
1064int i40e_napi_poll(struct napi_struct *napi, int budget)
1065{
1066 struct i40e_q_vector *q_vector =
1067 container_of(napi, struct i40e_q_vector, napi);
1068 struct i40e_vsi *vsi = q_vector->vsi;
1069 bool clean_complete = true;
1070 int budget_per_ring;
1071 int i;
1072
1073 if (test_bit(__I40E_DOWN, &vsi->state)) {
1074 napi_complete(napi);
1075 return 0;
1076 }
1077
1078 /* We attempt to distribute budget to each Rx queue fairly, but don't
1079 * allow the budget to go below 1 because that would exit polling early.
1080 * Since the actual Tx work is minimal, we can give the Tx a larger
1081 * budget and be more aggressive about cleaning up the Tx descriptors.
1082 */
1083 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1084 for (i = 0; i < q_vector->num_ringpairs; i++) {
1085 clean_complete &= i40e_clean_tx_irq(q_vector->tx.ring[i],
1086 vsi->work_limit);
1087 clean_complete &= i40e_clean_rx_irq(q_vector->rx.ring[i],
1088 budget_per_ring);
1089 }
1090
1091 /* If work not completed, return budget and polling will return */
1092 if (!clean_complete)
1093 return budget;
1094
1095 /* Work is done so exit the polling mode and re-enable the interrupt */
1096 napi_complete(napi);
1097 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1098 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1099 i40e_update_dynamic_itr(q_vector);
1100
1101 if (!test_bit(__I40E_DOWN, &vsi->state)) {
1102 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1103 i40e_irq_dynamic_enable(vsi,
1104 q_vector->v_idx + vsi->base_vector);
1105 } else {
1106 struct i40e_hw *hw = &vsi->back->hw;
1107 /* We re-enable the queue 0 cause, but
1108 * don't worry about dynamic_enable
1109 * because we left it on for the other
1110 * possible interrupts during napi
1111 */
1112 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
1113 qval |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1114 wr32(hw, I40E_QINT_RQCTL(0), qval);
1115
1116 qval = rd32(hw, I40E_QINT_TQCTL(0));
1117 qval |= I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1118 wr32(hw, I40E_QINT_TQCTL(0), qval);
1119 i40e_flush(hw);
1120 }
1121 }
1122
1123 return 0;
1124}
1125
1126/**
1127 * i40e_atr - Add a Flow Director ATR filter
1128 * @tx_ring: ring to add programming descriptor to
1129 * @skb: send buffer
1130 * @flags: send flags
1131 * @protocol: wire protocol
1132 **/
1133static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
1134 u32 flags, __be16 protocol)
1135{
1136 struct i40e_filter_program_desc *fdir_desc;
1137 struct i40e_pf *pf = tx_ring->vsi->back;
1138 union {
1139 unsigned char *network;
1140 struct iphdr *ipv4;
1141 struct ipv6hdr *ipv6;
1142 } hdr;
1143 struct tcphdr *th;
1144 unsigned int hlen;
1145 u32 flex_ptype, dtype_cmd;
1146
1147 /* make sure ATR is enabled */
1148 if (!(pf->flags & I40E_FLAG_FDIR_ATR_ENABLED))
1149 return;
1150
1151 /* if sampling is disabled do nothing */
1152 if (!tx_ring->atr_sample_rate)
1153 return;
1154
1155 tx_ring->atr_count++;
1156
1157 /* snag network header to get L4 type and address */
1158 hdr.network = skb_network_header(skb);
1159
1160 /* Currently only IPv4/IPv6 with TCP is supported */
1161 if (protocol == htons(ETH_P_IP)) {
1162 if (hdr.ipv4->protocol != IPPROTO_TCP)
1163 return;
1164
1165 /* access ihl as a u8 to avoid unaligned access on ia64 */
1166 hlen = (hdr.network[0] & 0x0F) << 2;
1167 } else if (protocol == htons(ETH_P_IPV6)) {
1168 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1169 return;
1170
1171 hlen = sizeof(struct ipv6hdr);
1172 } else {
1173 return;
1174 }
1175
1176 th = (struct tcphdr *)(hdr.network + hlen);
1177
1178 /* sample on all syn/fin packets or once every atr sample rate */
1179 if (!th->fin && !th->syn && (tx_ring->atr_count < tx_ring->atr_sample_rate))
1180 return;
1181
1182 tx_ring->atr_count = 0;
1183
1184 /* grab the next descriptor */
1185 fdir_desc = I40E_TX_FDIRDESC(tx_ring, tx_ring->next_to_use);
1186 tx_ring->next_to_use++;
1187 if (tx_ring->next_to_use == tx_ring->count)
1188 tx_ring->next_to_use = 0;
1189
1190 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1191 I40E_TXD_FLTR_QW0_QINDEX_MASK;
1192 flex_ptype |= (protocol == htons(ETH_P_IP)) ?
1193 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
1194 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
1195 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
1196 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
1197
1198 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
1199
1200 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
1201
1202 dtype_cmd |= th->fin ?
1203 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1204 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
1205 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1206 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1207
1208 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
1209 I40E_TXD_FLTR_QW1_DEST_SHIFT;
1210
1211 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
1212 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
1213
1214 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
1215 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
1216}
1217
1218#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
1219/**
1220 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1221 * @skb: send buffer
1222 * @tx_ring: ring to send buffer on
1223 * @flags: the tx flags to be set
1224 *
1225 * Checks the skb and set up correspondingly several generic transmit flags
1226 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1227 *
1228 * Returns error code indicate the frame should be dropped upon error and the
1229 * otherwise returns 0 to indicate the flags has been set properly.
1230 **/
1231static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1232 struct i40e_ring *tx_ring,
1233 u32 *flags)
1234{
1235 __be16 protocol = skb->protocol;
1236 u32 tx_flags = 0;
1237
1238 /* if we have a HW VLAN tag being added, default to the HW one */
1239 if (vlan_tx_tag_present(skb)) {
1240 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1241 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1242 /* else if it is a SW VLAN, check the next protocol and store the tag */
1243 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
1244 struct vlan_hdr *vhdr, _vhdr;
1245 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1246 if (!vhdr)
1247 return -EINVAL;
1248
1249 protocol = vhdr->h_vlan_encapsulated_proto;
1250 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1251 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1252 }
1253
1254 /* Insert 802.1p priority into VLAN header */
1255 if ((tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED) &&
1256 ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
1257 (skb->priority != TC_PRIO_CONTROL))) {
1258 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
1259 tx_flags |= (skb->priority & 0x7) <<
1260 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
1261 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
1262 struct vlan_ethhdr *vhdr;
1263 if (skb_header_cloned(skb) &&
1264 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
1265 return -ENOMEM;
1266 vhdr = (struct vlan_ethhdr *)skb->data;
1267 vhdr->h_vlan_TCI = htons(tx_flags >>
1268 I40E_TX_FLAGS_VLAN_SHIFT);
1269 } else {
1270 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1271 }
1272 }
1273 *flags = tx_flags;
1274 return 0;
1275}
1276
1277/**
1278 * i40e_tx_csum - is checksum offload requested
1279 * @tx_ring: ptr to the ring to send
1280 * @skb: ptr to the skb we're sending
1281 * @tx_flags: the collected send information
1282 * @protocol: the send protocol
1283 *
1284 * Returns true if checksum offload is requested
1285 **/
1286static bool i40e_tx_csum(struct i40e_ring *tx_ring, struct sk_buff *skb,
1287 u32 tx_flags, __be16 protocol)
1288{
1289 if ((skb->ip_summed != CHECKSUM_PARTIAL) &&
1290 !(tx_flags & I40E_TX_FLAGS_TXSW)) {
1291 if (!(tx_flags & I40E_TX_FLAGS_HW_VLAN))
1292 return false;
1293 }
1294
1295 return skb->ip_summed == CHECKSUM_PARTIAL;
1296}
1297
1298/**
1299 * i40e_tso - set up the tso context descriptor
1300 * @tx_ring: ptr to the ring to send
1301 * @skb: ptr to the skb we're sending
1302 * @tx_flags: the collected send information
1303 * @protocol: the send protocol
1304 * @hdr_len: ptr to the size of the packet header
1305 * @cd_tunneling: ptr to context descriptor bits
1306 *
1307 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1308 **/
1309static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1310 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1311 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1312{
1313 u32 cd_cmd, cd_tso_len, cd_mss;
1314 struct tcphdr *tcph;
1315 struct iphdr *iph;
1316 u32 l4len;
1317 int err;
1318 struct ipv6hdr *ipv6h;
1319
1320 if (!skb_is_gso(skb))
1321 return 0;
1322
1323 if (skb_header_cloned(skb)) {
1324 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1325 if (err)
1326 return err;
1327 }
1328
1329 if (protocol == __constant_htons(ETH_P_IP)) {
1330 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1331 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1332 iph->tot_len = 0;
1333 iph->check = 0;
1334 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1335 0, IPPROTO_TCP, 0);
1336 } else if (skb_is_gso_v6(skb)) {
1337
1338 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1339 : ipv6_hdr(skb);
1340 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1341 ipv6h->payload_len = 0;
1342 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1343 0, IPPROTO_TCP, 0);
1344 }
1345
1346 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1347 *hdr_len = (skb->encapsulation
1348 ? (skb_inner_transport_header(skb) - skb->data)
1349 : skb_transport_offset(skb)) + l4len;
1350
1351 /* find the field values */
1352 cd_cmd = I40E_TX_CTX_DESC_TSO;
1353 cd_tso_len = skb->len - *hdr_len;
1354 cd_mss = skb_shinfo(skb)->gso_size;
1355 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT)
1356 | ((u64)cd_tso_len
1357 << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1358 | ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1359 return 1;
1360}
1361
1362/**
1363 * i40e_tx_enable_csum - Enable Tx checksum offloads
1364 * @skb: send buffer
1365 * @tx_flags: Tx flags currently set
1366 * @td_cmd: Tx descriptor command bits to set
1367 * @td_offset: Tx descriptor header offsets to set
1368 * @cd_tunneling: ptr to context desc bits
1369 **/
1370static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1371 u32 *td_cmd, u32 *td_offset,
1372 struct i40e_ring *tx_ring,
1373 u32 *cd_tunneling)
1374{
1375 struct ipv6hdr *this_ipv6_hdr;
1376 unsigned int this_tcp_hdrlen;
1377 struct iphdr *this_ip_hdr;
1378 u32 network_hdr_len;
1379 u8 l4_hdr = 0;
1380
1381 if (skb->encapsulation) {
1382 network_hdr_len = skb_inner_network_header_len(skb);
1383 this_ip_hdr = inner_ip_hdr(skb);
1384 this_ipv6_hdr = inner_ipv6_hdr(skb);
1385 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1386
1387 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1388
1389 if (tx_flags & I40E_TX_FLAGS_TSO) {
1390 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1391 ip_hdr(skb)->check = 0;
1392 } else {
1393 *cd_tunneling |=
1394 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1395 }
1396 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1397 if (tx_flags & I40E_TX_FLAGS_TSO) {
1398 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1399 ip_hdr(skb)->check = 0;
1400 } else {
1401 *cd_tunneling |=
1402 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1403 }
1404 }
1405
1406 /* Now set the ctx descriptor fields */
1407 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1408 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1409 I40E_TXD_CTX_UDP_TUNNELING |
1410 ((skb_inner_network_offset(skb) -
1411 skb_transport_offset(skb)) >> 1) <<
1412 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1413
1414 } else {
1415 network_hdr_len = skb_network_header_len(skb);
1416 this_ip_hdr = ip_hdr(skb);
1417 this_ipv6_hdr = ipv6_hdr(skb);
1418 this_tcp_hdrlen = tcp_hdrlen(skb);
1419 }
1420
1421 /* Enable IP checksum offloads */
1422 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1423 l4_hdr = this_ip_hdr->protocol;
1424 /* the stack computes the IP header already, the only time we
1425 * need the hardware to recompute it is in the case of TSO.
1426 */
1427 if (tx_flags & I40E_TX_FLAGS_TSO) {
1428 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1429 this_ip_hdr->check = 0;
1430 } else {
1431 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1432 }
1433 /* Now set the td_offset for IP header length */
1434 *td_offset = (network_hdr_len >> 2) <<
1435 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1436 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1437 l4_hdr = this_ipv6_hdr->nexthdr;
1438 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1439 /* Now set the td_offset for IP header length */
1440 *td_offset = (network_hdr_len >> 2) <<
1441 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1442 }
1443 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1444 *td_offset |= (skb_network_offset(skb) >> 1) <<
1445 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1446
1447 /* Enable L4 checksum offloads */
1448 switch (l4_hdr) {
1449 case IPPROTO_TCP:
1450 /* enable checksum offloads */
1451 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1452 *td_offset |= (this_tcp_hdrlen >> 2) <<
1453 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1454 break;
1455 case IPPROTO_SCTP:
1456 /* enable SCTP checksum offload */
1457 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1458 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1459 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1460 break;
1461 case IPPROTO_UDP:
1462 /* enable UDP checksum offload */
1463 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1464 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1465 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1466 break;
1467 default:
1468 break;
1469 }
1470}
1471
1472/**
1473 * i40e_create_tx_ctx Build the Tx context descriptor
1474 * @tx_ring: ring to create the descriptor on
1475 * @cd_type_cmd_tso_mss: Quad Word 1
1476 * @cd_tunneling: Quad Word 0 - bits 0-31
1477 * @cd_l2tag2: Quad Word 0 - bits 32-63
1478 **/
1479static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1480 const u64 cd_type_cmd_tso_mss,
1481 const u32 cd_tunneling, const u32 cd_l2tag2)
1482{
1483 struct i40e_tx_context_desc *context_desc;
1484
1485 if (!cd_type_cmd_tso_mss && !cd_tunneling && !cd_l2tag2)
1486 return;
1487
1488 /* grab the next descriptor */
1489 context_desc = I40E_TX_CTXTDESC(tx_ring, tx_ring->next_to_use);
1490 tx_ring->next_to_use++;
1491 if (tx_ring->next_to_use == tx_ring->count)
1492 tx_ring->next_to_use = 0;
1493
1494 /* cpu_to_le32 and assign to struct fields */
1495 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1496 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1497 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1498}
1499
1500/**
1501 * i40e_tx_map - Build the Tx descriptor
1502 * @tx_ring: ring to send buffer on
1503 * @skb: send buffer
1504 * @first: first buffer info buffer to use
1505 * @tx_flags: collected send information
1506 * @hdr_len: size of the packet header
1507 * @td_cmd: the command field in the descriptor
1508 * @td_offset: offset for checksum or crc
1509 **/
1510static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1511 struct i40e_tx_buffer *first, u32 tx_flags,
1512 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1513{
1514 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1515 unsigned int data_len = skb->data_len;
1516 unsigned int size = skb_headlen(skb);
1517 struct device *dev = tx_ring->dev;
1518 u32 paylen = skb->len - hdr_len;
1519 u16 i = tx_ring->next_to_use;
1520 struct i40e_tx_buffer *tx_bi;
1521 struct i40e_tx_desc *tx_desc;
1522 u32 buf_offset = 0;
1523 u32 td_tag = 0;
1524 dma_addr_t dma;
1525 u16 gso_segs;
1526
1527 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1528 if (dma_mapping_error(dev, dma))
1529 goto dma_error;
1530
1531 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1532 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1533 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1534 I40E_TX_FLAGS_VLAN_SHIFT;
1535 }
1536
1537 tx_desc = I40E_TX_DESC(tx_ring, i);
1538 for (;;) {
1539 while (size > I40E_MAX_DATA_PER_TXD) {
1540 tx_desc->buffer_addr = cpu_to_le64(dma + buf_offset);
1541 tx_desc->cmd_type_offset_bsz =
1542 build_ctob(td_cmd, td_offset,
1543 I40E_MAX_DATA_PER_TXD, td_tag);
1544
1545 buf_offset += I40E_MAX_DATA_PER_TXD;
1546 size -= I40E_MAX_DATA_PER_TXD;
1547
1548 tx_desc++;
1549 i++;
1550 if (i == tx_ring->count) {
1551 tx_desc = I40E_TX_DESC(tx_ring, 0);
1552 i = 0;
1553 }
1554 }
1555
1556 tx_bi = &tx_ring->tx_bi[i];
1557 tx_bi->length = buf_offset + size;
1558 tx_bi->tx_flags = tx_flags;
1559 tx_bi->dma = dma;
1560
1561 tx_desc->buffer_addr = cpu_to_le64(dma + buf_offset);
1562 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1563 size, td_tag);
1564
1565 if (likely(!data_len))
1566 break;
1567
1568 size = skb_frag_size(frag);
1569 data_len -= size;
1570 buf_offset = 0;
1571 tx_flags |= I40E_TX_FLAGS_MAPPED_AS_PAGE;
1572
1573 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1574 if (dma_mapping_error(dev, dma))
1575 goto dma_error;
1576
1577 tx_desc++;
1578 i++;
1579 if (i == tx_ring->count) {
1580 tx_desc = I40E_TX_DESC(tx_ring, 0);
1581 i = 0;
1582 }
1583
1584 frag++;
1585 }
1586
1587 tx_desc->cmd_type_offset_bsz |=
1588 cpu_to_le64((u64)I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT);
1589
1590 i++;
1591 if (i == tx_ring->count)
1592 i = 0;
1593
1594 tx_ring->next_to_use = i;
1595
1596 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1597 gso_segs = skb_shinfo(skb)->gso_segs;
1598 else
1599 gso_segs = 1;
1600
1601 /* multiply data chunks by size of headers */
1602 tx_bi->bytecount = paylen + (gso_segs * hdr_len);
1603 tx_bi->gso_segs = gso_segs;
1604 tx_bi->skb = skb;
1605
1606 /* set the timestamp and next to watch values */
1607 first->time_stamp = jiffies;
1608 first->next_to_watch = tx_desc;
1609
1610 /* Force memory writes to complete before letting h/w
1611 * know there are new descriptors to fetch. (Only
1612 * applicable for weak-ordered memory model archs,
1613 * such as IA-64).
1614 */
1615 wmb();
1616
1617 writel(i, tx_ring->tail);
1618 return;
1619
1620dma_error:
1621 dev_info(dev, "TX DMA map failed\n");
1622
1623 /* clear dma mappings for failed tx_bi map */
1624 for (;;) {
1625 tx_bi = &tx_ring->tx_bi[i];
1626 i40e_unmap_tx_resource(tx_ring, tx_bi);
1627 if (tx_bi == first)
1628 break;
1629 if (i == 0)
1630 i = tx_ring->count;
1631 i--;
1632 }
1633
1634 dev_kfree_skb_any(skb);
1635
1636 tx_ring->next_to_use = i;
1637}
1638
1639/**
1640 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1641 * @tx_ring: the ring to be checked
1642 * @size: the size buffer we want to assure is available
1643 *
1644 * Returns -EBUSY if a stop is needed, else 0
1645 **/
1646static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1647{
1648 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1649 smp_mb();
1650
1651 /* Check again in a case another CPU has just made room available. */
1652 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1653 return -EBUSY;
1654
1655 /* A reprieve! - use start_queue because it doesn't call schedule */
1656 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1657 ++tx_ring->tx_stats.restart_queue;
1658 return 0;
1659}
1660
1661/**
1662 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1663 * @tx_ring: the ring to be checked
1664 * @size: the size buffer we want to assure is available
1665 *
1666 * Returns 0 if stop is not needed
1667 **/
1668static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1669{
1670 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1671 return 0;
1672 return __i40e_maybe_stop_tx(tx_ring, size);
1673}
1674
1675/**
1676 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1677 * @skb: send buffer
1678 * @tx_ring: ring to send buffer on
1679 *
1680 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1681 * there is not enough descriptors available in this ring since we need at least
1682 * one descriptor.
1683 **/
1684static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1685 struct i40e_ring *tx_ring)
1686{
1687#if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1688 unsigned int f;
1689#endif
1690 int count = 0;
1691
1692 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1693 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1694 * + 2 desc gap to keep tail from touching head,
1695 * + 1 desc for context descriptor,
1696 * otherwise try next time
1697 */
1698#if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1699 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1700 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1701#else
1702 count += skb_shinfo(skb)->nr_frags;
1703#endif
1704 count += TXD_USE_COUNT(skb_headlen(skb));
1705 if (i40e_maybe_stop_tx(tx_ring, count + 3)) {
1706 tx_ring->tx_stats.tx_busy++;
1707 return 0;
1708 }
1709 return count;
1710}
1711
1712/**
1713 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1714 * @skb: send buffer
1715 * @tx_ring: ring to send buffer on
1716 *
1717 * Returns NETDEV_TX_OK if sent, else an error code
1718 **/
1719static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1720 struct i40e_ring *tx_ring)
1721{
1722 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1723 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1724 struct i40e_tx_buffer *first;
1725 u32 td_offset = 0;
1726 u32 tx_flags = 0;
1727 __be16 protocol;
1728 u32 td_cmd = 0;
1729 u8 hdr_len = 0;
1730 int tso;
1731 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1732 return NETDEV_TX_BUSY;
1733
1734 /* prepare the xmit flags */
1735 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1736 goto out_drop;
1737
1738 /* obtain protocol of skb */
1739 protocol = skb->protocol;
1740
1741 /* record the location of the first descriptor for this packet */
1742 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1743
1744 /* setup IPv4/IPv6 offloads */
1745 if (protocol == __constant_htons(ETH_P_IP))
1746 tx_flags |= I40E_TX_FLAGS_IPV4;
1747 else if (protocol == __constant_htons(ETH_P_IPV6))
1748 tx_flags |= I40E_TX_FLAGS_IPV6;
1749
1750 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1751 &cd_type_cmd_tso_mss, &cd_tunneling);
1752
1753 if (tso < 0)
1754 goto out_drop;
1755 else if (tso)
1756 tx_flags |= I40E_TX_FLAGS_TSO;
1757
1758 skb_tx_timestamp(skb);
1759
1760 /* Always offload the checksum, since it's in the data descriptor */
1761 if (i40e_tx_csum(tx_ring, skb, tx_flags, protocol))
1762 tx_flags |= I40E_TX_FLAGS_CSUM;
1763
1764 /* always enable offload insertion */
1765 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1766
1767 if (tx_flags & I40E_TX_FLAGS_CSUM)
1768 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1769 tx_ring, &cd_tunneling);
1770
1771 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1772 cd_tunneling, cd_l2tag2);
1773
1774 /* Add Flow Director ATR if it's enabled.
1775 *
1776 * NOTE: this must always be directly before the data descriptor.
1777 */
1778 i40e_atr(tx_ring, skb, tx_flags, protocol);
1779
1780 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1781 td_cmd, td_offset);
1782
1783 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1784
1785 return NETDEV_TX_OK;
1786
1787out_drop:
1788 dev_kfree_skb_any(skb);
1789 return NETDEV_TX_OK;
1790}
1791
1792/**
1793 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1794 * @skb: send buffer
1795 * @netdev: network interface device structure
1796 *
1797 * Returns NETDEV_TX_OK if sent, else an error code
1798 **/
1799netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1800{
1801 struct i40e_netdev_priv *np = netdev_priv(netdev);
1802 struct i40e_vsi *vsi = np->vsi;
1803 struct i40e_ring *tx_ring = &vsi->tx_rings[skb->queue_mapping];
1804
1805 /* hardware can't handle really short frames, hardware padding works
1806 * beyond this point
1807 */
1808 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1809 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1810 return NETDEV_TX_OK;
1811 skb->len = I40E_MIN_TX_LEN;
1812 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1813 }
1814
1815 return i40e_xmit_frame_ring(skb, tx_ring);
1816}
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