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fd0a05ce JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
fd0a05ce JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
fd0a05ce JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
1c112a64 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
fd0a05ce | 29 | #include "i40e.h" |
206812b5 | 30 | #include "i40e_prototype.h" |
fd0a05ce JB |
31 | |
32 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
33 | u32 td_tag) | |
34 | { | |
35 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
36 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
37 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
38 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
39 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
40 | } | |
41 | ||
eaefbd06 | 42 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) |
5e02f283 AD |
43 | /** |
44 | * i40e_fdir - Generate a Flow Director descriptor based on fdata | |
45 | * @tx_ring: Tx ring to send buffer on | |
46 | * @fdata: Flow director filter data | |
47 | * @add: Indicate if we are adding a rule or deleting one | |
48 | * | |
49 | **/ | |
50 | static void i40e_fdir(struct i40e_ring *tx_ring, | |
51 | struct i40e_fdir_filter *fdata, bool add) | |
52 | { | |
53 | struct i40e_filter_program_desc *fdir_desc; | |
54 | struct i40e_pf *pf = tx_ring->vsi->back; | |
55 | u32 flex_ptype, dtype_cmd; | |
56 | u16 i; | |
57 | ||
58 | /* grab the next descriptor */ | |
59 | i = tx_ring->next_to_use; | |
60 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
61 | ||
62 | i++; | |
63 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
64 | ||
65 | flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & | |
66 | (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); | |
67 | ||
68 | flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & | |
69 | (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); | |
70 | ||
71 | flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & | |
72 | (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
73 | ||
74 | /* Use LAN VSI Id if not programmed by user */ | |
75 | flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & | |
76 | ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << | |
77 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); | |
78 | ||
79 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
80 | ||
81 | dtype_cmd |= add ? | |
82 | I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
83 | I40E_TXD_FLTR_QW1_PCMD_SHIFT : | |
84 | I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << | |
85 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
86 | ||
87 | dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & | |
88 | (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); | |
89 | ||
90 | dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & | |
91 | (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); | |
92 | ||
93 | if (fdata->cnt_index) { | |
94 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; | |
95 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & | |
96 | ((u32)fdata->cnt_index << | |
97 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); | |
98 | } | |
99 | ||
100 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); | |
101 | fdir_desc->rsvd = cpu_to_le32(0); | |
102 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); | |
103 | fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); | |
104 | } | |
105 | ||
49d7d933 | 106 | #define I40E_FD_CLEAN_DELAY 10 |
fd0a05ce JB |
107 | /** |
108 | * i40e_program_fdir_filter - Program a Flow Director filter | |
17a73f6b JG |
109 | * @fdir_data: Packet data that will be filter parameters |
110 | * @raw_packet: the pre-allocated packet buffer for FDir | |
b40c82e6 | 111 | * @pf: The PF pointer |
fd0a05ce JB |
112 | * @add: True for add/update, False for remove |
113 | **/ | |
1eb846ac AD |
114 | static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, |
115 | u8 *raw_packet, struct i40e_pf *pf, | |
116 | bool add) | |
fd0a05ce | 117 | { |
49d7d933 | 118 | struct i40e_tx_buffer *tx_buf, *first; |
fd0a05ce JB |
119 | struct i40e_tx_desc *tx_desc; |
120 | struct i40e_ring *tx_ring; | |
121 | struct i40e_vsi *vsi; | |
122 | struct device *dev; | |
123 | dma_addr_t dma; | |
124 | u32 td_cmd = 0; | |
125 | u16 i; | |
126 | ||
127 | /* find existing FDIR VSI */ | |
128 | vsi = NULL; | |
505682cd | 129 | for (i = 0; i < pf->num_alloc_vsi; i++) |
fd0a05ce JB |
130 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) |
131 | vsi = pf->vsi[i]; | |
132 | if (!vsi) | |
133 | return -ENOENT; | |
134 | ||
9f65e15b | 135 | tx_ring = vsi->tx_rings[0]; |
fd0a05ce JB |
136 | dev = tx_ring->dev; |
137 | ||
49d7d933 | 138 | /* we need two descriptors to add/del a filter and we can wait */ |
ed245406 AD |
139 | for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { |
140 | if (!i) | |
141 | return -EAGAIN; | |
49d7d933 | 142 | msleep_interruptible(1); |
ed245406 | 143 | } |
49d7d933 | 144 | |
17a73f6b JG |
145 | dma = dma_map_single(dev, raw_packet, |
146 | I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); | |
fd0a05ce JB |
147 | if (dma_mapping_error(dev, dma)) |
148 | goto dma_fail; | |
149 | ||
150 | /* grab the next descriptor */ | |
fc4ac67b | 151 | i = tx_ring->next_to_use; |
49d7d933 | 152 | first = &tx_ring->tx_bi[i]; |
5e02f283 | 153 | i40e_fdir(tx_ring, fdir_data, add); |
fd0a05ce JB |
154 | |
155 | /* Now program a dummy descriptor */ | |
fc4ac67b AD |
156 | i = tx_ring->next_to_use; |
157 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
298deef1 | 158 | tx_buf = &tx_ring->tx_bi[i]; |
fc4ac67b | 159 | |
49d7d933 ASJ |
160 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
161 | ||
162 | memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); | |
fd0a05ce | 163 | |
298deef1 | 164 | /* record length, and DMA address */ |
17a73f6b | 165 | dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); |
298deef1 ASJ |
166 | dma_unmap_addr_set(tx_buf, dma, dma); |
167 | ||
fd0a05ce | 168 | tx_desc->buffer_addr = cpu_to_le64(dma); |
eaefbd06 | 169 | td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; |
fd0a05ce | 170 | |
49d7d933 ASJ |
171 | tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; |
172 | tx_buf->raw_buf = (void *)raw_packet; | |
173 | ||
fd0a05ce | 174 | tx_desc->cmd_type_offset_bsz = |
17a73f6b | 175 | build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); |
fd0a05ce | 176 | |
fd0a05ce | 177 | /* Force memory writes to complete before letting h/w |
49d7d933 | 178 | * know there are new descriptors to fetch. |
fd0a05ce JB |
179 | */ |
180 | wmb(); | |
181 | ||
fc4ac67b | 182 | /* Mark the data descriptor to be watched */ |
49d7d933 | 183 | first->next_to_watch = tx_desc; |
fc4ac67b | 184 | |
fd0a05ce JB |
185 | writel(tx_ring->next_to_use, tx_ring->tail); |
186 | return 0; | |
187 | ||
188 | dma_fail: | |
189 | return -1; | |
190 | } | |
191 | ||
17a73f6b JG |
192 | #define IP_HEADER_OFFSET 14 |
193 | #define I40E_UDPIP_DUMMY_PACKET_LEN 42 | |
194 | /** | |
195 | * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters | |
196 | * @vsi: pointer to the targeted VSI | |
197 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
198 | * @add: true adds a filter, false removes it |
199 | * | |
200 | * Returns 0 if the filters were successfully added or removed | |
201 | **/ | |
202 | static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, | |
203 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 204 | bool add) |
17a73f6b JG |
205 | { |
206 | struct i40e_pf *pf = vsi->back; | |
207 | struct udphdr *udp; | |
208 | struct iphdr *ip; | |
209 | bool err = false; | |
49d7d933 | 210 | u8 *raw_packet; |
17a73f6b | 211 | int ret; |
17a73f6b JG |
212 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, |
213 | 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, | |
214 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
215 | ||
49d7d933 ASJ |
216 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
217 | if (!raw_packet) | |
218 | return -ENOMEM; | |
17a73f6b JG |
219 | memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); |
220 | ||
221 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
222 | udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET | |
223 | + sizeof(struct iphdr)); | |
224 | ||
225 | ip->daddr = fd_data->dst_ip[0]; | |
226 | udp->dest = fd_data->dst_port; | |
227 | ip->saddr = fd_data->src_ip[0]; | |
228 | udp->source = fd_data->src_port; | |
229 | ||
b2d36c03 KS |
230 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; |
231 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
232 | if (ret) { | |
233 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
234 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
235 | fd_data->pctype, fd_data->fd_id, ret); | |
b2d36c03 | 236 | err = true; |
4205d379 | 237 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
238 | if (add) |
239 | dev_info(&pf->pdev->dev, | |
240 | "Filter OK for PCTYPE %d loc = %d\n", | |
241 | fd_data->pctype, fd_data->fd_id); | |
242 | else | |
243 | dev_info(&pf->pdev->dev, | |
244 | "Filter deleted for PCTYPE %d loc = %d\n", | |
245 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b | 246 | } |
a42e7a36 KP |
247 | if (err) |
248 | kfree(raw_packet); | |
249 | ||
17a73f6b JG |
250 | return err ? -EOPNOTSUPP : 0; |
251 | } | |
252 | ||
253 | #define I40E_TCPIP_DUMMY_PACKET_LEN 54 | |
254 | /** | |
255 | * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters | |
256 | * @vsi: pointer to the targeted VSI | |
257 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
258 | * @add: true adds a filter, false removes it |
259 | * | |
260 | * Returns 0 if the filters were successfully added or removed | |
261 | **/ | |
262 | static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, | |
263 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 264 | bool add) |
17a73f6b JG |
265 | { |
266 | struct i40e_pf *pf = vsi->back; | |
267 | struct tcphdr *tcp; | |
268 | struct iphdr *ip; | |
269 | bool err = false; | |
49d7d933 | 270 | u8 *raw_packet; |
17a73f6b JG |
271 | int ret; |
272 | /* Dummy packet */ | |
273 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
274 | 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, | |
275 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, | |
276 | 0x0, 0x72, 0, 0, 0, 0}; | |
277 | ||
49d7d933 ASJ |
278 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
279 | if (!raw_packet) | |
280 | return -ENOMEM; | |
17a73f6b JG |
281 | memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); |
282 | ||
283 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
284 | tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET | |
285 | + sizeof(struct iphdr)); | |
286 | ||
287 | ip->daddr = fd_data->dst_ip[0]; | |
288 | tcp->dest = fd_data->dst_port; | |
289 | ip->saddr = fd_data->src_ip[0]; | |
290 | tcp->source = fd_data->src_port; | |
291 | ||
292 | if (add) { | |
1e1be8f6 | 293 | pf->fd_tcp_rule++; |
234dc4e6 JK |
294 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
295 | I40E_DEBUG_FD & pf->hw.debug_mask) | |
296 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); | |
297 | pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; | |
1e1be8f6 ASJ |
298 | } else { |
299 | pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ? | |
300 | (pf->fd_tcp_rule - 1) : 0; | |
301 | if (pf->fd_tcp_rule == 0) { | |
234dc4e6 JK |
302 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
303 | I40E_DEBUG_FD & pf->hw.debug_mask) | |
2e4875e3 | 304 | dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); |
234dc4e6 | 305 | pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; |
1e1be8f6 | 306 | } |
17a73f6b JG |
307 | } |
308 | ||
b2d36c03 | 309 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; |
17a73f6b JG |
310 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); |
311 | ||
312 | if (ret) { | |
313 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
314 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
315 | fd_data->pctype, fd_data->fd_id, ret); | |
17a73f6b | 316 | err = true; |
4205d379 | 317 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
318 | if (add) |
319 | dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", | |
320 | fd_data->pctype, fd_data->fd_id); | |
321 | else | |
322 | dev_info(&pf->pdev->dev, | |
323 | "Filter deleted for PCTYPE %d loc = %d\n", | |
324 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
325 | } |
326 | ||
a42e7a36 KP |
327 | if (err) |
328 | kfree(raw_packet); | |
329 | ||
17a73f6b JG |
330 | return err ? -EOPNOTSUPP : 0; |
331 | } | |
332 | ||
17a73f6b JG |
333 | #define I40E_IP_DUMMY_PACKET_LEN 34 |
334 | /** | |
335 | * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for | |
336 | * a specific flow spec | |
337 | * @vsi: pointer to the targeted VSI | |
338 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
339 | * @add: true adds a filter, false removes it |
340 | * | |
341 | * Returns 0 if the filters were successfully added or removed | |
342 | **/ | |
343 | static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, | |
344 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 345 | bool add) |
17a73f6b JG |
346 | { |
347 | struct i40e_pf *pf = vsi->back; | |
348 | struct iphdr *ip; | |
349 | bool err = false; | |
49d7d933 | 350 | u8 *raw_packet; |
17a73f6b JG |
351 | int ret; |
352 | int i; | |
353 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
354 | 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, | |
355 | 0, 0, 0, 0}; | |
356 | ||
17a73f6b JG |
357 | for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; |
358 | i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { | |
49d7d933 ASJ |
359 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
360 | if (!raw_packet) | |
361 | return -ENOMEM; | |
362 | memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); | |
363 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
364 | ||
365 | ip->saddr = fd_data->src_ip[0]; | |
366 | ip->daddr = fd_data->dst_ip[0]; | |
367 | ip->protocol = 0; | |
368 | ||
17a73f6b JG |
369 | fd_data->pctype = i; |
370 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
371 | ||
372 | if (ret) { | |
373 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
374 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
375 | fd_data->pctype, fd_data->fd_id, ret); | |
17a73f6b | 376 | err = true; |
4205d379 | 377 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
378 | if (add) |
379 | dev_info(&pf->pdev->dev, | |
380 | "Filter OK for PCTYPE %d loc = %d\n", | |
381 | fd_data->pctype, fd_data->fd_id); | |
382 | else | |
383 | dev_info(&pf->pdev->dev, | |
384 | "Filter deleted for PCTYPE %d loc = %d\n", | |
385 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
386 | } |
387 | } | |
388 | ||
a42e7a36 KP |
389 | if (err) |
390 | kfree(raw_packet); | |
391 | ||
17a73f6b JG |
392 | return err ? -EOPNOTSUPP : 0; |
393 | } | |
394 | ||
395 | /** | |
396 | * i40e_add_del_fdir - Build raw packets to add/del fdir filter | |
397 | * @vsi: pointer to the targeted VSI | |
398 | * @cmd: command to get or set RX flow classification rules | |
399 | * @add: true adds a filter, false removes it | |
400 | * | |
401 | **/ | |
402 | int i40e_add_del_fdir(struct i40e_vsi *vsi, | |
403 | struct i40e_fdir_filter *input, bool add) | |
404 | { | |
405 | struct i40e_pf *pf = vsi->back; | |
17a73f6b JG |
406 | int ret; |
407 | ||
17a73f6b JG |
408 | switch (input->flow_type & ~FLOW_EXT) { |
409 | case TCP_V4_FLOW: | |
49d7d933 | 410 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
411 | break; |
412 | case UDP_V4_FLOW: | |
49d7d933 | 413 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 414 | break; |
17a73f6b JG |
415 | case IP_USER_FLOW: |
416 | switch (input->ip4_proto) { | |
417 | case IPPROTO_TCP: | |
49d7d933 | 418 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
419 | break; |
420 | case IPPROTO_UDP: | |
49d7d933 | 421 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b | 422 | break; |
e1da71ca | 423 | case IPPROTO_IP: |
49d7d933 | 424 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b | 425 | break; |
e1da71ca AD |
426 | default: |
427 | /* We cannot support masking based on protocol */ | |
428 | goto unsupported_flow; | |
17a73f6b JG |
429 | } |
430 | break; | |
431 | default: | |
e1da71ca | 432 | unsupported_flow: |
c5ffe7e1 | 433 | dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", |
17a73f6b JG |
434 | input->flow_type); |
435 | ret = -EINVAL; | |
436 | } | |
437 | ||
49d7d933 | 438 | /* The buffer allocated here is freed by the i40e_clean_tx_ring() */ |
17a73f6b JG |
439 | return ret; |
440 | } | |
441 | ||
fd0a05ce JB |
442 | /** |
443 | * i40e_fd_handle_status - check the Programming Status for FD | |
444 | * @rx_ring: the Rx ring for this descriptor | |
55a5e60b | 445 | * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. |
fd0a05ce JB |
446 | * @prog_id: the id originally used for programming |
447 | * | |
448 | * This is used to verify if the FD programming or invalidation | |
449 | * requested by SW to the HW is successful or not and take actions accordingly. | |
450 | **/ | |
55a5e60b ASJ |
451 | static void i40e_fd_handle_status(struct i40e_ring *rx_ring, |
452 | union i40e_rx_desc *rx_desc, u8 prog_id) | |
fd0a05ce | 453 | { |
55a5e60b ASJ |
454 | struct i40e_pf *pf = rx_ring->vsi->back; |
455 | struct pci_dev *pdev = pf->pdev; | |
456 | u32 fcnt_prog, fcnt_avail; | |
fd0a05ce | 457 | u32 error; |
55a5e60b | 458 | u64 qw; |
fd0a05ce | 459 | |
55a5e60b | 460 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
fd0a05ce JB |
461 | error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> |
462 | I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; | |
463 | ||
41a1d04b | 464 | if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { |
3487b6c3 | 465 | pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); |
f7233c54 ASJ |
466 | if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || |
467 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
468 | dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", | |
3487b6c3 | 469 | pf->fd_inv); |
55a5e60b | 470 | |
04294e38 ASJ |
471 | /* Check if the programming error is for ATR. |
472 | * If so, auto disable ATR and set a state for | |
473 | * flush in progress. Next time we come here if flush is in | |
474 | * progress do nothing, once flush is complete the state will | |
475 | * be cleared. | |
476 | */ | |
477 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) | |
478 | return; | |
479 | ||
1e1be8f6 ASJ |
480 | pf->fd_add_err++; |
481 | /* store the current atr filter count */ | |
482 | pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); | |
483 | ||
04294e38 ASJ |
484 | if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && |
485 | (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { | |
486 | pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; | |
487 | set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); | |
488 | } | |
489 | ||
55a5e60b | 490 | /* filter programming failed most likely due to table full */ |
04294e38 | 491 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 492 | fcnt_avail = pf->fdir_pf_filter_count; |
55a5e60b ASJ |
493 | /* If ATR is running fcnt_prog can quickly change, |
494 | * if we are very close to full, it makes sense to disable | |
495 | * FD ATR/SB and then re-enable it when there is room. | |
496 | */ | |
497 | if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { | |
1e1be8f6 | 498 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
b814ba65 | 499 | !(pf->auto_disable_flags & |
b814ba65 | 500 | I40E_FLAG_FD_SB_ENABLED)) { |
2e4875e3 ASJ |
501 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
502 | dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); | |
55a5e60b ASJ |
503 | pf->auto_disable_flags |= |
504 | I40E_FLAG_FD_SB_ENABLED; | |
55a5e60b | 505 | } |
55a5e60b | 506 | } |
41a1d04b | 507 | } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { |
13c2884f | 508 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
e99bdd39 | 509 | dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", |
13c2884f | 510 | rx_desc->wb.qword0.hi_dword.fd_id); |
55a5e60b | 511 | } |
fd0a05ce JB |
512 | } |
513 | ||
514 | /** | |
a5e9c572 | 515 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer |
fd0a05ce JB |
516 | * @ring: the ring that owns the buffer |
517 | * @tx_buffer: the buffer to free | |
518 | **/ | |
a5e9c572 AD |
519 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, |
520 | struct i40e_tx_buffer *tx_buffer) | |
fd0a05ce | 521 | { |
a5e9c572 | 522 | if (tx_buffer->skb) { |
64bfd68e AD |
523 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
524 | kfree(tx_buffer->raw_buf); | |
525 | else | |
526 | dev_kfree_skb_any(tx_buffer->skb); | |
a5e9c572 | 527 | if (dma_unmap_len(tx_buffer, len)) |
fd0a05ce | 528 | dma_unmap_single(ring->dev, |
35a1e2ad AD |
529 | dma_unmap_addr(tx_buffer, dma), |
530 | dma_unmap_len(tx_buffer, len), | |
fd0a05ce | 531 | DMA_TO_DEVICE); |
a5e9c572 AD |
532 | } else if (dma_unmap_len(tx_buffer, len)) { |
533 | dma_unmap_page(ring->dev, | |
534 | dma_unmap_addr(tx_buffer, dma), | |
535 | dma_unmap_len(tx_buffer, len), | |
536 | DMA_TO_DEVICE); | |
fd0a05ce | 537 | } |
a42e7a36 | 538 | |
a5e9c572 AD |
539 | tx_buffer->next_to_watch = NULL; |
540 | tx_buffer->skb = NULL; | |
35a1e2ad | 541 | dma_unmap_len_set(tx_buffer, len, 0); |
a5e9c572 | 542 | /* tx_buffer must be completely set up in the transmit path */ |
fd0a05ce JB |
543 | } |
544 | ||
545 | /** | |
546 | * i40e_clean_tx_ring - Free any empty Tx buffers | |
547 | * @tx_ring: ring to be cleaned | |
548 | **/ | |
549 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring) | |
550 | { | |
fd0a05ce JB |
551 | unsigned long bi_size; |
552 | u16 i; | |
553 | ||
554 | /* ring already cleared, nothing to do */ | |
555 | if (!tx_ring->tx_bi) | |
556 | return; | |
557 | ||
558 | /* Free all the Tx ring sk_buffs */ | |
a5e9c572 AD |
559 | for (i = 0; i < tx_ring->count; i++) |
560 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
fd0a05ce JB |
561 | |
562 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
563 | memset(tx_ring->tx_bi, 0, bi_size); | |
564 | ||
565 | /* Zero out the descriptor ring */ | |
566 | memset(tx_ring->desc, 0, tx_ring->size); | |
567 | ||
568 | tx_ring->next_to_use = 0; | |
569 | tx_ring->next_to_clean = 0; | |
7070ce0a AD |
570 | |
571 | if (!tx_ring->netdev) | |
572 | return; | |
573 | ||
574 | /* cleanup Tx queue statistics */ | |
e486bdfd | 575 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
fd0a05ce JB |
576 | } |
577 | ||
578 | /** | |
579 | * i40e_free_tx_resources - Free Tx resources per queue | |
580 | * @tx_ring: Tx descriptor ring for a specific queue | |
581 | * | |
582 | * Free all transmit software resources | |
583 | **/ | |
584 | void i40e_free_tx_resources(struct i40e_ring *tx_ring) | |
585 | { | |
586 | i40e_clean_tx_ring(tx_ring); | |
587 | kfree(tx_ring->tx_bi); | |
588 | tx_ring->tx_bi = NULL; | |
589 | ||
590 | if (tx_ring->desc) { | |
591 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
592 | tx_ring->desc, tx_ring->dma); | |
593 | tx_ring->desc = NULL; | |
594 | } | |
595 | } | |
596 | ||
597 | /** | |
598 | * i40e_get_tx_pending - how many tx descriptors not processed | |
599 | * @tx_ring: the ring of descriptors | |
dd353109 | 600 | * @in_sw: is tx_pending being checked in SW or HW |
fd0a05ce JB |
601 | * |
602 | * Since there is no access to the ring head register | |
603 | * in XL710, we need to use our local copies | |
604 | **/ | |
dd353109 | 605 | u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
fd0a05ce | 606 | { |
a68de58d JB |
607 | u32 head, tail; |
608 | ||
dd353109 ASJ |
609 | if (!in_sw) |
610 | head = i40e_get_head(ring); | |
611 | else | |
612 | head = ring->next_to_clean; | |
a68de58d JB |
613 | tail = readl(ring->tail); |
614 | ||
615 | if (head != tail) | |
616 | return (head < tail) ? | |
617 | tail - head : (tail + ring->count - head); | |
618 | ||
619 | return 0; | |
fd0a05ce JB |
620 | } |
621 | ||
d91649f5 JB |
622 | #define WB_STRIDE 0x3 |
623 | ||
fd0a05ce JB |
624 | /** |
625 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
626 | * @vsi: the VSI we care about |
627 | * @tx_ring: Tx ring to clean | |
628 | * @napi_budget: Used to determine if we are in netpoll | |
fd0a05ce JB |
629 | * |
630 | * Returns true if there's any budget left (e.g. the clean is finished) | |
631 | **/ | |
a619afe8 AD |
632 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
633 | struct i40e_ring *tx_ring, int napi_budget) | |
fd0a05ce JB |
634 | { |
635 | u16 i = tx_ring->next_to_clean; | |
636 | struct i40e_tx_buffer *tx_buf; | |
1943d8ba | 637 | struct i40e_tx_desc *tx_head; |
fd0a05ce | 638 | struct i40e_tx_desc *tx_desc; |
a619afe8 AD |
639 | unsigned int total_bytes = 0, total_packets = 0; |
640 | unsigned int budget = vsi->work_limit; | |
fd0a05ce JB |
641 | |
642 | tx_buf = &tx_ring->tx_bi[i]; | |
643 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
a5e9c572 | 644 | i -= tx_ring->count; |
fd0a05ce | 645 | |
1943d8ba JB |
646 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
647 | ||
a5e9c572 AD |
648 | do { |
649 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
fd0a05ce JB |
650 | |
651 | /* if next_to_watch is not set then there is no work pending */ | |
652 | if (!eop_desc) | |
653 | break; | |
654 | ||
a5e9c572 AD |
655 | /* prevent any other reads prior to eop_desc */ |
656 | read_barrier_depends(); | |
657 | ||
1943d8ba JB |
658 | /* we have caught up to head, no work left to do */ |
659 | if (tx_head == tx_desc) | |
fd0a05ce JB |
660 | break; |
661 | ||
c304fdac | 662 | /* clear next_to_watch to prevent false hangs */ |
fd0a05ce | 663 | tx_buf->next_to_watch = NULL; |
fd0a05ce | 664 | |
a5e9c572 AD |
665 | /* update the statistics for this packet */ |
666 | total_bytes += tx_buf->bytecount; | |
667 | total_packets += tx_buf->gso_segs; | |
fd0a05ce | 668 | |
a5e9c572 | 669 | /* free the skb */ |
a619afe8 | 670 | napi_consume_skb(tx_buf->skb, napi_budget); |
fd0a05ce | 671 | |
a5e9c572 AD |
672 | /* unmap skb header data */ |
673 | dma_unmap_single(tx_ring->dev, | |
674 | dma_unmap_addr(tx_buf, dma), | |
675 | dma_unmap_len(tx_buf, len), | |
676 | DMA_TO_DEVICE); | |
fd0a05ce | 677 | |
a5e9c572 AD |
678 | /* clear tx_buffer data */ |
679 | tx_buf->skb = NULL; | |
680 | dma_unmap_len_set(tx_buf, len, 0); | |
fd0a05ce | 681 | |
a5e9c572 AD |
682 | /* unmap remaining buffers */ |
683 | while (tx_desc != eop_desc) { | |
fd0a05ce JB |
684 | |
685 | tx_buf++; | |
686 | tx_desc++; | |
687 | i++; | |
a5e9c572 AD |
688 | if (unlikely(!i)) { |
689 | i -= tx_ring->count; | |
fd0a05ce JB |
690 | tx_buf = tx_ring->tx_bi; |
691 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
692 | } | |
fd0a05ce | 693 | |
a5e9c572 AD |
694 | /* unmap any remaining paged data */ |
695 | if (dma_unmap_len(tx_buf, len)) { | |
696 | dma_unmap_page(tx_ring->dev, | |
697 | dma_unmap_addr(tx_buf, dma), | |
698 | dma_unmap_len(tx_buf, len), | |
699 | DMA_TO_DEVICE); | |
700 | dma_unmap_len_set(tx_buf, len, 0); | |
701 | } | |
702 | } | |
703 | ||
704 | /* move us one more past the eop_desc for start of next pkt */ | |
705 | tx_buf++; | |
706 | tx_desc++; | |
707 | i++; | |
708 | if (unlikely(!i)) { | |
709 | i -= tx_ring->count; | |
710 | tx_buf = tx_ring->tx_bi; | |
711 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
712 | } | |
713 | ||
016890b9 JB |
714 | prefetch(tx_desc); |
715 | ||
a5e9c572 AD |
716 | /* update budget accounting */ |
717 | budget--; | |
718 | } while (likely(budget)); | |
719 | ||
720 | i += tx_ring->count; | |
fd0a05ce | 721 | tx_ring->next_to_clean = i; |
980e9b11 | 722 | u64_stats_update_begin(&tx_ring->syncp); |
a114d0a6 AD |
723 | tx_ring->stats.bytes += total_bytes; |
724 | tx_ring->stats.packets += total_packets; | |
980e9b11 | 725 | u64_stats_update_end(&tx_ring->syncp); |
fd0a05ce JB |
726 | tx_ring->q_vector->tx.total_bytes += total_bytes; |
727 | tx_ring->q_vector->tx.total_packets += total_packets; | |
a5e9c572 | 728 | |
58044743 | 729 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
58044743 AS |
730 | /* check to see if there are < 4 descriptors |
731 | * waiting to be written back, then kick the hardware to force | |
732 | * them to be written back in case we stay in NAPI. | |
733 | * In this mode on X722 we do not enable Interrupt. | |
734 | */ | |
88dc9e6f | 735 | unsigned int j = i40e_get_tx_pending(tx_ring, false); |
58044743 AS |
736 | |
737 | if (budget && | |
738 | ((j / (WB_STRIDE + 1)) == 0) && (j != 0) && | |
a619afe8 | 739 | !test_bit(__I40E_DOWN, &vsi->state) && |
58044743 AS |
740 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) |
741 | tx_ring->arm_wb = true; | |
742 | } | |
d91649f5 | 743 | |
e486bdfd AD |
744 | /* notify netdev of completed buffers */ |
745 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
7070ce0a AD |
746 | total_packets, total_bytes); |
747 | ||
fd0a05ce JB |
748 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
749 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
750 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
751 | /* Make sure that anybody stopping the queue after this | |
752 | * sees the new next_to_clean. | |
753 | */ | |
754 | smp_mb(); | |
755 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
756 | tx_ring->queue_index) && | |
a619afe8 | 757 | !test_bit(__I40E_DOWN, &vsi->state)) { |
fd0a05ce JB |
758 | netif_wake_subqueue(tx_ring->netdev, |
759 | tx_ring->queue_index); | |
760 | ++tx_ring->tx_stats.restart_queue; | |
761 | } | |
762 | } | |
763 | ||
d91649f5 JB |
764 | return !!budget; |
765 | } | |
766 | ||
767 | /** | |
ecc6a239 | 768 | * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
d91649f5 | 769 | * @vsi: the VSI we care about |
ecc6a239 | 770 | * @q_vector: the vector on which to enable writeback |
d91649f5 JB |
771 | * |
772 | **/ | |
ecc6a239 ASJ |
773 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
774 | struct i40e_q_vector *q_vector) | |
d91649f5 | 775 | { |
8e0764b4 | 776 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 777 | u32 val; |
8e0764b4 | 778 | |
ecc6a239 ASJ |
779 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
780 | return; | |
8e0764b4 | 781 | |
ecc6a239 ASJ |
782 | if (q_vector->arm_wb_state) |
783 | return; | |
8e0764b4 | 784 | |
ecc6a239 ASJ |
785 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { |
786 | val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | | |
787 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 788 | |
ecc6a239 ASJ |
789 | wr32(&vsi->back->hw, |
790 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), | |
791 | val); | |
792 | } else { | |
793 | val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | | |
794 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 795 | |
ecc6a239 ASJ |
796 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); |
797 | } | |
798 | q_vector->arm_wb_state = true; | |
799 | } | |
800 | ||
801 | /** | |
802 | * i40e_force_wb - Issue SW Interrupt so HW does a wb | |
803 | * @vsi: the VSI we care about | |
804 | * @q_vector: the vector on which to force writeback | |
805 | * | |
806 | **/ | |
807 | void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
808 | { | |
809 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { | |
8e0764b4 ASJ |
810 | u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | |
811 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ | |
812 | I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | | |
813 | I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; | |
814 | /* allow 00 to be written to the index */ | |
815 | ||
816 | wr32(&vsi->back->hw, | |
817 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + | |
818 | vsi->base_vector - 1), val); | |
819 | } else { | |
820 | u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
821 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ | |
822 | I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | | |
823 | I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; | |
824 | /* allow 00 to be written to the index */ | |
825 | ||
826 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); | |
827 | } | |
fd0a05ce JB |
828 | } |
829 | ||
830 | /** | |
831 | * i40e_set_new_dynamic_itr - Find new ITR level | |
832 | * @rc: structure containing ring performance data | |
833 | * | |
8f5e39ce JB |
834 | * Returns true if ITR changed, false if not |
835 | * | |
fd0a05ce JB |
836 | * Stores a new ITR value based on packets and byte counts during |
837 | * the last interrupt. The advantage of per interrupt computation | |
838 | * is faster updates and more accurate ITR for the current traffic | |
839 | * pattern. Constants in this function were computed based on | |
840 | * theoretical maximum wire speed and thresholds were set based on | |
841 | * testing data as well as attempting to minimize response time | |
842 | * while increasing bulk throughput. | |
843 | **/ | |
8f5e39ce | 844 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
fd0a05ce JB |
845 | { |
846 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
c56625d5 | 847 | struct i40e_q_vector *qv = rc->ring->q_vector; |
fd0a05ce JB |
848 | u32 new_itr = rc->itr; |
849 | int bytes_per_int; | |
51cc6d9f | 850 | int usecs; |
fd0a05ce JB |
851 | |
852 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 853 | return false; |
fd0a05ce JB |
854 | |
855 | /* simple throttlerate management | |
c56625d5 | 856 | * 0-10MB/s lowest (50000 ints/s) |
fd0a05ce | 857 | * 10-20MB/s low (20000 ints/s) |
c56625d5 JB |
858 | * 20-1249MB/s bulk (18000 ints/s) |
859 | * > 40000 Rx packets per second (8000 ints/s) | |
51cc6d9f JB |
860 | * |
861 | * The math works out because the divisor is in 10^(-6) which | |
862 | * turns the bytes/us input value into MB/s values, but | |
863 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
864 | * are in 2 usec increments in the ITR registers, and make sure |
865 | * to use the smoothed values that the countdown timer gives us. | |
fd0a05ce | 866 | */ |
ee2319cf | 867 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
51cc6d9f | 868 | bytes_per_int = rc->total_bytes / usecs; |
ee2319cf | 869 | |
de32e3ef | 870 | switch (new_latency_range) { |
fd0a05ce JB |
871 | case I40E_LOWEST_LATENCY: |
872 | if (bytes_per_int > 10) | |
873 | new_latency_range = I40E_LOW_LATENCY; | |
874 | break; | |
875 | case I40E_LOW_LATENCY: | |
876 | if (bytes_per_int > 20) | |
877 | new_latency_range = I40E_BULK_LATENCY; | |
878 | else if (bytes_per_int <= 10) | |
879 | new_latency_range = I40E_LOWEST_LATENCY; | |
880 | break; | |
881 | case I40E_BULK_LATENCY: | |
c56625d5 | 882 | case I40E_ULTRA_LATENCY: |
de32e3ef CW |
883 | default: |
884 | if (bytes_per_int <= 20) | |
885 | new_latency_range = I40E_LOW_LATENCY; | |
fd0a05ce JB |
886 | break; |
887 | } | |
c56625d5 JB |
888 | |
889 | /* this is to adjust RX more aggressively when streaming small | |
890 | * packets. The value of 40000 was picked as it is just beyond | |
891 | * what the hardware can receive per second if in low latency | |
892 | * mode. | |
893 | */ | |
894 | #define RX_ULTRA_PACKET_RATE 40000 | |
895 | ||
896 | if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && | |
897 | (&qv->rx == rc)) | |
898 | new_latency_range = I40E_ULTRA_LATENCY; | |
899 | ||
de32e3ef | 900 | rc->latency_range = new_latency_range; |
fd0a05ce JB |
901 | |
902 | switch (new_latency_range) { | |
903 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 904 | new_itr = I40E_ITR_50K; |
fd0a05ce JB |
905 | break; |
906 | case I40E_LOW_LATENCY: | |
907 | new_itr = I40E_ITR_20K; | |
908 | break; | |
909 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
910 | new_itr = I40E_ITR_18K; |
911 | break; | |
912 | case I40E_ULTRA_LATENCY: | |
fd0a05ce JB |
913 | new_itr = I40E_ITR_8K; |
914 | break; | |
915 | default: | |
916 | break; | |
917 | } | |
918 | ||
fd0a05ce JB |
919 | rc->total_bytes = 0; |
920 | rc->total_packets = 0; | |
8f5e39ce JB |
921 | |
922 | if (new_itr != rc->itr) { | |
923 | rc->itr = new_itr; | |
924 | return true; | |
925 | } | |
926 | ||
927 | return false; | |
fd0a05ce JB |
928 | } |
929 | ||
fd0a05ce JB |
930 | /** |
931 | * i40e_clean_programming_status - clean the programming status descriptor | |
932 | * @rx_ring: the rx ring that has this descriptor | |
933 | * @rx_desc: the rx descriptor written back by HW | |
934 | * | |
935 | * Flow director should handle FD_FILTER_STATUS to check its filter programming | |
936 | * status being successful or not and take actions accordingly. FCoE should | |
937 | * handle its context/filter programming/invalidation status and take actions. | |
938 | * | |
939 | **/ | |
940 | static void i40e_clean_programming_status(struct i40e_ring *rx_ring, | |
941 | union i40e_rx_desc *rx_desc) | |
942 | { | |
943 | u64 qw; | |
944 | u8 id; | |
945 | ||
946 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
947 | id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> | |
948 | I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; | |
949 | ||
950 | if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) | |
55a5e60b | 951 | i40e_fd_handle_status(rx_ring, rx_desc, id); |
38e00438 VD |
952 | #ifdef I40E_FCOE |
953 | else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || | |
954 | (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) | |
955 | i40e_fcoe_handle_status(rx_ring, rx_desc, id); | |
956 | #endif | |
fd0a05ce JB |
957 | } |
958 | ||
959 | /** | |
960 | * i40e_setup_tx_descriptors - Allocate the Tx descriptors | |
961 | * @tx_ring: the tx ring to set up | |
962 | * | |
963 | * Return 0 on success, negative on error | |
964 | **/ | |
965 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
966 | { | |
967 | struct device *dev = tx_ring->dev; | |
968 | int bi_size; | |
969 | ||
970 | if (!dev) | |
971 | return -ENOMEM; | |
972 | ||
e908f815 JB |
973 | /* warn if we are about to overwrite the pointer */ |
974 | WARN_ON(tx_ring->tx_bi); | |
fd0a05ce JB |
975 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
976 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
977 | if (!tx_ring->tx_bi) | |
978 | goto err; | |
979 | ||
980 | /* round up to nearest 4K */ | |
981 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
982 | /* add u32 for head writeback, align after this takes care of |
983 | * guaranteeing this is at least one cache line in size | |
984 | */ | |
985 | tx_ring->size += sizeof(u32); | |
fd0a05ce JB |
986 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
987 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
988 | &tx_ring->dma, GFP_KERNEL); | |
989 | if (!tx_ring->desc) { | |
990 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
991 | tx_ring->size); | |
992 | goto err; | |
993 | } | |
994 | ||
995 | tx_ring->next_to_use = 0; | |
996 | tx_ring->next_to_clean = 0; | |
997 | return 0; | |
998 | ||
999 | err: | |
1000 | kfree(tx_ring->tx_bi); | |
1001 | tx_ring->tx_bi = NULL; | |
1002 | return -ENOMEM; | |
1003 | } | |
1004 | ||
1005 | /** | |
1006 | * i40e_clean_rx_ring - Free Rx buffers | |
1007 | * @rx_ring: ring to be cleaned | |
1008 | **/ | |
1009 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring) | |
1010 | { | |
1011 | struct device *dev = rx_ring->dev; | |
fd0a05ce JB |
1012 | unsigned long bi_size; |
1013 | u16 i; | |
1014 | ||
1015 | /* ring already cleared, nothing to do */ | |
1016 | if (!rx_ring->rx_bi) | |
1017 | return; | |
1018 | ||
1019 | /* Free all the Rx ring sk_buffs */ | |
1020 | for (i = 0; i < rx_ring->count; i++) { | |
1a557afc JB |
1021 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
1022 | ||
fd0a05ce JB |
1023 | if (rx_bi->skb) { |
1024 | dev_kfree_skb(rx_bi->skb); | |
1025 | rx_bi->skb = NULL; | |
1026 | } | |
1a557afc JB |
1027 | if (!rx_bi->page) |
1028 | continue; | |
1029 | ||
1030 | dma_unmap_page(dev, rx_bi->dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
1031 | __free_pages(rx_bi->page, 0); | |
1032 | ||
1033 | rx_bi->page = NULL; | |
1034 | rx_bi->page_offset = 0; | |
fd0a05ce JB |
1035 | } |
1036 | ||
1037 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
1038 | memset(rx_ring->rx_bi, 0, bi_size); | |
1039 | ||
1040 | /* Zero out the descriptor ring */ | |
1041 | memset(rx_ring->desc, 0, rx_ring->size); | |
1042 | ||
1a557afc | 1043 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1044 | rx_ring->next_to_clean = 0; |
1045 | rx_ring->next_to_use = 0; | |
1046 | } | |
1047 | ||
1048 | /** | |
1049 | * i40e_free_rx_resources - Free Rx resources | |
1050 | * @rx_ring: ring to clean the resources from | |
1051 | * | |
1052 | * Free all receive software resources | |
1053 | **/ | |
1054 | void i40e_free_rx_resources(struct i40e_ring *rx_ring) | |
1055 | { | |
1056 | i40e_clean_rx_ring(rx_ring); | |
1057 | kfree(rx_ring->rx_bi); | |
1058 | rx_ring->rx_bi = NULL; | |
1059 | ||
1060 | if (rx_ring->desc) { | |
1061 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
1062 | rx_ring->desc, rx_ring->dma); | |
1063 | rx_ring->desc = NULL; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | /** | |
1068 | * i40e_setup_rx_descriptors - Allocate Rx descriptors | |
1069 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
1070 | * | |
1071 | * Returns 0 on success, negative on failure | |
1072 | **/ | |
1073 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
1074 | { | |
1075 | struct device *dev = rx_ring->dev; | |
1076 | int bi_size; | |
1077 | ||
e908f815 JB |
1078 | /* warn if we are about to overwrite the pointer */ |
1079 | WARN_ON(rx_ring->rx_bi); | |
fd0a05ce JB |
1080 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
1081 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1082 | if (!rx_ring->rx_bi) | |
1083 | goto err; | |
1084 | ||
f217d6ca | 1085 | u64_stats_init(&rx_ring->syncp); |
638702bd | 1086 | |
fd0a05ce | 1087 | /* Round up to nearest 4K */ |
1a557afc | 1088 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
fd0a05ce JB |
1089 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
1090 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
1091 | &rx_ring->dma, GFP_KERNEL); | |
1092 | ||
1093 | if (!rx_ring->desc) { | |
1094 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
1095 | rx_ring->size); | |
1096 | goto err; | |
1097 | } | |
1098 | ||
1a557afc | 1099 | rx_ring->next_to_alloc = 0; |
fd0a05ce JB |
1100 | rx_ring->next_to_clean = 0; |
1101 | rx_ring->next_to_use = 0; | |
1102 | ||
1103 | return 0; | |
1104 | err: | |
1105 | kfree(rx_ring->rx_bi); | |
1106 | rx_ring->rx_bi = NULL; | |
1107 | return -ENOMEM; | |
1108 | } | |
1109 | ||
1110 | /** | |
1111 | * i40e_release_rx_desc - Store the new tail and head values | |
1112 | * @rx_ring: ring to bump | |
1113 | * @val: new head index | |
1114 | **/ | |
1115 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
1116 | { | |
1117 | rx_ring->next_to_use = val; | |
1a557afc JB |
1118 | |
1119 | /* update next to alloc since we have filled the ring */ | |
1120 | rx_ring->next_to_alloc = val; | |
1121 | ||
fd0a05ce JB |
1122 | /* Force memory writes to complete before letting h/w |
1123 | * know there are new descriptors to fetch. (Only | |
1124 | * applicable for weak-ordered memory model archs, | |
1125 | * such as IA-64). | |
1126 | */ | |
1127 | wmb(); | |
1128 | writel(val, rx_ring->tail); | |
1129 | } | |
1130 | ||
1131 | /** | |
1a557afc JB |
1132 | * i40e_alloc_mapped_page - recycle or make a new page |
1133 | * @rx_ring: ring to use | |
1134 | * @bi: rx_buffer struct to modify | |
c2e245ab | 1135 | * |
1a557afc JB |
1136 | * Returns true if the page was successfully allocated or |
1137 | * reused. | |
fd0a05ce | 1138 | **/ |
1a557afc JB |
1139 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
1140 | struct i40e_rx_buffer *bi) | |
a132af24 | 1141 | { |
1a557afc JB |
1142 | struct page *page = bi->page; |
1143 | dma_addr_t dma; | |
a132af24 | 1144 | |
1a557afc JB |
1145 | /* since we are recycling buffers we should seldom need to alloc */ |
1146 | if (likely(page)) { | |
1147 | rx_ring->rx_stats.page_reuse_count++; | |
1148 | return true; | |
1149 | } | |
a132af24 | 1150 | |
1a557afc JB |
1151 | /* alloc new page for storage */ |
1152 | page = dev_alloc_page(); | |
1153 | if (unlikely(!page)) { | |
1154 | rx_ring->rx_stats.alloc_page_failed++; | |
1155 | return false; | |
1156 | } | |
a132af24 | 1157 | |
1a557afc JB |
1158 | /* map page for use */ |
1159 | dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
f16704e5 | 1160 | |
1a557afc JB |
1161 | /* if mapping failed free memory back to system since |
1162 | * there isn't much point in holding memory we can't use | |
f16704e5 | 1163 | */ |
1a557afc JB |
1164 | if (dma_mapping_error(rx_ring->dev, dma)) { |
1165 | __free_pages(page, 0); | |
1166 | rx_ring->rx_stats.alloc_page_failed++; | |
1167 | return false; | |
a132af24 MW |
1168 | } |
1169 | ||
1a557afc JB |
1170 | bi->dma = dma; |
1171 | bi->page = page; | |
1172 | bi->page_offset = 0; | |
c2e245ab | 1173 | |
1a557afc JB |
1174 | return true; |
1175 | } | |
c2e245ab | 1176 | |
1a557afc JB |
1177 | /** |
1178 | * i40e_receive_skb - Send a completed packet up the stack | |
1179 | * @rx_ring: rx ring in play | |
1180 | * @skb: packet to send up | |
1181 | * @vlan_tag: vlan tag for packet | |
1182 | **/ | |
1183 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
1184 | struct sk_buff *skb, u16 vlan_tag) | |
1185 | { | |
1186 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
c2e245ab | 1187 | |
1a557afc JB |
1188 | if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
1189 | (vlan_tag & VLAN_VID_MASK)) | |
1190 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
1191 | ||
1192 | napi_gro_receive(&q_vector->napi, skb); | |
a132af24 MW |
1193 | } |
1194 | ||
1195 | /** | |
1a557afc | 1196 | * i40e_alloc_rx_buffers - Replace used receive buffers |
a132af24 MW |
1197 | * @rx_ring: ring to place buffers on |
1198 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 1199 | * |
1a557afc | 1200 | * Returns false if all allocations were successful, true if any fail |
a132af24 | 1201 | **/ |
1a557afc | 1202 | bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
fd0a05ce | 1203 | { |
1a557afc | 1204 | u16 ntu = rx_ring->next_to_use; |
fd0a05ce JB |
1205 | union i40e_rx_desc *rx_desc; |
1206 | struct i40e_rx_buffer *bi; | |
fd0a05ce JB |
1207 | |
1208 | /* do nothing if no valid netdev defined */ | |
1209 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 1210 | return false; |
fd0a05ce | 1211 | |
1a557afc JB |
1212 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
1213 | bi = &rx_ring->rx_bi[ntu]; | |
fd0a05ce | 1214 | |
1a557afc JB |
1215 | do { |
1216 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
1217 | goto no_buffers; | |
fd0a05ce | 1218 | |
1a557afc JB |
1219 | /* Refresh the desc even if buffer_addrs didn't change |
1220 | * because each write-back erases this info. | |
1221 | */ | |
1222 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
a132af24 | 1223 | rx_desc->read.hdr_addr = 0; |
fd0a05ce | 1224 | |
1a557afc JB |
1225 | rx_desc++; |
1226 | bi++; | |
1227 | ntu++; | |
1228 | if (unlikely(ntu == rx_ring->count)) { | |
1229 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
1230 | bi = rx_ring->rx_bi; | |
1231 | ntu = 0; | |
1232 | } | |
1233 | ||
1234 | /* clear the status bits for the next_to_use descriptor */ | |
1235 | rx_desc->wb.qword1.status_error_len = 0; | |
1236 | ||
1237 | cleaned_count--; | |
1238 | } while (cleaned_count); | |
1239 | ||
1240 | if (rx_ring->next_to_use != ntu) | |
1241 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1242 | |
1243 | return false; | |
1244 | ||
fd0a05ce | 1245 | no_buffers: |
1a557afc JB |
1246 | if (rx_ring->next_to_use != ntu) |
1247 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
1248 | |
1249 | /* make sure to come back via polling to try again after | |
1250 | * allocation failure | |
1251 | */ | |
1252 | return true; | |
fd0a05ce JB |
1253 | } |
1254 | ||
fd0a05ce JB |
1255 | /** |
1256 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
1257 | * @vsi: the VSI we care about | |
1258 | * @skb: skb currently being received and modified | |
1a557afc JB |
1259 | * @rx_desc: the receive descriptor |
1260 | * | |
1261 | * skb->protocol must be set before this function is called | |
fd0a05ce JB |
1262 | **/ |
1263 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
1264 | struct sk_buff *skb, | |
1a557afc | 1265 | union i40e_rx_desc *rx_desc) |
fd0a05ce | 1266 | { |
1a557afc | 1267 | struct i40e_rx_ptype_decoded decoded; |
1a557afc | 1268 | u32 rx_error, rx_status; |
858296c8 | 1269 | bool ipv4, ipv6; |
1a557afc JB |
1270 | u8 ptype; |
1271 | u64 qword; | |
1272 | ||
1273 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1274 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
1275 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
1276 | I40E_RXD_QW1_ERROR_SHIFT; | |
1277 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1278 | I40E_RXD_QW1_STATUS_SHIFT; | |
1279 | decoded = decode_rx_desc_ptype(ptype); | |
8144f0f7 | 1280 | |
fd0a05ce JB |
1281 | skb->ip_summed = CHECKSUM_NONE; |
1282 | ||
1a557afc JB |
1283 | skb_checksum_none_assert(skb); |
1284 | ||
fd0a05ce | 1285 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
1286 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
1287 | return; | |
1288 | ||
1289 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 1290 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
1291 | return; |
1292 | ||
1293 | /* both known and outer_ip must be set for the below code to work */ | |
1294 | if (!(decoded.known && decoded.outer_ip)) | |
fd0a05ce JB |
1295 | return; |
1296 | ||
fad57330 AD |
1297 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
1298 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
1299 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
1300 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
1301 | |
1302 | if (ipv4 && | |
41a1d04b JB |
1303 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
1304 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
1305 | goto checksum_fail; |
1306 | ||
ddf1d0d7 | 1307 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 1308 | if (ipv6 && |
41a1d04b | 1309 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 1310 | /* don't increment checksum err here, non-fatal err */ |
8ee75a8e SN |
1311 | return; |
1312 | ||
8a3c91cc | 1313 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 1314 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
1315 | goto checksum_fail; |
1316 | ||
1317 | /* handle packets that were not able to be checksummed due | |
1318 | * to arrival speed, in this case the stack can compute | |
1319 | * the csum. | |
1320 | */ | |
41a1d04b | 1321 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
fd0a05ce | 1322 | return; |
fd0a05ce | 1323 | |
858296c8 AD |
1324 | /* If there is an outer header present that might contain a checksum |
1325 | * we need to bump the checksum level by 1 to reflect the fact that | |
1326 | * we are indicating we validated the inner checksum. | |
8a3c91cc | 1327 | */ |
858296c8 AD |
1328 | if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) |
1329 | skb->csum_level = 1; | |
1330 | ||
1331 | /* Only report checksum unnecessary for TCP, UDP, or SCTP */ | |
1332 | switch (decoded.inner_prot) { | |
1333 | case I40E_RX_PTYPE_INNER_PROT_TCP: | |
1334 | case I40E_RX_PTYPE_INNER_PROT_UDP: | |
1335 | case I40E_RX_PTYPE_INNER_PROT_SCTP: | |
1336 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1337 | /* fall though */ | |
1338 | default: | |
1339 | break; | |
1340 | } | |
8a3c91cc JB |
1341 | |
1342 | return; | |
1343 | ||
1344 | checksum_fail: | |
1345 | vsi->back->hw_csum_rx_error++; | |
fd0a05ce JB |
1346 | } |
1347 | ||
1348 | /** | |
857942fd | 1349 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
1350 | * @ptype: the ptype value from the descriptor |
1351 | * | |
1352 | * Returns a hash type to be used by skb_set_hash | |
1353 | **/ | |
1a557afc | 1354 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
1355 | { |
1356 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
1357 | ||
1358 | if (!decoded.known) | |
1359 | return PKT_HASH_TYPE_NONE; | |
1360 | ||
1361 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1362 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
1363 | return PKT_HASH_TYPE_L4; | |
1364 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1365 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
1366 | return PKT_HASH_TYPE_L3; | |
1367 | else | |
1368 | return PKT_HASH_TYPE_L2; | |
1369 | } | |
1370 | ||
857942fd ASJ |
1371 | /** |
1372 | * i40e_rx_hash - set the hash value in the skb | |
1373 | * @ring: descriptor ring | |
1374 | * @rx_desc: specific descriptor | |
1375 | **/ | |
1376 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
1377 | union i40e_rx_desc *rx_desc, | |
1378 | struct sk_buff *skb, | |
1379 | u8 rx_ptype) | |
1380 | { | |
1381 | u32 hash; | |
1a557afc | 1382 | const __le64 rss_mask = |
857942fd ASJ |
1383 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
1384 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
1385 | ||
a876c3ba | 1386 | if (!(ring->netdev->features & NETIF_F_RXHASH)) |
857942fd ASJ |
1387 | return; |
1388 | ||
1389 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
1390 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
1391 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
1392 | } | |
1393 | } | |
1394 | ||
a132af24 | 1395 | /** |
1a557afc JB |
1396 | * i40e_process_skb_fields - Populate skb header fields from Rx descriptor |
1397 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1398 | * @rx_desc: pointer to the EOP Rx descriptor | |
1399 | * @skb: pointer to current skb being populated | |
1400 | * @rx_ptype: the packet type decoded by hardware | |
1401 | * | |
1402 | * This function checks the ring, descriptor, and packet information in | |
1403 | * order to populate the hash, checksum, VLAN, protocol, and | |
1404 | * other fields within the skb. | |
1405 | **/ | |
1406 | static inline | |
1407 | void i40e_process_skb_fields(struct i40e_ring *rx_ring, | |
1408 | union i40e_rx_desc *rx_desc, struct sk_buff *skb, | |
1409 | u8 rx_ptype) | |
1410 | { | |
1411 | u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1412 | u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1413 | I40E_RXD_QW1_STATUS_SHIFT; | |
1414 | u32 rsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> | |
1415 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; | |
1416 | ||
1417 | if (unlikely(rsyn)) { | |
1418 | i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, rsyn); | |
1419 | rx_ring->last_rx_timestamp = jiffies; | |
1420 | } | |
1421 | ||
1422 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); | |
1423 | ||
1424 | /* modifies the skb - consumes the enet header */ | |
1425 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
1426 | ||
1427 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); | |
1428 | ||
1429 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
1430 | } | |
1431 | ||
1432 | /** | |
1433 | * i40e_pull_tail - i40e specific version of skb_pull_tail | |
1434 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1435 | * @skb: pointer to current skb being adjusted | |
1436 | * | |
1437 | * This function is an i40e specific version of __pskb_pull_tail. The | |
1438 | * main difference between this version and the original function is that | |
1439 | * this function can make several assumptions about the state of things | |
1440 | * that allow for significant optimizations versus the standard function. | |
1441 | * As a result we can do things like drop a frag and maintain an accurate | |
1442 | * truesize for the skb. | |
1443 | */ | |
1444 | static void i40e_pull_tail(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
1445 | { | |
1446 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1447 | unsigned char *va; | |
1448 | unsigned int pull_len; | |
1449 | ||
1450 | /* it is valid to use page_address instead of kmap since we are | |
1451 | * working with pages allocated out of the lomem pool per | |
1452 | * alloc_page(GFP_ATOMIC) | |
1453 | */ | |
1454 | va = skb_frag_address(frag); | |
1455 | ||
1456 | /* we need the header to contain the greater of either ETH_HLEN or | |
1457 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1458 | */ | |
1459 | pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE); | |
1460 | ||
1461 | /* align pull length to size of long to optimize memcpy performance */ | |
1462 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1463 | ||
1464 | /* update all of the pointers */ | |
1465 | skb_frag_size_sub(frag, pull_len); | |
1466 | frag->page_offset += pull_len; | |
1467 | skb->data_len -= pull_len; | |
1468 | skb->tail += pull_len; | |
1469 | } | |
1470 | ||
1471 | /** | |
1472 | * i40e_cleanup_headers - Correct empty headers | |
1473 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1474 | * @skb: pointer to current skb being fixed | |
1475 | * | |
1476 | * Also address the case where we are pulling data in on pages only | |
1477 | * and as such no data is present in the skb header. | |
1478 | * | |
1479 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1480 | * it is large enough to qualify as a valid Ethernet frame. | |
1481 | * | |
1482 | * Returns true if an error was encountered and skb was freed. | |
1483 | **/ | |
1484 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
1485 | { | |
1486 | /* place header in linear portion of buffer */ | |
1487 | if (skb_is_nonlinear(skb)) | |
1488 | i40e_pull_tail(rx_ring, skb); | |
1489 | ||
1490 | /* if eth_skb_pad returns an error the skb was freed */ | |
1491 | if (eth_skb_pad(skb)) | |
1492 | return true; | |
1493 | ||
1494 | return false; | |
1495 | } | |
1496 | ||
1497 | /** | |
1498 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
1499 | * @rx_ring: rx descriptor ring to store buffers on | |
1500 | * @old_buff: donor buffer to have page reused | |
1501 | * | |
1502 | * Synchronizes page for reuse by the adapter | |
1503 | **/ | |
1504 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
1505 | struct i40e_rx_buffer *old_buff) | |
1506 | { | |
1507 | struct i40e_rx_buffer *new_buff; | |
1508 | u16 nta = rx_ring->next_to_alloc; | |
1509 | ||
1510 | new_buff = &rx_ring->rx_bi[nta]; | |
1511 | ||
1512 | /* update, and store next to alloc */ | |
1513 | nta++; | |
1514 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1515 | ||
1516 | /* transfer page from old buffer to new buffer */ | |
1517 | *new_buff = *old_buff; | |
1518 | } | |
1519 | ||
1520 | /** | |
1521 | * i40e_page_is_reserved - check if reuse is possible | |
1522 | * @page: page struct to check | |
1523 | */ | |
1524 | static inline bool i40e_page_is_reserved(struct page *page) | |
1525 | { | |
1526 | return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); | |
1527 | } | |
1528 | ||
1529 | /** | |
1530 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1531 | * @rx_ring: rx descriptor ring to transact packets on | |
1532 | * @rx_buffer: buffer containing page to add | |
1533 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1534 | * @skb: sk_buff to place the data into | |
1535 | * | |
1536 | * This function will add the data contained in rx_buffer->page to the skb. | |
1537 | * This is done either through a direct copy if the data in the buffer is | |
1538 | * less than the skb header size, otherwise it will just attach the page as | |
1539 | * a frag to the skb. | |
1540 | * | |
1541 | * The function will then update the page offset if necessary and return | |
1542 | * true if the buffer can be reused by the adapter. | |
1543 | **/ | |
1544 | static bool i40e_add_rx_frag(struct i40e_ring *rx_ring, | |
1545 | struct i40e_rx_buffer *rx_buffer, | |
1546 | union i40e_rx_desc *rx_desc, | |
1547 | struct sk_buff *skb) | |
1548 | { | |
1549 | struct page *page = rx_buffer->page; | |
1550 | u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1551 | unsigned int size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> | |
1552 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1553 | #if (PAGE_SIZE < 8192) | |
1554 | unsigned int truesize = I40E_RXBUFFER_2048; | |
1555 | #else | |
1556 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
1557 | unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048; | |
1558 | #endif | |
1559 | ||
1560 | /* will the data fit in the skb we allocated? if so, just | |
1561 | * copy it as it is pretty small anyway | |
1562 | */ | |
1563 | if ((size <= I40E_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { | |
1564 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
1565 | ||
1566 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); | |
1567 | ||
1568 | /* page is not reserved, we can reuse buffer as-is */ | |
1569 | if (likely(!i40e_page_is_reserved(page))) | |
1570 | return true; | |
1571 | ||
1572 | /* this page cannot be reused so discard it */ | |
1573 | __free_pages(page, 0); | |
1574 | return false; | |
1575 | } | |
1576 | ||
1577 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, | |
1578 | rx_buffer->page_offset, size, truesize); | |
1579 | ||
1580 | /* avoid re-using remote pages */ | |
1581 | if (unlikely(i40e_page_is_reserved(page))) | |
1582 | return false; | |
1583 | ||
1584 | #if (PAGE_SIZE < 8192) | |
1585 | /* if we are only owner of page we can reuse it */ | |
1586 | if (unlikely(page_count(page) != 1)) | |
1587 | return false; | |
1588 | ||
1589 | /* flip page offset to other buffer */ | |
1590 | rx_buffer->page_offset ^= truesize; | |
1591 | #else | |
1592 | /* move offset up to the next cache line */ | |
1593 | rx_buffer->page_offset += truesize; | |
1594 | ||
1595 | if (rx_buffer->page_offset > last_offset) | |
1596 | return false; | |
1597 | #endif | |
1598 | ||
1599 | /* Even if we own the page, we are not allowed to use atomic_set() | |
1600 | * This would break get_page_unless_zero() users. | |
1601 | */ | |
1602 | get_page(rx_buffer->page); | |
1603 | ||
1604 | return true; | |
1605 | } | |
1606 | ||
1607 | /** | |
1608 | * i40e_fetch_rx_buffer - Allocate skb and populate it | |
1609 | * @rx_ring: rx descriptor ring to transact packets on | |
1610 | * @rx_desc: descriptor containing info written by hardware | |
a132af24 | 1611 | * |
1a557afc JB |
1612 | * This function allocates an skb on the fly, and populates it with the page |
1613 | * data from the current receive descriptor, taking care to set up the skb | |
1614 | * correctly, as well as handling calling the page recycle function if | |
1615 | * necessary. | |
1616 | */ | |
1617 | static inline | |
1618 | struct sk_buff *i40e_fetch_rx_buffer(struct i40e_ring *rx_ring, | |
1619 | union i40e_rx_desc *rx_desc) | |
1620 | { | |
1621 | struct i40e_rx_buffer *rx_buffer; | |
1622 | struct sk_buff *skb; | |
1623 | struct page *page; | |
1624 | ||
1625 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1626 | page = rx_buffer->page; | |
1627 | prefetchw(page); | |
1628 | ||
1629 | skb = rx_buffer->skb; | |
1630 | ||
1631 | if (likely(!skb)) { | |
1632 | void *page_addr = page_address(page) + rx_buffer->page_offset; | |
1633 | ||
1634 | /* prefetch first cache line of first page */ | |
1635 | prefetch(page_addr); | |
1636 | #if L1_CACHE_BYTES < 128 | |
1637 | prefetch(page_addr + L1_CACHE_BYTES); | |
1638 | #endif | |
1639 | ||
1640 | /* allocate a skb to store the frags */ | |
1641 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
1642 | I40E_RX_HDR_SIZE, | |
1643 | GFP_ATOMIC | __GFP_NOWARN); | |
1644 | if (unlikely(!skb)) { | |
1645 | rx_ring->rx_stats.alloc_buff_failed++; | |
1646 | return NULL; | |
1647 | } | |
1648 | ||
1649 | /* we will be copying header into skb->data in | |
1650 | * pskb_may_pull so it is in our interest to prefetch | |
1651 | * it now to avoid a possible cache miss | |
1652 | */ | |
1653 | prefetchw(skb->data); | |
1654 | } else { | |
1655 | rx_buffer->skb = NULL; | |
1656 | } | |
1657 | ||
1658 | /* we are reusing so sync this buffer for CPU use */ | |
1659 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1660 | rx_buffer->dma, | |
1661 | rx_buffer->page_offset, | |
1662 | I40E_RXBUFFER_2048, | |
1663 | DMA_FROM_DEVICE); | |
1664 | ||
1665 | /* pull page into skb */ | |
1666 | if (i40e_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
1667 | /* hand second half of page back to the ring */ | |
1668 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1669 | rx_ring->rx_stats.page_reuse_count++; | |
1670 | } else { | |
1671 | /* we are not reusing the buffer so unmap it */ | |
1672 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, PAGE_SIZE, | |
1673 | DMA_FROM_DEVICE); | |
1674 | } | |
1675 | ||
1676 | /* clear contents of buffer_info */ | |
1677 | rx_buffer->page = NULL; | |
1678 | ||
1679 | return skb; | |
1680 | } | |
1681 | ||
1682 | /** | |
1683 | * i40e_is_non_eop - process handling of non-EOP buffers | |
1684 | * @rx_ring: Rx ring being processed | |
1685 | * @rx_desc: Rx descriptor for current buffer | |
1686 | * @skb: Current socket buffer containing buffer in progress | |
1687 | * | |
1688 | * This function updates next to clean. If the buffer is an EOP buffer | |
1689 | * this function exits returning false, otherwise it will place the | |
1690 | * sk_buff in the next buffer to be chained and return true indicating | |
1691 | * that this is in fact a non-EOP buffer. | |
a132af24 | 1692 | **/ |
1a557afc JB |
1693 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, |
1694 | union i40e_rx_desc *rx_desc, | |
1695 | struct sk_buff *skb) | |
1696 | { | |
1697 | u32 ntc = rx_ring->next_to_clean + 1; | |
1698 | ||
1699 | /* fetch, update, and store next to clean */ | |
1700 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1701 | rx_ring->next_to_clean = ntc; | |
1702 | ||
1703 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1704 | ||
1705 | #define staterrlen rx_desc->wb.qword1.status_error_len | |
1706 | if (unlikely(i40e_rx_is_programming_status(le64_to_cpu(staterrlen)))) { | |
1707 | i40e_clean_programming_status(rx_ring, rx_desc); | |
1708 | rx_ring->rx_bi[ntc].skb = skb; | |
1709 | return true; | |
1710 | } | |
1711 | /* if we are the last buffer then there is nothing else to do */ | |
1712 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
1713 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
1714 | return false; | |
1715 | ||
1716 | /* place skb in next buffer to be received */ | |
1717 | rx_ring->rx_bi[ntc].skb = skb; | |
1718 | rx_ring->rx_stats.non_eop_descs++; | |
1719 | ||
1720 | return true; | |
1721 | } | |
1722 | ||
1723 | /** | |
1724 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1725 | * @rx_ring: rx descriptor ring to transact packets on | |
1726 | * @budget: Total limit on number of packets to process | |
1727 | * | |
1728 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1729 | * processing. The advantage to this is that on systems that have | |
1730 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1731 | * it by maintaining the mapping of the page to the system. | |
1732 | * | |
1733 | * Returns amount of work completed | |
1734 | **/ | |
1735 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) | |
a132af24 MW |
1736 | { |
1737 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
1738 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); | |
c2e245ab | 1739 | bool failure = false; |
a132af24 | 1740 | |
1a557afc JB |
1741 | while (likely(total_rx_packets < budget)) { |
1742 | union i40e_rx_desc *rx_desc; | |
a132af24 | 1743 | struct sk_buff *skb; |
1a557afc | 1744 | u32 rx_status; |
a132af24 | 1745 | u16 vlan_tag; |
1a557afc JB |
1746 | u8 rx_ptype; |
1747 | u64 qword; | |
1748 | ||
fd0a05ce JB |
1749 | /* return some buffers to hardware, one at a time is too slow */ |
1750 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 1751 | failure = failure || |
1a557afc | 1752 | i40e_alloc_rx_buffers(rx_ring, cleaned_count); |
fd0a05ce JB |
1753 | cleaned_count = 0; |
1754 | } | |
1755 | ||
1a557afc JB |
1756 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
1757 | ||
fd0a05ce | 1758 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1a557afc JB |
1759 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> |
1760 | I40E_RXD_QW1_PTYPE_SHIFT; | |
829af3ac | 1761 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> |
1a557afc | 1762 | I40E_RXD_QW1_STATUS_SHIFT; |
a132af24 | 1763 | |
41a1d04b | 1764 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) |
a132af24 MW |
1765 | break; |
1766 | ||
1a557afc JB |
1767 | /* status_error_len will always be zero for unused descriptors |
1768 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
1769 | * which is always zero because packet split isn't used, if the | |
1770 | * hardware wrote DD then it will be non-zero | |
1771 | */ | |
1772 | if (!rx_desc->wb.qword1.status_error_len) | |
1773 | break; | |
1774 | ||
a132af24 MW |
1775 | /* This memory barrier is needed to keep us from reading |
1776 | * any other fields out of the rx_desc until we know the | |
1777 | * DD bit is set. | |
1778 | */ | |
67317166 | 1779 | dma_rmb(); |
a132af24 | 1780 | |
1a557afc JB |
1781 | skb = i40e_fetch_rx_buffer(rx_ring, rx_desc); |
1782 | if (!skb) | |
1783 | break; | |
a132af24 | 1784 | |
a132af24 MW |
1785 | cleaned_count++; |
1786 | ||
1a557afc | 1787 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 1788 | continue; |
a132af24 | 1789 | |
1a557afc JB |
1790 | /* ERR_MASK will only have valid bits if EOP set, and |
1791 | * what we are doing here is actually checking | |
1792 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
1793 | * the error field | |
1794 | */ | |
1795 | if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
a132af24 | 1796 | dev_kfree_skb_any(skb); |
a132af24 MW |
1797 | continue; |
1798 | } | |
1799 | ||
1a557afc JB |
1800 | if (i40e_cleanup_headers(rx_ring, skb)) |
1801 | continue; | |
a132af24 MW |
1802 | |
1803 | /* probably a little skewed due to removing CRC */ | |
1804 | total_rx_bytes += skb->len; | |
a132af24 | 1805 | |
1a557afc JB |
1806 | /* populate checksum, VLAN, and protocol */ |
1807 | i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); | |
a132af24 | 1808 | |
a132af24 | 1809 | #ifdef I40E_FCOE |
1f15d667 JB |
1810 | if (unlikely( |
1811 | i40e_rx_is_fcoe(rx_ptype) && | |
1812 | !i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) { | |
a132af24 MW |
1813 | dev_kfree_skb_any(skb); |
1814 | continue; | |
1815 | } | |
1816 | #endif | |
1a557afc JB |
1817 | |
1818 | vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? | |
1819 | le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; | |
1820 | ||
a132af24 MW |
1821 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
1822 | ||
1a557afc JB |
1823 | /* update budget accounting */ |
1824 | total_rx_packets++; | |
1825 | } | |
fd0a05ce | 1826 | |
980e9b11 | 1827 | u64_stats_update_begin(&rx_ring->syncp); |
a114d0a6 AD |
1828 | rx_ring->stats.packets += total_rx_packets; |
1829 | rx_ring->stats.bytes += total_rx_bytes; | |
980e9b11 | 1830 | u64_stats_update_end(&rx_ring->syncp); |
fd0a05ce JB |
1831 | rx_ring->q_vector->rx.total_packets += total_rx_packets; |
1832 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1833 | ||
1a557afc | 1834 | /* guarantee a trip back through this routine if there was a failure */ |
c2e245ab | 1835 | return failure ? budget : total_rx_packets; |
fd0a05ce JB |
1836 | } |
1837 | ||
8f5e39ce JB |
1838 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
1839 | { | |
1840 | u32 val; | |
1841 | ||
1842 | val = I40E_PFINT_DYN_CTLN_INTENA_MASK | | |
40d72a50 JB |
1843 | /* Don't clear PBA because that can cause lost interrupts that |
1844 | * came in while we were cleaning/polling | |
1845 | */ | |
8f5e39ce JB |
1846 | (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | |
1847 | (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); | |
1848 | ||
1849 | return val; | |
1850 | } | |
1851 | ||
1852 | /* a small macro to shorten up some long lines */ | |
1853 | #define INTREG I40E_PFINT_DYN_CTLN | |
65e87c03 JK |
1854 | static inline int get_rx_itr_enabled(struct i40e_vsi *vsi, int idx) |
1855 | { | |
1856 | return !!(vsi->rx_rings[idx]->rx_itr_setting); | |
1857 | } | |
1858 | ||
1859 | static inline int get_tx_itr_enabled(struct i40e_vsi *vsi, int idx) | |
1860 | { | |
1861 | return !!(vsi->tx_rings[idx]->tx_itr_setting); | |
1862 | } | |
8f5e39ce | 1863 | |
de32e3ef CW |
1864 | /** |
1865 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
1866 | * @vsi: the VSI we care about | |
1867 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
1868 | * | |
1869 | **/ | |
1870 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
1871 | struct i40e_q_vector *q_vector) | |
1872 | { | |
1873 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
1874 | bool rx = false, tx = false; |
1875 | u32 rxval, txval; | |
de32e3ef | 1876 | int vector; |
a75e8005 | 1877 | int idx = q_vector->v_idx; |
65e87c03 | 1878 | int rx_itr_setting, tx_itr_setting; |
de32e3ef CW |
1879 | |
1880 | vector = (q_vector->v_idx + vsi->base_vector); | |
8f5e39ce | 1881 | |
ee2319cf JB |
1882 | /* avoid dynamic calculation if in countdown mode OR if |
1883 | * all dynamic is disabled | |
1884 | */ | |
8f5e39ce JB |
1885 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
1886 | ||
65e87c03 JK |
1887 | rx_itr_setting = get_rx_itr_enabled(vsi, idx); |
1888 | tx_itr_setting = get_tx_itr_enabled(vsi, idx); | |
1889 | ||
ee2319cf | 1890 | if (q_vector->itr_countdown > 0 || |
65e87c03 JK |
1891 | (!ITR_IS_DYNAMIC(rx_itr_setting) && |
1892 | !ITR_IS_DYNAMIC(tx_itr_setting))) { | |
ee2319cf JB |
1893 | goto enable_int; |
1894 | } | |
1895 | ||
65e87c03 | 1896 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
1897 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
1898 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 1899 | } |
8f5e39ce | 1900 | |
65e87c03 | 1901 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
1902 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
1903 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
de32e3ef | 1904 | } |
8f5e39ce JB |
1905 | |
1906 | if (rx || tx) { | |
1907 | /* get the higher of the two ITR adjustments and | |
1908 | * use the same value for both ITR registers | |
1909 | * when in adaptive mode (Rx and/or Tx) | |
1910 | */ | |
1911 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
1912 | ||
1913 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
1914 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
1915 | tx = true; | |
1916 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
1917 | rx = true; | |
1918 | } | |
1919 | ||
1920 | /* only need to enable the interrupt once, but need | |
1921 | * to possibly update both ITR values | |
1922 | */ | |
1923 | if (rx) { | |
1924 | /* set the INTENA_MSK_MASK so that this first write | |
1925 | * won't actually enable the interrupt, instead just | |
1926 | * updating the ITR (it's bit 31 PF and VF) | |
1927 | */ | |
1928 | rxval |= BIT(31); | |
1929 | /* don't check _DOWN because interrupt isn't being enabled */ | |
1930 | wr32(hw, INTREG(vector - 1), rxval); | |
1931 | } | |
1932 | ||
ee2319cf | 1933 | enable_int: |
8f5e39ce JB |
1934 | if (!test_bit(__I40E_DOWN, &vsi->state)) |
1935 | wr32(hw, INTREG(vector - 1), txval); | |
ee2319cf JB |
1936 | |
1937 | if (q_vector->itr_countdown) | |
1938 | q_vector->itr_countdown--; | |
1939 | else | |
1940 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
1941 | } |
1942 | ||
fd0a05ce JB |
1943 | /** |
1944 | * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1945 | * @napi: napi struct with our devices info in it | |
1946 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1947 | * | |
1948 | * This function will clean all queues associated with a q_vector. | |
1949 | * | |
1950 | * Returns the amount of work done | |
1951 | **/ | |
1952 | int i40e_napi_poll(struct napi_struct *napi, int budget) | |
1953 | { | |
1954 | struct i40e_q_vector *q_vector = | |
1955 | container_of(napi, struct i40e_q_vector, napi); | |
1956 | struct i40e_vsi *vsi = q_vector->vsi; | |
cd0b6fa6 | 1957 | struct i40e_ring *ring; |
fd0a05ce | 1958 | bool clean_complete = true; |
d91649f5 | 1959 | bool arm_wb = false; |
fd0a05ce | 1960 | int budget_per_ring; |
32b3e08f | 1961 | int work_done = 0; |
fd0a05ce JB |
1962 | |
1963 | if (test_bit(__I40E_DOWN, &vsi->state)) { | |
1964 | napi_complete(napi); | |
1965 | return 0; | |
1966 | } | |
1967 | ||
9c6c1259 KP |
1968 | /* Clear hung_detected bit */ |
1969 | clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected); | |
cd0b6fa6 AD |
1970 | /* Since the actual Tx work is minimal, we can give the Tx a larger |
1971 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1972 | */ | |
d91649f5 | 1973 | i40e_for_each_ring(ring, q_vector->tx) { |
a619afe8 | 1974 | if (!i40e_clean_tx_irq(vsi, ring, budget)) { |
f2edaaaa AD |
1975 | clean_complete = false; |
1976 | continue; | |
1977 | } | |
1978 | arm_wb |= ring->arm_wb; | |
0deda868 | 1979 | ring->arm_wb = false; |
d91649f5 | 1980 | } |
cd0b6fa6 | 1981 | |
c67caceb AD |
1982 | /* Handle case where we are called by netpoll with a budget of 0 */ |
1983 | if (budget <= 0) | |
1984 | goto tx_only; | |
1985 | ||
fd0a05ce JB |
1986 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
1987 | * allow the budget to go below 1 because that would exit polling early. | |
fd0a05ce JB |
1988 | */ |
1989 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
cd0b6fa6 | 1990 | |
a132af24 | 1991 | i40e_for_each_ring(ring, q_vector->rx) { |
1a557afc | 1992 | int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); |
32b3e08f JB |
1993 | |
1994 | work_done += cleaned; | |
f2edaaaa AD |
1995 | /* if we clean as many as budgeted, we must not be done */ |
1996 | if (cleaned >= budget_per_ring) | |
1997 | clean_complete = false; | |
a132af24 | 1998 | } |
fd0a05ce JB |
1999 | |
2000 | /* If work not completed, return budget and polling will return */ | |
d91649f5 | 2001 | if (!clean_complete) { |
c67caceb | 2002 | tx_only: |
164c9f54 ASJ |
2003 | if (arm_wb) { |
2004 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
ecc6a239 | 2005 | i40e_enable_wb_on_itr(vsi, q_vector); |
164c9f54 | 2006 | } |
fd0a05ce | 2007 | return budget; |
d91649f5 | 2008 | } |
fd0a05ce | 2009 | |
8e0764b4 ASJ |
2010 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
2011 | q_vector->arm_wb_state = false; | |
2012 | ||
fd0a05ce | 2013 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 2014 | napi_complete_done(napi, work_done); |
de32e3ef CW |
2015 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { |
2016 | i40e_update_enable_itr(vsi, q_vector); | |
2017 | } else { /* Legacy mode */ | |
40d72a50 | 2018 | i40e_irq_dynamic_enable_icr0(vsi->back, false); |
fd0a05ce | 2019 | } |
fd0a05ce JB |
2020 | return 0; |
2021 | } | |
2022 | ||
2023 | /** | |
2024 | * i40e_atr - Add a Flow Director ATR filter | |
2025 | * @tx_ring: ring to add programming descriptor to | |
2026 | * @skb: send buffer | |
89232c3b | 2027 | * @tx_flags: send tx flags |
fd0a05ce JB |
2028 | **/ |
2029 | static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
6b037cd4 | 2030 | u32 tx_flags) |
fd0a05ce JB |
2031 | { |
2032 | struct i40e_filter_program_desc *fdir_desc; | |
2033 | struct i40e_pf *pf = tx_ring->vsi->back; | |
2034 | union { | |
2035 | unsigned char *network; | |
2036 | struct iphdr *ipv4; | |
2037 | struct ipv6hdr *ipv6; | |
2038 | } hdr; | |
2039 | struct tcphdr *th; | |
2040 | unsigned int hlen; | |
2041 | u32 flex_ptype, dtype_cmd; | |
ffcc55c0 | 2042 | int l4_proto; |
fc4ac67b | 2043 | u16 i; |
fd0a05ce JB |
2044 | |
2045 | /* make sure ATR is enabled */ | |
60ea5f83 | 2046 | if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) |
fd0a05ce JB |
2047 | return; |
2048 | ||
04294e38 ASJ |
2049 | if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) |
2050 | return; | |
2051 | ||
fd0a05ce JB |
2052 | /* if sampling is disabled do nothing */ |
2053 | if (!tx_ring->atr_sample_rate) | |
2054 | return; | |
2055 | ||
6b037cd4 | 2056 | /* Currently only IPv4/IPv6 with TCP is supported */ |
89232c3b ASJ |
2057 | if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) |
2058 | return; | |
fd0a05ce | 2059 | |
ffcc55c0 AD |
2060 | /* snag network header to get L4 type and address */ |
2061 | hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? | |
2062 | skb_inner_network_header(skb) : skb_network_header(skb); | |
fd0a05ce | 2063 | |
ffcc55c0 AD |
2064 | /* Note: tx_flags gets modified to reflect inner protocols in |
2065 | * tx_enable_csum function if encap is enabled. | |
2066 | */ | |
2067 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
6b037cd4 | 2068 | /* access ihl as u8 to avoid unaligned access on ia64 */ |
ffcc55c0 AD |
2069 | hlen = (hdr.network[0] & 0x0F) << 2; |
2070 | l4_proto = hdr.ipv4->protocol; | |
fd0a05ce | 2071 | } else { |
ffcc55c0 AD |
2072 | hlen = hdr.network - skb->data; |
2073 | l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); | |
2074 | hlen -= hdr.network - skb->data; | |
fd0a05ce JB |
2075 | } |
2076 | ||
6b037cd4 | 2077 | if (l4_proto != IPPROTO_TCP) |
89232c3b ASJ |
2078 | return; |
2079 | ||
fd0a05ce JB |
2080 | th = (struct tcphdr *)(hdr.network + hlen); |
2081 | ||
55a5e60b ASJ |
2082 | /* Due to lack of space, no more new filters can be programmed */ |
2083 | if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) | |
2084 | return; | |
72b74869 ASJ |
2085 | if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && |
2086 | (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) { | |
52eb95ef ASJ |
2087 | /* HW ATR eviction will take care of removing filters on FIN |
2088 | * and RST packets. | |
2089 | */ | |
2090 | if (th->fin || th->rst) | |
2091 | return; | |
2092 | } | |
55a5e60b ASJ |
2093 | |
2094 | tx_ring->atr_count++; | |
2095 | ||
ce806783 ASJ |
2096 | /* sample on all syn/fin/rst packets or once every atr sample rate */ |
2097 | if (!th->fin && | |
2098 | !th->syn && | |
2099 | !th->rst && | |
2100 | (tx_ring->atr_count < tx_ring->atr_sample_rate)) | |
fd0a05ce JB |
2101 | return; |
2102 | ||
2103 | tx_ring->atr_count = 0; | |
2104 | ||
2105 | /* grab the next descriptor */ | |
fc4ac67b AD |
2106 | i = tx_ring->next_to_use; |
2107 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
2108 | ||
2109 | i++; | |
2110 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2111 | |
2112 | flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & | |
2113 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
6b037cd4 | 2114 | flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? |
fd0a05ce JB |
2115 | (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << |
2116 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : | |
2117 | (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << | |
2118 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
2119 | ||
2120 | flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
2121 | ||
2122 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
2123 | ||
ce806783 | 2124 | dtype_cmd |= (th->fin || th->rst) ? |
fd0a05ce JB |
2125 | (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
2126 | I40E_TXD_FLTR_QW1_PCMD_SHIFT) : | |
2127 | (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
2128 | I40E_TXD_FLTR_QW1_PCMD_SHIFT); | |
2129 | ||
2130 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << | |
2131 | I40E_TXD_FLTR_QW1_DEST_SHIFT; | |
2132 | ||
2133 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << | |
2134 | I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; | |
2135 | ||
433c47de | 2136 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
6a899024 | 2137 | if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) |
60ccd45c ASJ |
2138 | dtype_cmd |= |
2139 | ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << | |
2140 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2141 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
2142 | else | |
2143 | dtype_cmd |= | |
2144 | ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << | |
2145 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2146 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
433c47de | 2147 | |
72b74869 ASJ |
2148 | if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && |
2149 | (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) | |
52eb95ef ASJ |
2150 | dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; |
2151 | ||
fd0a05ce | 2152 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); |
99753ea6 | 2153 | fdir_desc->rsvd = cpu_to_le32(0); |
fd0a05ce | 2154 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); |
99753ea6 | 2155 | fdir_desc->fd_id = cpu_to_le32(0); |
fd0a05ce JB |
2156 | } |
2157 | ||
fd0a05ce JB |
2158 | /** |
2159 | * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW | |
2160 | * @skb: send buffer | |
2161 | * @tx_ring: ring to send buffer on | |
2162 | * @flags: the tx flags to be set | |
2163 | * | |
2164 | * Checks the skb and set up correspondingly several generic transmit flags | |
2165 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
2166 | * | |
2167 | * Returns error code indicate the frame should be dropped upon error and the | |
2168 | * otherwise returns 0 to indicate the flags has been set properly. | |
2169 | **/ | |
38e00438 | 2170 | #ifdef I40E_FCOE |
3e587cf3 | 2171 | inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, |
fd0a05ce JB |
2172 | struct i40e_ring *tx_ring, |
2173 | u32 *flags) | |
3e587cf3 JB |
2174 | #else |
2175 | static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, | |
2176 | struct i40e_ring *tx_ring, | |
2177 | u32 *flags) | |
38e00438 | 2178 | #endif |
fd0a05ce JB |
2179 | { |
2180 | __be16 protocol = skb->protocol; | |
2181 | u32 tx_flags = 0; | |
2182 | ||
31eaaccf GR |
2183 | if (protocol == htons(ETH_P_8021Q) && |
2184 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
2185 | /* When HW VLAN acceleration is turned off by the user the | |
2186 | * stack sets the protocol to 8021q so that the driver | |
2187 | * can take any steps required to support the SW only | |
2188 | * VLAN handling. In our case the driver doesn't need | |
2189 | * to take any further steps so just set the protocol | |
2190 | * to the encapsulated ethertype. | |
2191 | */ | |
2192 | skb->protocol = vlan_get_protocol(skb); | |
2193 | goto out; | |
2194 | } | |
2195 | ||
fd0a05ce | 2196 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
2197 | if (skb_vlan_tag_present(skb)) { |
2198 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
fd0a05ce JB |
2199 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
2200 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
0e2fe46c | 2201 | } else if (protocol == htons(ETH_P_8021Q)) { |
fd0a05ce | 2202 | struct vlan_hdr *vhdr, _vhdr; |
6995b36c | 2203 | |
fd0a05ce JB |
2204 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
2205 | if (!vhdr) | |
2206 | return -EINVAL; | |
2207 | ||
2208 | protocol = vhdr->h_vlan_encapsulated_proto; | |
2209 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
2210 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
2211 | } | |
2212 | ||
d40d00b1 NP |
2213 | if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) |
2214 | goto out; | |
2215 | ||
fd0a05ce | 2216 | /* Insert 802.1p priority into VLAN header */ |
38e00438 VD |
2217 | if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || |
2218 | (skb->priority != TC_PRIO_CONTROL)) { | |
fd0a05ce JB |
2219 | tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; |
2220 | tx_flags |= (skb->priority & 0x7) << | |
2221 | I40E_TX_FLAGS_VLAN_PRIO_SHIFT; | |
2222 | if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { | |
2223 | struct vlan_ethhdr *vhdr; | |
dd225bc6 FR |
2224 | int rc; |
2225 | ||
2226 | rc = skb_cow_head(skb, 0); | |
2227 | if (rc < 0) | |
2228 | return rc; | |
fd0a05ce JB |
2229 | vhdr = (struct vlan_ethhdr *)skb->data; |
2230 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
2231 | I40E_TX_FLAGS_VLAN_SHIFT); | |
2232 | } else { | |
2233 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; | |
2234 | } | |
2235 | } | |
d40d00b1 NP |
2236 | |
2237 | out: | |
fd0a05ce JB |
2238 | *flags = tx_flags; |
2239 | return 0; | |
2240 | } | |
2241 | ||
fd0a05ce JB |
2242 | /** |
2243 | * i40e_tso - set up the tso context descriptor | |
fd0a05ce | 2244 | * @skb: ptr to the skb we're sending |
fd0a05ce | 2245 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 2246 | * @cd_type_cmd_tso_mss: Quad Word 1 |
fd0a05ce JB |
2247 | * |
2248 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
2249 | **/ | |
84b07992 | 2250 | static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss) |
fd0a05ce | 2251 | { |
03f9d6a5 | 2252 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
2253 | union { |
2254 | struct iphdr *v4; | |
2255 | struct ipv6hdr *v6; | |
2256 | unsigned char *hdr; | |
2257 | } ip; | |
c49a7bc3 AD |
2258 | union { |
2259 | struct tcphdr *tcp; | |
5453205c | 2260 | struct udphdr *udp; |
c49a7bc3 AD |
2261 | unsigned char *hdr; |
2262 | } l4; | |
2263 | u32 paylen, l4_offset; | |
fd0a05ce | 2264 | int err; |
fd0a05ce | 2265 | |
e9f6563d SN |
2266 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2267 | return 0; | |
2268 | ||
fd0a05ce JB |
2269 | if (!skb_is_gso(skb)) |
2270 | return 0; | |
2271 | ||
dd225bc6 FR |
2272 | err = skb_cow_head(skb, 0); |
2273 | if (err < 0) | |
2274 | return err; | |
fd0a05ce | 2275 | |
c777019a AD |
2276 | ip.hdr = skb_network_header(skb); |
2277 | l4.hdr = skb_transport_header(skb); | |
df23075f | 2278 | |
c777019a AD |
2279 | /* initialize outer IP header fields */ |
2280 | if (ip.v4->version == 4) { | |
2281 | ip.v4->tot_len = 0; | |
2282 | ip.v4->check = 0; | |
c49a7bc3 | 2283 | } else { |
c777019a AD |
2284 | ip.v6->payload_len = 0; |
2285 | } | |
2286 | ||
577389a5 | 2287 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 2288 | SKB_GSO_GRE_CSUM | |
7e13318d | 2289 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 2290 | SKB_GSO_IPXIP6 | |
577389a5 | 2291 | SKB_GSO_UDP_TUNNEL | |
5453205c | 2292 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
2293 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
2294 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
2295 | l4.udp->len = 0; | |
2296 | ||
5453205c AD |
2297 | /* determine offset of outer transport header */ |
2298 | l4_offset = l4.hdr - skb->data; | |
2299 | ||
2300 | /* remove payload length from outer checksum */ | |
24d41e5e AD |
2301 | paylen = skb->len - l4_offset; |
2302 | csum_replace_by_diff(&l4.udp->check, htonl(paylen)); | |
5453205c AD |
2303 | } |
2304 | ||
c777019a AD |
2305 | /* reset pointers to inner headers */ |
2306 | ip.hdr = skb_inner_network_header(skb); | |
2307 | l4.hdr = skb_inner_transport_header(skb); | |
2308 | ||
2309 | /* initialize inner IP header fields */ | |
2310 | if (ip.v4->version == 4) { | |
2311 | ip.v4->tot_len = 0; | |
2312 | ip.v4->check = 0; | |
2313 | } else { | |
2314 | ip.v6->payload_len = 0; | |
2315 | } | |
fd0a05ce JB |
2316 | } |
2317 | ||
c49a7bc3 AD |
2318 | /* determine offset of inner transport header */ |
2319 | l4_offset = l4.hdr - skb->data; | |
2320 | ||
2321 | /* remove payload length from inner checksum */ | |
24d41e5e AD |
2322 | paylen = skb->len - l4_offset; |
2323 | csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); | |
c49a7bc3 AD |
2324 | |
2325 | /* compute length of segmentation header */ | |
2326 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
fd0a05ce JB |
2327 | |
2328 | /* find the field values */ | |
2329 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
2330 | cd_tso_len = skb->len - *hdr_len; | |
2331 | cd_mss = skb_shinfo(skb)->gso_size; | |
03f9d6a5 AD |
2332 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
2333 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
2334 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
fd0a05ce JB |
2335 | return 1; |
2336 | } | |
2337 | ||
beb0dff1 JK |
2338 | /** |
2339 | * i40e_tsyn - set up the tsyn context descriptor | |
2340 | * @tx_ring: ptr to the ring to send | |
2341 | * @skb: ptr to the skb we're sending | |
2342 | * @tx_flags: the collected send information | |
9c883bd3 | 2343 | * @cd_type_cmd_tso_mss: Quad Word 1 |
beb0dff1 JK |
2344 | * |
2345 | * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen | |
2346 | **/ | |
2347 | static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2348 | u32 tx_flags, u64 *cd_type_cmd_tso_mss) | |
2349 | { | |
2350 | struct i40e_pf *pf; | |
2351 | ||
2352 | if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) | |
2353 | return 0; | |
2354 | ||
2355 | /* Tx timestamps cannot be sampled when doing TSO */ | |
2356 | if (tx_flags & I40E_TX_FLAGS_TSO) | |
2357 | return 0; | |
2358 | ||
2359 | /* only timestamp the outbound packet if the user has requested it and | |
2360 | * we are not already transmitting a packet to be timestamped | |
2361 | */ | |
2362 | pf = i40e_netdev_to_pf(tx_ring->netdev); | |
22b4777d JK |
2363 | if (!(pf->flags & I40E_FLAG_PTP)) |
2364 | return 0; | |
2365 | ||
9ce34f02 JK |
2366 | if (pf->ptp_tx && |
2367 | !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { | |
beb0dff1 JK |
2368 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
2369 | pf->ptp_tx_skb = skb_get(skb); | |
2370 | } else { | |
2371 | return 0; | |
2372 | } | |
2373 | ||
2374 | *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << | |
2375 | I40E_TXD_CTX_QW1_CMD_SHIFT; | |
2376 | ||
beb0dff1 JK |
2377 | return 1; |
2378 | } | |
2379 | ||
fd0a05ce JB |
2380 | /** |
2381 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
2382 | * @skb: send buffer | |
89232c3b | 2383 | * @tx_flags: pointer to Tx flags currently set |
fd0a05ce JB |
2384 | * @td_cmd: Tx descriptor command bits to set |
2385 | * @td_offset: Tx descriptor header offsets to set | |
554f4544 | 2386 | * @tx_ring: Tx descriptor ring |
fd0a05ce JB |
2387 | * @cd_tunneling: ptr to context desc bits |
2388 | **/ | |
529f1f65 AD |
2389 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
2390 | u32 *td_cmd, u32 *td_offset, | |
2391 | struct i40e_ring *tx_ring, | |
2392 | u32 *cd_tunneling) | |
fd0a05ce | 2393 | { |
b96b78f2 AD |
2394 | union { |
2395 | struct iphdr *v4; | |
2396 | struct ipv6hdr *v6; | |
2397 | unsigned char *hdr; | |
2398 | } ip; | |
2399 | union { | |
2400 | struct tcphdr *tcp; | |
2401 | struct udphdr *udp; | |
2402 | unsigned char *hdr; | |
2403 | } l4; | |
a3fd9d88 | 2404 | unsigned char *exthdr; |
d1bd743b | 2405 | u32 offset, cmd = 0; |
a3fd9d88 | 2406 | __be16 frag_off; |
b96b78f2 AD |
2407 | u8 l4_proto = 0; |
2408 | ||
529f1f65 AD |
2409 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2410 | return 0; | |
2411 | ||
b96b78f2 AD |
2412 | ip.hdr = skb_network_header(skb); |
2413 | l4.hdr = skb_transport_header(skb); | |
fd0a05ce | 2414 | |
475b4205 AD |
2415 | /* compute outer L2 header size */ |
2416 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
2417 | ||
fd0a05ce | 2418 | if (skb->encapsulation) { |
d1bd743b | 2419 | u32 tunnel = 0; |
a0064728 AD |
2420 | /* define outer network header type */ |
2421 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
2422 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2423 | I40E_TX_CTX_EXT_IP_IPV4 : | |
2424 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
2425 | ||
a0064728 AD |
2426 | l4_proto = ip.v4->protocol; |
2427 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 2428 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
2429 | |
2430 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 2431 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
2432 | if (l4.hdr != exthdr) |
2433 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2434 | &l4_proto, &frag_off); | |
a0064728 AD |
2435 | } |
2436 | ||
2437 | /* define outer transport */ | |
2438 | switch (l4_proto) { | |
45991204 | 2439 | case IPPROTO_UDP: |
475b4205 | 2440 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
6a899024 | 2441 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
45991204 | 2442 | break; |
c1d1791d | 2443 | case IPPROTO_GRE: |
475b4205 | 2444 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 | 2445 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
c1d1791d | 2446 | break; |
577389a5 AD |
2447 | case IPPROTO_IPIP: |
2448 | case IPPROTO_IPV6: | |
2449 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; | |
2450 | l4.hdr = skb_inner_network_header(skb); | |
2451 | break; | |
45991204 | 2452 | default: |
529f1f65 AD |
2453 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2454 | return -1; | |
2455 | ||
2456 | skb_checksum_help(skb); | |
2457 | return 0; | |
45991204 | 2458 | } |
b96b78f2 | 2459 | |
577389a5 AD |
2460 | /* compute outer L3 header size */ |
2461 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
2462 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
2463 | ||
2464 | /* switch IP header pointer from outer to inner header */ | |
2465 | ip.hdr = skb_inner_network_header(skb); | |
2466 | ||
475b4205 AD |
2467 | /* compute tunnel header size */ |
2468 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
2469 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
2470 | ||
5453205c AD |
2471 | /* indicate if we need to offload outer UDP header */ |
2472 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 2473 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
2474 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
2475 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
2476 | ||
475b4205 AD |
2477 | /* record tunnel offload values */ |
2478 | *cd_tunneling |= tunnel; | |
2479 | ||
b96b78f2 | 2480 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 2481 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 2482 | l4_proto = 0; |
fd0a05ce | 2483 | |
a0064728 AD |
2484 | /* reset type as we transition from outer to inner headers */ |
2485 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
2486 | if (ip.v4->version == 4) | |
2487 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
2488 | if (ip.v6->version == 6) | |
89232c3b | 2489 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
fd0a05ce JB |
2490 | } |
2491 | ||
2492 | /* Enable IP checksum offloads */ | |
89232c3b | 2493 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 2494 | l4_proto = ip.v4->protocol; |
fd0a05ce JB |
2495 | /* the stack computes the IP header already, the only time we |
2496 | * need the hardware to recompute it is in the case of TSO. | |
2497 | */ | |
475b4205 AD |
2498 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2499 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
2500 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 2501 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 2502 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
2503 | |
2504 | exthdr = ip.hdr + sizeof(*ip.v6); | |
2505 | l4_proto = ip.v6->nexthdr; | |
2506 | if (l4.hdr != exthdr) | |
2507 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2508 | &l4_proto, &frag_off); | |
fd0a05ce | 2509 | } |
b96b78f2 | 2510 | |
475b4205 AD |
2511 | /* compute inner L3 header size */ |
2512 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
fd0a05ce JB |
2513 | |
2514 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 2515 | switch (l4_proto) { |
fd0a05ce JB |
2516 | case IPPROTO_TCP: |
2517 | /* enable checksum offloads */ | |
475b4205 AD |
2518 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
2519 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2520 | break; |
2521 | case IPPROTO_SCTP: | |
2522 | /* enable SCTP checksum offload */ | |
475b4205 AD |
2523 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
2524 | offset |= (sizeof(struct sctphdr) >> 2) << | |
2525 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2526 | break; |
2527 | case IPPROTO_UDP: | |
2528 | /* enable UDP checksum offload */ | |
475b4205 AD |
2529 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
2530 | offset |= (sizeof(struct udphdr) >> 2) << | |
2531 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2532 | break; |
2533 | default: | |
529f1f65 AD |
2534 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2535 | return -1; | |
2536 | skb_checksum_help(skb); | |
2537 | return 0; | |
fd0a05ce | 2538 | } |
475b4205 AD |
2539 | |
2540 | *td_cmd |= cmd; | |
2541 | *td_offset |= offset; | |
529f1f65 AD |
2542 | |
2543 | return 1; | |
fd0a05ce JB |
2544 | } |
2545 | ||
2546 | /** | |
2547 | * i40e_create_tx_ctx Build the Tx context descriptor | |
2548 | * @tx_ring: ring to create the descriptor on | |
2549 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
2550 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
2551 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
2552 | **/ | |
2553 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
2554 | const u64 cd_type_cmd_tso_mss, | |
2555 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
2556 | { | |
2557 | struct i40e_tx_context_desc *context_desc; | |
fc4ac67b | 2558 | int i = tx_ring->next_to_use; |
fd0a05ce | 2559 | |
ff40dd5d JB |
2560 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
2561 | !cd_tunneling && !cd_l2tag2) | |
fd0a05ce JB |
2562 | return; |
2563 | ||
2564 | /* grab the next descriptor */ | |
fc4ac67b AD |
2565 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); |
2566 | ||
2567 | i++; | |
2568 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2569 | |
2570 | /* cpu_to_le32 and assign to struct fields */ | |
2571 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
2572 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 2573 | context_desc->rsvd = cpu_to_le16(0); |
fd0a05ce JB |
2574 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
2575 | } | |
2576 | ||
4567dc10 ED |
2577 | /** |
2578 | * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions | |
2579 | * @tx_ring: the ring to be checked | |
2580 | * @size: the size buffer we want to assure is available | |
2581 | * | |
2582 | * Returns -EBUSY if a stop is needed, else 0 | |
2583 | **/ | |
4ec441df | 2584 | int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
4567dc10 ED |
2585 | { |
2586 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2587 | /* Memory barrier before checking head and tail */ | |
2588 | smp_mb(); | |
2589 | ||
2590 | /* Check again in a case another CPU has just made room available. */ | |
2591 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
2592 | return -EBUSY; | |
2593 | ||
2594 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
2595 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2596 | ++tx_ring->tx_stats.restart_queue; | |
2597 | return 0; | |
2598 | } | |
2599 | ||
71da6197 | 2600 | /** |
3f3f7cb8 | 2601 | * __i40e_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 2602 | * @skb: send buffer |
71da6197 | 2603 | * |
3f3f7cb8 AD |
2604 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
2605 | * and so we need to figure out the cases where we need to linearize the skb. | |
2606 | * | |
2607 | * For TSO we need to count the TSO header and segment payload separately. | |
2608 | * As such we need to check cases where we have 7 fragments or more as we | |
2609 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
2610 | * the segment payload in the first descriptor, and another 7 for the | |
2611 | * fragments. | |
71da6197 | 2612 | **/ |
2d37490b | 2613 | bool __i40e_chk_linearize(struct sk_buff *skb) |
71da6197 | 2614 | { |
2d37490b | 2615 | const struct skb_frag_struct *frag, *stale; |
3f3f7cb8 | 2616 | int nr_frags, sum; |
71da6197 | 2617 | |
3f3f7cb8 | 2618 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 2619 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 2620 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 2621 | return false; |
71da6197 | 2622 | |
2d37490b | 2623 | /* We need to walk through the list and validate that each group |
841493a3 | 2624 | * of 6 fragments totals at least gso_size. |
2d37490b | 2625 | */ |
3f3f7cb8 | 2626 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
2627 | frag = &skb_shinfo(skb)->frags[0]; |
2628 | ||
2629 | /* Initialize size to the negative value of gso_size minus 1. We | |
2630 | * use this as the worst case scenerio in which the frag ahead | |
2631 | * of us only provides one byte which is why we are limited to 6 | |
2632 | * descriptors for a single transmit as the header and previous | |
2633 | * fragment are already consuming 2 descriptors. | |
2634 | */ | |
3f3f7cb8 | 2635 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 2636 | |
3f3f7cb8 AD |
2637 | /* Add size of frags 0 through 4 to create our initial sum */ |
2638 | sum += skb_frag_size(frag++); | |
2639 | sum += skb_frag_size(frag++); | |
2640 | sum += skb_frag_size(frag++); | |
2641 | sum += skb_frag_size(frag++); | |
2642 | sum += skb_frag_size(frag++); | |
2d37490b AD |
2643 | |
2644 | /* Walk through fragments adding latest fragment, testing it, and | |
2645 | * then removing stale fragments from the sum. | |
2646 | */ | |
2647 | stale = &skb_shinfo(skb)->frags[0]; | |
2648 | for (;;) { | |
3f3f7cb8 | 2649 | sum += skb_frag_size(frag++); |
2d37490b AD |
2650 | |
2651 | /* if sum is negative we failed to make sufficient progress */ | |
2652 | if (sum < 0) | |
2653 | return true; | |
2654 | ||
841493a3 | 2655 | if (!nr_frags--) |
2d37490b AD |
2656 | break; |
2657 | ||
3f3f7cb8 | 2658 | sum -= skb_frag_size(stale++); |
71da6197 AS |
2659 | } |
2660 | ||
2d37490b | 2661 | return false; |
71da6197 AS |
2662 | } |
2663 | ||
fd0a05ce JB |
2664 | /** |
2665 | * i40e_tx_map - Build the Tx descriptor | |
2666 | * @tx_ring: ring to send buffer on | |
2667 | * @skb: send buffer | |
2668 | * @first: first buffer info buffer to use | |
2669 | * @tx_flags: collected send information | |
2670 | * @hdr_len: size of the packet header | |
2671 | * @td_cmd: the command field in the descriptor | |
2672 | * @td_offset: offset for checksum or crc | |
2673 | **/ | |
38e00438 | 2674 | #ifdef I40E_FCOE |
3e587cf3 | 2675 | inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
fd0a05ce JB |
2676 | struct i40e_tx_buffer *first, u32 tx_flags, |
2677 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
3e587cf3 JB |
2678 | #else |
2679 | static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2680 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2681 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
38e00438 | 2682 | #endif |
fd0a05ce | 2683 | { |
fd0a05ce JB |
2684 | unsigned int data_len = skb->data_len; |
2685 | unsigned int size = skb_headlen(skb); | |
a5e9c572 | 2686 | struct skb_frag_struct *frag; |
fd0a05ce JB |
2687 | struct i40e_tx_buffer *tx_bi; |
2688 | struct i40e_tx_desc *tx_desc; | |
a5e9c572 | 2689 | u16 i = tx_ring->next_to_use; |
fd0a05ce JB |
2690 | u32 td_tag = 0; |
2691 | dma_addr_t dma; | |
2692 | u16 gso_segs; | |
58044743 AS |
2693 | u16 desc_count = 0; |
2694 | bool tail_bump = true; | |
2695 | bool do_rs = false; | |
fd0a05ce | 2696 | |
fd0a05ce JB |
2697 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { |
2698 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2699 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2700 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2701 | } | |
2702 | ||
a5e9c572 AD |
2703 | if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) |
2704 | gso_segs = skb_shinfo(skb)->gso_segs; | |
2705 | else | |
2706 | gso_segs = 1; | |
2707 | ||
2708 | /* multiply data chunks by size of headers */ | |
2709 | first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); | |
2710 | first->gso_segs = gso_segs; | |
2711 | first->skb = skb; | |
2712 | first->tx_flags = tx_flags; | |
2713 | ||
2714 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2715 | ||
fd0a05ce | 2716 | tx_desc = I40E_TX_DESC(tx_ring, i); |
a5e9c572 AD |
2717 | tx_bi = first; |
2718 | ||
2719 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
2720 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
2721 | ||
a5e9c572 AD |
2722 | if (dma_mapping_error(tx_ring->dev, dma)) |
2723 | goto dma_error; | |
2724 | ||
2725 | /* record length, and DMA address */ | |
2726 | dma_unmap_len_set(tx_bi, len, size); | |
2727 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2728 | ||
5c4654da AD |
2729 | /* align size to end of page */ |
2730 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
a5e9c572 AD |
2731 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2732 | ||
2733 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
fd0a05ce JB |
2734 | tx_desc->cmd_type_offset_bsz = |
2735 | build_ctob(td_cmd, td_offset, | |
5c4654da | 2736 | max_data, td_tag); |
fd0a05ce | 2737 | |
fd0a05ce JB |
2738 | tx_desc++; |
2739 | i++; | |
58044743 AS |
2740 | desc_count++; |
2741 | ||
fd0a05ce JB |
2742 | if (i == tx_ring->count) { |
2743 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2744 | i = 0; | |
2745 | } | |
fd0a05ce | 2746 | |
5c4654da AD |
2747 | dma += max_data; |
2748 | size -= max_data; | |
fd0a05ce | 2749 | |
5c4654da | 2750 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
a5e9c572 AD |
2751 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2752 | } | |
fd0a05ce JB |
2753 | |
2754 | if (likely(!data_len)) | |
2755 | break; | |
2756 | ||
a5e9c572 AD |
2757 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, |
2758 | size, td_tag); | |
fd0a05ce JB |
2759 | |
2760 | tx_desc++; | |
2761 | i++; | |
58044743 AS |
2762 | desc_count++; |
2763 | ||
fd0a05ce JB |
2764 | if (i == tx_ring->count) { |
2765 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2766 | i = 0; | |
2767 | } | |
2768 | ||
a5e9c572 AD |
2769 | size = skb_frag_size(frag); |
2770 | data_len -= size; | |
fd0a05ce | 2771 | |
a5e9c572 AD |
2772 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
2773 | DMA_TO_DEVICE); | |
fd0a05ce | 2774 | |
a5e9c572 AD |
2775 | tx_bi = &tx_ring->tx_bi[i]; |
2776 | } | |
fd0a05ce | 2777 | |
a5e9c572 AD |
2778 | /* set next_to_watch value indicating a packet is present */ |
2779 | first->next_to_watch = tx_desc; | |
2780 | ||
2781 | i++; | |
2782 | if (i == tx_ring->count) | |
2783 | i = 0; | |
2784 | ||
2785 | tx_ring->next_to_use = i; | |
2786 | ||
e486bdfd | 2787 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
4567dc10 | 2788 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
58044743 AS |
2789 | |
2790 | /* Algorithm to optimize tail and RS bit setting: | |
2791 | * if xmit_more is supported | |
2792 | * if xmit_more is true | |
2793 | * do not update tail and do not mark RS bit. | |
2794 | * if xmit_more is false and last xmit_more was false | |
2795 | * if every packet spanned less than 4 desc | |
2796 | * then set RS bit on 4th packet and update tail | |
2797 | * on every packet | |
2798 | * else | |
2799 | * update tail and set RS bit on every packet. | |
2800 | * if xmit_more is false and last_xmit_more was true | |
2801 | * update tail and set RS bit. | |
2802 | * | |
2803 | * Optimization: wmb to be issued only in case of tail update. | |
2804 | * Also optimize the Descriptor WB path for RS bit with the same | |
2805 | * algorithm. | |
2806 | * | |
2807 | * Note: If there are less than 4 packets | |
2808 | * pending and interrupts were disabled the service task will | |
2809 | * trigger a force WB. | |
2810 | */ | |
2811 | if (skb->xmit_more && | |
e486bdfd | 2812 | !netif_xmit_stopped(txring_txq(tx_ring))) { |
58044743 AS |
2813 | tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; |
2814 | tail_bump = false; | |
2815 | } else if (!skb->xmit_more && | |
e486bdfd | 2816 | !netif_xmit_stopped(txring_txq(tx_ring)) && |
58044743 AS |
2817 | (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) && |
2818 | (tx_ring->packet_stride < WB_STRIDE) && | |
2819 | (desc_count < WB_STRIDE)) { | |
2820 | tx_ring->packet_stride++; | |
2821 | } else { | |
2822 | tx_ring->packet_stride = 0; | |
2823 | tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; | |
2824 | do_rs = true; | |
2825 | } | |
2826 | if (do_rs) | |
2827 | tx_ring->packet_stride = 0; | |
2828 | ||
2829 | tx_desc->cmd_type_offset_bsz = | |
2830 | build_ctob(td_cmd, td_offset, size, td_tag) | | |
2831 | cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD : | |
2832 | I40E_TX_DESC_CMD_EOP) << | |
2833 | I40E_TXD_QW1_CMD_SHIFT); | |
2834 | ||
a5e9c572 | 2835 | /* notify HW of packet */ |
ffeac836 | 2836 | if (!tail_bump) { |
489ce7a4 | 2837 | prefetchw(tx_desc + 1); |
ffeac836 | 2838 | } else { |
58044743 AS |
2839 | /* Force memory writes to complete before letting h/w |
2840 | * know there are new descriptors to fetch. (Only | |
2841 | * applicable for weak-ordered memory model archs, | |
2842 | * such as IA-64). | |
2843 | */ | |
2844 | wmb(); | |
2845 | writel(i, tx_ring->tail); | |
2846 | } | |
fd0a05ce JB |
2847 | return; |
2848 | ||
2849 | dma_error: | |
a5e9c572 | 2850 | dev_info(tx_ring->dev, "TX DMA map failed\n"); |
fd0a05ce JB |
2851 | |
2852 | /* clear dma mappings for failed tx_bi map */ | |
2853 | for (;;) { | |
2854 | tx_bi = &tx_ring->tx_bi[i]; | |
a5e9c572 | 2855 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); |
fd0a05ce JB |
2856 | if (tx_bi == first) |
2857 | break; | |
2858 | if (i == 0) | |
2859 | i = tx_ring->count; | |
2860 | i--; | |
2861 | } | |
2862 | ||
fd0a05ce JB |
2863 | tx_ring->next_to_use = i; |
2864 | } | |
2865 | ||
fd0a05ce JB |
2866 | /** |
2867 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
2868 | * @skb: send buffer | |
2869 | * @tx_ring: ring to send buffer on | |
2870 | * | |
2871 | * Returns NETDEV_TX_OK if sent, else an error code | |
2872 | **/ | |
2873 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
2874 | struct i40e_ring *tx_ring) | |
2875 | { | |
2876 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
2877 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
2878 | struct i40e_tx_buffer *first; | |
2879 | u32 td_offset = 0; | |
2880 | u32 tx_flags = 0; | |
2881 | __be16 protocol; | |
2882 | u32 td_cmd = 0; | |
2883 | u8 hdr_len = 0; | |
4ec441df | 2884 | int tso, count; |
beb0dff1 | 2885 | int tsyn; |
6995b36c | 2886 | |
b74118f0 JB |
2887 | /* prefetch the data, we'll need it later */ |
2888 | prefetch(skb->data); | |
2889 | ||
4ec441df | 2890 | count = i40e_xmit_descriptor_count(skb); |
2d37490b AD |
2891 | if (i40e_chk_linearize(skb, count)) { |
2892 | if (__skb_linearize(skb)) | |
2893 | goto out_drop; | |
5c4654da | 2894 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
2895 | tx_ring->tx_stats.tx_linearize++; |
2896 | } | |
4ec441df AD |
2897 | |
2898 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
2899 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
2900 | * + 4 desc gap to avoid the cache line where head is, | |
2901 | * + 1 desc for context descriptor, | |
2902 | * otherwise try next time | |
2903 | */ | |
2904 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
2905 | tx_ring->tx_stats.tx_busy++; | |
fd0a05ce | 2906 | return NETDEV_TX_BUSY; |
4ec441df | 2907 | } |
fd0a05ce JB |
2908 | |
2909 | /* prepare the xmit flags */ | |
2910 | if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) | |
2911 | goto out_drop; | |
2912 | ||
2913 | /* obtain protocol of skb */ | |
3d34dd03 | 2914 | protocol = vlan_get_protocol(skb); |
fd0a05ce JB |
2915 | |
2916 | /* record the location of the first descriptor for this packet */ | |
2917 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
2918 | ||
2919 | /* setup IPv4/IPv6 offloads */ | |
0e2fe46c | 2920 | if (protocol == htons(ETH_P_IP)) |
fd0a05ce | 2921 | tx_flags |= I40E_TX_FLAGS_IPV4; |
0e2fe46c | 2922 | else if (protocol == htons(ETH_P_IPV6)) |
fd0a05ce JB |
2923 | tx_flags |= I40E_TX_FLAGS_IPV6; |
2924 | ||
84b07992 | 2925 | tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss); |
fd0a05ce JB |
2926 | |
2927 | if (tso < 0) | |
2928 | goto out_drop; | |
2929 | else if (tso) | |
2930 | tx_flags |= I40E_TX_FLAGS_TSO; | |
2931 | ||
3bc67973 AD |
2932 | /* Always offload the checksum, since it's in the data descriptor */ |
2933 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, | |
2934 | tx_ring, &cd_tunneling); | |
2935 | if (tso < 0) | |
2936 | goto out_drop; | |
2937 | ||
beb0dff1 JK |
2938 | tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); |
2939 | ||
2940 | if (tsyn) | |
2941 | tx_flags |= I40E_TX_FLAGS_TSYN; | |
2942 | ||
259afec7 JK |
2943 | skb_tx_timestamp(skb); |
2944 | ||
b1941306 AD |
2945 | /* always enable CRC insertion offload */ |
2946 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
2947 | ||
fd0a05ce JB |
2948 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
2949 | cd_tunneling, cd_l2tag2); | |
2950 | ||
2951 | /* Add Flow Director ATR if it's enabled. | |
2952 | * | |
2953 | * NOTE: this must always be directly before the data descriptor. | |
2954 | */ | |
6b037cd4 | 2955 | i40e_atr(tx_ring, skb, tx_flags); |
fd0a05ce JB |
2956 | |
2957 | i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, | |
2958 | td_cmd, td_offset); | |
2959 | ||
fd0a05ce JB |
2960 | return NETDEV_TX_OK; |
2961 | ||
2962 | out_drop: | |
2963 | dev_kfree_skb_any(skb); | |
2964 | return NETDEV_TX_OK; | |
2965 | } | |
2966 | ||
2967 | /** | |
2968 | * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
2969 | * @skb: send buffer | |
2970 | * @netdev: network interface device structure | |
2971 | * | |
2972 | * Returns NETDEV_TX_OK if sent, else an error code | |
2973 | **/ | |
2974 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2975 | { | |
2976 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2977 | struct i40e_vsi *vsi = np->vsi; | |
9f65e15b | 2978 | struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; |
fd0a05ce JB |
2979 | |
2980 | /* hardware can't handle really short frames, hardware padding works | |
2981 | * beyond this point | |
2982 | */ | |
a94d9e22 AD |
2983 | if (skb_put_padto(skb, I40E_MIN_TX_LEN)) |
2984 | return NETDEV_TX_OK; | |
fd0a05ce JB |
2985 | |
2986 | return i40e_xmit_frame_ring(skb, tx_ring); | |
2987 | } |