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fd0a05ce JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
fd0a05ce JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
fd0a05ce JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
1c112a64 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
fd0a05ce | 29 | #include "i40e.h" |
206812b5 | 30 | #include "i40e_prototype.h" |
fd0a05ce JB |
31 | |
32 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
33 | u32 td_tag) | |
34 | { | |
35 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
36 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
37 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
38 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
39 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
40 | } | |
41 | ||
eaefbd06 | 42 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) |
49d7d933 | 43 | #define I40E_FD_CLEAN_DELAY 10 |
fd0a05ce JB |
44 | /** |
45 | * i40e_program_fdir_filter - Program a Flow Director filter | |
17a73f6b JG |
46 | * @fdir_data: Packet data that will be filter parameters |
47 | * @raw_packet: the pre-allocated packet buffer for FDir | |
b40c82e6 | 48 | * @pf: The PF pointer |
fd0a05ce JB |
49 | * @add: True for add/update, False for remove |
50 | **/ | |
17a73f6b | 51 | int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet, |
fd0a05ce JB |
52 | struct i40e_pf *pf, bool add) |
53 | { | |
54 | struct i40e_filter_program_desc *fdir_desc; | |
49d7d933 | 55 | struct i40e_tx_buffer *tx_buf, *first; |
fd0a05ce JB |
56 | struct i40e_tx_desc *tx_desc; |
57 | struct i40e_ring *tx_ring; | |
eaefbd06 | 58 | unsigned int fpt, dcc; |
fd0a05ce JB |
59 | struct i40e_vsi *vsi; |
60 | struct device *dev; | |
61 | dma_addr_t dma; | |
62 | u32 td_cmd = 0; | |
49d7d933 | 63 | u16 delay = 0; |
fd0a05ce JB |
64 | u16 i; |
65 | ||
66 | /* find existing FDIR VSI */ | |
67 | vsi = NULL; | |
505682cd | 68 | for (i = 0; i < pf->num_alloc_vsi; i++) |
fd0a05ce JB |
69 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) |
70 | vsi = pf->vsi[i]; | |
71 | if (!vsi) | |
72 | return -ENOENT; | |
73 | ||
9f65e15b | 74 | tx_ring = vsi->tx_rings[0]; |
fd0a05ce JB |
75 | dev = tx_ring->dev; |
76 | ||
49d7d933 ASJ |
77 | /* we need two descriptors to add/del a filter and we can wait */ |
78 | do { | |
79 | if (I40E_DESC_UNUSED(tx_ring) > 1) | |
80 | break; | |
81 | msleep_interruptible(1); | |
82 | delay++; | |
83 | } while (delay < I40E_FD_CLEAN_DELAY); | |
84 | ||
85 | if (!(I40E_DESC_UNUSED(tx_ring) > 1)) | |
86 | return -EAGAIN; | |
87 | ||
17a73f6b JG |
88 | dma = dma_map_single(dev, raw_packet, |
89 | I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); | |
fd0a05ce JB |
90 | if (dma_mapping_error(dev, dma)) |
91 | goto dma_fail; | |
92 | ||
93 | /* grab the next descriptor */ | |
fc4ac67b AD |
94 | i = tx_ring->next_to_use; |
95 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
49d7d933 ASJ |
96 | first = &tx_ring->tx_bi[i]; |
97 | memset(first, 0, sizeof(struct i40e_tx_buffer)); | |
fc4ac67b | 98 | |
49d7d933 | 99 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
fd0a05ce | 100 | |
eaefbd06 JB |
101 | fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & |
102 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
fd0a05ce | 103 | |
eaefbd06 JB |
104 | fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) & |
105 | I40E_TXD_FLTR_QW0_FLEXOFF_MASK; | |
fd0a05ce | 106 | |
eaefbd06 JB |
107 | fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) & |
108 | I40E_TXD_FLTR_QW0_PCTYPE_MASK; | |
fd0a05ce JB |
109 | |
110 | /* Use LAN VSI Id if not programmed by user */ | |
111 | if (fdir_data->dest_vsi == 0) | |
eaefbd06 JB |
112 | fpt |= (pf->vsi[pf->lan_vsi]->id) << |
113 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
fd0a05ce | 114 | else |
eaefbd06 JB |
115 | fpt |= ((u32)fdir_data->dest_vsi << |
116 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) & | |
117 | I40E_TXD_FLTR_QW0_DEST_VSI_MASK; | |
118 | ||
eaefbd06 | 119 | dcc = I40E_TX_DESC_DTYPE_FILTER_PROG; |
fd0a05ce JB |
120 | |
121 | if (add) | |
eaefbd06 JB |
122 | dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << |
123 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
fd0a05ce | 124 | else |
eaefbd06 JB |
125 | dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
126 | I40E_TXD_FLTR_QW1_PCMD_SHIFT; | |
fd0a05ce | 127 | |
eaefbd06 JB |
128 | dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) & |
129 | I40E_TXD_FLTR_QW1_DEST_MASK; | |
fd0a05ce | 130 | |
eaefbd06 JB |
131 | dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) & |
132 | I40E_TXD_FLTR_QW1_FD_STATUS_MASK; | |
fd0a05ce JB |
133 | |
134 | if (fdir_data->cnt_index != 0) { | |
eaefbd06 JB |
135 | dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
136 | dcc |= ((u32)fdir_data->cnt_index << | |
137 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
433c47de | 138 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; |
fd0a05ce JB |
139 | } |
140 | ||
99753ea6 JB |
141 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt); |
142 | fdir_desc->rsvd = cpu_to_le32(0); | |
eaefbd06 | 143 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc); |
fd0a05ce JB |
144 | fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id); |
145 | ||
146 | /* Now program a dummy descriptor */ | |
fc4ac67b AD |
147 | i = tx_ring->next_to_use; |
148 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
298deef1 | 149 | tx_buf = &tx_ring->tx_bi[i]; |
fc4ac67b | 150 | |
49d7d933 ASJ |
151 | tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; |
152 | ||
153 | memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); | |
fd0a05ce | 154 | |
298deef1 | 155 | /* record length, and DMA address */ |
17a73f6b | 156 | dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); |
298deef1 ASJ |
157 | dma_unmap_addr_set(tx_buf, dma, dma); |
158 | ||
fd0a05ce | 159 | tx_desc->buffer_addr = cpu_to_le64(dma); |
eaefbd06 | 160 | td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; |
fd0a05ce | 161 | |
49d7d933 ASJ |
162 | tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; |
163 | tx_buf->raw_buf = (void *)raw_packet; | |
164 | ||
fd0a05ce | 165 | tx_desc->cmd_type_offset_bsz = |
17a73f6b | 166 | build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); |
fd0a05ce | 167 | |
fd0a05ce | 168 | /* Force memory writes to complete before letting h/w |
49d7d933 | 169 | * know there are new descriptors to fetch. |
fd0a05ce JB |
170 | */ |
171 | wmb(); | |
172 | ||
fc4ac67b | 173 | /* Mark the data descriptor to be watched */ |
49d7d933 | 174 | first->next_to_watch = tx_desc; |
fc4ac67b | 175 | |
fd0a05ce JB |
176 | writel(tx_ring->next_to_use, tx_ring->tail); |
177 | return 0; | |
178 | ||
179 | dma_fail: | |
180 | return -1; | |
181 | } | |
182 | ||
17a73f6b JG |
183 | #define IP_HEADER_OFFSET 14 |
184 | #define I40E_UDPIP_DUMMY_PACKET_LEN 42 | |
185 | /** | |
186 | * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters | |
187 | * @vsi: pointer to the targeted VSI | |
188 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
189 | * @add: true adds a filter, false removes it |
190 | * | |
191 | * Returns 0 if the filters were successfully added or removed | |
192 | **/ | |
193 | static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, | |
194 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 195 | bool add) |
17a73f6b JG |
196 | { |
197 | struct i40e_pf *pf = vsi->back; | |
198 | struct udphdr *udp; | |
199 | struct iphdr *ip; | |
200 | bool err = false; | |
49d7d933 | 201 | u8 *raw_packet; |
17a73f6b | 202 | int ret; |
17a73f6b JG |
203 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, |
204 | 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, | |
205 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; | |
206 | ||
49d7d933 ASJ |
207 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
208 | if (!raw_packet) | |
209 | return -ENOMEM; | |
17a73f6b JG |
210 | memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); |
211 | ||
212 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
213 | udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET | |
214 | + sizeof(struct iphdr)); | |
215 | ||
216 | ip->daddr = fd_data->dst_ip[0]; | |
217 | udp->dest = fd_data->dst_port; | |
218 | ip->saddr = fd_data->src_ip[0]; | |
219 | udp->source = fd_data->src_port; | |
220 | ||
b2d36c03 KS |
221 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; |
222 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
223 | if (ret) { | |
224 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
225 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
226 | fd_data->pctype, fd_data->fd_id, ret); | |
b2d36c03 | 227 | err = true; |
4205d379 | 228 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
229 | if (add) |
230 | dev_info(&pf->pdev->dev, | |
231 | "Filter OK for PCTYPE %d loc = %d\n", | |
232 | fd_data->pctype, fd_data->fd_id); | |
233 | else | |
234 | dev_info(&pf->pdev->dev, | |
235 | "Filter deleted for PCTYPE %d loc = %d\n", | |
236 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b | 237 | } |
a42e7a36 KP |
238 | if (err) |
239 | kfree(raw_packet); | |
240 | ||
17a73f6b JG |
241 | return err ? -EOPNOTSUPP : 0; |
242 | } | |
243 | ||
244 | #define I40E_TCPIP_DUMMY_PACKET_LEN 54 | |
245 | /** | |
246 | * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters | |
247 | * @vsi: pointer to the targeted VSI | |
248 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
249 | * @add: true adds a filter, false removes it |
250 | * | |
251 | * Returns 0 if the filters were successfully added or removed | |
252 | **/ | |
253 | static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, | |
254 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 255 | bool add) |
17a73f6b JG |
256 | { |
257 | struct i40e_pf *pf = vsi->back; | |
258 | struct tcphdr *tcp; | |
259 | struct iphdr *ip; | |
260 | bool err = false; | |
49d7d933 | 261 | u8 *raw_packet; |
17a73f6b JG |
262 | int ret; |
263 | /* Dummy packet */ | |
264 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
265 | 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, | |
266 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, | |
267 | 0x0, 0x72, 0, 0, 0, 0}; | |
268 | ||
49d7d933 ASJ |
269 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
270 | if (!raw_packet) | |
271 | return -ENOMEM; | |
17a73f6b JG |
272 | memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); |
273 | ||
274 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
275 | tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET | |
276 | + sizeof(struct iphdr)); | |
277 | ||
278 | ip->daddr = fd_data->dst_ip[0]; | |
279 | tcp->dest = fd_data->dst_port; | |
280 | ip->saddr = fd_data->src_ip[0]; | |
281 | tcp->source = fd_data->src_port; | |
282 | ||
283 | if (add) { | |
1e1be8f6 | 284 | pf->fd_tcp_rule++; |
17a73f6b | 285 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) { |
2e4875e3 ASJ |
286 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
287 | dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); | |
17a73f6b JG |
288 | pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; |
289 | } | |
1e1be8f6 ASJ |
290 | } else { |
291 | pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ? | |
292 | (pf->fd_tcp_rule - 1) : 0; | |
293 | if (pf->fd_tcp_rule == 0) { | |
294 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
2e4875e3 ASJ |
295 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
296 | dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); | |
1e1be8f6 | 297 | } |
17a73f6b JG |
298 | } |
299 | ||
b2d36c03 | 300 | fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; |
17a73f6b JG |
301 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); |
302 | ||
303 | if (ret) { | |
304 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
305 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
306 | fd_data->pctype, fd_data->fd_id, ret); | |
17a73f6b | 307 | err = true; |
4205d379 | 308 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
309 | if (add) |
310 | dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", | |
311 | fd_data->pctype, fd_data->fd_id); | |
312 | else | |
313 | dev_info(&pf->pdev->dev, | |
314 | "Filter deleted for PCTYPE %d loc = %d\n", | |
315 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
316 | } |
317 | ||
a42e7a36 KP |
318 | if (err) |
319 | kfree(raw_packet); | |
320 | ||
17a73f6b JG |
321 | return err ? -EOPNOTSUPP : 0; |
322 | } | |
323 | ||
324 | /** | |
325 | * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for | |
326 | * a specific flow spec | |
327 | * @vsi: pointer to the targeted VSI | |
328 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
329 | * @add: true adds a filter, false removes it |
330 | * | |
4eeb1fff | 331 | * Returns 0 if the filters were successfully added or removed |
17a73f6b JG |
332 | **/ |
333 | static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, | |
334 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 335 | bool add) |
17a73f6b JG |
336 | { |
337 | return -EOPNOTSUPP; | |
338 | } | |
339 | ||
340 | #define I40E_IP_DUMMY_PACKET_LEN 34 | |
341 | /** | |
342 | * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for | |
343 | * a specific flow spec | |
344 | * @vsi: pointer to the targeted VSI | |
345 | * @fd_data: the flow director data required for the FDir descriptor | |
17a73f6b JG |
346 | * @add: true adds a filter, false removes it |
347 | * | |
348 | * Returns 0 if the filters were successfully added or removed | |
349 | **/ | |
350 | static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, | |
351 | struct i40e_fdir_filter *fd_data, | |
49d7d933 | 352 | bool add) |
17a73f6b JG |
353 | { |
354 | struct i40e_pf *pf = vsi->back; | |
355 | struct iphdr *ip; | |
356 | bool err = false; | |
49d7d933 | 357 | u8 *raw_packet; |
17a73f6b JG |
358 | int ret; |
359 | int i; | |
360 | static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, | |
361 | 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, | |
362 | 0, 0, 0, 0}; | |
363 | ||
17a73f6b JG |
364 | for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; |
365 | i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { | |
49d7d933 ASJ |
366 | raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); |
367 | if (!raw_packet) | |
368 | return -ENOMEM; | |
369 | memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); | |
370 | ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); | |
371 | ||
372 | ip->saddr = fd_data->src_ip[0]; | |
373 | ip->daddr = fd_data->dst_ip[0]; | |
374 | ip->protocol = 0; | |
375 | ||
17a73f6b JG |
376 | fd_data->pctype = i; |
377 | ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); | |
378 | ||
379 | if (ret) { | |
380 | dev_info(&pf->pdev->dev, | |
e99bdd39 CW |
381 | "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", |
382 | fd_data->pctype, fd_data->fd_id, ret); | |
17a73f6b | 383 | err = true; |
4205d379 | 384 | } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { |
f7233c54 ASJ |
385 | if (add) |
386 | dev_info(&pf->pdev->dev, | |
387 | "Filter OK for PCTYPE %d loc = %d\n", | |
388 | fd_data->pctype, fd_data->fd_id); | |
389 | else | |
390 | dev_info(&pf->pdev->dev, | |
391 | "Filter deleted for PCTYPE %d loc = %d\n", | |
392 | fd_data->pctype, fd_data->fd_id); | |
17a73f6b JG |
393 | } |
394 | } | |
395 | ||
a42e7a36 KP |
396 | if (err) |
397 | kfree(raw_packet); | |
398 | ||
17a73f6b JG |
399 | return err ? -EOPNOTSUPP : 0; |
400 | } | |
401 | ||
402 | /** | |
403 | * i40e_add_del_fdir - Build raw packets to add/del fdir filter | |
404 | * @vsi: pointer to the targeted VSI | |
405 | * @cmd: command to get or set RX flow classification rules | |
406 | * @add: true adds a filter, false removes it | |
407 | * | |
408 | **/ | |
409 | int i40e_add_del_fdir(struct i40e_vsi *vsi, | |
410 | struct i40e_fdir_filter *input, bool add) | |
411 | { | |
412 | struct i40e_pf *pf = vsi->back; | |
17a73f6b JG |
413 | int ret; |
414 | ||
17a73f6b JG |
415 | switch (input->flow_type & ~FLOW_EXT) { |
416 | case TCP_V4_FLOW: | |
49d7d933 | 417 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
418 | break; |
419 | case UDP_V4_FLOW: | |
49d7d933 | 420 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b JG |
421 | break; |
422 | case SCTP_V4_FLOW: | |
49d7d933 | 423 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); |
17a73f6b JG |
424 | break; |
425 | case IPV4_FLOW: | |
49d7d933 | 426 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b JG |
427 | break; |
428 | case IP_USER_FLOW: | |
429 | switch (input->ip4_proto) { | |
430 | case IPPROTO_TCP: | |
49d7d933 | 431 | ret = i40e_add_del_fdir_tcpv4(vsi, input, add); |
17a73f6b JG |
432 | break; |
433 | case IPPROTO_UDP: | |
49d7d933 | 434 | ret = i40e_add_del_fdir_udpv4(vsi, input, add); |
17a73f6b JG |
435 | break; |
436 | case IPPROTO_SCTP: | |
49d7d933 | 437 | ret = i40e_add_del_fdir_sctpv4(vsi, input, add); |
17a73f6b JG |
438 | break; |
439 | default: | |
49d7d933 | 440 | ret = i40e_add_del_fdir_ipv4(vsi, input, add); |
17a73f6b JG |
441 | break; |
442 | } | |
443 | break; | |
444 | default: | |
c5ffe7e1 | 445 | dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", |
17a73f6b JG |
446 | input->flow_type); |
447 | ret = -EINVAL; | |
448 | } | |
449 | ||
49d7d933 | 450 | /* The buffer allocated here is freed by the i40e_clean_tx_ring() */ |
17a73f6b JG |
451 | return ret; |
452 | } | |
453 | ||
fd0a05ce JB |
454 | /** |
455 | * i40e_fd_handle_status - check the Programming Status for FD | |
456 | * @rx_ring: the Rx ring for this descriptor | |
55a5e60b | 457 | * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. |
fd0a05ce JB |
458 | * @prog_id: the id originally used for programming |
459 | * | |
460 | * This is used to verify if the FD programming or invalidation | |
461 | * requested by SW to the HW is successful or not and take actions accordingly. | |
462 | **/ | |
55a5e60b ASJ |
463 | static void i40e_fd_handle_status(struct i40e_ring *rx_ring, |
464 | union i40e_rx_desc *rx_desc, u8 prog_id) | |
fd0a05ce | 465 | { |
55a5e60b ASJ |
466 | struct i40e_pf *pf = rx_ring->vsi->back; |
467 | struct pci_dev *pdev = pf->pdev; | |
468 | u32 fcnt_prog, fcnt_avail; | |
fd0a05ce | 469 | u32 error; |
55a5e60b | 470 | u64 qw; |
fd0a05ce | 471 | |
55a5e60b | 472 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
fd0a05ce JB |
473 | error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> |
474 | I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; | |
475 | ||
41a1d04b | 476 | if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { |
3487b6c3 | 477 | pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); |
f7233c54 ASJ |
478 | if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || |
479 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
480 | dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", | |
3487b6c3 | 481 | pf->fd_inv); |
55a5e60b | 482 | |
04294e38 ASJ |
483 | /* Check if the programming error is for ATR. |
484 | * If so, auto disable ATR and set a state for | |
485 | * flush in progress. Next time we come here if flush is in | |
486 | * progress do nothing, once flush is complete the state will | |
487 | * be cleared. | |
488 | */ | |
489 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) | |
490 | return; | |
491 | ||
1e1be8f6 ASJ |
492 | pf->fd_add_err++; |
493 | /* store the current atr filter count */ | |
494 | pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); | |
495 | ||
04294e38 ASJ |
496 | if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && |
497 | (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { | |
498 | pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; | |
499 | set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); | |
500 | } | |
501 | ||
55a5e60b | 502 | /* filter programming failed most likely due to table full */ |
04294e38 | 503 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 504 | fcnt_avail = pf->fdir_pf_filter_count; |
55a5e60b ASJ |
505 | /* If ATR is running fcnt_prog can quickly change, |
506 | * if we are very close to full, it makes sense to disable | |
507 | * FD ATR/SB and then re-enable it when there is room. | |
508 | */ | |
509 | if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { | |
1e1be8f6 | 510 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
b814ba65 | 511 | !(pf->auto_disable_flags & |
b814ba65 | 512 | I40E_FLAG_FD_SB_ENABLED)) { |
2e4875e3 ASJ |
513 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
514 | dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); | |
55a5e60b ASJ |
515 | pf->auto_disable_flags |= |
516 | I40E_FLAG_FD_SB_ENABLED; | |
55a5e60b | 517 | } |
55a5e60b | 518 | } |
41a1d04b | 519 | } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { |
13c2884f | 520 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
e99bdd39 | 521 | dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", |
13c2884f | 522 | rx_desc->wb.qword0.hi_dword.fd_id); |
55a5e60b | 523 | } |
fd0a05ce JB |
524 | } |
525 | ||
526 | /** | |
a5e9c572 | 527 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer |
fd0a05ce JB |
528 | * @ring: the ring that owns the buffer |
529 | * @tx_buffer: the buffer to free | |
530 | **/ | |
a5e9c572 AD |
531 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, |
532 | struct i40e_tx_buffer *tx_buffer) | |
fd0a05ce | 533 | { |
a5e9c572 | 534 | if (tx_buffer->skb) { |
a42e7a36 | 535 | dev_kfree_skb_any(tx_buffer->skb); |
a5e9c572 | 536 | if (dma_unmap_len(tx_buffer, len)) |
fd0a05ce | 537 | dma_unmap_single(ring->dev, |
35a1e2ad AD |
538 | dma_unmap_addr(tx_buffer, dma), |
539 | dma_unmap_len(tx_buffer, len), | |
fd0a05ce | 540 | DMA_TO_DEVICE); |
a5e9c572 AD |
541 | } else if (dma_unmap_len(tx_buffer, len)) { |
542 | dma_unmap_page(ring->dev, | |
543 | dma_unmap_addr(tx_buffer, dma), | |
544 | dma_unmap_len(tx_buffer, len), | |
545 | DMA_TO_DEVICE); | |
fd0a05ce | 546 | } |
a42e7a36 KP |
547 | |
548 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) | |
549 | kfree(tx_buffer->raw_buf); | |
550 | ||
a5e9c572 AD |
551 | tx_buffer->next_to_watch = NULL; |
552 | tx_buffer->skb = NULL; | |
35a1e2ad | 553 | dma_unmap_len_set(tx_buffer, len, 0); |
a5e9c572 | 554 | /* tx_buffer must be completely set up in the transmit path */ |
fd0a05ce JB |
555 | } |
556 | ||
557 | /** | |
558 | * i40e_clean_tx_ring - Free any empty Tx buffers | |
559 | * @tx_ring: ring to be cleaned | |
560 | **/ | |
561 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring) | |
562 | { | |
fd0a05ce JB |
563 | unsigned long bi_size; |
564 | u16 i; | |
565 | ||
566 | /* ring already cleared, nothing to do */ | |
567 | if (!tx_ring->tx_bi) | |
568 | return; | |
569 | ||
570 | /* Free all the Tx ring sk_buffs */ | |
a5e9c572 AD |
571 | for (i = 0; i < tx_ring->count; i++) |
572 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
fd0a05ce JB |
573 | |
574 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
575 | memset(tx_ring->tx_bi, 0, bi_size); | |
576 | ||
577 | /* Zero out the descriptor ring */ | |
578 | memset(tx_ring->desc, 0, tx_ring->size); | |
579 | ||
580 | tx_ring->next_to_use = 0; | |
581 | tx_ring->next_to_clean = 0; | |
7070ce0a AD |
582 | |
583 | if (!tx_ring->netdev) | |
584 | return; | |
585 | ||
586 | /* cleanup Tx queue statistics */ | |
587 | netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, | |
588 | tx_ring->queue_index)); | |
fd0a05ce JB |
589 | } |
590 | ||
591 | /** | |
592 | * i40e_free_tx_resources - Free Tx resources per queue | |
593 | * @tx_ring: Tx descriptor ring for a specific queue | |
594 | * | |
595 | * Free all transmit software resources | |
596 | **/ | |
597 | void i40e_free_tx_resources(struct i40e_ring *tx_ring) | |
598 | { | |
599 | i40e_clean_tx_ring(tx_ring); | |
600 | kfree(tx_ring->tx_bi); | |
601 | tx_ring->tx_bi = NULL; | |
602 | ||
603 | if (tx_ring->desc) { | |
604 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
605 | tx_ring->desc, tx_ring->dma); | |
606 | tx_ring->desc = NULL; | |
607 | } | |
608 | } | |
609 | ||
610 | /** | |
611 | * i40e_get_tx_pending - how many tx descriptors not processed | |
612 | * @tx_ring: the ring of descriptors | |
dd353109 | 613 | * @in_sw: is tx_pending being checked in SW or HW |
fd0a05ce JB |
614 | * |
615 | * Since there is no access to the ring head register | |
616 | * in XL710, we need to use our local copies | |
617 | **/ | |
dd353109 | 618 | u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
fd0a05ce | 619 | { |
a68de58d JB |
620 | u32 head, tail; |
621 | ||
dd353109 ASJ |
622 | if (!in_sw) |
623 | head = i40e_get_head(ring); | |
624 | else | |
625 | head = ring->next_to_clean; | |
a68de58d JB |
626 | tail = readl(ring->tail); |
627 | ||
628 | if (head != tail) | |
629 | return (head < tail) ? | |
630 | tail - head : (tail + ring->count - head); | |
631 | ||
632 | return 0; | |
fd0a05ce JB |
633 | } |
634 | ||
d91649f5 JB |
635 | #define WB_STRIDE 0x3 |
636 | ||
fd0a05ce JB |
637 | /** |
638 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
639 | * @tx_ring: tx ring to clean | |
640 | * @budget: how many cleans we're allowed | |
641 | * | |
642 | * Returns true if there's any budget left (e.g. the clean is finished) | |
643 | **/ | |
644 | static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) | |
645 | { | |
646 | u16 i = tx_ring->next_to_clean; | |
647 | struct i40e_tx_buffer *tx_buf; | |
1943d8ba | 648 | struct i40e_tx_desc *tx_head; |
fd0a05ce JB |
649 | struct i40e_tx_desc *tx_desc; |
650 | unsigned int total_packets = 0; | |
651 | unsigned int total_bytes = 0; | |
652 | ||
653 | tx_buf = &tx_ring->tx_bi[i]; | |
654 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
a5e9c572 | 655 | i -= tx_ring->count; |
fd0a05ce | 656 | |
1943d8ba JB |
657 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
658 | ||
a5e9c572 AD |
659 | do { |
660 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
fd0a05ce JB |
661 | |
662 | /* if next_to_watch is not set then there is no work pending */ | |
663 | if (!eop_desc) | |
664 | break; | |
665 | ||
a5e9c572 AD |
666 | /* prevent any other reads prior to eop_desc */ |
667 | read_barrier_depends(); | |
668 | ||
1943d8ba JB |
669 | /* we have caught up to head, no work left to do */ |
670 | if (tx_head == tx_desc) | |
fd0a05ce JB |
671 | break; |
672 | ||
c304fdac | 673 | /* clear next_to_watch to prevent false hangs */ |
fd0a05ce | 674 | tx_buf->next_to_watch = NULL; |
fd0a05ce | 675 | |
a5e9c572 AD |
676 | /* update the statistics for this packet */ |
677 | total_bytes += tx_buf->bytecount; | |
678 | total_packets += tx_buf->gso_segs; | |
fd0a05ce | 679 | |
a5e9c572 | 680 | /* free the skb */ |
a81fb049 | 681 | dev_consume_skb_any(tx_buf->skb); |
fd0a05ce | 682 | |
a5e9c572 AD |
683 | /* unmap skb header data */ |
684 | dma_unmap_single(tx_ring->dev, | |
685 | dma_unmap_addr(tx_buf, dma), | |
686 | dma_unmap_len(tx_buf, len), | |
687 | DMA_TO_DEVICE); | |
fd0a05ce | 688 | |
a5e9c572 AD |
689 | /* clear tx_buffer data */ |
690 | tx_buf->skb = NULL; | |
691 | dma_unmap_len_set(tx_buf, len, 0); | |
fd0a05ce | 692 | |
a5e9c572 AD |
693 | /* unmap remaining buffers */ |
694 | while (tx_desc != eop_desc) { | |
fd0a05ce JB |
695 | |
696 | tx_buf++; | |
697 | tx_desc++; | |
698 | i++; | |
a5e9c572 AD |
699 | if (unlikely(!i)) { |
700 | i -= tx_ring->count; | |
fd0a05ce JB |
701 | tx_buf = tx_ring->tx_bi; |
702 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
703 | } | |
fd0a05ce | 704 | |
a5e9c572 AD |
705 | /* unmap any remaining paged data */ |
706 | if (dma_unmap_len(tx_buf, len)) { | |
707 | dma_unmap_page(tx_ring->dev, | |
708 | dma_unmap_addr(tx_buf, dma), | |
709 | dma_unmap_len(tx_buf, len), | |
710 | DMA_TO_DEVICE); | |
711 | dma_unmap_len_set(tx_buf, len, 0); | |
712 | } | |
713 | } | |
714 | ||
715 | /* move us one more past the eop_desc for start of next pkt */ | |
716 | tx_buf++; | |
717 | tx_desc++; | |
718 | i++; | |
719 | if (unlikely(!i)) { | |
720 | i -= tx_ring->count; | |
721 | tx_buf = tx_ring->tx_bi; | |
722 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
723 | } | |
724 | ||
016890b9 JB |
725 | prefetch(tx_desc); |
726 | ||
a5e9c572 AD |
727 | /* update budget accounting */ |
728 | budget--; | |
729 | } while (likely(budget)); | |
730 | ||
731 | i += tx_ring->count; | |
fd0a05ce | 732 | tx_ring->next_to_clean = i; |
980e9b11 | 733 | u64_stats_update_begin(&tx_ring->syncp); |
a114d0a6 AD |
734 | tx_ring->stats.bytes += total_bytes; |
735 | tx_ring->stats.packets += total_packets; | |
980e9b11 | 736 | u64_stats_update_end(&tx_ring->syncp); |
fd0a05ce JB |
737 | tx_ring->q_vector->tx.total_bytes += total_bytes; |
738 | tx_ring->q_vector->tx.total_packets += total_packets; | |
a5e9c572 | 739 | |
58044743 AS |
740 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
741 | unsigned int j = 0; | |
742 | ||
743 | /* check to see if there are < 4 descriptors | |
744 | * waiting to be written back, then kick the hardware to force | |
745 | * them to be written back in case we stay in NAPI. | |
746 | * In this mode on X722 we do not enable Interrupt. | |
747 | */ | |
dd353109 | 748 | j = i40e_get_tx_pending(tx_ring, false); |
58044743 AS |
749 | |
750 | if (budget && | |
751 | ((j / (WB_STRIDE + 1)) == 0) && (j != 0) && | |
752 | !test_bit(__I40E_DOWN, &tx_ring->vsi->state) && | |
753 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) | |
754 | tx_ring->arm_wb = true; | |
755 | } | |
d91649f5 | 756 | |
7070ce0a AD |
757 | netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, |
758 | tx_ring->queue_index), | |
759 | total_packets, total_bytes); | |
760 | ||
fd0a05ce JB |
761 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
762 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
763 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
764 | /* Make sure that anybody stopping the queue after this | |
765 | * sees the new next_to_clean. | |
766 | */ | |
767 | smp_mb(); | |
768 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
769 | tx_ring->queue_index) && | |
770 | !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) { | |
771 | netif_wake_subqueue(tx_ring->netdev, | |
772 | tx_ring->queue_index); | |
773 | ++tx_ring->tx_stats.restart_queue; | |
774 | } | |
775 | } | |
776 | ||
d91649f5 JB |
777 | return !!budget; |
778 | } | |
779 | ||
780 | /** | |
ecc6a239 | 781 | * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
d91649f5 | 782 | * @vsi: the VSI we care about |
ecc6a239 | 783 | * @q_vector: the vector on which to enable writeback |
d91649f5 JB |
784 | * |
785 | **/ | |
ecc6a239 ASJ |
786 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
787 | struct i40e_q_vector *q_vector) | |
d91649f5 | 788 | { |
8e0764b4 | 789 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 790 | u32 val; |
8e0764b4 | 791 | |
ecc6a239 ASJ |
792 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
793 | return; | |
8e0764b4 | 794 | |
ecc6a239 ASJ |
795 | if (q_vector->arm_wb_state) |
796 | return; | |
8e0764b4 | 797 | |
ecc6a239 ASJ |
798 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { |
799 | val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | | |
800 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 801 | |
ecc6a239 ASJ |
802 | wr32(&vsi->back->hw, |
803 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), | |
804 | val); | |
805 | } else { | |
806 | val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | | |
807 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ | |
a3d772a3 | 808 | |
ecc6a239 ASJ |
809 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); |
810 | } | |
811 | q_vector->arm_wb_state = true; | |
812 | } | |
813 | ||
814 | /** | |
815 | * i40e_force_wb - Issue SW Interrupt so HW does a wb | |
816 | * @vsi: the VSI we care about | |
817 | * @q_vector: the vector on which to force writeback | |
818 | * | |
819 | **/ | |
820 | void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
821 | { | |
822 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { | |
8e0764b4 ASJ |
823 | u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | |
824 | I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ | |
825 | I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | | |
826 | I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; | |
827 | /* allow 00 to be written to the index */ | |
828 | ||
829 | wr32(&vsi->back->hw, | |
830 | I40E_PFINT_DYN_CTLN(q_vector->v_idx + | |
831 | vsi->base_vector - 1), val); | |
832 | } else { | |
833 | u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
834 | I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ | |
835 | I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | | |
836 | I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; | |
837 | /* allow 00 to be written to the index */ | |
838 | ||
839 | wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); | |
840 | } | |
fd0a05ce JB |
841 | } |
842 | ||
843 | /** | |
844 | * i40e_set_new_dynamic_itr - Find new ITR level | |
845 | * @rc: structure containing ring performance data | |
846 | * | |
8f5e39ce JB |
847 | * Returns true if ITR changed, false if not |
848 | * | |
fd0a05ce JB |
849 | * Stores a new ITR value based on packets and byte counts during |
850 | * the last interrupt. The advantage of per interrupt computation | |
851 | * is faster updates and more accurate ITR for the current traffic | |
852 | * pattern. Constants in this function were computed based on | |
853 | * theoretical maximum wire speed and thresholds were set based on | |
854 | * testing data as well as attempting to minimize response time | |
855 | * while increasing bulk throughput. | |
856 | **/ | |
8f5e39ce | 857 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
fd0a05ce JB |
858 | { |
859 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
c56625d5 | 860 | struct i40e_q_vector *qv = rc->ring->q_vector; |
fd0a05ce JB |
861 | u32 new_itr = rc->itr; |
862 | int bytes_per_int; | |
51cc6d9f | 863 | int usecs; |
fd0a05ce JB |
864 | |
865 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 866 | return false; |
fd0a05ce JB |
867 | |
868 | /* simple throttlerate management | |
c56625d5 | 869 | * 0-10MB/s lowest (50000 ints/s) |
fd0a05ce | 870 | * 10-20MB/s low (20000 ints/s) |
c56625d5 JB |
871 | * 20-1249MB/s bulk (18000 ints/s) |
872 | * > 40000 Rx packets per second (8000 ints/s) | |
51cc6d9f JB |
873 | * |
874 | * The math works out because the divisor is in 10^(-6) which | |
875 | * turns the bytes/us input value into MB/s values, but | |
876 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
877 | * are in 2 usec increments in the ITR registers, and make sure |
878 | * to use the smoothed values that the countdown timer gives us. | |
fd0a05ce | 879 | */ |
ee2319cf | 880 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
51cc6d9f | 881 | bytes_per_int = rc->total_bytes / usecs; |
ee2319cf | 882 | |
de32e3ef | 883 | switch (new_latency_range) { |
fd0a05ce JB |
884 | case I40E_LOWEST_LATENCY: |
885 | if (bytes_per_int > 10) | |
886 | new_latency_range = I40E_LOW_LATENCY; | |
887 | break; | |
888 | case I40E_LOW_LATENCY: | |
889 | if (bytes_per_int > 20) | |
890 | new_latency_range = I40E_BULK_LATENCY; | |
891 | else if (bytes_per_int <= 10) | |
892 | new_latency_range = I40E_LOWEST_LATENCY; | |
893 | break; | |
894 | case I40E_BULK_LATENCY: | |
c56625d5 | 895 | case I40E_ULTRA_LATENCY: |
de32e3ef CW |
896 | default: |
897 | if (bytes_per_int <= 20) | |
898 | new_latency_range = I40E_LOW_LATENCY; | |
fd0a05ce JB |
899 | break; |
900 | } | |
c56625d5 JB |
901 | |
902 | /* this is to adjust RX more aggressively when streaming small | |
903 | * packets. The value of 40000 was picked as it is just beyond | |
904 | * what the hardware can receive per second if in low latency | |
905 | * mode. | |
906 | */ | |
907 | #define RX_ULTRA_PACKET_RATE 40000 | |
908 | ||
909 | if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && | |
910 | (&qv->rx == rc)) | |
911 | new_latency_range = I40E_ULTRA_LATENCY; | |
912 | ||
de32e3ef | 913 | rc->latency_range = new_latency_range; |
fd0a05ce JB |
914 | |
915 | switch (new_latency_range) { | |
916 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 917 | new_itr = I40E_ITR_50K; |
fd0a05ce JB |
918 | break; |
919 | case I40E_LOW_LATENCY: | |
920 | new_itr = I40E_ITR_20K; | |
921 | break; | |
922 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
923 | new_itr = I40E_ITR_18K; |
924 | break; | |
925 | case I40E_ULTRA_LATENCY: | |
fd0a05ce JB |
926 | new_itr = I40E_ITR_8K; |
927 | break; | |
928 | default: | |
929 | break; | |
930 | } | |
931 | ||
fd0a05ce JB |
932 | rc->total_bytes = 0; |
933 | rc->total_packets = 0; | |
8f5e39ce JB |
934 | |
935 | if (new_itr != rc->itr) { | |
936 | rc->itr = new_itr; | |
937 | return true; | |
938 | } | |
939 | ||
940 | return false; | |
fd0a05ce JB |
941 | } |
942 | ||
fd0a05ce JB |
943 | /** |
944 | * i40e_clean_programming_status - clean the programming status descriptor | |
945 | * @rx_ring: the rx ring that has this descriptor | |
946 | * @rx_desc: the rx descriptor written back by HW | |
947 | * | |
948 | * Flow director should handle FD_FILTER_STATUS to check its filter programming | |
949 | * status being successful or not and take actions accordingly. FCoE should | |
950 | * handle its context/filter programming/invalidation status and take actions. | |
951 | * | |
952 | **/ | |
953 | static void i40e_clean_programming_status(struct i40e_ring *rx_ring, | |
954 | union i40e_rx_desc *rx_desc) | |
955 | { | |
956 | u64 qw; | |
957 | u8 id; | |
958 | ||
959 | qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
960 | id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> | |
961 | I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; | |
962 | ||
963 | if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) | |
55a5e60b | 964 | i40e_fd_handle_status(rx_ring, rx_desc, id); |
38e00438 VD |
965 | #ifdef I40E_FCOE |
966 | else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || | |
967 | (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) | |
968 | i40e_fcoe_handle_status(rx_ring, rx_desc, id); | |
969 | #endif | |
fd0a05ce JB |
970 | } |
971 | ||
972 | /** | |
973 | * i40e_setup_tx_descriptors - Allocate the Tx descriptors | |
974 | * @tx_ring: the tx ring to set up | |
975 | * | |
976 | * Return 0 on success, negative on error | |
977 | **/ | |
978 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
979 | { | |
980 | struct device *dev = tx_ring->dev; | |
981 | int bi_size; | |
982 | ||
983 | if (!dev) | |
984 | return -ENOMEM; | |
985 | ||
e908f815 JB |
986 | /* warn if we are about to overwrite the pointer */ |
987 | WARN_ON(tx_ring->tx_bi); | |
fd0a05ce JB |
988 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
989 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
990 | if (!tx_ring->tx_bi) | |
991 | goto err; | |
992 | ||
993 | /* round up to nearest 4K */ | |
994 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
995 | /* add u32 for head writeback, align after this takes care of |
996 | * guaranteeing this is at least one cache line in size | |
997 | */ | |
998 | tx_ring->size += sizeof(u32); | |
fd0a05ce JB |
999 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1000 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
1001 | &tx_ring->dma, GFP_KERNEL); | |
1002 | if (!tx_ring->desc) { | |
1003 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
1004 | tx_ring->size); | |
1005 | goto err; | |
1006 | } | |
1007 | ||
1008 | tx_ring->next_to_use = 0; | |
1009 | tx_ring->next_to_clean = 0; | |
1010 | return 0; | |
1011 | ||
1012 | err: | |
1013 | kfree(tx_ring->tx_bi); | |
1014 | tx_ring->tx_bi = NULL; | |
1015 | return -ENOMEM; | |
1016 | } | |
1017 | ||
1018 | /** | |
1019 | * i40e_clean_rx_ring - Free Rx buffers | |
1020 | * @rx_ring: ring to be cleaned | |
1021 | **/ | |
1022 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring) | |
1023 | { | |
1024 | struct device *dev = rx_ring->dev; | |
1025 | struct i40e_rx_buffer *rx_bi; | |
1026 | unsigned long bi_size; | |
1027 | u16 i; | |
1028 | ||
1029 | /* ring already cleared, nothing to do */ | |
1030 | if (!rx_ring->rx_bi) | |
1031 | return; | |
1032 | ||
a132af24 MW |
1033 | if (ring_is_ps_enabled(rx_ring)) { |
1034 | int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count; | |
1035 | ||
1036 | rx_bi = &rx_ring->rx_bi[0]; | |
1037 | if (rx_bi->hdr_buf) { | |
1038 | dma_free_coherent(dev, | |
1039 | bufsz, | |
1040 | rx_bi->hdr_buf, | |
1041 | rx_bi->dma); | |
1042 | for (i = 0; i < rx_ring->count; i++) { | |
1043 | rx_bi = &rx_ring->rx_bi[i]; | |
1044 | rx_bi->dma = 0; | |
37a2973a | 1045 | rx_bi->hdr_buf = NULL; |
a132af24 MW |
1046 | } |
1047 | } | |
1048 | } | |
fd0a05ce JB |
1049 | /* Free all the Rx ring sk_buffs */ |
1050 | for (i = 0; i < rx_ring->count; i++) { | |
1051 | rx_bi = &rx_ring->rx_bi[i]; | |
1052 | if (rx_bi->dma) { | |
1053 | dma_unmap_single(dev, | |
1054 | rx_bi->dma, | |
1055 | rx_ring->rx_buf_len, | |
1056 | DMA_FROM_DEVICE); | |
1057 | rx_bi->dma = 0; | |
1058 | } | |
1059 | if (rx_bi->skb) { | |
1060 | dev_kfree_skb(rx_bi->skb); | |
1061 | rx_bi->skb = NULL; | |
1062 | } | |
1063 | if (rx_bi->page) { | |
1064 | if (rx_bi->page_dma) { | |
1065 | dma_unmap_page(dev, | |
1066 | rx_bi->page_dma, | |
f16704e5 | 1067 | PAGE_SIZE, |
fd0a05ce JB |
1068 | DMA_FROM_DEVICE); |
1069 | rx_bi->page_dma = 0; | |
1070 | } | |
1071 | __free_page(rx_bi->page); | |
1072 | rx_bi->page = NULL; | |
1073 | rx_bi->page_offset = 0; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
1078 | memset(rx_ring->rx_bi, 0, bi_size); | |
1079 | ||
1080 | /* Zero out the descriptor ring */ | |
1081 | memset(rx_ring->desc, 0, rx_ring->size); | |
1082 | ||
1083 | rx_ring->next_to_clean = 0; | |
1084 | rx_ring->next_to_use = 0; | |
1085 | } | |
1086 | ||
1087 | /** | |
1088 | * i40e_free_rx_resources - Free Rx resources | |
1089 | * @rx_ring: ring to clean the resources from | |
1090 | * | |
1091 | * Free all receive software resources | |
1092 | **/ | |
1093 | void i40e_free_rx_resources(struct i40e_ring *rx_ring) | |
1094 | { | |
1095 | i40e_clean_rx_ring(rx_ring); | |
1096 | kfree(rx_ring->rx_bi); | |
1097 | rx_ring->rx_bi = NULL; | |
1098 | ||
1099 | if (rx_ring->desc) { | |
1100 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
1101 | rx_ring->desc, rx_ring->dma); | |
1102 | rx_ring->desc = NULL; | |
1103 | } | |
1104 | } | |
1105 | ||
a132af24 MW |
1106 | /** |
1107 | * i40e_alloc_rx_headers - allocate rx header buffers | |
1108 | * @rx_ring: ring to alloc buffers | |
1109 | * | |
1110 | * Allocate rx header buffers for the entire ring. As these are static, | |
1111 | * this is only called when setting up a new ring. | |
1112 | **/ | |
1113 | void i40e_alloc_rx_headers(struct i40e_ring *rx_ring) | |
1114 | { | |
1115 | struct device *dev = rx_ring->dev; | |
1116 | struct i40e_rx_buffer *rx_bi; | |
1117 | dma_addr_t dma; | |
1118 | void *buffer; | |
1119 | int buf_size; | |
1120 | int i; | |
1121 | ||
1122 | if (rx_ring->rx_bi[0].hdr_buf) | |
1123 | return; | |
1124 | /* Make sure the buffers don't cross cache line boundaries. */ | |
1125 | buf_size = ALIGN(rx_ring->rx_hdr_len, 256); | |
1126 | buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count, | |
1127 | &dma, GFP_KERNEL); | |
1128 | if (!buffer) | |
1129 | return; | |
1130 | for (i = 0; i < rx_ring->count; i++) { | |
1131 | rx_bi = &rx_ring->rx_bi[i]; | |
1132 | rx_bi->dma = dma + (i * buf_size); | |
1133 | rx_bi->hdr_buf = buffer + (i * buf_size); | |
1134 | } | |
1135 | } | |
1136 | ||
fd0a05ce JB |
1137 | /** |
1138 | * i40e_setup_rx_descriptors - Allocate Rx descriptors | |
1139 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
1140 | * | |
1141 | * Returns 0 on success, negative on failure | |
1142 | **/ | |
1143 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
1144 | { | |
1145 | struct device *dev = rx_ring->dev; | |
1146 | int bi_size; | |
1147 | ||
e908f815 JB |
1148 | /* warn if we are about to overwrite the pointer */ |
1149 | WARN_ON(rx_ring->rx_bi); | |
fd0a05ce JB |
1150 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
1151 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
1152 | if (!rx_ring->rx_bi) | |
1153 | goto err; | |
1154 | ||
f217d6ca | 1155 | u64_stats_init(&rx_ring->syncp); |
638702bd | 1156 | |
fd0a05ce JB |
1157 | /* Round up to nearest 4K */ |
1158 | rx_ring->size = ring_is_16byte_desc_enabled(rx_ring) | |
1159 | ? rx_ring->count * sizeof(union i40e_16byte_rx_desc) | |
1160 | : rx_ring->count * sizeof(union i40e_32byte_rx_desc); | |
1161 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
1162 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
1163 | &rx_ring->dma, GFP_KERNEL); | |
1164 | ||
1165 | if (!rx_ring->desc) { | |
1166 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
1167 | rx_ring->size); | |
1168 | goto err; | |
1169 | } | |
1170 | ||
1171 | rx_ring->next_to_clean = 0; | |
1172 | rx_ring->next_to_use = 0; | |
1173 | ||
1174 | return 0; | |
1175 | err: | |
1176 | kfree(rx_ring->rx_bi); | |
1177 | rx_ring->rx_bi = NULL; | |
1178 | return -ENOMEM; | |
1179 | } | |
1180 | ||
1181 | /** | |
1182 | * i40e_release_rx_desc - Store the new tail and head values | |
1183 | * @rx_ring: ring to bump | |
1184 | * @val: new head index | |
1185 | **/ | |
1186 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
1187 | { | |
1188 | rx_ring->next_to_use = val; | |
1189 | /* Force memory writes to complete before letting h/w | |
1190 | * know there are new descriptors to fetch. (Only | |
1191 | * applicable for weak-ordered memory model archs, | |
1192 | * such as IA-64). | |
1193 | */ | |
1194 | wmb(); | |
1195 | writel(val, rx_ring->tail); | |
1196 | } | |
1197 | ||
1198 | /** | |
a132af24 | 1199 | * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split |
fd0a05ce JB |
1200 | * @rx_ring: ring to place buffers on |
1201 | * @cleaned_count: number of buffers to replace | |
c2e245ab JB |
1202 | * |
1203 | * Returns true if any errors on allocation | |
fd0a05ce | 1204 | **/ |
c2e245ab | 1205 | bool i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count) |
a132af24 MW |
1206 | { |
1207 | u16 i = rx_ring->next_to_use; | |
1208 | union i40e_rx_desc *rx_desc; | |
1209 | struct i40e_rx_buffer *bi; | |
f16704e5 | 1210 | const int current_node = numa_node_id(); |
a132af24 MW |
1211 | |
1212 | /* do nothing if no valid netdev defined */ | |
1213 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 1214 | return false; |
a132af24 MW |
1215 | |
1216 | while (cleaned_count--) { | |
1217 | rx_desc = I40E_RX_DESC(rx_ring, i); | |
1218 | bi = &rx_ring->rx_bi[i]; | |
1219 | ||
1220 | if (bi->skb) /* desc is in use */ | |
1221 | goto no_buffers; | |
f16704e5 MW |
1222 | |
1223 | /* If we've been moved to a different NUMA node, release the | |
1224 | * page so we can get a new one on the current node. | |
1225 | */ | |
1226 | if (bi->page && page_to_nid(bi->page) != current_node) { | |
1227 | dma_unmap_page(rx_ring->dev, | |
1228 | bi->page_dma, | |
1229 | PAGE_SIZE, | |
1230 | DMA_FROM_DEVICE); | |
1231 | __free_page(bi->page); | |
1232 | bi->page = NULL; | |
1233 | bi->page_dma = 0; | |
1234 | rx_ring->rx_stats.realloc_count++; | |
1235 | } else if (bi->page) { | |
1236 | rx_ring->rx_stats.page_reuse_count++; | |
1237 | } | |
1238 | ||
a132af24 MW |
1239 | if (!bi->page) { |
1240 | bi->page = alloc_page(GFP_ATOMIC); | |
1241 | if (!bi->page) { | |
1242 | rx_ring->rx_stats.alloc_page_failed++; | |
1243 | goto no_buffers; | |
1244 | } | |
a132af24 MW |
1245 | bi->page_dma = dma_map_page(rx_ring->dev, |
1246 | bi->page, | |
f16704e5 MW |
1247 | 0, |
1248 | PAGE_SIZE, | |
a132af24 | 1249 | DMA_FROM_DEVICE); |
f16704e5 | 1250 | if (dma_mapping_error(rx_ring->dev, bi->page_dma)) { |
a132af24 | 1251 | rx_ring->rx_stats.alloc_page_failed++; |
f16704e5 MW |
1252 | __free_page(bi->page); |
1253 | bi->page = NULL; | |
a132af24 | 1254 | bi->page_dma = 0; |
f16704e5 | 1255 | bi->page_offset = 0; |
a132af24 MW |
1256 | goto no_buffers; |
1257 | } | |
f16704e5 | 1258 | bi->page_offset = 0; |
a132af24 MW |
1259 | } |
1260 | ||
a132af24 MW |
1261 | /* Refresh the desc even if buffer_addrs didn't change |
1262 | * because each write-back erases this info. | |
1263 | */ | |
f16704e5 MW |
1264 | rx_desc->read.pkt_addr = |
1265 | cpu_to_le64(bi->page_dma + bi->page_offset); | |
a132af24 MW |
1266 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); |
1267 | i++; | |
1268 | if (i == rx_ring->count) | |
1269 | i = 0; | |
1270 | } | |
1271 | ||
c2e245ab JB |
1272 | if (rx_ring->next_to_use != i) |
1273 | i40e_release_rx_desc(rx_ring, i); | |
1274 | ||
1275 | return false; | |
1276 | ||
a132af24 MW |
1277 | no_buffers: |
1278 | if (rx_ring->next_to_use != i) | |
1279 | i40e_release_rx_desc(rx_ring, i); | |
c2e245ab JB |
1280 | |
1281 | /* make sure to come back via polling to try again after | |
1282 | * allocation failure | |
1283 | */ | |
1284 | return true; | |
a132af24 MW |
1285 | } |
1286 | ||
1287 | /** | |
1288 | * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer | |
1289 | * @rx_ring: ring to place buffers on | |
1290 | * @cleaned_count: number of buffers to replace | |
c2e245ab JB |
1291 | * |
1292 | * Returns true if any errors on allocation | |
a132af24 | 1293 | **/ |
c2e245ab | 1294 | bool i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count) |
fd0a05ce JB |
1295 | { |
1296 | u16 i = rx_ring->next_to_use; | |
1297 | union i40e_rx_desc *rx_desc; | |
1298 | struct i40e_rx_buffer *bi; | |
1299 | struct sk_buff *skb; | |
1300 | ||
1301 | /* do nothing if no valid netdev defined */ | |
1302 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 1303 | return false; |
fd0a05ce JB |
1304 | |
1305 | while (cleaned_count--) { | |
1306 | rx_desc = I40E_RX_DESC(rx_ring, i); | |
1307 | bi = &rx_ring->rx_bi[i]; | |
1308 | skb = bi->skb; | |
1309 | ||
1310 | if (!skb) { | |
dd1a5df8 JB |
1311 | skb = __netdev_alloc_skb_ip_align(rx_ring->netdev, |
1312 | rx_ring->rx_buf_len, | |
1313 | GFP_ATOMIC | | |
1314 | __GFP_NOWARN); | |
fd0a05ce | 1315 | if (!skb) { |
420136cc | 1316 | rx_ring->rx_stats.alloc_buff_failed++; |
fd0a05ce JB |
1317 | goto no_buffers; |
1318 | } | |
1319 | /* initialize queue mapping */ | |
1320 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
1321 | bi->skb = skb; | |
1322 | } | |
1323 | ||
1324 | if (!bi->dma) { | |
1325 | bi->dma = dma_map_single(rx_ring->dev, | |
1326 | skb->data, | |
1327 | rx_ring->rx_buf_len, | |
1328 | DMA_FROM_DEVICE); | |
1329 | if (dma_mapping_error(rx_ring->dev, bi->dma)) { | |
420136cc | 1330 | rx_ring->rx_stats.alloc_buff_failed++; |
fd0a05ce | 1331 | bi->dma = 0; |
c2e245ab JB |
1332 | dev_kfree_skb(bi->skb); |
1333 | bi->skb = NULL; | |
fd0a05ce JB |
1334 | goto no_buffers; |
1335 | } | |
1336 | } | |
1337 | ||
a132af24 MW |
1338 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
1339 | rx_desc->read.hdr_addr = 0; | |
fd0a05ce JB |
1340 | i++; |
1341 | if (i == rx_ring->count) | |
1342 | i = 0; | |
1343 | } | |
1344 | ||
c2e245ab JB |
1345 | if (rx_ring->next_to_use != i) |
1346 | i40e_release_rx_desc(rx_ring, i); | |
1347 | ||
1348 | return false; | |
1349 | ||
fd0a05ce JB |
1350 | no_buffers: |
1351 | if (rx_ring->next_to_use != i) | |
1352 | i40e_release_rx_desc(rx_ring, i); | |
c2e245ab JB |
1353 | |
1354 | /* make sure to come back via polling to try again after | |
1355 | * allocation failure | |
1356 | */ | |
1357 | return true; | |
fd0a05ce JB |
1358 | } |
1359 | ||
1360 | /** | |
1361 | * i40e_receive_skb - Send a completed packet up the stack | |
1362 | * @rx_ring: rx ring in play | |
1363 | * @skb: packet to send up | |
1364 | * @vlan_tag: vlan tag for packet | |
1365 | **/ | |
1366 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
1367 | struct sk_buff *skb, u16 vlan_tag) | |
1368 | { | |
1369 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
fd0a05ce JB |
1370 | |
1371 | if (vlan_tag & VLAN_VID_MASK) | |
1372 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
1373 | ||
8b650359 | 1374 | napi_gro_receive(&q_vector->napi, skb); |
fd0a05ce JB |
1375 | } |
1376 | ||
1377 | /** | |
1378 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
1379 | * @vsi: the VSI we care about | |
1380 | * @skb: skb currently being received and modified | |
1381 | * @rx_status: status value of last descriptor in packet | |
1382 | * @rx_error: error value of last descriptor in packet | |
8144f0f7 | 1383 | * @rx_ptype: ptype value of last descriptor in packet |
fd0a05ce JB |
1384 | **/ |
1385 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
1386 | struct sk_buff *skb, | |
1387 | u32 rx_status, | |
8144f0f7 JG |
1388 | u32 rx_error, |
1389 | u16 rx_ptype) | |
fd0a05ce | 1390 | { |
8a3c91cc | 1391 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype); |
fad57330 | 1392 | bool ipv4, ipv6, ipv4_tunnel, ipv6_tunnel; |
8144f0f7 | 1393 | |
fd0a05ce JB |
1394 | skb->ip_summed = CHECKSUM_NONE; |
1395 | ||
1396 | /* Rx csum enabled and ip headers found? */ | |
8a3c91cc JB |
1397 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
1398 | return; | |
1399 | ||
1400 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 1401 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
1402 | return; |
1403 | ||
1404 | /* both known and outer_ip must be set for the below code to work */ | |
1405 | if (!(decoded.known && decoded.outer_ip)) | |
fd0a05ce JB |
1406 | return; |
1407 | ||
fad57330 AD |
1408 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
1409 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
1410 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
1411 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
1412 | |
1413 | if (ipv4 && | |
41a1d04b JB |
1414 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
1415 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
1416 | goto checksum_fail; |
1417 | ||
ddf1d0d7 | 1418 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 1419 | if (ipv6 && |
41a1d04b | 1420 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 1421 | /* don't increment checksum err here, non-fatal err */ |
8ee75a8e SN |
1422 | return; |
1423 | ||
8a3c91cc | 1424 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 1425 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
1426 | goto checksum_fail; |
1427 | ||
1428 | /* handle packets that were not able to be checksummed due | |
1429 | * to arrival speed, in this case the stack can compute | |
1430 | * the csum. | |
1431 | */ | |
41a1d04b | 1432 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
fd0a05ce | 1433 | return; |
fd0a05ce | 1434 | |
a9c9a81f AD |
1435 | /* The hardware supported by this driver does not validate outer |
1436 | * checksums for tunneled VXLAN or GENEVE frames. I don't agree | |
1437 | * with it but the specification states that you "MAY validate", it | |
1438 | * doesn't make it a hard requirement so if we have validated the | |
1439 | * inner checksum report CHECKSUM_UNNECESSARY. | |
8a3c91cc | 1440 | */ |
8144f0f7 | 1441 | |
fad57330 AD |
1442 | ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) && |
1443 | (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4); | |
1444 | ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) && | |
1445 | (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4); | |
1446 | ||
fd0a05ce | 1447 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
fa4ba69b | 1448 | skb->csum_level = ipv4_tunnel || ipv6_tunnel; |
8a3c91cc JB |
1449 | |
1450 | return; | |
1451 | ||
1452 | checksum_fail: | |
1453 | vsi->back->hw_csum_rx_error++; | |
fd0a05ce JB |
1454 | } |
1455 | ||
1456 | /** | |
857942fd | 1457 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
1458 | * @ptype: the ptype value from the descriptor |
1459 | * | |
1460 | * Returns a hash type to be used by skb_set_hash | |
1461 | **/ | |
857942fd | 1462 | static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
1463 | { |
1464 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
1465 | ||
1466 | if (!decoded.known) | |
1467 | return PKT_HASH_TYPE_NONE; | |
1468 | ||
1469 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1470 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
1471 | return PKT_HASH_TYPE_L4; | |
1472 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
1473 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
1474 | return PKT_HASH_TYPE_L3; | |
1475 | else | |
1476 | return PKT_HASH_TYPE_L2; | |
1477 | } | |
1478 | ||
857942fd ASJ |
1479 | /** |
1480 | * i40e_rx_hash - set the hash value in the skb | |
1481 | * @ring: descriptor ring | |
1482 | * @rx_desc: specific descriptor | |
1483 | **/ | |
1484 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
1485 | union i40e_rx_desc *rx_desc, | |
1486 | struct sk_buff *skb, | |
1487 | u8 rx_ptype) | |
1488 | { | |
1489 | u32 hash; | |
1490 | const __le64 rss_mask = | |
1491 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << | |
1492 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
1493 | ||
1494 | if (ring->netdev->features & NETIF_F_RXHASH) | |
1495 | return; | |
1496 | ||
1497 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
1498 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
1499 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
1500 | } | |
1501 | } | |
1502 | ||
fd0a05ce | 1503 | /** |
a132af24 | 1504 | * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split |
fd0a05ce JB |
1505 | * @rx_ring: rx ring to clean |
1506 | * @budget: how many cleans we're allowed | |
1507 | * | |
1508 | * Returns true if there's any budget left (e.g. the clean is finished) | |
1509 | **/ | |
c2e245ab | 1510 | static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget) |
fd0a05ce JB |
1511 | { |
1512 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
1513 | u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo; | |
1514 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); | |
fd0a05ce JB |
1515 | struct i40e_vsi *vsi = rx_ring->vsi; |
1516 | u16 i = rx_ring->next_to_clean; | |
1517 | union i40e_rx_desc *rx_desc; | |
1518 | u32 rx_error, rx_status; | |
c2e245ab | 1519 | bool failure = false; |
206812b5 | 1520 | u8 rx_ptype; |
fd0a05ce | 1521 | u64 qword; |
f16704e5 | 1522 | u32 copysize; |
fd0a05ce | 1523 | |
390f86df EB |
1524 | if (budget <= 0) |
1525 | return 0; | |
1526 | ||
a132af24 | 1527 | do { |
fd0a05ce JB |
1528 | struct i40e_rx_buffer *rx_bi; |
1529 | struct sk_buff *skb; | |
1530 | u16 vlan_tag; | |
a132af24 MW |
1531 | /* return some buffers to hardware, one at a time is too slow */ |
1532 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab JB |
1533 | failure = failure || |
1534 | i40e_alloc_rx_buffers_ps(rx_ring, | |
1535 | cleaned_count); | |
a132af24 MW |
1536 | cleaned_count = 0; |
1537 | } | |
1538 | ||
1539 | i = rx_ring->next_to_clean; | |
1540 | rx_desc = I40E_RX_DESC(rx_ring, i); | |
1541 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1542 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1543 | I40E_RXD_QW1_STATUS_SHIFT; | |
1544 | ||
41a1d04b | 1545 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) |
a132af24 MW |
1546 | break; |
1547 | ||
1548 | /* This memory barrier is needed to keep us from reading | |
1549 | * any other fields out of the rx_desc until we know the | |
1550 | * DD bit is set. | |
1551 | */ | |
67317166 | 1552 | dma_rmb(); |
f16704e5 MW |
1553 | /* sync header buffer for reading */ |
1554 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1555 | rx_ring->rx_bi[0].dma, | |
1556 | i * rx_ring->rx_hdr_len, | |
1557 | rx_ring->rx_hdr_len, | |
1558 | DMA_FROM_DEVICE); | |
fd0a05ce JB |
1559 | if (i40e_rx_is_programming_status(qword)) { |
1560 | i40e_clean_programming_status(rx_ring, rx_desc); | |
a132af24 MW |
1561 | I40E_RX_INCREMENT(rx_ring, i); |
1562 | continue; | |
fd0a05ce JB |
1563 | } |
1564 | rx_bi = &rx_ring->rx_bi[i]; | |
1565 | skb = rx_bi->skb; | |
a132af24 | 1566 | if (likely(!skb)) { |
dd1a5df8 JB |
1567 | skb = __netdev_alloc_skb_ip_align(rx_ring->netdev, |
1568 | rx_ring->rx_hdr_len, | |
1569 | GFP_ATOMIC | | |
1570 | __GFP_NOWARN); | |
8b6ed9c2 | 1571 | if (!skb) { |
a132af24 | 1572 | rx_ring->rx_stats.alloc_buff_failed++; |
c2e245ab | 1573 | failure = true; |
8b6ed9c2 JB |
1574 | break; |
1575 | } | |
1576 | ||
a132af24 MW |
1577 | /* initialize queue mapping */ |
1578 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
1579 | /* we are reusing so sync this buffer for CPU use */ | |
1580 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
3578fa0a JB |
1581 | rx_ring->rx_bi[0].dma, |
1582 | i * rx_ring->rx_hdr_len, | |
a132af24 MW |
1583 | rx_ring->rx_hdr_len, |
1584 | DMA_FROM_DEVICE); | |
1585 | } | |
829af3ac MW |
1586 | rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> |
1587 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1588 | rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >> | |
1589 | I40E_RXD_QW1_LENGTH_HBUF_SHIFT; | |
1590 | rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >> | |
1591 | I40E_RXD_QW1_LENGTH_SPH_SHIFT; | |
1592 | ||
1593 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
1594 | I40E_RXD_QW1_ERROR_SHIFT; | |
41a1d04b JB |
1595 | rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT); |
1596 | rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT); | |
fd0a05ce | 1597 | |
8144f0f7 JG |
1598 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> |
1599 | I40E_RXD_QW1_PTYPE_SHIFT; | |
f16704e5 MW |
1600 | /* sync half-page for reading */ |
1601 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1602 | rx_bi->page_dma, | |
1603 | rx_bi->page_offset, | |
1604 | PAGE_SIZE / 2, | |
1605 | DMA_FROM_DEVICE); | |
1606 | prefetch(page_address(rx_bi->page) + rx_bi->page_offset); | |
fd0a05ce | 1607 | rx_bi->skb = NULL; |
a132af24 | 1608 | cleaned_count++; |
f16704e5 | 1609 | copysize = 0; |
a132af24 MW |
1610 | if (rx_hbo || rx_sph) { |
1611 | int len; | |
6995b36c | 1612 | |
fd0a05ce JB |
1613 | if (rx_hbo) |
1614 | len = I40E_RX_HDR_SIZE; | |
fd0a05ce | 1615 | else |
a132af24 MW |
1616 | len = rx_header_len; |
1617 | memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len); | |
1618 | } else if (skb->len == 0) { | |
1619 | int len; | |
f16704e5 MW |
1620 | unsigned char *va = page_address(rx_bi->page) + |
1621 | rx_bi->page_offset; | |
a132af24 | 1622 | |
f16704e5 MW |
1623 | len = min(rx_packet_len, rx_ring->rx_hdr_len); |
1624 | memcpy(__skb_put(skb, len), va, len); | |
1625 | copysize = len; | |
a132af24 | 1626 | rx_packet_len -= len; |
fd0a05ce | 1627 | } |
fd0a05ce | 1628 | /* Get the rest of the data if this was a header split */ |
a132af24 | 1629 | if (rx_packet_len) { |
f16704e5 MW |
1630 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, |
1631 | rx_bi->page, | |
1632 | rx_bi->page_offset + copysize, | |
1633 | rx_packet_len, I40E_RXBUFFER_2048); | |
1634 | ||
f16704e5 MW |
1635 | /* If the page count is more than 2, then both halves |
1636 | * of the page are used and we need to free it. Do it | |
1637 | * here instead of in the alloc code. Otherwise one | |
1638 | * of the half-pages might be released between now and | |
1639 | * then, and we wouldn't know which one to use. | |
16fd08b8 MW |
1640 | * Don't call get_page and free_page since those are |
1641 | * both expensive atomic operations that just change | |
1642 | * the refcount in opposite directions. Just give the | |
1643 | * page to the stack; he can have our refcount. | |
f16704e5 MW |
1644 | */ |
1645 | if (page_count(rx_bi->page) > 2) { | |
1646 | dma_unmap_page(rx_ring->dev, | |
1647 | rx_bi->page_dma, | |
1648 | PAGE_SIZE, | |
1649 | DMA_FROM_DEVICE); | |
fd0a05ce | 1650 | rx_bi->page = NULL; |
f16704e5 MW |
1651 | rx_bi->page_dma = 0; |
1652 | rx_ring->rx_stats.realloc_count++; | |
16fd08b8 MW |
1653 | } else { |
1654 | get_page(rx_bi->page); | |
1655 | /* switch to the other half-page here; the | |
1656 | * allocation code programs the right addr | |
1657 | * into HW. If we haven't used this half-page, | |
1658 | * the address won't be changed, and HW can | |
1659 | * just use it next time through. | |
1660 | */ | |
1661 | rx_bi->page_offset ^= PAGE_SIZE / 2; | |
f16704e5 | 1662 | } |
fd0a05ce | 1663 | |
fd0a05ce | 1664 | } |
a132af24 | 1665 | I40E_RX_INCREMENT(rx_ring, i); |
fd0a05ce JB |
1666 | |
1667 | if (unlikely( | |
41a1d04b | 1668 | !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) { |
fd0a05ce JB |
1669 | struct i40e_rx_buffer *next_buffer; |
1670 | ||
1671 | next_buffer = &rx_ring->rx_bi[i]; | |
a132af24 | 1672 | next_buffer->skb = skb; |
fd0a05ce | 1673 | rx_ring->rx_stats.non_eop_descs++; |
a132af24 | 1674 | continue; |
fd0a05ce JB |
1675 | } |
1676 | ||
1677 | /* ERR_MASK will only have valid bits if EOP set */ | |
41a1d04b | 1678 | if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) { |
fd0a05ce | 1679 | dev_kfree_skb_any(skb); |
a132af24 | 1680 | continue; |
fd0a05ce JB |
1681 | } |
1682 | ||
857942fd ASJ |
1683 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); |
1684 | ||
beb0dff1 JK |
1685 | if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) { |
1686 | i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status & | |
1687 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> | |
1688 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT); | |
1689 | rx_ring->last_rx_timestamp = jiffies; | |
1690 | } | |
1691 | ||
fd0a05ce JB |
1692 | /* probably a little skewed due to removing CRC */ |
1693 | total_rx_bytes += skb->len; | |
1694 | total_rx_packets++; | |
1695 | ||
1696 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
8144f0f7 JG |
1697 | |
1698 | i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype); | |
1699 | ||
41a1d04b | 1700 | vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) |
fd0a05ce JB |
1701 | ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) |
1702 | : 0; | |
38e00438 VD |
1703 | #ifdef I40E_FCOE |
1704 | if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) { | |
1705 | dev_kfree_skb_any(skb); | |
a132af24 | 1706 | continue; |
38e00438 VD |
1707 | } |
1708 | #endif | |
fd0a05ce JB |
1709 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
1710 | ||
fd0a05ce | 1711 | rx_desc->wb.qword1.status_error_len = 0; |
fd0a05ce | 1712 | |
a132af24 MW |
1713 | } while (likely(total_rx_packets < budget)); |
1714 | ||
1715 | u64_stats_update_begin(&rx_ring->syncp); | |
1716 | rx_ring->stats.packets += total_rx_packets; | |
1717 | rx_ring->stats.bytes += total_rx_bytes; | |
1718 | u64_stats_update_end(&rx_ring->syncp); | |
1719 | rx_ring->q_vector->rx.total_packets += total_rx_packets; | |
1720 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1721 | ||
c2e245ab | 1722 | return failure ? budget : total_rx_packets; |
a132af24 MW |
1723 | } |
1724 | ||
1725 | /** | |
1726 | * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer | |
1727 | * @rx_ring: rx ring to clean | |
1728 | * @budget: how many cleans we're allowed | |
1729 | * | |
1730 | * Returns number of packets cleaned | |
1731 | **/ | |
1732 | static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget) | |
1733 | { | |
1734 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
1735 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); | |
1736 | struct i40e_vsi *vsi = rx_ring->vsi; | |
1737 | union i40e_rx_desc *rx_desc; | |
1738 | u32 rx_error, rx_status; | |
1739 | u16 rx_packet_len; | |
c2e245ab | 1740 | bool failure = false; |
a132af24 MW |
1741 | u8 rx_ptype; |
1742 | u64 qword; | |
1743 | u16 i; | |
1744 | ||
1745 | do { | |
1746 | struct i40e_rx_buffer *rx_bi; | |
1747 | struct sk_buff *skb; | |
1748 | u16 vlan_tag; | |
fd0a05ce JB |
1749 | /* return some buffers to hardware, one at a time is too slow */ |
1750 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab JB |
1751 | failure = failure || |
1752 | i40e_alloc_rx_buffers_1buf(rx_ring, | |
1753 | cleaned_count); | |
fd0a05ce JB |
1754 | cleaned_count = 0; |
1755 | } | |
1756 | ||
a132af24 MW |
1757 | i = rx_ring->next_to_clean; |
1758 | rx_desc = I40E_RX_DESC(rx_ring, i); | |
fd0a05ce | 1759 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
829af3ac | 1760 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> |
a132af24 MW |
1761 | I40E_RXD_QW1_STATUS_SHIFT; |
1762 | ||
41a1d04b | 1763 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) |
a132af24 MW |
1764 | break; |
1765 | ||
1766 | /* This memory barrier is needed to keep us from reading | |
1767 | * any other fields out of the rx_desc until we know the | |
1768 | * DD bit is set. | |
1769 | */ | |
67317166 | 1770 | dma_rmb(); |
a132af24 MW |
1771 | |
1772 | if (i40e_rx_is_programming_status(qword)) { | |
1773 | i40e_clean_programming_status(rx_ring, rx_desc); | |
1774 | I40E_RX_INCREMENT(rx_ring, i); | |
1775 | continue; | |
1776 | } | |
1777 | rx_bi = &rx_ring->rx_bi[i]; | |
1778 | skb = rx_bi->skb; | |
1779 | prefetch(skb->data); | |
1780 | ||
1781 | rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> | |
1782 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1783 | ||
1784 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
1785 | I40E_RXD_QW1_ERROR_SHIFT; | |
41a1d04b | 1786 | rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT); |
a132af24 MW |
1787 | |
1788 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> | |
1789 | I40E_RXD_QW1_PTYPE_SHIFT; | |
1790 | rx_bi->skb = NULL; | |
1791 | cleaned_count++; | |
1792 | ||
1793 | /* Get the header and possibly the whole packet | |
1794 | * If this is an skb from previous receive dma will be 0 | |
1795 | */ | |
1796 | skb_put(skb, rx_packet_len); | |
1797 | dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len, | |
1798 | DMA_FROM_DEVICE); | |
1799 | rx_bi->dma = 0; | |
1800 | ||
1801 | I40E_RX_INCREMENT(rx_ring, i); | |
1802 | ||
1803 | if (unlikely( | |
41a1d04b | 1804 | !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) { |
a132af24 MW |
1805 | rx_ring->rx_stats.non_eop_descs++; |
1806 | continue; | |
1807 | } | |
1808 | ||
1809 | /* ERR_MASK will only have valid bits if EOP set */ | |
41a1d04b | 1810 | if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) { |
a132af24 | 1811 | dev_kfree_skb_any(skb); |
a132af24 MW |
1812 | continue; |
1813 | } | |
1814 | ||
857942fd | 1815 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); |
a132af24 MW |
1816 | if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) { |
1817 | i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status & | |
1818 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> | |
1819 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT); | |
1820 | rx_ring->last_rx_timestamp = jiffies; | |
1821 | } | |
1822 | ||
1823 | /* probably a little skewed due to removing CRC */ | |
1824 | total_rx_bytes += skb->len; | |
1825 | total_rx_packets++; | |
1826 | ||
1827 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
1828 | ||
1829 | i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype); | |
1830 | ||
41a1d04b | 1831 | vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) |
a132af24 MW |
1832 | ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) |
1833 | : 0; | |
1834 | #ifdef I40E_FCOE | |
1835 | if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) { | |
1836 | dev_kfree_skb_any(skb); | |
1837 | continue; | |
1838 | } | |
1839 | #endif | |
1840 | i40e_receive_skb(rx_ring, skb, vlan_tag); | |
1841 | ||
a132af24 MW |
1842 | rx_desc->wb.qword1.status_error_len = 0; |
1843 | } while (likely(total_rx_packets < budget)); | |
fd0a05ce | 1844 | |
980e9b11 | 1845 | u64_stats_update_begin(&rx_ring->syncp); |
a114d0a6 AD |
1846 | rx_ring->stats.packets += total_rx_packets; |
1847 | rx_ring->stats.bytes += total_rx_bytes; | |
980e9b11 | 1848 | u64_stats_update_end(&rx_ring->syncp); |
fd0a05ce JB |
1849 | rx_ring->q_vector->rx.total_packets += total_rx_packets; |
1850 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1851 | ||
c2e245ab | 1852 | return failure ? budget : total_rx_packets; |
fd0a05ce JB |
1853 | } |
1854 | ||
8f5e39ce JB |
1855 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
1856 | { | |
1857 | u32 val; | |
1858 | ||
1859 | val = I40E_PFINT_DYN_CTLN_INTENA_MASK | | |
40d72a50 JB |
1860 | /* Don't clear PBA because that can cause lost interrupts that |
1861 | * came in while we were cleaning/polling | |
1862 | */ | |
8f5e39ce JB |
1863 | (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | |
1864 | (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); | |
1865 | ||
1866 | return val; | |
1867 | } | |
1868 | ||
1869 | /* a small macro to shorten up some long lines */ | |
1870 | #define INTREG I40E_PFINT_DYN_CTLN | |
1871 | ||
de32e3ef CW |
1872 | /** |
1873 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
1874 | * @vsi: the VSI we care about | |
1875 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
1876 | * | |
1877 | **/ | |
1878 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
1879 | struct i40e_q_vector *q_vector) | |
1880 | { | |
1881 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
1882 | bool rx = false, tx = false; |
1883 | u32 rxval, txval; | |
de32e3ef | 1884 | int vector; |
de32e3ef CW |
1885 | |
1886 | vector = (q_vector->v_idx + vsi->base_vector); | |
8f5e39ce | 1887 | |
ee2319cf JB |
1888 | /* avoid dynamic calculation if in countdown mode OR if |
1889 | * all dynamic is disabled | |
1890 | */ | |
8f5e39ce JB |
1891 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
1892 | ||
ee2319cf JB |
1893 | if (q_vector->itr_countdown > 0 || |
1894 | (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) && | |
1895 | !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) { | |
1896 | goto enable_int; | |
1897 | } | |
1898 | ||
de32e3ef | 1899 | if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) { |
8f5e39ce JB |
1900 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
1901 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 1902 | } |
8f5e39ce | 1903 | |
de32e3ef | 1904 | if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) { |
8f5e39ce JB |
1905 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
1906 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
de32e3ef | 1907 | } |
8f5e39ce JB |
1908 | |
1909 | if (rx || tx) { | |
1910 | /* get the higher of the two ITR adjustments and | |
1911 | * use the same value for both ITR registers | |
1912 | * when in adaptive mode (Rx and/or Tx) | |
1913 | */ | |
1914 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
1915 | ||
1916 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
1917 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
1918 | tx = true; | |
1919 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
1920 | rx = true; | |
1921 | } | |
1922 | ||
1923 | /* only need to enable the interrupt once, but need | |
1924 | * to possibly update both ITR values | |
1925 | */ | |
1926 | if (rx) { | |
1927 | /* set the INTENA_MSK_MASK so that this first write | |
1928 | * won't actually enable the interrupt, instead just | |
1929 | * updating the ITR (it's bit 31 PF and VF) | |
1930 | */ | |
1931 | rxval |= BIT(31); | |
1932 | /* don't check _DOWN because interrupt isn't being enabled */ | |
1933 | wr32(hw, INTREG(vector - 1), rxval); | |
1934 | } | |
1935 | ||
ee2319cf | 1936 | enable_int: |
8f5e39ce JB |
1937 | if (!test_bit(__I40E_DOWN, &vsi->state)) |
1938 | wr32(hw, INTREG(vector - 1), txval); | |
ee2319cf JB |
1939 | |
1940 | if (q_vector->itr_countdown) | |
1941 | q_vector->itr_countdown--; | |
1942 | else | |
1943 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
1944 | } |
1945 | ||
fd0a05ce JB |
1946 | /** |
1947 | * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1948 | * @napi: napi struct with our devices info in it | |
1949 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1950 | * | |
1951 | * This function will clean all queues associated with a q_vector. | |
1952 | * | |
1953 | * Returns the amount of work done | |
1954 | **/ | |
1955 | int i40e_napi_poll(struct napi_struct *napi, int budget) | |
1956 | { | |
1957 | struct i40e_q_vector *q_vector = | |
1958 | container_of(napi, struct i40e_q_vector, napi); | |
1959 | struct i40e_vsi *vsi = q_vector->vsi; | |
cd0b6fa6 | 1960 | struct i40e_ring *ring; |
fd0a05ce | 1961 | bool clean_complete = true; |
d91649f5 | 1962 | bool arm_wb = false; |
fd0a05ce | 1963 | int budget_per_ring; |
32b3e08f | 1964 | int work_done = 0; |
fd0a05ce JB |
1965 | |
1966 | if (test_bit(__I40E_DOWN, &vsi->state)) { | |
1967 | napi_complete(napi); | |
1968 | return 0; | |
1969 | } | |
1970 | ||
9c6c1259 KP |
1971 | /* Clear hung_detected bit */ |
1972 | clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected); | |
cd0b6fa6 AD |
1973 | /* Since the actual Tx work is minimal, we can give the Tx a larger |
1974 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1975 | */ | |
d91649f5 | 1976 | i40e_for_each_ring(ring, q_vector->tx) { |
1a36d7fa MW |
1977 | clean_complete = clean_complete && |
1978 | i40e_clean_tx_irq(ring, vsi->work_limit); | |
44cdb791 | 1979 | arm_wb = arm_wb || ring->arm_wb; |
0deda868 | 1980 | ring->arm_wb = false; |
d91649f5 | 1981 | } |
cd0b6fa6 | 1982 | |
c67caceb AD |
1983 | /* Handle case where we are called by netpoll with a budget of 0 */ |
1984 | if (budget <= 0) | |
1985 | goto tx_only; | |
1986 | ||
fd0a05ce JB |
1987 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
1988 | * allow the budget to go below 1 because that would exit polling early. | |
fd0a05ce JB |
1989 | */ |
1990 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
cd0b6fa6 | 1991 | |
a132af24 | 1992 | i40e_for_each_ring(ring, q_vector->rx) { |
32b3e08f JB |
1993 | int cleaned; |
1994 | ||
a132af24 MW |
1995 | if (ring_is_ps_enabled(ring)) |
1996 | cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring); | |
1997 | else | |
1998 | cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring); | |
32b3e08f JB |
1999 | |
2000 | work_done += cleaned; | |
a132af24 | 2001 | /* if we didn't clean as many as budgeted, we must be done */ |
1a36d7fa | 2002 | clean_complete = clean_complete && (budget_per_ring > cleaned); |
a132af24 | 2003 | } |
fd0a05ce JB |
2004 | |
2005 | /* If work not completed, return budget and polling will return */ | |
d91649f5 | 2006 | if (!clean_complete) { |
c67caceb | 2007 | tx_only: |
164c9f54 ASJ |
2008 | if (arm_wb) { |
2009 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
ecc6a239 | 2010 | i40e_enable_wb_on_itr(vsi, q_vector); |
164c9f54 | 2011 | } |
fd0a05ce | 2012 | return budget; |
d91649f5 | 2013 | } |
fd0a05ce | 2014 | |
8e0764b4 ASJ |
2015 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
2016 | q_vector->arm_wb_state = false; | |
2017 | ||
fd0a05ce | 2018 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 2019 | napi_complete_done(napi, work_done); |
de32e3ef CW |
2020 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { |
2021 | i40e_update_enable_itr(vsi, q_vector); | |
2022 | } else { /* Legacy mode */ | |
40d72a50 | 2023 | i40e_irq_dynamic_enable_icr0(vsi->back, false); |
fd0a05ce | 2024 | } |
fd0a05ce JB |
2025 | return 0; |
2026 | } | |
2027 | ||
2028 | /** | |
2029 | * i40e_atr - Add a Flow Director ATR filter | |
2030 | * @tx_ring: ring to add programming descriptor to | |
2031 | * @skb: send buffer | |
89232c3b | 2032 | * @tx_flags: send tx flags |
fd0a05ce JB |
2033 | **/ |
2034 | static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
6b037cd4 | 2035 | u32 tx_flags) |
fd0a05ce JB |
2036 | { |
2037 | struct i40e_filter_program_desc *fdir_desc; | |
2038 | struct i40e_pf *pf = tx_ring->vsi->back; | |
2039 | union { | |
2040 | unsigned char *network; | |
2041 | struct iphdr *ipv4; | |
2042 | struct ipv6hdr *ipv6; | |
2043 | } hdr; | |
2044 | struct tcphdr *th; | |
2045 | unsigned int hlen; | |
2046 | u32 flex_ptype, dtype_cmd; | |
6b037cd4 | 2047 | u8 l4_proto; |
fc4ac67b | 2048 | u16 i; |
fd0a05ce JB |
2049 | |
2050 | /* make sure ATR is enabled */ | |
60ea5f83 | 2051 | if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) |
fd0a05ce JB |
2052 | return; |
2053 | ||
04294e38 ASJ |
2054 | if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) |
2055 | return; | |
2056 | ||
fd0a05ce JB |
2057 | /* if sampling is disabled do nothing */ |
2058 | if (!tx_ring->atr_sample_rate) | |
2059 | return; | |
2060 | ||
6b037cd4 | 2061 | /* Currently only IPv4/IPv6 with TCP is supported */ |
89232c3b ASJ |
2062 | if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) |
2063 | return; | |
fd0a05ce | 2064 | |
6a899024 | 2065 | if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) { |
89232c3b ASJ |
2066 | /* snag network header to get L4 type and address */ |
2067 | hdr.network = skb_network_header(skb); | |
fd0a05ce | 2068 | |
6b037cd4 | 2069 | /* access ihl as u8 to avoid unaligned access on ia64 */ |
89232c3b ASJ |
2070 | if (tx_flags & I40E_TX_FLAGS_IPV4) |
2071 | hlen = (hdr.network[0] & 0x0F) << 2; | |
89232c3b | 2072 | else |
6b037cd4 | 2073 | hlen = sizeof(struct ipv6hdr); |
fd0a05ce | 2074 | } else { |
89232c3b ASJ |
2075 | hdr.network = skb_inner_network_header(skb); |
2076 | hlen = skb_inner_network_header_len(skb); | |
fd0a05ce JB |
2077 | } |
2078 | ||
6b037cd4 | 2079 | /* Note: tx_flags gets modified to reflect inner protocols in |
89232c3b ASJ |
2080 | * tx_enable_csum function if encap is enabled. |
2081 | */ | |
6b037cd4 AD |
2082 | l4_proto = (tx_flags & I40E_TX_FLAGS_IPV4) ? hdr.ipv4->protocol : |
2083 | hdr.ipv6->nexthdr; | |
2084 | if (l4_proto != IPPROTO_TCP) | |
89232c3b ASJ |
2085 | return; |
2086 | ||
fd0a05ce JB |
2087 | th = (struct tcphdr *)(hdr.network + hlen); |
2088 | ||
55a5e60b ASJ |
2089 | /* Due to lack of space, no more new filters can be programmed */ |
2090 | if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) | |
2091 | return; | |
72b74869 ASJ |
2092 | if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && |
2093 | (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) { | |
52eb95ef ASJ |
2094 | /* HW ATR eviction will take care of removing filters on FIN |
2095 | * and RST packets. | |
2096 | */ | |
2097 | if (th->fin || th->rst) | |
2098 | return; | |
2099 | } | |
55a5e60b ASJ |
2100 | |
2101 | tx_ring->atr_count++; | |
2102 | ||
ce806783 ASJ |
2103 | /* sample on all syn/fin/rst packets or once every atr sample rate */ |
2104 | if (!th->fin && | |
2105 | !th->syn && | |
2106 | !th->rst && | |
2107 | (tx_ring->atr_count < tx_ring->atr_sample_rate)) | |
fd0a05ce JB |
2108 | return; |
2109 | ||
2110 | tx_ring->atr_count = 0; | |
2111 | ||
2112 | /* grab the next descriptor */ | |
fc4ac67b AD |
2113 | i = tx_ring->next_to_use; |
2114 | fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); | |
2115 | ||
2116 | i++; | |
2117 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2118 | |
2119 | flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & | |
2120 | I40E_TXD_FLTR_QW0_QINDEX_MASK; | |
6b037cd4 | 2121 | flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? |
fd0a05ce JB |
2122 | (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << |
2123 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : | |
2124 | (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << | |
2125 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); | |
2126 | ||
2127 | flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; | |
2128 | ||
2129 | dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; | |
2130 | ||
ce806783 | 2131 | dtype_cmd |= (th->fin || th->rst) ? |
fd0a05ce JB |
2132 | (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << |
2133 | I40E_TXD_FLTR_QW1_PCMD_SHIFT) : | |
2134 | (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << | |
2135 | I40E_TXD_FLTR_QW1_PCMD_SHIFT); | |
2136 | ||
2137 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << | |
2138 | I40E_TXD_FLTR_QW1_DEST_SHIFT; | |
2139 | ||
2140 | dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << | |
2141 | I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; | |
2142 | ||
433c47de | 2143 | dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; |
6a899024 | 2144 | if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) |
60ccd45c ASJ |
2145 | dtype_cmd |= |
2146 | ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << | |
2147 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2148 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
2149 | else | |
2150 | dtype_cmd |= | |
2151 | ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << | |
2152 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & | |
2153 | I40E_TXD_FLTR_QW1_CNTINDEX_MASK; | |
433c47de | 2154 | |
72b74869 ASJ |
2155 | if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && |
2156 | (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) | |
52eb95ef ASJ |
2157 | dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; |
2158 | ||
fd0a05ce | 2159 | fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); |
99753ea6 | 2160 | fdir_desc->rsvd = cpu_to_le32(0); |
fd0a05ce | 2161 | fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); |
99753ea6 | 2162 | fdir_desc->fd_id = cpu_to_le32(0); |
fd0a05ce JB |
2163 | } |
2164 | ||
fd0a05ce JB |
2165 | /** |
2166 | * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW | |
2167 | * @skb: send buffer | |
2168 | * @tx_ring: ring to send buffer on | |
2169 | * @flags: the tx flags to be set | |
2170 | * | |
2171 | * Checks the skb and set up correspondingly several generic transmit flags | |
2172 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
2173 | * | |
2174 | * Returns error code indicate the frame should be dropped upon error and the | |
2175 | * otherwise returns 0 to indicate the flags has been set properly. | |
2176 | **/ | |
38e00438 | 2177 | #ifdef I40E_FCOE |
3e587cf3 | 2178 | inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, |
fd0a05ce JB |
2179 | struct i40e_ring *tx_ring, |
2180 | u32 *flags) | |
3e587cf3 JB |
2181 | #else |
2182 | static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, | |
2183 | struct i40e_ring *tx_ring, | |
2184 | u32 *flags) | |
38e00438 | 2185 | #endif |
fd0a05ce JB |
2186 | { |
2187 | __be16 protocol = skb->protocol; | |
2188 | u32 tx_flags = 0; | |
2189 | ||
31eaaccf GR |
2190 | if (protocol == htons(ETH_P_8021Q) && |
2191 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
2192 | /* When HW VLAN acceleration is turned off by the user the | |
2193 | * stack sets the protocol to 8021q so that the driver | |
2194 | * can take any steps required to support the SW only | |
2195 | * VLAN handling. In our case the driver doesn't need | |
2196 | * to take any further steps so just set the protocol | |
2197 | * to the encapsulated ethertype. | |
2198 | */ | |
2199 | skb->protocol = vlan_get_protocol(skb); | |
2200 | goto out; | |
2201 | } | |
2202 | ||
fd0a05ce | 2203 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
2204 | if (skb_vlan_tag_present(skb)) { |
2205 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
fd0a05ce JB |
2206 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
2207 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
0e2fe46c | 2208 | } else if (protocol == htons(ETH_P_8021Q)) { |
fd0a05ce | 2209 | struct vlan_hdr *vhdr, _vhdr; |
6995b36c | 2210 | |
fd0a05ce JB |
2211 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
2212 | if (!vhdr) | |
2213 | return -EINVAL; | |
2214 | ||
2215 | protocol = vhdr->h_vlan_encapsulated_proto; | |
2216 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
2217 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
2218 | } | |
2219 | ||
d40d00b1 NP |
2220 | if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) |
2221 | goto out; | |
2222 | ||
fd0a05ce | 2223 | /* Insert 802.1p priority into VLAN header */ |
38e00438 VD |
2224 | if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || |
2225 | (skb->priority != TC_PRIO_CONTROL)) { | |
fd0a05ce JB |
2226 | tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; |
2227 | tx_flags |= (skb->priority & 0x7) << | |
2228 | I40E_TX_FLAGS_VLAN_PRIO_SHIFT; | |
2229 | if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { | |
2230 | struct vlan_ethhdr *vhdr; | |
dd225bc6 FR |
2231 | int rc; |
2232 | ||
2233 | rc = skb_cow_head(skb, 0); | |
2234 | if (rc < 0) | |
2235 | return rc; | |
fd0a05ce JB |
2236 | vhdr = (struct vlan_ethhdr *)skb->data; |
2237 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
2238 | I40E_TX_FLAGS_VLAN_SHIFT); | |
2239 | } else { | |
2240 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; | |
2241 | } | |
2242 | } | |
d40d00b1 NP |
2243 | |
2244 | out: | |
fd0a05ce JB |
2245 | *flags = tx_flags; |
2246 | return 0; | |
2247 | } | |
2248 | ||
fd0a05ce JB |
2249 | /** |
2250 | * i40e_tso - set up the tso context descriptor | |
2251 | * @tx_ring: ptr to the ring to send | |
2252 | * @skb: ptr to the skb we're sending | |
fd0a05ce | 2253 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 2254 | * @cd_type_cmd_tso_mss: Quad Word 1 |
fd0a05ce JB |
2255 | * |
2256 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
2257 | **/ | |
2258 | static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
9c883bd3 | 2259 | u8 *hdr_len, u64 *cd_type_cmd_tso_mss) |
fd0a05ce | 2260 | { |
03f9d6a5 | 2261 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
2262 | union { |
2263 | struct iphdr *v4; | |
2264 | struct ipv6hdr *v6; | |
2265 | unsigned char *hdr; | |
2266 | } ip; | |
c49a7bc3 AD |
2267 | union { |
2268 | struct tcphdr *tcp; | |
5453205c | 2269 | struct udphdr *udp; |
c49a7bc3 AD |
2270 | unsigned char *hdr; |
2271 | } l4; | |
2272 | u32 paylen, l4_offset; | |
fd0a05ce | 2273 | int err; |
fd0a05ce | 2274 | |
e9f6563d SN |
2275 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2276 | return 0; | |
2277 | ||
fd0a05ce JB |
2278 | if (!skb_is_gso(skb)) |
2279 | return 0; | |
2280 | ||
dd225bc6 FR |
2281 | err = skb_cow_head(skb, 0); |
2282 | if (err < 0) | |
2283 | return err; | |
fd0a05ce | 2284 | |
c777019a AD |
2285 | ip.hdr = skb_network_header(skb); |
2286 | l4.hdr = skb_transport_header(skb); | |
df23075f | 2287 | |
c777019a AD |
2288 | /* initialize outer IP header fields */ |
2289 | if (ip.v4->version == 4) { | |
2290 | ip.v4->tot_len = 0; | |
2291 | ip.v4->check = 0; | |
c49a7bc3 | 2292 | } else { |
c777019a AD |
2293 | ip.v6->payload_len = 0; |
2294 | } | |
2295 | ||
5453205c AD |
2296 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_UDP_TUNNEL | SKB_GSO_GRE | |
2297 | SKB_GSO_UDP_TUNNEL_CSUM)) { | |
2298 | if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) { | |
2299 | /* determine offset of outer transport header */ | |
2300 | l4_offset = l4.hdr - skb->data; | |
2301 | ||
2302 | /* remove payload length from outer checksum */ | |
2303 | paylen = (__force u16)l4.udp->check; | |
2304 | paylen += ntohs(1) * (u16)~(skb->len - l4_offset); | |
2305 | l4.udp->check = ~csum_fold((__force __wsum)paylen); | |
2306 | } | |
2307 | ||
c777019a AD |
2308 | /* reset pointers to inner headers */ |
2309 | ip.hdr = skb_inner_network_header(skb); | |
2310 | l4.hdr = skb_inner_transport_header(skb); | |
2311 | ||
2312 | /* initialize inner IP header fields */ | |
2313 | if (ip.v4->version == 4) { | |
2314 | ip.v4->tot_len = 0; | |
2315 | ip.v4->check = 0; | |
2316 | } else { | |
2317 | ip.v6->payload_len = 0; | |
2318 | } | |
fd0a05ce JB |
2319 | } |
2320 | ||
c49a7bc3 AD |
2321 | /* determine offset of inner transport header */ |
2322 | l4_offset = l4.hdr - skb->data; | |
2323 | ||
2324 | /* remove payload length from inner checksum */ | |
2325 | paylen = (__force u16)l4.tcp->check; | |
2326 | paylen += ntohs(1) * (u16)~(skb->len - l4_offset); | |
2327 | l4.tcp->check = ~csum_fold((__force __wsum)paylen); | |
2328 | ||
2329 | /* compute length of segmentation header */ | |
2330 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
fd0a05ce JB |
2331 | |
2332 | /* find the field values */ | |
2333 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
2334 | cd_tso_len = skb->len - *hdr_len; | |
2335 | cd_mss = skb_shinfo(skb)->gso_size; | |
03f9d6a5 AD |
2336 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
2337 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
2338 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
fd0a05ce JB |
2339 | return 1; |
2340 | } | |
2341 | ||
beb0dff1 JK |
2342 | /** |
2343 | * i40e_tsyn - set up the tsyn context descriptor | |
2344 | * @tx_ring: ptr to the ring to send | |
2345 | * @skb: ptr to the skb we're sending | |
2346 | * @tx_flags: the collected send information | |
9c883bd3 | 2347 | * @cd_type_cmd_tso_mss: Quad Word 1 |
beb0dff1 JK |
2348 | * |
2349 | * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen | |
2350 | **/ | |
2351 | static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2352 | u32 tx_flags, u64 *cd_type_cmd_tso_mss) | |
2353 | { | |
2354 | struct i40e_pf *pf; | |
2355 | ||
2356 | if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) | |
2357 | return 0; | |
2358 | ||
2359 | /* Tx timestamps cannot be sampled when doing TSO */ | |
2360 | if (tx_flags & I40E_TX_FLAGS_TSO) | |
2361 | return 0; | |
2362 | ||
2363 | /* only timestamp the outbound packet if the user has requested it and | |
2364 | * we are not already transmitting a packet to be timestamped | |
2365 | */ | |
2366 | pf = i40e_netdev_to_pf(tx_ring->netdev); | |
22b4777d JK |
2367 | if (!(pf->flags & I40E_FLAG_PTP)) |
2368 | return 0; | |
2369 | ||
9ce34f02 JK |
2370 | if (pf->ptp_tx && |
2371 | !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { | |
beb0dff1 JK |
2372 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
2373 | pf->ptp_tx_skb = skb_get(skb); | |
2374 | } else { | |
2375 | return 0; | |
2376 | } | |
2377 | ||
2378 | *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << | |
2379 | I40E_TXD_CTX_QW1_CMD_SHIFT; | |
2380 | ||
beb0dff1 JK |
2381 | return 1; |
2382 | } | |
2383 | ||
fd0a05ce JB |
2384 | /** |
2385 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
2386 | * @skb: send buffer | |
89232c3b | 2387 | * @tx_flags: pointer to Tx flags currently set |
fd0a05ce JB |
2388 | * @td_cmd: Tx descriptor command bits to set |
2389 | * @td_offset: Tx descriptor header offsets to set | |
554f4544 | 2390 | * @tx_ring: Tx descriptor ring |
fd0a05ce JB |
2391 | * @cd_tunneling: ptr to context desc bits |
2392 | **/ | |
529f1f65 AD |
2393 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
2394 | u32 *td_cmd, u32 *td_offset, | |
2395 | struct i40e_ring *tx_ring, | |
2396 | u32 *cd_tunneling) | |
fd0a05ce | 2397 | { |
b96b78f2 AD |
2398 | union { |
2399 | struct iphdr *v4; | |
2400 | struct ipv6hdr *v6; | |
2401 | unsigned char *hdr; | |
2402 | } ip; | |
2403 | union { | |
2404 | struct tcphdr *tcp; | |
2405 | struct udphdr *udp; | |
2406 | unsigned char *hdr; | |
2407 | } l4; | |
a3fd9d88 | 2408 | unsigned char *exthdr; |
475b4205 | 2409 | u32 offset, cmd = 0, tunnel = 0; |
a3fd9d88 | 2410 | __be16 frag_off; |
b96b78f2 AD |
2411 | u8 l4_proto = 0; |
2412 | ||
529f1f65 AD |
2413 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
2414 | return 0; | |
2415 | ||
b96b78f2 AD |
2416 | ip.hdr = skb_network_header(skb); |
2417 | l4.hdr = skb_transport_header(skb); | |
fd0a05ce | 2418 | |
475b4205 AD |
2419 | /* compute outer L2 header size */ |
2420 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
2421 | ||
fd0a05ce | 2422 | if (skb->encapsulation) { |
a0064728 AD |
2423 | /* define outer network header type */ |
2424 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
2425 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2426 | I40E_TX_CTX_EXT_IP_IPV4 : | |
2427 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
2428 | ||
a0064728 AD |
2429 | l4_proto = ip.v4->protocol; |
2430 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 2431 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
2432 | |
2433 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 2434 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
2435 | if (l4.hdr != exthdr) |
2436 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2437 | &l4_proto, &frag_off); | |
a0064728 AD |
2438 | } |
2439 | ||
475b4205 AD |
2440 | /* compute outer L3 header size */ |
2441 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
2442 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
2443 | ||
2444 | /* switch IP header pointer from outer to inner header */ | |
2445 | ip.hdr = skb_inner_network_header(skb); | |
2446 | ||
a0064728 AD |
2447 | /* define outer transport */ |
2448 | switch (l4_proto) { | |
45991204 | 2449 | case IPPROTO_UDP: |
475b4205 | 2450 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
6a899024 | 2451 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
45991204 | 2452 | break; |
c1d1791d | 2453 | case IPPROTO_GRE: |
475b4205 | 2454 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 | 2455 | *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; |
c1d1791d | 2456 | break; |
45991204 | 2457 | default: |
529f1f65 AD |
2458 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2459 | return -1; | |
2460 | ||
2461 | skb_checksum_help(skb); | |
2462 | return 0; | |
45991204 | 2463 | } |
b96b78f2 | 2464 | |
475b4205 AD |
2465 | /* compute tunnel header size */ |
2466 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
2467 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
2468 | ||
5453205c AD |
2469 | /* indicate if we need to offload outer UDP header */ |
2470 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
2471 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) | |
2472 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
2473 | ||
475b4205 AD |
2474 | /* record tunnel offload values */ |
2475 | *cd_tunneling |= tunnel; | |
2476 | ||
b96b78f2 | 2477 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 2478 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 2479 | l4_proto = 0; |
fd0a05ce | 2480 | |
a0064728 AD |
2481 | /* reset type as we transition from outer to inner headers */ |
2482 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
2483 | if (ip.v4->version == 4) | |
2484 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
2485 | if (ip.v6->version == 6) | |
89232c3b | 2486 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
fd0a05ce JB |
2487 | } |
2488 | ||
2489 | /* Enable IP checksum offloads */ | |
89232c3b | 2490 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 2491 | l4_proto = ip.v4->protocol; |
fd0a05ce JB |
2492 | /* the stack computes the IP header already, the only time we |
2493 | * need the hardware to recompute it is in the case of TSO. | |
2494 | */ | |
475b4205 AD |
2495 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
2496 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
2497 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 2498 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 2499 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
2500 | |
2501 | exthdr = ip.hdr + sizeof(*ip.v6); | |
2502 | l4_proto = ip.v6->nexthdr; | |
2503 | if (l4.hdr != exthdr) | |
2504 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
2505 | &l4_proto, &frag_off); | |
fd0a05ce | 2506 | } |
b96b78f2 | 2507 | |
475b4205 AD |
2508 | /* compute inner L3 header size */ |
2509 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
fd0a05ce JB |
2510 | |
2511 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 2512 | switch (l4_proto) { |
fd0a05ce JB |
2513 | case IPPROTO_TCP: |
2514 | /* enable checksum offloads */ | |
475b4205 AD |
2515 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
2516 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2517 | break; |
2518 | case IPPROTO_SCTP: | |
2519 | /* enable SCTP checksum offload */ | |
475b4205 AD |
2520 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
2521 | offset |= (sizeof(struct sctphdr) >> 2) << | |
2522 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2523 | break; |
2524 | case IPPROTO_UDP: | |
2525 | /* enable UDP checksum offload */ | |
475b4205 AD |
2526 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
2527 | offset |= (sizeof(struct udphdr) >> 2) << | |
2528 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
fd0a05ce JB |
2529 | break; |
2530 | default: | |
529f1f65 AD |
2531 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
2532 | return -1; | |
2533 | skb_checksum_help(skb); | |
2534 | return 0; | |
fd0a05ce | 2535 | } |
475b4205 AD |
2536 | |
2537 | *td_cmd |= cmd; | |
2538 | *td_offset |= offset; | |
529f1f65 AD |
2539 | |
2540 | return 1; | |
fd0a05ce JB |
2541 | } |
2542 | ||
2543 | /** | |
2544 | * i40e_create_tx_ctx Build the Tx context descriptor | |
2545 | * @tx_ring: ring to create the descriptor on | |
2546 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
2547 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
2548 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
2549 | **/ | |
2550 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
2551 | const u64 cd_type_cmd_tso_mss, | |
2552 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
2553 | { | |
2554 | struct i40e_tx_context_desc *context_desc; | |
fc4ac67b | 2555 | int i = tx_ring->next_to_use; |
fd0a05ce | 2556 | |
ff40dd5d JB |
2557 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
2558 | !cd_tunneling && !cd_l2tag2) | |
fd0a05ce JB |
2559 | return; |
2560 | ||
2561 | /* grab the next descriptor */ | |
fc4ac67b AD |
2562 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); |
2563 | ||
2564 | i++; | |
2565 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
fd0a05ce JB |
2566 | |
2567 | /* cpu_to_le32 and assign to struct fields */ | |
2568 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
2569 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 2570 | context_desc->rsvd = cpu_to_le16(0); |
fd0a05ce JB |
2571 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
2572 | } | |
2573 | ||
4567dc10 ED |
2574 | /** |
2575 | * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions | |
2576 | * @tx_ring: the ring to be checked | |
2577 | * @size: the size buffer we want to assure is available | |
2578 | * | |
2579 | * Returns -EBUSY if a stop is needed, else 0 | |
2580 | **/ | |
2581 | static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) | |
2582 | { | |
2583 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2584 | /* Memory barrier before checking head and tail */ | |
2585 | smp_mb(); | |
2586 | ||
2587 | /* Check again in a case another CPU has just made room available. */ | |
2588 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
2589 | return -EBUSY; | |
2590 | ||
2591 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
2592 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2593 | ++tx_ring->tx_stats.restart_queue; | |
2594 | return 0; | |
2595 | } | |
2596 | ||
2597 | /** | |
2598 | * i40e_maybe_stop_tx - 1st level check for tx stop conditions | |
2599 | * @tx_ring: the ring to be checked | |
2600 | * @size: the size buffer we want to assure is available | |
2601 | * | |
2602 | * Returns 0 if stop is not needed | |
2603 | **/ | |
2604 | #ifdef I40E_FCOE | |
3e587cf3 | 2605 | inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
4567dc10 | 2606 | #else |
3e587cf3 | 2607 | static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
4567dc10 ED |
2608 | #endif |
2609 | { | |
2610 | if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) | |
2611 | return 0; | |
2612 | return __i40e_maybe_stop_tx(tx_ring, size); | |
2613 | } | |
2614 | ||
71da6197 AS |
2615 | /** |
2616 | * i40e_chk_linearize - Check if there are more than 8 fragments per packet | |
2617 | * @skb: send buffer | |
2618 | * @tx_flags: collected send information | |
71da6197 AS |
2619 | * |
2620 | * Note: Our HW can't scatter-gather more than 8 fragments to build | |
2621 | * a packet on the wire and so we need to figure out the cases where we | |
2622 | * need to linearize the skb. | |
2623 | **/ | |
30520831 | 2624 | static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags) |
71da6197 AS |
2625 | { |
2626 | struct skb_frag_struct *frag; | |
2627 | bool linearize = false; | |
2628 | unsigned int size = 0; | |
2629 | u16 num_frags; | |
2630 | u16 gso_segs; | |
2631 | ||
2632 | num_frags = skb_shinfo(skb)->nr_frags; | |
2633 | gso_segs = skb_shinfo(skb)->gso_segs; | |
2634 | ||
2635 | if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) { | |
30520831 | 2636 | u16 j = 0; |
71da6197 AS |
2637 | |
2638 | if (num_frags < (I40E_MAX_BUFFER_TXD)) | |
2639 | goto linearize_chk_done; | |
2640 | /* try the simple math, if we have too many frags per segment */ | |
2641 | if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) > | |
2642 | I40E_MAX_BUFFER_TXD) { | |
2643 | linearize = true; | |
2644 | goto linearize_chk_done; | |
2645 | } | |
2646 | frag = &skb_shinfo(skb)->frags[0]; | |
71da6197 AS |
2647 | /* we might still have more fragments per segment */ |
2648 | do { | |
2649 | size += skb_frag_size(frag); | |
2650 | frag++; j++; | |
30520831 ASJ |
2651 | if ((size >= skb_shinfo(skb)->gso_size) && |
2652 | (j < I40E_MAX_BUFFER_TXD)) { | |
2653 | size = (size % skb_shinfo(skb)->gso_size); | |
2654 | j = (size) ? 1 : 0; | |
2655 | } | |
71da6197 | 2656 | if (j == I40E_MAX_BUFFER_TXD) { |
30520831 ASJ |
2657 | linearize = true; |
2658 | break; | |
71da6197 AS |
2659 | } |
2660 | num_frags--; | |
2661 | } while (num_frags); | |
2662 | } else { | |
2663 | if (num_frags >= I40E_MAX_BUFFER_TXD) | |
2664 | linearize = true; | |
2665 | } | |
2666 | ||
2667 | linearize_chk_done: | |
2668 | return linearize; | |
2669 | } | |
2670 | ||
fd0a05ce JB |
2671 | /** |
2672 | * i40e_tx_map - Build the Tx descriptor | |
2673 | * @tx_ring: ring to send buffer on | |
2674 | * @skb: send buffer | |
2675 | * @first: first buffer info buffer to use | |
2676 | * @tx_flags: collected send information | |
2677 | * @hdr_len: size of the packet header | |
2678 | * @td_cmd: the command field in the descriptor | |
2679 | * @td_offset: offset for checksum or crc | |
2680 | **/ | |
38e00438 | 2681 | #ifdef I40E_FCOE |
3e587cf3 | 2682 | inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
fd0a05ce JB |
2683 | struct i40e_tx_buffer *first, u32 tx_flags, |
2684 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
3e587cf3 JB |
2685 | #else |
2686 | static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
2687 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2688 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
38e00438 | 2689 | #endif |
fd0a05ce | 2690 | { |
fd0a05ce JB |
2691 | unsigned int data_len = skb->data_len; |
2692 | unsigned int size = skb_headlen(skb); | |
a5e9c572 | 2693 | struct skb_frag_struct *frag; |
fd0a05ce JB |
2694 | struct i40e_tx_buffer *tx_bi; |
2695 | struct i40e_tx_desc *tx_desc; | |
a5e9c572 | 2696 | u16 i = tx_ring->next_to_use; |
fd0a05ce JB |
2697 | u32 td_tag = 0; |
2698 | dma_addr_t dma; | |
2699 | u16 gso_segs; | |
58044743 AS |
2700 | u16 desc_count = 0; |
2701 | bool tail_bump = true; | |
2702 | bool do_rs = false; | |
fd0a05ce | 2703 | |
fd0a05ce JB |
2704 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { |
2705 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2706 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2707 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2708 | } | |
2709 | ||
a5e9c572 AD |
2710 | if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) |
2711 | gso_segs = skb_shinfo(skb)->gso_segs; | |
2712 | else | |
2713 | gso_segs = 1; | |
2714 | ||
2715 | /* multiply data chunks by size of headers */ | |
2716 | first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); | |
2717 | first->gso_segs = gso_segs; | |
2718 | first->skb = skb; | |
2719 | first->tx_flags = tx_flags; | |
2720 | ||
2721 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2722 | ||
fd0a05ce | 2723 | tx_desc = I40E_TX_DESC(tx_ring, i); |
a5e9c572 AD |
2724 | tx_bi = first; |
2725 | ||
2726 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
2727 | if (dma_mapping_error(tx_ring->dev, dma)) | |
2728 | goto dma_error; | |
2729 | ||
2730 | /* record length, and DMA address */ | |
2731 | dma_unmap_len_set(tx_bi, len, size); | |
2732 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2733 | ||
2734 | tx_desc->buffer_addr = cpu_to_le64(dma); | |
2735 | ||
2736 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
fd0a05ce JB |
2737 | tx_desc->cmd_type_offset_bsz = |
2738 | build_ctob(td_cmd, td_offset, | |
2739 | I40E_MAX_DATA_PER_TXD, td_tag); | |
2740 | ||
fd0a05ce JB |
2741 | tx_desc++; |
2742 | i++; | |
58044743 AS |
2743 | desc_count++; |
2744 | ||
fd0a05ce JB |
2745 | if (i == tx_ring->count) { |
2746 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2747 | i = 0; | |
2748 | } | |
fd0a05ce | 2749 | |
a5e9c572 AD |
2750 | dma += I40E_MAX_DATA_PER_TXD; |
2751 | size -= I40E_MAX_DATA_PER_TXD; | |
fd0a05ce | 2752 | |
a5e9c572 AD |
2753 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2754 | } | |
fd0a05ce JB |
2755 | |
2756 | if (likely(!data_len)) | |
2757 | break; | |
2758 | ||
a5e9c572 AD |
2759 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, |
2760 | size, td_tag); | |
fd0a05ce JB |
2761 | |
2762 | tx_desc++; | |
2763 | i++; | |
58044743 AS |
2764 | desc_count++; |
2765 | ||
fd0a05ce JB |
2766 | if (i == tx_ring->count) { |
2767 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2768 | i = 0; | |
2769 | } | |
2770 | ||
a5e9c572 AD |
2771 | size = skb_frag_size(frag); |
2772 | data_len -= size; | |
fd0a05ce | 2773 | |
a5e9c572 AD |
2774 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
2775 | DMA_TO_DEVICE); | |
fd0a05ce | 2776 | |
a5e9c572 AD |
2777 | tx_bi = &tx_ring->tx_bi[i]; |
2778 | } | |
fd0a05ce | 2779 | |
a5e9c572 AD |
2780 | /* set next_to_watch value indicating a packet is present */ |
2781 | first->next_to_watch = tx_desc; | |
2782 | ||
2783 | i++; | |
2784 | if (i == tx_ring->count) | |
2785 | i = 0; | |
2786 | ||
2787 | tx_ring->next_to_use = i; | |
2788 | ||
58044743 AS |
2789 | netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, |
2790 | tx_ring->queue_index), | |
2791 | first->bytecount); | |
4567dc10 | 2792 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
58044743 AS |
2793 | |
2794 | /* Algorithm to optimize tail and RS bit setting: | |
2795 | * if xmit_more is supported | |
2796 | * if xmit_more is true | |
2797 | * do not update tail and do not mark RS bit. | |
2798 | * if xmit_more is false and last xmit_more was false | |
2799 | * if every packet spanned less than 4 desc | |
2800 | * then set RS bit on 4th packet and update tail | |
2801 | * on every packet | |
2802 | * else | |
2803 | * update tail and set RS bit on every packet. | |
2804 | * if xmit_more is false and last_xmit_more was true | |
2805 | * update tail and set RS bit. | |
2806 | * | |
2807 | * Optimization: wmb to be issued only in case of tail update. | |
2808 | * Also optimize the Descriptor WB path for RS bit with the same | |
2809 | * algorithm. | |
2810 | * | |
2811 | * Note: If there are less than 4 packets | |
2812 | * pending and interrupts were disabled the service task will | |
2813 | * trigger a force WB. | |
2814 | */ | |
2815 | if (skb->xmit_more && | |
2816 | !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, | |
2817 | tx_ring->queue_index))) { | |
2818 | tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; | |
2819 | tail_bump = false; | |
2820 | } else if (!skb->xmit_more && | |
2821 | !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, | |
2822 | tx_ring->queue_index)) && | |
2823 | (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) && | |
2824 | (tx_ring->packet_stride < WB_STRIDE) && | |
2825 | (desc_count < WB_STRIDE)) { | |
2826 | tx_ring->packet_stride++; | |
2827 | } else { | |
2828 | tx_ring->packet_stride = 0; | |
2829 | tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; | |
2830 | do_rs = true; | |
2831 | } | |
2832 | if (do_rs) | |
2833 | tx_ring->packet_stride = 0; | |
2834 | ||
2835 | tx_desc->cmd_type_offset_bsz = | |
2836 | build_ctob(td_cmd, td_offset, size, td_tag) | | |
2837 | cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD : | |
2838 | I40E_TX_DESC_CMD_EOP) << | |
2839 | I40E_TXD_QW1_CMD_SHIFT); | |
2840 | ||
a5e9c572 | 2841 | /* notify HW of packet */ |
58044743 | 2842 | if (!tail_bump) |
489ce7a4 | 2843 | prefetchw(tx_desc + 1); |
a5e9c572 | 2844 | |
58044743 AS |
2845 | if (tail_bump) { |
2846 | /* Force memory writes to complete before letting h/w | |
2847 | * know there are new descriptors to fetch. (Only | |
2848 | * applicable for weak-ordered memory model archs, | |
2849 | * such as IA-64). | |
2850 | */ | |
2851 | wmb(); | |
2852 | writel(i, tx_ring->tail); | |
2853 | } | |
2854 | ||
fd0a05ce JB |
2855 | return; |
2856 | ||
2857 | dma_error: | |
a5e9c572 | 2858 | dev_info(tx_ring->dev, "TX DMA map failed\n"); |
fd0a05ce JB |
2859 | |
2860 | /* clear dma mappings for failed tx_bi map */ | |
2861 | for (;;) { | |
2862 | tx_bi = &tx_ring->tx_bi[i]; | |
a5e9c572 | 2863 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); |
fd0a05ce JB |
2864 | if (tx_bi == first) |
2865 | break; | |
2866 | if (i == 0) | |
2867 | i = tx_ring->count; | |
2868 | i--; | |
2869 | } | |
2870 | ||
fd0a05ce JB |
2871 | tx_ring->next_to_use = i; |
2872 | } | |
2873 | ||
fd0a05ce JB |
2874 | /** |
2875 | * i40e_xmit_descriptor_count - calculate number of tx descriptors needed | |
2876 | * @skb: send buffer | |
2877 | * @tx_ring: ring to send buffer on | |
2878 | * | |
2879 | * Returns number of data descriptors needed for this skb. Returns 0 to indicate | |
2880 | * there is not enough descriptors available in this ring since we need at least | |
2881 | * one descriptor. | |
2882 | **/ | |
38e00438 | 2883 | #ifdef I40E_FCOE |
3e587cf3 | 2884 | inline int i40e_xmit_descriptor_count(struct sk_buff *skb, |
fd0a05ce | 2885 | struct i40e_ring *tx_ring) |
3e587cf3 JB |
2886 | #else |
2887 | static inline int i40e_xmit_descriptor_count(struct sk_buff *skb, | |
2888 | struct i40e_ring *tx_ring) | |
38e00438 | 2889 | #endif |
fd0a05ce | 2890 | { |
fd0a05ce | 2891 | unsigned int f; |
fd0a05ce JB |
2892 | int count = 0; |
2893 | ||
2894 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
2895 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
be560521 | 2896 | * + 4 desc gap to avoid the cache line where head is, |
fd0a05ce JB |
2897 | * + 1 desc for context descriptor, |
2898 | * otherwise try next time | |
2899 | */ | |
fd0a05ce JB |
2900 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
2901 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
980093eb | 2902 | |
fd0a05ce | 2903 | count += TXD_USE_COUNT(skb_headlen(skb)); |
be560521 | 2904 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { |
fd0a05ce JB |
2905 | tx_ring->tx_stats.tx_busy++; |
2906 | return 0; | |
2907 | } | |
2908 | return count; | |
2909 | } | |
2910 | ||
2911 | /** | |
2912 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
2913 | * @skb: send buffer | |
2914 | * @tx_ring: ring to send buffer on | |
2915 | * | |
2916 | * Returns NETDEV_TX_OK if sent, else an error code | |
2917 | **/ | |
2918 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
2919 | struct i40e_ring *tx_ring) | |
2920 | { | |
2921 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
2922 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
2923 | struct i40e_tx_buffer *first; | |
2924 | u32 td_offset = 0; | |
2925 | u32 tx_flags = 0; | |
2926 | __be16 protocol; | |
2927 | u32 td_cmd = 0; | |
2928 | u8 hdr_len = 0; | |
beb0dff1 | 2929 | int tsyn; |
fd0a05ce | 2930 | int tso; |
6995b36c | 2931 | |
b74118f0 JB |
2932 | /* prefetch the data, we'll need it later */ |
2933 | prefetch(skb->data); | |
2934 | ||
fd0a05ce JB |
2935 | if (0 == i40e_xmit_descriptor_count(skb, tx_ring)) |
2936 | return NETDEV_TX_BUSY; | |
2937 | ||
2938 | /* prepare the xmit flags */ | |
2939 | if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) | |
2940 | goto out_drop; | |
2941 | ||
2942 | /* obtain protocol of skb */ | |
3d34dd03 | 2943 | protocol = vlan_get_protocol(skb); |
fd0a05ce JB |
2944 | |
2945 | /* record the location of the first descriptor for this packet */ | |
2946 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
2947 | ||
2948 | /* setup IPv4/IPv6 offloads */ | |
0e2fe46c | 2949 | if (protocol == htons(ETH_P_IP)) |
fd0a05ce | 2950 | tx_flags |= I40E_TX_FLAGS_IPV4; |
0e2fe46c | 2951 | else if (protocol == htons(ETH_P_IPV6)) |
fd0a05ce JB |
2952 | tx_flags |= I40E_TX_FLAGS_IPV6; |
2953 | ||
9c883bd3 | 2954 | tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss); |
fd0a05ce JB |
2955 | |
2956 | if (tso < 0) | |
2957 | goto out_drop; | |
2958 | else if (tso) | |
2959 | tx_flags |= I40E_TX_FLAGS_TSO; | |
2960 | ||
beb0dff1 JK |
2961 | tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); |
2962 | ||
2963 | if (tsyn) | |
2964 | tx_flags |= I40E_TX_FLAGS_TSYN; | |
2965 | ||
2fc3d715 | 2966 | if (i40e_chk_linearize(skb, tx_flags)) { |
71da6197 AS |
2967 | if (skb_linearize(skb)) |
2968 | goto out_drop; | |
2fc3d715 ASJ |
2969 | tx_ring->tx_stats.tx_linearize++; |
2970 | } | |
259afec7 JK |
2971 | skb_tx_timestamp(skb); |
2972 | ||
b1941306 AD |
2973 | /* always enable CRC insertion offload */ |
2974 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
2975 | ||
fd0a05ce | 2976 | /* Always offload the checksum, since it's in the data descriptor */ |
529f1f65 AD |
2977 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, |
2978 | tx_ring, &cd_tunneling); | |
2979 | if (tso < 0) | |
2980 | goto out_drop; | |
fd0a05ce JB |
2981 | |
2982 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, | |
2983 | cd_tunneling, cd_l2tag2); | |
2984 | ||
2985 | /* Add Flow Director ATR if it's enabled. | |
2986 | * | |
2987 | * NOTE: this must always be directly before the data descriptor. | |
2988 | */ | |
6b037cd4 | 2989 | i40e_atr(tx_ring, skb, tx_flags); |
fd0a05ce JB |
2990 | |
2991 | i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, | |
2992 | td_cmd, td_offset); | |
2993 | ||
fd0a05ce JB |
2994 | return NETDEV_TX_OK; |
2995 | ||
2996 | out_drop: | |
2997 | dev_kfree_skb_any(skb); | |
2998 | return NETDEV_TX_OK; | |
2999 | } | |
3000 | ||
3001 | /** | |
3002 | * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
3003 | * @skb: send buffer | |
3004 | * @netdev: network interface device structure | |
3005 | * | |
3006 | * Returns NETDEV_TX_OK if sent, else an error code | |
3007 | **/ | |
3008 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
3009 | { | |
3010 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
3011 | struct i40e_vsi *vsi = np->vsi; | |
9f65e15b | 3012 | struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; |
fd0a05ce JB |
3013 | |
3014 | /* hardware can't handle really short frames, hardware padding works | |
3015 | * beyond this point | |
3016 | */ | |
a94d9e22 AD |
3017 | if (skb_put_padto(skb, I40E_MIN_TX_LEN)) |
3018 | return NETDEV_TX_OK; | |
fd0a05ce JB |
3019 | |
3020 | return i40e_xmit_frame_ring(skb, tx_ring); | |
3021 | } |