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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / i40e / i40e_virtchnl_pf.c
CommitLineData
5c3c48ac
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
40d72a50 4 * Copyright(c) 2013 - 2016 Intel Corporation.
5c3c48ac
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
5c3c48ac
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e.h"
28
532b0455
MW		 29/*********************notification routines***********************/
30
31/**
32 * i40e_vc_vf_broadcast
33 * @pf: pointer to the PF structure
34 * @opcode: operation code
35 * @retval: return value
36 * @msg: pointer to the msg buffer
37 * @msglen: msg length
38 *
39 * send a message to all VFs on a given PF
40 **/
41static void i40e_vc_vf_broadcast(struct i40e_pf *pf,
42 enum i40e_virtchnl_ops v_opcode,
43 i40e_status v_retval, u8 *msg,
44 u16 msglen)
45{
46 struct i40e_hw *hw = &pf->hw;
47 struct i40e_vf *vf = pf->vf;
48 int i;
49
50 for (i = 0; i < pf->num_alloc_vfs; i++, vf++) {
a1b5a24f 51 int abs_vf_id = vf->vf_id + (int)hw->func_caps.vf_base_id;
532b0455
MW		 52 /* Not all vfs are enabled so skip the ones that are not */
53 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states) &&
54 !test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states))
55 continue;
56
57 /* Ignore return value on purpose - a given VF may fail, but
58 * we need to keep going and send to all of them
59 */
60 i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
61 msg, msglen, NULL);
62 }
63}
64
65/**
55f7d723 66 * i40e_vc_notify_vf_link_state
532b0455
MW		 67 * @vf: pointer to the VF structure
68 *
69 * send a link status message to a single VF
70 **/
71static void i40e_vc_notify_vf_link_state(struct i40e_vf *vf)
72{
73 struct i40e_virtchnl_pf_event pfe;
74 struct i40e_pf *pf = vf->pf;
75 struct i40e_hw *hw = &pf->hw;
76 struct i40e_link_status *ls = &pf->hw.phy.link_info;
a1b5a24f 77 int abs_vf_id = vf->vf_id + (int)hw->func_caps.vf_base_id;
532b0455
MW		 78
79 pfe.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
80 pfe.severity = I40E_PF_EVENT_SEVERITY_INFO;
81 if (vf->link_forced) {
82 pfe.event_data.link_event.link_status = vf->link_up;
83 pfe.event_data.link_event.link_speed =
84 (vf->link_up ? I40E_LINK_SPEED_40GB : 0);
85 } else {
86 pfe.event_data.link_event.link_status =
87 ls->link_info & I40E_AQ_LINK_UP;
88 pfe.event_data.link_event.link_speed = ls->link_speed;
89 }
90 i40e_aq_send_msg_to_vf(hw, abs_vf_id, I40E_VIRTCHNL_OP_EVENT,
91 0, (u8 *)&pfe, sizeof(pfe), NULL);
92}
93
94/**
95 * i40e_vc_notify_link_state
96 * @pf: pointer to the PF structure
97 *
98 * send a link status message to all VFs on a given PF
99 **/
100void i40e_vc_notify_link_state(struct i40e_pf *pf)
101{
102 int i;
103
104 for (i = 0; i < pf->num_alloc_vfs; i++)
105 i40e_vc_notify_vf_link_state(&pf->vf[i]);
106}
107
108/**
109 * i40e_vc_notify_reset
110 * @pf: pointer to the PF structure
111 *
112 * indicate a pending reset to all VFs on a given PF
113 **/
114void i40e_vc_notify_reset(struct i40e_pf *pf)
115{
116 struct i40e_virtchnl_pf_event pfe;
117
118 pfe.event = I40E_VIRTCHNL_EVENT_RESET_IMPENDING;
119 pfe.severity = I40E_PF_EVENT_SEVERITY_CERTAIN_DOOM;
120 i40e_vc_vf_broadcast(pf, I40E_VIRTCHNL_OP_EVENT, 0,
121 (u8 *)&pfe, sizeof(struct i40e_virtchnl_pf_event));
122}
123
124/**
125 * i40e_vc_notify_vf_reset
126 * @vf: pointer to the VF structure
127 *
128 * indicate a pending reset to the given VF
129 **/
130void i40e_vc_notify_vf_reset(struct i40e_vf *vf)
131{
132 struct i40e_virtchnl_pf_event pfe;
133 int abs_vf_id;
134
135 /* validate the request */
136 if (!vf || vf->vf_id >= vf->pf->num_alloc_vfs)
137 return;
138
139 /* verify if the VF is in either init or active before proceeding */
140 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states) &&
141 !test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states))
142 return;
143
a1b5a24f 144 abs_vf_id = vf->vf_id + (int)vf->pf->hw.func_caps.vf_base_id;
532b0455
MW		 145
146 pfe.event = I40E_VIRTCHNL_EVENT_RESET_IMPENDING;
147 pfe.severity = I40E_PF_EVENT_SEVERITY_CERTAIN_DOOM;
148 i40e_aq_send_msg_to_vf(&vf->pf->hw, abs_vf_id, I40E_VIRTCHNL_OP_EVENT,
149 0, (u8 *)&pfe,
150 sizeof(struct i40e_virtchnl_pf_event), NULL);
151}
5c3c48ac
JB		 152/***********************misc routines*****************************/
153
f9b4b627
GR		 154/**
155 * i40e_vc_disable_vf
b40c82e6
JK		 156 * @pf: pointer to the PF info
157 * @vf: pointer to the VF info
f9b4b627
GR		 158 *
159 * Disable the VF through a SW reset
160 **/
161static inline void i40e_vc_disable_vf(struct i40e_pf *pf, struct i40e_vf *vf)
162{
54f455ee
MW		 163 i40e_vc_notify_vf_reset(vf);
164 i40e_reset_vf(vf, false);
f9b4b627
GR		 165}
166
5c3c48ac
JB		 167/**
168 * i40e_vc_isvalid_vsi_id
b40c82e6
JK		 169 * @vf: pointer to the VF info
170 * @vsi_id: VF relative VSI id
5c3c48ac 171 *
b40c82e6 172 * check for the valid VSI id
5c3c48ac 173 **/
fdf0e0bf 174static inline bool i40e_vc_isvalid_vsi_id(struct i40e_vf *vf, u16 vsi_id)
5c3c48ac
JB		 175{
176 struct i40e_pf *pf = vf->pf;
fdf0e0bf 177 struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
5c3c48ac 178
fdf0e0bf 179 return (vsi && (vsi->vf_id == vf->vf_id));
5c3c48ac
JB		 180}
181
182/**
183 * i40e_vc_isvalid_queue_id
b40c82e6 184 * @vf: pointer to the VF info
5c3c48ac
JB		 185 * @vsi_id: vsi id
186 * @qid: vsi relative queue id
187 *
188 * check for the valid queue id
189 **/
fdf0e0bf 190static inline bool i40e_vc_isvalid_queue_id(struct i40e_vf *vf, u16 vsi_id,
5c3c48ac
JB		 191 u8 qid)
192{
193 struct i40e_pf *pf = vf->pf;
fdf0e0bf 194 struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
5c3c48ac 195
fdf0e0bf 196 return (vsi && (qid < vsi->alloc_queue_pairs));
5c3c48ac
JB		 197}
198
199/**
200 * i40e_vc_isvalid_vector_id
b40c82e6
JK		 201 * @vf: pointer to the VF info
202 * @vector_id: VF relative vector id
5c3c48ac
JB		 203 *
204 * check for the valid vector id
205 **/
206static inline bool i40e_vc_isvalid_vector_id(struct i40e_vf *vf, u8 vector_id)
207{
208 struct i40e_pf *pf = vf->pf;
209
9347eb77 210 return vector_id < pf->hw.func_caps.num_msix_vectors_vf;
5c3c48ac
JB		 211}
212
213/***********************vf resource mgmt routines*****************/
214
215/**
216 * i40e_vc_get_pf_queue_id
b40c82e6 217 * @vf: pointer to the VF info
fdf0e0bf 218 * @vsi_id: id of VSI as provided by the FW
5c3c48ac
JB		 219 * @vsi_queue_id: vsi relative queue id
220 *
b40c82e6 221 * return PF relative queue id
5c3c48ac 222 **/
fdf0e0bf 223static u16 i40e_vc_get_pf_queue_id(struct i40e_vf *vf, u16 vsi_id,
5c3c48ac
JB		 224 u8 vsi_queue_id)
225{
226 struct i40e_pf *pf = vf->pf;
fdf0e0bf 227 struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
5c3c48ac
JB		 228 u16 pf_queue_id = I40E_QUEUE_END_OF_LIST;
229
fdf0e0bf
ASJ		 230 if (!vsi)
231 return pf_queue_id;
232
5c3c48ac
JB		 233 if (le16_to_cpu(vsi->info.mapping_flags) &
234 I40E_AQ_VSI_QUE_MAP_NONCONTIG)
235 pf_queue_id =
236 le16_to_cpu(vsi->info.queue_mapping[vsi_queue_id]);
237 else
238 pf_queue_id = le16_to_cpu(vsi->info.queue_mapping[0]) +
239 vsi_queue_id;
240
241 return pf_queue_id;
242}
243
5c3c48ac
JB		 244/**
245 * i40e_config_irq_link_list
b40c82e6 246 * @vf: pointer to the VF info
fdf0e0bf 247 * @vsi_id: id of VSI as given by the FW
5c3c48ac
JB		 248 * @vecmap: irq map info
249 *
250 * configure irq link list from the map
251 **/
fdf0e0bf 252static void i40e_config_irq_link_list(struct i40e_vf *vf, u16 vsi_id,
5c3c48ac
JB		 253 struct i40e_virtchnl_vector_map *vecmap)
254{
255 unsigned long linklistmap = 0, tempmap;
256 struct i40e_pf *pf = vf->pf;
257 struct i40e_hw *hw = &pf->hw;
258 u16 vsi_queue_id, pf_queue_id;
259 enum i40e_queue_type qtype;
260 u16 next_q, vector_id;
261 u32 reg, reg_idx;
262 u16 itr_idx = 0;
263
264 vector_id = vecmap->vector_id;
265 /* setup the head */
266 if (0 == vector_id)
267 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id);
268 else
269 reg_idx = I40E_VPINT_LNKLSTN(
9347eb77
MW		 270 ((pf->hw.func_caps.num_msix_vectors_vf - 1) * vf->vf_id) +
271 (vector_id - 1));
5c3c48ac
JB		 272
273 if (vecmap->rxq_map == 0 && vecmap->txq_map == 0) {
274 /* Special case - No queues mapped on this vector */
275 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
276 goto irq_list_done;
277 }
278 tempmap = vecmap->rxq_map;
4836650b 279 for_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {
41a1d04b
JB		 280 linklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES *
281 vsi_queue_id));
5c3c48ac
JB		 282 }
283
284 tempmap = vecmap->txq_map;
4836650b 285 for_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {
41a1d04b
JB		 286 linklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES *
287 vsi_queue_id + 1));
5c3c48ac
JB		 288 }
289
290 next_q = find_first_bit(&linklistmap,
291 (I40E_MAX_VSI_QP *
292 I40E_VIRTCHNL_SUPPORTED_QTYPES));
b82bc49e
MW		 293 vsi_queue_id = next_q / I40E_VIRTCHNL_SUPPORTED_QTYPES;
294 qtype = next_q % I40E_VIRTCHNL_SUPPORTED_QTYPES;
fdf0e0bf 295 pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id, vsi_queue_id);
5c3c48ac
JB		 296 reg = ((qtype << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) | pf_queue_id);
297
298 wr32(hw, reg_idx, reg);
299
300 while (next_q < (I40E_MAX_VSI_QP * I40E_VIRTCHNL_SUPPORTED_QTYPES)) {
301 switch (qtype) {
302 case I40E_QUEUE_TYPE_RX:
303 reg_idx = I40E_QINT_RQCTL(pf_queue_id);
304 itr_idx = vecmap->rxitr_idx;
305 break;
306 case I40E_QUEUE_TYPE_TX:
307 reg_idx = I40E_QINT_TQCTL(pf_queue_id);
308 itr_idx = vecmap->txitr_idx;
309 break;
310 default:
311 break;
312 }
313
314 next_q = find_next_bit(&linklistmap,
315 (I40E_MAX_VSI_QP *
316 I40E_VIRTCHNL_SUPPORTED_QTYPES),
317 next_q + 1);
829af3ac
MW		 318 if (next_q <
319 (I40E_MAX_VSI_QP * I40E_VIRTCHNL_SUPPORTED_QTYPES)) {
5c3c48ac
JB		 320 vsi_queue_id = next_q / I40E_VIRTCHNL_SUPPORTED_QTYPES;
321 qtype = next_q % I40E_VIRTCHNL_SUPPORTED_QTYPES;
fdf0e0bf 322 pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id,
5c3c48ac
JB		 323 vsi_queue_id);
324 } else {
325 pf_queue_id = I40E_QUEUE_END_OF_LIST;
326 qtype = 0;
327 }
328
329 /* format for the RQCTL & TQCTL regs is same */
330 reg = (vector_id) |
331 (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
332 (pf_queue_id << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
41a1d04b 333 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
5c3c48ac
JB		 334 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
335 wr32(hw, reg_idx, reg);
336 }
337
b8262a6d
ASJ		 338 /* if the vf is running in polling mode and using interrupt zero,
339 * need to disable auto-mask on enabling zero interrupt for VFs.
340 */
341 if ((vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING) &&
342 (vector_id == 0)) {
343 reg = rd32(hw, I40E_GLINT_CTL);
344 if (!(reg & I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK)) {
345 reg |= I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
346 wr32(hw, I40E_GLINT_CTL, reg);
347 }
348 }
349
5c3c48ac
JB		 350irq_list_done:
351 i40e_flush(hw);
352}
353
e3219ce6
ASJ		 354/**
355 * i40e_release_iwarp_qvlist
356 * @vf: pointer to the VF.
357 *
358 **/
359static void i40e_release_iwarp_qvlist(struct i40e_vf *vf)
360{
361 struct i40e_pf *pf = vf->pf;
362 struct i40e_virtchnl_iwarp_qvlist_info *qvlist_info = vf->qvlist_info;
363 u32 msix_vf;
364 u32 i;
365
366 if (!vf->qvlist_info)
367 return;
368
369 msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
370 for (i = 0; i < qvlist_info->num_vectors; i++) {
371 struct i40e_virtchnl_iwarp_qv_info *qv_info;
372 u32 next_q_index, next_q_type;
373 struct i40e_hw *hw = &pf->hw;
374 u32 v_idx, reg_idx, reg;
375
376 qv_info = &qvlist_info->qv_info[i];
377 if (!qv_info)
378 continue;
379 v_idx = qv_info->v_idx;
380 if (qv_info->ceq_idx != I40E_QUEUE_INVALID_IDX) {
381 /* Figure out the queue after CEQ and make that the
382 * first queue.
383 */
384 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx;
385 reg = rd32(hw, I40E_VPINT_CEQCTL(reg_idx));
386 next_q_index = (reg & I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK)
387 >> I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT;
388 next_q_type = (reg & I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK)
389 >> I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT;
390
391 reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1);
392 reg = (next_q_index &
393 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) |
394 (next_q_type <<
395 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT);
396
397 wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg);
398 }
399 }
400 kfree(vf->qvlist_info);
401 vf->qvlist_info = NULL;
402}
403
404/**
405 * i40e_config_iwarp_qvlist
406 * @vf: pointer to the VF info
407 * @qvlist_info: queue and vector list
408 *
409 * Return 0 on success or < 0 on error
410 **/
411static int i40e_config_iwarp_qvlist(struct i40e_vf *vf,
412 struct i40e_virtchnl_iwarp_qvlist_info *qvlist_info)
413{
414 struct i40e_pf *pf = vf->pf;
415 struct i40e_hw *hw = &pf->hw;
416 struct i40e_virtchnl_iwarp_qv_info *qv_info;
417 u32 v_idx, i, reg_idx, reg;
418 u32 next_q_idx, next_q_type;
419 u32 msix_vf, size;
420
421 size = sizeof(struct i40e_virtchnl_iwarp_qvlist_info) +
422 (sizeof(struct i40e_virtchnl_iwarp_qv_info) *
423 (qvlist_info->num_vectors - 1));
424 vf->qvlist_info = kzalloc(size, GFP_KERNEL);
425 vf->qvlist_info->num_vectors = qvlist_info->num_vectors;
426
427 msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
428 for (i = 0; i < qvlist_info->num_vectors; i++) {
429 qv_info = &qvlist_info->qv_info[i];
430 if (!qv_info)
431 continue;
432 v_idx = qv_info->v_idx;
433
434 /* Validate vector id belongs to this vf */
435 if (!i40e_vc_isvalid_vector_id(vf, v_idx))
436 goto err;
437
438 vf->qvlist_info->qv_info[i] = *qv_info;
439
440 reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1);
441 /* We might be sharing the interrupt, so get the first queue
442 * index and type, push it down the list by adding the new
443 * queue on top. Also link it with the new queue in CEQCTL.
444 */
445 reg = rd32(hw, I40E_VPINT_LNKLSTN(reg_idx));
446 next_q_idx = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) >>
447 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT);
448 next_q_type = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK) >>
449 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT);
450
451 if (qv_info->ceq_idx != I40E_QUEUE_INVALID_IDX) {
452 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx;
453 reg = (I40E_VPINT_CEQCTL_CAUSE_ENA_MASK |
454 (v_idx << I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT) |
455 (qv_info->itr_idx << I40E_VPINT_CEQCTL_ITR_INDX_SHIFT) |
456 (next_q_type << I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) |
457 (next_q_idx << I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT));
458 wr32(hw, I40E_VPINT_CEQCTL(reg_idx), reg);
459
460 reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1);
461 reg = (qv_info->ceq_idx &
462 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) |
463 (I40E_QUEUE_TYPE_PE_CEQ <<
464 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT);
465 wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg);
466 }
467
468 if (qv_info->aeq_idx != I40E_QUEUE_INVALID_IDX) {
469 reg = (I40E_VPINT_AEQCTL_CAUSE_ENA_MASK |
470 (v_idx << I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) |
471 (qv_info->itr_idx << I40E_VPINT_AEQCTL_ITR_INDX_SHIFT));
472
473 wr32(hw, I40E_VPINT_AEQCTL(vf->vf_id), reg);
474 }
475 }
476
477 return 0;
478err:
479 kfree(vf->qvlist_info);
480 vf->qvlist_info = NULL;
481 return -EINVAL;
482}
483
5c3c48ac
JB		 484/**
485 * i40e_config_vsi_tx_queue
b40c82e6 486 * @vf: pointer to the VF info
fdf0e0bf 487 * @vsi_id: id of VSI as provided by the FW
5c3c48ac
JB		 488 * @vsi_queue_id: vsi relative queue index
489 * @info: config. info
490 *
491 * configure tx queue
492 **/
fdf0e0bf 493static int i40e_config_vsi_tx_queue(struct i40e_vf *vf, u16 vsi_id,
5c3c48ac
JB		 494 u16 vsi_queue_id,
495 struct i40e_virtchnl_txq_info *info)
496{
497 struct i40e_pf *pf = vf->pf;
498 struct i40e_hw *hw = &pf->hw;
499 struct i40e_hmc_obj_txq tx_ctx;
fdf0e0bf 500 struct i40e_vsi *vsi;
5c3c48ac
JB		 501 u16 pf_queue_id;
502 u32 qtx_ctl;
503 int ret = 0;
504
d4a0658d
CW		 505 if (!i40e_vc_isvalid_vsi_id(vf, info->vsi_id)) {
506 ret = -ENOENT;
507 goto error_context;
508 }
fdf0e0bf
ASJ		 509 pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id, vsi_queue_id);
510 vsi = i40e_find_vsi_from_id(pf, vsi_id);
d4a0658d
CW		 511 if (!vsi) {
512 ret = -ENOENT;
513 goto error_context;
514 }
5c3c48ac
JB		 515
516 /* clear the context structure first */
517 memset(&tx_ctx, 0, sizeof(struct i40e_hmc_obj_txq));
518
519 /* only set the required fields */
520 tx_ctx.base = info->dma_ring_addr / 128;
521 tx_ctx.qlen = info->ring_len;
fdf0e0bf 522 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[0]);
5c3c48ac 523 tx_ctx.rdylist_act = 0;
5d29896a
AS		 524 tx_ctx.head_wb_ena = info->headwb_enabled;
525 tx_ctx.head_wb_addr = info->dma_headwb_addr;
5c3c48ac
JB		 526
527 /* clear the context in the HMC */
528 ret = i40e_clear_lan_tx_queue_context(hw, pf_queue_id);
529 if (ret) {
530 dev_err(&pf->pdev->dev,
531 "Failed to clear VF LAN Tx queue context %d, error: %d\n",
532 pf_queue_id, ret);
533 ret = -ENOENT;
534 goto error_context;
535 }
536
537 /* set the context in the HMC */
538 ret = i40e_set_lan_tx_queue_context(hw, pf_queue_id, &tx_ctx);
539 if (ret) {
540 dev_err(&pf->pdev->dev,
541 "Failed to set VF LAN Tx queue context %d error: %d\n",
542 pf_queue_id, ret);
543 ret = -ENOENT;
544 goto error_context;
545 }
546
547 /* associate this queue with the PCI VF function */
548 qtx_ctl = I40E_QTX_CTL_VF_QUEUE;
13fd9774 549 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)
5c3c48ac
JB		 550 & I40E_QTX_CTL_PF_INDX_MASK);
551 qtx_ctl |= (((vf->vf_id + hw->func_caps.vf_base_id)
552 << I40E_QTX_CTL_VFVM_INDX_SHIFT)
553 & I40E_QTX_CTL_VFVM_INDX_MASK);
554 wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl);
555 i40e_flush(hw);
556
557error_context:
558 return ret;
559}
560
561/**
562 * i40e_config_vsi_rx_queue
b40c82e6 563 * @vf: pointer to the VF info
fdf0e0bf 564 * @vsi_id: id of VSI as provided by the FW
5c3c48ac
JB		 565 * @vsi_queue_id: vsi relative queue index
566 * @info: config. info
567 *
568 * configure rx queue
569 **/
fdf0e0bf 570static int i40e_config_vsi_rx_queue(struct i40e_vf *vf, u16 vsi_id,
5c3c48ac
JB		 571 u16 vsi_queue_id,
572 struct i40e_virtchnl_rxq_info *info)
573{
574 struct i40e_pf *pf = vf->pf;
575 struct i40e_hw *hw = &pf->hw;
576 struct i40e_hmc_obj_rxq rx_ctx;
577 u16 pf_queue_id;
578 int ret = 0;
579
fdf0e0bf 580 pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id, vsi_queue_id);
5c3c48ac
JB		 581
582 /* clear the context structure first */
583 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
584
585 /* only set the required fields */
586 rx_ctx.base = info->dma_ring_addr / 128;
587 rx_ctx.qlen = info->ring_len;
588
589 if (info->splithdr_enabled) {
590 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
591 I40E_RX_SPLIT_IP |
592 I40E_RX_SPLIT_TCP_UDP |
593 I40E_RX_SPLIT_SCTP;
594 /* header length validation */
595 if (info->hdr_size > ((2 * 1024) - 64)) {
596 ret = -EINVAL;
597 goto error_param;
598 }
599 rx_ctx.hbuff = info->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
600
19b85e67 601 /* set split mode 10b */
d6b3bca1 602 rx_ctx.dtype = I40E_RX_DTYPE_HEADER_SPLIT;
5c3c48ac
JB		 603 }
604
605 /* databuffer length validation */
606 if (info->databuffer_size > ((16 * 1024) - 128)) {
607 ret = -EINVAL;
608 goto error_param;
609 }
610 rx_ctx.dbuff = info->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
611
612 /* max pkt. length validation */
613 if (info->max_pkt_size >= (16 * 1024) || info->max_pkt_size < 64) {
614 ret = -EINVAL;
615 goto error_param;
616 }
617 rx_ctx.rxmax = info->max_pkt_size;
618
619 /* enable 32bytes desc always */
620 rx_ctx.dsize = 1;
621
622 /* default values */
5c3c48ac
JB		 623 rx_ctx.lrxqthresh = 2;
624 rx_ctx.crcstrip = 1;
50d41659 625 rx_ctx.prefena = 1;
c1d11cef 626 rx_ctx.l2tsel = 1;
5c3c48ac
JB		 627
628 /* clear the context in the HMC */
629 ret = i40e_clear_lan_rx_queue_context(hw, pf_queue_id);
630 if (ret) {
631 dev_err(&pf->pdev->dev,
632 "Failed to clear VF LAN Rx queue context %d, error: %d\n",
633 pf_queue_id, ret);
634 ret = -ENOENT;
635 goto error_param;
636 }
637
638 /* set the context in the HMC */
639 ret = i40e_set_lan_rx_queue_context(hw, pf_queue_id, &rx_ctx);
640 if (ret) {
641 dev_err(&pf->pdev->dev,
642 "Failed to set VF LAN Rx queue context %d error: %d\n",
643 pf_queue_id, ret);
644 ret = -ENOENT;
645 goto error_param;
646 }
647
648error_param:
649 return ret;
650}
651
652/**
653 * i40e_alloc_vsi_res
b40c82e6 654 * @vf: pointer to the VF info
5c3c48ac
JB		 655 * @type: type of VSI to allocate
656 *
b40c82e6 657 * alloc VF vsi context & resources
5c3c48ac
JB		 658 **/
659static int i40e_alloc_vsi_res(struct i40e_vf *vf, enum i40e_vsi_type type)
660{
661 struct i40e_mac_filter *f = NULL;
662 struct i40e_pf *pf = vf->pf;
5c3c48ac
JB		 663 struct i40e_vsi *vsi;
664 int ret = 0;
665
666 vsi = i40e_vsi_setup(pf, type, pf->vsi[pf->lan_vsi]->seid, vf->vf_id);
667
668 if (!vsi) {
669 dev_err(&pf->pdev->dev,
b40c82e6 670 "add vsi failed for VF %d, aq_err %d\n",
5c3c48ac
JB		 671 vf->vf_id, pf->hw.aq.asq_last_status);
672 ret = -ENOENT;
673 goto error_alloc_vsi_res;
674 }
675 if (type == I40E_VSI_SRIOV) {
bb360717 676 u64 hena = i40e_pf_get_default_rss_hena(pf);
435c084a 677 u8 broadcast[ETH_ALEN];
bb360717 678
fdf0e0bf 679 vf->lan_vsi_idx = vsi->idx;
5c3c48ac 680 vf->lan_vsi_id = vsi->id;
6c12fcbf
GR		 681 /* If the port VLAN has been configured and then the
682 * VF driver was removed then the VSI port VLAN
683 * configuration was destroyed. Check if there is
684 * a port VLAN and restore the VSI configuration if
685 * needed.
686 */
687 if (vf->port_vlan_id)
688 i40e_vsi_add_pvid(vsi, vf->port_vlan_id);
21659035 689
278e7d0b 690 spin_lock_bh(&vsi->mac_filter_hash_lock);
b7b713a8 691 if (is_valid_ether_addr(vf->default_lan_addr.addr)) {
9569a9a4
JK		 692 f = i40e_add_mac_filter(vsi,
693 vf->default_lan_addr.addr);
b7b713a8
MW		 694 if (!f)
695 dev_info(&pf->pdev->dev,
696 "Could not add MAC filter %pM for VF %d\n",
697 vf->default_lan_addr.addr, vf->vf_id);
698 }
435c084a 699 eth_broadcast_addr(broadcast);
9569a9a4 700 f = i40e_add_mac_filter(vsi, broadcast);
435c084a
JK		 701 if (!f)
702 dev_info(&pf->pdev->dev,
703 "Could not allocate VF broadcast filter\n");
278e7d0b 704 spin_unlock_bh(&vsi->mac_filter_hash_lock);
bb360717
MW		 705 i40e_write_rx_ctl(&pf->hw, I40E_VFQF_HENA1(0, vf->vf_id),
706 (u32)hena);
707 i40e_write_rx_ctl(&pf->hw, I40E_VFQF_HENA1(1, vf->vf_id),
708 (u32)(hena >> 32));
5c3c48ac 709 }
6dbbbfb2 710
5c3c48ac 711 /* program mac filter */
17652c63 712 ret = i40e_sync_vsi_filters(vsi);
fd1646ee 713 if (ret)
5c3c48ac 714 dev_err(&pf->pdev->dev, "Unable to program ucast filters\n");
5c3c48ac 715
6b192891
MW		 716 /* Set VF bandwidth if specified */
717 if (vf->tx_rate) {
718 ret = i40e_aq_config_vsi_bw_limit(&pf->hw, vsi->seid,
719 vf->tx_rate / 50, 0, NULL);
720 if (ret)
721 dev_err(&pf->pdev->dev, "Unable to set tx rate, VF %d, error code %d.\n",
722 vf->vf_id, ret);
723 }
724
5c3c48ac
JB		 725error_alloc_vsi_res:
726 return ret;
727}
728
805bd5bd
MW		 729/**
730 * i40e_enable_vf_mappings
b40c82e6 731 * @vf: pointer to the VF info
805bd5bd 732 *
b40c82e6 733 * enable VF mappings
805bd5bd
MW		 734 **/
735static void i40e_enable_vf_mappings(struct i40e_vf *vf)
736{
737 struct i40e_pf *pf = vf->pf;
738 struct i40e_hw *hw = &pf->hw;
739 u32 reg, total_queue_pairs = 0;
740 int j;
741
742 /* Tell the hardware we're using noncontiguous mapping. HW requires
743 * that VF queues be mapped using this method, even when they are
744 * contiguous in real life
745 */
272cdaf2
SN		 746 i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),
747 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
805bd5bd
MW		 748
749 /* enable VF vplan_qtable mappings */
750 reg = I40E_VPLAN_MAPENA_TXRX_ENA_MASK;
751 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), reg);
752
753 /* map PF queues to VF queues */
fdf0e0bf
ASJ		 754 for (j = 0; j < pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs; j++) {
755 u16 qid = i40e_vc_get_pf_queue_id(vf, vf->lan_vsi_id, j);
6995b36c 756
805bd5bd
MW		 757 reg = (qid & I40E_VPLAN_QTABLE_QINDEX_MASK);
758 wr32(hw, I40E_VPLAN_QTABLE(total_queue_pairs, vf->vf_id), reg);
759 total_queue_pairs++;
760 }
761
762 /* map PF queues to VSI */
763 for (j = 0; j < 7; j++) {
fdf0e0bf 764 if (j * 2 >= pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs) {
805bd5bd
MW		 765 reg = 0x07FF07FF; /* unused */
766 } else {
fdf0e0bf 767 u16 qid = i40e_vc_get_pf_queue_id(vf, vf->lan_vsi_id,
805bd5bd
MW		 768 j * 2);
769 reg = qid;
fdf0e0bf 770 qid = i40e_vc_get_pf_queue_id(vf, vf->lan_vsi_id,
805bd5bd
MW		 771 (j * 2) + 1);
772 reg |= qid << 16;
773 }
272cdaf2
SN		 774 i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id),
775 reg);
805bd5bd
MW		 776 }
777
778 i40e_flush(hw);
779}
780
781/**
782 * i40e_disable_vf_mappings
b40c82e6 783 * @vf: pointer to the VF info
805bd5bd 784 *
b40c82e6 785 * disable VF mappings
805bd5bd
MW		 786 **/
787static void i40e_disable_vf_mappings(struct i40e_vf *vf)
788{
789 struct i40e_pf *pf = vf->pf;
790 struct i40e_hw *hw = &pf->hw;
791 int i;
792
793 /* disable qp mappings */
794 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), 0);
795 for (i = 0; i < I40E_MAX_VSI_QP; i++)
796 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_id),
797 I40E_QUEUE_END_OF_LIST);
798 i40e_flush(hw);
799}
800
801/**
802 * i40e_free_vf_res
b40c82e6 803 * @vf: pointer to the VF info
805bd5bd 804 *
b40c82e6 805 * free VF resources
805bd5bd
MW		 806 **/
807static void i40e_free_vf_res(struct i40e_vf *vf)
808{
809 struct i40e_pf *pf = vf->pf;
fc18eaa0
MW		 810 struct i40e_hw *hw = &pf->hw;
811 u32 reg_idx, reg;
812 int i, msix_vf;
805bd5bd
MW		 813
814 /* free vsi & disconnect it from the parent uplink */
fdf0e0bf
ASJ		 815 if (vf->lan_vsi_idx) {
816 i40e_vsi_release(pf->vsi[vf->lan_vsi_idx]);
817 vf->lan_vsi_idx = 0;
805bd5bd 818 vf->lan_vsi_id = 0;
13fd3f9c 819 vf->num_mac = 0;
805bd5bd 820 }
9347eb77
MW		 821 msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
822
fc18eaa0
MW		 823 /* disable interrupts so the VF starts in a known state */
824 for (i = 0; i < msix_vf; i++) {
825 /* format is same for both registers */
826 if (0 == i)
827 reg_idx = I40E_VFINT_DYN_CTL0(vf->vf_id);
828 else
829 reg_idx = I40E_VFINT_DYN_CTLN(((msix_vf - 1) *
830 (vf->vf_id))
831 + (i - 1));
832 wr32(hw, reg_idx, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
833 i40e_flush(hw);
834 }
805bd5bd 835
fc18eaa0
MW		 836 /* clear the irq settings */
837 for (i = 0; i < msix_vf; i++) {
838 /* format is same for both registers */
839 if (0 == i)
840 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id);
841 else
842 reg_idx = I40E_VPINT_LNKLSTN(((msix_vf - 1) *
843 (vf->vf_id))
844 + (i - 1));
845 reg = (I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK |
846 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
847 wr32(hw, reg_idx, reg);
848 i40e_flush(hw);
849 }
b564d62e 850 /* reset some of the state variables keeping track of the resources */
805bd5bd
MW		 851 vf->num_queue_pairs = 0;
852 vf->vf_states = 0;
21be99ec 853 clear_bit(I40E_VF_STAT_INIT, &vf->vf_states);
805bd5bd
MW		 854}
855
856/**
857 * i40e_alloc_vf_res
b40c82e6 858 * @vf: pointer to the VF info
805bd5bd 859 *
b40c82e6 860 * allocate VF resources
805bd5bd
MW		 861 **/
862static int i40e_alloc_vf_res(struct i40e_vf *vf)
863{
864 struct i40e_pf *pf = vf->pf;
865 int total_queue_pairs = 0;
866 int ret;
867
868 /* allocate hw vsi context & associated resources */
869 ret = i40e_alloc_vsi_res(vf, I40E_VSI_SRIOV);
870 if (ret)
871 goto error_alloc;
fdf0e0bf 872 total_queue_pairs += pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs;
692fb0a7
ASJ		 873
874 if (vf->trusted)
875 set_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
876 else
877 clear_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
805bd5bd
MW		 878
879 /* store the total qps number for the runtime
b40c82e6 880 * VF req validation
805bd5bd
MW		 881 */
882 vf->num_queue_pairs = total_queue_pairs;
883
b40c82e6 884 /* VF is now completely initialized */
805bd5bd
MW		 885 set_bit(I40E_VF_STAT_INIT, &vf->vf_states);
886
887error_alloc:
888 if (ret)
889 i40e_free_vf_res(vf);
890
891 return ret;
892}
893
fc18eaa0
MW		 894#define VF_DEVICE_STATUS 0xAA
895#define VF_TRANS_PENDING_MASK 0x20
896/**
897 * i40e_quiesce_vf_pci
b40c82e6 898 * @vf: pointer to the VF structure
fc18eaa0
MW		 899 *
900 * Wait for VF PCI transactions to be cleared after reset. Returns -EIO
901 * if the transactions never clear.
902 **/
903static int i40e_quiesce_vf_pci(struct i40e_vf *vf)
904{
905 struct i40e_pf *pf = vf->pf;
906 struct i40e_hw *hw = &pf->hw;
907 int vf_abs_id, i;
908 u32 reg;
909
b141d619 910 vf_abs_id = vf->vf_id + hw->func_caps.vf_base_id;
fc18eaa0
MW		 911
912 wr32(hw, I40E_PF_PCI_CIAA,
913 VF_DEVICE_STATUS | (vf_abs_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
914 for (i = 0; i < 100; i++) {
915 reg = rd32(hw, I40E_PF_PCI_CIAD);
916 if ((reg & VF_TRANS_PENDING_MASK) == 0)
917 return 0;
918 udelay(1);
919 }
920 return -EIO;
921}
922
5c3c48ac
JB		 923/**
924 * i40e_reset_vf
b40c82e6 925 * @vf: pointer to the VF structure
5c3c48ac
JB		 926 * @flr: VFLR was issued or not
927 *
b40c82e6 928 * reset the VF
5c3c48ac 929 **/
fc18eaa0 930void i40e_reset_vf(struct i40e_vf *vf, bool flr)
5c3c48ac 931{
5c3c48ac
JB		 932 struct i40e_pf *pf = vf->pf;
933 struct i40e_hw *hw = &pf->hw;
7e5a313e 934 u32 reg, reg_idx, bit_idx;
5c3c48ac 935 bool rsd = false;
fc18eaa0 936 int i;
5c3c48ac 937
3ba9bcb4
MW		 938 if (test_and_set_bit(__I40E_VF_DISABLE, &pf->state))
939 return;
940
5c3c48ac 941 /* warn the VF */
5c3c48ac
JB		 942 clear_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);
943
fc18eaa0
MW		 944 /* In the case of a VFLR, the HW has already reset the VF and we
945 * just need to clean up, so don't hit the VFRTRIG register.
5c3c48ac
JB		 946 */
947 if (!flr) {
b40c82e6 948 /* reset VF using VPGEN_VFRTRIG reg */
fc18eaa0
MW		 949 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id));
950 reg |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
5c3c48ac
JB		 951 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
952 i40e_flush(hw);
953 }
7369ca87
MW		 954 /* clear the VFLR bit in GLGEN_VFLRSTAT */
955 reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32;
956 bit_idx = (hw->func_caps.vf_base_id + vf->vf_id) % 32;
957 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
30728c5b 958 i40e_flush(hw);
5c3c48ac 959
fc18eaa0
MW		 960 if (i40e_quiesce_vf_pci(vf))
961 dev_err(&pf->pdev->dev, "VF %d PCI transactions stuck\n",
962 vf->vf_id);
963
5c3c48ac
JB		 964 /* poll VPGEN_VFRSTAT reg to make sure
965 * that reset is complete
966 */
1750a22f
MW		 967 for (i = 0; i < 10; i++) {
968 /* VF reset requires driver to first reset the VF and then
969 * poll the status register to make sure that the reset
970 * completed successfully. Due to internal HW FIFO flushes,
971 * we must wait 10ms before the register will be valid.
5c3c48ac 972 */
1750a22f 973 usleep_range(10000, 20000);
5c3c48ac
JB		 974 reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id));
975 if (reg & I40E_VPGEN_VFRSTAT_VFRD_MASK) {
976 rsd = true;
977 break;
978 }
979 }
980
57175ac1
ASJ		 981 if (flr)
982 usleep_range(10000, 20000);
983
5c3c48ac 984 if (!rsd)
fc18eaa0 985 dev_err(&pf->pdev->dev, "VF reset check timeout on VF %d\n",
5c3c48ac 986 vf->vf_id);
fc18eaa0 987 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_COMPLETED);
5c3c48ac
JB		 988 /* clear the reset bit in the VPGEN_VFRTRIG reg */
989 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id));
990 reg &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
991 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
fc18eaa0
MW		 992
993 /* On initial reset, we won't have any queues */
fdf0e0bf 994 if (vf->lan_vsi_idx == 0)
fc18eaa0
MW		 995 goto complete_reset;
996
3aa7b74d 997 i40e_vsi_stop_rings(pf->vsi[vf->lan_vsi_idx]);
fc18eaa0 998complete_reset:
b40c82e6 999 /* reallocate VF resources to reset the VSI state */
fc18eaa0 1000 i40e_free_vf_res(vf);
21be99ec 1001 if (!i40e_alloc_vf_res(vf)) {
e3219ce6 1002 int abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
21be99ec
MW		 1003 i40e_enable_vf_mappings(vf);
1004 set_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);
1005 clear_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6a23449a
AD		 1006 /* Do not notify the client during VF init */
1007 if (vf->pf->num_alloc_vfs)
1008 i40e_notify_client_of_vf_reset(pf, abs_vf_id);
dc5b4e9f 1009 vf->num_vlan = 0;
21be99ec 1010 }
5c3c48ac 1011 /* tell the VF the reset is done */
fc18eaa0 1012 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);
7e5a313e 1013
5c3c48ac 1014 i40e_flush(hw);
3ba9bcb4 1015 clear_bit(__I40E_VF_DISABLE, &pf->state);
5c3c48ac 1016}
c354229f 1017
5c3c48ac
JB		 1018/**
1019 * i40e_free_vfs
b40c82e6 1020 * @pf: pointer to the PF structure
5c3c48ac 1021 *
b40c82e6 1022 * free VF resources
5c3c48ac
JB		 1023 **/
1024void i40e_free_vfs(struct i40e_pf *pf)
1025{
f7414531
MW		 1026 struct i40e_hw *hw = &pf->hw;
1027 u32 reg_idx, bit_idx;
1028 int i, tmp, vf_id;
5c3c48ac
JB		 1029
1030 if (!pf->vf)
1031 return;
3ba9bcb4
MW		 1032 while (test_and_set_bit(__I40E_VF_DISABLE, &pf->state))
1033 usleep_range(1000, 2000);
5c3c48ac 1034
e3219ce6 1035 i40e_notify_client_of_vf_enable(pf, 0);
0325fca7
MW		 1036 for (i = 0; i < pf->num_alloc_vfs; i++)
1037 if (test_bit(I40E_VF_STAT_INIT, &pf->vf[i].vf_states))
3aa7b74d 1038 i40e_vsi_stop_rings(pf->vsi[pf->vf[i].lan_vsi_idx]);
44434638 1039
6a9ddb36
MW		 1040 /* Disable IOV before freeing resources. This lets any VF drivers
1041 * running in the host get themselves cleaned up before we yank
1042 * the carpet out from underneath their feet.
1043 */
1044 if (!pci_vfs_assigned(pf->pdev))
1045 pci_disable_sriov(pf->pdev);
6d7b967d
MW		 1046 else
1047 dev_warn(&pf->pdev->dev, "VFs are assigned - not disabling SR-IOV\n");
6a9ddb36
MW		 1048
1049 msleep(20); /* let any messages in transit get finished up */
1050
b40c82e6 1051 /* free up VF resources */
6c1b5bff
MW		 1052 tmp = pf->num_alloc_vfs;
1053 pf->num_alloc_vfs = 0;
1054 for (i = 0; i < tmp; i++) {
5c3c48ac
JB		 1055 if (test_bit(I40E_VF_STAT_INIT, &pf->vf[i].vf_states))
1056 i40e_free_vf_res(&pf->vf[i]);
1057 /* disable qp mappings */
1058 i40e_disable_vf_mappings(&pf->vf[i]);
1059 }
1060
1061 kfree(pf->vf);
1062 pf->vf = NULL;
5c3c48ac 1063
9e5634df
MW		 1064 /* This check is for when the driver is unloaded while VFs are
1065 * assigned. Setting the number of VFs to 0 through sysfs is caught
1066 * before this function ever gets called.
1067 */
c24817b6 1068 if (!pci_vfs_assigned(pf->pdev)) {
f7414531
MW		 1069 /* Acknowledge VFLR for all VFS. Without this, VFs will fail to
1070 * work correctly when SR-IOV gets re-enabled.
1071 */
1072 for (vf_id = 0; vf_id < tmp; vf_id++) {
1073 reg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;
1074 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
41a1d04b 1075 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
f7414531 1076 }
c354229f 1077 }
3ba9bcb4 1078 clear_bit(__I40E_VF_DISABLE, &pf->state);
5c3c48ac
JB		 1079}
1080
1081#ifdef CONFIG_PCI_IOV
1082/**
1083 * i40e_alloc_vfs
b40c82e6
JK		 1084 * @pf: pointer to the PF structure
1085 * @num_alloc_vfs: number of VFs to allocate
5c3c48ac 1086 *
b40c82e6 1087 * allocate VF resources
5c3c48ac 1088 **/
4aeec010 1089int i40e_alloc_vfs(struct i40e_pf *pf, u16 num_alloc_vfs)
5c3c48ac
JB		 1090{
1091 struct i40e_vf *vfs;
1092 int i, ret = 0;
1093
6c1b5bff 1094 /* Disable interrupt 0 so we don't try to handle the VFLR. */
2ef28cfb
MW		 1095 i40e_irq_dynamic_disable_icr0(pf);
1096
4aeec010
MW		 1097 /* Check to see if we're just allocating resources for extant VFs */
1098 if (pci_num_vf(pf->pdev) != num_alloc_vfs) {
1099 ret = pci_enable_sriov(pf->pdev, num_alloc_vfs);
1100 if (ret) {
de445b3d 1101 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
4aeec010
MW		 1102 pf->num_alloc_vfs = 0;
1103 goto err_iov;
1104 }
5c3c48ac 1105 }
5c3c48ac 1106 /* allocate memory */
cc6456af 1107 vfs = kcalloc(num_alloc_vfs, sizeof(struct i40e_vf), GFP_KERNEL);
5c3c48ac
JB		 1108 if (!vfs) {
1109 ret = -ENOMEM;
1110 goto err_alloc;
1111 }
c674d125 1112 pf->vf = vfs;
5c3c48ac
JB		 1113
1114 /* apply default profile */
1115 for (i = 0; i < num_alloc_vfs; i++) {
1116 vfs[i].pf = pf;
1117 vfs[i].parent_type = I40E_SWITCH_ELEMENT_TYPE_VEB;
1118 vfs[i].vf_id = i;
1119
1120 /* assign default capabilities */
1121 set_bit(I40E_VIRTCHNL_VF_CAP_L2, &vfs[i].vf_caps);
c674d125 1122 vfs[i].spoofchk = true;
b40c82e6 1123 /* VF resources get allocated during reset */
fc18eaa0 1124 i40e_reset_vf(&vfs[i], false);
5c3c48ac 1125
5c3c48ac 1126 }
5c3c48ac
JB		 1127 pf->num_alloc_vfs = num_alloc_vfs;
1128
6a23449a
AD		 1129 i40e_notify_client_of_vf_enable(pf, num_alloc_vfs);
1130
5c3c48ac
JB		 1131err_alloc:
1132 if (ret)
1133 i40e_free_vfs(pf);
1134err_iov:
6c1b5bff 1135 /* Re-enable interrupt 0. */
40d72a50 1136 i40e_irq_dynamic_enable_icr0(pf, false);
5c3c48ac
JB		 1137 return ret;
1138}
1139
1140#endif
1141/**
1142 * i40e_pci_sriov_enable
1143 * @pdev: pointer to a pci_dev structure
b40c82e6 1144 * @num_vfs: number of VFs to allocate
5c3c48ac
JB		 1145 *
1146 * Enable or change the number of VFs
1147 **/
1148static int i40e_pci_sriov_enable(struct pci_dev *pdev, int num_vfs)
1149{
1150#ifdef CONFIG_PCI_IOV
1151 struct i40e_pf *pf = pci_get_drvdata(pdev);
1152 int pre_existing_vfs = pci_num_vf(pdev);
1153 int err = 0;
1154
6995b36c 1155 if (test_bit(__I40E_TESTING, &pf->state)) {
e17bc411
GR		 1156 dev_warn(&pdev->dev,
1157 "Cannot enable SR-IOV virtual functions while the device is undergoing diagnostic testing\n");
1158 err = -EPERM;
1159 goto err_out;
1160 }
1161
5c3c48ac
JB		 1162 if (pre_existing_vfs && pre_existing_vfs != num_vfs)
1163 i40e_free_vfs(pf);
1164 else if (pre_existing_vfs && pre_existing_vfs == num_vfs)
1165 goto out;
1166
1167 if (num_vfs > pf->num_req_vfs) {
96c8d073
MW		 1168 dev_warn(&pdev->dev, "Unable to enable %d VFs. Limited to %d VFs due to device resource constraints.\n",
1169 num_vfs, pf->num_req_vfs);
5c3c48ac
JB		 1170 err = -EPERM;
1171 goto err_out;
1172 }
1173
96c8d073 1174 dev_info(&pdev->dev, "Allocating %d VFs.\n", num_vfs);
5c3c48ac
JB		 1175 err = i40e_alloc_vfs(pf, num_vfs);
1176 if (err) {
1177 dev_warn(&pdev->dev, "Failed to enable SR-IOV: %d\n", err);
1178 goto err_out;
1179 }
1180
1181out:
1182 return num_vfs;
1183
1184err_out:
1185 return err;
1186#endif
1187 return 0;
1188}
1189
1190/**
1191 * i40e_pci_sriov_configure
1192 * @pdev: pointer to a pci_dev structure
b40c82e6 1193 * @num_vfs: number of VFs to allocate
5c3c48ac
JB		 1194 *
1195 * Enable or change the number of VFs. Called when the user updates the number
1196 * of VFs in sysfs.
1197 **/
1198int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
1199{
1200 struct i40e_pf *pf = pci_get_drvdata(pdev);
1201
fc60861e
ASJ		 1202 if (num_vfs) {
1203 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
1204 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
1205 i40e_do_reset_safe(pf,
1206 BIT_ULL(__I40E_PF_RESET_REQUESTED));
1207 }
5c3c48ac 1208 return i40e_pci_sriov_enable(pdev, num_vfs);
fc60861e 1209 }
5c3c48ac 1210
c24817b6 1211 if (!pci_vfs_assigned(pf->pdev)) {
9e5634df 1212 i40e_free_vfs(pf);
fc60861e
ASJ		 1213 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
1214 i40e_do_reset_safe(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
9e5634df
MW		 1215 } else {
1216 dev_warn(&pdev->dev, "Unable to free VFs because some are assigned to VMs.\n");
1217 return -EINVAL;
1218 }
5c3c48ac
JB		 1219 return 0;
1220}
1221
1222/***********************virtual channel routines******************/
1223
1224/**
1225 * i40e_vc_send_msg_to_vf
b40c82e6 1226 * @vf: pointer to the VF info
5c3c48ac
JB		 1227 * @v_opcode: virtual channel opcode
1228 * @v_retval: virtual channel return value
1229 * @msg: pointer to the msg buffer
1230 * @msglen: msg length
1231 *
b40c82e6 1232 * send msg to VF
5c3c48ac
JB		 1233 **/
1234static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode,
1235 u32 v_retval, u8 *msg, u16 msglen)
1236{
6e7b5bd3
ASJ		 1237 struct i40e_pf *pf;
1238 struct i40e_hw *hw;
1239 int abs_vf_id;
5c3c48ac
JB		 1240 i40e_status aq_ret;
1241
6e7b5bd3
ASJ		 1242 /* validate the request */
1243 if (!vf || vf->vf_id >= vf->pf->num_alloc_vfs)
1244 return -EINVAL;
1245
1246 pf = vf->pf;
1247 hw = &pf->hw;
1248 abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
1249
5c3c48ac
JB		 1250 /* single place to detect unsuccessful return values */
1251 if (v_retval) {
1252 vf->num_invalid_msgs++;
18b7af57
MW		 1253 dev_info(&pf->pdev->dev, "VF %d failed opcode %d, retval: %d\n",
1254 vf->vf_id, v_opcode, v_retval);
5c3c48ac
JB		 1255 if (vf->num_invalid_msgs >
1256 I40E_DEFAULT_NUM_INVALID_MSGS_ALLOWED) {
1257 dev_err(&pf->pdev->dev,
1258 "Number of invalid messages exceeded for VF %d\n",
1259 vf->vf_id);
1260 dev_err(&pf->pdev->dev, "Use PF Control I/F to enable the VF\n");
1261 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
1262 }
1263 } else {
1264 vf->num_valid_msgs++;
5d38c93e
JW		 1265 /* reset the invalid counter, if a valid message is received. */
1266 vf->num_invalid_msgs = 0;
5c3c48ac
JB		 1267 }
1268
f19efbb5 1269 aq_ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
7efa84b7 1270 msg, msglen, NULL);
5c3c48ac 1271 if (aq_ret) {
18b7af57
MW		 1272 dev_info(&pf->pdev->dev,
1273 "Unable to send the message to VF %d aq_err %d\n",
1274 vf->vf_id, pf->hw.aq.asq_last_status);
5c3c48ac
JB		 1275 return -EIO;
1276 }
1277
1278 return 0;
1279}
1280
1281/**
1282 * i40e_vc_send_resp_to_vf
b40c82e6 1283 * @vf: pointer to the VF info
5c3c48ac
JB		 1284 * @opcode: operation code
1285 * @retval: return value
1286 *
b40c82e6 1287 * send resp msg to VF
5c3c48ac
JB		 1288 **/
1289static int i40e_vc_send_resp_to_vf(struct i40e_vf *vf,
1290 enum i40e_virtchnl_ops opcode,
1291 i40e_status retval)
1292{
1293 return i40e_vc_send_msg_to_vf(vf, opcode, retval, NULL, 0);
1294}
1295
1296/**
1297 * i40e_vc_get_version_msg
b40c82e6 1298 * @vf: pointer to the VF info
5c3c48ac 1299 *
b40c82e6 1300 * called from the VF to request the API version used by the PF
5c3c48ac 1301 **/
f4ca1a22 1302static int i40e_vc_get_version_msg(struct i40e_vf *vf, u8 *msg)
5c3c48ac
JB		 1303{
1304 struct i40e_virtchnl_version_info info = {
1305 I40E_VIRTCHNL_VERSION_MAJOR, I40E_VIRTCHNL_VERSION_MINOR
1306 };
1307
f4ca1a22 1308 vf->vf_ver = *(struct i40e_virtchnl_version_info *)msg;
606a5488
MW		 1309 /* VFs running the 1.0 API expect to get 1.0 back or they will cry. */
1310 if (VF_IS_V10(vf))
1311 info.minor = I40E_VIRTCHNL_VERSION_MINOR_NO_VF_CAPS;
5c3c48ac
JB		 1312 return i40e_vc_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_VERSION,
1313 I40E_SUCCESS, (u8 *)&info,
1314 sizeof(struct
1315 i40e_virtchnl_version_info));
1316}
1317
1318/**
1319 * i40e_vc_get_vf_resources_msg
b40c82e6 1320 * @vf: pointer to the VF info
5c3c48ac
JB		 1321 * @msg: pointer to the msg buffer
1322 * @msglen: msg length
1323 *
b40c82e6 1324 * called from the VF to request its resources
5c3c48ac 1325 **/
f4ca1a22 1326static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
5c3c48ac
JB		 1327{
1328 struct i40e_virtchnl_vf_resource *vfres = NULL;
1329 struct i40e_pf *pf = vf->pf;
1330 i40e_status aq_ret = 0;
1331 struct i40e_vsi *vsi;
5c3c48ac 1332 int num_vsis = 1;
442b25e4 1333 int len = 0;
5c3c48ac
JB		 1334 int ret;
1335
1336 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
1337 aq_ret = I40E_ERR_PARAM;
1338 goto err;
1339 }
1340
1341 len = (sizeof(struct i40e_virtchnl_vf_resource) +
1342 sizeof(struct i40e_virtchnl_vsi_resource) * num_vsis);
1343
1344 vfres = kzalloc(len, GFP_KERNEL);
1345 if (!vfres) {
1346 aq_ret = I40E_ERR_NO_MEMORY;
1347 len = 0;
1348 goto err;
1349 }
f4ca1a22
MW		 1350 if (VF_IS_V11(vf))
1351 vf->driver_caps = *(u32 *)msg;
1352 else
1353 vf->driver_caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
1354 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
1355 I40E_VIRTCHNL_VF_OFFLOAD_VLAN;
5c3c48ac
JB		 1356
1357 vfres->vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2;
fdf0e0bf 1358 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac 1359 if (!vsi->info.pvid)
e25d00b8 1360 vfres->vf_offload_flags |= I40E_VIRTCHNL_VF_OFFLOAD_VLAN;
e3219ce6
ASJ		 1361
1362 if (i40e_vf_client_capable(pf, vf->vf_id, I40E_CLIENT_IWARP) &&
1363 (vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_IWARP)) {
1364 vfres->vf_offload_flags |= I40E_VIRTCHNL_VF_OFFLOAD_IWARP;
1365 set_bit(I40E_VF_STAT_IWARPENA, &vf->vf_states);
1366 }
1367
c4e1868c
MW		 1368 if (vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RSS_PF) {
1369 vfres->vf_offload_flags |= I40E_VIRTCHNL_VF_OFFLOAD_RSS_PF;
e25d00b8 1370 } else {
c4e1868c
MW		 1371 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
1372 (vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ))
1373 vfres->vf_offload_flags |=
1374 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ;
1375 else
1376 vfres->vf_offload_flags |=
1377 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG;
e25d00b8 1378 }
1f012279 1379
3d0da5b7
ASJ		 1380 if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) {
1381 if (vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2)
1382 vfres->vf_offload_flags |=
1383 I40E_VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2;
1384 }
1385
14c5f5d2
SN		 1386 if (vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING) {
1387 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
1388 dev_err(&pf->pdev->dev,
1389 "VF %d requested polling mode: this feature is supported only when the device is running in single function per port (SFP) mode\n",
1390 vf->vf_id);
1391 ret = I40E_ERR_PARAM;
1392 goto err;
1393 }
1f012279 1394 vfres->vf_offload_flags |= I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
14c5f5d2 1395 }
1f012279 1396
f6d83d13
ASJ		 1397 if (pf->flags & I40E_FLAG_WB_ON_ITR_CAPABLE) {
1398 if (vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_WB_ON_ITR)
1399 vfres->vf_offload_flags |=
1400 I40E_VIRTCHNL_VF_OFFLOAD_WB_ON_ITR;
1401 }
1402
5c3c48ac
JB		 1403 vfres->num_vsis = num_vsis;
1404 vfres->num_queue_pairs = vf->num_queue_pairs;
1405 vfres->max_vectors = pf->hw.func_caps.num_msix_vectors_vf;
c4e1868c
MW		 1406 vfres->rss_key_size = I40E_HKEY_ARRAY_SIZE;
1407 vfres->rss_lut_size = I40E_VF_HLUT_ARRAY_SIZE;
1408
fdf0e0bf 1409 if (vf->lan_vsi_idx) {
442b25e4
MW		 1410 vfres->vsi_res[0].vsi_id = vf->lan_vsi_id;
1411 vfres->vsi_res[0].vsi_type = I40E_VSI_SRIOV;
1412 vfres->vsi_res[0].num_queue_pairs = vsi->alloc_queue_pairs;
f578f5f4 1413 /* VFs only use TC 0 */
442b25e4 1414 vfres->vsi_res[0].qset_handle
f578f5f4 1415 = le16_to_cpu(vsi->info.qs_handle[0]);
442b25e4 1416 ether_addr_copy(vfres->vsi_res[0].default_mac_addr,
6995b36c 1417 vf->default_lan_addr.addr);
5c3c48ac
JB		 1418 }
1419 set_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);
1420
1421err:
b40c82e6 1422 /* send the response back to the VF */
5c3c48ac
JB		 1423 ret = i40e_vc_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
1424 aq_ret, (u8 *)vfres, len);
1425
1426 kfree(vfres);
1427 return ret;
1428}
1429
1430/**
1431 * i40e_vc_reset_vf_msg
b40c82e6 1432 * @vf: pointer to the VF info
5c3c48ac
JB		 1433 * @msg: pointer to the msg buffer
1434 * @msglen: msg length
1435 *
b40c82e6
JK		 1436 * called from the VF to reset itself,
1437 * unlike other virtchnl messages, PF driver
1438 * doesn't send the response back to the VF
5c3c48ac 1439 **/
fc18eaa0 1440static void i40e_vc_reset_vf_msg(struct i40e_vf *vf)
5c3c48ac 1441{
fc18eaa0
MW		 1442 if (test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states))
1443 i40e_reset_vf(vf, false);
5c3c48ac
JB		 1444}
1445
5676a8b9
ASJ		 1446/**
1447 * i40e_getnum_vf_vsi_vlan_filters
1448 * @vsi: pointer to the vsi
1449 *
1450 * called to get the number of VLANs offloaded on this VF
1451 **/
1452static inline int i40e_getnum_vf_vsi_vlan_filters(struct i40e_vsi *vsi)
1453{
1454 struct i40e_mac_filter *f;
278e7d0b 1455 int num_vlans = 0, bkt;
5676a8b9 1456
278e7d0b 1457 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) {
5676a8b9
ASJ		 1458 if (f->vlan >= 0 && f->vlan <= I40E_MAX_VLANID)
1459 num_vlans++;
1460 }
1461
1462 return num_vlans;
1463}
1464
5c3c48ac
JB		 1465/**
1466 * i40e_vc_config_promiscuous_mode_msg
b40c82e6 1467 * @vf: pointer to the VF info
5c3c48ac
JB		 1468 * @msg: pointer to the msg buffer
1469 * @msglen: msg length
1470 *
b40c82e6
JK		 1471 * called from the VF to configure the promiscuous mode of
1472 * VF vsis
5c3c48ac
JB		 1473 **/
1474static int i40e_vc_config_promiscuous_mode_msg(struct i40e_vf *vf,
1475 u8 *msg, u16 msglen)
1476{
1477 struct i40e_virtchnl_promisc_info *info =
1478 (struct i40e_virtchnl_promisc_info *)msg;
1479 struct i40e_pf *pf = vf->pf;
1480 struct i40e_hw *hw = &pf->hw;
5676a8b9
ASJ		 1481 struct i40e_mac_filter *f;
1482 i40e_status aq_ret = 0;
5c3c48ac 1483 bool allmulti = false;
5676a8b9
ASJ		 1484 struct i40e_vsi *vsi;
1485 bool alluni = false;
1486 int aq_err = 0;
278e7d0b 1487 int bkt;
5c3c48ac 1488
fdf0e0bf 1489 vsi = i40e_find_vsi_from_id(pf, info->vsi_id);
5c3c48ac 1490 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
d4a0658d
CW		 1491 !i40e_vc_isvalid_vsi_id(vf, info->vsi_id) ||
1492 !vsi) {
eee4172a
MW		 1493 aq_ret = I40E_ERR_PARAM;
1494 goto error_param;
1495 }
1496 if (!test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps)) {
5676a8b9 1497 dev_err(&pf->pdev->dev,
eee4172a 1498 "Unprivileged VF %d is attempting to configure promiscuous mode\n",
5676a8b9 1499 vf->vf_id);
eee4172a
MW		 1500 /* Lie to the VF on purpose. */
1501 aq_ret = 0;
5c3c48ac
JB		 1502 goto error_param;
1503 }
5676a8b9 1504 /* Multicast promiscuous handling*/
5c3c48ac
JB		 1505 if (info->flags & I40E_FLAG_VF_MULTICAST_PROMISC)
1506 allmulti = true;
5676a8b9
ASJ		 1507
1508 if (vf->port_vlan_id) {
1509 aq_ret = i40e_aq_set_vsi_mc_promisc_on_vlan(hw, vsi->seid,
1510 allmulti,
1511 vf->port_vlan_id,
1512 NULL);
1513 } else if (i40e_getnum_vf_vsi_vlan_filters(vsi)) {
278e7d0b 1514 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) {
47d34839
ASJ		 1515 if (f->vlan < 0 || f->vlan > I40E_MAX_VLANID)
1516 continue;
1517 aq_ret = i40e_aq_set_vsi_mc_promisc_on_vlan(hw,
1518 vsi->seid,
1519 allmulti,
1520 f->vlan,
1521 NULL);
5676a8b9
ASJ		 1522 aq_err = pf->hw.aq.asq_last_status;
1523 if (aq_ret) {
1524 dev_err(&pf->pdev->dev,
1525 "Could not add VLAN %d to multicast promiscuous domain err %s aq_err %s\n",
1526 f->vlan,
1527 i40e_stat_str(&pf->hw, aq_ret),
1528 i40e_aq_str(&pf->hw, aq_err));
1529 break;
1530 }
1531 }
1532 } else {
1533 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1534 allmulti, NULL);
1535 aq_err = pf->hw.aq.asq_last_status;
1536 if (aq_ret) {
1537 dev_err(&pf->pdev->dev,
1538 "VF %d failed to set multicast promiscuous mode err %s aq_err %s\n",
1539 vf->vf_id,
1540 i40e_stat_str(&pf->hw, aq_ret),
1541 i40e_aq_str(&pf->hw, aq_err));
7429c0bd 1542 goto error_param;
5676a8b9
ASJ		 1543 }
1544 }
1545
1546 if (!aq_ret) {
1547 dev_info(&pf->pdev->dev,
1548 "VF %d successfully set multicast promiscuous mode\n",
1549 vf->vf_id);
1550 if (allmulti)
1551 set_bit(I40E_VF_STAT_MC_PROMISC, &vf->vf_states);
1552 else
1553 clear_bit(I40E_VF_STAT_MC_PROMISC, &vf->vf_states);
1554 }
1555
1556 if (info->flags & I40E_FLAG_VF_UNICAST_PROMISC)
1557 alluni = true;
1558 if (vf->port_vlan_id) {
1559 aq_ret = i40e_aq_set_vsi_uc_promisc_on_vlan(hw, vsi->seid,
1560 alluni,
1561 vf->port_vlan_id,
1562 NULL);
1563 } else if (i40e_getnum_vf_vsi_vlan_filters(vsi)) {
278e7d0b 1564 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) {
5676a8b9 1565 aq_ret = 0;
ce927db4 1566 if (f->vlan >= 0 && f->vlan <= I40E_MAX_VLANID) {
5676a8b9
ASJ		 1567 aq_ret =
1568 i40e_aq_set_vsi_uc_promisc_on_vlan(hw,
1569 vsi->seid,
1570 alluni,
1571 f->vlan,
1572 NULL);
1573 aq_err = pf->hw.aq.asq_last_status;
ce927db4 1574 }
5676a8b9
ASJ		 1575 if (aq_ret)
1576 dev_err(&pf->pdev->dev,
1577 "Could not add VLAN %d to Unicast promiscuous domain err %s aq_err %s\n",
1578 f->vlan,
1579 i40e_stat_str(&pf->hw, aq_ret),
1580 i40e_aq_str(&pf->hw, aq_err));
1581 }
1582 } else {
1583 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
b5569892
ASJ		 1584 allmulti, NULL,
1585 true);
5676a8b9 1586 aq_err = pf->hw.aq.asq_last_status;
7429c0bd 1587 if (aq_ret) {
5676a8b9
ASJ		 1588 dev_err(&pf->pdev->dev,
1589 "VF %d failed to set unicast promiscuous mode %8.8x err %s aq_err %s\n",
1590 vf->vf_id, info->flags,
1591 i40e_stat_str(&pf->hw, aq_ret),
1592 i40e_aq_str(&pf->hw, aq_err));
7429c0bd
JK		 1593 goto error_param;
1594 }
5676a8b9
ASJ		 1595 }
1596
5676a8b9
ASJ		 1597 if (!aq_ret) {
1598 dev_info(&pf->pdev->dev,
1599 "VF %d successfully set unicast promiscuous mode\n",
1600 vf->vf_id);
1601 if (alluni)
1602 set_bit(I40E_VF_STAT_UC_PROMISC, &vf->vf_states);
1603 else
1604 clear_bit(I40E_VF_STAT_UC_PROMISC, &vf->vf_states);
1605 }
5c3c48ac
JB		 1606
1607error_param:
b40c82e6 1608 /* send the response to the VF */
5c3c48ac
JB		 1609 return i40e_vc_send_resp_to_vf(vf,
1610 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE,
1611 aq_ret);
1612}
1613
1614/**
1615 * i40e_vc_config_queues_msg
b40c82e6 1616 * @vf: pointer to the VF info
5c3c48ac
JB		 1617 * @msg: pointer to the msg buffer
1618 * @msglen: msg length
1619 *
b40c82e6 1620 * called from the VF to configure the rx/tx
5c3c48ac
JB		 1621 * queues
1622 **/
1623static int i40e_vc_config_queues_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
1624{
1625 struct i40e_virtchnl_vsi_queue_config_info *qci =
1626 (struct i40e_virtchnl_vsi_queue_config_info *)msg;
1627 struct i40e_virtchnl_queue_pair_info *qpi;
5f5e33b6 1628 struct i40e_pf *pf = vf->pf;
5c3c48ac
JB		 1629 u16 vsi_id, vsi_queue_id;
1630 i40e_status aq_ret = 0;
1631 int i;
1632
1633 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states)) {
1634 aq_ret = I40E_ERR_PARAM;
1635 goto error_param;
1636 }
1637
1638 vsi_id = qci->vsi_id;
1639 if (!i40e_vc_isvalid_vsi_id(vf, vsi_id)) {
1640 aq_ret = I40E_ERR_PARAM;
1641 goto error_param;
1642 }
1643 for (i = 0; i < qci->num_queue_pairs; i++) {
1644 qpi = &qci->qpair[i];
1645 vsi_queue_id = qpi->txq.queue_id;
1646 if ((qpi->txq.vsi_id != vsi_id) ||
1647 (qpi->rxq.vsi_id != vsi_id) ||
1648 (qpi->rxq.queue_id != vsi_queue_id) ||
1649 !i40e_vc_isvalid_queue_id(vf, vsi_id, vsi_queue_id)) {
1650 aq_ret = I40E_ERR_PARAM;
1651 goto error_param;
1652 }
1653
1654 if (i40e_config_vsi_rx_queue(vf, vsi_id, vsi_queue_id,
1655 &qpi->rxq) ||
1656 i40e_config_vsi_tx_queue(vf, vsi_id, vsi_queue_id,
1657 &qpi->txq)) {
1658 aq_ret = I40E_ERR_PARAM;
1659 goto error_param;
1660 }
1661 }
b40c82e6 1662 /* set vsi num_queue_pairs in use to num configured by VF */
fdf0e0bf 1663 pf->vsi[vf->lan_vsi_idx]->num_queue_pairs = qci->num_queue_pairs;
5c3c48ac
JB		 1664
1665error_param:
b40c82e6 1666 /* send the response to the VF */
5c3c48ac
JB		 1667 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,
1668 aq_ret);
1669}
1670
1671/**
1672 * i40e_vc_config_irq_map_msg
b40c82e6 1673 * @vf: pointer to the VF info
5c3c48ac
JB		 1674 * @msg: pointer to the msg buffer
1675 * @msglen: msg length
1676 *
b40c82e6 1677 * called from the VF to configure the irq to
5c3c48ac
JB		 1678 * queue map
1679 **/
1680static int i40e_vc_config_irq_map_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
1681{
1682 struct i40e_virtchnl_irq_map_info *irqmap_info =
1683 (struct i40e_virtchnl_irq_map_info *)msg;
1684 struct i40e_virtchnl_vector_map *map;
1685 u16 vsi_id, vsi_queue_id, vector_id;
1686 i40e_status aq_ret = 0;
1687 unsigned long tempmap;
1688 int i;
1689
1690 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states)) {
1691 aq_ret = I40E_ERR_PARAM;
1692 goto error_param;
1693 }
1694
1695 for (i = 0; i < irqmap_info->num_vectors; i++) {
1696 map = &irqmap_info->vecmap[i];
1697
1698 vector_id = map->vector_id;
1699 vsi_id = map->vsi_id;
1700 /* validate msg params */
1701 if (!i40e_vc_isvalid_vector_id(vf, vector_id) ||
1702 !i40e_vc_isvalid_vsi_id(vf, vsi_id)) {
1703 aq_ret = I40E_ERR_PARAM;
1704 goto error_param;
1705 }
1706
1707 /* lookout for the invalid queue index */
1708 tempmap = map->rxq_map;
4836650b 1709 for_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {
5c3c48ac
JB		 1710 if (!i40e_vc_isvalid_queue_id(vf, vsi_id,
1711 vsi_queue_id)) {
1712 aq_ret = I40E_ERR_PARAM;
1713 goto error_param;
1714 }
5c3c48ac
JB		 1715 }
1716
1717 tempmap = map->txq_map;
4836650b 1718 for_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {
5c3c48ac
JB		 1719 if (!i40e_vc_isvalid_queue_id(vf, vsi_id,
1720 vsi_queue_id)) {
1721 aq_ret = I40E_ERR_PARAM;
1722 goto error_param;
1723 }
5c3c48ac
JB		 1724 }
1725
1726 i40e_config_irq_link_list(vf, vsi_id, map);
1727 }
1728error_param:
b40c82e6 1729 /* send the response to the VF */
5c3c48ac
JB		 1730 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,
1731 aq_ret);
1732}
1733
1734/**
1735 * i40e_vc_enable_queues_msg
b40c82e6 1736 * @vf: pointer to the VF info
5c3c48ac
JB		 1737 * @msg: pointer to the msg buffer
1738 * @msglen: msg length
1739 *
b40c82e6 1740 * called from the VF to enable all or specific queue(s)
5c3c48ac
JB		 1741 **/
1742static int i40e_vc_enable_queues_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
1743{
1744 struct i40e_virtchnl_queue_select *vqs =
1745 (struct i40e_virtchnl_queue_select *)msg;
1746 struct i40e_pf *pf = vf->pf;
1747 u16 vsi_id = vqs->vsi_id;
1748 i40e_status aq_ret = 0;
5c3c48ac
JB		 1749
1750 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states)) {
1751 aq_ret = I40E_ERR_PARAM;
1752 goto error_param;
1753 }
1754
1755 if (!i40e_vc_isvalid_vsi_id(vf, vsi_id)) {
1756 aq_ret = I40E_ERR_PARAM;
1757 goto error_param;
1758 }
1759
1760 if ((0 == vqs->rx_queues) && (0 == vqs->tx_queues)) {
1761 aq_ret = I40E_ERR_PARAM;
1762 goto error_param;
1763 }
fdf0e0bf 1764
3aa7b74d 1765 if (i40e_vsi_start_rings(pf->vsi[vf->lan_vsi_idx]))
88f6563d 1766 aq_ret = I40E_ERR_TIMEOUT;
5c3c48ac 1767error_param:
b40c82e6 1768 /* send the response to the VF */
5c3c48ac
JB		 1769 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES,
1770 aq_ret);
1771}
1772
1773/**
1774 * i40e_vc_disable_queues_msg
b40c82e6 1775 * @vf: pointer to the VF info
5c3c48ac
JB		 1776 * @msg: pointer to the msg buffer
1777 * @msglen: msg length
1778 *
b40c82e6 1779 * called from the VF to disable all or specific
5c3c48ac
JB		 1780 * queue(s)
1781 **/
1782static int i40e_vc_disable_queues_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
1783{
1784 struct i40e_virtchnl_queue_select *vqs =
1785 (struct i40e_virtchnl_queue_select *)msg;
1786 struct i40e_pf *pf = vf->pf;
5c3c48ac 1787 i40e_status aq_ret = 0;
5c3c48ac
JB		 1788
1789 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states)) {
1790 aq_ret = I40E_ERR_PARAM;
1791 goto error_param;
1792 }
1793
1794 if (!i40e_vc_isvalid_vsi_id(vf, vqs->vsi_id)) {
1795 aq_ret = I40E_ERR_PARAM;
1796 goto error_param;
1797 }
1798
1799 if ((0 == vqs->rx_queues) && (0 == vqs->tx_queues)) {
1800 aq_ret = I40E_ERR_PARAM;
1801 goto error_param;
1802 }
fdf0e0bf 1803
3aa7b74d 1804 i40e_vsi_stop_rings(pf->vsi[vf->lan_vsi_idx]);
5c3c48ac
JB		 1805
1806error_param:
b40c82e6 1807 /* send the response to the VF */
5c3c48ac
JB		 1808 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES,
1809 aq_ret);
1810}
1811
1812/**
1813 * i40e_vc_get_stats_msg
b40c82e6 1814 * @vf: pointer to the VF info
5c3c48ac
JB		 1815 * @msg: pointer to the msg buffer
1816 * @msglen: msg length
1817 *
b40c82e6 1818 * called from the VF to get vsi stats
5c3c48ac
JB		 1819 **/
1820static int i40e_vc_get_stats_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
1821{
1822 struct i40e_virtchnl_queue_select *vqs =
1823 (struct i40e_virtchnl_queue_select *)msg;
1824 struct i40e_pf *pf = vf->pf;
1825 struct i40e_eth_stats stats;
1826 i40e_status aq_ret = 0;
1827 struct i40e_vsi *vsi;
1828
1829 memset(&stats, 0, sizeof(struct i40e_eth_stats));
1830
1831 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states)) {
1832 aq_ret = I40E_ERR_PARAM;
1833 goto error_param;
1834 }
1835
1836 if (!i40e_vc_isvalid_vsi_id(vf, vqs->vsi_id)) {
1837 aq_ret = I40E_ERR_PARAM;
1838 goto error_param;
1839 }
1840
fdf0e0bf 1841 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac
JB		 1842 if (!vsi) {
1843 aq_ret = I40E_ERR_PARAM;
1844 goto error_param;
1845 }
1846 i40e_update_eth_stats(vsi);
5a9769c8 1847 stats = vsi->eth_stats;
5c3c48ac
JB		 1848
1849error_param:
b40c82e6 1850 /* send the response back to the VF */
5c3c48ac
JB		 1851 return i40e_vc_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_STATS, aq_ret,
1852 (u8 *)&stats, sizeof(stats));
1853}
1854
5f527ba9
ASJ		 1855/* If the VF is not trusted restrict the number of MAC/VLAN it can program */
1856#define I40E_VC_MAX_MAC_ADDR_PER_VF 8
1857#define I40E_VC_MAX_VLAN_PER_VF 8
1858
f657a6e1
GR		 1859/**
1860 * i40e_check_vf_permission
b40c82e6 1861 * @vf: pointer to the VF info
f657a6e1
GR		 1862 * @macaddr: pointer to the MAC Address being checked
1863 *
1864 * Check if the VF has permission to add or delete unicast MAC address
1865 * filters and return error code -EPERM if not. Then check if the
1866 * address filter requested is broadcast or zero and if so return
1867 * an invalid MAC address error code.
1868 **/
1869static inline int i40e_check_vf_permission(struct i40e_vf *vf, u8 *macaddr)
1870{
1871 struct i40e_pf *pf = vf->pf;
1872 int ret = 0;
1873
1874 if (is_broadcast_ether_addr(macaddr) ||
1875 is_zero_ether_addr(macaddr)) {
1876 dev_err(&pf->pdev->dev, "invalid VF MAC addr %pM\n", macaddr);
1877 ret = I40E_ERR_INVALID_MAC_ADDR;
5017c2a8 1878 } else if (vf->pf_set_mac && !is_multicast_ether_addr(macaddr) &&
692fb0a7 1879 !test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps) &&
5017c2a8 1880 !ether_addr_equal(macaddr, vf->default_lan_addr.addr)) {
f657a6e1
GR		 1881 /* If the host VMM administrator has set the VF MAC address
1882 * administratively via the ndo_set_vf_mac command then deny
1883 * permission to the VF to add or delete unicast MAC addresses.
692fb0a7 1884 * Unless the VF is privileged and then it can do whatever.
5017c2a8
GR		 1885 * The VF may request to set the MAC address filter already
1886 * assigned to it so do not return an error in that case.
f657a6e1
GR		 1887 */
1888 dev_err(&pf->pdev->dev,
692fb0a7 1889 "VF attempting to override administratively set MAC address, reload the VF driver to resume normal operation\n");
f657a6e1 1890 ret = -EPERM;
5f527ba9
ASJ		 1891 } else if ((vf->num_mac >= I40E_VC_MAX_MAC_ADDR_PER_VF) &&
1892 !test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps)) {
1893 dev_err(&pf->pdev->dev,
1894 "VF is not trusted, switch the VF to trusted to add more functionality\n");
1895 ret = -EPERM;
f657a6e1
GR		 1896 }
1897 return ret;
1898}
1899
5c3c48ac
JB		 1900/**
1901 * i40e_vc_add_mac_addr_msg
b40c82e6 1902 * @vf: pointer to the VF info
5c3c48ac
JB		 1903 * @msg: pointer to the msg buffer
1904 * @msglen: msg length
1905 *
1906 * add guest mac address filter
1907 **/
1908static int i40e_vc_add_mac_addr_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
1909{
1910 struct i40e_virtchnl_ether_addr_list *al =
1911 (struct i40e_virtchnl_ether_addr_list *)msg;
1912 struct i40e_pf *pf = vf->pf;
1913 struct i40e_vsi *vsi = NULL;
1914 u16 vsi_id = al->vsi_id;
f657a6e1 1915 i40e_status ret = 0;
5c3c48ac
JB		 1916 int i;
1917
1918 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
5c3c48ac 1919 !i40e_vc_isvalid_vsi_id(vf, vsi_id)) {
f657a6e1 1920 ret = I40E_ERR_PARAM;
5c3c48ac
JB		 1921 goto error_param;
1922 }
1923
1924 for (i = 0; i < al->num_elements; i++) {
f657a6e1
GR		 1925 ret = i40e_check_vf_permission(vf, al->list[i].addr);
1926 if (ret)
5c3c48ac 1927 goto error_param;
5c3c48ac 1928 }
fdf0e0bf 1929 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac 1930
21659035
KP		 1931 /* Lock once, because all function inside for loop accesses VSI's
1932 * MAC filter list which needs to be protected using same lock.
1933 */
278e7d0b 1934 spin_lock_bh(&vsi->mac_filter_hash_lock);
21659035 1935
5c3c48ac
JB		 1936 /* add new addresses to the list */
1937 for (i = 0; i < al->num_elements; i++) {
1938 struct i40e_mac_filter *f;
1939
1bc87e80 1940 f = i40e_find_mac(vsi, al->list[i].addr);
7aaf9536 1941 if (!f)
feffdbe4 1942 f = i40e_add_mac_filter(vsi, al->list[i].addr);
5c3c48ac
JB		 1943
1944 if (!f) {
1945 dev_err(&pf->pdev->dev,
8d8f2295
MW		 1946 "Unable to add MAC filter %pM for VF %d\n",
1947 al->list[i].addr, vf->vf_id);
f657a6e1 1948 ret = I40E_ERR_PARAM;
278e7d0b 1949 spin_unlock_bh(&vsi->mac_filter_hash_lock);
5c3c48ac 1950 goto error_param;
5f527ba9
ASJ		 1951 } else {
1952 vf->num_mac++;
5c3c48ac
JB		 1953 }
1954 }
278e7d0b 1955 spin_unlock_bh(&vsi->mac_filter_hash_lock);
5c3c48ac
JB		 1956
1957 /* program the updated filter list */
ea02e90b
MW		 1958 ret = i40e_sync_vsi_filters(vsi);
1959 if (ret)
1960 dev_err(&pf->pdev->dev, "Unable to program VF %d MAC filters, error %d\n",
1961 vf->vf_id, ret);
5c3c48ac
JB		 1962
1963error_param:
b40c82e6 1964 /* send the response to the VF */
5c3c48ac 1965 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,
f657a6e1 1966 ret);
5c3c48ac
JB		 1967}
1968
1969/**
1970 * i40e_vc_del_mac_addr_msg
b40c82e6 1971 * @vf: pointer to the VF info
5c3c48ac
JB		 1972 * @msg: pointer to the msg buffer
1973 * @msglen: msg length
1974 *
1975 * remove guest mac address filter
1976 **/
1977static int i40e_vc_del_mac_addr_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
1978{
1979 struct i40e_virtchnl_ether_addr_list *al =
1980 (struct i40e_virtchnl_ether_addr_list *)msg;
1981 struct i40e_pf *pf = vf->pf;
1982 struct i40e_vsi *vsi = NULL;
1983 u16 vsi_id = al->vsi_id;
f657a6e1 1984 i40e_status ret = 0;
5c3c48ac
JB		 1985 int i;
1986
1987 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
5c3c48ac 1988 !i40e_vc_isvalid_vsi_id(vf, vsi_id)) {
f657a6e1 1989 ret = I40E_ERR_PARAM;
5c3c48ac
JB		 1990 goto error_param;
1991 }
f657a6e1
GR		 1992
1993 for (i = 0; i < al->num_elements; i++) {
700bbf6c
MW		 1994 if (is_broadcast_ether_addr(al->list[i].addr) ||
1995 is_zero_ether_addr(al->list[i].addr)) {
8d8f2295
MW		 1996 dev_err(&pf->pdev->dev, "Invalid MAC addr %pM for VF %d\n",
1997 al->list[i].addr, vf->vf_id);
700bbf6c 1998 ret = I40E_ERR_INVALID_MAC_ADDR;
f657a6e1 1999 goto error_param;
700bbf6c 2000 }
f657a6e1 2001 }
fdf0e0bf 2002 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac 2003
278e7d0b 2004 spin_lock_bh(&vsi->mac_filter_hash_lock);
5c3c48ac
JB		 2005 /* delete addresses from the list */
2006 for (i = 0; i < al->num_elements; i++)
feffdbe4 2007 if (i40e_del_mac_filter(vsi, al->list[i].addr)) {
b36e9ab5 2008 ret = I40E_ERR_INVALID_MAC_ADDR;
278e7d0b 2009 spin_unlock_bh(&vsi->mac_filter_hash_lock);
b36e9ab5 2010 goto error_param;
5f527ba9
ASJ		 2011 } else {
2012 vf->num_mac--;
b36e9ab5
MW		 2013 }
2014
278e7d0b 2015 spin_unlock_bh(&vsi->mac_filter_hash_lock);
5c3c48ac
JB		 2016
2017 /* program the updated filter list */
ea02e90b
MW		 2018 ret = i40e_sync_vsi_filters(vsi);
2019 if (ret)
2020 dev_err(&pf->pdev->dev, "Unable to program VF %d MAC filters, error %d\n",
2021 vf->vf_id, ret);
5c3c48ac
JB		 2022
2023error_param:
b40c82e6 2024 /* send the response to the VF */
5c3c48ac 2025 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,
f657a6e1 2026 ret);
5c3c48ac
JB		 2027}
2028
2029/**
2030 * i40e_vc_add_vlan_msg
b40c82e6 2031 * @vf: pointer to the VF info
5c3c48ac
JB		 2032 * @msg: pointer to the msg buffer
2033 * @msglen: msg length
2034 *
2035 * program guest vlan id
2036 **/
2037static int i40e_vc_add_vlan_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
2038{
2039 struct i40e_virtchnl_vlan_filter_list *vfl =
2040 (struct i40e_virtchnl_vlan_filter_list *)msg;
2041 struct i40e_pf *pf = vf->pf;
2042 struct i40e_vsi *vsi = NULL;
2043 u16 vsi_id = vfl->vsi_id;
2044 i40e_status aq_ret = 0;
2045 int i;
2046
5f527ba9
ASJ		 2047 if ((vf->num_vlan >= I40E_VC_MAX_VLAN_PER_VF) &&
2048 !test_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps)) {
2049 dev_err(&pf->pdev->dev,
2050 "VF is not trusted, switch the VF to trusted to add more VLAN addresses\n");
2051 goto error_param;
2052 }
5c3c48ac 2053 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
5c3c48ac
JB		 2054 !i40e_vc_isvalid_vsi_id(vf, vsi_id)) {
2055 aq_ret = I40E_ERR_PARAM;
2056 goto error_param;
2057 }
2058
2059 for (i = 0; i < vfl->num_elements; i++) {
2060 if (vfl->vlan_id[i] > I40E_MAX_VLANID) {
2061 aq_ret = I40E_ERR_PARAM;
2062 dev_err(&pf->pdev->dev,
2063 "invalid VF VLAN id %d\n", vfl->vlan_id[i]);
2064 goto error_param;
2065 }
2066 }
fdf0e0bf 2067 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac
JB		 2068 if (vsi->info.pvid) {
2069 aq_ret = I40E_ERR_PARAM;
2070 goto error_param;
2071 }
2072
2073 i40e_vlan_stripping_enable(vsi);
2074 for (i = 0; i < vfl->num_elements; i++) {
2075 /* add new VLAN filter */
2076 int ret = i40e_vsi_add_vlan(vsi, vfl->vlan_id[i]);
5f527ba9
ASJ		 2077 if (!ret)
2078 vf->num_vlan++;
6995b36c 2079
5676a8b9
ASJ		 2080 if (test_bit(I40E_VF_STAT_UC_PROMISC, &vf->vf_states))
2081 i40e_aq_set_vsi_uc_promisc_on_vlan(&pf->hw, vsi->seid,
2082 true,
2083 vfl->vlan_id[i],
2084 NULL);
2085 if (test_bit(I40E_VF_STAT_MC_PROMISC, &vf->vf_states))
2086 i40e_aq_set_vsi_mc_promisc_on_vlan(&pf->hw, vsi->seid,
2087 true,
2088 vfl->vlan_id[i],
2089 NULL);
2090
5c3c48ac
JB		 2091 if (ret)
2092 dev_err(&pf->pdev->dev,
8d8f2295
MW		 2093 "Unable to add VLAN filter %d for VF %d, error %d\n",
2094 vfl->vlan_id[i], vf->vf_id, ret);
5c3c48ac
JB		 2095 }
2096
2097error_param:
b40c82e6 2098 /* send the response to the VF */
5c3c48ac
JB		 2099 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_ADD_VLAN, aq_ret);
2100}
2101
2102/**
2103 * i40e_vc_remove_vlan_msg
b40c82e6 2104 * @vf: pointer to the VF info
5c3c48ac
JB		 2105 * @msg: pointer to the msg buffer
2106 * @msglen: msg length
2107 *
2108 * remove programmed guest vlan id
2109 **/
2110static int i40e_vc_remove_vlan_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
2111{
2112 struct i40e_virtchnl_vlan_filter_list *vfl =
2113 (struct i40e_virtchnl_vlan_filter_list *)msg;
2114 struct i40e_pf *pf = vf->pf;
2115 struct i40e_vsi *vsi = NULL;
2116 u16 vsi_id = vfl->vsi_id;
2117 i40e_status aq_ret = 0;
2118 int i;
2119
2120 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
5c3c48ac
JB		 2121 !i40e_vc_isvalid_vsi_id(vf, vsi_id)) {
2122 aq_ret = I40E_ERR_PARAM;
2123 goto error_param;
2124 }
2125
2126 for (i = 0; i < vfl->num_elements; i++) {
2127 if (vfl->vlan_id[i] > I40E_MAX_VLANID) {
2128 aq_ret = I40E_ERR_PARAM;
2129 goto error_param;
2130 }
2131 }
2132
fdf0e0bf 2133 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac
JB		 2134 if (vsi->info.pvid) {
2135 aq_ret = I40E_ERR_PARAM;
2136 goto error_param;
2137 }
2138
2139 for (i = 0; i < vfl->num_elements; i++) {
3aa7b74d
FS		 2140 i40e_vsi_kill_vlan(vsi, vfl->vlan_id[i]);
2141 vf->num_vlan--;
6995b36c 2142
5676a8b9
ASJ		 2143 if (test_bit(I40E_VF_STAT_UC_PROMISC, &vf->vf_states))
2144 i40e_aq_set_vsi_uc_promisc_on_vlan(&pf->hw, vsi->seid,
2145 false,
2146 vfl->vlan_id[i],
2147 NULL);
2148 if (test_bit(I40E_VF_STAT_MC_PROMISC, &vf->vf_states))
2149 i40e_aq_set_vsi_mc_promisc_on_vlan(&pf->hw, vsi->seid,
2150 false,
2151 vfl->vlan_id[i],
2152 NULL);
5c3c48ac
JB		 2153 }
2154
2155error_param:
b40c82e6 2156 /* send the response to the VF */
5c3c48ac
JB		 2157 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_DEL_VLAN, aq_ret);
2158}
2159
e3219ce6
ASJ		 2160/**
2161 * i40e_vc_iwarp_msg
2162 * @vf: pointer to the VF info
2163 * @msg: pointer to the msg buffer
2164 * @msglen: msg length
2165 *
2166 * called from the VF for the iwarp msgs
2167 **/
2168static int i40e_vc_iwarp_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
2169{
2170 struct i40e_pf *pf = vf->pf;
2171 int abs_vf_id = vf->vf_id + pf->hw.func_caps.vf_base_id;
2172 i40e_status aq_ret = 0;
2173
2174 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
2175 !test_bit(I40E_VF_STAT_IWARPENA, &vf->vf_states)) {
2176 aq_ret = I40E_ERR_PARAM;
2177 goto error_param;
2178 }
2179
2180 i40e_notify_client_of_vf_msg(pf->vsi[pf->lan_vsi], abs_vf_id,
2181 msg, msglen);
2182
2183error_param:
2184 /* send the response to the VF */
2185 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_IWARP,
2186 aq_ret);
2187}
2188
2189/**
2190 * i40e_vc_iwarp_qvmap_msg
2191 * @vf: pointer to the VF info
2192 * @msg: pointer to the msg buffer
2193 * @msglen: msg length
2194 * @config: config qvmap or release it
2195 *
2196 * called from the VF for the iwarp msgs
2197 **/
2198static int i40e_vc_iwarp_qvmap_msg(struct i40e_vf *vf, u8 *msg, u16 msglen,
2199 bool config)
2200{
2201 struct i40e_virtchnl_iwarp_qvlist_info *qvlist_info =
2202 (struct i40e_virtchnl_iwarp_qvlist_info *)msg;
2203 i40e_status aq_ret = 0;
2204
2205 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
2206 !test_bit(I40E_VF_STAT_IWARPENA, &vf->vf_states)) {
2207 aq_ret = I40E_ERR_PARAM;
2208 goto error_param;
2209 }
2210
2211 if (config) {
2212 if (i40e_config_iwarp_qvlist(vf, qvlist_info))
2213 aq_ret = I40E_ERR_PARAM;
2214 } else {
2215 i40e_release_iwarp_qvlist(vf);
2216 }
2217
2218error_param:
2219 /* send the response to the VF */
2220 return i40e_vc_send_resp_to_vf(vf,
8d9d927f
MW		 2221 config ? I40E_VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP :
2222 I40E_VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP,
e3219ce6
ASJ		 2223 aq_ret);
2224}
2225
c4e1868c
MW		 2226/**
2227 * i40e_vc_config_rss_key
2228 * @vf: pointer to the VF info
2229 * @msg: pointer to the msg buffer
2230 * @msglen: msg length
2231 *
2232 * Configure the VF's RSS key
2233 **/
2234static int i40e_vc_config_rss_key(struct i40e_vf *vf, u8 *msg, u16 msglen)
2235{
2236 struct i40e_virtchnl_rss_key *vrk =
2237 (struct i40e_virtchnl_rss_key *)msg;
2238 struct i40e_pf *pf = vf->pf;
2239 struct i40e_vsi *vsi = NULL;
2240 u16 vsi_id = vrk->vsi_id;
2241 i40e_status aq_ret = 0;
2242
2243 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
c4e1868c
MW		 2244 !i40e_vc_isvalid_vsi_id(vf, vsi_id) ||
2245 (vrk->key_len != I40E_HKEY_ARRAY_SIZE)) {
2246 aq_ret = I40E_ERR_PARAM;
2247 goto err;
2248 }
2249
2250 vsi = pf->vsi[vf->lan_vsi_idx];
2251 aq_ret = i40e_config_rss(vsi, vrk->key, NULL, 0);
2252err:
2253 /* send the response to the VF */
2254 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_RSS_KEY,
2255 aq_ret);
2256}
2257
2258/**
2259 * i40e_vc_config_rss_lut
2260 * @vf: pointer to the VF info
2261 * @msg: pointer to the msg buffer
2262 * @msglen: msg length
2263 *
2264 * Configure the VF's RSS LUT
2265 **/
2266static int i40e_vc_config_rss_lut(struct i40e_vf *vf, u8 *msg, u16 msglen)
2267{
2268 struct i40e_virtchnl_rss_lut *vrl =
2269 (struct i40e_virtchnl_rss_lut *)msg;
2270 struct i40e_pf *pf = vf->pf;
2271 struct i40e_vsi *vsi = NULL;
2272 u16 vsi_id = vrl->vsi_id;
2273 i40e_status aq_ret = 0;
2274
2275 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||
c4e1868c
MW		 2276 !i40e_vc_isvalid_vsi_id(vf, vsi_id) ||
2277 (vrl->lut_entries != I40E_VF_HLUT_ARRAY_SIZE)) {
2278 aq_ret = I40E_ERR_PARAM;
2279 goto err;
2280 }
2281
2282 vsi = pf->vsi[vf->lan_vsi_idx];
2283 aq_ret = i40e_config_rss(vsi, NULL, vrl->lut, I40E_VF_HLUT_ARRAY_SIZE);
2284 /* send the response to the VF */
2285err:
2286 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_RSS_LUT,
2287 aq_ret);
2288}
2289
2290/**
2291 * i40e_vc_get_rss_hena
2292 * @vf: pointer to the VF info
2293 * @msg: pointer to the msg buffer
2294 * @msglen: msg length
2295 *
2296 * Return the RSS HENA bits allowed by the hardware
2297 **/
2298static int i40e_vc_get_rss_hena(struct i40e_vf *vf, u8 *msg, u16 msglen)
2299{
2300 struct i40e_virtchnl_rss_hena *vrh = NULL;
2301 struct i40e_pf *pf = vf->pf;
2302 i40e_status aq_ret = 0;
2303 int len = 0;
2304
692fb0a7 2305 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states)) {
c4e1868c
MW		 2306 aq_ret = I40E_ERR_PARAM;
2307 goto err;
2308 }
2309 len = sizeof(struct i40e_virtchnl_rss_hena);
2310
2311 vrh = kzalloc(len, GFP_KERNEL);
2312 if (!vrh) {
2313 aq_ret = I40E_ERR_NO_MEMORY;
2314 len = 0;
2315 goto err;
2316 }
2317 vrh->hena = i40e_pf_get_default_rss_hena(pf);
2318err:
2319 /* send the response back to the VF */
2320 aq_ret = i40e_vc_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_RSS_HENA_CAPS,
2321 aq_ret, (u8 *)vrh, len);
b7d2cd95 2322 kfree(vrh);
c4e1868c
MW		 2323 return aq_ret;
2324}
2325
2326/**
2327 * i40e_vc_set_rss_hena
2328 * @vf: pointer to the VF info
2329 * @msg: pointer to the msg buffer
2330 * @msglen: msg length
2331 *
2332 * Set the RSS HENA bits for the VF
2333 **/
2334static int i40e_vc_set_rss_hena(struct i40e_vf *vf, u8 *msg, u16 msglen)
2335{
2336 struct i40e_virtchnl_rss_hena *vrh =
2337 (struct i40e_virtchnl_rss_hena *)msg;
2338 struct i40e_pf *pf = vf->pf;
2339 struct i40e_hw *hw = &pf->hw;
2340 i40e_status aq_ret = 0;
2341
692fb0a7 2342 if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states)) {
c4e1868c
MW		 2343 aq_ret = I40E_ERR_PARAM;
2344 goto err;
2345 }
2346 i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(0, vf->vf_id), (u32)vrh->hena);
2347 i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(1, vf->vf_id),
2348 (u32)(vrh->hena >> 32));
2349
2350 /* send the response to the VF */
2351err:
2352 return i40e_vc_send_resp_to_vf(vf, I40E_VIRTCHNL_OP_SET_RSS_HENA,
2353 aq_ret);
2354}
2355
5c3c48ac
JB		 2356/**
2357 * i40e_vc_validate_vf_msg
b40c82e6 2358 * @vf: pointer to the VF info
5c3c48ac
JB		 2359 * @msg: pointer to the msg buffer
2360 * @msglen: msg length
2361 * @msghndl: msg handle
2362 *
2363 * validate msg
2364 **/
2365static int i40e_vc_validate_vf_msg(struct i40e_vf *vf, u32 v_opcode,
2366 u32 v_retval, u8 *msg, u16 msglen)
2367{
2368 bool err_msg_format = false;
3ed439c5 2369 int valid_len = 0;
5c3c48ac
JB		 2370
2371 /* Check if VF is disabled. */
2372 if (test_bit(I40E_VF_STAT_DISABLED, &vf->vf_states))
2373 return I40E_ERR_PARAM;
2374
2375 /* Validate message length. */
2376 switch (v_opcode) {
2377 case I40E_VIRTCHNL_OP_VERSION:
2378 valid_len = sizeof(struct i40e_virtchnl_version_info);
2379 break;
2380 case I40E_VIRTCHNL_OP_RESET_VF:
5c3c48ac 2381 break;
f4ca1a22
MW		 2382 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
2383 if (VF_IS_V11(vf))
2384 valid_len = sizeof(u32);
f4ca1a22 2385 break;
5c3c48ac
JB		 2386 case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE:
2387 valid_len = sizeof(struct i40e_virtchnl_txq_info);
2388 break;
2389 case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE:
2390 valid_len = sizeof(struct i40e_virtchnl_rxq_info);
2391 break;
2392 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES:
2393 valid_len = sizeof(struct i40e_virtchnl_vsi_queue_config_info);
2394 if (msglen >= valid_len) {
2395 struct i40e_virtchnl_vsi_queue_config_info *vqc =
2396 (struct i40e_virtchnl_vsi_queue_config_info *)msg;
2397 valid_len += (vqc->num_queue_pairs *
2398 sizeof(struct
2399 i40e_virtchnl_queue_pair_info));
2400 if (vqc->num_queue_pairs == 0)
2401 err_msg_format = true;
2402 }
2403 break;
2404 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP:
2405 valid_len = sizeof(struct i40e_virtchnl_irq_map_info);
2406 if (msglen >= valid_len) {
2407 struct i40e_virtchnl_irq_map_info *vimi =
2408 (struct i40e_virtchnl_irq_map_info *)msg;
2409 valid_len += (vimi->num_vectors *
2410 sizeof(struct i40e_virtchnl_vector_map));
2411 if (vimi->num_vectors == 0)
2412 err_msg_format = true;
2413 }
2414 break;
2415 case I40E_VIRTCHNL_OP_ENABLE_QUEUES:
2416 case I40E_VIRTCHNL_OP_DISABLE_QUEUES:
2417 valid_len = sizeof(struct i40e_virtchnl_queue_select);
2418 break;
2419 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS:
2420 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS:
2421 valid_len = sizeof(struct i40e_virtchnl_ether_addr_list);
2422 if (msglen >= valid_len) {
2423 struct i40e_virtchnl_ether_addr_list *veal =
2424 (struct i40e_virtchnl_ether_addr_list *)msg;
2425 valid_len += veal->num_elements *
2426 sizeof(struct i40e_virtchnl_ether_addr);
2427 if (veal->num_elements == 0)
2428 err_msg_format = true;
2429 }
2430 break;
2431 case I40E_VIRTCHNL_OP_ADD_VLAN:
2432 case I40E_VIRTCHNL_OP_DEL_VLAN:
2433 valid_len = sizeof(struct i40e_virtchnl_vlan_filter_list);
2434 if (msglen >= valid_len) {
2435 struct i40e_virtchnl_vlan_filter_list *vfl =
2436 (struct i40e_virtchnl_vlan_filter_list *)msg;
2437 valid_len += vfl->num_elements * sizeof(u16);
2438 if (vfl->num_elements == 0)
2439 err_msg_format = true;
2440 }
2441 break;
2442 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
2443 valid_len = sizeof(struct i40e_virtchnl_promisc_info);
2444 break;
2445 case I40E_VIRTCHNL_OP_GET_STATS:
2446 valid_len = sizeof(struct i40e_virtchnl_queue_select);
2447 break;
e3219ce6
ASJ		 2448 case I40E_VIRTCHNL_OP_IWARP:
2449 /* These messages are opaque to us and will be validated in
2450 * the RDMA client code. We just need to check for nonzero
2451 * length. The firmware will enforce max length restrictions.
2452 */
2453 if (msglen)
2454 valid_len = msglen;
2455 else
2456 err_msg_format = true;
2457 break;
2458 case I40E_VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP:
2459 valid_len = 0;
2460 break;
2461 case I40E_VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP:
2462 valid_len = sizeof(struct i40e_virtchnl_iwarp_qvlist_info);
2463 if (msglen >= valid_len) {
2464 struct i40e_virtchnl_iwarp_qvlist_info *qv =
2465 (struct i40e_virtchnl_iwarp_qvlist_info *)msg;
2466 if (qv->num_vectors == 0) {
2467 err_msg_format = true;
2468 break;
2469 }
2470 valid_len += ((qv->num_vectors - 1) *
2471 sizeof(struct i40e_virtchnl_iwarp_qv_info));
2472 }
2473 break;
c4e1868c
MW		 2474 case I40E_VIRTCHNL_OP_CONFIG_RSS_KEY:
2475 valid_len = sizeof(struct i40e_virtchnl_rss_key);
2476 if (msglen >= valid_len) {
2477 struct i40e_virtchnl_rss_key *vrk =
2478 (struct i40e_virtchnl_rss_key *)msg;
2479 if (vrk->key_len != I40E_HKEY_ARRAY_SIZE) {
2480 err_msg_format = true;
2481 break;
2482 }
2483 valid_len += vrk->key_len - 1;
2484 }
2485 break;
2486 case I40E_VIRTCHNL_OP_CONFIG_RSS_LUT:
2487 valid_len = sizeof(struct i40e_virtchnl_rss_lut);
2488 if (msglen >= valid_len) {
2489 struct i40e_virtchnl_rss_lut *vrl =
2490 (struct i40e_virtchnl_rss_lut *)msg;
2491 if (vrl->lut_entries != I40E_VF_HLUT_ARRAY_SIZE) {
2492 err_msg_format = true;
2493 break;
2494 }
2495 valid_len += vrl->lut_entries - 1;
2496 }
2497 break;
2498 case I40E_VIRTCHNL_OP_GET_RSS_HENA_CAPS:
c4e1868c
MW		 2499 break;
2500 case I40E_VIRTCHNL_OP_SET_RSS_HENA:
2501 valid_len = sizeof(struct i40e_virtchnl_rss_hena);
2502 break;
5c3c48ac
JB		 2503 /* These are always errors coming from the VF. */
2504 case I40E_VIRTCHNL_OP_EVENT:
2505 case I40E_VIRTCHNL_OP_UNKNOWN:
2506 default:
2507 return -EPERM;
5c3c48ac
JB		 2508 }
2509 /* few more checks */
2510 if ((valid_len != msglen) || (err_msg_format)) {
2511 i40e_vc_send_resp_to_vf(vf, v_opcode, I40E_ERR_PARAM);
2512 return -EINVAL;
2513 } else {
2514 return 0;
2515 }
2516}
2517
2518/**
2519 * i40e_vc_process_vf_msg
b40c82e6
JK		 2520 * @pf: pointer to the PF structure
2521 * @vf_id: source VF id
5c3c48ac
JB		 2522 * @msg: pointer to the msg buffer
2523 * @msglen: msg length
2524 * @msghndl: msg handle
2525 *
2526 * called from the common aeq/arq handler to
b40c82e6 2527 * process request from VF
5c3c48ac 2528 **/
a1b5a24f 2529int i40e_vc_process_vf_msg(struct i40e_pf *pf, s16 vf_id, u32 v_opcode,
5c3c48ac
JB		 2530 u32 v_retval, u8 *msg, u16 msglen)
2531{
5c3c48ac 2532 struct i40e_hw *hw = &pf->hw;
a1b5a24f 2533 int local_vf_id = vf_id - (s16)hw->func_caps.vf_base_id;
6c1b5bff 2534 struct i40e_vf *vf;
5c3c48ac
JB		 2535 int ret;
2536
2537 pf->vf_aq_requests++;
7efa84b7 2538 if (local_vf_id >= pf->num_alloc_vfs)
6c1b5bff 2539 return -EINVAL;
7efa84b7 2540 vf = &(pf->vf[local_vf_id]);
5c3c48ac
JB		 2541 /* perform basic checks on the msg */
2542 ret = i40e_vc_validate_vf_msg(vf, v_opcode, v_retval, msg, msglen);
2543
2544 if (ret) {
b40c82e6 2545 dev_err(&pf->pdev->dev, "Invalid message from VF %d, opcode %d, len %d\n",
7efa84b7 2546 local_vf_id, v_opcode, msglen);
5c3c48ac
JB		 2547 return ret;
2548 }
bae3cae4 2549
5c3c48ac
JB		 2550 switch (v_opcode) {
2551 case I40E_VIRTCHNL_OP_VERSION:
f4ca1a22 2552 ret = i40e_vc_get_version_msg(vf, msg);
5c3c48ac
JB		 2553 break;
2554 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
f4ca1a22 2555 ret = i40e_vc_get_vf_resources_msg(vf, msg);
5c3c48ac
JB		 2556 break;
2557 case I40E_VIRTCHNL_OP_RESET_VF:
fc18eaa0
MW		 2558 i40e_vc_reset_vf_msg(vf);
2559 ret = 0;
5c3c48ac
JB		 2560 break;
2561 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
2562 ret = i40e_vc_config_promiscuous_mode_msg(vf, msg, msglen);
2563 break;
2564 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES:
2565 ret = i40e_vc_config_queues_msg(vf, msg, msglen);
2566 break;
2567 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP:
2568 ret = i40e_vc_config_irq_map_msg(vf, msg, msglen);
2569 break;
2570 case I40E_VIRTCHNL_OP_ENABLE_QUEUES:
2571 ret = i40e_vc_enable_queues_msg(vf, msg, msglen);
055b295d 2572 i40e_vc_notify_vf_link_state(vf);
5c3c48ac
JB		 2573 break;
2574 case I40E_VIRTCHNL_OP_DISABLE_QUEUES:
2575 ret = i40e_vc_disable_queues_msg(vf, msg, msglen);
2576 break;
2577 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS:
2578 ret = i40e_vc_add_mac_addr_msg(vf, msg, msglen);
2579 break;
2580 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS:
2581 ret = i40e_vc_del_mac_addr_msg(vf, msg, msglen);
2582 break;
2583 case I40E_VIRTCHNL_OP_ADD_VLAN:
2584 ret = i40e_vc_add_vlan_msg(vf, msg, msglen);
2585 break;
2586 case I40E_VIRTCHNL_OP_DEL_VLAN:
2587 ret = i40e_vc_remove_vlan_msg(vf, msg, msglen);
2588 break;
2589 case I40E_VIRTCHNL_OP_GET_STATS:
2590 ret = i40e_vc_get_stats_msg(vf, msg, msglen);
2591 break;
e3219ce6
ASJ		 2592 case I40E_VIRTCHNL_OP_IWARP:
2593 ret = i40e_vc_iwarp_msg(vf, msg, msglen);
2594 break;
2595 case I40E_VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP:
2596 ret = i40e_vc_iwarp_qvmap_msg(vf, msg, msglen, true);
2597 break;
2598 case I40E_VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP:
2599 ret = i40e_vc_iwarp_qvmap_msg(vf, msg, msglen, false);
2600 break;
c4e1868c
MW		 2601 case I40E_VIRTCHNL_OP_CONFIG_RSS_KEY:
2602 ret = i40e_vc_config_rss_key(vf, msg, msglen);
2603 break;
2604 case I40E_VIRTCHNL_OP_CONFIG_RSS_LUT:
2605 ret = i40e_vc_config_rss_lut(vf, msg, msglen);
2606 break;
2607 case I40E_VIRTCHNL_OP_GET_RSS_HENA_CAPS:
2608 ret = i40e_vc_get_rss_hena(vf, msg, msglen);
2609 break;
2610 case I40E_VIRTCHNL_OP_SET_RSS_HENA:
2611 ret = i40e_vc_set_rss_hena(vf, msg, msglen);
2612 break;
2613
5c3c48ac
JB		 2614 case I40E_VIRTCHNL_OP_UNKNOWN:
2615 default:
b40c82e6 2616 dev_err(&pf->pdev->dev, "Unsupported opcode %d from VF %d\n",
7efa84b7 2617 v_opcode, local_vf_id);
5c3c48ac
JB		 2618 ret = i40e_vc_send_resp_to_vf(vf, v_opcode,
2619 I40E_ERR_NOT_IMPLEMENTED);
2620 break;
2621 }
2622
2623 return ret;
2624}
2625
2626/**
2627 * i40e_vc_process_vflr_event
b40c82e6 2628 * @pf: pointer to the PF structure
5c3c48ac
JB		 2629 *
2630 * called from the vlfr irq handler to
b40c82e6 2631 * free up VF resources and state variables
5c3c48ac
JB		 2632 **/
2633int i40e_vc_process_vflr_event(struct i40e_pf *pf)
2634{
5c3c48ac 2635 struct i40e_hw *hw = &pf->hw;
a1b5a24f 2636 u32 reg, reg_idx, bit_idx;
5c3c48ac 2637 struct i40e_vf *vf;
a1b5a24f 2638 int vf_id;
5c3c48ac
JB		 2639
2640 if (!test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
2641 return 0;
2642
0d790327
MW		 2643 /* Re-enable the VFLR interrupt cause here, before looking for which
2644 * VF got reset. Otherwise, if another VF gets a reset while the
2645 * first one is being processed, that interrupt will be lost, and
2646 * that VF will be stuck in reset forever.
2647 */
c5c2f7c3
MW		 2648 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
2649 reg |= I40E_PFINT_ICR0_ENA_VFLR_MASK;
2650 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
2651 i40e_flush(hw);
2652
5c3c48ac
JB		 2653 clear_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2654 for (vf_id = 0; vf_id < pf->num_alloc_vfs; vf_id++) {
2655 reg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;
2656 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
b40c82e6 2657 /* read GLGEN_VFLRSTAT register to find out the flr VFs */
5c3c48ac
JB		 2658 vf = &pf->vf[vf_id];
2659 reg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx));
7369ca87 2660 if (reg & BIT(bit_idx))
7e5a313e 2661 /* i40e_reset_vf will clear the bit in GLGEN_VFLRSTAT */
7369ca87 2662 i40e_reset_vf(vf, true);
5c3c48ac
JB		 2663 }
2664
5c3c48ac
JB		 2665 return 0;
2666}
2667
5c3c48ac
JB		 2668/**
2669 * i40e_ndo_set_vf_mac
2670 * @netdev: network interface device structure
b40c82e6 2671 * @vf_id: VF identifier
5c3c48ac
JB		 2672 * @mac: mac address
2673 *
b40c82e6 2674 * program VF mac address
5c3c48ac
JB		 2675 **/
2676int i40e_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2677{
2678 struct i40e_netdev_priv *np = netdev_priv(netdev);
2679 struct i40e_vsi *vsi = np->vsi;
2680 struct i40e_pf *pf = vsi->back;
2681 struct i40e_mac_filter *f;
2682 struct i40e_vf *vf;
2683 int ret = 0;
278e7d0b 2684 int bkt;
5c3c48ac
JB		 2685
2686 /* validate the request */
2687 if (vf_id >= pf->num_alloc_vfs) {
2688 dev_err(&pf->pdev->dev,
2689 "Invalid VF Identifier %d\n", vf_id);
2690 ret = -EINVAL;
2691 goto error_param;
2692 }
2693
2694 vf = &(pf->vf[vf_id]);
fdf0e0bf 2695 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac 2696 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
2d166c30
MW		 2697 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
2698 vf_id);
2699 ret = -EAGAIN;
5c3c48ac
JB		 2700 goto error_param;
2701 }
2702
efd8e39a 2703 if (is_multicast_ether_addr(mac)) {
5c3c48ac 2704 dev_err(&pf->pdev->dev,
efd8e39a 2705 "Invalid Ethernet address %pM for VF %d\n", mac, vf_id);
5c3c48ac
JB		 2706 ret = -EINVAL;
2707 goto error_param;
2708 }
2709
21659035 2710 /* Lock once because below invoked function add/del_filter requires
278e7d0b 2711 * mac_filter_hash_lock to be held
21659035 2712 */
278e7d0b 2713 spin_lock_bh(&vsi->mac_filter_hash_lock);
21659035 2714
5c3c48ac 2715 /* delete the temporary mac address */
efd8e39a 2716 if (!is_zero_ether_addr(vf->default_lan_addr.addr))
9569a9a4 2717 i40e_del_mac_filter(vsi, vf->default_lan_addr.addr);
5c3c48ac 2718
29f71bb0
GR		 2719 /* Delete all the filters for this VSI - we're going to kill it
2720 * anyway.
2721 */
278e7d0b 2722 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist)
148141bb 2723 __i40e_del_filter(vsi, f);
5c3c48ac 2724
278e7d0b 2725 spin_unlock_bh(&vsi->mac_filter_hash_lock);
21659035 2726
5c3c48ac
JB		 2727 dev_info(&pf->pdev->dev, "Setting MAC %pM on VF %d\n", mac, vf_id);
2728 /* program mac filter */
17652c63 2729 if (i40e_sync_vsi_filters(vsi)) {
5c3c48ac
JB		 2730 dev_err(&pf->pdev->dev, "Unable to program ucast filters\n");
2731 ret = -EIO;
2732 goto error_param;
2733 }
9a173901 2734 ether_addr_copy(vf->default_lan_addr.addr, mac);
f657a6e1 2735 vf->pf_set_mac = true;
17413a80
GR		 2736 /* Force the VF driver stop so it has to reload with new MAC address */
2737 i40e_vc_disable_vf(pf, vf);
5c3c48ac 2738 dev_info(&pf->pdev->dev, "Reload the VF driver to make this change effective.\n");
5c3c48ac
JB		 2739
2740error_param:
2741 return ret;
2742}
2743
2744/**
2745 * i40e_ndo_set_vf_port_vlan
2746 * @netdev: network interface device structure
b40c82e6 2747 * @vf_id: VF identifier
5c3c48ac
JB		 2748 * @vlan_id: mac address
2749 * @qos: priority setting
79aab093 2750 * @vlan_proto: vlan protocol
5c3c48ac 2751 *
b40c82e6 2752 * program VF vlan id and/or qos
5c3c48ac 2753 **/
79aab093
MS		 2754int i40e_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,
2755 u16 vlan_id, u8 qos, __be16 vlan_proto)
5c3c48ac 2756{
f7fc2f2e 2757 u16 vlanprio = vlan_id | (qos << I40E_VLAN_PRIORITY_SHIFT);
5c3c48ac
JB		 2758 struct i40e_netdev_priv *np = netdev_priv(netdev);
2759 struct i40e_pf *pf = np->vsi->back;
2760 struct i40e_vsi *vsi;
2761 struct i40e_vf *vf;
2762 int ret = 0;
2763
2764 /* validate the request */
2765 if (vf_id >= pf->num_alloc_vfs) {
2766 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
2767 ret = -EINVAL;
2768 goto error_pvid;
2769 }
2770
2771 if ((vlan_id > I40E_MAX_VLANID) || (qos > 7)) {
2772 dev_err(&pf->pdev->dev, "Invalid VF Parameters\n");
2773 ret = -EINVAL;
2774 goto error_pvid;
2775 }
2776
79aab093
MS		 2777 if (vlan_proto != htons(ETH_P_8021Q)) {
2778 dev_err(&pf->pdev->dev, "VF VLAN protocol is not supported\n");
2779 ret = -EPROTONOSUPPORT;
2780 goto error_pvid;
2781 }
2782
5c3c48ac 2783 vf = &(pf->vf[vf_id]);
fdf0e0bf 2784 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac 2785 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
2d166c30
MW		 2786 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
2787 vf_id);
2788 ret = -EAGAIN;
5c3c48ac
JB		 2789 goto error_pvid;
2790 }
2791
f7fc2f2e 2792 if (le16_to_cpu(vsi->info.pvid) == vlanprio)
85927ec1
MW		 2793 /* duplicate request, so just return success */
2794 goto error_pvid;
2795
9af52f60 2796 /* Locked once because multiple functions below iterate list */
278e7d0b 2797 spin_lock_bh(&vsi->mac_filter_hash_lock);
21659035 2798
9af52f60 2799 if (le16_to_cpu(vsi->info.pvid) == 0 && i40e_is_vsi_in_vlan(vsi)) {
99a4973c
GR		 2800 dev_err(&pf->pdev->dev,
2801 "VF %d has already configured VLAN filters and the administrator is requesting a port VLAN override.\nPlease unload and reload the VF driver for this change to take effect.\n",
2802 vf_id);
f9b4b627
GR		 2803 /* Administrator Error - knock the VF offline until he does
2804 * the right thing by reconfiguring his network correctly
2805 * and then reloading the VF driver.
2806 */
2807 i40e_vc_disable_vf(pf, vf);
35f3472a
MW		 2808 /* During reset the VF got a new VSI, so refresh the pointer. */
2809 vsi = pf->vsi[vf->lan_vsi_idx];
f9b4b627 2810 }
99a4973c 2811
8d82a7c5
GR		 2812 /* Check for condition where there was already a port VLAN ID
2813 * filter set and now it is being deleted by setting it to zero.
1315f7c3
GR		 2814 * Additionally check for the condition where there was a port
2815 * VLAN but now there is a new and different port VLAN being set.
8d82a7c5
GR		 2816 * Before deleting all the old VLAN filters we must add new ones
2817 * with -1 (I40E_VLAN_ANY) or otherwise we're left with all our
2818 * MAC addresses deleted.
2819 */
1315f7c3 2820 if ((!(vlan_id || qos) ||
f7fc2f2e 2821 vlanprio != le16_to_cpu(vsi->info.pvid)) &&
9af52f60
JK		 2822 vsi->info.pvid) {
2823 ret = i40e_add_vlan_all_mac(vsi, I40E_VLAN_ANY);
2824 if (ret) {
2825 dev_info(&vsi->back->pdev->dev,
2826 "add VF VLAN failed, ret=%d aq_err=%d\n", ret,
2827 vsi->back->hw.aq.asq_last_status);
2828 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2829 goto error_pvid;
2830 }
2831 }
8d82a7c5 2832
5c3c48ac 2833 if (vsi->info.pvid) {
9af52f60
JK		 2834 /* remove all filters on the old VLAN */
2835 i40e_rm_vlan_all_mac(vsi, (le16_to_cpu(vsi->info.pvid) &
2836 VLAN_VID_MASK));
5c3c48ac 2837 }
9af52f60 2838
5c3c48ac 2839 if (vlan_id || qos)
f7fc2f2e 2840 ret = i40e_vsi_add_pvid(vsi, vlanprio);
5c3c48ac 2841 else
6c12fcbf 2842 i40e_vsi_remove_pvid(vsi);
5c3c48ac
JB		 2843
2844 if (vlan_id) {
2845 dev_info(&pf->pdev->dev, "Setting VLAN %d, QOS 0x%x on VF %d\n",
2846 vlan_id, qos, vf_id);
2847
9af52f60
JK		 2848 /* add new VLAN filter for each MAC */
2849 ret = i40e_add_vlan_all_mac(vsi, vlan_id);
5c3c48ac
JB		 2850 if (ret) {
2851 dev_info(&vsi->back->pdev->dev,
2852 "add VF VLAN failed, ret=%d aq_err=%d\n", ret,
2853 vsi->back->hw.aq.asq_last_status);
9af52f60 2854 spin_unlock_bh(&vsi->mac_filter_hash_lock);
5c3c48ac
JB		 2855 goto error_pvid;
2856 }
9af52f60
JK		 2857
2858 /* remove the previously added non-VLAN MAC filters */
2859 i40e_rm_vlan_all_mac(vsi, I40E_VLAN_ANY);
5c3c48ac
JB		 2860 }
2861
9af52f60
JK		 2862 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2863
2864 /* Schedule the worker thread to take care of applying changes */
2865 i40e_service_event_schedule(vsi->back);
2866
5c3c48ac
JB		 2867 if (ret) {
2868 dev_err(&pf->pdev->dev, "Unable to update VF vsi context\n");
2869 goto error_pvid;
2870 }
9af52f60 2871
6c12fcbf
GR		 2872 /* The Port VLAN needs to be saved across resets the same as the
2873 * default LAN MAC address.
2874 */
2875 vf->port_vlan_id = le16_to_cpu(vsi->info.pvid);
5c3c48ac
JB		 2876 ret = 0;
2877
2878error_pvid:
2879 return ret;
2880}
2881
84590fd9
MW		 2882#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
2883#define I40E_MAX_BW_INACTIVE_ACCUM 4 /* device can accumulate 4 credits max */
5c3c48ac
JB		 2884/**
2885 * i40e_ndo_set_vf_bw
2886 * @netdev: network interface device structure
b40c82e6
JK		 2887 * @vf_id: VF identifier
2888 * @tx_rate: Tx rate
5c3c48ac 2889 *
b40c82e6 2890 * configure VF Tx rate
5c3c48ac 2891 **/
ed616689
SC		 2892int i40e_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate,
2893 int max_tx_rate)
5c3c48ac 2894{
6b192891
MW		 2895 struct i40e_netdev_priv *np = netdev_priv(netdev);
2896 struct i40e_pf *pf = np->vsi->back;
2897 struct i40e_vsi *vsi;
2898 struct i40e_vf *vf;
2899 int speed = 0;
2900 int ret = 0;
2901
2902 /* validate the request */
2903 if (vf_id >= pf->num_alloc_vfs) {
2904 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d.\n", vf_id);
2905 ret = -EINVAL;
2906 goto error;
2907 }
2908
ed616689 2909 if (min_tx_rate) {
b40c82e6 2910 dev_err(&pf->pdev->dev, "Invalid min tx rate (%d) (greater than 0) specified for VF %d.\n",
ed616689
SC		 2911 min_tx_rate, vf_id);
2912 return -EINVAL;
2913 }
2914
6b192891 2915 vf = &(pf->vf[vf_id]);
fdf0e0bf 2916 vsi = pf->vsi[vf->lan_vsi_idx];
6b192891 2917 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
2d166c30
MW		 2918 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
2919 vf_id);
2920 ret = -EAGAIN;
6b192891
MW		 2921 goto error;
2922 }
2923
2924 switch (pf->hw.phy.link_info.link_speed) {
2925 case I40E_LINK_SPEED_40GB:
2926 speed = 40000;
2927 break;
3123237a
CW		 2928 case I40E_LINK_SPEED_25GB:
2929 speed = 25000;
2930 break;
07f169c3
MW		 2931 case I40E_LINK_SPEED_20GB:
2932 speed = 20000;
2933 break;
6b192891
MW		 2934 case I40E_LINK_SPEED_10GB:
2935 speed = 10000;
2936 break;
2937 case I40E_LINK_SPEED_1GB:
2938 speed = 1000;
2939 break;
2940 default:
2941 break;
2942 }
2943
ed616689 2944 if (max_tx_rate > speed) {
ff00f3a9 2945 dev_err(&pf->pdev->dev, "Invalid max tx rate %d specified for VF %d.\n",
ed616689 2946 max_tx_rate, vf->vf_id);
6b192891
MW		 2947 ret = -EINVAL;
2948 goto error;
2949 }
2950
dac9b31a
MW		 2951 if ((max_tx_rate < 50) && (max_tx_rate > 0)) {
2952 dev_warn(&pf->pdev->dev, "Setting max Tx rate to minimum usable value of 50Mbps.\n");
2953 max_tx_rate = 50;
2954 }
2955
6b192891 2956 /* Tx rate credits are in values of 50Mbps, 0 is disabled*/
84590fd9
MW		 2957 ret = i40e_aq_config_vsi_bw_limit(&pf->hw, vsi->seid,
2958 max_tx_rate / I40E_BW_CREDIT_DIVISOR,
2959 I40E_MAX_BW_INACTIVE_ACCUM, NULL);
6b192891 2960 if (ret) {
ed616689 2961 dev_err(&pf->pdev->dev, "Unable to set max tx rate, error code %d.\n",
6b192891
MW		 2962 ret);
2963 ret = -EIO;
2964 goto error;
2965 }
ed616689 2966 vf->tx_rate = max_tx_rate;
6b192891
MW		 2967error:
2968 return ret;
5c3c48ac
JB		 2969}
2970
2971/**
2972 * i40e_ndo_get_vf_config
2973 * @netdev: network interface device structure
b40c82e6
JK		 2974 * @vf_id: VF identifier
2975 * @ivi: VF configuration structure
5c3c48ac 2976 *
b40c82e6 2977 * return VF configuration
5c3c48ac
JB		 2978 **/
2979int i40e_ndo_get_vf_config(struct net_device *netdev,
2980 int vf_id, struct ifla_vf_info *ivi)
2981{
2982 struct i40e_netdev_priv *np = netdev_priv(netdev);
5c3c48ac
JB		 2983 struct i40e_vsi *vsi = np->vsi;
2984 struct i40e_pf *pf = vsi->back;
2985 struct i40e_vf *vf;
2986 int ret = 0;
2987
2988 /* validate the request */
2989 if (vf_id >= pf->num_alloc_vfs) {
2990 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
2991 ret = -EINVAL;
2992 goto error_param;
2993 }
2994
2995 vf = &(pf->vf[vf_id]);
2996 /* first vsi is always the LAN vsi */
fdf0e0bf 2997 vsi = pf->vsi[vf->lan_vsi_idx];
5c3c48ac 2998 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
2d166c30
MW		 2999 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
3000 vf_id);
3001 ret = -EAGAIN;
5c3c48ac
JB		 3002 goto error_param;
3003 }
3004
3005 ivi->vf = vf_id;
3006
6995b36c 3007 ether_addr_copy(ivi->mac, vf->default_lan_addr.addr);
5c3c48ac 3008
ed616689
SC		 3009 ivi->max_tx_rate = vf->tx_rate;
3010 ivi->min_tx_rate = 0;
5c3c48ac
JB		 3011 ivi->vlan = le16_to_cpu(vsi->info.pvid) & I40E_VLAN_MASK;
3012 ivi->qos = (le16_to_cpu(vsi->info.pvid) & I40E_PRIORITY_MASK) >>
3013 I40E_VLAN_PRIORITY_SHIFT;
84ca55a0
MW		 3014 if (vf->link_forced == false)
3015 ivi->linkstate = IFLA_VF_LINK_STATE_AUTO;
3016 else if (vf->link_up == true)
3017 ivi->linkstate = IFLA_VF_LINK_STATE_ENABLE;
3018 else
3019 ivi->linkstate = IFLA_VF_LINK_STATE_DISABLE;
c674d125 3020 ivi->spoofchk = vf->spoofchk;
d40062f3 3021 ivi->trusted = vf->trusted;
5c3c48ac
JB		 3022 ret = 0;
3023
3024error_param:
3025 return ret;
3026}
588aefa0
MW		 3027
3028/**
3029 * i40e_ndo_set_vf_link_state
3030 * @netdev: network interface device structure
b40c82e6 3031 * @vf_id: VF identifier
588aefa0
MW		 3032 * @link: required link state
3033 *
3034 * Set the link state of a specified VF, regardless of physical link state
3035 **/
3036int i40e_ndo_set_vf_link_state(struct net_device *netdev, int vf_id, int link)
3037{
3038 struct i40e_netdev_priv *np = netdev_priv(netdev);
3039 struct i40e_pf *pf = np->vsi->back;
3040 struct i40e_virtchnl_pf_event pfe;
3041 struct i40e_hw *hw = &pf->hw;
3042 struct i40e_vf *vf;
f19efbb5 3043 int abs_vf_id;
588aefa0
MW		 3044 int ret = 0;
3045
3046 /* validate the request */
3047 if (vf_id >= pf->num_alloc_vfs) {
3048 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
3049 ret = -EINVAL;
3050 goto error_out;
3051 }
3052
3053 vf = &pf->vf[vf_id];
f19efbb5 3054 abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
588aefa0
MW		 3055
3056 pfe.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
3057 pfe.severity = I40E_PF_EVENT_SEVERITY_INFO;
3058
3059 switch (link) {
3060 case IFLA_VF_LINK_STATE_AUTO:
3061 vf->link_forced = false;
3062 pfe.event_data.link_event.link_status =
3063 pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP;
3064 pfe.event_data.link_event.link_speed =
3065 pf->hw.phy.link_info.link_speed;
3066 break;
3067 case IFLA_VF_LINK_STATE_ENABLE:
3068 vf->link_forced = true;
3069 vf->link_up = true;
3070 pfe.event_data.link_event.link_status = true;
3071 pfe.event_data.link_event.link_speed = I40E_LINK_SPEED_40GB;
3072 break;
3073 case IFLA_VF_LINK_STATE_DISABLE:
3074 vf->link_forced = true;
3075 vf->link_up = false;
3076 pfe.event_data.link_event.link_status = false;
3077 pfe.event_data.link_event.link_speed = 0;
3078 break;
3079 default:
3080 ret = -EINVAL;
3081 goto error_out;
3082 }
3083 /* Notify the VF of its new link state */
f19efbb5 3084 i40e_aq_send_msg_to_vf(hw, abs_vf_id, I40E_VIRTCHNL_OP_EVENT,
588aefa0
MW		 3085 0, (u8 *)&pfe, sizeof(pfe), NULL);
3086
3087error_out:
3088 return ret;
3089}
c674d125
MW		 3090
3091/**
3092 * i40e_ndo_set_vf_spoofchk
3093 * @netdev: network interface device structure
b40c82e6 3094 * @vf_id: VF identifier
c674d125
MW		 3095 * @enable: flag to enable or disable feature
3096 *
3097 * Enable or disable VF spoof checking
3098 **/
e6d9004d 3099int i40e_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_id, bool enable)
c674d125
MW		 3100{
3101 struct i40e_netdev_priv *np = netdev_priv(netdev);
3102 struct i40e_vsi *vsi = np->vsi;
3103 struct i40e_pf *pf = vsi->back;
3104 struct i40e_vsi_context ctxt;
3105 struct i40e_hw *hw = &pf->hw;
3106 struct i40e_vf *vf;
3107 int ret = 0;
3108
3109 /* validate the request */
3110 if (vf_id >= pf->num_alloc_vfs) {
3111 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
3112 ret = -EINVAL;
3113 goto out;
3114 }
3115
3116 vf = &(pf->vf[vf_id]);
2d166c30
MW		 3117 if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
3118 dev_err(&pf->pdev->dev, "VF %d still in reset. Try again.\n",
3119 vf_id);
3120 ret = -EAGAIN;
3121 goto out;
3122 }
c674d125
MW		 3123
3124 if (enable == vf->spoofchk)
3125 goto out;
3126
3127 vf->spoofchk = enable;
3128 memset(&ctxt, 0, sizeof(ctxt));
fdf0e0bf 3129 ctxt.seid = pf->vsi[vf->lan_vsi_idx]->seid;
c674d125
MW		 3130 ctxt.pf_num = pf->hw.pf_id;
3131 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
3132 if (enable)
30d71af5
GR		 3133 ctxt.info.sec_flags |= (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
3134 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
c674d125
MW		 3135 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3136 if (ret) {
3137 dev_err(&pf->pdev->dev, "Error %d updating VSI parameters\n",
3138 ret);
3139 ret = -EIO;
3140 }
3141out:
3142 return ret;
3143}
c3bbbd20
ASJ		 3144
3145/**
3146 * i40e_ndo_set_vf_trust
3147 * @netdev: network interface device structure of the pf
3148 * @vf_id: VF identifier
3149 * @setting: trust setting
3150 *
3151 * Enable or disable VF trust setting
3152 **/
3153int i40e_ndo_set_vf_trust(struct net_device *netdev, int vf_id, bool setting)
3154{
3155 struct i40e_netdev_priv *np = netdev_priv(netdev);
3156 struct i40e_pf *pf = np->vsi->back;
3157 struct i40e_vf *vf;
3158 int ret = 0;
3159
3160 /* validate the request */
3161 if (vf_id >= pf->num_alloc_vfs) {
3162 dev_err(&pf->pdev->dev, "Invalid VF Identifier %d\n", vf_id);
3163 return -EINVAL;
3164 }
3165
3166 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3167 dev_err(&pf->pdev->dev, "Trusted VF not supported in MFP mode.\n");
3168 return -EINVAL;
3169 }
3170
3171 vf = &pf->vf[vf_id];
3172
3173 if (!vf)
3174 return -EINVAL;
3175 if (setting == vf->trusted)
3176 goto out;
3177
3178 vf->trusted = setting;
3179 i40e_vc_notify_vf_reset(vf);
3180 i40e_reset_vf(vf, false);
3181 dev_info(&pf->pdev->dev, "VF %u is now %strusted\n",
3182 vf_id, setting ? "" : "un");
3183out:
3184 return ret;
3185}
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