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7f12ad74 GR |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
7f12ad74 GR |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
b831607d JB |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
7f12ad74 GR |
18 | * The full GNU General Public License is included in this distribution in |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
7ed3f5f0 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
7ed3f5f0 | 29 | |
7f12ad74 | 30 | #include "i40evf.h" |
ed0980c4 | 31 | #include "i40e_trace.h" |
206812b5 | 32 | #include "i40e_prototype.h" |
7f12ad74 GR |
33 | |
34 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
35 | u32 td_tag) | |
36 | { | |
37 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
38 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
39 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
40 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
41 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
42 | } | |
43 | ||
44 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) | |
45 | ||
46 | /** | |
47 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer | |
48 | * @ring: the ring that owns the buffer | |
49 | * @tx_buffer: the buffer to free | |
50 | **/ | |
51 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, | |
52 | struct i40e_tx_buffer *tx_buffer) | |
53 | { | |
54 | if (tx_buffer->skb) { | |
64bfd68e AD |
55 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
56 | kfree(tx_buffer->raw_buf); | |
57 | else | |
58 | dev_kfree_skb_any(tx_buffer->skb); | |
7f12ad74 GR |
59 | if (dma_unmap_len(tx_buffer, len)) |
60 | dma_unmap_single(ring->dev, | |
61 | dma_unmap_addr(tx_buffer, dma), | |
62 | dma_unmap_len(tx_buffer, len), | |
63 | DMA_TO_DEVICE); | |
64 | } else if (dma_unmap_len(tx_buffer, len)) { | |
65 | dma_unmap_page(ring->dev, | |
66 | dma_unmap_addr(tx_buffer, dma), | |
67 | dma_unmap_len(tx_buffer, len), | |
68 | DMA_TO_DEVICE); | |
69 | } | |
a42e7a36 | 70 | |
7f12ad74 GR |
71 | tx_buffer->next_to_watch = NULL; |
72 | tx_buffer->skb = NULL; | |
73 | dma_unmap_len_set(tx_buffer, len, 0); | |
74 | /* tx_buffer must be completely set up in the transmit path */ | |
75 | } | |
76 | ||
77 | /** | |
78 | * i40evf_clean_tx_ring - Free any empty Tx buffers | |
79 | * @tx_ring: ring to be cleaned | |
80 | **/ | |
81 | void i40evf_clean_tx_ring(struct i40e_ring *tx_ring) | |
82 | { | |
83 | unsigned long bi_size; | |
84 | u16 i; | |
85 | ||
86 | /* ring already cleared, nothing to do */ | |
87 | if (!tx_ring->tx_bi) | |
88 | return; | |
89 | ||
90 | /* Free all the Tx ring sk_buffs */ | |
91 | for (i = 0; i < tx_ring->count; i++) | |
92 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
93 | ||
94 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
95 | memset(tx_ring->tx_bi, 0, bi_size); | |
96 | ||
97 | /* Zero out the descriptor ring */ | |
98 | memset(tx_ring->desc, 0, tx_ring->size); | |
99 | ||
100 | tx_ring->next_to_use = 0; | |
101 | tx_ring->next_to_clean = 0; | |
102 | ||
103 | if (!tx_ring->netdev) | |
104 | return; | |
105 | ||
106 | /* cleanup Tx queue statistics */ | |
e486bdfd | 107 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
7f12ad74 GR |
108 | } |
109 | ||
110 | /** | |
111 | * i40evf_free_tx_resources - Free Tx resources per queue | |
112 | * @tx_ring: Tx descriptor ring for a specific queue | |
113 | * | |
114 | * Free all transmit software resources | |
115 | **/ | |
116 | void i40evf_free_tx_resources(struct i40e_ring *tx_ring) | |
117 | { | |
118 | i40evf_clean_tx_ring(tx_ring); | |
119 | kfree(tx_ring->tx_bi); | |
120 | tx_ring->tx_bi = NULL; | |
121 | ||
122 | if (tx_ring->desc) { | |
123 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
124 | tx_ring->desc, tx_ring->dma); | |
125 | tx_ring->desc = NULL; | |
126 | } | |
127 | } | |
128 | ||
a68de58d | 129 | /** |
9c6c1259 KP |
130 | * i40evf_get_tx_pending - how many Tx descriptors not processed |
131 | * @tx_ring: the ring of descriptors | |
dd353109 | 132 | * @in_sw: is tx_pending being checked in SW or HW |
a68de58d | 133 | * |
9c6c1259 KP |
134 | * Since there is no access to the ring head register |
135 | * in XL710, we need to use our local copies | |
a68de58d | 136 | **/ |
dd353109 | 137 | u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
a68de58d | 138 | { |
9c6c1259 | 139 | u32 head, tail; |
a68de58d | 140 | |
b1cb07db | 141 | head = ring->next_to_clean; |
9c6c1259 KP |
142 | tail = readl(ring->tail); |
143 | ||
144 | if (head != tail) | |
145 | return (head < tail) ? | |
146 | tail - head : (tail + ring->count - head); | |
147 | ||
148 | return 0; | |
a68de58d JB |
149 | } |
150 | ||
1dc8b538 | 151 | #define WB_STRIDE 4 |
c29af37f | 152 | |
7f12ad74 GR |
153 | /** |
154 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
155 | * @vsi: the VSI we care about |
156 | * @tx_ring: Tx ring to clean | |
157 | * @napi_budget: Used to determine if we are in netpoll | |
7f12ad74 GR |
158 | * |
159 | * Returns true if there's any budget left (e.g. the clean is finished) | |
160 | **/ | |
a619afe8 AD |
161 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
162 | struct i40e_ring *tx_ring, int napi_budget) | |
7f12ad74 GR |
163 | { |
164 | u16 i = tx_ring->next_to_clean; | |
165 | struct i40e_tx_buffer *tx_buf; | |
166 | struct i40e_tx_desc *tx_desc; | |
a619afe8 AD |
167 | unsigned int total_bytes = 0, total_packets = 0; |
168 | unsigned int budget = vsi->work_limit; | |
7f12ad74 GR |
169 | |
170 | tx_buf = &tx_ring->tx_bi[i]; | |
171 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
172 | i -= tx_ring->count; | |
173 | ||
174 | do { | |
175 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
176 | ||
177 | /* if next_to_watch is not set then there is no work pending */ | |
178 | if (!eop_desc) | |
179 | break; | |
180 | ||
181 | /* prevent any other reads prior to eop_desc */ | |
f72271e2 | 182 | smp_rmb(); |
7f12ad74 | 183 | |
ed0980c4 | 184 | i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); |
b1cb07db PB |
185 | /* if the descriptor isn't done, no work yet to do */ |
186 | if (!(eop_desc->cmd_type_offset_bsz & | |
187 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
7f12ad74 GR |
188 | break; |
189 | ||
190 | /* clear next_to_watch to prevent false hangs */ | |
191 | tx_buf->next_to_watch = NULL; | |
192 | ||
193 | /* update the statistics for this packet */ | |
194 | total_bytes += tx_buf->bytecount; | |
195 | total_packets += tx_buf->gso_segs; | |
196 | ||
197 | /* free the skb */ | |
a619afe8 | 198 | napi_consume_skb(tx_buf->skb, napi_budget); |
7f12ad74 GR |
199 | |
200 | /* unmap skb header data */ | |
201 | dma_unmap_single(tx_ring->dev, | |
202 | dma_unmap_addr(tx_buf, dma), | |
203 | dma_unmap_len(tx_buf, len), | |
204 | DMA_TO_DEVICE); | |
205 | ||
206 | /* clear tx_buffer data */ | |
207 | tx_buf->skb = NULL; | |
208 | dma_unmap_len_set(tx_buf, len, 0); | |
209 | ||
210 | /* unmap remaining buffers */ | |
211 | while (tx_desc != eop_desc) { | |
ed0980c4 SP |
212 | i40e_trace(clean_tx_irq_unmap, |
213 | tx_ring, tx_desc, tx_buf); | |
7f12ad74 GR |
214 | |
215 | tx_buf++; | |
216 | tx_desc++; | |
217 | i++; | |
218 | if (unlikely(!i)) { | |
219 | i -= tx_ring->count; | |
220 | tx_buf = tx_ring->tx_bi; | |
221 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
222 | } | |
223 | ||
224 | /* unmap any remaining paged data */ | |
225 | if (dma_unmap_len(tx_buf, len)) { | |
226 | dma_unmap_page(tx_ring->dev, | |
227 | dma_unmap_addr(tx_buf, dma), | |
228 | dma_unmap_len(tx_buf, len), | |
229 | DMA_TO_DEVICE); | |
230 | dma_unmap_len_set(tx_buf, len, 0); | |
231 | } | |
232 | } | |
233 | ||
234 | /* move us one more past the eop_desc for start of next pkt */ | |
235 | tx_buf++; | |
236 | tx_desc++; | |
237 | i++; | |
238 | if (unlikely(!i)) { | |
239 | i -= tx_ring->count; | |
240 | tx_buf = tx_ring->tx_bi; | |
241 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
242 | } | |
243 | ||
016890b9 JB |
244 | prefetch(tx_desc); |
245 | ||
7f12ad74 GR |
246 | /* update budget accounting */ |
247 | budget--; | |
248 | } while (likely(budget)); | |
249 | ||
250 | i += tx_ring->count; | |
251 | tx_ring->next_to_clean = i; | |
252 | u64_stats_update_begin(&tx_ring->syncp); | |
253 | tx_ring->stats.bytes += total_bytes; | |
254 | tx_ring->stats.packets += total_packets; | |
255 | u64_stats_update_end(&tx_ring->syncp); | |
256 | tx_ring->q_vector->tx.total_bytes += total_bytes; | |
257 | tx_ring->q_vector->tx.total_packets += total_packets; | |
258 | ||
f6d83d13 | 259 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
f6d83d13 ASJ |
260 | /* check to see if there are < 4 descriptors |
261 | * waiting to be written back, then kick the hardware to force | |
262 | * them to be written back in case we stay in NAPI. | |
263 | * In this mode on X722 we do not enable Interrupt. | |
264 | */ | |
88dc9e6f | 265 | unsigned int j = i40evf_get_tx_pending(tx_ring, false); |
f6d83d13 ASJ |
266 | |
267 | if (budget && | |
1dc8b538 | 268 | ((j / WB_STRIDE) == 0) && (j > 0) && |
0da36b97 | 269 | !test_bit(__I40E_VSI_DOWN, vsi->state) && |
f6d83d13 ASJ |
270 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) |
271 | tx_ring->arm_wb = true; | |
272 | } | |
273 | ||
e486bdfd AD |
274 | /* notify netdev of completed buffers */ |
275 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
7f12ad74 GR |
276 | total_packets, total_bytes); |
277 | ||
b85c94b6 | 278 | #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) |
7f12ad74 GR |
279 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
280 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
281 | /* Make sure that anybody stopping the queue after this | |
282 | * sees the new next_to_clean. | |
283 | */ | |
284 | smp_mb(); | |
285 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
286 | tx_ring->queue_index) && | |
0da36b97 | 287 | !test_bit(__I40E_VSI_DOWN, vsi->state)) { |
7f12ad74 GR |
288 | netif_wake_subqueue(tx_ring->netdev, |
289 | tx_ring->queue_index); | |
290 | ++tx_ring->tx_stats.restart_queue; | |
291 | } | |
292 | } | |
293 | ||
b03a8c1f | 294 | return !!budget; |
7f12ad74 GR |
295 | } |
296 | ||
c29af37f | 297 | /** |
ecc6a239 | 298 | * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
c29af37f | 299 | * @vsi: the VSI we care about |
ecc6a239 | 300 | * @q_vector: the vector on which to enable writeback |
c29af37f ASJ |
301 | * |
302 | **/ | |
ecc6a239 ASJ |
303 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
304 | struct i40e_q_vector *q_vector) | |
c29af37f | 305 | { |
8e0764b4 | 306 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 307 | u32 val; |
8e0764b4 | 308 | |
ecc6a239 ASJ |
309 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
310 | return; | |
311 | ||
312 | if (q_vector->arm_wb_state) | |
313 | return; | |
314 | ||
315 | val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | | |
316 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */ | |
317 | ||
318 | wr32(&vsi->back->hw, | |
319 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + | |
320 | vsi->base_vector - 1), val); | |
321 | q_vector->arm_wb_state = true; | |
322 | } | |
323 | ||
324 | /** | |
325 | * i40evf_force_wb - Issue SW Interrupt so HW does a wb | |
326 | * @vsi: the VSI we care about | |
327 | * @q_vector: the vector on which to force writeback | |
328 | * | |
329 | **/ | |
330 | void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
331 | { | |
332 | u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
333 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */ | |
334 | I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK | | |
335 | I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK | |
336 | /* allow 00 to be written to the index */; | |
337 | ||
338 | wr32(&vsi->back->hw, | |
339 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1), | |
340 | val); | |
c29af37f ASJ |
341 | } |
342 | ||
7f12ad74 GR |
343 | /** |
344 | * i40e_set_new_dynamic_itr - Find new ITR level | |
345 | * @rc: structure containing ring performance data | |
346 | * | |
8f5e39ce JB |
347 | * Returns true if ITR changed, false if not |
348 | * | |
7f12ad74 GR |
349 | * Stores a new ITR value based on packets and byte counts during |
350 | * the last interrupt. The advantage of per interrupt computation | |
351 | * is faster updates and more accurate ITR for the current traffic | |
352 | * pattern. Constants in this function were computed based on | |
353 | * theoretical maximum wire speed and thresholds were set based on | |
354 | * testing data as well as attempting to minimize response time | |
355 | * while increasing bulk throughput. | |
356 | **/ | |
8f5e39ce | 357 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
7f12ad74 GR |
358 | { |
359 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
360 | u32 new_itr = rc->itr; | |
2b634bb0 | 361 | int bytes_per_usec; |
742c9875 | 362 | unsigned int usecs, estimated_usecs; |
7f12ad74 GR |
363 | |
364 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 365 | return false; |
7f12ad74 | 366 | |
742c9875 | 367 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
2b634bb0 | 368 | bytes_per_usec = rc->total_bytes / usecs; |
742c9875 JK |
369 | |
370 | /* The calculations in this algorithm depend on interrupts actually | |
371 | * firing at the ITR rate. This may not happen if the packet rate is | |
372 | * really low, or if we've been napi polling. Check to make sure | |
373 | * that's not the case before we continue. | |
374 | */ | |
375 | estimated_usecs = jiffies_to_usecs(jiffies - rc->last_itr_update); | |
376 | if (estimated_usecs > usecs) { | |
377 | new_latency_range = I40E_LOW_LATENCY; | |
378 | goto reset_latency; | |
379 | } | |
380 | ||
7f12ad74 | 381 | /* simple throttlerate management |
c56625d5 | 382 | * 0-10MB/s lowest (50000 ints/s) |
7f12ad74 | 383 | * 10-20MB/s low (20000 ints/s) |
c56625d5 | 384 | * 20-1249MB/s bulk (18000 ints/s) |
51cc6d9f JB |
385 | * |
386 | * The math works out because the divisor is in 10^(-6) which | |
387 | * turns the bytes/us input value into MB/s values, but | |
388 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
389 | * are in 2 usec increments in the ITR registers, and make sure |
390 | * to use the smoothed values that the countdown timer gives us. | |
7f12ad74 | 391 | */ |
de32e3ef | 392 | switch (new_latency_range) { |
7f12ad74 | 393 | case I40E_LOWEST_LATENCY: |
2b634bb0 | 394 | if (bytes_per_usec > 10) |
7f12ad74 GR |
395 | new_latency_range = I40E_LOW_LATENCY; |
396 | break; | |
397 | case I40E_LOW_LATENCY: | |
2b634bb0 | 398 | if (bytes_per_usec > 20) |
7f12ad74 | 399 | new_latency_range = I40E_BULK_LATENCY; |
2b634bb0 | 400 | else if (bytes_per_usec <= 10) |
7f12ad74 GR |
401 | new_latency_range = I40E_LOWEST_LATENCY; |
402 | break; | |
403 | case I40E_BULK_LATENCY: | |
de32e3ef | 404 | default: |
2b634bb0 | 405 | if (bytes_per_usec <= 20) |
de32e3ef | 406 | new_latency_range = I40E_LOW_LATENCY; |
7f12ad74 GR |
407 | break; |
408 | } | |
c56625d5 | 409 | |
742c9875 | 410 | reset_latency: |
de32e3ef | 411 | rc->latency_range = new_latency_range; |
7f12ad74 GR |
412 | |
413 | switch (new_latency_range) { | |
414 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 415 | new_itr = I40E_ITR_50K; |
7f12ad74 GR |
416 | break; |
417 | case I40E_LOW_LATENCY: | |
418 | new_itr = I40E_ITR_20K; | |
419 | break; | |
420 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
421 | new_itr = I40E_ITR_18K; |
422 | break; | |
7f12ad74 GR |
423 | default: |
424 | break; | |
425 | } | |
426 | ||
7f12ad74 GR |
427 | rc->total_bytes = 0; |
428 | rc->total_packets = 0; | |
742c9875 | 429 | rc->last_itr_update = jiffies; |
8f5e39ce JB |
430 | |
431 | if (new_itr != rc->itr) { | |
432 | rc->itr = new_itr; | |
433 | return true; | |
434 | } | |
8f5e39ce | 435 | return false; |
7f12ad74 GR |
436 | } |
437 | ||
4eeb1fff | 438 | /** |
7f12ad74 GR |
439 | * i40evf_setup_tx_descriptors - Allocate the Tx descriptors |
440 | * @tx_ring: the tx ring to set up | |
441 | * | |
442 | * Return 0 on success, negative on error | |
443 | **/ | |
444 | int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
445 | { | |
446 | struct device *dev = tx_ring->dev; | |
447 | int bi_size; | |
448 | ||
449 | if (!dev) | |
450 | return -ENOMEM; | |
451 | ||
67c818a1 MW |
452 | /* warn if we are about to overwrite the pointer */ |
453 | WARN_ON(tx_ring->tx_bi); | |
7f12ad74 GR |
454 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
455 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
456 | if (!tx_ring->tx_bi) | |
457 | goto err; | |
458 | ||
459 | /* round up to nearest 4K */ | |
460 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
461 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
462 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
463 | &tx_ring->dma, GFP_KERNEL); | |
464 | if (!tx_ring->desc) { | |
465 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
466 | tx_ring->size); | |
467 | goto err; | |
468 | } | |
469 | ||
470 | tx_ring->next_to_use = 0; | |
471 | tx_ring->next_to_clean = 0; | |
472 | return 0; | |
473 | ||
474 | err: | |
475 | kfree(tx_ring->tx_bi); | |
476 | tx_ring->tx_bi = NULL; | |
477 | return -ENOMEM; | |
478 | } | |
479 | ||
480 | /** | |
481 | * i40evf_clean_rx_ring - Free Rx buffers | |
482 | * @rx_ring: ring to be cleaned | |
483 | **/ | |
484 | void i40evf_clean_rx_ring(struct i40e_ring *rx_ring) | |
485 | { | |
7f12ad74 GR |
486 | unsigned long bi_size; |
487 | u16 i; | |
488 | ||
489 | /* ring already cleared, nothing to do */ | |
490 | if (!rx_ring->rx_bi) | |
491 | return; | |
492 | ||
e72e5659 SP |
493 | if (rx_ring->skb) { |
494 | dev_kfree_skb(rx_ring->skb); | |
495 | rx_ring->skb = NULL; | |
496 | } | |
497 | ||
7f12ad74 GR |
498 | /* Free all the Rx ring sk_buffs */ |
499 | for (i = 0; i < rx_ring->count; i++) { | |
ab9ad98e JB |
500 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
501 | ||
ab9ad98e JB |
502 | if (!rx_bi->page) |
503 | continue; | |
504 | ||
59605bc0 AD |
505 | /* Invalidate cache lines that may have been written to by |
506 | * device so that we avoid corrupting memory. | |
507 | */ | |
508 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
509 | rx_bi->dma, | |
510 | rx_bi->page_offset, | |
98efd694 | 511 | rx_ring->rx_buf_len, |
59605bc0 AD |
512 | DMA_FROM_DEVICE); |
513 | ||
514 | /* free resources associated with mapping */ | |
515 | dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, | |
98efd694 | 516 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
517 | DMA_FROM_DEVICE, |
518 | I40E_RX_DMA_ATTR); | |
98efd694 | 519 | |
1793668c | 520 | __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); |
ab9ad98e JB |
521 | |
522 | rx_bi->page = NULL; | |
523 | rx_bi->page_offset = 0; | |
7f12ad74 GR |
524 | } |
525 | ||
526 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
527 | memset(rx_ring->rx_bi, 0, bi_size); | |
528 | ||
529 | /* Zero out the descriptor ring */ | |
530 | memset(rx_ring->desc, 0, rx_ring->size); | |
531 | ||
ab9ad98e | 532 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
533 | rx_ring->next_to_clean = 0; |
534 | rx_ring->next_to_use = 0; | |
535 | } | |
536 | ||
537 | /** | |
538 | * i40evf_free_rx_resources - Free Rx resources | |
539 | * @rx_ring: ring to clean the resources from | |
540 | * | |
541 | * Free all receive software resources | |
542 | **/ | |
543 | void i40evf_free_rx_resources(struct i40e_ring *rx_ring) | |
544 | { | |
545 | i40evf_clean_rx_ring(rx_ring); | |
546 | kfree(rx_ring->rx_bi); | |
547 | rx_ring->rx_bi = NULL; | |
548 | ||
549 | if (rx_ring->desc) { | |
550 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
551 | rx_ring->desc, rx_ring->dma); | |
552 | rx_ring->desc = NULL; | |
553 | } | |
554 | } | |
555 | ||
556 | /** | |
557 | * i40evf_setup_rx_descriptors - Allocate Rx descriptors | |
558 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
559 | * | |
560 | * Returns 0 on success, negative on failure | |
561 | **/ | |
562 | int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
563 | { | |
564 | struct device *dev = rx_ring->dev; | |
565 | int bi_size; | |
566 | ||
67c818a1 MW |
567 | /* warn if we are about to overwrite the pointer */ |
568 | WARN_ON(rx_ring->rx_bi); | |
7f12ad74 GR |
569 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
570 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
571 | if (!rx_ring->rx_bi) | |
572 | goto err; | |
573 | ||
f217d6ca | 574 | u64_stats_init(&rx_ring->syncp); |
638702bd | 575 | |
7f12ad74 | 576 | /* Round up to nearest 4K */ |
ab9ad98e | 577 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
7f12ad74 GR |
578 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
579 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
580 | &rx_ring->dma, GFP_KERNEL); | |
581 | ||
582 | if (!rx_ring->desc) { | |
583 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
584 | rx_ring->size); | |
585 | goto err; | |
586 | } | |
587 | ||
ab9ad98e | 588 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
589 | rx_ring->next_to_clean = 0; |
590 | rx_ring->next_to_use = 0; | |
591 | ||
592 | return 0; | |
593 | err: | |
594 | kfree(rx_ring->rx_bi); | |
595 | rx_ring->rx_bi = NULL; | |
596 | return -ENOMEM; | |
597 | } | |
598 | ||
599 | /** | |
600 | * i40e_release_rx_desc - Store the new tail and head values | |
601 | * @rx_ring: ring to bump | |
602 | * @val: new head index | |
603 | **/ | |
604 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
605 | { | |
606 | rx_ring->next_to_use = val; | |
ab9ad98e JB |
607 | |
608 | /* update next to alloc since we have filled the ring */ | |
609 | rx_ring->next_to_alloc = val; | |
610 | ||
7f12ad74 GR |
611 | /* Force memory writes to complete before letting h/w |
612 | * know there are new descriptors to fetch. (Only | |
613 | * applicable for weak-ordered memory model archs, | |
614 | * such as IA-64). | |
615 | */ | |
616 | wmb(); | |
617 | writel(val, rx_ring->tail); | |
618 | } | |
619 | ||
ca9ec088 AD |
620 | /** |
621 | * i40e_rx_offset - Return expected offset into page to access data | |
622 | * @rx_ring: Ring we are requesting offset of | |
623 | * | |
624 | * Returns the offset value for ring into the data buffer. | |
625 | */ | |
626 | static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring) | |
627 | { | |
628 | return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0; | |
629 | } | |
630 | ||
7f12ad74 | 631 | /** |
ab9ad98e JB |
632 | * i40e_alloc_mapped_page - recycle or make a new page |
633 | * @rx_ring: ring to use | |
634 | * @bi: rx_buffer struct to modify | |
c2e245ab | 635 | * |
ab9ad98e JB |
636 | * Returns true if the page was successfully allocated or |
637 | * reused. | |
a132af24 | 638 | **/ |
ab9ad98e JB |
639 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
640 | struct i40e_rx_buffer *bi) | |
a132af24 | 641 | { |
ab9ad98e JB |
642 | struct page *page = bi->page; |
643 | dma_addr_t dma; | |
a132af24 | 644 | |
ab9ad98e JB |
645 | /* since we are recycling buffers we should seldom need to alloc */ |
646 | if (likely(page)) { | |
647 | rx_ring->rx_stats.page_reuse_count++; | |
648 | return true; | |
649 | } | |
a132af24 | 650 | |
ab9ad98e | 651 | /* alloc new page for storage */ |
98efd694 | 652 | page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); |
ab9ad98e JB |
653 | if (unlikely(!page)) { |
654 | rx_ring->rx_stats.alloc_page_failed++; | |
655 | return false; | |
656 | } | |
a132af24 | 657 | |
ab9ad98e | 658 | /* map page for use */ |
59605bc0 | 659 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
98efd694 | 660 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
661 | DMA_FROM_DEVICE, |
662 | I40E_RX_DMA_ATTR); | |
f16704e5 | 663 | |
ab9ad98e JB |
664 | /* if mapping failed free memory back to system since |
665 | * there isn't much point in holding memory we can't use | |
f16704e5 | 666 | */ |
ab9ad98e | 667 | if (dma_mapping_error(rx_ring->dev, dma)) { |
98efd694 | 668 | __free_pages(page, i40e_rx_pg_order(rx_ring)); |
ab9ad98e JB |
669 | rx_ring->rx_stats.alloc_page_failed++; |
670 | return false; | |
a132af24 MW |
671 | } |
672 | ||
ab9ad98e JB |
673 | bi->dma = dma; |
674 | bi->page = page; | |
ca9ec088 | 675 | bi->page_offset = i40e_rx_offset(rx_ring); |
a0cfc313 AD |
676 | |
677 | /* initialize pagecnt_bias to 1 representing we fully own page */ | |
1793668c | 678 | bi->pagecnt_bias = 1; |
c2e245ab | 679 | |
ab9ad98e JB |
680 | return true; |
681 | } | |
c2e245ab | 682 | |
ab9ad98e JB |
683 | /** |
684 | * i40e_receive_skb - Send a completed packet up the stack | |
685 | * @rx_ring: rx ring in play | |
686 | * @skb: packet to send up | |
687 | * @vlan_tag: vlan tag for packet | |
688 | **/ | |
689 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
690 | struct sk_buff *skb, u16 vlan_tag) | |
691 | { | |
692 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
c2e245ab | 693 | |
ab9ad98e JB |
694 | if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
695 | (vlan_tag & VLAN_VID_MASK)) | |
696 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
697 | ||
698 | napi_gro_receive(&q_vector->napi, skb); | |
a132af24 MW |
699 | } |
700 | ||
701 | /** | |
ab9ad98e | 702 | * i40evf_alloc_rx_buffers - Replace used receive buffers |
7f12ad74 GR |
703 | * @rx_ring: ring to place buffers on |
704 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 705 | * |
ab9ad98e | 706 | * Returns false if all allocations were successful, true if any fail |
7f12ad74 | 707 | **/ |
ab9ad98e | 708 | bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
7f12ad74 | 709 | { |
ab9ad98e | 710 | u16 ntu = rx_ring->next_to_use; |
7f12ad74 GR |
711 | union i40e_rx_desc *rx_desc; |
712 | struct i40e_rx_buffer *bi; | |
7f12ad74 GR |
713 | |
714 | /* do nothing if no valid netdev defined */ | |
715 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 716 | return false; |
7f12ad74 | 717 | |
ab9ad98e JB |
718 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
719 | bi = &rx_ring->rx_bi[ntu]; | |
7f12ad74 | 720 | |
ab9ad98e JB |
721 | do { |
722 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
723 | goto no_buffers; | |
7f12ad74 | 724 | |
59605bc0 AD |
725 | /* sync the buffer for use by the device */ |
726 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
727 | bi->page_offset, | |
98efd694 | 728 | rx_ring->rx_buf_len, |
59605bc0 AD |
729 | DMA_FROM_DEVICE); |
730 | ||
ab9ad98e JB |
731 | /* Refresh the desc even if buffer_addrs didn't change |
732 | * because each write-back erases this info. | |
733 | */ | |
734 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
7f12ad74 | 735 | |
ab9ad98e JB |
736 | rx_desc++; |
737 | bi++; | |
738 | ntu++; | |
739 | if (unlikely(ntu == rx_ring->count)) { | |
740 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
741 | bi = rx_ring->rx_bi; | |
742 | ntu = 0; | |
743 | } | |
744 | ||
745 | /* clear the status bits for the next_to_use descriptor */ | |
746 | rx_desc->wb.qword1.status_error_len = 0; | |
747 | ||
748 | cleaned_count--; | |
749 | } while (cleaned_count); | |
750 | ||
751 | if (rx_ring->next_to_use != ntu) | |
752 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
753 | |
754 | return false; | |
755 | ||
7f12ad74 | 756 | no_buffers: |
ab9ad98e JB |
757 | if (rx_ring->next_to_use != ntu) |
758 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
759 | |
760 | /* make sure to come back via polling to try again after | |
761 | * allocation failure | |
762 | */ | |
763 | return true; | |
7f12ad74 GR |
764 | } |
765 | ||
7f12ad74 GR |
766 | /** |
767 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
768 | * @vsi: the VSI we care about | |
769 | * @skb: skb currently being received and modified | |
ab9ad98e | 770 | * @rx_desc: the receive descriptor |
7f12ad74 GR |
771 | **/ |
772 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
773 | struct sk_buff *skb, | |
ab9ad98e | 774 | union i40e_rx_desc *rx_desc) |
7f12ad74 | 775 | { |
ab9ad98e | 776 | struct i40e_rx_ptype_decoded decoded; |
ab9ad98e | 777 | u32 rx_error, rx_status; |
858296c8 | 778 | bool ipv4, ipv6; |
ab9ad98e JB |
779 | u8 ptype; |
780 | u64 qword; | |
781 | ||
782 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
783 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
784 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
785 | I40E_RXD_QW1_ERROR_SHIFT; | |
786 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
787 | I40E_RXD_QW1_STATUS_SHIFT; | |
788 | decoded = decode_rx_desc_ptype(ptype); | |
7f12ad74 | 789 | |
7f12ad74 GR |
790 | skb->ip_summed = CHECKSUM_NONE; |
791 | ||
ab9ad98e JB |
792 | skb_checksum_none_assert(skb); |
793 | ||
7f12ad74 | 794 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
795 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
796 | return; | |
797 | ||
798 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 799 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
800 | return; |
801 | ||
802 | /* both known and outer_ip must be set for the below code to work */ | |
803 | if (!(decoded.known && decoded.outer_ip)) | |
7f12ad74 GR |
804 | return; |
805 | ||
fad57330 AD |
806 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
807 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
808 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
809 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
810 | |
811 | if (ipv4 && | |
41a1d04b JB |
812 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
813 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
814 | goto checksum_fail; |
815 | ||
ddf1d0d7 | 816 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 817 | if (ipv6 && |
41a1d04b | 818 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 819 | /* don't increment checksum err here, non-fatal err */ |
7f12ad74 GR |
820 | return; |
821 | ||
8a3c91cc | 822 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 823 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
824 | goto checksum_fail; |
825 | ||
826 | /* handle packets that were not able to be checksummed due | |
827 | * to arrival speed, in this case the stack can compute | |
828 | * the csum. | |
829 | */ | |
41a1d04b | 830 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
7f12ad74 | 831 | return; |
7f12ad74 | 832 | |
858296c8 AD |
833 | /* Only report checksum unnecessary for TCP, UDP, or SCTP */ |
834 | switch (decoded.inner_prot) { | |
835 | case I40E_RX_PTYPE_INNER_PROT_TCP: | |
836 | case I40E_RX_PTYPE_INNER_PROT_UDP: | |
837 | case I40E_RX_PTYPE_INNER_PROT_SCTP: | |
838 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
839 | /* fall though */ | |
840 | default: | |
841 | break; | |
842 | } | |
8a3c91cc JB |
843 | |
844 | return; | |
845 | ||
846 | checksum_fail: | |
847 | vsi->back->hw_csum_rx_error++; | |
7f12ad74 GR |
848 | } |
849 | ||
850 | /** | |
857942fd | 851 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
852 | * @ptype: the ptype value from the descriptor |
853 | * | |
854 | * Returns a hash type to be used by skb_set_hash | |
855 | **/ | |
ab9ad98e | 856 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
857 | { |
858 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
859 | ||
860 | if (!decoded.known) | |
861 | return PKT_HASH_TYPE_NONE; | |
862 | ||
863 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
864 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
865 | return PKT_HASH_TYPE_L4; | |
866 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
867 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
868 | return PKT_HASH_TYPE_L3; | |
869 | else | |
870 | return PKT_HASH_TYPE_L2; | |
871 | } | |
872 | ||
857942fd ASJ |
873 | /** |
874 | * i40e_rx_hash - set the hash value in the skb | |
875 | * @ring: descriptor ring | |
876 | * @rx_desc: specific descriptor | |
877 | **/ | |
878 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
879 | union i40e_rx_desc *rx_desc, | |
880 | struct sk_buff *skb, | |
881 | u8 rx_ptype) | |
882 | { | |
883 | u32 hash; | |
ab9ad98e | 884 | const __le64 rss_mask = |
857942fd ASJ |
885 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
886 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
887 | ||
888 | if (ring->netdev->features & NETIF_F_RXHASH) | |
889 | return; | |
890 | ||
891 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
892 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
893 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
894 | } | |
895 | } | |
896 | ||
7f12ad74 | 897 | /** |
ab9ad98e JB |
898 | * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor |
899 | * @rx_ring: rx descriptor ring packet is being transacted on | |
900 | * @rx_desc: pointer to the EOP Rx descriptor | |
901 | * @skb: pointer to current skb being populated | |
902 | * @rx_ptype: the packet type decoded by hardware | |
7f12ad74 | 903 | * |
ab9ad98e JB |
904 | * This function checks the ring, descriptor, and packet information in |
905 | * order to populate the hash, checksum, VLAN, protocol, and | |
906 | * other fields within the skb. | |
7f12ad74 | 907 | **/ |
ab9ad98e JB |
908 | static inline |
909 | void i40evf_process_skb_fields(struct i40e_ring *rx_ring, | |
910 | union i40e_rx_desc *rx_desc, struct sk_buff *skb, | |
911 | u8 rx_ptype) | |
7f12ad74 | 912 | { |
ab9ad98e | 913 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); |
7f12ad74 | 914 | |
ab9ad98e | 915 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); |
a132af24 | 916 | |
ab9ad98e | 917 | skb_record_rx_queue(skb, rx_ring->queue_index); |
a5b268e4 AD |
918 | |
919 | /* modifies the skb - consumes the enet header */ | |
920 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
ab9ad98e | 921 | } |
a132af24 | 922 | |
ab9ad98e JB |
923 | /** |
924 | * i40e_cleanup_headers - Correct empty headers | |
925 | * @rx_ring: rx descriptor ring packet is being transacted on | |
926 | * @skb: pointer to current skb being fixed | |
927 | * | |
928 | * Also address the case where we are pulling data in on pages only | |
929 | * and as such no data is present in the skb header. | |
930 | * | |
931 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
932 | * it is large enough to qualify as a valid Ethernet frame. | |
933 | * | |
934 | * Returns true if an error was encountered and skb was freed. | |
935 | **/ | |
936 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
937 | { | |
ab9ad98e JB |
938 | /* if eth_skb_pad returns an error the skb was freed */ |
939 | if (eth_skb_pad(skb)) | |
940 | return true; | |
7f12ad74 | 941 | |
ab9ad98e JB |
942 | return false; |
943 | } | |
857942fd | 944 | |
ab9ad98e JB |
945 | /** |
946 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
947 | * @rx_ring: rx descriptor ring to store buffers on | |
948 | * @old_buff: donor buffer to have page reused | |
949 | * | |
950 | * Synchronizes page for reuse by the adapter | |
951 | **/ | |
952 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
953 | struct i40e_rx_buffer *old_buff) | |
954 | { | |
955 | struct i40e_rx_buffer *new_buff; | |
956 | u16 nta = rx_ring->next_to_alloc; | |
7f12ad74 | 957 | |
ab9ad98e | 958 | new_buff = &rx_ring->rx_bi[nta]; |
7f12ad74 | 959 | |
ab9ad98e JB |
960 | /* update, and store next to alloc */ |
961 | nta++; | |
962 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
7f12ad74 | 963 | |
ab9ad98e | 964 | /* transfer page from old buffer to new buffer */ |
1793668c AD |
965 | new_buff->dma = old_buff->dma; |
966 | new_buff->page = old_buff->page; | |
967 | new_buff->page_offset = old_buff->page_offset; | |
968 | new_buff->pagecnt_bias = old_buff->pagecnt_bias; | |
ab9ad98e JB |
969 | } |
970 | ||
971 | /** | |
9b37c937 | 972 | * i40e_page_is_reusable - check if any reuse is possible |
ab9ad98e | 973 | * @page: page struct to check |
9b37c937 SP |
974 | * |
975 | * A page is not reusable if it was allocated under low memory | |
976 | * conditions, or it's not in the same NUMA node as this CPU. | |
ab9ad98e | 977 | */ |
9b37c937 | 978 | static inline bool i40e_page_is_reusable(struct page *page) |
ab9ad98e | 979 | { |
9b37c937 SP |
980 | return (page_to_nid(page) == numa_mem_id()) && |
981 | !page_is_pfmemalloc(page); | |
982 | } | |
983 | ||
984 | /** | |
985 | * i40e_can_reuse_rx_page - Determine if this page can be reused by | |
986 | * the adapter for another receive | |
987 | * | |
988 | * @rx_buffer: buffer containing the page | |
9b37c937 SP |
989 | * |
990 | * If page is reusable, rx_buffer->page_offset is adjusted to point to | |
991 | * an unused region in the page. | |
992 | * | |
993 | * For small pages, @truesize will be a constant value, half the size | |
994 | * of the memory at page. We'll attempt to alternate between high and | |
995 | * low halves of the page, with one half ready for use by the hardware | |
996 | * and the other half being consumed by the stack. We use the page | |
997 | * ref count to determine whether the stack has finished consuming the | |
998 | * portion of this page that was passed up with a previous packet. If | |
999 | * the page ref count is >1, we'll assume the "other" half page is | |
1000 | * still busy, and this page cannot be reused. | |
1001 | * | |
1002 | * For larger pages, @truesize will be the actual space used by the | |
1003 | * received packet (adjusted upward to an even multiple of the cache | |
1004 | * line size). This will advance through the page by the amount | |
1005 | * actually consumed by the received packets while there is still | |
1006 | * space for a buffer. Each region of larger pages will be used at | |
1007 | * most once, after which the page will not be reused. | |
1008 | * | |
1009 | * In either case, if the page is reusable its refcount is increased. | |
1010 | **/ | |
a0cfc313 | 1011 | static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer) |
9b37c937 | 1012 | { |
a0cfc313 AD |
1013 | unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; |
1014 | struct page *page = rx_buffer->page; | |
9b37c937 SP |
1015 | |
1016 | /* Is any reuse possible? */ | |
1017 | if (unlikely(!i40e_page_is_reusable(page))) | |
1018 | return false; | |
1019 | ||
1020 | #if (PAGE_SIZE < 8192) | |
1021 | /* if we are only owner of page we can reuse it */ | |
a0cfc313 | 1022 | if (unlikely((page_count(page) - pagecnt_bias) > 1)) |
9b37c937 | 1023 | return false; |
9b37c937 | 1024 | #else |
98efd694 AD |
1025 | #define I40E_LAST_OFFSET \ |
1026 | (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) | |
1027 | if (rx_buffer->page_offset > I40E_LAST_OFFSET) | |
9b37c937 SP |
1028 | return false; |
1029 | #endif | |
1030 | ||
1793668c AD |
1031 | /* If we have drained the page fragment pool we need to update |
1032 | * the pagecnt_bias and page count so that we fully restock the | |
1033 | * number of references the driver holds. | |
1034 | */ | |
a0cfc313 | 1035 | if (unlikely(!pagecnt_bias)) { |
1793668c AD |
1036 | page_ref_add(page, USHRT_MAX); |
1037 | rx_buffer->pagecnt_bias = USHRT_MAX; | |
1038 | } | |
9b37c937 SP |
1039 | |
1040 | return true; | |
ab9ad98e JB |
1041 | } |
1042 | ||
1043 | /** | |
1044 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1045 | * @rx_ring: rx descriptor ring to transact packets on | |
1046 | * @rx_buffer: buffer containing page to add | |
ab9ad98e | 1047 | * @skb: sk_buff to place the data into |
a0cfc313 | 1048 | * @size: packet length from rx_desc |
ab9ad98e JB |
1049 | * |
1050 | * This function will add the data contained in rx_buffer->page to the skb. | |
fa2343e9 | 1051 | * It will just attach the page as a frag to the skb. |
ab9ad98e | 1052 | * |
fa2343e9 | 1053 | * The function will then update the page offset. |
ab9ad98e | 1054 | **/ |
a0cfc313 | 1055 | static void i40e_add_rx_frag(struct i40e_ring *rx_ring, |
ab9ad98e | 1056 | struct i40e_rx_buffer *rx_buffer, |
a0cfc313 AD |
1057 | struct sk_buff *skb, |
1058 | unsigned int size) | |
ab9ad98e | 1059 | { |
ab9ad98e | 1060 | #if (PAGE_SIZE < 8192) |
98efd694 | 1061 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
ab9ad98e | 1062 | #else |
ca9ec088 | 1063 | unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)); |
a132af24 | 1064 | #endif |
ab9ad98e | 1065 | |
fa2343e9 AD |
1066 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, |
1067 | rx_buffer->page_offset, size, truesize); | |
ab9ad98e | 1068 | |
a0cfc313 AD |
1069 | /* page is being used so we must update the page offset */ |
1070 | #if (PAGE_SIZE < 8192) | |
1071 | rx_buffer->page_offset ^= truesize; | |
1072 | #else | |
1073 | rx_buffer->page_offset += truesize; | |
1074 | #endif | |
ab9ad98e JB |
1075 | } |
1076 | ||
9a064128 AD |
1077 | /** |
1078 | * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use | |
1079 | * @rx_ring: rx descriptor ring to transact packets on | |
1080 | * @size: size of buffer to add to skb | |
1081 | * | |
1082 | * This function will pull an Rx buffer from the ring and synchronize it | |
1083 | * for use by the CPU. | |
1084 | */ | |
1085 | static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, | |
1086 | const unsigned int size) | |
1087 | { | |
1088 | struct i40e_rx_buffer *rx_buffer; | |
1089 | ||
1090 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1091 | prefetchw(rx_buffer->page); | |
1092 | ||
1093 | /* we are reusing so sync this buffer for CPU use */ | |
1094 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1095 | rx_buffer->dma, | |
1096 | rx_buffer->page_offset, | |
1097 | size, | |
1098 | DMA_FROM_DEVICE); | |
1099 | ||
a0cfc313 AD |
1100 | /* We have pulled a buffer for use, so decrement pagecnt_bias */ |
1101 | rx_buffer->pagecnt_bias--; | |
1102 | ||
9a064128 AD |
1103 | return rx_buffer; |
1104 | } | |
1105 | ||
ab9ad98e | 1106 | /** |
fa2343e9 | 1107 | * i40e_construct_skb - Allocate skb and populate it |
ab9ad98e | 1108 | * @rx_ring: rx descriptor ring to transact packets on |
9a064128 | 1109 | * @rx_buffer: rx buffer to pull data from |
d57c0e08 | 1110 | * @size: size of buffer to add to skb |
ab9ad98e | 1111 | * |
fa2343e9 AD |
1112 | * This function allocates an skb. It then populates it with the page |
1113 | * data from the current receive descriptor, taking care to set up the | |
1114 | * skb correctly. | |
ab9ad98e | 1115 | */ |
fa2343e9 AD |
1116 | static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, |
1117 | struct i40e_rx_buffer *rx_buffer, | |
1118 | unsigned int size) | |
ab9ad98e | 1119 | { |
fa2343e9 AD |
1120 | void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; |
1121 | #if (PAGE_SIZE < 8192) | |
98efd694 | 1122 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
fa2343e9 AD |
1123 | #else |
1124 | unsigned int truesize = SKB_DATA_ALIGN(size); | |
1125 | #endif | |
1126 | unsigned int headlen; | |
1127 | struct sk_buff *skb; | |
ab9ad98e | 1128 | |
fa2343e9 AD |
1129 | /* prefetch first cache line of first page */ |
1130 | prefetch(va); | |
ab9ad98e | 1131 | #if L1_CACHE_BYTES < 128 |
fa2343e9 | 1132 | prefetch(va + L1_CACHE_BYTES); |
ab9ad98e JB |
1133 | #endif |
1134 | ||
fa2343e9 AD |
1135 | /* allocate a skb to store the frags */ |
1136 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
1137 | I40E_RX_HDR_SIZE, | |
1138 | GFP_ATOMIC | __GFP_NOWARN); | |
1139 | if (unlikely(!skb)) | |
1140 | return NULL; | |
1141 | ||
1142 | /* Determine available headroom for copy */ | |
1143 | headlen = size; | |
1144 | if (headlen > I40E_RX_HDR_SIZE) | |
1145 | headlen = eth_get_headlen(va, I40E_RX_HDR_SIZE); | |
ab9ad98e | 1146 | |
fa2343e9 AD |
1147 | /* align pull length to size of long to optimize memcpy performance */ |
1148 | memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); | |
1149 | ||
1150 | /* update all of the pointers */ | |
1151 | size -= headlen; | |
1152 | if (size) { | |
1153 | skb_add_rx_frag(skb, 0, rx_buffer->page, | |
1154 | rx_buffer->page_offset + headlen, | |
1155 | size, truesize); | |
1156 | ||
1157 | /* buffer is used by skb, update page_offset */ | |
1158 | #if (PAGE_SIZE < 8192) | |
1159 | rx_buffer->page_offset ^= truesize; | |
1160 | #else | |
1161 | rx_buffer->page_offset += truesize; | |
1162 | #endif | |
1163 | } else { | |
1164 | /* buffer is unused, reset bias back to rx_buffer */ | |
1165 | rx_buffer->pagecnt_bias++; | |
1166 | } | |
a0cfc313 AD |
1167 | |
1168 | return skb; | |
1169 | } | |
1170 | ||
f8b45b74 AD |
1171 | /** |
1172 | * i40e_build_skb - Build skb around an existing buffer | |
1173 | * @rx_ring: Rx descriptor ring to transact packets on | |
1174 | * @rx_buffer: Rx buffer to pull data from | |
1175 | * @size: size of buffer to add to skb | |
1176 | * | |
1177 | * This function builds an skb around an existing Rx buffer, taking care | |
1178 | * to set up the skb correctly and avoid any memcpy overhead. | |
1179 | */ | |
1180 | static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, | |
1181 | struct i40e_rx_buffer *rx_buffer, | |
1182 | unsigned int size) | |
1183 | { | |
1184 | void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; | |
1185 | #if (PAGE_SIZE < 8192) | |
1186 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; | |
1187 | #else | |
2aae918c BT |
1188 | unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1189 | SKB_DATA_ALIGN(I40E_SKB_PAD + size); | |
f8b45b74 AD |
1190 | #endif |
1191 | struct sk_buff *skb; | |
1192 | ||
1193 | /* prefetch first cache line of first page */ | |
1194 | prefetch(va); | |
1195 | #if L1_CACHE_BYTES < 128 | |
1196 | prefetch(va + L1_CACHE_BYTES); | |
1197 | #endif | |
1198 | /* build an skb around the page buffer */ | |
1199 | skb = build_skb(va - I40E_SKB_PAD, truesize); | |
1200 | if (unlikely(!skb)) | |
1201 | return NULL; | |
1202 | ||
1203 | /* update pointers within the skb to store the data */ | |
1204 | skb_reserve(skb, I40E_SKB_PAD); | |
1205 | __skb_put(skb, size); | |
1206 | ||
1207 | /* buffer is used by skb, update page_offset */ | |
1208 | #if (PAGE_SIZE < 8192) | |
1209 | rx_buffer->page_offset ^= truesize; | |
1210 | #else | |
1211 | rx_buffer->page_offset += truesize; | |
1212 | #endif | |
1213 | ||
1214 | return skb; | |
1215 | } | |
1216 | ||
a0cfc313 AD |
1217 | /** |
1218 | * i40e_put_rx_buffer - Clean up used buffer and either recycle or free | |
1219 | * @rx_ring: rx descriptor ring to transact packets on | |
1220 | * @rx_buffer: rx buffer to pull data from | |
1221 | * | |
1222 | * This function will clean up the contents of the rx_buffer. It will | |
1223 | * either recycle the bufer or unmap it and free the associated resources. | |
1224 | */ | |
1225 | static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, | |
1226 | struct i40e_rx_buffer *rx_buffer) | |
1227 | { | |
1228 | if (i40e_can_reuse_rx_page(rx_buffer)) { | |
ab9ad98e JB |
1229 | /* hand second half of page back to the ring */ |
1230 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1231 | rx_ring->rx_stats.page_reuse_count++; | |
1232 | } else { | |
1233 | /* we are not reusing the buffer so unmap it */ | |
98efd694 AD |
1234 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, |
1235 | i40e_rx_pg_size(rx_ring), | |
59605bc0 | 1236 | DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); |
1793668c AD |
1237 | __page_frag_cache_drain(rx_buffer->page, |
1238 | rx_buffer->pagecnt_bias); | |
ab9ad98e JB |
1239 | } |
1240 | ||
1241 | /* clear contents of buffer_info */ | |
1242 | rx_buffer->page = NULL; | |
ab9ad98e JB |
1243 | } |
1244 | ||
1245 | /** | |
1246 | * i40e_is_non_eop - process handling of non-EOP buffers | |
1247 | * @rx_ring: Rx ring being processed | |
1248 | * @rx_desc: Rx descriptor for current buffer | |
1249 | * @skb: Current socket buffer containing buffer in progress | |
1250 | * | |
1251 | * This function updates next to clean. If the buffer is an EOP buffer | |
1252 | * this function exits returning false, otherwise it will place the | |
1253 | * sk_buff in the next buffer to be chained and return true indicating | |
1254 | * that this is in fact a non-EOP buffer. | |
1255 | **/ | |
1256 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, | |
1257 | union i40e_rx_desc *rx_desc, | |
1258 | struct sk_buff *skb) | |
1259 | { | |
1260 | u32 ntc = rx_ring->next_to_clean + 1; | |
1261 | ||
1262 | /* fetch, update, and store next to clean */ | |
1263 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1264 | rx_ring->next_to_clean = ntc; | |
1265 | ||
1266 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1267 | ||
1268 | /* if we are the last buffer then there is nothing else to do */ | |
1269 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
1270 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
1271 | return false; | |
1272 | ||
ab9ad98e JB |
1273 | rx_ring->rx_stats.non_eop_descs++; |
1274 | ||
1275 | return true; | |
a132af24 MW |
1276 | } |
1277 | ||
1278 | /** | |
ab9ad98e JB |
1279 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf |
1280 | * @rx_ring: rx descriptor ring to transact packets on | |
1281 | * @budget: Total limit on number of packets to process | |
1282 | * | |
1283 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1284 | * processing. The advantage to this is that on systems that have | |
1285 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1286 | * it by maintaining the mapping of the page to the system. | |
a132af24 | 1287 | * |
ab9ad98e | 1288 | * Returns amount of work completed |
a132af24 | 1289 | **/ |
ab9ad98e | 1290 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) |
a132af24 MW |
1291 | { |
1292 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
e72e5659 | 1293 | struct sk_buff *skb = rx_ring->skb; |
a132af24 | 1294 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); |
c2e245ab | 1295 | bool failure = false; |
a132af24 | 1296 | |
b85c94b6 | 1297 | while (likely(total_rx_packets < (unsigned int)budget)) { |
9a064128 | 1298 | struct i40e_rx_buffer *rx_buffer; |
ab9ad98e | 1299 | union i40e_rx_desc *rx_desc; |
d57c0e08 | 1300 | unsigned int size; |
a132af24 | 1301 | u16 vlan_tag; |
ab9ad98e JB |
1302 | u8 rx_ptype; |
1303 | u64 qword; | |
1304 | ||
7f12ad74 GR |
1305 | /* return some buffers to hardware, one at a time is too slow */ |
1306 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 1307 | failure = failure || |
ab9ad98e | 1308 | i40evf_alloc_rx_buffers(rx_ring, cleaned_count); |
7f12ad74 GR |
1309 | cleaned_count = 0; |
1310 | } | |
1311 | ||
ab9ad98e JB |
1312 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
1313 | ||
ab9ad98e JB |
1314 | /* status_error_len will always be zero for unused descriptors |
1315 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
1316 | * which is always zero because packet split isn't used, if the | |
d57c0e08 | 1317 | * hardware wrote DD then the length will be non-zero |
ab9ad98e | 1318 | */ |
d57c0e08 | 1319 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
ab9ad98e | 1320 | |
a132af24 | 1321 | /* This memory barrier is needed to keep us from reading |
d57c0e08 AD |
1322 | * any other fields out of the rx_desc until we have |
1323 | * verified the descriptor has been written back. | |
a132af24 | 1324 | */ |
67317166 | 1325 | dma_rmb(); |
a132af24 | 1326 | |
0e626ff7 AD |
1327 | size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> |
1328 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1329 | if (!size) | |
1330 | break; | |
1331 | ||
ed0980c4 | 1332 | i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb); |
9a064128 AD |
1333 | rx_buffer = i40e_get_rx_buffer(rx_ring, size); |
1334 | ||
fa2343e9 AD |
1335 | /* retrieve a buffer from the ring */ |
1336 | if (skb) | |
1337 | i40e_add_rx_frag(rx_ring, rx_buffer, skb, size); | |
f8b45b74 AD |
1338 | else if (ring_uses_build_skb(rx_ring)) |
1339 | skb = i40e_build_skb(rx_ring, rx_buffer, size); | |
fa2343e9 AD |
1340 | else |
1341 | skb = i40e_construct_skb(rx_ring, rx_buffer, size); | |
1342 | ||
1343 | /* exit if we failed to retrieve a buffer */ | |
1344 | if (!skb) { | |
1345 | rx_ring->rx_stats.alloc_buff_failed++; | |
1346 | rx_buffer->pagecnt_bias++; | |
ab9ad98e | 1347 | break; |
fa2343e9 | 1348 | } |
a132af24 | 1349 | |
a0cfc313 | 1350 | i40e_put_rx_buffer(rx_ring, rx_buffer); |
a132af24 MW |
1351 | cleaned_count++; |
1352 | ||
ab9ad98e | 1353 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 1354 | continue; |
a132af24 | 1355 | |
ab9ad98e JB |
1356 | /* ERR_MASK will only have valid bits if EOP set, and |
1357 | * what we are doing here is actually checking | |
1358 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
1359 | * the error field | |
1360 | */ | |
1361 | if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
a132af24 | 1362 | dev_kfree_skb_any(skb); |
741b8b83 | 1363 | skb = NULL; |
a132af24 MW |
1364 | continue; |
1365 | } | |
1366 | ||
e72e5659 SP |
1367 | if (i40e_cleanup_headers(rx_ring, skb)) { |
1368 | skb = NULL; | |
ab9ad98e | 1369 | continue; |
e72e5659 | 1370 | } |
ab9ad98e | 1371 | |
a132af24 MW |
1372 | /* probably a little skewed due to removing CRC */ |
1373 | total_rx_bytes += skb->len; | |
a132af24 | 1374 | |
99dad8b3 AD |
1375 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1376 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> | |
1377 | I40E_RXD_QW1_PTYPE_SHIFT; | |
1378 | ||
ab9ad98e JB |
1379 | /* populate checksum, VLAN, and protocol */ |
1380 | i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); | |
a132af24 | 1381 | |
a132af24 | 1382 | |
ab9ad98e JB |
1383 | vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? |
1384 | le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; | |
1385 | ||
ed0980c4 | 1386 | i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb); |
a132af24 | 1387 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
e72e5659 | 1388 | skb = NULL; |
a132af24 | 1389 | |
ab9ad98e JB |
1390 | /* update budget accounting */ |
1391 | total_rx_packets++; | |
1392 | } | |
7f12ad74 | 1393 | |
e72e5659 SP |
1394 | rx_ring->skb = skb; |
1395 | ||
7f12ad74 GR |
1396 | u64_stats_update_begin(&rx_ring->syncp); |
1397 | rx_ring->stats.packets += total_rx_packets; | |
1398 | rx_ring->stats.bytes += total_rx_bytes; | |
1399 | u64_stats_update_end(&rx_ring->syncp); | |
1400 | rx_ring->q_vector->rx.total_packets += total_rx_packets; | |
1401 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1402 | ||
ab9ad98e | 1403 | /* guarantee a trip back through this routine if there was a failure */ |
b85c94b6 | 1404 | return failure ? budget : (int)total_rx_packets; |
7f12ad74 GR |
1405 | } |
1406 | ||
8f5e39ce JB |
1407 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
1408 | { | |
1409 | u32 val; | |
1410 | ||
1411 | val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
dbadbbe2 | 1412 | I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK | |
8f5e39ce JB |
1413 | (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | |
1414 | (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT); | |
1415 | ||
1416 | return val; | |
1417 | } | |
1418 | ||
1419 | /* a small macro to shorten up some long lines */ | |
1420 | #define INTREG I40E_VFINT_DYN_CTLN1 | |
3c234c47 | 1421 | static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 JK |
1422 | { |
1423 | struct i40evf_adapter *adapter = vsi->back; | |
1424 | ||
3c234c47 | 1425 | return adapter->rx_rings[idx].rx_itr_setting; |
65e87c03 JK |
1426 | } |
1427 | ||
3c234c47 | 1428 | static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 JK |
1429 | { |
1430 | struct i40evf_adapter *adapter = vsi->back; | |
1431 | ||
3c234c47 | 1432 | return adapter->tx_rings[idx].tx_itr_setting; |
65e87c03 | 1433 | } |
8f5e39ce | 1434 | |
de32e3ef CW |
1435 | /** |
1436 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
1437 | * @vsi: the VSI we care about | |
1438 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
1439 | * | |
1440 | **/ | |
1441 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
1442 | struct i40e_q_vector *q_vector) | |
1443 | { | |
1444 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
1445 | bool rx = false, tx = false; |
1446 | u32 rxval, txval; | |
de32e3ef | 1447 | int vector; |
65e87c03 JK |
1448 | int idx = q_vector->v_idx; |
1449 | int rx_itr_setting, tx_itr_setting; | |
de32e3ef CW |
1450 | |
1451 | vector = (q_vector->v_idx + vsi->base_vector); | |
ee2319cf JB |
1452 | |
1453 | /* avoid dynamic calculation if in countdown mode OR if | |
1454 | * all dynamic is disabled | |
1455 | */ | |
8f5e39ce JB |
1456 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
1457 | ||
3c234c47 CW |
1458 | rx_itr_setting = get_rx_itr(vsi, idx); |
1459 | tx_itr_setting = get_tx_itr(vsi, idx); | |
65e87c03 | 1460 | |
ee2319cf | 1461 | if (q_vector->itr_countdown > 0 || |
65e87c03 JK |
1462 | (!ITR_IS_DYNAMIC(rx_itr_setting) && |
1463 | !ITR_IS_DYNAMIC(tx_itr_setting))) { | |
ee2319cf JB |
1464 | goto enable_int; |
1465 | } | |
1466 | ||
65e87c03 | 1467 | if (ITR_IS_DYNAMIC(rx_itr_setting)) { |
8f5e39ce JB |
1468 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
1469 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 1470 | } |
4eeb1fff | 1471 | |
65e87c03 | 1472 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
1473 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
1474 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
1475 | } | |
4eeb1fff | 1476 | |
8f5e39ce JB |
1477 | if (rx || tx) { |
1478 | /* get the higher of the two ITR adjustments and | |
1479 | * use the same value for both ITR registers | |
1480 | * when in adaptive mode (Rx and/or Tx) | |
1481 | */ | |
1482 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
1483 | ||
1484 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
1485 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
1486 | tx = true; | |
1487 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
1488 | rx = true; | |
de32e3ef | 1489 | } |
8f5e39ce JB |
1490 | |
1491 | /* only need to enable the interrupt once, but need | |
1492 | * to possibly update both ITR values | |
1493 | */ | |
1494 | if (rx) { | |
1495 | /* set the INTENA_MSK_MASK so that this first write | |
1496 | * won't actually enable the interrupt, instead just | |
1497 | * updating the ITR (it's bit 31 PF and VF) | |
1498 | */ | |
1499 | rxval |= BIT(31); | |
1500 | /* don't check _DOWN because interrupt isn't being enabled */ | |
1501 | wr32(hw, INTREG(vector - 1), rxval); | |
1502 | } | |
1503 | ||
ee2319cf | 1504 | enable_int: |
0da36b97 | 1505 | if (!test_bit(__I40E_VSI_DOWN, vsi->state)) |
8f5e39ce | 1506 | wr32(hw, INTREG(vector - 1), txval); |
ee2319cf JB |
1507 | |
1508 | if (q_vector->itr_countdown) | |
1509 | q_vector->itr_countdown--; | |
1510 | else | |
1511 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
1512 | } |
1513 | ||
7f12ad74 GR |
1514 | /** |
1515 | * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1516 | * @napi: napi struct with our devices info in it | |
1517 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1518 | * | |
1519 | * This function will clean all queues associated with a q_vector. | |
1520 | * | |
1521 | * Returns the amount of work done | |
1522 | **/ | |
1523 | int i40evf_napi_poll(struct napi_struct *napi, int budget) | |
1524 | { | |
1525 | struct i40e_q_vector *q_vector = | |
1526 | container_of(napi, struct i40e_q_vector, napi); | |
1527 | struct i40e_vsi *vsi = q_vector->vsi; | |
1528 | struct i40e_ring *ring; | |
1529 | bool clean_complete = true; | |
c29af37f | 1530 | bool arm_wb = false; |
7f12ad74 | 1531 | int budget_per_ring; |
32b3e08f | 1532 | int work_done = 0; |
7f12ad74 | 1533 | |
0da36b97 | 1534 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) { |
7f12ad74 GR |
1535 | napi_complete(napi); |
1536 | return 0; | |
1537 | } | |
1538 | ||
1539 | /* Since the actual Tx work is minimal, we can give the Tx a larger | |
1540 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1541 | */ | |
c29af37f | 1542 | i40e_for_each_ring(ring, q_vector->tx) { |
a619afe8 | 1543 | if (!i40e_clean_tx_irq(vsi, ring, budget)) { |
f2edaaaa AD |
1544 | clean_complete = false; |
1545 | continue; | |
1546 | } | |
1547 | arm_wb |= ring->arm_wb; | |
0deda868 | 1548 | ring->arm_wb = false; |
c29af37f | 1549 | } |
7f12ad74 | 1550 | |
c67caceb AD |
1551 | /* Handle case where we are called by netpoll with a budget of 0 */ |
1552 | if (budget <= 0) | |
1553 | goto tx_only; | |
1554 | ||
7f12ad74 GR |
1555 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
1556 | * allow the budget to go below 1 because that would exit polling early. | |
1557 | */ | |
1558 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
1559 | ||
a132af24 | 1560 | i40e_for_each_ring(ring, q_vector->rx) { |
ab9ad98e | 1561 | int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); |
32b3e08f JB |
1562 | |
1563 | work_done += cleaned; | |
f2edaaaa AD |
1564 | /* if we clean as many as budgeted, we must not be done */ |
1565 | if (cleaned >= budget_per_ring) | |
1566 | clean_complete = false; | |
a132af24 | 1567 | } |
7f12ad74 GR |
1568 | |
1569 | /* If work not completed, return budget and polling will return */ | |
c29af37f | 1570 | if (!clean_complete) { |
96db776a AB |
1571 | int cpu_id = smp_processor_id(); |
1572 | ||
1573 | /* It is possible that the interrupt affinity has changed but, | |
1574 | * if the cpu is pegged at 100%, polling will never exit while | |
1575 | * traffic continues and the interrupt will be stuck on this | |
1576 | * cpu. We check to make sure affinity is correct before we | |
1577 | * continue to poll, otherwise we must stop polling so the | |
1578 | * interrupt can move to the correct cpu. | |
1579 | */ | |
6d977729 JK |
1580 | if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) { |
1581 | /* Tell napi that we are done polling */ | |
1582 | napi_complete_done(napi, work_done); | |
1583 | ||
1584 | /* Force an interrupt */ | |
1585 | i40evf_force_wb(vsi, q_vector); | |
1586 | ||
1587 | /* Return budget-1 so that polling stops */ | |
1588 | return budget - 1; | |
1589 | } | |
c67caceb | 1590 | tx_only: |
6d977729 JK |
1591 | if (arm_wb) { |
1592 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
1593 | i40e_enable_wb_on_itr(vsi, q_vector); | |
164c9f54 | 1594 | } |
6d977729 | 1595 | return budget; |
c29af37f | 1596 | } |
7f12ad74 | 1597 | |
8e0764b4 ASJ |
1598 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
1599 | q_vector->arm_wb_state = false; | |
1600 | ||
7f12ad74 | 1601 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 1602 | napi_complete_done(napi, work_done); |
96db776a | 1603 | |
6d977729 | 1604 | i40e_update_enable_itr(vsi, q_vector); |
96db776a | 1605 | |
6beb84a7 | 1606 | return min(work_done, budget - 1); |
7f12ad74 GR |
1607 | } |
1608 | ||
1609 | /** | |
3e587cf3 | 1610 | * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW |
7f12ad74 GR |
1611 | * @skb: send buffer |
1612 | * @tx_ring: ring to send buffer on | |
1613 | * @flags: the tx flags to be set | |
1614 | * | |
1615 | * Checks the skb and set up correspondingly several generic transmit flags | |
1616 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
1617 | * | |
1618 | * Returns error code indicate the frame should be dropped upon error and the | |
1619 | * otherwise returns 0 to indicate the flags has been set properly. | |
1620 | **/ | |
3e587cf3 JB |
1621 | static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb, |
1622 | struct i40e_ring *tx_ring, | |
1623 | u32 *flags) | |
7f12ad74 GR |
1624 | { |
1625 | __be16 protocol = skb->protocol; | |
1626 | u32 tx_flags = 0; | |
1627 | ||
31eaaccf GR |
1628 | if (protocol == htons(ETH_P_8021Q) && |
1629 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
1630 | /* When HW VLAN acceleration is turned off by the user the | |
1631 | * stack sets the protocol to 8021q so that the driver | |
1632 | * can take any steps required to support the SW only | |
1633 | * VLAN handling. In our case the driver doesn't need | |
1634 | * to take any further steps so just set the protocol | |
1635 | * to the encapsulated ethertype. | |
1636 | */ | |
1637 | skb->protocol = vlan_get_protocol(skb); | |
1638 | goto out; | |
1639 | } | |
1640 | ||
7f12ad74 | 1641 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
1642 | if (skb_vlan_tag_present(skb)) { |
1643 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
7f12ad74 GR |
1644 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
1645 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
1646 | } else if (protocol == htons(ETH_P_8021Q)) { | |
1647 | struct vlan_hdr *vhdr, _vhdr; | |
6995b36c | 1648 | |
7f12ad74 GR |
1649 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
1650 | if (!vhdr) | |
1651 | return -EINVAL; | |
1652 | ||
1653 | protocol = vhdr->h_vlan_encapsulated_proto; | |
1654 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
1655 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
1656 | } | |
1657 | ||
31eaaccf | 1658 | out: |
7f12ad74 GR |
1659 | *flags = tx_flags; |
1660 | return 0; | |
1661 | } | |
1662 | ||
1663 | /** | |
1664 | * i40e_tso - set up the tso context descriptor | |
52ea3e80 | 1665 | * @first: pointer to first Tx buffer for xmit |
7f12ad74 | 1666 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 1667 | * @cd_type_cmd_tso_mss: Quad Word 1 |
7f12ad74 GR |
1668 | * |
1669 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
1670 | **/ | |
52ea3e80 AD |
1671 | static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, |
1672 | u64 *cd_type_cmd_tso_mss) | |
7f12ad74 | 1673 | { |
52ea3e80 | 1674 | struct sk_buff *skb = first->skb; |
03f9d6a5 | 1675 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
1676 | union { |
1677 | struct iphdr *v4; | |
1678 | struct ipv6hdr *v6; | |
1679 | unsigned char *hdr; | |
1680 | } ip; | |
c49a7bc3 AD |
1681 | union { |
1682 | struct tcphdr *tcp; | |
5453205c | 1683 | struct udphdr *udp; |
c49a7bc3 AD |
1684 | unsigned char *hdr; |
1685 | } l4; | |
1686 | u32 paylen, l4_offset; | |
52ea3e80 | 1687 | u16 gso_segs, gso_size; |
7f12ad74 | 1688 | int err; |
7f12ad74 | 1689 | |
e9f6563d SN |
1690 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1691 | return 0; | |
1692 | ||
7f12ad74 GR |
1693 | if (!skb_is_gso(skb)) |
1694 | return 0; | |
1695 | ||
fe6d4aa4 FR |
1696 | err = skb_cow_head(skb, 0); |
1697 | if (err < 0) | |
1698 | return err; | |
7f12ad74 | 1699 | |
c777019a AD |
1700 | ip.hdr = skb_network_header(skb); |
1701 | l4.hdr = skb_transport_header(skb); | |
85e76d03 | 1702 | |
c777019a AD |
1703 | /* initialize outer IP header fields */ |
1704 | if (ip.v4->version == 4) { | |
1705 | ip.v4->tot_len = 0; | |
1706 | ip.v4->check = 0; | |
c49a7bc3 | 1707 | } else { |
c777019a AD |
1708 | ip.v6->payload_len = 0; |
1709 | } | |
1710 | ||
577389a5 | 1711 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 1712 | SKB_GSO_GRE_CSUM | |
7e13318d | 1713 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 1714 | SKB_GSO_IPXIP6 | |
577389a5 | 1715 | SKB_GSO_UDP_TUNNEL | |
5453205c | 1716 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
1717 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
1718 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
1719 | l4.udp->len = 0; | |
1720 | ||
5453205c AD |
1721 | /* determine offset of outer transport header */ |
1722 | l4_offset = l4.hdr - skb->data; | |
1723 | ||
1724 | /* remove payload length from outer checksum */ | |
24d41e5e | 1725 | paylen = skb->len - l4_offset; |
b9c015d4 JK |
1726 | csum_replace_by_diff(&l4.udp->check, |
1727 | (__force __wsum)htonl(paylen)); | |
5453205c AD |
1728 | } |
1729 | ||
c777019a AD |
1730 | /* reset pointers to inner headers */ |
1731 | ip.hdr = skb_inner_network_header(skb); | |
1732 | l4.hdr = skb_inner_transport_header(skb); | |
1733 | ||
1734 | /* initialize inner IP header fields */ | |
1735 | if (ip.v4->version == 4) { | |
1736 | ip.v4->tot_len = 0; | |
1737 | ip.v4->check = 0; | |
1738 | } else { | |
1739 | ip.v6->payload_len = 0; | |
1740 | } | |
7f12ad74 GR |
1741 | } |
1742 | ||
c49a7bc3 AD |
1743 | /* determine offset of inner transport header */ |
1744 | l4_offset = l4.hdr - skb->data; | |
1745 | ||
1746 | /* remove payload length from inner checksum */ | |
24d41e5e | 1747 | paylen = skb->len - l4_offset; |
b9c015d4 | 1748 | csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); |
c49a7bc3 AD |
1749 | |
1750 | /* compute length of segmentation header */ | |
1751 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
7f12ad74 | 1752 | |
52ea3e80 AD |
1753 | /* pull values out of skb_shinfo */ |
1754 | gso_size = skb_shinfo(skb)->gso_size; | |
1755 | gso_segs = skb_shinfo(skb)->gso_segs; | |
1756 | ||
1757 | /* update GSO size and bytecount with header size */ | |
1758 | first->gso_segs = gso_segs; | |
1759 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
1760 | ||
7f12ad74 GR |
1761 | /* find the field values */ |
1762 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
1763 | cd_tso_len = skb->len - *hdr_len; | |
52ea3e80 | 1764 | cd_mss = gso_size; |
03f9d6a5 AD |
1765 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
1766 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
1767 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
7f12ad74 GR |
1768 | return 1; |
1769 | } | |
1770 | ||
1771 | /** | |
1772 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
1773 | * @skb: send buffer | |
89232c3b | 1774 | * @tx_flags: pointer to Tx flags currently set |
7f12ad74 GR |
1775 | * @td_cmd: Tx descriptor command bits to set |
1776 | * @td_offset: Tx descriptor header offsets to set | |
529f1f65 | 1777 | * @tx_ring: Tx descriptor ring |
7f12ad74 GR |
1778 | * @cd_tunneling: ptr to context desc bits |
1779 | **/ | |
529f1f65 AD |
1780 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
1781 | u32 *td_cmd, u32 *td_offset, | |
1782 | struct i40e_ring *tx_ring, | |
1783 | u32 *cd_tunneling) | |
7f12ad74 | 1784 | { |
b96b78f2 AD |
1785 | union { |
1786 | struct iphdr *v4; | |
1787 | struct ipv6hdr *v6; | |
1788 | unsigned char *hdr; | |
1789 | } ip; | |
1790 | union { | |
1791 | struct tcphdr *tcp; | |
1792 | struct udphdr *udp; | |
1793 | unsigned char *hdr; | |
1794 | } l4; | |
a3fd9d88 | 1795 | unsigned char *exthdr; |
d1bd743b | 1796 | u32 offset, cmd = 0; |
a3fd9d88 | 1797 | __be16 frag_off; |
b96b78f2 AD |
1798 | u8 l4_proto = 0; |
1799 | ||
529f1f65 AD |
1800 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1801 | return 0; | |
1802 | ||
b96b78f2 AD |
1803 | ip.hdr = skb_network_header(skb); |
1804 | l4.hdr = skb_transport_header(skb); | |
7f12ad74 | 1805 | |
475b4205 AD |
1806 | /* compute outer L2 header size */ |
1807 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
1808 | ||
7f12ad74 | 1809 | if (skb->encapsulation) { |
d1bd743b | 1810 | u32 tunnel = 0; |
a0064728 AD |
1811 | /* define outer network header type */ |
1812 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
1813 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1814 | I40E_TX_CTX_EXT_IP_IPV4 : | |
1815 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
1816 | ||
a0064728 AD |
1817 | l4_proto = ip.v4->protocol; |
1818 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 1819 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
1820 | |
1821 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 1822 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
1823 | if (l4.hdr != exthdr) |
1824 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1825 | &l4_proto, &frag_off); | |
a0064728 AD |
1826 | } |
1827 | ||
1828 | /* define outer transport */ | |
1829 | switch (l4_proto) { | |
45991204 | 1830 | case IPPROTO_UDP: |
475b4205 | 1831 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
89232c3b | 1832 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
45991204 | 1833 | break; |
a0064728 | 1834 | case IPPROTO_GRE: |
475b4205 | 1835 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 AD |
1836 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
1837 | break; | |
577389a5 AD |
1838 | case IPPROTO_IPIP: |
1839 | case IPPROTO_IPV6: | |
1840 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; | |
1841 | l4.hdr = skb_inner_network_header(skb); | |
1842 | break; | |
45991204 | 1843 | default: |
529f1f65 AD |
1844 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1845 | return -1; | |
1846 | ||
1847 | skb_checksum_help(skb); | |
1848 | return 0; | |
45991204 | 1849 | } |
b96b78f2 | 1850 | |
577389a5 AD |
1851 | /* compute outer L3 header size */ |
1852 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
1853 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
1854 | ||
1855 | /* switch IP header pointer from outer to inner header */ | |
1856 | ip.hdr = skb_inner_network_header(skb); | |
1857 | ||
475b4205 AD |
1858 | /* compute tunnel header size */ |
1859 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
1860 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
1861 | ||
5453205c AD |
1862 | /* indicate if we need to offload outer UDP header */ |
1863 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 1864 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
1865 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
1866 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
1867 | ||
475b4205 AD |
1868 | /* record tunnel offload values */ |
1869 | *cd_tunneling |= tunnel; | |
1870 | ||
b96b78f2 | 1871 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 1872 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 1873 | l4_proto = 0; |
7f12ad74 | 1874 | |
a0064728 AD |
1875 | /* reset type as we transition from outer to inner headers */ |
1876 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
1877 | if (ip.v4->version == 4) | |
1878 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
1879 | if (ip.v6->version == 6) | |
89232c3b | 1880 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
7f12ad74 GR |
1881 | } |
1882 | ||
1883 | /* Enable IP checksum offloads */ | |
89232c3b | 1884 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 1885 | l4_proto = ip.v4->protocol; |
7f12ad74 GR |
1886 | /* the stack computes the IP header already, the only time we |
1887 | * need the hardware to recompute it is in the case of TSO. | |
1888 | */ | |
475b4205 AD |
1889 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1890 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
1891 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 1892 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 1893 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
1894 | |
1895 | exthdr = ip.hdr + sizeof(*ip.v6); | |
1896 | l4_proto = ip.v6->nexthdr; | |
1897 | if (l4.hdr != exthdr) | |
1898 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1899 | &l4_proto, &frag_off); | |
7f12ad74 | 1900 | } |
b96b78f2 | 1901 | |
475b4205 AD |
1902 | /* compute inner L3 header size */ |
1903 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
7f12ad74 GR |
1904 | |
1905 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 1906 | switch (l4_proto) { |
7f12ad74 GR |
1907 | case IPPROTO_TCP: |
1908 | /* enable checksum offloads */ | |
475b4205 AD |
1909 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
1910 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1911 | break; |
1912 | case IPPROTO_SCTP: | |
1913 | /* enable SCTP checksum offload */ | |
475b4205 AD |
1914 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
1915 | offset |= (sizeof(struct sctphdr) >> 2) << | |
1916 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1917 | break; |
1918 | case IPPROTO_UDP: | |
1919 | /* enable UDP checksum offload */ | |
475b4205 AD |
1920 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
1921 | offset |= (sizeof(struct udphdr) >> 2) << | |
1922 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1923 | break; |
1924 | default: | |
529f1f65 AD |
1925 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1926 | return -1; | |
1927 | skb_checksum_help(skb); | |
1928 | return 0; | |
7f12ad74 | 1929 | } |
475b4205 AD |
1930 | |
1931 | *td_cmd |= cmd; | |
1932 | *td_offset |= offset; | |
529f1f65 AD |
1933 | |
1934 | return 1; | |
7f12ad74 GR |
1935 | } |
1936 | ||
1937 | /** | |
1938 | * i40e_create_tx_ctx Build the Tx context descriptor | |
1939 | * @tx_ring: ring to create the descriptor on | |
1940 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
1941 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
1942 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
1943 | **/ | |
1944 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
1945 | const u64 cd_type_cmd_tso_mss, | |
1946 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
1947 | { | |
1948 | struct i40e_tx_context_desc *context_desc; | |
1949 | int i = tx_ring->next_to_use; | |
1950 | ||
ff40dd5d JB |
1951 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
1952 | !cd_tunneling && !cd_l2tag2) | |
7f12ad74 GR |
1953 | return; |
1954 | ||
1955 | /* grab the next descriptor */ | |
1956 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); | |
1957 | ||
1958 | i++; | |
1959 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
1960 | ||
1961 | /* cpu_to_le32 and assign to struct fields */ | |
1962 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
1963 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 1964 | context_desc->rsvd = cpu_to_le16(0); |
7f12ad74 GR |
1965 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
1966 | } | |
1967 | ||
4eeb1fff | 1968 | /** |
3f3f7cb8 | 1969 | * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 1970 | * @skb: send buffer |
71da6197 | 1971 | * |
3f3f7cb8 AD |
1972 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
1973 | * and so we need to figure out the cases where we need to linearize the skb. | |
1974 | * | |
1975 | * For TSO we need to count the TSO header and segment payload separately. | |
1976 | * As such we need to check cases where we have 7 fragments or more as we | |
1977 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
1978 | * the segment payload in the first descriptor, and another 7 for the | |
1979 | * fragments. | |
71da6197 | 1980 | **/ |
2d37490b | 1981 | bool __i40evf_chk_linearize(struct sk_buff *skb) |
71da6197 | 1982 | { |
2d37490b | 1983 | const struct skb_frag_struct *frag, *stale; |
3f3f7cb8 | 1984 | int nr_frags, sum; |
71da6197 | 1985 | |
3f3f7cb8 | 1986 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 1987 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 1988 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 1989 | return false; |
71da6197 | 1990 | |
2d37490b | 1991 | /* We need to walk through the list and validate that each group |
841493a3 | 1992 | * of 6 fragments totals at least gso_size. |
2d37490b | 1993 | */ |
3f3f7cb8 | 1994 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
1995 | frag = &skb_shinfo(skb)->frags[0]; |
1996 | ||
1997 | /* Initialize size to the negative value of gso_size minus 1. We | |
1998 | * use this as the worst case scenerio in which the frag ahead | |
1999 | * of us only provides one byte which is why we are limited to 6 | |
2000 | * descriptors for a single transmit as the header and previous | |
2001 | * fragment are already consuming 2 descriptors. | |
2002 | */ | |
3f3f7cb8 | 2003 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 2004 | |
3f3f7cb8 AD |
2005 | /* Add size of frags 0 through 4 to create our initial sum */ |
2006 | sum += skb_frag_size(frag++); | |
2007 | sum += skb_frag_size(frag++); | |
2008 | sum += skb_frag_size(frag++); | |
2009 | sum += skb_frag_size(frag++); | |
2010 | sum += skb_frag_size(frag++); | |
2d37490b AD |
2011 | |
2012 | /* Walk through fragments adding latest fragment, testing it, and | |
2013 | * then removing stale fragments from the sum. | |
2014 | */ | |
2015 | stale = &skb_shinfo(skb)->frags[0]; | |
2016 | for (;;) { | |
3f3f7cb8 | 2017 | sum += skb_frag_size(frag++); |
2d37490b AD |
2018 | |
2019 | /* if sum is negative we failed to make sufficient progress */ | |
2020 | if (sum < 0) | |
2021 | return true; | |
2022 | ||
841493a3 | 2023 | if (!nr_frags--) |
2d37490b AD |
2024 | break; |
2025 | ||
3f3f7cb8 | 2026 | sum -= skb_frag_size(stale++); |
71da6197 AS |
2027 | } |
2028 | ||
2d37490b | 2029 | return false; |
71da6197 AS |
2030 | } |
2031 | ||
8f6a2b05 JB |
2032 | /** |
2033 | * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions | |
2034 | * @tx_ring: the ring to be checked | |
2035 | * @size: the size buffer we want to assure is available | |
2036 | * | |
2037 | * Returns -EBUSY if a stop is needed, else 0 | |
2038 | **/ | |
4ec441df | 2039 | int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
8f6a2b05 JB |
2040 | { |
2041 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2042 | /* Memory barrier before checking head and tail */ | |
2043 | smp_mb(); | |
2044 | ||
2045 | /* Check again in a case another CPU has just made room available. */ | |
2046 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
2047 | return -EBUSY; | |
2048 | ||
2049 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
2050 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2051 | ++tx_ring->tx_stats.restart_queue; | |
2052 | return 0; | |
2053 | } | |
2054 | ||
7f12ad74 | 2055 | /** |
3e587cf3 | 2056 | * i40evf_tx_map - Build the Tx descriptor |
7f12ad74 GR |
2057 | * @tx_ring: ring to send buffer on |
2058 | * @skb: send buffer | |
2059 | * @first: first buffer info buffer to use | |
2060 | * @tx_flags: collected send information | |
2061 | * @hdr_len: size of the packet header | |
2062 | * @td_cmd: the command field in the descriptor | |
2063 | * @td_offset: offset for checksum or crc | |
2064 | **/ | |
3e587cf3 JB |
2065 | static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
2066 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2067 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
7f12ad74 GR |
2068 | { |
2069 | unsigned int data_len = skb->data_len; | |
2070 | unsigned int size = skb_headlen(skb); | |
2071 | struct skb_frag_struct *frag; | |
2072 | struct i40e_tx_buffer *tx_bi; | |
2073 | struct i40e_tx_desc *tx_desc; | |
2074 | u16 i = tx_ring->next_to_use; | |
2075 | u32 td_tag = 0; | |
2076 | dma_addr_t dma; | |
7f12ad74 GR |
2077 | |
2078 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { | |
2079 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2080 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2081 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2082 | } | |
2083 | ||
7f12ad74 GR |
2084 | first->tx_flags = tx_flags; |
2085 | ||
2086 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2087 | ||
2088 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
2089 | tx_bi = first; | |
2090 | ||
2091 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
2092 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
2093 | ||
7f12ad74 GR |
2094 | if (dma_mapping_error(tx_ring->dev, dma)) |
2095 | goto dma_error; | |
2096 | ||
2097 | /* record length, and DMA address */ | |
2098 | dma_unmap_len_set(tx_bi, len, size); | |
2099 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2100 | ||
5c4654da AD |
2101 | /* align size to end of page */ |
2102 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
7f12ad74 GR |
2103 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2104 | ||
2105 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
2106 | tx_desc->cmd_type_offset_bsz = | |
2107 | build_ctob(td_cmd, td_offset, | |
5c4654da | 2108 | max_data, td_tag); |
7f12ad74 GR |
2109 | |
2110 | tx_desc++; | |
2111 | i++; | |
6a7fded7 | 2112 | |
7f12ad74 GR |
2113 | if (i == tx_ring->count) { |
2114 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2115 | i = 0; | |
2116 | } | |
2117 | ||
5c4654da AD |
2118 | dma += max_data; |
2119 | size -= max_data; | |
7f12ad74 | 2120 | |
5c4654da | 2121 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
7f12ad74 GR |
2122 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2123 | } | |
2124 | ||
2125 | if (likely(!data_len)) | |
2126 | break; | |
2127 | ||
2128 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, | |
2129 | size, td_tag); | |
2130 | ||
2131 | tx_desc++; | |
2132 | i++; | |
6a7fded7 | 2133 | |
7f12ad74 GR |
2134 | if (i == tx_ring->count) { |
2135 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2136 | i = 0; | |
2137 | } | |
2138 | ||
2139 | size = skb_frag_size(frag); | |
2140 | data_len -= size; | |
2141 | ||
2142 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, | |
2143 | DMA_TO_DEVICE); | |
2144 | ||
2145 | tx_bi = &tx_ring->tx_bi[i]; | |
2146 | } | |
2147 | ||
1dc8b538 | 2148 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
7f12ad74 GR |
2149 | |
2150 | i++; | |
2151 | if (i == tx_ring->count) | |
2152 | i = 0; | |
2153 | ||
2154 | tx_ring->next_to_use = i; | |
2155 | ||
4ec441df | 2156 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
6a7fded7 | 2157 | |
b1cb07db PB |
2158 | /* write last descriptor with RS and EOP bits */ |
2159 | td_cmd |= I40E_TXD_CMD; | |
6a7fded7 | 2160 | tx_desc->cmd_type_offset_bsz = |
1dc8b538 AD |
2161 | build_ctob(td_cmd, td_offset, size, td_tag); |
2162 | ||
2163 | /* Force memory writes to complete before letting h/w know there | |
2164 | * are new descriptors to fetch. | |
2165 | * | |
2166 | * We also use this memory barrier to make certain all of the | |
2167 | * status bits have been updated before next_to_watch is written. | |
2168 | */ | |
2169 | wmb(); | |
2170 | ||
2171 | /* set next_to_watch value indicating a packet is present */ | |
2172 | first->next_to_watch = tx_desc; | |
6a7fded7 | 2173 | |
7f12ad74 | 2174 | /* notify HW of packet */ |
b1cb07db | 2175 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { |
6a7fded7 | 2176 | writel(i, tx_ring->tail); |
1dc8b538 AD |
2177 | |
2178 | /* we need this if more than one processor can write to our tail | |
2179 | * at a time, it synchronizes IO on IA64/Altix systems | |
2180 | */ | |
2181 | mmiowb(); | |
6a7fded7 | 2182 | } |
1dc8b538 | 2183 | |
7f12ad74 GR |
2184 | return; |
2185 | ||
2186 | dma_error: | |
2187 | dev_info(tx_ring->dev, "TX DMA map failed\n"); | |
2188 | ||
2189 | /* clear dma mappings for failed tx_bi map */ | |
2190 | for (;;) { | |
2191 | tx_bi = &tx_ring->tx_bi[i]; | |
2192 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); | |
2193 | if (tx_bi == first) | |
2194 | break; | |
2195 | if (i == 0) | |
2196 | i = tx_ring->count; | |
2197 | i--; | |
2198 | } | |
2199 | ||
2200 | tx_ring->next_to_use = i; | |
2201 | } | |
2202 | ||
7f12ad74 GR |
2203 | /** |
2204 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
2205 | * @skb: send buffer | |
2206 | * @tx_ring: ring to send buffer on | |
2207 | * | |
2208 | * Returns NETDEV_TX_OK if sent, else an error code | |
2209 | **/ | |
2210 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
2211 | struct i40e_ring *tx_ring) | |
2212 | { | |
2213 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
2214 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
2215 | struct i40e_tx_buffer *first; | |
2216 | u32 td_offset = 0; | |
2217 | u32 tx_flags = 0; | |
2218 | __be16 protocol; | |
2219 | u32 td_cmd = 0; | |
2220 | u8 hdr_len = 0; | |
4ec441df | 2221 | int tso, count; |
6995b36c | 2222 | |
b74118f0 JB |
2223 | /* prefetch the data, we'll need it later */ |
2224 | prefetch(skb->data); | |
2225 | ||
ed0980c4 SP |
2226 | i40e_trace(xmit_frame_ring, skb, tx_ring); |
2227 | ||
4ec441df | 2228 | count = i40e_xmit_descriptor_count(skb); |
2d37490b | 2229 | if (i40e_chk_linearize(skb, count)) { |
52ea3e80 AD |
2230 | if (__skb_linearize(skb)) { |
2231 | dev_kfree_skb_any(skb); | |
2232 | return NETDEV_TX_OK; | |
2233 | } | |
5c4654da | 2234 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
2235 | tx_ring->tx_stats.tx_linearize++; |
2236 | } | |
4ec441df AD |
2237 | |
2238 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
2239 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
2240 | * + 4 desc gap to avoid the cache line where head is, | |
2241 | * + 1 desc for context descriptor, | |
2242 | * otherwise try next time | |
2243 | */ | |
2244 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
2245 | tx_ring->tx_stats.tx_busy++; | |
7f12ad74 | 2246 | return NETDEV_TX_BUSY; |
4ec441df | 2247 | } |
7f12ad74 | 2248 | |
52ea3e80 AD |
2249 | /* record the location of the first descriptor for this packet */ |
2250 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
2251 | first->skb = skb; | |
2252 | first->bytecount = skb->len; | |
2253 | first->gso_segs = 1; | |
2254 | ||
7f12ad74 | 2255 | /* prepare the xmit flags */ |
3e587cf3 | 2256 | if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) |
7f12ad74 GR |
2257 | goto out_drop; |
2258 | ||
2259 | /* obtain protocol of skb */ | |
a12c4158 | 2260 | protocol = vlan_get_protocol(skb); |
7f12ad74 | 2261 | |
7f12ad74 GR |
2262 | /* setup IPv4/IPv6 offloads */ |
2263 | if (protocol == htons(ETH_P_IP)) | |
2264 | tx_flags |= I40E_TX_FLAGS_IPV4; | |
2265 | else if (protocol == htons(ETH_P_IPV6)) | |
2266 | tx_flags |= I40E_TX_FLAGS_IPV6; | |
2267 | ||
52ea3e80 | 2268 | tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); |
7f12ad74 GR |
2269 | |
2270 | if (tso < 0) | |
2271 | goto out_drop; | |
2272 | else if (tso) | |
2273 | tx_flags |= I40E_TX_FLAGS_TSO; | |
2274 | ||
7f12ad74 | 2275 | /* Always offload the checksum, since it's in the data descriptor */ |
529f1f65 AD |
2276 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, |
2277 | tx_ring, &cd_tunneling); | |
2278 | if (tso < 0) | |
2279 | goto out_drop; | |
7f12ad74 | 2280 | |
3bc67973 AD |
2281 | skb_tx_timestamp(skb); |
2282 | ||
2283 | /* always enable CRC insertion offload */ | |
2284 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
2285 | ||
7f12ad74 GR |
2286 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
2287 | cd_tunneling, cd_l2tag2); | |
2288 | ||
3e587cf3 JB |
2289 | i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len, |
2290 | td_cmd, td_offset); | |
7f12ad74 | 2291 | |
7f12ad74 GR |
2292 | return NETDEV_TX_OK; |
2293 | ||
2294 | out_drop: | |
ed0980c4 | 2295 | i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); |
52ea3e80 AD |
2296 | dev_kfree_skb_any(first->skb); |
2297 | first->skb = NULL; | |
7f12ad74 GR |
2298 | return NETDEV_TX_OK; |
2299 | } | |
2300 | ||
2301 | /** | |
2302 | * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
2303 | * @skb: send buffer | |
2304 | * @netdev: network interface device structure | |
2305 | * | |
2306 | * Returns NETDEV_TX_OK if sent, else an error code | |
2307 | **/ | |
2308 | netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2309 | { | |
2310 | struct i40evf_adapter *adapter = netdev_priv(netdev); | |
0dd438d8 | 2311 | struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping]; |
7f12ad74 GR |
2312 | |
2313 | /* hardware can't handle really short frames, hardware padding works | |
2314 | * beyond this point | |
2315 | */ | |
2316 | if (unlikely(skb->len < I40E_MIN_TX_LEN)) { | |
2317 | if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len)) | |
2318 | return NETDEV_TX_OK; | |
2319 | skb->len = I40E_MIN_TX_LEN; | |
2320 | skb_set_tail_pointer(skb, I40E_MIN_TX_LEN); | |
2321 | } | |
2322 | ||
2323 | return i40e_xmit_frame_ring(skb, tx_ring); | |
2324 | } |