]>
Commit | Line | Data |
---|---|---|
5321a21c GR |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver | |
00e5ec4b | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
5321a21c GR |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
b831607d JB |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
5321a21c GR |
18 | * The full GNU General Public License is included in this distribution in |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
27 | #ifndef _I40EVF_H_ | |
28 | #define _I40EVF_H_ | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/aer.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/vmalloc.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/if_vlan.h> | |
38 | #include <linux/ip.h> | |
39 | #include <linux/tcp.h> | |
40 | #include <linux/sctp.h> | |
41 | #include <linux/ipv6.h> | |
42 | #include <net/ip6_checksum.h> | |
43 | #include <net/udp.h> | |
5321a21c GR |
44 | |
45 | #include "i40e_type.h" | |
46 | #include "i40e_virtchnl.h" | |
47 | #include "i40e_txrx.h" | |
48 | ||
49 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
50 | #define PFX "i40evf: " | |
5321a21c GR |
51 | |
52 | /* dummy struct to make common code less painful */ | |
53 | struct i40e_vsi { | |
54 | struct i40evf_adapter *back; | |
55 | struct net_device *netdev; | |
56 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
57 | u16 seid; | |
58 | u16 id; | |
59 | unsigned long state; | |
60 | int base_vector; | |
61 | u16 work_limit; | |
62 | /* high bit set means dynamic, use accessor routines to read/write. | |
63 | * hardware only supports 2us resolution for the ITR registers. | |
64 | * these values always store the USER setting, and must be converted | |
65 | * before programming to a register. | |
66 | */ | |
67 | u16 rx_itr_setting; | |
68 | u16 tx_itr_setting; | |
f578f5f4 | 69 | u16 qs_handle; |
5321a21c GR |
70 | }; |
71 | ||
72 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
73 | #define I40EVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
74 | #define I40EVF_DEFAULT_TXD 512 | |
75 | #define I40EVF_DEFAULT_RXD 512 | |
76 | #define I40EVF_MAX_TXD 4096 | |
77 | #define I40EVF_MIN_TXD 64 | |
78 | #define I40EVF_MAX_RXD 4096 | |
79 | #define I40EVF_MIN_RXD 64 | |
337eb08e | 80 | #define I40EVF_REQ_DESCRIPTOR_MULTIPLE 32 |
5321a21c GR |
81 | |
82 | /* Supported Rx Buffer Sizes */ | |
5321a21c GR |
83 | #define I40EVF_RXBUFFER_2048 2048 |
84 | #define I40EVF_MAX_RXBUFFER 16384 /* largest size for single descriptor */ | |
85 | #define I40EVF_MAX_AQ_BUF_SIZE 4096 | |
86 | #define I40EVF_AQ_LEN 32 | |
3f7e5c33 | 87 | #define I40EVF_AQ_MAX_ERR 20 /* times to try before resetting AQ */ |
5321a21c GR |
88 | |
89 | #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) | |
90 | ||
91 | #define I40E_RX_DESC(R, i) (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) | |
92 | #define I40E_TX_DESC(R, i) (&(((struct i40e_tx_desc *)((R)->desc))[i])) | |
93 | #define I40E_TX_CTXTDESC(R, i) \ | |
94 | (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) | |
1255b7a1 | 95 | #define MAX_QUEUES 16 |
5321a21c | 96 | |
e25d00b8 | 97 | #define I40EVF_HKEY_ARRAY_SIZE ((I40E_VFQF_HKEY_MAX_INDEX + 1) * 4) |
2c86ac3c | 98 | #define I40EVF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT_MAX_INDEX + 1) * 4) |
e25d00b8 | 99 | |
5321a21c GR |
100 | /* MAX_MSIX_Q_VECTORS of these are allocated, |
101 | * but we only use one per queue-specific vector. | |
102 | */ | |
103 | struct i40e_q_vector { | |
104 | struct i40evf_adapter *adapter; | |
105 | struct i40e_vsi *vsi; | |
106 | struct napi_struct napi; | |
107 | unsigned long reg_idx; | |
108 | struct i40e_ring_container rx; | |
109 | struct i40e_ring_container tx; | |
110 | u32 ring_mask; | |
111 | u8 num_ringpairs; /* total number of ring pairs in vector */ | |
ee2319cf JB |
112 | #define ITR_COUNTDOWN_START 100 |
113 | u8 itr_countdown; /* when 0 or 1 update ITR */ | |
5321a21c GR |
114 | int v_idx; /* vector index in list */ |
115 | char name[IFNAMSIZ + 9]; | |
8e0764b4 | 116 | bool arm_wb_state; |
5321a21c GR |
117 | cpumask_var_t affinity_mask; |
118 | }; | |
119 | ||
120 | /* Helper macros to switch between ints/sec and what the register uses. | |
121 | * And yes, it's the same math going both ways. The lowest value | |
122 | * supported by all of the i40e hardware is 8. | |
123 | */ | |
124 | #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ | |
125 | ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) | |
126 | #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG | |
127 | ||
128 | #define I40EVF_DESC_UNUSED(R) \ | |
129 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ | |
130 | (R)->next_to_clean - (R)->next_to_use - 1) | |
131 | ||
132 | #define I40EVF_RX_DESC_ADV(R, i) \ | |
133 | (&(((union i40e_adv_rx_desc *)((R).desc))[i])) | |
134 | #define I40EVF_TX_DESC_ADV(R, i) \ | |
135 | (&(((union i40e_adv_tx_desc *)((R).desc))[i])) | |
136 | #define I40EVF_TX_CTXTDESC_ADV(R, i) \ | |
137 | (&(((struct i40e_adv_tx_context_desc *)((R).desc))[i])) | |
138 | ||
139 | #define OTHER_VECTOR 1 | |
140 | #define NONQ_VECS (OTHER_VECTOR) | |
141 | ||
5321a21c GR |
142 | #define MIN_MSIX_Q_VECTORS 1 |
143 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NONQ_VECS) | |
144 | ||
145 | #define I40EVF_QUEUE_END_OF_LIST 0x7FF | |
146 | #define I40EVF_FREE_VECTOR 0x7FFF | |
147 | struct i40evf_mac_filter { | |
148 | struct list_head list; | |
149 | u8 macaddr[ETH_ALEN]; | |
150 | bool remove; /* filter needs to be removed */ | |
151 | bool add; /* filter needs to be added */ | |
152 | }; | |
153 | ||
154 | struct i40evf_vlan_filter { | |
155 | struct list_head list; | |
156 | u16 vlan; | |
157 | bool remove; /* filter needs to be removed */ | |
158 | bool add; /* filter needs to be added */ | |
159 | }; | |
160 | ||
161 | /* Driver state. The order of these is important! */ | |
162 | enum i40evf_state_t { | |
163 | __I40EVF_STARTUP, /* driver loaded, probe complete */ | |
5321a21c GR |
164 | __I40EVF_REMOVE, /* driver is being unloaded */ |
165 | __I40EVF_INIT_VERSION_CHECK, /* aq msg sent, awaiting reply */ | |
166 | __I40EVF_INIT_GET_RESOURCES, /* aq msg sent, awaiting reply */ | |
167 | __I40EVF_INIT_SW, /* got resources, setting up structs */ | |
ef8693eb | 168 | __I40EVF_RESETTING, /* in reset */ |
5321a21c GR |
169 | /* Below here, watchdog is running */ |
170 | __I40EVF_DOWN, /* ready, can be opened */ | |
209dc4da | 171 | __I40EVF_DOWN_PENDING, /* descending, waiting for watchdog */ |
5321a21c | 172 | __I40EVF_TESTING, /* in ethtool self-test */ |
5321a21c GR |
173 | __I40EVF_RUNNING, /* opened, working */ |
174 | }; | |
175 | ||
176 | enum i40evf_critical_section_t { | |
177 | __I40EVF_IN_CRITICAL_TASK, /* cannot be interrupted */ | |
178 | }; | |
179 | /* make common code happy */ | |
180 | #define __I40E_DOWN __I40EVF_DOWN | |
181 | ||
182 | /* board specific private data structure */ | |
183 | struct i40evf_adapter { | |
184 | struct timer_list watchdog_timer; | |
5321a21c GR |
185 | struct work_struct reset_task; |
186 | struct work_struct adminq_task; | |
187 | struct delayed_work init_task; | |
7d96ba1a | 188 | struct i40e_q_vector *q_vectors; |
5321a21c | 189 | struct list_head vlan_filter_list; |
e1dfee8e | 190 | char misc_vector_name[IFNAMSIZ + 9]; |
cc052927 | 191 | int num_active_queues; |
5321a21c | 192 | |
5321a21c | 193 | /* TX */ |
0dd438d8 | 194 | struct i40e_ring *tx_rings; |
5321a21c GR |
195 | u32 tx_timeout_count; |
196 | struct list_head mac_filter_list; | |
d732a184 | 197 | u32 tx_desc_count; |
5321a21c GR |
198 | |
199 | /* RX */ | |
0dd438d8 | 200 | struct i40e_ring *rx_rings; |
5321a21c | 201 | u64 hw_csum_rx_error; |
d732a184 | 202 | u32 rx_desc_count; |
5321a21c GR |
203 | int num_msix_vectors; |
204 | struct msix_entry *msix_entries; | |
205 | ||
e8106ebe | 206 | u32 flags; |
41a1d04b | 207 | #define I40EVF_FLAG_RX_CSUM_ENABLED BIT(0) |
41a1d04b JB |
208 | #define I40EVF_FLAG_IMIR_ENABLED BIT(5) |
209 | #define I40EVF_FLAG_MQ_CAPABLE BIT(6) | |
210 | #define I40EVF_FLAG_NEED_LINK_UPDATE BIT(7) | |
211 | #define I40EVF_FLAG_PF_COMMS_FAILED BIT(8) | |
212 | #define I40EVF_FLAG_RESET_PENDING BIT(9) | |
213 | #define I40EVF_FLAG_RESET_NEEDED BIT(10) | |
d502ce01 ASJ |
214 | #define I40EVF_FLAG_WB_ON_ITR_CAPABLE BIT(11) |
215 | #define I40EVF_FLAG_OUTER_UDP_CSUM_CAPABLE BIT(12) | |
14e52ee2 | 216 | #define I40EVF_FLAG_ADDR_SET_BY_PF BIT(13) |
47d34839 | 217 | #define I40EVF_FLAG_PROMISC_ON BIT(15) |
f42a5c74 | 218 | #define I40EVF_FLAG_ALLMULTI_ON BIT(16) |
d502ce01 | 219 | /* duplicates for common code */ |
5321a21c GR |
220 | #define I40E_FLAG_FDIR_ATR_ENABLED 0 |
221 | #define I40E_FLAG_DCB_ENABLED 0 | |
5321a21c | 222 | #define I40E_FLAG_RX_CSUM_ENABLED I40EVF_FLAG_RX_CSUM_ENABLED |
d502ce01 ASJ |
223 | #define I40E_FLAG_WB_ON_ITR_CAPABLE I40EVF_FLAG_WB_ON_ITR_CAPABLE |
224 | #define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE I40EVF_FLAG_OUTER_UDP_CSUM_CAPABLE | |
5321a21c GR |
225 | /* flags for admin queue service task */ |
226 | u32 aq_required; | |
41a1d04b JB |
227 | #define I40EVF_FLAG_AQ_ENABLE_QUEUES BIT(0) |
228 | #define I40EVF_FLAG_AQ_DISABLE_QUEUES BIT(1) | |
229 | #define I40EVF_FLAG_AQ_ADD_MAC_FILTER BIT(2) | |
230 | #define I40EVF_FLAG_AQ_ADD_VLAN_FILTER BIT(3) | |
231 | #define I40EVF_FLAG_AQ_DEL_MAC_FILTER BIT(4) | |
232 | #define I40EVF_FLAG_AQ_DEL_VLAN_FILTER BIT(5) | |
233 | #define I40EVF_FLAG_AQ_CONFIGURE_QUEUES BIT(6) | |
234 | #define I40EVF_FLAG_AQ_MAP_VECTORS BIT(7) | |
235 | #define I40EVF_FLAG_AQ_HANDLE_RESET BIT(8) | |
43a3d9ba | 236 | #define I40EVF_FLAG_AQ_CONFIGURE_RSS BIT(9) /* direct AQ config */ |
41a1d04b | 237 | #define I40EVF_FLAG_AQ_GET_CONFIG BIT(10) |
43a3d9ba MW |
238 | /* Newer style, RSS done by the PF so we can ignore hardware vagaries. */ |
239 | #define I40EVF_FLAG_AQ_GET_HENA BIT(11) | |
240 | #define I40EVF_FLAG_AQ_SET_HENA BIT(12) | |
241 | #define I40EVF_FLAG_AQ_SET_RSS_KEY BIT(13) | |
242 | #define I40EVF_FLAG_AQ_SET_RSS_LUT BIT(14) | |
47d34839 ASJ |
243 | #define I40EVF_FLAG_AQ_REQUEST_PROMISC BIT(15) |
244 | #define I40EVF_FLAG_AQ_RELEASE_PROMISC BIT(16) | |
f42a5c74 ASJ |
245 | #define I40EVF_FLAG_AQ_REQUEST_ALLMULTI BIT(17) |
246 | #define I40EVF_FLAG_AQ_RELEASE_ALLMULTI BIT(18) | |
ef8693eb | 247 | |
5321a21c GR |
248 | /* OS defined structs */ |
249 | struct net_device *netdev; | |
250 | struct pci_dev *pdev; | |
251 | struct net_device_stats net_stats; | |
252 | ||
708e8c24 | 253 | struct i40e_hw hw; /* defined in i40e_type.h */ |
5321a21c GR |
254 | |
255 | enum i40evf_state_t state; | |
75a64435 | 256 | unsigned long crit_section; |
5321a21c GR |
257 | |
258 | struct work_struct watchdog_task; | |
259 | bool netdev_registered; | |
5321a21c GR |
260 | bool link_up; |
261 | enum i40e_virtchnl_ops current_op; | |
c0913c2e MW |
262 | #define CLIENT_ENABLED(_a) ((_a)->vf_res ? \ |
263 | (_a)->vf_res->vf_offload_flags & \ | |
264 | I40E_VIRTCHNL_VF_OFFLOAD_IWARP : \ | |
265 | 0) | |
43a3d9ba MW |
266 | /* RSS by the PF should be preferred over RSS via other methods. */ |
267 | #define RSS_PF(_a) ((_a)->vf_res->vf_offload_flags & \ | |
268 | I40E_VIRTCHNL_VF_OFFLOAD_RSS_PF) | |
17a65a7f MW |
269 | #define RSS_AQ(_a) ((_a)->vf_res->vf_offload_flags & \ |
270 | I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ) | |
43a3d9ba MW |
271 | #define RSS_REG(_a) (!((_a)->vf_res->vf_offload_flags & \ |
272 | (I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ | \ | |
273 | I40E_VIRTCHNL_VF_OFFLOAD_RSS_PF))) | |
17a65a7f MW |
274 | #define VLAN_ALLOWED(_a) ((_a)->vf_res->vf_offload_flags & \ |
275 | I40E_VIRTCHNL_VF_OFFLOAD_VLAN) | |
5321a21c GR |
276 | struct i40e_virtchnl_vf_resource *vf_res; /* incl. all VSIs */ |
277 | struct i40e_virtchnl_vsi_resource *vsi_res; /* our LAN VSI */ | |
17a65a7f MW |
278 | struct i40e_virtchnl_version_info pf_version; |
279 | #define PF_IS_V11(_a) (((_a)->pf_version.major == 1) && \ | |
280 | ((_a)->pf_version.minor == 1)) | |
5321a21c GR |
281 | u16 msg_enable; |
282 | struct i40e_eth_stats current_stats; | |
283 | struct i40e_vsi vsi; | |
284 | u32 aq_wait_count; | |
43a3d9ba MW |
285 | /* RSS stuff */ |
286 | u64 hena; | |
287 | u16 rss_key_size; | |
288 | u16 rss_lut_size; | |
289 | u8 *rss_key; | |
290 | u8 *rss_lut; | |
5321a21c GR |
291 | }; |
292 | ||
5321a21c | 293 | |
00e5ec4b | 294 | /* Ethtool Private Flags */ |
00e5ec4b | 295 | |
5321a21c GR |
296 | /* needed by i40evf_ethtool.c */ |
297 | extern char i40evf_driver_name[]; | |
298 | extern const char i40evf_driver_version[]; | |
299 | ||
300 | int i40evf_up(struct i40evf_adapter *adapter); | |
301 | void i40evf_down(struct i40evf_adapter *adapter); | |
e6d038de | 302 | int i40evf_process_config(struct i40evf_adapter *adapter); |
00e5ec4b | 303 | void i40evf_schedule_reset(struct i40evf_adapter *adapter); |
5321a21c GR |
304 | void i40evf_reset(struct i40evf_adapter *adapter); |
305 | void i40evf_set_ethtool_ops(struct net_device *netdev); | |
306 | void i40evf_update_stats(struct i40evf_adapter *adapter); | |
307 | void i40evf_reset_interrupt_capability(struct i40evf_adapter *adapter); | |
308 | int i40evf_init_interrupt_scheme(struct i40evf_adapter *adapter); | |
309 | void i40evf_irq_enable_queues(struct i40evf_adapter *adapter, u32 mask); | |
e284fc88 MW |
310 | void i40evf_free_all_tx_resources(struct i40evf_adapter *adapter); |
311 | void i40evf_free_all_rx_resources(struct i40evf_adapter *adapter); | |
5321a21c GR |
312 | |
313 | void i40e_napi_add_all(struct i40evf_adapter *adapter); | |
314 | void i40e_napi_del_all(struct i40evf_adapter *adapter); | |
315 | ||
316 | int i40evf_send_api_ver(struct i40evf_adapter *adapter); | |
317 | int i40evf_verify_api_ver(struct i40evf_adapter *adapter); | |
318 | int i40evf_send_vf_config_msg(struct i40evf_adapter *adapter); | |
319 | int i40evf_get_vf_config(struct i40evf_adapter *adapter); | |
320 | void i40evf_irq_enable(struct i40evf_adapter *adapter, bool flush); | |
321 | void i40evf_configure_queues(struct i40evf_adapter *adapter); | |
322 | void i40evf_deconfigure_queues(struct i40evf_adapter *adapter); | |
323 | void i40evf_enable_queues(struct i40evf_adapter *adapter); | |
324 | void i40evf_disable_queues(struct i40evf_adapter *adapter); | |
325 | void i40evf_map_queues(struct i40evf_adapter *adapter); | |
326 | void i40evf_add_ether_addrs(struct i40evf_adapter *adapter); | |
327 | void i40evf_del_ether_addrs(struct i40evf_adapter *adapter); | |
328 | void i40evf_add_vlans(struct i40evf_adapter *adapter); | |
329 | void i40evf_del_vlans(struct i40evf_adapter *adapter); | |
330 | void i40evf_set_promiscuous(struct i40evf_adapter *adapter, int flags); | |
331 | void i40evf_request_stats(struct i40evf_adapter *adapter); | |
625777e3 | 332 | void i40evf_request_reset(struct i40evf_adapter *adapter); |
43a3d9ba MW |
333 | void i40evf_get_hena(struct i40evf_adapter *adapter); |
334 | void i40evf_set_hena(struct i40evf_adapter *adapter); | |
335 | void i40evf_set_rss_key(struct i40evf_adapter *adapter); | |
336 | void i40evf_set_rss_lut(struct i40evf_adapter *adapter); | |
5321a21c GR |
337 | void i40evf_virtchnl_completion(struct i40evf_adapter *adapter, |
338 | enum i40e_virtchnl_ops v_opcode, | |
339 | i40e_status v_retval, u8 *msg, u16 msglen); | |
43a3d9ba | 340 | int i40evf_config_rss(struct i40evf_adapter *adapter); |
5321a21c | 341 | #endif /* _I40EVF_H_ */ |