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7ec59eea AV |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright (c) 2018, Intel Corporation. */ | |
3 | ||
4 | #include "ice_common.h" | |
9c20346b | 5 | #include "ice_sched.h" |
7ec59eea AV |
6 | #include "ice_adminq_cmd.h" |
7 | ||
f31e4b6f AV |
8 | #define ICE_PF_RESET_WAIT_COUNT 200 |
9 | ||
22ef683b AV |
10 | #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \ |
11 | wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \ | |
cdedef59 AV |
12 | ((ICE_RX_OPC_MDID << \ |
13 | GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ | |
14 | GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ | |
15 | (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ | |
16 | GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) | |
17 | ||
22ef683b AV |
18 | #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \ |
19 | wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \ | |
cdedef59 AV |
20 | (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ |
21 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ | |
22 | (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ | |
23 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ | |
24 | (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ | |
25 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ | |
26 | (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ | |
27 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) | |
28 | ||
f31e4b6f AV |
29 | /** |
30 | * ice_set_mac_type - Sets MAC type | |
31 | * @hw: pointer to the HW structure | |
32 | * | |
33 | * This function sets the MAC type of the adapter based on the | |
34 | * vendor ID and device ID stored in the hw structure. | |
35 | */ | |
36 | static enum ice_status ice_set_mac_type(struct ice_hw *hw) | |
37 | { | |
38 | if (hw->vendor_id != PCI_VENDOR_ID_INTEL) | |
39 | return ICE_ERR_DEVICE_NOT_SUPPORTED; | |
40 | ||
41 | hw->mac_type = ICE_MAC_GENERIC; | |
42 | return 0; | |
43 | } | |
44 | ||
f203dca3 AV |
45 | /** |
46 | * ice_dev_onetime_setup - Temporary HW/FW workarounds | |
47 | * @hw: pointer to the HW structure | |
48 | * | |
49 | * This function provides temporary workarounds for certain issues | |
50 | * that are expected to be fixed in the HW/FW. | |
51 | */ | |
52 | void ice_dev_onetime_setup(struct ice_hw *hw) | |
53 | { | |
54 | /* configure Rx - set non pxe mode */ | |
55 | wr32(hw, GLLAN_RCTL_0, 0x1); | |
56 | ||
57 | #define MBX_PF_VT_PFALLOC 0x00231E80 | |
58 | /* set VFs per PF */ | |
59 | wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF)); | |
60 | } | |
61 | ||
f31e4b6f AV |
62 | /** |
63 | * ice_clear_pf_cfg - Clear PF configuration | |
64 | * @hw: pointer to the hardware structure | |
3968540b AV |
65 | * |
66 | * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port | |
67 | * configuration, flow director filters, etc.). | |
f31e4b6f AV |
68 | */ |
69 | enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) | |
70 | { | |
71 | struct ice_aq_desc desc; | |
72 | ||
73 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); | |
74 | ||
75 | return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); | |
76 | } | |
77 | ||
dc49c772 AV |
78 | /** |
79 | * ice_aq_manage_mac_read - manage MAC address read command | |
80 | * @hw: pointer to the hw struct | |
81 | * @buf: a virtual buffer to hold the manage MAC read response | |
82 | * @buf_size: Size of the virtual buffer | |
83 | * @cd: pointer to command details structure or NULL | |
84 | * | |
85 | * This function is used to return per PF station MAC address (0x0107). | |
86 | * NOTE: Upon successful completion of this command, MAC address information | |
87 | * is returned in user specified buffer. Please interpret user specified | |
88 | * buffer as "manage_mac_read" response. | |
89 | * Response such as various MAC addresses are stored in HW struct (port.mac) | |
90 | * ice_aq_discover_caps is expected to be called before this function is called. | |
91 | */ | |
92 | static enum ice_status | |
93 | ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, | |
94 | struct ice_sq_cd *cd) | |
95 | { | |
96 | struct ice_aqc_manage_mac_read_resp *resp; | |
97 | struct ice_aqc_manage_mac_read *cmd; | |
98 | struct ice_aq_desc desc; | |
99 | enum ice_status status; | |
100 | u16 flags; | |
d6fef10c | 101 | u8 i; |
dc49c772 AV |
102 | |
103 | cmd = &desc.params.mac_read; | |
104 | ||
105 | if (buf_size < sizeof(*resp)) | |
106 | return ICE_ERR_BUF_TOO_SHORT; | |
107 | ||
108 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); | |
109 | ||
110 | status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); | |
111 | if (status) | |
112 | return status; | |
113 | ||
114 | resp = (struct ice_aqc_manage_mac_read_resp *)buf; | |
115 | flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; | |
116 | ||
117 | if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { | |
118 | ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); | |
119 | return ICE_ERR_CFG; | |
120 | } | |
121 | ||
d6fef10c MFIP |
122 | /* A single port can report up to two (LAN and WoL) addresses */ |
123 | for (i = 0; i < cmd->num_addr; i++) | |
124 | if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { | |
125 | ether_addr_copy(hw->port_info->mac.lan_addr, | |
126 | resp[i].mac_addr); | |
127 | ether_addr_copy(hw->port_info->mac.perm_addr, | |
128 | resp[i].mac_addr); | |
129 | break; | |
130 | } | |
131 | ||
dc49c772 AV |
132 | return 0; |
133 | } | |
134 | ||
135 | /** | |
136 | * ice_aq_get_phy_caps - returns PHY capabilities | |
137 | * @pi: port information structure | |
138 | * @qual_mods: report qualified modules | |
139 | * @report_mode: report mode capabilities | |
140 | * @pcaps: structure for PHY capabilities to be filled | |
141 | * @cd: pointer to command details structure or NULL | |
142 | * | |
143 | * Returns the various PHY capabilities supported on the Port (0x0600) | |
144 | */ | |
48cb27f2 | 145 | enum ice_status |
dc49c772 AV |
146 | ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, |
147 | struct ice_aqc_get_phy_caps_data *pcaps, | |
148 | struct ice_sq_cd *cd) | |
149 | { | |
150 | struct ice_aqc_get_phy_caps *cmd; | |
151 | u16 pcaps_size = sizeof(*pcaps); | |
152 | struct ice_aq_desc desc; | |
153 | enum ice_status status; | |
154 | ||
155 | cmd = &desc.params.get_phy; | |
156 | ||
157 | if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) | |
158 | return ICE_ERR_PARAM; | |
159 | ||
160 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); | |
161 | ||
162 | if (qual_mods) | |
163 | cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); | |
164 | ||
165 | cmd->param0 |= cpu_to_le16(report_mode); | |
166 | status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); | |
167 | ||
aef74145 | 168 | if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { |
dc49c772 | 169 | pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); |
aef74145 AV |
170 | pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); |
171 | } | |
dc49c772 AV |
172 | |
173 | return status; | |
174 | } | |
175 | ||
176 | /** | |
177 | * ice_get_media_type - Gets media type | |
178 | * @pi: port information structure | |
179 | */ | |
180 | static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) | |
181 | { | |
182 | struct ice_link_status *hw_link_info; | |
183 | ||
184 | if (!pi) | |
185 | return ICE_MEDIA_UNKNOWN; | |
186 | ||
187 | hw_link_info = &pi->phy.link_info; | |
aef74145 AV |
188 | if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) |
189 | /* If more than one media type is selected, report unknown */ | |
190 | return ICE_MEDIA_UNKNOWN; | |
dc49c772 AV |
191 | |
192 | if (hw_link_info->phy_type_low) { | |
193 | switch (hw_link_info->phy_type_low) { | |
194 | case ICE_PHY_TYPE_LOW_1000BASE_SX: | |
195 | case ICE_PHY_TYPE_LOW_1000BASE_LX: | |
196 | case ICE_PHY_TYPE_LOW_10GBASE_SR: | |
197 | case ICE_PHY_TYPE_LOW_10GBASE_LR: | |
198 | case ICE_PHY_TYPE_LOW_10G_SFI_C2C: | |
199 | case ICE_PHY_TYPE_LOW_25GBASE_SR: | |
200 | case ICE_PHY_TYPE_LOW_25GBASE_LR: | |
201 | case ICE_PHY_TYPE_LOW_25G_AUI_C2C: | |
202 | case ICE_PHY_TYPE_LOW_40GBASE_SR4: | |
203 | case ICE_PHY_TYPE_LOW_40GBASE_LR4: | |
aef74145 AV |
204 | case ICE_PHY_TYPE_LOW_50GBASE_SR2: |
205 | case ICE_PHY_TYPE_LOW_50GBASE_LR2: | |
206 | case ICE_PHY_TYPE_LOW_50GBASE_SR: | |
207 | case ICE_PHY_TYPE_LOW_50GBASE_FR: | |
208 | case ICE_PHY_TYPE_LOW_50GBASE_LR: | |
209 | case ICE_PHY_TYPE_LOW_100GBASE_SR4: | |
210 | case ICE_PHY_TYPE_LOW_100GBASE_LR4: | |
211 | case ICE_PHY_TYPE_LOW_100GBASE_SR2: | |
212 | case ICE_PHY_TYPE_LOW_100GBASE_DR: | |
dc49c772 AV |
213 | return ICE_MEDIA_FIBER; |
214 | case ICE_PHY_TYPE_LOW_100BASE_TX: | |
215 | case ICE_PHY_TYPE_LOW_1000BASE_T: | |
216 | case ICE_PHY_TYPE_LOW_2500BASE_T: | |
217 | case ICE_PHY_TYPE_LOW_5GBASE_T: | |
218 | case ICE_PHY_TYPE_LOW_10GBASE_T: | |
219 | case ICE_PHY_TYPE_LOW_25GBASE_T: | |
220 | return ICE_MEDIA_BASET; | |
221 | case ICE_PHY_TYPE_LOW_10G_SFI_DA: | |
222 | case ICE_PHY_TYPE_LOW_25GBASE_CR: | |
223 | case ICE_PHY_TYPE_LOW_25GBASE_CR_S: | |
224 | case ICE_PHY_TYPE_LOW_25GBASE_CR1: | |
225 | case ICE_PHY_TYPE_LOW_40GBASE_CR4: | |
aef74145 AV |
226 | case ICE_PHY_TYPE_LOW_50GBASE_CR2: |
227 | case ICE_PHY_TYPE_LOW_50GBASE_CP: | |
228 | case ICE_PHY_TYPE_LOW_100GBASE_CR4: | |
229 | case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: | |
230 | case ICE_PHY_TYPE_LOW_100GBASE_CP2: | |
dc49c772 AV |
231 | return ICE_MEDIA_DA; |
232 | case ICE_PHY_TYPE_LOW_1000BASE_KX: | |
233 | case ICE_PHY_TYPE_LOW_2500BASE_KX: | |
234 | case ICE_PHY_TYPE_LOW_2500BASE_X: | |
235 | case ICE_PHY_TYPE_LOW_5GBASE_KR: | |
236 | case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: | |
237 | case ICE_PHY_TYPE_LOW_25GBASE_KR: | |
238 | case ICE_PHY_TYPE_LOW_25GBASE_KR1: | |
239 | case ICE_PHY_TYPE_LOW_25GBASE_KR_S: | |
240 | case ICE_PHY_TYPE_LOW_40GBASE_KR4: | |
aef74145 AV |
241 | case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: |
242 | case ICE_PHY_TYPE_LOW_50GBASE_KR2: | |
243 | case ICE_PHY_TYPE_LOW_100GBASE_KR4: | |
244 | case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: | |
245 | return ICE_MEDIA_BACKPLANE; | |
246 | } | |
247 | } else { | |
248 | switch (hw_link_info->phy_type_high) { | |
249 | case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: | |
dc49c772 AV |
250 | return ICE_MEDIA_BACKPLANE; |
251 | } | |
252 | } | |
dc49c772 AV |
253 | return ICE_MEDIA_UNKNOWN; |
254 | } | |
255 | ||
256 | /** | |
257 | * ice_aq_get_link_info | |
258 | * @pi: port information structure | |
259 | * @ena_lse: enable/disable LinkStatusEvent reporting | |
260 | * @link: pointer to link status structure - optional | |
261 | * @cd: pointer to command details structure or NULL | |
262 | * | |
263 | * Get Link Status (0x607). Returns the link status of the adapter. | |
264 | */ | |
4f4be03b | 265 | static enum ice_status |
dc49c772 AV |
266 | ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, |
267 | struct ice_link_status *link, struct ice_sq_cd *cd) | |
268 | { | |
269 | struct ice_link_status *hw_link_info_old, *hw_link_info; | |
270 | struct ice_aqc_get_link_status_data link_data = { 0 }; | |
271 | struct ice_aqc_get_link_status *resp; | |
272 | enum ice_media_type *hw_media_type; | |
273 | struct ice_fc_info *hw_fc_info; | |
274 | bool tx_pause, rx_pause; | |
275 | struct ice_aq_desc desc; | |
276 | enum ice_status status; | |
277 | u16 cmd_flags; | |
278 | ||
279 | if (!pi) | |
280 | return ICE_ERR_PARAM; | |
281 | hw_link_info_old = &pi->phy.link_info_old; | |
282 | hw_media_type = &pi->phy.media_type; | |
283 | hw_link_info = &pi->phy.link_info; | |
284 | hw_fc_info = &pi->fc; | |
285 | ||
286 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); | |
287 | cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; | |
288 | resp = &desc.params.get_link_status; | |
289 | resp->cmd_flags = cpu_to_le16(cmd_flags); | |
290 | resp->lport_num = pi->lport; | |
291 | ||
292 | status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data), | |
293 | cd); | |
294 | ||
295 | if (status) | |
296 | return status; | |
297 | ||
298 | /* save off old link status information */ | |
299 | *hw_link_info_old = *hw_link_info; | |
300 | ||
301 | /* update current link status information */ | |
302 | hw_link_info->link_speed = le16_to_cpu(link_data.link_speed); | |
303 | hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low); | |
aef74145 | 304 | hw_link_info->phy_type_high = le64_to_cpu(link_data.phy_type_high); |
dc49c772 AV |
305 | *hw_media_type = ice_get_media_type(pi); |
306 | hw_link_info->link_info = link_data.link_info; | |
307 | hw_link_info->an_info = link_data.an_info; | |
308 | hw_link_info->ext_info = link_data.ext_info; | |
309 | hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size); | |
310 | hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M; | |
311 | ||
312 | /* update fc info */ | |
313 | tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); | |
314 | rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); | |
315 | if (tx_pause && rx_pause) | |
316 | hw_fc_info->current_mode = ICE_FC_FULL; | |
317 | else if (tx_pause) | |
318 | hw_fc_info->current_mode = ICE_FC_TX_PAUSE; | |
319 | else if (rx_pause) | |
320 | hw_fc_info->current_mode = ICE_FC_RX_PAUSE; | |
321 | else | |
322 | hw_fc_info->current_mode = ICE_FC_NONE; | |
323 | ||
324 | hw_link_info->lse_ena = | |
325 | !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); | |
326 | ||
327 | /* save link status information */ | |
328 | if (link) | |
329 | *link = *hw_link_info; | |
330 | ||
331 | /* flag cleared so calling functions don't call AQ again */ | |
332 | pi->phy.get_link_info = false; | |
333 | ||
334 | return status; | |
335 | } | |
336 | ||
cdedef59 | 337 | /** |
22ef683b | 338 | * ice_init_flex_flags |
cdedef59 | 339 | * @hw: pointer to the hardware structure |
22ef683b | 340 | * @prof_id: Rx Descriptor Builder profile ID |
cdedef59 | 341 | * |
22ef683b | 342 | * Function to initialize Rx flex flags |
cdedef59 | 343 | */ |
22ef683b | 344 | static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id) |
cdedef59 AV |
345 | { |
346 | u8 idx = 0; | |
347 | ||
22ef683b AV |
348 | /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout: |
349 | * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE | |
350 | * flexiflags1[3:0] - Not used for flag programming | |
351 | * flexiflags2[7:0] - Tunnel and VLAN types | |
352 | * 2 invalid fields in last index | |
353 | */ | |
354 | switch (prof_id) { | |
355 | /* Rx flex flags are currently programmed for the NIC profiles only. | |
356 | * Different flag bit programming configurations can be added per | |
357 | * profile as needed. | |
358 | */ | |
359 | case ICE_RXDID_FLEX_NIC: | |
360 | case ICE_RXDID_FLEX_NIC_2: | |
361 | ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG, | |
362 | ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI, | |
363 | ICE_RXFLG_FIN, idx++); | |
364 | /* flex flag 1 is not used for flexi-flag programming, skipping | |
365 | * these four FLG64 bits. | |
366 | */ | |
367 | ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST, | |
368 | ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++); | |
369 | ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI, | |
370 | ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100, | |
371 | ICE_RXFLG_EVLAN_x9100, idx++); | |
372 | ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100, | |
373 | ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC, | |
374 | ICE_RXFLG_TNL0, idx++); | |
375 | ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2, | |
376 | ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx); | |
377 | break; | |
378 | ||
379 | default: | |
380 | ice_debug(hw, ICE_DBG_INIT, | |
381 | "Flag programming for profile ID %d not supported\n", | |
382 | prof_id); | |
383 | } | |
384 | } | |
385 | ||
386 | /** | |
387 | * ice_init_flex_flds | |
388 | * @hw: pointer to the hardware structure | |
389 | * @prof_id: Rx Descriptor Builder profile ID | |
390 | * | |
391 | * Function to initialize flex descriptors | |
392 | */ | |
393 | static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id) | |
394 | { | |
395 | enum ice_flex_rx_mdid mdid; | |
396 | ||
397 | switch (prof_id) { | |
398 | case ICE_RXDID_FLEX_NIC: | |
399 | case ICE_RXDID_FLEX_NIC_2: | |
400 | ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0); | |
401 | ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1); | |
402 | ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2); | |
403 | ||
404 | mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ? | |
405 | ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH; | |
406 | ||
407 | ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3); | |
408 | ||
409 | ice_init_flex_flags(hw, prof_id); | |
410 | break; | |
411 | ||
412 | default: | |
413 | ice_debug(hw, ICE_DBG_INIT, | |
414 | "Field init for profile ID %d not supported\n", | |
415 | prof_id); | |
416 | } | |
cdedef59 AV |
417 | } |
418 | ||
9daf8208 AV |
419 | /** |
420 | * ice_init_fltr_mgmt_struct - initializes filter management list and locks | |
421 | * @hw: pointer to the hw struct | |
422 | */ | |
423 | static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) | |
424 | { | |
425 | struct ice_switch_info *sw; | |
426 | ||
427 | hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), | |
428 | sizeof(*hw->switch_info), GFP_KERNEL); | |
429 | sw = hw->switch_info; | |
430 | ||
431 | if (!sw) | |
432 | return ICE_ERR_NO_MEMORY; | |
433 | ||
434 | INIT_LIST_HEAD(&sw->vsi_list_map_head); | |
435 | ||
5fb597d7 | 436 | return ice_init_def_sw_recp(hw); |
9daf8208 AV |
437 | } |
438 | ||
439 | /** | |
440 | * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks | |
441 | * @hw: pointer to the hw struct | |
442 | */ | |
443 | static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) | |
444 | { | |
445 | struct ice_switch_info *sw = hw->switch_info; | |
446 | struct ice_vsi_list_map_info *v_pos_map; | |
447 | struct ice_vsi_list_map_info *v_tmp_map; | |
80d144c9 AV |
448 | struct ice_sw_recipe *recps; |
449 | u8 i; | |
9daf8208 AV |
450 | |
451 | list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, | |
452 | list_entry) { | |
453 | list_del(&v_pos_map->list_entry); | |
454 | devm_kfree(ice_hw_to_dev(hw), v_pos_map); | |
455 | } | |
80d144c9 AV |
456 | recps = hw->switch_info->recp_list; |
457 | for (i = 0; i < ICE_SW_LKUP_LAST; i++) { | |
458 | struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; | |
459 | ||
460 | recps[i].root_rid = i; | |
461 | mutex_destroy(&recps[i].filt_rule_lock); | |
462 | list_for_each_entry_safe(lst_itr, tmp_entry, | |
463 | &recps[i].filt_rules, list_entry) { | |
464 | list_del(&lst_itr->list_entry); | |
465 | devm_kfree(ice_hw_to_dev(hw), lst_itr); | |
466 | } | |
467 | } | |
334cb062 | 468 | ice_rm_all_sw_replay_rule_info(hw); |
80d144c9 | 469 | devm_kfree(ice_hw_to_dev(hw), sw->recp_list); |
9daf8208 AV |
470 | devm_kfree(ice_hw_to_dev(hw), sw); |
471 | } | |
472 | ||
8b97ceb1 HT |
473 | #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \ |
474 | (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry))) | |
475 | #define ICE_FW_LOG_DESC_SIZE_MAX \ | |
476 | ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX) | |
477 | ||
478 | /** | |
479 | * ice_cfg_fw_log - configure FW logging | |
480 | * @hw: pointer to the hw struct | |
481 | * @enable: enable certain FW logging events if true, disable all if false | |
482 | * | |
483 | * This function enables/disables the FW logging via Rx CQ events and a UART | |
484 | * port based on predetermined configurations. FW logging via the Rx CQ can be | |
485 | * enabled/disabled for individual PF's. However, FW logging via the UART can | |
486 | * only be enabled/disabled for all PFs on the same device. | |
487 | * | |
488 | * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in | |
489 | * hw->fw_log need to be set accordingly, e.g. based on user-provided input, | |
490 | * before initializing the device. | |
491 | * | |
492 | * When re/configuring FW logging, callers need to update the "cfg" elements of | |
493 | * the hw->fw_log.evnts array with the desired logging event configurations for | |
494 | * modules of interest. When disabling FW logging completely, the callers can | |
495 | * just pass false in the "enable" parameter. On completion, the function will | |
496 | * update the "cur" element of the hw->fw_log.evnts array with the resulting | |
497 | * logging event configurations of the modules that are being re/configured. FW | |
498 | * logging modules that are not part of a reconfiguration operation retain their | |
499 | * previous states. | |
500 | * | |
501 | * Before resetting the device, it is recommended that the driver disables FW | |
502 | * logging before shutting down the control queue. When disabling FW logging | |
503 | * ("enable" = false), the latest configurations of FW logging events stored in | |
504 | * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after | |
505 | * a device reset. | |
506 | * | |
507 | * When enabling FW logging to emit log messages via the Rx CQ during the | |
508 | * device's initialization phase, a mechanism alternative to interrupt handlers | |
509 | * needs to be used to extract FW log messages from the Rx CQ periodically and | |
510 | * to prevent the Rx CQ from being full and stalling other types of control | |
511 | * messages from FW to SW. Interrupts are typically disabled during the device's | |
512 | * initialization phase. | |
513 | */ | |
514 | static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) | |
515 | { | |
516 | struct ice_aqc_fw_logging_data *data = NULL; | |
517 | struct ice_aqc_fw_logging *cmd; | |
518 | enum ice_status status = 0; | |
519 | u16 i, chgs = 0, len = 0; | |
520 | struct ice_aq_desc desc; | |
521 | u8 actv_evnts = 0; | |
522 | void *buf = NULL; | |
523 | ||
524 | if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) | |
525 | return 0; | |
526 | ||
527 | /* Disable FW logging only when the control queue is still responsive */ | |
528 | if (!enable && | |
529 | (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) | |
530 | return 0; | |
531 | ||
532 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); | |
533 | cmd = &desc.params.fw_logging; | |
534 | ||
535 | /* Indicate which controls are valid */ | |
536 | if (hw->fw_log.cq_en) | |
537 | cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; | |
538 | ||
539 | if (hw->fw_log.uart_en) | |
540 | cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; | |
541 | ||
542 | if (enable) { | |
543 | /* Fill in an array of entries with FW logging modules and | |
544 | * logging events being reconfigured. | |
545 | */ | |
546 | for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { | |
547 | u16 val; | |
548 | ||
549 | /* Keep track of enabled event types */ | |
550 | actv_evnts |= hw->fw_log.evnts[i].cfg; | |
551 | ||
552 | if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) | |
553 | continue; | |
554 | ||
555 | if (!data) { | |
556 | data = devm_kzalloc(ice_hw_to_dev(hw), | |
557 | ICE_FW_LOG_DESC_SIZE_MAX, | |
558 | GFP_KERNEL); | |
559 | if (!data) | |
560 | return ICE_ERR_NO_MEMORY; | |
561 | } | |
562 | ||
563 | val = i << ICE_AQC_FW_LOG_ID_S; | |
564 | val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; | |
565 | data->entry[chgs++] = cpu_to_le16(val); | |
566 | } | |
567 | ||
568 | /* Only enable FW logging if at least one module is specified. | |
569 | * If FW logging is currently enabled but all modules are not | |
570 | * enabled to emit log messages, disable FW logging altogether. | |
571 | */ | |
572 | if (actv_evnts) { | |
573 | /* Leave if there is effectively no change */ | |
574 | if (!chgs) | |
575 | goto out; | |
576 | ||
577 | if (hw->fw_log.cq_en) | |
578 | cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; | |
579 | ||
580 | if (hw->fw_log.uart_en) | |
581 | cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; | |
582 | ||
583 | buf = data; | |
584 | len = ICE_FW_LOG_DESC_SIZE(chgs); | |
585 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
586 | } | |
587 | } | |
588 | ||
589 | status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); | |
590 | if (!status) { | |
591 | /* Update the current configuration to reflect events enabled. | |
592 | * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW | |
593 | * logging mode is enabled for the device. They do not reflect | |
594 | * actual modules being enabled to emit log messages. So, their | |
595 | * values remain unchanged even when all modules are disabled. | |
596 | */ | |
597 | u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; | |
598 | ||
599 | hw->fw_log.actv_evnts = actv_evnts; | |
600 | for (i = 0; i < cnt; i++) { | |
601 | u16 v, m; | |
602 | ||
603 | if (!enable) { | |
604 | /* When disabling all FW logging events as part | |
605 | * of device's de-initialization, the original | |
606 | * configurations are retained, and can be used | |
607 | * to reconfigure FW logging later if the device | |
608 | * is re-initialized. | |
609 | */ | |
610 | hw->fw_log.evnts[i].cur = 0; | |
611 | continue; | |
612 | } | |
613 | ||
614 | v = le16_to_cpu(data->entry[i]); | |
615 | m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; | |
616 | hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; | |
617 | } | |
618 | } | |
619 | ||
620 | out: | |
621 | if (data) | |
622 | devm_kfree(ice_hw_to_dev(hw), data); | |
623 | ||
624 | return status; | |
625 | } | |
626 | ||
627 | /** | |
628 | * ice_output_fw_log | |
629 | * @hw: pointer to the hw struct | |
630 | * @desc: pointer to the AQ message descriptor | |
631 | * @buf: pointer to the buffer accompanying the AQ message | |
632 | * | |
633 | * Formats a FW Log message and outputs it via the standard driver logs. | |
634 | */ | |
635 | void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) | |
636 | { | |
637 | ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n"); | |
638 | ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf, | |
639 | le16_to_cpu(desc->datalen)); | |
640 | ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n"); | |
641 | } | |
642 | ||
9e4ab4c2 BC |
643 | /** |
644 | * ice_get_itr_intrl_gran - determine int/intrl granularity | |
645 | * @hw: pointer to the hw struct | |
646 | * | |
647 | * Determines the itr/intrl granularities based on the maximum aggregate | |
648 | * bandwidth according to the device's configuration during power-on. | |
649 | */ | |
650 | static enum ice_status ice_get_itr_intrl_gran(struct ice_hw *hw) | |
651 | { | |
652 | u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & | |
653 | GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> | |
654 | GL_PWR_MODE_CTL_CAR_MAX_BW_S; | |
655 | ||
656 | switch (max_agg_bw) { | |
657 | case ICE_MAX_AGG_BW_200G: | |
658 | case ICE_MAX_AGG_BW_100G: | |
659 | case ICE_MAX_AGG_BW_50G: | |
660 | hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; | |
661 | hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; | |
662 | break; | |
663 | case ICE_MAX_AGG_BW_25G: | |
664 | hw->itr_gran = ICE_ITR_GRAN_MAX_25; | |
665 | hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; | |
666 | break; | |
667 | default: | |
668 | ice_debug(hw, ICE_DBG_INIT, | |
669 | "Failed to determine itr/intrl granularity\n"); | |
670 | return ICE_ERR_CFG; | |
671 | } | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
f31e4b6f AV |
676 | /** |
677 | * ice_init_hw - main hardware initialization routine | |
678 | * @hw: pointer to the hardware structure | |
679 | */ | |
680 | enum ice_status ice_init_hw(struct ice_hw *hw) | |
681 | { | |
dc49c772 | 682 | struct ice_aqc_get_phy_caps_data *pcaps; |
f31e4b6f | 683 | enum ice_status status; |
dc49c772 AV |
684 | u16 mac_buf_len; |
685 | void *mac_buf; | |
f31e4b6f AV |
686 | |
687 | /* Set MAC type based on DeviceID */ | |
688 | status = ice_set_mac_type(hw); | |
689 | if (status) | |
690 | return status; | |
691 | ||
692 | hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & | |
693 | PF_FUNC_RID_FUNC_NUM_M) >> | |
694 | PF_FUNC_RID_FUNC_NUM_S; | |
695 | ||
696 | status = ice_reset(hw, ICE_RESET_PFR); | |
697 | if (status) | |
698 | return status; | |
699 | ||
9e4ab4c2 BC |
700 | status = ice_get_itr_intrl_gran(hw); |
701 | if (status) | |
702 | return status; | |
940b61af | 703 | |
f31e4b6f AV |
704 | status = ice_init_all_ctrlq(hw); |
705 | if (status) | |
706 | goto err_unroll_cqinit; | |
707 | ||
8b97ceb1 HT |
708 | /* Enable FW logging. Not fatal if this fails. */ |
709 | status = ice_cfg_fw_log(hw, true); | |
710 | if (status) | |
711 | ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); | |
712 | ||
f31e4b6f AV |
713 | status = ice_clear_pf_cfg(hw); |
714 | if (status) | |
715 | goto err_unroll_cqinit; | |
716 | ||
717 | ice_clear_pxe_mode(hw); | |
718 | ||
719 | status = ice_init_nvm(hw); | |
720 | if (status) | |
721 | goto err_unroll_cqinit; | |
722 | ||
9c20346b AV |
723 | status = ice_get_caps(hw); |
724 | if (status) | |
725 | goto err_unroll_cqinit; | |
726 | ||
727 | hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), | |
728 | sizeof(*hw->port_info), GFP_KERNEL); | |
729 | if (!hw->port_info) { | |
730 | status = ICE_ERR_NO_MEMORY; | |
731 | goto err_unroll_cqinit; | |
732 | } | |
733 | ||
734 | /* set the back pointer to hw */ | |
735 | hw->port_info->hw = hw; | |
736 | ||
737 | /* Initialize port_info struct with switch configuration data */ | |
738 | status = ice_get_initial_sw_cfg(hw); | |
739 | if (status) | |
740 | goto err_unroll_alloc; | |
741 | ||
9daf8208 AV |
742 | hw->evb_veb = true; |
743 | ||
d337f2af | 744 | /* Query the allocated resources for Tx scheduler */ |
9c20346b AV |
745 | status = ice_sched_query_res_alloc(hw); |
746 | if (status) { | |
747 | ice_debug(hw, ICE_DBG_SCHED, | |
748 | "Failed to get scheduler allocated resources\n"); | |
749 | goto err_unroll_alloc; | |
750 | } | |
751 | ||
dc49c772 AV |
752 | /* Initialize port_info struct with scheduler data */ |
753 | status = ice_sched_init_port(hw->port_info); | |
754 | if (status) | |
755 | goto err_unroll_sched; | |
756 | ||
757 | pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); | |
758 | if (!pcaps) { | |
759 | status = ICE_ERR_NO_MEMORY; | |
760 | goto err_unroll_sched; | |
761 | } | |
762 | ||
763 | /* Initialize port_info struct with PHY capabilities */ | |
764 | status = ice_aq_get_phy_caps(hw->port_info, false, | |
765 | ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); | |
766 | devm_kfree(ice_hw_to_dev(hw), pcaps); | |
767 | if (status) | |
768 | goto err_unroll_sched; | |
769 | ||
770 | /* Initialize port_info struct with link information */ | |
771 | status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); | |
772 | if (status) | |
773 | goto err_unroll_sched; | |
774 | ||
b36c598c AV |
775 | /* need a valid SW entry point to build a Tx tree */ |
776 | if (!hw->sw_entry_point_layer) { | |
777 | ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); | |
778 | status = ICE_ERR_CFG; | |
779 | goto err_unroll_sched; | |
780 | } | |
9be1d6f8 | 781 | INIT_LIST_HEAD(&hw->agg_list); |
b36c598c | 782 | |
9daf8208 AV |
783 | status = ice_init_fltr_mgmt_struct(hw); |
784 | if (status) | |
785 | goto err_unroll_sched; | |
786 | ||
f203dca3 AV |
787 | ice_dev_onetime_setup(hw); |
788 | ||
d6fef10c MFIP |
789 | /* Get MAC information */ |
790 | /* A single port can report up to two (LAN and WoL) addresses */ | |
791 | mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, | |
792 | sizeof(struct ice_aqc_manage_mac_read_resp), | |
793 | GFP_KERNEL); | |
794 | mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); | |
dc49c772 | 795 | |
63bb4e1e WY |
796 | if (!mac_buf) { |
797 | status = ICE_ERR_NO_MEMORY; | |
9daf8208 | 798 | goto err_unroll_fltr_mgmt_struct; |
63bb4e1e | 799 | } |
dc49c772 AV |
800 | |
801 | status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); | |
802 | devm_kfree(ice_hw_to_dev(hw), mac_buf); | |
803 | ||
804 | if (status) | |
9daf8208 | 805 | goto err_unroll_fltr_mgmt_struct; |
dc49c772 | 806 | |
22ef683b AV |
807 | ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC); |
808 | ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2); | |
cdedef59 | 809 | |
f31e4b6f AV |
810 | return 0; |
811 | ||
9daf8208 AV |
812 | err_unroll_fltr_mgmt_struct: |
813 | ice_cleanup_fltr_mgmt_struct(hw); | |
dc49c772 AV |
814 | err_unroll_sched: |
815 | ice_sched_cleanup_all(hw); | |
9c20346b AV |
816 | err_unroll_alloc: |
817 | devm_kfree(ice_hw_to_dev(hw), hw->port_info); | |
f31e4b6f AV |
818 | err_unroll_cqinit: |
819 | ice_shutdown_all_ctrlq(hw); | |
820 | return status; | |
821 | } | |
822 | ||
823 | /** | |
824 | * ice_deinit_hw - unroll initialization operations done by ice_init_hw | |
825 | * @hw: pointer to the hardware structure | |
826 | */ | |
827 | void ice_deinit_hw(struct ice_hw *hw) | |
828 | { | |
8b97ceb1 HT |
829 | ice_cleanup_fltr_mgmt_struct(hw); |
830 | ||
9c20346b | 831 | ice_sched_cleanup_all(hw); |
9be1d6f8 | 832 | ice_sched_clear_agg(hw); |
dc49c772 | 833 | |
9c20346b AV |
834 | if (hw->port_info) { |
835 | devm_kfree(ice_hw_to_dev(hw), hw->port_info); | |
836 | hw->port_info = NULL; | |
837 | } | |
9daf8208 | 838 | |
8b97ceb1 HT |
839 | /* Attempt to disable FW logging before shutting down control queues */ |
840 | ice_cfg_fw_log(hw, false); | |
841 | ice_shutdown_all_ctrlq(hw); | |
33e055fc VR |
842 | |
843 | /* Clear VSI contexts if not already cleared */ | |
844 | ice_clear_all_vsi_ctx(hw); | |
f31e4b6f AV |
845 | } |
846 | ||
847 | /** | |
848 | * ice_check_reset - Check to see if a global reset is complete | |
849 | * @hw: pointer to the hardware structure | |
850 | */ | |
851 | enum ice_status ice_check_reset(struct ice_hw *hw) | |
852 | { | |
853 | u32 cnt, reg = 0, grst_delay; | |
854 | ||
855 | /* Poll for Device Active state in case a recent CORER, GLOBR, | |
856 | * or EMPR has occurred. The grst delay value is in 100ms units. | |
857 | * Add 1sec for outstanding AQ commands that can take a long time. | |
858 | */ | |
859 | grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> | |
860 | GLGEN_RSTCTL_GRSTDEL_S) + 10; | |
861 | ||
862 | for (cnt = 0; cnt < grst_delay; cnt++) { | |
863 | mdelay(100); | |
864 | reg = rd32(hw, GLGEN_RSTAT); | |
865 | if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) | |
866 | break; | |
867 | } | |
868 | ||
869 | if (cnt == grst_delay) { | |
870 | ice_debug(hw, ICE_DBG_INIT, | |
871 | "Global reset polling failed to complete.\n"); | |
872 | return ICE_ERR_RESET_FAILED; | |
873 | } | |
874 | ||
875 | #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ | |
876 | GLNVM_ULD_GLOBR_DONE_M) | |
877 | ||
878 | /* Device is Active; check Global Reset processes are done */ | |
879 | for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { | |
880 | reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; | |
881 | if (reg == ICE_RESET_DONE_MASK) { | |
882 | ice_debug(hw, ICE_DBG_INIT, | |
883 | "Global reset processes done. %d\n", cnt); | |
884 | break; | |
885 | } | |
886 | mdelay(10); | |
887 | } | |
888 | ||
889 | if (cnt == ICE_PF_RESET_WAIT_COUNT) { | |
890 | ice_debug(hw, ICE_DBG_INIT, | |
891 | "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", | |
892 | reg); | |
893 | return ICE_ERR_RESET_FAILED; | |
894 | } | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | /** | |
900 | * ice_pf_reset - Reset the PF | |
901 | * @hw: pointer to the hardware structure | |
902 | * | |
903 | * If a global reset has been triggered, this function checks | |
904 | * for its completion and then issues the PF reset | |
905 | */ | |
906 | static enum ice_status ice_pf_reset(struct ice_hw *hw) | |
907 | { | |
908 | u32 cnt, reg; | |
909 | ||
910 | /* If at function entry a global reset was already in progress, i.e. | |
911 | * state is not 'device active' or any of the reset done bits are not | |
912 | * set in GLNVM_ULD, there is no need for a PF Reset; poll until the | |
913 | * global reset is done. | |
914 | */ | |
915 | if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || | |
916 | (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { | |
917 | /* poll on global reset currently in progress until done */ | |
918 | if (ice_check_reset(hw)) | |
919 | return ICE_ERR_RESET_FAILED; | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | /* Reset the PF */ | |
925 | reg = rd32(hw, PFGEN_CTRL); | |
926 | ||
927 | wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); | |
928 | ||
929 | for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { | |
930 | reg = rd32(hw, PFGEN_CTRL); | |
931 | if (!(reg & PFGEN_CTRL_PFSWR_M)) | |
932 | break; | |
933 | ||
934 | mdelay(1); | |
935 | } | |
936 | ||
937 | if (cnt == ICE_PF_RESET_WAIT_COUNT) { | |
938 | ice_debug(hw, ICE_DBG_INIT, | |
939 | "PF reset polling failed to complete.\n"); | |
940 | return ICE_ERR_RESET_FAILED; | |
941 | } | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | /** | |
947 | * ice_reset - Perform different types of reset | |
948 | * @hw: pointer to the hardware structure | |
949 | * @req: reset request | |
950 | * | |
951 | * This function triggers a reset as specified by the req parameter. | |
952 | * | |
953 | * Note: | |
954 | * If anything other than a PF reset is triggered, PXE mode is restored. | |
955 | * This has to be cleared using ice_clear_pxe_mode again, once the AQ | |
956 | * interface has been restored in the rebuild flow. | |
957 | */ | |
958 | enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) | |
959 | { | |
960 | u32 val = 0; | |
961 | ||
962 | switch (req) { | |
963 | case ICE_RESET_PFR: | |
964 | return ice_pf_reset(hw); | |
965 | case ICE_RESET_CORER: | |
966 | ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); | |
967 | val = GLGEN_RTRIG_CORER_M; | |
968 | break; | |
969 | case ICE_RESET_GLOBR: | |
970 | ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); | |
971 | val = GLGEN_RTRIG_GLOBR_M; | |
972 | break; | |
0f9d5027 AV |
973 | default: |
974 | return ICE_ERR_PARAM; | |
f31e4b6f AV |
975 | } |
976 | ||
977 | val |= rd32(hw, GLGEN_RTRIG); | |
978 | wr32(hw, GLGEN_RTRIG, val); | |
979 | ice_flush(hw); | |
980 | ||
981 | /* wait for the FW to be ready */ | |
982 | return ice_check_reset(hw); | |
983 | } | |
984 | ||
cdedef59 AV |
985 | /** |
986 | * ice_copy_rxq_ctx_to_hw | |
987 | * @hw: pointer to the hardware structure | |
988 | * @ice_rxq_ctx: pointer to the rxq context | |
d337f2af | 989 | * @rxq_index: the index of the Rx queue |
cdedef59 AV |
990 | * |
991 | * Copies rxq context from dense structure to hw register space | |
992 | */ | |
993 | static enum ice_status | |
994 | ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) | |
995 | { | |
996 | u8 i; | |
997 | ||
998 | if (!ice_rxq_ctx) | |
999 | return ICE_ERR_BAD_PTR; | |
1000 | ||
1001 | if (rxq_index > QRX_CTRL_MAX_INDEX) | |
1002 | return ICE_ERR_PARAM; | |
1003 | ||
1004 | /* Copy each dword separately to hw */ | |
1005 | for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { | |
1006 | wr32(hw, QRX_CONTEXT(i, rxq_index), | |
1007 | *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); | |
1008 | ||
1009 | ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, | |
1010 | *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); | |
1011 | } | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | /* LAN Rx Queue Context */ | |
1017 | static const struct ice_ctx_ele ice_rlan_ctx_info[] = { | |
1018 | /* Field Width LSB */ | |
1019 | ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), | |
1020 | ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), | |
1021 | ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), | |
1022 | ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), | |
1023 | ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), | |
1024 | ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), | |
1025 | ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), | |
1026 | ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), | |
1027 | ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), | |
1028 | ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), | |
1029 | ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), | |
1030 | ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), | |
1031 | ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), | |
1032 | ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), | |
1033 | ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), | |
1034 | ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), | |
1035 | ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), | |
1036 | ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), | |
1037 | ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), | |
1038 | { 0 } | |
1039 | }; | |
1040 | ||
1041 | /** | |
1042 | * ice_write_rxq_ctx | |
1043 | * @hw: pointer to the hardware structure | |
1044 | * @rlan_ctx: pointer to the rxq context | |
d337f2af | 1045 | * @rxq_index: the index of the Rx queue |
cdedef59 AV |
1046 | * |
1047 | * Converts rxq context from sparse to dense structure and then writes | |
1048 | * it to hw register space | |
1049 | */ | |
1050 | enum ice_status | |
1051 | ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, | |
1052 | u32 rxq_index) | |
1053 | { | |
1054 | u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; | |
1055 | ||
1056 | ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); | |
1057 | return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); | |
1058 | } | |
1059 | ||
1060 | /* LAN Tx Queue Context */ | |
1061 | const struct ice_ctx_ele ice_tlan_ctx_info[] = { | |
1062 | /* Field Width LSB */ | |
1063 | ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), | |
1064 | ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), | |
1065 | ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), | |
1066 | ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), | |
1067 | ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), | |
1068 | ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), | |
1069 | ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), | |
1070 | ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), | |
1071 | ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), | |
1072 | ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), | |
1073 | ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), | |
1074 | ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), | |
1075 | ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), | |
1076 | ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), | |
1077 | ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), | |
1078 | ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), | |
1079 | ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), | |
1080 | ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), | |
1081 | ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), | |
1082 | ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), | |
1083 | ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), | |
1084 | ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), | |
1085 | ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), | |
1086 | ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), | |
1087 | ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), | |
1088 | ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), | |
1089 | ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171), | |
1090 | { 0 } | |
1091 | }; | |
1092 | ||
7ec59eea AV |
1093 | /** |
1094 | * ice_debug_cq | |
1095 | * @hw: pointer to the hardware structure | |
1096 | * @mask: debug mask | |
1097 | * @desc: pointer to control queue descriptor | |
1098 | * @buf: pointer to command buffer | |
1099 | * @buf_len: max length of buf | |
1100 | * | |
1101 | * Dumps debug log about control command with descriptor contents. | |
1102 | */ | |
1103 | void ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, | |
1104 | void *buf, u16 buf_len) | |
1105 | { | |
1106 | struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; | |
1107 | u16 len; | |
1108 | ||
1109 | #ifndef CONFIG_DYNAMIC_DEBUG | |
1110 | if (!(mask & hw->debug_mask)) | |
1111 | return; | |
1112 | #endif | |
1113 | ||
1114 | if (!desc) | |
1115 | return; | |
1116 | ||
1117 | len = le16_to_cpu(cq_desc->datalen); | |
1118 | ||
1119 | ice_debug(hw, mask, | |
1120 | "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", | |
1121 | le16_to_cpu(cq_desc->opcode), | |
1122 | le16_to_cpu(cq_desc->flags), | |
1123 | le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval)); | |
1124 | ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", | |
1125 | le32_to_cpu(cq_desc->cookie_high), | |
1126 | le32_to_cpu(cq_desc->cookie_low)); | |
1127 | ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", | |
1128 | le32_to_cpu(cq_desc->params.generic.param0), | |
1129 | le32_to_cpu(cq_desc->params.generic.param1)); | |
1130 | ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", | |
1131 | le32_to_cpu(cq_desc->params.generic.addr_high), | |
1132 | le32_to_cpu(cq_desc->params.generic.addr_low)); | |
1133 | if (buf && cq_desc->datalen != 0) { | |
1134 | ice_debug(hw, mask, "Buffer:\n"); | |
1135 | if (buf_len < len) | |
1136 | len = buf_len; | |
1137 | ||
1138 | ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); | |
1139 | } | |
1140 | } | |
1141 | ||
1142 | /* FW Admin Queue command wrappers */ | |
1143 | ||
1144 | /** | |
1145 | * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue | |
1146 | * @hw: pointer to the hw struct | |
1147 | * @desc: descriptor describing the command | |
1148 | * @buf: buffer to use for indirect commands (NULL for direct commands) | |
1149 | * @buf_size: size of buffer for indirect commands (0 for direct commands) | |
1150 | * @cd: pointer to command details structure | |
1151 | * | |
1152 | * Helper function to send FW Admin Queue commands to the FW Admin Queue. | |
1153 | */ | |
1154 | enum ice_status | |
1155 | ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, | |
1156 | u16 buf_size, struct ice_sq_cd *cd) | |
1157 | { | |
1158 | return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); | |
1159 | } | |
1160 | ||
1161 | /** | |
1162 | * ice_aq_get_fw_ver | |
1163 | * @hw: pointer to the hw struct | |
1164 | * @cd: pointer to command details structure or NULL | |
1165 | * | |
1166 | * Get the firmware version (0x0001) from the admin queue commands | |
1167 | */ | |
1168 | enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) | |
1169 | { | |
1170 | struct ice_aqc_get_ver *resp; | |
1171 | struct ice_aq_desc desc; | |
1172 | enum ice_status status; | |
1173 | ||
1174 | resp = &desc.params.get_ver; | |
1175 | ||
1176 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); | |
1177 | ||
1178 | status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
1179 | ||
1180 | if (!status) { | |
1181 | hw->fw_branch = resp->fw_branch; | |
1182 | hw->fw_maj_ver = resp->fw_major; | |
1183 | hw->fw_min_ver = resp->fw_minor; | |
1184 | hw->fw_patch = resp->fw_patch; | |
1185 | hw->fw_build = le32_to_cpu(resp->fw_build); | |
1186 | hw->api_branch = resp->api_branch; | |
1187 | hw->api_maj_ver = resp->api_major; | |
1188 | hw->api_min_ver = resp->api_minor; | |
1189 | hw->api_patch = resp->api_patch; | |
1190 | } | |
1191 | ||
1192 | return status; | |
1193 | } | |
1194 | ||
1195 | /** | |
1196 | * ice_aq_q_shutdown | |
1197 | * @hw: pointer to the hw struct | |
1198 | * @unloading: is the driver unloading itself | |
1199 | * | |
1200 | * Tell the Firmware that we're shutting down the AdminQ and whether | |
1201 | * or not the driver is unloading as well (0x0003). | |
1202 | */ | |
1203 | enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) | |
1204 | { | |
1205 | struct ice_aqc_q_shutdown *cmd; | |
1206 | struct ice_aq_desc desc; | |
1207 | ||
1208 | cmd = &desc.params.q_shutdown; | |
1209 | ||
1210 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); | |
1211 | ||
1212 | if (unloading) | |
1213 | cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING); | |
1214 | ||
1215 | return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); | |
1216 | } | |
f31e4b6f AV |
1217 | |
1218 | /** | |
1219 | * ice_aq_req_res | |
1220 | * @hw: pointer to the hw struct | |
1221 | * @res: resource id | |
1222 | * @access: access type | |
1223 | * @sdp_number: resource number | |
1224 | * @timeout: the maximum time in ms that the driver may hold the resource | |
1225 | * @cd: pointer to command details structure or NULL | |
1226 | * | |
ff2b1321 DN |
1227 | * Requests common resource using the admin queue commands (0x0008). |
1228 | * When attempting to acquire the Global Config Lock, the driver can | |
1229 | * learn of three states: | |
1230 | * 1) ICE_SUCCESS - acquired lock, and can perform download package | |
1231 | * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load | |
1232 | * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has | |
1233 | * successfully downloaded the package; the driver does | |
1234 | * not have to download the package and can continue | |
1235 | * loading | |
1236 | * | |
1237 | * Note that if the caller is in an acquire lock, perform action, release lock | |
1238 | * phase of operation, it is possible that the FW may detect a timeout and issue | |
1239 | * a CORER. In this case, the driver will receive a CORER interrupt and will | |
1240 | * have to determine its cause. The calling thread that is handling this flow | |
1241 | * will likely get an error propagated back to it indicating the Download | |
1242 | * Package, Update Package or the Release Resource AQ commands timed out. | |
f31e4b6f AV |
1243 | */ |
1244 | static enum ice_status | |
1245 | ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, | |
1246 | enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, | |
1247 | struct ice_sq_cd *cd) | |
1248 | { | |
1249 | struct ice_aqc_req_res *cmd_resp; | |
1250 | struct ice_aq_desc desc; | |
1251 | enum ice_status status; | |
1252 | ||
1253 | cmd_resp = &desc.params.res_owner; | |
1254 | ||
1255 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); | |
1256 | ||
1257 | cmd_resp->res_id = cpu_to_le16(res); | |
1258 | cmd_resp->access_type = cpu_to_le16(access); | |
1259 | cmd_resp->res_number = cpu_to_le32(sdp_number); | |
ff2b1321 DN |
1260 | cmd_resp->timeout = cpu_to_le32(*timeout); |
1261 | *timeout = 0; | |
f31e4b6f AV |
1262 | |
1263 | status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
ff2b1321 | 1264 | |
f31e4b6f AV |
1265 | /* The completion specifies the maximum time in ms that the driver |
1266 | * may hold the resource in the Timeout field. | |
ff2b1321 DN |
1267 | */ |
1268 | ||
1269 | /* Global config lock response utilizes an additional status field. | |
1270 | * | |
1271 | * If the Global config lock resource is held by some other driver, the | |
1272 | * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field | |
1273 | * and the timeout field indicates the maximum time the current owner | |
1274 | * of the resource has to free it. | |
1275 | */ | |
1276 | if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { | |
1277 | if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { | |
1278 | *timeout = le32_to_cpu(cmd_resp->timeout); | |
1279 | return 0; | |
1280 | } else if (le16_to_cpu(cmd_resp->status) == | |
1281 | ICE_AQ_RES_GLBL_IN_PROG) { | |
1282 | *timeout = le32_to_cpu(cmd_resp->timeout); | |
1283 | return ICE_ERR_AQ_ERROR; | |
1284 | } else if (le16_to_cpu(cmd_resp->status) == | |
1285 | ICE_AQ_RES_GLBL_DONE) { | |
1286 | return ICE_ERR_AQ_NO_WORK; | |
1287 | } | |
1288 | ||
1289 | /* invalid FW response, force a timeout immediately */ | |
1290 | *timeout = 0; | |
1291 | return ICE_ERR_AQ_ERROR; | |
1292 | } | |
1293 | ||
1294 | /* If the resource is held by some other driver, the command completes | |
1295 | * with a busy return value and the timeout field indicates the maximum | |
1296 | * time the current owner of the resource has to free it. | |
f31e4b6f AV |
1297 | */ |
1298 | if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) | |
1299 | *timeout = le32_to_cpu(cmd_resp->timeout); | |
1300 | ||
1301 | return status; | |
1302 | } | |
1303 | ||
1304 | /** | |
1305 | * ice_aq_release_res | |
1306 | * @hw: pointer to the hw struct | |
1307 | * @res: resource id | |
1308 | * @sdp_number: resource number | |
1309 | * @cd: pointer to command details structure or NULL | |
1310 | * | |
1311 | * release common resource using the admin queue commands (0x0009) | |
1312 | */ | |
1313 | static enum ice_status | |
1314 | ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, | |
1315 | struct ice_sq_cd *cd) | |
1316 | { | |
1317 | struct ice_aqc_req_res *cmd; | |
1318 | struct ice_aq_desc desc; | |
1319 | ||
1320 | cmd = &desc.params.res_owner; | |
1321 | ||
1322 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); | |
1323 | ||
1324 | cmd->res_id = cpu_to_le16(res); | |
1325 | cmd->res_number = cpu_to_le32(sdp_number); | |
1326 | ||
1327 | return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
1328 | } | |
1329 | ||
1330 | /** | |
1331 | * ice_acquire_res | |
1332 | * @hw: pointer to the HW structure | |
1333 | * @res: resource id | |
1334 | * @access: access type (read or write) | |
ff2b1321 | 1335 | * @timeout: timeout in milliseconds |
f31e4b6f AV |
1336 | * |
1337 | * This function will attempt to acquire the ownership of a resource. | |
1338 | */ | |
1339 | enum ice_status | |
1340 | ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, | |
ff2b1321 | 1341 | enum ice_aq_res_access_type access, u32 timeout) |
f31e4b6f AV |
1342 | { |
1343 | #define ICE_RES_POLLING_DELAY_MS 10 | |
1344 | u32 delay = ICE_RES_POLLING_DELAY_MS; | |
ff2b1321 | 1345 | u32 time_left = timeout; |
f31e4b6f | 1346 | enum ice_status status; |
f31e4b6f AV |
1347 | |
1348 | status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); | |
1349 | ||
ff2b1321 DN |
1350 | /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has |
1351 | * previously acquired the resource and performed any necessary updates; | |
1352 | * in this case the caller does not obtain the resource and has no | |
1353 | * further work to do. | |
f31e4b6f | 1354 | */ |
ff2b1321 | 1355 | if (status == ICE_ERR_AQ_NO_WORK) |
f31e4b6f | 1356 | goto ice_acquire_res_exit; |
f31e4b6f AV |
1357 | |
1358 | if (status) | |
1359 | ice_debug(hw, ICE_DBG_RES, | |
1360 | "resource %d acquire type %d failed.\n", res, access); | |
1361 | ||
1362 | /* If necessary, poll until the current lock owner timeouts */ | |
1363 | timeout = time_left; | |
1364 | while (status && timeout && time_left) { | |
1365 | mdelay(delay); | |
1366 | timeout = (timeout > delay) ? timeout - delay : 0; | |
1367 | status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); | |
1368 | ||
ff2b1321 | 1369 | if (status == ICE_ERR_AQ_NO_WORK) |
f31e4b6f | 1370 | /* lock free, but no work to do */ |
f31e4b6f | 1371 | break; |
f31e4b6f AV |
1372 | |
1373 | if (!status) | |
1374 | /* lock acquired */ | |
1375 | break; | |
1376 | } | |
1377 | if (status && status != ICE_ERR_AQ_NO_WORK) | |
1378 | ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); | |
1379 | ||
1380 | ice_acquire_res_exit: | |
1381 | if (status == ICE_ERR_AQ_NO_WORK) { | |
1382 | if (access == ICE_RES_WRITE) | |
1383 | ice_debug(hw, ICE_DBG_RES, | |
1384 | "resource indicates no work to do.\n"); | |
1385 | else | |
1386 | ice_debug(hw, ICE_DBG_RES, | |
1387 | "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); | |
1388 | } | |
1389 | return status; | |
1390 | } | |
1391 | ||
1392 | /** | |
1393 | * ice_release_res | |
1394 | * @hw: pointer to the HW structure | |
1395 | * @res: resource id | |
1396 | * | |
1397 | * This function will release a resource using the proper Admin Command. | |
1398 | */ | |
1399 | void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) | |
1400 | { | |
1401 | enum ice_status status; | |
1402 | u32 total_delay = 0; | |
1403 | ||
1404 | status = ice_aq_release_res(hw, res, 0, NULL); | |
1405 | ||
1406 | /* there are some rare cases when trying to release the resource | |
1407 | * results in an admin Q timeout, so handle them correctly | |
1408 | */ | |
1409 | while ((status == ICE_ERR_AQ_TIMEOUT) && | |
1410 | (total_delay < hw->adminq.sq_cmd_timeout)) { | |
1411 | mdelay(1); | |
1412 | status = ice_aq_release_res(hw, res, 0, NULL); | |
1413 | total_delay++; | |
1414 | } | |
1415 | } | |
1416 | ||
995c90f2 AV |
1417 | /** |
1418 | * ice_get_guar_num_vsi - determine number of guar VSI for a PF | |
1419 | * @hw: pointer to the hw structure | |
1420 | * | |
1421 | * Determine the number of valid functions by going through the bitmap returned | |
1422 | * from parsing capabilities and use this to calculate the number of VSI per PF. | |
1423 | */ | |
1424 | static u32 ice_get_guar_num_vsi(struct ice_hw *hw) | |
1425 | { | |
1426 | u8 funcs; | |
1427 | ||
1428 | #define ICE_CAPS_VALID_FUNCS_M 0xFF | |
1429 | funcs = hweight8(hw->dev_caps.common_cap.valid_functions & | |
1430 | ICE_CAPS_VALID_FUNCS_M); | |
1431 | ||
1432 | if (!funcs) | |
1433 | return 0; | |
1434 | ||
1435 | return ICE_MAX_VSI / funcs; | |
1436 | } | |
1437 | ||
9c20346b AV |
1438 | /** |
1439 | * ice_parse_caps - parse function/device capabilities | |
1440 | * @hw: pointer to the hw struct | |
1441 | * @buf: pointer to a buffer containing function/device capability records | |
1442 | * @cap_count: number of capability records in the list | |
1443 | * @opc: type of capabilities list to parse | |
1444 | * | |
1445 | * Helper function to parse function(0x000a)/device(0x000b) capabilities list. | |
1446 | */ | |
1447 | static void | |
1448 | ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, | |
1449 | enum ice_adminq_opc opc) | |
1450 | { | |
1451 | struct ice_aqc_list_caps_elem *cap_resp; | |
1452 | struct ice_hw_func_caps *func_p = NULL; | |
1453 | struct ice_hw_dev_caps *dev_p = NULL; | |
1454 | struct ice_hw_common_caps *caps; | |
1455 | u32 i; | |
1456 | ||
1457 | if (!buf) | |
1458 | return; | |
1459 | ||
1460 | cap_resp = (struct ice_aqc_list_caps_elem *)buf; | |
1461 | ||
1462 | if (opc == ice_aqc_opc_list_dev_caps) { | |
1463 | dev_p = &hw->dev_caps; | |
1464 | caps = &dev_p->common_cap; | |
1465 | } else if (opc == ice_aqc_opc_list_func_caps) { | |
1466 | func_p = &hw->func_caps; | |
1467 | caps = &func_p->common_cap; | |
1468 | } else { | |
1469 | ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); | |
1470 | return; | |
1471 | } | |
1472 | ||
1473 | for (i = 0; caps && i < cap_count; i++, cap_resp++) { | |
1474 | u32 logical_id = le32_to_cpu(cap_resp->logical_id); | |
1475 | u32 phys_id = le32_to_cpu(cap_resp->phys_id); | |
1476 | u32 number = le32_to_cpu(cap_resp->number); | |
1477 | u16 cap = le16_to_cpu(cap_resp->cap); | |
1478 | ||
1479 | switch (cap) { | |
995c90f2 AV |
1480 | case ICE_AQC_CAPS_VALID_FUNCTIONS: |
1481 | caps->valid_functions = number; | |
1482 | ice_debug(hw, ICE_DBG_INIT, | |
1483 | "HW caps: Valid Functions = %d\n", | |
1484 | caps->valid_functions); | |
1485 | break; | |
75d2b253 AV |
1486 | case ICE_AQC_CAPS_SRIOV: |
1487 | caps->sr_iov_1_1 = (number == 1); | |
1488 | ice_debug(hw, ICE_DBG_INIT, | |
1489 | "HW caps: SR-IOV = %d\n", caps->sr_iov_1_1); | |
1490 | break; | |
1491 | case ICE_AQC_CAPS_VF: | |
1492 | if (dev_p) { | |
1493 | dev_p->num_vfs_exposed = number; | |
1494 | ice_debug(hw, ICE_DBG_INIT, | |
1495 | "HW caps: VFs exposed = %d\n", | |
1496 | dev_p->num_vfs_exposed); | |
1497 | } else if (func_p) { | |
1498 | func_p->num_allocd_vfs = number; | |
1499 | func_p->vf_base_id = logical_id; | |
1500 | ice_debug(hw, ICE_DBG_INIT, | |
1501 | "HW caps: VFs allocated = %d\n", | |
1502 | func_p->num_allocd_vfs); | |
1503 | ice_debug(hw, ICE_DBG_INIT, | |
1504 | "HW caps: VF base_id = %d\n", | |
1505 | func_p->vf_base_id); | |
1506 | } | |
1507 | break; | |
9c20346b AV |
1508 | case ICE_AQC_CAPS_VSI: |
1509 | if (dev_p) { | |
1510 | dev_p->num_vsi_allocd_to_host = number; | |
1511 | ice_debug(hw, ICE_DBG_INIT, | |
1512 | "HW caps: Dev.VSI cnt = %d\n", | |
1513 | dev_p->num_vsi_allocd_to_host); | |
1514 | } else if (func_p) { | |
995c90f2 | 1515 | func_p->guar_num_vsi = ice_get_guar_num_vsi(hw); |
9c20346b AV |
1516 | ice_debug(hw, ICE_DBG_INIT, |
1517 | "HW caps: Func.VSI cnt = %d\n", | |
995c90f2 | 1518 | number); |
9c20346b AV |
1519 | } |
1520 | break; | |
1521 | case ICE_AQC_CAPS_RSS: | |
1522 | caps->rss_table_size = number; | |
1523 | caps->rss_table_entry_width = logical_id; | |
1524 | ice_debug(hw, ICE_DBG_INIT, | |
1525 | "HW caps: RSS table size = %d\n", | |
1526 | caps->rss_table_size); | |
1527 | ice_debug(hw, ICE_DBG_INIT, | |
1528 | "HW caps: RSS table width = %d\n", | |
1529 | caps->rss_table_entry_width); | |
1530 | break; | |
1531 | case ICE_AQC_CAPS_RXQS: | |
1532 | caps->num_rxq = number; | |
1533 | caps->rxq_first_id = phys_id; | |
1534 | ice_debug(hw, ICE_DBG_INIT, | |
1535 | "HW caps: Num Rx Qs = %d\n", caps->num_rxq); | |
1536 | ice_debug(hw, ICE_DBG_INIT, | |
1537 | "HW caps: Rx first queue ID = %d\n", | |
1538 | caps->rxq_first_id); | |
1539 | break; | |
1540 | case ICE_AQC_CAPS_TXQS: | |
1541 | caps->num_txq = number; | |
1542 | caps->txq_first_id = phys_id; | |
1543 | ice_debug(hw, ICE_DBG_INIT, | |
1544 | "HW caps: Num Tx Qs = %d\n", caps->num_txq); | |
1545 | ice_debug(hw, ICE_DBG_INIT, | |
1546 | "HW caps: Tx first queue ID = %d\n", | |
1547 | caps->txq_first_id); | |
1548 | break; | |
1549 | case ICE_AQC_CAPS_MSIX: | |
1550 | caps->num_msix_vectors = number; | |
1551 | caps->msix_vector_first_id = phys_id; | |
1552 | ice_debug(hw, ICE_DBG_INIT, | |
1553 | "HW caps: MSIX vector count = %d\n", | |
1554 | caps->num_msix_vectors); | |
1555 | ice_debug(hw, ICE_DBG_INIT, | |
1556 | "HW caps: MSIX first vector index = %d\n", | |
1557 | caps->msix_vector_first_id); | |
1558 | break; | |
1559 | case ICE_AQC_CAPS_MAX_MTU: | |
1560 | caps->max_mtu = number; | |
1561 | if (dev_p) | |
1562 | ice_debug(hw, ICE_DBG_INIT, | |
1563 | "HW caps: Dev.MaxMTU = %d\n", | |
1564 | caps->max_mtu); | |
1565 | else if (func_p) | |
1566 | ice_debug(hw, ICE_DBG_INIT, | |
1567 | "HW caps: func.MaxMTU = %d\n", | |
1568 | caps->max_mtu); | |
1569 | break; | |
1570 | default: | |
1571 | ice_debug(hw, ICE_DBG_INIT, | |
1572 | "HW caps: Unknown capability[%d]: 0x%x\n", i, | |
1573 | cap); | |
1574 | break; | |
1575 | } | |
1576 | } | |
1577 | } | |
1578 | ||
1579 | /** | |
1580 | * ice_aq_discover_caps - query function/device capabilities | |
1581 | * @hw: pointer to the hw struct | |
1582 | * @buf: a virtual buffer to hold the capabilities | |
1583 | * @buf_size: Size of the virtual buffer | |
7d86cf38 | 1584 | * @cap_count: cap count needed if AQ err==ENOMEM |
9c20346b AV |
1585 | * @opc: capabilities type to discover - pass in the command opcode |
1586 | * @cd: pointer to command details structure or NULL | |
1587 | * | |
1588 | * Get the function(0x000a)/device(0x000b) capabilities description from | |
1589 | * the firmware. | |
1590 | */ | |
1591 | static enum ice_status | |
7d86cf38 | 1592 | ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, |
9c20346b AV |
1593 | enum ice_adminq_opc opc, struct ice_sq_cd *cd) |
1594 | { | |
1595 | struct ice_aqc_list_caps *cmd; | |
1596 | struct ice_aq_desc desc; | |
1597 | enum ice_status status; | |
1598 | ||
1599 | cmd = &desc.params.get_cap; | |
1600 | ||
1601 | if (opc != ice_aqc_opc_list_func_caps && | |
1602 | opc != ice_aqc_opc_list_dev_caps) | |
1603 | return ICE_ERR_PARAM; | |
1604 | ||
1605 | ice_fill_dflt_direct_cmd_desc(&desc, opc); | |
1606 | ||
1607 | status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); | |
1608 | if (!status) | |
1609 | ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); | |
7d86cf38 | 1610 | else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) |
99189e8b | 1611 | *cap_count = le32_to_cpu(cmd->count); |
9c20346b AV |
1612 | return status; |
1613 | } | |
1614 | ||
1615 | /** | |
7d86cf38 | 1616 | * ice_discover_caps - get info about the HW |
9c20346b | 1617 | * @hw: pointer to the hardware structure |
7d86cf38 | 1618 | * @opc: capabilities type to discover - pass in the command opcode |
9c20346b | 1619 | */ |
7d86cf38 AV |
1620 | static enum ice_status ice_discover_caps(struct ice_hw *hw, |
1621 | enum ice_adminq_opc opc) | |
9c20346b AV |
1622 | { |
1623 | enum ice_status status; | |
7d86cf38 | 1624 | u32 cap_count; |
9c20346b AV |
1625 | u16 cbuf_len; |
1626 | u8 retries; | |
1627 | ||
1628 | /* The driver doesn't know how many capabilities the device will return | |
1629 | * so the buffer size required isn't known ahead of time. The driver | |
1630 | * starts with cbuf_len and if this turns out to be insufficient, the | |
7d86cf38 AV |
1631 | * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs. |
1632 | * The driver then allocates the buffer based on the count and retries | |
1633 | * the operation. So it follows that the retry count is 2. | |
9c20346b AV |
1634 | */ |
1635 | #define ICE_GET_CAP_BUF_COUNT 40 | |
1636 | #define ICE_GET_CAP_RETRY_COUNT 2 | |
1637 | ||
7d86cf38 | 1638 | cap_count = ICE_GET_CAP_BUF_COUNT; |
9c20346b AV |
1639 | retries = ICE_GET_CAP_RETRY_COUNT; |
1640 | ||
1641 | do { | |
1642 | void *cbuf; | |
1643 | ||
7d86cf38 AV |
1644 | cbuf_len = (u16)(cap_count * |
1645 | sizeof(struct ice_aqc_list_caps_elem)); | |
9c20346b AV |
1646 | cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); |
1647 | if (!cbuf) | |
1648 | return ICE_ERR_NO_MEMORY; | |
1649 | ||
7d86cf38 AV |
1650 | status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count, |
1651 | opc, NULL); | |
9c20346b AV |
1652 | devm_kfree(ice_hw_to_dev(hw), cbuf); |
1653 | ||
1654 | if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) | |
1655 | break; | |
1656 | ||
1657 | /* If ENOMEM is returned, try again with bigger buffer */ | |
9c20346b AV |
1658 | } while (--retries); |
1659 | ||
1660 | return status; | |
1661 | } | |
1662 | ||
7d86cf38 AV |
1663 | /** |
1664 | * ice_get_caps - get info about the HW | |
1665 | * @hw: pointer to the hardware structure | |
1666 | */ | |
1667 | enum ice_status ice_get_caps(struct ice_hw *hw) | |
1668 | { | |
1669 | enum ice_status status; | |
1670 | ||
1671 | status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); | |
1672 | if (!status) | |
1673 | status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); | |
1674 | ||
1675 | return status; | |
1676 | } | |
1677 | ||
e94d4478 AV |
1678 | /** |
1679 | * ice_aq_manage_mac_write - manage MAC address write command | |
1680 | * @hw: pointer to the hw struct | |
1681 | * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address | |
1682 | * @flags: flags to control write behavior | |
1683 | * @cd: pointer to command details structure or NULL | |
1684 | * | |
1685 | * This function is used to write MAC address to the NVM (0x0108). | |
1686 | */ | |
1687 | enum ice_status | |
d671e3e0 | 1688 | ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, |
e94d4478 AV |
1689 | struct ice_sq_cd *cd) |
1690 | { | |
1691 | struct ice_aqc_manage_mac_write *cmd; | |
1692 | struct ice_aq_desc desc; | |
1693 | ||
1694 | cmd = &desc.params.mac_write; | |
1695 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); | |
1696 | ||
1697 | cmd->flags = flags; | |
1698 | ||
1699 | /* Prep values for flags, sah, sal */ | |
d671e3e0 JK |
1700 | cmd->sah = htons(*((const u16 *)mac_addr)); |
1701 | cmd->sal = htonl(*((const u32 *)(mac_addr + 2))); | |
e94d4478 AV |
1702 | |
1703 | return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
1704 | } | |
1705 | ||
f31e4b6f AV |
1706 | /** |
1707 | * ice_aq_clear_pxe_mode | |
1708 | * @hw: pointer to the hw struct | |
1709 | * | |
1710 | * Tell the firmware that the driver is taking over from PXE (0x0110). | |
1711 | */ | |
1712 | static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) | |
1713 | { | |
1714 | struct ice_aq_desc desc; | |
1715 | ||
1716 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); | |
1717 | desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; | |
1718 | ||
1719 | return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); | |
1720 | } | |
1721 | ||
1722 | /** | |
1723 | * ice_clear_pxe_mode - clear pxe operations mode | |
1724 | * @hw: pointer to the hw struct | |
1725 | * | |
1726 | * Make sure all PXE mode settings are cleared, including things | |
1727 | * like descriptor fetch/write-back mode. | |
1728 | */ | |
1729 | void ice_clear_pxe_mode(struct ice_hw *hw) | |
1730 | { | |
1731 | if (ice_check_sq_alive(hw, &hw->adminq)) | |
1732 | ice_aq_clear_pxe_mode(hw); | |
1733 | } | |
cdedef59 | 1734 | |
48cb27f2 CC |
1735 | /** |
1736 | * ice_get_link_speed_based_on_phy_type - returns link speed | |
1737 | * @phy_type_low: lower part of phy_type | |
aef74145 | 1738 | * @phy_type_high: higher part of phy_type |
48cb27f2 | 1739 | * |
aef74145 AV |
1740 | * This helper function will convert an entry in phy type structure |
1741 | * [phy_type_low, phy_type_high] to its corresponding link speed. | |
1742 | * Note: In the structure of [phy_type_low, phy_type_high], there should | |
1743 | * be one bit set, as this function will convert one phy type to its | |
48cb27f2 | 1744 | * speed. |
48cb27f2 CC |
1745 | * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned |
1746 | * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned | |
1747 | */ | |
aef74145 AV |
1748 | static u16 |
1749 | ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) | |
48cb27f2 | 1750 | { |
aef74145 | 1751 | u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; |
48cb27f2 CC |
1752 | u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; |
1753 | ||
1754 | switch (phy_type_low) { | |
1755 | case ICE_PHY_TYPE_LOW_100BASE_TX: | |
1756 | case ICE_PHY_TYPE_LOW_100M_SGMII: | |
1757 | speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; | |
1758 | break; | |
1759 | case ICE_PHY_TYPE_LOW_1000BASE_T: | |
1760 | case ICE_PHY_TYPE_LOW_1000BASE_SX: | |
1761 | case ICE_PHY_TYPE_LOW_1000BASE_LX: | |
1762 | case ICE_PHY_TYPE_LOW_1000BASE_KX: | |
1763 | case ICE_PHY_TYPE_LOW_1G_SGMII: | |
1764 | speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; | |
1765 | break; | |
1766 | case ICE_PHY_TYPE_LOW_2500BASE_T: | |
1767 | case ICE_PHY_TYPE_LOW_2500BASE_X: | |
1768 | case ICE_PHY_TYPE_LOW_2500BASE_KX: | |
1769 | speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; | |
1770 | break; | |
1771 | case ICE_PHY_TYPE_LOW_5GBASE_T: | |
1772 | case ICE_PHY_TYPE_LOW_5GBASE_KR: | |
1773 | speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; | |
1774 | break; | |
1775 | case ICE_PHY_TYPE_LOW_10GBASE_T: | |
1776 | case ICE_PHY_TYPE_LOW_10G_SFI_DA: | |
1777 | case ICE_PHY_TYPE_LOW_10GBASE_SR: | |
1778 | case ICE_PHY_TYPE_LOW_10GBASE_LR: | |
1779 | case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: | |
1780 | case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: | |
1781 | case ICE_PHY_TYPE_LOW_10G_SFI_C2C: | |
1782 | speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; | |
1783 | break; | |
1784 | case ICE_PHY_TYPE_LOW_25GBASE_T: | |
1785 | case ICE_PHY_TYPE_LOW_25GBASE_CR: | |
1786 | case ICE_PHY_TYPE_LOW_25GBASE_CR_S: | |
1787 | case ICE_PHY_TYPE_LOW_25GBASE_CR1: | |
1788 | case ICE_PHY_TYPE_LOW_25GBASE_SR: | |
1789 | case ICE_PHY_TYPE_LOW_25GBASE_LR: | |
1790 | case ICE_PHY_TYPE_LOW_25GBASE_KR: | |
1791 | case ICE_PHY_TYPE_LOW_25GBASE_KR_S: | |
1792 | case ICE_PHY_TYPE_LOW_25GBASE_KR1: | |
1793 | case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: | |
1794 | case ICE_PHY_TYPE_LOW_25G_AUI_C2C: | |
1795 | speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; | |
1796 | break; | |
1797 | case ICE_PHY_TYPE_LOW_40GBASE_CR4: | |
1798 | case ICE_PHY_TYPE_LOW_40GBASE_SR4: | |
1799 | case ICE_PHY_TYPE_LOW_40GBASE_LR4: | |
1800 | case ICE_PHY_TYPE_LOW_40GBASE_KR4: | |
1801 | case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: | |
1802 | case ICE_PHY_TYPE_LOW_40G_XLAUI: | |
1803 | speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; | |
1804 | break; | |
aef74145 AV |
1805 | case ICE_PHY_TYPE_LOW_50GBASE_CR2: |
1806 | case ICE_PHY_TYPE_LOW_50GBASE_SR2: | |
1807 | case ICE_PHY_TYPE_LOW_50GBASE_LR2: | |
1808 | case ICE_PHY_TYPE_LOW_50GBASE_KR2: | |
1809 | case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: | |
1810 | case ICE_PHY_TYPE_LOW_50G_LAUI2: | |
1811 | case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: | |
1812 | case ICE_PHY_TYPE_LOW_50G_AUI2: | |
1813 | case ICE_PHY_TYPE_LOW_50GBASE_CP: | |
1814 | case ICE_PHY_TYPE_LOW_50GBASE_SR: | |
1815 | case ICE_PHY_TYPE_LOW_50GBASE_FR: | |
1816 | case ICE_PHY_TYPE_LOW_50GBASE_LR: | |
1817 | case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: | |
1818 | case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: | |
1819 | case ICE_PHY_TYPE_LOW_50G_AUI1: | |
1820 | speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; | |
1821 | break; | |
1822 | case ICE_PHY_TYPE_LOW_100GBASE_CR4: | |
1823 | case ICE_PHY_TYPE_LOW_100GBASE_SR4: | |
1824 | case ICE_PHY_TYPE_LOW_100GBASE_LR4: | |
1825 | case ICE_PHY_TYPE_LOW_100GBASE_KR4: | |
1826 | case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: | |
1827 | case ICE_PHY_TYPE_LOW_100G_CAUI4: | |
1828 | case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: | |
1829 | case ICE_PHY_TYPE_LOW_100G_AUI4: | |
1830 | case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: | |
1831 | case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: | |
1832 | case ICE_PHY_TYPE_LOW_100GBASE_CP2: | |
1833 | case ICE_PHY_TYPE_LOW_100GBASE_SR2: | |
1834 | case ICE_PHY_TYPE_LOW_100GBASE_DR: | |
1835 | speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; | |
1836 | break; | |
48cb27f2 CC |
1837 | default: |
1838 | speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; | |
1839 | break; | |
1840 | } | |
1841 | ||
aef74145 AV |
1842 | switch (phy_type_high) { |
1843 | case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: | |
1844 | case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: | |
1845 | case ICE_PHY_TYPE_HIGH_100G_CAUI2: | |
1846 | case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: | |
1847 | case ICE_PHY_TYPE_HIGH_100G_AUI2: | |
1848 | speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; | |
1849 | break; | |
1850 | default: | |
1851 | speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; | |
1852 | break; | |
1853 | } | |
1854 | ||
1855 | if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && | |
1856 | speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) | |
1857 | return ICE_AQ_LINK_SPEED_UNKNOWN; | |
1858 | else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && | |
1859 | speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) | |
1860 | return ICE_AQ_LINK_SPEED_UNKNOWN; | |
1861 | else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && | |
1862 | speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) | |
1863 | return speed_phy_type_low; | |
1864 | else | |
1865 | return speed_phy_type_high; | |
48cb27f2 CC |
1866 | } |
1867 | ||
1868 | /** | |
1869 | * ice_update_phy_type | |
1870 | * @phy_type_low: pointer to the lower part of phy_type | |
aef74145 | 1871 | * @phy_type_high: pointer to the higher part of phy_type |
48cb27f2 CC |
1872 | * @link_speeds_bitmap: targeted link speeds bitmap |
1873 | * | |
1874 | * Note: For the link_speeds_bitmap structure, you can check it at | |
1875 | * [ice_aqc_get_link_status->link_speed]. Caller can pass in | |
1876 | * link_speeds_bitmap include multiple speeds. | |
1877 | * | |
aef74145 AV |
1878 | * Each entry in this [phy_type_low, phy_type_high] structure will |
1879 | * present a certain link speed. This helper function will turn on bits | |
1880 | * in [phy_type_low, phy_type_high] structure based on the value of | |
48cb27f2 CC |
1881 | * link_speeds_bitmap input parameter. |
1882 | */ | |
aef74145 AV |
1883 | void |
1884 | ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, | |
1885 | u16 link_speeds_bitmap) | |
48cb27f2 CC |
1886 | { |
1887 | u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN; | |
aef74145 | 1888 | u64 pt_high; |
48cb27f2 CC |
1889 | u64 pt_low; |
1890 | int index; | |
1891 | ||
1892 | /* We first check with low part of phy_type */ | |
1893 | for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { | |
1894 | pt_low = BIT_ULL(index); | |
aef74145 | 1895 | speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); |
48cb27f2 CC |
1896 | |
1897 | if (link_speeds_bitmap & speed) | |
1898 | *phy_type_low |= BIT_ULL(index); | |
1899 | } | |
aef74145 AV |
1900 | |
1901 | /* We then check with high part of phy_type */ | |
1902 | for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { | |
1903 | pt_high = BIT_ULL(index); | |
1904 | speed = ice_get_link_speed_based_on_phy_type(0, pt_high); | |
1905 | ||
1906 | if (link_speeds_bitmap & speed) | |
1907 | *phy_type_high |= BIT_ULL(index); | |
1908 | } | |
48cb27f2 CC |
1909 | } |
1910 | ||
fcea6f3d AV |
1911 | /** |
1912 | * ice_aq_set_phy_cfg | |
1913 | * @hw: pointer to the hw struct | |
1914 | * @lport: logical port number | |
1915 | * @cfg: structure with PHY configuration data to be set | |
1916 | * @cd: pointer to command details structure or NULL | |
1917 | * | |
1918 | * Set the various PHY configuration parameters supported on the Port. | |
1919 | * One or more of the Set PHY config parameters may be ignored in an MFP | |
1920 | * mode as the PF may not have the privilege to set some of the PHY Config | |
1921 | * parameters. This status will be indicated by the command response (0x0601). | |
1922 | */ | |
48cb27f2 | 1923 | enum ice_status |
fcea6f3d AV |
1924 | ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, |
1925 | struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) | |
1926 | { | |
fcea6f3d AV |
1927 | struct ice_aq_desc desc; |
1928 | ||
1929 | if (!cfg) | |
1930 | return ICE_ERR_PARAM; | |
1931 | ||
fcea6f3d | 1932 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); |
48cb27f2 CC |
1933 | desc.params.set_phy.lport_num = lport; |
1934 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
fcea6f3d AV |
1935 | |
1936 | return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); | |
1937 | } | |
1938 | ||
1939 | /** | |
1940 | * ice_update_link_info - update status of the HW network link | |
1941 | * @pi: port info structure of the interested logical port | |
1942 | */ | |
5755143d | 1943 | enum ice_status ice_update_link_info(struct ice_port_info *pi) |
fcea6f3d AV |
1944 | { |
1945 | struct ice_aqc_get_phy_caps_data *pcaps; | |
1946 | struct ice_phy_info *phy_info; | |
1947 | enum ice_status status; | |
1948 | struct ice_hw *hw; | |
1949 | ||
1950 | if (!pi) | |
1951 | return ICE_ERR_PARAM; | |
1952 | ||
1953 | hw = pi->hw; | |
1954 | ||
1955 | pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); | |
1956 | if (!pcaps) | |
1957 | return ICE_ERR_NO_MEMORY; | |
1958 | ||
1959 | phy_info = &pi->phy; | |
1960 | status = ice_aq_get_link_info(pi, true, NULL, NULL); | |
1961 | if (status) | |
1962 | goto out; | |
1963 | ||
1964 | if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) { | |
1965 | status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, | |
1966 | pcaps, NULL); | |
1967 | if (status) | |
1968 | goto out; | |
1969 | ||
1970 | memcpy(phy_info->link_info.module_type, &pcaps->module_type, | |
1971 | sizeof(phy_info->link_info.module_type)); | |
1972 | } | |
1973 | out: | |
1974 | devm_kfree(ice_hw_to_dev(hw), pcaps); | |
1975 | return status; | |
1976 | } | |
1977 | ||
1978 | /** | |
1979 | * ice_set_fc | |
1980 | * @pi: port information structure | |
1981 | * @aq_failures: pointer to status code, specific to ice_set_fc routine | |
48cb27f2 | 1982 | * @ena_auto_link_update: enable automatic link update |
fcea6f3d AV |
1983 | * |
1984 | * Set the requested flow control mode. | |
1985 | */ | |
1986 | enum ice_status | |
48cb27f2 | 1987 | ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) |
fcea6f3d AV |
1988 | { |
1989 | struct ice_aqc_set_phy_cfg_data cfg = { 0 }; | |
1990 | struct ice_aqc_get_phy_caps_data *pcaps; | |
1991 | enum ice_status status; | |
1992 | u8 pause_mask = 0x0; | |
1993 | struct ice_hw *hw; | |
1994 | ||
1995 | if (!pi) | |
1996 | return ICE_ERR_PARAM; | |
1997 | hw = pi->hw; | |
1998 | *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; | |
1999 | ||
2000 | switch (pi->fc.req_mode) { | |
2001 | case ICE_FC_FULL: | |
2002 | pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; | |
2003 | pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; | |
2004 | break; | |
2005 | case ICE_FC_RX_PAUSE: | |
2006 | pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; | |
2007 | break; | |
2008 | case ICE_FC_TX_PAUSE: | |
2009 | pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; | |
2010 | break; | |
2011 | default: | |
2012 | break; | |
2013 | } | |
2014 | ||
2015 | pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); | |
2016 | if (!pcaps) | |
2017 | return ICE_ERR_NO_MEMORY; | |
2018 | ||
2019 | /* Get the current phy config */ | |
2020 | status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, | |
2021 | NULL); | |
2022 | if (status) { | |
2023 | *aq_failures = ICE_SET_FC_AQ_FAIL_GET; | |
2024 | goto out; | |
2025 | } | |
2026 | ||
2027 | /* clear the old pause settings */ | |
2028 | cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | | |
2029 | ICE_AQC_PHY_EN_RX_LINK_PAUSE); | |
2030 | /* set the new capabilities */ | |
2031 | cfg.caps |= pause_mask; | |
2032 | /* If the capabilities have changed, then set the new config */ | |
2033 | if (cfg.caps != pcaps->caps) { | |
2034 | int retry_count, retry_max = 10; | |
2035 | ||
2036 | /* Auto restart link so settings take effect */ | |
48cb27f2 CC |
2037 | if (ena_auto_link_update) |
2038 | cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; | |
fcea6f3d | 2039 | /* Copy over all the old settings */ |
aef74145 | 2040 | cfg.phy_type_high = pcaps->phy_type_high; |
fcea6f3d AV |
2041 | cfg.phy_type_low = pcaps->phy_type_low; |
2042 | cfg.low_power_ctrl = pcaps->low_power_ctrl; | |
2043 | cfg.eee_cap = pcaps->eee_cap; | |
2044 | cfg.eeer_value = pcaps->eeer_value; | |
2045 | cfg.link_fec_opt = pcaps->link_fec_options; | |
2046 | ||
2047 | status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); | |
2048 | if (status) { | |
2049 | *aq_failures = ICE_SET_FC_AQ_FAIL_SET; | |
2050 | goto out; | |
2051 | } | |
2052 | ||
2053 | /* Update the link info | |
2054 | * It sometimes takes a really long time for link to | |
2055 | * come back from the atomic reset. Thus, we wait a | |
2056 | * little bit. | |
2057 | */ | |
2058 | for (retry_count = 0; retry_count < retry_max; retry_count++) { | |
2059 | status = ice_update_link_info(pi); | |
2060 | ||
2061 | if (!status) | |
2062 | break; | |
2063 | ||
2064 | mdelay(100); | |
2065 | } | |
2066 | ||
2067 | if (status) | |
2068 | *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; | |
2069 | } | |
2070 | ||
2071 | out: | |
2072 | devm_kfree(ice_hw_to_dev(hw), pcaps); | |
2073 | return status; | |
2074 | } | |
2075 | ||
0b28b702 AV |
2076 | /** |
2077 | * ice_get_link_status - get status of the HW network link | |
2078 | * @pi: port information structure | |
2079 | * @link_up: pointer to bool (true/false = linkup/linkdown) | |
2080 | * | |
2081 | * Variable link_up is true if link is up, false if link is down. | |
2082 | * The variable link_up is invalid if status is non zero. As a | |
2083 | * result of this call, link status reporting becomes enabled | |
2084 | */ | |
2085 | enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) | |
2086 | { | |
2087 | struct ice_phy_info *phy_info; | |
2088 | enum ice_status status = 0; | |
2089 | ||
c7f2c42b | 2090 | if (!pi || !link_up) |
0b28b702 AV |
2091 | return ICE_ERR_PARAM; |
2092 | ||
2093 | phy_info = &pi->phy; | |
2094 | ||
2095 | if (phy_info->get_link_info) { | |
2096 | status = ice_update_link_info(pi); | |
2097 | ||
2098 | if (status) | |
2099 | ice_debug(pi->hw, ICE_DBG_LINK, | |
2100 | "get link status error, status = %d\n", | |
2101 | status); | |
2102 | } | |
2103 | ||
2104 | *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; | |
2105 | ||
2106 | return status; | |
2107 | } | |
2108 | ||
fcea6f3d AV |
2109 | /** |
2110 | * ice_aq_set_link_restart_an | |
2111 | * @pi: pointer to the port information structure | |
2112 | * @ena_link: if true: enable link, if false: disable link | |
2113 | * @cd: pointer to command details structure or NULL | |
2114 | * | |
2115 | * Sets up the link and restarts the Auto-Negotiation over the link. | |
2116 | */ | |
2117 | enum ice_status | |
2118 | ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, | |
2119 | struct ice_sq_cd *cd) | |
2120 | { | |
2121 | struct ice_aqc_restart_an *cmd; | |
2122 | struct ice_aq_desc desc; | |
2123 | ||
2124 | cmd = &desc.params.restart_an; | |
2125 | ||
2126 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); | |
2127 | ||
2128 | cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; | |
2129 | cmd->lport_num = pi->lport; | |
2130 | if (ena_link) | |
2131 | cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; | |
2132 | else | |
2133 | cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; | |
2134 | ||
2135 | return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); | |
2136 | } | |
2137 | ||
8e151d50 AV |
2138 | /** |
2139 | * ice_aq_set_port_id_led | |
2140 | * @pi: pointer to the port information | |
2141 | * @is_orig_mode: is this LED set to original mode (by the net-list) | |
2142 | * @cd: pointer to command details structure or NULL | |
2143 | * | |
2144 | * Set LED value for the given port (0x06e9) | |
2145 | */ | |
2146 | enum ice_status | |
2147 | ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, | |
2148 | struct ice_sq_cd *cd) | |
2149 | { | |
2150 | struct ice_aqc_set_port_id_led *cmd; | |
2151 | struct ice_hw *hw = pi->hw; | |
2152 | struct ice_aq_desc desc; | |
2153 | ||
2154 | cmd = &desc.params.set_port_id_led; | |
2155 | ||
2156 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); | |
2157 | ||
2158 | if (is_orig_mode) | |
2159 | cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; | |
2160 | else | |
2161 | cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; | |
2162 | ||
2163 | return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
2164 | } | |
2165 | ||
d76a60ba AV |
2166 | /** |
2167 | * __ice_aq_get_set_rss_lut | |
2168 | * @hw: pointer to the hardware structure | |
2169 | * @vsi_id: VSI FW index | |
2170 | * @lut_type: LUT table type | |
2171 | * @lut: pointer to the LUT buffer provided by the caller | |
2172 | * @lut_size: size of the LUT buffer | |
2173 | * @glob_lut_idx: global LUT index | |
2174 | * @set: set true to set the table, false to get the table | |
2175 | * | |
2176 | * Internal function to get (0x0B05) or set (0x0B03) RSS look up table | |
2177 | */ | |
2178 | static enum ice_status | |
2179 | __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, | |
2180 | u16 lut_size, u8 glob_lut_idx, bool set) | |
2181 | { | |
2182 | struct ice_aqc_get_set_rss_lut *cmd_resp; | |
2183 | struct ice_aq_desc desc; | |
2184 | enum ice_status status; | |
2185 | u16 flags = 0; | |
2186 | ||
2187 | cmd_resp = &desc.params.get_set_rss_lut; | |
2188 | ||
2189 | if (set) { | |
2190 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); | |
2191 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
2192 | } else { | |
2193 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); | |
2194 | } | |
2195 | ||
2196 | cmd_resp->vsi_id = cpu_to_le16(((vsi_id << | |
2197 | ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & | |
2198 | ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | | |
2199 | ICE_AQC_GSET_RSS_LUT_VSI_VALID); | |
2200 | ||
2201 | switch (lut_type) { | |
2202 | case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: | |
2203 | case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: | |
2204 | case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: | |
2205 | flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & | |
2206 | ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); | |
2207 | break; | |
2208 | default: | |
2209 | status = ICE_ERR_PARAM; | |
2210 | goto ice_aq_get_set_rss_lut_exit; | |
2211 | } | |
2212 | ||
2213 | if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { | |
2214 | flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & | |
2215 | ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); | |
2216 | ||
2217 | if (!set) | |
2218 | goto ice_aq_get_set_rss_lut_send; | |
2219 | } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { | |
2220 | if (!set) | |
2221 | goto ice_aq_get_set_rss_lut_send; | |
2222 | } else { | |
2223 | goto ice_aq_get_set_rss_lut_send; | |
2224 | } | |
2225 | ||
2226 | /* LUT size is only valid for Global and PF table types */ | |
4381147d AV |
2227 | switch (lut_size) { |
2228 | case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: | |
2229 | break; | |
2230 | case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: | |
d76a60ba AV |
2231 | flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << |
2232 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & | |
2233 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; | |
4381147d AV |
2234 | break; |
2235 | case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: | |
2236 | if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { | |
2237 | flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << | |
2238 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & | |
2239 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; | |
2240 | break; | |
2241 | } | |
2242 | /* fall-through */ | |
2243 | default: | |
d76a60ba AV |
2244 | status = ICE_ERR_PARAM; |
2245 | goto ice_aq_get_set_rss_lut_exit; | |
2246 | } | |
2247 | ||
2248 | ice_aq_get_set_rss_lut_send: | |
2249 | cmd_resp->flags = cpu_to_le16(flags); | |
2250 | status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); | |
2251 | ||
2252 | ice_aq_get_set_rss_lut_exit: | |
2253 | return status; | |
2254 | } | |
2255 | ||
2256 | /** | |
2257 | * ice_aq_get_rss_lut | |
2258 | * @hw: pointer to the hardware structure | |
4fb33f31 | 2259 | * @vsi_handle: software VSI handle |
d76a60ba AV |
2260 | * @lut_type: LUT table type |
2261 | * @lut: pointer to the LUT buffer provided by the caller | |
2262 | * @lut_size: size of the LUT buffer | |
2263 | * | |
2264 | * get the RSS lookup table, PF or VSI type | |
2265 | */ | |
2266 | enum ice_status | |
4fb33f31 AV |
2267 | ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, |
2268 | u8 *lut, u16 lut_size) | |
d76a60ba | 2269 | { |
4fb33f31 AV |
2270 | if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) |
2271 | return ICE_ERR_PARAM; | |
2272 | ||
2273 | return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), | |
2274 | lut_type, lut, lut_size, 0, false); | |
d76a60ba AV |
2275 | } |
2276 | ||
2277 | /** | |
2278 | * ice_aq_set_rss_lut | |
2279 | * @hw: pointer to the hardware structure | |
4fb33f31 | 2280 | * @vsi_handle: software VSI handle |
d76a60ba AV |
2281 | * @lut_type: LUT table type |
2282 | * @lut: pointer to the LUT buffer provided by the caller | |
2283 | * @lut_size: size of the LUT buffer | |
2284 | * | |
2285 | * set the RSS lookup table, PF or VSI type | |
2286 | */ | |
2287 | enum ice_status | |
4fb33f31 AV |
2288 | ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, |
2289 | u8 *lut, u16 lut_size) | |
d76a60ba | 2290 | { |
4fb33f31 AV |
2291 | if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) |
2292 | return ICE_ERR_PARAM; | |
2293 | ||
2294 | return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), | |
2295 | lut_type, lut, lut_size, 0, true); | |
d76a60ba AV |
2296 | } |
2297 | ||
2298 | /** | |
2299 | * __ice_aq_get_set_rss_key | |
2300 | * @hw: pointer to the hw struct | |
2301 | * @vsi_id: VSI FW index | |
2302 | * @key: pointer to key info struct | |
2303 | * @set: set true to set the key, false to get the key | |
2304 | * | |
2305 | * get (0x0B04) or set (0x0B02) the RSS key per VSI | |
2306 | */ | |
2307 | static enum | |
2308 | ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, | |
2309 | struct ice_aqc_get_set_rss_keys *key, | |
2310 | bool set) | |
2311 | { | |
2312 | struct ice_aqc_get_set_rss_key *cmd_resp; | |
2313 | u16 key_size = sizeof(*key); | |
2314 | struct ice_aq_desc desc; | |
2315 | ||
2316 | cmd_resp = &desc.params.get_set_rss_key; | |
2317 | ||
2318 | if (set) { | |
2319 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); | |
2320 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
2321 | } else { | |
2322 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); | |
2323 | } | |
2324 | ||
2325 | cmd_resp->vsi_id = cpu_to_le16(((vsi_id << | |
2326 | ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & | |
2327 | ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | | |
2328 | ICE_AQC_GSET_RSS_KEY_VSI_VALID); | |
2329 | ||
2330 | return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); | |
2331 | } | |
2332 | ||
2333 | /** | |
2334 | * ice_aq_get_rss_key | |
2335 | * @hw: pointer to the hw struct | |
4fb33f31 | 2336 | * @vsi_handle: software VSI handle |
d76a60ba AV |
2337 | * @key: pointer to key info struct |
2338 | * | |
2339 | * get the RSS key per VSI | |
2340 | */ | |
2341 | enum ice_status | |
4fb33f31 | 2342 | ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, |
d76a60ba AV |
2343 | struct ice_aqc_get_set_rss_keys *key) |
2344 | { | |
4fb33f31 AV |
2345 | if (!ice_is_vsi_valid(hw, vsi_handle) || !key) |
2346 | return ICE_ERR_PARAM; | |
2347 | ||
2348 | return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), | |
2349 | key, false); | |
d76a60ba AV |
2350 | } |
2351 | ||
2352 | /** | |
2353 | * ice_aq_set_rss_key | |
2354 | * @hw: pointer to the hw struct | |
4fb33f31 | 2355 | * @vsi_handle: software VSI handle |
d76a60ba AV |
2356 | * @keys: pointer to key info struct |
2357 | * | |
2358 | * set the RSS key per VSI | |
2359 | */ | |
2360 | enum ice_status | |
4fb33f31 | 2361 | ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, |
d76a60ba AV |
2362 | struct ice_aqc_get_set_rss_keys *keys) |
2363 | { | |
4fb33f31 AV |
2364 | if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) |
2365 | return ICE_ERR_PARAM; | |
2366 | ||
2367 | return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), | |
2368 | keys, true); | |
d76a60ba AV |
2369 | } |
2370 | ||
cdedef59 AV |
2371 | /** |
2372 | * ice_aq_add_lan_txq | |
2373 | * @hw: pointer to the hardware structure | |
2374 | * @num_qgrps: Number of added queue groups | |
2375 | * @qg_list: list of queue groups to be added | |
2376 | * @buf_size: size of buffer for indirect command | |
2377 | * @cd: pointer to command details structure or NULL | |
2378 | * | |
2379 | * Add Tx LAN queue (0x0C30) | |
2380 | * | |
2381 | * NOTE: | |
2382 | * Prior to calling add Tx LAN queue: | |
2383 | * Initialize the following as part of the Tx queue context: | |
2384 | * Completion queue ID if the queue uses Completion queue, Quanta profile, | |
2385 | * Cache profile and Packet shaper profile. | |
2386 | * | |
2387 | * After add Tx LAN queue AQ command is completed: | |
2388 | * Interrupts should be associated with specific queues, | |
2389 | * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue | |
2390 | * flow. | |
2391 | */ | |
2392 | static enum ice_status | |
2393 | ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, | |
2394 | struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, | |
2395 | struct ice_sq_cd *cd) | |
2396 | { | |
2397 | u16 i, sum_header_size, sum_q_size = 0; | |
2398 | struct ice_aqc_add_tx_qgrp *list; | |
2399 | struct ice_aqc_add_txqs *cmd; | |
2400 | struct ice_aq_desc desc; | |
2401 | ||
2402 | cmd = &desc.params.add_txqs; | |
2403 | ||
2404 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); | |
2405 | ||
2406 | if (!qg_list) | |
2407 | return ICE_ERR_PARAM; | |
2408 | ||
2409 | if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) | |
2410 | return ICE_ERR_PARAM; | |
2411 | ||
2412 | sum_header_size = num_qgrps * | |
2413 | (sizeof(*qg_list) - sizeof(*qg_list->txqs)); | |
2414 | ||
2415 | list = qg_list; | |
2416 | for (i = 0; i < num_qgrps; i++) { | |
2417 | struct ice_aqc_add_txqs_perq *q = list->txqs; | |
2418 | ||
2419 | sum_q_size += list->num_txqs * sizeof(*q); | |
2420 | list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); | |
2421 | } | |
2422 | ||
2423 | if (buf_size != (sum_header_size + sum_q_size)) | |
2424 | return ICE_ERR_PARAM; | |
2425 | ||
2426 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
2427 | ||
2428 | cmd->num_qgrps = num_qgrps; | |
2429 | ||
2430 | return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); | |
2431 | } | |
2432 | ||
2433 | /** | |
2434 | * ice_aq_dis_lan_txq | |
2435 | * @hw: pointer to the hardware structure | |
2436 | * @num_qgrps: number of groups in the list | |
2437 | * @qg_list: the list of groups to disable | |
2438 | * @buf_size: the total size of the qg_list buffer in bytes | |
ddf30f7f AV |
2439 | * @rst_src: if called due to reset, specifies the RST source |
2440 | * @vmvf_num: the relative VM or VF number that is undergoing the reset | |
cdedef59 AV |
2441 | * @cd: pointer to command details structure or NULL |
2442 | * | |
2443 | * Disable LAN Tx queue (0x0C31) | |
2444 | */ | |
2445 | static enum ice_status | |
2446 | ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, | |
2447 | struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, | |
ddf30f7f | 2448 | enum ice_disq_rst_src rst_src, u16 vmvf_num, |
cdedef59 AV |
2449 | struct ice_sq_cd *cd) |
2450 | { | |
2451 | struct ice_aqc_dis_txqs *cmd; | |
2452 | struct ice_aq_desc desc; | |
6e9650d5 | 2453 | enum ice_status status; |
cdedef59 AV |
2454 | u16 i, sz = 0; |
2455 | ||
2456 | cmd = &desc.params.dis_txqs; | |
2457 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); | |
2458 | ||
ddf30f7f AV |
2459 | /* qg_list can be NULL only in VM/VF reset flow */ |
2460 | if (!qg_list && !rst_src) | |
cdedef59 AV |
2461 | return ICE_ERR_PARAM; |
2462 | ||
2463 | if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) | |
2464 | return ICE_ERR_PARAM; | |
ddf30f7f | 2465 | |
cdedef59 AV |
2466 | cmd->num_entries = num_qgrps; |
2467 | ||
ddf30f7f AV |
2468 | cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & |
2469 | ICE_AQC_Q_DIS_TIMEOUT_M); | |
2470 | ||
2471 | switch (rst_src) { | |
2472 | case ICE_VM_RESET: | |
2473 | cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; | |
2474 | cmd->vmvf_and_timeout |= | |
2475 | cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); | |
2476 | break; | |
2477 | case ICE_VF_RESET: | |
2478 | cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; | |
2479 | /* In this case, FW expects vmvf_num to be absolute VF id */ | |
2480 | cmd->vmvf_and_timeout |= | |
2481 | cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & | |
2482 | ICE_AQC_Q_DIS_VMVF_NUM_M); | |
2483 | break; | |
2484 | case ICE_NO_RESET: | |
2485 | default: | |
2486 | break; | |
2487 | } | |
2488 | ||
6e9650d5 VR |
2489 | /* flush pipe on time out */ |
2490 | cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; | |
ddf30f7f AV |
2491 | /* If no queue group info, we are in a reset flow. Issue the AQ */ |
2492 | if (!qg_list) | |
2493 | goto do_aq; | |
2494 | ||
2495 | /* set RD bit to indicate that command buffer is provided by the driver | |
2496 | * and it needs to be read by the firmware | |
2497 | */ | |
2498 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
2499 | ||
cdedef59 AV |
2500 | for (i = 0; i < num_qgrps; ++i) { |
2501 | /* Calculate the size taken up by the queue IDs in this group */ | |
2502 | sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); | |
2503 | ||
2504 | /* Add the size of the group header */ | |
2505 | sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); | |
2506 | ||
2507 | /* If the num of queues is even, add 2 bytes of padding */ | |
2508 | if ((qg_list[i].num_qs % 2) == 0) | |
2509 | sz += 2; | |
2510 | } | |
2511 | ||
2512 | if (buf_size != sz) | |
2513 | return ICE_ERR_PARAM; | |
2514 | ||
ddf30f7f | 2515 | do_aq: |
6e9650d5 VR |
2516 | status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); |
2517 | if (status) { | |
2518 | if (!qg_list) | |
2519 | ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", | |
2520 | vmvf_num, hw->adminq.sq_last_status); | |
2521 | else | |
2522 | ice_debug(hw, ICE_DBG_SCHED, "disable Q %d failed %d\n", | |
2523 | le16_to_cpu(qg_list[0].q_id[0]), | |
2524 | hw->adminq.sq_last_status); | |
2525 | } | |
2526 | return status; | |
cdedef59 AV |
2527 | } |
2528 | ||
2529 | /* End of FW Admin Queue command wrappers */ | |
2530 | ||
2531 | /** | |
2532 | * ice_write_byte - write a byte to a packed context structure | |
2533 | * @src_ctx: the context structure to read from | |
2534 | * @dest_ctx: the context to be written to | |
2535 | * @ce_info: a description of the struct to be filled | |
2536 | */ | |
2537 | static void ice_write_byte(u8 *src_ctx, u8 *dest_ctx, | |
2538 | const struct ice_ctx_ele *ce_info) | |
2539 | { | |
2540 | u8 src_byte, dest_byte, mask; | |
2541 | u8 *from, *dest; | |
2542 | u16 shift_width; | |
2543 | ||
2544 | /* copy from the next struct field */ | |
2545 | from = src_ctx + ce_info->offset; | |
2546 | ||
2547 | /* prepare the bits and mask */ | |
2548 | shift_width = ce_info->lsb % 8; | |
2549 | mask = (u8)(BIT(ce_info->width) - 1); | |
2550 | ||
2551 | src_byte = *from; | |
2552 | src_byte &= mask; | |
2553 | ||
2554 | /* shift to correct alignment */ | |
2555 | mask <<= shift_width; | |
2556 | src_byte <<= shift_width; | |
2557 | ||
2558 | /* get the current bits from the target bit string */ | |
2559 | dest = dest_ctx + (ce_info->lsb / 8); | |
2560 | ||
2561 | memcpy(&dest_byte, dest, sizeof(dest_byte)); | |
2562 | ||
2563 | dest_byte &= ~mask; /* get the bits not changing */ | |
2564 | dest_byte |= src_byte; /* add in the new bits */ | |
2565 | ||
2566 | /* put it all back */ | |
2567 | memcpy(dest, &dest_byte, sizeof(dest_byte)); | |
2568 | } | |
2569 | ||
2570 | /** | |
2571 | * ice_write_word - write a word to a packed context structure | |
2572 | * @src_ctx: the context structure to read from | |
2573 | * @dest_ctx: the context to be written to | |
2574 | * @ce_info: a description of the struct to be filled | |
2575 | */ | |
2576 | static void ice_write_word(u8 *src_ctx, u8 *dest_ctx, | |
2577 | const struct ice_ctx_ele *ce_info) | |
2578 | { | |
2579 | u16 src_word, mask; | |
2580 | __le16 dest_word; | |
2581 | u8 *from, *dest; | |
2582 | u16 shift_width; | |
2583 | ||
2584 | /* copy from the next struct field */ | |
2585 | from = src_ctx + ce_info->offset; | |
2586 | ||
2587 | /* prepare the bits and mask */ | |
2588 | shift_width = ce_info->lsb % 8; | |
2589 | mask = BIT(ce_info->width) - 1; | |
2590 | ||
2591 | /* don't swizzle the bits until after the mask because the mask bits | |
2592 | * will be in a different bit position on big endian machines | |
2593 | */ | |
2594 | src_word = *(u16 *)from; | |
2595 | src_word &= mask; | |
2596 | ||
2597 | /* shift to correct alignment */ | |
2598 | mask <<= shift_width; | |
2599 | src_word <<= shift_width; | |
2600 | ||
2601 | /* get the current bits from the target bit string */ | |
2602 | dest = dest_ctx + (ce_info->lsb / 8); | |
2603 | ||
2604 | memcpy(&dest_word, dest, sizeof(dest_word)); | |
2605 | ||
2606 | dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ | |
2607 | dest_word |= cpu_to_le16(src_word); /* add in the new bits */ | |
2608 | ||
2609 | /* put it all back */ | |
2610 | memcpy(dest, &dest_word, sizeof(dest_word)); | |
2611 | } | |
2612 | ||
2613 | /** | |
2614 | * ice_write_dword - write a dword to a packed context structure | |
2615 | * @src_ctx: the context structure to read from | |
2616 | * @dest_ctx: the context to be written to | |
2617 | * @ce_info: a description of the struct to be filled | |
2618 | */ | |
2619 | static void ice_write_dword(u8 *src_ctx, u8 *dest_ctx, | |
2620 | const struct ice_ctx_ele *ce_info) | |
2621 | { | |
2622 | u32 src_dword, mask; | |
2623 | __le32 dest_dword; | |
2624 | u8 *from, *dest; | |
2625 | u16 shift_width; | |
2626 | ||
2627 | /* copy from the next struct field */ | |
2628 | from = src_ctx + ce_info->offset; | |
2629 | ||
2630 | /* prepare the bits and mask */ | |
2631 | shift_width = ce_info->lsb % 8; | |
2632 | ||
2633 | /* if the field width is exactly 32 on an x86 machine, then the shift | |
2634 | * operation will not work because the SHL instructions count is masked | |
2635 | * to 5 bits so the shift will do nothing | |
2636 | */ | |
2637 | if (ce_info->width < 32) | |
2638 | mask = BIT(ce_info->width) - 1; | |
2639 | else | |
2640 | mask = (u32)~0; | |
2641 | ||
2642 | /* don't swizzle the bits until after the mask because the mask bits | |
2643 | * will be in a different bit position on big endian machines | |
2644 | */ | |
2645 | src_dword = *(u32 *)from; | |
2646 | src_dword &= mask; | |
2647 | ||
2648 | /* shift to correct alignment */ | |
2649 | mask <<= shift_width; | |
2650 | src_dword <<= shift_width; | |
2651 | ||
2652 | /* get the current bits from the target bit string */ | |
2653 | dest = dest_ctx + (ce_info->lsb / 8); | |
2654 | ||
2655 | memcpy(&dest_dword, dest, sizeof(dest_dword)); | |
2656 | ||
2657 | dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ | |
2658 | dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ | |
2659 | ||
2660 | /* put it all back */ | |
2661 | memcpy(dest, &dest_dword, sizeof(dest_dword)); | |
2662 | } | |
2663 | ||
2664 | /** | |
2665 | * ice_write_qword - write a qword to a packed context structure | |
2666 | * @src_ctx: the context structure to read from | |
2667 | * @dest_ctx: the context to be written to | |
2668 | * @ce_info: a description of the struct to be filled | |
2669 | */ | |
2670 | static void ice_write_qword(u8 *src_ctx, u8 *dest_ctx, | |
2671 | const struct ice_ctx_ele *ce_info) | |
2672 | { | |
2673 | u64 src_qword, mask; | |
2674 | __le64 dest_qword; | |
2675 | u8 *from, *dest; | |
2676 | u16 shift_width; | |
2677 | ||
2678 | /* copy from the next struct field */ | |
2679 | from = src_ctx + ce_info->offset; | |
2680 | ||
2681 | /* prepare the bits and mask */ | |
2682 | shift_width = ce_info->lsb % 8; | |
2683 | ||
2684 | /* if the field width is exactly 64 on an x86 machine, then the shift | |
2685 | * operation will not work because the SHL instructions count is masked | |
2686 | * to 6 bits so the shift will do nothing | |
2687 | */ | |
2688 | if (ce_info->width < 64) | |
2689 | mask = BIT_ULL(ce_info->width) - 1; | |
2690 | else | |
2691 | mask = (u64)~0; | |
2692 | ||
2693 | /* don't swizzle the bits until after the mask because the mask bits | |
2694 | * will be in a different bit position on big endian machines | |
2695 | */ | |
2696 | src_qword = *(u64 *)from; | |
2697 | src_qword &= mask; | |
2698 | ||
2699 | /* shift to correct alignment */ | |
2700 | mask <<= shift_width; | |
2701 | src_qword <<= shift_width; | |
2702 | ||
2703 | /* get the current bits from the target bit string */ | |
2704 | dest = dest_ctx + (ce_info->lsb / 8); | |
2705 | ||
2706 | memcpy(&dest_qword, dest, sizeof(dest_qword)); | |
2707 | ||
2708 | dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ | |
2709 | dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ | |
2710 | ||
2711 | /* put it all back */ | |
2712 | memcpy(dest, &dest_qword, sizeof(dest_qword)); | |
2713 | } | |
2714 | ||
2715 | /** | |
2716 | * ice_set_ctx - set context bits in packed structure | |
2717 | * @src_ctx: pointer to a generic non-packed context structure | |
2718 | * @dest_ctx: pointer to memory for the packed structure | |
2719 | * @ce_info: a description of the structure to be transformed | |
2720 | */ | |
2721 | enum ice_status | |
2722 | ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) | |
2723 | { | |
2724 | int f; | |
2725 | ||
2726 | for (f = 0; ce_info[f].width; f++) { | |
2727 | /* We have to deal with each element of the FW response | |
2728 | * using the correct size so that we are correct regardless | |
2729 | * of the endianness of the machine. | |
2730 | */ | |
2731 | switch (ce_info[f].size_of) { | |
2732 | case sizeof(u8): | |
2733 | ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); | |
2734 | break; | |
2735 | case sizeof(u16): | |
2736 | ice_write_word(src_ctx, dest_ctx, &ce_info[f]); | |
2737 | break; | |
2738 | case sizeof(u32): | |
2739 | ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); | |
2740 | break; | |
2741 | case sizeof(u64): | |
2742 | ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); | |
2743 | break; | |
2744 | default: | |
2745 | return ICE_ERR_INVAL_SIZE; | |
2746 | } | |
2747 | } | |
2748 | ||
2749 | return 0; | |
2750 | } | |
2751 | ||
2752 | /** | |
2753 | * ice_ena_vsi_txq | |
2754 | * @pi: port information structure | |
4fb33f31 | 2755 | * @vsi_handle: software VSI handle |
cdedef59 AV |
2756 | * @tc: tc number |
2757 | * @num_qgrps: Number of added queue groups | |
2758 | * @buf: list of queue groups to be added | |
2759 | * @buf_size: size of buffer for indirect command | |
2760 | * @cd: pointer to command details structure or NULL | |
2761 | * | |
2762 | * This function adds one lan q | |
2763 | */ | |
2764 | enum ice_status | |
4fb33f31 | 2765 | ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps, |
cdedef59 AV |
2766 | struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, |
2767 | struct ice_sq_cd *cd) | |
2768 | { | |
2769 | struct ice_aqc_txsched_elem_data node = { 0 }; | |
2770 | struct ice_sched_node *parent; | |
2771 | enum ice_status status; | |
2772 | struct ice_hw *hw; | |
2773 | ||
2774 | if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) | |
2775 | return ICE_ERR_CFG; | |
2776 | ||
2777 | if (num_qgrps > 1 || buf->num_txqs > 1) | |
2778 | return ICE_ERR_MAX_LIMIT; | |
2779 | ||
2780 | hw = pi->hw; | |
2781 | ||
4fb33f31 AV |
2782 | if (!ice_is_vsi_valid(hw, vsi_handle)) |
2783 | return ICE_ERR_PARAM; | |
2784 | ||
cdedef59 AV |
2785 | mutex_lock(&pi->sched_lock); |
2786 | ||
2787 | /* find a parent node */ | |
4fb33f31 | 2788 | parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, |
cdedef59 AV |
2789 | ICE_SCHED_NODE_OWNER_LAN); |
2790 | if (!parent) { | |
2791 | status = ICE_ERR_PARAM; | |
2792 | goto ena_txq_exit; | |
2793 | } | |
4fb33f31 | 2794 | |
cdedef59 AV |
2795 | buf->parent_teid = parent->info.node_teid; |
2796 | node.parent_teid = parent->info.node_teid; | |
2797 | /* Mark that the values in the "generic" section as valid. The default | |
2798 | * value in the "generic" section is zero. This means that : | |
2799 | * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. | |
2800 | * - 0 priority among siblings, indicated by Bit 1-3. | |
2801 | * - WFQ, indicated by Bit 4. | |
2802 | * - 0 Adjustment value is used in PSM credit update flow, indicated by | |
2803 | * Bit 5-6. | |
2804 | * - Bit 7 is reserved. | |
2805 | * Without setting the generic section as valid in valid_sections, the | |
2806 | * Admin Q command will fail with error code ICE_AQ_RC_EINVAL. | |
2807 | */ | |
2808 | buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; | |
2809 | ||
2810 | /* add the lan q */ | |
2811 | status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); | |
6e9650d5 VR |
2812 | if (status) { |
2813 | ice_debug(hw, ICE_DBG_SCHED, "enable Q %d failed %d\n", | |
2814 | le16_to_cpu(buf->txqs[0].txq_id), | |
2815 | hw->adminq.sq_last_status); | |
cdedef59 | 2816 | goto ena_txq_exit; |
6e9650d5 | 2817 | } |
cdedef59 AV |
2818 | |
2819 | node.node_teid = buf->txqs[0].q_teid; | |
2820 | node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; | |
2821 | ||
2822 | /* add a leaf node into schduler tree q layer */ | |
2823 | status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); | |
2824 | ||
2825 | ena_txq_exit: | |
2826 | mutex_unlock(&pi->sched_lock); | |
2827 | return status; | |
2828 | } | |
2829 | ||
2830 | /** | |
2831 | * ice_dis_vsi_txq | |
2832 | * @pi: port information structure | |
2833 | * @num_queues: number of queues | |
2834 | * @q_ids: pointer to the q_id array | |
2835 | * @q_teids: pointer to queue node teids | |
ddf30f7f AV |
2836 | * @rst_src: if called due to reset, specifies the RST source |
2837 | * @vmvf_num: the relative VM or VF number that is undergoing the reset | |
cdedef59 AV |
2838 | * @cd: pointer to command details structure or NULL |
2839 | * | |
2840 | * This function removes queues and their corresponding nodes in SW DB | |
2841 | */ | |
2842 | enum ice_status | |
2843 | ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids, | |
ddf30f7f AV |
2844 | u32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num, |
2845 | struct ice_sq_cd *cd) | |
cdedef59 AV |
2846 | { |
2847 | enum ice_status status = ICE_ERR_DOES_NOT_EXIST; | |
2848 | struct ice_aqc_dis_txq_item qg_list; | |
2849 | u16 i; | |
2850 | ||
2851 | if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) | |
2852 | return ICE_ERR_CFG; | |
2853 | ||
ddf30f7f AV |
2854 | /* if queue is disabled already yet the disable queue command has to be |
2855 | * sent to complete the VF reset, then call ice_aq_dis_lan_txq without | |
2856 | * any queue information | |
2857 | */ | |
2858 | ||
2859 | if (!num_queues && rst_src) | |
2860 | return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, vmvf_num, | |
2861 | NULL); | |
2862 | ||
cdedef59 AV |
2863 | mutex_lock(&pi->sched_lock); |
2864 | ||
2865 | for (i = 0; i < num_queues; i++) { | |
2866 | struct ice_sched_node *node; | |
2867 | ||
2868 | node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); | |
2869 | if (!node) | |
2870 | continue; | |
2871 | qg_list.parent_teid = node->info.parent_teid; | |
2872 | qg_list.num_qs = 1; | |
2873 | qg_list.q_id[0] = cpu_to_le16(q_ids[i]); | |
2874 | status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, | |
ddf30f7f AV |
2875 | sizeof(qg_list), rst_src, vmvf_num, |
2876 | cd); | |
cdedef59 AV |
2877 | |
2878 | if (status) | |
2879 | break; | |
2880 | ice_free_sched_node(pi, node); | |
2881 | } | |
2882 | mutex_unlock(&pi->sched_lock); | |
2883 | return status; | |
2884 | } | |
5513b920 AV |
2885 | |
2886 | /** | |
2887 | * ice_cfg_vsi_qs - configure the new/exisiting VSI queues | |
2888 | * @pi: port information structure | |
4fb33f31 | 2889 | * @vsi_handle: software VSI handle |
5513b920 AV |
2890 | * @tc_bitmap: TC bitmap |
2891 | * @maxqs: max queues array per TC | |
2892 | * @owner: lan or rdma | |
2893 | * | |
2894 | * This function adds/updates the VSI queues per TC. | |
2895 | */ | |
2896 | static enum ice_status | |
4fb33f31 | 2897 | ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, |
5513b920 AV |
2898 | u16 *maxqs, u8 owner) |
2899 | { | |
2900 | enum ice_status status = 0; | |
2901 | u8 i; | |
2902 | ||
2903 | if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) | |
2904 | return ICE_ERR_CFG; | |
2905 | ||
4fb33f31 AV |
2906 | if (!ice_is_vsi_valid(pi->hw, vsi_handle)) |
2907 | return ICE_ERR_PARAM; | |
2908 | ||
5513b920 AV |
2909 | mutex_lock(&pi->sched_lock); |
2910 | ||
2911 | for (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) { | |
2912 | /* configuration is possible only if TC node is present */ | |
2913 | if (!ice_sched_get_tc_node(pi, i)) | |
2914 | continue; | |
2915 | ||
4fb33f31 | 2916 | status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, |
5513b920 AV |
2917 | ice_is_tc_ena(tc_bitmap, i)); |
2918 | if (status) | |
2919 | break; | |
2920 | } | |
2921 | ||
2922 | mutex_unlock(&pi->sched_lock); | |
2923 | return status; | |
2924 | } | |
2925 | ||
2926 | /** | |
2927 | * ice_cfg_vsi_lan - configure VSI lan queues | |
2928 | * @pi: port information structure | |
4fb33f31 | 2929 | * @vsi_handle: software VSI handle |
5513b920 AV |
2930 | * @tc_bitmap: TC bitmap |
2931 | * @max_lanqs: max lan queues array per TC | |
2932 | * | |
2933 | * This function adds/updates the VSI lan queues per TC. | |
2934 | */ | |
2935 | enum ice_status | |
4fb33f31 | 2936 | ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, |
5513b920 AV |
2937 | u16 *max_lanqs) |
2938 | { | |
4fb33f31 | 2939 | return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, |
5513b920 AV |
2940 | ICE_SCHED_NODE_OWNER_LAN); |
2941 | } | |
45d3d428 | 2942 | |
334cb062 AV |
2943 | /** |
2944 | * ice_replay_pre_init - replay pre initialization | |
2945 | * @hw: pointer to the hw struct | |
2946 | * | |
2947 | * Initializes required config data for VSI, FD, ACL, and RSS before replay. | |
2948 | */ | |
2949 | static enum ice_status ice_replay_pre_init(struct ice_hw *hw) | |
2950 | { | |
2951 | struct ice_switch_info *sw = hw->switch_info; | |
2952 | u8 i; | |
2953 | ||
2954 | /* Delete old entries from replay filter list head if there is any */ | |
2955 | ice_rm_all_sw_replay_rule_info(hw); | |
2956 | /* In start of replay, move entries into replay_rules list, it | |
2957 | * will allow adding rules entries back to filt_rules list, | |
2958 | * which is operational list. | |
2959 | */ | |
2960 | for (i = 0; i < ICE_SW_LKUP_LAST; i++) | |
2961 | list_replace_init(&sw->recp_list[i].filt_rules, | |
2962 | &sw->recp_list[i].filt_replay_rules); | |
2963 | ||
2964 | return 0; | |
2965 | } | |
2966 | ||
2967 | /** | |
2968 | * ice_replay_vsi - replay VSI configuration | |
2969 | * @hw: pointer to the hw struct | |
2970 | * @vsi_handle: driver VSI handle | |
2971 | * | |
2972 | * Restore all VSI configuration after reset. It is required to call this | |
2973 | * function with main VSI first. | |
2974 | */ | |
2975 | enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) | |
2976 | { | |
2977 | enum ice_status status; | |
2978 | ||
2979 | if (!ice_is_vsi_valid(hw, vsi_handle)) | |
2980 | return ICE_ERR_PARAM; | |
2981 | ||
2982 | /* Replay pre-initialization if there is any */ | |
2983 | if (vsi_handle == ICE_MAIN_VSI_HANDLE) { | |
2984 | status = ice_replay_pre_init(hw); | |
2985 | if (status) | |
2986 | return status; | |
2987 | } | |
2988 | ||
2989 | /* Replay per VSI all filters */ | |
2990 | status = ice_replay_vsi_all_fltr(hw, vsi_handle); | |
2991 | return status; | |
2992 | } | |
2993 | ||
2994 | /** | |
2995 | * ice_replay_post - post replay configuration cleanup | |
2996 | * @hw: pointer to the hw struct | |
2997 | * | |
2998 | * Post replay cleanup. | |
2999 | */ | |
3000 | void ice_replay_post(struct ice_hw *hw) | |
3001 | { | |
3002 | /* Delete old entries from replay filter list head */ | |
3003 | ice_rm_all_sw_replay_rule_info(hw); | |
3004 | } | |
3005 | ||
45d3d428 AV |
3006 | /** |
3007 | * ice_stat_update40 - read 40 bit stat from the chip and update stat values | |
3008 | * @hw: ptr to the hardware info | |
3009 | * @hireg: high 32 bit HW register to read from | |
3010 | * @loreg: low 32 bit HW register to read from | |
3011 | * @prev_stat_loaded: bool to specify if previous stats are loaded | |
3012 | * @prev_stat: ptr to previous loaded stat value | |
3013 | * @cur_stat: ptr to current stat value | |
3014 | */ | |
3015 | void ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg, | |
3016 | bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat) | |
3017 | { | |
3018 | u64 new_data; | |
3019 | ||
3020 | new_data = rd32(hw, loreg); | |
3021 | new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; | |
3022 | ||
3023 | /* device stats are not reset at PFR, they likely will not be zeroed | |
3024 | * when the driver starts. So save the first values read and use them as | |
3025 | * offsets to be subtracted from the raw values in order to report stats | |
3026 | * that count from zero. | |
3027 | */ | |
3028 | if (!prev_stat_loaded) | |
3029 | *prev_stat = new_data; | |
3030 | if (new_data >= *prev_stat) | |
3031 | *cur_stat = new_data - *prev_stat; | |
3032 | else | |
3033 | /* to manage the potential roll-over */ | |
3034 | *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat; | |
3035 | *cur_stat &= 0xFFFFFFFFFFULL; | |
3036 | } | |
3037 | ||
3038 | /** | |
3039 | * ice_stat_update32 - read 32 bit stat from the chip and update stat values | |
3040 | * @hw: ptr to the hardware info | |
3041 | * @reg: HW register to read from | |
3042 | * @prev_stat_loaded: bool to specify if previous stats are loaded | |
3043 | * @prev_stat: ptr to previous loaded stat value | |
3044 | * @cur_stat: ptr to current stat value | |
3045 | */ | |
3046 | void ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, | |
3047 | u64 *prev_stat, u64 *cur_stat) | |
3048 | { | |
3049 | u32 new_data; | |
3050 | ||
3051 | new_data = rd32(hw, reg); | |
3052 | ||
3053 | /* device stats are not reset at PFR, they likely will not be zeroed | |
3054 | * when the driver starts. So save the first values read and use them as | |
3055 | * offsets to be subtracted from the raw values in order to report stats | |
3056 | * that count from zero. | |
3057 | */ | |
3058 | if (!prev_stat_loaded) | |
3059 | *prev_stat = new_data; | |
3060 | if (new_data >= *prev_stat) | |
3061 | *cur_stat = new_data - *prev_stat; | |
3062 | else | |
3063 | /* to manage the potential roll-over */ | |
3064 | *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat; | |
3065 | } |