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7ec59eea AV |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright (c) 2018, Intel Corporation. */ | |
3 | ||
4 | #include "ice_common.h" | |
9c20346b | 5 | #include "ice_sched.h" |
7ec59eea AV |
6 | #include "ice_adminq_cmd.h" |
7 | ||
f31e4b6f AV |
8 | #define ICE_PF_RESET_WAIT_COUNT 200 |
9 | ||
cdedef59 AV |
10 | #define ICE_NIC_FLX_ENTRY(hw, mdid, idx) \ |
11 | wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(ICE_RXDID_FLEX_NIC), \ | |
12 | ((ICE_RX_OPC_MDID << \ | |
13 | GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ | |
14 | GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ | |
15 | (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ | |
16 | GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) | |
17 | ||
18 | #define ICE_NIC_FLX_FLG_ENTRY(hw, flg_0, flg_1, flg_2, flg_3, idx) \ | |
19 | wr32((hw), GLFLXP_RXDID_FLAGS(ICE_RXDID_FLEX_NIC, idx), \ | |
20 | (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ | |
21 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ | |
22 | (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ | |
23 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ | |
24 | (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ | |
25 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ | |
26 | (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ | |
27 | GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) | |
28 | ||
f31e4b6f AV |
29 | /** |
30 | * ice_set_mac_type - Sets MAC type | |
31 | * @hw: pointer to the HW structure | |
32 | * | |
33 | * This function sets the MAC type of the adapter based on the | |
34 | * vendor ID and device ID stored in the hw structure. | |
35 | */ | |
36 | static enum ice_status ice_set_mac_type(struct ice_hw *hw) | |
37 | { | |
38 | if (hw->vendor_id != PCI_VENDOR_ID_INTEL) | |
39 | return ICE_ERR_DEVICE_NOT_SUPPORTED; | |
40 | ||
41 | hw->mac_type = ICE_MAC_GENERIC; | |
42 | return 0; | |
43 | } | |
44 | ||
45 | /** | |
46 | * ice_clear_pf_cfg - Clear PF configuration | |
47 | * @hw: pointer to the hardware structure | |
48 | */ | |
49 | enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) | |
50 | { | |
51 | struct ice_aq_desc desc; | |
52 | ||
53 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); | |
54 | ||
55 | return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); | |
56 | } | |
57 | ||
dc49c772 AV |
58 | /** |
59 | * ice_aq_manage_mac_read - manage MAC address read command | |
60 | * @hw: pointer to the hw struct | |
61 | * @buf: a virtual buffer to hold the manage MAC read response | |
62 | * @buf_size: Size of the virtual buffer | |
63 | * @cd: pointer to command details structure or NULL | |
64 | * | |
65 | * This function is used to return per PF station MAC address (0x0107). | |
66 | * NOTE: Upon successful completion of this command, MAC address information | |
67 | * is returned in user specified buffer. Please interpret user specified | |
68 | * buffer as "manage_mac_read" response. | |
69 | * Response such as various MAC addresses are stored in HW struct (port.mac) | |
70 | * ice_aq_discover_caps is expected to be called before this function is called. | |
71 | */ | |
72 | static enum ice_status | |
73 | ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, | |
74 | struct ice_sq_cd *cd) | |
75 | { | |
76 | struct ice_aqc_manage_mac_read_resp *resp; | |
77 | struct ice_aqc_manage_mac_read *cmd; | |
78 | struct ice_aq_desc desc; | |
79 | enum ice_status status; | |
80 | u16 flags; | |
81 | ||
82 | cmd = &desc.params.mac_read; | |
83 | ||
84 | if (buf_size < sizeof(*resp)) | |
85 | return ICE_ERR_BUF_TOO_SHORT; | |
86 | ||
87 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); | |
88 | ||
89 | status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); | |
90 | if (status) | |
91 | return status; | |
92 | ||
93 | resp = (struct ice_aqc_manage_mac_read_resp *)buf; | |
94 | flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; | |
95 | ||
96 | if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { | |
97 | ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); | |
98 | return ICE_ERR_CFG; | |
99 | } | |
100 | ||
101 | ether_addr_copy(hw->port_info->mac.lan_addr, resp->mac_addr); | |
102 | ether_addr_copy(hw->port_info->mac.perm_addr, resp->mac_addr); | |
103 | return 0; | |
104 | } | |
105 | ||
106 | /** | |
107 | * ice_aq_get_phy_caps - returns PHY capabilities | |
108 | * @pi: port information structure | |
109 | * @qual_mods: report qualified modules | |
110 | * @report_mode: report mode capabilities | |
111 | * @pcaps: structure for PHY capabilities to be filled | |
112 | * @cd: pointer to command details structure or NULL | |
113 | * | |
114 | * Returns the various PHY capabilities supported on the Port (0x0600) | |
115 | */ | |
116 | static enum ice_status | |
117 | ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, | |
118 | struct ice_aqc_get_phy_caps_data *pcaps, | |
119 | struct ice_sq_cd *cd) | |
120 | { | |
121 | struct ice_aqc_get_phy_caps *cmd; | |
122 | u16 pcaps_size = sizeof(*pcaps); | |
123 | struct ice_aq_desc desc; | |
124 | enum ice_status status; | |
125 | ||
126 | cmd = &desc.params.get_phy; | |
127 | ||
128 | if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) | |
129 | return ICE_ERR_PARAM; | |
130 | ||
131 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); | |
132 | ||
133 | if (qual_mods) | |
134 | cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); | |
135 | ||
136 | cmd->param0 |= cpu_to_le16(report_mode); | |
137 | status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); | |
138 | ||
139 | if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) | |
140 | pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); | |
141 | ||
142 | return status; | |
143 | } | |
144 | ||
145 | /** | |
146 | * ice_get_media_type - Gets media type | |
147 | * @pi: port information structure | |
148 | */ | |
149 | static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) | |
150 | { | |
151 | struct ice_link_status *hw_link_info; | |
152 | ||
153 | if (!pi) | |
154 | return ICE_MEDIA_UNKNOWN; | |
155 | ||
156 | hw_link_info = &pi->phy.link_info; | |
157 | ||
158 | if (hw_link_info->phy_type_low) { | |
159 | switch (hw_link_info->phy_type_low) { | |
160 | case ICE_PHY_TYPE_LOW_1000BASE_SX: | |
161 | case ICE_PHY_TYPE_LOW_1000BASE_LX: | |
162 | case ICE_PHY_TYPE_LOW_10GBASE_SR: | |
163 | case ICE_PHY_TYPE_LOW_10GBASE_LR: | |
164 | case ICE_PHY_TYPE_LOW_10G_SFI_C2C: | |
165 | case ICE_PHY_TYPE_LOW_25GBASE_SR: | |
166 | case ICE_PHY_TYPE_LOW_25GBASE_LR: | |
167 | case ICE_PHY_TYPE_LOW_25G_AUI_C2C: | |
168 | case ICE_PHY_TYPE_LOW_40GBASE_SR4: | |
169 | case ICE_PHY_TYPE_LOW_40GBASE_LR4: | |
170 | return ICE_MEDIA_FIBER; | |
171 | case ICE_PHY_TYPE_LOW_100BASE_TX: | |
172 | case ICE_PHY_TYPE_LOW_1000BASE_T: | |
173 | case ICE_PHY_TYPE_LOW_2500BASE_T: | |
174 | case ICE_PHY_TYPE_LOW_5GBASE_T: | |
175 | case ICE_PHY_TYPE_LOW_10GBASE_T: | |
176 | case ICE_PHY_TYPE_LOW_25GBASE_T: | |
177 | return ICE_MEDIA_BASET; | |
178 | case ICE_PHY_TYPE_LOW_10G_SFI_DA: | |
179 | case ICE_PHY_TYPE_LOW_25GBASE_CR: | |
180 | case ICE_PHY_TYPE_LOW_25GBASE_CR_S: | |
181 | case ICE_PHY_TYPE_LOW_25GBASE_CR1: | |
182 | case ICE_PHY_TYPE_LOW_40GBASE_CR4: | |
183 | return ICE_MEDIA_DA; | |
184 | case ICE_PHY_TYPE_LOW_1000BASE_KX: | |
185 | case ICE_PHY_TYPE_LOW_2500BASE_KX: | |
186 | case ICE_PHY_TYPE_LOW_2500BASE_X: | |
187 | case ICE_PHY_TYPE_LOW_5GBASE_KR: | |
188 | case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: | |
189 | case ICE_PHY_TYPE_LOW_25GBASE_KR: | |
190 | case ICE_PHY_TYPE_LOW_25GBASE_KR1: | |
191 | case ICE_PHY_TYPE_LOW_25GBASE_KR_S: | |
192 | case ICE_PHY_TYPE_LOW_40GBASE_KR4: | |
193 | return ICE_MEDIA_BACKPLANE; | |
194 | } | |
195 | } | |
196 | ||
197 | return ICE_MEDIA_UNKNOWN; | |
198 | } | |
199 | ||
200 | /** | |
201 | * ice_aq_get_link_info | |
202 | * @pi: port information structure | |
203 | * @ena_lse: enable/disable LinkStatusEvent reporting | |
204 | * @link: pointer to link status structure - optional | |
205 | * @cd: pointer to command details structure or NULL | |
206 | * | |
207 | * Get Link Status (0x607). Returns the link status of the adapter. | |
208 | */ | |
209 | enum ice_status | |
210 | ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, | |
211 | struct ice_link_status *link, struct ice_sq_cd *cd) | |
212 | { | |
213 | struct ice_link_status *hw_link_info_old, *hw_link_info; | |
214 | struct ice_aqc_get_link_status_data link_data = { 0 }; | |
215 | struct ice_aqc_get_link_status *resp; | |
216 | enum ice_media_type *hw_media_type; | |
217 | struct ice_fc_info *hw_fc_info; | |
218 | bool tx_pause, rx_pause; | |
219 | struct ice_aq_desc desc; | |
220 | enum ice_status status; | |
221 | u16 cmd_flags; | |
222 | ||
223 | if (!pi) | |
224 | return ICE_ERR_PARAM; | |
225 | hw_link_info_old = &pi->phy.link_info_old; | |
226 | hw_media_type = &pi->phy.media_type; | |
227 | hw_link_info = &pi->phy.link_info; | |
228 | hw_fc_info = &pi->fc; | |
229 | ||
230 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); | |
231 | cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; | |
232 | resp = &desc.params.get_link_status; | |
233 | resp->cmd_flags = cpu_to_le16(cmd_flags); | |
234 | resp->lport_num = pi->lport; | |
235 | ||
236 | status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data), | |
237 | cd); | |
238 | ||
239 | if (status) | |
240 | return status; | |
241 | ||
242 | /* save off old link status information */ | |
243 | *hw_link_info_old = *hw_link_info; | |
244 | ||
245 | /* update current link status information */ | |
246 | hw_link_info->link_speed = le16_to_cpu(link_data.link_speed); | |
247 | hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low); | |
248 | *hw_media_type = ice_get_media_type(pi); | |
249 | hw_link_info->link_info = link_data.link_info; | |
250 | hw_link_info->an_info = link_data.an_info; | |
251 | hw_link_info->ext_info = link_data.ext_info; | |
252 | hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size); | |
253 | hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M; | |
254 | ||
255 | /* update fc info */ | |
256 | tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); | |
257 | rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); | |
258 | if (tx_pause && rx_pause) | |
259 | hw_fc_info->current_mode = ICE_FC_FULL; | |
260 | else if (tx_pause) | |
261 | hw_fc_info->current_mode = ICE_FC_TX_PAUSE; | |
262 | else if (rx_pause) | |
263 | hw_fc_info->current_mode = ICE_FC_RX_PAUSE; | |
264 | else | |
265 | hw_fc_info->current_mode = ICE_FC_NONE; | |
266 | ||
267 | hw_link_info->lse_ena = | |
268 | !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); | |
269 | ||
270 | /* save link status information */ | |
271 | if (link) | |
272 | *link = *hw_link_info; | |
273 | ||
274 | /* flag cleared so calling functions don't call AQ again */ | |
275 | pi->phy.get_link_info = false; | |
276 | ||
277 | return status; | |
278 | } | |
279 | ||
cdedef59 AV |
280 | /** |
281 | * ice_init_flex_parser - initialize rx flex parser | |
282 | * @hw: pointer to the hardware structure | |
283 | * | |
284 | * Function to initialize flex descriptors | |
285 | */ | |
286 | static void ice_init_flex_parser(struct ice_hw *hw) | |
287 | { | |
288 | u8 idx = 0; | |
289 | ||
290 | ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_LOW, 0); | |
291 | ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_HIGH, 1); | |
292 | ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_LOWER, 2); | |
293 | ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_HIGH, 3); | |
294 | ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_FRG, ICE_RXFLG_UDP_GRE, | |
295 | ICE_RXFLG_PKT_DSI, ICE_RXFLG_FIN, idx++); | |
296 | ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_SYN, ICE_RXFLG_RST, | |
297 | ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++); | |
298 | ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, | |
299 | ICE_RXFLG_EVLAN_x8100, ICE_RXFLG_EVLAN_x9100, | |
300 | idx++); | |
301 | ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_VLAN_x8100, ICE_RXFLG_TNL_VLAN, | |
302 | ICE_RXFLG_TNL_MAC, ICE_RXFLG_TNL0, idx++); | |
303 | ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2, | |
304 | ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx); | |
305 | } | |
306 | ||
9daf8208 AV |
307 | /** |
308 | * ice_init_fltr_mgmt_struct - initializes filter management list and locks | |
309 | * @hw: pointer to the hw struct | |
310 | */ | |
311 | static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) | |
312 | { | |
313 | struct ice_switch_info *sw; | |
314 | ||
315 | hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), | |
316 | sizeof(*hw->switch_info), GFP_KERNEL); | |
317 | sw = hw->switch_info; | |
318 | ||
319 | if (!sw) | |
320 | return ICE_ERR_NO_MEMORY; | |
321 | ||
322 | INIT_LIST_HEAD(&sw->vsi_list_map_head); | |
323 | ||
324 | mutex_init(&sw->mac_list_lock); | |
325 | INIT_LIST_HEAD(&sw->mac_list_head); | |
326 | ||
327 | mutex_init(&sw->vlan_list_lock); | |
328 | INIT_LIST_HEAD(&sw->vlan_list_head); | |
329 | ||
330 | mutex_init(&sw->eth_m_list_lock); | |
331 | INIT_LIST_HEAD(&sw->eth_m_list_head); | |
332 | ||
333 | mutex_init(&sw->promisc_list_lock); | |
334 | INIT_LIST_HEAD(&sw->promisc_list_head); | |
335 | ||
336 | mutex_init(&sw->mac_vlan_list_lock); | |
337 | INIT_LIST_HEAD(&sw->mac_vlan_list_head); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | /** | |
343 | * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks | |
344 | * @hw: pointer to the hw struct | |
345 | */ | |
346 | static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) | |
347 | { | |
348 | struct ice_switch_info *sw = hw->switch_info; | |
349 | struct ice_vsi_list_map_info *v_pos_map; | |
350 | struct ice_vsi_list_map_info *v_tmp_map; | |
351 | ||
352 | list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, | |
353 | list_entry) { | |
354 | list_del(&v_pos_map->list_entry); | |
355 | devm_kfree(ice_hw_to_dev(hw), v_pos_map); | |
356 | } | |
357 | ||
358 | mutex_destroy(&sw->mac_list_lock); | |
359 | mutex_destroy(&sw->vlan_list_lock); | |
360 | mutex_destroy(&sw->eth_m_list_lock); | |
361 | mutex_destroy(&sw->promisc_list_lock); | |
362 | mutex_destroy(&sw->mac_vlan_list_lock); | |
363 | ||
364 | devm_kfree(ice_hw_to_dev(hw), sw); | |
365 | } | |
366 | ||
f31e4b6f AV |
367 | /** |
368 | * ice_init_hw - main hardware initialization routine | |
369 | * @hw: pointer to the hardware structure | |
370 | */ | |
371 | enum ice_status ice_init_hw(struct ice_hw *hw) | |
372 | { | |
dc49c772 | 373 | struct ice_aqc_get_phy_caps_data *pcaps; |
f31e4b6f | 374 | enum ice_status status; |
dc49c772 AV |
375 | u16 mac_buf_len; |
376 | void *mac_buf; | |
f31e4b6f AV |
377 | |
378 | /* Set MAC type based on DeviceID */ | |
379 | status = ice_set_mac_type(hw); | |
380 | if (status) | |
381 | return status; | |
382 | ||
383 | hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & | |
384 | PF_FUNC_RID_FUNC_NUM_M) >> | |
385 | PF_FUNC_RID_FUNC_NUM_S; | |
386 | ||
387 | status = ice_reset(hw, ICE_RESET_PFR); | |
388 | if (status) | |
389 | return status; | |
390 | ||
940b61af AV |
391 | /* set these values to minimum allowed */ |
392 | hw->itr_gran_200 = ICE_ITR_GRAN_MIN_200; | |
393 | hw->itr_gran_100 = ICE_ITR_GRAN_MIN_100; | |
394 | hw->itr_gran_50 = ICE_ITR_GRAN_MIN_50; | |
395 | hw->itr_gran_25 = ICE_ITR_GRAN_MIN_25; | |
396 | ||
f31e4b6f AV |
397 | status = ice_init_all_ctrlq(hw); |
398 | if (status) | |
399 | goto err_unroll_cqinit; | |
400 | ||
401 | status = ice_clear_pf_cfg(hw); | |
402 | if (status) | |
403 | goto err_unroll_cqinit; | |
404 | ||
405 | ice_clear_pxe_mode(hw); | |
406 | ||
407 | status = ice_init_nvm(hw); | |
408 | if (status) | |
409 | goto err_unroll_cqinit; | |
410 | ||
9c20346b AV |
411 | status = ice_get_caps(hw); |
412 | if (status) | |
413 | goto err_unroll_cqinit; | |
414 | ||
415 | hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), | |
416 | sizeof(*hw->port_info), GFP_KERNEL); | |
417 | if (!hw->port_info) { | |
418 | status = ICE_ERR_NO_MEMORY; | |
419 | goto err_unroll_cqinit; | |
420 | } | |
421 | ||
422 | /* set the back pointer to hw */ | |
423 | hw->port_info->hw = hw; | |
424 | ||
425 | /* Initialize port_info struct with switch configuration data */ | |
426 | status = ice_get_initial_sw_cfg(hw); | |
427 | if (status) | |
428 | goto err_unroll_alloc; | |
429 | ||
9daf8208 AV |
430 | hw->evb_veb = true; |
431 | ||
9c20346b AV |
432 | /* Query the allocated resources for tx scheduler */ |
433 | status = ice_sched_query_res_alloc(hw); | |
434 | if (status) { | |
435 | ice_debug(hw, ICE_DBG_SCHED, | |
436 | "Failed to get scheduler allocated resources\n"); | |
437 | goto err_unroll_alloc; | |
438 | } | |
439 | ||
dc49c772 AV |
440 | /* Initialize port_info struct with scheduler data */ |
441 | status = ice_sched_init_port(hw->port_info); | |
442 | if (status) | |
443 | goto err_unroll_sched; | |
444 | ||
445 | pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); | |
446 | if (!pcaps) { | |
447 | status = ICE_ERR_NO_MEMORY; | |
448 | goto err_unroll_sched; | |
449 | } | |
450 | ||
451 | /* Initialize port_info struct with PHY capabilities */ | |
452 | status = ice_aq_get_phy_caps(hw->port_info, false, | |
453 | ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); | |
454 | devm_kfree(ice_hw_to_dev(hw), pcaps); | |
455 | if (status) | |
456 | goto err_unroll_sched; | |
457 | ||
458 | /* Initialize port_info struct with link information */ | |
459 | status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); | |
460 | if (status) | |
461 | goto err_unroll_sched; | |
462 | ||
9daf8208 AV |
463 | status = ice_init_fltr_mgmt_struct(hw); |
464 | if (status) | |
465 | goto err_unroll_sched; | |
466 | ||
dc49c772 AV |
467 | /* Get port MAC information */ |
468 | mac_buf_len = sizeof(struct ice_aqc_manage_mac_read_resp); | |
469 | mac_buf = devm_kzalloc(ice_hw_to_dev(hw), mac_buf_len, GFP_KERNEL); | |
470 | ||
471 | if (!mac_buf) | |
9daf8208 | 472 | goto err_unroll_fltr_mgmt_struct; |
dc49c772 AV |
473 | |
474 | status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); | |
475 | devm_kfree(ice_hw_to_dev(hw), mac_buf); | |
476 | ||
477 | if (status) | |
9daf8208 | 478 | goto err_unroll_fltr_mgmt_struct; |
dc49c772 | 479 | |
cdedef59 AV |
480 | ice_init_flex_parser(hw); |
481 | ||
f31e4b6f AV |
482 | return 0; |
483 | ||
9daf8208 AV |
484 | err_unroll_fltr_mgmt_struct: |
485 | ice_cleanup_fltr_mgmt_struct(hw); | |
dc49c772 AV |
486 | err_unroll_sched: |
487 | ice_sched_cleanup_all(hw); | |
9c20346b AV |
488 | err_unroll_alloc: |
489 | devm_kfree(ice_hw_to_dev(hw), hw->port_info); | |
f31e4b6f AV |
490 | err_unroll_cqinit: |
491 | ice_shutdown_all_ctrlq(hw); | |
492 | return status; | |
493 | } | |
494 | ||
495 | /** | |
496 | * ice_deinit_hw - unroll initialization operations done by ice_init_hw | |
497 | * @hw: pointer to the hardware structure | |
498 | */ | |
499 | void ice_deinit_hw(struct ice_hw *hw) | |
500 | { | |
9c20346b | 501 | ice_sched_cleanup_all(hw); |
f31e4b6f | 502 | ice_shutdown_all_ctrlq(hw); |
dc49c772 | 503 | |
9c20346b AV |
504 | if (hw->port_info) { |
505 | devm_kfree(ice_hw_to_dev(hw), hw->port_info); | |
506 | hw->port_info = NULL; | |
507 | } | |
9daf8208 AV |
508 | |
509 | ice_cleanup_fltr_mgmt_struct(hw); | |
f31e4b6f AV |
510 | } |
511 | ||
512 | /** | |
513 | * ice_check_reset - Check to see if a global reset is complete | |
514 | * @hw: pointer to the hardware structure | |
515 | */ | |
516 | enum ice_status ice_check_reset(struct ice_hw *hw) | |
517 | { | |
518 | u32 cnt, reg = 0, grst_delay; | |
519 | ||
520 | /* Poll for Device Active state in case a recent CORER, GLOBR, | |
521 | * or EMPR has occurred. The grst delay value is in 100ms units. | |
522 | * Add 1sec for outstanding AQ commands that can take a long time. | |
523 | */ | |
524 | grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> | |
525 | GLGEN_RSTCTL_GRSTDEL_S) + 10; | |
526 | ||
527 | for (cnt = 0; cnt < grst_delay; cnt++) { | |
528 | mdelay(100); | |
529 | reg = rd32(hw, GLGEN_RSTAT); | |
530 | if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) | |
531 | break; | |
532 | } | |
533 | ||
534 | if (cnt == grst_delay) { | |
535 | ice_debug(hw, ICE_DBG_INIT, | |
536 | "Global reset polling failed to complete.\n"); | |
537 | return ICE_ERR_RESET_FAILED; | |
538 | } | |
539 | ||
540 | #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ | |
541 | GLNVM_ULD_GLOBR_DONE_M) | |
542 | ||
543 | /* Device is Active; check Global Reset processes are done */ | |
544 | for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { | |
545 | reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; | |
546 | if (reg == ICE_RESET_DONE_MASK) { | |
547 | ice_debug(hw, ICE_DBG_INIT, | |
548 | "Global reset processes done. %d\n", cnt); | |
549 | break; | |
550 | } | |
551 | mdelay(10); | |
552 | } | |
553 | ||
554 | if (cnt == ICE_PF_RESET_WAIT_COUNT) { | |
555 | ice_debug(hw, ICE_DBG_INIT, | |
556 | "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", | |
557 | reg); | |
558 | return ICE_ERR_RESET_FAILED; | |
559 | } | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | /** | |
565 | * ice_pf_reset - Reset the PF | |
566 | * @hw: pointer to the hardware structure | |
567 | * | |
568 | * If a global reset has been triggered, this function checks | |
569 | * for its completion and then issues the PF reset | |
570 | */ | |
571 | static enum ice_status ice_pf_reset(struct ice_hw *hw) | |
572 | { | |
573 | u32 cnt, reg; | |
574 | ||
575 | /* If at function entry a global reset was already in progress, i.e. | |
576 | * state is not 'device active' or any of the reset done bits are not | |
577 | * set in GLNVM_ULD, there is no need for a PF Reset; poll until the | |
578 | * global reset is done. | |
579 | */ | |
580 | if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || | |
581 | (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { | |
582 | /* poll on global reset currently in progress until done */ | |
583 | if (ice_check_reset(hw)) | |
584 | return ICE_ERR_RESET_FAILED; | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | /* Reset the PF */ | |
590 | reg = rd32(hw, PFGEN_CTRL); | |
591 | ||
592 | wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); | |
593 | ||
594 | for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { | |
595 | reg = rd32(hw, PFGEN_CTRL); | |
596 | if (!(reg & PFGEN_CTRL_PFSWR_M)) | |
597 | break; | |
598 | ||
599 | mdelay(1); | |
600 | } | |
601 | ||
602 | if (cnt == ICE_PF_RESET_WAIT_COUNT) { | |
603 | ice_debug(hw, ICE_DBG_INIT, | |
604 | "PF reset polling failed to complete.\n"); | |
605 | return ICE_ERR_RESET_FAILED; | |
606 | } | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | /** | |
612 | * ice_reset - Perform different types of reset | |
613 | * @hw: pointer to the hardware structure | |
614 | * @req: reset request | |
615 | * | |
616 | * This function triggers a reset as specified by the req parameter. | |
617 | * | |
618 | * Note: | |
619 | * If anything other than a PF reset is triggered, PXE mode is restored. | |
620 | * This has to be cleared using ice_clear_pxe_mode again, once the AQ | |
621 | * interface has been restored in the rebuild flow. | |
622 | */ | |
623 | enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) | |
624 | { | |
625 | u32 val = 0; | |
626 | ||
627 | switch (req) { | |
628 | case ICE_RESET_PFR: | |
629 | return ice_pf_reset(hw); | |
630 | case ICE_RESET_CORER: | |
631 | ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); | |
632 | val = GLGEN_RTRIG_CORER_M; | |
633 | break; | |
634 | case ICE_RESET_GLOBR: | |
635 | ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); | |
636 | val = GLGEN_RTRIG_GLOBR_M; | |
637 | break; | |
638 | } | |
639 | ||
640 | val |= rd32(hw, GLGEN_RTRIG); | |
641 | wr32(hw, GLGEN_RTRIG, val); | |
642 | ice_flush(hw); | |
643 | ||
644 | /* wait for the FW to be ready */ | |
645 | return ice_check_reset(hw); | |
646 | } | |
647 | ||
cdedef59 AV |
648 | /** |
649 | * ice_copy_rxq_ctx_to_hw | |
650 | * @hw: pointer to the hardware structure | |
651 | * @ice_rxq_ctx: pointer to the rxq context | |
652 | * @rxq_index: the index of the rx queue | |
653 | * | |
654 | * Copies rxq context from dense structure to hw register space | |
655 | */ | |
656 | static enum ice_status | |
657 | ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) | |
658 | { | |
659 | u8 i; | |
660 | ||
661 | if (!ice_rxq_ctx) | |
662 | return ICE_ERR_BAD_PTR; | |
663 | ||
664 | if (rxq_index > QRX_CTRL_MAX_INDEX) | |
665 | return ICE_ERR_PARAM; | |
666 | ||
667 | /* Copy each dword separately to hw */ | |
668 | for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { | |
669 | wr32(hw, QRX_CONTEXT(i, rxq_index), | |
670 | *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); | |
671 | ||
672 | ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, | |
673 | *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); | |
674 | } | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
679 | /* LAN Rx Queue Context */ | |
680 | static const struct ice_ctx_ele ice_rlan_ctx_info[] = { | |
681 | /* Field Width LSB */ | |
682 | ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), | |
683 | ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), | |
684 | ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), | |
685 | ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), | |
686 | ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), | |
687 | ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), | |
688 | ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), | |
689 | ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), | |
690 | ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), | |
691 | ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), | |
692 | ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), | |
693 | ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), | |
694 | ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), | |
695 | ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), | |
696 | ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), | |
697 | ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), | |
698 | ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), | |
699 | ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), | |
700 | ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), | |
701 | { 0 } | |
702 | }; | |
703 | ||
704 | /** | |
705 | * ice_write_rxq_ctx | |
706 | * @hw: pointer to the hardware structure | |
707 | * @rlan_ctx: pointer to the rxq context | |
708 | * @rxq_index: the index of the rx queue | |
709 | * | |
710 | * Converts rxq context from sparse to dense structure and then writes | |
711 | * it to hw register space | |
712 | */ | |
713 | enum ice_status | |
714 | ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, | |
715 | u32 rxq_index) | |
716 | { | |
717 | u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; | |
718 | ||
719 | ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); | |
720 | return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); | |
721 | } | |
722 | ||
723 | /* LAN Tx Queue Context */ | |
724 | const struct ice_ctx_ele ice_tlan_ctx_info[] = { | |
725 | /* Field Width LSB */ | |
726 | ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), | |
727 | ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), | |
728 | ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), | |
729 | ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), | |
730 | ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), | |
731 | ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), | |
732 | ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), | |
733 | ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), | |
734 | ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), | |
735 | ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), | |
736 | ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), | |
737 | ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), | |
738 | ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), | |
739 | ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), | |
740 | ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), | |
741 | ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), | |
742 | ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), | |
743 | ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), | |
744 | ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), | |
745 | ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), | |
746 | ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), | |
747 | ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), | |
748 | ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), | |
749 | ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), | |
750 | ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), | |
751 | ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), | |
752 | ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171), | |
753 | { 0 } | |
754 | }; | |
755 | ||
7ec59eea AV |
756 | /** |
757 | * ice_debug_cq | |
758 | * @hw: pointer to the hardware structure | |
759 | * @mask: debug mask | |
760 | * @desc: pointer to control queue descriptor | |
761 | * @buf: pointer to command buffer | |
762 | * @buf_len: max length of buf | |
763 | * | |
764 | * Dumps debug log about control command with descriptor contents. | |
765 | */ | |
766 | void ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, | |
767 | void *buf, u16 buf_len) | |
768 | { | |
769 | struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; | |
770 | u16 len; | |
771 | ||
772 | #ifndef CONFIG_DYNAMIC_DEBUG | |
773 | if (!(mask & hw->debug_mask)) | |
774 | return; | |
775 | #endif | |
776 | ||
777 | if (!desc) | |
778 | return; | |
779 | ||
780 | len = le16_to_cpu(cq_desc->datalen); | |
781 | ||
782 | ice_debug(hw, mask, | |
783 | "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", | |
784 | le16_to_cpu(cq_desc->opcode), | |
785 | le16_to_cpu(cq_desc->flags), | |
786 | le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval)); | |
787 | ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", | |
788 | le32_to_cpu(cq_desc->cookie_high), | |
789 | le32_to_cpu(cq_desc->cookie_low)); | |
790 | ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", | |
791 | le32_to_cpu(cq_desc->params.generic.param0), | |
792 | le32_to_cpu(cq_desc->params.generic.param1)); | |
793 | ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", | |
794 | le32_to_cpu(cq_desc->params.generic.addr_high), | |
795 | le32_to_cpu(cq_desc->params.generic.addr_low)); | |
796 | if (buf && cq_desc->datalen != 0) { | |
797 | ice_debug(hw, mask, "Buffer:\n"); | |
798 | if (buf_len < len) | |
799 | len = buf_len; | |
800 | ||
801 | ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); | |
802 | } | |
803 | } | |
804 | ||
805 | /* FW Admin Queue command wrappers */ | |
806 | ||
807 | /** | |
808 | * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue | |
809 | * @hw: pointer to the hw struct | |
810 | * @desc: descriptor describing the command | |
811 | * @buf: buffer to use for indirect commands (NULL for direct commands) | |
812 | * @buf_size: size of buffer for indirect commands (0 for direct commands) | |
813 | * @cd: pointer to command details structure | |
814 | * | |
815 | * Helper function to send FW Admin Queue commands to the FW Admin Queue. | |
816 | */ | |
817 | enum ice_status | |
818 | ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, | |
819 | u16 buf_size, struct ice_sq_cd *cd) | |
820 | { | |
821 | return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); | |
822 | } | |
823 | ||
824 | /** | |
825 | * ice_aq_get_fw_ver | |
826 | * @hw: pointer to the hw struct | |
827 | * @cd: pointer to command details structure or NULL | |
828 | * | |
829 | * Get the firmware version (0x0001) from the admin queue commands | |
830 | */ | |
831 | enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) | |
832 | { | |
833 | struct ice_aqc_get_ver *resp; | |
834 | struct ice_aq_desc desc; | |
835 | enum ice_status status; | |
836 | ||
837 | resp = &desc.params.get_ver; | |
838 | ||
839 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); | |
840 | ||
841 | status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
842 | ||
843 | if (!status) { | |
844 | hw->fw_branch = resp->fw_branch; | |
845 | hw->fw_maj_ver = resp->fw_major; | |
846 | hw->fw_min_ver = resp->fw_minor; | |
847 | hw->fw_patch = resp->fw_patch; | |
848 | hw->fw_build = le32_to_cpu(resp->fw_build); | |
849 | hw->api_branch = resp->api_branch; | |
850 | hw->api_maj_ver = resp->api_major; | |
851 | hw->api_min_ver = resp->api_minor; | |
852 | hw->api_patch = resp->api_patch; | |
853 | } | |
854 | ||
855 | return status; | |
856 | } | |
857 | ||
858 | /** | |
859 | * ice_aq_q_shutdown | |
860 | * @hw: pointer to the hw struct | |
861 | * @unloading: is the driver unloading itself | |
862 | * | |
863 | * Tell the Firmware that we're shutting down the AdminQ and whether | |
864 | * or not the driver is unloading as well (0x0003). | |
865 | */ | |
866 | enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) | |
867 | { | |
868 | struct ice_aqc_q_shutdown *cmd; | |
869 | struct ice_aq_desc desc; | |
870 | ||
871 | cmd = &desc.params.q_shutdown; | |
872 | ||
873 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); | |
874 | ||
875 | if (unloading) | |
876 | cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING); | |
877 | ||
878 | return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); | |
879 | } | |
f31e4b6f AV |
880 | |
881 | /** | |
882 | * ice_aq_req_res | |
883 | * @hw: pointer to the hw struct | |
884 | * @res: resource id | |
885 | * @access: access type | |
886 | * @sdp_number: resource number | |
887 | * @timeout: the maximum time in ms that the driver may hold the resource | |
888 | * @cd: pointer to command details structure or NULL | |
889 | * | |
890 | * requests common resource using the admin queue commands (0x0008) | |
891 | */ | |
892 | static enum ice_status | |
893 | ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, | |
894 | enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, | |
895 | struct ice_sq_cd *cd) | |
896 | { | |
897 | struct ice_aqc_req_res *cmd_resp; | |
898 | struct ice_aq_desc desc; | |
899 | enum ice_status status; | |
900 | ||
901 | cmd_resp = &desc.params.res_owner; | |
902 | ||
903 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); | |
904 | ||
905 | cmd_resp->res_id = cpu_to_le16(res); | |
906 | cmd_resp->access_type = cpu_to_le16(access); | |
907 | cmd_resp->res_number = cpu_to_le32(sdp_number); | |
908 | ||
909 | status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
910 | /* The completion specifies the maximum time in ms that the driver | |
911 | * may hold the resource in the Timeout field. | |
912 | * If the resource is held by someone else, the command completes with | |
913 | * busy return value and the timeout field indicates the maximum time | |
914 | * the current owner of the resource has to free it. | |
915 | */ | |
916 | if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) | |
917 | *timeout = le32_to_cpu(cmd_resp->timeout); | |
918 | ||
919 | return status; | |
920 | } | |
921 | ||
922 | /** | |
923 | * ice_aq_release_res | |
924 | * @hw: pointer to the hw struct | |
925 | * @res: resource id | |
926 | * @sdp_number: resource number | |
927 | * @cd: pointer to command details structure or NULL | |
928 | * | |
929 | * release common resource using the admin queue commands (0x0009) | |
930 | */ | |
931 | static enum ice_status | |
932 | ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, | |
933 | struct ice_sq_cd *cd) | |
934 | { | |
935 | struct ice_aqc_req_res *cmd; | |
936 | struct ice_aq_desc desc; | |
937 | ||
938 | cmd = &desc.params.res_owner; | |
939 | ||
940 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); | |
941 | ||
942 | cmd->res_id = cpu_to_le16(res); | |
943 | cmd->res_number = cpu_to_le32(sdp_number); | |
944 | ||
945 | return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | |
946 | } | |
947 | ||
948 | /** | |
949 | * ice_acquire_res | |
950 | * @hw: pointer to the HW structure | |
951 | * @res: resource id | |
952 | * @access: access type (read or write) | |
953 | * | |
954 | * This function will attempt to acquire the ownership of a resource. | |
955 | */ | |
956 | enum ice_status | |
957 | ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, | |
958 | enum ice_aq_res_access_type access) | |
959 | { | |
960 | #define ICE_RES_POLLING_DELAY_MS 10 | |
961 | u32 delay = ICE_RES_POLLING_DELAY_MS; | |
962 | enum ice_status status; | |
963 | u32 time_left = 0; | |
964 | u32 timeout; | |
965 | ||
966 | status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); | |
967 | ||
968 | /* An admin queue return code of ICE_AQ_RC_EEXIST means that another | |
969 | * driver has previously acquired the resource and performed any | |
970 | * necessary updates; in this case the caller does not obtain the | |
971 | * resource and has no further work to do. | |
972 | */ | |
973 | if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) { | |
974 | status = ICE_ERR_AQ_NO_WORK; | |
975 | goto ice_acquire_res_exit; | |
976 | } | |
977 | ||
978 | if (status) | |
979 | ice_debug(hw, ICE_DBG_RES, | |
980 | "resource %d acquire type %d failed.\n", res, access); | |
981 | ||
982 | /* If necessary, poll until the current lock owner timeouts */ | |
983 | timeout = time_left; | |
984 | while (status && timeout && time_left) { | |
985 | mdelay(delay); | |
986 | timeout = (timeout > delay) ? timeout - delay : 0; | |
987 | status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); | |
988 | ||
989 | if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) { | |
990 | /* lock free, but no work to do */ | |
991 | status = ICE_ERR_AQ_NO_WORK; | |
992 | break; | |
993 | } | |
994 | ||
995 | if (!status) | |
996 | /* lock acquired */ | |
997 | break; | |
998 | } | |
999 | if (status && status != ICE_ERR_AQ_NO_WORK) | |
1000 | ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); | |
1001 | ||
1002 | ice_acquire_res_exit: | |
1003 | if (status == ICE_ERR_AQ_NO_WORK) { | |
1004 | if (access == ICE_RES_WRITE) | |
1005 | ice_debug(hw, ICE_DBG_RES, | |
1006 | "resource indicates no work to do.\n"); | |
1007 | else | |
1008 | ice_debug(hw, ICE_DBG_RES, | |
1009 | "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); | |
1010 | } | |
1011 | return status; | |
1012 | } | |
1013 | ||
1014 | /** | |
1015 | * ice_release_res | |
1016 | * @hw: pointer to the HW structure | |
1017 | * @res: resource id | |
1018 | * | |
1019 | * This function will release a resource using the proper Admin Command. | |
1020 | */ | |
1021 | void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) | |
1022 | { | |
1023 | enum ice_status status; | |
1024 | u32 total_delay = 0; | |
1025 | ||
1026 | status = ice_aq_release_res(hw, res, 0, NULL); | |
1027 | ||
1028 | /* there are some rare cases when trying to release the resource | |
1029 | * results in an admin Q timeout, so handle them correctly | |
1030 | */ | |
1031 | while ((status == ICE_ERR_AQ_TIMEOUT) && | |
1032 | (total_delay < hw->adminq.sq_cmd_timeout)) { | |
1033 | mdelay(1); | |
1034 | status = ice_aq_release_res(hw, res, 0, NULL); | |
1035 | total_delay++; | |
1036 | } | |
1037 | } | |
1038 | ||
9c20346b AV |
1039 | /** |
1040 | * ice_parse_caps - parse function/device capabilities | |
1041 | * @hw: pointer to the hw struct | |
1042 | * @buf: pointer to a buffer containing function/device capability records | |
1043 | * @cap_count: number of capability records in the list | |
1044 | * @opc: type of capabilities list to parse | |
1045 | * | |
1046 | * Helper function to parse function(0x000a)/device(0x000b) capabilities list. | |
1047 | */ | |
1048 | static void | |
1049 | ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, | |
1050 | enum ice_adminq_opc opc) | |
1051 | { | |
1052 | struct ice_aqc_list_caps_elem *cap_resp; | |
1053 | struct ice_hw_func_caps *func_p = NULL; | |
1054 | struct ice_hw_dev_caps *dev_p = NULL; | |
1055 | struct ice_hw_common_caps *caps; | |
1056 | u32 i; | |
1057 | ||
1058 | if (!buf) | |
1059 | return; | |
1060 | ||
1061 | cap_resp = (struct ice_aqc_list_caps_elem *)buf; | |
1062 | ||
1063 | if (opc == ice_aqc_opc_list_dev_caps) { | |
1064 | dev_p = &hw->dev_caps; | |
1065 | caps = &dev_p->common_cap; | |
1066 | } else if (opc == ice_aqc_opc_list_func_caps) { | |
1067 | func_p = &hw->func_caps; | |
1068 | caps = &func_p->common_cap; | |
1069 | } else { | |
1070 | ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); | |
1071 | return; | |
1072 | } | |
1073 | ||
1074 | for (i = 0; caps && i < cap_count; i++, cap_resp++) { | |
1075 | u32 logical_id = le32_to_cpu(cap_resp->logical_id); | |
1076 | u32 phys_id = le32_to_cpu(cap_resp->phys_id); | |
1077 | u32 number = le32_to_cpu(cap_resp->number); | |
1078 | u16 cap = le16_to_cpu(cap_resp->cap); | |
1079 | ||
1080 | switch (cap) { | |
1081 | case ICE_AQC_CAPS_VSI: | |
1082 | if (dev_p) { | |
1083 | dev_p->num_vsi_allocd_to_host = number; | |
1084 | ice_debug(hw, ICE_DBG_INIT, | |
1085 | "HW caps: Dev.VSI cnt = %d\n", | |
1086 | dev_p->num_vsi_allocd_to_host); | |
1087 | } else if (func_p) { | |
1088 | func_p->guaranteed_num_vsi = number; | |
1089 | ice_debug(hw, ICE_DBG_INIT, | |
1090 | "HW caps: Func.VSI cnt = %d\n", | |
1091 | func_p->guaranteed_num_vsi); | |
1092 | } | |
1093 | break; | |
1094 | case ICE_AQC_CAPS_RSS: | |
1095 | caps->rss_table_size = number; | |
1096 | caps->rss_table_entry_width = logical_id; | |
1097 | ice_debug(hw, ICE_DBG_INIT, | |
1098 | "HW caps: RSS table size = %d\n", | |
1099 | caps->rss_table_size); | |
1100 | ice_debug(hw, ICE_DBG_INIT, | |
1101 | "HW caps: RSS table width = %d\n", | |
1102 | caps->rss_table_entry_width); | |
1103 | break; | |
1104 | case ICE_AQC_CAPS_RXQS: | |
1105 | caps->num_rxq = number; | |
1106 | caps->rxq_first_id = phys_id; | |
1107 | ice_debug(hw, ICE_DBG_INIT, | |
1108 | "HW caps: Num Rx Qs = %d\n", caps->num_rxq); | |
1109 | ice_debug(hw, ICE_DBG_INIT, | |
1110 | "HW caps: Rx first queue ID = %d\n", | |
1111 | caps->rxq_first_id); | |
1112 | break; | |
1113 | case ICE_AQC_CAPS_TXQS: | |
1114 | caps->num_txq = number; | |
1115 | caps->txq_first_id = phys_id; | |
1116 | ice_debug(hw, ICE_DBG_INIT, | |
1117 | "HW caps: Num Tx Qs = %d\n", caps->num_txq); | |
1118 | ice_debug(hw, ICE_DBG_INIT, | |
1119 | "HW caps: Tx first queue ID = %d\n", | |
1120 | caps->txq_first_id); | |
1121 | break; | |
1122 | case ICE_AQC_CAPS_MSIX: | |
1123 | caps->num_msix_vectors = number; | |
1124 | caps->msix_vector_first_id = phys_id; | |
1125 | ice_debug(hw, ICE_DBG_INIT, | |
1126 | "HW caps: MSIX vector count = %d\n", | |
1127 | caps->num_msix_vectors); | |
1128 | ice_debug(hw, ICE_DBG_INIT, | |
1129 | "HW caps: MSIX first vector index = %d\n", | |
1130 | caps->msix_vector_first_id); | |
1131 | break; | |
1132 | case ICE_AQC_CAPS_MAX_MTU: | |
1133 | caps->max_mtu = number; | |
1134 | if (dev_p) | |
1135 | ice_debug(hw, ICE_DBG_INIT, | |
1136 | "HW caps: Dev.MaxMTU = %d\n", | |
1137 | caps->max_mtu); | |
1138 | else if (func_p) | |
1139 | ice_debug(hw, ICE_DBG_INIT, | |
1140 | "HW caps: func.MaxMTU = %d\n", | |
1141 | caps->max_mtu); | |
1142 | break; | |
1143 | default: | |
1144 | ice_debug(hw, ICE_DBG_INIT, | |
1145 | "HW caps: Unknown capability[%d]: 0x%x\n", i, | |
1146 | cap); | |
1147 | break; | |
1148 | } | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | /** | |
1153 | * ice_aq_discover_caps - query function/device capabilities | |
1154 | * @hw: pointer to the hw struct | |
1155 | * @buf: a virtual buffer to hold the capabilities | |
1156 | * @buf_size: Size of the virtual buffer | |
1157 | * @data_size: Size of the returned data, or buf size needed if AQ err==ENOMEM | |
1158 | * @opc: capabilities type to discover - pass in the command opcode | |
1159 | * @cd: pointer to command details structure or NULL | |
1160 | * | |
1161 | * Get the function(0x000a)/device(0x000b) capabilities description from | |
1162 | * the firmware. | |
1163 | */ | |
1164 | static enum ice_status | |
1165 | ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u16 *data_size, | |
1166 | enum ice_adminq_opc opc, struct ice_sq_cd *cd) | |
1167 | { | |
1168 | struct ice_aqc_list_caps *cmd; | |
1169 | struct ice_aq_desc desc; | |
1170 | enum ice_status status; | |
1171 | ||
1172 | cmd = &desc.params.get_cap; | |
1173 | ||
1174 | if (opc != ice_aqc_opc_list_func_caps && | |
1175 | opc != ice_aqc_opc_list_dev_caps) | |
1176 | return ICE_ERR_PARAM; | |
1177 | ||
1178 | ice_fill_dflt_direct_cmd_desc(&desc, opc); | |
1179 | ||
1180 | status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); | |
1181 | if (!status) | |
1182 | ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); | |
1183 | *data_size = le16_to_cpu(desc.datalen); | |
1184 | ||
1185 | return status; | |
1186 | } | |
1187 | ||
1188 | /** | |
1189 | * ice_get_caps - get info about the HW | |
1190 | * @hw: pointer to the hardware structure | |
1191 | */ | |
1192 | enum ice_status ice_get_caps(struct ice_hw *hw) | |
1193 | { | |
1194 | enum ice_status status; | |
1195 | u16 data_size = 0; | |
1196 | u16 cbuf_len; | |
1197 | u8 retries; | |
1198 | ||
1199 | /* The driver doesn't know how many capabilities the device will return | |
1200 | * so the buffer size required isn't known ahead of time. The driver | |
1201 | * starts with cbuf_len and if this turns out to be insufficient, the | |
1202 | * device returns ICE_AQ_RC_ENOMEM and also the buffer size it needs. | |
1203 | * The driver then allocates the buffer of this size and retries the | |
1204 | * operation. So it follows that the retry count is 2. | |
1205 | */ | |
1206 | #define ICE_GET_CAP_BUF_COUNT 40 | |
1207 | #define ICE_GET_CAP_RETRY_COUNT 2 | |
1208 | ||
1209 | cbuf_len = ICE_GET_CAP_BUF_COUNT * | |
1210 | sizeof(struct ice_aqc_list_caps_elem); | |
1211 | ||
1212 | retries = ICE_GET_CAP_RETRY_COUNT; | |
1213 | ||
1214 | do { | |
1215 | void *cbuf; | |
1216 | ||
1217 | cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); | |
1218 | if (!cbuf) | |
1219 | return ICE_ERR_NO_MEMORY; | |
1220 | ||
1221 | status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &data_size, | |
1222 | ice_aqc_opc_list_func_caps, NULL); | |
1223 | devm_kfree(ice_hw_to_dev(hw), cbuf); | |
1224 | ||
1225 | if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) | |
1226 | break; | |
1227 | ||
1228 | /* If ENOMEM is returned, try again with bigger buffer */ | |
1229 | cbuf_len = data_size; | |
1230 | } while (--retries); | |
1231 | ||
1232 | return status; | |
1233 | } | |
1234 | ||
f31e4b6f AV |
1235 | /** |
1236 | * ice_aq_clear_pxe_mode | |
1237 | * @hw: pointer to the hw struct | |
1238 | * | |
1239 | * Tell the firmware that the driver is taking over from PXE (0x0110). | |
1240 | */ | |
1241 | static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) | |
1242 | { | |
1243 | struct ice_aq_desc desc; | |
1244 | ||
1245 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); | |
1246 | desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; | |
1247 | ||
1248 | return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); | |
1249 | } | |
1250 | ||
1251 | /** | |
1252 | * ice_clear_pxe_mode - clear pxe operations mode | |
1253 | * @hw: pointer to the hw struct | |
1254 | * | |
1255 | * Make sure all PXE mode settings are cleared, including things | |
1256 | * like descriptor fetch/write-back mode. | |
1257 | */ | |
1258 | void ice_clear_pxe_mode(struct ice_hw *hw) | |
1259 | { | |
1260 | if (ice_check_sq_alive(hw, &hw->adminq)) | |
1261 | ice_aq_clear_pxe_mode(hw); | |
1262 | } | |
cdedef59 | 1263 | |
fcea6f3d AV |
1264 | /** |
1265 | * ice_aq_set_phy_cfg | |
1266 | * @hw: pointer to the hw struct | |
1267 | * @lport: logical port number | |
1268 | * @cfg: structure with PHY configuration data to be set | |
1269 | * @cd: pointer to command details structure or NULL | |
1270 | * | |
1271 | * Set the various PHY configuration parameters supported on the Port. | |
1272 | * One or more of the Set PHY config parameters may be ignored in an MFP | |
1273 | * mode as the PF may not have the privilege to set some of the PHY Config | |
1274 | * parameters. This status will be indicated by the command response (0x0601). | |
1275 | */ | |
1276 | static enum ice_status | |
1277 | ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, | |
1278 | struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) | |
1279 | { | |
1280 | struct ice_aqc_set_phy_cfg *cmd; | |
1281 | struct ice_aq_desc desc; | |
1282 | ||
1283 | if (!cfg) | |
1284 | return ICE_ERR_PARAM; | |
1285 | ||
1286 | cmd = &desc.params.set_phy; | |
1287 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); | |
1288 | cmd->lport_num = lport; | |
1289 | ||
1290 | return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); | |
1291 | } | |
1292 | ||
1293 | /** | |
1294 | * ice_update_link_info - update status of the HW network link | |
1295 | * @pi: port info structure of the interested logical port | |
1296 | */ | |
1297 | static enum ice_status | |
1298 | ice_update_link_info(struct ice_port_info *pi) | |
1299 | { | |
1300 | struct ice_aqc_get_phy_caps_data *pcaps; | |
1301 | struct ice_phy_info *phy_info; | |
1302 | enum ice_status status; | |
1303 | struct ice_hw *hw; | |
1304 | ||
1305 | if (!pi) | |
1306 | return ICE_ERR_PARAM; | |
1307 | ||
1308 | hw = pi->hw; | |
1309 | ||
1310 | pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); | |
1311 | if (!pcaps) | |
1312 | return ICE_ERR_NO_MEMORY; | |
1313 | ||
1314 | phy_info = &pi->phy; | |
1315 | status = ice_aq_get_link_info(pi, true, NULL, NULL); | |
1316 | if (status) | |
1317 | goto out; | |
1318 | ||
1319 | if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) { | |
1320 | status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, | |
1321 | pcaps, NULL); | |
1322 | if (status) | |
1323 | goto out; | |
1324 | ||
1325 | memcpy(phy_info->link_info.module_type, &pcaps->module_type, | |
1326 | sizeof(phy_info->link_info.module_type)); | |
1327 | } | |
1328 | out: | |
1329 | devm_kfree(ice_hw_to_dev(hw), pcaps); | |
1330 | return status; | |
1331 | } | |
1332 | ||
1333 | /** | |
1334 | * ice_set_fc | |
1335 | * @pi: port information structure | |
1336 | * @aq_failures: pointer to status code, specific to ice_set_fc routine | |
1337 | * @atomic_restart: enable automatic link update | |
1338 | * | |
1339 | * Set the requested flow control mode. | |
1340 | */ | |
1341 | enum ice_status | |
1342 | ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool atomic_restart) | |
1343 | { | |
1344 | struct ice_aqc_set_phy_cfg_data cfg = { 0 }; | |
1345 | struct ice_aqc_get_phy_caps_data *pcaps; | |
1346 | enum ice_status status; | |
1347 | u8 pause_mask = 0x0; | |
1348 | struct ice_hw *hw; | |
1349 | ||
1350 | if (!pi) | |
1351 | return ICE_ERR_PARAM; | |
1352 | hw = pi->hw; | |
1353 | *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; | |
1354 | ||
1355 | switch (pi->fc.req_mode) { | |
1356 | case ICE_FC_FULL: | |
1357 | pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; | |
1358 | pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; | |
1359 | break; | |
1360 | case ICE_FC_RX_PAUSE: | |
1361 | pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; | |
1362 | break; | |
1363 | case ICE_FC_TX_PAUSE: | |
1364 | pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; | |
1365 | break; | |
1366 | default: | |
1367 | break; | |
1368 | } | |
1369 | ||
1370 | pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); | |
1371 | if (!pcaps) | |
1372 | return ICE_ERR_NO_MEMORY; | |
1373 | ||
1374 | /* Get the current phy config */ | |
1375 | status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, | |
1376 | NULL); | |
1377 | if (status) { | |
1378 | *aq_failures = ICE_SET_FC_AQ_FAIL_GET; | |
1379 | goto out; | |
1380 | } | |
1381 | ||
1382 | /* clear the old pause settings */ | |
1383 | cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | | |
1384 | ICE_AQC_PHY_EN_RX_LINK_PAUSE); | |
1385 | /* set the new capabilities */ | |
1386 | cfg.caps |= pause_mask; | |
1387 | /* If the capabilities have changed, then set the new config */ | |
1388 | if (cfg.caps != pcaps->caps) { | |
1389 | int retry_count, retry_max = 10; | |
1390 | ||
1391 | /* Auto restart link so settings take effect */ | |
1392 | if (atomic_restart) | |
1393 | cfg.caps |= ICE_AQ_PHY_ENA_ATOMIC_LINK; | |
1394 | /* Copy over all the old settings */ | |
1395 | cfg.phy_type_low = pcaps->phy_type_low; | |
1396 | cfg.low_power_ctrl = pcaps->low_power_ctrl; | |
1397 | cfg.eee_cap = pcaps->eee_cap; | |
1398 | cfg.eeer_value = pcaps->eeer_value; | |
1399 | cfg.link_fec_opt = pcaps->link_fec_options; | |
1400 | ||
1401 | status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); | |
1402 | if (status) { | |
1403 | *aq_failures = ICE_SET_FC_AQ_FAIL_SET; | |
1404 | goto out; | |
1405 | } | |
1406 | ||
1407 | /* Update the link info | |
1408 | * It sometimes takes a really long time for link to | |
1409 | * come back from the atomic reset. Thus, we wait a | |
1410 | * little bit. | |
1411 | */ | |
1412 | for (retry_count = 0; retry_count < retry_max; retry_count++) { | |
1413 | status = ice_update_link_info(pi); | |
1414 | ||
1415 | if (!status) | |
1416 | break; | |
1417 | ||
1418 | mdelay(100); | |
1419 | } | |
1420 | ||
1421 | if (status) | |
1422 | *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; | |
1423 | } | |
1424 | ||
1425 | out: | |
1426 | devm_kfree(ice_hw_to_dev(hw), pcaps); | |
1427 | return status; | |
1428 | } | |
1429 | ||
1430 | /** | |
1431 | * ice_aq_set_link_restart_an | |
1432 | * @pi: pointer to the port information structure | |
1433 | * @ena_link: if true: enable link, if false: disable link | |
1434 | * @cd: pointer to command details structure or NULL | |
1435 | * | |
1436 | * Sets up the link and restarts the Auto-Negotiation over the link. | |
1437 | */ | |
1438 | enum ice_status | |
1439 | ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, | |
1440 | struct ice_sq_cd *cd) | |
1441 | { | |
1442 | struct ice_aqc_restart_an *cmd; | |
1443 | struct ice_aq_desc desc; | |
1444 | ||
1445 | cmd = &desc.params.restart_an; | |
1446 | ||
1447 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); | |
1448 | ||
1449 | cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; | |
1450 | cmd->lport_num = pi->lport; | |
1451 | if (ena_link) | |
1452 | cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; | |
1453 | else | |
1454 | cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; | |
1455 | ||
1456 | return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); | |
1457 | } | |
1458 | ||
d76a60ba AV |
1459 | /** |
1460 | * __ice_aq_get_set_rss_lut | |
1461 | * @hw: pointer to the hardware structure | |
1462 | * @vsi_id: VSI FW index | |
1463 | * @lut_type: LUT table type | |
1464 | * @lut: pointer to the LUT buffer provided by the caller | |
1465 | * @lut_size: size of the LUT buffer | |
1466 | * @glob_lut_idx: global LUT index | |
1467 | * @set: set true to set the table, false to get the table | |
1468 | * | |
1469 | * Internal function to get (0x0B05) or set (0x0B03) RSS look up table | |
1470 | */ | |
1471 | static enum ice_status | |
1472 | __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, | |
1473 | u16 lut_size, u8 glob_lut_idx, bool set) | |
1474 | { | |
1475 | struct ice_aqc_get_set_rss_lut *cmd_resp; | |
1476 | struct ice_aq_desc desc; | |
1477 | enum ice_status status; | |
1478 | u16 flags = 0; | |
1479 | ||
1480 | cmd_resp = &desc.params.get_set_rss_lut; | |
1481 | ||
1482 | if (set) { | |
1483 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); | |
1484 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
1485 | } else { | |
1486 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); | |
1487 | } | |
1488 | ||
1489 | cmd_resp->vsi_id = cpu_to_le16(((vsi_id << | |
1490 | ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & | |
1491 | ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | | |
1492 | ICE_AQC_GSET_RSS_LUT_VSI_VALID); | |
1493 | ||
1494 | switch (lut_type) { | |
1495 | case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: | |
1496 | case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: | |
1497 | case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: | |
1498 | flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & | |
1499 | ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); | |
1500 | break; | |
1501 | default: | |
1502 | status = ICE_ERR_PARAM; | |
1503 | goto ice_aq_get_set_rss_lut_exit; | |
1504 | } | |
1505 | ||
1506 | if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { | |
1507 | flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & | |
1508 | ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); | |
1509 | ||
1510 | if (!set) | |
1511 | goto ice_aq_get_set_rss_lut_send; | |
1512 | } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { | |
1513 | if (!set) | |
1514 | goto ice_aq_get_set_rss_lut_send; | |
1515 | } else { | |
1516 | goto ice_aq_get_set_rss_lut_send; | |
1517 | } | |
1518 | ||
1519 | /* LUT size is only valid for Global and PF table types */ | |
1520 | if (lut_size == ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128) { | |
1521 | flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << | |
1522 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & | |
1523 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; | |
1524 | } else if (lut_size == ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512) { | |
1525 | flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << | |
1526 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & | |
1527 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; | |
1528 | } else if ((lut_size == ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) && | |
1529 | (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF)) { | |
1530 | flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << | |
1531 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & | |
1532 | ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; | |
1533 | } else { | |
1534 | status = ICE_ERR_PARAM; | |
1535 | goto ice_aq_get_set_rss_lut_exit; | |
1536 | } | |
1537 | ||
1538 | ice_aq_get_set_rss_lut_send: | |
1539 | cmd_resp->flags = cpu_to_le16(flags); | |
1540 | status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); | |
1541 | ||
1542 | ice_aq_get_set_rss_lut_exit: | |
1543 | return status; | |
1544 | } | |
1545 | ||
1546 | /** | |
1547 | * ice_aq_get_rss_lut | |
1548 | * @hw: pointer to the hardware structure | |
1549 | * @vsi_id: VSI FW index | |
1550 | * @lut_type: LUT table type | |
1551 | * @lut: pointer to the LUT buffer provided by the caller | |
1552 | * @lut_size: size of the LUT buffer | |
1553 | * | |
1554 | * get the RSS lookup table, PF or VSI type | |
1555 | */ | |
1556 | enum ice_status | |
1557 | ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, | |
1558 | u16 lut_size) | |
1559 | { | |
1560 | return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0, | |
1561 | false); | |
1562 | } | |
1563 | ||
1564 | /** | |
1565 | * ice_aq_set_rss_lut | |
1566 | * @hw: pointer to the hardware structure | |
1567 | * @vsi_id: VSI FW index | |
1568 | * @lut_type: LUT table type | |
1569 | * @lut: pointer to the LUT buffer provided by the caller | |
1570 | * @lut_size: size of the LUT buffer | |
1571 | * | |
1572 | * set the RSS lookup table, PF or VSI type | |
1573 | */ | |
1574 | enum ice_status | |
1575 | ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, | |
1576 | u16 lut_size) | |
1577 | { | |
1578 | return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0, | |
1579 | true); | |
1580 | } | |
1581 | ||
1582 | /** | |
1583 | * __ice_aq_get_set_rss_key | |
1584 | * @hw: pointer to the hw struct | |
1585 | * @vsi_id: VSI FW index | |
1586 | * @key: pointer to key info struct | |
1587 | * @set: set true to set the key, false to get the key | |
1588 | * | |
1589 | * get (0x0B04) or set (0x0B02) the RSS key per VSI | |
1590 | */ | |
1591 | static enum | |
1592 | ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, | |
1593 | struct ice_aqc_get_set_rss_keys *key, | |
1594 | bool set) | |
1595 | { | |
1596 | struct ice_aqc_get_set_rss_key *cmd_resp; | |
1597 | u16 key_size = sizeof(*key); | |
1598 | struct ice_aq_desc desc; | |
1599 | ||
1600 | cmd_resp = &desc.params.get_set_rss_key; | |
1601 | ||
1602 | if (set) { | |
1603 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); | |
1604 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
1605 | } else { | |
1606 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); | |
1607 | } | |
1608 | ||
1609 | cmd_resp->vsi_id = cpu_to_le16(((vsi_id << | |
1610 | ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & | |
1611 | ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | | |
1612 | ICE_AQC_GSET_RSS_KEY_VSI_VALID); | |
1613 | ||
1614 | return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); | |
1615 | } | |
1616 | ||
1617 | /** | |
1618 | * ice_aq_get_rss_key | |
1619 | * @hw: pointer to the hw struct | |
1620 | * @vsi_id: VSI FW index | |
1621 | * @key: pointer to key info struct | |
1622 | * | |
1623 | * get the RSS key per VSI | |
1624 | */ | |
1625 | enum ice_status | |
1626 | ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_id, | |
1627 | struct ice_aqc_get_set_rss_keys *key) | |
1628 | { | |
1629 | return __ice_aq_get_set_rss_key(hw, vsi_id, key, false); | |
1630 | } | |
1631 | ||
1632 | /** | |
1633 | * ice_aq_set_rss_key | |
1634 | * @hw: pointer to the hw struct | |
1635 | * @vsi_id: VSI FW index | |
1636 | * @keys: pointer to key info struct | |
1637 | * | |
1638 | * set the RSS key per VSI | |
1639 | */ | |
1640 | enum ice_status | |
1641 | ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_id, | |
1642 | struct ice_aqc_get_set_rss_keys *keys) | |
1643 | { | |
1644 | return __ice_aq_get_set_rss_key(hw, vsi_id, keys, true); | |
1645 | } | |
1646 | ||
cdedef59 AV |
1647 | /** |
1648 | * ice_aq_add_lan_txq | |
1649 | * @hw: pointer to the hardware structure | |
1650 | * @num_qgrps: Number of added queue groups | |
1651 | * @qg_list: list of queue groups to be added | |
1652 | * @buf_size: size of buffer for indirect command | |
1653 | * @cd: pointer to command details structure or NULL | |
1654 | * | |
1655 | * Add Tx LAN queue (0x0C30) | |
1656 | * | |
1657 | * NOTE: | |
1658 | * Prior to calling add Tx LAN queue: | |
1659 | * Initialize the following as part of the Tx queue context: | |
1660 | * Completion queue ID if the queue uses Completion queue, Quanta profile, | |
1661 | * Cache profile and Packet shaper profile. | |
1662 | * | |
1663 | * After add Tx LAN queue AQ command is completed: | |
1664 | * Interrupts should be associated with specific queues, | |
1665 | * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue | |
1666 | * flow. | |
1667 | */ | |
1668 | static enum ice_status | |
1669 | ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, | |
1670 | struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, | |
1671 | struct ice_sq_cd *cd) | |
1672 | { | |
1673 | u16 i, sum_header_size, sum_q_size = 0; | |
1674 | struct ice_aqc_add_tx_qgrp *list; | |
1675 | struct ice_aqc_add_txqs *cmd; | |
1676 | struct ice_aq_desc desc; | |
1677 | ||
1678 | cmd = &desc.params.add_txqs; | |
1679 | ||
1680 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); | |
1681 | ||
1682 | if (!qg_list) | |
1683 | return ICE_ERR_PARAM; | |
1684 | ||
1685 | if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) | |
1686 | return ICE_ERR_PARAM; | |
1687 | ||
1688 | sum_header_size = num_qgrps * | |
1689 | (sizeof(*qg_list) - sizeof(*qg_list->txqs)); | |
1690 | ||
1691 | list = qg_list; | |
1692 | for (i = 0; i < num_qgrps; i++) { | |
1693 | struct ice_aqc_add_txqs_perq *q = list->txqs; | |
1694 | ||
1695 | sum_q_size += list->num_txqs * sizeof(*q); | |
1696 | list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); | |
1697 | } | |
1698 | ||
1699 | if (buf_size != (sum_header_size + sum_q_size)) | |
1700 | return ICE_ERR_PARAM; | |
1701 | ||
1702 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
1703 | ||
1704 | cmd->num_qgrps = num_qgrps; | |
1705 | ||
1706 | return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); | |
1707 | } | |
1708 | ||
1709 | /** | |
1710 | * ice_aq_dis_lan_txq | |
1711 | * @hw: pointer to the hardware structure | |
1712 | * @num_qgrps: number of groups in the list | |
1713 | * @qg_list: the list of groups to disable | |
1714 | * @buf_size: the total size of the qg_list buffer in bytes | |
1715 | * @cd: pointer to command details structure or NULL | |
1716 | * | |
1717 | * Disable LAN Tx queue (0x0C31) | |
1718 | */ | |
1719 | static enum ice_status | |
1720 | ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, | |
1721 | struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, | |
1722 | struct ice_sq_cd *cd) | |
1723 | { | |
1724 | struct ice_aqc_dis_txqs *cmd; | |
1725 | struct ice_aq_desc desc; | |
1726 | u16 i, sz = 0; | |
1727 | ||
1728 | cmd = &desc.params.dis_txqs; | |
1729 | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); | |
1730 | ||
1731 | if (!qg_list) | |
1732 | return ICE_ERR_PARAM; | |
1733 | ||
1734 | if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) | |
1735 | return ICE_ERR_PARAM; | |
1736 | desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); | |
1737 | cmd->num_entries = num_qgrps; | |
1738 | ||
1739 | for (i = 0; i < num_qgrps; ++i) { | |
1740 | /* Calculate the size taken up by the queue IDs in this group */ | |
1741 | sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); | |
1742 | ||
1743 | /* Add the size of the group header */ | |
1744 | sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); | |
1745 | ||
1746 | /* If the num of queues is even, add 2 bytes of padding */ | |
1747 | if ((qg_list[i].num_qs % 2) == 0) | |
1748 | sz += 2; | |
1749 | } | |
1750 | ||
1751 | if (buf_size != sz) | |
1752 | return ICE_ERR_PARAM; | |
1753 | ||
1754 | return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); | |
1755 | } | |
1756 | ||
1757 | /* End of FW Admin Queue command wrappers */ | |
1758 | ||
1759 | /** | |
1760 | * ice_write_byte - write a byte to a packed context structure | |
1761 | * @src_ctx: the context structure to read from | |
1762 | * @dest_ctx: the context to be written to | |
1763 | * @ce_info: a description of the struct to be filled | |
1764 | */ | |
1765 | static void ice_write_byte(u8 *src_ctx, u8 *dest_ctx, | |
1766 | const struct ice_ctx_ele *ce_info) | |
1767 | { | |
1768 | u8 src_byte, dest_byte, mask; | |
1769 | u8 *from, *dest; | |
1770 | u16 shift_width; | |
1771 | ||
1772 | /* copy from the next struct field */ | |
1773 | from = src_ctx + ce_info->offset; | |
1774 | ||
1775 | /* prepare the bits and mask */ | |
1776 | shift_width = ce_info->lsb % 8; | |
1777 | mask = (u8)(BIT(ce_info->width) - 1); | |
1778 | ||
1779 | src_byte = *from; | |
1780 | src_byte &= mask; | |
1781 | ||
1782 | /* shift to correct alignment */ | |
1783 | mask <<= shift_width; | |
1784 | src_byte <<= shift_width; | |
1785 | ||
1786 | /* get the current bits from the target bit string */ | |
1787 | dest = dest_ctx + (ce_info->lsb / 8); | |
1788 | ||
1789 | memcpy(&dest_byte, dest, sizeof(dest_byte)); | |
1790 | ||
1791 | dest_byte &= ~mask; /* get the bits not changing */ | |
1792 | dest_byte |= src_byte; /* add in the new bits */ | |
1793 | ||
1794 | /* put it all back */ | |
1795 | memcpy(dest, &dest_byte, sizeof(dest_byte)); | |
1796 | } | |
1797 | ||
1798 | /** | |
1799 | * ice_write_word - write a word to a packed context structure | |
1800 | * @src_ctx: the context structure to read from | |
1801 | * @dest_ctx: the context to be written to | |
1802 | * @ce_info: a description of the struct to be filled | |
1803 | */ | |
1804 | static void ice_write_word(u8 *src_ctx, u8 *dest_ctx, | |
1805 | const struct ice_ctx_ele *ce_info) | |
1806 | { | |
1807 | u16 src_word, mask; | |
1808 | __le16 dest_word; | |
1809 | u8 *from, *dest; | |
1810 | u16 shift_width; | |
1811 | ||
1812 | /* copy from the next struct field */ | |
1813 | from = src_ctx + ce_info->offset; | |
1814 | ||
1815 | /* prepare the bits and mask */ | |
1816 | shift_width = ce_info->lsb % 8; | |
1817 | mask = BIT(ce_info->width) - 1; | |
1818 | ||
1819 | /* don't swizzle the bits until after the mask because the mask bits | |
1820 | * will be in a different bit position on big endian machines | |
1821 | */ | |
1822 | src_word = *(u16 *)from; | |
1823 | src_word &= mask; | |
1824 | ||
1825 | /* shift to correct alignment */ | |
1826 | mask <<= shift_width; | |
1827 | src_word <<= shift_width; | |
1828 | ||
1829 | /* get the current bits from the target bit string */ | |
1830 | dest = dest_ctx + (ce_info->lsb / 8); | |
1831 | ||
1832 | memcpy(&dest_word, dest, sizeof(dest_word)); | |
1833 | ||
1834 | dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ | |
1835 | dest_word |= cpu_to_le16(src_word); /* add in the new bits */ | |
1836 | ||
1837 | /* put it all back */ | |
1838 | memcpy(dest, &dest_word, sizeof(dest_word)); | |
1839 | } | |
1840 | ||
1841 | /** | |
1842 | * ice_write_dword - write a dword to a packed context structure | |
1843 | * @src_ctx: the context structure to read from | |
1844 | * @dest_ctx: the context to be written to | |
1845 | * @ce_info: a description of the struct to be filled | |
1846 | */ | |
1847 | static void ice_write_dword(u8 *src_ctx, u8 *dest_ctx, | |
1848 | const struct ice_ctx_ele *ce_info) | |
1849 | { | |
1850 | u32 src_dword, mask; | |
1851 | __le32 dest_dword; | |
1852 | u8 *from, *dest; | |
1853 | u16 shift_width; | |
1854 | ||
1855 | /* copy from the next struct field */ | |
1856 | from = src_ctx + ce_info->offset; | |
1857 | ||
1858 | /* prepare the bits and mask */ | |
1859 | shift_width = ce_info->lsb % 8; | |
1860 | ||
1861 | /* if the field width is exactly 32 on an x86 machine, then the shift | |
1862 | * operation will not work because the SHL instructions count is masked | |
1863 | * to 5 bits so the shift will do nothing | |
1864 | */ | |
1865 | if (ce_info->width < 32) | |
1866 | mask = BIT(ce_info->width) - 1; | |
1867 | else | |
1868 | mask = (u32)~0; | |
1869 | ||
1870 | /* don't swizzle the bits until after the mask because the mask bits | |
1871 | * will be in a different bit position on big endian machines | |
1872 | */ | |
1873 | src_dword = *(u32 *)from; | |
1874 | src_dword &= mask; | |
1875 | ||
1876 | /* shift to correct alignment */ | |
1877 | mask <<= shift_width; | |
1878 | src_dword <<= shift_width; | |
1879 | ||
1880 | /* get the current bits from the target bit string */ | |
1881 | dest = dest_ctx + (ce_info->lsb / 8); | |
1882 | ||
1883 | memcpy(&dest_dword, dest, sizeof(dest_dword)); | |
1884 | ||
1885 | dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ | |
1886 | dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ | |
1887 | ||
1888 | /* put it all back */ | |
1889 | memcpy(dest, &dest_dword, sizeof(dest_dword)); | |
1890 | } | |
1891 | ||
1892 | /** | |
1893 | * ice_write_qword - write a qword to a packed context structure | |
1894 | * @src_ctx: the context structure to read from | |
1895 | * @dest_ctx: the context to be written to | |
1896 | * @ce_info: a description of the struct to be filled | |
1897 | */ | |
1898 | static void ice_write_qword(u8 *src_ctx, u8 *dest_ctx, | |
1899 | const struct ice_ctx_ele *ce_info) | |
1900 | { | |
1901 | u64 src_qword, mask; | |
1902 | __le64 dest_qword; | |
1903 | u8 *from, *dest; | |
1904 | u16 shift_width; | |
1905 | ||
1906 | /* copy from the next struct field */ | |
1907 | from = src_ctx + ce_info->offset; | |
1908 | ||
1909 | /* prepare the bits and mask */ | |
1910 | shift_width = ce_info->lsb % 8; | |
1911 | ||
1912 | /* if the field width is exactly 64 on an x86 machine, then the shift | |
1913 | * operation will not work because the SHL instructions count is masked | |
1914 | * to 6 bits so the shift will do nothing | |
1915 | */ | |
1916 | if (ce_info->width < 64) | |
1917 | mask = BIT_ULL(ce_info->width) - 1; | |
1918 | else | |
1919 | mask = (u64)~0; | |
1920 | ||
1921 | /* don't swizzle the bits until after the mask because the mask bits | |
1922 | * will be in a different bit position on big endian machines | |
1923 | */ | |
1924 | src_qword = *(u64 *)from; | |
1925 | src_qword &= mask; | |
1926 | ||
1927 | /* shift to correct alignment */ | |
1928 | mask <<= shift_width; | |
1929 | src_qword <<= shift_width; | |
1930 | ||
1931 | /* get the current bits from the target bit string */ | |
1932 | dest = dest_ctx + (ce_info->lsb / 8); | |
1933 | ||
1934 | memcpy(&dest_qword, dest, sizeof(dest_qword)); | |
1935 | ||
1936 | dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ | |
1937 | dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ | |
1938 | ||
1939 | /* put it all back */ | |
1940 | memcpy(dest, &dest_qword, sizeof(dest_qword)); | |
1941 | } | |
1942 | ||
1943 | /** | |
1944 | * ice_set_ctx - set context bits in packed structure | |
1945 | * @src_ctx: pointer to a generic non-packed context structure | |
1946 | * @dest_ctx: pointer to memory for the packed structure | |
1947 | * @ce_info: a description of the structure to be transformed | |
1948 | */ | |
1949 | enum ice_status | |
1950 | ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) | |
1951 | { | |
1952 | int f; | |
1953 | ||
1954 | for (f = 0; ce_info[f].width; f++) { | |
1955 | /* We have to deal with each element of the FW response | |
1956 | * using the correct size so that we are correct regardless | |
1957 | * of the endianness of the machine. | |
1958 | */ | |
1959 | switch (ce_info[f].size_of) { | |
1960 | case sizeof(u8): | |
1961 | ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); | |
1962 | break; | |
1963 | case sizeof(u16): | |
1964 | ice_write_word(src_ctx, dest_ctx, &ce_info[f]); | |
1965 | break; | |
1966 | case sizeof(u32): | |
1967 | ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); | |
1968 | break; | |
1969 | case sizeof(u64): | |
1970 | ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); | |
1971 | break; | |
1972 | default: | |
1973 | return ICE_ERR_INVAL_SIZE; | |
1974 | } | |
1975 | } | |
1976 | ||
1977 | return 0; | |
1978 | } | |
1979 | ||
1980 | /** | |
1981 | * ice_ena_vsi_txq | |
1982 | * @pi: port information structure | |
1983 | * @vsi_id: VSI id | |
1984 | * @tc: tc number | |
1985 | * @num_qgrps: Number of added queue groups | |
1986 | * @buf: list of queue groups to be added | |
1987 | * @buf_size: size of buffer for indirect command | |
1988 | * @cd: pointer to command details structure or NULL | |
1989 | * | |
1990 | * This function adds one lan q | |
1991 | */ | |
1992 | enum ice_status | |
1993 | ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_id, u8 tc, u8 num_qgrps, | |
1994 | struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, | |
1995 | struct ice_sq_cd *cd) | |
1996 | { | |
1997 | struct ice_aqc_txsched_elem_data node = { 0 }; | |
1998 | struct ice_sched_node *parent; | |
1999 | enum ice_status status; | |
2000 | struct ice_hw *hw; | |
2001 | ||
2002 | if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) | |
2003 | return ICE_ERR_CFG; | |
2004 | ||
2005 | if (num_qgrps > 1 || buf->num_txqs > 1) | |
2006 | return ICE_ERR_MAX_LIMIT; | |
2007 | ||
2008 | hw = pi->hw; | |
2009 | ||
2010 | mutex_lock(&pi->sched_lock); | |
2011 | ||
2012 | /* find a parent node */ | |
2013 | parent = ice_sched_get_free_qparent(pi, vsi_id, tc, | |
2014 | ICE_SCHED_NODE_OWNER_LAN); | |
2015 | if (!parent) { | |
2016 | status = ICE_ERR_PARAM; | |
2017 | goto ena_txq_exit; | |
2018 | } | |
2019 | buf->parent_teid = parent->info.node_teid; | |
2020 | node.parent_teid = parent->info.node_teid; | |
2021 | /* Mark that the values in the "generic" section as valid. The default | |
2022 | * value in the "generic" section is zero. This means that : | |
2023 | * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. | |
2024 | * - 0 priority among siblings, indicated by Bit 1-3. | |
2025 | * - WFQ, indicated by Bit 4. | |
2026 | * - 0 Adjustment value is used in PSM credit update flow, indicated by | |
2027 | * Bit 5-6. | |
2028 | * - Bit 7 is reserved. | |
2029 | * Without setting the generic section as valid in valid_sections, the | |
2030 | * Admin Q command will fail with error code ICE_AQ_RC_EINVAL. | |
2031 | */ | |
2032 | buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; | |
2033 | ||
2034 | /* add the lan q */ | |
2035 | status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); | |
2036 | if (status) | |
2037 | goto ena_txq_exit; | |
2038 | ||
2039 | node.node_teid = buf->txqs[0].q_teid; | |
2040 | node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; | |
2041 | ||
2042 | /* add a leaf node into schduler tree q layer */ | |
2043 | status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); | |
2044 | ||
2045 | ena_txq_exit: | |
2046 | mutex_unlock(&pi->sched_lock); | |
2047 | return status; | |
2048 | } | |
2049 | ||
2050 | /** | |
2051 | * ice_dis_vsi_txq | |
2052 | * @pi: port information structure | |
2053 | * @num_queues: number of queues | |
2054 | * @q_ids: pointer to the q_id array | |
2055 | * @q_teids: pointer to queue node teids | |
2056 | * @cd: pointer to command details structure or NULL | |
2057 | * | |
2058 | * This function removes queues and their corresponding nodes in SW DB | |
2059 | */ | |
2060 | enum ice_status | |
2061 | ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids, | |
2062 | u32 *q_teids, struct ice_sq_cd *cd) | |
2063 | { | |
2064 | enum ice_status status = ICE_ERR_DOES_NOT_EXIST; | |
2065 | struct ice_aqc_dis_txq_item qg_list; | |
2066 | u16 i; | |
2067 | ||
2068 | if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) | |
2069 | return ICE_ERR_CFG; | |
2070 | ||
2071 | mutex_lock(&pi->sched_lock); | |
2072 | ||
2073 | for (i = 0; i < num_queues; i++) { | |
2074 | struct ice_sched_node *node; | |
2075 | ||
2076 | node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); | |
2077 | if (!node) | |
2078 | continue; | |
2079 | qg_list.parent_teid = node->info.parent_teid; | |
2080 | qg_list.num_qs = 1; | |
2081 | qg_list.q_id[0] = cpu_to_le16(q_ids[i]); | |
2082 | status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, | |
2083 | sizeof(qg_list), cd); | |
2084 | ||
2085 | if (status) | |
2086 | break; | |
2087 | ice_free_sched_node(pi, node); | |
2088 | } | |
2089 | mutex_unlock(&pi->sched_lock); | |
2090 | return status; | |
2091 | } | |
5513b920 AV |
2092 | |
2093 | /** | |
2094 | * ice_cfg_vsi_qs - configure the new/exisiting VSI queues | |
2095 | * @pi: port information structure | |
2096 | * @vsi_id: VSI Id | |
2097 | * @tc_bitmap: TC bitmap | |
2098 | * @maxqs: max queues array per TC | |
2099 | * @owner: lan or rdma | |
2100 | * | |
2101 | * This function adds/updates the VSI queues per TC. | |
2102 | */ | |
2103 | static enum ice_status | |
2104 | ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap, | |
2105 | u16 *maxqs, u8 owner) | |
2106 | { | |
2107 | enum ice_status status = 0; | |
2108 | u8 i; | |
2109 | ||
2110 | if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) | |
2111 | return ICE_ERR_CFG; | |
2112 | ||
2113 | mutex_lock(&pi->sched_lock); | |
2114 | ||
2115 | for (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) { | |
2116 | /* configuration is possible only if TC node is present */ | |
2117 | if (!ice_sched_get_tc_node(pi, i)) | |
2118 | continue; | |
2119 | ||
2120 | status = ice_sched_cfg_vsi(pi, vsi_id, i, maxqs[i], owner, | |
2121 | ice_is_tc_ena(tc_bitmap, i)); | |
2122 | if (status) | |
2123 | break; | |
2124 | } | |
2125 | ||
2126 | mutex_unlock(&pi->sched_lock); | |
2127 | return status; | |
2128 | } | |
2129 | ||
2130 | /** | |
2131 | * ice_cfg_vsi_lan - configure VSI lan queues | |
2132 | * @pi: port information structure | |
2133 | * @vsi_id: VSI Id | |
2134 | * @tc_bitmap: TC bitmap | |
2135 | * @max_lanqs: max lan queues array per TC | |
2136 | * | |
2137 | * This function adds/updates the VSI lan queues per TC. | |
2138 | */ | |
2139 | enum ice_status | |
2140 | ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap, | |
2141 | u16 *max_lanqs) | |
2142 | { | |
2143 | return ice_cfg_vsi_qs(pi, vsi_id, tc_bitmap, max_lanqs, | |
2144 | ICE_SCHED_NODE_OWNER_LAN); | |
2145 | } |