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ice: separate out control queue lock creation
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / intel / ice / ice_common.c
CommitLineData
7ec59eea
AV		 1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, Intel Corporation. */
3
4#include "ice_common.h"
9c20346b 5#include "ice_sched.h"
7ec59eea
AV		 6#include "ice_adminq_cmd.h"
7
f31e4b6f
AV		 8#define ICE_PF_RESET_WAIT_COUNT 200
9
22ef683b
AV		 10#define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
cdedef59
AV		 12 ((ICE_RX_OPC_MDID << \
13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
17
22ef683b
AV		 18#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
19 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
cdedef59
AV		 20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
28
f31e4b6f
AV		 29/**
30 * ice_set_mac_type - Sets MAC type
31 * @hw: pointer to the HW structure
32 *
33 * This function sets the MAC type of the adapter based on the
f9867df6 34 * vendor ID and device ID stored in the HW structure.
f31e4b6f
AV		 35 */
36static enum ice_status ice_set_mac_type(struct ice_hw *hw)
37{
38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
39 return ICE_ERR_DEVICE_NOT_SUPPORTED;
40
41 hw->mac_type = ICE_MAC_GENERIC;
42 return 0;
43}
44
f203dca3
AV		 45/**
46 * ice_dev_onetime_setup - Temporary HW/FW workarounds
47 * @hw: pointer to the HW structure
48 *
49 * This function provides temporary workarounds for certain issues
50 * that are expected to be fixed in the HW/FW.
51 */
52void ice_dev_onetime_setup(struct ice_hw *hw)
53{
f203dca3
AV		 54#define MBX_PF_VT_PFALLOC 0x00231E80
55 /* set VFs per PF */
56 wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF));
57}
58
f31e4b6f
AV		 59/**
60 * ice_clear_pf_cfg - Clear PF configuration
61 * @hw: pointer to the hardware structure
3968540b
AV		 62 *
63 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
64 * configuration, flow director filters, etc.).
f31e4b6f
AV		 65 */
66enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
67{
68 struct ice_aq_desc desc;
69
70 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
71
72 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
73}
74
dc49c772
AV		 75/**
76 * ice_aq_manage_mac_read - manage MAC address read command
f9867df6 77 * @hw: pointer to the HW struct
dc49c772
AV		 78 * @buf: a virtual buffer to hold the manage MAC read response
79 * @buf_size: Size of the virtual buffer
80 * @cd: pointer to command details structure or NULL
81 *
82 * This function is used to return per PF station MAC address (0x0107).
83 * NOTE: Upon successful completion of this command, MAC address information
84 * is returned in user specified buffer. Please interpret user specified
85 * buffer as "manage_mac_read" response.
86 * Response such as various MAC addresses are stored in HW struct (port.mac)
87 * ice_aq_discover_caps is expected to be called before this function is called.
88 */
89static enum ice_status
90ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_sq_cd *cd)
92{
93 struct ice_aqc_manage_mac_read_resp *resp;
94 struct ice_aqc_manage_mac_read *cmd;
95 struct ice_aq_desc desc;
96 enum ice_status status;
97 u16 flags;
d6fef10c 98 u8 i;
dc49c772
AV		 99
100 cmd = &desc.params.mac_read;
101
102 if (buf_size < sizeof(*resp))
103 return ICE_ERR_BUF_TOO_SHORT;
104
105 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
106
107 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
108 if (status)
109 return status;
110
111 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
112 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
113
114 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
115 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
116 return ICE_ERR_CFG;
117 }
118
d6fef10c
MFIP		 119 /* A single port can report up to two (LAN and WoL) addresses */
120 for (i = 0; i < cmd->num_addr; i++)
121 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
122 ether_addr_copy(hw->port_info->mac.lan_addr,
123 resp[i].mac_addr);
124 ether_addr_copy(hw->port_info->mac.perm_addr,
125 resp[i].mac_addr);
126 break;
127 }
128
dc49c772
AV		 129 return 0;
130}
131
132/**
133 * ice_aq_get_phy_caps - returns PHY capabilities
134 * @pi: port information structure
135 * @qual_mods: report qualified modules
136 * @report_mode: report mode capabilities
137 * @pcaps: structure for PHY capabilities to be filled
138 * @cd: pointer to command details structure or NULL
139 *
140 * Returns the various PHY capabilities supported on the Port (0x0600)
141 */
48cb27f2 142enum ice_status
dc49c772
AV		 143ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
144 struct ice_aqc_get_phy_caps_data *pcaps,
145 struct ice_sq_cd *cd)
146{
147 struct ice_aqc_get_phy_caps *cmd;
148 u16 pcaps_size = sizeof(*pcaps);
149 struct ice_aq_desc desc;
150 enum ice_status status;
151
152 cmd = &desc.params.get_phy;
153
154 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
155 return ICE_ERR_PARAM;
156
157 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
158
159 if (qual_mods)
160 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
161
162 cmd->param0 |= cpu_to_le16(report_mode);
163 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
164
aef74145 165 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
dc49c772 166 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
aef74145
AV		 167 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
168 }
dc49c772
AV		 169
170 return status;
171}
172
173/**
174 * ice_get_media_type - Gets media type
175 * @pi: port information structure
176 */
177static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
178{
179 struct ice_link_status *hw_link_info;
180
181 if (!pi)
182 return ICE_MEDIA_UNKNOWN;
183
184 hw_link_info = &pi->phy.link_info;
aef74145
AV		 185 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
186 /* If more than one media type is selected, report unknown */
187 return ICE_MEDIA_UNKNOWN;
dc49c772
AV		 188
189 if (hw_link_info->phy_type_low) {
190 switch (hw_link_info->phy_type_low) {
191 case ICE_PHY_TYPE_LOW_1000BASE_SX:
192 case ICE_PHY_TYPE_LOW_1000BASE_LX:
193 case ICE_PHY_TYPE_LOW_10GBASE_SR:
194 case ICE_PHY_TYPE_LOW_10GBASE_LR:
195 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
196 case ICE_PHY_TYPE_LOW_25GBASE_SR:
197 case ICE_PHY_TYPE_LOW_25GBASE_LR:
198 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
199 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
200 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
aef74145
AV		 201 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
202 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
203 case ICE_PHY_TYPE_LOW_50GBASE_SR:
204 case ICE_PHY_TYPE_LOW_50GBASE_FR:
205 case ICE_PHY_TYPE_LOW_50GBASE_LR:
206 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_100GBASE_DR:
dc49c772
AV		 210 return ICE_MEDIA_FIBER;
211 case ICE_PHY_TYPE_LOW_100BASE_TX:
212 case ICE_PHY_TYPE_LOW_1000BASE_T:
213 case ICE_PHY_TYPE_LOW_2500BASE_T:
214 case ICE_PHY_TYPE_LOW_5GBASE_T:
215 case ICE_PHY_TYPE_LOW_10GBASE_T:
216 case ICE_PHY_TYPE_LOW_25GBASE_T:
217 return ICE_MEDIA_BASET;
218 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
219 case ICE_PHY_TYPE_LOW_25GBASE_CR:
220 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
221 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
222 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
aef74145
AV		 223 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
224 case ICE_PHY_TYPE_LOW_50GBASE_CP:
225 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
226 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
227 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
dc49c772
AV		 228 return ICE_MEDIA_DA;
229 case ICE_PHY_TYPE_LOW_1000BASE_KX:
230 case ICE_PHY_TYPE_LOW_2500BASE_KX:
231 case ICE_PHY_TYPE_LOW_2500BASE_X:
232 case ICE_PHY_TYPE_LOW_5GBASE_KR:
233 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
234 case ICE_PHY_TYPE_LOW_25GBASE_KR:
235 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
236 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
237 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
aef74145
AV		 238 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
239 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
240 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
241 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
242 return ICE_MEDIA_BACKPLANE;
243 }
244 } else {
245 switch (hw_link_info->phy_type_high) {
246 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
dc49c772
AV		 247 return ICE_MEDIA_BACKPLANE;
248 }
249 }
dc49c772
AV		 250 return ICE_MEDIA_UNKNOWN;
251}
252
253/**
254 * ice_aq_get_link_info
255 * @pi: port information structure
256 * @ena_lse: enable/disable LinkStatusEvent reporting
257 * @link: pointer to link status structure - optional
258 * @cd: pointer to command details structure or NULL
259 *
260 * Get Link Status (0x607). Returns the link status of the adapter.
261 */
250c3b3e 262enum ice_status
dc49c772
AV		 263ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
264 struct ice_link_status *link, struct ice_sq_cd *cd)
265{
266 struct ice_link_status *hw_link_info_old, *hw_link_info;
267 struct ice_aqc_get_link_status_data link_data = { 0 };
268 struct ice_aqc_get_link_status *resp;
269 enum ice_media_type *hw_media_type;
270 struct ice_fc_info *hw_fc_info;
271 bool tx_pause, rx_pause;
272 struct ice_aq_desc desc;
273 enum ice_status status;
274 u16 cmd_flags;
275
276 if (!pi)
277 return ICE_ERR_PARAM;
278 hw_link_info_old = &pi->phy.link_info_old;
279 hw_media_type = &pi->phy.media_type;
280 hw_link_info = &pi->phy.link_info;
281 hw_fc_info = &pi->fc;
282
283 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
284 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
285 resp = &desc.params.get_link_status;
286 resp->cmd_flags = cpu_to_le16(cmd_flags);
287 resp->lport_num = pi->lport;
288
289 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),
290 cd);
291
292 if (status)
293 return status;
294
295 /* save off old link status information */
296 *hw_link_info_old = *hw_link_info;
297
298 /* update current link status information */
299 hw_link_info->link_speed = le16_to_cpu(link_data.link_speed);
300 hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low);
aef74145 301 hw_link_info->phy_type_high = le64_to_cpu(link_data.phy_type_high);
dc49c772
AV		 302 *hw_media_type = ice_get_media_type(pi);
303 hw_link_info->link_info = link_data.link_info;
304 hw_link_info->an_info = link_data.an_info;
305 hw_link_info->ext_info = link_data.ext_info;
306 hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size);
f776b3ac
PG		 307 hw_link_info->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
308 hw_link_info->topo_media_conflict = link_data.topo_media_conflict;
dc49c772
AV		 309 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;
310
311 /* update fc info */
312 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
313 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
314 if (tx_pause && rx_pause)
315 hw_fc_info->current_mode = ICE_FC_FULL;
316 else if (tx_pause)
317 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
318 else if (rx_pause)
319 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
320 else
321 hw_fc_info->current_mode = ICE_FC_NONE;
322
323 hw_link_info->lse_ena =
324 !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
325
326 /* save link status information */
327 if (link)
328 *link = *hw_link_info;
329
330 /* flag cleared so calling functions don't call AQ again */
331 pi->phy.get_link_info = false;
332
1b5c19c7 333 return 0;
dc49c772
AV		 334}
335
cdedef59 336/**
22ef683b 337 * ice_init_flex_flags
cdedef59 338 * @hw: pointer to the hardware structure
22ef683b 339 * @prof_id: Rx Descriptor Builder profile ID
cdedef59 340 *
22ef683b 341 * Function to initialize Rx flex flags
cdedef59 342 */
22ef683b 343static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
cdedef59
AV		 344{
345 u8 idx = 0;
346
22ef683b
AV		 347 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
348 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
349 * flexiflags1[3:0] - Not used for flag programming
350 * flexiflags2[7:0] - Tunnel and VLAN types
351 * 2 invalid fields in last index
352 */
353 switch (prof_id) {
354 /* Rx flex flags are currently programmed for the NIC profiles only.
355 * Different flag bit programming configurations can be added per
356 * profile as needed.
357 */
358 case ICE_RXDID_FLEX_NIC:
359 case ICE_RXDID_FLEX_NIC_2:
86e81794
CC		 360 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
361 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
362 ICE_FLG_FIN, idx++);
22ef683b
AV		 363 /* flex flag 1 is not used for flexi-flag programming, skipping
364 * these four FLG64 bits.
365 */
86e81794
CC		 366 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
367 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
368 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
369 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
370 ICE_FLG_EVLAN_x9100, idx++);
371 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
372 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
373 ICE_FLG_TNL0, idx++);
374 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
375 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
22ef683b
AV		 376 break;
377
378 default:
379 ice_debug(hw, ICE_DBG_INIT,
380 "Flag programming for profile ID %d not supported\n",
381 prof_id);
382 }
383}
384
385/**
386 * ice_init_flex_flds
387 * @hw: pointer to the hardware structure
388 * @prof_id: Rx Descriptor Builder profile ID
389 *
390 * Function to initialize flex descriptors
391 */
392static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
393{
394 enum ice_flex_rx_mdid mdid;
395
396 switch (prof_id) {
397 case ICE_RXDID_FLEX_NIC:
398 case ICE_RXDID_FLEX_NIC_2:
399 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);
400 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);
401 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);
402
403 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
404 ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;
405
406 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
407
408 ice_init_flex_flags(hw, prof_id);
409 break;
410
411 default:
412 ice_debug(hw, ICE_DBG_INIT,
413 "Field init for profile ID %d not supported\n",
414 prof_id);
415 }
cdedef59
AV		 416}
417
9daf8208
AV		 418/**
419 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
f9867df6 420 * @hw: pointer to the HW struct
9daf8208
AV		 421 */
422static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
423{
424 struct ice_switch_info *sw;
425
426 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
427 sizeof(*hw->switch_info), GFP_KERNEL);
428 sw = hw->switch_info;
429
430 if (!sw)
431 return ICE_ERR_NO_MEMORY;
432
433 INIT_LIST_HEAD(&sw->vsi_list_map_head);
434
5fb597d7 435 return ice_init_def_sw_recp(hw);
9daf8208
AV		 436}
437
438/**
439 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
f9867df6 440 * @hw: pointer to the HW struct
9daf8208
AV		 441 */
442static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
443{
444 struct ice_switch_info *sw = hw->switch_info;
445 struct ice_vsi_list_map_info *v_pos_map;
446 struct ice_vsi_list_map_info *v_tmp_map;
80d144c9
AV		 447 struct ice_sw_recipe *recps;
448 u8 i;
9daf8208
AV		 449
450 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
451 list_entry) {
452 list_del(&v_pos_map->list_entry);
453 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
454 }
80d144c9
AV		 455 recps = hw->switch_info->recp_list;
456 for (i = 0; i < ICE_SW_LKUP_LAST; i++) {
457 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
458
459 recps[i].root_rid = i;
460 mutex_destroy(&recps[i].filt_rule_lock);
461 list_for_each_entry_safe(lst_itr, tmp_entry,
462 &recps[i].filt_rules, list_entry) {
463 list_del(&lst_itr->list_entry);
464 devm_kfree(ice_hw_to_dev(hw), lst_itr);
465 }
466 }
334cb062 467 ice_rm_all_sw_replay_rule_info(hw);
80d144c9 468 devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
9daf8208
AV		 469 devm_kfree(ice_hw_to_dev(hw), sw);
470}
471
8b97ceb1
HT		 472#define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
473 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
474#define ICE_FW_LOG_DESC_SIZE_MAX \
475 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
476
11fe1b3a
DN		 477/**
478 * ice_get_fw_log_cfg - get FW logging configuration
479 * @hw: pointer to the HW struct
480 */
481static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
482{
483 struct ice_aqc_fw_logging_data *config;
484 struct ice_aq_desc desc;
485 enum ice_status status;
486 u16 size;
487
488 size = ICE_FW_LOG_DESC_SIZE_MAX;
489 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL);
490 if (!config)
491 return ICE_ERR_NO_MEMORY;
492
493 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
494
495 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF);
496 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
497
498 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
499 if (!status) {
500 u16 i;
501
2f2da36e 502 /* Save FW logging information into the HW structure */
11fe1b3a
DN		 503 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
504 u16 v, m, flgs;
505
506 v = le16_to_cpu(config->entry[i]);
507 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
508 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
509
510 if (m < ICE_AQC_FW_LOG_ID_MAX)
511 hw->fw_log.evnts[m].cur = flgs;
512 }
513 }
514
515 devm_kfree(ice_hw_to_dev(hw), config);
516
517 return status;
518}
519
8b97ceb1
HT		 520/**
521 * ice_cfg_fw_log - configure FW logging
f9867df6 522 * @hw: pointer to the HW struct
8b97ceb1
HT		 523 * @enable: enable certain FW logging events if true, disable all if false
524 *
525 * This function enables/disables the FW logging via Rx CQ events and a UART
526 * port based on predetermined configurations. FW logging via the Rx CQ can be
527 * enabled/disabled for individual PF's. However, FW logging via the UART can
528 * only be enabled/disabled for all PFs on the same device.
529 *
530 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
531 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
532 * before initializing the device.
533 *
534 * When re/configuring FW logging, callers need to update the "cfg" elements of
535 * the hw->fw_log.evnts array with the desired logging event configurations for
536 * modules of interest. When disabling FW logging completely, the callers can
537 * just pass false in the "enable" parameter. On completion, the function will
538 * update the "cur" element of the hw->fw_log.evnts array with the resulting
539 * logging event configurations of the modules that are being re/configured. FW
540 * logging modules that are not part of a reconfiguration operation retain their
541 * previous states.
542 *
543 * Before resetting the device, it is recommended that the driver disables FW
544 * logging before shutting down the control queue. When disabling FW logging
545 * ("enable" = false), the latest configurations of FW logging events stored in
546 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
547 * a device reset.
548 *
549 * When enabling FW logging to emit log messages via the Rx CQ during the
550 * device's initialization phase, a mechanism alternative to interrupt handlers
551 * needs to be used to extract FW log messages from the Rx CQ periodically and
552 * to prevent the Rx CQ from being full and stalling other types of control
553 * messages from FW to SW. Interrupts are typically disabled during the device's
554 * initialization phase.
555 */
556static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
557{
558 struct ice_aqc_fw_logging_data *data = NULL;
559 struct ice_aqc_fw_logging *cmd;
560 enum ice_status status = 0;
561 u16 i, chgs = 0, len = 0;
562 struct ice_aq_desc desc;
563 u8 actv_evnts = 0;
564 void *buf = NULL;
565
566 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
567 return 0;
568
569 /* Disable FW logging only when the control queue is still responsive */
570 if (!enable &&
571 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
572 return 0;
573
11fe1b3a
DN		 574 /* Get current FW log settings */
575 status = ice_get_fw_log_cfg(hw);
576 if (status)
577 return status;
578
8b97ceb1
HT		 579 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
580 cmd = &desc.params.fw_logging;
581
582 /* Indicate which controls are valid */
583 if (hw->fw_log.cq_en)
584 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
585
586 if (hw->fw_log.uart_en)
587 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
588
589 if (enable) {
590 /* Fill in an array of entries with FW logging modules and
591 * logging events being reconfigured.
592 */
593 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
594 u16 val;
595
596 /* Keep track of enabled event types */
597 actv_evnts |= hw->fw_log.evnts[i].cfg;
598
599 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
600 continue;
601
602 if (!data) {
603 data = devm_kzalloc(ice_hw_to_dev(hw),
604 ICE_FW_LOG_DESC_SIZE_MAX,
605 GFP_KERNEL);
606 if (!data)
607 return ICE_ERR_NO_MEMORY;
608 }
609
610 val = i << ICE_AQC_FW_LOG_ID_S;
611 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
612 data->entry[chgs++] = cpu_to_le16(val);
613 }
614
615 /* Only enable FW logging if at least one module is specified.
616 * If FW logging is currently enabled but all modules are not
617 * enabled to emit log messages, disable FW logging altogether.
618 */
619 if (actv_evnts) {
620 /* Leave if there is effectively no change */
621 if (!chgs)
622 goto out;
623
624 if (hw->fw_log.cq_en)
625 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
626
627 if (hw->fw_log.uart_en)
628 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
629
630 buf = data;
631 len = ICE_FW_LOG_DESC_SIZE(chgs);
632 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
633 }
634 }
635
636 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
637 if (!status) {
638 /* Update the current configuration to reflect events enabled.
639 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
640 * logging mode is enabled for the device. They do not reflect
641 * actual modules being enabled to emit log messages. So, their
642 * values remain unchanged even when all modules are disabled.
643 */
644 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
645
646 hw->fw_log.actv_evnts = actv_evnts;
647 for (i = 0; i < cnt; i++) {
648 u16 v, m;
649
650 if (!enable) {
651 /* When disabling all FW logging events as part
652 * of device's de-initialization, the original
653 * configurations are retained, and can be used
654 * to reconfigure FW logging later if the device
655 * is re-initialized.
656 */
657 hw->fw_log.evnts[i].cur = 0;
658 continue;
659 }
660
661 v = le16_to_cpu(data->entry[i]);
662 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
663 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
664 }
665 }
666
667out:
668 if (data)
669 devm_kfree(ice_hw_to_dev(hw), data);
670
671 return status;
672}
673
674/**
675 * ice_output_fw_log
f9867df6 676 * @hw: pointer to the HW struct
8b97ceb1
HT		 677 * @desc: pointer to the AQ message descriptor
678 * @buf: pointer to the buffer accompanying the AQ message
679 *
680 * Formats a FW Log message and outputs it via the standard driver logs.
681 */
682void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
683{
4f70daa0
JK		 684 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
685 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
8b97ceb1 686 le16_to_cpu(desc->datalen));
4f70daa0 687 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
8b97ceb1
HT		 688}
689
9e4ab4c2
BC		 690/**
691 * ice_get_itr_intrl_gran - determine int/intrl granularity
f9867df6 692 * @hw: pointer to the HW struct
9e4ab4c2 693 *
2f2da36e 694 * Determines the ITR/intrl granularities based on the maximum aggregate
9e4ab4c2
BC		 695 * bandwidth according to the device's configuration during power-on.
696 */
fe7219fa 697static void ice_get_itr_intrl_gran(struct ice_hw *hw)
9e4ab4c2
BC		 698{
699 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
700 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
701 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
702
703 switch (max_agg_bw) {
704 case ICE_MAX_AGG_BW_200G:
705 case ICE_MAX_AGG_BW_100G:
706 case ICE_MAX_AGG_BW_50G:
707 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
708 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
709 break;
710 case ICE_MAX_AGG_BW_25G:
711 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
712 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
713 break;
9e4ab4c2 714 }
9e4ab4c2
BC		 715}
716
f31e4b6f
AV		 717/**
718 * ice_init_hw - main hardware initialization routine
719 * @hw: pointer to the hardware structure
720 */
721enum ice_status ice_init_hw(struct ice_hw *hw)
722{
dc49c772 723 struct ice_aqc_get_phy_caps_data *pcaps;
f31e4b6f 724 enum ice_status status;
dc49c772
AV		 725 u16 mac_buf_len;
726 void *mac_buf;
f31e4b6f
AV		 727
728 /* Set MAC type based on DeviceID */
729 status = ice_set_mac_type(hw);
730 if (status)
731 return status;
732
733 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
734 PF_FUNC_RID_FUNC_NUM_M) >>
735 PF_FUNC_RID_FUNC_NUM_S;
736
737 status = ice_reset(hw, ICE_RESET_PFR);
738 if (status)
739 return status;
740
fe7219fa 741 ice_get_itr_intrl_gran(hw);
940b61af 742
5c91ecfd 743 status = ice_create_all_ctrlq(hw);
f31e4b6f
AV		 744 if (status)
745 goto err_unroll_cqinit;
746
8b97ceb1
HT		 747 /* Enable FW logging. Not fatal if this fails. */
748 status = ice_cfg_fw_log(hw, true);
749 if (status)
750 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
751
f31e4b6f
AV		 752 status = ice_clear_pf_cfg(hw);
753 if (status)
754 goto err_unroll_cqinit;
755
756 ice_clear_pxe_mode(hw);
757
758 status = ice_init_nvm(hw);
759 if (status)
760 goto err_unroll_cqinit;
761
9c20346b
AV		 762 status = ice_get_caps(hw);
763 if (status)
764 goto err_unroll_cqinit;
765
766 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
767 sizeof(*hw->port_info), GFP_KERNEL);
768 if (!hw->port_info) {
769 status = ICE_ERR_NO_MEMORY;
770 goto err_unroll_cqinit;
771 }
772
f9867df6 773 /* set the back pointer to HW */
9c20346b
AV		 774 hw->port_info->hw = hw;
775
776 /* Initialize port_info struct with switch configuration data */
777 status = ice_get_initial_sw_cfg(hw);
778 if (status)
779 goto err_unroll_alloc;
780
9daf8208
AV		 781 hw->evb_veb = true;
782
d337f2af 783 /* Query the allocated resources for Tx scheduler */
9c20346b
AV		 784 status = ice_sched_query_res_alloc(hw);
785 if (status) {
786 ice_debug(hw, ICE_DBG_SCHED,
787 "Failed to get scheduler allocated resources\n");
788 goto err_unroll_alloc;
789 }
790
dc49c772
AV		 791 /* Initialize port_info struct with scheduler data */
792 status = ice_sched_init_port(hw->port_info);
793 if (status)
794 goto err_unroll_sched;
795
796 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
797 if (!pcaps) {
798 status = ICE_ERR_NO_MEMORY;
799 goto err_unroll_sched;
800 }
801
802 /* Initialize port_info struct with PHY capabilities */
803 status = ice_aq_get_phy_caps(hw->port_info, false,
804 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
805 devm_kfree(ice_hw_to_dev(hw), pcaps);
806 if (status)
807 goto err_unroll_sched;
808
809 /* Initialize port_info struct with link information */
810 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
811 if (status)
812 goto err_unroll_sched;
813
b36c598c
AV		 814 /* need a valid SW entry point to build a Tx tree */
815 if (!hw->sw_entry_point_layer) {
816 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
817 status = ICE_ERR_CFG;
818 goto err_unroll_sched;
819 }
9be1d6f8 820 INIT_LIST_HEAD(&hw->agg_list);
b36c598c 821
9daf8208
AV		 822 status = ice_init_fltr_mgmt_struct(hw);
823 if (status)
824 goto err_unroll_sched;
825
f203dca3
AV		 826 ice_dev_onetime_setup(hw);
827
d6fef10c
MFIP		 828 /* Get MAC information */
829 /* A single port can report up to two (LAN and WoL) addresses */
830 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
831 sizeof(struct ice_aqc_manage_mac_read_resp),
832 GFP_KERNEL);
833 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
dc49c772 834
63bb4e1e
WY		 835 if (!mac_buf) {
836 status = ICE_ERR_NO_MEMORY;
9daf8208 837 goto err_unroll_fltr_mgmt_struct;
63bb4e1e 838 }
dc49c772
AV		 839
840 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
841 devm_kfree(ice_hw_to_dev(hw), mac_buf);
842
843 if (status)
9daf8208 844 goto err_unroll_fltr_mgmt_struct;
dc49c772 845
22ef683b
AV		 846 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
847 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
cdedef59 848
f31e4b6f
AV		 849 return 0;
850
9daf8208
AV		 851err_unroll_fltr_mgmt_struct:
852 ice_cleanup_fltr_mgmt_struct(hw);
dc49c772
AV		 853err_unroll_sched:
854 ice_sched_cleanup_all(hw);
9c20346b
AV		 855err_unroll_alloc:
856 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
f31e4b6f 857err_unroll_cqinit:
5c91ecfd 858 ice_destroy_all_ctrlq(hw);
f31e4b6f
AV		 859 return status;
860}
861
862/**
863 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
864 * @hw: pointer to the hardware structure
ed14245a
AV		 865 *
866 * This should be called only during nominal operation, not as a result of
867 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
868 * applicable initializations if it fails for any reason.
f31e4b6f
AV		 869 */
870void ice_deinit_hw(struct ice_hw *hw)
871{
8b97ceb1
HT		 872 ice_cleanup_fltr_mgmt_struct(hw);
873
9c20346b 874 ice_sched_cleanup_all(hw);
9be1d6f8 875 ice_sched_clear_agg(hw);
dc49c772 876
9c20346b
AV		 877 if (hw->port_info) {
878 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
879 hw->port_info = NULL;
880 }
9daf8208 881
8b97ceb1
HT		 882 /* Attempt to disable FW logging before shutting down control queues */
883 ice_cfg_fw_log(hw, false);
5c91ecfd 884 ice_destroy_all_ctrlq(hw);
33e055fc
VR		 885
886 /* Clear VSI contexts if not already cleared */
887 ice_clear_all_vsi_ctx(hw);
f31e4b6f
AV		 888}
889
890/**
891 * ice_check_reset - Check to see if a global reset is complete
892 * @hw: pointer to the hardware structure
893 */
894enum ice_status ice_check_reset(struct ice_hw *hw)
895{
896 u32 cnt, reg = 0, grst_delay;
897
898 /* Poll for Device Active state in case a recent CORER, GLOBR,
899 * or EMPR has occurred. The grst delay value is in 100ms units.
900 * Add 1sec for outstanding AQ commands that can take a long time.
901 */
902 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
903 GLGEN_RSTCTL_GRSTDEL_S) + 10;
904
905 for (cnt = 0; cnt < grst_delay; cnt++) {
906 mdelay(100);
907 reg = rd32(hw, GLGEN_RSTAT);
908 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
909 break;
910 }
911
912 if (cnt == grst_delay) {
913 ice_debug(hw, ICE_DBG_INIT,
914 "Global reset polling failed to complete.\n");
915 return ICE_ERR_RESET_FAILED;
916 }
917
918#define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
919 GLNVM_ULD_GLOBR_DONE_M)
920
921 /* Device is Active; check Global Reset processes are done */
922 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
923 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
924 if (reg == ICE_RESET_DONE_MASK) {
925 ice_debug(hw, ICE_DBG_INIT,
926 "Global reset processes done. %d\n", cnt);
927 break;
928 }
929 mdelay(10);
930 }
931
932 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
933 ice_debug(hw, ICE_DBG_INIT,
934 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
935 reg);
936 return ICE_ERR_RESET_FAILED;
937 }
938
939 return 0;
940}
941
942/**
943 * ice_pf_reset - Reset the PF
944 * @hw: pointer to the hardware structure
945 *
946 * If a global reset has been triggered, this function checks
947 * for its completion and then issues the PF reset
948 */
949static enum ice_status ice_pf_reset(struct ice_hw *hw)
950{
951 u32 cnt, reg;
952
953 /* If at function entry a global reset was already in progress, i.e.
954 * state is not 'device active' or any of the reset done bits are not
955 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
956 * global reset is done.
957 */
958 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
959 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
960 /* poll on global reset currently in progress until done */
961 if (ice_check_reset(hw))
962 return ICE_ERR_RESET_FAILED;
963
964 return 0;
965 }
966
967 /* Reset the PF */
968 reg = rd32(hw, PFGEN_CTRL);
969
970 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
971
972 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
973 reg = rd32(hw, PFGEN_CTRL);
974 if (!(reg & PFGEN_CTRL_PFSWR_M))
975 break;
976
977 mdelay(1);
978 }
979
980 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
981 ice_debug(hw, ICE_DBG_INIT,
982 "PF reset polling failed to complete.\n");
983 return ICE_ERR_RESET_FAILED;
984 }
985
986 return 0;
987}
988
989/**
990 * ice_reset - Perform different types of reset
991 * @hw: pointer to the hardware structure
992 * @req: reset request
993 *
994 * This function triggers a reset as specified by the req parameter.
995 *
996 * Note:
997 * If anything other than a PF reset is triggered, PXE mode is restored.
998 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
999 * interface has been restored in the rebuild flow.
1000 */
1001enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1002{
1003 u32 val = 0;
1004
1005 switch (req) {
1006 case ICE_RESET_PFR:
1007 return ice_pf_reset(hw);
1008 case ICE_RESET_CORER:
1009 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1010 val = GLGEN_RTRIG_CORER_M;
1011 break;
1012 case ICE_RESET_GLOBR:
1013 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1014 val = GLGEN_RTRIG_GLOBR_M;
1015 break;
0f9d5027
AV		 1016 default:
1017 return ICE_ERR_PARAM;
f31e4b6f
AV		 1018 }
1019
1020 val |= rd32(hw, GLGEN_RTRIG);
1021 wr32(hw, GLGEN_RTRIG, val);
1022 ice_flush(hw);
1023
1024 /* wait for the FW to be ready */
1025 return ice_check_reset(hw);
1026}
1027
cdedef59
AV		 1028/**
1029 * ice_copy_rxq_ctx_to_hw
1030 * @hw: pointer to the hardware structure
1031 * @ice_rxq_ctx: pointer to the rxq context
d337f2af 1032 * @rxq_index: the index of the Rx queue
cdedef59 1033 *
f9867df6 1034 * Copies rxq context from dense structure to HW register space
cdedef59
AV		 1035 */
1036static enum ice_status
1037ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1038{
1039 u8 i;
1040
1041 if (!ice_rxq_ctx)
1042 return ICE_ERR_BAD_PTR;
1043
1044 if (rxq_index > QRX_CTRL_MAX_INDEX)
1045 return ICE_ERR_PARAM;
1046
f9867df6 1047 /* Copy each dword separately to HW */
cdedef59
AV		 1048 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1049 wr32(hw, QRX_CONTEXT(i, rxq_index),
1050 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1051
1052 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1053 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1054 }
1055
1056 return 0;
1057}
1058
1059/* LAN Rx Queue Context */
1060static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1061 /* Field Width LSB */
1062 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1063 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1064 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1065 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1066 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1067 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1068 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1069 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1070 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1071 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1072 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1073 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1074 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1075 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1076 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1077 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1078 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1079 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1080 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
c31a5c25 1081 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
cdedef59
AV		 1082 { 0 }
1083};
1084
1085/**
1086 * ice_write_rxq_ctx
1087 * @hw: pointer to the hardware structure
1088 * @rlan_ctx: pointer to the rxq context
d337f2af 1089 * @rxq_index: the index of the Rx queue
cdedef59
AV		 1090 *
1091 * Converts rxq context from sparse to dense structure and then writes
c31a5c25
BC		 1092 * it to HW register space and enables the hardware to prefetch descriptors
1093 * instead of only fetching them on demand
cdedef59
AV		 1094 */
1095enum ice_status
1096ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1097 u32 rxq_index)
1098{
1099 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1100
c31a5c25
BC		 1101 if (!rlan_ctx)
1102 return ICE_ERR_BAD_PTR;
1103
1104 rlan_ctx->prefena = 1;
1105
cdedef59
AV		 1106 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1107 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1108}
1109
1110/* LAN Tx Queue Context */
1111const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1112 /* Field Width LSB */
1113 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1114 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1115 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1116 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1117 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1118 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1119 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1120 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1121 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1122 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1123 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1124 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1125 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1126 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1127 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1128 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1129 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1130 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1131 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1132 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1133 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1134 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1135 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1136 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1137 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1138 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1139 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
1140 { 0 }
1141};
1142
7ec59eea
AV		 1143/**
1144 * ice_debug_cq
1145 * @hw: pointer to the hardware structure
1146 * @mask: debug mask
1147 * @desc: pointer to control queue descriptor
1148 * @buf: pointer to command buffer
1149 * @buf_len: max length of buf
1150 *
1151 * Dumps debug log about control command with descriptor contents.
1152 */
c8b7abdd
BA		 1153void
1154ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf,
1155 u16 buf_len)
7ec59eea
AV		 1156{
1157 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1158 u16 len;
1159
1160#ifndef CONFIG_DYNAMIC_DEBUG
1161 if (!(mask & hw->debug_mask))
1162 return;
1163#endif
1164
1165 if (!desc)
1166 return;
1167
1168 len = le16_to_cpu(cq_desc->datalen);
1169
1170 ice_debug(hw, mask,
1171 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1172 le16_to_cpu(cq_desc->opcode),
1173 le16_to_cpu(cq_desc->flags),
1174 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval));
1175 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1176 le32_to_cpu(cq_desc->cookie_high),
1177 le32_to_cpu(cq_desc->cookie_low));
1178 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
1179 le32_to_cpu(cq_desc->params.generic.param0),
1180 le32_to_cpu(cq_desc->params.generic.param1));
1181 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
1182 le32_to_cpu(cq_desc->params.generic.addr_high),
1183 le32_to_cpu(cq_desc->params.generic.addr_low));
1184 if (buf && cq_desc->datalen != 0) {
1185 ice_debug(hw, mask, "Buffer:\n");
1186 if (buf_len < len)
1187 len = buf_len;
1188
1189 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1190 }
1191}
1192
1193/* FW Admin Queue command wrappers */
1194
1195/**
1196 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
f9867df6 1197 * @hw: pointer to the HW struct
7ec59eea
AV		 1198 * @desc: descriptor describing the command
1199 * @buf: buffer to use for indirect commands (NULL for direct commands)
1200 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1201 * @cd: pointer to command details structure
1202 *
1203 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1204 */
1205enum ice_status
1206ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1207 u16 buf_size, struct ice_sq_cd *cd)
1208{
1209 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1210}
1211
1212/**
1213 * ice_aq_get_fw_ver
f9867df6 1214 * @hw: pointer to the HW struct
7ec59eea
AV		 1215 * @cd: pointer to command details structure or NULL
1216 *
1217 * Get the firmware version (0x0001) from the admin queue commands
1218 */
1219enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1220{
1221 struct ice_aqc_get_ver *resp;
1222 struct ice_aq_desc desc;
1223 enum ice_status status;
1224
1225 resp = &desc.params.get_ver;
1226
1227 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1228
1229 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1230
1231 if (!status) {
1232 hw->fw_branch = resp->fw_branch;
1233 hw->fw_maj_ver = resp->fw_major;
1234 hw->fw_min_ver = resp->fw_minor;
1235 hw->fw_patch = resp->fw_patch;
1236 hw->fw_build = le32_to_cpu(resp->fw_build);
1237 hw->api_branch = resp->api_branch;
1238 hw->api_maj_ver = resp->api_major;
1239 hw->api_min_ver = resp->api_minor;
1240 hw->api_patch = resp->api_patch;
1241 }
1242
1243 return status;
1244}
1245
1246/**
1247 * ice_aq_q_shutdown
f9867df6 1248 * @hw: pointer to the HW struct
7ec59eea
AV		 1249 * @unloading: is the driver unloading itself
1250 *
1251 * Tell the Firmware that we're shutting down the AdminQ and whether
1252 * or not the driver is unloading as well (0x0003).
1253 */
1254enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1255{
1256 struct ice_aqc_q_shutdown *cmd;
1257 struct ice_aq_desc desc;
1258
1259 cmd = &desc.params.q_shutdown;
1260
1261 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1262
1263 if (unloading)
1264 cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING);
1265
1266 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1267}
f31e4b6f
AV		 1268
1269/**
1270 * ice_aq_req_res
f9867df6
AV		 1271 * @hw: pointer to the HW struct
1272 * @res: resource ID
f31e4b6f
AV		 1273 * @access: access type
1274 * @sdp_number: resource number
1275 * @timeout: the maximum time in ms that the driver may hold the resource
1276 * @cd: pointer to command details structure or NULL
1277 *
ff2b1321
DN		 1278 * Requests common resource using the admin queue commands (0x0008).
1279 * When attempting to acquire the Global Config Lock, the driver can
1280 * learn of three states:
1281 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1282 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1283 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1284 * successfully downloaded the package; the driver does
1285 * not have to download the package and can continue
1286 * loading
1287 *
1288 * Note that if the caller is in an acquire lock, perform action, release lock
1289 * phase of operation, it is possible that the FW may detect a timeout and issue
1290 * a CORER. In this case, the driver will receive a CORER interrupt and will
1291 * have to determine its cause. The calling thread that is handling this flow
1292 * will likely get an error propagated back to it indicating the Download
1293 * Package, Update Package or the Release Resource AQ commands timed out.
f31e4b6f
AV		 1294 */
1295static enum ice_status
1296ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1297 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1298 struct ice_sq_cd *cd)
1299{
1300 struct ice_aqc_req_res *cmd_resp;
1301 struct ice_aq_desc desc;
1302 enum ice_status status;
1303
1304 cmd_resp = &desc.params.res_owner;
1305
1306 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1307
1308 cmd_resp->res_id = cpu_to_le16(res);
1309 cmd_resp->access_type = cpu_to_le16(access);
1310 cmd_resp->res_number = cpu_to_le32(sdp_number);
ff2b1321
DN		 1311 cmd_resp->timeout = cpu_to_le32(*timeout);
1312 *timeout = 0;
f31e4b6f
AV		 1313
1314 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
ff2b1321 1315
f31e4b6f
AV		 1316 /* The completion specifies the maximum time in ms that the driver
1317 * may hold the resource in the Timeout field.
ff2b1321
DN		 1318 */
1319
1320 /* Global config lock response utilizes an additional status field.
1321 *
1322 * If the Global config lock resource is held by some other driver, the
1323 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1324 * and the timeout field indicates the maximum time the current owner
1325 * of the resource has to free it.
1326 */
1327 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1328 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1329 *timeout = le32_to_cpu(cmd_resp->timeout);
1330 return 0;
1331 } else if (le16_to_cpu(cmd_resp->status) ==
1332 ICE_AQ_RES_GLBL_IN_PROG) {
1333 *timeout = le32_to_cpu(cmd_resp->timeout);
1334 return ICE_ERR_AQ_ERROR;
1335 } else if (le16_to_cpu(cmd_resp->status) ==
1336 ICE_AQ_RES_GLBL_DONE) {
1337 return ICE_ERR_AQ_NO_WORK;
1338 }
1339
1340 /* invalid FW response, force a timeout immediately */
1341 *timeout = 0;
1342 return ICE_ERR_AQ_ERROR;
1343 }
1344
1345 /* If the resource is held by some other driver, the command completes
1346 * with a busy return value and the timeout field indicates the maximum
1347 * time the current owner of the resource has to free it.
f31e4b6f
AV		 1348 */
1349 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1350 *timeout = le32_to_cpu(cmd_resp->timeout);
1351
1352 return status;
1353}
1354
1355/**
1356 * ice_aq_release_res
f9867df6
AV		 1357 * @hw: pointer to the HW struct
1358 * @res: resource ID
f31e4b6f
AV		 1359 * @sdp_number: resource number
1360 * @cd: pointer to command details structure or NULL
1361 *
1362 * release common resource using the admin queue commands (0x0009)
1363 */
1364static enum ice_status
1365ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1366 struct ice_sq_cd *cd)
1367{
1368 struct ice_aqc_req_res *cmd;
1369 struct ice_aq_desc desc;
1370
1371 cmd = &desc.params.res_owner;
1372
1373 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1374
1375 cmd->res_id = cpu_to_le16(res);
1376 cmd->res_number = cpu_to_le32(sdp_number);
1377
1378 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1379}
1380
1381/**
1382 * ice_acquire_res
1383 * @hw: pointer to the HW structure
f9867df6 1384 * @res: resource ID
f31e4b6f 1385 * @access: access type (read or write)
ff2b1321 1386 * @timeout: timeout in milliseconds
f31e4b6f
AV		 1387 *
1388 * This function will attempt to acquire the ownership of a resource.
1389 */
1390enum ice_status
1391ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
ff2b1321 1392 enum ice_aq_res_access_type access, u32 timeout)
f31e4b6f
AV		 1393{
1394#define ICE_RES_POLLING_DELAY_MS 10
1395 u32 delay = ICE_RES_POLLING_DELAY_MS;
ff2b1321 1396 u32 time_left = timeout;
f31e4b6f 1397 enum ice_status status;
f31e4b6f
AV		 1398
1399 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1400
ff2b1321
DN		 1401 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1402 * previously acquired the resource and performed any necessary updates;
1403 * in this case the caller does not obtain the resource and has no
1404 * further work to do.
f31e4b6f 1405 */
ff2b1321 1406 if (status == ICE_ERR_AQ_NO_WORK)
f31e4b6f 1407 goto ice_acquire_res_exit;
f31e4b6f
AV		 1408
1409 if (status)
1410 ice_debug(hw, ICE_DBG_RES,
1411 "resource %d acquire type %d failed.\n", res, access);
1412
1413 /* If necessary, poll until the current lock owner timeouts */
1414 timeout = time_left;
1415 while (status && timeout && time_left) {
1416 mdelay(delay);
1417 timeout = (timeout > delay) ? timeout - delay : 0;
1418 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1419
ff2b1321 1420 if (status == ICE_ERR_AQ_NO_WORK)
f31e4b6f 1421 /* lock free, but no work to do */
f31e4b6f 1422 break;
f31e4b6f
AV		 1423
1424 if (!status)
1425 /* lock acquired */
1426 break;
1427 }
1428 if (status && status != ICE_ERR_AQ_NO_WORK)
1429 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1430
1431ice_acquire_res_exit:
1432 if (status == ICE_ERR_AQ_NO_WORK) {
1433 if (access == ICE_RES_WRITE)
1434 ice_debug(hw, ICE_DBG_RES,
1435 "resource indicates no work to do.\n");
1436 else
1437 ice_debug(hw, ICE_DBG_RES,
1438 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1439 }
1440 return status;
1441}
1442
1443/**
1444 * ice_release_res
1445 * @hw: pointer to the HW structure
f9867df6 1446 * @res: resource ID
f31e4b6f
AV		 1447 *
1448 * This function will release a resource using the proper Admin Command.
1449 */
1450void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1451{
1452 enum ice_status status;
1453 u32 total_delay = 0;
1454
1455 status = ice_aq_release_res(hw, res, 0, NULL);
1456
1457 /* there are some rare cases when trying to release the resource
f9867df6 1458 * results in an admin queue timeout, so handle them correctly
f31e4b6f
AV		 1459 */
1460 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1461 (total_delay < hw->adminq.sq_cmd_timeout)) {
1462 mdelay(1);
1463 status = ice_aq_release_res(hw, res, 0, NULL);
1464 total_delay++;
1465 }
1466}
1467
995c90f2 1468/**
7a1f7111 1469 * ice_get_num_per_func - determine number of resources per PF
f9867df6 1470 * @hw: pointer to the HW structure
7a1f7111 1471 * @max: value to be evenly split between each PF
995c90f2
AV		 1472 *
1473 * Determine the number of valid functions by going through the bitmap returned
7a1f7111
BC		 1474 * from parsing capabilities and use this to calculate the number of resources
1475 * per PF based on the max value passed in.
995c90f2 1476 */
7a1f7111 1477static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
995c90f2
AV		 1478{
1479 u8 funcs;
1480
1481#define ICE_CAPS_VALID_FUNCS_M 0xFF
1482 funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
1483 ICE_CAPS_VALID_FUNCS_M);
1484
1485 if (!funcs)
1486 return 0;
1487
7a1f7111 1488 return max / funcs;
995c90f2
AV		 1489}
1490
9c20346b
AV		 1491/**
1492 * ice_parse_caps - parse function/device capabilities
f9867df6 1493 * @hw: pointer to the HW struct
9c20346b
AV		 1494 * @buf: pointer to a buffer containing function/device capability records
1495 * @cap_count: number of capability records in the list
1496 * @opc: type of capabilities list to parse
1497 *
1498 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1499 */
1500static void
1501ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1502 enum ice_adminq_opc opc)
1503{
1504 struct ice_aqc_list_caps_elem *cap_resp;
1505 struct ice_hw_func_caps *func_p = NULL;
1506 struct ice_hw_dev_caps *dev_p = NULL;
1507 struct ice_hw_common_caps *caps;
a84db525 1508 char const *prefix;
9c20346b
AV		 1509 u32 i;
1510
1511 if (!buf)
1512 return;
1513
1514 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1515
1516 if (opc == ice_aqc_opc_list_dev_caps) {
1517 dev_p = &hw->dev_caps;
1518 caps = &dev_p->common_cap;
a84db525 1519 prefix = "dev cap";
9c20346b
AV		 1520 } else if (opc == ice_aqc_opc_list_func_caps) {
1521 func_p = &hw->func_caps;
1522 caps = &func_p->common_cap;
a84db525 1523 prefix = "func cap";
9c20346b
AV		 1524 } else {
1525 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1526 return;
1527 }
1528
1529 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1530 u32 logical_id = le32_to_cpu(cap_resp->logical_id);
1531 u32 phys_id = le32_to_cpu(cap_resp->phys_id);
1532 u32 number = le32_to_cpu(cap_resp->number);
1533 u16 cap = le16_to_cpu(cap_resp->cap);
1534
1535 switch (cap) {
995c90f2
AV		 1536 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1537 caps->valid_functions = number;
1538 ice_debug(hw, ICE_DBG_INIT,
a84db525 1539 "%s: valid functions = %d\n", prefix,
995c90f2
AV		 1540 caps->valid_functions);
1541 break;
75d2b253
AV		 1542 case ICE_AQC_CAPS_SRIOV:
1543 caps->sr_iov_1_1 = (number == 1);
1544 ice_debug(hw, ICE_DBG_INIT,
a84db525
AV		 1545 "%s: SR-IOV = %d\n", prefix,
1546 caps->sr_iov_1_1);
75d2b253
AV		 1547 break;
1548 case ICE_AQC_CAPS_VF:
1549 if (dev_p) {
1550 dev_p->num_vfs_exposed = number;
1551 ice_debug(hw, ICE_DBG_INIT,
a84db525 1552 "%s: VFs exposed = %d\n", prefix,
75d2b253
AV		 1553 dev_p->num_vfs_exposed);
1554 } else if (func_p) {
1555 func_p->num_allocd_vfs = number;
1556 func_p->vf_base_id = logical_id;
1557 ice_debug(hw, ICE_DBG_INIT,
a84db525 1558 "%s: VFs allocated = %d\n", prefix,
75d2b253
AV		 1559 func_p->num_allocd_vfs);
1560 ice_debug(hw, ICE_DBG_INIT,
a84db525 1561 "%s: VF base_id = %d\n", prefix,
75d2b253
AV		 1562 func_p->vf_base_id);
1563 }
1564 break;
9c20346b
AV		 1565 case ICE_AQC_CAPS_VSI:
1566 if (dev_p) {
1567 dev_p->num_vsi_allocd_to_host = number;
1568 ice_debug(hw, ICE_DBG_INIT,
a84db525
AV		 1569 "%s: num VSI alloc to host = %d\n",
1570 prefix,
9c20346b
AV		 1571 dev_p->num_vsi_allocd_to_host);
1572 } else if (func_p) {
7a1f7111
BC		 1573 func_p->guar_num_vsi =
1574 ice_get_num_per_func(hw, ICE_MAX_VSI);
9c20346b 1575 ice_debug(hw, ICE_DBG_INIT,
a84db525
AV		 1576 "%s: num guaranteed VSI (fw) = %d\n",
1577 prefix, number);
1578 ice_debug(hw, ICE_DBG_INIT,
1579 "%s: num guaranteed VSI = %d\n",
1580 prefix, func_p->guar_num_vsi);
9c20346b
AV		 1581 }
1582 break;
1583 case ICE_AQC_CAPS_RSS:
1584 caps->rss_table_size = number;
1585 caps->rss_table_entry_width = logical_id;
1586 ice_debug(hw, ICE_DBG_INIT,
a84db525 1587 "%s: RSS table size = %d\n", prefix,
9c20346b
AV		 1588 caps->rss_table_size);
1589 ice_debug(hw, ICE_DBG_INIT,
a84db525 1590 "%s: RSS table width = %d\n", prefix,
9c20346b
AV		 1591 caps->rss_table_entry_width);
1592 break;
1593 case ICE_AQC_CAPS_RXQS:
1594 caps->num_rxq = number;
1595 caps->rxq_first_id = phys_id;
1596 ice_debug(hw, ICE_DBG_INIT,
a84db525
AV		 1597 "%s: num Rx queues = %d\n", prefix,
1598 caps->num_rxq);
9c20346b 1599 ice_debug(hw, ICE_DBG_INIT,
a84db525 1600 "%s: Rx first queue ID = %d\n", prefix,
9c20346b
AV		 1601 caps->rxq_first_id);
1602 break;
1603 case ICE_AQC_CAPS_TXQS:
1604 caps->num_txq = number;
1605 caps->txq_first_id = phys_id;
1606 ice_debug(hw, ICE_DBG_INIT,
a84db525
AV		 1607 "%s: num Tx queues = %d\n", prefix,
1608 caps->num_txq);
9c20346b 1609 ice_debug(hw, ICE_DBG_INIT,
a84db525 1610 "%s: Tx first queue ID = %d\n", prefix,
9c20346b
AV		 1611 caps->txq_first_id);
1612 break;
1613 case ICE_AQC_CAPS_MSIX:
1614 caps->num_msix_vectors = number;
1615 caps->msix_vector_first_id = phys_id;
1616 ice_debug(hw, ICE_DBG_INIT,
a84db525 1617 "%s: MSIX vector count = %d\n", prefix,
9c20346b
AV		 1618 caps->num_msix_vectors);
1619 ice_debug(hw, ICE_DBG_INIT,
a84db525 1620 "%s: MSIX first vector index = %d\n", prefix,
9c20346b
AV		 1621 caps->msix_vector_first_id);
1622 break;
1623 case ICE_AQC_CAPS_MAX_MTU:
1624 caps->max_mtu = number;
a84db525
AV		 1625 ice_debug(hw, ICE_DBG_INIT, "%s: max MTU = %d\n",
1626 prefix, caps->max_mtu);
9c20346b
AV		 1627 break;
1628 default:
1629 ice_debug(hw, ICE_DBG_INIT,
a84db525
AV		 1630 "%s: unknown capability[%d]: 0x%x\n", prefix,
1631 i, cap);
9c20346b
AV		 1632 break;
1633 }
1634 }
1635}
1636
1637/**
1638 * ice_aq_discover_caps - query function/device capabilities
f9867df6 1639 * @hw: pointer to the HW struct
9c20346b
AV		 1640 * @buf: a virtual buffer to hold the capabilities
1641 * @buf_size: Size of the virtual buffer
7d86cf38 1642 * @cap_count: cap count needed if AQ err==ENOMEM
9c20346b
AV		 1643 * @opc: capabilities type to discover - pass in the command opcode
1644 * @cd: pointer to command details structure or NULL
1645 *
1646 * Get the function(0x000a)/device(0x000b) capabilities description from
1647 * the firmware.
1648 */
1649static enum ice_status
7d86cf38 1650ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
9c20346b
AV		 1651 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1652{
1653 struct ice_aqc_list_caps *cmd;
1654 struct ice_aq_desc desc;
1655 enum ice_status status;
1656
1657 cmd = &desc.params.get_cap;
1658
1659 if (opc != ice_aqc_opc_list_func_caps &&
1660 opc != ice_aqc_opc_list_dev_caps)
1661 return ICE_ERR_PARAM;
1662
1663 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1664
1665 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1666 if (!status)
1667 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc);
7d86cf38 1668 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
99189e8b 1669 *cap_count = le32_to_cpu(cmd->count);
9c20346b
AV		 1670 return status;
1671}
1672
1673/**
7d86cf38 1674 * ice_discover_caps - get info about the HW
9c20346b 1675 * @hw: pointer to the hardware structure
7d86cf38 1676 * @opc: capabilities type to discover - pass in the command opcode
9c20346b 1677 */
c8b7abdd
BA		 1678static enum ice_status
1679ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
9c20346b
AV		 1680{
1681 enum ice_status status;
7d86cf38 1682 u32 cap_count;
9c20346b
AV		 1683 u16 cbuf_len;
1684 u8 retries;
1685
1686 /* The driver doesn't know how many capabilities the device will return
1687 * so the buffer size required isn't known ahead of time. The driver
1688 * starts with cbuf_len and if this turns out to be insufficient, the
7d86cf38
AV		 1689 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1690 * The driver then allocates the buffer based on the count and retries
1691 * the operation. So it follows that the retry count is 2.
9c20346b
AV		 1692 */
1693#define ICE_GET_CAP_BUF_COUNT 40
1694#define ICE_GET_CAP_RETRY_COUNT 2
1695
7d86cf38 1696 cap_count = ICE_GET_CAP_BUF_COUNT;
9c20346b
AV		 1697 retries = ICE_GET_CAP_RETRY_COUNT;
1698
1699 do {
1700 void *cbuf;
1701
7d86cf38
AV		 1702 cbuf_len = (u16)(cap_count *
1703 sizeof(struct ice_aqc_list_caps_elem));
9c20346b
AV		 1704 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL);
1705 if (!cbuf)
1706 return ICE_ERR_NO_MEMORY;
1707
7d86cf38
AV		 1708 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
1709 opc, NULL);
9c20346b
AV		 1710 devm_kfree(ice_hw_to_dev(hw), cbuf);
1711
1712 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
1713 break;
1714
1715 /* If ENOMEM is returned, try again with bigger buffer */
9c20346b
AV		 1716 } while (--retries);
1717
1718 return status;
1719}
1720
7d86cf38
AV		 1721/**
1722 * ice_get_caps - get info about the HW
1723 * @hw: pointer to the hardware structure
1724 */
1725enum ice_status ice_get_caps(struct ice_hw *hw)
1726{
1727 enum ice_status status;
1728
1729 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
1730 if (!status)
1731 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
1732
1733 return status;
1734}
1735
e94d4478
AV		 1736/**
1737 * ice_aq_manage_mac_write - manage MAC address write command
f9867df6 1738 * @hw: pointer to the HW struct
e94d4478
AV		 1739 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
1740 * @flags: flags to control write behavior
1741 * @cd: pointer to command details structure or NULL
1742 *
1743 * This function is used to write MAC address to the NVM (0x0108).
1744 */
1745enum ice_status
d671e3e0 1746ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
e94d4478
AV		 1747 struct ice_sq_cd *cd)
1748{
1749 struct ice_aqc_manage_mac_write *cmd;
1750 struct ice_aq_desc desc;
1751
1752 cmd = &desc.params.mac_write;
1753 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
1754
1755 cmd->flags = flags;
1756
1757 /* Prep values for flags, sah, sal */
d671e3e0
JK		 1758 cmd->sah = htons(*((const u16 *)mac_addr));
1759 cmd->sal = htonl(*((const u32 *)(mac_addr + 2)));
e94d4478
AV		 1760
1761 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1762}
1763
f31e4b6f
AV		 1764/**
1765 * ice_aq_clear_pxe_mode
f9867df6 1766 * @hw: pointer to the HW struct
f31e4b6f
AV		 1767 *
1768 * Tell the firmware that the driver is taking over from PXE (0x0110).
1769 */
1770static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
1771{
1772 struct ice_aq_desc desc;
1773
1774 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
1775 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
1776
1777 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1778}
1779
1780/**
1781 * ice_clear_pxe_mode - clear pxe operations mode
f9867df6 1782 * @hw: pointer to the HW struct
f31e4b6f
AV		 1783 *
1784 * Make sure all PXE mode settings are cleared, including things
1785 * like descriptor fetch/write-back mode.
1786 */
1787void ice_clear_pxe_mode(struct ice_hw *hw)
1788{
1789 if (ice_check_sq_alive(hw, &hw->adminq))
1790 ice_aq_clear_pxe_mode(hw);
1791}
cdedef59 1792
48cb27f2
CC		 1793/**
1794 * ice_get_link_speed_based_on_phy_type - returns link speed
1795 * @phy_type_low: lower part of phy_type
aef74145 1796 * @phy_type_high: higher part of phy_type
48cb27f2 1797 *
f9867df6 1798 * This helper function will convert an entry in PHY type structure
aef74145
AV		 1799 * [phy_type_low, phy_type_high] to its corresponding link speed.
1800 * Note: In the structure of [phy_type_low, phy_type_high], there should
f9867df6 1801 * be one bit set, as this function will convert one PHY type to its
48cb27f2 1802 * speed.
48cb27f2
CC		 1803 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
1804 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
1805 */
aef74145
AV		 1806static u16
1807ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
48cb27f2 1808{
aef74145 1809 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
48cb27f2
CC		 1810 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
1811
1812 switch (phy_type_low) {
1813 case ICE_PHY_TYPE_LOW_100BASE_TX:
1814 case ICE_PHY_TYPE_LOW_100M_SGMII:
1815 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
1816 break;
1817 case ICE_PHY_TYPE_LOW_1000BASE_T:
1818 case ICE_PHY_TYPE_LOW_1000BASE_SX:
1819 case ICE_PHY_TYPE_LOW_1000BASE_LX:
1820 case ICE_PHY_TYPE_LOW_1000BASE_KX:
1821 case ICE_PHY_TYPE_LOW_1G_SGMII:
1822 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
1823 break;
1824 case ICE_PHY_TYPE_LOW_2500BASE_T:
1825 case ICE_PHY_TYPE_LOW_2500BASE_X:
1826 case ICE_PHY_TYPE_LOW_2500BASE_KX:
1827 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
1828 break;
1829 case ICE_PHY_TYPE_LOW_5GBASE_T:
1830 case ICE_PHY_TYPE_LOW_5GBASE_KR:
1831 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
1832 break;
1833 case ICE_PHY_TYPE_LOW_10GBASE_T:
1834 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
1835 case ICE_PHY_TYPE_LOW_10GBASE_SR:
1836 case ICE_PHY_TYPE_LOW_10GBASE_LR:
1837 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
1838 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
1839 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
1840 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
1841 break;
1842 case ICE_PHY_TYPE_LOW_25GBASE_T:
1843 case ICE_PHY_TYPE_LOW_25GBASE_CR:
1844 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
1845 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
1846 case ICE_PHY_TYPE_LOW_25GBASE_SR:
1847 case ICE_PHY_TYPE_LOW_25GBASE_LR:
1848 case ICE_PHY_TYPE_LOW_25GBASE_KR:
1849 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
1850 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
1851 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
1852 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
1853 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
1854 break;
1855 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
1856 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
1857 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
1858 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
1859 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
1860 case ICE_PHY_TYPE_LOW_40G_XLAUI:
1861 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
1862 break;
aef74145
AV		 1863 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
1864 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
1865 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
1866 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
1867 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
1868 case ICE_PHY_TYPE_LOW_50G_LAUI2:
1869 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
1870 case ICE_PHY_TYPE_LOW_50G_AUI2:
1871 case ICE_PHY_TYPE_LOW_50GBASE_CP:
1872 case ICE_PHY_TYPE_LOW_50GBASE_SR:
1873 case ICE_PHY_TYPE_LOW_50GBASE_FR:
1874 case ICE_PHY_TYPE_LOW_50GBASE_LR:
1875 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
1876 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
1877 case ICE_PHY_TYPE_LOW_50G_AUI1:
1878 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
1879 break;
1880 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
1881 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
1882 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
1883 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
1884 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
1885 case ICE_PHY_TYPE_LOW_100G_CAUI4:
1886 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
1887 case ICE_PHY_TYPE_LOW_100G_AUI4:
1888 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
1889 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
1890 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
1891 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
1892 case ICE_PHY_TYPE_LOW_100GBASE_DR:
1893 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
1894 break;
48cb27f2
CC		 1895 default:
1896 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
1897 break;
1898 }
1899
aef74145
AV		 1900 switch (phy_type_high) {
1901 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
1902 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
1903 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
1904 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
1905 case ICE_PHY_TYPE_HIGH_100G_AUI2:
1906 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
1907 break;
1908 default:
1909 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
1910 break;
1911 }
1912
1913 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
1914 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
1915 return ICE_AQ_LINK_SPEED_UNKNOWN;
1916 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
1917 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
1918 return ICE_AQ_LINK_SPEED_UNKNOWN;
1919 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
1920 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
1921 return speed_phy_type_low;
1922 else
1923 return speed_phy_type_high;
48cb27f2
CC		 1924}
1925
1926/**
1927 * ice_update_phy_type
1928 * @phy_type_low: pointer to the lower part of phy_type
aef74145 1929 * @phy_type_high: pointer to the higher part of phy_type
48cb27f2
CC		 1930 * @link_speeds_bitmap: targeted link speeds bitmap
1931 *
1932 * Note: For the link_speeds_bitmap structure, you can check it at
1933 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
1934 * link_speeds_bitmap include multiple speeds.
1935 *
aef74145
AV		 1936 * Each entry in this [phy_type_low, phy_type_high] structure will
1937 * present a certain link speed. This helper function will turn on bits
1938 * in [phy_type_low, phy_type_high] structure based on the value of
48cb27f2
CC		 1939 * link_speeds_bitmap input parameter.
1940 */
aef74145
AV		 1941void
1942ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
1943 u16 link_speeds_bitmap)
48cb27f2 1944{
aef74145 1945 u64 pt_high;
48cb27f2
CC		 1946 u64 pt_low;
1947 int index;
207e3721 1948 u16 speed;
48cb27f2
CC		 1949
1950 /* We first check with low part of phy_type */
1951 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
1952 pt_low = BIT_ULL(index);
aef74145 1953 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
48cb27f2
CC		 1954
1955 if (link_speeds_bitmap & speed)
1956 *phy_type_low |= BIT_ULL(index);
1957 }
aef74145
AV		 1958
1959 /* We then check with high part of phy_type */
1960 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
1961 pt_high = BIT_ULL(index);
1962 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
1963
1964 if (link_speeds_bitmap & speed)
1965 *phy_type_high |= BIT_ULL(index);
1966 }
48cb27f2
CC		 1967}
1968
fcea6f3d
AV		 1969/**
1970 * ice_aq_set_phy_cfg
f9867df6 1971 * @hw: pointer to the HW struct
fcea6f3d
AV		 1972 * @lport: logical port number
1973 * @cfg: structure with PHY configuration data to be set
1974 * @cd: pointer to command details structure or NULL
1975 *
1976 * Set the various PHY configuration parameters supported on the Port.
1977 * One or more of the Set PHY config parameters may be ignored in an MFP
1978 * mode as the PF may not have the privilege to set some of the PHY Config
1979 * parameters. This status will be indicated by the command response (0x0601).
1980 */
48cb27f2 1981enum ice_status
fcea6f3d
AV		 1982ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
1983 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
1984{
fcea6f3d
AV		 1985 struct ice_aq_desc desc;
1986
1987 if (!cfg)
1988 return ICE_ERR_PARAM;
1989
d8df260a
CC		 1990 /* Ensure that only valid bits of cfg->caps can be turned on. */
1991 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
1992 ice_debug(hw, ICE_DBG_PHY,
1993 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
1994 cfg->caps);
1995
1996 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
1997 }
1998
fcea6f3d 1999 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
48cb27f2
CC		 2000 desc.params.set_phy.lport_num = lport;
2001 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
fcea6f3d
AV		 2002
2003 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2004}
2005
2006/**
2007 * ice_update_link_info - update status of the HW network link
2008 * @pi: port info structure of the interested logical port
2009 */
5755143d 2010enum ice_status ice_update_link_info(struct ice_port_info *pi)
fcea6f3d 2011{
092a33d4 2012 struct ice_link_status *li;
fcea6f3d 2013 enum ice_status status;
fcea6f3d
AV		 2014
2015 if (!pi)
2016 return ICE_ERR_PARAM;
2017
092a33d4 2018 li = &pi->phy.link_info;
fcea6f3d 2019
fcea6f3d
AV		 2020 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2021 if (status)
092a33d4
BA		 2022 return status;
2023
2024 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2025 struct ice_aqc_get_phy_caps_data *pcaps;
2026 struct ice_hw *hw;
2027
2028 hw = pi->hw;
2029 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps),
2030 GFP_KERNEL);
2031 if (!pcaps)
2032 return ICE_ERR_NO_MEMORY;
fcea6f3d 2033
fcea6f3d
AV		 2034 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,
2035 pcaps, NULL);
092a33d4
BA		 2036 if (!status)
2037 memcpy(li->module_type, &pcaps->module_type,
2038 sizeof(li->module_type));
fcea6f3d 2039
092a33d4 2040 devm_kfree(ice_hw_to_dev(hw), pcaps);
fcea6f3d 2041 }
092a33d4 2042
fcea6f3d
AV		 2043 return status;
2044}
2045
2046/**
2047 * ice_set_fc
2048 * @pi: port information structure
2049 * @aq_failures: pointer to status code, specific to ice_set_fc routine
48cb27f2 2050 * @ena_auto_link_update: enable automatic link update
fcea6f3d
AV		 2051 *
2052 * Set the requested flow control mode.
2053 */
2054enum ice_status
48cb27f2 2055ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
fcea6f3d
AV		 2056{
2057 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2058 struct ice_aqc_get_phy_caps_data *pcaps;
2059 enum ice_status status;
2060 u8 pause_mask = 0x0;
2061 struct ice_hw *hw;
2062
2063 if (!pi)
2064 return ICE_ERR_PARAM;
2065 hw = pi->hw;
2066 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2067
2068 switch (pi->fc.req_mode) {
2069 case ICE_FC_FULL:
2070 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2071 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2072 break;
2073 case ICE_FC_RX_PAUSE:
2074 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2075 break;
2076 case ICE_FC_TX_PAUSE:
2077 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2078 break;
2079 default:
2080 break;
2081 }
2082
2083 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
2084 if (!pcaps)
2085 return ICE_ERR_NO_MEMORY;
2086
f9867df6 2087 /* Get the current PHY config */
fcea6f3d
AV		 2088 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2089 NULL);
2090 if (status) {
2091 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2092 goto out;
2093 }
2094
2095 /* clear the old pause settings */
2096 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2097 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
d8df260a 2098
fcea6f3d
AV		 2099 /* set the new capabilities */
2100 cfg.caps |= pause_mask;
d8df260a 2101
fcea6f3d
AV		 2102 /* If the capabilities have changed, then set the new config */
2103 if (cfg.caps != pcaps->caps) {
2104 int retry_count, retry_max = 10;
2105
2106 /* Auto restart link so settings take effect */
48cb27f2
CC		 2107 if (ena_auto_link_update)
2108 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
fcea6f3d 2109 /* Copy over all the old settings */
aef74145 2110 cfg.phy_type_high = pcaps->phy_type_high;
fcea6f3d
AV		 2111 cfg.phy_type_low = pcaps->phy_type_low;
2112 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2113 cfg.eee_cap = pcaps->eee_cap;
2114 cfg.eeer_value = pcaps->eeer_value;
2115 cfg.link_fec_opt = pcaps->link_fec_options;
2116
2117 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2118 if (status) {
2119 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2120 goto out;
2121 }
2122
2123 /* Update the link info
2124 * It sometimes takes a really long time for link to
2125 * come back from the atomic reset. Thus, we wait a
2126 * little bit.
2127 */
2128 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2129 status = ice_update_link_info(pi);
2130
2131 if (!status)
2132 break;
2133
2134 mdelay(100);
2135 }
2136
2137 if (status)
2138 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2139 }
2140
2141out:
2142 devm_kfree(ice_hw_to_dev(hw), pcaps);
2143 return status;
2144}
2145
f776b3ac
PG		 2146/**
2147 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2148 * @caps: PHY ability structure to copy date from
2149 * @cfg: PHY configuration structure to copy data to
2150 *
2151 * Helper function to copy AQC PHY get ability data to PHY set configuration
2152 * data structure
2153 */
2154void
2155ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2156 struct ice_aqc_set_phy_cfg_data *cfg)
2157{
2158 if (!caps || !cfg)
2159 return;
2160
2161 cfg->phy_type_low = caps->phy_type_low;
2162 cfg->phy_type_high = caps->phy_type_high;
2163 cfg->caps = caps->caps;
2164 cfg->low_power_ctrl = caps->low_power_ctrl;
2165 cfg->eee_cap = caps->eee_cap;
2166 cfg->eeer_value = caps->eeer_value;
2167 cfg->link_fec_opt = caps->link_fec_options;
2168}
2169
2170/**
2171 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2172 * @cfg: PHY configuration data to set FEC mode
2173 * @fec: FEC mode to configure
2174 *
2175 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2176 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2177 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2178 */
2179void
2180ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2181{
2182 switch (fec) {
2183 case ICE_FEC_BASER:
2184 /* Clear auto FEC and RS bits, and AND BASE-R ability
2185 * bits and OR request bits.
2186 */
2187 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2188 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2189 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2190 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2191 ICE_AQC_PHY_FEC_25G_KR_REQ;
2192 break;
2193 case ICE_FEC_RS:
2194 /* Clear auto FEC and BASE-R bits, and AND RS ability
2195 * bits and OR request bits.
2196 */
2197 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2198 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2199 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2200 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2201 break;
2202 case ICE_FEC_NONE:
2203 /* Clear auto FEC and all FEC option bits. */
2204 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2205 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2206 break;
2207 case ICE_FEC_AUTO:
2208 /* AND auto FEC bit, and all caps bits. */
2209 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2210 break;
2211 }
2212}
2213
0b28b702
AV		 2214/**
2215 * ice_get_link_status - get status of the HW network link
2216 * @pi: port information structure
2217 * @link_up: pointer to bool (true/false = linkup/linkdown)
2218 *
2219 * Variable link_up is true if link is up, false if link is down.
2220 * The variable link_up is invalid if status is non zero. As a
2221 * result of this call, link status reporting becomes enabled
2222 */
2223enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2224{
2225 struct ice_phy_info *phy_info;
2226 enum ice_status status = 0;
2227
c7f2c42b 2228 if (!pi || !link_up)
0b28b702
AV		 2229 return ICE_ERR_PARAM;
2230
2231 phy_info = &pi->phy;
2232
2233 if (phy_info->get_link_info) {
2234 status = ice_update_link_info(pi);
2235
2236 if (status)
2237 ice_debug(pi->hw, ICE_DBG_LINK,
2238 "get link status error, status = %d\n",
2239 status);
2240 }
2241
2242 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2243
2244 return status;
2245}
2246
fcea6f3d
AV		 2247/**
2248 * ice_aq_set_link_restart_an
2249 * @pi: pointer to the port information structure
2250 * @ena_link: if true: enable link, if false: disable link
2251 * @cd: pointer to command details structure or NULL
2252 *
2253 * Sets up the link and restarts the Auto-Negotiation over the link.
2254 */
2255enum ice_status
2256ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2257 struct ice_sq_cd *cd)
2258{
2259 struct ice_aqc_restart_an *cmd;
2260 struct ice_aq_desc desc;
2261
2262 cmd = &desc.params.restart_an;
2263
2264 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2265
2266 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2267 cmd->lport_num = pi->lport;
2268 if (ena_link)
2269 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2270 else
2271 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2272
2273 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2274}
2275
250c3b3e
BC		 2276/**
2277 * ice_aq_set_event_mask
2278 * @hw: pointer to the HW struct
2279 * @port_num: port number of the physical function
2280 * @mask: event mask to be set
2281 * @cd: pointer to command details structure or NULL
2282 *
2283 * Set event mask (0x0613)
2284 */
2285enum ice_status
2286ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2287 struct ice_sq_cd *cd)
2288{
2289 struct ice_aqc_set_event_mask *cmd;
2290 struct ice_aq_desc desc;
2291
2292 cmd = &desc.params.set_event_mask;
2293
2294 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2295
2296 cmd->lport_num = port_num;
2297
2298 cmd->event_mask = cpu_to_le16(mask);
2299 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2300}
2301
0e674aeb
AV		 2302/**
2303 * ice_aq_set_mac_loopback
2304 * @hw: pointer to the HW struct
2305 * @ena_lpbk: Enable or Disable loopback
2306 * @cd: pointer to command details structure or NULL
2307 *
2308 * Enable/disable loopback on a given port
2309 */
2310enum ice_status
2311ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2312{
2313 struct ice_aqc_set_mac_lb *cmd;
2314 struct ice_aq_desc desc;
2315
2316 cmd = &desc.params.set_mac_lb;
2317
2318 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2319 if (ena_lpbk)
2320 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2321
2322 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2323}
2324
8e151d50
AV		 2325/**
2326 * ice_aq_set_port_id_led
2327 * @pi: pointer to the port information
2328 * @is_orig_mode: is this LED set to original mode (by the net-list)
2329 * @cd: pointer to command details structure or NULL
2330 *
2331 * Set LED value for the given port (0x06e9)
2332 */
2333enum ice_status
2334ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2335 struct ice_sq_cd *cd)
2336{
2337 struct ice_aqc_set_port_id_led *cmd;
2338 struct ice_hw *hw = pi->hw;
2339 struct ice_aq_desc desc;
2340
2341 cmd = &desc.params.set_port_id_led;
2342
2343 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2344
2345 if (is_orig_mode)
2346 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2347 else
2348 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2349
2350 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2351}
2352
d76a60ba
AV		 2353/**
2354 * __ice_aq_get_set_rss_lut
2355 * @hw: pointer to the hardware structure
2356 * @vsi_id: VSI FW index
2357 * @lut_type: LUT table type
2358 * @lut: pointer to the LUT buffer provided by the caller
2359 * @lut_size: size of the LUT buffer
2360 * @glob_lut_idx: global LUT index
2361 * @set: set true to set the table, false to get the table
2362 *
2363 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2364 */
2365static enum ice_status
2366__ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2367 u16 lut_size, u8 glob_lut_idx, bool set)
2368{
2369 struct ice_aqc_get_set_rss_lut *cmd_resp;
2370 struct ice_aq_desc desc;
2371 enum ice_status status;
2372 u16 flags = 0;
2373
2374 cmd_resp = &desc.params.get_set_rss_lut;
2375
2376 if (set) {
2377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2378 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2379 } else {
2380 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2381 }
2382
2383 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
2384 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2385 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2386 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2387
2388 switch (lut_type) {
2389 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2390 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2391 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2392 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2393 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2394 break;
2395 default:
2396 status = ICE_ERR_PARAM;
2397 goto ice_aq_get_set_rss_lut_exit;
2398 }
2399
2400 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2401 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2402 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2403
2404 if (!set)
2405 goto ice_aq_get_set_rss_lut_send;
2406 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2407 if (!set)
2408 goto ice_aq_get_set_rss_lut_send;
2409 } else {
2410 goto ice_aq_get_set_rss_lut_send;
2411 }
2412
2413 /* LUT size is only valid for Global and PF table types */
4381147d
AV		 2414 switch (lut_size) {
2415 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2416 break;
2417 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
d76a60ba
AV		 2418 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2419 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2420 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
4381147d
AV		 2421 break;
2422 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2423 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2424 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2425 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2426 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2427 break;
2428 }
2429 /* fall-through */
2430 default:
d76a60ba
AV		 2431 status = ICE_ERR_PARAM;
2432 goto ice_aq_get_set_rss_lut_exit;
2433 }
2434
2435ice_aq_get_set_rss_lut_send:
2436 cmd_resp->flags = cpu_to_le16(flags);
2437 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2438
2439ice_aq_get_set_rss_lut_exit:
2440 return status;
2441}
2442
2443/**
2444 * ice_aq_get_rss_lut
2445 * @hw: pointer to the hardware structure
4fb33f31 2446 * @vsi_handle: software VSI handle
d76a60ba
AV		 2447 * @lut_type: LUT table type
2448 * @lut: pointer to the LUT buffer provided by the caller
2449 * @lut_size: size of the LUT buffer
2450 *
2451 * get the RSS lookup table, PF or VSI type
2452 */
2453enum ice_status
4fb33f31
AV		 2454ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2455 u8 *lut, u16 lut_size)
d76a60ba 2456{
4fb33f31
AV		 2457 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2458 return ICE_ERR_PARAM;
2459
2460 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2461 lut_type, lut, lut_size, 0, false);
d76a60ba
AV		 2462}
2463
2464/**
2465 * ice_aq_set_rss_lut
2466 * @hw: pointer to the hardware structure
4fb33f31 2467 * @vsi_handle: software VSI handle
d76a60ba
AV		 2468 * @lut_type: LUT table type
2469 * @lut: pointer to the LUT buffer provided by the caller
2470 * @lut_size: size of the LUT buffer
2471 *
2472 * set the RSS lookup table, PF or VSI type
2473 */
2474enum ice_status
4fb33f31
AV		 2475ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2476 u8 *lut, u16 lut_size)
d76a60ba 2477{
4fb33f31
AV		 2478 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2479 return ICE_ERR_PARAM;
2480
2481 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2482 lut_type, lut, lut_size, 0, true);
d76a60ba
AV		 2483}
2484
2485/**
2486 * __ice_aq_get_set_rss_key
f9867df6 2487 * @hw: pointer to the HW struct
d76a60ba
AV		 2488 * @vsi_id: VSI FW index
2489 * @key: pointer to key info struct
2490 * @set: set true to set the key, false to get the key
2491 *
2492 * get (0x0B04) or set (0x0B02) the RSS key per VSI
2493 */
2494static enum
2495ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
2496 struct ice_aqc_get_set_rss_keys *key,
2497 bool set)
2498{
2499 struct ice_aqc_get_set_rss_key *cmd_resp;
2500 u16 key_size = sizeof(*key);
2501 struct ice_aq_desc desc;
2502
2503 cmd_resp = &desc.params.get_set_rss_key;
2504
2505 if (set) {
2506 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
2507 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2508 } else {
2509 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
2510 }
2511
2512 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
2513 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
2514 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
2515 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
2516
2517 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
2518}
2519
2520/**
2521 * ice_aq_get_rss_key
f9867df6 2522 * @hw: pointer to the HW struct
4fb33f31 2523 * @vsi_handle: software VSI handle
d76a60ba
AV		 2524 * @key: pointer to key info struct
2525 *
2526 * get the RSS key per VSI
2527 */
2528enum ice_status
4fb33f31 2529ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
d76a60ba
AV		 2530 struct ice_aqc_get_set_rss_keys *key)
2531{
4fb33f31
AV		 2532 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
2533 return ICE_ERR_PARAM;
2534
2535 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2536 key, false);
d76a60ba
AV		 2537}
2538
2539/**
2540 * ice_aq_set_rss_key
f9867df6 2541 * @hw: pointer to the HW struct
4fb33f31 2542 * @vsi_handle: software VSI handle
d76a60ba
AV		 2543 * @keys: pointer to key info struct
2544 *
2545 * set the RSS key per VSI
2546 */
2547enum ice_status
4fb33f31 2548ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
d76a60ba
AV		 2549 struct ice_aqc_get_set_rss_keys *keys)
2550{
4fb33f31
AV		 2551 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
2552 return ICE_ERR_PARAM;
2553
2554 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2555 keys, true);
d76a60ba
AV		 2556}
2557
cdedef59
AV		 2558/**
2559 * ice_aq_add_lan_txq
2560 * @hw: pointer to the hardware structure
2561 * @num_qgrps: Number of added queue groups
2562 * @qg_list: list of queue groups to be added
2563 * @buf_size: size of buffer for indirect command
2564 * @cd: pointer to command details structure or NULL
2565 *
2566 * Add Tx LAN queue (0x0C30)
2567 *
2568 * NOTE:
2569 * Prior to calling add Tx LAN queue:
2570 * Initialize the following as part of the Tx queue context:
2571 * Completion queue ID if the queue uses Completion queue, Quanta profile,
2572 * Cache profile and Packet shaper profile.
2573 *
2574 * After add Tx LAN queue AQ command is completed:
2575 * Interrupts should be associated with specific queues,
2576 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
2577 * flow.
2578 */
2579static enum ice_status
2580ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2581 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
2582 struct ice_sq_cd *cd)
2583{
2584 u16 i, sum_header_size, sum_q_size = 0;
2585 struct ice_aqc_add_tx_qgrp *list;
2586 struct ice_aqc_add_txqs *cmd;
2587 struct ice_aq_desc desc;
2588
2589 cmd = &desc.params.add_txqs;
2590
2591 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
2592
2593 if (!qg_list)
2594 return ICE_ERR_PARAM;
2595
2596 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2597 return ICE_ERR_PARAM;
2598
2599 sum_header_size = num_qgrps *
2600 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
2601
2602 list = qg_list;
2603 for (i = 0; i < num_qgrps; i++) {
2604 struct ice_aqc_add_txqs_perq *q = list->txqs;
2605
2606 sum_q_size += list->num_txqs * sizeof(*q);
2607 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
2608 }
2609
2610 if (buf_size != (sum_header_size + sum_q_size))
2611 return ICE_ERR_PARAM;
2612
2613 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2614
2615 cmd->num_qgrps = num_qgrps;
2616
2617 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2618}
2619
2620/**
2621 * ice_aq_dis_lan_txq
2622 * @hw: pointer to the hardware structure
2623 * @num_qgrps: number of groups in the list
2624 * @qg_list: the list of groups to disable
2625 * @buf_size: the total size of the qg_list buffer in bytes
94c4441b 2626 * @rst_src: if called due to reset, specifies the reset source
ddf30f7f 2627 * @vmvf_num: the relative VM or VF number that is undergoing the reset
cdedef59
AV		 2628 * @cd: pointer to command details structure or NULL
2629 *
2630 * Disable LAN Tx queue (0x0C31)
2631 */
2632static enum ice_status
2633ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2634 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
ddf30f7f 2635 enum ice_disq_rst_src rst_src, u16 vmvf_num,
cdedef59
AV		 2636 struct ice_sq_cd *cd)
2637{
2638 struct ice_aqc_dis_txqs *cmd;
2639 struct ice_aq_desc desc;
6e9650d5 2640 enum ice_status status;
cdedef59
AV		 2641 u16 i, sz = 0;
2642
2643 cmd = &desc.params.dis_txqs;
2644 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
2645
ddf30f7f
AV		 2646 /* qg_list can be NULL only in VM/VF reset flow */
2647 if (!qg_list && !rst_src)
cdedef59
AV		 2648 return ICE_ERR_PARAM;
2649
2650 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2651 return ICE_ERR_PARAM;
ddf30f7f 2652
cdedef59
AV		 2653 cmd->num_entries = num_qgrps;
2654
ddf30f7f
AV		 2655 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
2656 ICE_AQC_Q_DIS_TIMEOUT_M);
2657
2658 switch (rst_src) {
2659 case ICE_VM_RESET:
2660 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
2661 cmd->vmvf_and_timeout |=
2662 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
2663 break;
2664 case ICE_VF_RESET:
2665 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
f9867df6 2666 /* In this case, FW expects vmvf_num to be absolute VF ID */
ddf30f7f
AV		 2667 cmd->vmvf_and_timeout |=
2668 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &
2669 ICE_AQC_Q_DIS_VMVF_NUM_M);
2670 break;
2671 case ICE_NO_RESET:
2672 default:
2673 break;
2674 }
2675
6e9650d5
VR		 2676 /* flush pipe on time out */
2677 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
ddf30f7f
AV		 2678 /* If no queue group info, we are in a reset flow. Issue the AQ */
2679 if (!qg_list)
2680 goto do_aq;
2681
2682 /* set RD bit to indicate that command buffer is provided by the driver
2683 * and it needs to be read by the firmware
2684 */
2685 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2686
cdedef59
AV		 2687 for (i = 0; i < num_qgrps; ++i) {
2688 /* Calculate the size taken up by the queue IDs in this group */
2689 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
2690
2691 /* Add the size of the group header */
2692 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
2693
2694 /* If the num of queues is even, add 2 bytes of padding */
2695 if ((qg_list[i].num_qs % 2) == 0)
2696 sz += 2;
2697 }
2698
2699 if (buf_size != sz)
2700 return ICE_ERR_PARAM;
2701
ddf30f7f 2702do_aq:
6e9650d5
VR		 2703 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2704 if (status) {
2705 if (!qg_list)
2706 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
2707 vmvf_num, hw->adminq.sq_last_status);
2708 else
2f2da36e 2709 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
6e9650d5
VR		 2710 le16_to_cpu(qg_list[0].q_id[0]),
2711 hw->adminq.sq_last_status);
2712 }
2713 return status;
cdedef59
AV		 2714}
2715
2716/* End of FW Admin Queue command wrappers */
2717
2718/**
2719 * ice_write_byte - write a byte to a packed context structure
2720 * @src_ctx: the context structure to read from
2721 * @dest_ctx: the context to be written to
2722 * @ce_info: a description of the struct to be filled
2723 */
c8b7abdd
BA		 2724static void
2725ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
cdedef59
AV		 2726{
2727 u8 src_byte, dest_byte, mask;
2728 u8 *from, *dest;
2729 u16 shift_width;
2730
2731 /* copy from the next struct field */
2732 from = src_ctx + ce_info->offset;
2733
2734 /* prepare the bits and mask */
2735 shift_width = ce_info->lsb % 8;
2736 mask = (u8)(BIT(ce_info->width) - 1);
2737
2738 src_byte = *from;
2739 src_byte &= mask;
2740
2741 /* shift to correct alignment */
2742 mask <<= shift_width;
2743 src_byte <<= shift_width;
2744
2745 /* get the current bits from the target bit string */
2746 dest = dest_ctx + (ce_info->lsb / 8);
2747
2748 memcpy(&dest_byte, dest, sizeof(dest_byte));
2749
2750 dest_byte &= ~mask; /* get the bits not changing */
2751 dest_byte |= src_byte; /* add in the new bits */
2752
2753 /* put it all back */
2754 memcpy(dest, &dest_byte, sizeof(dest_byte));
2755}
2756
2757/**
2758 * ice_write_word - write a word to a packed context structure
2759 * @src_ctx: the context structure to read from
2760 * @dest_ctx: the context to be written to
2761 * @ce_info: a description of the struct to be filled
2762 */
c8b7abdd
BA		 2763static void
2764ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
cdedef59
AV		 2765{
2766 u16 src_word, mask;
2767 __le16 dest_word;
2768 u8 *from, *dest;
2769 u16 shift_width;
2770
2771 /* copy from the next struct field */
2772 from = src_ctx + ce_info->offset;
2773
2774 /* prepare the bits and mask */
2775 shift_width = ce_info->lsb % 8;
2776 mask = BIT(ce_info->width) - 1;
2777
2778 /* don't swizzle the bits until after the mask because the mask bits
2779 * will be in a different bit position on big endian machines
2780 */
2781 src_word = *(u16 *)from;
2782 src_word &= mask;
2783
2784 /* shift to correct alignment */
2785 mask <<= shift_width;
2786 src_word <<= shift_width;
2787
2788 /* get the current bits from the target bit string */
2789 dest = dest_ctx + (ce_info->lsb / 8);
2790
2791 memcpy(&dest_word, dest, sizeof(dest_word));
2792
2793 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
2794 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
2795
2796 /* put it all back */
2797 memcpy(dest, &dest_word, sizeof(dest_word));
2798}
2799
2800/**
2801 * ice_write_dword - write a dword to a packed context structure
2802 * @src_ctx: the context structure to read from
2803 * @dest_ctx: the context to be written to
2804 * @ce_info: a description of the struct to be filled
2805 */
c8b7abdd
BA		 2806static void
2807ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
cdedef59
AV		 2808{
2809 u32 src_dword, mask;
2810 __le32 dest_dword;
2811 u8 *from, *dest;
2812 u16 shift_width;
2813
2814 /* copy from the next struct field */
2815 from = src_ctx + ce_info->offset;
2816
2817 /* prepare the bits and mask */
2818 shift_width = ce_info->lsb % 8;
2819
2820 /* if the field width is exactly 32 on an x86 machine, then the shift
2821 * operation will not work because the SHL instructions count is masked
2822 * to 5 bits so the shift will do nothing
2823 */
2824 if (ce_info->width < 32)
2825 mask = BIT(ce_info->width) - 1;
2826 else
2827 mask = (u32)~0;
2828
2829 /* don't swizzle the bits until after the mask because the mask bits
2830 * will be in a different bit position on big endian machines
2831 */
2832 src_dword = *(u32 *)from;
2833 src_dword &= mask;
2834
2835 /* shift to correct alignment */
2836 mask <<= shift_width;
2837 src_dword <<= shift_width;
2838
2839 /* get the current bits from the target bit string */
2840 dest = dest_ctx + (ce_info->lsb / 8);
2841
2842 memcpy(&dest_dword, dest, sizeof(dest_dword));
2843
2844 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
2845 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
2846
2847 /* put it all back */
2848 memcpy(dest, &dest_dword, sizeof(dest_dword));
2849}
2850
2851/**
2852 * ice_write_qword - write a qword to a packed context structure
2853 * @src_ctx: the context structure to read from
2854 * @dest_ctx: the context to be written to
2855 * @ce_info: a description of the struct to be filled
2856 */
c8b7abdd
BA		 2857static void
2858ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
cdedef59
AV		 2859{
2860 u64 src_qword, mask;
2861 __le64 dest_qword;
2862 u8 *from, *dest;
2863 u16 shift_width;
2864
2865 /* copy from the next struct field */
2866 from = src_ctx + ce_info->offset;
2867
2868 /* prepare the bits and mask */
2869 shift_width = ce_info->lsb % 8;
2870
2871 /* if the field width is exactly 64 on an x86 machine, then the shift
2872 * operation will not work because the SHL instructions count is masked
2873 * to 6 bits so the shift will do nothing
2874 */
2875 if (ce_info->width < 64)
2876 mask = BIT_ULL(ce_info->width) - 1;
2877 else
2878 mask = (u64)~0;
2879
2880 /* don't swizzle the bits until after the mask because the mask bits
2881 * will be in a different bit position on big endian machines
2882 */
2883 src_qword = *(u64 *)from;
2884 src_qword &= mask;
2885
2886 /* shift to correct alignment */
2887 mask <<= shift_width;
2888 src_qword <<= shift_width;
2889
2890 /* get the current bits from the target bit string */
2891 dest = dest_ctx + (ce_info->lsb / 8);
2892
2893 memcpy(&dest_qword, dest, sizeof(dest_qword));
2894
2895 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
2896 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
2897
2898 /* put it all back */
2899 memcpy(dest, &dest_qword, sizeof(dest_qword));
2900}
2901
2902/**
2903 * ice_set_ctx - set context bits in packed structure
2904 * @src_ctx: pointer to a generic non-packed context structure
2905 * @dest_ctx: pointer to memory for the packed structure
2906 * @ce_info: a description of the structure to be transformed
2907 */
2908enum ice_status
2909ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2910{
2911 int f;
2912
2913 for (f = 0; ce_info[f].width; f++) {
2914 /* We have to deal with each element of the FW response
2915 * using the correct size so that we are correct regardless
2916 * of the endianness of the machine.
2917 */
2918 switch (ce_info[f].size_of) {
2919 case sizeof(u8):
2920 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
2921 break;
2922 case sizeof(u16):
2923 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
2924 break;
2925 case sizeof(u32):
2926 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
2927 break;
2928 case sizeof(u64):
2929 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
2930 break;
2931 default:
2932 return ICE_ERR_INVAL_SIZE;
2933 }
2934 }
2935
2936 return 0;
2937}
2938
bb87ee0e
AV		 2939/**
2940 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
2941 * @hw: pointer to the HW struct
2942 * @vsi_handle: software VSI handle
2943 * @tc: TC number
2944 * @q_handle: software queue handle
2945 */
2946static struct ice_q_ctx *
2947ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
2948{
2949 struct ice_vsi_ctx *vsi;
2950 struct ice_q_ctx *q_ctx;
2951
2952 vsi = ice_get_vsi_ctx(hw, vsi_handle);
2953 if (!vsi)
2954 return NULL;
2955 if (q_handle >= vsi->num_lan_q_entries[tc])
2956 return NULL;
2957 if (!vsi->lan_q_ctx[tc])
2958 return NULL;
2959 q_ctx = vsi->lan_q_ctx[tc];
2960 return &q_ctx[q_handle];
2961}
2962
cdedef59
AV		 2963/**
2964 * ice_ena_vsi_txq
2965 * @pi: port information structure
4fb33f31 2966 * @vsi_handle: software VSI handle
f9867df6 2967 * @tc: TC number
bb87ee0e 2968 * @q_handle: software queue handle
cdedef59
AV		 2969 * @num_qgrps: Number of added queue groups
2970 * @buf: list of queue groups to be added
2971 * @buf_size: size of buffer for indirect command
2972 * @cd: pointer to command details structure or NULL
2973 *
f9867df6 2974 * This function adds one LAN queue
cdedef59
AV		 2975 */
2976enum ice_status
bb87ee0e
AV		 2977ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
2978 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
cdedef59
AV		 2979 struct ice_sq_cd *cd)
2980{
2981 struct ice_aqc_txsched_elem_data node = { 0 };
2982 struct ice_sched_node *parent;
bb87ee0e 2983 struct ice_q_ctx *q_ctx;
cdedef59
AV		 2984 enum ice_status status;
2985 struct ice_hw *hw;
2986
2987 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
2988 return ICE_ERR_CFG;
2989
2990 if (num_qgrps > 1 || buf->num_txqs > 1)
2991 return ICE_ERR_MAX_LIMIT;
2992
2993 hw = pi->hw;
2994
4fb33f31
AV		 2995 if (!ice_is_vsi_valid(hw, vsi_handle))
2996 return ICE_ERR_PARAM;
2997
cdedef59
AV		 2998 mutex_lock(&pi->sched_lock);
2999
bb87ee0e
AV		 3000 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3001 if (!q_ctx) {
3002 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3003 q_handle);
3004 status = ICE_ERR_PARAM;
3005 goto ena_txq_exit;
3006 }
3007
cdedef59 3008 /* find a parent node */
4fb33f31 3009 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
cdedef59
AV		 3010 ICE_SCHED_NODE_OWNER_LAN);
3011 if (!parent) {
3012 status = ICE_ERR_PARAM;
3013 goto ena_txq_exit;
3014 }
4fb33f31 3015
cdedef59
AV		 3016 buf->parent_teid = parent->info.node_teid;
3017 node.parent_teid = parent->info.node_teid;
3018 /* Mark that the values in the "generic" section as valid. The default
3019 * value in the "generic" section is zero. This means that :
3020 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3021 * - 0 priority among siblings, indicated by Bit 1-3.
3022 * - WFQ, indicated by Bit 4.
3023 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3024 * Bit 5-6.
3025 * - Bit 7 is reserved.
3026 * Without setting the generic section as valid in valid_sections, the
f9867df6 3027 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
cdedef59
AV		 3028 */
3029 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3030
f9867df6 3031 /* add the LAN queue */
cdedef59 3032 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
6e9650d5 3033 if (status) {
bb87ee0e 3034 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
6e9650d5
VR		 3035 le16_to_cpu(buf->txqs[0].txq_id),
3036 hw->adminq.sq_last_status);
cdedef59 3037 goto ena_txq_exit;
6e9650d5 3038 }
cdedef59
AV		 3039
3040 node.node_teid = buf->txqs[0].q_teid;
3041 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
bb87ee0e 3042 q_ctx->q_handle = q_handle;
cdedef59 3043
f9867df6 3044 /* add a leaf node into schduler tree queue layer */
cdedef59
AV		 3045 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3046
3047ena_txq_exit:
3048 mutex_unlock(&pi->sched_lock);
3049 return status;
3050}
3051
3052/**
3053 * ice_dis_vsi_txq
3054 * @pi: port information structure
bb87ee0e
AV		 3055 * @vsi_handle: software VSI handle
3056 * @tc: TC number
cdedef59 3057 * @num_queues: number of queues
bb87ee0e 3058 * @q_handles: pointer to software queue handle array
cdedef59
AV		 3059 * @q_ids: pointer to the q_id array
3060 * @q_teids: pointer to queue node teids
94c4441b 3061 * @rst_src: if called due to reset, specifies the reset source
ddf30f7f 3062 * @vmvf_num: the relative VM or VF number that is undergoing the reset
cdedef59
AV		 3063 * @cd: pointer to command details structure or NULL
3064 *
3065 * This function removes queues and their corresponding nodes in SW DB
3066 */
3067enum ice_status
bb87ee0e
AV		 3068ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3069 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3070 enum ice_disq_rst_src rst_src, u16 vmvf_num,
ddf30f7f 3071 struct ice_sq_cd *cd)
cdedef59
AV		 3072{
3073 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3074 struct ice_aqc_dis_txq_item qg_list;
bb87ee0e 3075 struct ice_q_ctx *q_ctx;
cdedef59
AV		 3076 u16 i;
3077
3078 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3079 return ICE_ERR_CFG;
3080
85796d6e
AA		 3081 if (!num_queues) {
3082 /* if queue is disabled already yet the disable queue command
3083 * has to be sent to complete the VF reset, then call
3084 * ice_aq_dis_lan_txq without any queue information
3085 */
3086 if (rst_src)
3087 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3088 vmvf_num, NULL);
3089 return ICE_ERR_CFG;
3090 }
ddf30f7f 3091
cdedef59
AV		 3092 mutex_lock(&pi->sched_lock);
3093
3094 for (i = 0; i < num_queues; i++) {
3095 struct ice_sched_node *node;
3096
3097 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3098 if (!node)
3099 continue;
bb87ee0e
AV		 3100 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3101 if (!q_ctx) {
3102 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3103 q_handles[i]);
3104 continue;
3105 }
3106 if (q_ctx->q_handle != q_handles[i]) {
3107 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3108 q_ctx->q_handle, q_handles[i]);
3109 continue;
3110 }
cdedef59
AV		 3111 qg_list.parent_teid = node->info.parent_teid;
3112 qg_list.num_qs = 1;
3113 qg_list.q_id[0] = cpu_to_le16(q_ids[i]);
3114 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
ddf30f7f
AV		 3115 sizeof(qg_list), rst_src, vmvf_num,
3116 cd);
cdedef59
AV		 3117
3118 if (status)
3119 break;
3120 ice_free_sched_node(pi, node);
bb87ee0e 3121 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
cdedef59
AV		 3122 }
3123 mutex_unlock(&pi->sched_lock);
3124 return status;
3125}
5513b920
AV		 3126
3127/**
94c4441b 3128 * ice_cfg_vsi_qs - configure the new/existing VSI queues
5513b920 3129 * @pi: port information structure
4fb33f31 3130 * @vsi_handle: software VSI handle
5513b920
AV		 3131 * @tc_bitmap: TC bitmap
3132 * @maxqs: max queues array per TC
f9867df6 3133 * @owner: LAN or RDMA
5513b920
AV		 3134 *
3135 * This function adds/updates the VSI queues per TC.
3136 */
3137static enum ice_status
4fb33f31 3138ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
5513b920
AV		 3139 u16 *maxqs, u8 owner)
3140{
3141 enum ice_status status = 0;
3142 u8 i;
3143
3144 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3145 return ICE_ERR_CFG;
3146
4fb33f31
AV		 3147 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3148 return ICE_ERR_PARAM;
3149
5513b920
AV		 3150 mutex_lock(&pi->sched_lock);
3151
2bdc97be 3152 ice_for_each_traffic_class(i) {
5513b920
AV		 3153 /* configuration is possible only if TC node is present */
3154 if (!ice_sched_get_tc_node(pi, i))
3155 continue;
3156
4fb33f31 3157 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
5513b920
AV		 3158 ice_is_tc_ena(tc_bitmap, i));
3159 if (status)
3160 break;
3161 }
3162
3163 mutex_unlock(&pi->sched_lock);
3164 return status;
3165}
3166
3167/**
f9867df6 3168 * ice_cfg_vsi_lan - configure VSI LAN queues
5513b920 3169 * @pi: port information structure
4fb33f31 3170 * @vsi_handle: software VSI handle
5513b920 3171 * @tc_bitmap: TC bitmap
f9867df6 3172 * @max_lanqs: max LAN queues array per TC
5513b920 3173 *
f9867df6 3174 * This function adds/updates the VSI LAN queues per TC.
5513b920
AV		 3175 */
3176enum ice_status
4fb33f31 3177ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
5513b920
AV		 3178 u16 *max_lanqs)
3179{
4fb33f31 3180 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
5513b920
AV		 3181 ICE_SCHED_NODE_OWNER_LAN);
3182}
45d3d428 3183
334cb062
AV		 3184/**
3185 * ice_replay_pre_init - replay pre initialization
f9867df6 3186 * @hw: pointer to the HW struct
334cb062
AV		 3187 *
3188 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3189 */
3190static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3191{
3192 struct ice_switch_info *sw = hw->switch_info;
3193 u8 i;
3194
3195 /* Delete old entries from replay filter list head if there is any */
3196 ice_rm_all_sw_replay_rule_info(hw);
3197 /* In start of replay, move entries into replay_rules list, it
3198 * will allow adding rules entries back to filt_rules list,
3199 * which is operational list.
3200 */
3201 for (i = 0; i < ICE_SW_LKUP_LAST; i++)
3202 list_replace_init(&sw->recp_list[i].filt_rules,
3203 &sw->recp_list[i].filt_replay_rules);
3204
3205 return 0;
3206}
3207
3208/**
3209 * ice_replay_vsi - replay VSI configuration
f9867df6 3210 * @hw: pointer to the HW struct
334cb062
AV		 3211 * @vsi_handle: driver VSI handle
3212 *
3213 * Restore all VSI configuration after reset. It is required to call this
3214 * function with main VSI first.
3215 */
3216enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3217{
3218 enum ice_status status;
3219
3220 if (!ice_is_vsi_valid(hw, vsi_handle))
3221 return ICE_ERR_PARAM;
3222
3223 /* Replay pre-initialization if there is any */
3224 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3225 status = ice_replay_pre_init(hw);
3226 if (status)
3227 return status;
3228 }
3229
3230 /* Replay per VSI all filters */
3231 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3232 return status;
3233}
3234
3235/**
3236 * ice_replay_post - post replay configuration cleanup
f9867df6 3237 * @hw: pointer to the HW struct
334cb062
AV		 3238 *
3239 * Post replay cleanup.
3240 */
3241void ice_replay_post(struct ice_hw *hw)
3242{
3243 /* Delete old entries from replay filter list head */
3244 ice_rm_all_sw_replay_rule_info(hw);
3245}
3246
45d3d428
AV		 3247/**
3248 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
3249 * @hw: ptr to the hardware info
36517fd3 3250 * @reg: offset of 64 bit HW register to read from
45d3d428
AV		 3251 * @prev_stat_loaded: bool to specify if previous stats are loaded
3252 * @prev_stat: ptr to previous loaded stat value
3253 * @cur_stat: ptr to current stat value
3254 */
c8b7abdd 3255void
36517fd3
JK		 3256ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3257 u64 *prev_stat, u64 *cur_stat)
45d3d428 3258{
36517fd3 3259 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
45d3d428
AV		 3260
3261 /* device stats are not reset at PFR, they likely will not be zeroed
36517fd3
JK		 3262 * when the driver starts. Thus, save the value from the first read
3263 * without adding to the statistic value so that we report stats which
3264 * count up from zero.
45d3d428 3265 */
36517fd3 3266 if (!prev_stat_loaded) {
45d3d428 3267 *prev_stat = new_data;
36517fd3
JK		 3268 return;
3269 }
3270
3271 /* Calculate the difference between the new and old values, and then
3272 * add it to the software stat value.
3273 */
45d3d428 3274 if (new_data >= *prev_stat)
36517fd3 3275 *cur_stat += new_data - *prev_stat;
45d3d428
AV		 3276 else
3277 /* to manage the potential roll-over */
36517fd3
JK		 3278 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
3279
3280 /* Update the previously stored value to prepare for next read */
3281 *prev_stat = new_data;
45d3d428
AV		 3282}
3283
3284/**
3285 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
3286 * @hw: ptr to the hardware info
36517fd3 3287 * @reg: offset of HW register to read from
45d3d428
AV		 3288 * @prev_stat_loaded: bool to specify if previous stats are loaded
3289 * @prev_stat: ptr to previous loaded stat value
3290 * @cur_stat: ptr to current stat value
3291 */
c8b7abdd
BA		 3292void
3293ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3294 u64 *prev_stat, u64 *cur_stat)
45d3d428
AV		 3295{
3296 u32 new_data;
3297
3298 new_data = rd32(hw, reg);
3299
3300 /* device stats are not reset at PFR, they likely will not be zeroed
36517fd3
JK		 3301 * when the driver starts. Thus, save the value from the first read
3302 * without adding to the statistic value so that we report stats which
3303 * count up from zero.
45d3d428 3304 */
36517fd3 3305 if (!prev_stat_loaded) {
45d3d428 3306 *prev_stat = new_data;
36517fd3
JK		 3307 return;
3308 }
3309
3310 /* Calculate the difference between the new and old values, and then
3311 * add it to the software stat value.
3312 */
45d3d428 3313 if (new_data >= *prev_stat)
36517fd3 3314 *cur_stat += new_data - *prev_stat;
45d3d428
AV		 3315 else
3316 /* to manage the potential roll-over */
36517fd3
JK		 3317 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
3318
3319 /* Update the previously stored value to prepare for next read */
3320 *prev_stat = new_data;
45d3d428 3321}
7b9ffc76
AV		 3322
3323/**
3324 * ice_sched_query_elem - query element information from HW
3325 * @hw: pointer to the HW struct
3326 * @node_teid: node TEID to be queried
3327 * @buf: buffer to element information
3328 *
3329 * This function queries HW element information
3330 */
3331enum ice_status
3332ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
3333 struct ice_aqc_get_elem *buf)
3334{
3335 u16 buf_size, num_elem_ret = 0;
3336 enum ice_status status;
3337
3338 buf_size = sizeof(*buf);
3339 memset(buf, 0, buf_size);
3340 buf->generic[0].node_teid = cpu_to_le32(node_teid);
3341 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
3342 NULL);
3343 if (status || num_elem_ret != 1)
3344 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
3345 return status;
3346}
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