[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / igb / e1000_hw.h

/* Intel(R) Gigabit Ethernet Linux driver
 * Copyright(c) 2007-2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 */

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/netdevice.h>

#include "e1000_regs.h"
#include "e1000_defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82576			0x10C9
#define E1000_DEV_ID_82576_FIBER		0x10E6
#define E1000_DEV_ID_82576_SERDES		0x10E7
#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
#define E1000_DEV_ID_82576_NS			0x150A
#define E1000_DEV_ID_82576_NS_SERDES		0x1518
#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
#define E1000_DEV_ID_82575EB_COPPER		0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
#define E1000_DEV_ID_82580_COPPER		0x150E
#define E1000_DEV_ID_82580_FIBER		0x150F
#define E1000_DEV_ID_82580_SERDES		0x1510
#define E1000_DEV_ID_82580_SGMII		0x1511
#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
#define E1000_DEV_ID_DH89XXCC_SFP		0x0440
#define E1000_DEV_ID_I350_COPPER		0x1521
#define E1000_DEV_ID_I350_FIBER			0x1522
#define E1000_DEV_ID_I350_SERDES		0x1523
#define E1000_DEV_ID_I350_SGMII			0x1524
#define E1000_DEV_ID_I210_COPPER		0x1533
#define E1000_DEV_ID_I210_FIBER			0x1536
#define E1000_DEV_ID_I210_SERDES		0x1537
#define E1000_DEV_ID_I210_SGMII			0x1538
#define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
#define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
#define E1000_DEV_ID_I211_COPPER		0x1539
#define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
#define E1000_DEV_ID_I354_SGMII			0x1F41
#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45

#define E1000_REVISION_2 2
#define E1000_REVISION_4 4

#define E1000_FUNC_0     0
#define E1000_FUNC_1     1
#define E1000_FUNC_2     2
#define E1000_FUNC_3     3

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9

enum e1000_mac_type {
	e1000_undefined = 0,
	e1000_82575,
	e1000_82576,
	e1000_82580,
	e1000_i350,
	e1000_i354,
	e1000_i210,
	e1000_i211,
	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
};

enum e1000_media_type {
	e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,
	e1000_media_type_fiber = 2,
	e1000_media_type_internal_serdes = 3,
	e1000_num_media_types
};

enum e1000_nvm_type {
	e1000_nvm_unknown = 0,
	e1000_nvm_none,
	e1000_nvm_eeprom_spi,
	e1000_nvm_flash_hw,
	e1000_nvm_invm,
	e1000_nvm_flash_sw
};

enum e1000_nvm_override {
	e1000_nvm_override_none = 0,
	e1000_nvm_override_spi_small,
	e1000_nvm_override_spi_large,
};

enum e1000_phy_type {
	e1000_phy_unknown = 0,
	e1000_phy_none,
	e1000_phy_m88,
	e1000_phy_igp,
	e1000_phy_igp_2,
	e1000_phy_gg82563,
	e1000_phy_igp_3,
	e1000_phy_ife,
	e1000_phy_82580,
	e1000_phy_i210,
};

enum e1000_bus_type {
	e1000_bus_type_unknown = 0,
	e1000_bus_type_pci,
	e1000_bus_type_pcix,
	e1000_bus_type_pci_express,
	e1000_bus_type_reserved
};

enum e1000_bus_speed {
	e1000_bus_speed_unknown = 0,
	e1000_bus_speed_33,
	e1000_bus_speed_66,
	e1000_bus_speed_100,
	e1000_bus_speed_120,
	e1000_bus_speed_133,
	e1000_bus_speed_2500,
	e1000_bus_speed_5000,
	e1000_bus_speed_reserved
};

enum e1000_bus_width {
	e1000_bus_width_unknown = 0,
	e1000_bus_width_pcie_x1,
	e1000_bus_width_pcie_x2,
	e1000_bus_width_pcie_x4 = 4,
	e1000_bus_width_pcie_x8 = 8,
	e1000_bus_width_32,
	e1000_bus_width_64,
	e1000_bus_width_reserved
};

enum e1000_1000t_rx_status {
	e1000_1000t_rx_status_not_ok = 0,
	e1000_1000t_rx_status_ok,
	e1000_1000t_rx_status_undefined = 0xFF
};

enum e1000_rev_polarity {
	e1000_rev_polarity_normal = 0,
	e1000_rev_polarity_reversed,
	e1000_rev_polarity_undefined = 0xFF
};

enum e1000_fc_mode {
	e1000_fc_none = 0,
	e1000_fc_rx_pause,
	e1000_fc_tx_pause,
	e1000_fc_full,
	e1000_fc_default = 0xFF
};

/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
	u64 crcerrs;
	u64 algnerrc;
	u64 symerrs;
	u64 rxerrc;
	u64 mpc;
	u64 scc;
	u64 ecol;
	u64 mcc;
	u64 latecol;
	u64 colc;
	u64 dc;
	u64 tncrs;
	u64 sec;
	u64 cexterr;
	u64 rlec;
	u64 xonrxc;
	u64 xontxc;
	u64 xoffrxc;
	u64 xofftxc;
	u64 fcruc;
	u64 prc64;
	u64 prc127;
	u64 prc255;
	u64 prc511;
	u64 prc1023;
	u64 prc1522;
	u64 gprc;
	u64 bprc;
	u64 mprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 rnbc;
	u64 ruc;
	u64 rfc;
	u64 roc;
	u64 rjc;
	u64 mgprc;
	u64 mgpdc;
	u64 mgptc;
	u64 tor;
	u64 tot;
	u64 tpr;
	u64 tpt;
	u64 ptc64;
	u64 ptc127;
	u64 ptc255;
	u64 ptc511;
	u64 ptc1023;
	u64 ptc1522;
	u64 mptc;
	u64 bptc;
	u64 tsctc;
	u64 tsctfc;
	u64 iac;
	u64 icrxptc;
	u64 icrxatc;
	u64 ictxptc;
	u64 ictxatc;
	u64 ictxqec;
	u64 ictxqmtc;
	u64 icrxdmtc;
	u64 icrxoc;
	u64 cbtmpc;
	u64 htdpmc;
	u64 cbrdpc;
	u64 cbrmpc;
	u64 rpthc;
	u64 hgptc;
	u64 htcbdpc;
	u64 hgorc;
	u64 hgotc;
	u64 lenerrs;
	u64 scvpc;
	u64 hrmpc;
	u64 doosync;
	u64 o2bgptc;
	u64 o2bspc;
	u64 b2ospc;
	u64 b2ogprc;
};

struct e1000_phy_stats {
	u32 idle_errors;
	u32 receive_errors;
};

struct e1000_host_mng_dhcp_cookie {
	u32 signature;
	u8  status;
	u8  reserved0;
	u16 vlan_id;
	u32 reserved1;
	u16 reserved2;
	u8  reserved3;
	u8  checksum;
};

/* Host Interface "Rev 1" */
struct e1000_host_command_header {
	u8 command_id;
	u8 command_length;
	u8 command_options;
	u8 checksum;
};

#define E1000_HI_MAX_DATA_LENGTH     252
struct e1000_host_command_info {
	struct e1000_host_command_header command_header;
	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
};

/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
	u8  command_id;
	u8  checksum;
	u16 reserved1;
	u16 reserved2;
	u16 command_length;
};

#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
struct e1000_host_mng_command_info {
	struct e1000_host_mng_command_header command_header;
	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
};

#include "e1000_mac.h"
#include "e1000_phy.h"
#include "e1000_nvm.h"
#include "e1000_mbx.h"

struct e1000_mac_operations {
	s32 (*check_for_link)(struct e1000_hw *);
	s32 (*reset_hw)(struct e1000_hw *);
	s32 (*init_hw)(struct e1000_hw *);
	bool (*check_mng_mode)(struct e1000_hw *);
	s32 (*setup_physical_interface)(struct e1000_hw *);
	void (*rar_set)(struct e1000_hw *, u8 *, u32);
	s32 (*read_mac_addr)(struct e1000_hw *);
	s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
	s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
	void (*release_swfw_sync)(struct e1000_hw *, u16);
#ifdef CONFIG_IGB_HWMON
	s32 (*get_thermal_sensor_data)(struct e1000_hw *);
	s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
#endif

};

struct e1000_phy_operations {
	s32 (*acquire)(struct e1000_hw *);
	s32 (*check_polarity)(struct e1000_hw *);
	s32 (*check_reset_block)(struct e1000_hw *);
	s32 (*force_speed_duplex)(struct e1000_hw *);
	s32 (*get_cfg_done)(struct e1000_hw *hw);
	s32 (*get_cable_length)(struct e1000_hw *);
	s32 (*get_phy_info)(struct e1000_hw *);
	s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
	void (*release)(struct e1000_hw *);
	s32 (*reset)(struct e1000_hw *);
	s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
	s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
	s32 (*write_reg)(struct e1000_hw *, u32, u16);
	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
};

struct e1000_nvm_operations {
	s32 (*acquire)(struct e1000_hw *);
	s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
	void (*release)(struct e1000_hw *);
	s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
	s32 (*update)(struct e1000_hw *);
	s32 (*validate)(struct e1000_hw *);
	s32 (*valid_led_default)(struct e1000_hw *, u16 *);
};

#define E1000_MAX_SENSORS		3

struct e1000_thermal_diode_data {
	u8 location;
	u8 temp;
	u8 caution_thresh;
	u8 max_op_thresh;
};

struct e1000_thermal_sensor_data {
	struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
};

struct e1000_info {
	s32 (*get_invariants)(struct e1000_hw *);
	struct e1000_mac_operations *mac_ops;
	struct e1000_phy_operations *phy_ops;
	struct e1000_nvm_operations *nvm_ops;
};

extern const struct e1000_info e1000_82575_info;

struct e1000_mac_info {
	struct e1000_mac_operations ops;

	u8 addr[6];
	u8 perm_addr[6];

	enum e1000_mac_type type;

	u32 ledctl_default;
	u32 ledctl_mode1;
	u32 ledctl_mode2;
	u32 mc_filter_type;
	u32 txcw;

	u16 mta_reg_count;
	u16 uta_reg_count;

	/* Maximum size of the MTA register table in all supported adapters */
	#define MAX_MTA_REG 128
	u32 mta_shadow[MAX_MTA_REG];
	u16 rar_entry_count;

	u8  forced_speed_duplex;

	bool adaptive_ifs;
	bool arc_subsystem_valid;
	bool asf_firmware_present;
	bool autoneg;
	bool autoneg_failed;
	bool disable_hw_init_bits;
	bool get_link_status;
	bool ifs_params_forced;
	bool in_ifs_mode;
	bool report_tx_early;
	bool serdes_has_link;
	bool tx_pkt_filtering;
	struct e1000_thermal_sensor_data thermal_sensor_data;
};

struct e1000_phy_info {
	struct e1000_phy_operations ops;

	enum e1000_phy_type type;

	enum e1000_1000t_rx_status local_rx;
	enum e1000_1000t_rx_status remote_rx;
	enum e1000_ms_type ms_type;
	enum e1000_ms_type original_ms_type;
	enum e1000_rev_polarity cable_polarity;
	enum e1000_smart_speed smart_speed;

	u32 addr;
	u32 id;
	u32 reset_delay_us; /* in usec */
	u32 revision;

	enum e1000_media_type media_type;

	u16 autoneg_advertised;
	u16 autoneg_mask;
	u16 cable_length;
	u16 max_cable_length;
	u16 min_cable_length;

	u8 mdix;

	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool reset_disable;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};

struct e1000_nvm_info {
	struct e1000_nvm_operations ops;
	enum e1000_nvm_type type;
	enum e1000_nvm_override override;

	u32 flash_bank_size;
	u32 flash_base_addr;

	u16 word_size;
	u16 delay_usec;
	u16 address_bits;
	u16 opcode_bits;
	u16 page_size;
};

struct e1000_bus_info {
	enum e1000_bus_type type;
	enum e1000_bus_speed speed;
	enum e1000_bus_width width;

	u32 snoop;

	u16 func;
	u16 pci_cmd_word;
};

struct e1000_fc_info {
	u32 high_water;     /* Flow control high-water mark */
	u32 low_water;      /* Flow control low-water mark */
	u16 pause_time;     /* Flow control pause timer */
	bool send_xon;      /* Flow control send XON */
	bool strict_ieee;   /* Strict IEEE mode */
	enum e1000_fc_mode current_mode; /* Type of flow control */
	enum e1000_fc_mode requested_mode;
};

struct e1000_mbx_operations {
	s32 (*init_params)(struct e1000_hw *hw);
	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*check_for_msg)(struct e1000_hw *, u16);
	s32 (*check_for_ack)(struct e1000_hw *, u16);
	s32 (*check_for_rst)(struct e1000_hw *, u16);
};

struct e1000_mbx_stats {
	u32 msgs_tx;
	u32 msgs_rx;

	u32 acks;
	u32 reqs;
	u32 rsts;
};

struct e1000_mbx_info {
	struct e1000_mbx_operations ops;
	struct e1000_mbx_stats stats;
	u32 timeout;
	u32 usec_delay;
	u16 size;
};

struct e1000_dev_spec_82575 {
	bool sgmii_active;
	bool global_device_reset;
	bool eee_disable;
	bool clear_semaphore_once;
	struct e1000_sfp_flags eth_flags;
	bool module_plugged;
	u8 media_port;
	bool media_changed;
	bool mas_capable;
};

struct e1000_hw {
	void *back;

	u8 __iomem *hw_addr;
	u8 __iomem *flash_address;
	unsigned long io_base;

	struct e1000_mac_info  mac;
	struct e1000_fc_info   fc;
	struct e1000_phy_info  phy;
	struct e1000_nvm_info  nvm;
	struct e1000_bus_info  bus;
	struct e1000_mbx_info mbx;
	struct e1000_host_mng_dhcp_cookie mng_cookie;

	union {
		struct e1000_dev_spec_82575	_82575;
	} dev_spec;

	u16 device_id;
	u16 subsystem_vendor_id;
	u16 subsystem_device_id;
	u16 vendor_id;

	u8  revision_id;
};

struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
#define hw_dbg(format, arg...) \
	netdev_dbg(igb_get_hw_dev(hw), format, ##arg)

/* These functions must be implemented by drivers */
s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
#endif /* _E1000_HW_H_ */
Commit	Line	Data
e52c0f96 CW	1	/* Intel(R) Gigabit Ethernet Linux driver
	2	* Copyright(c) 2007-2014 Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	*
	7	* This program is distributed in the hope it will be useful, but WITHOUT
	8	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	9	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	10	* more details.
	11	*
	12	* You should have received a copy of the GNU General Public License along with
	13	* this program; if not, see <http://www.gnu.org/licenses/>.
	14	*
	15	* The full GNU General Public License is included in this distribution in
	16	* the file called "COPYING".
	17	*
	18	* Contact Information:
	19	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	20	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	21	*/
9d5c8243 AK	22
	23	#ifndef _E1000_HW_H_
	24	#define _E1000_HW_H_
	25
	26	#include <linux/types.h>
	27	#include <linux/delay.h>
	28	#include <linux/io.h>
c041076a	29	#include <linux/netdevice.h>
9d5c8243	30
9d5c8243 AK	31	#include "e1000_regs.h"
	32	#include "e1000_defines.h"
	33
	34	struct e1000_hw;
	35
b980ac18 JK	36	#define E1000_DEV_ID_82576 0x10C9
	37	#define E1000_DEV_ID_82576_FIBER 0x10E6
	38	#define E1000_DEV_ID_82576_SERDES 0x10E7
	39	#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
	40	#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
	41	#define E1000_DEV_ID_82576_NS 0x150A
	42	#define E1000_DEV_ID_82576_NS_SERDES 0x1518
	43	#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
	44	#define E1000_DEV_ID_82575EB_COPPER 0x10A7
	45	#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
	46	#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
	47	#define E1000_DEV_ID_82580_COPPER 0x150E
	48	#define E1000_DEV_ID_82580_FIBER 0x150F
	49	#define E1000_DEV_ID_82580_SERDES 0x1510
	50	#define E1000_DEV_ID_82580_SGMII 0x1511
	51	#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
	52	#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
	53	#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
	54	#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
	55	#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
	56	#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
	57	#define E1000_DEV_ID_I350_COPPER 0x1521
	58	#define E1000_DEV_ID_I350_FIBER 0x1522
	59	#define E1000_DEV_ID_I350_SERDES 0x1523
	60	#define E1000_DEV_ID_I350_SGMII 0x1524
f96a8a0b	61	#define E1000_DEV_ID_I210_COPPER 0x1533
f96a8a0b CW	62	#define E1000_DEV_ID_I210_FIBER 0x1536
	63	#define E1000_DEV_ID_I210_SERDES 0x1537
	64	#define E1000_DEV_ID_I210_SGMII 0x1538
53b87ce3 CW	65	#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
53b87ce3 CW	66	#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
f96a8a0b	67	#define E1000_DEV_ID_I211_COPPER 0x1539
ceb5f13b CW	68	#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
	69	#define E1000_DEV_ID_I354_SGMII 0x1F41
	70	#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
9d5c8243 AK	71
	72	#define E1000_REVISION_2 2
	73	#define E1000_REVISION_4 4
	74
70d92f86	75	#define E1000_FUNC_0 0
9d5c8243	76	#define E1000_FUNC_1 1
bb2ac47b AD	77	#define E1000_FUNC_2 2
bb2ac47b AD	78	#define E1000_FUNC_3 3
9d5c8243	79
bb2ac47b	80	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
22896639	81	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
bb2ac47b AD	82	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
bb2ac47b AD	83	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
22896639	84
9d5c8243 AK	85	enum e1000_mac_type {
	86	e1000_undefined = 0,
	87	e1000_82575,
2d064c06	88	e1000_82576,
bb2ac47b	89	e1000_82580,
d2ba2ed8	90	e1000_i350,
ceb5f13b	91	e1000_i354,
f96a8a0b CW	92	e1000_i210,
f96a8a0b CW	93	e1000_i211,
9d5c8243 AK	94	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	95	};
	96
	97	enum e1000_media_type {
	98	e1000_media_type_unknown = 0,
	99	e1000_media_type_copper = 1,
f502ef7d AA	100	e1000_media_type_fiber = 2,
f502ef7d AA	101	e1000_media_type_internal_serdes = 3,
9d5c8243 AK	102	e1000_num_media_types
	103	};
	104
	105	enum e1000_nvm_type {
	106	e1000_nvm_unknown = 0,
	107	e1000_nvm_none,
	108	e1000_nvm_eeprom_spi,
9d5c8243	109	e1000_nvm_flash_hw,
5a823d8c	110	e1000_nvm_invm,
9d5c8243 AK	111	e1000_nvm_flash_sw
	112	};
	113
	114	enum e1000_nvm_override {
	115	e1000_nvm_override_none = 0,
	116	e1000_nvm_override_spi_small,
	117	e1000_nvm_override_spi_large,
9d5c8243 AK	118	};
	119
	120	enum e1000_phy_type {
	121	e1000_phy_unknown = 0,
	122	e1000_phy_none,
	123	e1000_phy_m88,
	124	e1000_phy_igp,
	125	e1000_phy_igp_2,
	126	e1000_phy_gg82563,
	127	e1000_phy_igp_3,
	128	e1000_phy_ife,
2909c3f7	129	e1000_phy_82580,
f96a8a0b	130	e1000_phy_i210,
9d5c8243 AK	131	};
	132
	133	enum e1000_bus_type {
	134	e1000_bus_type_unknown = 0,
	135	e1000_bus_type_pci,
	136	e1000_bus_type_pcix,
	137	e1000_bus_type_pci_express,
	138	e1000_bus_type_reserved
	139	};
	140
	141	enum e1000_bus_speed {
	142	e1000_bus_speed_unknown = 0,
	143	e1000_bus_speed_33,
	144	e1000_bus_speed_66,
	145	e1000_bus_speed_100,
	146	e1000_bus_speed_120,
	147	e1000_bus_speed_133,
	148	e1000_bus_speed_2500,
	149	e1000_bus_speed_5000,
	150	e1000_bus_speed_reserved
	151	};
	152
	153	enum e1000_bus_width {
	154	e1000_bus_width_unknown = 0,
	155	e1000_bus_width_pcie_x1,
	156	e1000_bus_width_pcie_x2,
	157	e1000_bus_width_pcie_x4 = 4,
	158	e1000_bus_width_pcie_x8 = 8,
	159	e1000_bus_width_32,
	160	e1000_bus_width_64,
	161	e1000_bus_width_reserved
	162	};
	163
	164	enum e1000_1000t_rx_status {
	165	e1000_1000t_rx_status_not_ok = 0,
	166	e1000_1000t_rx_status_ok,
	167	e1000_1000t_rx_status_undefined = 0xFF
	168	};
	169
	170	enum e1000_rev_polarity {
	171	e1000_rev_polarity_normal = 0,
	172	e1000_rev_polarity_reversed,
	173	e1000_rev_polarity_undefined = 0xFF
	174	};
	175
0cce119a	176	enum e1000_fc_mode {
9d5c8243 AK	177	e1000_fc_none = 0,
	178	e1000_fc_rx_pause,
	179	e1000_fc_tx_pause,
	180	e1000_fc_full,
	181	e1000_fc_default = 0xFF
	182	};
	183
9d5c8243 AK	184	/* Statistics counters collected by the MAC */
	185	struct e1000_hw_stats {
	186	u64 crcerrs;
	187	u64 algnerrc;
	188	u64 symerrs;
	189	u64 rxerrc;
	190	u64 mpc;
	191	u64 scc;
	192	u64 ecol;
	193	u64 mcc;
	194	u64 latecol;
	195	u64 colc;
	196	u64 dc;
	197	u64 tncrs;
	198	u64 sec;
	199	u64 cexterr;
	200	u64 rlec;
	201	u64 xonrxc;
	202	u64 xontxc;
	203	u64 xoffrxc;
	204	u64 xofftxc;
	205	u64 fcruc;
	206	u64 prc64;
	207	u64 prc127;
	208	u64 prc255;
	209	u64 prc511;
	210	u64 prc1023;
	211	u64 prc1522;
	212	u64 gprc;
	213	u64 bprc;
	214	u64 mprc;
	215	u64 gptc;
	216	u64 gorc;
	217	u64 gotc;
	218	u64 rnbc;
	219	u64 ruc;
	220	u64 rfc;
	221	u64 roc;
	222	u64 rjc;
	223	u64 mgprc;
	224	u64 mgpdc;
	225	u64 mgptc;
	226	u64 tor;
	227	u64 tot;
	228	u64 tpr;
	229	u64 tpt;
	230	u64 ptc64;
	231	u64 ptc127;
	232	u64 ptc255;
	233	u64 ptc511;
	234	u64 ptc1023;
	235	u64 ptc1522;
	236	u64 mptc;
	237	u64 bptc;
	238	u64 tsctc;
	239	u64 tsctfc;
	240	u64 iac;
	241	u64 icrxptc;
	242	u64 icrxatc;
	243	u64 ictxptc;
	244	u64 ictxatc;
	245	u64 ictxqec;
	246	u64 ictxqmtc;
	247	u64 icrxdmtc;
248	u64 icrxoc;
249	u64 cbtmpc;
250	u64 htdpmc;
251	u64 cbrdpc;
252	u64 cbrmpc;
253	u64 rpthc;
254	u64 hgptc;
255	u64 htcbdpc;
256	u64 hgorc;
257	u64 hgotc;
258	u64 lenerrs;
259	u64 scvpc;
260	u64 hrmpc;
dda0e083	261	u64 doosync;
0a915b95 CW	262	u64 o2bgptc;
	263	u64 o2bspc;
	264	u64 b2ospc;
	265	u64 b2ogprc;
9d5c8243 AK	266	};
	267
	268	struct e1000_phy_stats {
	269	u32 idle_errors;
	270	u32 receive_errors;
	271	};
	272
	273	struct e1000_host_mng_dhcp_cookie {
	274	u32 signature;
	275	u8 status;
	276	u8 reserved0;
	277	u16 vlan_id;
	278	u32 reserved1;
	279	u16 reserved2;
	280	u8 reserved3;
	281	u8 checksum;
	282	};
	283
	284	/* Host Interface "Rev 1" */
	285	struct e1000_host_command_header {
	286	u8 command_id;
	287	u8 command_length;
	288	u8 command_options;
	289	u8 checksum;
	290	};
	291
	292	#define E1000_HI_MAX_DATA_LENGTH 252
	293	struct e1000_host_command_info {
	294	struct e1000_host_command_header command_header;
	295	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
	296	};
	297
	298	/* Host Interface "Rev 2" */
	299	struct e1000_host_mng_command_header {
	300	u8 command_id;
	301	u8 checksum;
	302	u16 reserved1;
	303	u16 reserved2;
	304	u16 command_length;
	305	};
	306
	307	#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
	308	struct e1000_host_mng_command_info {
	309	struct e1000_host_mng_command_header command_header;
	310	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
	311	};
	312
	313	#include "e1000_mac.h"
	314	#include "e1000_phy.h"
	315	#include "e1000_nvm.h"
4ae196df	316	#include "e1000_mbx.h"
9d5c8243 AK	317
9d5c8243 AK	318	struct e1000_mac_operations {
9005df38 CW	319	s32 (check_for_link)(struct e1000_hw );
	320	s32 (reset_hw)(struct e1000_hw );
	321	s32 (init_hw)(struct e1000_hw );
2d064c06	322	bool (check_mng_mode)(struct e1000_hw );
9005df38	323	s32 (setup_physical_interface)(struct e1000_hw );
9d5c8243	324	void (rar_set)(struct e1000_hw , u8 *, u32);
9005df38 CW	325	s32 (read_mac_addr)(struct e1000_hw );
	326	s32 (get_speed_and_duplex)(struct e1000_hw , u16 , u16 );
	327	s32 (acquire_swfw_sync)(struct e1000_hw , u16);
f96a8a0b	328	void (release_swfw_sync)(struct e1000_hw , u16);
e428893b CW	329	#ifdef CONFIG_IGB_HWMON
	330	s32 (get_thermal_sensor_data)(struct e1000_hw );
	331	s32 (init_thermal_sensor_thresh)(struct e1000_hw );
	332	#endif
f96a8a0b	333
9d5c8243 AK	334	};
	335
	336	struct e1000_phy_operations {
9005df38 CW	337	s32 (acquire)(struct e1000_hw );
	338	s32 (check_polarity)(struct e1000_hw );
	339	s32 (check_reset_block)(struct e1000_hw );
	340	s32 (force_speed_duplex)(struct e1000_hw );
	341	s32 (get_cfg_done)(struct e1000_hw hw);
	342	s32 (get_cable_length)(struct e1000_hw );
	343	s32 (get_phy_info)(struct e1000_hw );
	344	s32 (read_reg)(struct e1000_hw , u32, u16 *);
a8d2a0c2	345	void (release)(struct e1000_hw );
9005df38 CW	346	s32 (reset)(struct e1000_hw );
	347	s32 (set_d0_lplu_state)(struct e1000_hw , bool);
	348	s32 (set_d3_lplu_state)(struct e1000_hw , bool);
	349	s32 (write_reg)(struct e1000_hw , u32, u16);
441fc6fd CW	350	s32 (read_i2c_byte)(struct e1000_hw , u8, u8, u8 *);
441fc6fd CW	351	s32 (write_i2c_byte)(struct e1000_hw , u8, u8, u8);
9d5c8243 AK	352	};
	353
	354	struct e1000_nvm_operations {
9005df38 CW	355	s32 (acquire)(struct e1000_hw );
9005df38 CW	356	s32 (read)(struct e1000_hw , u16, u16, u16 *);
312c75ae	357	void (release)(struct e1000_hw );
9005df38 CW	358	s32 (write)(struct e1000_hw , u16, u16, u16 *);
	359	s32 (update)(struct e1000_hw );
	360	s32 (validate)(struct e1000_hw );
	361	s32 (valid_led_default)(struct e1000_hw , u16 *);
9d5c8243 AK	362	};
9d5c8243 AK	363
aca5dae8 CW	364	#define E1000_MAX_SENSORS 3
	365
	366	struct e1000_thermal_diode_data {
	367	u8 location;
	368	u8 temp;
	369	u8 caution_thresh;
	370	u8 max_op_thresh;
	371	};
	372
	373	struct e1000_thermal_sensor_data {
	374	struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
	375	};
	376
9d5c8243 AK	377	struct e1000_info {
	378	s32 (get_invariants)(struct e1000_hw );
	379	struct e1000_mac_operations *mac_ops;
	380	struct e1000_phy_operations *phy_ops;
	381	struct e1000_nvm_operations *nvm_ops;
	382	};
	383
	384	extern const struct e1000_info e1000_82575_info;
	385
	386	struct e1000_mac_info {
	387	struct e1000_mac_operations ops;
	388
	389	u8 addr[6];
	390	u8 perm_addr[6];
	391
	392	enum e1000_mac_type type;
	393
9d5c8243 AK	394	u32 ledctl_default;
	395	u32 ledctl_mode1;
	396	u32 ledctl_mode2;
	397	u32 mc_filter_type;
9d5c8243 AK	398	u32 txcw;
9d5c8243 AK	399
9d5c8243	400	u16 mta_reg_count;
68d480c4	401	u16 uta_reg_count;
28fc06f5 AD	402
	403	/* Maximum size of the MTA register table in all supported adapters */
	404	#define MAX_MTA_REG 128
	405	u32 mta_shadow[MAX_MTA_REG];
9d5c8243 AK	406	u16 rar_entry_count;
	407
	408	u8 forced_speed_duplex;
	409
	410	bool adaptive_ifs;
	411	bool arc_subsystem_valid;
	412	bool asf_firmware_present;
	413	bool autoneg;
	414	bool autoneg_failed;
9d5c8243 AK	415	bool disable_hw_init_bits;
	416	bool get_link_status;
	417	bool ifs_params_forced;
	418	bool in_ifs_mode;
	419	bool report_tx_early;
	420	bool serdes_has_link;
	421	bool tx_pkt_filtering;
aca5dae8	422	struct e1000_thermal_sensor_data thermal_sensor_data;
9d5c8243 AK	423	};
	424
	425	struct e1000_phy_info {
	426	struct e1000_phy_operations ops;
	427
	428	enum e1000_phy_type type;
	429
	430	enum e1000_1000t_rx_status local_rx;
	431	enum e1000_1000t_rx_status remote_rx;
	432	enum e1000_ms_type ms_type;
	433	enum e1000_ms_type original_ms_type;
	434	enum e1000_rev_polarity cable_polarity;
	435	enum e1000_smart_speed smart_speed;
	436
	437	u32 addr;
	438	u32 id;
	439	u32 reset_delay_us; /* in usec */
	440	u32 revision;
	441
	442	enum e1000_media_type media_type;
	443
	444	u16 autoneg_advertised;
	445	u16 autoneg_mask;
	446	u16 cable_length;
	447	u16 max_cable_length;
	448	u16 min_cable_length;
	449
	450	u8 mdix;
	451
	452	bool disable_polarity_correction;
	453	bool is_mdix;
	454	bool polarity_correction;
	455	bool reset_disable;
	456	bool speed_downgraded;
	457	bool autoneg_wait_to_complete;
	458	};
	459
	460	struct e1000_nvm_info {
	461	struct e1000_nvm_operations ops;
9d5c8243 AK	462	enum e1000_nvm_type type;
	463	enum e1000_nvm_override override;
	464
	465	u32 flash_bank_size;
	466	u32 flash_base_addr;
	467
	468	u16 word_size;
	469	u16 delay_usec;
	470	u16 address_bits;
	471	u16 opcode_bits;
	472	u16 page_size;
	473	};
	474
	475	struct e1000_bus_info {
	476	enum e1000_bus_type type;
	477	enum e1000_bus_speed speed;
	478	enum e1000_bus_width width;
	479
	480	u32 snoop;
	481
	482	u16 func;
	483	u16 pci_cmd_word;
	484	};
	485
	486	struct e1000_fc_info {
	487	u32 high_water; /* Flow control high-water mark */
	488	u32 low_water; /* Flow control low-water mark */
	489	u16 pause_time; /* Flow control pause timer */
	490	bool send_xon; /* Flow control send XON */
	491	bool strict_ieee; /* Strict IEEE mode */
0cce119a AD	492	enum e1000_fc_mode current_mode; /* Type of flow control */
0cce119a AD	493	enum e1000_fc_mode requested_mode;
9d5c8243 AK	494	};
9d5c8243 AK	495
4ae196df AD	496	struct e1000_mbx_operations {
	497	s32 (init_params)(struct e1000_hw hw);
	498	s32 (read)(struct e1000_hw , u32 *, u16, u16);
	499	s32 (write)(struct e1000_hw , u32 *, u16, u16);
	500	s32 (read_posted)(struct e1000_hw , u32 *, u16, u16);
	501	s32 (write_posted)(struct e1000_hw , u32 *, u16, u16);
	502	s32 (check_for_msg)(struct e1000_hw , u16);
	503	s32 (check_for_ack)(struct e1000_hw , u16);
	504	s32 (check_for_rst)(struct e1000_hw , u16);
	505	};
	506
	507	struct e1000_mbx_stats {
	508	u32 msgs_tx;
	509	u32 msgs_rx;
	510
	511	u32 acks;
	512	u32 reqs;
	513	u32 rsts;
	514	};
	515
	516	struct e1000_mbx_info {
	517	struct e1000_mbx_operations ops;
	518	struct e1000_mbx_stats stats;
	519	u32 timeout;
	520	u32 usec_delay;
	521	u16 size;
	522	};
	523
c1889bfe AD	524	struct e1000_dev_spec_82575 {
c1889bfe AD	525	bool sgmii_active;
bb2ac47b	526	bool global_device_reset;
09b068d4	527	bool eee_disable;
d44e7a9a	528	bool clear_semaphore_once;
641ac5c0 AA	529	struct e1000_sfp_flags eth_flags;
641ac5c0 AA	530	bool module_plugged;
2bdfc4e2 CW	531	u8 media_port;
2bdfc4e2 CW	532	bool media_changed;
56cec249	533	bool mas_capable;
c1889bfe AD	534	};
c1889bfe AD	535
9d5c8243 AK	536	struct e1000_hw {
9d5c8243 AK	537	void *back;
9d5c8243 AK	538
	539	u8 __iomem *hw_addr;
	540	u8 __iomem *flash_address;
	541	unsigned long io_base;
	542
	543	struct e1000_mac_info mac;
	544	struct e1000_fc_info fc;
	545	struct e1000_phy_info phy;
	546	struct e1000_nvm_info nvm;
	547	struct e1000_bus_info bus;
4ae196df	548	struct e1000_mbx_info mbx;
9d5c8243 AK	549	struct e1000_host_mng_dhcp_cookie mng_cookie;
9d5c8243 AK	550
c1889bfe AD	551	union {
	552	struct e1000_dev_spec_82575 _82575;
	553	} dev_spec;
9d5c8243 AK	554
	555	u16 device_id;
	556	u16 subsystem_vendor_id;
	557	u16 subsystem_device_id;
	558	u16 vendor_id;
	559
	560	u8 revision_id;
	561	};
	562
5ccc921a	563	struct net_device igb_get_hw_dev(struct e1000_hw hw);
652fff32	564	#define hw_dbg(format, arg...) \
c041076a AD	565	netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
c041076a AD	566
009bc06e	567	/* These functions must be implemented by drivers */
5ccc921a JP	568	s32 igb_read_pcie_cap_reg(struct e1000_hw hw, u32 reg, u16 value);
5ccc921a JP	569	s32 igb_write_pcie_cap_reg(struct e1000_hw hw, u32 reg, u16 value);
94826487 TF	570
	571	void igb_read_pci_cfg(struct e1000_hw hw, u32 reg, u16 value);
	572	void igb_write_pci_cfg(struct e1000_hw hw, u32 reg, u16 value);
c041076a	573	#endif /* _E1000_HW_H_ */