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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243
AK		 23
24/* ethtool support for igb */
25
26#include <linux/vmalloc.h>
27#include <linux/netdevice.h>
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
31#include <linux/if_ether.h>
32#include <linux/ethtool.h>
d43c36dc 33#include <linux/sched.h>
5a0e3ad6 34#include <linux/slab.h>
749ab2cd 35#include <linux/pm_runtime.h>
1a1c225b 36#include <linux/highmem.h>
87371b9d 37#include <linux/mdio.h>
9d5c8243
AK		 38
39#include "igb.h"
40
41struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45};
46
128e45eb
AD		 47#define IGB_STAT(_name, _stat) { \
48 .stat_string = _name, \
49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50 .stat_offset = offsetof(struct igb_adapter, _stat) \
51}
9d5c8243 52static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 53 IGB_STAT("rx_packets", stats.gprc),
54 IGB_STAT("tx_packets", stats.gptc),
55 IGB_STAT("rx_bytes", stats.gorc),
56 IGB_STAT("tx_bytes", stats.gotc),
57 IGB_STAT("rx_broadcast", stats.bprc),
58 IGB_STAT("tx_broadcast", stats.bptc),
59 IGB_STAT("rx_multicast", stats.mprc),
60 IGB_STAT("tx_multicast", stats.mptc),
61 IGB_STAT("multicast", stats.mprc),
62 IGB_STAT("collisions", stats.colc),
63 IGB_STAT("rx_crc_errors", stats.crcerrs),
64 IGB_STAT("rx_no_buffer_count", stats.rnbc),
65 IGB_STAT("rx_missed_errors", stats.mpc),
66 IGB_STAT("tx_aborted_errors", stats.ecol),
67 IGB_STAT("tx_carrier_errors", stats.tncrs),
68 IGB_STAT("tx_window_errors", stats.latecol),
69 IGB_STAT("tx_abort_late_coll", stats.latecol),
70 IGB_STAT("tx_deferred_ok", stats.dc),
71 IGB_STAT("tx_single_coll_ok", stats.scc),
72 IGB_STAT("tx_multi_coll_ok", stats.mcc),
73 IGB_STAT("tx_timeout_count", tx_timeout_count),
74 IGB_STAT("rx_long_length_errors", stats.roc),
75 IGB_STAT("rx_short_length_errors", stats.ruc),
76 IGB_STAT("rx_align_errors", stats.algnerrc),
77 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81 IGB_STAT("tx_flow_control_xon", stats.xontxc),
82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83 IGB_STAT("rx_long_byte_count", stats.gorc),
84 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85 IGB_STAT("tx_smbus", stats.mgptc),
86 IGB_STAT("rx_smbus", stats.mgprc),
87 IGB_STAT("dropped_smbus", stats.mgpdc),
0a915b95
CW		 88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
428f1f71 92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
fc580751 93 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
128e45eb
AD		 94};
95
96#define IGB_NETDEV_STAT(_net_stat) { \
97 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 100}
101static const struct igb_stats igb_gstrings_net_stats[] = {
102 IGB_NETDEV_STAT(rx_errors),
103 IGB_NETDEV_STAT(tx_errors),
104 IGB_NETDEV_STAT(tx_dropped),
105 IGB_NETDEV_STAT(rx_length_errors),
106 IGB_NETDEV_STAT(rx_over_errors),
107 IGB_NETDEV_STAT(rx_frame_errors),
108 IGB_NETDEV_STAT(rx_fifo_errors),
109 IGB_NETDEV_STAT(tx_fifo_errors),
110 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 111};
112
128e45eb
AD		 113#define IGB_GLOBAL_STATS_LEN \
114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
115#define IGB_NETDEV_STATS_LEN \
116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
117#define IGB_RX_QUEUE_STATS_LEN \
118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 119
120#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
121
9d5c8243 122#define IGB_QUEUE_STATS_LEN \
317f66bd 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 124 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 126 IGB_TX_QUEUE_STATS_LEN))
127#define IGB_STATS_LEN \
128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
129
9d5c8243
AK		 130static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
131 "Register test (offline)", "Eeprom test (offline)",
132 "Interrupt test (offline)", "Loopback test (offline)",
133 "Link test (on/offline)"
134};
317f66bd 135#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 136
137static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
138{
139 struct igb_adapter *adapter = netdev_priv(netdev);
140 struct e1000_hw *hw = &adapter->hw;
641ac5c0
AA		 141 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
142 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
317f66bd 143 u32 status;
d4f3cd49 144 u32 speed;
9d5c8243 145
01237139 146 status = rd32(E1000_STATUS);
9d5c8243
AK		 147 if (hw->phy.media_type == e1000_media_type_copper) {
148
149 ecmd->supported = (SUPPORTED_10baseT_Half |
150 SUPPORTED_10baseT_Full |
151 SUPPORTED_100baseT_Half |
152 SUPPORTED_100baseT_Full |
153 SUPPORTED_1000baseT_Full|
154 SUPPORTED_Autoneg |
42f3c43b
AA		 155 SUPPORTED_TP |
156 SUPPORTED_Pause);
157 ecmd->advertising = ADVERTISED_TP;
9d5c8243
AK		 158
159 if (hw->mac.autoneg == 1) {
160 ecmd->advertising |= ADVERTISED_Autoneg;
161 /* the e1000 autoneg seems to match ethtool nicely */
162 ecmd->advertising |= hw->phy.autoneg_advertised;
163 }
164
165 ecmd->port = PORT_TP;
166 ecmd->phy_address = hw->phy.addr;
f502ef7d 167 ecmd->transceiver = XCVR_INTERNAL;
9d5c8243 168 } else {
641ac5c0 169 ecmd->supported = (SUPPORTED_FIBRE |
01237139 170 SUPPORTED_1000baseKX_Full |
ceb5f13b
CW		 171 SUPPORTED_Autoneg |
172 SUPPORTED_Pause);
01237139
CW		 173 ecmd->advertising = (ADVERTISED_FIBRE |
174 ADVERTISED_1000baseKX_Full);
175 if (hw->mac.type == e1000_i354) {
176 if ((hw->device_id ==
177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
178 !(status & E1000_STATUS_2P5_SKU_OVER)) {
179 ecmd->supported |= SUPPORTED_2500baseX_Full;
180 ecmd->supported &=
181 ~SUPPORTED_1000baseKX_Full;
182 ecmd->advertising |= ADVERTISED_2500baseX_Full;
183 ecmd->advertising &=
184 ~ADVERTISED_1000baseKX_Full;
185 }
641ac5c0
AA		 186 }
187 if (eth_flags->e100_base_fx) {
188 ecmd->supported |= SUPPORTED_100baseT_Full;
189 ecmd->advertising |= ADVERTISED_100baseT_Full;
ceb5f13b 190 }
f502ef7d
AA		 191 if (hw->mac.autoneg == 1)
192 ecmd->advertising |= ADVERTISED_Autoneg;
9d5c8243
AK		 193
194 ecmd->port = PORT_FIBRE;
f502ef7d 195 ecmd->transceiver = XCVR_EXTERNAL;
9d5c8243 196 }
373e6978
AA		 197 if (hw->mac.autoneg != 1)
198 ecmd->advertising &= ~(ADVERTISED_Pause |
199 ADVERTISED_Asym_Pause);
200
01237139
CW		 201 switch (hw->fc.requested_mode) {
202 case e1000_fc_full:
373e6978 203 ecmd->advertising |= ADVERTISED_Pause;
01237139
CW		 204 break;
205 case e1000_fc_rx_pause:
373e6978
AA		 206 ecmd->advertising |= (ADVERTISED_Pause |
207 ADVERTISED_Asym_Pause);
01237139
CW		 208 break;
209 case e1000_fc_tx_pause:
373e6978 210 ecmd->advertising |= ADVERTISED_Asym_Pause;
01237139
CW		 211 break;
212 default:
373e6978
AA		 213 ecmd->advertising &= ~(ADVERTISED_Pause |
214 ADVERTISED_Asym_Pause);
01237139 215 }
317f66bd 216 if (status & E1000_STATUS_LU) {
01237139
CW		 217 if ((status & E1000_STATUS_2P5_SKU) &&
218 !(status & E1000_STATUS_2P5_SKU_OVER)) {
d4f3cd49 219 speed = SPEED_2500;
41fcfbea 220 } else if (status & E1000_STATUS_SPEED_1000) {
d4f3cd49 221 speed = SPEED_1000;
41fcfbea 222 } else if (status & E1000_STATUS_SPEED_100) {
d4f3cd49 223 speed = SPEED_100;
41fcfbea 224 } else {
d4f3cd49 225 speed = SPEED_10;
41fcfbea 226 }
317f66bd
AD		 227 if ((status & E1000_STATUS_FD) ||
228 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 229 ecmd->duplex = DUPLEX_FULL;
230 else
231 ecmd->duplex = DUPLEX_HALF;
232 } else {
d4f3cd49 233 speed = SPEED_UNKNOWN;
537fae01 234 ecmd->duplex = DUPLEX_UNKNOWN;
9d5c8243 235 }
d4f3cd49 236 ethtool_cmd_speed_set(ecmd, speed);
f502ef7d
AA		 237 if ((hw->phy.media_type == e1000_media_type_fiber) ||
238 hw->mac.autoneg)
239 ecmd->autoneg = AUTONEG_ENABLE;
240 else
241 ecmd->autoneg = AUTONEG_DISABLE;
8376dad0
JB		 242
243 /* MDI-X => 2; MDI =>1; Invalid =>0 */
244 if (hw->phy.media_type == e1000_media_type_copper)
245 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
246 ETH_TP_MDI;
247 else
248 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
249
250 if (hw->phy.mdix == AUTO_ALL_MODES)
251 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
252 else
253 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
254
9d5c8243
AK		 255 return 0;
256}
257
258static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
259{
260 struct igb_adapter *adapter = netdev_priv(netdev);
261 struct e1000_hw *hw = &adapter->hw;
262
263 /* When SoL/IDER sessions are active, autoneg/speed/duplex
b980ac18
JK		 264 * cannot be changed
265 */
9d5c8243 266 if (igb_check_reset_block(hw)) {
d836200a
JJ		 267 dev_err(&adapter->pdev->dev,
268 "Cannot change link characteristics when SoL/IDER is active.\n");
9d5c8243
AK		 269 return -EINVAL;
270 }
271
b980ac18 272 /* MDI setting is only allowed when autoneg enabled because
8376dad0
JB		 273 * some hardware doesn't allow MDI setting when speed or
274 * duplex is forced.
275 */
276 if (ecmd->eth_tp_mdix_ctrl) {
277 if (hw->phy.media_type != e1000_media_type_copper)
278 return -EOPNOTSUPP;
279
280 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
281 (ecmd->autoneg != AUTONEG_ENABLE)) {
282 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
283 return -EINVAL;
284 }
285 }
286
9d5c8243 287 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 288 usleep_range(1000, 2000);
9d5c8243
AK		 289
290 if (ecmd->autoneg == AUTONEG_ENABLE) {
291 hw->mac.autoneg = 1;
f502ef7d
AA		 292 if (hw->phy.media_type == e1000_media_type_fiber) {
293 hw->phy.autoneg_advertised = ecmd->advertising |
294 ADVERTISED_FIBRE |
295 ADVERTISED_Autoneg;
ceb5f13b
CW		 296 switch (adapter->link_speed) {
297 case SPEED_2500:
298 hw->phy.autoneg_advertised =
299 ADVERTISED_2500baseX_Full;
300 break;
301 case SPEED_1000:
f502ef7d
AA		 302 hw->phy.autoneg_advertised =
303 ADVERTISED_1000baseT_Full;
ceb5f13b
CW		 304 break;
305 case SPEED_100:
f502ef7d
AA		 306 hw->phy.autoneg_advertised =
307 ADVERTISED_100baseT_Full;
ceb5f13b
CW		 308 break;
309 default:
310 break;
311 }
f502ef7d
AA		 312 } else {
313 hw->phy.autoneg_advertised = ecmd->advertising |
314 ADVERTISED_TP |
315 ADVERTISED_Autoneg;
316 }
9d5c8243 317 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 318 if (adapter->fc_autoneg)
319 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 320 } else {
25db0338 321 u32 speed = ethtool_cmd_speed(ecmd);
8376dad0 322 /* calling this overrides forced MDI setting */
14ad2513 323 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
9d5c8243
AK		 324 clear_bit(__IGB_RESETTING, &adapter->state);
325 return -EINVAL;
326 }
dcc3ae9a 327 }
9d5c8243 328
8376dad0
JB		 329 /* MDI-X => 2; MDI => 1; Auto => 3 */
330 if (ecmd->eth_tp_mdix_ctrl) {
b980ac18 331 /* fix up the value for auto (3 => 0) as zero is mapped
8376dad0
JB		 332 * internally to auto
333 */
334 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
335 hw->phy.mdix = AUTO_ALL_MODES;
336 else
337 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
338 }
339
9d5c8243 340 /* reset the link */
9d5c8243
AK		 341 if (netif_running(adapter->netdev)) {
342 igb_down(adapter);
343 igb_up(adapter);
344 } else
345 igb_reset(adapter);
346
347 clear_bit(__IGB_RESETTING, &adapter->state);
348 return 0;
349}
350
3145535a
NN		 351static u32 igb_get_link(struct net_device *netdev)
352{
353 struct igb_adapter *adapter = netdev_priv(netdev);
354 struct e1000_mac_info *mac = &adapter->hw.mac;
355
b980ac18 356 /* If the link is not reported up to netdev, interrupts are disabled,
3145535a
NN		 357 * and so the physical link state may have changed since we last
358 * looked. Set get_link_status to make sure that the true link
359 * state is interrogated, rather than pulling a cached and possibly
360 * stale link state from the driver.
361 */
362 if (!netif_carrier_ok(netdev))
363 mac->get_link_status = 1;
364
365 return igb_has_link(adapter);
366}
367
9d5c8243
AK		 368static void igb_get_pauseparam(struct net_device *netdev,
369 struct ethtool_pauseparam *pause)
370{
371 struct igb_adapter *adapter = netdev_priv(netdev);
372 struct e1000_hw *hw = &adapter->hw;
373
374 pause->autoneg =
375 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
376
0cce119a 377 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 378 pause->rx_pause = 1;
0cce119a 379 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 380 pause->tx_pause = 1;
0cce119a 381 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 382 pause->rx_pause = 1;
383 pause->tx_pause = 1;
384 }
385}
386
387static int igb_set_pauseparam(struct net_device *netdev,
388 struct ethtool_pauseparam *pause)
389{
390 struct igb_adapter *adapter = netdev_priv(netdev);
391 struct e1000_hw *hw = &adapter->hw;
392 int retval = 0;
393
373e6978
AA		 394 /* 100basefx does not support setting link flow control */
395 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
396 return -EINVAL;
397
9d5c8243
AK		 398 adapter->fc_autoneg = pause->autoneg;
399
400 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 401 usleep_range(1000, 2000);
9d5c8243 402
9d5c8243 403 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 404 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 405 if (netif_running(adapter->netdev)) {
406 igb_down(adapter);
407 igb_up(adapter);
317f66bd 408 } else {
9d5c8243 409 igb_reset(adapter);
317f66bd 410 }
0cce119a
AD		 411 } else {
412 if (pause->rx_pause && pause->tx_pause)
413 hw->fc.requested_mode = e1000_fc_full;
414 else if (pause->rx_pause && !pause->tx_pause)
415 hw->fc.requested_mode = e1000_fc_rx_pause;
416 else if (!pause->rx_pause && pause->tx_pause)
417 hw->fc.requested_mode = e1000_fc_tx_pause;
418 else if (!pause->rx_pause && !pause->tx_pause)
419 hw->fc.requested_mode = e1000_fc_none;
420
421 hw->fc.current_mode = hw->fc.requested_mode;
422
dcc3ae9a
AD		 423 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
424 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 425 }
9d5c8243
AK		 426
427 clear_bit(__IGB_RESETTING, &adapter->state);
428 return retval;
429}
430
9d5c8243
AK		 431static u32 igb_get_msglevel(struct net_device *netdev)
432{
433 struct igb_adapter *adapter = netdev_priv(netdev);
434 return adapter->msg_enable;
435}
436
437static void igb_set_msglevel(struct net_device *netdev, u32 data)
438{
439 struct igb_adapter *adapter = netdev_priv(netdev);
440 adapter->msg_enable = data;
441}
442
443static int igb_get_regs_len(struct net_device *netdev)
444{
7e3b4ffb 445#define IGB_REGS_LEN 739
9d5c8243
AK		 446 return IGB_REGS_LEN * sizeof(u32);
447}
448
449static void igb_get_regs(struct net_device *netdev,
450 struct ethtool_regs *regs, void *p)
451{
452 struct igb_adapter *adapter = netdev_priv(netdev);
453 struct e1000_hw *hw = &adapter->hw;
454 u32 *regs_buff = p;
455 u8 i;
456
457 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
458
459 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
460
461 /* General Registers */
462 regs_buff[0] = rd32(E1000_CTRL);
463 regs_buff[1] = rd32(E1000_STATUS);
464 regs_buff[2] = rd32(E1000_CTRL_EXT);
465 regs_buff[3] = rd32(E1000_MDIC);
466 regs_buff[4] = rd32(E1000_SCTL);
467 regs_buff[5] = rd32(E1000_CONNSW);
468 regs_buff[6] = rd32(E1000_VET);
469 regs_buff[7] = rd32(E1000_LEDCTL);
470 regs_buff[8] = rd32(E1000_PBA);
471 regs_buff[9] = rd32(E1000_PBS);
472 regs_buff[10] = rd32(E1000_FRTIMER);
473 regs_buff[11] = rd32(E1000_TCPTIMER);
474
475 /* NVM Register */
476 regs_buff[12] = rd32(E1000_EECD);
477
478 /* Interrupt */
fe59de38 479 /* Reading EICS for EICR because they read the
b980ac18
JK		 480 * same but EICS does not clear on read
481 */
fe59de38 482 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 483 regs_buff[14] = rd32(E1000_EICS);
484 regs_buff[15] = rd32(E1000_EIMS);
485 regs_buff[16] = rd32(E1000_EIMC);
486 regs_buff[17] = rd32(E1000_EIAC);
487 regs_buff[18] = rd32(E1000_EIAM);
fe59de38 488 /* Reading ICS for ICR because they read the
b980ac18
JK		 489 * same but ICS does not clear on read
490 */
fe59de38 491 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 492 regs_buff[20] = rd32(E1000_ICS);
493 regs_buff[21] = rd32(E1000_IMS);
494 regs_buff[22] = rd32(E1000_IMC);
495 regs_buff[23] = rd32(E1000_IAC);
496 regs_buff[24] = rd32(E1000_IAM);
497 regs_buff[25] = rd32(E1000_IMIRVP);
498
499 /* Flow Control */
500 regs_buff[26] = rd32(E1000_FCAL);
501 regs_buff[27] = rd32(E1000_FCAH);
502 regs_buff[28] = rd32(E1000_FCTTV);
503 regs_buff[29] = rd32(E1000_FCRTL);
504 regs_buff[30] = rd32(E1000_FCRTH);
505 regs_buff[31] = rd32(E1000_FCRTV);
506
507 /* Receive */
508 regs_buff[32] = rd32(E1000_RCTL);
509 regs_buff[33] = rd32(E1000_RXCSUM);
510 regs_buff[34] = rd32(E1000_RLPML);
511 regs_buff[35] = rd32(E1000_RFCTL);
512 regs_buff[36] = rd32(E1000_MRQC);
e1739522 513 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 514
515 /* Transmit */
516 regs_buff[38] = rd32(E1000_TCTL);
517 regs_buff[39] = rd32(E1000_TCTL_EXT);
518 regs_buff[40] = rd32(E1000_TIPG);
519 regs_buff[41] = rd32(E1000_DTXCTL);
520
521 /* Wake Up */
522 regs_buff[42] = rd32(E1000_WUC);
523 regs_buff[43] = rd32(E1000_WUFC);
524 regs_buff[44] = rd32(E1000_WUS);
525 regs_buff[45] = rd32(E1000_IPAV);
526 regs_buff[46] = rd32(E1000_WUPL);
527
528 /* MAC */
529 regs_buff[47] = rd32(E1000_PCS_CFG0);
530 regs_buff[48] = rd32(E1000_PCS_LCTL);
531 regs_buff[49] = rd32(E1000_PCS_LSTAT);
532 regs_buff[50] = rd32(E1000_PCS_ANADV);
533 regs_buff[51] = rd32(E1000_PCS_LPAB);
534 regs_buff[52] = rd32(E1000_PCS_NPTX);
535 regs_buff[53] = rd32(E1000_PCS_LPABNP);
536
537 /* Statistics */
538 regs_buff[54] = adapter->stats.crcerrs;
539 regs_buff[55] = adapter->stats.algnerrc;
540 regs_buff[56] = adapter->stats.symerrs;
541 regs_buff[57] = adapter->stats.rxerrc;
542 regs_buff[58] = adapter->stats.mpc;
543 regs_buff[59] = adapter->stats.scc;
544 regs_buff[60] = adapter->stats.ecol;
545 regs_buff[61] = adapter->stats.mcc;
546 regs_buff[62] = adapter->stats.latecol;
547 regs_buff[63] = adapter->stats.colc;
548 regs_buff[64] = adapter->stats.dc;
549 regs_buff[65] = adapter->stats.tncrs;
550 regs_buff[66] = adapter->stats.sec;
551 regs_buff[67] = adapter->stats.htdpmc;
552 regs_buff[68] = adapter->stats.rlec;
553 regs_buff[69] = adapter->stats.xonrxc;
554 regs_buff[70] = adapter->stats.xontxc;
555 regs_buff[71] = adapter->stats.xoffrxc;
556 regs_buff[72] = adapter->stats.xofftxc;
557 regs_buff[73] = adapter->stats.fcruc;
558 regs_buff[74] = adapter->stats.prc64;
559 regs_buff[75] = adapter->stats.prc127;
560 regs_buff[76] = adapter->stats.prc255;
561 regs_buff[77] = adapter->stats.prc511;
562 regs_buff[78] = adapter->stats.prc1023;
563 regs_buff[79] = adapter->stats.prc1522;
564 regs_buff[80] = adapter->stats.gprc;
565 regs_buff[81] = adapter->stats.bprc;
566 regs_buff[82] = adapter->stats.mprc;
567 regs_buff[83] = adapter->stats.gptc;
568 regs_buff[84] = adapter->stats.gorc;
569 regs_buff[86] = adapter->stats.gotc;
570 regs_buff[88] = adapter->stats.rnbc;
571 regs_buff[89] = adapter->stats.ruc;
572 regs_buff[90] = adapter->stats.rfc;
573 regs_buff[91] = adapter->stats.roc;
574 regs_buff[92] = adapter->stats.rjc;
575 regs_buff[93] = adapter->stats.mgprc;
576 regs_buff[94] = adapter->stats.mgpdc;
577 regs_buff[95] = adapter->stats.mgptc;
578 regs_buff[96] = adapter->stats.tor;
579 regs_buff[98] = adapter->stats.tot;
580 regs_buff[100] = adapter->stats.tpr;
581 regs_buff[101] = adapter->stats.tpt;
582 regs_buff[102] = adapter->stats.ptc64;
583 regs_buff[103] = adapter->stats.ptc127;
584 regs_buff[104] = adapter->stats.ptc255;
585 regs_buff[105] = adapter->stats.ptc511;
586 regs_buff[106] = adapter->stats.ptc1023;
587 regs_buff[107] = adapter->stats.ptc1522;
588 regs_buff[108] = adapter->stats.mptc;
589 regs_buff[109] = adapter->stats.bptc;
590 regs_buff[110] = adapter->stats.tsctc;
591 regs_buff[111] = adapter->stats.iac;
592 regs_buff[112] = adapter->stats.rpthc;
593 regs_buff[113] = adapter->stats.hgptc;
594 regs_buff[114] = adapter->stats.hgorc;
595 regs_buff[116] = adapter->stats.hgotc;
596 regs_buff[118] = adapter->stats.lenerrs;
597 regs_buff[119] = adapter->stats.scvpc;
598 regs_buff[120] = adapter->stats.hrmpc;
599
9d5c8243
AK		 600 for (i = 0; i < 4; i++)
601 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
602 for (i = 0; i < 4; i++)
83ab50a5 603 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 604 for (i = 0; i < 4; i++)
605 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
606 for (i = 0; i < 4; i++)
607 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
608 for (i = 0; i < 4; i++)
609 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
610 for (i = 0; i < 4; i++)
611 regs_buff[141 + i] = rd32(E1000_RDH(i));
612 for (i = 0; i < 4; i++)
613 regs_buff[145 + i] = rd32(E1000_RDT(i));
614 for (i = 0; i < 4; i++)
615 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
616
617 for (i = 0; i < 10; i++)
618 regs_buff[153 + i] = rd32(E1000_EITR(i));
619 for (i = 0; i < 8; i++)
620 regs_buff[163 + i] = rd32(E1000_IMIR(i));
621 for (i = 0; i < 8; i++)
622 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
623 for (i = 0; i < 16; i++)
624 regs_buff[179 + i] = rd32(E1000_RAL(i));
625 for (i = 0; i < 16; i++)
626 regs_buff[195 + i] = rd32(E1000_RAH(i));
627
628 for (i = 0; i < 4; i++)
629 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
630 for (i = 0; i < 4; i++)
631 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
632 for (i = 0; i < 4; i++)
633 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
634 for (i = 0; i < 4; i++)
635 regs_buff[223 + i] = rd32(E1000_TDH(i));
636 for (i = 0; i < 4; i++)
637 regs_buff[227 + i] = rd32(E1000_TDT(i));
638 for (i = 0; i < 4; i++)
639 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
640 for (i = 0; i < 4; i++)
641 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
642 for (i = 0; i < 4; i++)
643 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
644 for (i = 0; i < 4; i++)
645 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
646
647 for (i = 0; i < 4; i++)
648 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
649 for (i = 0; i < 4; i++)
650 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
651 for (i = 0; i < 32; i++)
652 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
653 for (i = 0; i < 128; i++)
654 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
655 for (i = 0; i < 128; i++)
656 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
657 for (i = 0; i < 4; i++)
658 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
659
660 regs_buff[547] = rd32(E1000_TDFH);
661 regs_buff[548] = rd32(E1000_TDFT);
662 regs_buff[549] = rd32(E1000_TDFHS);
663 regs_buff[550] = rd32(E1000_TDFPC);
f96a8a0b
CW		 664
665 if (hw->mac.type > e1000_82580) {
666 regs_buff[551] = adapter->stats.o2bgptc;
667 regs_buff[552] = adapter->stats.b2ospc;
668 regs_buff[553] = adapter->stats.o2bspc;
669 regs_buff[554] = adapter->stats.b2ogprc;
670 }
7e3b4ffb
KS		 671
672 if (hw->mac.type != e1000_82576)
673 return;
674 for (i = 0; i < 12; i++)
675 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
676 for (i = 0; i < 4; i++)
677 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
678 for (i = 0; i < 12; i++)
679 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
680 for (i = 0; i < 12; i++)
681 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
682 for (i = 0; i < 12; i++)
683 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
684 for (i = 0; i < 12; i++)
685 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
686 for (i = 0; i < 12; i++)
687 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
688 for (i = 0; i < 12; i++)
689 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
690
691 for (i = 0; i < 12; i++)
692 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
693 for (i = 0; i < 12; i++)
694 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
695 for (i = 0; i < 12; i++)
696 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
697 for (i = 0; i < 12; i++)
698 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
699 for (i = 0; i < 12; i++)
700 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
701 for (i = 0; i < 12; i++)
702 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
703 for (i = 0; i < 12; i++)
704 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
705 for (i = 0; i < 12; i++)
706 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
9d5c8243
AK		 707}
708
709static int igb_get_eeprom_len(struct net_device *netdev)
710{
711 struct igb_adapter *adapter = netdev_priv(netdev);
712 return adapter->hw.nvm.word_size * 2;
713}
714
715static int igb_get_eeprom(struct net_device *netdev,
716 struct ethtool_eeprom *eeprom, u8 *bytes)
717{
718 struct igb_adapter *adapter = netdev_priv(netdev);
719 struct e1000_hw *hw = &adapter->hw;
720 u16 *eeprom_buff;
721 int first_word, last_word;
722 int ret_val = 0;
723 u16 i;
724
725 if (eeprom->len == 0)
726 return -EINVAL;
727
728 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
729
730 first_word = eeprom->offset >> 1;
731 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
732
733 eeprom_buff = kmalloc(sizeof(u16) *
734 (last_word - first_word + 1), GFP_KERNEL);
735 if (!eeprom_buff)
736 return -ENOMEM;
737
738 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 739 ret_val = hw->nvm.ops.read(hw, first_word,
b980ac18
JK		 740 last_word - first_word + 1,
741 eeprom_buff);
9d5c8243
AK		 742 else {
743 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 744 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
b980ac18 745 &eeprom_buff[i]);
9d5c8243
AK		 746 if (ret_val)
747 break;
748 }
749 }
750
751 /* Device's eeprom is always little-endian, word addressable */
752 for (i = 0; i < last_word - first_word + 1; i++)
753 le16_to_cpus(&eeprom_buff[i]);
754
755 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
756 eeprom->len);
757 kfree(eeprom_buff);
758
759 return ret_val;
760}
761
762static int igb_set_eeprom(struct net_device *netdev,
763 struct ethtool_eeprom *eeprom, u8 *bytes)
764{
765 struct igb_adapter *adapter = netdev_priv(netdev);
766 struct e1000_hw *hw = &adapter->hw;
767 u16 *eeprom_buff;
768 void *ptr;
769 int max_len, first_word, last_word, ret_val = 0;
770 u16 i;
771
772 if (eeprom->len == 0)
773 return -EOPNOTSUPP;
774
a71fc313
FT		 775 if ((hw->mac.type >= e1000_i210) &&
776 !igb_get_flash_presence_i210(hw)) {
f96a8a0b 777 return -EOPNOTSUPP;
a71fc313 778 }
f96a8a0b 779
9d5c8243
AK		 780 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
781 return -EFAULT;
782
783 max_len = hw->nvm.word_size * 2;
784
785 first_word = eeprom->offset >> 1;
786 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
787 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
788 if (!eeprom_buff)
789 return -ENOMEM;
790
791 ptr = (void *)eeprom_buff;
792
793 if (eeprom->offset & 1) {
b980ac18
JK		 794 /* need read/modify/write of first changed EEPROM word
795 * only the second byte of the word is being modified
796 */
312c75ae 797 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 798 &eeprom_buff[0]);
799 ptr++;
800 }
801 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
b980ac18
JK		 802 /* need read/modify/write of last changed EEPROM word
803 * only the first byte of the word is being modified
804 */
312c75ae 805 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 806 &eeprom_buff[last_word - first_word]);
807 }
808
809 /* Device's eeprom is always little-endian, word addressable */
810 for (i = 0; i < last_word - first_word + 1; i++)
811 le16_to_cpus(&eeprom_buff[i]);
812
813 memcpy(ptr, bytes, eeprom->len);
814
815 for (i = 0; i < last_word - first_word + 1; i++)
816 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
817
312c75ae 818 ret_val = hw->nvm.ops.write(hw, first_word,
b980ac18 819 last_word - first_word + 1, eeprom_buff);
9d5c8243 820
2a0a0f1e
CW		 821 /* Update the checksum if nvm write succeeded */
822 if (ret_val == 0)
4322e561 823 hw->nvm.ops.update(hw);
9d5c8243 824
d67974f0 825 igb_set_fw_version(adapter);
9d5c8243
AK		 826 kfree(eeprom_buff);
827 return ret_val;
828}
829
830static void igb_get_drvinfo(struct net_device *netdev,
831 struct ethtool_drvinfo *drvinfo)
832{
833 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 834
612a94d6
RJ		 835 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
836 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
9d5c8243 837
b980ac18 838 /* EEPROM image version # is reported as firmware version # for
d67974f0
CW		 839 * 82575 controllers
840 */
841 strlcpy(drvinfo->fw_version, adapter->fw_version,
842 sizeof(drvinfo->fw_version));
612a94d6
RJ		 843 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
844 sizeof(drvinfo->bus_info));
9d5c8243
AK		 845 drvinfo->n_stats = IGB_STATS_LEN;
846 drvinfo->testinfo_len = IGB_TEST_LEN;
847 drvinfo->regdump_len = igb_get_regs_len(netdev);
848 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
849}
850
851static void igb_get_ringparam(struct net_device *netdev,
852 struct ethtool_ringparam *ring)
853{
854 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 855
856 ring->rx_max_pending = IGB_MAX_RXD;
857 ring->tx_max_pending = IGB_MAX_TXD;
68fd9910
AD		 858 ring->rx_pending = adapter->rx_ring_count;
859 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 860}
861
862static int igb_set_ringparam(struct net_device *netdev,
863 struct ethtool_ringparam *ring)
864{
865 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 866 struct igb_ring *temp_ring;
6d9f4fc4 867 int i, err = 0;
0e15439a 868 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 869
870 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
871 return -EINVAL;
872
0e15439a
AD		 873 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
874 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 875 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
876
0e15439a
AD		 877 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
878 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 879 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
880
68fd9910
AD		 881 if ((new_tx_count == adapter->tx_ring_count) &&
882 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 883 /* nothing to do */
884 return 0;
885 }
886
6d9f4fc4 887 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 888 usleep_range(1000, 2000);
6d9f4fc4
AD		 889
890 if (!netif_running(adapter->netdev)) {
891 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 892 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 893 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 894 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 895 adapter->tx_ring_count = new_tx_count;
896 adapter->rx_ring_count = new_rx_count;
897 goto clear_reset;
898 }
899
68fd9910 900 if (adapter->num_tx_queues > adapter->num_rx_queues)
b980ac18
JK		 901 temp_ring = vmalloc(adapter->num_tx_queues *
902 sizeof(struct igb_ring));
68fd9910 903 else
b980ac18
JK		 904 temp_ring = vmalloc(adapter->num_rx_queues *
905 sizeof(struct igb_ring));
68fd9910 906
6d9f4fc4
AD		 907 if (!temp_ring) {
908 err = -ENOMEM;
909 goto clear_reset;
910 }
9d5c8243 911
6d9f4fc4 912 igb_down(adapter);
9d5c8243 913
b980ac18 914 /* We can't just free everything and then setup again,
9d5c8243 915 * because the ISRs in MSI-X mode get passed pointers
b980ac18 916 * to the Tx and Rx ring structs.
9d5c8243 917 */
68fd9910 918 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 919 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 920 memcpy(&temp_ring[i], adapter->tx_ring[i],
921 sizeof(struct igb_ring));
922
68fd9910 923 temp_ring[i].count = new_tx_count;
80785298 924 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 925 if (err) {
68fd9910
AD		 926 while (i) {
927 i--;
928 igb_free_tx_resources(&temp_ring[i]);
929 }
9d5c8243
AK		 930 goto err_setup;
931 }
9d5c8243 932 }
68fd9910 933
3025a446
AD		 934 for (i = 0; i < adapter->num_tx_queues; i++) {
935 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 936
3025a446
AD		 937 memcpy(adapter->tx_ring[i], &temp_ring[i],
938 sizeof(struct igb_ring));
939 }
68fd9910
AD		 940
941 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 942 }
943
3025a446 944 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 945 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 946 memcpy(&temp_ring[i], adapter->rx_ring[i],
947 sizeof(struct igb_ring));
948
68fd9910 949 temp_ring[i].count = new_rx_count;
80785298 950 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 951 if (err) {
68fd9910
AD		 952 while (i) {
953 i--;
954 igb_free_rx_resources(&temp_ring[i]);
955 }
9d5c8243
AK		 956 goto err_setup;
957 }
958
9d5c8243 959 }
68fd9910 960
3025a446
AD		 961 for (i = 0; i < adapter->num_rx_queues; i++) {
962 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 963
3025a446
AD		 964 memcpy(adapter->rx_ring[i], &temp_ring[i],
965 sizeof(struct igb_ring));
966 }
68fd9910
AD		 967
968 adapter->rx_ring_count = new_rx_count;
9d5c8243 969 }
9d5c8243 970err_setup:
6d9f4fc4 971 igb_up(adapter);
68fd9910 972 vfree(temp_ring);
6d9f4fc4
AD		 973clear_reset:
974 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 975 return err;
976}
977
978/* ethtool register test data */
979struct igb_reg_test {
980 u16 reg;
2d064c06
AD		 981 u16 reg_offset;
982 u16 array_len;
983 u16 test_type;
9d5c8243
AK		 984 u32 mask;
985 u32 write;
986};
987
988/* In the hardware, registers are laid out either singly, in arrays
989 * spaced 0x100 bytes apart, or in contiguous tables. We assume
990 * most tests take place on arrays or single registers (handled
991 * as a single-element array) and special-case the tables.
992 * Table tests are always pattern tests.
993 *
994 * We also make provision for some required setup steps by specifying
995 * registers to be written without any read-back testing.
996 */
997
998#define PATTERN_TEST 1
999#define SET_READ_TEST 2
1000#define WRITE_NO_TEST 3
1001#define TABLE32_TEST 4
1002#define TABLE64_TEST_LO 5
1003#define TABLE64_TEST_HI 6
1004
f96a8a0b
CW		 1005/* i210 reg test */
1006static struct igb_reg_test reg_test_i210[] = {
1007 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1008 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1009 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1010 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1011 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1012 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1013 /* RDH is read-only for i210, only test RDT. */
1014 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1015 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1016 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1017 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1018 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1019 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1020 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1021 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1022 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1023 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1024 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1025 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1026 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1027 0xFFFFFFFF, 0xFFFFFFFF },
1028 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1029 0x900FFFFF, 0xFFFFFFFF },
1030 { E1000_MTA, 0, 128, TABLE32_TEST,
1031 0xFFFFFFFF, 0xFFFFFFFF },
1032 { 0, 0, 0, 0, 0 }
1033};
1034
d2ba2ed8
AD		 1035/* i350 reg test */
1036static struct igb_reg_test reg_test_i350[] = {
1037 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1038 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1039 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1040 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1041 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1042 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1043 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1044 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1045 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1046 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1047 /* RDH is read-only for i350, only test RDT. */
1048 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1049 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1050 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1051 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1052 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1053 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1054 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1055 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1056 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1057 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1058 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1059 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1060 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1061 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
9005df38
CW		 1062 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1063 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
d2ba2ed8
AD		 1064 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1065 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1066 0xFFFFFFFF, 0xFFFFFFFF },
1067 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1068 0xC3FFFFFF, 0xFFFFFFFF },
1069 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1070 0xFFFFFFFF, 0xFFFFFFFF },
1071 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1072 0xC3FFFFFF, 0xFFFFFFFF },
1073 { E1000_MTA, 0, 128, TABLE32_TEST,
1074 0xFFFFFFFF, 0xFFFFFFFF },
1075 { 0, 0, 0, 0 }
1076};
1077
55cac248
AD		 1078/* 82580 reg test */
1079static struct igb_reg_test reg_test_82580[] = {
1080 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1081 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1082 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1083 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1084 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1085 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1086 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1087 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1088 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1089 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1090 /* RDH is read-only for 82580, only test RDT. */
1091 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1092 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1093 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1094 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1095 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1096 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1097 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1099 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1100 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1101 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1102 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1103 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1104 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
9005df38
CW		 1105 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1106 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
55cac248
AD		 1107 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1108 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1109 0xFFFFFFFF, 0xFFFFFFFF },
1110 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1111 0x83FFFFFF, 0xFFFFFFFF },
1112 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1113 0xFFFFFFFF, 0xFFFFFFFF },
1114 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1115 0x83FFFFFF, 0xFFFFFFFF },
1116 { E1000_MTA, 0, 128, TABLE32_TEST,
1117 0xFFFFFFFF, 0xFFFFFFFF },
1118 { 0, 0, 0, 0 }
1119};
1120
2d064c06
AD		 1121/* 82576 reg test */
1122static struct igb_reg_test reg_test_82576[] = {
1123 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1124 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1125 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1126 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1127 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1128 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1129 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1130 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1131 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1132 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1133 /* Enable all RX queues before testing. */
c502ea2e
CW		 1134 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1135 E1000_RXDCTL_QUEUE_ENABLE },
1136 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1137 E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 1138 /* RDH is read-only for 82576, only test RDT. */
1139 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 1140 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 1141 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 1142 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 1143 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1144 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1145 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1146 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1147 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1149 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1150 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06 1152 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
9005df38
CW		 1153 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1154 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
2d064c06
AD		 1155 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1156 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1158 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1159 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
9005df38 1160 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
2d064c06
AD		 1161 { 0, 0, 0, 0 }
1162};
1163
1164/* 82575 register test */
9d5c8243 1165static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 1166 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1167 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1168 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1169 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1171 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1172 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 1173 /* Enable all four RX queues before testing. */
c502ea2e
CW		 1174 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1175 E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 1176 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 1177 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1178 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1179 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1180 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1181 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1182 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1183 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1184 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1185 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1186 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1187 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1188 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1189 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1190 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1191 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1192 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1193 { 0, 0, 0, 0 }
1194};
1195
1196static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1197 int reg, u32 mask, u32 write)
1198{
2753f4ce 1199 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1200 u32 pat, val;
d34a15ab
CW		 1201 static const u32 _test[] = {
1202 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
9d5c8243 1203 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce 1204 wr32(reg, (_test[pat] & write));
93ed8359 1205 val = rd32(reg) & mask;
9d5c8243 1206 if (val != (_test[pat] & write & mask)) {
d836200a
JJ		 1207 dev_err(&adapter->pdev->dev,
1208 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
9d5c8243
AK		 1209 reg, val, (_test[pat] & write & mask));
1210 *data = reg;
f6f38e27 1211 return true;
9d5c8243
AK		 1212 }
1213 }
317f66bd 1214
f6f38e27 1215 return false;
9d5c8243
AK		 1216}
1217
1218static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1219 int reg, u32 mask, u32 write)
1220{
2753f4ce 1221 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1222 u32 val;
9005df38 1223
2753f4ce
AD		 1224 wr32(reg, write & mask);
1225 val = rd32(reg);
9d5c8243 1226 if ((write & mask) != (val & mask)) {
d836200a 1227 dev_err(&adapter->pdev->dev,
c502ea2e
CW		 1228 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1229 reg, (val & mask), (write & mask));
9d5c8243 1230 *data = reg;
f6f38e27 1231 return true;
9d5c8243 1232 }
317f66bd 1233
f6f38e27 1234 return false;
9d5c8243
AK		 1235}
1236
1237#define REG_PATTERN_TEST(reg, mask, write) \
1238 do { \
1239 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1240 return 1; \
1241 } while (0)
1242
1243#define REG_SET_AND_CHECK(reg, mask, write) \
1244 do { \
1245 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1246 return 1; \
1247 } while (0)
1248
1249static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1250{
1251 struct e1000_hw *hw = &adapter->hw;
1252 struct igb_reg_test *test;
1253 u32 value, before, after;
1254 u32 i, toggle;
1255
2d064c06 1256 switch (adapter->hw.mac.type) {
d2ba2ed8 1257 case e1000_i350:
ceb5f13b 1258 case e1000_i354:
d2ba2ed8
AD		 1259 test = reg_test_i350;
1260 toggle = 0x7FEFF3FF;
1261 break;
f96a8a0b
CW		 1262 case e1000_i210:
1263 case e1000_i211:
1264 test = reg_test_i210;
1265 toggle = 0x7FEFF3FF;
1266 break;
55cac248
AD		 1267 case e1000_82580:
1268 test = reg_test_82580;
1269 toggle = 0x7FEFF3FF;
1270 break;
2d064c06
AD		 1271 case e1000_82576:
1272 test = reg_test_82576;
317f66bd 1273 toggle = 0x7FFFF3FF;
2d064c06
AD		 1274 break;
1275 default:
1276 test = reg_test_82575;
317f66bd 1277 toggle = 0x7FFFF3FF;
2d064c06
AD		 1278 break;
1279 }
9d5c8243
AK		 1280
1281 /* Because the status register is such a special case,
1282 * we handle it separately from the rest of the register
1283 * tests. Some bits are read-only, some toggle, and some
1284 * are writable on newer MACs.
1285 */
1286 before = rd32(E1000_STATUS);
1287 value = (rd32(E1000_STATUS) & toggle);
1288 wr32(E1000_STATUS, toggle);
1289 after = rd32(E1000_STATUS) & toggle;
1290 if (value != after) {
d836200a
JJ		 1291 dev_err(&adapter->pdev->dev,
1292 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1293 after, value);
9d5c8243
AK		 1294 *data = 1;
1295 return 1;
1296 }
1297 /* restore previous status */
1298 wr32(E1000_STATUS, before);
1299
1300 /* Perform the remainder of the register test, looping through
1301 * the test table until we either fail or reach the null entry.
1302 */
1303 while (test->reg) {
1304 for (i = 0; i < test->array_len; i++) {
1305 switch (test->test_type) {
1306 case PATTERN_TEST:
2753f4ce
AD		 1307 REG_PATTERN_TEST(test->reg +
1308 (i * test->reg_offset),
9d5c8243
AK		 1309 test->mask,
1310 test->write);
1311 break;
1312 case SET_READ_TEST:
2753f4ce
AD		 1313 REG_SET_AND_CHECK(test->reg +
1314 (i * test->reg_offset),
9d5c8243
AK		 1315 test->mask,
1316 test->write);
1317 break;
1318 case WRITE_NO_TEST:
1319 writel(test->write,
1320 (adapter->hw.hw_addr + test->reg)
2d064c06 1321 + (i * test->reg_offset));
9d5c8243
AK		 1322 break;
1323 case TABLE32_TEST:
1324 REG_PATTERN_TEST(test->reg + (i * 4),
1325 test->mask,
1326 test->write);
1327 break;
1328 case TABLE64_TEST_LO:
1329 REG_PATTERN_TEST(test->reg + (i * 8),
1330 test->mask,
1331 test->write);
1332 break;
1333 case TABLE64_TEST_HI:
1334 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1335 test->mask,
1336 test->write);
1337 break;
1338 }
1339 }
1340 test++;
1341 }
1342
1343 *data = 0;
1344 return 0;
1345}
1346
1347static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1348{
53b87ce3
CW		 1349 struct e1000_hw *hw = &adapter->hw;
1350
9d5c8243 1351 *data = 0;
9d5c8243 1352
53b87ce3
CW		 1353 /* Validate eeprom on all parts but flashless */
1354 switch (hw->mac.type) {
1355 case e1000_i210:
1356 case e1000_i211:
1357 if (igb_get_flash_presence_i210(hw)) {
1358 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1359 *data = 2;
1360 }
1361 break;
1362 default:
f96a8a0b
CW		 1363 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1364 *data = 2;
53b87ce3 1365 break;
f96a8a0b 1366 }
9d5c8243
AK		 1367
1368 return *data;
1369}
1370
1371static irqreturn_t igb_test_intr(int irq, void *data)
1372{
317f66bd 1373 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1374 struct e1000_hw *hw = &adapter->hw;
1375
1376 adapter->test_icr |= rd32(E1000_ICR);
1377
1378 return IRQ_HANDLED;
1379}
1380
1381static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1382{
1383 struct e1000_hw *hw = &adapter->hw;
1384 struct net_device *netdev = adapter->netdev;
2753f4ce 1385 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1386 u32 irq = adapter->pdev->irq;
1387
1388 *data = 0;
1389
1390 /* Hook up test interrupt handler just for this test */
cd14ef54 1391 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4eefa8f0 1392 if (request_irq(adapter->msix_entries[0].vector,
9005df38 1393 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1394 *data = 1;
1395 return -1;
1396 }
4eefa8f0 1397 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1398 shared_int = false;
4eefa8f0 1399 if (request_irq(irq,
9005df38 1400 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1401 *data = 1;
1402 return -1;
1403 }
a0607fd3 1404 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1405 netdev->name, adapter)) {
9d5c8243 1406 shared_int = false;
a0607fd3 1407 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1408 netdev->name, adapter)) {
9d5c8243
AK		 1409 *data = 1;
1410 return -1;
1411 }
1412 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1413 (shared_int ? "shared" : "unshared"));
317f66bd 1414
9d5c8243 1415 /* Disable all the interrupts */
4eefa8f0 1416 wr32(E1000_IMC, ~0);
945a5151 1417 wrfl();
0d451e79 1418 usleep_range(10000, 11000);
9d5c8243 1419
2753f4ce 1420 /* Define all writable bits for ICS */
4eefa8f0 1421 switch (hw->mac.type) {
2753f4ce
AD		 1422 case e1000_82575:
1423 ics_mask = 0x37F47EDD;
1424 break;
1425 case e1000_82576:
1426 ics_mask = 0x77D4FBFD;
1427 break;
55cac248
AD		 1428 case e1000_82580:
1429 ics_mask = 0x77DCFED5;
1430 break;
d2ba2ed8 1431 case e1000_i350:
ceb5f13b 1432 case e1000_i354:
f96a8a0b
CW		 1433 case e1000_i210:
1434 case e1000_i211:
d2ba2ed8
AD		 1435 ics_mask = 0x77DCFED5;
1436 break;
2753f4ce
AD		 1437 default:
1438 ics_mask = 0x7FFFFFFF;
1439 break;
1440 }
1441
9d5c8243 1442 /* Test each interrupt */
2753f4ce 1443 for (; i < 31; i++) {
9d5c8243
AK		 1444 /* Interrupt to test */
1445 mask = 1 << i;
1446
2753f4ce
AD		 1447 if (!(mask & ics_mask))
1448 continue;
1449
9d5c8243
AK		 1450 if (!shared_int) {
1451 /* Disable the interrupt to be reported in
1452 * the cause register and then force the same
1453 * interrupt and see if one gets posted. If
1454 * an interrupt was posted to the bus, the
1455 * test failed.
1456 */
1457 adapter->test_icr = 0;
2753f4ce
AD		 1458
1459 /* Flush any pending interrupts */
1460 wr32(E1000_ICR, ~0);
1461
1462 wr32(E1000_IMC, mask);
1463 wr32(E1000_ICS, mask);
945a5151 1464 wrfl();
0d451e79 1465 usleep_range(10000, 11000);
9d5c8243
AK		 1466
1467 if (adapter->test_icr & mask) {
1468 *data = 3;
1469 break;
1470 }
1471 }
1472
1473 /* Enable the interrupt to be reported in
1474 * the cause register and then force the same
1475 * interrupt and see if one gets posted. If
1476 * an interrupt was not posted to the bus, the
1477 * test failed.
1478 */
1479 adapter->test_icr = 0;
2753f4ce
AD		 1480
1481 /* Flush any pending interrupts */
1482 wr32(E1000_ICR, ~0);
1483
9d5c8243
AK		 1484 wr32(E1000_IMS, mask);
1485 wr32(E1000_ICS, mask);
945a5151 1486 wrfl();
0d451e79 1487 usleep_range(10000, 11000);
9d5c8243
AK		 1488
1489 if (!(adapter->test_icr & mask)) {
1490 *data = 4;
1491 break;
1492 }
1493
1494 if (!shared_int) {
1495 /* Disable the other interrupts to be reported in
1496 * the cause register and then force the other
1497 * interrupts and see if any get posted. If
1498 * an interrupt was posted to the bus, the
1499 * test failed.
1500 */
1501 adapter->test_icr = 0;
2753f4ce
AD		 1502
1503 /* Flush any pending interrupts */
1504 wr32(E1000_ICR, ~0);
1505
1506 wr32(E1000_IMC, ~mask);
1507 wr32(E1000_ICS, ~mask);
945a5151 1508 wrfl();
0d451e79 1509 usleep_range(10000, 11000);
9d5c8243 1510
2753f4ce 1511 if (adapter->test_icr & mask) {
9d5c8243
AK		 1512 *data = 5;
1513 break;
1514 }
1515 }
1516 }
1517
1518 /* Disable all the interrupts */
2753f4ce 1519 wr32(E1000_IMC, ~0);
945a5151 1520 wrfl();
0d451e79 1521 usleep_range(10000, 11000);
9d5c8243
AK		 1522
1523 /* Unhook test interrupt handler */
cd14ef54 1524 if (adapter->flags & IGB_FLAG_HAS_MSIX)
4eefa8f0
AD		 1525 free_irq(adapter->msix_entries[0].vector, adapter);
1526 else
1527 free_irq(irq, adapter);
9d5c8243
AK		 1528
1529 return *data;
1530}
1531
1532static void igb_free_desc_rings(struct igb_adapter *adapter)
1533{
d7ee5b3a
AD		 1534 igb_free_tx_resources(&adapter->test_tx_ring);
1535 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1536}
1537
1538static int igb_setup_desc_rings(struct igb_adapter *adapter)
1539{
9d5c8243
AK		 1540 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1541 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1542 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1543 int ret_val;
9d5c8243
AK		 1544
1545 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1546 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1547 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1548 tx_ring->netdev = adapter->netdev;
1549 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1550
d7ee5b3a 1551 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1552 ret_val = 1;
1553 goto err_nomem;
1554 }
1555
d7ee5b3a
AD		 1556 igb_setup_tctl(adapter);
1557 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1558
9d5c8243 1559 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1560 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1561 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a 1562 rx_ring->netdev = adapter->netdev;
d7ee5b3a
AD		 1563 rx_ring->reg_idx = adapter->vfs_allocated_count;
1564
1565 if (igb_setup_rx_resources(rx_ring)) {
1566 ret_val = 3;
9d5c8243
AK		 1567 goto err_nomem;
1568 }
9d5c8243 1569
d7ee5b3a
AD		 1570 /* set the default queue to queue 0 of PF */
1571 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1572
d7ee5b3a
AD		 1573 /* enable receive ring */
1574 igb_setup_rctl(adapter);
1575 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1576
cd392f5c 1577 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1578
1579 return 0;
1580
1581err_nomem:
1582 igb_free_desc_rings(adapter);
1583 return ret_val;
1584}
1585
1586static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1587{
1588 struct e1000_hw *hw = &adapter->hw;
1589
1590 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1591 igb_write_phy_reg(hw, 29, 0x001F);
1592 igb_write_phy_reg(hw, 30, 0x8FFC);
1593 igb_write_phy_reg(hw, 29, 0x001A);
1594 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1595}
1596
1597static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1598{
1599 struct e1000_hw *hw = &adapter->hw;
1600 u32 ctrl_reg = 0;
9d5c8243
AK		 1601
1602 hw->mac.autoneg = false;
1603
8aa23f0d
CW		 1604 if (hw->phy.type == e1000_phy_m88) {
1605 if (hw->phy.id != I210_I_PHY_ID) {
1606 /* Auto-MDI/MDIX Off */
1607 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1608 /* reset to update Auto-MDI/MDIX */
1609 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1610 /* autoneg off */
1611 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1612 } else {
1613 /* force 1000, set loopback */
1614 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1615 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1616 }
5aa3a449
TF		 1617 } else if (hw->phy.type == e1000_phy_82580) {
1618 /* enable MII loopback */
1619 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
9d5c8243
AK		 1620 }
1621
119b0e03
SA		 1622 /* add small delay to avoid loopback test failure */
1623 msleep(50);
1624
9d5c8243 1625 /* force 1000, set loopback */
f5f4cf08 1626 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1627
1628 /* Now set up the MAC to the same speed/duplex as the PHY. */
1629 ctrl_reg = rd32(E1000_CTRL);
1630 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1631 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1632 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1633 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1634 E1000_CTRL_FD | /* Force Duplex to FULL */
1635 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1636
8aa23f0d 1637 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1638 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1639
1640 wr32(E1000_CTRL, ctrl_reg);
1641
1642 /* Disable the receiver on the PHY so when a cable is plugged in, the
1643 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1644 */
8aa23f0d 1645 if (hw->phy.type == e1000_phy_m88)
9d5c8243
AK		 1646 igb_phy_disable_receiver(adapter);
1647
8aa23f0d 1648 mdelay(500);
9d5c8243
AK		 1649 return 0;
1650}
1651
1652static int igb_set_phy_loopback(struct igb_adapter *adapter)
1653{
1654 return igb_integrated_phy_loopback(adapter);
1655}
1656
1657static int igb_setup_loopback_test(struct igb_adapter *adapter)
1658{
1659 struct e1000_hw *hw = &adapter->hw;
2d064c06 1660 u32 reg;
9d5c8243 1661
317f66bd
AD		 1662 reg = rd32(E1000_CTRL_EXT);
1663
1664 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1665 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
a14bc2bb
RH		 1666 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1667 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1668 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
a4e979a2 1669 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
3cfcf036
TF		 1670 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1671 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
a14bc2bb
RH		 1672 /* Enable DH89xxCC MPHY for near end loopback */
1673 reg = rd32(E1000_MPHY_ADDR_CTL);
1674 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1675 E1000_MPHY_PCS_CLK_REG_OFFSET;
1676 wr32(E1000_MPHY_ADDR_CTL, reg);
1677
1678 reg = rd32(E1000_MPHY_DATA);
1679 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1680 wr32(E1000_MPHY_DATA, reg);
1681 }
1682
2d064c06
AD		 1683 reg = rd32(E1000_RCTL);
1684 reg |= E1000_RCTL_LBM_TCVR;
1685 wr32(E1000_RCTL, reg);
1686
1687 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1688
1689 reg = rd32(E1000_CTRL);
1690 reg &= ~(E1000_CTRL_RFCE |
1691 E1000_CTRL_TFCE |
1692 E1000_CTRL_LRST);
1693 reg |= E1000_CTRL_SLU |
2753f4ce 1694 E1000_CTRL_FD;
2d064c06
AD		 1695 wr32(E1000_CTRL, reg);
1696
1697 /* Unset switch control to serdes energy detect */
1698 reg = rd32(E1000_CONNSW);
1699 reg &= ~E1000_CONNSW_ENRGSRC;
1700 wr32(E1000_CONNSW, reg);
1701
3860a0bf 1702 /* Unset sigdetect for SERDES loopback on
0ba96d3d 1703 * 82580 and newer devices.
3860a0bf 1704 */
0ba96d3d 1705 if (hw->mac.type >= e1000_82580) {
3860a0bf
CW		 1706 reg = rd32(E1000_PCS_CFG0);
1707 reg |= E1000_PCS_CFG_IGN_SD;
1708 wr32(E1000_PCS_CFG0, reg);
3860a0bf
CW		 1709 }
1710
2d064c06
AD		 1711 /* Set PCS register for forced speed */
1712 reg = rd32(E1000_PCS_LCTL);
1713 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1714 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1715 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1716 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1717 E1000_PCS_LCTL_FSD | /* Force Speed */
1718 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1719 wr32(E1000_PCS_LCTL, reg);
1720
9d5c8243 1721 return 0;
9d5c8243
AK		 1722 }
1723
317f66bd 1724 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1725}
1726
1727static void igb_loopback_cleanup(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 u32 rctl;
1731 u16 phy_reg;
1732
a14bc2bb
RH		 1733 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1734 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1735 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
a4e979a2
FT		 1736 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1737 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
a14bc2bb
RH		 1738 u32 reg;
1739
1740 /* Disable near end loopback on DH89xxCC */
1741 reg = rd32(E1000_MPHY_ADDR_CTL);
1742 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1743 E1000_MPHY_PCS_CLK_REG_OFFSET;
1744 wr32(E1000_MPHY_ADDR_CTL, reg);
1745
1746 reg = rd32(E1000_MPHY_DATA);
1747 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1748 wr32(E1000_MPHY_DATA, reg);
1749 }
1750
9d5c8243
AK		 1751 rctl = rd32(E1000_RCTL);
1752 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1753 wr32(E1000_RCTL, rctl);
1754
1755 hw->mac.autoneg = true;
f5f4cf08 1756 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1757 if (phy_reg & MII_CR_LOOPBACK) {
1758 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1759 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1760 igb_phy_sw_reset(hw);
1761 }
1762}
1763
1764static void igb_create_lbtest_frame(struct sk_buff *skb,
1765 unsigned int frame_size)
1766{
1767 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1768 frame_size /= 2;
1769 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1770 memset(&skb->data[frame_size + 10], 0xBE, 1);
1771 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1772}
1773
1a1c225b
AD		 1774static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1775 unsigned int frame_size)
9d5c8243 1776{
1a1c225b
AD		 1777 unsigned char *data;
1778 bool match = true;
1779
1780 frame_size >>= 1;
1781
cbc8e55f 1782 data = kmap(rx_buffer->page);
1a1c225b
AD		 1783
1784 if (data[3] != 0xFF ||
1785 data[frame_size + 10] != 0xBE ||
1786 data[frame_size + 12] != 0xAF)
1787 match = false;
1788
1789 kunmap(rx_buffer->page);
1790
1791 return match;
9d5c8243
AK		 1792}
1793
ad93d17e 1794static int igb_clean_test_rings(struct igb_ring *rx_ring,
b980ac18
JK		 1795 struct igb_ring *tx_ring,
1796 unsigned int size)
ad93d17e
AD		 1797{
1798 union e1000_adv_rx_desc *rx_desc;
06034649
AD		 1799 struct igb_rx_buffer *rx_buffer_info;
1800 struct igb_tx_buffer *tx_buffer_info;
6ad4edfc 1801 u16 rx_ntc, tx_ntc, count = 0;
ad93d17e
AD		 1802
1803 /* initialize next to clean and descriptor values */
1804 rx_ntc = rx_ring->next_to_clean;
1805 tx_ntc = tx_ring->next_to_clean;
60136906 1806 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e 1807
3ceb90fd 1808 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
b980ac18 1809 /* check Rx buffer */
06034649 1810 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
ad93d17e 1811
cbc8e55f
AD		 1812 /* sync Rx buffer for CPU read */
1813 dma_sync_single_for_cpu(rx_ring->dev,
1814 rx_buffer_info->dma,
de78d1f9 1815 IGB_RX_BUFSZ,
cbc8e55f 1816 DMA_FROM_DEVICE);
ad93d17e
AD		 1817
1818 /* verify contents of skb */
1a1c225b 1819 if (igb_check_lbtest_frame(rx_buffer_info, size))
ad93d17e
AD		 1820 count++;
1821
cbc8e55f
AD		 1822 /* sync Rx buffer for device write */
1823 dma_sync_single_for_device(rx_ring->dev,
1824 rx_buffer_info->dma,
de78d1f9 1825 IGB_RX_BUFSZ,
cbc8e55f
AD		 1826 DMA_FROM_DEVICE);
1827
b980ac18 1828 /* unmap buffer on Tx side */
06034649
AD		 1829 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1830 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
ad93d17e 1831
b980ac18 1832 /* increment Rx/Tx next to clean counters */
ad93d17e
AD		 1833 rx_ntc++;
1834 if (rx_ntc == rx_ring->count)
1835 rx_ntc = 0;
1836 tx_ntc++;
1837 if (tx_ntc == tx_ring->count)
1838 tx_ntc = 0;
1839
1840 /* fetch next descriptor */
60136906 1841 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e
AD		 1842 }
1843
cbc8e55f 1844 netdev_tx_reset_queue(txring_txq(tx_ring));
51a76c30 1845
ad93d17e 1846 /* re-map buffers to ring, store next to clean values */
cd392f5c 1847 igb_alloc_rx_buffers(rx_ring, count);
ad93d17e
AD		 1848 rx_ring->next_to_clean = rx_ntc;
1849 tx_ring->next_to_clean = tx_ntc;
1850
1851 return count;
1852}
1853
9d5c8243
AK		 1854static int igb_run_loopback_test(struct igb_adapter *adapter)
1855{
9d5c8243
AK		 1856 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1857 struct igb_ring *rx_ring = &adapter->test_rx_ring;
6ad4edfc
AD		 1858 u16 i, j, lc, good_cnt;
1859 int ret_val = 0;
44390ca6 1860 unsigned int size = IGB_RX_HDR_LEN;
ad93d17e
AD		 1861 netdev_tx_t tx_ret_val;
1862 struct sk_buff *skb;
1863
1864 /* allocate test skb */
1865 skb = alloc_skb(size, GFP_KERNEL);
1866 if (!skb)
1867 return 11;
9d5c8243 1868
ad93d17e
AD		 1869 /* place data into test skb */
1870 igb_create_lbtest_frame(skb, size);
1871 skb_put(skb, size);
9d5c8243 1872
b980ac18 1873 /* Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1874 * The idea is to wrap the largest ring a number of times using 64
1875 * send/receive pairs during each loop
1876 */
1877
1878 if (rx_ring->count <= tx_ring->count)
1879 lc = ((tx_ring->count / 64) * 2) + 1;
1880 else
1881 lc = ((rx_ring->count / 64) * 2) + 1;
1882
9d5c8243 1883 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1884 /* reset count of good packets */
9d5c8243 1885 good_cnt = 0;
ad93d17e
AD		 1886
1887 /* place 64 packets on the transmit queue*/
1888 for (i = 0; i < 64; i++) {
1889 skb_get(skb);
cd392f5c 1890 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
ad93d17e 1891 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1892 good_cnt++;
ad93d17e
AD		 1893 }
1894
9d5c8243 1895 if (good_cnt != 64) {
ad93d17e 1896 ret_val = 12;
9d5c8243
AK		 1897 break;
1898 }
ad93d17e 1899
b980ac18 1900 /* allow 200 milliseconds for packets to go from Tx to Rx */
ad93d17e
AD		 1901 msleep(200);
1902
1903 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1904 if (good_cnt != 64) {
1905 ret_val = 13;
9d5c8243
AK		 1906 break;
1907 }
1908 } /* end loop count loop */
ad93d17e
AD		 1909
1910 /* free the original skb */
1911 kfree_skb(skb);
1912
9d5c8243
AK		 1913 return ret_val;
1914}
1915
1916static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1917{
1918 /* PHY loopback cannot be performed if SoL/IDER
b980ac18
JK		 1919 * sessions are active
1920 */
9d5c8243
AK		 1921 if (igb_check_reset_block(&adapter->hw)) {
1922 dev_err(&adapter->pdev->dev,
d836200a 1923 "Cannot do PHY loopback test when SoL/IDER is active.\n");
f96a8a0b
CW		 1924 *data = 0;
1925 goto out;
1926 }
ceb5f13b
CW		 1927
1928 if (adapter->hw.mac.type == e1000_i354) {
1929 dev_info(&adapter->pdev->dev,
1930 "Loopback test not supported on i354.\n");
1931 *data = 0;
1932 goto out;
1933 }
9d5c8243
AK		 1934 *data = igb_setup_desc_rings(adapter);
1935 if (*data)
1936 goto out;
1937 *data = igb_setup_loopback_test(adapter);
1938 if (*data)
1939 goto err_loopback;
1940 *data = igb_run_loopback_test(adapter);
1941 igb_loopback_cleanup(adapter);
1942
1943err_loopback:
1944 igb_free_desc_rings(adapter);
1945out:
1946 return *data;
1947}
1948
1949static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1950{
1951 struct e1000_hw *hw = &adapter->hw;
1952 *data = 0;
1953 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1954 int i = 0;
9005df38 1955
9d5c8243
AK		 1956 hw->mac.serdes_has_link = false;
1957
1958 /* On some blade server designs, link establishment
b980ac18
JK		 1959 * could take as long as 2-3 minutes
1960 */
9d5c8243
AK		 1961 do {
1962 hw->mac.ops.check_for_link(&adapter->hw);
1963 if (hw->mac.serdes_has_link)
1964 return *data;
1965 msleep(20);
1966 } while (i++ < 3750);
1967
1968 *data = 1;
1969 } else {
1970 hw->mac.ops.check_for_link(&adapter->hw);
1971 if (hw->mac.autoneg)
4507dc9f 1972 msleep(5000);
9d5c8243 1973
317f66bd 1974 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1975 *data = 1;
1976 }
1977 return *data;
1978}
1979
1980static void igb_diag_test(struct net_device *netdev,
1981 struct ethtool_test *eth_test, u64 *data)
1982{
1983 struct igb_adapter *adapter = netdev_priv(netdev);
1984 u16 autoneg_advertised;
1985 u8 forced_speed_duplex, autoneg;
1986 bool if_running = netif_running(netdev);
1987
1988 set_bit(__IGB_TESTING, &adapter->state);
56cec249
CW		 1989
1990 /* can't do offline tests on media switching devices */
1991 if (adapter->hw.dev_spec._82575.mas_capable)
1992 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
9d5c8243
AK		 1993 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1994 /* Offline tests */
1995
1996 /* save speed, duplex, autoneg settings */
1997 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1998 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1999 autoneg = adapter->hw.mac.autoneg;
2000
2001 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2002
88a268c1
NN		 2003 /* power up link for link test */
2004 igb_power_up_link(adapter);
2005
9d5c8243 2006 /* Link test performed before hardware reset so autoneg doesn't
b980ac18
JK		 2007 * interfere with test result
2008 */
9d5c8243
AK		 2009 if (igb_link_test(adapter, &data[4]))
2010 eth_test->flags |= ETH_TEST_FL_FAILED;
2011
2012 if (if_running)
2013 /* indicate we're in test mode */
2014 dev_close(netdev);
2015 else
2016 igb_reset(adapter);
2017
2018 if (igb_reg_test(adapter, &data[0]))
2019 eth_test->flags |= ETH_TEST_FL_FAILED;
2020
2021 igb_reset(adapter);
2022 if (igb_eeprom_test(adapter, &data[1]))
2023 eth_test->flags |= ETH_TEST_FL_FAILED;
2024
2025 igb_reset(adapter);
2026 if (igb_intr_test(adapter, &data[2]))
2027 eth_test->flags |= ETH_TEST_FL_FAILED;
2028
2029 igb_reset(adapter);
88a268c1
NN		 2030 /* power up link for loopback test */
2031 igb_power_up_link(adapter);
9d5c8243
AK		 2032 if (igb_loopback_test(adapter, &data[3]))
2033 eth_test->flags |= ETH_TEST_FL_FAILED;
2034
2035 /* restore speed, duplex, autoneg settings */
2036 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2037 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2038 adapter->hw.mac.autoneg = autoneg;
2039
2040 /* force this routine to wait until autoneg complete/timeout */
2041 adapter->hw.phy.autoneg_wait_to_complete = true;
2042 igb_reset(adapter);
2043 adapter->hw.phy.autoneg_wait_to_complete = false;
2044
2045 clear_bit(__IGB_TESTING, &adapter->state);
2046 if (if_running)
2047 dev_open(netdev);
2048 } else {
2049 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 2050
2051 /* PHY is powered down when interface is down */
8d420a1b
AD		 2052 if (if_running && igb_link_test(adapter, &data[4]))
2053 eth_test->flags |= ETH_TEST_FL_FAILED;
2054 else
88a268c1 2055 data[4] = 0;
9d5c8243
AK		 2056
2057 /* Online tests aren't run; pass by default */
2058 data[0] = 0;
2059 data[1] = 0;
2060 data[2] = 0;
2061 data[3] = 0;
2062
2063 clear_bit(__IGB_TESTING, &adapter->state);
2064 }
2065 msleep_interruptible(4 * 1000);
2066}
2067
9d5c8243
AK		 2068static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2069{
2070 struct igb_adapter *adapter = netdev_priv(netdev);
2071
9d5c8243
AK		 2072 wol->wolopts = 0;
2073
63d4a8f9 2074 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2075 return;
2076
42ce4126
AA		 2077 wol->supported = WAKE_UCAST | WAKE_MCAST |
2078 WAKE_BCAST | WAKE_MAGIC |
2079 WAKE_PHY;
2080
9d5c8243
AK		 2081 /* apply any specific unsupported masks here */
2082 switch (adapter->hw.device_id) {
2083 default:
2084 break;
2085 }
2086
2087 if (adapter->wol & E1000_WUFC_EX)
2088 wol->wolopts |= WAKE_UCAST;
2089 if (adapter->wol & E1000_WUFC_MC)
2090 wol->wolopts |= WAKE_MCAST;
2091 if (adapter->wol & E1000_WUFC_BC)
2092 wol->wolopts |= WAKE_BCAST;
2093 if (adapter->wol & E1000_WUFC_MAG)
2094 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 2095 if (adapter->wol & E1000_WUFC_LNKC)
2096 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 2097}
2098
2099static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2100{
2101 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 2102
22939f06 2103 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 2104 return -EOPNOTSUPP;
2105
63d4a8f9 2106 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2107 return wol->wolopts ? -EOPNOTSUPP : 0;
2108
9d5c8243
AK		 2109 /* these settings will always override what we currently have */
2110 adapter->wol = 0;
2111
2112 if (wol->wolopts & WAKE_UCAST)
2113 adapter->wol |= E1000_WUFC_EX;
2114 if (wol->wolopts & WAKE_MCAST)
2115 adapter->wol |= E1000_WUFC_MC;
2116 if (wol->wolopts & WAKE_BCAST)
2117 adapter->wol |= E1000_WUFC_BC;
2118 if (wol->wolopts & WAKE_MAGIC)
2119 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 2120 if (wol->wolopts & WAKE_PHY)
2121 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 2122 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2123
9d5c8243
AK		 2124 return 0;
2125}
2126
9d5c8243
AK		 2127/* bit defines for adapter->led_status */
2128#define IGB_LED_ON 0
2129
936db355
JK		 2130static int igb_set_phys_id(struct net_device *netdev,
2131 enum ethtool_phys_id_state state)
9d5c8243
AK		 2132{
2133 struct igb_adapter *adapter = netdev_priv(netdev);
2134 struct e1000_hw *hw = &adapter->hw;
2135
936db355
JK		 2136 switch (state) {
2137 case ETHTOOL_ID_ACTIVE:
2138 igb_blink_led(hw);
2139 return 2;
2140 case ETHTOOL_ID_ON:
2141 igb_blink_led(hw);
2142 break;
2143 case ETHTOOL_ID_OFF:
2144 igb_led_off(hw);
2145 break;
2146 case ETHTOOL_ID_INACTIVE:
2147 igb_led_off(hw);
2148 clear_bit(IGB_LED_ON, &adapter->led_status);
2149 igb_cleanup_led(hw);
2150 break;
2151 }
9d5c8243
AK		 2152
2153 return 0;
2154}
2155
2156static int igb_set_coalesce(struct net_device *netdev,
2157 struct ethtool_coalesce *ec)
2158{
2159 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 2160 int i;
9d5c8243 2161
0c5bbeb8
TF		 2162 if (ec->rx_max_coalesced_frames ||
2163 ec->rx_coalesce_usecs_irq ||
2164 ec->rx_max_coalesced_frames_irq ||
2165 ec->tx_max_coalesced_frames ||
2166 ec->tx_coalesce_usecs_irq ||
2167 ec->stats_block_coalesce_usecs ||
2168 ec->use_adaptive_rx_coalesce ||
2169 ec->use_adaptive_tx_coalesce ||
2170 ec->pkt_rate_low ||
2171 ec->rx_coalesce_usecs_low ||
2172 ec->rx_max_coalesced_frames_low ||
2173 ec->tx_coalesce_usecs_low ||
2174 ec->tx_max_coalesced_frames_low ||
2175 ec->pkt_rate_high ||
2176 ec->rx_coalesce_usecs_high ||
2177 ec->rx_max_coalesced_frames_high ||
2178 ec->tx_coalesce_usecs_high ||
2179 ec->tx_max_coalesced_frames_high ||
2180 ec->rate_sample_interval)
2181 return -ENOTSUPP;
2182
9d5c8243
AK		 2183 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2184 ((ec->rx_coalesce_usecs > 3) &&
2185 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2186 (ec->rx_coalesce_usecs == 2))
2187 return -EINVAL;
2188
4fc82adf
AD		 2189 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2190 ((ec->tx_coalesce_usecs > 3) &&
2191 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2192 (ec->tx_coalesce_usecs == 2))
2193 return -EINVAL;
2194
2195 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2196 return -EINVAL;
2197
831ec0b4
CW		 2198 /* If ITR is disabled, disable DMAC */
2199 if (ec->rx_coalesce_usecs == 0) {
2200 if (adapter->flags & IGB_FLAG_DMAC)
2201 adapter->flags &= ~IGB_FLAG_DMAC;
2202 }
2203
9d5c8243 2204 /* convert to rate of irq's per second */
4fc82adf
AD		 2205 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2206 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2207 else
2208 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2209
2210 /* convert to rate of irq's per second */
2211 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2212 adapter->tx_itr_setting = adapter->rx_itr_setting;
2213 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2214 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2215 else
2216 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2217
047e0030
AD		 2218 for (i = 0; i < adapter->num_q_vectors; i++) {
2219 struct igb_q_vector *q_vector = adapter->q_vector[i];
0ba82994
AD		 2220 q_vector->tx.work_limit = adapter->tx_work_limit;
2221 if (q_vector->rx.ring)
4fc82adf
AD		 2222 q_vector->itr_val = adapter->rx_itr_setting;
2223 else
2224 q_vector->itr_val = adapter->tx_itr_setting;
2225 if (q_vector->itr_val && q_vector->itr_val <= 3)
2226 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2227 q_vector->set_itr = 1;
2228 }
9d5c8243
AK		 2229
2230 return 0;
2231}
2232
2233static int igb_get_coalesce(struct net_device *netdev,
2234 struct ethtool_coalesce *ec)
2235{
2236 struct igb_adapter *adapter = netdev_priv(netdev);
2237
4fc82adf
AD		 2238 if (adapter->rx_itr_setting <= 3)
2239 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2240 else
4fc82adf
AD		 2241 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2242
2243 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2244 if (adapter->tx_itr_setting <= 3)
2245 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2246 else
2247 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2248 }
9d5c8243
AK		 2249
2250 return 0;
2251}
2252
9d5c8243
AK		 2253static int igb_nway_reset(struct net_device *netdev)
2254{
2255 struct igb_adapter *adapter = netdev_priv(netdev);
2256 if (netif_running(netdev))
2257 igb_reinit_locked(adapter);
2258 return 0;
2259}
2260
2261static int igb_get_sset_count(struct net_device *netdev, int sset)
2262{
2263 switch (sset) {
2264 case ETH_SS_STATS:
2265 return IGB_STATS_LEN;
2266 case ETH_SS_TEST:
2267 return IGB_TEST_LEN;
2268 default:
2269 return -ENOTSUPP;
2270 }
2271}
2272
2273static void igb_get_ethtool_stats(struct net_device *netdev,
2274 struct ethtool_stats *stats, u64 *data)
2275{
2276 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2277 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2278 unsigned int start;
2279 struct igb_ring *ring;
2280 int i, j;
128e45eb 2281 char *p;
9d5c8243 2282
12dcd86b
ED		 2283 spin_lock(&adapter->stats64_lock);
2284 igb_update_stats(adapter, net_stats);
317f66bd 2285
9d5c8243 2286 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2287 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2288 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2289 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2290 }
128e45eb
AD		 2291 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2292 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2293 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2294 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2295 }
e21ed353 2296 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2297 u64 restart2;
2298
2299 ring = adapter->tx_ring[j];
2300 do {
57a7744e 2301 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 2302 data[i] = ring->tx_stats.packets;
2303 data[i+1] = ring->tx_stats.bytes;
2304 data[i+2] = ring->tx_stats.restart_queue;
57a7744e 2305 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b 2306 do {
57a7744e 2307 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
12dcd86b 2308 restart2 = ring->tx_stats.restart_queue2;
57a7744e 2309 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
12dcd86b
ED		 2310 data[i+2] += restart2;
2311
2312 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2313 }
9d5c8243 2314 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2315 ring = adapter->rx_ring[j];
2316 do {
57a7744e 2317 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 2318 data[i] = ring->rx_stats.packets;
2319 data[i+1] = ring->rx_stats.bytes;
2320 data[i+2] = ring->rx_stats.drops;
2321 data[i+3] = ring->rx_stats.csum_err;
2322 data[i+4] = ring->rx_stats.alloc_failed;
57a7744e 2323 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b 2324 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2325 }
12dcd86b 2326 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2327}
2328
2329static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2330{
2331 struct igb_adapter *adapter = netdev_priv(netdev);
2332 u8 *p = data;
2333 int i;
2334
2335 switch (stringset) {
2336 case ETH_SS_TEST:
2337 memcpy(data, *igb_gstrings_test,
2338 IGB_TEST_LEN*ETH_GSTRING_LEN);
2339 break;
2340 case ETH_SS_STATS:
2341 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2342 memcpy(p, igb_gstrings_stats[i].stat_string,
2343 ETH_GSTRING_LEN);
2344 p += ETH_GSTRING_LEN;
2345 }
128e45eb
AD		 2346 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2347 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2348 ETH_GSTRING_LEN);
2349 p += ETH_GSTRING_LEN;
2350 }
9d5c8243
AK		 2351 for (i = 0; i < adapter->num_tx_queues; i++) {
2352 sprintf(p, "tx_queue_%u_packets", i);
2353 p += ETH_GSTRING_LEN;
2354 sprintf(p, "tx_queue_%u_bytes", i);
2355 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2356 sprintf(p, "tx_queue_%u_restart", i);
2357 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2358 }
2359 for (i = 0; i < adapter->num_rx_queues; i++) {
2360 sprintf(p, "rx_queue_%u_packets", i);
2361 p += ETH_GSTRING_LEN;
2362 sprintf(p, "rx_queue_%u_bytes", i);
2363 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2364 sprintf(p, "rx_queue_%u_drops", i);
2365 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2366 sprintf(p, "rx_queue_%u_csum_err", i);
2367 p += ETH_GSTRING_LEN;
2368 sprintf(p, "rx_queue_%u_alloc_failed", i);
2369 p += ETH_GSTRING_LEN;
9d5c8243 2370 }
b980ac18 2371 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
9d5c8243
AK		 2372 break;
2373 }
2374}
2375
a79f4f88 2376static int igb_get_ts_info(struct net_device *dev,
a9188028 2377 struct ethtool_ts_info *info)
cb41145e
CW		 2378{
2379 struct igb_adapter *adapter = netdev_priv(dev);
2380
0f49da0e
KI		 2381 if (adapter->ptp_clock)
2382 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2383 else
2384 info->phc_index = -1;
2385
a9188028 2386 switch (adapter->hw.mac.type) {
b66e2397
MV		 2387 case e1000_82575:
2388 info->so_timestamping =
2389 SOF_TIMESTAMPING_TX_SOFTWARE |
2390 SOF_TIMESTAMPING_RX_SOFTWARE |
2391 SOF_TIMESTAMPING_SOFTWARE;
2392 return 0;
a9188028
MV		 2393 case e1000_82576:
2394 case e1000_82580:
2395 case e1000_i350:
ceb5f13b 2396 case e1000_i354:
a9188028
MV		 2397 case e1000_i210:
2398 case e1000_i211:
2399 info->so_timestamping =
b66e2397
MV		 2400 SOF_TIMESTAMPING_TX_SOFTWARE |
2401 SOF_TIMESTAMPING_RX_SOFTWARE |
2402 SOF_TIMESTAMPING_SOFTWARE |
a9188028
MV		 2403 SOF_TIMESTAMPING_TX_HARDWARE |
2404 SOF_TIMESTAMPING_RX_HARDWARE |
2405 SOF_TIMESTAMPING_RAW_HARDWARE;
cb41145e 2406
a9188028
MV		 2407 info->tx_types =
2408 (1 << HWTSTAMP_TX_OFF) |
2409 (1 << HWTSTAMP_TX_ON);
cb41145e 2410
a9188028 2411 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
cb41145e 2412
a9188028
MV		 2413 /* 82576 does not support timestamping all packets. */
2414 if (adapter->hw.mac.type >= e1000_82580)
2415 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2416 else
2417 info->rx_filters |=
2418 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2419 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
a9188028
MV		 2420 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2421
2422 return 0;
a9188028
MV		 2423 default:
2424 return -EOPNOTSUPP;
2425 }
2426}
cb41145e 2427
039454a8
AA		 2428static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2429 struct ethtool_rxnfc *cmd)
2430{
2431 cmd->data = 0;
2432
2433 /* Report default options for RSS on igb */
2434 switch (cmd->flow_type) {
2435 case TCP_V4_FLOW:
2436 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2437 /* Fall through */
039454a8
AA		 2438 case UDP_V4_FLOW:
2439 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2440 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2441 /* Fall through */
039454a8
AA		 2442 case SCTP_V4_FLOW:
2443 case AH_ESP_V4_FLOW:
2444 case AH_V4_FLOW:
2445 case ESP_V4_FLOW:
2446 case IPV4_FLOW:
2447 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2448 break;
2449 case TCP_V6_FLOW:
2450 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2451 /* Fall through */
039454a8
AA		 2452 case UDP_V6_FLOW:
2453 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2454 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2455 /* Fall through */
039454a8
AA		 2456 case SCTP_V6_FLOW:
2457 case AH_ESP_V6_FLOW:
2458 case AH_V6_FLOW:
2459 case ESP_V6_FLOW:
2460 case IPV6_FLOW:
2461 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2462 break;
2463 default:
2464 return -EINVAL;
2465 }
2466
2467 return 0;
2468}
2469
2470static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
b980ac18 2471 u32 *rule_locs)
039454a8
AA		 2472{
2473 struct igb_adapter *adapter = netdev_priv(dev);
2474 int ret = -EOPNOTSUPP;
2475
2476 switch (cmd->cmd) {
2477 case ETHTOOL_GRXRINGS:
2478 cmd->data = adapter->num_rx_queues;
2479 ret = 0;
2480 break;
2481 case ETHTOOL_GRXFH:
2482 ret = igb_get_rss_hash_opts(adapter, cmd);
2483 break;
2484 default:
2485 break;
2486 }
2487
2488 return ret;
2489}
2490
2491#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2492 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2493static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2494 struct ethtool_rxnfc *nfc)
2495{
2496 u32 flags = adapter->flags;
2497
2498 /* RSS does not support anything other than hashing
2499 * to queues on src and dst IPs and ports
2500 */
2501 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2502 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2503 return -EINVAL;
2504
2505 switch (nfc->flow_type) {
2506 case TCP_V4_FLOW:
2507 case TCP_V6_FLOW:
2508 if (!(nfc->data & RXH_IP_SRC) ||
2509 !(nfc->data & RXH_IP_DST) ||
2510 !(nfc->data & RXH_L4_B_0_1) ||
2511 !(nfc->data & RXH_L4_B_2_3))
2512 return -EINVAL;
2513 break;
2514 case UDP_V4_FLOW:
2515 if (!(nfc->data & RXH_IP_SRC) ||
2516 !(nfc->data & RXH_IP_DST))
2517 return -EINVAL;
2518 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2519 case 0:
2520 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2521 break;
2522 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2523 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2524 break;
2525 default:
2526 return -EINVAL;
2527 }
2528 break;
2529 case UDP_V6_FLOW:
2530 if (!(nfc->data & RXH_IP_SRC) ||
2531 !(nfc->data & RXH_IP_DST))
2532 return -EINVAL;
2533 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2534 case 0:
2535 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2536 break;
2537 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2538 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2539 break;
2540 default:
2541 return -EINVAL;
2542 }
2543 break;
2544 case AH_ESP_V4_FLOW:
2545 case AH_V4_FLOW:
2546 case ESP_V4_FLOW:
2547 case SCTP_V4_FLOW:
2548 case AH_ESP_V6_FLOW:
2549 case AH_V6_FLOW:
2550 case ESP_V6_FLOW:
2551 case SCTP_V6_FLOW:
2552 if (!(nfc->data & RXH_IP_SRC) ||
2553 !(nfc->data & RXH_IP_DST) ||
2554 (nfc->data & RXH_L4_B_0_1) ||
2555 (nfc->data & RXH_L4_B_2_3))
2556 return -EINVAL;
2557 break;
2558 default:
2559 return -EINVAL;
2560 }
2561
2562 /* if we changed something we need to update flags */
2563 if (flags != adapter->flags) {
2564 struct e1000_hw *hw = &adapter->hw;
2565 u32 mrqc = rd32(E1000_MRQC);
2566
2567 if ((flags & UDP_RSS_FLAGS) &&
2568 !(adapter->flags & UDP_RSS_FLAGS))
2569 dev_err(&adapter->pdev->dev,
2570 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2571
2572 adapter->flags = flags;
2573
2574 /* Perform hash on these packet types */
2575 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2576 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2577 E1000_MRQC_RSS_FIELD_IPV6 |
2578 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2579
2580 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2581 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2582
2583 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2584 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2585
2586 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2587 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2588
2589 wr32(E1000_MRQC, mrqc);
2590 }
2591
2592 return 0;
2593}
2594
2595static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2596{
2597 struct igb_adapter *adapter = netdev_priv(dev);
2598 int ret = -EOPNOTSUPP;
2599
2600 switch (cmd->cmd) {
2601 case ETHTOOL_SRXFH:
2602 ret = igb_set_rss_hash_opt(adapter, cmd);
2603 break;
2604 default:
2605 break;
2606 }
2607
2608 return ret;
2609}
2610
24a372cd
AA		 2611static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2612{
2613 struct igb_adapter *adapter = netdev_priv(netdev);
2614 struct e1000_hw *hw = &adapter->hw;
f4c01e96 2615 u32 ret_val;
87371b9d 2616 u16 phy_data;
24a372cd
AA		 2617
2618 if ((hw->mac.type < e1000_i350) ||
2619 (hw->phy.media_type != e1000_media_type_copper))
2620 return -EOPNOTSUPP;
2621
2622 edata->supported = (SUPPORTED_1000baseT_Full |
2623 SUPPORTED_100baseT_Full);
f4c01e96
CW		 2624 if (!hw->dev_spec._82575.eee_disable)
2625 edata->advertised =
2626 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
24a372cd 2627
f4c01e96
CW		 2628 /* The IPCNFG and EEER registers are not supported on I354. */
2629 if (hw->mac.type == e1000_i354) {
2630 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
2631 } else {
2632 u32 eeer;
2633
2634 eeer = rd32(E1000_EEER);
24a372cd 2635
f4c01e96
CW		 2636 /* EEE status on negotiated link */
2637 if (eeer & E1000_EEER_EEE_NEG)
2638 edata->eee_active = true;
24a372cd 2639
f4c01e96
CW		 2640 if (eeer & E1000_EEER_TX_LPI_EN)
2641 edata->tx_lpi_enabled = true;
2642 }
24a372cd 2643
87371b9d
MV		 2644 /* EEE Link Partner Advertised */
2645 switch (hw->mac.type) {
2646 case e1000_i350:
2647 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
2648 &phy_data);
2649 if (ret_val)
2650 return -ENODATA;
2651
2652 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
87371b9d 2653 break;
f4c01e96 2654 case e1000_i354:
87371b9d
MV		 2655 case e1000_i210:
2656 case e1000_i211:
2657 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
2658 E1000_EEE_LP_ADV_DEV_I210,
2659 &phy_data);
2660 if (ret_val)
2661 return -ENODATA;
2662
2663 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2664
2665 break;
2666 default:
2667 break;
2668 }
2669
24a372cd
AA		 2670 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2671
f4c01e96
CW		 2672 if ((hw->mac.type == e1000_i354) &&
2673 (edata->eee_enabled))
24a372cd
AA		 2674 edata->tx_lpi_enabled = true;
2675
2676 /* Report correct negotiated EEE status for devices that
2677 * wrongly report EEE at half-duplex
2678 */
2679 if (adapter->link_duplex == HALF_DUPLEX) {
2680 edata->eee_enabled = false;
2681 edata->eee_active = false;
2682 edata->tx_lpi_enabled = false;
2683 edata->advertised &= ~edata->advertised;
2684 }
2685
2686 return 0;
2687}
2688
2689static int igb_set_eee(struct net_device *netdev,
2690 struct ethtool_eee *edata)
2691{
2692 struct igb_adapter *adapter = netdev_priv(netdev);
2693 struct e1000_hw *hw = &adapter->hw;
2694 struct ethtool_eee eee_curr;
c4c112f1 2695 bool adv1g_eee = true, adv100m_eee = true;
24a372cd
AA		 2696 s32 ret_val;
2697
2698 if ((hw->mac.type < e1000_i350) ||
2699 (hw->phy.media_type != e1000_media_type_copper))
2700 return -EOPNOTSUPP;
2701
58e4e1f6
AK		 2702 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
2703
24a372cd
AA		 2704 ret_val = igb_get_eee(netdev, &eee_curr);
2705 if (ret_val)
2706 return ret_val;
2707
2708 if (eee_curr.eee_enabled) {
2709 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2710 dev_err(&adapter->pdev->dev,
2711 "Setting EEE tx-lpi is not supported\n");
2712 return -EINVAL;
2713 }
2714
2715 /* Tx LPI timer is not implemented currently */
2716 if (edata->tx_lpi_timer) {
2717 dev_err(&adapter->pdev->dev,
2718 "Setting EEE Tx LPI timer is not supported\n");
2719 return -EINVAL;
2720 }
2721
c4c112f1
TF		 2722 if (!edata->advertised || (edata->advertised &
2723 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
24a372cd 2724 dev_err(&adapter->pdev->dev,
c4c112f1 2725 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
24a372cd
AA		 2726 return -EINVAL;
2727 }
c4c112f1
TF		 2728 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
2729 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
24a372cd
AA		 2730
2731 } else if (!edata->eee_enabled) {
2732 dev_err(&adapter->pdev->dev,
2733 "Setting EEE options are not supported with EEE disabled\n");
2734 return -EINVAL;
2735 }
2736
f4c01e96 2737 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
24a372cd
AA		 2738 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2739 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
f4c01e96 2740 adapter->flags |= IGB_FLAG_EEE;
24a372cd
AA		 2741
2742 /* reset link */
8a650aa2
AA		 2743 if (netif_running(netdev))
2744 igb_reinit_locked(adapter);
2745 else
24a372cd
AA		 2746 igb_reset(adapter);
2747 }
2748
c4c112f1
TF		 2749 if (hw->mac.type == e1000_i354)
2750 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
2751 else
2752 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
2753
2754 if (ret_val) {
2755 dev_err(&adapter->pdev->dev,
2756 "Problem setting EEE advertisement options\n");
2757 return -EINVAL;
2758 }
2759
24a372cd
AA		 2760 return 0;
2761}
2762
f69aa390
AA		 2763static int igb_get_module_info(struct net_device *netdev,
2764 struct ethtool_modinfo *modinfo)
2765{
2766 struct igb_adapter *adapter = netdev_priv(netdev);
2767 struct e1000_hw *hw = &adapter->hw;
23d87824 2768 u32 status = 0;
f69aa390
AA		 2769 u16 sff8472_rev, addr_mode;
2770 bool page_swap = false;
2771
2772 if ((hw->phy.media_type == e1000_media_type_copper) ||
2773 (hw->phy.media_type == e1000_media_type_unknown))
2774 return -EOPNOTSUPP;
2775
2776 /* Check whether we support SFF-8472 or not */
2777 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
23d87824 2778 if (status)
f69aa390
AA		 2779 return -EIO;
2780
2781 /* addressing mode is not supported */
2782 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
23d87824 2783 if (status)
f69aa390
AA		 2784 return -EIO;
2785
2786 /* addressing mode is not supported */
2787 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2788 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2789 page_swap = true;
2790 }
2791
2792 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2793 /* We have an SFP, but it does not support SFF-8472 */
2794 modinfo->type = ETH_MODULE_SFF_8079;
2795 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2796 } else {
2797 /* We have an SFP which supports a revision of SFF-8472 */
2798 modinfo->type = ETH_MODULE_SFF_8472;
2799 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2800 }
2801
2802 return 0;
2803}
2804
2805static int igb_get_module_eeprom(struct net_device *netdev,
2806 struct ethtool_eeprom *ee, u8 *data)
2807{
2808 struct igb_adapter *adapter = netdev_priv(netdev);
2809 struct e1000_hw *hw = &adapter->hw;
23d87824 2810 u32 status = 0;
f69aa390
AA		 2811 u16 *dataword;
2812 u16 first_word, last_word;
2813 int i = 0;
2814
2815 if (ee->len == 0)
2816 return -EINVAL;
2817
2818 first_word = ee->offset >> 1;
2819 last_word = (ee->offset + ee->len - 1) >> 1;
2820
2821 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2822 GFP_KERNEL);
2823 if (!dataword)
2824 return -ENOMEM;
2825
2826 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2827 for (i = 0; i < last_word - first_word + 1; i++) {
2828 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
23d87824 2829 if (status) {
f69aa390 2830 /* Error occurred while reading module */
db41b87d 2831 kfree(dataword);
f69aa390 2832 return -EIO;
db41b87d 2833 }
f69aa390
AA		 2834
2835 be16_to_cpus(&dataword[i]);
2836 }
2837
2838 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2839 kfree(dataword);
2840
2841 return 0;
2842}
2843
a79f4f88
MV		 2844static int igb_ethtool_begin(struct net_device *netdev)
2845{
2846 struct igb_adapter *adapter = netdev_priv(netdev);
2847 pm_runtime_get_sync(&adapter->pdev->dev);
2848 return 0;
2849}
2850
2851static void igb_ethtool_complete(struct net_device *netdev)
2852{
2853 struct igb_adapter *adapter = netdev_priv(netdev);
2854 pm_runtime_put(&adapter->pdev->dev);
2855}
2856
ed12cc9a
LMV		 2857static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
2858{
2859 return IGB_RETA_SIZE;
2860}
2861
892311f6
EP		 2862static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
2863 u8 *hfunc)
ed12cc9a
LMV		 2864{
2865 struct igb_adapter *adapter = netdev_priv(netdev);
2866 int i;
2867
892311f6
EP		 2868 if (hfunc)
2869 *hfunc = ETH_RSS_HASH_TOP;
2870 if (!indir)
2871 return 0;
ed12cc9a
LMV		 2872 for (i = 0; i < IGB_RETA_SIZE; i++)
2873 indir[i] = adapter->rss_indir_tbl[i];
2874
2875 return 0;
2876}
2877
2878void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
2879{
2880 struct e1000_hw *hw = &adapter->hw;
2881 u32 reg = E1000_RETA(0);
2882 u32 shift = 0;
2883 int i = 0;
2884
2885 switch (hw->mac.type) {
2886 case e1000_82575:
2887 shift = 6;
2888 break;
2889 case e1000_82576:
2890 /* 82576 supports 2 RSS queues for SR-IOV */
2891 if (adapter->vfs_allocated_count)
2892 shift = 3;
2893 break;
2894 default:
2895 break;
2896 }
2897
2898 while (i < IGB_RETA_SIZE) {
2899 u32 val = 0;
2900 int j;
2901
2902 for (j = 3; j >= 0; j--) {
2903 val <<= 8;
2904 val |= adapter->rss_indir_tbl[i + j];
2905 }
2906
2907 wr32(reg, val << shift);
2908 reg += 4;
2909 i += 4;
2910 }
2911}
2912
fe62d001 2913static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
892311f6 2914 const u8 *key, const u8 hfunc)
ed12cc9a
LMV		 2915{
2916 struct igb_adapter *adapter = netdev_priv(netdev);
2917 struct e1000_hw *hw = &adapter->hw;
2918 int i;
2919 u32 num_queues;
2920
892311f6
EP		 2921 /* We do not allow change in unsupported parameters */
2922 if (key ||
2923 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
2924 return -EOPNOTSUPP;
2925 if (!indir)
2926 return 0;
2927
ed12cc9a
LMV		 2928 num_queues = adapter->rss_queues;
2929
2930 switch (hw->mac.type) {
2931 case e1000_82576:
2932 /* 82576 supports 2 RSS queues for SR-IOV */
2933 if (adapter->vfs_allocated_count)
2934 num_queues = 2;
2935 break;
2936 default:
2937 break;
2938 }
2939
2940 /* Verify user input. */
2941 for (i = 0; i < IGB_RETA_SIZE; i++)
2942 if (indir[i] >= num_queues)
2943 return -EINVAL;
2944
2945
2946 for (i = 0; i < IGB_RETA_SIZE; i++)
2947 adapter->rss_indir_tbl[i] = indir[i];
2948
2949 igb_write_rss_indir_tbl(adapter);
2950
2951 return 0;
2952}
2953
907b7835
LMV		 2954static unsigned int igb_max_channels(struct igb_adapter *adapter)
2955{
2956 struct e1000_hw *hw = &adapter->hw;
2957 unsigned int max_combined = 0;
2958
2959 switch (hw->mac.type) {
2960 case e1000_i211:
2961 max_combined = IGB_MAX_RX_QUEUES_I211;
2962 break;
2963 case e1000_82575:
2964 case e1000_i210:
2965 max_combined = IGB_MAX_RX_QUEUES_82575;
2966 break;
2967 case e1000_i350:
2968 if (!!adapter->vfs_allocated_count) {
2969 max_combined = 1;
2970 break;
2971 }
2972 /* fall through */
2973 case e1000_82576:
2974 if (!!adapter->vfs_allocated_count) {
2975 max_combined = 2;
2976 break;
2977 }
2978 /* fall through */
2979 case e1000_82580:
2980 case e1000_i354:
2981 default:
2982 max_combined = IGB_MAX_RX_QUEUES;
2983 break;
2984 }
2985
2986 return max_combined;
2987}
2988
2989static void igb_get_channels(struct net_device *netdev,
2990 struct ethtool_channels *ch)
2991{
2992 struct igb_adapter *adapter = netdev_priv(netdev);
2993
2994 /* Report maximum channels */
2995 ch->max_combined = igb_max_channels(adapter);
2996
2997 /* Report info for other vector */
cd14ef54 2998 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
907b7835
LMV		 2999 ch->max_other = NON_Q_VECTORS;
3000 ch->other_count = NON_Q_VECTORS;
3001 }
3002
3003 ch->combined_count = adapter->rss_queues;
3004}
3005
3006static int igb_set_channels(struct net_device *netdev,
3007 struct ethtool_channels *ch)
3008{
3009 struct igb_adapter *adapter = netdev_priv(netdev);
3010 unsigned int count = ch->combined_count;
72ddef05 3011 unsigned int max_combined = 0;
907b7835
LMV		 3012
3013 /* Verify they are not requesting separate vectors */
3014 if (!count || ch->rx_count || ch->tx_count)
3015 return -EINVAL;
3016
3017 /* Verify other_count is valid and has not been changed */
3018 if (ch->other_count != NON_Q_VECTORS)
3019 return -EINVAL;
3020
3021 /* Verify the number of channels doesn't exceed hw limits */
72ddef05
SS		 3022 max_combined = igb_max_channels(adapter);
3023 if (count > max_combined)
907b7835
LMV		 3024 return -EINVAL;
3025
3026 if (count != adapter->rss_queues) {
3027 adapter->rss_queues = count;
72ddef05 3028 igb_set_flag_queue_pairs(adapter, max_combined);
907b7835
LMV		 3029
3030 /* Hardware has to reinitialize queues and interrupts to
3031 * match the new configuration.
3032 */
3033 return igb_reinit_queues(adapter);
3034 }
3035
3036 return 0;
3037}
3038
0fc0b732 3039static const struct ethtool_ops igb_ethtool_ops = {
b980ac18
JK		 3040 .get_settings = igb_get_settings,
3041 .set_settings = igb_set_settings,
3042 .get_drvinfo = igb_get_drvinfo,
3043 .get_regs_len = igb_get_regs_len,
3044 .get_regs = igb_get_regs,
3045 .get_wol = igb_get_wol,
3046 .set_wol = igb_set_wol,
3047 .get_msglevel = igb_get_msglevel,
3048 .set_msglevel = igb_set_msglevel,
3049 .nway_reset = igb_nway_reset,
3050 .get_link = igb_get_link,
3051 .get_eeprom_len = igb_get_eeprom_len,
3052 .get_eeprom = igb_get_eeprom,
3053 .set_eeprom = igb_set_eeprom,
3054 .get_ringparam = igb_get_ringparam,
3055 .set_ringparam = igb_set_ringparam,
3056 .get_pauseparam = igb_get_pauseparam,
3057 .set_pauseparam = igb_set_pauseparam,
3058 .self_test = igb_diag_test,
3059 .get_strings = igb_get_strings,
3060 .set_phys_id = igb_set_phys_id,
3061 .get_sset_count = igb_get_sset_count,
3062 .get_ethtool_stats = igb_get_ethtool_stats,
3063 .get_coalesce = igb_get_coalesce,
3064 .set_coalesce = igb_set_coalesce,
3065 .get_ts_info = igb_get_ts_info,
039454a8
AA		 3066 .get_rxnfc = igb_get_rxnfc,
3067 .set_rxnfc = igb_set_rxnfc,
24a372cd
AA		 3068 .get_eee = igb_get_eee,
3069 .set_eee = igb_set_eee,
f69aa390
AA		 3070 .get_module_info = igb_get_module_info,
3071 .get_module_eeprom = igb_get_module_eeprom,
ed12cc9a 3072 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
fe62d001
BH		 3073 .get_rxfh = igb_get_rxfh,
3074 .set_rxfh = igb_set_rxfh,
907b7835
LMV		 3075 .get_channels = igb_get_channels,
3076 .set_channels = igb_set_channels,
a79f4f88
MV		 3077 .begin = igb_ethtool_begin,
3078 .complete = igb_ethtool_complete,
9d5c8243
AK		 3079};
3080
3081void igb_set_ethtool_ops(struct net_device *netdev)
3082{
7ad24ea4 3083 netdev->ethtool_ops = &igb_ethtool_ops;
9d5c8243 3084}
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