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igb: Add timeout for PTP Tx work item
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
200e5fd5 63#define MAJ 4
6699938b
CW		 64#define MIN 1
65#define BUILD 2
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 72static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 73
9d5c8243
AK		 74static const struct e1000_info *igb_info_tbl[] = {
75 [board_82575] = &e1000_82575_info,
76};
77
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
109 /* required last entry */
110 {0, }
111};
112
113MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
114
115void igb_reset(struct igb_adapter *);
116static int igb_setup_all_tx_resources(struct igb_adapter *);
117static int igb_setup_all_rx_resources(struct igb_adapter *);
118static void igb_free_all_tx_resources(struct igb_adapter *);
119static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 120static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 121static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 122static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 123static int igb_sw_init(struct igb_adapter *);
124static int igb_open(struct net_device *);
125static int igb_close(struct net_device *);
53c7d064 126static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 127static void igb_configure_tx(struct igb_adapter *);
128static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 129static void igb_clean_all_tx_rings(struct igb_adapter *);
130static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 131static void igb_clean_tx_ring(struct igb_ring *);
132static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 133static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 134static void igb_update_phy_info(unsigned long);
135static void igb_watchdog(unsigned long);
136static void igb_watchdog_task(struct work_struct *);
cd392f5c 137static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 138static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
139 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 140static int igb_change_mtu(struct net_device *, int);
141static int igb_set_mac(struct net_device *, void *);
68d480c4 142static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 143static irqreturn_t igb_intr(int irq, void *);
144static irqreturn_t igb_intr_msi(int irq, void *);
145static irqreturn_t igb_msix_other(int irq, void *);
047e0030 146static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 147#ifdef CONFIG_IGB_DCA
047e0030 148static void igb_update_dca(struct igb_q_vector *);
fe4506b6 149static void igb_setup_dca(struct igb_adapter *);
421e02f0 150#endif /* CONFIG_IGB_DCA */
661086df 151static int igb_poll(struct napi_struct *, int);
13fde97a 152static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 153static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 154static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
155static void igb_tx_timeout(struct net_device *);
156static void igb_reset_task(struct work_struct *);
c8f44aff 157static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 158static int igb_vlan_rx_add_vid(struct net_device *, u16);
159static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 160static void igb_restore_vlan(struct igb_adapter *);
26ad9178 161static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 162static void igb_ping_all_vfs(struct igb_adapter *);
163static void igb_msg_task(struct igb_adapter *);
4ae196df 164static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 165static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 166static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 167static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
168static int igb_ndo_set_vf_vlan(struct net_device *netdev,
169 int vf, u16 vlan, u8 qos);
170static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
171static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
172 struct ifla_vf_info *ivi);
17dc566c 173static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 174
175#ifdef CONFIG_PCI_IOV
0224d663 176static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 177static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 178#endif
9d5c8243 179
9d5c8243 180#ifdef CONFIG_PM
d9dd966d 181#ifdef CONFIG_PM_SLEEP
749ab2cd 182static int igb_suspend(struct device *);
d9dd966d 183#endif
749ab2cd
YZ		 184static int igb_resume(struct device *);
185#ifdef CONFIG_PM_RUNTIME
186static int igb_runtime_suspend(struct device *dev);
187static int igb_runtime_resume(struct device *dev);
188static int igb_runtime_idle(struct device *dev);
189#endif
190static const struct dev_pm_ops igb_pm_ops = {
191 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
192 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
193 igb_runtime_idle)
194};
9d5c8243
AK		 195#endif
196static void igb_shutdown(struct pci_dev *);
fa44f2f1 197static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 198#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 199static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
200static struct notifier_block dca_notifier = {
201 .notifier_call = igb_notify_dca,
202 .next = NULL,
203 .priority = 0
204};
205#endif
9d5c8243
AK		 206#ifdef CONFIG_NET_POLL_CONTROLLER
207/* for netdump / net console */
208static void igb_netpoll(struct net_device *);
209#endif
37680117 210#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 211static unsigned int max_vfs = 0;
212module_param(max_vfs, uint, 0);
213MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
214 "per physical function");
215#endif /* CONFIG_PCI_IOV */
216
9d5c8243
AK		 217static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
218 pci_channel_state_t);
219static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
220static void igb_io_resume(struct pci_dev *);
221
3646f0e5 222static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 223 .error_detected = igb_io_error_detected,
224 .slot_reset = igb_io_slot_reset,
225 .resume = igb_io_resume,
226};
227
b6e0c419 228static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 229
230static struct pci_driver igb_driver = {
231 .name = igb_driver_name,
232 .id_table = igb_pci_tbl,
233 .probe = igb_probe,
9f9a12f8 234 .remove = igb_remove,
9d5c8243 235#ifdef CONFIG_PM
749ab2cd 236 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 237#endif
238 .shutdown = igb_shutdown,
fa44f2f1 239 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 240 .err_handler = &igb_err_handler
241};
242
243MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
244MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
245MODULE_LICENSE("GPL");
246MODULE_VERSION(DRV_VERSION);
247
b3f4d599 248#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
249static int debug = -1;
250module_param(debug, int, 0);
251MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
252
c97ec42a
TI		 253struct igb_reg_info {
254 u32 ofs;
255 char *name;
256};
257
258static const struct igb_reg_info igb_reg_info_tbl[] = {
259
260 /* General Registers */
261 {E1000_CTRL, "CTRL"},
262 {E1000_STATUS, "STATUS"},
263 {E1000_CTRL_EXT, "CTRL_EXT"},
264
265 /* Interrupt Registers */
266 {E1000_ICR, "ICR"},
267
268 /* RX Registers */
269 {E1000_RCTL, "RCTL"},
270 {E1000_RDLEN(0), "RDLEN"},
271 {E1000_RDH(0), "RDH"},
272 {E1000_RDT(0), "RDT"},
273 {E1000_RXDCTL(0), "RXDCTL"},
274 {E1000_RDBAL(0), "RDBAL"},
275 {E1000_RDBAH(0), "RDBAH"},
276
277 /* TX Registers */
278 {E1000_TCTL, "TCTL"},
279 {E1000_TDBAL(0), "TDBAL"},
280 {E1000_TDBAH(0), "TDBAH"},
281 {E1000_TDLEN(0), "TDLEN"},
282 {E1000_TDH(0), "TDH"},
283 {E1000_TDT(0), "TDT"},
284 {E1000_TXDCTL(0), "TXDCTL"},
285 {E1000_TDFH, "TDFH"},
286 {E1000_TDFT, "TDFT"},
287 {E1000_TDFHS, "TDFHS"},
288 {E1000_TDFPC, "TDFPC"},
289
290 /* List Terminator */
291 {}
292};
293
294/*
295 * igb_regdump - register printout routine
296 */
297static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
298{
299 int n = 0;
300 char rname[16];
301 u32 regs[8];
302
303 switch (reginfo->ofs) {
304 case E1000_RDLEN(0):
305 for (n = 0; n < 4; n++)
306 regs[n] = rd32(E1000_RDLEN(n));
307 break;
308 case E1000_RDH(0):
309 for (n = 0; n < 4; n++)
310 regs[n] = rd32(E1000_RDH(n));
311 break;
312 case E1000_RDT(0):
313 for (n = 0; n < 4; n++)
314 regs[n] = rd32(E1000_RDT(n));
315 break;
316 case E1000_RXDCTL(0):
317 for (n = 0; n < 4; n++)
318 regs[n] = rd32(E1000_RXDCTL(n));
319 break;
320 case E1000_RDBAL(0):
321 for (n = 0; n < 4; n++)
322 regs[n] = rd32(E1000_RDBAL(n));
323 break;
324 case E1000_RDBAH(0):
325 for (n = 0; n < 4; n++)
326 regs[n] = rd32(E1000_RDBAH(n));
327 break;
328 case E1000_TDBAL(0):
329 for (n = 0; n < 4; n++)
330 regs[n] = rd32(E1000_RDBAL(n));
331 break;
332 case E1000_TDBAH(0):
333 for (n = 0; n < 4; n++)
334 regs[n] = rd32(E1000_TDBAH(n));
335 break;
336 case E1000_TDLEN(0):
337 for (n = 0; n < 4; n++)
338 regs[n] = rd32(E1000_TDLEN(n));
339 break;
340 case E1000_TDH(0):
341 for (n = 0; n < 4; n++)
342 regs[n] = rd32(E1000_TDH(n));
343 break;
344 case E1000_TDT(0):
345 for (n = 0; n < 4; n++)
346 regs[n] = rd32(E1000_TDT(n));
347 break;
348 case E1000_TXDCTL(0):
349 for (n = 0; n < 4; n++)
350 regs[n] = rd32(E1000_TXDCTL(n));
351 break;
352 default:
876d2d6f 353 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 354 return;
355 }
356
357 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 358 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
359 regs[2], regs[3]);
c97ec42a
TI		 360}
361
362/*
363 * igb_dump - Print registers, tx-rings and rx-rings
364 */
365static void igb_dump(struct igb_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 struct e1000_hw *hw = &adapter->hw;
369 struct igb_reg_info *reginfo;
c97ec42a
TI		 370 struct igb_ring *tx_ring;
371 union e1000_adv_tx_desc *tx_desc;
372 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 373 struct igb_ring *rx_ring;
374 union e1000_adv_rx_desc *rx_desc;
375 u32 staterr;
6ad4edfc 376 u16 i, n;
c97ec42a
TI		 377
378 if (!netif_msg_hw(adapter))
379 return;
380
381 /* Print netdevice Info */
382 if (netdev) {
383 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 384 pr_info("Device Name state trans_start "
385 "last_rx\n");
386 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
387 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 388 }
389
390 /* Print Registers */
391 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 392 pr_info(" Register Name Value\n");
c97ec42a
TI		 393 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
394 reginfo->name; reginfo++) {
395 igb_regdump(hw, reginfo);
396 }
397
398 /* Print TX Ring Summary */
399 if (!netdev || !netif_running(netdev))
400 goto exit;
401
402 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 403 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 404 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 405 struct igb_tx_buffer *buffer_info;
c97ec42a 406 tx_ring = adapter->tx_ring[n];
06034649 407 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 408 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
409 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 410 (u64)dma_unmap_addr(buffer_info, dma),
411 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 412 buffer_info->next_to_watch,
413 (u64)buffer_info->time_stamp);
c97ec42a
TI		 414 }
415
416 /* Print TX Rings */
417 if (!netif_msg_tx_done(adapter))
418 goto rx_ring_summary;
419
420 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
421
422 /* Transmit Descriptor Formats
423 *
424 * Advanced Transmit Descriptor
425 * +--------------------------------------------------------------+
426 * 0 | Buffer Address [63:0] |
427 * +--------------------------------------------------------------+
428 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
429 * +--------------------------------------------------------------+
430 * 63 46 45 40 39 38 36 35 32 31 24 15 0
431 */
432
433 for (n = 0; n < adapter->num_tx_queues; n++) {
434 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 435 pr_info("------------------------------------\n");
436 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
437 pr_info("------------------------------------\n");
438 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
439 "[bi->dma ] leng ntw timestamp "
440 "bi->skb\n");
c97ec42a
TI		 441
442 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 443 const char *next_desc;
06034649 444 struct igb_tx_buffer *buffer_info;
60136906 445 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 446 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 447 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 448 if (i == tx_ring->next_to_use &&
449 i == tx_ring->next_to_clean)
450 next_desc = " NTC/U";
451 else if (i == tx_ring->next_to_use)
452 next_desc = " NTU";
453 else if (i == tx_ring->next_to_clean)
454 next_desc = " NTC";
455 else
456 next_desc = "";
457
458 pr_info("T [0x%03X] %016llX %016llX %016llX"
459 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 460 le64_to_cpu(u0->a),
461 le64_to_cpu(u0->b),
c9f14bf3
AD		 462 (u64)dma_unmap_addr(buffer_info, dma),
463 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 464 buffer_info->next_to_watch,
465 (u64)buffer_info->time_stamp,
876d2d6f 466 buffer_info->skb, next_desc);
c97ec42a 467
b669588a 468 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS,
b669588a 471 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 472 dma_unmap_len(buffer_info, len),
473 true);
c97ec42a
TI		 474 }
475 }
476
477 /* Print RX Rings Summary */
478rx_ring_summary:
479 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 480 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 481 for (n = 0; n < adapter->num_rx_queues; n++) {
482 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 483 pr_info(" %5d %5X %5X\n",
484 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 485 }
486
487 /* Print RX Rings */
488 if (!netif_msg_rx_status(adapter))
489 goto exit;
490
491 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
492
493 /* Advanced Receive Descriptor (Read) Format
494 * 63 1 0
495 * +-----------------------------------------------------+
496 * 0 | Packet Buffer Address [63:1] |A0/NSE|
497 * +----------------------------------------------+------+
498 * 8 | Header Buffer Address [63:1] | DD |
499 * +-----------------------------------------------------+
500 *
501 *
502 * Advanced Receive Descriptor (Write-Back) Format
503 *
504 * 63 48 47 32 31 30 21 20 17 16 4 3 0
505 * +------------------------------------------------------+
506 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
507 * | Checksum Ident | | | | Type | Type |
508 * +------------------------------------------------------+
509 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
510 * +------------------------------------------------------+
511 * 63 48 47 32 31 20 19 0
512 */
513
514 for (n = 0; n < adapter->num_rx_queues; n++) {
515 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 516 pr_info("------------------------------------\n");
517 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
518 pr_info("------------------------------------\n");
519 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
520 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
521 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
522 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 523
524 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 525 const char *next_desc;
06034649
AD		 526 struct igb_rx_buffer *buffer_info;
527 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 528 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 529 u0 = (struct my_u0 *)rx_desc;
530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 531
532 if (i == rx_ring->next_to_use)
533 next_desc = " NTU";
534 else if (i == rx_ring->next_to_clean)
535 next_desc = " NTC";
536 else
537 next_desc = "";
538
c97ec42a
TI		 539 if (staterr & E1000_RXD_STAT_DD) {
540 /* Descriptor Done */
1a1c225b
AD		 541 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
542 "RWB", i,
c97ec42a
TI		 543 le64_to_cpu(u0->a),
544 le64_to_cpu(u0->b),
1a1c225b 545 next_desc);
c97ec42a 546 } else {
1a1c225b
AD		 547 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
548 "R ", i,
c97ec42a
TI		 549 le64_to_cpu(u0->a),
550 le64_to_cpu(u0->b),
551 (u64)buffer_info->dma,
1a1c225b 552 next_desc);
c97ec42a 553
b669588a 554 if (netif_msg_pktdata(adapter) &&
1a1c225b 555 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 556 print_hex_dump(KERN_INFO, "",
557 DUMP_PREFIX_ADDRESS,
558 16, 1,
b669588a
ET		 559 page_address(buffer_info->page) +
560 buffer_info->page_offset,
de78d1f9 561 IGB_RX_BUFSZ, true);
c97ec42a
TI		 562 }
563 }
c97ec42a
TI		 564 }
565 }
566
567exit:
568 return;
569}
570
441fc6fd
CW		 571/* igb_get_i2c_data - Reads the I2C SDA data bit
572 * @hw: pointer to hardware structure
573 * @i2cctl: Current value of I2CCTL register
574 *
575 * Returns the I2C data bit value
576 */
577static int igb_get_i2c_data(void *data)
578{
579 struct igb_adapter *adapter = (struct igb_adapter *)data;
580 struct e1000_hw *hw = &adapter->hw;
581 s32 i2cctl = rd32(E1000_I2CPARAMS);
582
583 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
584}
585
586/* igb_set_i2c_data - Sets the I2C data bit
587 * @data: pointer to hardware structure
588 * @state: I2C data value (0 or 1) to set
589 *
590 * Sets the I2C data bit
591 */
592static void igb_set_i2c_data(void *data, int state)
593{
594 struct igb_adapter *adapter = (struct igb_adapter *)data;
595 struct e1000_hw *hw = &adapter->hw;
596 s32 i2cctl = rd32(E1000_I2CPARAMS);
597
598 if (state)
599 i2cctl |= E1000_I2C_DATA_OUT;
600 else
601 i2cctl &= ~E1000_I2C_DATA_OUT;
602
603 i2cctl &= ~E1000_I2C_DATA_OE_N;
604 i2cctl |= E1000_I2C_CLK_OE_N;
605 wr32(E1000_I2CPARAMS, i2cctl);
606 wrfl();
607
608}
609
610/* igb_set_i2c_clk - Sets the I2C SCL clock
611 * @data: pointer to hardware structure
612 * @state: state to set clock
613 *
614 * Sets the I2C clock line to state
615 */
616static void igb_set_i2c_clk(void *data, int state)
617{
618 struct igb_adapter *adapter = (struct igb_adapter *)data;
619 struct e1000_hw *hw = &adapter->hw;
620 s32 i2cctl = rd32(E1000_I2CPARAMS);
621
622 if (state) {
623 i2cctl |= E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 } else {
626 i2cctl &= ~E1000_I2C_CLK_OUT;
627 i2cctl &= ~E1000_I2C_CLK_OE_N;
628 }
629 wr32(E1000_I2CPARAMS, i2cctl);
630 wrfl();
631}
632
633/* igb_get_i2c_clk - Gets the I2C SCL clock state
634 * @data: pointer to hardware structure
635 *
636 * Gets the I2C clock state
637 */
638static int igb_get_i2c_clk(void *data)
639{
640 struct igb_adapter *adapter = (struct igb_adapter *)data;
641 struct e1000_hw *hw = &adapter->hw;
642 s32 i2cctl = rd32(E1000_I2CPARAMS);
643
644 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
645}
646
647static const struct i2c_algo_bit_data igb_i2c_algo = {
648 .setsda = igb_set_i2c_data,
649 .setscl = igb_set_i2c_clk,
650 .getsda = igb_get_i2c_data,
651 .getscl = igb_get_i2c_clk,
652 .udelay = 5,
653 .timeout = 20,
654};
655
9d5c8243 656/**
c041076a 657 * igb_get_hw_dev - return device
9d5c8243
AK		 658 * used by hardware layer to print debugging information
659 **/
c041076a 660struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 661{
662 struct igb_adapter *adapter = hw->back;
c041076a 663 return adapter->netdev;
9d5c8243 664}
38c845c7 665
9d5c8243
AK		 666/**
667 * igb_init_module - Driver Registration Routine
668 *
669 * igb_init_module is the first routine called when the driver is
670 * loaded. All it does is register with the PCI subsystem.
671 **/
672static int __init igb_init_module(void)
673{
674 int ret;
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243
AK		 676 igb_driver_string, igb_driver_version);
677
876d2d6f 678 pr_info("%s\n", igb_copyright);
9d5c8243 679
421e02f0 680#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 681 dca_register_notify(&dca_notifier);
682#endif
bbd98fe4 683 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 684 return ret;
685}
686
687module_init(igb_init_module);
688
689/**
690 * igb_exit_module - Driver Exit Cleanup Routine
691 *
692 * igb_exit_module is called just before the driver is removed
693 * from memory.
694 **/
695static void __exit igb_exit_module(void)
696{
421e02f0 697#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 698 dca_unregister_notify(&dca_notifier);
699#endif
9d5c8243
AK		 700 pci_unregister_driver(&igb_driver);
701}
702
703module_exit(igb_exit_module);
704
26bc19ec
AD		 705#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706/**
707 * igb_cache_ring_register - Descriptor ring to register mapping
708 * @adapter: board private structure to initialize
709 *
710 * Once we know the feature-set enabled for the device, we'll cache
711 * the register offset the descriptor ring is assigned to.
712 **/
713static void igb_cache_ring_register(struct igb_adapter *adapter)
714{
ee1b9f06 715 int i = 0, j = 0;
047e0030 716 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 717
718 switch (adapter->hw.mac.type) {
719 case e1000_82576:
720 /* The queues are allocated for virtualization such that VF 0
721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
722 * In order to avoid collision we start at the first free queue
723 * and continue consuming queues in the same sequence
724 */
ee1b9f06 725 if (adapter->vfs_allocated_count) {
a99955fc 726 for (; i < adapter->rss_queues; i++)
3025a446
AD		 727 adapter->rx_ring[i]->reg_idx = rbase_offset +
728 Q_IDX_82576(i);
ee1b9f06 729 }
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
f96a8a0b
CW		 733 case e1000_i210:
734 case e1000_i211:
26bc19ec 735 default:
ee1b9f06 736 for (; i < adapter->num_rx_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 738 for (; j < adapter->num_tx_queues; j++)
3025a446 739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 740 break;
741 }
742}
743
4be000c8
AD		 744/**
745 * igb_write_ivar - configure ivar for given MSI-X vector
746 * @hw: pointer to the HW structure
747 * @msix_vector: vector number we are allocating to a given ring
748 * @index: row index of IVAR register to write within IVAR table
749 * @offset: column offset of in IVAR, should be multiple of 8
750 *
751 * This function is intended to handle the writing of the IVAR register
752 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
753 * each containing an cause allocation for an Rx and Tx ring, and a
754 * variable number of rows depending on the number of queues supported.
755 **/
756static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
757 int index, int offset)
758{
759 u32 ivar = array_rd32(E1000_IVAR0, index);
760
761 /* clear any bits that are currently set */
762 ivar &= ~((u32)0xFF << offset);
763
764 /* write vector and valid bit */
765 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
766
767 array_wr32(E1000_IVAR0, index, ivar);
768}
769
9d5c8243 770#define IGB_N0_QUEUE -1
047e0030 771static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 772{
047e0030 773 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 774 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 775 int rx_queue = IGB_N0_QUEUE;
776 int tx_queue = IGB_N0_QUEUE;
4be000c8 777 u32 msixbm = 0;
047e0030 778
0ba82994
AD		 779 if (q_vector->rx.ring)
780 rx_queue = q_vector->rx.ring->reg_idx;
781 if (q_vector->tx.ring)
782 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 783
784 switch (hw->mac.type) {
785 case e1000_82575:
9d5c8243
AK		 786 /* The 82575 assigns vectors using a bitmask, which matches the
787 bitmask for the EICR/EIMS/EIMC registers. To assign one
788 or more queues to a vector, we write the appropriate bits
789 into the MSIXBM register for that vector. */
047e0030 790 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 791 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 792 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 793 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 794 if (!adapter->msix_entries && msix_vector == 0)
795 msixbm |= E1000_EIMS_OTHER;
9d5c8243 796 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 797 q_vector->eims_value = msixbm;
2d064c06
AD		 798 break;
799 case e1000_82576:
4be000c8
AD		 800 /*
801 * 82576 uses a table that essentially consists of 2 columns
802 * with 8 rows. The ordering is column-major so we use the
803 * lower 3 bits as the row index, and the 4th bit as the
804 * column offset.
805 */
806 if (rx_queue > IGB_N0_QUEUE)
807 igb_write_ivar(hw, msix_vector,
808 rx_queue & 0x7,
809 (rx_queue & 0x8) << 1);
810 if (tx_queue > IGB_N0_QUEUE)
811 igb_write_ivar(hw, msix_vector,
812 tx_queue & 0x7,
813 ((tx_queue & 0x8) << 1) + 8);
047e0030 814 q_vector->eims_value = 1 << msix_vector;
2d064c06 815 break;
55cac248 816 case e1000_82580:
d2ba2ed8 817 case e1000_i350:
f96a8a0b
CW		 818 case e1000_i210:
819 case e1000_i211:
4be000c8
AD		 820 /*
821 * On 82580 and newer adapters the scheme is similar to 82576
822 * however instead of ordering column-major we have things
823 * ordered row-major. So we traverse the table by using
824 * bit 0 as the column offset, and the remaining bits as the
825 * row index.
826 */
827 if (rx_queue > IGB_N0_QUEUE)
828 igb_write_ivar(hw, msix_vector,
829 rx_queue >> 1,
830 (rx_queue & 0x1) << 4);
831 if (tx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 tx_queue >> 1,
834 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 835 q_vector->eims_value = 1 << msix_vector;
836 break;
2d064c06
AD		 837 default:
838 BUG();
839 break;
840 }
26b39276
AD		 841
842 /* add q_vector eims value to global eims_enable_mask */
843 adapter->eims_enable_mask |= q_vector->eims_value;
844
845 /* configure q_vector to set itr on first interrupt */
846 q_vector->set_itr = 1;
9d5c8243
AK		 847}
848
849/**
850 * igb_configure_msix - Configure MSI-X hardware
851 *
852 * igb_configure_msix sets up the hardware to properly
853 * generate MSI-X interrupts.
854 **/
855static void igb_configure_msix(struct igb_adapter *adapter)
856{
857 u32 tmp;
858 int i, vector = 0;
859 struct e1000_hw *hw = &adapter->hw;
860
861 adapter->eims_enable_mask = 0;
9d5c8243
AK		 862
863 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 864 switch (hw->mac.type) {
865 case e1000_82575:
9d5c8243
AK		 866 tmp = rd32(E1000_CTRL_EXT);
867 /* enable MSI-X PBA support*/
868 tmp |= E1000_CTRL_EXT_PBA_CLR;
869
870 /* Auto-Mask interrupts upon ICR read. */
871 tmp |= E1000_CTRL_EXT_EIAME;
872 tmp |= E1000_CTRL_EXT_IRCA;
873
874 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 875
876 /* enable msix_other interrupt */
877 array_wr32(E1000_MSIXBM(0), vector++,
878 E1000_EIMS_OTHER);
844290e5 879 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 880
2d064c06
AD		 881 break;
882
883 case e1000_82576:
55cac248 884 case e1000_82580:
d2ba2ed8 885 case e1000_i350:
f96a8a0b
CW		 886 case e1000_i210:
887 case e1000_i211:
047e0030
AD		 888 /* Turn on MSI-X capability first, or our settings
889 * won't stick. And it will take days to debug. */
890 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
891 E1000_GPIE_PBA | E1000_GPIE_EIAME |
892 E1000_GPIE_NSICR);
893
894 /* enable msix_other interrupt */
895 adapter->eims_other = 1 << vector;
2d064c06 896 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 897
047e0030 898 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 899 break;
900 default:
901 /* do nothing, since nothing else supports MSI-X */
902 break;
903 } /* switch (hw->mac.type) */
047e0030
AD		 904
905 adapter->eims_enable_mask |= adapter->eims_other;
906
26b39276
AD		 907 for (i = 0; i < adapter->num_q_vectors; i++)
908 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 909
9d5c8243
AK		 910 wrfl();
911}
912
913/**
914 * igb_request_msix - Initialize MSI-X interrupts
915 *
916 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
917 * kernel.
918 **/
919static int igb_request_msix(struct igb_adapter *adapter)
920{
921 struct net_device *netdev = adapter->netdev;
047e0030 922 struct e1000_hw *hw = &adapter->hw;
52285b76 923 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 924
047e0030 925 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 926 igb_msix_other, 0, netdev->name, adapter);
047e0030 927 if (err)
52285b76 928 goto err_out;
047e0030
AD		 929
930 for (i = 0; i < adapter->num_q_vectors; i++) {
931 struct igb_q_vector *q_vector = adapter->q_vector[i];
932
52285b76
SA		 933 vector++;
934
047e0030
AD		 935 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
936
0ba82994 937 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 938 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 939 q_vector->rx.ring->queue_index);
940 else if (q_vector->tx.ring)
047e0030 941 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 942 q_vector->tx.ring->queue_index);
943 else if (q_vector->rx.ring)
047e0030 944 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 945 q_vector->rx.ring->queue_index);
9d5c8243 946 else
047e0030
AD		 947 sprintf(q_vector->name, "%s-unused", netdev->name);
948
9d5c8243 949 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 950 igb_msix_ring, 0, q_vector->name,
047e0030 951 q_vector);
9d5c8243 952 if (err)
52285b76 953 goto err_free;
9d5c8243
AK		 954 }
955
9d5c8243
AK		 956 igb_configure_msix(adapter);
957 return 0;
52285b76
SA		 958
959err_free:
960 /* free already assigned IRQs */
961 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
962
963 vector--;
964 for (i = 0; i < vector; i++) {
965 free_irq(adapter->msix_entries[free_vector++].vector,
966 adapter->q_vector[i]);
967 }
968err_out:
9d5c8243
AK		 969 return err;
970}
971
972static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
973{
974 if (adapter->msix_entries) {
975 pci_disable_msix(adapter->pdev);
976 kfree(adapter->msix_entries);
977 adapter->msix_entries = NULL;
047e0030 978 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 979 pci_disable_msi(adapter->pdev);
047e0030 980 }
9d5c8243
AK		 981}
982
5536d210
AD		 983/**
984 * igb_free_q_vector - Free memory allocated for specific interrupt vector
985 * @adapter: board private structure to initialize
986 * @v_idx: Index of vector to be freed
987 *
988 * This function frees the memory allocated to the q_vector. In addition if
989 * NAPI is enabled it will delete any references to the NAPI struct prior
990 * to freeing the q_vector.
991 **/
992static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
993{
994 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
995
996 if (q_vector->tx.ring)
997 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
998
999 if (q_vector->rx.ring)
1000 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1001
1002 adapter->q_vector[v_idx] = NULL;
1003 netif_napi_del(&q_vector->napi);
1004
1005 /*
1006 * ixgbe_get_stats64() might access the rings on this vector,
1007 * we must wait a grace period before freeing it.
1008 */
1009 kfree_rcu(q_vector, rcu);
1010}
1011
047e0030
AD		 1012/**
1013 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1014 * @adapter: board private structure to initialize
1015 *
1016 * This function frees the memory allocated to the q_vectors. In addition if
1017 * NAPI is enabled it will delete any references to the NAPI struct prior
1018 * to freeing the q_vector.
1019 **/
1020static void igb_free_q_vectors(struct igb_adapter *adapter)
1021{
5536d210
AD		 1022 int v_idx = adapter->num_q_vectors;
1023
1024 adapter->num_tx_queues = 0;
1025 adapter->num_rx_queues = 0;
047e0030 1026 adapter->num_q_vectors = 0;
5536d210
AD		 1027
1028 while (v_idx--)
1029 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1030}
1031
1032/**
1033 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1034 *
1035 * This function resets the device so that it has 0 rx queues, tx queues, and
1036 * MSI-X interrupts allocated.
1037 */
1038static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1039{
047e0030
AD		 1040 igb_free_q_vectors(adapter);
1041 igb_reset_interrupt_capability(adapter);
1042}
9d5c8243
AK		 1043
1044/**
1045 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1046 *
1047 * Attempt to configure interrupts using the best available
1048 * capabilities of the hardware and kernel.
1049 **/
53c7d064 1050static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1051{
1052 int err;
1053 int numvecs, i;
1054
53c7d064
SA		 1055 if (!msix)
1056 goto msi_only;
1057
83b7180d 1058 /* Number of supported queues. */
a99955fc 1059 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1060 if (adapter->vfs_allocated_count)
1061 adapter->num_tx_queues = 1;
1062 else
1063 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1064
047e0030
AD		 1065 /* start with one vector for every rx queue */
1066 numvecs = adapter->num_rx_queues;
1067
3ad2f3fb 1068 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1069 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1070 numvecs += adapter->num_tx_queues;
047e0030
AD		 1071
1072 /* store the number of vectors reserved for queues */
1073 adapter->num_q_vectors = numvecs;
1074
1075 /* add 1 vector for link status interrupts */
1076 numvecs++;
9d5c8243
AK		 1077 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1078 GFP_KERNEL);
f96a8a0b 1079
9d5c8243
AK		 1080 if (!adapter->msix_entries)
1081 goto msi_only;
1082
1083 for (i = 0; i < numvecs; i++)
1084 adapter->msix_entries[i].entry = i;
1085
1086 err = pci_enable_msix(adapter->pdev,
1087 adapter->msix_entries,
1088 numvecs);
1089 if (err == 0)
0c2cc02e 1090 return;
9d5c8243
AK		 1091
1092 igb_reset_interrupt_capability(adapter);
1093
1094 /* If we can't do MSI-X, try MSI */
1095msi_only:
2a3abf6d
AD		 1096#ifdef CONFIG_PCI_IOV
1097 /* disable SR-IOV for non MSI-X configurations */
1098 if (adapter->vf_data) {
1099 struct e1000_hw *hw = &adapter->hw;
1100 /* disable iov and allow time for transactions to clear */
1101 pci_disable_sriov(adapter->pdev);
1102 msleep(500);
1103
1104 kfree(adapter->vf_data);
1105 adapter->vf_data = NULL;
1106 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1107 wrfl();
2a3abf6d
AD		 1108 msleep(100);
1109 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1110 }
1111#endif
4fc82adf 1112 adapter->vfs_allocated_count = 0;
a99955fc 1113 adapter->rss_queues = 1;
4fc82adf 1114 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1115 adapter->num_rx_queues = 1;
661086df 1116 adapter->num_tx_queues = 1;
047e0030 1117 adapter->num_q_vectors = 1;
9d5c8243 1118 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1119 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1120}
1121
5536d210
AD		 1122static void igb_add_ring(struct igb_ring *ring,
1123 struct igb_ring_container *head)
1124{
1125 head->ring = ring;
1126 head->count++;
1127}
1128
047e0030 1129/**
5536d210 1130 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1131 * @adapter: board private structure to initialize
5536d210
AD		 1132 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1133 * @v_idx: index of vector in adapter struct
1134 * @txr_count: total number of Tx rings to allocate
1135 * @txr_idx: index of first Tx ring to allocate
1136 * @rxr_count: total number of Rx rings to allocate
1137 * @rxr_idx: index of first Rx ring to allocate
047e0030 1138 *
5536d210 1139 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1140 **/
5536d210
AD		 1141static int igb_alloc_q_vector(struct igb_adapter *adapter,
1142 int v_count, int v_idx,
1143 int txr_count, int txr_idx,
1144 int rxr_count, int rxr_idx)
047e0030
AD		 1145{
1146 struct igb_q_vector *q_vector;
5536d210
AD		 1147 struct igb_ring *ring;
1148 int ring_count, size;
047e0030 1149
5536d210
AD		 1150 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1151 if (txr_count > 1 || rxr_count > 1)
1152 return -ENOMEM;
1153
1154 ring_count = txr_count + rxr_count;
1155 size = sizeof(struct igb_q_vector) +
1156 (sizeof(struct igb_ring) * ring_count);
1157
1158 /* allocate q_vector and rings */
1159 q_vector = kzalloc(size, GFP_KERNEL);
1160 if (!q_vector)
1161 return -ENOMEM;
1162
1163 /* initialize NAPI */
1164 netif_napi_add(adapter->netdev, &q_vector->napi,
1165 igb_poll, 64);
1166
1167 /* tie q_vector and adapter together */
1168 adapter->q_vector[v_idx] = q_vector;
1169 q_vector->adapter = adapter;
1170
1171 /* initialize work limits */
1172 q_vector->tx.work_limit = adapter->tx_work_limit;
1173
1174 /* initialize ITR configuration */
1175 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1176 q_vector->itr_val = IGB_START_ITR;
1177
1178 /* initialize pointer to rings */
1179 ring = q_vector->ring;
1180
1181 if (txr_count) {
1182 /* assign generic ring traits */
1183 ring->dev = &adapter->pdev->dev;
1184 ring->netdev = adapter->netdev;
1185
1186 /* configure backlink on ring */
1187 ring->q_vector = q_vector;
1188
1189 /* update q_vector Tx values */
1190 igb_add_ring(ring, &q_vector->tx);
1191
1192 /* For 82575, context index must be unique per ring. */
1193 if (adapter->hw.mac.type == e1000_82575)
1194 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1195
1196 /* apply Tx specific ring traits */
1197 ring->count = adapter->tx_ring_count;
1198 ring->queue_index = txr_idx;
1199
1200 /* assign ring to adapter */
1201 adapter->tx_ring[txr_idx] = ring;
1202
1203 /* push pointer to next ring */
1204 ring++;
047e0030 1205 }
81c2fc22 1206
5536d210
AD		 1207 if (rxr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
047e0030 1211
5536d210
AD		 1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
047e0030 1214
5536d210
AD		 1215 /* update q_vector Rx values */
1216 igb_add_ring(ring, &q_vector->rx);
047e0030 1217
5536d210
AD		 1218 /* set flag indicating ring supports SCTP checksum offload */
1219 if (adapter->hw.mac.type >= e1000_82576)
1220 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1221
5536d210
AD		 1222 /*
1223 * On i350, i210, and i211, loopback VLAN packets
1224 * have the tag byte-swapped.
1225 * */
1226 if (adapter->hw.mac.type >= e1000_i350)
1227 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1228
5536d210
AD		 1229 /* apply Rx specific ring traits */
1230 ring->count = adapter->rx_ring_count;
1231 ring->queue_index = rxr_idx;
1232
1233 /* assign ring to adapter */
1234 adapter->rx_ring[rxr_idx] = ring;
1235 }
1236
1237 return 0;
047e0030
AD		 1238}
1239
5536d210 1240
047e0030 1241/**
5536d210
AD		 1242 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1243 * @adapter: board private structure to initialize
047e0030 1244 *
5536d210
AD		 1245 * We allocate one q_vector per queue interrupt. If allocation fails we
1246 * return -ENOMEM.
047e0030 1247 **/
5536d210 1248static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1249{
5536d210
AD		 1250 int q_vectors = adapter->num_q_vectors;
1251 int rxr_remaining = adapter->num_rx_queues;
1252 int txr_remaining = adapter->num_tx_queues;
1253 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1254 int err;
047e0030 1255
5536d210
AD		 1256 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1257 for (; rxr_remaining; v_idx++) {
1258 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1259 0, 0, 1, rxr_idx);
047e0030 1260
5536d210
AD		 1261 if (err)
1262 goto err_out;
1263
1264 /* update counts and index */
1265 rxr_remaining--;
1266 rxr_idx++;
047e0030 1267 }
047e0030 1268 }
5536d210
AD		 1269
1270 for (; v_idx < q_vectors; v_idx++) {
1271 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1272 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1273 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1274 tqpv, txr_idx, rqpv, rxr_idx);
1275
1276 if (err)
1277 goto err_out;
1278
1279 /* update counts and index */
1280 rxr_remaining -= rqpv;
1281 txr_remaining -= tqpv;
1282 rxr_idx++;
1283 txr_idx++;
1284 }
1285
047e0030 1286 return 0;
5536d210
AD		 1287
1288err_out:
1289 adapter->num_tx_queues = 0;
1290 adapter->num_rx_queues = 0;
1291 adapter->num_q_vectors = 0;
1292
1293 while (v_idx--)
1294 igb_free_q_vector(adapter, v_idx);
1295
1296 return -ENOMEM;
047e0030
AD		 1297}
1298
1299/**
1300 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1301 *
1302 * This function initializes the interrupts and allocates all of the queues.
1303 **/
53c7d064 1304static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1305{
1306 struct pci_dev *pdev = adapter->pdev;
1307 int err;
1308
53c7d064 1309 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1310
1311 err = igb_alloc_q_vectors(adapter);
1312 if (err) {
1313 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1314 goto err_alloc_q_vectors;
1315 }
1316
5536d210 1317 igb_cache_ring_register(adapter);
047e0030
AD		 1318
1319 return 0;
5536d210 1320
047e0030
AD		 1321err_alloc_q_vectors:
1322 igb_reset_interrupt_capability(adapter);
1323 return err;
1324}
1325
9d5c8243
AK		 1326/**
1327 * igb_request_irq - initialize interrupts
1328 *
1329 * Attempts to configure interrupts using the best available
1330 * capabilities of the hardware and kernel.
1331 **/
1332static int igb_request_irq(struct igb_adapter *adapter)
1333{
1334 struct net_device *netdev = adapter->netdev;
047e0030 1335 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1336 int err = 0;
1337
1338 if (adapter->msix_entries) {
1339 err = igb_request_msix(adapter);
844290e5 1340 if (!err)
9d5c8243 1341 goto request_done;
9d5c8243 1342 /* fall back to MSI */
5536d210
AD		 1343 igb_free_all_tx_resources(adapter);
1344 igb_free_all_rx_resources(adapter);
53c7d064 1345
047e0030 1346 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1347 err = igb_init_interrupt_scheme(adapter, false);
1348 if (err)
047e0030 1349 goto request_done;
53c7d064 1350
047e0030
AD		 1351 igb_setup_all_tx_resources(adapter);
1352 igb_setup_all_rx_resources(adapter);
53c7d064 1353 igb_configure(adapter);
9d5c8243 1354 }
844290e5 1355
c74d588e
AD		 1356 igb_assign_vector(adapter->q_vector[0], 0);
1357
7dfc16fa 1358 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1359 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1360 netdev->name, adapter);
9d5c8243
AK		 1361 if (!err)
1362 goto request_done;
047e0030 1363
9d5c8243
AK		 1364 /* fall back to legacy interrupts */
1365 igb_reset_interrupt_capability(adapter);
7dfc16fa 1366 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1367 }
1368
c74d588e 1369 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1370 netdev->name, adapter);
9d5c8243 1371
6cb5e577 1372 if (err)
c74d588e 1373 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1374 err);
9d5c8243
AK		 1375
1376request_done:
1377 return err;
1378}
1379
1380static void igb_free_irq(struct igb_adapter *adapter)
1381{
9d5c8243
AK		 1382 if (adapter->msix_entries) {
1383 int vector = 0, i;
1384
047e0030 1385 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1386
0d1ae7f4 1387 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1388 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1389 adapter->q_vector[i]);
047e0030
AD		 1390 } else {
1391 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1392 }
9d5c8243
AK		 1393}
1394
1395/**
1396 * igb_irq_disable - Mask off interrupt generation on the NIC
1397 * @adapter: board private structure
1398 **/
1399static void igb_irq_disable(struct igb_adapter *adapter)
1400{
1401 struct e1000_hw *hw = &adapter->hw;
1402
25568a53
AD		 1403 /*
1404 * we need to be careful when disabling interrupts. The VFs are also
1405 * mapped into these registers and so clearing the bits can cause
1406 * issues on the VF drivers so we only need to clear what we set
1407 */
9d5c8243 1408 if (adapter->msix_entries) {
2dfd1212
AD		 1409 u32 regval = rd32(E1000_EIAM);
1410 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1411 wr32(E1000_EIMC, adapter->eims_enable_mask);
1412 regval = rd32(E1000_EIAC);
1413 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1414 }
844290e5
PW		 1415
1416 wr32(E1000_IAM, 0);
9d5c8243
AK		 1417 wr32(E1000_IMC, ~0);
1418 wrfl();
81a61859
ET		 1419 if (adapter->msix_entries) {
1420 int i;
1421 for (i = 0; i < adapter->num_q_vectors; i++)
1422 synchronize_irq(adapter->msix_entries[i].vector);
1423 } else {
1424 synchronize_irq(adapter->pdev->irq);
1425 }
9d5c8243
AK		 1426}
1427
1428/**
1429 * igb_irq_enable - Enable default interrupt generation settings
1430 * @adapter: board private structure
1431 **/
1432static void igb_irq_enable(struct igb_adapter *adapter)
1433{
1434 struct e1000_hw *hw = &adapter->hw;
1435
1436 if (adapter->msix_entries) {
06218a8d 1437 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1438 u32 regval = rd32(E1000_EIAC);
1439 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAM);
1441 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1442 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1443 if (adapter->vfs_allocated_count) {
4ae196df 1444 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1445 ims |= E1000_IMS_VMMB;
1446 }
1447 wr32(E1000_IMS, ims);
844290e5 1448 } else {
55cac248
AD		 1449 wr32(E1000_IMS, IMS_ENABLE_MASK |
1450 E1000_IMS_DRSTA);
1451 wr32(E1000_IAM, IMS_ENABLE_MASK |
1452 E1000_IMS_DRSTA);
844290e5 1453 }
9d5c8243
AK		 1454}
1455
1456static void igb_update_mng_vlan(struct igb_adapter *adapter)
1457{
51466239 1458 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1459 u16 vid = adapter->hw.mng_cookie.vlan_id;
1460 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1461
1462 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1463 /* add VID to filter table */
1464 igb_vfta_set(hw, vid, true);
1465 adapter->mng_vlan_id = vid;
1466 } else {
1467 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1468 }
1469
1470 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1471 (vid != old_vid) &&
b2cb09b1 1472 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1473 /* remove VID from filter table */
1474 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1475 }
1476}
1477
1478/**
1479 * igb_release_hw_control - release control of the h/w to f/w
1480 * @adapter: address of board private structure
1481 *
1482 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1483 * For ASF and Pass Through versions of f/w this means that the
1484 * driver is no longer loaded.
1485 *
1486 **/
1487static void igb_release_hw_control(struct igb_adapter *adapter)
1488{
1489 struct e1000_hw *hw = &adapter->hw;
1490 u32 ctrl_ext;
1491
1492 /* Let firmware take over control of h/w */
1493 ctrl_ext = rd32(E1000_CTRL_EXT);
1494 wr32(E1000_CTRL_EXT,
1495 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1496}
1497
9d5c8243
AK		 1498/**
1499 * igb_get_hw_control - get control of the h/w from f/w
1500 * @adapter: address of board private structure
1501 *
1502 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1503 * For ASF and Pass Through versions of f/w this means that
1504 * the driver is loaded.
1505 *
1506 **/
1507static void igb_get_hw_control(struct igb_adapter *adapter)
1508{
1509 struct e1000_hw *hw = &adapter->hw;
1510 u32 ctrl_ext;
1511
1512 /* Let firmware know the driver has taken over */
1513 ctrl_ext = rd32(E1000_CTRL_EXT);
1514 wr32(E1000_CTRL_EXT,
1515 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1516}
1517
9d5c8243
AK		 1518/**
1519 * igb_configure - configure the hardware for RX and TX
1520 * @adapter: private board structure
1521 **/
1522static void igb_configure(struct igb_adapter *adapter)
1523{
1524 struct net_device *netdev = adapter->netdev;
1525 int i;
1526
1527 igb_get_hw_control(adapter);
ff41f8dc 1528 igb_set_rx_mode(netdev);
9d5c8243
AK		 1529
1530 igb_restore_vlan(adapter);
9d5c8243 1531
85b430b4 1532 igb_setup_tctl(adapter);
06cf2666 1533 igb_setup_mrqc(adapter);
9d5c8243 1534 igb_setup_rctl(adapter);
85b430b4
AD		 1535
1536 igb_configure_tx(adapter);
9d5c8243 1537 igb_configure_rx(adapter);
662d7205
AD		 1538
1539 igb_rx_fifo_flush_82575(&adapter->hw);
1540
c493ea45 1541 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1542 * at least 1 descriptor unused to make sure
1543 * next_to_use != next_to_clean */
1544 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1545 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1546 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1547 }
9d5c8243
AK		 1548}
1549
88a268c1
NN		 1550/**
1551 * igb_power_up_link - Power up the phy/serdes link
1552 * @adapter: address of board private structure
1553 **/
1554void igb_power_up_link(struct igb_adapter *adapter)
1555{
76886596
AA		 1556 igb_reset_phy(&adapter->hw);
1557
88a268c1
NN		 1558 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1559 igb_power_up_phy_copper(&adapter->hw);
1560 else
1561 igb_power_up_serdes_link_82575(&adapter->hw);
1562}
1563
1564/**
1565 * igb_power_down_link - Power down the phy/serdes link
1566 * @adapter: address of board private structure
1567 */
1568static void igb_power_down_link(struct igb_adapter *adapter)
1569{
1570 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1571 igb_power_down_phy_copper_82575(&adapter->hw);
1572 else
1573 igb_shutdown_serdes_link_82575(&adapter->hw);
1574}
9d5c8243
AK		 1575
1576/**
1577 * igb_up - Open the interface and prepare it to handle traffic
1578 * @adapter: board private structure
1579 **/
9d5c8243
AK		 1580int igb_up(struct igb_adapter *adapter)
1581{
1582 struct e1000_hw *hw = &adapter->hw;
1583 int i;
1584
1585 /* hardware has been reset, we need to reload some things */
1586 igb_configure(adapter);
1587
1588 clear_bit(__IGB_DOWN, &adapter->state);
1589
0d1ae7f4
AD		 1590 for (i = 0; i < adapter->num_q_vectors; i++)
1591 napi_enable(&(adapter->q_vector[i]->napi));
1592
844290e5 1593 if (adapter->msix_entries)
9d5c8243 1594 igb_configure_msix(adapter);
feeb2721
AD		 1595 else
1596 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1597
1598 /* Clear any pending interrupts. */
1599 rd32(E1000_ICR);
1600 igb_irq_enable(adapter);
1601
d4960307
AD		 1602 /* notify VFs that reset has been completed */
1603 if (adapter->vfs_allocated_count) {
1604 u32 reg_data = rd32(E1000_CTRL_EXT);
1605 reg_data |= E1000_CTRL_EXT_PFRSTD;
1606 wr32(E1000_CTRL_EXT, reg_data);
1607 }
1608
4cb9be7a
JB		 1609 netif_tx_start_all_queues(adapter->netdev);
1610
25568a53
AD		 1611 /* start the watchdog. */
1612 hw->mac.get_link_status = 1;
1613 schedule_work(&adapter->watchdog_task);
1614
9d5c8243
AK		 1615 return 0;
1616}
1617
1618void igb_down(struct igb_adapter *adapter)
1619{
9d5c8243 1620 struct net_device *netdev = adapter->netdev;
330a6d6a 1621 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1622 u32 tctl, rctl;
1623 int i;
1624
1625 /* signal that we're down so the interrupt handler does not
1626 * reschedule our watchdog timer */
1627 set_bit(__IGB_DOWN, &adapter->state);
1628
1629 /* disable receives in the hardware */
1630 rctl = rd32(E1000_RCTL);
1631 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1632 /* flush and sleep below */
1633
fd2ea0a7 1634 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1635
1636 /* disable transmits in the hardware */
1637 tctl = rd32(E1000_TCTL);
1638 tctl &= ~E1000_TCTL_EN;
1639 wr32(E1000_TCTL, tctl);
1640 /* flush both disables and wait for them to finish */
1641 wrfl();
1642 msleep(10);
1643
0d1ae7f4
AD		 1644 for (i = 0; i < adapter->num_q_vectors; i++)
1645 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1646
9d5c8243
AK		 1647 igb_irq_disable(adapter);
1648
1649 del_timer_sync(&adapter->watchdog_timer);
1650 del_timer_sync(&adapter->phy_info_timer);
1651
9d5c8243 1652 netif_carrier_off(netdev);
04fe6358
AD		 1653
1654 /* record the stats before reset*/
12dcd86b
ED		 1655 spin_lock(&adapter->stats64_lock);
1656 igb_update_stats(adapter, &adapter->stats64);
1657 spin_unlock(&adapter->stats64_lock);
04fe6358 1658
9d5c8243
AK		 1659 adapter->link_speed = 0;
1660 adapter->link_duplex = 0;
1661
3023682e
JK		 1662 if (!pci_channel_offline(adapter->pdev))
1663 igb_reset(adapter);
9d5c8243
AK		 1664 igb_clean_all_tx_rings(adapter);
1665 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1666#ifdef CONFIG_IGB_DCA
1667
1668 /* since we reset the hardware DCA settings were cleared */
1669 igb_setup_dca(adapter);
1670#endif
9d5c8243
AK		 1671}
1672
1673void igb_reinit_locked(struct igb_adapter *adapter)
1674{
1675 WARN_ON(in_interrupt());
1676 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1677 msleep(1);
1678 igb_down(adapter);
1679 igb_up(adapter);
1680 clear_bit(__IGB_RESETTING, &adapter->state);
1681}
1682
1683void igb_reset(struct igb_adapter *adapter)
1684{
090b1795 1685 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1686 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1687 struct e1000_mac_info *mac = &hw->mac;
1688 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1689 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1690
1691 /* Repartition Pba for greater than 9k mtu
1692 * To take effect CTRL.RST is required.
1693 */
fa4dfae0 1694 switch (mac->type) {
d2ba2ed8 1695 case e1000_i350:
55cac248
AD		 1696 case e1000_82580:
1697 pba = rd32(E1000_RXPBS);
1698 pba = igb_rxpbs_adjust_82580(pba);
1699 break;
fa4dfae0 1700 case e1000_82576:
d249be54
AD		 1701 pba = rd32(E1000_RXPBS);
1702 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1703 break;
1704 case e1000_82575:
f96a8a0b
CW		 1705 case e1000_i210:
1706 case e1000_i211:
fa4dfae0
AD		 1707 default:
1708 pba = E1000_PBA_34K;
1709 break;
2d064c06 1710 }
9d5c8243 1711
2d064c06
AD		 1712 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1713 (mac->type < e1000_82576)) {
9d5c8243
AK		 1714 /* adjust PBA for jumbo frames */
1715 wr32(E1000_PBA, pba);
1716
1717 /* To maintain wire speed transmits, the Tx FIFO should be
1718 * large enough to accommodate two full transmit packets,
1719 * rounded up to the next 1KB and expressed in KB. Likewise,
1720 * the Rx FIFO should be large enough to accommodate at least
1721 * one full receive packet and is similarly rounded up and
1722 * expressed in KB. */
1723 pba = rd32(E1000_PBA);
1724 /* upper 16 bits has Tx packet buffer allocation size in KB */
1725 tx_space = pba >> 16;
1726 /* lower 16 bits has Rx packet buffer allocation size in KB */
1727 pba &= 0xffff;
1728 /* the tx fifo also stores 16 bytes of information about the tx
1729 * but don't include ethernet FCS because hardware appends it */
1730 min_tx_space = (adapter->max_frame_size +
85e8d004 1731 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1732 ETH_FCS_LEN) * 2;
1733 min_tx_space = ALIGN(min_tx_space, 1024);
1734 min_tx_space >>= 10;
1735 /* software strips receive CRC, so leave room for it */
1736 min_rx_space = adapter->max_frame_size;
1737 min_rx_space = ALIGN(min_rx_space, 1024);
1738 min_rx_space >>= 10;
1739
1740 /* If current Tx allocation is less than the min Tx FIFO size,
1741 * and the min Tx FIFO size is less than the current Rx FIFO
1742 * allocation, take space away from current Rx allocation */
1743 if (tx_space < min_tx_space &&
1744 ((min_tx_space - tx_space) < pba)) {
1745 pba = pba - (min_tx_space - tx_space);
1746
1747 /* if short on rx space, rx wins and must trump tx
1748 * adjustment */
1749 if (pba < min_rx_space)
1750 pba = min_rx_space;
1751 }
2d064c06 1752 wr32(E1000_PBA, pba);
9d5c8243 1753 }
9d5c8243
AK		 1754
1755 /* flow control settings */
1756 /* The high water mark must be low enough to fit one full frame
1757 * (or the size used for early receive) above it in the Rx FIFO.
1758 * Set it to the lower of:
1759 * - 90% of the Rx FIFO size, or
1760 * - the full Rx FIFO size minus one full frame */
1761 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1762 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1763
d48507fe 1764 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1765 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1766 fc->pause_time = 0xFFFF;
1767 fc->send_xon = 1;
0cce119a 1768 fc->current_mode = fc->requested_mode;
9d5c8243 1769
4ae196df
AD		 1770 /* disable receive for all VFs and wait one second */
1771 if (adapter->vfs_allocated_count) {
1772 int i;
1773 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1774 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1775
1776 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1777 igb_ping_all_vfs(adapter);
4ae196df
AD		 1778
1779 /* disable transmits and receives */
1780 wr32(E1000_VFRE, 0);
1781 wr32(E1000_VFTE, 0);
1782 }
1783
9d5c8243 1784 /* Allow time for pending master requests to run */
330a6d6a 1785 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1786 wr32(E1000_WUC, 0);
1787
330a6d6a 1788 if (hw->mac.ops.init_hw(hw))
090b1795 1789 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1790
a27416bb
MV		 1791 /*
1792 * Flow control settings reset on hardware reset, so guarantee flow
1793 * control is off when forcing speed.
1794 */
1795 if (!hw->mac.autoneg)
1796 igb_force_mac_fc(hw);
1797
b6e0c419 1798 igb_init_dmac(adapter, pba);
e428893b
CW		 1799#ifdef CONFIG_IGB_HWMON
1800 /* Re-initialize the thermal sensor on i350 devices. */
1801 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1802 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1803 /* If present, re-initialize the external thermal sensor
1804 * interface.
1805 */
1806 if (adapter->ets)
1807 mac->ops.init_thermal_sensor_thresh(hw);
1808 }
1809 }
1810#endif
88a268c1
NN		 1811 if (!netif_running(adapter->netdev))
1812 igb_power_down_link(adapter);
1813
9d5c8243
AK		 1814 igb_update_mng_vlan(adapter);
1815
1816 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1817 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1818
1f6e8178
MV		 1819 /* Re-enable PTP, where applicable. */
1820 igb_ptp_reset(adapter);
1f6e8178 1821
330a6d6a 1822 igb_get_phy_info(hw);
9d5c8243
AK		 1823}
1824
c8f44aff
MM		 1825static netdev_features_t igb_fix_features(struct net_device *netdev,
1826 netdev_features_t features)
b2cb09b1
JP		 1827{
1828 /*
1829 * Since there is no support for separate rx/tx vlan accel
1830 * enable/disable make sure tx flag is always in same state as rx.
1831 */
1832 if (features & NETIF_F_HW_VLAN_RX)
1833 features |= NETIF_F_HW_VLAN_TX;
1834 else
1835 features &= ~NETIF_F_HW_VLAN_TX;
1836
1837 return features;
1838}
1839
c8f44aff
MM		 1840static int igb_set_features(struct net_device *netdev,
1841 netdev_features_t features)
ac52caa3 1842{
c8f44aff 1843 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1844 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1845
b2cb09b1
JP		 1846 if (changed & NETIF_F_HW_VLAN_RX)
1847 igb_vlan_mode(netdev, features);
1848
89eaefb6
BG		 1849 if (!(changed & NETIF_F_RXALL))
1850 return 0;
1851
1852 netdev->features = features;
1853
1854 if (netif_running(netdev))
1855 igb_reinit_locked(adapter);
1856 else
1857 igb_reset(adapter);
1858
ac52caa3
MM		 1859 return 0;
1860}
1861
2e5c6922 1862static const struct net_device_ops igb_netdev_ops = {
559e9c49 1863 .ndo_open = igb_open,
2e5c6922 1864 .ndo_stop = igb_close,
cd392f5c 1865 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1866 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1867 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1868 .ndo_set_mac_address = igb_set_mac,
1869 .ndo_change_mtu = igb_change_mtu,
1870 .ndo_do_ioctl = igb_ioctl,
1871 .ndo_tx_timeout = igb_tx_timeout,
1872 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1873 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1874 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1875 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1876 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1877 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1878 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1879#ifdef CONFIG_NET_POLL_CONTROLLER
1880 .ndo_poll_controller = igb_netpoll,
1881#endif
b2cb09b1
JP		 1882 .ndo_fix_features = igb_fix_features,
1883 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1884};
1885
d67974f0
CW		 1886/**
1887 * igb_set_fw_version - Configure version string for ethtool
1888 * @adapter: adapter struct
1889 *
1890 **/
1891void igb_set_fw_version(struct igb_adapter *adapter)
1892{
1893 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1894 struct e1000_fw_version fw;
1895
1896 igb_get_fw_version(hw, &fw);
1897
1898 switch (hw->mac.type) {
1899 case e1000_i211:
d67974f0 1900 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1901 "%2d.%2d-%d",
1902 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1903 break;
1904
1905 default:
1906 /* if option is rom valid, display its version too */
1907 if (fw.or_valid) {
1908 snprintf(adapter->fw_version,
1909 sizeof(adapter->fw_version),
1910 "%d.%d, 0x%08x, %d.%d.%d",
1911 fw.eep_major, fw.eep_minor, fw.etrack_id,
1912 fw.or_major, fw.or_build, fw.or_patch);
1913 /* no option rom */
1914 } else {
1915 snprintf(adapter->fw_version,
1916 sizeof(adapter->fw_version),
1917 "%d.%d, 0x%08x",
1918 fw.eep_major, fw.eep_minor, fw.etrack_id);
1919 }
1920 break;
d67974f0 1921 }
d67974f0
CW		 1922 return;
1923}
1924
441fc6fd
CW		 1925static const struct i2c_board_info i350_sensor_info = {
1926 I2C_BOARD_INFO("i350bb", 0Xf8),
1927};
1928
1929/* igb_init_i2c - Init I2C interface
1930 * @adapter: pointer to adapter structure
1931 *
1932 */
1933static s32 igb_init_i2c(struct igb_adapter *adapter)
1934{
1935 s32 status = E1000_SUCCESS;
1936
1937 /* I2C interface supported on i350 devices */
1938 if (adapter->hw.mac.type != e1000_i350)
1939 return E1000_SUCCESS;
1940
1941 /* Initialize the i2c bus which is controlled by the registers.
1942 * This bus will use the i2c_algo_bit structue that implements
1943 * the protocol through toggling of the 4 bits in the register.
1944 */
1945 adapter->i2c_adap.owner = THIS_MODULE;
1946 adapter->i2c_algo = igb_i2c_algo;
1947 adapter->i2c_algo.data = adapter;
1948 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1949 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1950 strlcpy(adapter->i2c_adap.name, "igb BB",
1951 sizeof(adapter->i2c_adap.name));
1952 status = i2c_bit_add_bus(&adapter->i2c_adap);
1953 return status;
1954}
1955
9d5c8243
AK		 1956/**
1957 * igb_probe - Device Initialization Routine
1958 * @pdev: PCI device information struct
1959 * @ent: entry in igb_pci_tbl
1960 *
1961 * Returns 0 on success, negative on failure
1962 *
1963 * igb_probe initializes an adapter identified by a pci_dev structure.
1964 * The OS initialization, configuring of the adapter private structure,
1965 * and a hardware reset occur.
1966 **/
1dd06ae8 1967static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1968{
1969 struct net_device *netdev;
1970 struct igb_adapter *adapter;
1971 struct e1000_hw *hw;
4337e993 1972 u16 eeprom_data = 0;
9835fd73 1973 s32 ret_val;
4337e993 1974 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1975 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1976 unsigned long mmio_start, mmio_len;
2d6a5e95 1977 int err, pci_using_dac;
9835fd73 1978 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1979
bded64a7
AG		 1980 /* Catch broken hardware that put the wrong VF device ID in
1981 * the PCIe SR-IOV capability.
1982 */
1983 if (pdev->is_virtfn) {
1984 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1985 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1986 return -EINVAL;
1987 }
1988
aed5dec3 1989 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1990 if (err)
1991 return err;
1992
1993 pci_using_dac = 0;
59d71989 1994 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1995 if (!err) {
59d71989 1996 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1997 if (!err)
1998 pci_using_dac = 1;
1999 } else {
59d71989 2000 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2001 if (err) {
59d71989 2002 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 2003 if (err) {
2004 dev_err(&pdev->dev, "No usable DMA "
2005 "configuration, aborting\n");
2006 goto err_dma;
2007 }
2008 }
2009 }
2010
aed5dec3
AD		 2011 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2012 IORESOURCE_MEM),
2013 igb_driver_name);
9d5c8243
AK		 2014 if (err)
2015 goto err_pci_reg;
2016
19d5afd4 2017 pci_enable_pcie_error_reporting(pdev);
40a914fa 2018
9d5c8243 2019 pci_set_master(pdev);
c682fc23 2020 pci_save_state(pdev);
9d5c8243
AK		 2021
2022 err = -ENOMEM;
1bfaf07b 2023 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2024 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2025 if (!netdev)
2026 goto err_alloc_etherdev;
2027
2028 SET_NETDEV_DEV(netdev, &pdev->dev);
2029
2030 pci_set_drvdata(pdev, netdev);
2031 adapter = netdev_priv(netdev);
2032 adapter->netdev = netdev;
2033 adapter->pdev = pdev;
2034 hw = &adapter->hw;
2035 hw->back = adapter;
b3f4d599 2036 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2037
2038 mmio_start = pci_resource_start(pdev, 0);
2039 mmio_len = pci_resource_len(pdev, 0);
2040
2041 err = -EIO;
28b0759c
AD		 2042 hw->hw_addr = ioremap(mmio_start, mmio_len);
2043 if (!hw->hw_addr)
9d5c8243
AK		 2044 goto err_ioremap;
2045
2e5c6922 2046 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2047 igb_set_ethtool_ops(netdev);
9d5c8243 2048 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2049
2050 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2051
2052 netdev->mem_start = mmio_start;
2053 netdev->mem_end = mmio_start + mmio_len;
2054
9d5c8243
AK		 2055 /* PCI config space info */
2056 hw->vendor_id = pdev->vendor;
2057 hw->device_id = pdev->device;
2058 hw->revision_id = pdev->revision;
2059 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2060 hw->subsystem_device_id = pdev->subsystem_device;
2061
9d5c8243
AK		 2062 /* Copy the default MAC, PHY and NVM function pointers */
2063 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2064 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2065 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2066 /* Initialize skew-specific constants */
2067 err = ei->get_invariants(hw);
2068 if (err)
450c87c8 2069 goto err_sw_init;
9d5c8243 2070
450c87c8 2071 /* setup the private structure */
9d5c8243
AK		 2072 err = igb_sw_init(adapter);
2073 if (err)
2074 goto err_sw_init;
2075
2076 igb_get_bus_info_pcie(hw);
2077
2078 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2079
2080 /* Copper options */
2081 if (hw->phy.media_type == e1000_media_type_copper) {
2082 hw->phy.mdix = AUTO_ALL_MODES;
2083 hw->phy.disable_polarity_correction = false;
2084 hw->phy.ms_type = e1000_ms_hw_default;
2085 }
2086
2087 if (igb_check_reset_block(hw))
2088 dev_info(&pdev->dev,
2089 "PHY reset is blocked due to SOL/IDER session.\n");
2090
077887c3
AD		 2091 /*
2092 * features is initialized to 0 in allocation, it might have bits
2093 * set by igb_sw_init so we should use an or instead of an
2094 * assignment.
2095 */
2096 netdev->features |= NETIF_F_SG |
2097 NETIF_F_IP_CSUM |
2098 NETIF_F_IPV6_CSUM |
2099 NETIF_F_TSO |
2100 NETIF_F_TSO6 |
2101 NETIF_F_RXHASH |
2102 NETIF_F_RXCSUM |
2103 NETIF_F_HW_VLAN_RX |
2104 NETIF_F_HW_VLAN_TX;
2105
2106 /* copy netdev features into list of user selectable features */
2107 netdev->hw_features |= netdev->features;
89eaefb6 2108 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2109
2110 /* set this bit last since it cannot be part of hw_features */
2111 netdev->features |= NETIF_F_HW_VLAN_FILTER;
2112
2113 netdev->vlan_features |= NETIF_F_TSO |
2114 NETIF_F_TSO6 |
2115 NETIF_F_IP_CSUM |
2116 NETIF_F_IPV6_CSUM |
2117 NETIF_F_SG;
48f29ffc 2118
6b8f0922
BG		 2119 netdev->priv_flags |= IFF_SUPP_NOFCS;
2120
7b872a55 2121 if (pci_using_dac) {
9d5c8243 2122 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2123 netdev->vlan_features |= NETIF_F_HIGHDMA;
2124 }
9d5c8243 2125
ac52caa3
MM		 2126 if (hw->mac.type >= e1000_82576) {
2127 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2128 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2129 }
b9473560 2130
01789349
JP		 2131 netdev->priv_flags |= IFF_UNICAST_FLT;
2132
330a6d6a 2133 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2134
2135 /* before reading the NVM, reset the controller to put the device in a
2136 * known good starting state */
2137 hw->mac.ops.reset_hw(hw);
2138
f96a8a0b
CW		 2139 /*
2140 * make sure the NVM is good , i211 parts have special NVM that
2141 * doesn't contain a checksum
2142 */
2143 if (hw->mac.type != e1000_i211) {
2144 if (hw->nvm.ops.validate(hw) < 0) {
2145 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2146 err = -EIO;
2147 goto err_eeprom;
2148 }
9d5c8243
AK		 2149 }
2150
2151 /* copy the MAC address out of the NVM */
2152 if (hw->mac.ops.read_mac_addr(hw))
2153 dev_err(&pdev->dev, "NVM Read Error\n");
2154
2155 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2156
aaeb6cdf 2157 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2158 dev_err(&pdev->dev, "Invalid MAC Address\n");
2159 err = -EIO;
2160 goto err_eeprom;
2161 }
2162
d67974f0
CW		 2163 /* get firmware version for ethtool -i */
2164 igb_set_fw_version(adapter);
2165
c061b18d 2166 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2167 (unsigned long) adapter);
c061b18d 2168 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2169 (unsigned long) adapter);
9d5c8243
AK		 2170
2171 INIT_WORK(&adapter->reset_task, igb_reset_task);
2172 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2173
450c87c8 2174 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2175 adapter->fc_autoneg = true;
2176 hw->mac.autoneg = true;
2177 hw->phy.autoneg_advertised = 0x2f;
2178
0cce119a
AD		 2179 hw->fc.requested_mode = e1000_fc_default;
2180 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2181
9d5c8243
AK		 2182 igb_validate_mdi_setting(hw);
2183
63d4a8f9 2184 /* By default, support wake on port A */
a2cf8b6c 2185 if (hw->bus.func == 0)
63d4a8f9
MV		 2186 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2187
2188 /* Check the NVM for wake support on non-port A ports */
2189 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2190 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2191 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2192 &eeprom_data);
a2cf8b6c
AD		 2193 else if (hw->bus.func == 1)
2194 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2195
63d4a8f9
MV		 2196 if (eeprom_data & IGB_EEPROM_APME)
2197 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2198
2199 /* now that we have the eeprom settings, apply the special cases where
2200 * the eeprom may be wrong or the board simply won't support wake on
2201 * lan on a particular port */
2202 switch (pdev->device) {
2203 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2204 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2205 break;
2206 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2207 case E1000_DEV_ID_82576_FIBER:
2208 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2209 /* Wake events only supported on port A for dual fiber
2210 * regardless of eeprom setting */
2211 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2212 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2213 break;
c8ea5ea9 2214 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2215 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2216 /* if quad port adapter, disable WoL on all but port A */
2217 if (global_quad_port_a != 0)
63d4a8f9 2218 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2219 else
2220 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2221 /* Reset for multiple quad port adapters */
2222 if (++global_quad_port_a == 4)
2223 global_quad_port_a = 0;
2224 break;
63d4a8f9
MV		 2225 default:
2226 /* If the device can't wake, don't set software support */
2227 if (!device_can_wakeup(&adapter->pdev->dev))
2228 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2229 }
2230
2231 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2232 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2233 adapter->wol |= E1000_WUFC_MAG;
2234
2235 /* Some vendors want WoL disabled by default, but still supported */
2236 if ((hw->mac.type == e1000_i350) &&
2237 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2238 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2239 adapter->wol = 0;
2240 }
2241
2242 device_set_wakeup_enable(&adapter->pdev->dev,
2243 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2244
2245 /* reset the hardware with the new settings */
2246 igb_reset(adapter);
2247
441fc6fd
CW		 2248 /* Init the I2C interface */
2249 err = igb_init_i2c(adapter);
2250 if (err) {
2251 dev_err(&pdev->dev, "failed to init i2c interface\n");
2252 goto err_eeprom;
2253 }
2254
9d5c8243
AK		 2255 /* let the f/w know that the h/w is now under the control of the
2256 * driver. */
2257 igb_get_hw_control(adapter);
2258
9d5c8243
AK		 2259 strcpy(netdev->name, "eth%d");
2260 err = register_netdev(netdev);
2261 if (err)
2262 goto err_register;
2263
b168dfc5
JB		 2264 /* carrier off reporting is important to ethtool even BEFORE open */
2265 netif_carrier_off(netdev);
2266
421e02f0 2267#ifdef CONFIG_IGB_DCA
bbd98fe4 2268 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2269 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2270 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2271 igb_setup_dca(adapter);
2272 }
fe4506b6 2273
38c845c7 2274#endif
e428893b
CW		 2275#ifdef CONFIG_IGB_HWMON
2276 /* Initialize the thermal sensor on i350 devices. */
2277 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2278 u16 ets_word;
3c89f6d0 2279
e428893b
CW		 2280 /*
2281 * Read the NVM to determine if this i350 device supports an
2282 * external thermal sensor.
2283 */
2284 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2285 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2286 adapter->ets = true;
2287 else
2288 adapter->ets = false;
2289 if (igb_sysfs_init(adapter))
2290 dev_err(&pdev->dev,
2291 "failed to allocate sysfs resources\n");
2292 } else {
2293 adapter->ets = false;
2294 }
2295#endif
673b8b70 2296 /* do hw tstamp init after resetting */
7ebae817 2297 igb_ptp_init(adapter);
673b8b70 2298
9d5c8243
AK		 2299 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2300 /* print bus type/speed/width info */
7c510e4b 2301 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2302 netdev->name,
559e9c49 2303 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2304 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2305 "unknown"),
59c3de89
AD		 2306 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2307 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2308 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2309 "unknown"),
7c510e4b 2310 netdev->dev_addr);
9d5c8243 2311
9835fd73
CW		 2312 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2313 if (ret_val)
2314 strcpy(part_str, "Unknown");
2315 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2316 dev_info(&pdev->dev,
2317 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2318 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2319 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2320 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2321 switch (hw->mac.type) {
2322 case e1000_i350:
f96a8a0b
CW		 2323 case e1000_i210:
2324 case e1000_i211:
09b068d4
CW		 2325 igb_set_eee_i350(hw);
2326 break;
2327 default:
2328 break;
2329 }
749ab2cd
YZ		 2330
2331 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2332 return 0;
2333
2334err_register:
2335 igb_release_hw_control(adapter);
441fc6fd 2336 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2337err_eeprom:
2338 if (!igb_check_reset_block(hw))
f5f4cf08 2339 igb_reset_phy(hw);
9d5c8243
AK		 2340
2341 if (hw->flash_address)
2342 iounmap(hw->flash_address);
9d5c8243 2343err_sw_init:
047e0030 2344 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2345 iounmap(hw->hw_addr);
2346err_ioremap:
2347 free_netdev(netdev);
2348err_alloc_etherdev:
559e9c49
AD		 2349 pci_release_selected_regions(pdev,
2350 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2351err_pci_reg:
2352err_dma:
2353 pci_disable_device(pdev);
2354 return err;
2355}
2356
fa44f2f1
GR		 2357#ifdef CONFIG_PCI_IOV
2358static int igb_disable_sriov(struct pci_dev *pdev)
2359{
2360 struct net_device *netdev = pci_get_drvdata(pdev);
2361 struct igb_adapter *adapter = netdev_priv(netdev);
2362 struct e1000_hw *hw = &adapter->hw;
2363
2364 /* reclaim resources allocated to VFs */
2365 if (adapter->vf_data) {
2366 /* disable iov and allow time for transactions to clear */
2367 if (igb_vfs_are_assigned(adapter)) {
2368 dev_warn(&pdev->dev,
2369 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2370 return -EPERM;
2371 } else {
2372 pci_disable_sriov(pdev);
2373 msleep(500);
2374 }
2375
2376 kfree(adapter->vf_data);
2377 adapter->vf_data = NULL;
2378 adapter->vfs_allocated_count = 0;
2379 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2380 wrfl();
2381 msleep(100);
2382 dev_info(&pdev->dev, "IOV Disabled\n");
2383
2384 /* Re-enable DMA Coalescing flag since IOV is turned off */
2385 adapter->flags |= IGB_FLAG_DMAC;
2386 }
2387
2388 return 0;
2389}
2390
2391static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2392{
2393 struct net_device *netdev = pci_get_drvdata(pdev);
2394 struct igb_adapter *adapter = netdev_priv(netdev);
2395 int old_vfs = pci_num_vf(pdev);
2396 int err = 0;
2397 int i;
2398
2399 if (!num_vfs)
2400 goto out;
2401 else if (old_vfs && old_vfs == num_vfs)
2402 goto out;
2403 else if (old_vfs && old_vfs != num_vfs)
2404 err = igb_disable_sriov(pdev);
2405
2406 if (err)
2407 goto out;
2408
2409 if (num_vfs > 7) {
2410 err = -EPERM;
2411 goto out;
2412 }
2413
2414 adapter->vfs_allocated_count = num_vfs;
2415
2416 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2417 sizeof(struct vf_data_storage), GFP_KERNEL);
2418
2419 /* if allocation failed then we do not support SR-IOV */
2420 if (!adapter->vf_data) {
2421 adapter->vfs_allocated_count = 0;
2422 dev_err(&pdev->dev,
2423 "Unable to allocate memory for VF Data Storage\n");
2424 err = -ENOMEM;
2425 goto out;
2426 }
2427
2428 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2429 if (err)
2430 goto err_out;
2431
2432 dev_info(&pdev->dev, "%d VFs allocated\n",
2433 adapter->vfs_allocated_count);
2434 for (i = 0; i < adapter->vfs_allocated_count; i++)
2435 igb_vf_configure(adapter, i);
2436
2437 /* DMA Coalescing is not supported in IOV mode. */
2438 adapter->flags &= ~IGB_FLAG_DMAC;
2439 goto out;
2440
2441err_out:
2442 kfree(adapter->vf_data);
2443 adapter->vf_data = NULL;
2444 adapter->vfs_allocated_count = 0;
2445out:
2446 return err;
2447}
2448
2449#endif
441fc6fd
CW		 2450/*
2451 * igb_remove_i2c - Cleanup I2C interface
2452 * @adapter: pointer to adapter structure
2453 *
2454 */
2455static void igb_remove_i2c(struct igb_adapter *adapter)
2456{
2457
2458 /* free the adapter bus structure */
2459 i2c_del_adapter(&adapter->i2c_adap);
2460}
2461
9d5c8243
AK		 2462/**
2463 * igb_remove - Device Removal Routine
2464 * @pdev: PCI device information struct
2465 *
2466 * igb_remove is called by the PCI subsystem to alert the driver
2467 * that it should release a PCI device. The could be caused by a
2468 * Hot-Plug event, or because the driver is going to be removed from
2469 * memory.
2470 **/
9f9a12f8 2471static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2472{
2473 struct net_device *netdev = pci_get_drvdata(pdev);
2474 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2475 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2476
749ab2cd 2477 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2478#ifdef CONFIG_IGB_HWMON
2479 igb_sysfs_exit(adapter);
2480#endif
441fc6fd 2481 igb_remove_i2c(adapter);
a79f4f88 2482 igb_ptp_stop(adapter);
760141a5
TH		 2483 /*
2484 * The watchdog timer may be rescheduled, so explicitly
2485 * disable watchdog from being rescheduled.
2486 */
9d5c8243
AK		 2487 set_bit(__IGB_DOWN, &adapter->state);
2488 del_timer_sync(&adapter->watchdog_timer);
2489 del_timer_sync(&adapter->phy_info_timer);
2490
760141a5
TH		 2491 cancel_work_sync(&adapter->reset_task);
2492 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2493
421e02f0 2494#ifdef CONFIG_IGB_DCA
7dfc16fa 2495 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2496 dev_info(&pdev->dev, "DCA disabled\n");
2497 dca_remove_requester(&pdev->dev);
7dfc16fa 2498 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2499 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2500 }
2501#endif
2502
9d5c8243
AK		 2503 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2504 * would have already happened in close and is redundant. */
2505 igb_release_hw_control(adapter);
2506
2507 unregister_netdev(netdev);
2508
047e0030 2509 igb_clear_interrupt_scheme(adapter);
9d5c8243 2510
37680117 2511#ifdef CONFIG_PCI_IOV
fa44f2f1 2512 igb_disable_sriov(pdev);
37680117 2513#endif
559e9c49 2514
28b0759c
AD		 2515 iounmap(hw->hw_addr);
2516 if (hw->flash_address)
2517 iounmap(hw->flash_address);
559e9c49
AD		 2518 pci_release_selected_regions(pdev,
2519 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2520
1128c756 2521 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2522 free_netdev(netdev);
2523
19d5afd4 2524 pci_disable_pcie_error_reporting(pdev);
40a914fa 2525
9d5c8243
AK		 2526 pci_disable_device(pdev);
2527}
2528
a6b623e0
AD		 2529/**
2530 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2531 * @adapter: board private structure to initialize
2532 *
2533 * This function initializes the vf specific data storage and then attempts to
2534 * allocate the VFs. The reason for ordering it this way is because it is much
2535 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2536 * the memory for the VFs.
2537 **/
9f9a12f8 2538static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2539{
2540#ifdef CONFIG_PCI_IOV
2541 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2542 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2543
f96a8a0b
CW		 2544 /* Virtualization features not supported on i210 family. */
2545 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2546 return;
2547
fa44f2f1
GR		 2548 igb_enable_sriov(pdev, max_vfs);
2549 pci_sriov_set_totalvfs(pdev, 7);
0224d663 2550
a6b623e0
AD		 2551#endif /* CONFIG_PCI_IOV */
2552}
2553
fa44f2f1 2554static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2555{
2556 struct e1000_hw *hw = &adapter->hw;
374a542d 2557 u32 max_rss_queues;
9d5c8243 2558
374a542d 2559 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2560 switch (hw->mac.type) {
374a542d
MV		 2561 case e1000_i211:
2562 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2563 break;
2564 case e1000_82575:
f96a8a0b 2565 case e1000_i210:
374a542d
MV		 2566 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2567 break;
2568 case e1000_i350:
2569 /* I350 cannot do RSS and SR-IOV at the same time */
2570 if (!!adapter->vfs_allocated_count) {
2571 max_rss_queues = 1;
2572 break;
2573 }
2574 /* fall through */
2575 case e1000_82576:
2576 if (!!adapter->vfs_allocated_count) {
2577 max_rss_queues = 2;
2578 break;
2579 }
2580 /* fall through */
2581 case e1000_82580:
2582 default:
2583 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2584 break;
374a542d
MV		 2585 }
2586
2587 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2588
2589 /* Determine if we need to pair queues. */
2590 switch (hw->mac.type) {
2591 case e1000_82575:
f96a8a0b 2592 case e1000_i211:
374a542d 2593 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2594 break;
374a542d
MV		 2595 case e1000_82576:
2596 /*
2597 * If VFs are going to be allocated with RSS queues then we
2598 * should pair the queues in order to conserve interrupts due
2599 * to limited supply.
2600 */
2601 if ((adapter->rss_queues > 1) &&
2602 (adapter->vfs_allocated_count > 6))
2603 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2604 /* fall through */
2605 case e1000_82580:
2606 case e1000_i350:
2607 case e1000_i210:
f96a8a0b 2608 default:
374a542d
MV		 2609 /*
2610 * If rss_queues > half of max_rss_queues, pair the queues in
2611 * order to conserve interrupts due to limited supply.
2612 */
2613 if (adapter->rss_queues > (max_rss_queues / 2))
2614 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2615 break;
2616 }
fa44f2f1
GR		 2617}
2618
2619/**
2620 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2621 * @adapter: board private structure to initialize
2622 *
2623 * igb_sw_init initializes the Adapter private data structure.
2624 * Fields are initialized based on PCI device information and
2625 * OS network device settings (MTU size).
2626 **/
2627static int igb_sw_init(struct igb_adapter *adapter)
2628{
2629 struct e1000_hw *hw = &adapter->hw;
2630 struct net_device *netdev = adapter->netdev;
2631 struct pci_dev *pdev = adapter->pdev;
2632
2633 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2634
2635 /* set default ring sizes */
2636 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2637 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2638
2639 /* set default ITR values */
2640 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2641 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2642
2643 /* set default work limits */
2644 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2645
2646 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2647 VLAN_HLEN;
2648 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2649
2650 spin_lock_init(&adapter->stats64_lock);
2651#ifdef CONFIG_PCI_IOV
2652 switch (hw->mac.type) {
2653 case e1000_82576:
2654 case e1000_i350:
2655 if (max_vfs > 7) {
2656 dev_warn(&pdev->dev,
2657 "Maximum of 7 VFs per PF, using max\n");
2658 adapter->vfs_allocated_count = 7;
2659 } else
2660 adapter->vfs_allocated_count = max_vfs;
2661 if (adapter->vfs_allocated_count)
2662 dev_warn(&pdev->dev,
2663 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2664 break;
2665 default:
2666 break;
2667 }
2668#endif /* CONFIG_PCI_IOV */
2669
2670 igb_init_queue_configuration(adapter);
a99955fc 2671
1128c756
CW		 2672 /* Setup and initialize a copy of the hw vlan table array */
2673 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2674 E1000_VLAN_FILTER_TBL_SIZE,
2675 GFP_ATOMIC);
2676
a6b623e0 2677 /* This call may decrease the number of queues */
53c7d064 2678 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2679 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2680 return -ENOMEM;
2681 }
2682
a6b623e0
AD		 2683 igb_probe_vfs(adapter);
2684
9d5c8243
AK		 2685 /* Explicitly disable IRQ since the NIC can be in any state. */
2686 igb_irq_disable(adapter);
2687
f96a8a0b 2688 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2689 adapter->flags &= ~IGB_FLAG_DMAC;
2690
9d5c8243
AK		 2691 set_bit(__IGB_DOWN, &adapter->state);
2692 return 0;
2693}
2694
2695/**
2696 * igb_open - Called when a network interface is made active
2697 * @netdev: network interface device structure
2698 *
2699 * Returns 0 on success, negative value on failure
2700 *
2701 * The open entry point is called when a network interface is made
2702 * active by the system (IFF_UP). At this point all resources needed
2703 * for transmit and receive operations are allocated, the interrupt
2704 * handler is registered with the OS, the watchdog timer is started,
2705 * and the stack is notified that the interface is ready.
2706 **/
749ab2cd 2707static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2708{
2709 struct igb_adapter *adapter = netdev_priv(netdev);
2710 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2711 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2712 int err;
2713 int i;
2714
2715 /* disallow open during test */
749ab2cd
YZ		 2716 if (test_bit(__IGB_TESTING, &adapter->state)) {
2717 WARN_ON(resuming);
9d5c8243 2718 return -EBUSY;
749ab2cd
YZ		 2719 }
2720
2721 if (!resuming)
2722 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2723
b168dfc5
JB		 2724 netif_carrier_off(netdev);
2725
9d5c8243
AK		 2726 /* allocate transmit descriptors */
2727 err = igb_setup_all_tx_resources(adapter);
2728 if (err)
2729 goto err_setup_tx;
2730
2731 /* allocate receive descriptors */
2732 err = igb_setup_all_rx_resources(adapter);
2733 if (err)
2734 goto err_setup_rx;
2735
88a268c1 2736 igb_power_up_link(adapter);
9d5c8243 2737
9d5c8243
AK		 2738 /* before we allocate an interrupt, we must be ready to handle it.
2739 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2740 * as soon as we call pci_request_irq, so we have to setup our
2741 * clean_rx handler before we do so. */
2742 igb_configure(adapter);
2743
2744 err = igb_request_irq(adapter);
2745 if (err)
2746 goto err_req_irq;
2747
0c2cc02e
AD		 2748 /* Notify the stack of the actual queue counts. */
2749 err = netif_set_real_num_tx_queues(adapter->netdev,
2750 adapter->num_tx_queues);
2751 if (err)
2752 goto err_set_queues;
2753
2754 err = netif_set_real_num_rx_queues(adapter->netdev,
2755 adapter->num_rx_queues);
2756 if (err)
2757 goto err_set_queues;
2758
9d5c8243
AK		 2759 /* From here on the code is the same as igb_up() */
2760 clear_bit(__IGB_DOWN, &adapter->state);
2761
0d1ae7f4
AD		 2762 for (i = 0; i < adapter->num_q_vectors; i++)
2763 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2764
2765 /* Clear any pending interrupts. */
2766 rd32(E1000_ICR);
844290e5
PW		 2767
2768 igb_irq_enable(adapter);
2769
d4960307
AD		 2770 /* notify VFs that reset has been completed */
2771 if (adapter->vfs_allocated_count) {
2772 u32 reg_data = rd32(E1000_CTRL_EXT);
2773 reg_data |= E1000_CTRL_EXT_PFRSTD;
2774 wr32(E1000_CTRL_EXT, reg_data);
2775 }
2776
d55b53ff
JK		 2777 netif_tx_start_all_queues(netdev);
2778
749ab2cd
YZ		 2779 if (!resuming)
2780 pm_runtime_put(&pdev->dev);
2781
25568a53
AD		 2782 /* start the watchdog. */
2783 hw->mac.get_link_status = 1;
2784 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2785
2786 return 0;
2787
0c2cc02e
AD		 2788err_set_queues:
2789 igb_free_irq(adapter);
9d5c8243
AK		 2790err_req_irq:
2791 igb_release_hw_control(adapter);
88a268c1 2792 igb_power_down_link(adapter);
9d5c8243
AK		 2793 igb_free_all_rx_resources(adapter);
2794err_setup_rx:
2795 igb_free_all_tx_resources(adapter);
2796err_setup_tx:
2797 igb_reset(adapter);
749ab2cd
YZ		 2798 if (!resuming)
2799 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2800
2801 return err;
2802}
2803
749ab2cd
YZ		 2804static int igb_open(struct net_device *netdev)
2805{
2806 return __igb_open(netdev, false);
2807}
2808
9d5c8243
AK		 2809/**
2810 * igb_close - Disables a network interface
2811 * @netdev: network interface device structure
2812 *
2813 * Returns 0, this is not allowed to fail
2814 *
2815 * The close entry point is called when an interface is de-activated
2816 * by the OS. The hardware is still under the driver's control, but
2817 * needs to be disabled. A global MAC reset is issued to stop the
2818 * hardware, and all transmit and receive resources are freed.
2819 **/
749ab2cd 2820static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2821{
2822 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2823 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2824
2825 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2826
749ab2cd
YZ		 2827 if (!suspending)
2828 pm_runtime_get_sync(&pdev->dev);
2829
2830 igb_down(adapter);
9d5c8243
AK		 2831 igb_free_irq(adapter);
2832
2833 igb_free_all_tx_resources(adapter);
2834 igb_free_all_rx_resources(adapter);
2835
749ab2cd
YZ		 2836 if (!suspending)
2837 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2838 return 0;
2839}
2840
749ab2cd
YZ		 2841static int igb_close(struct net_device *netdev)
2842{
2843 return __igb_close(netdev, false);
2844}
2845
9d5c8243
AK		 2846/**
2847 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2848 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2849 *
2850 * Return 0 on success, negative on failure
2851 **/
80785298 2852int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2853{
59d71989 2854 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2855 int size;
2856
06034649 2857 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2858
2859 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2860 if (!tx_ring->tx_buffer_info)
9d5c8243 2861 goto err;
9d5c8243
AK		 2862
2863 /* round up to nearest 4K */
85e8d004 2864 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2865 tx_ring->size = ALIGN(tx_ring->size, 4096);
2866
5536d210
AD		 2867 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2868 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2869 if (!tx_ring->desc)
2870 goto err;
2871
9d5c8243
AK		 2872 tx_ring->next_to_use = 0;
2873 tx_ring->next_to_clean = 0;
81c2fc22 2874
9d5c8243
AK		 2875 return 0;
2876
2877err:
06034649 2878 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2879 tx_ring->tx_buffer_info = NULL;
2880 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2881 return -ENOMEM;
2882}
2883
2884/**
2885 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2886 * (Descriptors) for all queues
2887 * @adapter: board private structure
2888 *
2889 * Return 0 on success, negative on failure
2890 **/
2891static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2892{
439705e1 2893 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2894 int i, err = 0;
2895
2896 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2897 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2898 if (err) {
439705e1 2899 dev_err(&pdev->dev,
9d5c8243
AK		 2900 "Allocation for Tx Queue %u failed\n", i);
2901 for (i--; i >= 0; i--)
3025a446 2902 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2903 break;
2904 }
2905 }
2906
2907 return err;
2908}
2909
2910/**
85b430b4
AD		 2911 * igb_setup_tctl - configure the transmit control registers
2912 * @adapter: Board private structure
9d5c8243 2913 **/
d7ee5b3a 2914void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2915{
9d5c8243
AK		 2916 struct e1000_hw *hw = &adapter->hw;
2917 u32 tctl;
9d5c8243 2918
85b430b4
AD		 2919 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2920 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2921
2922 /* Program the Transmit Control Register */
9d5c8243
AK		 2923 tctl = rd32(E1000_TCTL);
2924 tctl &= ~E1000_TCTL_CT;
2925 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2926 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2927
2928 igb_config_collision_dist(hw);
2929
9d5c8243
AK		 2930 /* Enable transmits */
2931 tctl |= E1000_TCTL_EN;
2932
2933 wr32(E1000_TCTL, tctl);
2934}
2935
85b430b4
AD		 2936/**
2937 * igb_configure_tx_ring - Configure transmit ring after Reset
2938 * @adapter: board private structure
2939 * @ring: tx ring to configure
2940 *
2941 * Configure a transmit ring after a reset.
2942 **/
d7ee5b3a
AD		 2943void igb_configure_tx_ring(struct igb_adapter *adapter,
2944 struct igb_ring *ring)
85b430b4
AD		 2945{
2946 struct e1000_hw *hw = &adapter->hw;
a74420e0 2947 u32 txdctl = 0;
85b430b4
AD		 2948 u64 tdba = ring->dma;
2949 int reg_idx = ring->reg_idx;
2950
2951 /* disable the queue */
a74420e0 2952 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2953 wrfl();
2954 mdelay(10);
2955
2956 wr32(E1000_TDLEN(reg_idx),
2957 ring->count * sizeof(union e1000_adv_tx_desc));
2958 wr32(E1000_TDBAL(reg_idx),
2959 tdba & 0x00000000ffffffffULL);
2960 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2961
fce99e34 2962 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2963 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2964 writel(0, ring->tail);
85b430b4
AD		 2965
2966 txdctl |= IGB_TX_PTHRESH;
2967 txdctl |= IGB_TX_HTHRESH << 8;
2968 txdctl |= IGB_TX_WTHRESH << 16;
2969
2970 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2971 wr32(E1000_TXDCTL(reg_idx), txdctl);
2972}
2973
2974/**
2975 * igb_configure_tx - Configure transmit Unit after Reset
2976 * @adapter: board private structure
2977 *
2978 * Configure the Tx unit of the MAC after a reset.
2979 **/
2980static void igb_configure_tx(struct igb_adapter *adapter)
2981{
2982 int i;
2983
2984 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2985 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2986}
2987
9d5c8243
AK		 2988/**
2989 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2990 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2991 *
2992 * Returns 0 on success, negative on failure
2993 **/
80785298 2994int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2995{
59d71989 2996 struct device *dev = rx_ring->dev;
f33005a6 2997 int size;
9d5c8243 2998
06034649 2999 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3000
3001 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3002 if (!rx_ring->rx_buffer_info)
9d5c8243 3003 goto err;
9d5c8243 3004
9d5c8243 3005 /* Round up to nearest 4K */
f33005a6 3006 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3007 rx_ring->size = ALIGN(rx_ring->size, 4096);
3008
5536d210
AD		 3009 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3010 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3011 if (!rx_ring->desc)
3012 goto err;
3013
cbc8e55f 3014 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3015 rx_ring->next_to_clean = 0;
3016 rx_ring->next_to_use = 0;
9d5c8243 3017
9d5c8243
AK		 3018 return 0;
3019
3020err:
06034649
AD		 3021 vfree(rx_ring->rx_buffer_info);
3022 rx_ring->rx_buffer_info = NULL;
f33005a6 3023 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3024 return -ENOMEM;
3025}
3026
3027/**
3028 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3029 * (Descriptors) for all queues
3030 * @adapter: board private structure
3031 *
3032 * Return 0 on success, negative on failure
3033 **/
3034static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3035{
439705e1 3036 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3037 int i, err = 0;
3038
3039 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3040 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3041 if (err) {
439705e1 3042 dev_err(&pdev->dev,
9d5c8243
AK		 3043 "Allocation for Rx Queue %u failed\n", i);
3044 for (i--; i >= 0; i--)
3025a446 3045 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3046 break;
3047 }
3048 }
3049
3050 return err;
3051}
3052
06cf2666
AD		 3053/**
3054 * igb_setup_mrqc - configure the multiple receive queue control registers
3055 * @adapter: Board private structure
3056 **/
3057static void igb_setup_mrqc(struct igb_adapter *adapter)
3058{
3059 struct e1000_hw *hw = &adapter->hw;
3060 u32 mrqc, rxcsum;
797fd4be 3061 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3062 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3063 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3064 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3065 0xFA01ACBE };
06cf2666
AD		 3066
3067 /* Fill out hash function seeds */
a57fe23e
AD		 3068 for (j = 0; j < 10; j++)
3069 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3070
a99955fc 3071 num_rx_queues = adapter->rss_queues;
06cf2666 3072
797fd4be
AD		 3073 switch (hw->mac.type) {
3074 case e1000_82575:
3075 shift = 6;
3076 break;
3077 case e1000_82576:
3078 /* 82576 supports 2 RSS queues for SR-IOV */
3079 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3080 shift = 3;
3081 num_rx_queues = 2;
06cf2666 3082 }
797fd4be
AD		 3083 break;
3084 default:
3085 break;
06cf2666
AD		 3086 }
3087
797fd4be
AD		 3088 /*
3089 * Populate the indirection table 4 entries at a time. To do this
3090 * we are generating the results for n and n+2 and then interleaving
3091 * those with the results with n+1 and n+3.
3092 */
3093 for (j = 0; j < 32; j++) {
3094 /* first pass generates n and n+2 */
3095 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3096 u32 reta = (base & 0x07800780) >> (7 - shift);
3097
3098 /* second pass generates n+1 and n+3 */
3099 base += 0x00010001 * num_rx_queues;
3100 reta |= (base & 0x07800780) << (1 + shift);
3101
3102 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3103 }
3104
3105 /*
3106 * Disable raw packet checksumming so that RSS hash is placed in
3107 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3108 * offloads as they are enabled by default
3109 */
3110 rxcsum = rd32(E1000_RXCSUM);
3111 rxcsum |= E1000_RXCSUM_PCSD;
3112
3113 if (adapter->hw.mac.type >= e1000_82576)
3114 /* Enable Receive Checksum Offload for SCTP */
3115 rxcsum |= E1000_RXCSUM_CRCOFL;
3116
3117 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3118 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3119
039454a8
AA		 3120 /* Generate RSS hash based on packet types, TCP/UDP
3121 * port numbers and/or IPv4/v6 src and dst addresses
3122 */
f96a8a0b
CW		 3123 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3124 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3125 E1000_MRQC_RSS_FIELD_IPV6 |
3126 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3127 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3128
039454a8
AA		 3129 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3130 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3131 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3132 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3133
06cf2666
AD		 3134 /* If VMDq is enabled then we set the appropriate mode for that, else
3135 * we default to RSS so that an RSS hash is calculated per packet even
3136 * if we are only using one queue */
3137 if (adapter->vfs_allocated_count) {
3138 if (hw->mac.type > e1000_82575) {
3139 /* Set the default pool for the PF's first queue */
3140 u32 vtctl = rd32(E1000_VT_CTL);
3141 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3142 E1000_VT_CTL_DISABLE_DEF_POOL);
3143 vtctl |= adapter->vfs_allocated_count <<
3144 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3145 wr32(E1000_VT_CTL, vtctl);
3146 }
a99955fc 3147 if (adapter->rss_queues > 1)
f96a8a0b 3148 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3149 else
f96a8a0b 3150 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3151 } else {
f96a8a0b
CW		 3152 if (hw->mac.type != e1000_i211)
3153 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3154 }
3155 igb_vmm_control(adapter);
3156
06cf2666
AD		 3157 wr32(E1000_MRQC, mrqc);
3158}
3159
9d5c8243
AK		 3160/**
3161 * igb_setup_rctl - configure the receive control registers
3162 * @adapter: Board private structure
3163 **/
d7ee5b3a 3164void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3165{
3166 struct e1000_hw *hw = &adapter->hw;
3167 u32 rctl;
9d5c8243
AK		 3168
3169 rctl = rd32(E1000_RCTL);
3170
3171 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3172 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3173
69d728ba 3174 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3175 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3176
87cb7e8c
AK		 3177 /*
3178 * enable stripping of CRC. It's unlikely this will break BMC
3179 * redirection as it did with e1000. Newer features require
3180 * that the HW strips the CRC.
73cd78f1 3181 */
87cb7e8c 3182 rctl |= E1000_RCTL_SECRC;
9d5c8243 3183
559e9c49 3184 /* disable store bad packets and clear size bits. */
ec54d7d6 3185 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3186
6ec43fe6
AD		 3187 /* enable LPE to prevent packets larger than max_frame_size */
3188 rctl |= E1000_RCTL_LPE;
9d5c8243 3189
952f72a8
AD		 3190 /* disable queue 0 to prevent tail write w/o re-config */
3191 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3192
e1739522
AD		 3193 /* Attention!!! For SR-IOV PF driver operations you must enable
3194 * queue drop for all VF and PF queues to prevent head of line blocking
3195 * if an un-trusted VF does not provide descriptors to hardware.
3196 */
3197 if (adapter->vfs_allocated_count) {
e1739522
AD		 3198 /* set all queue drop enable bits */
3199 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3200 }
3201
89eaefb6
BG		 3202 /* This is useful for sniffing bad packets. */
3203 if (adapter->netdev->features & NETIF_F_RXALL) {
3204 /* UPE and MPE will be handled by normal PROMISC logic
3205 * in e1000e_set_rx_mode */
3206 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3207 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3208 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3209
3210 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3211 E1000_RCTL_DPF | /* Allow filtered pause */
3212 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3213 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3214 * and that breaks VLANs.
3215 */
3216 }
3217
9d5c8243
AK		 3218 wr32(E1000_RCTL, rctl);
3219}
3220
7d5753f0
AD		 3221static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3222 int vfn)
3223{
3224 struct e1000_hw *hw = &adapter->hw;
3225 u32 vmolr;
3226
3227 /* if it isn't the PF check to see if VFs are enabled and
3228 * increase the size to support vlan tags */
3229 if (vfn < adapter->vfs_allocated_count &&
3230 adapter->vf_data[vfn].vlans_enabled)
3231 size += VLAN_TAG_SIZE;
3232
3233 vmolr = rd32(E1000_VMOLR(vfn));
3234 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3235 vmolr |= size | E1000_VMOLR_LPE;
3236 wr32(E1000_VMOLR(vfn), vmolr);
3237
3238 return 0;
3239}
3240
e1739522
AD		 3241/**
3242 * igb_rlpml_set - set maximum receive packet size
3243 * @adapter: board private structure
3244 *
3245 * Configure maximum receivable packet size.
3246 **/
3247static void igb_rlpml_set(struct igb_adapter *adapter)
3248{
153285f9 3249 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3250 struct e1000_hw *hw = &adapter->hw;
3251 u16 pf_id = adapter->vfs_allocated_count;
3252
e1739522
AD		 3253 if (pf_id) {
3254 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3255 /*
3256 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3257 * to our max jumbo frame size, in case we need to enable
3258 * jumbo frames on one of the rings later.
3259 * This will not pass over-length frames into the default
3260 * queue because it's gated by the VMOLR.RLPML.
3261 */
7d5753f0 3262 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3263 }
3264
3265 wr32(E1000_RLPML, max_frame_size);
3266}
3267
8151d294
WM		 3268static inline void igb_set_vmolr(struct igb_adapter *adapter,
3269 int vfn, bool aupe)
7d5753f0
AD		 3270{
3271 struct e1000_hw *hw = &adapter->hw;
3272 u32 vmolr;
3273
3274 /*
3275 * This register exists only on 82576 and newer so if we are older then
3276 * we should exit and do nothing
3277 */
3278 if (hw->mac.type < e1000_82576)
3279 return;
3280
3281 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3282 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3283 if (aupe)
3284 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3285 else
3286 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3287
3288 /* clear all bits that might not be set */
3289 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3290
a99955fc 3291 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3292 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3293 /*
3294 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3295 * multicast packets
3296 */
3297 if (vfn <= adapter->vfs_allocated_count)
3298 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3299
3300 wr32(E1000_VMOLR(vfn), vmolr);
3301}
3302
85b430b4
AD		 3303/**
3304 * igb_configure_rx_ring - Configure a receive ring after Reset
3305 * @adapter: board private structure
3306 * @ring: receive ring to be configured
3307 *
3308 * Configure the Rx unit of the MAC after a reset.
3309 **/
d7ee5b3a
AD		 3310void igb_configure_rx_ring(struct igb_adapter *adapter,
3311 struct igb_ring *ring)
85b430b4
AD		 3312{
3313 struct e1000_hw *hw = &adapter->hw;
3314 u64 rdba = ring->dma;
3315 int reg_idx = ring->reg_idx;
a74420e0 3316 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3317
3318 /* disable the queue */
a74420e0 3319 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3320
3321 /* Set DMA base address registers */
3322 wr32(E1000_RDBAL(reg_idx),
3323 rdba & 0x00000000ffffffffULL);
3324 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3325 wr32(E1000_RDLEN(reg_idx),
3326 ring->count * sizeof(union e1000_adv_rx_desc));
3327
3328 /* initialize head and tail */
fce99e34 3329 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3330 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3331 writel(0, ring->tail);
85b430b4 3332
952f72a8 3333 /* set descriptor configuration */
44390ca6 3334 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3335 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3336 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3337 if (hw->mac.type >= e1000_82580)
757b77e2 3338 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3339 /* Only set Drop Enable if we are supporting multiple queues */
3340 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3341 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3342
3343 wr32(E1000_SRRCTL(reg_idx), srrctl);
3344
7d5753f0 3345 /* set filtering for VMDQ pools */
8151d294 3346 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3347
85b430b4
AD		 3348 rxdctl |= IGB_RX_PTHRESH;
3349 rxdctl |= IGB_RX_HTHRESH << 8;
3350 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3351
3352 /* enable receive descriptor fetching */
3353 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3354 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3355}
3356
9d5c8243
AK		 3357/**
3358 * igb_configure_rx - Configure receive Unit after Reset
3359 * @adapter: board private structure
3360 *
3361 * Configure the Rx unit of the MAC after a reset.
3362 **/
3363static void igb_configure_rx(struct igb_adapter *adapter)
3364{
9107584e 3365 int i;
9d5c8243 3366
68d480c4
AD		 3367 /* set UTA to appropriate mode */
3368 igb_set_uta(adapter);
3369
26ad9178
AD		 3370 /* set the correct pool for the PF default MAC address in entry 0 */
3371 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3372 adapter->vfs_allocated_count);
3373
06cf2666
AD		 3374 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3375 * the Base and Length of the Rx Descriptor Ring */
3376 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3377 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3378}
3379
3380/**
3381 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3382 * @tx_ring: Tx descriptor ring for a specific queue
3383 *
3384 * Free all transmit software resources
3385 **/
68fd9910 3386void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3387{
3b644cf6 3388 igb_clean_tx_ring(tx_ring);
9d5c8243 3389
06034649
AD		 3390 vfree(tx_ring->tx_buffer_info);
3391 tx_ring->tx_buffer_info = NULL;
9d5c8243 3392
439705e1
AD		 3393 /* if not set, then don't free */
3394 if (!tx_ring->desc)
3395 return;
3396
59d71989
AD		 3397 dma_free_coherent(tx_ring->dev, tx_ring->size,
3398 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3399
3400 tx_ring->desc = NULL;
3401}
3402
3403/**
3404 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3405 * @adapter: board private structure
3406 *
3407 * Free all transmit software resources
3408 **/
3409static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3410{
3411 int i;
3412
3413 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3414 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3415}
3416
ebe42d16
AD		 3417void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3418 struct igb_tx_buffer *tx_buffer)
3419{
3420 if (tx_buffer->skb) {
3421 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3422 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3423 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3424 dma_unmap_addr(tx_buffer, dma),
3425 dma_unmap_len(tx_buffer, len),
ebe42d16 3426 DMA_TO_DEVICE);
c9f14bf3 3427 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3428 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3429 dma_unmap_addr(tx_buffer, dma),
3430 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3431 DMA_TO_DEVICE);
3432 }
3433 tx_buffer->next_to_watch = NULL;
3434 tx_buffer->skb = NULL;
c9f14bf3 3435 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3436 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3437}
3438
3439/**
3440 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3441 * @tx_ring: ring to be cleaned
3442 **/
3b644cf6 3443static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3444{
06034649 3445 struct igb_tx_buffer *buffer_info;
9d5c8243 3446 unsigned long size;
6ad4edfc 3447 u16 i;
9d5c8243 3448
06034649 3449 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3450 return;
3451 /* Free all the Tx ring sk_buffs */
3452
3453 for (i = 0; i < tx_ring->count; i++) {
06034649 3454 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3455 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3456 }
3457
dad8a3b3
JF		 3458 netdev_tx_reset_queue(txring_txq(tx_ring));
3459
06034649
AD		 3460 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3461 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3462
3463 /* Zero out the descriptor ring */
9d5c8243
AK		 3464 memset(tx_ring->desc, 0, tx_ring->size);
3465
3466 tx_ring->next_to_use = 0;
3467 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3468}
3469
3470/**
3471 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3472 * @adapter: board private structure
3473 **/
3474static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3475{
3476 int i;
3477
3478 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3479 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3480}
3481
3482/**
3483 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3484 * @rx_ring: ring to clean the resources from
3485 *
3486 * Free all receive software resources
3487 **/
68fd9910 3488void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3489{
3b644cf6 3490 igb_clean_rx_ring(rx_ring);
9d5c8243 3491
06034649
AD		 3492 vfree(rx_ring->rx_buffer_info);
3493 rx_ring->rx_buffer_info = NULL;
9d5c8243 3494
439705e1
AD		 3495 /* if not set, then don't free */
3496 if (!rx_ring->desc)
3497 return;
3498
59d71989
AD		 3499 dma_free_coherent(rx_ring->dev, rx_ring->size,
3500 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3501
3502 rx_ring->desc = NULL;
3503}
3504
3505/**
3506 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3507 * @adapter: board private structure
3508 *
3509 * Free all receive software resources
3510 **/
3511static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3512{
3513 int i;
3514
3515 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3516 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3517}
3518
3519/**
3520 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3521 * @rx_ring: ring to free buffers from
3522 **/
3b644cf6 3523static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3524{
9d5c8243 3525 unsigned long size;
c023cd88 3526 u16 i;
9d5c8243 3527
1a1c225b
AD		 3528 if (rx_ring->skb)
3529 dev_kfree_skb(rx_ring->skb);
3530 rx_ring->skb = NULL;
3531
06034649 3532 if (!rx_ring->rx_buffer_info)
9d5c8243 3533 return;
439705e1 3534
9d5c8243
AK		 3535 /* Free all the Rx ring sk_buffs */
3536 for (i = 0; i < rx_ring->count; i++) {
06034649 3537 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3538
cbc8e55f
AD		 3539 if (!buffer_info->page)
3540 continue;
3541
3542 dma_unmap_page(rx_ring->dev,
3543 buffer_info->dma,
3544 PAGE_SIZE,
3545 DMA_FROM_DEVICE);
3546 __free_page(buffer_info->page);
3547
1a1c225b 3548 buffer_info->page = NULL;
9d5c8243
AK		 3549 }
3550
06034649
AD		 3551 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3552 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3553
3554 /* Zero out the descriptor ring */
3555 memset(rx_ring->desc, 0, rx_ring->size);
3556
cbc8e55f 3557 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3558 rx_ring->next_to_clean = 0;
3559 rx_ring->next_to_use = 0;
9d5c8243
AK		 3560}
3561
3562/**
3563 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3564 * @adapter: board private structure
3565 **/
3566static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3567{
3568 int i;
3569
3570 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3571 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3572}
3573
3574/**
3575 * igb_set_mac - Change the Ethernet Address of the NIC
3576 * @netdev: network interface device structure
3577 * @p: pointer to an address structure
3578 *
3579 * Returns 0 on success, negative on failure
3580 **/
3581static int igb_set_mac(struct net_device *netdev, void *p)
3582{
3583 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3584 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3585 struct sockaddr *addr = p;
3586
3587 if (!is_valid_ether_addr(addr->sa_data))
3588 return -EADDRNOTAVAIL;
3589
3590 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3591 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3592
26ad9178
AD		 3593 /* set the correct pool for the new PF MAC address in entry 0 */
3594 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3595 adapter->vfs_allocated_count);
e1739522 3596
9d5c8243
AK		 3597 return 0;
3598}
3599
3600/**
68d480c4 3601 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3602 * @netdev: network interface device structure
3603 *
68d480c4
AD		 3604 * Writes multicast address list to the MTA hash table.
3605 * Returns: -ENOMEM on failure
3606 * 0 on no addresses written
3607 * X on writing X addresses to MTA
9d5c8243 3608 **/
68d480c4 3609static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3610{
3611 struct igb_adapter *adapter = netdev_priv(netdev);
3612 struct e1000_hw *hw = &adapter->hw;
22bedad3 3613 struct netdev_hw_addr *ha;
68d480c4 3614 u8 *mta_list;
9d5c8243
AK		 3615 int i;
3616
4cd24eaf 3617 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3618 /* nothing to program, so clear mc list */
3619 igb_update_mc_addr_list(hw, NULL, 0);
3620 igb_restore_vf_multicasts(adapter);
3621 return 0;
3622 }
9d5c8243 3623
4cd24eaf 3624 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3625 if (!mta_list)
3626 return -ENOMEM;
ff41f8dc 3627
68d480c4 3628 /* The shared function expects a packed array of only addresses. */
48e2f183 3629 i = 0;
22bedad3
JP		 3630 netdev_for_each_mc_addr(ha, netdev)
3631 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3632
68d480c4
AD		 3633 igb_update_mc_addr_list(hw, mta_list, i);
3634 kfree(mta_list);
3635
4cd24eaf 3636 return netdev_mc_count(netdev);
68d480c4
AD		 3637}
3638
3639/**
3640 * igb_write_uc_addr_list - write unicast addresses to RAR table
3641 * @netdev: network interface device structure
3642 *
3643 * Writes unicast address list to the RAR table.
3644 * Returns: -ENOMEM on failure/insufficient address space
3645 * 0 on no addresses written
3646 * X on writing X addresses to the RAR table
3647 **/
3648static int igb_write_uc_addr_list(struct net_device *netdev)
3649{
3650 struct igb_adapter *adapter = netdev_priv(netdev);
3651 struct e1000_hw *hw = &adapter->hw;
3652 unsigned int vfn = adapter->vfs_allocated_count;
3653 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3654 int count = 0;
3655
3656 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3657 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3658 return -ENOMEM;
9d5c8243 3659
32e7bfc4 3660 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3661 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3662
3663 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3664 if (!rar_entries)
3665 break;
26ad9178
AD		 3666 igb_rar_set_qsel(adapter, ha->addr,
3667 rar_entries--,
68d480c4
AD		 3668 vfn);
3669 count++;
ff41f8dc
AD		 3670 }
3671 }
3672 /* write the addresses in reverse order to avoid write combining */
3673 for (; rar_entries > 0 ; rar_entries--) {
3674 wr32(E1000_RAH(rar_entries), 0);
3675 wr32(E1000_RAL(rar_entries), 0);
3676 }
3677 wrfl();
3678
68d480c4
AD		 3679 return count;
3680}
3681
3682/**
3683 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3684 * @netdev: network interface device structure
3685 *
3686 * The set_rx_mode entry point is called whenever the unicast or multicast
3687 * address lists or the network interface flags are updated. This routine is
3688 * responsible for configuring the hardware for proper unicast, multicast,
3689 * promiscuous mode, and all-multi behavior.
3690 **/
3691static void igb_set_rx_mode(struct net_device *netdev)
3692{
3693 struct igb_adapter *adapter = netdev_priv(netdev);
3694 struct e1000_hw *hw = &adapter->hw;
3695 unsigned int vfn = adapter->vfs_allocated_count;
3696 u32 rctl, vmolr = 0;
3697 int count;
3698
3699 /* Check for Promiscuous and All Multicast modes */
3700 rctl = rd32(E1000_RCTL);
3701
3702 /* clear the effected bits */
3703 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3704
3705 if (netdev->flags & IFF_PROMISC) {
3706 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3707 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3708 } else {
3709 if (netdev->flags & IFF_ALLMULTI) {
3710 rctl |= E1000_RCTL_MPE;
3711 vmolr |= E1000_VMOLR_MPME;
3712 } else {
3713 /*
3714 * Write addresses to the MTA, if the attempt fails
25985edc 3715 * then we should just turn on promiscuous mode so
68d480c4
AD		 3716 * that we can at least receive multicast traffic
3717 */
3718 count = igb_write_mc_addr_list(netdev);
3719 if (count < 0) {
3720 rctl |= E1000_RCTL_MPE;
3721 vmolr |= E1000_VMOLR_MPME;
3722 } else if (count) {
3723 vmolr |= E1000_VMOLR_ROMPE;
3724 }
3725 }
3726 /*
3727 * Write addresses to available RAR registers, if there is not
3728 * sufficient space to store all the addresses then enable
25985edc 3729 * unicast promiscuous mode
68d480c4
AD		 3730 */
3731 count = igb_write_uc_addr_list(netdev);
3732 if (count < 0) {
3733 rctl |= E1000_RCTL_UPE;
3734 vmolr |= E1000_VMOLR_ROPE;
3735 }
3736 rctl |= E1000_RCTL_VFE;
28fc06f5 3737 }
68d480c4 3738 wr32(E1000_RCTL, rctl);
28fc06f5 3739
68d480c4
AD		 3740 /*
3741 * In order to support SR-IOV and eventually VMDq it is necessary to set
3742 * the VMOLR to enable the appropriate modes. Without this workaround
3743 * we will have issues with VLAN tag stripping not being done for frames
3744 * that are only arriving because we are the default pool
3745 */
f96a8a0b 3746 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3747 return;
9d5c8243 3748
68d480c4
AD		 3749 vmolr |= rd32(E1000_VMOLR(vfn)) &
3750 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3751 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3752 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3753}
3754
13800469
GR		 3755static void igb_check_wvbr(struct igb_adapter *adapter)
3756{
3757 struct e1000_hw *hw = &adapter->hw;
3758 u32 wvbr = 0;
3759
3760 switch (hw->mac.type) {
3761 case e1000_82576:
3762 case e1000_i350:
3763 if (!(wvbr = rd32(E1000_WVBR)))
3764 return;
3765 break;
3766 default:
3767 break;
3768 }
3769
3770 adapter->wvbr |= wvbr;
3771}
3772
3773#define IGB_STAGGERED_QUEUE_OFFSET 8
3774
3775static void igb_spoof_check(struct igb_adapter *adapter)
3776{
3777 int j;
3778
3779 if (!adapter->wvbr)
3780 return;
3781
3782 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3783 if (adapter->wvbr & (1 << j) ||
3784 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3785 dev_warn(&adapter->pdev->dev,
3786 "Spoof event(s) detected on VF %d\n", j);
3787 adapter->wvbr &=
3788 ~((1 << j) |
3789 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3790 }
3791 }
3792}
3793
9d5c8243
AK		 3794/* Need to wait a few seconds after link up to get diagnostic information from
3795 * the phy */
3796static void igb_update_phy_info(unsigned long data)
3797{
3798 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3799 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3800}
3801
4d6b725e
AD		 3802/**
3803 * igb_has_link - check shared code for link and determine up/down
3804 * @adapter: pointer to driver private info
3805 **/
3145535a 3806bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3807{
3808 struct e1000_hw *hw = &adapter->hw;
3809 bool link_active = false;
3810 s32 ret_val = 0;
3811
3812 /* get_link_status is set on LSC (link status) interrupt or
3813 * rx sequence error interrupt. get_link_status will stay
3814 * false until the e1000_check_for_link establishes link
3815 * for copper adapters ONLY
3816 */
3817 switch (hw->phy.media_type) {
3818 case e1000_media_type_copper:
3819 if (hw->mac.get_link_status) {
3820 ret_val = hw->mac.ops.check_for_link(hw);
3821 link_active = !hw->mac.get_link_status;
3822 } else {
3823 link_active = true;
3824 }
3825 break;
4d6b725e
AD		 3826 case e1000_media_type_internal_serdes:
3827 ret_val = hw->mac.ops.check_for_link(hw);
3828 link_active = hw->mac.serdes_has_link;
3829 break;
3830 default:
3831 case e1000_media_type_unknown:
3832 break;
3833 }
3834
3835 return link_active;
3836}
3837
563988dc
SA		 3838static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3839{
3840 bool ret = false;
3841 u32 ctrl_ext, thstat;
3842
f96a8a0b 3843 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3844 if (hw->mac.type == e1000_i350) {
3845 thstat = rd32(E1000_THSTAT);
3846 ctrl_ext = rd32(E1000_CTRL_EXT);
3847
3848 if ((hw->phy.media_type == e1000_media_type_copper) &&
3849 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3850 ret = !!(thstat & event);
3851 }
3852 }
3853
3854 return ret;
3855}
3856
9d5c8243
AK		 3857/**
3858 * igb_watchdog - Timer Call-back
3859 * @data: pointer to adapter cast into an unsigned long
3860 **/
3861static void igb_watchdog(unsigned long data)
3862{
3863 struct igb_adapter *adapter = (struct igb_adapter *)data;
3864 /* Do the rest outside of interrupt context */
3865 schedule_work(&adapter->watchdog_task);
3866}
3867
3868static void igb_watchdog_task(struct work_struct *work)
3869{
3870 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3871 struct igb_adapter,
3872 watchdog_task);
9d5c8243 3873 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3874 struct net_device *netdev = adapter->netdev;
563988dc 3875 u32 link;
7a6ea550 3876 int i;
9d5c8243 3877
4d6b725e 3878 link = igb_has_link(adapter);
9d5c8243 3879 if (link) {
749ab2cd
YZ		 3880 /* Cancel scheduled suspend requests. */
3881 pm_runtime_resume(netdev->dev.parent);
3882
9d5c8243
AK		 3883 if (!netif_carrier_ok(netdev)) {
3884 u32 ctrl;
330a6d6a
AD		 3885 hw->mac.ops.get_speed_and_duplex(hw,
3886 &adapter->link_speed,
3887 &adapter->link_duplex);
9d5c8243
AK		 3888
3889 ctrl = rd32(E1000_CTRL);
527d47c1 3890 /* Links status message must follow this format */
876d2d6f
JK		 3891 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3892 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3893 netdev->name,
3894 adapter->link_speed,
3895 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3896 "Full" : "Half",
3897 (ctrl & E1000_CTRL_TFCE) &&
3898 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3899 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3900 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3901
563988dc 3902 /* check for thermal sensor event */
876d2d6f
JK		 3903 if (igb_thermal_sensor_event(hw,
3904 E1000_THSTAT_LINK_THROTTLE)) {
3905 netdev_info(netdev, "The network adapter link "
3906 "speed was downshifted because it "
3907 "overheated\n");
7ef5ed1c 3908 }
563988dc 3909
d07f3e37 3910 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3911 adapter->tx_timeout_factor = 1;
3912 switch (adapter->link_speed) {
3913 case SPEED_10:
9d5c8243
AK		 3914 adapter->tx_timeout_factor = 14;
3915 break;
3916 case SPEED_100:
9d5c8243
AK		 3917 /* maybe add some timeout factor ? */
3918 break;
3919 }
3920
3921 netif_carrier_on(netdev);
9d5c8243 3922
4ae196df 3923 igb_ping_all_vfs(adapter);
17dc566c 3924 igb_check_vf_rate_limit(adapter);
4ae196df 3925
4b1a9877 3926 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3927 if (!test_bit(__IGB_DOWN, &adapter->state))
3928 mod_timer(&adapter->phy_info_timer,
3929 round_jiffies(jiffies + 2 * HZ));
3930 }
3931 } else {
3932 if (netif_carrier_ok(netdev)) {
3933 adapter->link_speed = 0;
3934 adapter->link_duplex = 0;
563988dc
SA		 3935
3936 /* check for thermal sensor event */
876d2d6f
JK		 3937 if (igb_thermal_sensor_event(hw,
3938 E1000_THSTAT_PWR_DOWN)) {
3939 netdev_err(netdev, "The network adapter was "
3940 "stopped because it overheated\n");
7ef5ed1c 3941 }
563988dc 3942
527d47c1
AD		 3943 /* Links status message must follow this format */
3944 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3945 netdev->name);
9d5c8243 3946 netif_carrier_off(netdev);
4b1a9877 3947
4ae196df
AD		 3948 igb_ping_all_vfs(adapter);
3949
4b1a9877 3950 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3951 if (!test_bit(__IGB_DOWN, &adapter->state))
3952 mod_timer(&adapter->phy_info_timer,
3953 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3954
3955 pm_schedule_suspend(netdev->dev.parent,
3956 MSEC_PER_SEC * 5);
9d5c8243
AK		 3957 }
3958 }
3959
12dcd86b
ED		 3960 spin_lock(&adapter->stats64_lock);
3961 igb_update_stats(adapter, &adapter->stats64);
3962 spin_unlock(&adapter->stats64_lock);
9d5c8243 3963
dbabb065 3964 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3965 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3966 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3967 /* We've lost link, so the controller stops DMA,
3968 * but we've got queued Tx work that's never going
3969 * to get done, so reset controller to flush Tx.
3970 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3971 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3972 adapter->tx_timeout_count++;
3973 schedule_work(&adapter->reset_task);
3974 /* return immediately since reset is imminent */
3975 return;
3976 }
9d5c8243 3977 }
9d5c8243 3978
dbabb065 3979 /* Force detection of hung controller every watchdog period */
6d095fa8 3980 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3981 }
f7ba205e 3982
9d5c8243 3983 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3984 if (adapter->msix_entries) {
047e0030 3985 u32 eics = 0;
0d1ae7f4
AD		 3986 for (i = 0; i < adapter->num_q_vectors; i++)
3987 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3988 wr32(E1000_EICS, eics);
3989 } else {
3990 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3991 }
9d5c8243 3992
13800469
GR		 3993 igb_spoof_check(adapter);
3994
9d5c8243
AK		 3995 /* Reset the timer */
3996 if (!test_bit(__IGB_DOWN, &adapter->state))
3997 mod_timer(&adapter->watchdog_timer,
3998 round_jiffies(jiffies + 2 * HZ));
3999}
4000
4001enum latency_range {
4002 lowest_latency = 0,
4003 low_latency = 1,
4004 bulk_latency = 2,
4005 latency_invalid = 255
4006};
4007
6eb5a7f1
AD		 4008/**
4009 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4010 *
4011 * Stores a new ITR value based on strictly on packet size. This
4012 * algorithm is less sophisticated than that used in igb_update_itr,
4013 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 4014 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 4015 * were determined based on theoretical maximum wire speed and testing
4016 * data, in order to minimize response time while increasing bulk
4017 * throughput.
4018 * This functionality is controlled by the InterruptThrottleRate module
4019 * parameter (see igb_param.c)
4020 * NOTE: This function is called only when operating in a multiqueue
4021 * receive environment.
047e0030 4022 * @q_vector: pointer to q_vector
6eb5a7f1 4023 **/
047e0030 4024static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4025{
047e0030 4026 int new_val = q_vector->itr_val;
6eb5a7f1 4027 int avg_wire_size = 0;
047e0030 4028 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4029 unsigned int packets;
9d5c8243 4030
6eb5a7f1
AD		 4031 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4032 * ints/sec - ITR timer value of 120 ticks.
4033 */
4034 if (adapter->link_speed != SPEED_1000) {
0ba82994 4035 new_val = IGB_4K_ITR;
6eb5a7f1 4036 goto set_itr_val;
9d5c8243 4037 }
047e0030 4038
0ba82994
AD		 4039 packets = q_vector->rx.total_packets;
4040 if (packets)
4041 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4042
0ba82994
AD		 4043 packets = q_vector->tx.total_packets;
4044 if (packets)
4045 avg_wire_size = max_t(u32, avg_wire_size,
4046 q_vector->tx.total_bytes / packets);
047e0030
AD		 4047
4048 /* if avg_wire_size isn't set no work was done */
4049 if (!avg_wire_size)
4050 goto clear_counts;
9d5c8243 4051
6eb5a7f1
AD		 4052 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4053 avg_wire_size += 24;
4054
4055 /* Don't starve jumbo frames */
4056 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4057
6eb5a7f1
AD		 4058 /* Give a little boost to mid-size frames */
4059 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4060 new_val = avg_wire_size / 3;
4061 else
4062 new_val = avg_wire_size / 2;
9d5c8243 4063
0ba82994
AD		 4064 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4065 if (new_val < IGB_20K_ITR &&
4066 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4067 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4068 new_val = IGB_20K_ITR;
abe1c363 4069
6eb5a7f1 4070set_itr_val:
047e0030
AD		 4071 if (new_val != q_vector->itr_val) {
4072 q_vector->itr_val = new_val;
4073 q_vector->set_itr = 1;
9d5c8243 4074 }
6eb5a7f1 4075clear_counts:
0ba82994
AD		 4076 q_vector->rx.total_bytes = 0;
4077 q_vector->rx.total_packets = 0;
4078 q_vector->tx.total_bytes = 0;
4079 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4080}
4081
4082/**
4083 * igb_update_itr - update the dynamic ITR value based on statistics
4084 * Stores a new ITR value based on packets and byte
4085 * counts during the last interrupt. The advantage of per interrupt
4086 * computation is faster updates and more accurate ITR for the current
4087 * traffic pattern. Constants in this function were computed
4088 * based on theoretical maximum wire speed and thresholds were set based
4089 * on testing data as well as attempting to minimize response time
4090 * while increasing bulk throughput.
4091 * this functionality is controlled by the InterruptThrottleRate module
4092 * parameter (see igb_param.c)
4093 * NOTE: These calculations are only valid when operating in a single-
4094 * queue environment.
0ba82994
AD		 4095 * @q_vector: pointer to q_vector
4096 * @ring_container: ring info to update the itr for
9d5c8243 4097 **/
0ba82994
AD		 4098static void igb_update_itr(struct igb_q_vector *q_vector,
4099 struct igb_ring_container *ring_container)
9d5c8243 4100{
0ba82994
AD		 4101 unsigned int packets = ring_container->total_packets;
4102 unsigned int bytes = ring_container->total_bytes;
4103 u8 itrval = ring_container->itr;
9d5c8243 4104
0ba82994 4105 /* no packets, exit with status unchanged */
9d5c8243 4106 if (packets == 0)
0ba82994 4107 return;
9d5c8243 4108
0ba82994 4109 switch (itrval) {
9d5c8243
AK		 4110 case lowest_latency:
4111 /* handle TSO and jumbo frames */
4112 if (bytes/packets > 8000)
0ba82994 4113 itrval = bulk_latency;
9d5c8243 4114 else if ((packets < 5) && (bytes > 512))
0ba82994 4115 itrval = low_latency;
9d5c8243
AK		 4116 break;
4117 case low_latency: /* 50 usec aka 20000 ints/s */
4118 if (bytes > 10000) {
4119 /* this if handles the TSO accounting */
4120 if (bytes/packets > 8000) {
0ba82994 4121 itrval = bulk_latency;
9d5c8243 4122 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4123 itrval = bulk_latency;
9d5c8243 4124 } else if ((packets > 35)) {
0ba82994 4125 itrval = lowest_latency;
9d5c8243
AK		 4126 }
4127 } else if (bytes/packets > 2000) {
0ba82994 4128 itrval = bulk_latency;
9d5c8243 4129 } else if (packets <= 2 && bytes < 512) {
0ba82994 4130 itrval = lowest_latency;
9d5c8243
AK		 4131 }
4132 break;
4133 case bulk_latency: /* 250 usec aka 4000 ints/s */
4134 if (bytes > 25000) {
4135 if (packets > 35)
0ba82994 4136 itrval = low_latency;
1e5c3d21 4137 } else if (bytes < 1500) {
0ba82994 4138 itrval = low_latency;
9d5c8243
AK		 4139 }
4140 break;
4141 }
4142
0ba82994
AD		 4143 /* clear work counters since we have the values we need */
4144 ring_container->total_bytes = 0;
4145 ring_container->total_packets = 0;
4146
4147 /* write updated itr to ring container */
4148 ring_container->itr = itrval;
9d5c8243
AK		 4149}
4150
0ba82994 4151static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4152{
0ba82994 4153 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4154 u32 new_itr = q_vector->itr_val;
0ba82994 4155 u8 current_itr = 0;
9d5c8243
AK		 4156
4157 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4158 if (adapter->link_speed != SPEED_1000) {
4159 current_itr = 0;
0ba82994 4160 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4161 goto set_itr_now;
4162 }
4163
0ba82994
AD		 4164 igb_update_itr(q_vector, &q_vector->tx);
4165 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4166
0ba82994 4167 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4168
6eb5a7f1 4169 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4170 if (current_itr == lowest_latency &&
4171 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4172 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4173 current_itr = low_latency;
4174
9d5c8243
AK		 4175 switch (current_itr) {
4176 /* counts and packets in update_itr are dependent on these numbers */
4177 case lowest_latency:
0ba82994 4178 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4179 break;
4180 case low_latency:
0ba82994 4181 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4182 break;
4183 case bulk_latency:
0ba82994 4184 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4185 break;
4186 default:
4187 break;
4188 }
4189
4190set_itr_now:
047e0030 4191 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4192 /* this attempts to bias the interrupt rate towards Bulk
4193 * by adding intermediate steps when interrupt rate is
4194 * increasing */
047e0030
AD		 4195 new_itr = new_itr > q_vector->itr_val ?
4196 max((new_itr * q_vector->itr_val) /
4197 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 4198 new_itr) :
9d5c8243
AK		 4199 new_itr;
4200 /* Don't write the value here; it resets the adapter's
4201 * internal timer, and causes us to delay far longer than
4202 * we should between interrupts. Instead, we write the ITR
4203 * value at the beginning of the next interrupt so the timing
4204 * ends up being correct.
4205 */
047e0030
AD		 4206 q_vector->itr_val = new_itr;
4207 q_vector->set_itr = 1;
9d5c8243 4208 }
9d5c8243
AK		 4209}
4210
c50b52a0
SH		 4211static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4212 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4213{
4214 struct e1000_adv_tx_context_desc *context_desc;
4215 u16 i = tx_ring->next_to_use;
4216
4217 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4218
4219 i++;
4220 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4221
4222 /* set bits to identify this as an advanced context descriptor */
4223 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4224
4225 /* For 82575, context index must be unique per ring. */
866cff06 4226 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4227 mss_l4len_idx |= tx_ring->reg_idx << 4;
4228
4229 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4230 context_desc->seqnum_seed = 0;
4231 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4232 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4233}
4234
7af40ad9
AD		 4235static int igb_tso(struct igb_ring *tx_ring,
4236 struct igb_tx_buffer *first,
4237 u8 *hdr_len)
9d5c8243 4238{
7af40ad9 4239 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4240 u32 vlan_macip_lens, type_tucmd;
4241 u32 mss_l4len_idx, l4len;
4242
ed6aa105
AD		 4243 if (skb->ip_summed != CHECKSUM_PARTIAL)
4244 return 0;
4245
7d13a7d0
AD		 4246 if (!skb_is_gso(skb))
4247 return 0;
9d5c8243
AK		 4248
4249 if (skb_header_cloned(skb)) {
7af40ad9 4250 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4251 if (err)
4252 return err;
4253 }
4254
7d13a7d0
AD		 4255 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4256 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4257
7af40ad9 4258 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4259 struct iphdr *iph = ip_hdr(skb);
4260 iph->tot_len = 0;
4261 iph->check = 0;
4262 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4263 iph->daddr, 0,
4264 IPPROTO_TCP,
4265 0);
7d13a7d0 4266 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4267 first->tx_flags |= IGB_TX_FLAGS_TSO |
4268 IGB_TX_FLAGS_CSUM |
4269 IGB_TX_FLAGS_IPV4;
8e1e8a47 4270 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4271 ipv6_hdr(skb)->payload_len = 0;
4272 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4273 &ipv6_hdr(skb)->daddr,
4274 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4275 first->tx_flags |= IGB_TX_FLAGS_TSO |
4276 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4277 }
4278
7af40ad9 4279 /* compute header lengths */
7d13a7d0
AD		 4280 l4len = tcp_hdrlen(skb);
4281 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4282
7af40ad9
AD		 4283 /* update gso size and bytecount with header size */
4284 first->gso_segs = skb_shinfo(skb)->gso_segs;
4285 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4286
9d5c8243 4287 /* MSS L4LEN IDX */
7d13a7d0
AD		 4288 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4289 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4290
7d13a7d0
AD		 4291 /* VLAN MACLEN IPLEN */
4292 vlan_macip_lens = skb_network_header_len(skb);
4293 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4294 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4295
7d13a7d0 4296 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4297
7d13a7d0 4298 return 1;
9d5c8243
AK		 4299}
4300
7af40ad9 4301static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4302{
7af40ad9 4303 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4304 u32 vlan_macip_lens = 0;
4305 u32 mss_l4len_idx = 0;
4306 u32 type_tucmd = 0;
9d5c8243 4307
7d13a7d0 4308 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4309 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4310 return;
7d13a7d0
AD		 4311 } else {
4312 u8 l4_hdr = 0;
7af40ad9 4313 switch (first->protocol) {
7d13a7d0
AD		 4314 case __constant_htons(ETH_P_IP):
4315 vlan_macip_lens |= skb_network_header_len(skb);
4316 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4317 l4_hdr = ip_hdr(skb)->protocol;
4318 break;
4319 case __constant_htons(ETH_P_IPV6):
4320 vlan_macip_lens |= skb_network_header_len(skb);
4321 l4_hdr = ipv6_hdr(skb)->nexthdr;
4322 break;
4323 default:
4324 if (unlikely(net_ratelimit())) {
4325 dev_warn(tx_ring->dev,
4326 "partial checksum but proto=%x!\n",
7af40ad9 4327 first->protocol);
fa4a7ef3 4328 }
7d13a7d0
AD		 4329 break;
4330 }
fa4a7ef3 4331
7d13a7d0
AD		 4332 switch (l4_hdr) {
4333 case IPPROTO_TCP:
4334 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4335 mss_l4len_idx = tcp_hdrlen(skb) <<
4336 E1000_ADVTXD_L4LEN_SHIFT;
4337 break;
4338 case IPPROTO_SCTP:
4339 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4340 mss_l4len_idx = sizeof(struct sctphdr) <<
4341 E1000_ADVTXD_L4LEN_SHIFT;
4342 break;
4343 case IPPROTO_UDP:
4344 mss_l4len_idx = sizeof(struct udphdr) <<
4345 E1000_ADVTXD_L4LEN_SHIFT;
4346 break;
4347 default:
4348 if (unlikely(net_ratelimit())) {
4349 dev_warn(tx_ring->dev,
4350 "partial checksum but l4 proto=%x!\n",
4351 l4_hdr);
44b0cda3 4352 }
7d13a7d0 4353 break;
9d5c8243 4354 }
7af40ad9
AD		 4355
4356 /* update TX checksum flag */
4357 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4358 }
9d5c8243 4359
7d13a7d0 4360 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4361 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4362
7d13a7d0 4363 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4364}
4365
1d9daf45
AD		 4366#define IGB_SET_FLAG(_input, _flag, _result) \
4367 ((_flag <= _result) ? \
4368 ((u32)(_input & _flag) * (_result / _flag)) : \
4369 ((u32)(_input & _flag) / (_flag / _result)))
4370
4371static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4372{
4373 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4374 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4375 E1000_ADVTXD_DCMD_DEXT |
4376 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4377
4378 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4379 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4380 (E1000_ADVTXD_DCMD_VLE));
4381
4382 /* set segmentation bits for TSO */
4383 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4384 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4385
4386 /* set timestamp bit if present */
1d9daf45
AD		 4387 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4388 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4389
1d9daf45
AD		 4390 /* insert frame checksum */
4391 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4392
4393 return cmd_type;
4394}
4395
7af40ad9
AD		 4396static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4397 union e1000_adv_tx_desc *tx_desc,
4398 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4399{
4400 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4401
1d9daf45
AD		 4402 /* 82575 requires a unique index per ring */
4403 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4404 olinfo_status |= tx_ring->reg_idx << 4;
4405
4406 /* insert L4 checksum */
1d9daf45
AD		 4407 olinfo_status |= IGB_SET_FLAG(tx_flags,
4408 IGB_TX_FLAGS_CSUM,
4409 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4410
1d9daf45
AD		 4411 /* insert IPv4 checksum */
4412 olinfo_status |= IGB_SET_FLAG(tx_flags,
4413 IGB_TX_FLAGS_IPV4,
4414 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4415
7af40ad9 4416 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4417}
4418
ebe42d16
AD		 4419/*
4420 * The largest size we can write to the descriptor is 65535. In order to
4421 * maintain a power of two alignment we have to limit ourselves to 32K.
4422 */
4423#define IGB_MAX_TXD_PWR 15
7af40ad9 4424#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4425
7af40ad9
AD		 4426static void igb_tx_map(struct igb_ring *tx_ring,
4427 struct igb_tx_buffer *first,
ebe42d16 4428 const u8 hdr_len)
9d5c8243 4429{
7af40ad9 4430 struct sk_buff *skb = first->skb;
c9f14bf3 4431 struct igb_tx_buffer *tx_buffer;
ebe42d16 4432 union e1000_adv_tx_desc *tx_desc;
80d0759e 4433 struct skb_frag_struct *frag;
ebe42d16 4434 dma_addr_t dma;
80d0759e 4435 unsigned int data_len, size;
7af40ad9 4436 u32 tx_flags = first->tx_flags;
1d9daf45 4437 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4438 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4439
4440 tx_desc = IGB_TX_DESC(tx_ring, i);
4441
80d0759e
AD		 4442 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4443
4444 size = skb_headlen(skb);
4445 data_len = skb->data_len;
ebe42d16
AD		 4446
4447 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4448
80d0759e
AD		 4449 tx_buffer = first;
4450
4451 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4452 if (dma_mapping_error(tx_ring->dev, dma))
4453 goto dma_error;
4454
4455 /* record length, and DMA address */
4456 dma_unmap_len_set(tx_buffer, len, size);
4457 dma_unmap_addr_set(tx_buffer, dma, dma);
4458
4459 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4460
ebe42d16
AD		 4461 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4462 tx_desc->read.cmd_type_len =
1d9daf45 4463 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4464
4465 i++;
4466 tx_desc++;
4467 if (i == tx_ring->count) {
4468 tx_desc = IGB_TX_DESC(tx_ring, 0);
4469 i = 0;
4470 }
80d0759e 4471 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4472
4473 dma += IGB_MAX_DATA_PER_TXD;
4474 size -= IGB_MAX_DATA_PER_TXD;
4475
ebe42d16
AD		 4476 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4477 }
4478
4479 if (likely(!data_len))
4480 break;
2bbfebe2 4481
1d9daf45 4482 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4483
65689fef 4484 i++;
ebe42d16
AD		 4485 tx_desc++;
4486 if (i == tx_ring->count) {
4487 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4488 i = 0;
ebe42d16 4489 }
80d0759e 4490 tx_desc->read.olinfo_status = 0;
65689fef 4491
9e903e08 4492 size = skb_frag_size(frag);
ebe42d16
AD		 4493 data_len -= size;
4494
4495 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4496 size, DMA_TO_DEVICE);
6366ad33 4497
c9f14bf3 4498 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4499 }
4500
ebe42d16 4501 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4502 cmd_type |= size | IGB_TXD_DCMD;
4503 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4504
80d0759e
AD		 4505 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4506
8542db05
AD		 4507 /* set the timestamp */
4508 first->time_stamp = jiffies;
4509
ebe42d16
AD		 4510 /*
4511 * Force memory writes to complete before letting h/w know there
4512 * are new descriptors to fetch. (Only applicable for weak-ordered
4513 * memory model archs, such as IA-64).
4514 *
4515 * We also need this memory barrier to make certain all of the
4516 * status bits have been updated before next_to_watch is written.
4517 */
4518 wmb();
4519
8542db05 4520 /* set next_to_watch value indicating a packet is present */
ebe42d16 4521 first->next_to_watch = tx_desc;
9d5c8243 4522
ebe42d16
AD		 4523 i++;
4524 if (i == tx_ring->count)
4525 i = 0;
6366ad33 4526
ebe42d16 4527 tx_ring->next_to_use = i;
6366ad33 4528
ebe42d16 4529 writel(i, tx_ring->tail);
6366ad33 4530
ebe42d16
AD		 4531 /* we need this if more than one processor can write to our tail
4532 * at a time, it syncronizes IO on IA64/Altix systems */
4533 mmiowb();
4534
4535 return;
4536
4537dma_error:
4538 dev_err(tx_ring->dev, "TX DMA map failed\n");
4539
4540 /* clear dma mappings for failed tx_buffer_info map */
4541 for (;;) {
c9f14bf3
AD		 4542 tx_buffer = &tx_ring->tx_buffer_info[i];
4543 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4544 if (tx_buffer == first)
ebe42d16 4545 break;
a77ff709
NN		 4546 if (i == 0)
4547 i = tx_ring->count;
6366ad33 4548 i--;
6366ad33
AD		 4549 }
4550
9d5c8243 4551 tx_ring->next_to_use = i;
9d5c8243
AK		 4552}
4553
6ad4edfc 4554static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4555{
e694e964
AD		 4556 struct net_device *netdev = tx_ring->netdev;
4557
661086df 4558 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4559
9d5c8243
AK		 4560 /* Herbert's original patch had:
4561 * smp_mb__after_netif_stop_queue();
4562 * but since that doesn't exist yet, just open code it. */
4563 smp_mb();
4564
4565 /* We need to check again in a case another CPU has just
4566 * made room available. */
c493ea45 4567 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4568 return -EBUSY;
4569
4570 /* A reprieve! */
661086df 4571 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4572
4573 u64_stats_update_begin(&tx_ring->tx_syncp2);
4574 tx_ring->tx_stats.restart_queue2++;
4575 u64_stats_update_end(&tx_ring->tx_syncp2);
4576
9d5c8243
AK		 4577 return 0;
4578}
4579
6ad4edfc 4580static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4581{
c493ea45 4582 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4583 return 0;
e694e964 4584 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4585}
4586
cd392f5c
AD		 4587netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4588 struct igb_ring *tx_ring)
9d5c8243 4589{
1f6e8178 4590 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4591 struct igb_tx_buffer *first;
ebe42d16 4592 int tso;
91d4ee33 4593 u32 tx_flags = 0;
31f6adbb 4594 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4595 u8 hdr_len = 0;
9d5c8243 4596
9d5c8243
AK		 4597 /* need: 1 descriptor per page,
4598 * + 2 desc gap to keep tail from touching head,
4599 * + 1 desc for skb->data,
4600 * + 1 desc for context descriptor,
4601 * otherwise try next time */
e694e964 4602 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4603 /* this is a hard error */
9d5c8243
AK		 4604 return NETDEV_TX_BUSY;
4605 }
33af6bcc 4606
7af40ad9
AD		 4607 /* record the location of the first descriptor for this packet */
4608 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4609 first->skb = skb;
4610 first->bytecount = skb->len;
4611 first->gso_segs = 1;
4612
b66e2397
MV		 4613 skb_tx_timestamp(skb);
4614
1f6e8178
MV		 4615 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4616 !(adapter->ptp_tx_skb))) {
2244d07b 4617 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4618 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4619
4620 adapter->ptp_tx_skb = skb_get(skb);
428f1f71 4621 adapter->ptp_tx_start = jiffies;
1f6e8178
MV		 4622 if (adapter->hw.mac.type == e1000_82576)
4623 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4624 }
9d5c8243 4625
eab6d18d 4626 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4627 tx_flags |= IGB_TX_FLAGS_VLAN;
4628 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4629 }
4630
7af40ad9
AD		 4631 /* record initial flags and protocol */
4632 first->tx_flags = tx_flags;
4633 first->protocol = protocol;
cdfd01fc 4634
7af40ad9
AD		 4635 tso = igb_tso(tx_ring, first, &hdr_len);
4636 if (tso < 0)
7d13a7d0 4637 goto out_drop;
7af40ad9
AD		 4638 else if (!tso)
4639 igb_tx_csum(tx_ring, first);
9d5c8243 4640
7af40ad9 4641 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4642
4643 /* Make sure there is space in the ring for the next send. */
e694e964 4644 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4645
9d5c8243 4646 return NETDEV_TX_OK;
7d13a7d0
AD		 4647
4648out_drop:
7af40ad9
AD		 4649 igb_unmap_and_free_tx_resource(tx_ring, first);
4650
7d13a7d0 4651 return NETDEV_TX_OK;
9d5c8243
AK		 4652}
4653
1cc3bd87
AD		 4654static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4655 struct sk_buff *skb)
4656{
4657 unsigned int r_idx = skb->queue_mapping;
4658
4659 if (r_idx >= adapter->num_tx_queues)
4660 r_idx = r_idx % adapter->num_tx_queues;
4661
4662 return adapter->tx_ring[r_idx];
4663}
4664
cd392f5c
AD		 4665static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4666 struct net_device *netdev)
9d5c8243
AK		 4667{
4668 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4669
4670 if (test_bit(__IGB_DOWN, &adapter->state)) {
4671 dev_kfree_skb_any(skb);
4672 return NETDEV_TX_OK;
4673 }
4674
4675 if (skb->len <= 0) {
4676 dev_kfree_skb_any(skb);
4677 return NETDEV_TX_OK;
4678 }
4679
1cc3bd87
AD		 4680 /*
4681 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4682 * in order to meet this minimum size requirement.
4683 */
ea5ceeab
TD		 4684 if (unlikely(skb->len < 17)) {
4685 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4686 return NETDEV_TX_OK;
4687 skb->len = 17;
ea5ceeab 4688 skb_set_tail_pointer(skb, 17);
1cc3bd87 4689 }
9d5c8243 4690
1cc3bd87 4691 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4692}
4693
4694/**
4695 * igb_tx_timeout - Respond to a Tx Hang
4696 * @netdev: network interface device structure
4697 **/
4698static void igb_tx_timeout(struct net_device *netdev)
4699{
4700 struct igb_adapter *adapter = netdev_priv(netdev);
4701 struct e1000_hw *hw = &adapter->hw;
4702
4703 /* Do the reset outside of interrupt context */
4704 adapter->tx_timeout_count++;
f7ba205e 4705
06218a8d 4706 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4707 hw->dev_spec._82575.global_device_reset = true;
4708
9d5c8243 4709 schedule_work(&adapter->reset_task);
265de409
AD		 4710 wr32(E1000_EICS,
4711 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4712}
4713
4714static void igb_reset_task(struct work_struct *work)
4715{
4716 struct igb_adapter *adapter;
4717 adapter = container_of(work, struct igb_adapter, reset_task);
4718
c97ec42a
TI		 4719 igb_dump(adapter);
4720 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4721 igb_reinit_locked(adapter);
4722}
4723
4724/**
12dcd86b 4725 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4726 * @netdev: network interface device structure
12dcd86b 4727 * @stats: rtnl_link_stats64 pointer
9d5c8243 4728 *
9d5c8243 4729 **/
12dcd86b
ED		 4730static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4731 struct rtnl_link_stats64 *stats)
9d5c8243 4732{
12dcd86b
ED		 4733 struct igb_adapter *adapter = netdev_priv(netdev);
4734
4735 spin_lock(&adapter->stats64_lock);
4736 igb_update_stats(adapter, &adapter->stats64);
4737 memcpy(stats, &adapter->stats64, sizeof(*stats));
4738 spin_unlock(&adapter->stats64_lock);
4739
4740 return stats;
9d5c8243
AK		 4741}
4742
4743/**
4744 * igb_change_mtu - Change the Maximum Transfer Unit
4745 * @netdev: network interface device structure
4746 * @new_mtu: new value for maximum frame size
4747 *
4748 * Returns 0 on success, negative on failure
4749 **/
4750static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4751{
4752 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4753 struct pci_dev *pdev = adapter->pdev;
153285f9 4754 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4755
c809d227 4756 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4757 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4758 return -EINVAL;
4759 }
4760
153285f9 4761#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4762 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4763 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4764 return -EINVAL;
4765 }
4766
4767 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4768 msleep(1);
73cd78f1 4769
9d5c8243
AK		 4770 /* igb_down has a dependency on max_frame_size */
4771 adapter->max_frame_size = max_frame;
559e9c49 4772
4c844851
AD		 4773 if (netif_running(netdev))
4774 igb_down(adapter);
9d5c8243 4775
090b1795 4776 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4777 netdev->mtu, new_mtu);
4778 netdev->mtu = new_mtu;
4779
4780 if (netif_running(netdev))
4781 igb_up(adapter);
4782 else
4783 igb_reset(adapter);
4784
4785 clear_bit(__IGB_RESETTING, &adapter->state);
4786
4787 return 0;
4788}
4789
4790/**
4791 * igb_update_stats - Update the board statistics counters
4792 * @adapter: board private structure
4793 **/
4794
12dcd86b
ED		 4795void igb_update_stats(struct igb_adapter *adapter,
4796 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4797{
4798 struct e1000_hw *hw = &adapter->hw;
4799 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4800 u32 reg, mpc;
9d5c8243 4801 u16 phy_tmp;
3f9c0164
AD		 4802 int i;
4803 u64 bytes, packets;
12dcd86b
ED		 4804 unsigned int start;
4805 u64 _bytes, _packets;
9d5c8243
AK		 4806
4807#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4808
4809 /*
4810 * Prevent stats update while adapter is being reset, or if the pci
4811 * connection is down.
4812 */
4813 if (adapter->link_speed == 0)
4814 return;
4815 if (pci_channel_offline(pdev))
4816 return;
4817
3f9c0164
AD		 4818 bytes = 0;
4819 packets = 0;
4820 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4821 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4822 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4823
ae1c07a6
AD		 4824 if (rqdpc) {
4825 ring->rx_stats.drops += rqdpc;
4826 net_stats->rx_fifo_errors += rqdpc;
4827 }
12dcd86b
ED		 4828
4829 do {
4830 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4831 _bytes = ring->rx_stats.bytes;
4832 _packets = ring->rx_stats.packets;
4833 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4834 bytes += _bytes;
4835 packets += _packets;
3f9c0164
AD		 4836 }
4837
128e45eb
AD		 4838 net_stats->rx_bytes = bytes;
4839 net_stats->rx_packets = packets;
3f9c0164
AD		 4840
4841 bytes = 0;
4842 packets = 0;
4843 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4844 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4845 do {
4846 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4847 _bytes = ring->tx_stats.bytes;
4848 _packets = ring->tx_stats.packets;
4849 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4850 bytes += _bytes;
4851 packets += _packets;
3f9c0164 4852 }
128e45eb
AD		 4853 net_stats->tx_bytes = bytes;
4854 net_stats->tx_packets = packets;
3f9c0164
AD		 4855
4856 /* read stats registers */
9d5c8243
AK		 4857 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4858 adapter->stats.gprc += rd32(E1000_GPRC);
4859 adapter->stats.gorc += rd32(E1000_GORCL);
4860 rd32(E1000_GORCH); /* clear GORCL */
4861 adapter->stats.bprc += rd32(E1000_BPRC);
4862 adapter->stats.mprc += rd32(E1000_MPRC);
4863 adapter->stats.roc += rd32(E1000_ROC);
4864
4865 adapter->stats.prc64 += rd32(E1000_PRC64);
4866 adapter->stats.prc127 += rd32(E1000_PRC127);
4867 adapter->stats.prc255 += rd32(E1000_PRC255);
4868 adapter->stats.prc511 += rd32(E1000_PRC511);
4869 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4870 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4871 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4872 adapter->stats.sec += rd32(E1000_SEC);
4873
fa3d9a6d
MW		 4874 mpc = rd32(E1000_MPC);
4875 adapter->stats.mpc += mpc;
4876 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4877 adapter->stats.scc += rd32(E1000_SCC);
4878 adapter->stats.ecol += rd32(E1000_ECOL);
4879 adapter->stats.mcc += rd32(E1000_MCC);
4880 adapter->stats.latecol += rd32(E1000_LATECOL);
4881 adapter->stats.dc += rd32(E1000_DC);
4882 adapter->stats.rlec += rd32(E1000_RLEC);
4883 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4884 adapter->stats.xontxc += rd32(E1000_XONTXC);
4885 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4886 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4887 adapter->stats.fcruc += rd32(E1000_FCRUC);
4888 adapter->stats.gptc += rd32(E1000_GPTC);
4889 adapter->stats.gotc += rd32(E1000_GOTCL);
4890 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4891 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4892 adapter->stats.ruc += rd32(E1000_RUC);
4893 adapter->stats.rfc += rd32(E1000_RFC);
4894 adapter->stats.rjc += rd32(E1000_RJC);
4895 adapter->stats.tor += rd32(E1000_TORH);
4896 adapter->stats.tot += rd32(E1000_TOTH);
4897 adapter->stats.tpr += rd32(E1000_TPR);
4898
4899 adapter->stats.ptc64 += rd32(E1000_PTC64);
4900 adapter->stats.ptc127 += rd32(E1000_PTC127);
4901 adapter->stats.ptc255 += rd32(E1000_PTC255);
4902 adapter->stats.ptc511 += rd32(E1000_PTC511);
4903 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4904 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4905
4906 adapter->stats.mptc += rd32(E1000_MPTC);
4907 adapter->stats.bptc += rd32(E1000_BPTC);
4908
2d0b0f69
NN		 4909 adapter->stats.tpt += rd32(E1000_TPT);
4910 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4911
4912 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4913 /* read internal phy specific stats */
4914 reg = rd32(E1000_CTRL_EXT);
4915 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4916 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4917
4918 /* this stat has invalid values on i210/i211 */
4919 if ((hw->mac.type != e1000_i210) &&
4920 (hw->mac.type != e1000_i211))
4921 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4922 }
4923
9d5c8243
AK		 4924 adapter->stats.tsctc += rd32(E1000_TSCTC);
4925 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4926
4927 adapter->stats.iac += rd32(E1000_IAC);
4928 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4929 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4930 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4931 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4932 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4933 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4934 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4935 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4936
4937 /* Fill out the OS statistics structure */
128e45eb
AD		 4938 net_stats->multicast = adapter->stats.mprc;
4939 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4940
4941 /* Rx Errors */
4942
4943 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4944 * our own version based on RUC and ROC */
128e45eb 4945 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4946 adapter->stats.crcerrs + adapter->stats.algnerrc +
4947 adapter->stats.ruc + adapter->stats.roc +
4948 adapter->stats.cexterr;
128e45eb
AD		 4949 net_stats->rx_length_errors = adapter->stats.ruc +
4950 adapter->stats.roc;
4951 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4952 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4953 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4954
4955 /* Tx Errors */
128e45eb
AD		 4956 net_stats->tx_errors = adapter->stats.ecol +
4957 adapter->stats.latecol;
4958 net_stats->tx_aborted_errors = adapter->stats.ecol;
4959 net_stats->tx_window_errors = adapter->stats.latecol;
4960 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4961
4962 /* Tx Dropped needs to be maintained elsewhere */
4963
4964 /* Phy Stats */
4965 if (hw->phy.media_type == e1000_media_type_copper) {
4966 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4967 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4968 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4969 adapter->phy_stats.idle_errors += phy_tmp;
4970 }
4971 }
4972
4973 /* Management Stats */
4974 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4975 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4976 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4977
4978 /* OS2BMC Stats */
4979 reg = rd32(E1000_MANC);
4980 if (reg & E1000_MANC_EN_BMC2OS) {
4981 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4982 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4983 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4984 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4985 }
9d5c8243
AK		 4986}
4987
9d5c8243
AK		 4988static irqreturn_t igb_msix_other(int irq, void *data)
4989{
047e0030 4990 struct igb_adapter *adapter = data;
9d5c8243 4991 struct e1000_hw *hw = &adapter->hw;
844290e5 4992 u32 icr = rd32(E1000_ICR);
844290e5 4993 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4994
7f081d40
AD		 4995 if (icr & E1000_ICR_DRSTA)
4996 schedule_work(&adapter->reset_task);
4997
047e0030 4998 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4999 /* HW is reporting DMA is out of sync */
5000 adapter->stats.doosync++;
13800469
GR		 5001 /* The DMA Out of Sync is also indication of a spoof event
5002 * in IOV mode. Check the Wrong VM Behavior register to
5003 * see if it is really a spoof event. */
5004 igb_check_wvbr(adapter);
dda0e083 5005 }
eebbbdba 5006
4ae196df
AD		 5007 /* Check for a mailbox event */
5008 if (icr & E1000_ICR_VMMB)
5009 igb_msg_task(adapter);
5010
5011 if (icr & E1000_ICR_LSC) {
5012 hw->mac.get_link_status = 1;
5013 /* guard against interrupt when we're going down */
5014 if (!test_bit(__IGB_DOWN, &adapter->state))
5015 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5016 }
5017
1f6e8178
MV		 5018 if (icr & E1000_ICR_TS) {
5019 u32 tsicr = rd32(E1000_TSICR);
5020
5021 if (tsicr & E1000_TSICR_TXTS) {
5022 /* acknowledge the interrupt */
5023 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5024 /* retrieve hardware timestamp */
5025 schedule_work(&adapter->ptp_tx_work);
5026 }
5027 }
1f6e8178 5028
844290e5 5029 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5030
5031 return IRQ_HANDLED;
5032}
5033
047e0030 5034static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5035{
26b39276 5036 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5037 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5038
047e0030
AD		 5039 if (!q_vector->set_itr)
5040 return;
73cd78f1 5041
047e0030
AD		 5042 if (!itr_val)
5043 itr_val = 0x4;
661086df 5044
26b39276
AD		 5045 if (adapter->hw.mac.type == e1000_82575)
5046 itr_val |= itr_val << 16;
661086df 5047 else
0ba82994 5048 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5049
047e0030
AD		 5050 writel(itr_val, q_vector->itr_register);
5051 q_vector->set_itr = 0;
6eb5a7f1
AD		 5052}
5053
047e0030 5054static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5055{
047e0030 5056 struct igb_q_vector *q_vector = data;
9d5c8243 5057
047e0030
AD		 5058 /* Write the ITR value calculated from the previous interrupt. */
5059 igb_write_itr(q_vector);
9d5c8243 5060
047e0030 5061 napi_schedule(&q_vector->napi);
844290e5 5062
047e0030 5063 return IRQ_HANDLED;
fe4506b6
JC		 5064}
5065
421e02f0 5066#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5067static void igb_update_tx_dca(struct igb_adapter *adapter,
5068 struct igb_ring *tx_ring,
5069 int cpu)
5070{
5071 struct e1000_hw *hw = &adapter->hw;
5072 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5073
5074 if (hw->mac.type != e1000_82575)
5075 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5076
5077 /*
5078 * We can enable relaxed ordering for reads, but not writes when
5079 * DCA is enabled. This is due to a known issue in some chipsets
5080 * which will cause the DCA tag to be cleared.
5081 */
5082 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5083 E1000_DCA_TXCTRL_DATA_RRO_EN |
5084 E1000_DCA_TXCTRL_DESC_DCA_EN;
5085
5086 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5087}
5088
5089static void igb_update_rx_dca(struct igb_adapter *adapter,
5090 struct igb_ring *rx_ring,
5091 int cpu)
5092{
5093 struct e1000_hw *hw = &adapter->hw;
5094 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5095
5096 if (hw->mac.type != e1000_82575)
5097 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5098
5099 /*
5100 * We can enable relaxed ordering for reads, but not writes when
5101 * DCA is enabled. This is due to a known issue in some chipsets
5102 * which will cause the DCA tag to be cleared.
5103 */
5104 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5105 E1000_DCA_RXCTRL_DESC_DCA_EN;
5106
5107 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5108}
5109
047e0030 5110static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5111{
047e0030 5112 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5113 int cpu = get_cpu();
fe4506b6 5114
047e0030
AD		 5115 if (q_vector->cpu == cpu)
5116 goto out_no_update;
5117
6a05004a
AD		 5118 if (q_vector->tx.ring)
5119 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5120
5121 if (q_vector->rx.ring)
5122 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5123
047e0030
AD		 5124 q_vector->cpu = cpu;
5125out_no_update:
fe4506b6
JC		 5126 put_cpu();
5127}
5128
5129static void igb_setup_dca(struct igb_adapter *adapter)
5130{
7e0e99ef 5131 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5132 int i;
5133
7dfc16fa 5134 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5135 return;
5136
7e0e99ef
AD		 5137 /* Always use CB2 mode, difference is masked in the CB driver. */
5138 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5139
047e0030 5140 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5141 adapter->q_vector[i]->cpu = -1;
5142 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5143 }
5144}
5145
5146static int __igb_notify_dca(struct device *dev, void *data)
5147{
5148 struct net_device *netdev = dev_get_drvdata(dev);
5149 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5150 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5151 struct e1000_hw *hw = &adapter->hw;
5152 unsigned long event = *(unsigned long *)data;
5153
5154 switch (event) {
5155 case DCA_PROVIDER_ADD:
5156 /* if already enabled, don't do it again */
7dfc16fa 5157 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5158 break;
fe4506b6 5159 if (dca_add_requester(dev) == 0) {
bbd98fe4 5160 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5161 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5162 igb_setup_dca(adapter);
5163 break;
5164 }
5165 /* Fall Through since DCA is disabled. */
5166 case DCA_PROVIDER_REMOVE:
7dfc16fa 5167 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5168 /* without this a class_device is left
047e0030 5169 * hanging around in the sysfs model */
fe4506b6 5170 dca_remove_requester(dev);
090b1795 5171 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5172 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5173 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5174 }
5175 break;
5176 }
bbd98fe4 5177
fe4506b6 5178 return 0;
9d5c8243
AK		 5179}
5180
fe4506b6
JC		 5181static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5182 void *p)
5183{
5184 int ret_val;
5185
5186 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5187 __igb_notify_dca);
5188
5189 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5190}
421e02f0 5191#endif /* CONFIG_IGB_DCA */
9d5c8243 5192
0224d663
GR		 5193#ifdef CONFIG_PCI_IOV
5194static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5195{
5196 unsigned char mac_addr[ETH_ALEN];
0224d663 5197
7efd26d0 5198 eth_random_addr(mac_addr);
0224d663
GR		 5199 igb_set_vf_mac(adapter, vf, mac_addr);
5200
f557147c 5201 return 0;
0224d663
GR		 5202}
5203
f557147c 5204static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 5205{
0224d663 5206 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 5207 struct pci_dev *vfdev;
5208 int dev_id;
0224d663
GR		 5209
5210 switch (adapter->hw.mac.type) {
5211 case e1000_82576:
f557147c 5212 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 5213 break;
5214 case e1000_i350:
f557147c 5215 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 5216 break;
5217 default:
f557147c 5218 return false;
0224d663
GR		 5219 }
5220
f557147c
SA		 5221 /* loop through all the VFs to see if we own any that are assigned */
5222 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5223 while (vfdev) {
5224 /* if we don't own it we don't care */
5225 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5226 /* if it is assigned we cannot release it */
5227 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5228 return true;
5229 }
f557147c
SA		 5230
5231 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5232 }
f557147c 5233
0224d663
GR		 5234 return false;
5235}
5236
5237#endif
4ae196df
AD		 5238static void igb_ping_all_vfs(struct igb_adapter *adapter)
5239{
5240 struct e1000_hw *hw = &adapter->hw;
5241 u32 ping;
5242 int i;
5243
5244 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5245 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5246 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5247 ping |= E1000_VT_MSGTYPE_CTS;
5248 igb_write_mbx(hw, &ping, 1, i);
5249 }
5250}
5251
7d5753f0
AD		 5252static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5253{
5254 struct e1000_hw *hw = &adapter->hw;
5255 u32 vmolr = rd32(E1000_VMOLR(vf));
5256 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5257
d85b9004 5258 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5259 IGB_VF_FLAG_MULTI_PROMISC);
5260 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5261
5262 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5263 vmolr |= E1000_VMOLR_MPME;
d85b9004 5264 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5265 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5266 } else {
5267 /*
5268 * if we have hashes and we are clearing a multicast promisc
5269 * flag we need to write the hashes to the MTA as this step
5270 * was previously skipped
5271 */
5272 if (vf_data->num_vf_mc_hashes > 30) {
5273 vmolr |= E1000_VMOLR_MPME;
5274 } else if (vf_data->num_vf_mc_hashes) {
5275 int j;
5276 vmolr |= E1000_VMOLR_ROMPE;
5277 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5278 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5279 }
5280 }
5281
5282 wr32(E1000_VMOLR(vf), vmolr);
5283
5284 /* there are flags left unprocessed, likely not supported */
5285 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5286 return -EINVAL;
5287
5288 return 0;
5289
5290}
5291
4ae196df
AD		 5292static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5293 u32 *msgbuf, u32 vf)
5294{
5295 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5296 u16 *hash_list = (u16 *)&msgbuf[1];
5297 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5298 int i;
5299
7d5753f0 5300 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5301 * to this VF for later use to restore when the PF multi cast
5302 * list changes
5303 */
5304 vf_data->num_vf_mc_hashes = n;
5305
7d5753f0
AD		 5306 /* only up to 30 hash values supported */
5307 if (n > 30)
5308 n = 30;
5309
5310 /* store the hashes for later use */
4ae196df 5311 for (i = 0; i < n; i++)
a419aef8 5312 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5313
5314 /* Flush and reset the mta with the new values */
ff41f8dc 5315 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5316
5317 return 0;
5318}
5319
5320static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5321{
5322 struct e1000_hw *hw = &adapter->hw;
5323 struct vf_data_storage *vf_data;
5324 int i, j;
5325
5326 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5327 u32 vmolr = rd32(E1000_VMOLR(i));
5328 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5329
4ae196df 5330 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5331
5332 if ((vf_data->num_vf_mc_hashes > 30) ||
5333 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5334 vmolr |= E1000_VMOLR_MPME;
5335 } else if (vf_data->num_vf_mc_hashes) {
5336 vmolr |= E1000_VMOLR_ROMPE;
5337 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5338 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5339 }
5340 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5341 }
5342}
5343
5344static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5345{
5346 struct e1000_hw *hw = &adapter->hw;
5347 u32 pool_mask, reg, vid;
5348 int i;
5349
5350 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5351
5352 /* Find the vlan filter for this id */
5353 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5354 reg = rd32(E1000_VLVF(i));
5355
5356 /* remove the vf from the pool */
5357 reg &= ~pool_mask;
5358
5359 /* if pool is empty then remove entry from vfta */
5360 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5361 (reg & E1000_VLVF_VLANID_ENABLE)) {
5362 reg = 0;
5363 vid = reg & E1000_VLVF_VLANID_MASK;
5364 igb_vfta_set(hw, vid, false);
5365 }
5366
5367 wr32(E1000_VLVF(i), reg);
5368 }
ae641bdc
AD		 5369
5370 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5371}
5372
5373static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5374{
5375 struct e1000_hw *hw = &adapter->hw;
5376 u32 reg, i;
5377
51466239
AD		 5378 /* The vlvf table only exists on 82576 hardware and newer */
5379 if (hw->mac.type < e1000_82576)
5380 return -1;
5381
5382 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5383 if (!adapter->vfs_allocated_count)
5384 return -1;
5385
5386 /* Find the vlan filter for this id */
5387 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5388 reg = rd32(E1000_VLVF(i));
5389 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5390 vid == (reg & E1000_VLVF_VLANID_MASK))
5391 break;
5392 }
5393
5394 if (add) {
5395 if (i == E1000_VLVF_ARRAY_SIZE) {
5396 /* Did not find a matching VLAN ID entry that was
5397 * enabled. Search for a free filter entry, i.e.
5398 * one without the enable bit set
5399 */
5400 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5401 reg = rd32(E1000_VLVF(i));
5402 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5403 break;
5404 }
5405 }
5406 if (i < E1000_VLVF_ARRAY_SIZE) {
5407 /* Found an enabled/available entry */
5408 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5409
5410 /* if !enabled we need to set this up in vfta */
5411 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5412 /* add VID to filter table */
5413 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5414 reg |= E1000_VLVF_VLANID_ENABLE;
5415 }
cad6d05f
AD		 5416 reg &= ~E1000_VLVF_VLANID_MASK;
5417 reg |= vid;
4ae196df 5418 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5419
5420 /* do not modify RLPML for PF devices */
5421 if (vf >= adapter->vfs_allocated_count)
5422 return 0;
5423
5424 if (!adapter->vf_data[vf].vlans_enabled) {
5425 u32 size;
5426 reg = rd32(E1000_VMOLR(vf));
5427 size = reg & E1000_VMOLR_RLPML_MASK;
5428 size += 4;
5429 reg &= ~E1000_VMOLR_RLPML_MASK;
5430 reg |= size;
5431 wr32(E1000_VMOLR(vf), reg);
5432 }
ae641bdc 5433
51466239 5434 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5435 }
5436 } else {
5437 if (i < E1000_VLVF_ARRAY_SIZE) {
5438 /* remove vf from the pool */
5439 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5440 /* if pool is empty then remove entry from vfta */
5441 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5442 reg = 0;
5443 igb_vfta_set(hw, vid, false);
5444 }
5445 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5446
5447 /* do not modify RLPML for PF devices */
5448 if (vf >= adapter->vfs_allocated_count)
5449 return 0;
5450
5451 adapter->vf_data[vf].vlans_enabled--;
5452 if (!adapter->vf_data[vf].vlans_enabled) {
5453 u32 size;
5454 reg = rd32(E1000_VMOLR(vf));
5455 size = reg & E1000_VMOLR_RLPML_MASK;
5456 size -= 4;
5457 reg &= ~E1000_VMOLR_RLPML_MASK;
5458 reg |= size;
5459 wr32(E1000_VMOLR(vf), reg);
5460 }
4ae196df
AD		 5461 }
5462 }
8151d294
WM		 5463 return 0;
5464}
5465
5466static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5467{
5468 struct e1000_hw *hw = &adapter->hw;
5469
5470 if (vid)
5471 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5472 else
5473 wr32(E1000_VMVIR(vf), 0);
5474}
5475
5476static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5477 int vf, u16 vlan, u8 qos)
5478{
5479 int err = 0;
5480 struct igb_adapter *adapter = netdev_priv(netdev);
5481
5482 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5483 return -EINVAL;
5484 if (vlan || qos) {
5485 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5486 if (err)
5487 goto out;
5488 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5489 igb_set_vmolr(adapter, vf, !vlan);
5490 adapter->vf_data[vf].pf_vlan = vlan;
5491 adapter->vf_data[vf].pf_qos = qos;
5492 dev_info(&adapter->pdev->dev,
5493 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5494 if (test_bit(__IGB_DOWN, &adapter->state)) {
5495 dev_warn(&adapter->pdev->dev,
5496 "The VF VLAN has been set,"
5497 " but the PF device is not up.\n");
5498 dev_warn(&adapter->pdev->dev,
5499 "Bring the PF device up before"
5500 " attempting to use the VF device.\n");
5501 }
5502 } else {
5503 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5504 false, vf);
5505 igb_set_vmvir(adapter, vlan, vf);
5506 igb_set_vmolr(adapter, vf, true);
5507 adapter->vf_data[vf].pf_vlan = 0;
5508 adapter->vf_data[vf].pf_qos = 0;
5509 }
5510out:
5511 return err;
4ae196df
AD		 5512}
5513
5514static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5515{
5516 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5517 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5518
5519 return igb_vlvf_set(adapter, vid, add, vf);
5520}
5521
f2ca0dbe 5522static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5523{
8fa7e0f7
GR		 5524 /* clear flags - except flag that indicates PF has set the MAC */
5525 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5526 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5527
5528 /* reset offloads to defaults */
8151d294 5529 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5530
5531 /* reset vlans for device */
5532 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5533 if (adapter->vf_data[vf].pf_vlan)
5534 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5535 adapter->vf_data[vf].pf_vlan,
5536 adapter->vf_data[vf].pf_qos);
5537 else
5538 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5539
5540 /* reset multicast table array for vf */
5541 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5542
5543 /* Flush and reset the mta with the new values */
ff41f8dc 5544 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5545}
5546
f2ca0dbe
AD		 5547static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5548{
5549 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5550
5551 /* generate a new mac address as we were hotplug removed/added */
8151d294 5552 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5553 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5554
5555 /* process remaining reset events */
5556 igb_vf_reset(adapter, vf);
5557}
5558
5559static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5560{
5561 struct e1000_hw *hw = &adapter->hw;
5562 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5563 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5564 u32 reg, msgbuf[3];
5565 u8 *addr = (u8 *)(&msgbuf[1]);
5566
5567 /* process all the same items cleared in a function level reset */
f2ca0dbe 5568 igb_vf_reset(adapter, vf);
4ae196df
AD		 5569
5570 /* set vf mac address */
26ad9178 5571 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5572
5573 /* enable transmit and receive for vf */
5574 reg = rd32(E1000_VFTE);
5575 wr32(E1000_VFTE, reg | (1 << vf));
5576 reg = rd32(E1000_VFRE);
5577 wr32(E1000_VFRE, reg | (1 << vf));
5578
8fa7e0f7 5579 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5580
5581 /* reply to reset with ack and vf mac address */
5582 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5583 memcpy(addr, vf_mac, 6);
5584 igb_write_mbx(hw, msgbuf, 3, vf);
5585}
5586
5587static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5588{
de42edde
GR		 5589 /*
5590 * The VF MAC Address is stored in a packed array of bytes
5591 * starting at the second 32 bit word of the msg array
5592 */
f2ca0dbe
AD		 5593 unsigned char *addr = (char *)&msg[1];
5594 int err = -1;
4ae196df 5595
f2ca0dbe
AD		 5596 if (is_valid_ether_addr(addr))
5597 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5598
f2ca0dbe 5599 return err;
4ae196df
AD		 5600}
5601
5602static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5603{
5604 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5605 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5606 u32 msg = E1000_VT_MSGTYPE_NACK;
5607
5608 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5609 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5610 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5611 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5612 vf_data->last_nack = jiffies;
4ae196df
AD		 5613 }
5614}
5615
f2ca0dbe 5616static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5617{
f2ca0dbe
AD		 5618 struct pci_dev *pdev = adapter->pdev;
5619 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5620 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5621 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5622 s32 retval;
5623
f2ca0dbe 5624 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5625
fef45f4c
AD		 5626 if (retval) {
5627 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5628 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5629 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5630 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5631 return;
5632 goto out;
5633 }
4ae196df
AD		 5634
5635 /* this is a message we already processed, do nothing */
5636 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5637 return;
4ae196df
AD		 5638
5639 /*
5640 * until the vf completes a reset it should not be
5641 * allowed to start any configuration.
5642 */
5643
5644 if (msgbuf[0] == E1000_VF_RESET) {
5645 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5646 return;
4ae196df
AD		 5647 }
5648
f2ca0dbe 5649 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5650 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5651 return;
5652 retval = -1;
5653 goto out;
4ae196df
AD		 5654 }
5655
5656 switch ((msgbuf[0] & 0xFFFF)) {
5657 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5658 retval = -EINVAL;
5659 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5660 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5661 else
5662 dev_warn(&pdev->dev,
5663 "VF %d attempted to override administratively "
5664 "set MAC address\nReload the VF driver to "
5665 "resume operations\n", vf);
4ae196df 5666 break;
7d5753f0
AD		 5667 case E1000_VF_SET_PROMISC:
5668 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5669 break;
4ae196df
AD		 5670 case E1000_VF_SET_MULTICAST:
5671 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5672 break;
5673 case E1000_VF_SET_LPE:
5674 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5675 break;
5676 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5677 retval = -1;
5678 if (vf_data->pf_vlan)
5679 dev_warn(&pdev->dev,
5680 "VF %d attempted to override administratively "
5681 "set VLAN tag\nReload the VF driver to "
5682 "resume operations\n", vf);
8151d294
WM		 5683 else
5684 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5685 break;
5686 default:
090b1795 5687 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5688 retval = -1;
5689 break;
5690 }
5691
fef45f4c
AD		 5692 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5693out:
4ae196df
AD		 5694 /* notify the VF of the results of what it sent us */
5695 if (retval)
5696 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5697 else
5698 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5699
4ae196df 5700 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5701}
4ae196df 5702
f2ca0dbe
AD		 5703static void igb_msg_task(struct igb_adapter *adapter)
5704{
5705 struct e1000_hw *hw = &adapter->hw;
5706 u32 vf;
5707
5708 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5709 /* process any reset requests */
5710 if (!igb_check_for_rst(hw, vf))
5711 igb_vf_reset_event(adapter, vf);
5712
5713 /* process any messages pending */
5714 if (!igb_check_for_msg(hw, vf))
5715 igb_rcv_msg_from_vf(adapter, vf);
5716
5717 /* process any acks */
5718 if (!igb_check_for_ack(hw, vf))
5719 igb_rcv_ack_from_vf(adapter, vf);
5720 }
4ae196df
AD		 5721}
5722
68d480c4
AD		 5723/**
5724 * igb_set_uta - Set unicast filter table address
5725 * @adapter: board private structure
5726 *
5727 * The unicast table address is a register array of 32-bit registers.
5728 * The table is meant to be used in a way similar to how the MTA is used
5729 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5730 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5731 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5732 **/
5733static void igb_set_uta(struct igb_adapter *adapter)
5734{
5735 struct e1000_hw *hw = &adapter->hw;
5736 int i;
5737
5738 /* The UTA table only exists on 82576 hardware and newer */
5739 if (hw->mac.type < e1000_82576)
5740 return;
5741
5742 /* we only need to do this if VMDq is enabled */
5743 if (!adapter->vfs_allocated_count)
5744 return;
5745
5746 for (i = 0; i < hw->mac.uta_reg_count; i++)
5747 array_wr32(E1000_UTA, i, ~0);
5748}
5749
9d5c8243
AK		 5750/**
5751 * igb_intr_msi - Interrupt Handler
5752 * @irq: interrupt number
5753 * @data: pointer to a network interface device structure
5754 **/
5755static irqreturn_t igb_intr_msi(int irq, void *data)
5756{
047e0030
AD		 5757 struct igb_adapter *adapter = data;
5758 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5759 struct e1000_hw *hw = &adapter->hw;
5760 /* read ICR disables interrupts using IAM */
5761 u32 icr = rd32(E1000_ICR);
5762
047e0030 5763 igb_write_itr(q_vector);
9d5c8243 5764
7f081d40
AD		 5765 if (icr & E1000_ICR_DRSTA)
5766 schedule_work(&adapter->reset_task);
5767
047e0030 5768 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5769 /* HW is reporting DMA is out of sync */
5770 adapter->stats.doosync++;
5771 }
5772
9d5c8243
AK		 5773 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5774 hw->mac.get_link_status = 1;
5775 if (!test_bit(__IGB_DOWN, &adapter->state))
5776 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5777 }
5778
1f6e8178
MV		 5779 if (icr & E1000_ICR_TS) {
5780 u32 tsicr = rd32(E1000_TSICR);
5781
5782 if (tsicr & E1000_TSICR_TXTS) {
5783 /* acknowledge the interrupt */
5784 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5785 /* retrieve hardware timestamp */
5786 schedule_work(&adapter->ptp_tx_work);
5787 }
5788 }
1f6e8178 5789
047e0030 5790 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5791
5792 return IRQ_HANDLED;
5793}
5794
5795/**
4a3c6433 5796 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5797 * @irq: interrupt number
5798 * @data: pointer to a network interface device structure
5799 **/
5800static irqreturn_t igb_intr(int irq, void *data)
5801{
047e0030
AD		 5802 struct igb_adapter *adapter = data;
5803 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5804 struct e1000_hw *hw = &adapter->hw;
5805 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5806 * need for the IMC write */
5807 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5808
5809 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5810 * not set, then the adapter didn't send an interrupt */
5811 if (!(icr & E1000_ICR_INT_ASSERTED))
5812 return IRQ_NONE;
5813
0ba82994
AD		 5814 igb_write_itr(q_vector);
5815
7f081d40
AD		 5816 if (icr & E1000_ICR_DRSTA)
5817 schedule_work(&adapter->reset_task);
5818
047e0030 5819 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5820 /* HW is reporting DMA is out of sync */
5821 adapter->stats.doosync++;
5822 }
5823
9d5c8243
AK		 5824 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5825 hw->mac.get_link_status = 1;
5826 /* guard against interrupt when we're going down */
5827 if (!test_bit(__IGB_DOWN, &adapter->state))
5828 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5829 }
5830
1f6e8178
MV		 5831 if (icr & E1000_ICR_TS) {
5832 u32 tsicr = rd32(E1000_TSICR);
5833
5834 if (tsicr & E1000_TSICR_TXTS) {
5835 /* acknowledge the interrupt */
5836 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5837 /* retrieve hardware timestamp */
5838 schedule_work(&adapter->ptp_tx_work);
5839 }
5840 }
1f6e8178 5841
047e0030 5842 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5843
5844 return IRQ_HANDLED;
5845}
5846
c50b52a0 5847static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5848{
047e0030 5849 struct igb_adapter *adapter = q_vector->adapter;
46544258 5850 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5851
0ba82994
AD		 5852 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5853 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5854 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5855 igb_set_itr(q_vector);
46544258 5856 else
047e0030 5857 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5858 }
5859
46544258
AD		 5860 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5861 if (adapter->msix_entries)
047e0030 5862 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5863 else
5864 igb_irq_enable(adapter);
5865 }
9d5c8243
AK		 5866}
5867
46544258
AD		 5868/**
5869 * igb_poll - NAPI Rx polling callback
5870 * @napi: napi polling structure
5871 * @budget: count of how many packets we should handle
5872 **/
5873static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5874{
047e0030
AD		 5875 struct igb_q_vector *q_vector = container_of(napi,
5876 struct igb_q_vector,
5877 napi);
16eb8815 5878 bool clean_complete = true;
9d5c8243 5879
421e02f0 5880#ifdef CONFIG_IGB_DCA
047e0030
AD		 5881 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5882 igb_update_dca(q_vector);
fe4506b6 5883#endif
0ba82994 5884 if (q_vector->tx.ring)
13fde97a 5885 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5886
0ba82994 5887 if (q_vector->rx.ring)
cd392f5c 5888 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5889
16eb8815
AD		 5890 /* If all work not completed, return budget and keep polling */
5891 if (!clean_complete)
5892 return budget;
46544258 5893
9d5c8243 5894 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5895 napi_complete(napi);
5896 igb_ring_irq_enable(q_vector);
9d5c8243 5897
16eb8815 5898 return 0;
9d5c8243 5899}
6d8126f9 5900
9d5c8243
AK		 5901/**
5902 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5903 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5904 *
9d5c8243
AK		 5905 * returns true if ring is completely cleaned
5906 **/
047e0030 5907static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5908{
047e0030 5909 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5910 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5911 struct igb_tx_buffer *tx_buffer;
f4128785 5912 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5913 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5914 unsigned int budget = q_vector->tx.work_limit;
8542db05 5915 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5916
13fde97a
AD		 5917 if (test_bit(__IGB_DOWN, &adapter->state))
5918 return true;
0e014cb1 5919
06034649 5920 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5921 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5922 i -= tx_ring->count;
9d5c8243 5923
f4128785
AD		 5924 do {
5925 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5926
5927 /* if next_to_watch is not set then there is no work pending */
5928 if (!eop_desc)
5929 break;
13fde97a 5930
f4128785
AD		 5931 /* prevent any other reads prior to eop_desc */
5932 rmb();
5933
13fde97a
AD		 5934 /* if DD is not set pending work has not been completed */
5935 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5936 break;
5937
8542db05
AD		 5938 /* clear next_to_watch to prevent false hangs */
5939 tx_buffer->next_to_watch = NULL;
9d5c8243 5940
ebe42d16
AD		 5941 /* update the statistics for this packet */
5942 total_bytes += tx_buffer->bytecount;
5943 total_packets += tx_buffer->gso_segs;
13fde97a 5944
ebe42d16
AD		 5945 /* free the skb */
5946 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5947
ebe42d16
AD		 5948 /* unmap skb header data */
5949 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5950 dma_unmap_addr(tx_buffer, dma),
5951 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5952 DMA_TO_DEVICE);
5953
c9f14bf3
AD		 5954 /* clear tx_buffer data */
5955 tx_buffer->skb = NULL;
5956 dma_unmap_len_set(tx_buffer, len, 0);
5957
ebe42d16
AD		 5958 /* clear last DMA location and unmap remaining buffers */
5959 while (tx_desc != eop_desc) {
13fde97a
AD		 5960 tx_buffer++;
5961 tx_desc++;
9d5c8243 5962 i++;
8542db05
AD		 5963 if (unlikely(!i)) {
5964 i -= tx_ring->count;
06034649 5965 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5966 tx_desc = IGB_TX_DESC(tx_ring, 0);
5967 }
ebe42d16
AD		 5968
5969 /* unmap any remaining paged data */
c9f14bf3 5970 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5971 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5972 dma_unmap_addr(tx_buffer, dma),
5973 dma_unmap_len(tx_buffer, len),
ebe42d16 5974 DMA_TO_DEVICE);
c9f14bf3 5975 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5976 }
5977 }
5978
ebe42d16
AD		 5979 /* move us one more past the eop_desc for start of next pkt */
5980 tx_buffer++;
5981 tx_desc++;
5982 i++;
5983 if (unlikely(!i)) {
5984 i -= tx_ring->count;
5985 tx_buffer = tx_ring->tx_buffer_info;
5986 tx_desc = IGB_TX_DESC(tx_ring, 0);
5987 }
f4128785
AD		 5988
5989 /* issue prefetch for next Tx descriptor */
5990 prefetch(tx_desc);
5991
5992 /* update budget accounting */
5993 budget--;
5994 } while (likely(budget));
0e014cb1 5995
bdbc0631
ED		 5996 netdev_tx_completed_queue(txring_txq(tx_ring),
5997 total_packets, total_bytes);
8542db05 5998 i += tx_ring->count;
9d5c8243 5999 tx_ring->next_to_clean = i;
13fde97a
AD		 6000 u64_stats_update_begin(&tx_ring->tx_syncp);
6001 tx_ring->tx_stats.bytes += total_bytes;
6002 tx_ring->tx_stats.packets += total_packets;
6003 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6004 q_vector->tx.total_bytes += total_bytes;
6005 q_vector->tx.total_packets += total_packets;
9d5c8243 6006
6d095fa8 6007 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6008 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6009
9d5c8243
AK		 6010 /* Detect a transmit hang in hardware, this serializes the
6011 * check with the clearing of time_stamp and movement of i */
6d095fa8 6012 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6013 if (tx_buffer->next_to_watch &&
8542db05 6014 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6015 (adapter->tx_timeout_factor * HZ)) &&
6016 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6017
9d5c8243 6018 /* detected Tx unit hang */
59d71989 6019 dev_err(tx_ring->dev,
9d5c8243 6020 "Detected Tx Unit Hang\n"
2d064c06 6021 " Tx Queue <%d>\n"
9d5c8243
AK		 6022 " TDH <%x>\n"
6023 " TDT <%x>\n"
6024 " next_to_use <%x>\n"
6025 " next_to_clean <%x>\n"
9d5c8243
AK		 6026 "buffer_info[next_to_clean]\n"
6027 " time_stamp <%lx>\n"
8542db05 6028 " next_to_watch <%p>\n"
9d5c8243
AK		 6029 " jiffies <%lx>\n"
6030 " desc.status <%x>\n",
2d064c06 6031 tx_ring->queue_index,
238ac817 6032 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6033 readl(tx_ring->tail),
9d5c8243
AK		 6034 tx_ring->next_to_use,
6035 tx_ring->next_to_clean,
8542db05 6036 tx_buffer->time_stamp,
f4128785 6037 tx_buffer->next_to_watch,
9d5c8243 6038 jiffies,
f4128785 6039 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6040 netif_stop_subqueue(tx_ring->netdev,
6041 tx_ring->queue_index);
6042
6043 /* we are about to reset, no point in enabling stuff */
6044 return true;
9d5c8243
AK		 6045 }
6046 }
13fde97a
AD		 6047
6048 if (unlikely(total_packets &&
6049 netif_carrier_ok(tx_ring->netdev) &&
6050 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
6051 /* Make sure that anybody stopping the queue after this
6052 * sees the new next_to_clean.
6053 */
6054 smp_mb();
6055 if (__netif_subqueue_stopped(tx_ring->netdev,
6056 tx_ring->queue_index) &&
6057 !(test_bit(__IGB_DOWN, &adapter->state))) {
6058 netif_wake_subqueue(tx_ring->netdev,
6059 tx_ring->queue_index);
6060
6061 u64_stats_update_begin(&tx_ring->tx_syncp);
6062 tx_ring->tx_stats.restart_queue++;
6063 u64_stats_update_end(&tx_ring->tx_syncp);
6064 }
6065 }
6066
6067 return !!budget;
9d5c8243
AK		 6068}
6069
cbc8e55f
AD		 6070/**
6071 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6072 * @rx_ring: rx descriptor ring to store buffers on
6073 * @old_buff: donor buffer to have page reused
6074 *
6075 * Synchronizes page for reuse by the adapter
6076 **/
6077static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6078 struct igb_rx_buffer *old_buff)
6079{
6080 struct igb_rx_buffer *new_buff;
6081 u16 nta = rx_ring->next_to_alloc;
6082
6083 new_buff = &rx_ring->rx_buffer_info[nta];
6084
6085 /* update, and store next to alloc */
6086 nta++;
6087 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6088
6089 /* transfer page from old buffer to new buffer */
6090 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6091
6092 /* sync the buffer for use by the device */
6093 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6094 old_buff->page_offset,
de78d1f9 6095 IGB_RX_BUFSZ,
cbc8e55f
AD		 6096 DMA_FROM_DEVICE);
6097}
6098
6099/**
6100 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6101 * @rx_ring: rx descriptor ring to transact packets on
6102 * @rx_buffer: buffer containing page to add
6103 * @rx_desc: descriptor containing length of buffer written by hardware
6104 * @skb: sk_buff to place the data into
6105 *
6106 * This function will add the data contained in rx_buffer->page to the skb.
6107 * This is done either through a direct copy if the data in the buffer is
6108 * less than the skb header size, otherwise it will just attach the page as
6109 * a frag to the skb.
6110 *
6111 * The function will then update the page offset if necessary and return
6112 * true if the buffer can be reused by the adapter.
6113 **/
6114static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6115 struct igb_rx_buffer *rx_buffer,
6116 union e1000_adv_rx_desc *rx_desc,
6117 struct sk_buff *skb)
6118{
6119 struct page *page = rx_buffer->page;
6120 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6121
6122 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6123 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6124
cbc8e55f
AD		 6125 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6126 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6127 va += IGB_TS_HDR_LEN;
6128 size -= IGB_TS_HDR_LEN;
6129 }
6130
cbc8e55f
AD		 6131 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6132
6133 /* we can reuse buffer as-is, just make sure it is local */
6134 if (likely(page_to_nid(page) == numa_node_id()))
6135 return true;
6136
6137 /* this page cannot be reused so discard it */
6138 put_page(page);
6139 return false;
6140 }
6141
6142 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 6143 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 6144
6145 /* avoid re-using remote pages */
6146 if (unlikely(page_to_nid(page) != numa_node_id()))
6147 return false;
6148
de78d1f9 6149#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 6150 /* if we are only owner of page we can reuse it */
6151 if (unlikely(page_count(page) != 1))
6152 return false;
6153
6154 /* flip page offset to other buffer */
de78d1f9 6155 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 6156
6157 /*
6158 * since we are the only owner of the page and we need to
6159 * increment it, just set the value to 2 in order to avoid
6160 * an unnecessary locked operation
6161 */
6162 atomic_set(&page->_count, 2);
de78d1f9
AD		 6163#else
6164 /* move offset up to the next cache line */
6165 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
6166
6167 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6168 return false;
6169
6170 /* bump ref count on page before it is given to the stack */
6171 get_page(page);
6172#endif
cbc8e55f
AD		 6173
6174 return true;
6175}
6176
2e334eee
AD		 6177static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6178 union e1000_adv_rx_desc *rx_desc,
6179 struct sk_buff *skb)
6180{
6181 struct igb_rx_buffer *rx_buffer;
6182 struct page *page;
6183
6184 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6185
6186 /*
6187 * This memory barrier is needed to keep us from reading
6188 * any other fields out of the rx_desc until we know the
6189 * RXD_STAT_DD bit is set
6190 */
6191 rmb();
6192
6193 page = rx_buffer->page;
6194 prefetchw(page);
6195
6196 if (likely(!skb)) {
6197 void *page_addr = page_address(page) +
6198 rx_buffer->page_offset;
6199
6200 /* prefetch first cache line of first page */
6201 prefetch(page_addr);
6202#if L1_CACHE_BYTES < 128
6203 prefetch(page_addr + L1_CACHE_BYTES);
6204#endif
6205
6206 /* allocate a skb to store the frags */
6207 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6208 IGB_RX_HDR_LEN);
6209 if (unlikely(!skb)) {
6210 rx_ring->rx_stats.alloc_failed++;
6211 return NULL;
6212 }
6213
6214 /*
6215 * we will be copying header into skb->data in
6216 * pskb_may_pull so it is in our interest to prefetch
6217 * it now to avoid a possible cache miss
6218 */
6219 prefetchw(skb->data);
6220 }
6221
6222 /* we are reusing so sync this buffer for CPU use */
6223 dma_sync_single_range_for_cpu(rx_ring->dev,
6224 rx_buffer->dma,
6225 rx_buffer->page_offset,
de78d1f9 6226 IGB_RX_BUFSZ,
2e334eee
AD		 6227 DMA_FROM_DEVICE);
6228
6229 /* pull page into skb */
6230 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6231 /* hand second half of page back to the ring */
6232 igb_reuse_rx_page(rx_ring, rx_buffer);
6233 } else {
6234 /* we are not reusing the buffer so unmap it */
6235 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6236 PAGE_SIZE, DMA_FROM_DEVICE);
6237 }
6238
6239 /* clear contents of rx_buffer */
6240 rx_buffer->page = NULL;
6241
6242 return skb;
6243}
6244
cd392f5c 6245static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6246 union e1000_adv_rx_desc *rx_desc,
6247 struct sk_buff *skb)
9d5c8243 6248{
bc8acf2c 6249 skb_checksum_none_assert(skb);
9d5c8243 6250
294e7d78 6251 /* Ignore Checksum bit is set */
3ceb90fd 6252 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6253 return;
6254
6255 /* Rx checksum disabled via ethtool */
6256 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6257 return;
85ad76b2 6258
9d5c8243 6259 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6260 if (igb_test_staterr(rx_desc,
6261 E1000_RXDEXT_STATERR_TCPE |
6262 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6263 /*
6264 * work around errata with sctp packets where the TCPE aka
6265 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6266 * packets, (aka let the stack check the crc32c)
6267 */
866cff06
AD		 6268 if (!((skb->len == 60) &&
6269 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6270 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6271 ring->rx_stats.csum_err++;
12dcd86b
ED		 6272 u64_stats_update_end(&ring->rx_syncp);
6273 }
9d5c8243 6274 /* let the stack verify checksum errors */
9d5c8243
AK		 6275 return;
6276 }
6277 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6278 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6279 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6280 skb->ip_summed = CHECKSUM_UNNECESSARY;
6281
3ceb90fd
AD		 6282 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6283 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6284}
6285
077887c3
AD		 6286static inline void igb_rx_hash(struct igb_ring *ring,
6287 union e1000_adv_rx_desc *rx_desc,
6288 struct sk_buff *skb)
6289{
6290 if (ring->netdev->features & NETIF_F_RXHASH)
6291 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6292}
6293
2e334eee
AD		 6294/**
6295 * igb_is_non_eop - process handling of non-EOP buffers
6296 * @rx_ring: Rx ring being processed
6297 * @rx_desc: Rx descriptor for current buffer
6298 * @skb: current socket buffer containing buffer in progress
6299 *
6300 * This function updates next to clean. If the buffer is an EOP buffer
6301 * this function exits returning false, otherwise it will place the
6302 * sk_buff in the next buffer to be chained and return true indicating
6303 * that this is in fact a non-EOP buffer.
6304 **/
6305static bool igb_is_non_eop(struct igb_ring *rx_ring,
6306 union e1000_adv_rx_desc *rx_desc)
6307{
6308 u32 ntc = rx_ring->next_to_clean + 1;
6309
6310 /* fetch, update, and store next to clean */
6311 ntc = (ntc < rx_ring->count) ? ntc : 0;
6312 rx_ring->next_to_clean = ntc;
6313
6314 prefetch(IGB_RX_DESC(rx_ring, ntc));
6315
6316 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6317 return false;
6318
6319 return true;
6320}
6321
1a1c225b
AD		 6322/**
6323 * igb_get_headlen - determine size of header for LRO/GRO
6324 * @data: pointer to the start of the headers
6325 * @max_len: total length of section to find headers in
6326 *
6327 * This function is meant to determine the length of headers that will
6328 * be recognized by hardware for LRO, and GRO offloads. The main
6329 * motivation of doing this is to only perform one pull for IPv4 TCP
6330 * packets so that we can do basic things like calculating the gso_size
6331 * based on the average data per packet.
6332 **/
6333static unsigned int igb_get_headlen(unsigned char *data,
6334 unsigned int max_len)
6335{
6336 union {
6337 unsigned char *network;
6338 /* l2 headers */
6339 struct ethhdr *eth;
6340 struct vlan_hdr *vlan;
6341 /* l3 headers */
6342 struct iphdr *ipv4;
6343 struct ipv6hdr *ipv6;
6344 } hdr;
6345 __be16 protocol;
6346 u8 nexthdr = 0; /* default to not TCP */
6347 u8 hlen;
6348
6349 /* this should never happen, but better safe than sorry */
6350 if (max_len < ETH_HLEN)
6351 return max_len;
6352
6353 /* initialize network frame pointer */
6354 hdr.network = data;
6355
6356 /* set first protocol and move network header forward */
6357 protocol = hdr.eth->h_proto;
6358 hdr.network += ETH_HLEN;
6359
6360 /* handle any vlan tag if present */
6361 if (protocol == __constant_htons(ETH_P_8021Q)) {
6362 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6363 return max_len;
6364
6365 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6366 hdr.network += VLAN_HLEN;
6367 }
6368
6369 /* handle L3 protocols */
6370 if (protocol == __constant_htons(ETH_P_IP)) {
6371 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6372 return max_len;
6373
6374 /* access ihl as a u8 to avoid unaligned access on ia64 */
6375 hlen = (hdr.network[0] & 0x0F) << 2;
6376
6377 /* verify hlen meets minimum size requirements */
6378 if (hlen < sizeof(struct iphdr))
6379 return hdr.network - data;
6380
f2fb4ab2
AD		 6381 /* record next protocol if header is present */
6382 if (!hdr.ipv4->frag_off)
6383 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6384 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6385 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6386 return max_len;
6387
6388 /* record next protocol */
6389 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6390 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6391 } else {
6392 return hdr.network - data;
6393 }
6394
f2fb4ab2
AD		 6395 /* relocate pointer to start of L4 header */
6396 hdr.network += hlen;
6397
1a1c225b
AD		 6398 /* finally sort out TCP */
6399 if (nexthdr == IPPROTO_TCP) {
6400 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6401 return max_len;
6402
6403 /* access doff as a u8 to avoid unaligned access on ia64 */
6404 hlen = (hdr.network[12] & 0xF0) >> 2;
6405
6406 /* verify hlen meets minimum size requirements */
6407 if (hlen < sizeof(struct tcphdr))
6408 return hdr.network - data;
6409
6410 hdr.network += hlen;
6411 } else if (nexthdr == IPPROTO_UDP) {
6412 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6413 return max_len;
6414
6415 hdr.network += sizeof(struct udphdr);
6416 }
6417
6418 /*
6419 * If everything has gone correctly hdr.network should be the
6420 * data section of the packet and will be the end of the header.
6421 * If not then it probably represents the end of the last recognized
6422 * header.
6423 */
6424 if ((hdr.network - data) < max_len)
6425 return hdr.network - data;
6426 else
6427 return max_len;
6428}
6429
6430/**
6431 * igb_pull_tail - igb specific version of skb_pull_tail
6432 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6433 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6434 * @skb: pointer to current skb being adjusted
6435 *
6436 * This function is an igb specific version of __pskb_pull_tail. The
6437 * main difference between this version and the original function is that
6438 * this function can make several assumptions about the state of things
6439 * that allow for significant optimizations versus the standard function.
6440 * As a result we can do things like drop a frag and maintain an accurate
6441 * truesize for the skb.
6442 */
6443static void igb_pull_tail(struct igb_ring *rx_ring,
6444 union e1000_adv_rx_desc *rx_desc,
6445 struct sk_buff *skb)
2d94d8ab 6446{
1a1c225b
AD		 6447 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6448 unsigned char *va;
6449 unsigned int pull_len;
6450
6451 /*
6452 * it is valid to use page_address instead of kmap since we are
6453 * working with pages allocated out of the lomem pool per
6454 * alloc_page(GFP_ATOMIC)
2d94d8ab 6455 */
1a1c225b
AD		 6456 va = skb_frag_address(frag);
6457
1a1c225b
AD		 6458 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6459 /* retrieve timestamp from buffer */
6460 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6461
6462 /* update pointers to remove timestamp header */
6463 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6464 frag->page_offset += IGB_TS_HDR_LEN;
6465 skb->data_len -= IGB_TS_HDR_LEN;
6466 skb->len -= IGB_TS_HDR_LEN;
6467
6468 /* move va to start of packet data */
6469 va += IGB_TS_HDR_LEN;
6470 }
6471
1a1c225b
AD		 6472 /*
6473 * we need the header to contain the greater of either ETH_HLEN or
6474 * 60 bytes if the skb->len is less than 60 for skb_pad.
6475 */
6476 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6477
6478 /* align pull length to size of long to optimize memcpy performance */
6479 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6480
6481 /* update all of the pointers */
6482 skb_frag_size_sub(frag, pull_len);
6483 frag->page_offset += pull_len;
6484 skb->data_len -= pull_len;
6485 skb->tail += pull_len;
6486}
6487
6488/**
6489 * igb_cleanup_headers - Correct corrupted or empty headers
6490 * @rx_ring: rx descriptor ring packet is being transacted on
6491 * @rx_desc: pointer to the EOP Rx descriptor
6492 * @skb: pointer to current skb being fixed
6493 *
6494 * Address the case where we are pulling data in on pages only
6495 * and as such no data is present in the skb header.
6496 *
6497 * In addition if skb is not at least 60 bytes we need to pad it so that
6498 * it is large enough to qualify as a valid Ethernet frame.
6499 *
6500 * Returns true if an error was encountered and skb was freed.
6501 **/
6502static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6503 union e1000_adv_rx_desc *rx_desc,
6504 struct sk_buff *skb)
6505{
6506
6507 if (unlikely((igb_test_staterr(rx_desc,
6508 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6509 struct net_device *netdev = rx_ring->netdev;
6510 if (!(netdev->features & NETIF_F_RXALL)) {
6511 dev_kfree_skb_any(skb);
6512 return true;
6513 }
6514 }
6515
6516 /* place header in linear portion of buffer */
6517 if (skb_is_nonlinear(skb))
6518 igb_pull_tail(rx_ring, rx_desc, skb);
6519
6520 /* if skb_pad returns an error the skb was freed */
6521 if (unlikely(skb->len < 60)) {
6522 int pad_len = 60 - skb->len;
6523
6524 if (skb_pad(skb, pad_len))
6525 return true;
6526 __skb_put(skb, pad_len);
6527 }
6528
6529 return false;
2d94d8ab
AD		 6530}
6531
db2ee5bd
AD		 6532/**
6533 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6534 * @rx_ring: rx descriptor ring packet is being transacted on
6535 * @rx_desc: pointer to the EOP Rx descriptor
6536 * @skb: pointer to current skb being populated
6537 *
6538 * This function checks the ring, descriptor, and packet information in
6539 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6540 * other fields within the skb.
6541 **/
6542static void igb_process_skb_fields(struct igb_ring *rx_ring,
6543 union e1000_adv_rx_desc *rx_desc,
6544 struct sk_buff *skb)
6545{
6546 struct net_device *dev = rx_ring->netdev;
6547
6548 igb_rx_hash(rx_ring, rx_desc, skb);
6549
6550 igb_rx_checksum(rx_ring, rx_desc, skb);
6551
db2ee5bd 6552 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6553
6554 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6555 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6556 u16 vid;
6557 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6558 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6559 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6560 else
6561 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6562
6563 __vlan_hwaccel_put_tag(skb, vid);
6564 }
6565
6566 skb_record_rx_queue(skb, rx_ring->queue_index);
6567
6568 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6569}
6570
2e334eee 6571static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6572{
0ba82994 6573 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6574 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6575 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6576 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6577
2e334eee
AD		 6578 do {
6579 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6580
2e334eee
AD		 6581 /* return some buffers to hardware, one at a time is too slow */
6582 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6583 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6584 cleaned_count = 0;
6585 }
bf36c1a0 6586
2e334eee 6587 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6588
2e334eee
AD		 6589 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6590 break;
9d5c8243 6591
2e334eee
AD		 6592 /* retrieve a buffer from the ring */
6593 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6594
2e334eee
AD		 6595 /* exit if we failed to retrieve a buffer */
6596 if (!skb)
6597 break;
1a1c225b 6598
2e334eee 6599 cleaned_count++;
1a1c225b 6600
2e334eee
AD		 6601 /* fetch next buffer in frame if non-eop */
6602 if (igb_is_non_eop(rx_ring, rx_desc))
6603 continue;
1a1c225b
AD		 6604
6605 /* verify the packet layout is correct */
6606 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6607 skb = NULL;
6608 continue;
9d5c8243 6609 }
9d5c8243 6610
db2ee5bd 6611 /* probably a little skewed due to removing CRC */
3ceb90fd 6612 total_bytes += skb->len;
3ceb90fd 6613
db2ee5bd
AD		 6614 /* populate checksum, timestamp, VLAN, and protocol */
6615 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6616
b2cb09b1 6617 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6618
1a1c225b
AD		 6619 /* reset skb pointer */
6620 skb = NULL;
6621
2e334eee
AD		 6622 /* update budget accounting */
6623 total_packets++;
6624 } while (likely(total_packets < budget));
bf36c1a0 6625
1a1c225b
AD		 6626 /* place incomplete frames back on ring for completion */
6627 rx_ring->skb = skb;
6628
12dcd86b 6629 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6630 rx_ring->rx_stats.packets += total_packets;
6631 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6632 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6633 q_vector->rx.total_packets += total_packets;
6634 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6635
6636 if (cleaned_count)
cd392f5c 6637 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6638
2e334eee 6639 return (total_packets < budget);
9d5c8243
AK		 6640}
6641
c023cd88 6642static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6643 struct igb_rx_buffer *bi)
c023cd88
AD		 6644{
6645 struct page *page = bi->page;
cbc8e55f 6646 dma_addr_t dma;
c023cd88 6647
cbc8e55f
AD		 6648 /* since we are recycling buffers we should seldom need to alloc */
6649 if (likely(page))
c023cd88
AD		 6650 return true;
6651
cbc8e55f
AD		 6652 /* alloc new page for storage */
6653 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6654 if (unlikely(!page)) {
6655 rx_ring->rx_stats.alloc_failed++;
6656 return false;
c023cd88
AD		 6657 }
6658
cbc8e55f
AD		 6659 /* map page for use */
6660 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6661
cbc8e55f
AD		 6662 /*
6663 * if mapping failed free memory back to system since
6664 * there isn't much point in holding memory we can't use
6665 */
1a1c225b 6666 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6667 __free_page(page);
6668
c023cd88
AD		 6669 rx_ring->rx_stats.alloc_failed++;
6670 return false;
6671 }
6672
1a1c225b 6673 bi->dma = dma;
cbc8e55f
AD		 6674 bi->page = page;
6675 bi->page_offset = 0;
1a1c225b 6676
c023cd88
AD		 6677 return true;
6678}
6679
9d5c8243 6680/**
cd392f5c 6681 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6682 * @adapter: address of board private structure
6683 **/
cd392f5c 6684void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6685{
9d5c8243 6686 union e1000_adv_rx_desc *rx_desc;
06034649 6687 struct igb_rx_buffer *bi;
c023cd88 6688 u16 i = rx_ring->next_to_use;
9d5c8243 6689
cbc8e55f
AD		 6690 /* nothing to do */
6691 if (!cleaned_count)
6692 return;
6693
60136906 6694 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6695 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6696 i -= rx_ring->count;
9d5c8243 6697
cbc8e55f 6698 do {
1a1c225b 6699 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6700 break;
9d5c8243 6701
cbc8e55f
AD		 6702 /*
6703 * Refresh the desc even if buffer_addrs didn't change
6704 * because each write-back erases this info.
6705 */
6706 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6707
c023cd88
AD		 6708 rx_desc++;
6709 bi++;
9d5c8243 6710 i++;
c023cd88 6711 if (unlikely(!i)) {
60136906 6712 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6713 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6714 i -= rx_ring->count;
6715 }
6716
6717 /* clear the hdr_addr for the next_to_use descriptor */
6718 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6719
6720 cleaned_count--;
6721 } while (cleaned_count);
9d5c8243 6722
c023cd88
AD		 6723 i += rx_ring->count;
6724
9d5c8243 6725 if (rx_ring->next_to_use != i) {
cbc8e55f 6726 /* record the next descriptor to use */
9d5c8243 6727 rx_ring->next_to_use = i;
9d5c8243 6728
cbc8e55f
AD		 6729 /* update next to alloc since we have filled the ring */
6730 rx_ring->next_to_alloc = i;
6731
6732 /*
6733 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6734 * know there are new descriptors to fetch. (Only
6735 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6736 * such as IA-64).
6737 */
9d5c8243 6738 wmb();
fce99e34 6739 writel(i, rx_ring->tail);
9d5c8243
AK		 6740 }
6741}
6742
6743/**
6744 * igb_mii_ioctl -
6745 * @netdev:
6746 * @ifreq:
6747 * @cmd:
6748 **/
6749static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6750{
6751 struct igb_adapter *adapter = netdev_priv(netdev);
6752 struct mii_ioctl_data *data = if_mii(ifr);
6753
6754 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6755 return -EOPNOTSUPP;
6756
6757 switch (cmd) {
6758 case SIOCGMIIPHY:
6759 data->phy_id = adapter->hw.phy.addr;
6760 break;
6761 case SIOCGMIIREG:
f5f4cf08
AD		 6762 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6763 &data->val_out))
9d5c8243
AK		 6764 return -EIO;
6765 break;
6766 case SIOCSMIIREG:
6767 default:
6768 return -EOPNOTSUPP;
6769 }
6770 return 0;
6771}
6772
6773/**
6774 * igb_ioctl -
6775 * @netdev:
6776 * @ifreq:
6777 * @cmd:
6778 **/
6779static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6780{
6781 switch (cmd) {
6782 case SIOCGMIIPHY:
6783 case SIOCGMIIREG:
6784 case SIOCSMIIREG:
6785 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6786 case SIOCSHWTSTAMP:
a79f4f88 6787 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6788 default:
6789 return -EOPNOTSUPP;
6790 }
6791}
6792
009bc06e
AD		 6793s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6794{
6795 struct igb_adapter *adapter = hw->back;
009bc06e 6796
23d028cc 6797 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6798 return -E1000_ERR_CONFIG;
6799
009bc06e
AD		 6800 return 0;
6801}
6802
6803s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6804{
6805 struct igb_adapter *adapter = hw->back;
009bc06e 6806
23d028cc 6807 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6808 return -E1000_ERR_CONFIG;
6809
009bc06e
AD		 6810 return 0;
6811}
6812
c8f44aff 6813static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6814{
6815 struct igb_adapter *adapter = netdev_priv(netdev);
6816 struct e1000_hw *hw = &adapter->hw;
6817 u32 ctrl, rctl;
5faf030c 6818 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6819
5faf030c 6820 if (enable) {
9d5c8243
AK		 6821 /* enable VLAN tag insert/strip */
6822 ctrl = rd32(E1000_CTRL);
6823 ctrl |= E1000_CTRL_VME;
6824 wr32(E1000_CTRL, ctrl);
6825
51466239 6826 /* Disable CFI check */
9d5c8243 6827 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6828 rctl &= ~E1000_RCTL_CFIEN;
6829 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6830 } else {
6831 /* disable VLAN tag insert/strip */
6832 ctrl = rd32(E1000_CTRL);
6833 ctrl &= ~E1000_CTRL_VME;
6834 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6835 }
6836
e1739522 6837 igb_rlpml_set(adapter);
9d5c8243
AK		 6838}
6839
8e586137 6840static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6841{
6842 struct igb_adapter *adapter = netdev_priv(netdev);
6843 struct e1000_hw *hw = &adapter->hw;
4ae196df 6844 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6845
51466239
AD		 6846 /* attempt to add filter to vlvf array */
6847 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6848
51466239
AD		 6849 /* add the filter since PF can receive vlans w/o entry in vlvf */
6850 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6851
6852 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6853
6854 return 0;
9d5c8243
AK		 6855}
6856
8e586137 6857static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6858{
6859 struct igb_adapter *adapter = netdev_priv(netdev);
6860 struct e1000_hw *hw = &adapter->hw;
4ae196df 6861 int pf_id = adapter->vfs_allocated_count;
51466239 6862 s32 err;
9d5c8243 6863
51466239
AD		 6864 /* remove vlan from VLVF table array */
6865 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6866
51466239
AD		 6867 /* if vid was not present in VLVF just remove it from table */
6868 if (err)
4ae196df 6869 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6870
6871 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6872
6873 return 0;
9d5c8243
AK		 6874}
6875
6876static void igb_restore_vlan(struct igb_adapter *adapter)
6877{
b2cb09b1 6878 u16 vid;
9d5c8243 6879
5faf030c
AD		 6880 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6881
b2cb09b1
JP		 6882 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6883 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6884}
6885
14ad2513 6886int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6887{
090b1795 6888 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6889 struct e1000_mac_info *mac = &adapter->hw.mac;
6890
6891 mac->autoneg = 0;
6892
14ad2513
DD		 6893 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6894 * for the switch() below to work */
6895 if ((spd & 1) || (dplx & ~1))
6896 goto err_inval;
6897
cd2638a8
CW		 6898 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6899 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6900 spd != SPEED_1000 &&
6901 dplx != DUPLEX_FULL)
6902 goto err_inval;
cd2638a8 6903
14ad2513 6904 switch (spd + dplx) {
9d5c8243
AK		 6905 case SPEED_10 + DUPLEX_HALF:
6906 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6907 break;
6908 case SPEED_10 + DUPLEX_FULL:
6909 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6910 break;
6911 case SPEED_100 + DUPLEX_HALF:
6912 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6913 break;
6914 case SPEED_100 + DUPLEX_FULL:
6915 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6916 break;
6917 case SPEED_1000 + DUPLEX_FULL:
6918 mac->autoneg = 1;
6919 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6920 break;
6921 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6922 default:
14ad2513 6923 goto err_inval;
9d5c8243 6924 }
8376dad0
JB		 6925
6926 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6927 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6928
9d5c8243 6929 return 0;
14ad2513
DD		 6930
6931err_inval:
6932 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6933 return -EINVAL;
9d5c8243
AK		 6934}
6935
749ab2cd
YZ		 6936static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6937 bool runtime)
9d5c8243
AK		 6938{
6939 struct net_device *netdev = pci_get_drvdata(pdev);
6940 struct igb_adapter *adapter = netdev_priv(netdev);
6941 struct e1000_hw *hw = &adapter->hw;
2d064c06 6942 u32 ctrl, rctl, status;
749ab2cd 6943 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6944#ifdef CONFIG_PM
6945 int retval = 0;
6946#endif
6947
6948 netif_device_detach(netdev);
6949
a88f10ec 6950 if (netif_running(netdev))
749ab2cd 6951 __igb_close(netdev, true);
a88f10ec 6952
047e0030 6953 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6954
6955#ifdef CONFIG_PM
6956 retval = pci_save_state(pdev);
6957 if (retval)
6958 return retval;
6959#endif
6960
6961 status = rd32(E1000_STATUS);
6962 if (status & E1000_STATUS_LU)
6963 wufc &= ~E1000_WUFC_LNKC;
6964
6965 if (wufc) {
6966 igb_setup_rctl(adapter);
ff41f8dc 6967 igb_set_rx_mode(netdev);
9d5c8243
AK		 6968
6969 /* turn on all-multi mode if wake on multicast is enabled */
6970 if (wufc & E1000_WUFC_MC) {
6971 rctl = rd32(E1000_RCTL);
6972 rctl |= E1000_RCTL_MPE;
6973 wr32(E1000_RCTL, rctl);
6974 }
6975
6976 ctrl = rd32(E1000_CTRL);
6977 /* advertise wake from D3Cold */
6978 #define E1000_CTRL_ADVD3WUC 0x00100000
6979 /* phy power management enable */
6980 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6981 ctrl |= E1000_CTRL_ADVD3WUC;
6982 wr32(E1000_CTRL, ctrl);
6983
9d5c8243 6984 /* Allow time for pending master requests to run */
330a6d6a 6985 igb_disable_pcie_master(hw);
9d5c8243
AK		 6986
6987 wr32(E1000_WUC, E1000_WUC_PME_EN);
6988 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6989 } else {
6990 wr32(E1000_WUC, 0);
6991 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6992 }
6993
3fe7c4c9
RW		 6994 *enable_wake = wufc || adapter->en_mng_pt;
6995 if (!*enable_wake)
88a268c1
NN		 6996 igb_power_down_link(adapter);
6997 else
6998 igb_power_up_link(adapter);
9d5c8243
AK		 6999
7000 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7001 * would have already happened in close and is redundant. */
7002 igb_release_hw_control(adapter);
7003
7004 pci_disable_device(pdev);
7005
9d5c8243
AK		 7006 return 0;
7007}
7008
7009#ifdef CONFIG_PM
d9dd966d 7010#ifdef CONFIG_PM_SLEEP
749ab2cd 7011static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7012{
7013 int retval;
7014 bool wake;
749ab2cd 7015 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7016
749ab2cd 7017 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7018 if (retval)
7019 return retval;
7020
7021 if (wake) {
7022 pci_prepare_to_sleep(pdev);
7023 } else {
7024 pci_wake_from_d3(pdev, false);
7025 pci_set_power_state(pdev, PCI_D3hot);
7026 }
7027
7028 return 0;
7029}
d9dd966d 7030#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7031
749ab2cd 7032static int igb_resume(struct device *dev)
9d5c8243 7033{
749ab2cd 7034 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7035 struct net_device *netdev = pci_get_drvdata(pdev);
7036 struct igb_adapter *adapter = netdev_priv(netdev);
7037 struct e1000_hw *hw = &adapter->hw;
7038 u32 err;
7039
7040 pci_set_power_state(pdev, PCI_D0);
7041 pci_restore_state(pdev);
b94f2d77 7042 pci_save_state(pdev);
42bfd33a 7043
aed5dec3 7044 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7045 if (err) {
7046 dev_err(&pdev->dev,
7047 "igb: Cannot enable PCI device from suspend\n");
7048 return err;
7049 }
7050 pci_set_master(pdev);
7051
7052 pci_enable_wake(pdev, PCI_D3hot, 0);
7053 pci_enable_wake(pdev, PCI_D3cold, 0);
7054
53c7d064 7055 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7056 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7057 return -ENOMEM;
9d5c8243
AK		 7058 }
7059
9d5c8243 7060 igb_reset(adapter);
a8564f03
AD		 7061
7062 /* let the f/w know that the h/w is now under the control of the
7063 * driver. */
7064 igb_get_hw_control(adapter);
7065
9d5c8243
AK		 7066 wr32(E1000_WUS, ~0);
7067
749ab2cd 7068 if (netdev->flags & IFF_UP) {
0c2cc02e 7069 rtnl_lock();
749ab2cd 7070 err = __igb_open(netdev, true);
0c2cc02e 7071 rtnl_unlock();
a88f10ec
AD		 7072 if (err)
7073 return err;
7074 }
9d5c8243
AK		 7075
7076 netif_device_attach(netdev);
749ab2cd
YZ		 7077 return 0;
7078}
7079
7080#ifdef CONFIG_PM_RUNTIME
7081static int igb_runtime_idle(struct device *dev)
7082{
7083 struct pci_dev *pdev = to_pci_dev(dev);
7084 struct net_device *netdev = pci_get_drvdata(pdev);
7085 struct igb_adapter *adapter = netdev_priv(netdev);
7086
7087 if (!igb_has_link(adapter))
7088 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7089
7090 return -EBUSY;
7091}
7092
7093static int igb_runtime_suspend(struct device *dev)
7094{
7095 struct pci_dev *pdev = to_pci_dev(dev);
7096 int retval;
7097 bool wake;
7098
7099 retval = __igb_shutdown(pdev, &wake, 1);
7100 if (retval)
7101 return retval;
7102
7103 if (wake) {
7104 pci_prepare_to_sleep(pdev);
7105 } else {
7106 pci_wake_from_d3(pdev, false);
7107 pci_set_power_state(pdev, PCI_D3hot);
7108 }
9d5c8243 7109
9d5c8243
AK		 7110 return 0;
7111}
749ab2cd
YZ		 7112
7113static int igb_runtime_resume(struct device *dev)
7114{
7115 return igb_resume(dev);
7116}
7117#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7118#endif
7119
7120static void igb_shutdown(struct pci_dev *pdev)
7121{
3fe7c4c9
RW		 7122 bool wake;
7123
749ab2cd 7124 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7125
7126 if (system_state == SYSTEM_POWER_OFF) {
7127 pci_wake_from_d3(pdev, wake);
7128 pci_set_power_state(pdev, PCI_D3hot);
7129 }
9d5c8243
AK		 7130}
7131
fa44f2f1
GR		 7132#ifdef CONFIG_PCI_IOV
7133static int igb_sriov_reinit(struct pci_dev *dev)
7134{
7135 struct net_device *netdev = pci_get_drvdata(dev);
7136 struct igb_adapter *adapter = netdev_priv(netdev);
7137 struct pci_dev *pdev = adapter->pdev;
7138
7139 rtnl_lock();
7140
7141 if (netif_running(netdev))
7142 igb_close(netdev);
7143
7144 igb_clear_interrupt_scheme(adapter);
7145
7146 igb_init_queue_configuration(adapter);
7147
7148 if (igb_init_interrupt_scheme(adapter, true)) {
7149 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7150 return -ENOMEM;
7151 }
7152
7153 if (netif_running(netdev))
7154 igb_open(netdev);
7155
7156 rtnl_unlock();
7157
7158 return 0;
7159}
7160
7161static int igb_pci_disable_sriov(struct pci_dev *dev)
7162{
7163 int err = igb_disable_sriov(dev);
7164
7165 if (!err)
7166 err = igb_sriov_reinit(dev);
7167
7168 return err;
7169}
7170
7171static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7172{
7173 int err = igb_enable_sriov(dev, num_vfs);
7174
7175 if (err)
7176 goto out;
7177
7178 err = igb_sriov_reinit(dev);
7179 if (!err)
7180 return num_vfs;
7181
7182out:
7183 return err;
7184}
7185
7186#endif
7187static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7188{
7189#ifdef CONFIG_PCI_IOV
7190 if (num_vfs == 0)
7191 return igb_pci_disable_sriov(dev);
7192 else
7193 return igb_pci_enable_sriov(dev, num_vfs);
7194#endif
7195 return 0;
7196}
7197
9d5c8243
AK		 7198#ifdef CONFIG_NET_POLL_CONTROLLER
7199/*
7200 * Polling 'interrupt' - used by things like netconsole to send skbs
7201 * without having to re-enable interrupts. It's not called while
7202 * the interrupt routine is executing.
7203 */
7204static void igb_netpoll(struct net_device *netdev)
7205{
7206 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7207 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7208 struct igb_q_vector *q_vector;
9d5c8243 7209 int i;
9d5c8243 7210
047e0030 7211 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7212 q_vector = adapter->q_vector[i];
7213 if (adapter->msix_entries)
7214 wr32(E1000_EIMC, q_vector->eims_value);
7215 else
7216 igb_irq_disable(adapter);
047e0030 7217 napi_schedule(&q_vector->napi);
eebbbdba 7218 }
9d5c8243
AK		 7219}
7220#endif /* CONFIG_NET_POLL_CONTROLLER */
7221
7222/**
7223 * igb_io_error_detected - called when PCI error is detected
7224 * @pdev: Pointer to PCI device
7225 * @state: The current pci connection state
7226 *
7227 * This function is called after a PCI bus error affecting
7228 * this device has been detected.
7229 */
7230static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7231 pci_channel_state_t state)
7232{
7233 struct net_device *netdev = pci_get_drvdata(pdev);
7234 struct igb_adapter *adapter = netdev_priv(netdev);
7235
7236 netif_device_detach(netdev);
7237
59ed6eec
AD		 7238 if (state == pci_channel_io_perm_failure)
7239 return PCI_ERS_RESULT_DISCONNECT;
7240
9d5c8243
AK		 7241 if (netif_running(netdev))
7242 igb_down(adapter);
7243 pci_disable_device(pdev);
7244
7245 /* Request a slot slot reset. */
7246 return PCI_ERS_RESULT_NEED_RESET;
7247}
7248
7249/**
7250 * igb_io_slot_reset - called after the pci bus has been reset.
7251 * @pdev: Pointer to PCI device
7252 *
7253 * Restart the card from scratch, as if from a cold-boot. Implementation
7254 * resembles the first-half of the igb_resume routine.
7255 */
7256static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7257{
7258 struct net_device *netdev = pci_get_drvdata(pdev);
7259 struct igb_adapter *adapter = netdev_priv(netdev);
7260 struct e1000_hw *hw = &adapter->hw;
40a914fa 7261 pci_ers_result_t result;
42bfd33a 7262 int err;
9d5c8243 7263
aed5dec3 7264 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7265 dev_err(&pdev->dev,
7266 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7267 result = PCI_ERS_RESULT_DISCONNECT;
7268 } else {
7269 pci_set_master(pdev);
7270 pci_restore_state(pdev);
b94f2d77 7271 pci_save_state(pdev);
9d5c8243 7272
40a914fa
AD		 7273 pci_enable_wake(pdev, PCI_D3hot, 0);
7274 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7275
40a914fa
AD		 7276 igb_reset(adapter);
7277 wr32(E1000_WUS, ~0);
7278 result = PCI_ERS_RESULT_RECOVERED;
7279 }
9d5c8243 7280
ea943d41
JK		 7281 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7282 if (err) {
7283 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7284 "failed 0x%0x\n", err);
7285 /* non-fatal, continue */
7286 }
40a914fa
AD		 7287
7288 return result;
9d5c8243
AK		 7289}
7290
7291/**
7292 * igb_io_resume - called when traffic can start flowing again.
7293 * @pdev: Pointer to PCI device
7294 *
7295 * This callback is called when the error recovery driver tells us that
7296 * its OK to resume normal operation. Implementation resembles the
7297 * second-half of the igb_resume routine.
7298 */
7299static void igb_io_resume(struct pci_dev *pdev)
7300{
7301 struct net_device *netdev = pci_get_drvdata(pdev);
7302 struct igb_adapter *adapter = netdev_priv(netdev);
7303
9d5c8243
AK		 7304 if (netif_running(netdev)) {
7305 if (igb_up(adapter)) {
7306 dev_err(&pdev->dev, "igb_up failed after reset\n");
7307 return;
7308 }
7309 }
7310
7311 netif_device_attach(netdev);
7312
7313 /* let the f/w know that the h/w is now under the control of the
7314 * driver. */
7315 igb_get_hw_control(adapter);
9d5c8243
AK		 7316}
7317
26ad9178
AD		 7318static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7319 u8 qsel)
7320{
7321 u32 rar_low, rar_high;
7322 struct e1000_hw *hw = &adapter->hw;
7323
7324 /* HW expects these in little endian so we reverse the byte order
7325 * from network order (big endian) to little endian
7326 */
7327 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7328 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7329 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7330
7331 /* Indicate to hardware the Address is Valid. */
7332 rar_high |= E1000_RAH_AV;
7333
7334 if (hw->mac.type == e1000_82575)
7335 rar_high |= E1000_RAH_POOL_1 * qsel;
7336 else
7337 rar_high |= E1000_RAH_POOL_1 << qsel;
7338
7339 wr32(E1000_RAL(index), rar_low);
7340 wrfl();
7341 wr32(E1000_RAH(index), rar_high);
7342 wrfl();
7343}
7344
4ae196df
AD		 7345static int igb_set_vf_mac(struct igb_adapter *adapter,
7346 int vf, unsigned char *mac_addr)
7347{
7348 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7349 /* VF MAC addresses start at end of receive addresses and moves
7350 * torwards the first, as a result a collision should not be possible */
7351 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7352
37680117 7353 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7354
26ad9178 7355 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7356
7357 return 0;
7358}
7359
8151d294
WM		 7360static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7361{
7362 struct igb_adapter *adapter = netdev_priv(netdev);
7363 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7364 return -EINVAL;
7365 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7366 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7367 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7368 " change effective.");
7369 if (test_bit(__IGB_DOWN, &adapter->state)) {
7370 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7371 " but the PF device is not up.\n");
7372 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7373 " attempting to use the VF device.\n");
7374 }
7375 return igb_set_vf_mac(adapter, vf, mac);
7376}
7377
17dc566c
LL		 7378static int igb_link_mbps(int internal_link_speed)
7379{
7380 switch (internal_link_speed) {
7381 case SPEED_100:
7382 return 100;
7383 case SPEED_1000:
7384 return 1000;
7385 default:
7386 return 0;
7387 }
7388}
7389
7390static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7391 int link_speed)
7392{
7393 int rf_dec, rf_int;
7394 u32 bcnrc_val;
7395
7396 if (tx_rate != 0) {
7397 /* Calculate the rate factor values to set */
7398 rf_int = link_speed / tx_rate;
7399 rf_dec = (link_speed - (rf_int * tx_rate));
7400 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7401
7402 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7403 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7404 E1000_RTTBCNRC_RF_INT_MASK);
7405 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7406 } else {
7407 bcnrc_val = 0;
7408 }
7409
7410 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7411 /*
7412 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7413 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7414 */
7415 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7416 wr32(E1000_RTTBCNRC, bcnrc_val);
7417}
7418
7419static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7420{
7421 int actual_link_speed, i;
7422 bool reset_rate = false;
7423
7424 /* VF TX rate limit was not set or not supported */
7425 if ((adapter->vf_rate_link_speed == 0) ||
7426 (adapter->hw.mac.type != e1000_82576))
7427 return;
7428
7429 actual_link_speed = igb_link_mbps(adapter->link_speed);
7430 if (actual_link_speed != adapter->vf_rate_link_speed) {
7431 reset_rate = true;
7432 adapter->vf_rate_link_speed = 0;
7433 dev_info(&adapter->pdev->dev,
7434 "Link speed has been changed. VF Transmit "
7435 "rate is disabled\n");
7436 }
7437
7438 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7439 if (reset_rate)
7440 adapter->vf_data[i].tx_rate = 0;
7441
7442 igb_set_vf_rate_limit(&adapter->hw, i,
7443 adapter->vf_data[i].tx_rate,
7444 actual_link_speed);
7445 }
7446}
7447
8151d294
WM		 7448static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7449{
17dc566c
LL		 7450 struct igb_adapter *adapter = netdev_priv(netdev);
7451 struct e1000_hw *hw = &adapter->hw;
7452 int actual_link_speed;
7453
7454 if (hw->mac.type != e1000_82576)
7455 return -EOPNOTSUPP;
7456
7457 actual_link_speed = igb_link_mbps(adapter->link_speed);
7458 if ((vf >= adapter->vfs_allocated_count) ||
7459 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7460 (tx_rate < 0) || (tx_rate > actual_link_speed))
7461 return -EINVAL;
7462
7463 adapter->vf_rate_link_speed = actual_link_speed;
7464 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7465 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7466
7467 return 0;
8151d294
WM		 7468}
7469
7470static int igb_ndo_get_vf_config(struct net_device *netdev,
7471 int vf, struct ifla_vf_info *ivi)
7472{
7473 struct igb_adapter *adapter = netdev_priv(netdev);
7474 if (vf >= adapter->vfs_allocated_count)
7475 return -EINVAL;
7476 ivi->vf = vf;
7477 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7478 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7479 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7480 ivi->qos = adapter->vf_data[vf].pf_qos;
7481 return 0;
7482}
7483
4ae196df
AD		 7484static void igb_vmm_control(struct igb_adapter *adapter)
7485{
7486 struct e1000_hw *hw = &adapter->hw;
10d8e907 7487 u32 reg;
4ae196df 7488
52a1dd4d
AD		 7489 switch (hw->mac.type) {
7490 case e1000_82575:
f96a8a0b
CW		 7491 case e1000_i210:
7492 case e1000_i211:
52a1dd4d
AD		 7493 default:
7494 /* replication is not supported for 82575 */
4ae196df 7495 return;
52a1dd4d
AD		 7496 case e1000_82576:
7497 /* notify HW that the MAC is adding vlan tags */
7498 reg = rd32(E1000_DTXCTL);
7499 reg |= E1000_DTXCTL_VLAN_ADDED;
7500 wr32(E1000_DTXCTL, reg);
7501 case e1000_82580:
7502 /* enable replication vlan tag stripping */
7503 reg = rd32(E1000_RPLOLR);
7504 reg |= E1000_RPLOLR_STRVLAN;
7505 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7506 case e1000_i350:
7507 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7508 break;
7509 }
10d8e907 7510
d4960307
AD		 7511 if (adapter->vfs_allocated_count) {
7512 igb_vmdq_set_loopback_pf(hw, true);
7513 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7514 igb_vmdq_set_anti_spoofing_pf(hw, true,
7515 adapter->vfs_allocated_count);
d4960307
AD		 7516 } else {
7517 igb_vmdq_set_loopback_pf(hw, false);
7518 igb_vmdq_set_replication_pf(hw, false);
7519 }
4ae196df
AD		 7520}
7521
b6e0c419
CW		 7522static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7523{
7524 struct e1000_hw *hw = &adapter->hw;
7525 u32 dmac_thr;
7526 u16 hwm;
7527
7528 if (hw->mac.type > e1000_82580) {
7529 if (adapter->flags & IGB_FLAG_DMAC) {
7530 u32 reg;
7531
7532 /* force threshold to 0. */
7533 wr32(E1000_DMCTXTH, 0);
7534
7535 /*
e8c626e9
MV		 7536 * DMA Coalescing high water mark needs to be greater
7537 * than the Rx threshold. Set hwm to PBA - max frame
7538 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7539 */
e8c626e9
MV		 7540 hwm = 64 * pba - adapter->max_frame_size / 16;
7541 if (hwm < 64 * (pba - 6))
7542 hwm = 64 * (pba - 6);
7543 reg = rd32(E1000_FCRTC);
7544 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7545 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7546 & E1000_FCRTC_RTH_COAL_MASK);
7547 wr32(E1000_FCRTC, reg);
7548
7549 /*
7550 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7551 * frame size, capping it at PBA - 10KB.
7552 */
7553 dmac_thr = pba - adapter->max_frame_size / 512;
7554 if (dmac_thr < pba - 10)
7555 dmac_thr = pba - 10;
b6e0c419
CW		 7556 reg = rd32(E1000_DMACR);
7557 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7558 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7559 & E1000_DMACR_DMACTHR_MASK);
7560
7561 /* transition to L0x or L1 if available..*/
7562 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7563
7564 /* watchdog timer= +-1000 usec in 32usec intervals */
7565 reg |= (1000 >> 5);
0c02dd98
MV		 7566
7567 /* Disable BMC-to-OS Watchdog Enable */
7568 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7569 wr32(E1000_DMACR, reg);
7570
7571 /*
7572 * no lower threshold to disable
7573 * coalescing(smart fifb)-UTRESH=0
7574 */
7575 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7576
7577 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7578
7579 wr32(E1000_DMCTLX, reg);
7580
7581 /*
7582 * free space in tx packet buffer to wake from
7583 * DMA coal
7584 */
7585 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7586 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7587
7588 /*
7589 * make low power state decision controlled
7590 * by DMA coal
7591 */
7592 reg = rd32(E1000_PCIEMISC);
7593 reg &= ~E1000_PCIEMISC_LX_DECISION;
7594 wr32(E1000_PCIEMISC, reg);
7595 } /* endif adapter->dmac is not disabled */
7596 } else if (hw->mac.type == e1000_82580) {
7597 u32 reg = rd32(E1000_PCIEMISC);
7598 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7599 wr32(E1000_DMACR, 0);
7600 }
7601}
7602
441fc6fd
CW		 7603static DEFINE_SPINLOCK(i2c_clients_lock);
7604
7605/* igb_get_i2c_client - returns matching client
7606 * in adapters's client list.
7607 * @adapter: adapter struct
7608 * @dev_addr: device address of i2c needed.
7609 */
7610struct i2c_client *
7611igb_get_i2c_client(struct igb_adapter *adapter, u8 dev_addr)
7612{
7613 ulong flags;
7614 struct igb_i2c_client_list *client_list;
7615 struct i2c_client *client = NULL;
7616 struct i2c_board_info client_info = {
7617 I2C_BOARD_INFO("igb", 0x00),
7618 };
7619
7620 spin_lock_irqsave(&i2c_clients_lock, flags);
7621 client_list = adapter->i2c_clients;
7622
7623 /* See if we already have an i2c_client */
7624 while (client_list) {
7625 if (client_list->client->addr == (dev_addr >> 1)) {
7626 client = client_list->client;
7627 goto exit;
7628 } else {
7629 client_list = client_list->next;
7630 }
7631 }
7632
e428893b
CW		 7633 /* no client_list found, create a new one as long as
7634 * irqs are not disabled
7635 */
7636 if (unlikely(irqs_disabled()))
7637 goto exit;
7638
441fc6fd
CW		 7639 client_list = kzalloc(sizeof(*client_list), GFP_KERNEL);
7640 if (client_list == NULL)
7641 goto exit;
7642
7643 /* dev_addr passed to us is left-shifted by 1 bit
7644 * i2c_new_device call expects it to be flush to the right.
7645 */
7646 client_info.addr = dev_addr >> 1;
7647 client_info.platform_data = adapter;
7648 client_list->client = i2c_new_device(&adapter->i2c_adap, &client_info);
7649 if (client_list->client == NULL) {
e428893b
CW		 7650 dev_info(&adapter->pdev->dev,
7651 "Failed to create new i2c device..\n");
441fc6fd
CW		 7652 goto err_no_client;
7653 }
7654
7655 /* insert new client at head of list */
7656 client_list->next = adapter->i2c_clients;
7657 adapter->i2c_clients = client_list;
7658
441fc6fd
CW		 7659 client = client_list->client;
7660 goto exit;
7661
7662err_no_client:
7663 kfree(client_list);
7664exit:
7665 spin_unlock_irqrestore(&i2c_clients_lock, flags);
7666 return client;
7667}
7668
7669/* igb_read_i2c_byte - Reads 8 bit word over I2C
7670 * @hw: pointer to hardware structure
7671 * @byte_offset: byte offset to read
7672 * @dev_addr: device address
7673 * @data: value read
7674 *
7675 * Performs byte read operation over I2C interface at
7676 * a specified device address.
7677 */
7678s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7679 u8 dev_addr, u8 *data)
7680{
7681 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7682 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7683 s32 status;
7684 u16 swfw_mask = 0;
7685
7686 if (!this_client)
7687 return E1000_ERR_I2C;
7688
7689 swfw_mask = E1000_SWFW_PHY0_SM;
7690
7691 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7692 != E1000_SUCCESS)
7693 return E1000_ERR_SWFW_SYNC;
7694
7695 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7696 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7697
7698 if (status < 0)
7699 return E1000_ERR_I2C;
7700 else {
7701 *data = status;
7702 return E1000_SUCCESS;
7703 }
7704}
7705
7706/* igb_write_i2c_byte - Writes 8 bit word over I2C
7707 * @hw: pointer to hardware structure
7708 * @byte_offset: byte offset to write
7709 * @dev_addr: device address
7710 * @data: value to write
7711 *
7712 * Performs byte write operation over I2C interface at
7713 * a specified device address.
7714 */
7715s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7716 u8 dev_addr, u8 data)
7717{
7718 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7719 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7720 s32 status;
7721 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7722
7723 if (!this_client)
7724 return E1000_ERR_I2C;
7725
7726 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7727 return E1000_ERR_SWFW_SYNC;
7728 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7729 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7730
7731 if (status)
7732 return E1000_ERR_I2C;
7733 else
7734 return E1000_SUCCESS;
7735
7736}
9d5c8243 7737/* igb_main.c */
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