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igb: Add i2c interface to igb.
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
200e5fd5 63#define MAJ 4
6699938b
CW		 64#define MIN 1
65#define BUILD 2
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 72static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 73
9d5c8243
AK		 74static const struct e1000_info *igb_info_tbl[] = {
75 [board_82575] = &e1000_82575_info,
76};
77
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
109 /* required last entry */
110 {0, }
111};
112
113MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
114
115void igb_reset(struct igb_adapter *);
116static int igb_setup_all_tx_resources(struct igb_adapter *);
117static int igb_setup_all_rx_resources(struct igb_adapter *);
118static void igb_free_all_tx_resources(struct igb_adapter *);
119static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 120static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 121static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 122static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 123static int igb_sw_init(struct igb_adapter *);
124static int igb_open(struct net_device *);
125static int igb_close(struct net_device *);
53c7d064 126static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 127static void igb_configure_tx(struct igb_adapter *);
128static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 129static void igb_clean_all_tx_rings(struct igb_adapter *);
130static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 131static void igb_clean_tx_ring(struct igb_ring *);
132static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 133static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 134static void igb_update_phy_info(unsigned long);
135static void igb_watchdog(unsigned long);
136static void igb_watchdog_task(struct work_struct *);
cd392f5c 137static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 138static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
139 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 140static int igb_change_mtu(struct net_device *, int);
141static int igb_set_mac(struct net_device *, void *);
68d480c4 142static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 143static irqreturn_t igb_intr(int irq, void *);
144static irqreturn_t igb_intr_msi(int irq, void *);
145static irqreturn_t igb_msix_other(int irq, void *);
047e0030 146static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 147#ifdef CONFIG_IGB_DCA
047e0030 148static void igb_update_dca(struct igb_q_vector *);
fe4506b6 149static void igb_setup_dca(struct igb_adapter *);
421e02f0 150#endif /* CONFIG_IGB_DCA */
661086df 151static int igb_poll(struct napi_struct *, int);
13fde97a 152static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 153static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 154static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
155static void igb_tx_timeout(struct net_device *);
156static void igb_reset_task(struct work_struct *);
c8f44aff 157static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 158static int igb_vlan_rx_add_vid(struct net_device *, u16);
159static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 160static void igb_restore_vlan(struct igb_adapter *);
26ad9178 161static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 162static void igb_ping_all_vfs(struct igb_adapter *);
163static void igb_msg_task(struct igb_adapter *);
4ae196df 164static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 165static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 166static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 167static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
168static int igb_ndo_set_vf_vlan(struct net_device *netdev,
169 int vf, u16 vlan, u8 qos);
170static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
171static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
172 struct ifla_vf_info *ivi);
17dc566c 173static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 174
175#ifdef CONFIG_PCI_IOV
0224d663 176static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 177static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 178#endif
9d5c8243 179
9d5c8243 180#ifdef CONFIG_PM
d9dd966d 181#ifdef CONFIG_PM_SLEEP
749ab2cd 182static int igb_suspend(struct device *);
d9dd966d 183#endif
749ab2cd
YZ		 184static int igb_resume(struct device *);
185#ifdef CONFIG_PM_RUNTIME
186static int igb_runtime_suspend(struct device *dev);
187static int igb_runtime_resume(struct device *dev);
188static int igb_runtime_idle(struct device *dev);
189#endif
190static const struct dev_pm_ops igb_pm_ops = {
191 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
192 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
193 igb_runtime_idle)
194};
9d5c8243
AK		 195#endif
196static void igb_shutdown(struct pci_dev *);
fa44f2f1 197static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 198#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 199static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
200static struct notifier_block dca_notifier = {
201 .notifier_call = igb_notify_dca,
202 .next = NULL,
203 .priority = 0
204};
205#endif
9d5c8243
AK		 206#ifdef CONFIG_NET_POLL_CONTROLLER
207/* for netdump / net console */
208static void igb_netpoll(struct net_device *);
209#endif
37680117 210#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 211static unsigned int max_vfs = 0;
212module_param(max_vfs, uint, 0);
213MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
214 "per physical function");
215#endif /* CONFIG_PCI_IOV */
216
9d5c8243
AK		 217static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
218 pci_channel_state_t);
219static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
220static void igb_io_resume(struct pci_dev *);
221
3646f0e5 222static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 223 .error_detected = igb_io_error_detected,
224 .slot_reset = igb_io_slot_reset,
225 .resume = igb_io_resume,
226};
227
b6e0c419 228static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 229
230static struct pci_driver igb_driver = {
231 .name = igb_driver_name,
232 .id_table = igb_pci_tbl,
233 .probe = igb_probe,
9f9a12f8 234 .remove = igb_remove,
9d5c8243 235#ifdef CONFIG_PM
749ab2cd 236 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 237#endif
238 .shutdown = igb_shutdown,
fa44f2f1 239 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 240 .err_handler = &igb_err_handler
241};
242
243MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
244MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
245MODULE_LICENSE("GPL");
246MODULE_VERSION(DRV_VERSION);
247
b3f4d599 248#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
249static int debug = -1;
250module_param(debug, int, 0);
251MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
252
c97ec42a
TI		 253struct igb_reg_info {
254 u32 ofs;
255 char *name;
256};
257
258static const struct igb_reg_info igb_reg_info_tbl[] = {
259
260 /* General Registers */
261 {E1000_CTRL, "CTRL"},
262 {E1000_STATUS, "STATUS"},
263 {E1000_CTRL_EXT, "CTRL_EXT"},
264
265 /* Interrupt Registers */
266 {E1000_ICR, "ICR"},
267
268 /* RX Registers */
269 {E1000_RCTL, "RCTL"},
270 {E1000_RDLEN(0), "RDLEN"},
271 {E1000_RDH(0), "RDH"},
272 {E1000_RDT(0), "RDT"},
273 {E1000_RXDCTL(0), "RXDCTL"},
274 {E1000_RDBAL(0), "RDBAL"},
275 {E1000_RDBAH(0), "RDBAH"},
276
277 /* TX Registers */
278 {E1000_TCTL, "TCTL"},
279 {E1000_TDBAL(0), "TDBAL"},
280 {E1000_TDBAH(0), "TDBAH"},
281 {E1000_TDLEN(0), "TDLEN"},
282 {E1000_TDH(0), "TDH"},
283 {E1000_TDT(0), "TDT"},
284 {E1000_TXDCTL(0), "TXDCTL"},
285 {E1000_TDFH, "TDFH"},
286 {E1000_TDFT, "TDFT"},
287 {E1000_TDFHS, "TDFHS"},
288 {E1000_TDFPC, "TDFPC"},
289
290 /* List Terminator */
291 {}
292};
293
294/*
295 * igb_regdump - register printout routine
296 */
297static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
298{
299 int n = 0;
300 char rname[16];
301 u32 regs[8];
302
303 switch (reginfo->ofs) {
304 case E1000_RDLEN(0):
305 for (n = 0; n < 4; n++)
306 regs[n] = rd32(E1000_RDLEN(n));
307 break;
308 case E1000_RDH(0):
309 for (n = 0; n < 4; n++)
310 regs[n] = rd32(E1000_RDH(n));
311 break;
312 case E1000_RDT(0):
313 for (n = 0; n < 4; n++)
314 regs[n] = rd32(E1000_RDT(n));
315 break;
316 case E1000_RXDCTL(0):
317 for (n = 0; n < 4; n++)
318 regs[n] = rd32(E1000_RXDCTL(n));
319 break;
320 case E1000_RDBAL(0):
321 for (n = 0; n < 4; n++)
322 regs[n] = rd32(E1000_RDBAL(n));
323 break;
324 case E1000_RDBAH(0):
325 for (n = 0; n < 4; n++)
326 regs[n] = rd32(E1000_RDBAH(n));
327 break;
328 case E1000_TDBAL(0):
329 for (n = 0; n < 4; n++)
330 regs[n] = rd32(E1000_RDBAL(n));
331 break;
332 case E1000_TDBAH(0):
333 for (n = 0; n < 4; n++)
334 regs[n] = rd32(E1000_TDBAH(n));
335 break;
336 case E1000_TDLEN(0):
337 for (n = 0; n < 4; n++)
338 regs[n] = rd32(E1000_TDLEN(n));
339 break;
340 case E1000_TDH(0):
341 for (n = 0; n < 4; n++)
342 regs[n] = rd32(E1000_TDH(n));
343 break;
344 case E1000_TDT(0):
345 for (n = 0; n < 4; n++)
346 regs[n] = rd32(E1000_TDT(n));
347 break;
348 case E1000_TXDCTL(0):
349 for (n = 0; n < 4; n++)
350 regs[n] = rd32(E1000_TXDCTL(n));
351 break;
352 default:
876d2d6f 353 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 354 return;
355 }
356
357 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 358 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
359 regs[2], regs[3]);
c97ec42a
TI		 360}
361
362/*
363 * igb_dump - Print registers, tx-rings and rx-rings
364 */
365static void igb_dump(struct igb_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 struct e1000_hw *hw = &adapter->hw;
369 struct igb_reg_info *reginfo;
c97ec42a
TI		 370 struct igb_ring *tx_ring;
371 union e1000_adv_tx_desc *tx_desc;
372 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 373 struct igb_ring *rx_ring;
374 union e1000_adv_rx_desc *rx_desc;
375 u32 staterr;
6ad4edfc 376 u16 i, n;
c97ec42a
TI		 377
378 if (!netif_msg_hw(adapter))
379 return;
380
381 /* Print netdevice Info */
382 if (netdev) {
383 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 384 pr_info("Device Name state trans_start "
385 "last_rx\n");
386 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
387 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 388 }
389
390 /* Print Registers */
391 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 392 pr_info(" Register Name Value\n");
c97ec42a
TI		 393 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
394 reginfo->name; reginfo++) {
395 igb_regdump(hw, reginfo);
396 }
397
398 /* Print TX Ring Summary */
399 if (!netdev || !netif_running(netdev))
400 goto exit;
401
402 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 403 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 404 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 405 struct igb_tx_buffer *buffer_info;
c97ec42a 406 tx_ring = adapter->tx_ring[n];
06034649 407 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 408 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
409 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 410 (u64)dma_unmap_addr(buffer_info, dma),
411 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 412 buffer_info->next_to_watch,
413 (u64)buffer_info->time_stamp);
c97ec42a
TI		 414 }
415
416 /* Print TX Rings */
417 if (!netif_msg_tx_done(adapter))
418 goto rx_ring_summary;
419
420 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
421
422 /* Transmit Descriptor Formats
423 *
424 * Advanced Transmit Descriptor
425 * +--------------------------------------------------------------+
426 * 0 | Buffer Address [63:0] |
427 * +--------------------------------------------------------------+
428 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
429 * +--------------------------------------------------------------+
430 * 63 46 45 40 39 38 36 35 32 31 24 15 0
431 */
432
433 for (n = 0; n < adapter->num_tx_queues; n++) {
434 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 435 pr_info("------------------------------------\n");
436 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
437 pr_info("------------------------------------\n");
438 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
439 "[bi->dma ] leng ntw timestamp "
440 "bi->skb\n");
c97ec42a
TI		 441
442 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 443 const char *next_desc;
06034649 444 struct igb_tx_buffer *buffer_info;
60136906 445 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 446 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 447 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 448 if (i == tx_ring->next_to_use &&
449 i == tx_ring->next_to_clean)
450 next_desc = " NTC/U";
451 else if (i == tx_ring->next_to_use)
452 next_desc = " NTU";
453 else if (i == tx_ring->next_to_clean)
454 next_desc = " NTC";
455 else
456 next_desc = "";
457
458 pr_info("T [0x%03X] %016llX %016llX %016llX"
459 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 460 le64_to_cpu(u0->a),
461 le64_to_cpu(u0->b),
c9f14bf3
AD		 462 (u64)dma_unmap_addr(buffer_info, dma),
463 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 464 buffer_info->next_to_watch,
465 (u64)buffer_info->time_stamp,
876d2d6f 466 buffer_info->skb, next_desc);
c97ec42a 467
b669588a 468 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS,
b669588a 471 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 472 dma_unmap_len(buffer_info, len),
473 true);
c97ec42a
TI		 474 }
475 }
476
477 /* Print RX Rings Summary */
478rx_ring_summary:
479 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 480 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 481 for (n = 0; n < adapter->num_rx_queues; n++) {
482 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 483 pr_info(" %5d %5X %5X\n",
484 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 485 }
486
487 /* Print RX Rings */
488 if (!netif_msg_rx_status(adapter))
489 goto exit;
490
491 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
492
493 /* Advanced Receive Descriptor (Read) Format
494 * 63 1 0
495 * +-----------------------------------------------------+
496 * 0 | Packet Buffer Address [63:1] |A0/NSE|
497 * +----------------------------------------------+------+
498 * 8 | Header Buffer Address [63:1] | DD |
499 * +-----------------------------------------------------+
500 *
501 *
502 * Advanced Receive Descriptor (Write-Back) Format
503 *
504 * 63 48 47 32 31 30 21 20 17 16 4 3 0
505 * +------------------------------------------------------+
506 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
507 * | Checksum Ident | | | | Type | Type |
508 * +------------------------------------------------------+
509 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
510 * +------------------------------------------------------+
511 * 63 48 47 32 31 20 19 0
512 */
513
514 for (n = 0; n < adapter->num_rx_queues; n++) {
515 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 516 pr_info("------------------------------------\n");
517 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
518 pr_info("------------------------------------\n");
519 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
520 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
521 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
522 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 523
524 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 525 const char *next_desc;
06034649
AD		 526 struct igb_rx_buffer *buffer_info;
527 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 528 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 529 u0 = (struct my_u0 *)rx_desc;
530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 531
532 if (i == rx_ring->next_to_use)
533 next_desc = " NTU";
534 else if (i == rx_ring->next_to_clean)
535 next_desc = " NTC";
536 else
537 next_desc = "";
538
c97ec42a
TI		 539 if (staterr & E1000_RXD_STAT_DD) {
540 /* Descriptor Done */
1a1c225b
AD		 541 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
542 "RWB", i,
c97ec42a
TI		 543 le64_to_cpu(u0->a),
544 le64_to_cpu(u0->b),
1a1c225b 545 next_desc);
c97ec42a 546 } else {
1a1c225b
AD		 547 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
548 "R ", i,
c97ec42a
TI		 549 le64_to_cpu(u0->a),
550 le64_to_cpu(u0->b),
551 (u64)buffer_info->dma,
1a1c225b 552 next_desc);
c97ec42a 553
b669588a 554 if (netif_msg_pktdata(adapter) &&
1a1c225b 555 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 556 print_hex_dump(KERN_INFO, "",
557 DUMP_PREFIX_ADDRESS,
558 16, 1,
b669588a
ET		 559 page_address(buffer_info->page) +
560 buffer_info->page_offset,
de78d1f9 561 IGB_RX_BUFSZ, true);
c97ec42a
TI		 562 }
563 }
c97ec42a
TI		 564 }
565 }
566
567exit:
568 return;
569}
570
441fc6fd
CW		 571/* igb_get_i2c_data - Reads the I2C SDA data bit
572 * @hw: pointer to hardware structure
573 * @i2cctl: Current value of I2CCTL register
574 *
575 * Returns the I2C data bit value
576 */
577static int igb_get_i2c_data(void *data)
578{
579 struct igb_adapter *adapter = (struct igb_adapter *)data;
580 struct e1000_hw *hw = &adapter->hw;
581 s32 i2cctl = rd32(E1000_I2CPARAMS);
582
583 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
584}
585
586/* igb_set_i2c_data - Sets the I2C data bit
587 * @data: pointer to hardware structure
588 * @state: I2C data value (0 or 1) to set
589 *
590 * Sets the I2C data bit
591 */
592static void igb_set_i2c_data(void *data, int state)
593{
594 struct igb_adapter *adapter = (struct igb_adapter *)data;
595 struct e1000_hw *hw = &adapter->hw;
596 s32 i2cctl = rd32(E1000_I2CPARAMS);
597
598 if (state)
599 i2cctl |= E1000_I2C_DATA_OUT;
600 else
601 i2cctl &= ~E1000_I2C_DATA_OUT;
602
603 i2cctl &= ~E1000_I2C_DATA_OE_N;
604 i2cctl |= E1000_I2C_CLK_OE_N;
605 wr32(E1000_I2CPARAMS, i2cctl);
606 wrfl();
607
608}
609
610/* igb_set_i2c_clk - Sets the I2C SCL clock
611 * @data: pointer to hardware structure
612 * @state: state to set clock
613 *
614 * Sets the I2C clock line to state
615 */
616static void igb_set_i2c_clk(void *data, int state)
617{
618 struct igb_adapter *adapter = (struct igb_adapter *)data;
619 struct e1000_hw *hw = &adapter->hw;
620 s32 i2cctl = rd32(E1000_I2CPARAMS);
621
622 if (state) {
623 i2cctl |= E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 } else {
626 i2cctl &= ~E1000_I2C_CLK_OUT;
627 i2cctl &= ~E1000_I2C_CLK_OE_N;
628 }
629 wr32(E1000_I2CPARAMS, i2cctl);
630 wrfl();
631}
632
633/* igb_get_i2c_clk - Gets the I2C SCL clock state
634 * @data: pointer to hardware structure
635 *
636 * Gets the I2C clock state
637 */
638static int igb_get_i2c_clk(void *data)
639{
640 struct igb_adapter *adapter = (struct igb_adapter *)data;
641 struct e1000_hw *hw = &adapter->hw;
642 s32 i2cctl = rd32(E1000_I2CPARAMS);
643
644 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
645}
646
647static const struct i2c_algo_bit_data igb_i2c_algo = {
648 .setsda = igb_set_i2c_data,
649 .setscl = igb_set_i2c_clk,
650 .getsda = igb_get_i2c_data,
651 .getscl = igb_get_i2c_clk,
652 .udelay = 5,
653 .timeout = 20,
654};
655
9d5c8243 656/**
c041076a 657 * igb_get_hw_dev - return device
9d5c8243
AK		 658 * used by hardware layer to print debugging information
659 **/
c041076a 660struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 661{
662 struct igb_adapter *adapter = hw->back;
c041076a 663 return adapter->netdev;
9d5c8243 664}
38c845c7 665
9d5c8243
AK		 666/**
667 * igb_init_module - Driver Registration Routine
668 *
669 * igb_init_module is the first routine called when the driver is
670 * loaded. All it does is register with the PCI subsystem.
671 **/
672static int __init igb_init_module(void)
673{
674 int ret;
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243
AK		 676 igb_driver_string, igb_driver_version);
677
876d2d6f 678 pr_info("%s\n", igb_copyright);
9d5c8243 679
421e02f0 680#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 681 dca_register_notify(&dca_notifier);
682#endif
bbd98fe4 683 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 684 return ret;
685}
686
687module_init(igb_init_module);
688
689/**
690 * igb_exit_module - Driver Exit Cleanup Routine
691 *
692 * igb_exit_module is called just before the driver is removed
693 * from memory.
694 **/
695static void __exit igb_exit_module(void)
696{
421e02f0 697#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 698 dca_unregister_notify(&dca_notifier);
699#endif
9d5c8243
AK		 700 pci_unregister_driver(&igb_driver);
701}
702
703module_exit(igb_exit_module);
704
26bc19ec
AD		 705#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706/**
707 * igb_cache_ring_register - Descriptor ring to register mapping
708 * @adapter: board private structure to initialize
709 *
710 * Once we know the feature-set enabled for the device, we'll cache
711 * the register offset the descriptor ring is assigned to.
712 **/
713static void igb_cache_ring_register(struct igb_adapter *adapter)
714{
ee1b9f06 715 int i = 0, j = 0;
047e0030 716 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 717
718 switch (adapter->hw.mac.type) {
719 case e1000_82576:
720 /* The queues are allocated for virtualization such that VF 0
721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
722 * In order to avoid collision we start at the first free queue
723 * and continue consuming queues in the same sequence
724 */
ee1b9f06 725 if (adapter->vfs_allocated_count) {
a99955fc 726 for (; i < adapter->rss_queues; i++)
3025a446
AD		 727 adapter->rx_ring[i]->reg_idx = rbase_offset +
728 Q_IDX_82576(i);
ee1b9f06 729 }
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
f96a8a0b
CW		 733 case e1000_i210:
734 case e1000_i211:
26bc19ec 735 default:
ee1b9f06 736 for (; i < adapter->num_rx_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 738 for (; j < adapter->num_tx_queues; j++)
3025a446 739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 740 break;
741 }
742}
743
4be000c8
AD		 744/**
745 * igb_write_ivar - configure ivar for given MSI-X vector
746 * @hw: pointer to the HW structure
747 * @msix_vector: vector number we are allocating to a given ring
748 * @index: row index of IVAR register to write within IVAR table
749 * @offset: column offset of in IVAR, should be multiple of 8
750 *
751 * This function is intended to handle the writing of the IVAR register
752 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
753 * each containing an cause allocation for an Rx and Tx ring, and a
754 * variable number of rows depending on the number of queues supported.
755 **/
756static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
757 int index, int offset)
758{
759 u32 ivar = array_rd32(E1000_IVAR0, index);
760
761 /* clear any bits that are currently set */
762 ivar &= ~((u32)0xFF << offset);
763
764 /* write vector and valid bit */
765 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
766
767 array_wr32(E1000_IVAR0, index, ivar);
768}
769
9d5c8243 770#define IGB_N0_QUEUE -1
047e0030 771static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 772{
047e0030 773 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 774 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 775 int rx_queue = IGB_N0_QUEUE;
776 int tx_queue = IGB_N0_QUEUE;
4be000c8 777 u32 msixbm = 0;
047e0030 778
0ba82994
AD		 779 if (q_vector->rx.ring)
780 rx_queue = q_vector->rx.ring->reg_idx;
781 if (q_vector->tx.ring)
782 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 783
784 switch (hw->mac.type) {
785 case e1000_82575:
9d5c8243
AK		 786 /* The 82575 assigns vectors using a bitmask, which matches the
787 bitmask for the EICR/EIMS/EIMC registers. To assign one
788 or more queues to a vector, we write the appropriate bits
789 into the MSIXBM register for that vector. */
047e0030 790 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 791 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 792 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 793 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 794 if (!adapter->msix_entries && msix_vector == 0)
795 msixbm |= E1000_EIMS_OTHER;
9d5c8243 796 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 797 q_vector->eims_value = msixbm;
2d064c06
AD		 798 break;
799 case e1000_82576:
4be000c8
AD		 800 /*
801 * 82576 uses a table that essentially consists of 2 columns
802 * with 8 rows. The ordering is column-major so we use the
803 * lower 3 bits as the row index, and the 4th bit as the
804 * column offset.
805 */
806 if (rx_queue > IGB_N0_QUEUE)
807 igb_write_ivar(hw, msix_vector,
808 rx_queue & 0x7,
809 (rx_queue & 0x8) << 1);
810 if (tx_queue > IGB_N0_QUEUE)
811 igb_write_ivar(hw, msix_vector,
812 tx_queue & 0x7,
813 ((tx_queue & 0x8) << 1) + 8);
047e0030 814 q_vector->eims_value = 1 << msix_vector;
2d064c06 815 break;
55cac248 816 case e1000_82580:
d2ba2ed8 817 case e1000_i350:
f96a8a0b
CW		 818 case e1000_i210:
819 case e1000_i211:
4be000c8
AD		 820 /*
821 * On 82580 and newer adapters the scheme is similar to 82576
822 * however instead of ordering column-major we have things
823 * ordered row-major. So we traverse the table by using
824 * bit 0 as the column offset, and the remaining bits as the
825 * row index.
826 */
827 if (rx_queue > IGB_N0_QUEUE)
828 igb_write_ivar(hw, msix_vector,
829 rx_queue >> 1,
830 (rx_queue & 0x1) << 4);
831 if (tx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 tx_queue >> 1,
834 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 835 q_vector->eims_value = 1 << msix_vector;
836 break;
2d064c06
AD		 837 default:
838 BUG();
839 break;
840 }
26b39276
AD		 841
842 /* add q_vector eims value to global eims_enable_mask */
843 adapter->eims_enable_mask |= q_vector->eims_value;
844
845 /* configure q_vector to set itr on first interrupt */
846 q_vector->set_itr = 1;
9d5c8243
AK		 847}
848
849/**
850 * igb_configure_msix - Configure MSI-X hardware
851 *
852 * igb_configure_msix sets up the hardware to properly
853 * generate MSI-X interrupts.
854 **/
855static void igb_configure_msix(struct igb_adapter *adapter)
856{
857 u32 tmp;
858 int i, vector = 0;
859 struct e1000_hw *hw = &adapter->hw;
860
861 adapter->eims_enable_mask = 0;
9d5c8243
AK		 862
863 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 864 switch (hw->mac.type) {
865 case e1000_82575:
9d5c8243
AK		 866 tmp = rd32(E1000_CTRL_EXT);
867 /* enable MSI-X PBA support*/
868 tmp |= E1000_CTRL_EXT_PBA_CLR;
869
870 /* Auto-Mask interrupts upon ICR read. */
871 tmp |= E1000_CTRL_EXT_EIAME;
872 tmp |= E1000_CTRL_EXT_IRCA;
873
874 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 875
876 /* enable msix_other interrupt */
877 array_wr32(E1000_MSIXBM(0), vector++,
878 E1000_EIMS_OTHER);
844290e5 879 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 880
2d064c06
AD		 881 break;
882
883 case e1000_82576:
55cac248 884 case e1000_82580:
d2ba2ed8 885 case e1000_i350:
f96a8a0b
CW		 886 case e1000_i210:
887 case e1000_i211:
047e0030
AD		 888 /* Turn on MSI-X capability first, or our settings
889 * won't stick. And it will take days to debug. */
890 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
891 E1000_GPIE_PBA | E1000_GPIE_EIAME |
892 E1000_GPIE_NSICR);
893
894 /* enable msix_other interrupt */
895 adapter->eims_other = 1 << vector;
2d064c06 896 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 897
047e0030 898 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 899 break;
900 default:
901 /* do nothing, since nothing else supports MSI-X */
902 break;
903 } /* switch (hw->mac.type) */
047e0030
AD		 904
905 adapter->eims_enable_mask |= adapter->eims_other;
906
26b39276
AD		 907 for (i = 0; i < adapter->num_q_vectors; i++)
908 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 909
9d5c8243
AK		 910 wrfl();
911}
912
913/**
914 * igb_request_msix - Initialize MSI-X interrupts
915 *
916 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
917 * kernel.
918 **/
919static int igb_request_msix(struct igb_adapter *adapter)
920{
921 struct net_device *netdev = adapter->netdev;
047e0030 922 struct e1000_hw *hw = &adapter->hw;
52285b76 923 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 924
047e0030 925 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 926 igb_msix_other, 0, netdev->name, adapter);
047e0030 927 if (err)
52285b76 928 goto err_out;
047e0030
AD		 929
930 for (i = 0; i < adapter->num_q_vectors; i++) {
931 struct igb_q_vector *q_vector = adapter->q_vector[i];
932
52285b76
SA		 933 vector++;
934
047e0030
AD		 935 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
936
0ba82994 937 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 938 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 939 q_vector->rx.ring->queue_index);
940 else if (q_vector->tx.ring)
047e0030 941 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 942 q_vector->tx.ring->queue_index);
943 else if (q_vector->rx.ring)
047e0030 944 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 945 q_vector->rx.ring->queue_index);
9d5c8243 946 else
047e0030
AD		 947 sprintf(q_vector->name, "%s-unused", netdev->name);
948
9d5c8243 949 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 950 igb_msix_ring, 0, q_vector->name,
047e0030 951 q_vector);
9d5c8243 952 if (err)
52285b76 953 goto err_free;
9d5c8243
AK		 954 }
955
9d5c8243
AK		 956 igb_configure_msix(adapter);
957 return 0;
52285b76
SA		 958
959err_free:
960 /* free already assigned IRQs */
961 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
962
963 vector--;
964 for (i = 0; i < vector; i++) {
965 free_irq(adapter->msix_entries[free_vector++].vector,
966 adapter->q_vector[i]);
967 }
968err_out:
9d5c8243
AK		 969 return err;
970}
971
972static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
973{
974 if (adapter->msix_entries) {
975 pci_disable_msix(adapter->pdev);
976 kfree(adapter->msix_entries);
977 adapter->msix_entries = NULL;
047e0030 978 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 979 pci_disable_msi(adapter->pdev);
047e0030 980 }
9d5c8243
AK		 981}
982
5536d210
AD		 983/**
984 * igb_free_q_vector - Free memory allocated for specific interrupt vector
985 * @adapter: board private structure to initialize
986 * @v_idx: Index of vector to be freed
987 *
988 * This function frees the memory allocated to the q_vector. In addition if
989 * NAPI is enabled it will delete any references to the NAPI struct prior
990 * to freeing the q_vector.
991 **/
992static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
993{
994 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
995
996 if (q_vector->tx.ring)
997 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
998
999 if (q_vector->rx.ring)
1000 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1001
1002 adapter->q_vector[v_idx] = NULL;
1003 netif_napi_del(&q_vector->napi);
1004
1005 /*
1006 * ixgbe_get_stats64() might access the rings on this vector,
1007 * we must wait a grace period before freeing it.
1008 */
1009 kfree_rcu(q_vector, rcu);
1010}
1011
047e0030
AD		 1012/**
1013 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1014 * @adapter: board private structure to initialize
1015 *
1016 * This function frees the memory allocated to the q_vectors. In addition if
1017 * NAPI is enabled it will delete any references to the NAPI struct prior
1018 * to freeing the q_vector.
1019 **/
1020static void igb_free_q_vectors(struct igb_adapter *adapter)
1021{
5536d210
AD		 1022 int v_idx = adapter->num_q_vectors;
1023
1024 adapter->num_tx_queues = 0;
1025 adapter->num_rx_queues = 0;
047e0030 1026 adapter->num_q_vectors = 0;
5536d210
AD		 1027
1028 while (v_idx--)
1029 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1030}
1031
1032/**
1033 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1034 *
1035 * This function resets the device so that it has 0 rx queues, tx queues, and
1036 * MSI-X interrupts allocated.
1037 */
1038static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1039{
047e0030
AD		 1040 igb_free_q_vectors(adapter);
1041 igb_reset_interrupt_capability(adapter);
1042}
9d5c8243
AK		 1043
1044/**
1045 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1046 *
1047 * Attempt to configure interrupts using the best available
1048 * capabilities of the hardware and kernel.
1049 **/
53c7d064 1050static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1051{
1052 int err;
1053 int numvecs, i;
1054
53c7d064
SA		 1055 if (!msix)
1056 goto msi_only;
1057
83b7180d 1058 /* Number of supported queues. */
a99955fc 1059 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1060 if (adapter->vfs_allocated_count)
1061 adapter->num_tx_queues = 1;
1062 else
1063 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1064
047e0030
AD		 1065 /* start with one vector for every rx queue */
1066 numvecs = adapter->num_rx_queues;
1067
3ad2f3fb 1068 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1069 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1070 numvecs += adapter->num_tx_queues;
047e0030
AD		 1071
1072 /* store the number of vectors reserved for queues */
1073 adapter->num_q_vectors = numvecs;
1074
1075 /* add 1 vector for link status interrupts */
1076 numvecs++;
9d5c8243
AK		 1077 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1078 GFP_KERNEL);
f96a8a0b 1079
9d5c8243
AK		 1080 if (!adapter->msix_entries)
1081 goto msi_only;
1082
1083 for (i = 0; i < numvecs; i++)
1084 adapter->msix_entries[i].entry = i;
1085
1086 err = pci_enable_msix(adapter->pdev,
1087 adapter->msix_entries,
1088 numvecs);
1089 if (err == 0)
0c2cc02e 1090 return;
9d5c8243
AK		 1091
1092 igb_reset_interrupt_capability(adapter);
1093
1094 /* If we can't do MSI-X, try MSI */
1095msi_only:
2a3abf6d
AD		 1096#ifdef CONFIG_PCI_IOV
1097 /* disable SR-IOV for non MSI-X configurations */
1098 if (adapter->vf_data) {
1099 struct e1000_hw *hw = &adapter->hw;
1100 /* disable iov and allow time for transactions to clear */
1101 pci_disable_sriov(adapter->pdev);
1102 msleep(500);
1103
1104 kfree(adapter->vf_data);
1105 adapter->vf_data = NULL;
1106 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1107 wrfl();
2a3abf6d
AD		 1108 msleep(100);
1109 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1110 }
1111#endif
4fc82adf 1112 adapter->vfs_allocated_count = 0;
a99955fc 1113 adapter->rss_queues = 1;
4fc82adf 1114 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1115 adapter->num_rx_queues = 1;
661086df 1116 adapter->num_tx_queues = 1;
047e0030 1117 adapter->num_q_vectors = 1;
9d5c8243 1118 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1119 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1120}
1121
5536d210
AD		 1122static void igb_add_ring(struct igb_ring *ring,
1123 struct igb_ring_container *head)
1124{
1125 head->ring = ring;
1126 head->count++;
1127}
1128
047e0030 1129/**
5536d210 1130 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1131 * @adapter: board private structure to initialize
5536d210
AD		 1132 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1133 * @v_idx: index of vector in adapter struct
1134 * @txr_count: total number of Tx rings to allocate
1135 * @txr_idx: index of first Tx ring to allocate
1136 * @rxr_count: total number of Rx rings to allocate
1137 * @rxr_idx: index of first Rx ring to allocate
047e0030 1138 *
5536d210 1139 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1140 **/
5536d210
AD		 1141static int igb_alloc_q_vector(struct igb_adapter *adapter,
1142 int v_count, int v_idx,
1143 int txr_count, int txr_idx,
1144 int rxr_count, int rxr_idx)
047e0030
AD		 1145{
1146 struct igb_q_vector *q_vector;
5536d210
AD		 1147 struct igb_ring *ring;
1148 int ring_count, size;
047e0030 1149
5536d210
AD		 1150 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1151 if (txr_count > 1 || rxr_count > 1)
1152 return -ENOMEM;
1153
1154 ring_count = txr_count + rxr_count;
1155 size = sizeof(struct igb_q_vector) +
1156 (sizeof(struct igb_ring) * ring_count);
1157
1158 /* allocate q_vector and rings */
1159 q_vector = kzalloc(size, GFP_KERNEL);
1160 if (!q_vector)
1161 return -ENOMEM;
1162
1163 /* initialize NAPI */
1164 netif_napi_add(adapter->netdev, &q_vector->napi,
1165 igb_poll, 64);
1166
1167 /* tie q_vector and adapter together */
1168 adapter->q_vector[v_idx] = q_vector;
1169 q_vector->adapter = adapter;
1170
1171 /* initialize work limits */
1172 q_vector->tx.work_limit = adapter->tx_work_limit;
1173
1174 /* initialize ITR configuration */
1175 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1176 q_vector->itr_val = IGB_START_ITR;
1177
1178 /* initialize pointer to rings */
1179 ring = q_vector->ring;
1180
1181 if (txr_count) {
1182 /* assign generic ring traits */
1183 ring->dev = &adapter->pdev->dev;
1184 ring->netdev = adapter->netdev;
1185
1186 /* configure backlink on ring */
1187 ring->q_vector = q_vector;
1188
1189 /* update q_vector Tx values */
1190 igb_add_ring(ring, &q_vector->tx);
1191
1192 /* For 82575, context index must be unique per ring. */
1193 if (adapter->hw.mac.type == e1000_82575)
1194 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1195
1196 /* apply Tx specific ring traits */
1197 ring->count = adapter->tx_ring_count;
1198 ring->queue_index = txr_idx;
1199
1200 /* assign ring to adapter */
1201 adapter->tx_ring[txr_idx] = ring;
1202
1203 /* push pointer to next ring */
1204 ring++;
047e0030 1205 }
81c2fc22 1206
5536d210
AD		 1207 if (rxr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
047e0030 1211
5536d210
AD		 1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
047e0030 1214
5536d210
AD		 1215 /* update q_vector Rx values */
1216 igb_add_ring(ring, &q_vector->rx);
047e0030 1217
5536d210
AD		 1218 /* set flag indicating ring supports SCTP checksum offload */
1219 if (adapter->hw.mac.type >= e1000_82576)
1220 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1221
5536d210
AD		 1222 /*
1223 * On i350, i210, and i211, loopback VLAN packets
1224 * have the tag byte-swapped.
1225 * */
1226 if (adapter->hw.mac.type >= e1000_i350)
1227 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1228
5536d210
AD		 1229 /* apply Rx specific ring traits */
1230 ring->count = adapter->rx_ring_count;
1231 ring->queue_index = rxr_idx;
1232
1233 /* assign ring to adapter */
1234 adapter->rx_ring[rxr_idx] = ring;
1235 }
1236
1237 return 0;
047e0030
AD		 1238}
1239
5536d210 1240
047e0030 1241/**
5536d210
AD		 1242 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1243 * @adapter: board private structure to initialize
047e0030 1244 *
5536d210
AD		 1245 * We allocate one q_vector per queue interrupt. If allocation fails we
1246 * return -ENOMEM.
047e0030 1247 **/
5536d210 1248static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1249{
5536d210
AD		 1250 int q_vectors = adapter->num_q_vectors;
1251 int rxr_remaining = adapter->num_rx_queues;
1252 int txr_remaining = adapter->num_tx_queues;
1253 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1254 int err;
047e0030 1255
5536d210
AD		 1256 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1257 for (; rxr_remaining; v_idx++) {
1258 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1259 0, 0, 1, rxr_idx);
047e0030 1260
5536d210
AD		 1261 if (err)
1262 goto err_out;
1263
1264 /* update counts and index */
1265 rxr_remaining--;
1266 rxr_idx++;
047e0030 1267 }
047e0030 1268 }
5536d210
AD		 1269
1270 for (; v_idx < q_vectors; v_idx++) {
1271 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1272 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1273 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1274 tqpv, txr_idx, rqpv, rxr_idx);
1275
1276 if (err)
1277 goto err_out;
1278
1279 /* update counts and index */
1280 rxr_remaining -= rqpv;
1281 txr_remaining -= tqpv;
1282 rxr_idx++;
1283 txr_idx++;
1284 }
1285
047e0030 1286 return 0;
5536d210
AD		 1287
1288err_out:
1289 adapter->num_tx_queues = 0;
1290 adapter->num_rx_queues = 0;
1291 adapter->num_q_vectors = 0;
1292
1293 while (v_idx--)
1294 igb_free_q_vector(adapter, v_idx);
1295
1296 return -ENOMEM;
047e0030
AD		 1297}
1298
1299/**
1300 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1301 *
1302 * This function initializes the interrupts and allocates all of the queues.
1303 **/
53c7d064 1304static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1305{
1306 struct pci_dev *pdev = adapter->pdev;
1307 int err;
1308
53c7d064 1309 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1310
1311 err = igb_alloc_q_vectors(adapter);
1312 if (err) {
1313 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1314 goto err_alloc_q_vectors;
1315 }
1316
5536d210 1317 igb_cache_ring_register(adapter);
047e0030
AD		 1318
1319 return 0;
5536d210 1320
047e0030
AD		 1321err_alloc_q_vectors:
1322 igb_reset_interrupt_capability(adapter);
1323 return err;
1324}
1325
9d5c8243
AK		 1326/**
1327 * igb_request_irq - initialize interrupts
1328 *
1329 * Attempts to configure interrupts using the best available
1330 * capabilities of the hardware and kernel.
1331 **/
1332static int igb_request_irq(struct igb_adapter *adapter)
1333{
1334 struct net_device *netdev = adapter->netdev;
047e0030 1335 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1336 int err = 0;
1337
1338 if (adapter->msix_entries) {
1339 err = igb_request_msix(adapter);
844290e5 1340 if (!err)
9d5c8243 1341 goto request_done;
9d5c8243 1342 /* fall back to MSI */
5536d210
AD		 1343 igb_free_all_tx_resources(adapter);
1344 igb_free_all_rx_resources(adapter);
53c7d064 1345
047e0030 1346 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1347 err = igb_init_interrupt_scheme(adapter, false);
1348 if (err)
047e0030 1349 goto request_done;
53c7d064 1350
047e0030
AD		 1351 igb_setup_all_tx_resources(adapter);
1352 igb_setup_all_rx_resources(adapter);
53c7d064 1353 igb_configure(adapter);
9d5c8243 1354 }
844290e5 1355
c74d588e
AD		 1356 igb_assign_vector(adapter->q_vector[0], 0);
1357
7dfc16fa 1358 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1359 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1360 netdev->name, adapter);
9d5c8243
AK		 1361 if (!err)
1362 goto request_done;
047e0030 1363
9d5c8243
AK		 1364 /* fall back to legacy interrupts */
1365 igb_reset_interrupt_capability(adapter);
7dfc16fa 1366 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1367 }
1368
c74d588e 1369 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1370 netdev->name, adapter);
9d5c8243 1371
6cb5e577 1372 if (err)
c74d588e 1373 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1374 err);
9d5c8243
AK		 1375
1376request_done:
1377 return err;
1378}
1379
1380static void igb_free_irq(struct igb_adapter *adapter)
1381{
9d5c8243
AK		 1382 if (adapter->msix_entries) {
1383 int vector = 0, i;
1384
047e0030 1385 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1386
0d1ae7f4 1387 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1388 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1389 adapter->q_vector[i]);
047e0030
AD		 1390 } else {
1391 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1392 }
9d5c8243
AK		 1393}
1394
1395/**
1396 * igb_irq_disable - Mask off interrupt generation on the NIC
1397 * @adapter: board private structure
1398 **/
1399static void igb_irq_disable(struct igb_adapter *adapter)
1400{
1401 struct e1000_hw *hw = &adapter->hw;
1402
25568a53
AD		 1403 /*
1404 * we need to be careful when disabling interrupts. The VFs are also
1405 * mapped into these registers and so clearing the bits can cause
1406 * issues on the VF drivers so we only need to clear what we set
1407 */
9d5c8243 1408 if (adapter->msix_entries) {
2dfd1212
AD		 1409 u32 regval = rd32(E1000_EIAM);
1410 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1411 wr32(E1000_EIMC, adapter->eims_enable_mask);
1412 regval = rd32(E1000_EIAC);
1413 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1414 }
844290e5
PW		 1415
1416 wr32(E1000_IAM, 0);
9d5c8243
AK		 1417 wr32(E1000_IMC, ~0);
1418 wrfl();
81a61859
ET		 1419 if (adapter->msix_entries) {
1420 int i;
1421 for (i = 0; i < adapter->num_q_vectors; i++)
1422 synchronize_irq(adapter->msix_entries[i].vector);
1423 } else {
1424 synchronize_irq(adapter->pdev->irq);
1425 }
9d5c8243
AK		 1426}
1427
1428/**
1429 * igb_irq_enable - Enable default interrupt generation settings
1430 * @adapter: board private structure
1431 **/
1432static void igb_irq_enable(struct igb_adapter *adapter)
1433{
1434 struct e1000_hw *hw = &adapter->hw;
1435
1436 if (adapter->msix_entries) {
06218a8d 1437 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1438 u32 regval = rd32(E1000_EIAC);
1439 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAM);
1441 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1442 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1443 if (adapter->vfs_allocated_count) {
4ae196df 1444 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1445 ims |= E1000_IMS_VMMB;
1446 }
1447 wr32(E1000_IMS, ims);
844290e5 1448 } else {
55cac248
AD		 1449 wr32(E1000_IMS, IMS_ENABLE_MASK |
1450 E1000_IMS_DRSTA);
1451 wr32(E1000_IAM, IMS_ENABLE_MASK |
1452 E1000_IMS_DRSTA);
844290e5 1453 }
9d5c8243
AK		 1454}
1455
1456static void igb_update_mng_vlan(struct igb_adapter *adapter)
1457{
51466239 1458 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1459 u16 vid = adapter->hw.mng_cookie.vlan_id;
1460 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1461
1462 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1463 /* add VID to filter table */
1464 igb_vfta_set(hw, vid, true);
1465 adapter->mng_vlan_id = vid;
1466 } else {
1467 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1468 }
1469
1470 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1471 (vid != old_vid) &&
b2cb09b1 1472 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1473 /* remove VID from filter table */
1474 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1475 }
1476}
1477
1478/**
1479 * igb_release_hw_control - release control of the h/w to f/w
1480 * @adapter: address of board private structure
1481 *
1482 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1483 * For ASF and Pass Through versions of f/w this means that the
1484 * driver is no longer loaded.
1485 *
1486 **/
1487static void igb_release_hw_control(struct igb_adapter *adapter)
1488{
1489 struct e1000_hw *hw = &adapter->hw;
1490 u32 ctrl_ext;
1491
1492 /* Let firmware take over control of h/w */
1493 ctrl_ext = rd32(E1000_CTRL_EXT);
1494 wr32(E1000_CTRL_EXT,
1495 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1496}
1497
9d5c8243
AK		 1498/**
1499 * igb_get_hw_control - get control of the h/w from f/w
1500 * @adapter: address of board private structure
1501 *
1502 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1503 * For ASF and Pass Through versions of f/w this means that
1504 * the driver is loaded.
1505 *
1506 **/
1507static void igb_get_hw_control(struct igb_adapter *adapter)
1508{
1509 struct e1000_hw *hw = &adapter->hw;
1510 u32 ctrl_ext;
1511
1512 /* Let firmware know the driver has taken over */
1513 ctrl_ext = rd32(E1000_CTRL_EXT);
1514 wr32(E1000_CTRL_EXT,
1515 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1516}
1517
9d5c8243
AK		 1518/**
1519 * igb_configure - configure the hardware for RX and TX
1520 * @adapter: private board structure
1521 **/
1522static void igb_configure(struct igb_adapter *adapter)
1523{
1524 struct net_device *netdev = adapter->netdev;
1525 int i;
1526
1527 igb_get_hw_control(adapter);
ff41f8dc 1528 igb_set_rx_mode(netdev);
9d5c8243
AK		 1529
1530 igb_restore_vlan(adapter);
9d5c8243 1531
85b430b4 1532 igb_setup_tctl(adapter);
06cf2666 1533 igb_setup_mrqc(adapter);
9d5c8243 1534 igb_setup_rctl(adapter);
85b430b4
AD		 1535
1536 igb_configure_tx(adapter);
9d5c8243 1537 igb_configure_rx(adapter);
662d7205
AD		 1538
1539 igb_rx_fifo_flush_82575(&adapter->hw);
1540
c493ea45 1541 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1542 * at least 1 descriptor unused to make sure
1543 * next_to_use != next_to_clean */
1544 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1545 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1546 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1547 }
9d5c8243
AK		 1548}
1549
88a268c1
NN		 1550/**
1551 * igb_power_up_link - Power up the phy/serdes link
1552 * @adapter: address of board private structure
1553 **/
1554void igb_power_up_link(struct igb_adapter *adapter)
1555{
76886596
AA		 1556 igb_reset_phy(&adapter->hw);
1557
88a268c1
NN		 1558 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1559 igb_power_up_phy_copper(&adapter->hw);
1560 else
1561 igb_power_up_serdes_link_82575(&adapter->hw);
1562}
1563
1564/**
1565 * igb_power_down_link - Power down the phy/serdes link
1566 * @adapter: address of board private structure
1567 */
1568static void igb_power_down_link(struct igb_adapter *adapter)
1569{
1570 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1571 igb_power_down_phy_copper_82575(&adapter->hw);
1572 else
1573 igb_shutdown_serdes_link_82575(&adapter->hw);
1574}
9d5c8243
AK		 1575
1576/**
1577 * igb_up - Open the interface and prepare it to handle traffic
1578 * @adapter: board private structure
1579 **/
9d5c8243
AK		 1580int igb_up(struct igb_adapter *adapter)
1581{
1582 struct e1000_hw *hw = &adapter->hw;
1583 int i;
1584
1585 /* hardware has been reset, we need to reload some things */
1586 igb_configure(adapter);
1587
1588 clear_bit(__IGB_DOWN, &adapter->state);
1589
0d1ae7f4
AD		 1590 for (i = 0; i < adapter->num_q_vectors; i++)
1591 napi_enable(&(adapter->q_vector[i]->napi));
1592
844290e5 1593 if (adapter->msix_entries)
9d5c8243 1594 igb_configure_msix(adapter);
feeb2721
AD		 1595 else
1596 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1597
1598 /* Clear any pending interrupts. */
1599 rd32(E1000_ICR);
1600 igb_irq_enable(adapter);
1601
d4960307
AD		 1602 /* notify VFs that reset has been completed */
1603 if (adapter->vfs_allocated_count) {
1604 u32 reg_data = rd32(E1000_CTRL_EXT);
1605 reg_data |= E1000_CTRL_EXT_PFRSTD;
1606 wr32(E1000_CTRL_EXT, reg_data);
1607 }
1608
4cb9be7a
JB		 1609 netif_tx_start_all_queues(adapter->netdev);
1610
25568a53
AD		 1611 /* start the watchdog. */
1612 hw->mac.get_link_status = 1;
1613 schedule_work(&adapter->watchdog_task);
1614
9d5c8243
AK		 1615 return 0;
1616}
1617
1618void igb_down(struct igb_adapter *adapter)
1619{
9d5c8243 1620 struct net_device *netdev = adapter->netdev;
330a6d6a 1621 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1622 u32 tctl, rctl;
1623 int i;
1624
1625 /* signal that we're down so the interrupt handler does not
1626 * reschedule our watchdog timer */
1627 set_bit(__IGB_DOWN, &adapter->state);
1628
1629 /* disable receives in the hardware */
1630 rctl = rd32(E1000_RCTL);
1631 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1632 /* flush and sleep below */
1633
fd2ea0a7 1634 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1635
1636 /* disable transmits in the hardware */
1637 tctl = rd32(E1000_TCTL);
1638 tctl &= ~E1000_TCTL_EN;
1639 wr32(E1000_TCTL, tctl);
1640 /* flush both disables and wait for them to finish */
1641 wrfl();
1642 msleep(10);
1643
0d1ae7f4
AD		 1644 for (i = 0; i < adapter->num_q_vectors; i++)
1645 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1646
9d5c8243
AK		 1647 igb_irq_disable(adapter);
1648
1649 del_timer_sync(&adapter->watchdog_timer);
1650 del_timer_sync(&adapter->phy_info_timer);
1651
9d5c8243 1652 netif_carrier_off(netdev);
04fe6358
AD		 1653
1654 /* record the stats before reset*/
12dcd86b
ED		 1655 spin_lock(&adapter->stats64_lock);
1656 igb_update_stats(adapter, &adapter->stats64);
1657 spin_unlock(&adapter->stats64_lock);
04fe6358 1658
9d5c8243
AK		 1659 adapter->link_speed = 0;
1660 adapter->link_duplex = 0;
1661
3023682e
JK		 1662 if (!pci_channel_offline(adapter->pdev))
1663 igb_reset(adapter);
9d5c8243
AK		 1664 igb_clean_all_tx_rings(adapter);
1665 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1666#ifdef CONFIG_IGB_DCA
1667
1668 /* since we reset the hardware DCA settings were cleared */
1669 igb_setup_dca(adapter);
1670#endif
9d5c8243
AK		 1671}
1672
1673void igb_reinit_locked(struct igb_adapter *adapter)
1674{
1675 WARN_ON(in_interrupt());
1676 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1677 msleep(1);
1678 igb_down(adapter);
1679 igb_up(adapter);
1680 clear_bit(__IGB_RESETTING, &adapter->state);
1681}
1682
1683void igb_reset(struct igb_adapter *adapter)
1684{
090b1795 1685 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1686 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1687 struct e1000_mac_info *mac = &hw->mac;
1688 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1689 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1690
1691 /* Repartition Pba for greater than 9k mtu
1692 * To take effect CTRL.RST is required.
1693 */
fa4dfae0 1694 switch (mac->type) {
d2ba2ed8 1695 case e1000_i350:
55cac248
AD		 1696 case e1000_82580:
1697 pba = rd32(E1000_RXPBS);
1698 pba = igb_rxpbs_adjust_82580(pba);
1699 break;
fa4dfae0 1700 case e1000_82576:
d249be54
AD		 1701 pba = rd32(E1000_RXPBS);
1702 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1703 break;
1704 case e1000_82575:
f96a8a0b
CW		 1705 case e1000_i210:
1706 case e1000_i211:
fa4dfae0
AD		 1707 default:
1708 pba = E1000_PBA_34K;
1709 break;
2d064c06 1710 }
9d5c8243 1711
2d064c06
AD		 1712 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1713 (mac->type < e1000_82576)) {
9d5c8243
AK		 1714 /* adjust PBA for jumbo frames */
1715 wr32(E1000_PBA, pba);
1716
1717 /* To maintain wire speed transmits, the Tx FIFO should be
1718 * large enough to accommodate two full transmit packets,
1719 * rounded up to the next 1KB and expressed in KB. Likewise,
1720 * the Rx FIFO should be large enough to accommodate at least
1721 * one full receive packet and is similarly rounded up and
1722 * expressed in KB. */
1723 pba = rd32(E1000_PBA);
1724 /* upper 16 bits has Tx packet buffer allocation size in KB */
1725 tx_space = pba >> 16;
1726 /* lower 16 bits has Rx packet buffer allocation size in KB */
1727 pba &= 0xffff;
1728 /* the tx fifo also stores 16 bytes of information about the tx
1729 * but don't include ethernet FCS because hardware appends it */
1730 min_tx_space = (adapter->max_frame_size +
85e8d004 1731 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1732 ETH_FCS_LEN) * 2;
1733 min_tx_space = ALIGN(min_tx_space, 1024);
1734 min_tx_space >>= 10;
1735 /* software strips receive CRC, so leave room for it */
1736 min_rx_space = adapter->max_frame_size;
1737 min_rx_space = ALIGN(min_rx_space, 1024);
1738 min_rx_space >>= 10;
1739
1740 /* If current Tx allocation is less than the min Tx FIFO size,
1741 * and the min Tx FIFO size is less than the current Rx FIFO
1742 * allocation, take space away from current Rx allocation */
1743 if (tx_space < min_tx_space &&
1744 ((min_tx_space - tx_space) < pba)) {
1745 pba = pba - (min_tx_space - tx_space);
1746
1747 /* if short on rx space, rx wins and must trump tx
1748 * adjustment */
1749 if (pba < min_rx_space)
1750 pba = min_rx_space;
1751 }
2d064c06 1752 wr32(E1000_PBA, pba);
9d5c8243 1753 }
9d5c8243
AK		 1754
1755 /* flow control settings */
1756 /* The high water mark must be low enough to fit one full frame
1757 * (or the size used for early receive) above it in the Rx FIFO.
1758 * Set it to the lower of:
1759 * - 90% of the Rx FIFO size, or
1760 * - the full Rx FIFO size minus one full frame */
1761 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1762 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1763
d48507fe 1764 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1765 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1766 fc->pause_time = 0xFFFF;
1767 fc->send_xon = 1;
0cce119a 1768 fc->current_mode = fc->requested_mode;
9d5c8243 1769
4ae196df
AD		 1770 /* disable receive for all VFs and wait one second */
1771 if (adapter->vfs_allocated_count) {
1772 int i;
1773 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1774 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1775
1776 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1777 igb_ping_all_vfs(adapter);
4ae196df
AD		 1778
1779 /* disable transmits and receives */
1780 wr32(E1000_VFRE, 0);
1781 wr32(E1000_VFTE, 0);
1782 }
1783
9d5c8243 1784 /* Allow time for pending master requests to run */
330a6d6a 1785 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1786 wr32(E1000_WUC, 0);
1787
330a6d6a 1788 if (hw->mac.ops.init_hw(hw))
090b1795 1789 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1790
a27416bb
MV		 1791 /*
1792 * Flow control settings reset on hardware reset, so guarantee flow
1793 * control is off when forcing speed.
1794 */
1795 if (!hw->mac.autoneg)
1796 igb_force_mac_fc(hw);
1797
b6e0c419 1798 igb_init_dmac(adapter, pba);
88a268c1
NN		 1799 if (!netif_running(adapter->netdev))
1800 igb_power_down_link(adapter);
1801
9d5c8243
AK		 1802 igb_update_mng_vlan(adapter);
1803
1804 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1805 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1806
1f6e8178
MV		 1807 /* Re-enable PTP, where applicable. */
1808 igb_ptp_reset(adapter);
1f6e8178 1809
330a6d6a 1810 igb_get_phy_info(hw);
9d5c8243
AK		 1811}
1812
c8f44aff
MM		 1813static netdev_features_t igb_fix_features(struct net_device *netdev,
1814 netdev_features_t features)
b2cb09b1
JP		 1815{
1816 /*
1817 * Since there is no support for separate rx/tx vlan accel
1818 * enable/disable make sure tx flag is always in same state as rx.
1819 */
1820 if (features & NETIF_F_HW_VLAN_RX)
1821 features |= NETIF_F_HW_VLAN_TX;
1822 else
1823 features &= ~NETIF_F_HW_VLAN_TX;
1824
1825 return features;
1826}
1827
c8f44aff
MM		 1828static int igb_set_features(struct net_device *netdev,
1829 netdev_features_t features)
ac52caa3 1830{
c8f44aff 1831 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1832 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1833
b2cb09b1
JP		 1834 if (changed & NETIF_F_HW_VLAN_RX)
1835 igb_vlan_mode(netdev, features);
1836
89eaefb6
BG		 1837 if (!(changed & NETIF_F_RXALL))
1838 return 0;
1839
1840 netdev->features = features;
1841
1842 if (netif_running(netdev))
1843 igb_reinit_locked(adapter);
1844 else
1845 igb_reset(adapter);
1846
ac52caa3
MM		 1847 return 0;
1848}
1849
2e5c6922 1850static const struct net_device_ops igb_netdev_ops = {
559e9c49 1851 .ndo_open = igb_open,
2e5c6922 1852 .ndo_stop = igb_close,
cd392f5c 1853 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1854 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1855 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1856 .ndo_set_mac_address = igb_set_mac,
1857 .ndo_change_mtu = igb_change_mtu,
1858 .ndo_do_ioctl = igb_ioctl,
1859 .ndo_tx_timeout = igb_tx_timeout,
1860 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1861 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1862 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1863 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1864 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1865 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1866 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1867#ifdef CONFIG_NET_POLL_CONTROLLER
1868 .ndo_poll_controller = igb_netpoll,
1869#endif
b2cb09b1
JP		 1870 .ndo_fix_features = igb_fix_features,
1871 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1872};
1873
d67974f0
CW		 1874/**
1875 * igb_set_fw_version - Configure version string for ethtool
1876 * @adapter: adapter struct
1877 *
1878 **/
1879void igb_set_fw_version(struct igb_adapter *adapter)
1880{
1881 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1882 struct e1000_fw_version fw;
1883
1884 igb_get_fw_version(hw, &fw);
1885
1886 switch (hw->mac.type) {
1887 case e1000_i211:
d67974f0 1888 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1889 "%2d.%2d-%d",
1890 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1891 break;
1892
1893 default:
1894 /* if option is rom valid, display its version too */
1895 if (fw.or_valid) {
1896 snprintf(adapter->fw_version,
1897 sizeof(adapter->fw_version),
1898 "%d.%d, 0x%08x, %d.%d.%d",
1899 fw.eep_major, fw.eep_minor, fw.etrack_id,
1900 fw.or_major, fw.or_build, fw.or_patch);
1901 /* no option rom */
1902 } else {
1903 snprintf(adapter->fw_version,
1904 sizeof(adapter->fw_version),
1905 "%d.%d, 0x%08x",
1906 fw.eep_major, fw.eep_minor, fw.etrack_id);
1907 }
1908 break;
d67974f0 1909 }
d67974f0
CW		 1910 return;
1911}
1912
441fc6fd
CW		 1913static const struct i2c_board_info i350_sensor_info = {
1914 I2C_BOARD_INFO("i350bb", 0Xf8),
1915};
1916
1917/* igb_init_i2c - Init I2C interface
1918 * @adapter: pointer to adapter structure
1919 *
1920 */
1921static s32 igb_init_i2c(struct igb_adapter *adapter)
1922{
1923 s32 status = E1000_SUCCESS;
1924
1925 /* I2C interface supported on i350 devices */
1926 if (adapter->hw.mac.type != e1000_i350)
1927 return E1000_SUCCESS;
1928
1929 /* Initialize the i2c bus which is controlled by the registers.
1930 * This bus will use the i2c_algo_bit structue that implements
1931 * the protocol through toggling of the 4 bits in the register.
1932 */
1933 adapter->i2c_adap.owner = THIS_MODULE;
1934 adapter->i2c_algo = igb_i2c_algo;
1935 adapter->i2c_algo.data = adapter;
1936 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1937 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1938 strlcpy(adapter->i2c_adap.name, "igb BB",
1939 sizeof(adapter->i2c_adap.name));
1940 status = i2c_bit_add_bus(&adapter->i2c_adap);
1941 return status;
1942}
1943
9d5c8243
AK		 1944/**
1945 * igb_probe - Device Initialization Routine
1946 * @pdev: PCI device information struct
1947 * @ent: entry in igb_pci_tbl
1948 *
1949 * Returns 0 on success, negative on failure
1950 *
1951 * igb_probe initializes an adapter identified by a pci_dev structure.
1952 * The OS initialization, configuring of the adapter private structure,
1953 * and a hardware reset occur.
1954 **/
1dd06ae8 1955static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1956{
1957 struct net_device *netdev;
1958 struct igb_adapter *adapter;
1959 struct e1000_hw *hw;
4337e993 1960 u16 eeprom_data = 0;
9835fd73 1961 s32 ret_val;
4337e993 1962 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1963 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1964 unsigned long mmio_start, mmio_len;
2d6a5e95 1965 int err, pci_using_dac;
9835fd73 1966 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1967
bded64a7
AG		 1968 /* Catch broken hardware that put the wrong VF device ID in
1969 * the PCIe SR-IOV capability.
1970 */
1971 if (pdev->is_virtfn) {
1972 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1973 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1974 return -EINVAL;
1975 }
1976
aed5dec3 1977 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1978 if (err)
1979 return err;
1980
1981 pci_using_dac = 0;
59d71989 1982 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1983 if (!err) {
59d71989 1984 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1985 if (!err)
1986 pci_using_dac = 1;
1987 } else {
59d71989 1988 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1989 if (err) {
59d71989 1990 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1991 if (err) {
1992 dev_err(&pdev->dev, "No usable DMA "
1993 "configuration, aborting\n");
1994 goto err_dma;
1995 }
1996 }
1997 }
1998
aed5dec3
AD		 1999 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2000 IORESOURCE_MEM),
2001 igb_driver_name);
9d5c8243
AK		 2002 if (err)
2003 goto err_pci_reg;
2004
19d5afd4 2005 pci_enable_pcie_error_reporting(pdev);
40a914fa 2006
9d5c8243 2007 pci_set_master(pdev);
c682fc23 2008 pci_save_state(pdev);
9d5c8243
AK		 2009
2010 err = -ENOMEM;
1bfaf07b 2011 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2012 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2013 if (!netdev)
2014 goto err_alloc_etherdev;
2015
2016 SET_NETDEV_DEV(netdev, &pdev->dev);
2017
2018 pci_set_drvdata(pdev, netdev);
2019 adapter = netdev_priv(netdev);
2020 adapter->netdev = netdev;
2021 adapter->pdev = pdev;
2022 hw = &adapter->hw;
2023 hw->back = adapter;
b3f4d599 2024 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2025
2026 mmio_start = pci_resource_start(pdev, 0);
2027 mmio_len = pci_resource_len(pdev, 0);
2028
2029 err = -EIO;
28b0759c
AD		 2030 hw->hw_addr = ioremap(mmio_start, mmio_len);
2031 if (!hw->hw_addr)
9d5c8243
AK		 2032 goto err_ioremap;
2033
2e5c6922 2034 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2035 igb_set_ethtool_ops(netdev);
9d5c8243 2036 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2037
2038 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2039
2040 netdev->mem_start = mmio_start;
2041 netdev->mem_end = mmio_start + mmio_len;
2042
9d5c8243
AK		 2043 /* PCI config space info */
2044 hw->vendor_id = pdev->vendor;
2045 hw->device_id = pdev->device;
2046 hw->revision_id = pdev->revision;
2047 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2048 hw->subsystem_device_id = pdev->subsystem_device;
2049
9d5c8243
AK		 2050 /* Copy the default MAC, PHY and NVM function pointers */
2051 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2052 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2053 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2054 /* Initialize skew-specific constants */
2055 err = ei->get_invariants(hw);
2056 if (err)
450c87c8 2057 goto err_sw_init;
9d5c8243 2058
450c87c8 2059 /* setup the private structure */
9d5c8243
AK		 2060 err = igb_sw_init(adapter);
2061 if (err)
2062 goto err_sw_init;
2063
2064 igb_get_bus_info_pcie(hw);
2065
2066 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2067
2068 /* Copper options */
2069 if (hw->phy.media_type == e1000_media_type_copper) {
2070 hw->phy.mdix = AUTO_ALL_MODES;
2071 hw->phy.disable_polarity_correction = false;
2072 hw->phy.ms_type = e1000_ms_hw_default;
2073 }
2074
2075 if (igb_check_reset_block(hw))
2076 dev_info(&pdev->dev,
2077 "PHY reset is blocked due to SOL/IDER session.\n");
2078
077887c3
AD		 2079 /*
2080 * features is initialized to 0 in allocation, it might have bits
2081 * set by igb_sw_init so we should use an or instead of an
2082 * assignment.
2083 */
2084 netdev->features |= NETIF_F_SG |
2085 NETIF_F_IP_CSUM |
2086 NETIF_F_IPV6_CSUM |
2087 NETIF_F_TSO |
2088 NETIF_F_TSO6 |
2089 NETIF_F_RXHASH |
2090 NETIF_F_RXCSUM |
2091 NETIF_F_HW_VLAN_RX |
2092 NETIF_F_HW_VLAN_TX;
2093
2094 /* copy netdev features into list of user selectable features */
2095 netdev->hw_features |= netdev->features;
89eaefb6 2096 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2097
2098 /* set this bit last since it cannot be part of hw_features */
2099 netdev->features |= NETIF_F_HW_VLAN_FILTER;
2100
2101 netdev->vlan_features |= NETIF_F_TSO |
2102 NETIF_F_TSO6 |
2103 NETIF_F_IP_CSUM |
2104 NETIF_F_IPV6_CSUM |
2105 NETIF_F_SG;
48f29ffc 2106
6b8f0922
BG		 2107 netdev->priv_flags |= IFF_SUPP_NOFCS;
2108
7b872a55 2109 if (pci_using_dac) {
9d5c8243 2110 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2111 netdev->vlan_features |= NETIF_F_HIGHDMA;
2112 }
9d5c8243 2113
ac52caa3
MM		 2114 if (hw->mac.type >= e1000_82576) {
2115 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2116 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2117 }
b9473560 2118
01789349
JP		 2119 netdev->priv_flags |= IFF_UNICAST_FLT;
2120
330a6d6a 2121 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2122
2123 /* before reading the NVM, reset the controller to put the device in a
2124 * known good starting state */
2125 hw->mac.ops.reset_hw(hw);
2126
f96a8a0b
CW		 2127 /*
2128 * make sure the NVM is good , i211 parts have special NVM that
2129 * doesn't contain a checksum
2130 */
2131 if (hw->mac.type != e1000_i211) {
2132 if (hw->nvm.ops.validate(hw) < 0) {
2133 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2134 err = -EIO;
2135 goto err_eeprom;
2136 }
9d5c8243
AK		 2137 }
2138
2139 /* copy the MAC address out of the NVM */
2140 if (hw->mac.ops.read_mac_addr(hw))
2141 dev_err(&pdev->dev, "NVM Read Error\n");
2142
2143 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2144
aaeb6cdf 2145 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2146 dev_err(&pdev->dev, "Invalid MAC Address\n");
2147 err = -EIO;
2148 goto err_eeprom;
2149 }
2150
d67974f0
CW		 2151 /* get firmware version for ethtool -i */
2152 igb_set_fw_version(adapter);
2153
c061b18d 2154 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2155 (unsigned long) adapter);
c061b18d 2156 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2157 (unsigned long) adapter);
9d5c8243
AK		 2158
2159 INIT_WORK(&adapter->reset_task, igb_reset_task);
2160 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2161
450c87c8 2162 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2163 adapter->fc_autoneg = true;
2164 hw->mac.autoneg = true;
2165 hw->phy.autoneg_advertised = 0x2f;
2166
0cce119a
AD		 2167 hw->fc.requested_mode = e1000_fc_default;
2168 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2169
9d5c8243
AK		 2170 igb_validate_mdi_setting(hw);
2171
63d4a8f9 2172 /* By default, support wake on port A */
a2cf8b6c 2173 if (hw->bus.func == 0)
63d4a8f9
MV		 2174 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2175
2176 /* Check the NVM for wake support on non-port A ports */
2177 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2178 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2179 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2180 &eeprom_data);
a2cf8b6c
AD		 2181 else if (hw->bus.func == 1)
2182 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2183
63d4a8f9
MV		 2184 if (eeprom_data & IGB_EEPROM_APME)
2185 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2186
2187 /* now that we have the eeprom settings, apply the special cases where
2188 * the eeprom may be wrong or the board simply won't support wake on
2189 * lan on a particular port */
2190 switch (pdev->device) {
2191 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2192 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2193 break;
2194 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2195 case E1000_DEV_ID_82576_FIBER:
2196 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2197 /* Wake events only supported on port A for dual fiber
2198 * regardless of eeprom setting */
2199 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2200 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2201 break;
c8ea5ea9 2202 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2203 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2204 /* if quad port adapter, disable WoL on all but port A */
2205 if (global_quad_port_a != 0)
63d4a8f9 2206 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2207 else
2208 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2209 /* Reset for multiple quad port adapters */
2210 if (++global_quad_port_a == 4)
2211 global_quad_port_a = 0;
2212 break;
63d4a8f9
MV		 2213 default:
2214 /* If the device can't wake, don't set software support */
2215 if (!device_can_wakeup(&adapter->pdev->dev))
2216 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2217 }
2218
2219 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2220 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2221 adapter->wol |= E1000_WUFC_MAG;
2222
2223 /* Some vendors want WoL disabled by default, but still supported */
2224 if ((hw->mac.type == e1000_i350) &&
2225 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2226 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2227 adapter->wol = 0;
2228 }
2229
2230 device_set_wakeup_enable(&adapter->pdev->dev,
2231 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2232
2233 /* reset the hardware with the new settings */
2234 igb_reset(adapter);
2235
441fc6fd
CW		 2236 /* Init the I2C interface */
2237 err = igb_init_i2c(adapter);
2238 if (err) {
2239 dev_err(&pdev->dev, "failed to init i2c interface\n");
2240 goto err_eeprom;
2241 }
2242
9d5c8243
AK		 2243 /* let the f/w know that the h/w is now under the control of the
2244 * driver. */
2245 igb_get_hw_control(adapter);
2246
9d5c8243
AK		 2247 strcpy(netdev->name, "eth%d");
2248 err = register_netdev(netdev);
2249 if (err)
2250 goto err_register;
2251
b168dfc5
JB		 2252 /* carrier off reporting is important to ethtool even BEFORE open */
2253 netif_carrier_off(netdev);
2254
421e02f0 2255#ifdef CONFIG_IGB_DCA
bbd98fe4 2256 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2257 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2258 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2259 igb_setup_dca(adapter);
2260 }
fe4506b6 2261
38c845c7 2262#endif
3c89f6d0 2263
673b8b70 2264 /* do hw tstamp init after resetting */
7ebae817 2265 igb_ptp_init(adapter);
673b8b70 2266
9d5c8243
AK		 2267 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2268 /* print bus type/speed/width info */
7c510e4b 2269 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2270 netdev->name,
559e9c49 2271 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2272 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2273 "unknown"),
59c3de89
AD		 2274 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2275 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2276 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2277 "unknown"),
7c510e4b 2278 netdev->dev_addr);
9d5c8243 2279
9835fd73
CW		 2280 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2281 if (ret_val)
2282 strcpy(part_str, "Unknown");
2283 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2284 dev_info(&pdev->dev,
2285 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2286 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2287 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2288 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2289 switch (hw->mac.type) {
2290 case e1000_i350:
f96a8a0b
CW		 2291 case e1000_i210:
2292 case e1000_i211:
09b068d4
CW		 2293 igb_set_eee_i350(hw);
2294 break;
2295 default:
2296 break;
2297 }
749ab2cd
YZ		 2298
2299 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2300 return 0;
2301
2302err_register:
2303 igb_release_hw_control(adapter);
441fc6fd 2304 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2305err_eeprom:
2306 if (!igb_check_reset_block(hw))
f5f4cf08 2307 igb_reset_phy(hw);
9d5c8243
AK		 2308
2309 if (hw->flash_address)
2310 iounmap(hw->flash_address);
9d5c8243 2311err_sw_init:
047e0030 2312 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2313 iounmap(hw->hw_addr);
2314err_ioremap:
2315 free_netdev(netdev);
2316err_alloc_etherdev:
559e9c49
AD		 2317 pci_release_selected_regions(pdev,
2318 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2319err_pci_reg:
2320err_dma:
2321 pci_disable_device(pdev);
2322 return err;
2323}
2324
fa44f2f1
GR		 2325#ifdef CONFIG_PCI_IOV
2326static int igb_disable_sriov(struct pci_dev *pdev)
2327{
2328 struct net_device *netdev = pci_get_drvdata(pdev);
2329 struct igb_adapter *adapter = netdev_priv(netdev);
2330 struct e1000_hw *hw = &adapter->hw;
2331
2332 /* reclaim resources allocated to VFs */
2333 if (adapter->vf_data) {
2334 /* disable iov and allow time for transactions to clear */
2335 if (igb_vfs_are_assigned(adapter)) {
2336 dev_warn(&pdev->dev,
2337 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2338 return -EPERM;
2339 } else {
2340 pci_disable_sriov(pdev);
2341 msleep(500);
2342 }
2343
2344 kfree(adapter->vf_data);
2345 adapter->vf_data = NULL;
2346 adapter->vfs_allocated_count = 0;
2347 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2348 wrfl();
2349 msleep(100);
2350 dev_info(&pdev->dev, "IOV Disabled\n");
2351
2352 /* Re-enable DMA Coalescing flag since IOV is turned off */
2353 adapter->flags |= IGB_FLAG_DMAC;
2354 }
2355
2356 return 0;
2357}
2358
2359static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2360{
2361 struct net_device *netdev = pci_get_drvdata(pdev);
2362 struct igb_adapter *adapter = netdev_priv(netdev);
2363 int old_vfs = pci_num_vf(pdev);
2364 int err = 0;
2365 int i;
2366
2367 if (!num_vfs)
2368 goto out;
2369 else if (old_vfs && old_vfs == num_vfs)
2370 goto out;
2371 else if (old_vfs && old_vfs != num_vfs)
2372 err = igb_disable_sriov(pdev);
2373
2374 if (err)
2375 goto out;
2376
2377 if (num_vfs > 7) {
2378 err = -EPERM;
2379 goto out;
2380 }
2381
2382 adapter->vfs_allocated_count = num_vfs;
2383
2384 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2385 sizeof(struct vf_data_storage), GFP_KERNEL);
2386
2387 /* if allocation failed then we do not support SR-IOV */
2388 if (!adapter->vf_data) {
2389 adapter->vfs_allocated_count = 0;
2390 dev_err(&pdev->dev,
2391 "Unable to allocate memory for VF Data Storage\n");
2392 err = -ENOMEM;
2393 goto out;
2394 }
2395
2396 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2397 if (err)
2398 goto err_out;
2399
2400 dev_info(&pdev->dev, "%d VFs allocated\n",
2401 adapter->vfs_allocated_count);
2402 for (i = 0; i < adapter->vfs_allocated_count; i++)
2403 igb_vf_configure(adapter, i);
2404
2405 /* DMA Coalescing is not supported in IOV mode. */
2406 adapter->flags &= ~IGB_FLAG_DMAC;
2407 goto out;
2408
2409err_out:
2410 kfree(adapter->vf_data);
2411 adapter->vf_data = NULL;
2412 adapter->vfs_allocated_count = 0;
2413out:
2414 return err;
2415}
2416
2417#endif
441fc6fd
CW		 2418/*
2419 * igb_remove_i2c - Cleanup I2C interface
2420 * @adapter: pointer to adapter structure
2421 *
2422 */
2423static void igb_remove_i2c(struct igb_adapter *adapter)
2424{
2425
2426 /* free the adapter bus structure */
2427 i2c_del_adapter(&adapter->i2c_adap);
2428}
2429
9d5c8243
AK		 2430/**
2431 * igb_remove - Device Removal Routine
2432 * @pdev: PCI device information struct
2433 *
2434 * igb_remove is called by the PCI subsystem to alert the driver
2435 * that it should release a PCI device. The could be caused by a
2436 * Hot-Plug event, or because the driver is going to be removed from
2437 * memory.
2438 **/
9f9a12f8 2439static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2440{
2441 struct net_device *netdev = pci_get_drvdata(pdev);
2442 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2443 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2444
749ab2cd 2445 pm_runtime_get_noresume(&pdev->dev);
441fc6fd
CW		 2446 igb_remove_i2c(adapter);
2447
a79f4f88 2448 igb_ptp_stop(adapter);
749ab2cd 2449
760141a5
TH		 2450 /*
2451 * The watchdog timer may be rescheduled, so explicitly
2452 * disable watchdog from being rescheduled.
2453 */
9d5c8243
AK		 2454 set_bit(__IGB_DOWN, &adapter->state);
2455 del_timer_sync(&adapter->watchdog_timer);
2456 del_timer_sync(&adapter->phy_info_timer);
2457
760141a5
TH		 2458 cancel_work_sync(&adapter->reset_task);
2459 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2460
421e02f0 2461#ifdef CONFIG_IGB_DCA
7dfc16fa 2462 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2463 dev_info(&pdev->dev, "DCA disabled\n");
2464 dca_remove_requester(&pdev->dev);
7dfc16fa 2465 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2466 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2467 }
2468#endif
2469
9d5c8243
AK		 2470 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2471 * would have already happened in close and is redundant. */
2472 igb_release_hw_control(adapter);
2473
2474 unregister_netdev(netdev);
2475
047e0030 2476 igb_clear_interrupt_scheme(adapter);
9d5c8243 2477
37680117 2478#ifdef CONFIG_PCI_IOV
fa44f2f1 2479 igb_disable_sriov(pdev);
37680117 2480#endif
559e9c49 2481
28b0759c
AD		 2482 iounmap(hw->hw_addr);
2483 if (hw->flash_address)
2484 iounmap(hw->flash_address);
559e9c49
AD		 2485 pci_release_selected_regions(pdev,
2486 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2487
1128c756 2488 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2489 free_netdev(netdev);
2490
19d5afd4 2491 pci_disable_pcie_error_reporting(pdev);
40a914fa 2492
9d5c8243
AK		 2493 pci_disable_device(pdev);
2494}
2495
a6b623e0
AD		 2496/**
2497 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2498 * @adapter: board private structure to initialize
2499 *
2500 * This function initializes the vf specific data storage and then attempts to
2501 * allocate the VFs. The reason for ordering it this way is because it is much
2502 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2503 * the memory for the VFs.
2504 **/
9f9a12f8 2505static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2506{
2507#ifdef CONFIG_PCI_IOV
2508 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2509 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2510
f96a8a0b
CW		 2511 /* Virtualization features not supported on i210 family. */
2512 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2513 return;
2514
fa44f2f1
GR		 2515 igb_enable_sriov(pdev, max_vfs);
2516 pci_sriov_set_totalvfs(pdev, 7);
0224d663 2517
a6b623e0
AD		 2518#endif /* CONFIG_PCI_IOV */
2519}
2520
fa44f2f1 2521static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2522{
2523 struct e1000_hw *hw = &adapter->hw;
374a542d 2524 u32 max_rss_queues;
9d5c8243 2525
374a542d 2526 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2527 switch (hw->mac.type) {
374a542d
MV		 2528 case e1000_i211:
2529 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2530 break;
2531 case e1000_82575:
f96a8a0b 2532 case e1000_i210:
374a542d
MV		 2533 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2534 break;
2535 case e1000_i350:
2536 /* I350 cannot do RSS and SR-IOV at the same time */
2537 if (!!adapter->vfs_allocated_count) {
2538 max_rss_queues = 1;
2539 break;
2540 }
2541 /* fall through */
2542 case e1000_82576:
2543 if (!!adapter->vfs_allocated_count) {
2544 max_rss_queues = 2;
2545 break;
2546 }
2547 /* fall through */
2548 case e1000_82580:
2549 default:
2550 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2551 break;
374a542d
MV		 2552 }
2553
2554 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2555
2556 /* Determine if we need to pair queues. */
2557 switch (hw->mac.type) {
2558 case e1000_82575:
f96a8a0b 2559 case e1000_i211:
374a542d 2560 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2561 break;
374a542d
MV		 2562 case e1000_82576:
2563 /*
2564 * If VFs are going to be allocated with RSS queues then we
2565 * should pair the queues in order to conserve interrupts due
2566 * to limited supply.
2567 */
2568 if ((adapter->rss_queues > 1) &&
2569 (adapter->vfs_allocated_count > 6))
2570 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2571 /* fall through */
2572 case e1000_82580:
2573 case e1000_i350:
2574 case e1000_i210:
f96a8a0b 2575 default:
374a542d
MV		 2576 /*
2577 * If rss_queues > half of max_rss_queues, pair the queues in
2578 * order to conserve interrupts due to limited supply.
2579 */
2580 if (adapter->rss_queues > (max_rss_queues / 2))
2581 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2582 break;
2583 }
fa44f2f1
GR		 2584}
2585
2586/**
2587 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2588 * @adapter: board private structure to initialize
2589 *
2590 * igb_sw_init initializes the Adapter private data structure.
2591 * Fields are initialized based on PCI device information and
2592 * OS network device settings (MTU size).
2593 **/
2594static int igb_sw_init(struct igb_adapter *adapter)
2595{
2596 struct e1000_hw *hw = &adapter->hw;
2597 struct net_device *netdev = adapter->netdev;
2598 struct pci_dev *pdev = adapter->pdev;
2599
2600 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2601
2602 /* set default ring sizes */
2603 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2604 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2605
2606 /* set default ITR values */
2607 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2608 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2609
2610 /* set default work limits */
2611 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2612
2613 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2614 VLAN_HLEN;
2615 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2616
2617 spin_lock_init(&adapter->stats64_lock);
2618#ifdef CONFIG_PCI_IOV
2619 switch (hw->mac.type) {
2620 case e1000_82576:
2621 case e1000_i350:
2622 if (max_vfs > 7) {
2623 dev_warn(&pdev->dev,
2624 "Maximum of 7 VFs per PF, using max\n");
2625 adapter->vfs_allocated_count = 7;
2626 } else
2627 adapter->vfs_allocated_count = max_vfs;
2628 if (adapter->vfs_allocated_count)
2629 dev_warn(&pdev->dev,
2630 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2631 break;
2632 default:
2633 break;
2634 }
2635#endif /* CONFIG_PCI_IOV */
2636
2637 igb_init_queue_configuration(adapter);
a99955fc 2638
1128c756
CW		 2639 /* Setup and initialize a copy of the hw vlan table array */
2640 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2641 E1000_VLAN_FILTER_TBL_SIZE,
2642 GFP_ATOMIC);
2643
a6b623e0 2644 /* This call may decrease the number of queues */
53c7d064 2645 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2646 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2647 return -ENOMEM;
2648 }
2649
a6b623e0
AD		 2650 igb_probe_vfs(adapter);
2651
9d5c8243
AK		 2652 /* Explicitly disable IRQ since the NIC can be in any state. */
2653 igb_irq_disable(adapter);
2654
f96a8a0b 2655 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2656 adapter->flags &= ~IGB_FLAG_DMAC;
2657
9d5c8243
AK		 2658 set_bit(__IGB_DOWN, &adapter->state);
2659 return 0;
2660}
2661
2662/**
2663 * igb_open - Called when a network interface is made active
2664 * @netdev: network interface device structure
2665 *
2666 * Returns 0 on success, negative value on failure
2667 *
2668 * The open entry point is called when a network interface is made
2669 * active by the system (IFF_UP). At this point all resources needed
2670 * for transmit and receive operations are allocated, the interrupt
2671 * handler is registered with the OS, the watchdog timer is started,
2672 * and the stack is notified that the interface is ready.
2673 **/
749ab2cd 2674static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2675{
2676 struct igb_adapter *adapter = netdev_priv(netdev);
2677 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2678 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2679 int err;
2680 int i;
2681
2682 /* disallow open during test */
749ab2cd
YZ		 2683 if (test_bit(__IGB_TESTING, &adapter->state)) {
2684 WARN_ON(resuming);
9d5c8243 2685 return -EBUSY;
749ab2cd
YZ		 2686 }
2687
2688 if (!resuming)
2689 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2690
b168dfc5
JB		 2691 netif_carrier_off(netdev);
2692
9d5c8243
AK		 2693 /* allocate transmit descriptors */
2694 err = igb_setup_all_tx_resources(adapter);
2695 if (err)
2696 goto err_setup_tx;
2697
2698 /* allocate receive descriptors */
2699 err = igb_setup_all_rx_resources(adapter);
2700 if (err)
2701 goto err_setup_rx;
2702
88a268c1 2703 igb_power_up_link(adapter);
9d5c8243 2704
9d5c8243
AK		 2705 /* before we allocate an interrupt, we must be ready to handle it.
2706 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2707 * as soon as we call pci_request_irq, so we have to setup our
2708 * clean_rx handler before we do so. */
2709 igb_configure(adapter);
2710
2711 err = igb_request_irq(adapter);
2712 if (err)
2713 goto err_req_irq;
2714
0c2cc02e
AD		 2715 /* Notify the stack of the actual queue counts. */
2716 err = netif_set_real_num_tx_queues(adapter->netdev,
2717 adapter->num_tx_queues);
2718 if (err)
2719 goto err_set_queues;
2720
2721 err = netif_set_real_num_rx_queues(adapter->netdev,
2722 adapter->num_rx_queues);
2723 if (err)
2724 goto err_set_queues;
2725
9d5c8243
AK		 2726 /* From here on the code is the same as igb_up() */
2727 clear_bit(__IGB_DOWN, &adapter->state);
2728
0d1ae7f4
AD		 2729 for (i = 0; i < adapter->num_q_vectors; i++)
2730 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2731
2732 /* Clear any pending interrupts. */
2733 rd32(E1000_ICR);
844290e5
PW		 2734
2735 igb_irq_enable(adapter);
2736
d4960307
AD		 2737 /* notify VFs that reset has been completed */
2738 if (adapter->vfs_allocated_count) {
2739 u32 reg_data = rd32(E1000_CTRL_EXT);
2740 reg_data |= E1000_CTRL_EXT_PFRSTD;
2741 wr32(E1000_CTRL_EXT, reg_data);
2742 }
2743
d55b53ff
JK		 2744 netif_tx_start_all_queues(netdev);
2745
749ab2cd
YZ		 2746 if (!resuming)
2747 pm_runtime_put(&pdev->dev);
2748
25568a53
AD		 2749 /* start the watchdog. */
2750 hw->mac.get_link_status = 1;
2751 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2752
2753 return 0;
2754
0c2cc02e
AD		 2755err_set_queues:
2756 igb_free_irq(adapter);
9d5c8243
AK		 2757err_req_irq:
2758 igb_release_hw_control(adapter);
88a268c1 2759 igb_power_down_link(adapter);
9d5c8243
AK		 2760 igb_free_all_rx_resources(adapter);
2761err_setup_rx:
2762 igb_free_all_tx_resources(adapter);
2763err_setup_tx:
2764 igb_reset(adapter);
749ab2cd
YZ		 2765 if (!resuming)
2766 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2767
2768 return err;
2769}
2770
749ab2cd
YZ		 2771static int igb_open(struct net_device *netdev)
2772{
2773 return __igb_open(netdev, false);
2774}
2775
9d5c8243
AK		 2776/**
2777 * igb_close - Disables a network interface
2778 * @netdev: network interface device structure
2779 *
2780 * Returns 0, this is not allowed to fail
2781 *
2782 * The close entry point is called when an interface is de-activated
2783 * by the OS. The hardware is still under the driver's control, but
2784 * needs to be disabled. A global MAC reset is issued to stop the
2785 * hardware, and all transmit and receive resources are freed.
2786 **/
749ab2cd 2787static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2788{
2789 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2790 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2791
2792 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2793
749ab2cd
YZ		 2794 if (!suspending)
2795 pm_runtime_get_sync(&pdev->dev);
2796
2797 igb_down(adapter);
9d5c8243
AK		 2798 igb_free_irq(adapter);
2799
2800 igb_free_all_tx_resources(adapter);
2801 igb_free_all_rx_resources(adapter);
2802
749ab2cd
YZ		 2803 if (!suspending)
2804 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2805 return 0;
2806}
2807
749ab2cd
YZ		 2808static int igb_close(struct net_device *netdev)
2809{
2810 return __igb_close(netdev, false);
2811}
2812
9d5c8243
AK		 2813/**
2814 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2815 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2816 *
2817 * Return 0 on success, negative on failure
2818 **/
80785298 2819int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2820{
59d71989 2821 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2822 int size;
2823
06034649 2824 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2825
2826 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2827 if (!tx_ring->tx_buffer_info)
9d5c8243 2828 goto err;
9d5c8243
AK		 2829
2830 /* round up to nearest 4K */
85e8d004 2831 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2832 tx_ring->size = ALIGN(tx_ring->size, 4096);
2833
5536d210
AD		 2834 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2835 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2836 if (!tx_ring->desc)
2837 goto err;
2838
9d5c8243
AK		 2839 tx_ring->next_to_use = 0;
2840 tx_ring->next_to_clean = 0;
81c2fc22 2841
9d5c8243
AK		 2842 return 0;
2843
2844err:
06034649 2845 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2846 tx_ring->tx_buffer_info = NULL;
2847 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2848 return -ENOMEM;
2849}
2850
2851/**
2852 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2853 * (Descriptors) for all queues
2854 * @adapter: board private structure
2855 *
2856 * Return 0 on success, negative on failure
2857 **/
2858static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2859{
439705e1 2860 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2861 int i, err = 0;
2862
2863 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2864 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2865 if (err) {
439705e1 2866 dev_err(&pdev->dev,
9d5c8243
AK		 2867 "Allocation for Tx Queue %u failed\n", i);
2868 for (i--; i >= 0; i--)
3025a446 2869 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2870 break;
2871 }
2872 }
2873
2874 return err;
2875}
2876
2877/**
85b430b4
AD		 2878 * igb_setup_tctl - configure the transmit control registers
2879 * @adapter: Board private structure
9d5c8243 2880 **/
d7ee5b3a 2881void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2882{
9d5c8243
AK		 2883 struct e1000_hw *hw = &adapter->hw;
2884 u32 tctl;
9d5c8243 2885
85b430b4
AD		 2886 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2887 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2888
2889 /* Program the Transmit Control Register */
9d5c8243
AK		 2890 tctl = rd32(E1000_TCTL);
2891 tctl &= ~E1000_TCTL_CT;
2892 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2893 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2894
2895 igb_config_collision_dist(hw);
2896
9d5c8243
AK		 2897 /* Enable transmits */
2898 tctl |= E1000_TCTL_EN;
2899
2900 wr32(E1000_TCTL, tctl);
2901}
2902
85b430b4
AD		 2903/**
2904 * igb_configure_tx_ring - Configure transmit ring after Reset
2905 * @adapter: board private structure
2906 * @ring: tx ring to configure
2907 *
2908 * Configure a transmit ring after a reset.
2909 **/
d7ee5b3a
AD		 2910void igb_configure_tx_ring(struct igb_adapter *adapter,
2911 struct igb_ring *ring)
85b430b4
AD		 2912{
2913 struct e1000_hw *hw = &adapter->hw;
a74420e0 2914 u32 txdctl = 0;
85b430b4
AD		 2915 u64 tdba = ring->dma;
2916 int reg_idx = ring->reg_idx;
2917
2918 /* disable the queue */
a74420e0 2919 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2920 wrfl();
2921 mdelay(10);
2922
2923 wr32(E1000_TDLEN(reg_idx),
2924 ring->count * sizeof(union e1000_adv_tx_desc));
2925 wr32(E1000_TDBAL(reg_idx),
2926 tdba & 0x00000000ffffffffULL);
2927 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2928
fce99e34 2929 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2930 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2931 writel(0, ring->tail);
85b430b4
AD		 2932
2933 txdctl |= IGB_TX_PTHRESH;
2934 txdctl |= IGB_TX_HTHRESH << 8;
2935 txdctl |= IGB_TX_WTHRESH << 16;
2936
2937 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2938 wr32(E1000_TXDCTL(reg_idx), txdctl);
2939}
2940
2941/**
2942 * igb_configure_tx - Configure transmit Unit after Reset
2943 * @adapter: board private structure
2944 *
2945 * Configure the Tx unit of the MAC after a reset.
2946 **/
2947static void igb_configure_tx(struct igb_adapter *adapter)
2948{
2949 int i;
2950
2951 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2952 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2953}
2954
9d5c8243
AK		 2955/**
2956 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2957 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2958 *
2959 * Returns 0 on success, negative on failure
2960 **/
80785298 2961int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2962{
59d71989 2963 struct device *dev = rx_ring->dev;
f33005a6 2964 int size;
9d5c8243 2965
06034649 2966 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 2967
2968 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2969 if (!rx_ring->rx_buffer_info)
9d5c8243 2970 goto err;
9d5c8243 2971
9d5c8243 2972 /* Round up to nearest 4K */
f33005a6 2973 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 2974 rx_ring->size = ALIGN(rx_ring->size, 4096);
2975
5536d210
AD		 2976 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2977 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2978 if (!rx_ring->desc)
2979 goto err;
2980
cbc8e55f 2981 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 2982 rx_ring->next_to_clean = 0;
2983 rx_ring->next_to_use = 0;
9d5c8243 2984
9d5c8243
AK		 2985 return 0;
2986
2987err:
06034649
AD		 2988 vfree(rx_ring->rx_buffer_info);
2989 rx_ring->rx_buffer_info = NULL;
f33005a6 2990 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 2991 return -ENOMEM;
2992}
2993
2994/**
2995 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2996 * (Descriptors) for all queues
2997 * @adapter: board private structure
2998 *
2999 * Return 0 on success, negative on failure
3000 **/
3001static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3002{
439705e1 3003 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3004 int i, err = 0;
3005
3006 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3007 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3008 if (err) {
439705e1 3009 dev_err(&pdev->dev,
9d5c8243
AK		 3010 "Allocation for Rx Queue %u failed\n", i);
3011 for (i--; i >= 0; i--)
3025a446 3012 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3013 break;
3014 }
3015 }
3016
3017 return err;
3018}
3019
06cf2666
AD		 3020/**
3021 * igb_setup_mrqc - configure the multiple receive queue control registers
3022 * @adapter: Board private structure
3023 **/
3024static void igb_setup_mrqc(struct igb_adapter *adapter)
3025{
3026 struct e1000_hw *hw = &adapter->hw;
3027 u32 mrqc, rxcsum;
797fd4be 3028 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3029 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3030 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3031 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3032 0xFA01ACBE };
06cf2666
AD		 3033
3034 /* Fill out hash function seeds */
a57fe23e
AD		 3035 for (j = 0; j < 10; j++)
3036 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3037
a99955fc 3038 num_rx_queues = adapter->rss_queues;
06cf2666 3039
797fd4be
AD		 3040 switch (hw->mac.type) {
3041 case e1000_82575:
3042 shift = 6;
3043 break;
3044 case e1000_82576:
3045 /* 82576 supports 2 RSS queues for SR-IOV */
3046 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3047 shift = 3;
3048 num_rx_queues = 2;
06cf2666 3049 }
797fd4be
AD		 3050 break;
3051 default:
3052 break;
06cf2666
AD		 3053 }
3054
797fd4be
AD		 3055 /*
3056 * Populate the indirection table 4 entries at a time. To do this
3057 * we are generating the results for n and n+2 and then interleaving
3058 * those with the results with n+1 and n+3.
3059 */
3060 for (j = 0; j < 32; j++) {
3061 /* first pass generates n and n+2 */
3062 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3063 u32 reta = (base & 0x07800780) >> (7 - shift);
3064
3065 /* second pass generates n+1 and n+3 */
3066 base += 0x00010001 * num_rx_queues;
3067 reta |= (base & 0x07800780) << (1 + shift);
3068
3069 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3070 }
3071
3072 /*
3073 * Disable raw packet checksumming so that RSS hash is placed in
3074 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3075 * offloads as they are enabled by default
3076 */
3077 rxcsum = rd32(E1000_RXCSUM);
3078 rxcsum |= E1000_RXCSUM_PCSD;
3079
3080 if (adapter->hw.mac.type >= e1000_82576)
3081 /* Enable Receive Checksum Offload for SCTP */
3082 rxcsum |= E1000_RXCSUM_CRCOFL;
3083
3084 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3085 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3086
039454a8
AA		 3087 /* Generate RSS hash based on packet types, TCP/UDP
3088 * port numbers and/or IPv4/v6 src and dst addresses
3089 */
f96a8a0b
CW		 3090 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3091 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3092 E1000_MRQC_RSS_FIELD_IPV6 |
3093 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3094 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3095
039454a8
AA		 3096 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3097 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3098 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3099 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3100
06cf2666
AD		 3101 /* If VMDq is enabled then we set the appropriate mode for that, else
3102 * we default to RSS so that an RSS hash is calculated per packet even
3103 * if we are only using one queue */
3104 if (adapter->vfs_allocated_count) {
3105 if (hw->mac.type > e1000_82575) {
3106 /* Set the default pool for the PF's first queue */
3107 u32 vtctl = rd32(E1000_VT_CTL);
3108 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3109 E1000_VT_CTL_DISABLE_DEF_POOL);
3110 vtctl |= adapter->vfs_allocated_count <<
3111 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3112 wr32(E1000_VT_CTL, vtctl);
3113 }
a99955fc 3114 if (adapter->rss_queues > 1)
f96a8a0b 3115 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3116 else
f96a8a0b 3117 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3118 } else {
f96a8a0b
CW		 3119 if (hw->mac.type != e1000_i211)
3120 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3121 }
3122 igb_vmm_control(adapter);
3123
06cf2666
AD		 3124 wr32(E1000_MRQC, mrqc);
3125}
3126
9d5c8243
AK		 3127/**
3128 * igb_setup_rctl - configure the receive control registers
3129 * @adapter: Board private structure
3130 **/
d7ee5b3a 3131void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3132{
3133 struct e1000_hw *hw = &adapter->hw;
3134 u32 rctl;
9d5c8243
AK		 3135
3136 rctl = rd32(E1000_RCTL);
3137
3138 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3139 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3140
69d728ba 3141 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3142 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3143
87cb7e8c
AK		 3144 /*
3145 * enable stripping of CRC. It's unlikely this will break BMC
3146 * redirection as it did with e1000. Newer features require
3147 * that the HW strips the CRC.
73cd78f1 3148 */
87cb7e8c 3149 rctl |= E1000_RCTL_SECRC;
9d5c8243 3150
559e9c49 3151 /* disable store bad packets and clear size bits. */
ec54d7d6 3152 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3153
6ec43fe6
AD		 3154 /* enable LPE to prevent packets larger than max_frame_size */
3155 rctl |= E1000_RCTL_LPE;
9d5c8243 3156
952f72a8
AD		 3157 /* disable queue 0 to prevent tail write w/o re-config */
3158 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3159
e1739522
AD		 3160 /* Attention!!! For SR-IOV PF driver operations you must enable
3161 * queue drop for all VF and PF queues to prevent head of line blocking
3162 * if an un-trusted VF does not provide descriptors to hardware.
3163 */
3164 if (adapter->vfs_allocated_count) {
e1739522
AD		 3165 /* set all queue drop enable bits */
3166 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3167 }
3168
89eaefb6
BG		 3169 /* This is useful for sniffing bad packets. */
3170 if (adapter->netdev->features & NETIF_F_RXALL) {
3171 /* UPE and MPE will be handled by normal PROMISC logic
3172 * in e1000e_set_rx_mode */
3173 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3174 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3175 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3176
3177 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3178 E1000_RCTL_DPF | /* Allow filtered pause */
3179 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3180 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3181 * and that breaks VLANs.
3182 */
3183 }
3184
9d5c8243
AK		 3185 wr32(E1000_RCTL, rctl);
3186}
3187
7d5753f0
AD		 3188static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3189 int vfn)
3190{
3191 struct e1000_hw *hw = &adapter->hw;
3192 u32 vmolr;
3193
3194 /* if it isn't the PF check to see if VFs are enabled and
3195 * increase the size to support vlan tags */
3196 if (vfn < adapter->vfs_allocated_count &&
3197 adapter->vf_data[vfn].vlans_enabled)
3198 size += VLAN_TAG_SIZE;
3199
3200 vmolr = rd32(E1000_VMOLR(vfn));
3201 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3202 vmolr |= size | E1000_VMOLR_LPE;
3203 wr32(E1000_VMOLR(vfn), vmolr);
3204
3205 return 0;
3206}
3207
e1739522
AD		 3208/**
3209 * igb_rlpml_set - set maximum receive packet size
3210 * @adapter: board private structure
3211 *
3212 * Configure maximum receivable packet size.
3213 **/
3214static void igb_rlpml_set(struct igb_adapter *adapter)
3215{
153285f9 3216 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3217 struct e1000_hw *hw = &adapter->hw;
3218 u16 pf_id = adapter->vfs_allocated_count;
3219
e1739522
AD		 3220 if (pf_id) {
3221 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3222 /*
3223 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3224 * to our max jumbo frame size, in case we need to enable
3225 * jumbo frames on one of the rings later.
3226 * This will not pass over-length frames into the default
3227 * queue because it's gated by the VMOLR.RLPML.
3228 */
7d5753f0 3229 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3230 }
3231
3232 wr32(E1000_RLPML, max_frame_size);
3233}
3234
8151d294
WM		 3235static inline void igb_set_vmolr(struct igb_adapter *adapter,
3236 int vfn, bool aupe)
7d5753f0
AD		 3237{
3238 struct e1000_hw *hw = &adapter->hw;
3239 u32 vmolr;
3240
3241 /*
3242 * This register exists only on 82576 and newer so if we are older then
3243 * we should exit and do nothing
3244 */
3245 if (hw->mac.type < e1000_82576)
3246 return;
3247
3248 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3249 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3250 if (aupe)
3251 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3252 else
3253 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3254
3255 /* clear all bits that might not be set */
3256 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3257
a99955fc 3258 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3259 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3260 /*
3261 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3262 * multicast packets
3263 */
3264 if (vfn <= adapter->vfs_allocated_count)
3265 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3266
3267 wr32(E1000_VMOLR(vfn), vmolr);
3268}
3269
85b430b4
AD		 3270/**
3271 * igb_configure_rx_ring - Configure a receive ring after Reset
3272 * @adapter: board private structure
3273 * @ring: receive ring to be configured
3274 *
3275 * Configure the Rx unit of the MAC after a reset.
3276 **/
d7ee5b3a
AD		 3277void igb_configure_rx_ring(struct igb_adapter *adapter,
3278 struct igb_ring *ring)
85b430b4
AD		 3279{
3280 struct e1000_hw *hw = &adapter->hw;
3281 u64 rdba = ring->dma;
3282 int reg_idx = ring->reg_idx;
a74420e0 3283 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3284
3285 /* disable the queue */
a74420e0 3286 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3287
3288 /* Set DMA base address registers */
3289 wr32(E1000_RDBAL(reg_idx),
3290 rdba & 0x00000000ffffffffULL);
3291 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3292 wr32(E1000_RDLEN(reg_idx),
3293 ring->count * sizeof(union e1000_adv_rx_desc));
3294
3295 /* initialize head and tail */
fce99e34 3296 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3297 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3298 writel(0, ring->tail);
85b430b4 3299
952f72a8 3300 /* set descriptor configuration */
44390ca6 3301 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3302 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3303 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3304 if (hw->mac.type >= e1000_82580)
757b77e2 3305 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3306 /* Only set Drop Enable if we are supporting multiple queues */
3307 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3308 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3309
3310 wr32(E1000_SRRCTL(reg_idx), srrctl);
3311
7d5753f0 3312 /* set filtering for VMDQ pools */
8151d294 3313 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3314
85b430b4
AD		 3315 rxdctl |= IGB_RX_PTHRESH;
3316 rxdctl |= IGB_RX_HTHRESH << 8;
3317 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3318
3319 /* enable receive descriptor fetching */
3320 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3321 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3322}
3323
9d5c8243
AK		 3324/**
3325 * igb_configure_rx - Configure receive Unit after Reset
3326 * @adapter: board private structure
3327 *
3328 * Configure the Rx unit of the MAC after a reset.
3329 **/
3330static void igb_configure_rx(struct igb_adapter *adapter)
3331{
9107584e 3332 int i;
9d5c8243 3333
68d480c4
AD		 3334 /* set UTA to appropriate mode */
3335 igb_set_uta(adapter);
3336
26ad9178
AD		 3337 /* set the correct pool for the PF default MAC address in entry 0 */
3338 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3339 adapter->vfs_allocated_count);
3340
06cf2666
AD		 3341 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3342 * the Base and Length of the Rx Descriptor Ring */
3343 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3344 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3345}
3346
3347/**
3348 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3349 * @tx_ring: Tx descriptor ring for a specific queue
3350 *
3351 * Free all transmit software resources
3352 **/
68fd9910 3353void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3354{
3b644cf6 3355 igb_clean_tx_ring(tx_ring);
9d5c8243 3356
06034649
AD		 3357 vfree(tx_ring->tx_buffer_info);
3358 tx_ring->tx_buffer_info = NULL;
9d5c8243 3359
439705e1
AD		 3360 /* if not set, then don't free */
3361 if (!tx_ring->desc)
3362 return;
3363
59d71989
AD		 3364 dma_free_coherent(tx_ring->dev, tx_ring->size,
3365 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3366
3367 tx_ring->desc = NULL;
3368}
3369
3370/**
3371 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3372 * @adapter: board private structure
3373 *
3374 * Free all transmit software resources
3375 **/
3376static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3377{
3378 int i;
3379
3380 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3381 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3382}
3383
ebe42d16
AD		 3384void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3385 struct igb_tx_buffer *tx_buffer)
3386{
3387 if (tx_buffer->skb) {
3388 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3389 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3390 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3391 dma_unmap_addr(tx_buffer, dma),
3392 dma_unmap_len(tx_buffer, len),
ebe42d16 3393 DMA_TO_DEVICE);
c9f14bf3 3394 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3395 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3396 dma_unmap_addr(tx_buffer, dma),
3397 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3398 DMA_TO_DEVICE);
3399 }
3400 tx_buffer->next_to_watch = NULL;
3401 tx_buffer->skb = NULL;
c9f14bf3 3402 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3403 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3404}
3405
3406/**
3407 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3408 * @tx_ring: ring to be cleaned
3409 **/
3b644cf6 3410static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3411{
06034649 3412 struct igb_tx_buffer *buffer_info;
9d5c8243 3413 unsigned long size;
6ad4edfc 3414 u16 i;
9d5c8243 3415
06034649 3416 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3417 return;
3418 /* Free all the Tx ring sk_buffs */
3419
3420 for (i = 0; i < tx_ring->count; i++) {
06034649 3421 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3422 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3423 }
3424
dad8a3b3
JF		 3425 netdev_tx_reset_queue(txring_txq(tx_ring));
3426
06034649
AD		 3427 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3428 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3429
3430 /* Zero out the descriptor ring */
9d5c8243
AK		 3431 memset(tx_ring->desc, 0, tx_ring->size);
3432
3433 tx_ring->next_to_use = 0;
3434 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3435}
3436
3437/**
3438 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3439 * @adapter: board private structure
3440 **/
3441static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3442{
3443 int i;
3444
3445 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3446 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3447}
3448
3449/**
3450 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3451 * @rx_ring: ring to clean the resources from
3452 *
3453 * Free all receive software resources
3454 **/
68fd9910 3455void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3456{
3b644cf6 3457 igb_clean_rx_ring(rx_ring);
9d5c8243 3458
06034649
AD		 3459 vfree(rx_ring->rx_buffer_info);
3460 rx_ring->rx_buffer_info = NULL;
9d5c8243 3461
439705e1
AD		 3462 /* if not set, then don't free */
3463 if (!rx_ring->desc)
3464 return;
3465
59d71989
AD		 3466 dma_free_coherent(rx_ring->dev, rx_ring->size,
3467 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3468
3469 rx_ring->desc = NULL;
3470}
3471
3472/**
3473 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3474 * @adapter: board private structure
3475 *
3476 * Free all receive software resources
3477 **/
3478static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3479{
3480 int i;
3481
3482 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3483 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3484}
3485
3486/**
3487 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3488 * @rx_ring: ring to free buffers from
3489 **/
3b644cf6 3490static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3491{
9d5c8243 3492 unsigned long size;
c023cd88 3493 u16 i;
9d5c8243 3494
1a1c225b
AD		 3495 if (rx_ring->skb)
3496 dev_kfree_skb(rx_ring->skb);
3497 rx_ring->skb = NULL;
3498
06034649 3499 if (!rx_ring->rx_buffer_info)
9d5c8243 3500 return;
439705e1 3501
9d5c8243
AK		 3502 /* Free all the Rx ring sk_buffs */
3503 for (i = 0; i < rx_ring->count; i++) {
06034649 3504 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3505
cbc8e55f
AD		 3506 if (!buffer_info->page)
3507 continue;
3508
3509 dma_unmap_page(rx_ring->dev,
3510 buffer_info->dma,
3511 PAGE_SIZE,
3512 DMA_FROM_DEVICE);
3513 __free_page(buffer_info->page);
3514
1a1c225b 3515 buffer_info->page = NULL;
9d5c8243
AK		 3516 }
3517
06034649
AD		 3518 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3519 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3520
3521 /* Zero out the descriptor ring */
3522 memset(rx_ring->desc, 0, rx_ring->size);
3523
cbc8e55f 3524 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3525 rx_ring->next_to_clean = 0;
3526 rx_ring->next_to_use = 0;
9d5c8243
AK		 3527}
3528
3529/**
3530 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3531 * @adapter: board private structure
3532 **/
3533static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3534{
3535 int i;
3536
3537 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3538 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3539}
3540
3541/**
3542 * igb_set_mac - Change the Ethernet Address of the NIC
3543 * @netdev: network interface device structure
3544 * @p: pointer to an address structure
3545 *
3546 * Returns 0 on success, negative on failure
3547 **/
3548static int igb_set_mac(struct net_device *netdev, void *p)
3549{
3550 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3551 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3552 struct sockaddr *addr = p;
3553
3554 if (!is_valid_ether_addr(addr->sa_data))
3555 return -EADDRNOTAVAIL;
3556
3557 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3558 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3559
26ad9178
AD		 3560 /* set the correct pool for the new PF MAC address in entry 0 */
3561 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3562 adapter->vfs_allocated_count);
e1739522 3563
9d5c8243
AK		 3564 return 0;
3565}
3566
3567/**
68d480c4 3568 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3569 * @netdev: network interface device structure
3570 *
68d480c4
AD		 3571 * Writes multicast address list to the MTA hash table.
3572 * Returns: -ENOMEM on failure
3573 * 0 on no addresses written
3574 * X on writing X addresses to MTA
9d5c8243 3575 **/
68d480c4 3576static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3577{
3578 struct igb_adapter *adapter = netdev_priv(netdev);
3579 struct e1000_hw *hw = &adapter->hw;
22bedad3 3580 struct netdev_hw_addr *ha;
68d480c4 3581 u8 *mta_list;
9d5c8243
AK		 3582 int i;
3583
4cd24eaf 3584 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3585 /* nothing to program, so clear mc list */
3586 igb_update_mc_addr_list(hw, NULL, 0);
3587 igb_restore_vf_multicasts(adapter);
3588 return 0;
3589 }
9d5c8243 3590
4cd24eaf 3591 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3592 if (!mta_list)
3593 return -ENOMEM;
ff41f8dc 3594
68d480c4 3595 /* The shared function expects a packed array of only addresses. */
48e2f183 3596 i = 0;
22bedad3
JP		 3597 netdev_for_each_mc_addr(ha, netdev)
3598 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3599
68d480c4
AD		 3600 igb_update_mc_addr_list(hw, mta_list, i);
3601 kfree(mta_list);
3602
4cd24eaf 3603 return netdev_mc_count(netdev);
68d480c4
AD		 3604}
3605
3606/**
3607 * igb_write_uc_addr_list - write unicast addresses to RAR table
3608 * @netdev: network interface device structure
3609 *
3610 * Writes unicast address list to the RAR table.
3611 * Returns: -ENOMEM on failure/insufficient address space
3612 * 0 on no addresses written
3613 * X on writing X addresses to the RAR table
3614 **/
3615static int igb_write_uc_addr_list(struct net_device *netdev)
3616{
3617 struct igb_adapter *adapter = netdev_priv(netdev);
3618 struct e1000_hw *hw = &adapter->hw;
3619 unsigned int vfn = adapter->vfs_allocated_count;
3620 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3621 int count = 0;
3622
3623 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3624 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3625 return -ENOMEM;
9d5c8243 3626
32e7bfc4 3627 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3628 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3629
3630 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3631 if (!rar_entries)
3632 break;
26ad9178
AD		 3633 igb_rar_set_qsel(adapter, ha->addr,
3634 rar_entries--,
68d480c4
AD		 3635 vfn);
3636 count++;
ff41f8dc
AD		 3637 }
3638 }
3639 /* write the addresses in reverse order to avoid write combining */
3640 for (; rar_entries > 0 ; rar_entries--) {
3641 wr32(E1000_RAH(rar_entries), 0);
3642 wr32(E1000_RAL(rar_entries), 0);
3643 }
3644 wrfl();
3645
68d480c4
AD		 3646 return count;
3647}
3648
3649/**
3650 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3651 * @netdev: network interface device structure
3652 *
3653 * The set_rx_mode entry point is called whenever the unicast or multicast
3654 * address lists or the network interface flags are updated. This routine is
3655 * responsible for configuring the hardware for proper unicast, multicast,
3656 * promiscuous mode, and all-multi behavior.
3657 **/
3658static void igb_set_rx_mode(struct net_device *netdev)
3659{
3660 struct igb_adapter *adapter = netdev_priv(netdev);
3661 struct e1000_hw *hw = &adapter->hw;
3662 unsigned int vfn = adapter->vfs_allocated_count;
3663 u32 rctl, vmolr = 0;
3664 int count;
3665
3666 /* Check for Promiscuous and All Multicast modes */
3667 rctl = rd32(E1000_RCTL);
3668
3669 /* clear the effected bits */
3670 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3671
3672 if (netdev->flags & IFF_PROMISC) {
3673 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3674 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3675 } else {
3676 if (netdev->flags & IFF_ALLMULTI) {
3677 rctl |= E1000_RCTL_MPE;
3678 vmolr |= E1000_VMOLR_MPME;
3679 } else {
3680 /*
3681 * Write addresses to the MTA, if the attempt fails
25985edc 3682 * then we should just turn on promiscuous mode so
68d480c4
AD		 3683 * that we can at least receive multicast traffic
3684 */
3685 count = igb_write_mc_addr_list(netdev);
3686 if (count < 0) {
3687 rctl |= E1000_RCTL_MPE;
3688 vmolr |= E1000_VMOLR_MPME;
3689 } else if (count) {
3690 vmolr |= E1000_VMOLR_ROMPE;
3691 }
3692 }
3693 /*
3694 * Write addresses to available RAR registers, if there is not
3695 * sufficient space to store all the addresses then enable
25985edc 3696 * unicast promiscuous mode
68d480c4
AD		 3697 */
3698 count = igb_write_uc_addr_list(netdev);
3699 if (count < 0) {
3700 rctl |= E1000_RCTL_UPE;
3701 vmolr |= E1000_VMOLR_ROPE;
3702 }
3703 rctl |= E1000_RCTL_VFE;
28fc06f5 3704 }
68d480c4 3705 wr32(E1000_RCTL, rctl);
28fc06f5 3706
68d480c4
AD		 3707 /*
3708 * In order to support SR-IOV and eventually VMDq it is necessary to set
3709 * the VMOLR to enable the appropriate modes. Without this workaround
3710 * we will have issues with VLAN tag stripping not being done for frames
3711 * that are only arriving because we are the default pool
3712 */
f96a8a0b 3713 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3714 return;
9d5c8243 3715
68d480c4
AD		 3716 vmolr |= rd32(E1000_VMOLR(vfn)) &
3717 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3718 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3719 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3720}
3721
13800469
GR		 3722static void igb_check_wvbr(struct igb_adapter *adapter)
3723{
3724 struct e1000_hw *hw = &adapter->hw;
3725 u32 wvbr = 0;
3726
3727 switch (hw->mac.type) {
3728 case e1000_82576:
3729 case e1000_i350:
3730 if (!(wvbr = rd32(E1000_WVBR)))
3731 return;
3732 break;
3733 default:
3734 break;
3735 }
3736
3737 adapter->wvbr |= wvbr;
3738}
3739
3740#define IGB_STAGGERED_QUEUE_OFFSET 8
3741
3742static void igb_spoof_check(struct igb_adapter *adapter)
3743{
3744 int j;
3745
3746 if (!adapter->wvbr)
3747 return;
3748
3749 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3750 if (adapter->wvbr & (1 << j) ||
3751 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3752 dev_warn(&adapter->pdev->dev,
3753 "Spoof event(s) detected on VF %d\n", j);
3754 adapter->wvbr &=
3755 ~((1 << j) |
3756 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3757 }
3758 }
3759}
3760
9d5c8243
AK		 3761/* Need to wait a few seconds after link up to get diagnostic information from
3762 * the phy */
3763static void igb_update_phy_info(unsigned long data)
3764{
3765 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3766 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3767}
3768
4d6b725e
AD		 3769/**
3770 * igb_has_link - check shared code for link and determine up/down
3771 * @adapter: pointer to driver private info
3772 **/
3145535a 3773bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3774{
3775 struct e1000_hw *hw = &adapter->hw;
3776 bool link_active = false;
3777 s32 ret_val = 0;
3778
3779 /* get_link_status is set on LSC (link status) interrupt or
3780 * rx sequence error interrupt. get_link_status will stay
3781 * false until the e1000_check_for_link establishes link
3782 * for copper adapters ONLY
3783 */
3784 switch (hw->phy.media_type) {
3785 case e1000_media_type_copper:
3786 if (hw->mac.get_link_status) {
3787 ret_val = hw->mac.ops.check_for_link(hw);
3788 link_active = !hw->mac.get_link_status;
3789 } else {
3790 link_active = true;
3791 }
3792 break;
4d6b725e
AD		 3793 case e1000_media_type_internal_serdes:
3794 ret_val = hw->mac.ops.check_for_link(hw);
3795 link_active = hw->mac.serdes_has_link;
3796 break;
3797 default:
3798 case e1000_media_type_unknown:
3799 break;
3800 }
3801
3802 return link_active;
3803}
3804
563988dc
SA		 3805static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3806{
3807 bool ret = false;
3808 u32 ctrl_ext, thstat;
3809
f96a8a0b 3810 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3811 if (hw->mac.type == e1000_i350) {
3812 thstat = rd32(E1000_THSTAT);
3813 ctrl_ext = rd32(E1000_CTRL_EXT);
3814
3815 if ((hw->phy.media_type == e1000_media_type_copper) &&
3816 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3817 ret = !!(thstat & event);
3818 }
3819 }
3820
3821 return ret;
3822}
3823
9d5c8243
AK		 3824/**
3825 * igb_watchdog - Timer Call-back
3826 * @data: pointer to adapter cast into an unsigned long
3827 **/
3828static void igb_watchdog(unsigned long data)
3829{
3830 struct igb_adapter *adapter = (struct igb_adapter *)data;
3831 /* Do the rest outside of interrupt context */
3832 schedule_work(&adapter->watchdog_task);
3833}
3834
3835static void igb_watchdog_task(struct work_struct *work)
3836{
3837 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3838 struct igb_adapter,
3839 watchdog_task);
9d5c8243 3840 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3841 struct net_device *netdev = adapter->netdev;
563988dc 3842 u32 link;
7a6ea550 3843 int i;
9d5c8243 3844
4d6b725e 3845 link = igb_has_link(adapter);
9d5c8243 3846 if (link) {
749ab2cd
YZ		 3847 /* Cancel scheduled suspend requests. */
3848 pm_runtime_resume(netdev->dev.parent);
3849
9d5c8243
AK		 3850 if (!netif_carrier_ok(netdev)) {
3851 u32 ctrl;
330a6d6a
AD		 3852 hw->mac.ops.get_speed_and_duplex(hw,
3853 &adapter->link_speed,
3854 &adapter->link_duplex);
9d5c8243
AK		 3855
3856 ctrl = rd32(E1000_CTRL);
527d47c1 3857 /* Links status message must follow this format */
876d2d6f
JK		 3858 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3859 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3860 netdev->name,
3861 adapter->link_speed,
3862 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3863 "Full" : "Half",
3864 (ctrl & E1000_CTRL_TFCE) &&
3865 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3866 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3867 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3868
563988dc 3869 /* check for thermal sensor event */
876d2d6f
JK		 3870 if (igb_thermal_sensor_event(hw,
3871 E1000_THSTAT_LINK_THROTTLE)) {
3872 netdev_info(netdev, "The network adapter link "
3873 "speed was downshifted because it "
3874 "overheated\n");
7ef5ed1c 3875 }
563988dc 3876
d07f3e37 3877 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3878 adapter->tx_timeout_factor = 1;
3879 switch (adapter->link_speed) {
3880 case SPEED_10:
9d5c8243
AK		 3881 adapter->tx_timeout_factor = 14;
3882 break;
3883 case SPEED_100:
9d5c8243
AK		 3884 /* maybe add some timeout factor ? */
3885 break;
3886 }
3887
3888 netif_carrier_on(netdev);
9d5c8243 3889
4ae196df 3890 igb_ping_all_vfs(adapter);
17dc566c 3891 igb_check_vf_rate_limit(adapter);
4ae196df 3892
4b1a9877 3893 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3894 if (!test_bit(__IGB_DOWN, &adapter->state))
3895 mod_timer(&adapter->phy_info_timer,
3896 round_jiffies(jiffies + 2 * HZ));
3897 }
3898 } else {
3899 if (netif_carrier_ok(netdev)) {
3900 adapter->link_speed = 0;
3901 adapter->link_duplex = 0;
563988dc
SA		 3902
3903 /* check for thermal sensor event */
876d2d6f
JK		 3904 if (igb_thermal_sensor_event(hw,
3905 E1000_THSTAT_PWR_DOWN)) {
3906 netdev_err(netdev, "The network adapter was "
3907 "stopped because it overheated\n");
7ef5ed1c 3908 }
563988dc 3909
527d47c1
AD		 3910 /* Links status message must follow this format */
3911 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3912 netdev->name);
9d5c8243 3913 netif_carrier_off(netdev);
4b1a9877 3914
4ae196df
AD		 3915 igb_ping_all_vfs(adapter);
3916
4b1a9877 3917 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3918 if (!test_bit(__IGB_DOWN, &adapter->state))
3919 mod_timer(&adapter->phy_info_timer,
3920 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3921
3922 pm_schedule_suspend(netdev->dev.parent,
3923 MSEC_PER_SEC * 5);
9d5c8243
AK		 3924 }
3925 }
3926
12dcd86b
ED		 3927 spin_lock(&adapter->stats64_lock);
3928 igb_update_stats(adapter, &adapter->stats64);
3929 spin_unlock(&adapter->stats64_lock);
9d5c8243 3930
dbabb065 3931 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3932 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3933 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3934 /* We've lost link, so the controller stops DMA,
3935 * but we've got queued Tx work that's never going
3936 * to get done, so reset controller to flush Tx.
3937 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3938 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3939 adapter->tx_timeout_count++;
3940 schedule_work(&adapter->reset_task);
3941 /* return immediately since reset is imminent */
3942 return;
3943 }
9d5c8243 3944 }
9d5c8243 3945
dbabb065 3946 /* Force detection of hung controller every watchdog period */
6d095fa8 3947 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3948 }
f7ba205e 3949
9d5c8243 3950 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3951 if (adapter->msix_entries) {
047e0030 3952 u32 eics = 0;
0d1ae7f4
AD		 3953 for (i = 0; i < adapter->num_q_vectors; i++)
3954 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3955 wr32(E1000_EICS, eics);
3956 } else {
3957 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3958 }
9d5c8243 3959
13800469
GR		 3960 igb_spoof_check(adapter);
3961
9d5c8243
AK		 3962 /* Reset the timer */
3963 if (!test_bit(__IGB_DOWN, &adapter->state))
3964 mod_timer(&adapter->watchdog_timer,
3965 round_jiffies(jiffies + 2 * HZ));
3966}
3967
3968enum latency_range {
3969 lowest_latency = 0,
3970 low_latency = 1,
3971 bulk_latency = 2,
3972 latency_invalid = 255
3973};
3974
6eb5a7f1
AD		 3975/**
3976 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3977 *
3978 * Stores a new ITR value based on strictly on packet size. This
3979 * algorithm is less sophisticated than that used in igb_update_itr,
3980 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3981 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3982 * were determined based on theoretical maximum wire speed and testing
3983 * data, in order to minimize response time while increasing bulk
3984 * throughput.
3985 * This functionality is controlled by the InterruptThrottleRate module
3986 * parameter (see igb_param.c)
3987 * NOTE: This function is called only when operating in a multiqueue
3988 * receive environment.
047e0030 3989 * @q_vector: pointer to q_vector
6eb5a7f1 3990 **/
047e0030 3991static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3992{
047e0030 3993 int new_val = q_vector->itr_val;
6eb5a7f1 3994 int avg_wire_size = 0;
047e0030 3995 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3996 unsigned int packets;
9d5c8243 3997
6eb5a7f1
AD		 3998 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3999 * ints/sec - ITR timer value of 120 ticks.
4000 */
4001 if (adapter->link_speed != SPEED_1000) {
0ba82994 4002 new_val = IGB_4K_ITR;
6eb5a7f1 4003 goto set_itr_val;
9d5c8243 4004 }
047e0030 4005
0ba82994
AD		 4006 packets = q_vector->rx.total_packets;
4007 if (packets)
4008 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4009
0ba82994
AD		 4010 packets = q_vector->tx.total_packets;
4011 if (packets)
4012 avg_wire_size = max_t(u32, avg_wire_size,
4013 q_vector->tx.total_bytes / packets);
047e0030
AD		 4014
4015 /* if avg_wire_size isn't set no work was done */
4016 if (!avg_wire_size)
4017 goto clear_counts;
9d5c8243 4018
6eb5a7f1
AD		 4019 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4020 avg_wire_size += 24;
4021
4022 /* Don't starve jumbo frames */
4023 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4024
6eb5a7f1
AD		 4025 /* Give a little boost to mid-size frames */
4026 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4027 new_val = avg_wire_size / 3;
4028 else
4029 new_val = avg_wire_size / 2;
9d5c8243 4030
0ba82994
AD		 4031 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4032 if (new_val < IGB_20K_ITR &&
4033 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4034 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4035 new_val = IGB_20K_ITR;
abe1c363 4036
6eb5a7f1 4037set_itr_val:
047e0030
AD		 4038 if (new_val != q_vector->itr_val) {
4039 q_vector->itr_val = new_val;
4040 q_vector->set_itr = 1;
9d5c8243 4041 }
6eb5a7f1 4042clear_counts:
0ba82994
AD		 4043 q_vector->rx.total_bytes = 0;
4044 q_vector->rx.total_packets = 0;
4045 q_vector->tx.total_bytes = 0;
4046 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4047}
4048
4049/**
4050 * igb_update_itr - update the dynamic ITR value based on statistics
4051 * Stores a new ITR value based on packets and byte
4052 * counts during the last interrupt. The advantage of per interrupt
4053 * computation is faster updates and more accurate ITR for the current
4054 * traffic pattern. Constants in this function were computed
4055 * based on theoretical maximum wire speed and thresholds were set based
4056 * on testing data as well as attempting to minimize response time
4057 * while increasing bulk throughput.
4058 * this functionality is controlled by the InterruptThrottleRate module
4059 * parameter (see igb_param.c)
4060 * NOTE: These calculations are only valid when operating in a single-
4061 * queue environment.
0ba82994
AD		 4062 * @q_vector: pointer to q_vector
4063 * @ring_container: ring info to update the itr for
9d5c8243 4064 **/
0ba82994
AD		 4065static void igb_update_itr(struct igb_q_vector *q_vector,
4066 struct igb_ring_container *ring_container)
9d5c8243 4067{
0ba82994
AD		 4068 unsigned int packets = ring_container->total_packets;
4069 unsigned int bytes = ring_container->total_bytes;
4070 u8 itrval = ring_container->itr;
9d5c8243 4071
0ba82994 4072 /* no packets, exit with status unchanged */
9d5c8243 4073 if (packets == 0)
0ba82994 4074 return;
9d5c8243 4075
0ba82994 4076 switch (itrval) {
9d5c8243
AK		 4077 case lowest_latency:
4078 /* handle TSO and jumbo frames */
4079 if (bytes/packets > 8000)
0ba82994 4080 itrval = bulk_latency;
9d5c8243 4081 else if ((packets < 5) && (bytes > 512))
0ba82994 4082 itrval = low_latency;
9d5c8243
AK		 4083 break;
4084 case low_latency: /* 50 usec aka 20000 ints/s */
4085 if (bytes > 10000) {
4086 /* this if handles the TSO accounting */
4087 if (bytes/packets > 8000) {
0ba82994 4088 itrval = bulk_latency;
9d5c8243 4089 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4090 itrval = bulk_latency;
9d5c8243 4091 } else if ((packets > 35)) {
0ba82994 4092 itrval = lowest_latency;
9d5c8243
AK		 4093 }
4094 } else if (bytes/packets > 2000) {
0ba82994 4095 itrval = bulk_latency;
9d5c8243 4096 } else if (packets <= 2 && bytes < 512) {
0ba82994 4097 itrval = lowest_latency;
9d5c8243
AK		 4098 }
4099 break;
4100 case bulk_latency: /* 250 usec aka 4000 ints/s */
4101 if (bytes > 25000) {
4102 if (packets > 35)
0ba82994 4103 itrval = low_latency;
1e5c3d21 4104 } else if (bytes < 1500) {
0ba82994 4105 itrval = low_latency;
9d5c8243
AK		 4106 }
4107 break;
4108 }
4109
0ba82994
AD		 4110 /* clear work counters since we have the values we need */
4111 ring_container->total_bytes = 0;
4112 ring_container->total_packets = 0;
4113
4114 /* write updated itr to ring container */
4115 ring_container->itr = itrval;
9d5c8243
AK		 4116}
4117
0ba82994 4118static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4119{
0ba82994 4120 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4121 u32 new_itr = q_vector->itr_val;
0ba82994 4122 u8 current_itr = 0;
9d5c8243
AK		 4123
4124 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4125 if (adapter->link_speed != SPEED_1000) {
4126 current_itr = 0;
0ba82994 4127 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4128 goto set_itr_now;
4129 }
4130
0ba82994
AD		 4131 igb_update_itr(q_vector, &q_vector->tx);
4132 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4133
0ba82994 4134 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4135
6eb5a7f1 4136 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4137 if (current_itr == lowest_latency &&
4138 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4139 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4140 current_itr = low_latency;
4141
9d5c8243
AK		 4142 switch (current_itr) {
4143 /* counts and packets in update_itr are dependent on these numbers */
4144 case lowest_latency:
0ba82994 4145 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4146 break;
4147 case low_latency:
0ba82994 4148 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4149 break;
4150 case bulk_latency:
0ba82994 4151 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4152 break;
4153 default:
4154 break;
4155 }
4156
4157set_itr_now:
047e0030 4158 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4159 /* this attempts to bias the interrupt rate towards Bulk
4160 * by adding intermediate steps when interrupt rate is
4161 * increasing */
047e0030
AD		 4162 new_itr = new_itr > q_vector->itr_val ?
4163 max((new_itr * q_vector->itr_val) /
4164 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 4165 new_itr) :
9d5c8243
AK		 4166 new_itr;
4167 /* Don't write the value here; it resets the adapter's
4168 * internal timer, and causes us to delay far longer than
4169 * we should between interrupts. Instead, we write the ITR
4170 * value at the beginning of the next interrupt so the timing
4171 * ends up being correct.
4172 */
047e0030
AD		 4173 q_vector->itr_val = new_itr;
4174 q_vector->set_itr = 1;
9d5c8243 4175 }
9d5c8243
AK		 4176}
4177
c50b52a0
SH		 4178static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4179 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4180{
4181 struct e1000_adv_tx_context_desc *context_desc;
4182 u16 i = tx_ring->next_to_use;
4183
4184 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4185
4186 i++;
4187 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4188
4189 /* set bits to identify this as an advanced context descriptor */
4190 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4191
4192 /* For 82575, context index must be unique per ring. */
866cff06 4193 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4194 mss_l4len_idx |= tx_ring->reg_idx << 4;
4195
4196 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4197 context_desc->seqnum_seed = 0;
4198 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4199 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4200}
4201
7af40ad9
AD		 4202static int igb_tso(struct igb_ring *tx_ring,
4203 struct igb_tx_buffer *first,
4204 u8 *hdr_len)
9d5c8243 4205{
7af40ad9 4206 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4207 u32 vlan_macip_lens, type_tucmd;
4208 u32 mss_l4len_idx, l4len;
4209
ed6aa105
AD		 4210 if (skb->ip_summed != CHECKSUM_PARTIAL)
4211 return 0;
4212
7d13a7d0
AD		 4213 if (!skb_is_gso(skb))
4214 return 0;
9d5c8243
AK		 4215
4216 if (skb_header_cloned(skb)) {
7af40ad9 4217 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4218 if (err)
4219 return err;
4220 }
4221
7d13a7d0
AD		 4222 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4223 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4224
7af40ad9 4225 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4226 struct iphdr *iph = ip_hdr(skb);
4227 iph->tot_len = 0;
4228 iph->check = 0;
4229 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4230 iph->daddr, 0,
4231 IPPROTO_TCP,
4232 0);
7d13a7d0 4233 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4234 first->tx_flags |= IGB_TX_FLAGS_TSO |
4235 IGB_TX_FLAGS_CSUM |
4236 IGB_TX_FLAGS_IPV4;
8e1e8a47 4237 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4238 ipv6_hdr(skb)->payload_len = 0;
4239 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4240 &ipv6_hdr(skb)->daddr,
4241 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4242 first->tx_flags |= IGB_TX_FLAGS_TSO |
4243 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4244 }
4245
7af40ad9 4246 /* compute header lengths */
7d13a7d0
AD		 4247 l4len = tcp_hdrlen(skb);
4248 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4249
7af40ad9
AD		 4250 /* update gso size and bytecount with header size */
4251 first->gso_segs = skb_shinfo(skb)->gso_segs;
4252 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4253
9d5c8243 4254 /* MSS L4LEN IDX */
7d13a7d0
AD		 4255 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4256 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4257
7d13a7d0
AD		 4258 /* VLAN MACLEN IPLEN */
4259 vlan_macip_lens = skb_network_header_len(skb);
4260 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4261 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4262
7d13a7d0 4263 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4264
7d13a7d0 4265 return 1;
9d5c8243
AK		 4266}
4267
7af40ad9 4268static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4269{
7af40ad9 4270 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4271 u32 vlan_macip_lens = 0;
4272 u32 mss_l4len_idx = 0;
4273 u32 type_tucmd = 0;
9d5c8243 4274
7d13a7d0 4275 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4276 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4277 return;
7d13a7d0
AD		 4278 } else {
4279 u8 l4_hdr = 0;
7af40ad9 4280 switch (first->protocol) {
7d13a7d0
AD		 4281 case __constant_htons(ETH_P_IP):
4282 vlan_macip_lens |= skb_network_header_len(skb);
4283 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4284 l4_hdr = ip_hdr(skb)->protocol;
4285 break;
4286 case __constant_htons(ETH_P_IPV6):
4287 vlan_macip_lens |= skb_network_header_len(skb);
4288 l4_hdr = ipv6_hdr(skb)->nexthdr;
4289 break;
4290 default:
4291 if (unlikely(net_ratelimit())) {
4292 dev_warn(tx_ring->dev,
4293 "partial checksum but proto=%x!\n",
7af40ad9 4294 first->protocol);
fa4a7ef3 4295 }
7d13a7d0
AD		 4296 break;
4297 }
fa4a7ef3 4298
7d13a7d0
AD		 4299 switch (l4_hdr) {
4300 case IPPROTO_TCP:
4301 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4302 mss_l4len_idx = tcp_hdrlen(skb) <<
4303 E1000_ADVTXD_L4LEN_SHIFT;
4304 break;
4305 case IPPROTO_SCTP:
4306 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4307 mss_l4len_idx = sizeof(struct sctphdr) <<
4308 E1000_ADVTXD_L4LEN_SHIFT;
4309 break;
4310 case IPPROTO_UDP:
4311 mss_l4len_idx = sizeof(struct udphdr) <<
4312 E1000_ADVTXD_L4LEN_SHIFT;
4313 break;
4314 default:
4315 if (unlikely(net_ratelimit())) {
4316 dev_warn(tx_ring->dev,
4317 "partial checksum but l4 proto=%x!\n",
4318 l4_hdr);
44b0cda3 4319 }
7d13a7d0 4320 break;
9d5c8243 4321 }
7af40ad9
AD		 4322
4323 /* update TX checksum flag */
4324 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4325 }
9d5c8243 4326
7d13a7d0 4327 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4328 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4329
7d13a7d0 4330 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4331}
4332
1d9daf45
AD		 4333#define IGB_SET_FLAG(_input, _flag, _result) \
4334 ((_flag <= _result) ? \
4335 ((u32)(_input & _flag) * (_result / _flag)) : \
4336 ((u32)(_input & _flag) / (_flag / _result)))
4337
4338static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4339{
4340 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4341 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4342 E1000_ADVTXD_DCMD_DEXT |
4343 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4344
4345 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4346 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4347 (E1000_ADVTXD_DCMD_VLE));
4348
4349 /* set segmentation bits for TSO */
4350 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4351 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4352
4353 /* set timestamp bit if present */
1d9daf45
AD		 4354 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4355 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4356
1d9daf45
AD		 4357 /* insert frame checksum */
4358 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4359
4360 return cmd_type;
4361}
4362
7af40ad9
AD		 4363static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4364 union e1000_adv_tx_desc *tx_desc,
4365 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4366{
4367 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4368
1d9daf45
AD		 4369 /* 82575 requires a unique index per ring */
4370 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4371 olinfo_status |= tx_ring->reg_idx << 4;
4372
4373 /* insert L4 checksum */
1d9daf45
AD		 4374 olinfo_status |= IGB_SET_FLAG(tx_flags,
4375 IGB_TX_FLAGS_CSUM,
4376 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4377
1d9daf45
AD		 4378 /* insert IPv4 checksum */
4379 olinfo_status |= IGB_SET_FLAG(tx_flags,
4380 IGB_TX_FLAGS_IPV4,
4381 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4382
7af40ad9 4383 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4384}
4385
ebe42d16
AD		 4386/*
4387 * The largest size we can write to the descriptor is 65535. In order to
4388 * maintain a power of two alignment we have to limit ourselves to 32K.
4389 */
4390#define IGB_MAX_TXD_PWR 15
7af40ad9 4391#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4392
7af40ad9
AD		 4393static void igb_tx_map(struct igb_ring *tx_ring,
4394 struct igb_tx_buffer *first,
ebe42d16 4395 const u8 hdr_len)
9d5c8243 4396{
7af40ad9 4397 struct sk_buff *skb = first->skb;
c9f14bf3 4398 struct igb_tx_buffer *tx_buffer;
ebe42d16 4399 union e1000_adv_tx_desc *tx_desc;
80d0759e 4400 struct skb_frag_struct *frag;
ebe42d16 4401 dma_addr_t dma;
80d0759e 4402 unsigned int data_len, size;
7af40ad9 4403 u32 tx_flags = first->tx_flags;
1d9daf45 4404 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4405 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4406
4407 tx_desc = IGB_TX_DESC(tx_ring, i);
4408
80d0759e
AD		 4409 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4410
4411 size = skb_headlen(skb);
4412 data_len = skb->data_len;
ebe42d16
AD		 4413
4414 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4415
80d0759e
AD		 4416 tx_buffer = first;
4417
4418 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4419 if (dma_mapping_error(tx_ring->dev, dma))
4420 goto dma_error;
4421
4422 /* record length, and DMA address */
4423 dma_unmap_len_set(tx_buffer, len, size);
4424 dma_unmap_addr_set(tx_buffer, dma, dma);
4425
4426 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4427
ebe42d16
AD		 4428 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4429 tx_desc->read.cmd_type_len =
1d9daf45 4430 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4431
4432 i++;
4433 tx_desc++;
4434 if (i == tx_ring->count) {
4435 tx_desc = IGB_TX_DESC(tx_ring, 0);
4436 i = 0;
4437 }
80d0759e 4438 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4439
4440 dma += IGB_MAX_DATA_PER_TXD;
4441 size -= IGB_MAX_DATA_PER_TXD;
4442
ebe42d16
AD		 4443 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4444 }
4445
4446 if (likely(!data_len))
4447 break;
2bbfebe2 4448
1d9daf45 4449 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4450
65689fef 4451 i++;
ebe42d16
AD		 4452 tx_desc++;
4453 if (i == tx_ring->count) {
4454 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4455 i = 0;
ebe42d16 4456 }
80d0759e 4457 tx_desc->read.olinfo_status = 0;
65689fef 4458
9e903e08 4459 size = skb_frag_size(frag);
ebe42d16
AD		 4460 data_len -= size;
4461
4462 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4463 size, DMA_TO_DEVICE);
6366ad33 4464
c9f14bf3 4465 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4466 }
4467
ebe42d16 4468 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4469 cmd_type |= size | IGB_TXD_DCMD;
4470 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4471
80d0759e
AD		 4472 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4473
8542db05
AD		 4474 /* set the timestamp */
4475 first->time_stamp = jiffies;
4476
ebe42d16
AD		 4477 /*
4478 * Force memory writes to complete before letting h/w know there
4479 * are new descriptors to fetch. (Only applicable for weak-ordered
4480 * memory model archs, such as IA-64).
4481 *
4482 * We also need this memory barrier to make certain all of the
4483 * status bits have been updated before next_to_watch is written.
4484 */
4485 wmb();
4486
8542db05 4487 /* set next_to_watch value indicating a packet is present */
ebe42d16 4488 first->next_to_watch = tx_desc;
9d5c8243 4489
ebe42d16
AD		 4490 i++;
4491 if (i == tx_ring->count)
4492 i = 0;
6366ad33 4493
ebe42d16 4494 tx_ring->next_to_use = i;
6366ad33 4495
ebe42d16 4496 writel(i, tx_ring->tail);
6366ad33 4497
ebe42d16
AD		 4498 /* we need this if more than one processor can write to our tail
4499 * at a time, it syncronizes IO on IA64/Altix systems */
4500 mmiowb();
4501
4502 return;
4503
4504dma_error:
4505 dev_err(tx_ring->dev, "TX DMA map failed\n");
4506
4507 /* clear dma mappings for failed tx_buffer_info map */
4508 for (;;) {
c9f14bf3
AD		 4509 tx_buffer = &tx_ring->tx_buffer_info[i];
4510 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4511 if (tx_buffer == first)
ebe42d16 4512 break;
a77ff709
NN		 4513 if (i == 0)
4514 i = tx_ring->count;
6366ad33 4515 i--;
6366ad33
AD		 4516 }
4517
9d5c8243 4518 tx_ring->next_to_use = i;
9d5c8243
AK		 4519}
4520
6ad4edfc 4521static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4522{
e694e964
AD		 4523 struct net_device *netdev = tx_ring->netdev;
4524
661086df 4525 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4526
9d5c8243
AK		 4527 /* Herbert's original patch had:
4528 * smp_mb__after_netif_stop_queue();
4529 * but since that doesn't exist yet, just open code it. */
4530 smp_mb();
4531
4532 /* We need to check again in a case another CPU has just
4533 * made room available. */
c493ea45 4534 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4535 return -EBUSY;
4536
4537 /* A reprieve! */
661086df 4538 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4539
4540 u64_stats_update_begin(&tx_ring->tx_syncp2);
4541 tx_ring->tx_stats.restart_queue2++;
4542 u64_stats_update_end(&tx_ring->tx_syncp2);
4543
9d5c8243
AK		 4544 return 0;
4545}
4546
6ad4edfc 4547static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4548{
c493ea45 4549 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4550 return 0;
e694e964 4551 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4552}
4553
cd392f5c
AD		 4554netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4555 struct igb_ring *tx_ring)
9d5c8243 4556{
1f6e8178 4557 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4558 struct igb_tx_buffer *first;
ebe42d16 4559 int tso;
91d4ee33 4560 u32 tx_flags = 0;
31f6adbb 4561 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4562 u8 hdr_len = 0;
9d5c8243 4563
9d5c8243
AK		 4564 /* need: 1 descriptor per page,
4565 * + 2 desc gap to keep tail from touching head,
4566 * + 1 desc for skb->data,
4567 * + 1 desc for context descriptor,
4568 * otherwise try next time */
e694e964 4569 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4570 /* this is a hard error */
9d5c8243
AK		 4571 return NETDEV_TX_BUSY;
4572 }
33af6bcc 4573
7af40ad9
AD		 4574 /* record the location of the first descriptor for this packet */
4575 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4576 first->skb = skb;
4577 first->bytecount = skb->len;
4578 first->gso_segs = 1;
4579
1f6e8178
MV		 4580 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4581 !(adapter->ptp_tx_skb))) {
2244d07b 4582 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4583 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4584
4585 adapter->ptp_tx_skb = skb_get(skb);
4586 if (adapter->hw.mac.type == e1000_82576)
4587 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4588 }
9d5c8243 4589
eab6d18d 4590 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4591 tx_flags |= IGB_TX_FLAGS_VLAN;
4592 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4593 }
4594
7af40ad9
AD		 4595 /* record initial flags and protocol */
4596 first->tx_flags = tx_flags;
4597 first->protocol = protocol;
cdfd01fc 4598
7af40ad9
AD		 4599 tso = igb_tso(tx_ring, first, &hdr_len);
4600 if (tso < 0)
7d13a7d0 4601 goto out_drop;
7af40ad9
AD		 4602 else if (!tso)
4603 igb_tx_csum(tx_ring, first);
9d5c8243 4604
7af40ad9 4605 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4606
4607 /* Make sure there is space in the ring for the next send. */
e694e964 4608 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4609
9d5c8243 4610 return NETDEV_TX_OK;
7d13a7d0
AD		 4611
4612out_drop:
7af40ad9
AD		 4613 igb_unmap_and_free_tx_resource(tx_ring, first);
4614
7d13a7d0 4615 return NETDEV_TX_OK;
9d5c8243
AK		 4616}
4617
1cc3bd87
AD		 4618static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4619 struct sk_buff *skb)
4620{
4621 unsigned int r_idx = skb->queue_mapping;
4622
4623 if (r_idx >= adapter->num_tx_queues)
4624 r_idx = r_idx % adapter->num_tx_queues;
4625
4626 return adapter->tx_ring[r_idx];
4627}
4628
cd392f5c
AD		 4629static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4630 struct net_device *netdev)
9d5c8243
AK		 4631{
4632 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4633
4634 if (test_bit(__IGB_DOWN, &adapter->state)) {
4635 dev_kfree_skb_any(skb);
4636 return NETDEV_TX_OK;
4637 }
4638
4639 if (skb->len <= 0) {
4640 dev_kfree_skb_any(skb);
4641 return NETDEV_TX_OK;
4642 }
4643
1cc3bd87
AD		 4644 /*
4645 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4646 * in order to meet this minimum size requirement.
4647 */
ea5ceeab
TD		 4648 if (unlikely(skb->len < 17)) {
4649 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4650 return NETDEV_TX_OK;
4651 skb->len = 17;
ea5ceeab 4652 skb_set_tail_pointer(skb, 17);
1cc3bd87 4653 }
9d5c8243 4654
1cc3bd87 4655 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4656}
4657
4658/**
4659 * igb_tx_timeout - Respond to a Tx Hang
4660 * @netdev: network interface device structure
4661 **/
4662static void igb_tx_timeout(struct net_device *netdev)
4663{
4664 struct igb_adapter *adapter = netdev_priv(netdev);
4665 struct e1000_hw *hw = &adapter->hw;
4666
4667 /* Do the reset outside of interrupt context */
4668 adapter->tx_timeout_count++;
f7ba205e 4669
06218a8d 4670 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4671 hw->dev_spec._82575.global_device_reset = true;
4672
9d5c8243 4673 schedule_work(&adapter->reset_task);
265de409
AD		 4674 wr32(E1000_EICS,
4675 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4676}
4677
4678static void igb_reset_task(struct work_struct *work)
4679{
4680 struct igb_adapter *adapter;
4681 adapter = container_of(work, struct igb_adapter, reset_task);
4682
c97ec42a
TI		 4683 igb_dump(adapter);
4684 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4685 igb_reinit_locked(adapter);
4686}
4687
4688/**
12dcd86b 4689 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4690 * @netdev: network interface device structure
12dcd86b 4691 * @stats: rtnl_link_stats64 pointer
9d5c8243 4692 *
9d5c8243 4693 **/
12dcd86b
ED		 4694static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4695 struct rtnl_link_stats64 *stats)
9d5c8243 4696{
12dcd86b
ED		 4697 struct igb_adapter *adapter = netdev_priv(netdev);
4698
4699 spin_lock(&adapter->stats64_lock);
4700 igb_update_stats(adapter, &adapter->stats64);
4701 memcpy(stats, &adapter->stats64, sizeof(*stats));
4702 spin_unlock(&adapter->stats64_lock);
4703
4704 return stats;
9d5c8243
AK		 4705}
4706
4707/**
4708 * igb_change_mtu - Change the Maximum Transfer Unit
4709 * @netdev: network interface device structure
4710 * @new_mtu: new value for maximum frame size
4711 *
4712 * Returns 0 on success, negative on failure
4713 **/
4714static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4715{
4716 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4717 struct pci_dev *pdev = adapter->pdev;
153285f9 4718 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4719
c809d227 4720 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4721 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4722 return -EINVAL;
4723 }
4724
153285f9 4725#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4726 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4727 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4728 return -EINVAL;
4729 }
4730
4731 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4732 msleep(1);
73cd78f1 4733
9d5c8243
AK		 4734 /* igb_down has a dependency on max_frame_size */
4735 adapter->max_frame_size = max_frame;
559e9c49 4736
4c844851
AD		 4737 if (netif_running(netdev))
4738 igb_down(adapter);
9d5c8243 4739
090b1795 4740 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4741 netdev->mtu, new_mtu);
4742 netdev->mtu = new_mtu;
4743
4744 if (netif_running(netdev))
4745 igb_up(adapter);
4746 else
4747 igb_reset(adapter);
4748
4749 clear_bit(__IGB_RESETTING, &adapter->state);
4750
4751 return 0;
4752}
4753
4754/**
4755 * igb_update_stats - Update the board statistics counters
4756 * @adapter: board private structure
4757 **/
4758
12dcd86b
ED		 4759void igb_update_stats(struct igb_adapter *adapter,
4760 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4761{
4762 struct e1000_hw *hw = &adapter->hw;
4763 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4764 u32 reg, mpc;
9d5c8243 4765 u16 phy_tmp;
3f9c0164
AD		 4766 int i;
4767 u64 bytes, packets;
12dcd86b
ED		 4768 unsigned int start;
4769 u64 _bytes, _packets;
9d5c8243
AK		 4770
4771#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4772
4773 /*
4774 * Prevent stats update while adapter is being reset, or if the pci
4775 * connection is down.
4776 */
4777 if (adapter->link_speed == 0)
4778 return;
4779 if (pci_channel_offline(pdev))
4780 return;
4781
3f9c0164
AD		 4782 bytes = 0;
4783 packets = 0;
4784 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4785 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4786 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4787
ae1c07a6
AD		 4788 if (rqdpc) {
4789 ring->rx_stats.drops += rqdpc;
4790 net_stats->rx_fifo_errors += rqdpc;
4791 }
12dcd86b
ED		 4792
4793 do {
4794 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4795 _bytes = ring->rx_stats.bytes;
4796 _packets = ring->rx_stats.packets;
4797 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4798 bytes += _bytes;
4799 packets += _packets;
3f9c0164
AD		 4800 }
4801
128e45eb
AD		 4802 net_stats->rx_bytes = bytes;
4803 net_stats->rx_packets = packets;
3f9c0164
AD		 4804
4805 bytes = 0;
4806 packets = 0;
4807 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4808 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4809 do {
4810 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4811 _bytes = ring->tx_stats.bytes;
4812 _packets = ring->tx_stats.packets;
4813 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4814 bytes += _bytes;
4815 packets += _packets;
3f9c0164 4816 }
128e45eb
AD		 4817 net_stats->tx_bytes = bytes;
4818 net_stats->tx_packets = packets;
3f9c0164
AD		 4819
4820 /* read stats registers */
9d5c8243
AK		 4821 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4822 adapter->stats.gprc += rd32(E1000_GPRC);
4823 adapter->stats.gorc += rd32(E1000_GORCL);
4824 rd32(E1000_GORCH); /* clear GORCL */
4825 adapter->stats.bprc += rd32(E1000_BPRC);
4826 adapter->stats.mprc += rd32(E1000_MPRC);
4827 adapter->stats.roc += rd32(E1000_ROC);
4828
4829 adapter->stats.prc64 += rd32(E1000_PRC64);
4830 adapter->stats.prc127 += rd32(E1000_PRC127);
4831 adapter->stats.prc255 += rd32(E1000_PRC255);
4832 adapter->stats.prc511 += rd32(E1000_PRC511);
4833 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4834 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4835 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4836 adapter->stats.sec += rd32(E1000_SEC);
4837
fa3d9a6d
MW		 4838 mpc = rd32(E1000_MPC);
4839 adapter->stats.mpc += mpc;
4840 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4841 adapter->stats.scc += rd32(E1000_SCC);
4842 adapter->stats.ecol += rd32(E1000_ECOL);
4843 adapter->stats.mcc += rd32(E1000_MCC);
4844 adapter->stats.latecol += rd32(E1000_LATECOL);
4845 adapter->stats.dc += rd32(E1000_DC);
4846 adapter->stats.rlec += rd32(E1000_RLEC);
4847 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4848 adapter->stats.xontxc += rd32(E1000_XONTXC);
4849 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4850 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4851 adapter->stats.fcruc += rd32(E1000_FCRUC);
4852 adapter->stats.gptc += rd32(E1000_GPTC);
4853 adapter->stats.gotc += rd32(E1000_GOTCL);
4854 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4855 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4856 adapter->stats.ruc += rd32(E1000_RUC);
4857 adapter->stats.rfc += rd32(E1000_RFC);
4858 adapter->stats.rjc += rd32(E1000_RJC);
4859 adapter->stats.tor += rd32(E1000_TORH);
4860 adapter->stats.tot += rd32(E1000_TOTH);
4861 adapter->stats.tpr += rd32(E1000_TPR);
4862
4863 adapter->stats.ptc64 += rd32(E1000_PTC64);
4864 adapter->stats.ptc127 += rd32(E1000_PTC127);
4865 adapter->stats.ptc255 += rd32(E1000_PTC255);
4866 adapter->stats.ptc511 += rd32(E1000_PTC511);
4867 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4868 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4869
4870 adapter->stats.mptc += rd32(E1000_MPTC);
4871 adapter->stats.bptc += rd32(E1000_BPTC);
4872
2d0b0f69
NN		 4873 adapter->stats.tpt += rd32(E1000_TPT);
4874 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4875
4876 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4877 /* read internal phy specific stats */
4878 reg = rd32(E1000_CTRL_EXT);
4879 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4880 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4881
4882 /* this stat has invalid values on i210/i211 */
4883 if ((hw->mac.type != e1000_i210) &&
4884 (hw->mac.type != e1000_i211))
4885 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4886 }
4887
9d5c8243
AK		 4888 adapter->stats.tsctc += rd32(E1000_TSCTC);
4889 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4890
4891 adapter->stats.iac += rd32(E1000_IAC);
4892 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4893 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4894 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4895 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4896 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4897 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4898 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4899 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4900
4901 /* Fill out the OS statistics structure */
128e45eb
AD		 4902 net_stats->multicast = adapter->stats.mprc;
4903 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4904
4905 /* Rx Errors */
4906
4907 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4908 * our own version based on RUC and ROC */
128e45eb 4909 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4910 adapter->stats.crcerrs + adapter->stats.algnerrc +
4911 adapter->stats.ruc + adapter->stats.roc +
4912 adapter->stats.cexterr;
128e45eb
AD		 4913 net_stats->rx_length_errors = adapter->stats.ruc +
4914 adapter->stats.roc;
4915 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4916 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4917 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4918
4919 /* Tx Errors */
128e45eb
AD		 4920 net_stats->tx_errors = adapter->stats.ecol +
4921 adapter->stats.latecol;
4922 net_stats->tx_aborted_errors = adapter->stats.ecol;
4923 net_stats->tx_window_errors = adapter->stats.latecol;
4924 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4925
4926 /* Tx Dropped needs to be maintained elsewhere */
4927
4928 /* Phy Stats */
4929 if (hw->phy.media_type == e1000_media_type_copper) {
4930 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4931 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4932 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4933 adapter->phy_stats.idle_errors += phy_tmp;
4934 }
4935 }
4936
4937 /* Management Stats */
4938 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4939 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4940 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4941
4942 /* OS2BMC Stats */
4943 reg = rd32(E1000_MANC);
4944 if (reg & E1000_MANC_EN_BMC2OS) {
4945 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4946 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4947 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4948 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4949 }
9d5c8243
AK		 4950}
4951
9d5c8243
AK		 4952static irqreturn_t igb_msix_other(int irq, void *data)
4953{
047e0030 4954 struct igb_adapter *adapter = data;
9d5c8243 4955 struct e1000_hw *hw = &adapter->hw;
844290e5 4956 u32 icr = rd32(E1000_ICR);
844290e5 4957 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4958
7f081d40
AD		 4959 if (icr & E1000_ICR_DRSTA)
4960 schedule_work(&adapter->reset_task);
4961
047e0030 4962 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4963 /* HW is reporting DMA is out of sync */
4964 adapter->stats.doosync++;
13800469
GR		 4965 /* The DMA Out of Sync is also indication of a spoof event
4966 * in IOV mode. Check the Wrong VM Behavior register to
4967 * see if it is really a spoof event. */
4968 igb_check_wvbr(adapter);
dda0e083 4969 }
eebbbdba 4970
4ae196df
AD		 4971 /* Check for a mailbox event */
4972 if (icr & E1000_ICR_VMMB)
4973 igb_msg_task(adapter);
4974
4975 if (icr & E1000_ICR_LSC) {
4976 hw->mac.get_link_status = 1;
4977 /* guard against interrupt when we're going down */
4978 if (!test_bit(__IGB_DOWN, &adapter->state))
4979 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4980 }
4981
1f6e8178
MV		 4982 if (icr & E1000_ICR_TS) {
4983 u32 tsicr = rd32(E1000_TSICR);
4984
4985 if (tsicr & E1000_TSICR_TXTS) {
4986 /* acknowledge the interrupt */
4987 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4988 /* retrieve hardware timestamp */
4989 schedule_work(&adapter->ptp_tx_work);
4990 }
4991 }
1f6e8178 4992
844290e5 4993 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4994
4995 return IRQ_HANDLED;
4996}
4997
047e0030 4998static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4999{
26b39276 5000 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5001 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5002
047e0030
AD		 5003 if (!q_vector->set_itr)
5004 return;
73cd78f1 5005
047e0030
AD		 5006 if (!itr_val)
5007 itr_val = 0x4;
661086df 5008
26b39276
AD		 5009 if (adapter->hw.mac.type == e1000_82575)
5010 itr_val |= itr_val << 16;
661086df 5011 else
0ba82994 5012 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5013
047e0030
AD		 5014 writel(itr_val, q_vector->itr_register);
5015 q_vector->set_itr = 0;
6eb5a7f1
AD		 5016}
5017
047e0030 5018static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5019{
047e0030 5020 struct igb_q_vector *q_vector = data;
9d5c8243 5021
047e0030
AD		 5022 /* Write the ITR value calculated from the previous interrupt. */
5023 igb_write_itr(q_vector);
9d5c8243 5024
047e0030 5025 napi_schedule(&q_vector->napi);
844290e5 5026
047e0030 5027 return IRQ_HANDLED;
fe4506b6
JC		 5028}
5029
421e02f0 5030#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5031static void igb_update_tx_dca(struct igb_adapter *adapter,
5032 struct igb_ring *tx_ring,
5033 int cpu)
5034{
5035 struct e1000_hw *hw = &adapter->hw;
5036 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5037
5038 if (hw->mac.type != e1000_82575)
5039 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5040
5041 /*
5042 * We can enable relaxed ordering for reads, but not writes when
5043 * DCA is enabled. This is due to a known issue in some chipsets
5044 * which will cause the DCA tag to be cleared.
5045 */
5046 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5047 E1000_DCA_TXCTRL_DATA_RRO_EN |
5048 E1000_DCA_TXCTRL_DESC_DCA_EN;
5049
5050 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5051}
5052
5053static void igb_update_rx_dca(struct igb_adapter *adapter,
5054 struct igb_ring *rx_ring,
5055 int cpu)
5056{
5057 struct e1000_hw *hw = &adapter->hw;
5058 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5059
5060 if (hw->mac.type != e1000_82575)
5061 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5062
5063 /*
5064 * We can enable relaxed ordering for reads, but not writes when
5065 * DCA is enabled. This is due to a known issue in some chipsets
5066 * which will cause the DCA tag to be cleared.
5067 */
5068 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5069 E1000_DCA_RXCTRL_DESC_DCA_EN;
5070
5071 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5072}
5073
047e0030 5074static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5075{
047e0030 5076 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5077 int cpu = get_cpu();
fe4506b6 5078
047e0030
AD		 5079 if (q_vector->cpu == cpu)
5080 goto out_no_update;
5081
6a05004a
AD		 5082 if (q_vector->tx.ring)
5083 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5084
5085 if (q_vector->rx.ring)
5086 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5087
047e0030
AD		 5088 q_vector->cpu = cpu;
5089out_no_update:
fe4506b6
JC		 5090 put_cpu();
5091}
5092
5093static void igb_setup_dca(struct igb_adapter *adapter)
5094{
7e0e99ef 5095 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5096 int i;
5097
7dfc16fa 5098 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5099 return;
5100
7e0e99ef
AD		 5101 /* Always use CB2 mode, difference is masked in the CB driver. */
5102 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5103
047e0030 5104 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5105 adapter->q_vector[i]->cpu = -1;
5106 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5107 }
5108}
5109
5110static int __igb_notify_dca(struct device *dev, void *data)
5111{
5112 struct net_device *netdev = dev_get_drvdata(dev);
5113 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5114 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5115 struct e1000_hw *hw = &adapter->hw;
5116 unsigned long event = *(unsigned long *)data;
5117
5118 switch (event) {
5119 case DCA_PROVIDER_ADD:
5120 /* if already enabled, don't do it again */
7dfc16fa 5121 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5122 break;
fe4506b6 5123 if (dca_add_requester(dev) == 0) {
bbd98fe4 5124 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5125 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5126 igb_setup_dca(adapter);
5127 break;
5128 }
5129 /* Fall Through since DCA is disabled. */
5130 case DCA_PROVIDER_REMOVE:
7dfc16fa 5131 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5132 /* without this a class_device is left
047e0030 5133 * hanging around in the sysfs model */
fe4506b6 5134 dca_remove_requester(dev);
090b1795 5135 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5136 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5137 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5138 }
5139 break;
5140 }
bbd98fe4 5141
fe4506b6 5142 return 0;
9d5c8243
AK		 5143}
5144
fe4506b6
JC		 5145static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5146 void *p)
5147{
5148 int ret_val;
5149
5150 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5151 __igb_notify_dca);
5152
5153 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5154}
421e02f0 5155#endif /* CONFIG_IGB_DCA */
9d5c8243 5156
0224d663
GR		 5157#ifdef CONFIG_PCI_IOV
5158static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5159{
5160 unsigned char mac_addr[ETH_ALEN];
0224d663 5161
7efd26d0 5162 eth_random_addr(mac_addr);
0224d663
GR		 5163 igb_set_vf_mac(adapter, vf, mac_addr);
5164
f557147c 5165 return 0;
0224d663
GR		 5166}
5167
f557147c 5168static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 5169{
0224d663 5170 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 5171 struct pci_dev *vfdev;
5172 int dev_id;
0224d663
GR		 5173
5174 switch (adapter->hw.mac.type) {
5175 case e1000_82576:
f557147c 5176 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 5177 break;
5178 case e1000_i350:
f557147c 5179 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 5180 break;
5181 default:
f557147c 5182 return false;
0224d663
GR		 5183 }
5184
f557147c
SA		 5185 /* loop through all the VFs to see if we own any that are assigned */
5186 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5187 while (vfdev) {
5188 /* if we don't own it we don't care */
5189 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5190 /* if it is assigned we cannot release it */
5191 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5192 return true;
5193 }
f557147c
SA		 5194
5195 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5196 }
f557147c 5197
0224d663
GR		 5198 return false;
5199}
5200
5201#endif
4ae196df
AD		 5202static void igb_ping_all_vfs(struct igb_adapter *adapter)
5203{
5204 struct e1000_hw *hw = &adapter->hw;
5205 u32 ping;
5206 int i;
5207
5208 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5209 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5210 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5211 ping |= E1000_VT_MSGTYPE_CTS;
5212 igb_write_mbx(hw, &ping, 1, i);
5213 }
5214}
5215
7d5753f0
AD		 5216static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5217{
5218 struct e1000_hw *hw = &adapter->hw;
5219 u32 vmolr = rd32(E1000_VMOLR(vf));
5220 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5221
d85b9004 5222 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5223 IGB_VF_FLAG_MULTI_PROMISC);
5224 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5225
5226 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5227 vmolr |= E1000_VMOLR_MPME;
d85b9004 5228 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5229 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5230 } else {
5231 /*
5232 * if we have hashes and we are clearing a multicast promisc
5233 * flag we need to write the hashes to the MTA as this step
5234 * was previously skipped
5235 */
5236 if (vf_data->num_vf_mc_hashes > 30) {
5237 vmolr |= E1000_VMOLR_MPME;
5238 } else if (vf_data->num_vf_mc_hashes) {
5239 int j;
5240 vmolr |= E1000_VMOLR_ROMPE;
5241 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5242 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5243 }
5244 }
5245
5246 wr32(E1000_VMOLR(vf), vmolr);
5247
5248 /* there are flags left unprocessed, likely not supported */
5249 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5250 return -EINVAL;
5251
5252 return 0;
5253
5254}
5255
4ae196df
AD		 5256static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5257 u32 *msgbuf, u32 vf)
5258{
5259 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5260 u16 *hash_list = (u16 *)&msgbuf[1];
5261 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5262 int i;
5263
7d5753f0 5264 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5265 * to this VF for later use to restore when the PF multi cast
5266 * list changes
5267 */
5268 vf_data->num_vf_mc_hashes = n;
5269
7d5753f0
AD		 5270 /* only up to 30 hash values supported */
5271 if (n > 30)
5272 n = 30;
5273
5274 /* store the hashes for later use */
4ae196df 5275 for (i = 0; i < n; i++)
a419aef8 5276 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5277
5278 /* Flush and reset the mta with the new values */
ff41f8dc 5279 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5280
5281 return 0;
5282}
5283
5284static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5285{
5286 struct e1000_hw *hw = &adapter->hw;
5287 struct vf_data_storage *vf_data;
5288 int i, j;
5289
5290 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5291 u32 vmolr = rd32(E1000_VMOLR(i));
5292 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5293
4ae196df 5294 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5295
5296 if ((vf_data->num_vf_mc_hashes > 30) ||
5297 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5298 vmolr |= E1000_VMOLR_MPME;
5299 } else if (vf_data->num_vf_mc_hashes) {
5300 vmolr |= E1000_VMOLR_ROMPE;
5301 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5302 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5303 }
5304 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5305 }
5306}
5307
5308static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5309{
5310 struct e1000_hw *hw = &adapter->hw;
5311 u32 pool_mask, reg, vid;
5312 int i;
5313
5314 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5315
5316 /* Find the vlan filter for this id */
5317 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5318 reg = rd32(E1000_VLVF(i));
5319
5320 /* remove the vf from the pool */
5321 reg &= ~pool_mask;
5322
5323 /* if pool is empty then remove entry from vfta */
5324 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5325 (reg & E1000_VLVF_VLANID_ENABLE)) {
5326 reg = 0;
5327 vid = reg & E1000_VLVF_VLANID_MASK;
5328 igb_vfta_set(hw, vid, false);
5329 }
5330
5331 wr32(E1000_VLVF(i), reg);
5332 }
ae641bdc
AD		 5333
5334 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5335}
5336
5337static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5338{
5339 struct e1000_hw *hw = &adapter->hw;
5340 u32 reg, i;
5341
51466239
AD		 5342 /* The vlvf table only exists on 82576 hardware and newer */
5343 if (hw->mac.type < e1000_82576)
5344 return -1;
5345
5346 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5347 if (!adapter->vfs_allocated_count)
5348 return -1;
5349
5350 /* Find the vlan filter for this id */
5351 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5352 reg = rd32(E1000_VLVF(i));
5353 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5354 vid == (reg & E1000_VLVF_VLANID_MASK))
5355 break;
5356 }
5357
5358 if (add) {
5359 if (i == E1000_VLVF_ARRAY_SIZE) {
5360 /* Did not find a matching VLAN ID entry that was
5361 * enabled. Search for a free filter entry, i.e.
5362 * one without the enable bit set
5363 */
5364 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5365 reg = rd32(E1000_VLVF(i));
5366 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5367 break;
5368 }
5369 }
5370 if (i < E1000_VLVF_ARRAY_SIZE) {
5371 /* Found an enabled/available entry */
5372 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5373
5374 /* if !enabled we need to set this up in vfta */
5375 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5376 /* add VID to filter table */
5377 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5378 reg |= E1000_VLVF_VLANID_ENABLE;
5379 }
cad6d05f
AD		 5380 reg &= ~E1000_VLVF_VLANID_MASK;
5381 reg |= vid;
4ae196df 5382 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5383
5384 /* do not modify RLPML for PF devices */
5385 if (vf >= adapter->vfs_allocated_count)
5386 return 0;
5387
5388 if (!adapter->vf_data[vf].vlans_enabled) {
5389 u32 size;
5390 reg = rd32(E1000_VMOLR(vf));
5391 size = reg & E1000_VMOLR_RLPML_MASK;
5392 size += 4;
5393 reg &= ~E1000_VMOLR_RLPML_MASK;
5394 reg |= size;
5395 wr32(E1000_VMOLR(vf), reg);
5396 }
ae641bdc 5397
51466239 5398 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5399 }
5400 } else {
5401 if (i < E1000_VLVF_ARRAY_SIZE) {
5402 /* remove vf from the pool */
5403 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5404 /* if pool is empty then remove entry from vfta */
5405 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5406 reg = 0;
5407 igb_vfta_set(hw, vid, false);
5408 }
5409 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5410
5411 /* do not modify RLPML for PF devices */
5412 if (vf >= adapter->vfs_allocated_count)
5413 return 0;
5414
5415 adapter->vf_data[vf].vlans_enabled--;
5416 if (!adapter->vf_data[vf].vlans_enabled) {
5417 u32 size;
5418 reg = rd32(E1000_VMOLR(vf));
5419 size = reg & E1000_VMOLR_RLPML_MASK;
5420 size -= 4;
5421 reg &= ~E1000_VMOLR_RLPML_MASK;
5422 reg |= size;
5423 wr32(E1000_VMOLR(vf), reg);
5424 }
4ae196df
AD		 5425 }
5426 }
8151d294
WM		 5427 return 0;
5428}
5429
5430static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5431{
5432 struct e1000_hw *hw = &adapter->hw;
5433
5434 if (vid)
5435 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5436 else
5437 wr32(E1000_VMVIR(vf), 0);
5438}
5439
5440static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5441 int vf, u16 vlan, u8 qos)
5442{
5443 int err = 0;
5444 struct igb_adapter *adapter = netdev_priv(netdev);
5445
5446 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5447 return -EINVAL;
5448 if (vlan || qos) {
5449 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5450 if (err)
5451 goto out;
5452 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5453 igb_set_vmolr(adapter, vf, !vlan);
5454 adapter->vf_data[vf].pf_vlan = vlan;
5455 adapter->vf_data[vf].pf_qos = qos;
5456 dev_info(&adapter->pdev->dev,
5457 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5458 if (test_bit(__IGB_DOWN, &adapter->state)) {
5459 dev_warn(&adapter->pdev->dev,
5460 "The VF VLAN has been set,"
5461 " but the PF device is not up.\n");
5462 dev_warn(&adapter->pdev->dev,
5463 "Bring the PF device up before"
5464 " attempting to use the VF device.\n");
5465 }
5466 } else {
5467 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5468 false, vf);
5469 igb_set_vmvir(adapter, vlan, vf);
5470 igb_set_vmolr(adapter, vf, true);
5471 adapter->vf_data[vf].pf_vlan = 0;
5472 adapter->vf_data[vf].pf_qos = 0;
5473 }
5474out:
5475 return err;
4ae196df
AD		 5476}
5477
5478static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5479{
5480 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5481 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5482
5483 return igb_vlvf_set(adapter, vid, add, vf);
5484}
5485
f2ca0dbe 5486static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5487{
8fa7e0f7
GR		 5488 /* clear flags - except flag that indicates PF has set the MAC */
5489 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5490 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5491
5492 /* reset offloads to defaults */
8151d294 5493 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5494
5495 /* reset vlans for device */
5496 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5497 if (adapter->vf_data[vf].pf_vlan)
5498 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5499 adapter->vf_data[vf].pf_vlan,
5500 adapter->vf_data[vf].pf_qos);
5501 else
5502 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5503
5504 /* reset multicast table array for vf */
5505 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5506
5507 /* Flush and reset the mta with the new values */
ff41f8dc 5508 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5509}
5510
f2ca0dbe
AD		 5511static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5512{
5513 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5514
5515 /* generate a new mac address as we were hotplug removed/added */
8151d294 5516 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5517 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5518
5519 /* process remaining reset events */
5520 igb_vf_reset(adapter, vf);
5521}
5522
5523static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5524{
5525 struct e1000_hw *hw = &adapter->hw;
5526 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5527 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5528 u32 reg, msgbuf[3];
5529 u8 *addr = (u8 *)(&msgbuf[1]);
5530
5531 /* process all the same items cleared in a function level reset */
f2ca0dbe 5532 igb_vf_reset(adapter, vf);
4ae196df
AD		 5533
5534 /* set vf mac address */
26ad9178 5535 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5536
5537 /* enable transmit and receive for vf */
5538 reg = rd32(E1000_VFTE);
5539 wr32(E1000_VFTE, reg | (1 << vf));
5540 reg = rd32(E1000_VFRE);
5541 wr32(E1000_VFRE, reg | (1 << vf));
5542
8fa7e0f7 5543 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5544
5545 /* reply to reset with ack and vf mac address */
5546 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5547 memcpy(addr, vf_mac, 6);
5548 igb_write_mbx(hw, msgbuf, 3, vf);
5549}
5550
5551static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5552{
de42edde
GR		 5553 /*
5554 * The VF MAC Address is stored in a packed array of bytes
5555 * starting at the second 32 bit word of the msg array
5556 */
f2ca0dbe
AD		 5557 unsigned char *addr = (char *)&msg[1];
5558 int err = -1;
4ae196df 5559
f2ca0dbe
AD		 5560 if (is_valid_ether_addr(addr))
5561 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5562
f2ca0dbe 5563 return err;
4ae196df
AD		 5564}
5565
5566static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5567{
5568 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5569 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5570 u32 msg = E1000_VT_MSGTYPE_NACK;
5571
5572 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5573 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5574 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5575 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5576 vf_data->last_nack = jiffies;
4ae196df
AD		 5577 }
5578}
5579
f2ca0dbe 5580static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5581{
f2ca0dbe
AD		 5582 struct pci_dev *pdev = adapter->pdev;
5583 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5584 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5585 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5586 s32 retval;
5587
f2ca0dbe 5588 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5589
fef45f4c
AD		 5590 if (retval) {
5591 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5592 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5593 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5594 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5595 return;
5596 goto out;
5597 }
4ae196df
AD		 5598
5599 /* this is a message we already processed, do nothing */
5600 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5601 return;
4ae196df
AD		 5602
5603 /*
5604 * until the vf completes a reset it should not be
5605 * allowed to start any configuration.
5606 */
5607
5608 if (msgbuf[0] == E1000_VF_RESET) {
5609 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5610 return;
4ae196df
AD		 5611 }
5612
f2ca0dbe 5613 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5614 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5615 return;
5616 retval = -1;
5617 goto out;
4ae196df
AD		 5618 }
5619
5620 switch ((msgbuf[0] & 0xFFFF)) {
5621 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5622 retval = -EINVAL;
5623 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5624 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5625 else
5626 dev_warn(&pdev->dev,
5627 "VF %d attempted to override administratively "
5628 "set MAC address\nReload the VF driver to "
5629 "resume operations\n", vf);
4ae196df 5630 break;
7d5753f0
AD		 5631 case E1000_VF_SET_PROMISC:
5632 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5633 break;
4ae196df
AD		 5634 case E1000_VF_SET_MULTICAST:
5635 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5636 break;
5637 case E1000_VF_SET_LPE:
5638 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5639 break;
5640 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5641 retval = -1;
5642 if (vf_data->pf_vlan)
5643 dev_warn(&pdev->dev,
5644 "VF %d attempted to override administratively "
5645 "set VLAN tag\nReload the VF driver to "
5646 "resume operations\n", vf);
8151d294
WM		 5647 else
5648 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5649 break;
5650 default:
090b1795 5651 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5652 retval = -1;
5653 break;
5654 }
5655
fef45f4c
AD		 5656 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5657out:
4ae196df
AD		 5658 /* notify the VF of the results of what it sent us */
5659 if (retval)
5660 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5661 else
5662 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5663
4ae196df 5664 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5665}
4ae196df 5666
f2ca0dbe
AD		 5667static void igb_msg_task(struct igb_adapter *adapter)
5668{
5669 struct e1000_hw *hw = &adapter->hw;
5670 u32 vf;
5671
5672 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5673 /* process any reset requests */
5674 if (!igb_check_for_rst(hw, vf))
5675 igb_vf_reset_event(adapter, vf);
5676
5677 /* process any messages pending */
5678 if (!igb_check_for_msg(hw, vf))
5679 igb_rcv_msg_from_vf(adapter, vf);
5680
5681 /* process any acks */
5682 if (!igb_check_for_ack(hw, vf))
5683 igb_rcv_ack_from_vf(adapter, vf);
5684 }
4ae196df
AD		 5685}
5686
68d480c4
AD		 5687/**
5688 * igb_set_uta - Set unicast filter table address
5689 * @adapter: board private structure
5690 *
5691 * The unicast table address is a register array of 32-bit registers.
5692 * The table is meant to be used in a way similar to how the MTA is used
5693 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5694 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5695 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5696 **/
5697static void igb_set_uta(struct igb_adapter *adapter)
5698{
5699 struct e1000_hw *hw = &adapter->hw;
5700 int i;
5701
5702 /* The UTA table only exists on 82576 hardware and newer */
5703 if (hw->mac.type < e1000_82576)
5704 return;
5705
5706 /* we only need to do this if VMDq is enabled */
5707 if (!adapter->vfs_allocated_count)
5708 return;
5709
5710 for (i = 0; i < hw->mac.uta_reg_count; i++)
5711 array_wr32(E1000_UTA, i, ~0);
5712}
5713
9d5c8243
AK		 5714/**
5715 * igb_intr_msi - Interrupt Handler
5716 * @irq: interrupt number
5717 * @data: pointer to a network interface device structure
5718 **/
5719static irqreturn_t igb_intr_msi(int irq, void *data)
5720{
047e0030
AD		 5721 struct igb_adapter *adapter = data;
5722 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5723 struct e1000_hw *hw = &adapter->hw;
5724 /* read ICR disables interrupts using IAM */
5725 u32 icr = rd32(E1000_ICR);
5726
047e0030 5727 igb_write_itr(q_vector);
9d5c8243 5728
7f081d40
AD		 5729 if (icr & E1000_ICR_DRSTA)
5730 schedule_work(&adapter->reset_task);
5731
047e0030 5732 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5733 /* HW is reporting DMA is out of sync */
5734 adapter->stats.doosync++;
5735 }
5736
9d5c8243
AK		 5737 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5738 hw->mac.get_link_status = 1;
5739 if (!test_bit(__IGB_DOWN, &adapter->state))
5740 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5741 }
5742
1f6e8178
MV		 5743 if (icr & E1000_ICR_TS) {
5744 u32 tsicr = rd32(E1000_TSICR);
5745
5746 if (tsicr & E1000_TSICR_TXTS) {
5747 /* acknowledge the interrupt */
5748 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5749 /* retrieve hardware timestamp */
5750 schedule_work(&adapter->ptp_tx_work);
5751 }
5752 }
1f6e8178 5753
047e0030 5754 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5755
5756 return IRQ_HANDLED;
5757}
5758
5759/**
4a3c6433 5760 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5761 * @irq: interrupt number
5762 * @data: pointer to a network interface device structure
5763 **/
5764static irqreturn_t igb_intr(int irq, void *data)
5765{
047e0030
AD		 5766 struct igb_adapter *adapter = data;
5767 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5768 struct e1000_hw *hw = &adapter->hw;
5769 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5770 * need for the IMC write */
5771 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5772
5773 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5774 * not set, then the adapter didn't send an interrupt */
5775 if (!(icr & E1000_ICR_INT_ASSERTED))
5776 return IRQ_NONE;
5777
0ba82994
AD		 5778 igb_write_itr(q_vector);
5779
7f081d40
AD		 5780 if (icr & E1000_ICR_DRSTA)
5781 schedule_work(&adapter->reset_task);
5782
047e0030 5783 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5784 /* HW is reporting DMA is out of sync */
5785 adapter->stats.doosync++;
5786 }
5787
9d5c8243
AK		 5788 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5789 hw->mac.get_link_status = 1;
5790 /* guard against interrupt when we're going down */
5791 if (!test_bit(__IGB_DOWN, &adapter->state))
5792 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5793 }
5794
1f6e8178
MV		 5795 if (icr & E1000_ICR_TS) {
5796 u32 tsicr = rd32(E1000_TSICR);
5797
5798 if (tsicr & E1000_TSICR_TXTS) {
5799 /* acknowledge the interrupt */
5800 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5801 /* retrieve hardware timestamp */
5802 schedule_work(&adapter->ptp_tx_work);
5803 }
5804 }
1f6e8178 5805
047e0030 5806 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5807
5808 return IRQ_HANDLED;
5809}
5810
c50b52a0 5811static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5812{
047e0030 5813 struct igb_adapter *adapter = q_vector->adapter;
46544258 5814 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5815
0ba82994
AD		 5816 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5817 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5818 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5819 igb_set_itr(q_vector);
46544258 5820 else
047e0030 5821 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5822 }
5823
46544258
AD		 5824 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5825 if (adapter->msix_entries)
047e0030 5826 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5827 else
5828 igb_irq_enable(adapter);
5829 }
9d5c8243
AK		 5830}
5831
46544258
AD		 5832/**
5833 * igb_poll - NAPI Rx polling callback
5834 * @napi: napi polling structure
5835 * @budget: count of how many packets we should handle
5836 **/
5837static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5838{
047e0030
AD		 5839 struct igb_q_vector *q_vector = container_of(napi,
5840 struct igb_q_vector,
5841 napi);
16eb8815 5842 bool clean_complete = true;
9d5c8243 5843
421e02f0 5844#ifdef CONFIG_IGB_DCA
047e0030
AD		 5845 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5846 igb_update_dca(q_vector);
fe4506b6 5847#endif
0ba82994 5848 if (q_vector->tx.ring)
13fde97a 5849 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5850
0ba82994 5851 if (q_vector->rx.ring)
cd392f5c 5852 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5853
16eb8815
AD		 5854 /* If all work not completed, return budget and keep polling */
5855 if (!clean_complete)
5856 return budget;
46544258 5857
9d5c8243 5858 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5859 napi_complete(napi);
5860 igb_ring_irq_enable(q_vector);
9d5c8243 5861
16eb8815 5862 return 0;
9d5c8243 5863}
6d8126f9 5864
9d5c8243
AK		 5865/**
5866 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5867 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5868 *
9d5c8243
AK		 5869 * returns true if ring is completely cleaned
5870 **/
047e0030 5871static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5872{
047e0030 5873 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5874 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5875 struct igb_tx_buffer *tx_buffer;
f4128785 5876 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5877 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5878 unsigned int budget = q_vector->tx.work_limit;
8542db05 5879 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5880
13fde97a
AD		 5881 if (test_bit(__IGB_DOWN, &adapter->state))
5882 return true;
0e014cb1 5883
06034649 5884 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5885 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5886 i -= tx_ring->count;
9d5c8243 5887
f4128785
AD		 5888 do {
5889 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5890
5891 /* if next_to_watch is not set then there is no work pending */
5892 if (!eop_desc)
5893 break;
13fde97a 5894
f4128785
AD		 5895 /* prevent any other reads prior to eop_desc */
5896 rmb();
5897
13fde97a
AD		 5898 /* if DD is not set pending work has not been completed */
5899 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5900 break;
5901
8542db05
AD		 5902 /* clear next_to_watch to prevent false hangs */
5903 tx_buffer->next_to_watch = NULL;
9d5c8243 5904
ebe42d16
AD		 5905 /* update the statistics for this packet */
5906 total_bytes += tx_buffer->bytecount;
5907 total_packets += tx_buffer->gso_segs;
13fde97a 5908
ebe42d16
AD		 5909 /* free the skb */
5910 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5911
ebe42d16
AD		 5912 /* unmap skb header data */
5913 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5914 dma_unmap_addr(tx_buffer, dma),
5915 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5916 DMA_TO_DEVICE);
5917
c9f14bf3
AD		 5918 /* clear tx_buffer data */
5919 tx_buffer->skb = NULL;
5920 dma_unmap_len_set(tx_buffer, len, 0);
5921
ebe42d16
AD		 5922 /* clear last DMA location and unmap remaining buffers */
5923 while (tx_desc != eop_desc) {
13fde97a
AD		 5924 tx_buffer++;
5925 tx_desc++;
9d5c8243 5926 i++;
8542db05
AD		 5927 if (unlikely(!i)) {
5928 i -= tx_ring->count;
06034649 5929 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5930 tx_desc = IGB_TX_DESC(tx_ring, 0);
5931 }
ebe42d16
AD		 5932
5933 /* unmap any remaining paged data */
c9f14bf3 5934 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5935 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5936 dma_unmap_addr(tx_buffer, dma),
5937 dma_unmap_len(tx_buffer, len),
ebe42d16 5938 DMA_TO_DEVICE);
c9f14bf3 5939 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5940 }
5941 }
5942
ebe42d16
AD		 5943 /* move us one more past the eop_desc for start of next pkt */
5944 tx_buffer++;
5945 tx_desc++;
5946 i++;
5947 if (unlikely(!i)) {
5948 i -= tx_ring->count;
5949 tx_buffer = tx_ring->tx_buffer_info;
5950 tx_desc = IGB_TX_DESC(tx_ring, 0);
5951 }
f4128785
AD		 5952
5953 /* issue prefetch for next Tx descriptor */
5954 prefetch(tx_desc);
5955
5956 /* update budget accounting */
5957 budget--;
5958 } while (likely(budget));
0e014cb1 5959
bdbc0631
ED		 5960 netdev_tx_completed_queue(txring_txq(tx_ring),
5961 total_packets, total_bytes);
8542db05 5962 i += tx_ring->count;
9d5c8243 5963 tx_ring->next_to_clean = i;
13fde97a
AD		 5964 u64_stats_update_begin(&tx_ring->tx_syncp);
5965 tx_ring->tx_stats.bytes += total_bytes;
5966 tx_ring->tx_stats.packets += total_packets;
5967 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5968 q_vector->tx.total_bytes += total_bytes;
5969 q_vector->tx.total_packets += total_packets;
9d5c8243 5970
6d095fa8 5971 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5972 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5973
9d5c8243
AK		 5974 /* Detect a transmit hang in hardware, this serializes the
5975 * check with the clearing of time_stamp and movement of i */
6d095fa8 5976 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 5977 if (tx_buffer->next_to_watch &&
8542db05 5978 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5979 (adapter->tx_timeout_factor * HZ)) &&
5980 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5981
9d5c8243 5982 /* detected Tx unit hang */
59d71989 5983 dev_err(tx_ring->dev,
9d5c8243 5984 "Detected Tx Unit Hang\n"
2d064c06 5985 " Tx Queue <%d>\n"
9d5c8243
AK		 5986 " TDH <%x>\n"
5987 " TDT <%x>\n"
5988 " next_to_use <%x>\n"
5989 " next_to_clean <%x>\n"
9d5c8243
AK		 5990 "buffer_info[next_to_clean]\n"
5991 " time_stamp <%lx>\n"
8542db05 5992 " next_to_watch <%p>\n"
9d5c8243
AK		 5993 " jiffies <%lx>\n"
5994 " desc.status <%x>\n",
2d064c06 5995 tx_ring->queue_index,
238ac817 5996 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5997 readl(tx_ring->tail),
9d5c8243
AK		 5998 tx_ring->next_to_use,
5999 tx_ring->next_to_clean,
8542db05 6000 tx_buffer->time_stamp,
f4128785 6001 tx_buffer->next_to_watch,
9d5c8243 6002 jiffies,
f4128785 6003 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6004 netif_stop_subqueue(tx_ring->netdev,
6005 tx_ring->queue_index);
6006
6007 /* we are about to reset, no point in enabling stuff */
6008 return true;
9d5c8243
AK		 6009 }
6010 }
13fde97a
AD		 6011
6012 if (unlikely(total_packets &&
6013 netif_carrier_ok(tx_ring->netdev) &&
6014 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
6015 /* Make sure that anybody stopping the queue after this
6016 * sees the new next_to_clean.
6017 */
6018 smp_mb();
6019 if (__netif_subqueue_stopped(tx_ring->netdev,
6020 tx_ring->queue_index) &&
6021 !(test_bit(__IGB_DOWN, &adapter->state))) {
6022 netif_wake_subqueue(tx_ring->netdev,
6023 tx_ring->queue_index);
6024
6025 u64_stats_update_begin(&tx_ring->tx_syncp);
6026 tx_ring->tx_stats.restart_queue++;
6027 u64_stats_update_end(&tx_ring->tx_syncp);
6028 }
6029 }
6030
6031 return !!budget;
9d5c8243
AK		 6032}
6033
cbc8e55f
AD		 6034/**
6035 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6036 * @rx_ring: rx descriptor ring to store buffers on
6037 * @old_buff: donor buffer to have page reused
6038 *
6039 * Synchronizes page for reuse by the adapter
6040 **/
6041static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6042 struct igb_rx_buffer *old_buff)
6043{
6044 struct igb_rx_buffer *new_buff;
6045 u16 nta = rx_ring->next_to_alloc;
6046
6047 new_buff = &rx_ring->rx_buffer_info[nta];
6048
6049 /* update, and store next to alloc */
6050 nta++;
6051 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6052
6053 /* transfer page from old buffer to new buffer */
6054 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6055
6056 /* sync the buffer for use by the device */
6057 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6058 old_buff->page_offset,
de78d1f9 6059 IGB_RX_BUFSZ,
cbc8e55f
AD		 6060 DMA_FROM_DEVICE);
6061}
6062
6063/**
6064 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6065 * @rx_ring: rx descriptor ring to transact packets on
6066 * @rx_buffer: buffer containing page to add
6067 * @rx_desc: descriptor containing length of buffer written by hardware
6068 * @skb: sk_buff to place the data into
6069 *
6070 * This function will add the data contained in rx_buffer->page to the skb.
6071 * This is done either through a direct copy if the data in the buffer is
6072 * less than the skb header size, otherwise it will just attach the page as
6073 * a frag to the skb.
6074 *
6075 * The function will then update the page offset if necessary and return
6076 * true if the buffer can be reused by the adapter.
6077 **/
6078static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6079 struct igb_rx_buffer *rx_buffer,
6080 union e1000_adv_rx_desc *rx_desc,
6081 struct sk_buff *skb)
6082{
6083 struct page *page = rx_buffer->page;
6084 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6085
6086 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6087 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6088
cbc8e55f
AD		 6089 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6090 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6091 va += IGB_TS_HDR_LEN;
6092 size -= IGB_TS_HDR_LEN;
6093 }
6094
cbc8e55f
AD		 6095 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6096
6097 /* we can reuse buffer as-is, just make sure it is local */
6098 if (likely(page_to_nid(page) == numa_node_id()))
6099 return true;
6100
6101 /* this page cannot be reused so discard it */
6102 put_page(page);
6103 return false;
6104 }
6105
6106 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 6107 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 6108
6109 /* avoid re-using remote pages */
6110 if (unlikely(page_to_nid(page) != numa_node_id()))
6111 return false;
6112
de78d1f9 6113#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 6114 /* if we are only owner of page we can reuse it */
6115 if (unlikely(page_count(page) != 1))
6116 return false;
6117
6118 /* flip page offset to other buffer */
de78d1f9 6119 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 6120
6121 /*
6122 * since we are the only owner of the page and we need to
6123 * increment it, just set the value to 2 in order to avoid
6124 * an unnecessary locked operation
6125 */
6126 atomic_set(&page->_count, 2);
de78d1f9
AD		 6127#else
6128 /* move offset up to the next cache line */
6129 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
6130
6131 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6132 return false;
6133
6134 /* bump ref count on page before it is given to the stack */
6135 get_page(page);
6136#endif
cbc8e55f
AD		 6137
6138 return true;
6139}
6140
2e334eee
AD		 6141static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6142 union e1000_adv_rx_desc *rx_desc,
6143 struct sk_buff *skb)
6144{
6145 struct igb_rx_buffer *rx_buffer;
6146 struct page *page;
6147
6148 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6149
6150 /*
6151 * This memory barrier is needed to keep us from reading
6152 * any other fields out of the rx_desc until we know the
6153 * RXD_STAT_DD bit is set
6154 */
6155 rmb();
6156
6157 page = rx_buffer->page;
6158 prefetchw(page);
6159
6160 if (likely(!skb)) {
6161 void *page_addr = page_address(page) +
6162 rx_buffer->page_offset;
6163
6164 /* prefetch first cache line of first page */
6165 prefetch(page_addr);
6166#if L1_CACHE_BYTES < 128
6167 prefetch(page_addr + L1_CACHE_BYTES);
6168#endif
6169
6170 /* allocate a skb to store the frags */
6171 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6172 IGB_RX_HDR_LEN);
6173 if (unlikely(!skb)) {
6174 rx_ring->rx_stats.alloc_failed++;
6175 return NULL;
6176 }
6177
6178 /*
6179 * we will be copying header into skb->data in
6180 * pskb_may_pull so it is in our interest to prefetch
6181 * it now to avoid a possible cache miss
6182 */
6183 prefetchw(skb->data);
6184 }
6185
6186 /* we are reusing so sync this buffer for CPU use */
6187 dma_sync_single_range_for_cpu(rx_ring->dev,
6188 rx_buffer->dma,
6189 rx_buffer->page_offset,
de78d1f9 6190 IGB_RX_BUFSZ,
2e334eee
AD		 6191 DMA_FROM_DEVICE);
6192
6193 /* pull page into skb */
6194 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6195 /* hand second half of page back to the ring */
6196 igb_reuse_rx_page(rx_ring, rx_buffer);
6197 } else {
6198 /* we are not reusing the buffer so unmap it */
6199 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6200 PAGE_SIZE, DMA_FROM_DEVICE);
6201 }
6202
6203 /* clear contents of rx_buffer */
6204 rx_buffer->page = NULL;
6205
6206 return skb;
6207}
6208
cd392f5c 6209static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6210 union e1000_adv_rx_desc *rx_desc,
6211 struct sk_buff *skb)
9d5c8243 6212{
bc8acf2c 6213 skb_checksum_none_assert(skb);
9d5c8243 6214
294e7d78 6215 /* Ignore Checksum bit is set */
3ceb90fd 6216 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6217 return;
6218
6219 /* Rx checksum disabled via ethtool */
6220 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6221 return;
85ad76b2 6222
9d5c8243 6223 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6224 if (igb_test_staterr(rx_desc,
6225 E1000_RXDEXT_STATERR_TCPE |
6226 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6227 /*
6228 * work around errata with sctp packets where the TCPE aka
6229 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6230 * packets, (aka let the stack check the crc32c)
6231 */
866cff06
AD		 6232 if (!((skb->len == 60) &&
6233 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6234 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6235 ring->rx_stats.csum_err++;
12dcd86b
ED		 6236 u64_stats_update_end(&ring->rx_syncp);
6237 }
9d5c8243 6238 /* let the stack verify checksum errors */
9d5c8243
AK		 6239 return;
6240 }
6241 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6242 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6243 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6244 skb->ip_summed = CHECKSUM_UNNECESSARY;
6245
3ceb90fd
AD		 6246 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6247 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6248}
6249
077887c3
AD		 6250static inline void igb_rx_hash(struct igb_ring *ring,
6251 union e1000_adv_rx_desc *rx_desc,
6252 struct sk_buff *skb)
6253{
6254 if (ring->netdev->features & NETIF_F_RXHASH)
6255 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6256}
6257
2e334eee
AD		 6258/**
6259 * igb_is_non_eop - process handling of non-EOP buffers
6260 * @rx_ring: Rx ring being processed
6261 * @rx_desc: Rx descriptor for current buffer
6262 * @skb: current socket buffer containing buffer in progress
6263 *
6264 * This function updates next to clean. If the buffer is an EOP buffer
6265 * this function exits returning false, otherwise it will place the
6266 * sk_buff in the next buffer to be chained and return true indicating
6267 * that this is in fact a non-EOP buffer.
6268 **/
6269static bool igb_is_non_eop(struct igb_ring *rx_ring,
6270 union e1000_adv_rx_desc *rx_desc)
6271{
6272 u32 ntc = rx_ring->next_to_clean + 1;
6273
6274 /* fetch, update, and store next to clean */
6275 ntc = (ntc < rx_ring->count) ? ntc : 0;
6276 rx_ring->next_to_clean = ntc;
6277
6278 prefetch(IGB_RX_DESC(rx_ring, ntc));
6279
6280 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6281 return false;
6282
6283 return true;
6284}
6285
1a1c225b
AD		 6286/**
6287 * igb_get_headlen - determine size of header for LRO/GRO
6288 * @data: pointer to the start of the headers
6289 * @max_len: total length of section to find headers in
6290 *
6291 * This function is meant to determine the length of headers that will
6292 * be recognized by hardware for LRO, and GRO offloads. The main
6293 * motivation of doing this is to only perform one pull for IPv4 TCP
6294 * packets so that we can do basic things like calculating the gso_size
6295 * based on the average data per packet.
6296 **/
6297static unsigned int igb_get_headlen(unsigned char *data,
6298 unsigned int max_len)
6299{
6300 union {
6301 unsigned char *network;
6302 /* l2 headers */
6303 struct ethhdr *eth;
6304 struct vlan_hdr *vlan;
6305 /* l3 headers */
6306 struct iphdr *ipv4;
6307 struct ipv6hdr *ipv6;
6308 } hdr;
6309 __be16 protocol;
6310 u8 nexthdr = 0; /* default to not TCP */
6311 u8 hlen;
6312
6313 /* this should never happen, but better safe than sorry */
6314 if (max_len < ETH_HLEN)
6315 return max_len;
6316
6317 /* initialize network frame pointer */
6318 hdr.network = data;
6319
6320 /* set first protocol and move network header forward */
6321 protocol = hdr.eth->h_proto;
6322 hdr.network += ETH_HLEN;
6323
6324 /* handle any vlan tag if present */
6325 if (protocol == __constant_htons(ETH_P_8021Q)) {
6326 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6327 return max_len;
6328
6329 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6330 hdr.network += VLAN_HLEN;
6331 }
6332
6333 /* handle L3 protocols */
6334 if (protocol == __constant_htons(ETH_P_IP)) {
6335 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6336 return max_len;
6337
6338 /* access ihl as a u8 to avoid unaligned access on ia64 */
6339 hlen = (hdr.network[0] & 0x0F) << 2;
6340
6341 /* verify hlen meets minimum size requirements */
6342 if (hlen < sizeof(struct iphdr))
6343 return hdr.network - data;
6344
f2fb4ab2
AD		 6345 /* record next protocol if header is present */
6346 if (!hdr.ipv4->frag_off)
6347 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6348 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6349 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6350 return max_len;
6351
6352 /* record next protocol */
6353 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6354 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6355 } else {
6356 return hdr.network - data;
6357 }
6358
f2fb4ab2
AD		 6359 /* relocate pointer to start of L4 header */
6360 hdr.network += hlen;
6361
1a1c225b
AD		 6362 /* finally sort out TCP */
6363 if (nexthdr == IPPROTO_TCP) {
6364 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6365 return max_len;
6366
6367 /* access doff as a u8 to avoid unaligned access on ia64 */
6368 hlen = (hdr.network[12] & 0xF0) >> 2;
6369
6370 /* verify hlen meets minimum size requirements */
6371 if (hlen < sizeof(struct tcphdr))
6372 return hdr.network - data;
6373
6374 hdr.network += hlen;
6375 } else if (nexthdr == IPPROTO_UDP) {
6376 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6377 return max_len;
6378
6379 hdr.network += sizeof(struct udphdr);
6380 }
6381
6382 /*
6383 * If everything has gone correctly hdr.network should be the
6384 * data section of the packet and will be the end of the header.
6385 * If not then it probably represents the end of the last recognized
6386 * header.
6387 */
6388 if ((hdr.network - data) < max_len)
6389 return hdr.network - data;
6390 else
6391 return max_len;
6392}
6393
6394/**
6395 * igb_pull_tail - igb specific version of skb_pull_tail
6396 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6397 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6398 * @skb: pointer to current skb being adjusted
6399 *
6400 * This function is an igb specific version of __pskb_pull_tail. The
6401 * main difference between this version and the original function is that
6402 * this function can make several assumptions about the state of things
6403 * that allow for significant optimizations versus the standard function.
6404 * As a result we can do things like drop a frag and maintain an accurate
6405 * truesize for the skb.
6406 */
6407static void igb_pull_tail(struct igb_ring *rx_ring,
6408 union e1000_adv_rx_desc *rx_desc,
6409 struct sk_buff *skb)
2d94d8ab 6410{
1a1c225b
AD		 6411 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6412 unsigned char *va;
6413 unsigned int pull_len;
6414
6415 /*
6416 * it is valid to use page_address instead of kmap since we are
6417 * working with pages allocated out of the lomem pool per
6418 * alloc_page(GFP_ATOMIC)
2d94d8ab 6419 */
1a1c225b
AD		 6420 va = skb_frag_address(frag);
6421
1a1c225b
AD		 6422 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6423 /* retrieve timestamp from buffer */
6424 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6425
6426 /* update pointers to remove timestamp header */
6427 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6428 frag->page_offset += IGB_TS_HDR_LEN;
6429 skb->data_len -= IGB_TS_HDR_LEN;
6430 skb->len -= IGB_TS_HDR_LEN;
6431
6432 /* move va to start of packet data */
6433 va += IGB_TS_HDR_LEN;
6434 }
6435
1a1c225b
AD		 6436 /*
6437 * we need the header to contain the greater of either ETH_HLEN or
6438 * 60 bytes if the skb->len is less than 60 for skb_pad.
6439 */
6440 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6441
6442 /* align pull length to size of long to optimize memcpy performance */
6443 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6444
6445 /* update all of the pointers */
6446 skb_frag_size_sub(frag, pull_len);
6447 frag->page_offset += pull_len;
6448 skb->data_len -= pull_len;
6449 skb->tail += pull_len;
6450}
6451
6452/**
6453 * igb_cleanup_headers - Correct corrupted or empty headers
6454 * @rx_ring: rx descriptor ring packet is being transacted on
6455 * @rx_desc: pointer to the EOP Rx descriptor
6456 * @skb: pointer to current skb being fixed
6457 *
6458 * Address the case where we are pulling data in on pages only
6459 * and as such no data is present in the skb header.
6460 *
6461 * In addition if skb is not at least 60 bytes we need to pad it so that
6462 * it is large enough to qualify as a valid Ethernet frame.
6463 *
6464 * Returns true if an error was encountered and skb was freed.
6465 **/
6466static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6467 union e1000_adv_rx_desc *rx_desc,
6468 struct sk_buff *skb)
6469{
6470
6471 if (unlikely((igb_test_staterr(rx_desc,
6472 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6473 struct net_device *netdev = rx_ring->netdev;
6474 if (!(netdev->features & NETIF_F_RXALL)) {
6475 dev_kfree_skb_any(skb);
6476 return true;
6477 }
6478 }
6479
6480 /* place header in linear portion of buffer */
6481 if (skb_is_nonlinear(skb))
6482 igb_pull_tail(rx_ring, rx_desc, skb);
6483
6484 /* if skb_pad returns an error the skb was freed */
6485 if (unlikely(skb->len < 60)) {
6486 int pad_len = 60 - skb->len;
6487
6488 if (skb_pad(skb, pad_len))
6489 return true;
6490 __skb_put(skb, pad_len);
6491 }
6492
6493 return false;
2d94d8ab
AD		 6494}
6495
db2ee5bd
AD		 6496/**
6497 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6498 * @rx_ring: rx descriptor ring packet is being transacted on
6499 * @rx_desc: pointer to the EOP Rx descriptor
6500 * @skb: pointer to current skb being populated
6501 *
6502 * This function checks the ring, descriptor, and packet information in
6503 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6504 * other fields within the skb.
6505 **/
6506static void igb_process_skb_fields(struct igb_ring *rx_ring,
6507 union e1000_adv_rx_desc *rx_desc,
6508 struct sk_buff *skb)
6509{
6510 struct net_device *dev = rx_ring->netdev;
6511
6512 igb_rx_hash(rx_ring, rx_desc, skb);
6513
6514 igb_rx_checksum(rx_ring, rx_desc, skb);
6515
db2ee5bd 6516 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6517
6518 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6519 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6520 u16 vid;
6521 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6522 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6523 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6524 else
6525 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6526
6527 __vlan_hwaccel_put_tag(skb, vid);
6528 }
6529
6530 skb_record_rx_queue(skb, rx_ring->queue_index);
6531
6532 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6533}
6534
2e334eee 6535static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6536{
0ba82994 6537 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6538 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6539 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6540 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6541
2e334eee
AD		 6542 do {
6543 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6544
2e334eee
AD		 6545 /* return some buffers to hardware, one at a time is too slow */
6546 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6547 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6548 cleaned_count = 0;
6549 }
bf36c1a0 6550
2e334eee 6551 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6552
2e334eee
AD		 6553 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6554 break;
9d5c8243 6555
2e334eee
AD		 6556 /* retrieve a buffer from the ring */
6557 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6558
2e334eee
AD		 6559 /* exit if we failed to retrieve a buffer */
6560 if (!skb)
6561 break;
1a1c225b 6562
2e334eee 6563 cleaned_count++;
1a1c225b 6564
2e334eee
AD		 6565 /* fetch next buffer in frame if non-eop */
6566 if (igb_is_non_eop(rx_ring, rx_desc))
6567 continue;
1a1c225b
AD		 6568
6569 /* verify the packet layout is correct */
6570 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6571 skb = NULL;
6572 continue;
9d5c8243 6573 }
9d5c8243 6574
db2ee5bd 6575 /* probably a little skewed due to removing CRC */
3ceb90fd 6576 total_bytes += skb->len;
3ceb90fd 6577
db2ee5bd
AD		 6578 /* populate checksum, timestamp, VLAN, and protocol */
6579 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6580
b2cb09b1 6581 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6582
1a1c225b
AD		 6583 /* reset skb pointer */
6584 skb = NULL;
6585
2e334eee
AD		 6586 /* update budget accounting */
6587 total_packets++;
6588 } while (likely(total_packets < budget));
bf36c1a0 6589
1a1c225b
AD		 6590 /* place incomplete frames back on ring for completion */
6591 rx_ring->skb = skb;
6592
12dcd86b 6593 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6594 rx_ring->rx_stats.packets += total_packets;
6595 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6596 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6597 q_vector->rx.total_packets += total_packets;
6598 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6599
6600 if (cleaned_count)
cd392f5c 6601 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6602
2e334eee 6603 return (total_packets < budget);
9d5c8243
AK		 6604}
6605
c023cd88 6606static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6607 struct igb_rx_buffer *bi)
c023cd88
AD		 6608{
6609 struct page *page = bi->page;
cbc8e55f 6610 dma_addr_t dma;
c023cd88 6611
cbc8e55f
AD		 6612 /* since we are recycling buffers we should seldom need to alloc */
6613 if (likely(page))
c023cd88
AD		 6614 return true;
6615
cbc8e55f
AD		 6616 /* alloc new page for storage */
6617 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6618 if (unlikely(!page)) {
6619 rx_ring->rx_stats.alloc_failed++;
6620 return false;
c023cd88
AD		 6621 }
6622
cbc8e55f
AD		 6623 /* map page for use */
6624 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6625
cbc8e55f
AD		 6626 /*
6627 * if mapping failed free memory back to system since
6628 * there isn't much point in holding memory we can't use
6629 */
1a1c225b 6630 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6631 __free_page(page);
6632
c023cd88
AD		 6633 rx_ring->rx_stats.alloc_failed++;
6634 return false;
6635 }
6636
1a1c225b 6637 bi->dma = dma;
cbc8e55f
AD		 6638 bi->page = page;
6639 bi->page_offset = 0;
1a1c225b 6640
c023cd88
AD		 6641 return true;
6642}
6643
9d5c8243 6644/**
cd392f5c 6645 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6646 * @adapter: address of board private structure
6647 **/
cd392f5c 6648void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6649{
9d5c8243 6650 union e1000_adv_rx_desc *rx_desc;
06034649 6651 struct igb_rx_buffer *bi;
c023cd88 6652 u16 i = rx_ring->next_to_use;
9d5c8243 6653
cbc8e55f
AD		 6654 /* nothing to do */
6655 if (!cleaned_count)
6656 return;
6657
60136906 6658 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6659 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6660 i -= rx_ring->count;
9d5c8243 6661
cbc8e55f 6662 do {
1a1c225b 6663 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6664 break;
9d5c8243 6665
cbc8e55f
AD		 6666 /*
6667 * Refresh the desc even if buffer_addrs didn't change
6668 * because each write-back erases this info.
6669 */
6670 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6671
c023cd88
AD		 6672 rx_desc++;
6673 bi++;
9d5c8243 6674 i++;
c023cd88 6675 if (unlikely(!i)) {
60136906 6676 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6677 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6678 i -= rx_ring->count;
6679 }
6680
6681 /* clear the hdr_addr for the next_to_use descriptor */
6682 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6683
6684 cleaned_count--;
6685 } while (cleaned_count);
9d5c8243 6686
c023cd88
AD		 6687 i += rx_ring->count;
6688
9d5c8243 6689 if (rx_ring->next_to_use != i) {
cbc8e55f 6690 /* record the next descriptor to use */
9d5c8243 6691 rx_ring->next_to_use = i;
9d5c8243 6692
cbc8e55f
AD		 6693 /* update next to alloc since we have filled the ring */
6694 rx_ring->next_to_alloc = i;
6695
6696 /*
6697 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6698 * know there are new descriptors to fetch. (Only
6699 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6700 * such as IA-64).
6701 */
9d5c8243 6702 wmb();
fce99e34 6703 writel(i, rx_ring->tail);
9d5c8243
AK		 6704 }
6705}
6706
6707/**
6708 * igb_mii_ioctl -
6709 * @netdev:
6710 * @ifreq:
6711 * @cmd:
6712 **/
6713static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6714{
6715 struct igb_adapter *adapter = netdev_priv(netdev);
6716 struct mii_ioctl_data *data = if_mii(ifr);
6717
6718 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6719 return -EOPNOTSUPP;
6720
6721 switch (cmd) {
6722 case SIOCGMIIPHY:
6723 data->phy_id = adapter->hw.phy.addr;
6724 break;
6725 case SIOCGMIIREG:
f5f4cf08
AD		 6726 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6727 &data->val_out))
9d5c8243
AK		 6728 return -EIO;
6729 break;
6730 case SIOCSMIIREG:
6731 default:
6732 return -EOPNOTSUPP;
6733 }
6734 return 0;
6735}
6736
6737/**
6738 * igb_ioctl -
6739 * @netdev:
6740 * @ifreq:
6741 * @cmd:
6742 **/
6743static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6744{
6745 switch (cmd) {
6746 case SIOCGMIIPHY:
6747 case SIOCGMIIREG:
6748 case SIOCSMIIREG:
6749 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6750 case SIOCSHWTSTAMP:
a79f4f88 6751 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6752 default:
6753 return -EOPNOTSUPP;
6754 }
6755}
6756
009bc06e
AD		 6757s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6758{
6759 struct igb_adapter *adapter = hw->back;
009bc06e 6760
23d028cc 6761 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6762 return -E1000_ERR_CONFIG;
6763
009bc06e
AD		 6764 return 0;
6765}
6766
6767s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6768{
6769 struct igb_adapter *adapter = hw->back;
009bc06e 6770
23d028cc 6771 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6772 return -E1000_ERR_CONFIG;
6773
009bc06e
AD		 6774 return 0;
6775}
6776
c8f44aff 6777static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6778{
6779 struct igb_adapter *adapter = netdev_priv(netdev);
6780 struct e1000_hw *hw = &adapter->hw;
6781 u32 ctrl, rctl;
5faf030c 6782 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6783
5faf030c 6784 if (enable) {
9d5c8243
AK		 6785 /* enable VLAN tag insert/strip */
6786 ctrl = rd32(E1000_CTRL);
6787 ctrl |= E1000_CTRL_VME;
6788 wr32(E1000_CTRL, ctrl);
6789
51466239 6790 /* Disable CFI check */
9d5c8243 6791 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6792 rctl &= ~E1000_RCTL_CFIEN;
6793 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6794 } else {
6795 /* disable VLAN tag insert/strip */
6796 ctrl = rd32(E1000_CTRL);
6797 ctrl &= ~E1000_CTRL_VME;
6798 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6799 }
6800
e1739522 6801 igb_rlpml_set(adapter);
9d5c8243
AK		 6802}
6803
8e586137 6804static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6805{
6806 struct igb_adapter *adapter = netdev_priv(netdev);
6807 struct e1000_hw *hw = &adapter->hw;
4ae196df 6808 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6809
51466239
AD		 6810 /* attempt to add filter to vlvf array */
6811 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6812
51466239
AD		 6813 /* add the filter since PF can receive vlans w/o entry in vlvf */
6814 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6815
6816 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6817
6818 return 0;
9d5c8243
AK		 6819}
6820
8e586137 6821static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6822{
6823 struct igb_adapter *adapter = netdev_priv(netdev);
6824 struct e1000_hw *hw = &adapter->hw;
4ae196df 6825 int pf_id = adapter->vfs_allocated_count;
51466239 6826 s32 err;
9d5c8243 6827
51466239
AD		 6828 /* remove vlan from VLVF table array */
6829 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6830
51466239
AD		 6831 /* if vid was not present in VLVF just remove it from table */
6832 if (err)
4ae196df 6833 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6834
6835 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6836
6837 return 0;
9d5c8243
AK		 6838}
6839
6840static void igb_restore_vlan(struct igb_adapter *adapter)
6841{
b2cb09b1 6842 u16 vid;
9d5c8243 6843
5faf030c
AD		 6844 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6845
b2cb09b1
JP		 6846 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6847 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6848}
6849
14ad2513 6850int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6851{
090b1795 6852 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6853 struct e1000_mac_info *mac = &adapter->hw.mac;
6854
6855 mac->autoneg = 0;
6856
14ad2513
DD		 6857 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6858 * for the switch() below to work */
6859 if ((spd & 1) || (dplx & ~1))
6860 goto err_inval;
6861
cd2638a8
CW		 6862 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6863 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6864 spd != SPEED_1000 &&
6865 dplx != DUPLEX_FULL)
6866 goto err_inval;
cd2638a8 6867
14ad2513 6868 switch (spd + dplx) {
9d5c8243
AK		 6869 case SPEED_10 + DUPLEX_HALF:
6870 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6871 break;
6872 case SPEED_10 + DUPLEX_FULL:
6873 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6874 break;
6875 case SPEED_100 + DUPLEX_HALF:
6876 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6877 break;
6878 case SPEED_100 + DUPLEX_FULL:
6879 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6880 break;
6881 case SPEED_1000 + DUPLEX_FULL:
6882 mac->autoneg = 1;
6883 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6884 break;
6885 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6886 default:
14ad2513 6887 goto err_inval;
9d5c8243 6888 }
8376dad0
JB		 6889
6890 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6891 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6892
9d5c8243 6893 return 0;
14ad2513
DD		 6894
6895err_inval:
6896 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6897 return -EINVAL;
9d5c8243
AK		 6898}
6899
749ab2cd
YZ		 6900static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6901 bool runtime)
9d5c8243
AK		 6902{
6903 struct net_device *netdev = pci_get_drvdata(pdev);
6904 struct igb_adapter *adapter = netdev_priv(netdev);
6905 struct e1000_hw *hw = &adapter->hw;
2d064c06 6906 u32 ctrl, rctl, status;
749ab2cd 6907 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6908#ifdef CONFIG_PM
6909 int retval = 0;
6910#endif
6911
6912 netif_device_detach(netdev);
6913
a88f10ec 6914 if (netif_running(netdev))
749ab2cd 6915 __igb_close(netdev, true);
a88f10ec 6916
047e0030 6917 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6918
6919#ifdef CONFIG_PM
6920 retval = pci_save_state(pdev);
6921 if (retval)
6922 return retval;
6923#endif
6924
6925 status = rd32(E1000_STATUS);
6926 if (status & E1000_STATUS_LU)
6927 wufc &= ~E1000_WUFC_LNKC;
6928
6929 if (wufc) {
6930 igb_setup_rctl(adapter);
ff41f8dc 6931 igb_set_rx_mode(netdev);
9d5c8243
AK		 6932
6933 /* turn on all-multi mode if wake on multicast is enabled */
6934 if (wufc & E1000_WUFC_MC) {
6935 rctl = rd32(E1000_RCTL);
6936 rctl |= E1000_RCTL_MPE;
6937 wr32(E1000_RCTL, rctl);
6938 }
6939
6940 ctrl = rd32(E1000_CTRL);
6941 /* advertise wake from D3Cold */
6942 #define E1000_CTRL_ADVD3WUC 0x00100000
6943 /* phy power management enable */
6944 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6945 ctrl |= E1000_CTRL_ADVD3WUC;
6946 wr32(E1000_CTRL, ctrl);
6947
9d5c8243 6948 /* Allow time for pending master requests to run */
330a6d6a 6949 igb_disable_pcie_master(hw);
9d5c8243
AK		 6950
6951 wr32(E1000_WUC, E1000_WUC_PME_EN);
6952 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6953 } else {
6954 wr32(E1000_WUC, 0);
6955 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6956 }
6957
3fe7c4c9
RW		 6958 *enable_wake = wufc || adapter->en_mng_pt;
6959 if (!*enable_wake)
88a268c1
NN		 6960 igb_power_down_link(adapter);
6961 else
6962 igb_power_up_link(adapter);
9d5c8243
AK		 6963
6964 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6965 * would have already happened in close and is redundant. */
6966 igb_release_hw_control(adapter);
6967
6968 pci_disable_device(pdev);
6969
9d5c8243
AK		 6970 return 0;
6971}
6972
6973#ifdef CONFIG_PM
d9dd966d 6974#ifdef CONFIG_PM_SLEEP
749ab2cd 6975static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 6976{
6977 int retval;
6978 bool wake;
749ab2cd 6979 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 6980
749ab2cd 6981 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6982 if (retval)
6983 return retval;
6984
6985 if (wake) {
6986 pci_prepare_to_sleep(pdev);
6987 } else {
6988 pci_wake_from_d3(pdev, false);
6989 pci_set_power_state(pdev, PCI_D3hot);
6990 }
6991
6992 return 0;
6993}
d9dd966d 6994#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 6995
749ab2cd 6996static int igb_resume(struct device *dev)
9d5c8243 6997{
749ab2cd 6998 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 6999 struct net_device *netdev = pci_get_drvdata(pdev);
7000 struct igb_adapter *adapter = netdev_priv(netdev);
7001 struct e1000_hw *hw = &adapter->hw;
7002 u32 err;
7003
7004 pci_set_power_state(pdev, PCI_D0);
7005 pci_restore_state(pdev);
b94f2d77 7006 pci_save_state(pdev);
42bfd33a 7007
aed5dec3 7008 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7009 if (err) {
7010 dev_err(&pdev->dev,
7011 "igb: Cannot enable PCI device from suspend\n");
7012 return err;
7013 }
7014 pci_set_master(pdev);
7015
7016 pci_enable_wake(pdev, PCI_D3hot, 0);
7017 pci_enable_wake(pdev, PCI_D3cold, 0);
7018
53c7d064 7019 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7020 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7021 return -ENOMEM;
9d5c8243
AK		 7022 }
7023
9d5c8243 7024 igb_reset(adapter);
a8564f03
AD		 7025
7026 /* let the f/w know that the h/w is now under the control of the
7027 * driver. */
7028 igb_get_hw_control(adapter);
7029
9d5c8243
AK		 7030 wr32(E1000_WUS, ~0);
7031
749ab2cd 7032 if (netdev->flags & IFF_UP) {
0c2cc02e 7033 rtnl_lock();
749ab2cd 7034 err = __igb_open(netdev, true);
0c2cc02e 7035 rtnl_unlock();
a88f10ec
AD		 7036 if (err)
7037 return err;
7038 }
9d5c8243
AK		 7039
7040 netif_device_attach(netdev);
749ab2cd
YZ		 7041 return 0;
7042}
7043
7044#ifdef CONFIG_PM_RUNTIME
7045static int igb_runtime_idle(struct device *dev)
7046{
7047 struct pci_dev *pdev = to_pci_dev(dev);
7048 struct net_device *netdev = pci_get_drvdata(pdev);
7049 struct igb_adapter *adapter = netdev_priv(netdev);
7050
7051 if (!igb_has_link(adapter))
7052 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7053
7054 return -EBUSY;
7055}
7056
7057static int igb_runtime_suspend(struct device *dev)
7058{
7059 struct pci_dev *pdev = to_pci_dev(dev);
7060 int retval;
7061 bool wake;
7062
7063 retval = __igb_shutdown(pdev, &wake, 1);
7064 if (retval)
7065 return retval;
7066
7067 if (wake) {
7068 pci_prepare_to_sleep(pdev);
7069 } else {
7070 pci_wake_from_d3(pdev, false);
7071 pci_set_power_state(pdev, PCI_D3hot);
7072 }
9d5c8243 7073
9d5c8243
AK		 7074 return 0;
7075}
749ab2cd
YZ		 7076
7077static int igb_runtime_resume(struct device *dev)
7078{
7079 return igb_resume(dev);
7080}
7081#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7082#endif
7083
7084static void igb_shutdown(struct pci_dev *pdev)
7085{
3fe7c4c9
RW		 7086 bool wake;
7087
749ab2cd 7088 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7089
7090 if (system_state == SYSTEM_POWER_OFF) {
7091 pci_wake_from_d3(pdev, wake);
7092 pci_set_power_state(pdev, PCI_D3hot);
7093 }
9d5c8243
AK		 7094}
7095
fa44f2f1
GR		 7096#ifdef CONFIG_PCI_IOV
7097static int igb_sriov_reinit(struct pci_dev *dev)
7098{
7099 struct net_device *netdev = pci_get_drvdata(dev);
7100 struct igb_adapter *adapter = netdev_priv(netdev);
7101 struct pci_dev *pdev = adapter->pdev;
7102
7103 rtnl_lock();
7104
7105 if (netif_running(netdev))
7106 igb_close(netdev);
7107
7108 igb_clear_interrupt_scheme(adapter);
7109
7110 igb_init_queue_configuration(adapter);
7111
7112 if (igb_init_interrupt_scheme(adapter, true)) {
7113 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7114 return -ENOMEM;
7115 }
7116
7117 if (netif_running(netdev))
7118 igb_open(netdev);
7119
7120 rtnl_unlock();
7121
7122 return 0;
7123}
7124
7125static int igb_pci_disable_sriov(struct pci_dev *dev)
7126{
7127 int err = igb_disable_sriov(dev);
7128
7129 if (!err)
7130 err = igb_sriov_reinit(dev);
7131
7132 return err;
7133}
7134
7135static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7136{
7137 int err = igb_enable_sriov(dev, num_vfs);
7138
7139 if (err)
7140 goto out;
7141
7142 err = igb_sriov_reinit(dev);
7143 if (!err)
7144 return num_vfs;
7145
7146out:
7147 return err;
7148}
7149
7150#endif
7151static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7152{
7153#ifdef CONFIG_PCI_IOV
7154 if (num_vfs == 0)
7155 return igb_pci_disable_sriov(dev);
7156 else
7157 return igb_pci_enable_sriov(dev, num_vfs);
7158#endif
7159 return 0;
7160}
7161
9d5c8243
AK		 7162#ifdef CONFIG_NET_POLL_CONTROLLER
7163/*
7164 * Polling 'interrupt' - used by things like netconsole to send skbs
7165 * without having to re-enable interrupts. It's not called while
7166 * the interrupt routine is executing.
7167 */
7168static void igb_netpoll(struct net_device *netdev)
7169{
7170 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7171 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7172 struct igb_q_vector *q_vector;
9d5c8243 7173 int i;
9d5c8243 7174
047e0030 7175 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7176 q_vector = adapter->q_vector[i];
7177 if (adapter->msix_entries)
7178 wr32(E1000_EIMC, q_vector->eims_value);
7179 else
7180 igb_irq_disable(adapter);
047e0030 7181 napi_schedule(&q_vector->napi);
eebbbdba 7182 }
9d5c8243
AK		 7183}
7184#endif /* CONFIG_NET_POLL_CONTROLLER */
7185
7186/**
7187 * igb_io_error_detected - called when PCI error is detected
7188 * @pdev: Pointer to PCI device
7189 * @state: The current pci connection state
7190 *
7191 * This function is called after a PCI bus error affecting
7192 * this device has been detected.
7193 */
7194static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7195 pci_channel_state_t state)
7196{
7197 struct net_device *netdev = pci_get_drvdata(pdev);
7198 struct igb_adapter *adapter = netdev_priv(netdev);
7199
7200 netif_device_detach(netdev);
7201
59ed6eec
AD		 7202 if (state == pci_channel_io_perm_failure)
7203 return PCI_ERS_RESULT_DISCONNECT;
7204
9d5c8243
AK		 7205 if (netif_running(netdev))
7206 igb_down(adapter);
7207 pci_disable_device(pdev);
7208
7209 /* Request a slot slot reset. */
7210 return PCI_ERS_RESULT_NEED_RESET;
7211}
7212
7213/**
7214 * igb_io_slot_reset - called after the pci bus has been reset.
7215 * @pdev: Pointer to PCI device
7216 *
7217 * Restart the card from scratch, as if from a cold-boot. Implementation
7218 * resembles the first-half of the igb_resume routine.
7219 */
7220static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7221{
7222 struct net_device *netdev = pci_get_drvdata(pdev);
7223 struct igb_adapter *adapter = netdev_priv(netdev);
7224 struct e1000_hw *hw = &adapter->hw;
40a914fa 7225 pci_ers_result_t result;
42bfd33a 7226 int err;
9d5c8243 7227
aed5dec3 7228 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7229 dev_err(&pdev->dev,
7230 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7231 result = PCI_ERS_RESULT_DISCONNECT;
7232 } else {
7233 pci_set_master(pdev);
7234 pci_restore_state(pdev);
b94f2d77 7235 pci_save_state(pdev);
9d5c8243 7236
40a914fa
AD		 7237 pci_enable_wake(pdev, PCI_D3hot, 0);
7238 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7239
40a914fa
AD		 7240 igb_reset(adapter);
7241 wr32(E1000_WUS, ~0);
7242 result = PCI_ERS_RESULT_RECOVERED;
7243 }
9d5c8243 7244
ea943d41
JK		 7245 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7246 if (err) {
7247 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7248 "failed 0x%0x\n", err);
7249 /* non-fatal, continue */
7250 }
40a914fa
AD		 7251
7252 return result;
9d5c8243
AK		 7253}
7254
7255/**
7256 * igb_io_resume - called when traffic can start flowing again.
7257 * @pdev: Pointer to PCI device
7258 *
7259 * This callback is called when the error recovery driver tells us that
7260 * its OK to resume normal operation. Implementation resembles the
7261 * second-half of the igb_resume routine.
7262 */
7263static void igb_io_resume(struct pci_dev *pdev)
7264{
7265 struct net_device *netdev = pci_get_drvdata(pdev);
7266 struct igb_adapter *adapter = netdev_priv(netdev);
7267
9d5c8243
AK		 7268 if (netif_running(netdev)) {
7269 if (igb_up(adapter)) {
7270 dev_err(&pdev->dev, "igb_up failed after reset\n");
7271 return;
7272 }
7273 }
7274
7275 netif_device_attach(netdev);
7276
7277 /* let the f/w know that the h/w is now under the control of the
7278 * driver. */
7279 igb_get_hw_control(adapter);
9d5c8243
AK		 7280}
7281
26ad9178
AD		 7282static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7283 u8 qsel)
7284{
7285 u32 rar_low, rar_high;
7286 struct e1000_hw *hw = &adapter->hw;
7287
7288 /* HW expects these in little endian so we reverse the byte order
7289 * from network order (big endian) to little endian
7290 */
7291 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7292 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7293 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7294
7295 /* Indicate to hardware the Address is Valid. */
7296 rar_high |= E1000_RAH_AV;
7297
7298 if (hw->mac.type == e1000_82575)
7299 rar_high |= E1000_RAH_POOL_1 * qsel;
7300 else
7301 rar_high |= E1000_RAH_POOL_1 << qsel;
7302
7303 wr32(E1000_RAL(index), rar_low);
7304 wrfl();
7305 wr32(E1000_RAH(index), rar_high);
7306 wrfl();
7307}
7308
4ae196df
AD		 7309static int igb_set_vf_mac(struct igb_adapter *adapter,
7310 int vf, unsigned char *mac_addr)
7311{
7312 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7313 /* VF MAC addresses start at end of receive addresses and moves
7314 * torwards the first, as a result a collision should not be possible */
7315 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7316
37680117 7317 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7318
26ad9178 7319 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7320
7321 return 0;
7322}
7323
8151d294
WM		 7324static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7325{
7326 struct igb_adapter *adapter = netdev_priv(netdev);
7327 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7328 return -EINVAL;
7329 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7330 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7331 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7332 " change effective.");
7333 if (test_bit(__IGB_DOWN, &adapter->state)) {
7334 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7335 " but the PF device is not up.\n");
7336 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7337 " attempting to use the VF device.\n");
7338 }
7339 return igb_set_vf_mac(adapter, vf, mac);
7340}
7341
17dc566c
LL		 7342static int igb_link_mbps(int internal_link_speed)
7343{
7344 switch (internal_link_speed) {
7345 case SPEED_100:
7346 return 100;
7347 case SPEED_1000:
7348 return 1000;
7349 default:
7350 return 0;
7351 }
7352}
7353
7354static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7355 int link_speed)
7356{
7357 int rf_dec, rf_int;
7358 u32 bcnrc_val;
7359
7360 if (tx_rate != 0) {
7361 /* Calculate the rate factor values to set */
7362 rf_int = link_speed / tx_rate;
7363 rf_dec = (link_speed - (rf_int * tx_rate));
7364 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7365
7366 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7367 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7368 E1000_RTTBCNRC_RF_INT_MASK);
7369 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7370 } else {
7371 bcnrc_val = 0;
7372 }
7373
7374 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7375 /*
7376 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7377 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7378 */
7379 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7380 wr32(E1000_RTTBCNRC, bcnrc_val);
7381}
7382
7383static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7384{
7385 int actual_link_speed, i;
7386 bool reset_rate = false;
7387
7388 /* VF TX rate limit was not set or not supported */
7389 if ((adapter->vf_rate_link_speed == 0) ||
7390 (adapter->hw.mac.type != e1000_82576))
7391 return;
7392
7393 actual_link_speed = igb_link_mbps(adapter->link_speed);
7394 if (actual_link_speed != adapter->vf_rate_link_speed) {
7395 reset_rate = true;
7396 adapter->vf_rate_link_speed = 0;
7397 dev_info(&adapter->pdev->dev,
7398 "Link speed has been changed. VF Transmit "
7399 "rate is disabled\n");
7400 }
7401
7402 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7403 if (reset_rate)
7404 adapter->vf_data[i].tx_rate = 0;
7405
7406 igb_set_vf_rate_limit(&adapter->hw, i,
7407 adapter->vf_data[i].tx_rate,
7408 actual_link_speed);
7409 }
7410}
7411
8151d294
WM		 7412static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7413{
17dc566c
LL		 7414 struct igb_adapter *adapter = netdev_priv(netdev);
7415 struct e1000_hw *hw = &adapter->hw;
7416 int actual_link_speed;
7417
7418 if (hw->mac.type != e1000_82576)
7419 return -EOPNOTSUPP;
7420
7421 actual_link_speed = igb_link_mbps(adapter->link_speed);
7422 if ((vf >= adapter->vfs_allocated_count) ||
7423 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7424 (tx_rate < 0) || (tx_rate > actual_link_speed))
7425 return -EINVAL;
7426
7427 adapter->vf_rate_link_speed = actual_link_speed;
7428 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7429 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7430
7431 return 0;
8151d294
WM		 7432}
7433
7434static int igb_ndo_get_vf_config(struct net_device *netdev,
7435 int vf, struct ifla_vf_info *ivi)
7436{
7437 struct igb_adapter *adapter = netdev_priv(netdev);
7438 if (vf >= adapter->vfs_allocated_count)
7439 return -EINVAL;
7440 ivi->vf = vf;
7441 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7442 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7443 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7444 ivi->qos = adapter->vf_data[vf].pf_qos;
7445 return 0;
7446}
7447
4ae196df
AD		 7448static void igb_vmm_control(struct igb_adapter *adapter)
7449{
7450 struct e1000_hw *hw = &adapter->hw;
10d8e907 7451 u32 reg;
4ae196df 7452
52a1dd4d
AD		 7453 switch (hw->mac.type) {
7454 case e1000_82575:
f96a8a0b
CW		 7455 case e1000_i210:
7456 case e1000_i211:
52a1dd4d
AD		 7457 default:
7458 /* replication is not supported for 82575 */
4ae196df 7459 return;
52a1dd4d
AD		 7460 case e1000_82576:
7461 /* notify HW that the MAC is adding vlan tags */
7462 reg = rd32(E1000_DTXCTL);
7463 reg |= E1000_DTXCTL_VLAN_ADDED;
7464 wr32(E1000_DTXCTL, reg);
7465 case e1000_82580:
7466 /* enable replication vlan tag stripping */
7467 reg = rd32(E1000_RPLOLR);
7468 reg |= E1000_RPLOLR_STRVLAN;
7469 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7470 case e1000_i350:
7471 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7472 break;
7473 }
10d8e907 7474
d4960307
AD		 7475 if (adapter->vfs_allocated_count) {
7476 igb_vmdq_set_loopback_pf(hw, true);
7477 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7478 igb_vmdq_set_anti_spoofing_pf(hw, true,
7479 adapter->vfs_allocated_count);
d4960307
AD		 7480 } else {
7481 igb_vmdq_set_loopback_pf(hw, false);
7482 igb_vmdq_set_replication_pf(hw, false);
7483 }
4ae196df
AD		 7484}
7485
b6e0c419
CW		 7486static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7487{
7488 struct e1000_hw *hw = &adapter->hw;
7489 u32 dmac_thr;
7490 u16 hwm;
7491
7492 if (hw->mac.type > e1000_82580) {
7493 if (adapter->flags & IGB_FLAG_DMAC) {
7494 u32 reg;
7495
7496 /* force threshold to 0. */
7497 wr32(E1000_DMCTXTH, 0);
7498
7499 /*
e8c626e9
MV		 7500 * DMA Coalescing high water mark needs to be greater
7501 * than the Rx threshold. Set hwm to PBA - max frame
7502 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7503 */
e8c626e9
MV		 7504 hwm = 64 * pba - adapter->max_frame_size / 16;
7505 if (hwm < 64 * (pba - 6))
7506 hwm = 64 * (pba - 6);
7507 reg = rd32(E1000_FCRTC);
7508 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7509 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7510 & E1000_FCRTC_RTH_COAL_MASK);
7511 wr32(E1000_FCRTC, reg);
7512
7513 /*
7514 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7515 * frame size, capping it at PBA - 10KB.
7516 */
7517 dmac_thr = pba - adapter->max_frame_size / 512;
7518 if (dmac_thr < pba - 10)
7519 dmac_thr = pba - 10;
b6e0c419
CW		 7520 reg = rd32(E1000_DMACR);
7521 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7522 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7523 & E1000_DMACR_DMACTHR_MASK);
7524
7525 /* transition to L0x or L1 if available..*/
7526 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7527
7528 /* watchdog timer= +-1000 usec in 32usec intervals */
7529 reg |= (1000 >> 5);
0c02dd98
MV		 7530
7531 /* Disable BMC-to-OS Watchdog Enable */
7532 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7533 wr32(E1000_DMACR, reg);
7534
7535 /*
7536 * no lower threshold to disable
7537 * coalescing(smart fifb)-UTRESH=0
7538 */
7539 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7540
7541 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7542
7543 wr32(E1000_DMCTLX, reg);
7544
7545 /*
7546 * free space in tx packet buffer to wake from
7547 * DMA coal
7548 */
7549 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7550 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7551
7552 /*
7553 * make low power state decision controlled
7554 * by DMA coal
7555 */
7556 reg = rd32(E1000_PCIEMISC);
7557 reg &= ~E1000_PCIEMISC_LX_DECISION;
7558 wr32(E1000_PCIEMISC, reg);
7559 } /* endif adapter->dmac is not disabled */
7560 } else if (hw->mac.type == e1000_82580) {
7561 u32 reg = rd32(E1000_PCIEMISC);
7562 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7563 wr32(E1000_DMACR, 0);
7564 }
7565}
7566
441fc6fd
CW		 7567static DEFINE_SPINLOCK(i2c_clients_lock);
7568
7569/* igb_get_i2c_client - returns matching client
7570 * in adapters's client list.
7571 * @adapter: adapter struct
7572 * @dev_addr: device address of i2c needed.
7573 */
7574struct i2c_client *
7575igb_get_i2c_client(struct igb_adapter *adapter, u8 dev_addr)
7576{
7577 ulong flags;
7578 struct igb_i2c_client_list *client_list;
7579 struct i2c_client *client = NULL;
7580 struct i2c_board_info client_info = {
7581 I2C_BOARD_INFO("igb", 0x00),
7582 };
7583
7584 spin_lock_irqsave(&i2c_clients_lock, flags);
7585 client_list = adapter->i2c_clients;
7586
7587 /* See if we already have an i2c_client */
7588 while (client_list) {
7589 if (client_list->client->addr == (dev_addr >> 1)) {
7590 client = client_list->client;
7591 goto exit;
7592 } else {
7593 client_list = client_list->next;
7594 }
7595 }
7596
7597 /* no client_list found, create a new one */
7598 client_list = kzalloc(sizeof(*client_list), GFP_KERNEL);
7599 if (client_list == NULL)
7600 goto exit;
7601
7602 /* dev_addr passed to us is left-shifted by 1 bit
7603 * i2c_new_device call expects it to be flush to the right.
7604 */
7605 client_info.addr = dev_addr >> 1;
7606 client_info.platform_data = adapter;
7607 client_list->client = i2c_new_device(&adapter->i2c_adap, &client_info);
7608 if (client_list->client == NULL) {
7609 dev_info(&adapter->pdev->dev, "Failed to create new i2c device..\n");
7610 goto err_no_client;
7611 }
7612
7613 /* insert new client at head of list */
7614 client_list->next = adapter->i2c_clients;
7615 adapter->i2c_clients = client_list;
7616
7617 spin_unlock_irqrestore(&i2c_clients_lock, flags);
7618
7619 client = client_list->client;
7620 goto exit;
7621
7622err_no_client:
7623 kfree(client_list);
7624exit:
7625 spin_unlock_irqrestore(&i2c_clients_lock, flags);
7626 return client;
7627}
7628
7629/* igb_read_i2c_byte - Reads 8 bit word over I2C
7630 * @hw: pointer to hardware structure
7631 * @byte_offset: byte offset to read
7632 * @dev_addr: device address
7633 * @data: value read
7634 *
7635 * Performs byte read operation over I2C interface at
7636 * a specified device address.
7637 */
7638s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7639 u8 dev_addr, u8 *data)
7640{
7641 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7642 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7643 s32 status;
7644 u16 swfw_mask = 0;
7645
7646 if (!this_client)
7647 return E1000_ERR_I2C;
7648
7649 swfw_mask = E1000_SWFW_PHY0_SM;
7650
7651 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7652 != E1000_SUCCESS)
7653 return E1000_ERR_SWFW_SYNC;
7654
7655 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7656 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7657
7658 if (status < 0)
7659 return E1000_ERR_I2C;
7660 else {
7661 *data = status;
7662 return E1000_SUCCESS;
7663 }
7664}
7665
7666/* igb_write_i2c_byte - Writes 8 bit word over I2C
7667 * @hw: pointer to hardware structure
7668 * @byte_offset: byte offset to write
7669 * @dev_addr: device address
7670 * @data: value to write
7671 *
7672 * Performs byte write operation over I2C interface at
7673 * a specified device address.
7674 */
7675s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7676 u8 dev_addr, u8 data)
7677{
7678 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7679 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7680 s32 status;
7681 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7682
7683 if (!this_client)
7684 return E1000_ERR_I2C;
7685
7686 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7687 return E1000_ERR_SWFW_SYNC;
7688 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7689 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7690
7691 if (status)
7692 return E1000_ERR_I2C;
7693 else
7694 return E1000_SUCCESS;
7695
7696}
9d5c8243 7697/* igb_main.c */
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