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igb: drop support for single buffer mode
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
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9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4297f99b 4 Copyright(c) 2007-2011 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
b2cb09b1 31#include <linux/bitops.h>
9d5c8243
AK		 32#include <linux/vmalloc.h>
33#include <linux/pagemap.h>
34#include <linux/netdevice.h>
9d5c8243 35#include <linux/ipv6.h>
5a0e3ad6 36#include <linux/slab.h>
9d5c8243
AK		 37#include <net/checksum.h>
38#include <net/ip6_checksum.h>
c6cb090b 39#include <linux/net_tstamp.h>
9d5c8243
AK		 40#include <linux/mii.h>
41#include <linux/ethtool.h>
01789349 42#include <linux/if.h>
9d5c8243
AK		 43#include <linux/if_vlan.h>
44#include <linux/pci.h>
c54106bb 45#include <linux/pci-aspm.h>
9d5c8243
AK		 46#include <linux/delay.h>
47#include <linux/interrupt.h>
48#include <linux/if_ether.h>
40a914fa 49#include <linux/aer.h>
70c71606 50#include <linux/prefetch.h>
421e02f0 51#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 52#include <linux/dca.h>
53#endif
9d5c8243
AK		 54#include "igb.h"
55
0d1fe82d
CW		 56#define MAJ 3
57#define MIN 0
58#define BUILD 6
0d1fe82d 59#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 60__stringify(BUILD) "-k"
9d5c8243
AK		 61char igb_driver_name[] = "igb";
62char igb_driver_version[] = DRV_VERSION;
63static const char igb_driver_string[] =
64 "Intel(R) Gigabit Ethernet Network Driver";
4c4b42cb 65static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
9d5c8243 66
9d5c8243
AK		 67static const struct e1000_info *igb_info_tbl[] = {
68 [board_82575] = &e1000_82575_info,
69};
70
a3aa1884 71static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
97 /* required last entry */
98 {0, }
99};
100
101MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
102
103void igb_reset(struct igb_adapter *);
104static int igb_setup_all_tx_resources(struct igb_adapter *);
105static int igb_setup_all_rx_resources(struct igb_adapter *);
106static void igb_free_all_tx_resources(struct igb_adapter *);
107static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 108static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 109static int igb_probe(struct pci_dev *, const struct pci_device_id *);
110static void __devexit igb_remove(struct pci_dev *pdev);
673b8b70 111static void igb_init_hw_timer(struct igb_adapter *adapter);
9d5c8243
AK		 112static int igb_sw_init(struct igb_adapter *);
113static int igb_open(struct net_device *);
114static int igb_close(struct net_device *);
115static void igb_configure_tx(struct igb_adapter *);
116static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 117static void igb_clean_all_tx_rings(struct igb_adapter *);
118static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 119static void igb_clean_tx_ring(struct igb_ring *);
120static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 121static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 122static void igb_update_phy_info(unsigned long);
123static void igb_watchdog(unsigned long);
124static void igb_watchdog_task(struct work_struct *);
b1a436c3 125static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 126static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
127 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 128static int igb_change_mtu(struct net_device *, int);
129static int igb_set_mac(struct net_device *, void *);
68d480c4 130static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 131static irqreturn_t igb_intr(int irq, void *);
132static irqreturn_t igb_intr_msi(int irq, void *);
133static irqreturn_t igb_msix_other(int irq, void *);
047e0030 134static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 135#ifdef CONFIG_IGB_DCA
047e0030 136static void igb_update_dca(struct igb_q_vector *);
fe4506b6 137static void igb_setup_dca(struct igb_adapter *);
421e02f0 138#endif /* CONFIG_IGB_DCA */
047e0030 139static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 140static int igb_poll(struct napi_struct *, int);
047e0030 141static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 142static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
143static void igb_tx_timeout(struct net_device *);
144static void igb_reset_task(struct work_struct *);
b2cb09b1 145static void igb_vlan_mode(struct net_device *netdev, u32 features);
9d5c8243
AK		 146static void igb_vlan_rx_add_vid(struct net_device *, u16);
147static void igb_vlan_rx_kill_vid(struct net_device *, u16);
148static void igb_restore_vlan(struct igb_adapter *);
26ad9178 149static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 150static void igb_ping_all_vfs(struct igb_adapter *);
151static void igb_msg_task(struct igb_adapter *);
4ae196df 152static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 153static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 154static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 155static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
156static int igb_ndo_set_vf_vlan(struct net_device *netdev,
157 int vf, u16 vlan, u8 qos);
158static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
159static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
160 struct ifla_vf_info *ivi);
17dc566c 161static void igb_check_vf_rate_limit(struct igb_adapter *);
9d5c8243 162
9d5c8243 163#ifdef CONFIG_PM
3fe7c4c9 164static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 165static int igb_resume(struct pci_dev *);
166#endif
167static void igb_shutdown(struct pci_dev *);
421e02f0 168#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 169static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
170static struct notifier_block dca_notifier = {
171 .notifier_call = igb_notify_dca,
172 .next = NULL,
173 .priority = 0
174};
175#endif
9d5c8243
AK		 176#ifdef CONFIG_NET_POLL_CONTROLLER
177/* for netdump / net console */
178static void igb_netpoll(struct net_device *);
179#endif
37680117 180#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 181static unsigned int max_vfs = 0;
182module_param(max_vfs, uint, 0);
183MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
184 "per physical function");
185#endif /* CONFIG_PCI_IOV */
186
9d5c8243
AK		 187static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
188 pci_channel_state_t);
189static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
190static void igb_io_resume(struct pci_dev *);
191
192static struct pci_error_handlers igb_err_handler = {
193 .error_detected = igb_io_error_detected,
194 .slot_reset = igb_io_slot_reset,
195 .resume = igb_io_resume,
196};
197
198
199static struct pci_driver igb_driver = {
200 .name = igb_driver_name,
201 .id_table = igb_pci_tbl,
202 .probe = igb_probe,
203 .remove = __devexit_p(igb_remove),
204#ifdef CONFIG_PM
25985edc 205 /* Power Management Hooks */
9d5c8243
AK		 206 .suspend = igb_suspend,
207 .resume = igb_resume,
208#endif
209 .shutdown = igb_shutdown,
210 .err_handler = &igb_err_handler
211};
212
213MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
214MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
215MODULE_LICENSE("GPL");
216MODULE_VERSION(DRV_VERSION);
217
c97ec42a
TI		 218struct igb_reg_info {
219 u32 ofs;
220 char *name;
221};
222
223static const struct igb_reg_info igb_reg_info_tbl[] = {
224
225 /* General Registers */
226 {E1000_CTRL, "CTRL"},
227 {E1000_STATUS, "STATUS"},
228 {E1000_CTRL_EXT, "CTRL_EXT"},
229
230 /* Interrupt Registers */
231 {E1000_ICR, "ICR"},
232
233 /* RX Registers */
234 {E1000_RCTL, "RCTL"},
235 {E1000_RDLEN(0), "RDLEN"},
236 {E1000_RDH(0), "RDH"},
237 {E1000_RDT(0), "RDT"},
238 {E1000_RXDCTL(0), "RXDCTL"},
239 {E1000_RDBAL(0), "RDBAL"},
240 {E1000_RDBAH(0), "RDBAH"},
241
242 /* TX Registers */
243 {E1000_TCTL, "TCTL"},
244 {E1000_TDBAL(0), "TDBAL"},
245 {E1000_TDBAH(0), "TDBAH"},
246 {E1000_TDLEN(0), "TDLEN"},
247 {E1000_TDH(0), "TDH"},
248 {E1000_TDT(0), "TDT"},
249 {E1000_TXDCTL(0), "TXDCTL"},
250 {E1000_TDFH, "TDFH"},
251 {E1000_TDFT, "TDFT"},
252 {E1000_TDFHS, "TDFHS"},
253 {E1000_TDFPC, "TDFPC"},
254
255 /* List Terminator */
256 {}
257};
258
259/*
260 * igb_regdump - register printout routine
261 */
262static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
263{
264 int n = 0;
265 char rname[16];
266 u32 regs[8];
267
268 switch (reginfo->ofs) {
269 case E1000_RDLEN(0):
270 for (n = 0; n < 4; n++)
271 regs[n] = rd32(E1000_RDLEN(n));
272 break;
273 case E1000_RDH(0):
274 for (n = 0; n < 4; n++)
275 regs[n] = rd32(E1000_RDH(n));
276 break;
277 case E1000_RDT(0):
278 for (n = 0; n < 4; n++)
279 regs[n] = rd32(E1000_RDT(n));
280 break;
281 case E1000_RXDCTL(0):
282 for (n = 0; n < 4; n++)
283 regs[n] = rd32(E1000_RXDCTL(n));
284 break;
285 case E1000_RDBAL(0):
286 for (n = 0; n < 4; n++)
287 regs[n] = rd32(E1000_RDBAL(n));
288 break;
289 case E1000_RDBAH(0):
290 for (n = 0; n < 4; n++)
291 regs[n] = rd32(E1000_RDBAH(n));
292 break;
293 case E1000_TDBAL(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RDBAL(n));
296 break;
297 case E1000_TDBAH(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_TDBAH(n));
300 break;
301 case E1000_TDLEN(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_TDLEN(n));
304 break;
305 case E1000_TDH(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_TDH(n));
308 break;
309 case E1000_TDT(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_TDT(n));
312 break;
313 case E1000_TXDCTL(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_TXDCTL(n));
316 break;
317 default:
318 printk(KERN_INFO "%-15s %08x\n",
319 reginfo->name, rd32(reginfo->ofs));
320 return;
321 }
322
323 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
324 printk(KERN_INFO "%-15s ", rname);
325 for (n = 0; n < 4; n++)
326 printk(KERN_CONT "%08x ", regs[n]);
327 printk(KERN_CONT "\n");
328}
329
330/*
331 * igb_dump - Print registers, tx-rings and rx-rings
332 */
333static void igb_dump(struct igb_adapter *adapter)
334{
335 struct net_device *netdev = adapter->netdev;
336 struct e1000_hw *hw = &adapter->hw;
337 struct igb_reg_info *reginfo;
338 int n = 0;
339 struct igb_ring *tx_ring;
340 union e1000_adv_tx_desc *tx_desc;
341 struct my_u0 { u64 a; u64 b; } *u0;
342 struct igb_buffer *buffer_info;
343 struct igb_ring *rx_ring;
344 union e1000_adv_rx_desc *rx_desc;
345 u32 staterr;
346 int i = 0;
347
348 if (!netif_msg_hw(adapter))
349 return;
350
351 /* Print netdevice Info */
352 if (netdev) {
353 dev_info(&adapter->pdev->dev, "Net device Info\n");
354 printk(KERN_INFO "Device Name state "
355 "trans_start last_rx\n");
356 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
357 netdev->name,
358 netdev->state,
359 netdev->trans_start,
360 netdev->last_rx);
361 }
362
363 /* Print Registers */
364 dev_info(&adapter->pdev->dev, "Register Dump\n");
365 printk(KERN_INFO " Register Name Value\n");
366 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
367 reginfo->name; reginfo++) {
368 igb_regdump(hw, reginfo);
369 }
370
371 /* Print TX Ring Summary */
372 if (!netdev || !netif_running(netdev))
373 goto exit;
374
375 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
376 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]"
377 " leng ntw timestamp\n");
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
381 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
382 n, tx_ring->next_to_use, tx_ring->next_to_clean,
383 (u64)buffer_info->dma,
384 buffer_info->length,
385 buffer_info->next_to_watch,
386 (u64)buffer_info->time_stamp);
387 }
388
389 /* Print TX Rings */
390 if (!netif_msg_tx_done(adapter))
391 goto rx_ring_summary;
392
393 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
394
395 /* Transmit Descriptor Formats
396 *
397 * Advanced Transmit Descriptor
398 * +--------------------------------------------------------------+
399 * 0 | Buffer Address [63:0] |
400 * +--------------------------------------------------------------+
401 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
402 * +--------------------------------------------------------------+
403 * 63 46 45 40 39 38 36 35 32 31 24 15 0
404 */
405
406 for (n = 0; n < adapter->num_tx_queues; n++) {
407 tx_ring = adapter->tx_ring[n];
408 printk(KERN_INFO "------------------------------------\n");
409 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
410 printk(KERN_INFO "------------------------------------\n");
411 printk(KERN_INFO "T [desc] [address 63:0 ] "
412 "[PlPOCIStDDM Ln] [bi->dma ] "
413 "leng ntw timestamp bi->skb\n");
414
415 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
416 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
417 buffer_info = &tx_ring->buffer_info[i];
418 u0 = (struct my_u0 *)tx_desc;
419 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
420 " %04X %3X %016llX %p", i,
421 le64_to_cpu(u0->a),
422 le64_to_cpu(u0->b),
423 (u64)buffer_info->dma,
424 buffer_info->length,
425 buffer_info->next_to_watch,
426 (u64)buffer_info->time_stamp,
427 buffer_info->skb);
428 if (i == tx_ring->next_to_use &&
429 i == tx_ring->next_to_clean)
430 printk(KERN_CONT " NTC/U\n");
431 else if (i == tx_ring->next_to_use)
432 printk(KERN_CONT " NTU\n");
433 else if (i == tx_ring->next_to_clean)
434 printk(KERN_CONT " NTC\n");
435 else
436 printk(KERN_CONT "\n");
437
438 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
439 print_hex_dump(KERN_INFO, "",
440 DUMP_PREFIX_ADDRESS,
441 16, 1, phys_to_virt(buffer_info->dma),
442 buffer_info->length, true);
443 }
444 }
445
446 /* Print RX Rings Summary */
447rx_ring_summary:
448 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
449 printk(KERN_INFO "Queue [NTU] [NTC]\n");
450 for (n = 0; n < adapter->num_rx_queues; n++) {
451 rx_ring = adapter->rx_ring[n];
452 printk(KERN_INFO " %5d %5X %5X\n", n,
453 rx_ring->next_to_use, rx_ring->next_to_clean);
454 }
455
456 /* Print RX Rings */
457 if (!netif_msg_rx_status(adapter))
458 goto exit;
459
460 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
461
462 /* Advanced Receive Descriptor (Read) Format
463 * 63 1 0
464 * +-----------------------------------------------------+
465 * 0 | Packet Buffer Address [63:1] |A0/NSE|
466 * +----------------------------------------------+------+
467 * 8 | Header Buffer Address [63:1] | DD |
468 * +-----------------------------------------------------+
469 *
470 *
471 * Advanced Receive Descriptor (Write-Back) Format
472 *
473 * 63 48 47 32 31 30 21 20 17 16 4 3 0
474 * +------------------------------------------------------+
475 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
476 * | Checksum Ident | | | | Type | Type |
477 * +------------------------------------------------------+
478 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
479 * +------------------------------------------------------+
480 * 63 48 47 32 31 20 19 0
481 */
482
483 for (n = 0; n < adapter->num_rx_queues; n++) {
484 rx_ring = adapter->rx_ring[n];
485 printk(KERN_INFO "------------------------------------\n");
486 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
487 printk(KERN_INFO "------------------------------------\n");
488 printk(KERN_INFO "R [desc] [ PktBuf A0] "
489 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
490 "<-- Adv Rx Read format\n");
491 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
492 "[vl er S cks ln] ---------------- [bi->skb] "
493 "<-- Adv Rx Write-Back format\n");
494
495 for (i = 0; i < rx_ring->count; i++) {
496 buffer_info = &rx_ring->buffer_info[i];
497 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
498 u0 = (struct my_u0 *)rx_desc;
499 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
500 if (staterr & E1000_RXD_STAT_DD) {
501 /* Descriptor Done */
502 printk(KERN_INFO "RWB[0x%03X] %016llX "
503 "%016llX ---------------- %p", i,
504 le64_to_cpu(u0->a),
505 le64_to_cpu(u0->b),
506 buffer_info->skb);
507 } else {
508 printk(KERN_INFO "R [0x%03X] %016llX "
509 "%016llX %016llX %p", i,
510 le64_to_cpu(u0->a),
511 le64_to_cpu(u0->b),
512 (u64)buffer_info->dma,
513 buffer_info->skb);
514
515 if (netif_msg_pktdata(adapter)) {
516 print_hex_dump(KERN_INFO, "",
517 DUMP_PREFIX_ADDRESS,
518 16, 1,
519 phys_to_virt(buffer_info->dma),
44390ca6
AD		 520 IGB_RX_HDR_LEN, true);
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS,
523 16, 1,
524 phys_to_virt(
525 buffer_info->page_dma +
526 buffer_info->page_offset),
527 PAGE_SIZE/2, true);
c97ec42a
TI		 528 }
529 }
530
531 if (i == rx_ring->next_to_use)
532 printk(KERN_CONT " NTU\n");
533 else if (i == rx_ring->next_to_clean)
534 printk(KERN_CONT " NTC\n");
535 else
536 printk(KERN_CONT "\n");
537
538 }
539 }
540
541exit:
542 return;
543}
544
545
38c845c7
PO		 546/**
547 * igb_read_clock - read raw cycle counter (to be used by time counter)
548 */
549static cycle_t igb_read_clock(const struct cyclecounter *tc)
550{
551 struct igb_adapter *adapter =
552 container_of(tc, struct igb_adapter, cycles);
553 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 554 u64 stamp = 0;
555 int shift = 0;
38c845c7 556
55cac248
AD		 557 /*
558 * The timestamp latches on lowest register read. For the 82580
559 * the lowest register is SYSTIMR instead of SYSTIML. However we never
560 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
561 */
562 if (hw->mac.type == e1000_82580) {
563 stamp = rd32(E1000_SYSTIMR) >> 8;
564 shift = IGB_82580_TSYNC_SHIFT;
565 }
566
c5b9bd5e
AD		 567 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
568 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 569 return stamp;
570}
571
9d5c8243 572/**
c041076a 573 * igb_get_hw_dev - return device
9d5c8243
AK		 574 * used by hardware layer to print debugging information
575 **/
c041076a 576struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 577{
578 struct igb_adapter *adapter = hw->back;
c041076a 579 return adapter->netdev;
9d5c8243 580}
38c845c7 581
9d5c8243
AK		 582/**
583 * igb_init_module - Driver Registration Routine
584 *
585 * igb_init_module is the first routine called when the driver is
586 * loaded. All it does is register with the PCI subsystem.
587 **/
588static int __init igb_init_module(void)
589{
590 int ret;
591 printk(KERN_INFO "%s - version %s\n",
592 igb_driver_string, igb_driver_version);
593
594 printk(KERN_INFO "%s\n", igb_copyright);
595
421e02f0 596#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 597 dca_register_notify(&dca_notifier);
598#endif
bbd98fe4 599 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 600 return ret;
601}
602
603module_init(igb_init_module);
604
605/**
606 * igb_exit_module - Driver Exit Cleanup Routine
607 *
608 * igb_exit_module is called just before the driver is removed
609 * from memory.
610 **/
611static void __exit igb_exit_module(void)
612{
421e02f0 613#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 614 dca_unregister_notify(&dca_notifier);
615#endif
9d5c8243
AK		 616 pci_unregister_driver(&igb_driver);
617}
618
619module_exit(igb_exit_module);
620
26bc19ec
AD		 621#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
622/**
623 * igb_cache_ring_register - Descriptor ring to register mapping
624 * @adapter: board private structure to initialize
625 *
626 * Once we know the feature-set enabled for the device, we'll cache
627 * the register offset the descriptor ring is assigned to.
628 **/
629static void igb_cache_ring_register(struct igb_adapter *adapter)
630{
ee1b9f06 631 int i = 0, j = 0;
047e0030 632 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 633
634 switch (adapter->hw.mac.type) {
635 case e1000_82576:
636 /* The queues are allocated for virtualization such that VF 0
637 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
638 * In order to avoid collision we start at the first free queue
639 * and continue consuming queues in the same sequence
640 */
ee1b9f06 641 if (adapter->vfs_allocated_count) {
a99955fc 642 for (; i < adapter->rss_queues; i++)
3025a446
AD		 643 adapter->rx_ring[i]->reg_idx = rbase_offset +
644 Q_IDX_82576(i);
ee1b9f06 645 }
26bc19ec 646 case e1000_82575:
55cac248 647 case e1000_82580:
d2ba2ed8 648 case e1000_i350:
26bc19ec 649 default:
ee1b9f06 650 for (; i < adapter->num_rx_queues; i++)
3025a446 651 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 652 for (; j < adapter->num_tx_queues; j++)
3025a446 653 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 654 break;
655 }
656}
657
047e0030
AD		 658static void igb_free_queues(struct igb_adapter *adapter)
659{
3025a446 660 int i;
047e0030 661
3025a446
AD		 662 for (i = 0; i < adapter->num_tx_queues; i++) {
663 kfree(adapter->tx_ring[i]);
664 adapter->tx_ring[i] = NULL;
665 }
666 for (i = 0; i < adapter->num_rx_queues; i++) {
667 kfree(adapter->rx_ring[i]);
668 adapter->rx_ring[i] = NULL;
669 }
047e0030
AD		 670 adapter->num_rx_queues = 0;
671 adapter->num_tx_queues = 0;
672}
673
9d5c8243
AK		 674/**
675 * igb_alloc_queues - Allocate memory for all rings
676 * @adapter: board private structure to initialize
677 *
678 * We allocate one ring per queue at run-time since we don't know the
679 * number of queues at compile-time.
680 **/
681static int igb_alloc_queues(struct igb_adapter *adapter)
682{
3025a446 683 struct igb_ring *ring;
9d5c8243
AK		 684 int i;
685
661086df 686 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 687 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
688 if (!ring)
689 goto err;
68fd9910 690 ring->count = adapter->tx_ring_count;
661086df 691 ring->queue_index = i;
59d71989 692 ring->dev = &adapter->pdev->dev;
e694e964 693 ring->netdev = adapter->netdev;
85ad76b2
AD		 694 /* For 82575, context index must be unique per ring. */
695 if (adapter->hw.mac.type == e1000_82575)
696 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 697 adapter->tx_ring[i] = ring;
661086df 698 }
85ad76b2 699
9d5c8243 700 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 701 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
702 if (!ring)
703 goto err;
68fd9910 704 ring->count = adapter->rx_ring_count;
844290e5 705 ring->queue_index = i;
59d71989 706 ring->dev = &adapter->pdev->dev;
e694e964 707 ring->netdev = adapter->netdev;
85ad76b2
AD		 708 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
709 /* set flag indicating ring supports SCTP checksum offload */
710 if (adapter->hw.mac.type >= e1000_82576)
711 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 712 adapter->rx_ring[i] = ring;
9d5c8243 713 }
26bc19ec
AD		 714
715 igb_cache_ring_register(adapter);
9d5c8243 716
047e0030 717 return 0;
a88f10ec 718
047e0030
AD		 719err:
720 igb_free_queues(adapter);
d1a8c9e1 721
047e0030 722 return -ENOMEM;
a88f10ec
AD		 723}
724
9d5c8243 725#define IGB_N0_QUEUE -1
047e0030 726static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 727{
728 u32 msixbm = 0;
047e0030 729 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 730 struct e1000_hw *hw = &adapter->hw;
2d064c06 731 u32 ivar, index;
047e0030
AD		 732 int rx_queue = IGB_N0_QUEUE;
733 int tx_queue = IGB_N0_QUEUE;
734
735 if (q_vector->rx_ring)
736 rx_queue = q_vector->rx_ring->reg_idx;
737 if (q_vector->tx_ring)
738 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 739
740 switch (hw->mac.type) {
741 case e1000_82575:
9d5c8243
AK		 742 /* The 82575 assigns vectors using a bitmask, which matches the
743 bitmask for the EICR/EIMS/EIMC registers. To assign one
744 or more queues to a vector, we write the appropriate bits
745 into the MSIXBM register for that vector. */
047e0030 746 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 747 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 748 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 749 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 750 if (!adapter->msix_entries && msix_vector == 0)
751 msixbm |= E1000_EIMS_OTHER;
9d5c8243 752 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 753 q_vector->eims_value = msixbm;
2d064c06
AD		 754 break;
755 case e1000_82576:
26bc19ec 756 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 757 Each queue has a single entry in the table to which we write
758 a vector number along with a "valid" bit. Sadly, the layout
759 of the table is somewhat counterintuitive. */
760 if (rx_queue > IGB_N0_QUEUE) {
047e0030 761 index = (rx_queue & 0x7);
2d064c06 762 ivar = array_rd32(E1000_IVAR0, index);
047e0030 763 if (rx_queue < 8) {
26bc19ec
AD		 764 /* vector goes into low byte of register */
765 ivar = ivar & 0xFFFFFF00;
766 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 767 } else {
768 /* vector goes into third byte of register */
769 ivar = ivar & 0xFF00FFFF;
770 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 771 }
2d064c06
AD		 772 array_wr32(E1000_IVAR0, index, ivar);
773 }
774 if (tx_queue > IGB_N0_QUEUE) {
047e0030 775 index = (tx_queue & 0x7);
2d064c06 776 ivar = array_rd32(E1000_IVAR0, index);
047e0030 777 if (tx_queue < 8) {
26bc19ec
AD		 778 /* vector goes into second byte of register */
779 ivar = ivar & 0xFFFF00FF;
780 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 781 } else {
782 /* vector goes into high byte of register */
783 ivar = ivar & 0x00FFFFFF;
784 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 785 }
2d064c06
AD		 786 array_wr32(E1000_IVAR0, index, ivar);
787 }
047e0030 788 q_vector->eims_value = 1 << msix_vector;
2d064c06 789 break;
55cac248 790 case e1000_82580:
d2ba2ed8 791 case e1000_i350:
55cac248
AD		 792 /* 82580 uses the same table-based approach as 82576 but has fewer
793 entries as a result we carry over for queues greater than 4. */
794 if (rx_queue > IGB_N0_QUEUE) {
795 index = (rx_queue >> 1);
796 ivar = array_rd32(E1000_IVAR0, index);
797 if (rx_queue & 0x1) {
798 /* vector goes into third byte of register */
799 ivar = ivar & 0xFF00FFFF;
800 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
801 } else {
802 /* vector goes into low byte of register */
803 ivar = ivar & 0xFFFFFF00;
804 ivar |= msix_vector | E1000_IVAR_VALID;
805 }
806 array_wr32(E1000_IVAR0, index, ivar);
807 }
808 if (tx_queue > IGB_N0_QUEUE) {
809 index = (tx_queue >> 1);
810 ivar = array_rd32(E1000_IVAR0, index);
811 if (tx_queue & 0x1) {
812 /* vector goes into high byte of register */
813 ivar = ivar & 0x00FFFFFF;
814 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
815 } else {
816 /* vector goes into second byte of register */
817 ivar = ivar & 0xFFFF00FF;
818 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
819 }
820 array_wr32(E1000_IVAR0, index, ivar);
821 }
822 q_vector->eims_value = 1 << msix_vector;
823 break;
2d064c06
AD		 824 default:
825 BUG();
826 break;
827 }
26b39276
AD		 828
829 /* add q_vector eims value to global eims_enable_mask */
830 adapter->eims_enable_mask |= q_vector->eims_value;
831
832 /* configure q_vector to set itr on first interrupt */
833 q_vector->set_itr = 1;
9d5c8243
AK		 834}
835
836/**
837 * igb_configure_msix - Configure MSI-X hardware
838 *
839 * igb_configure_msix sets up the hardware to properly
840 * generate MSI-X interrupts.
841 **/
842static void igb_configure_msix(struct igb_adapter *adapter)
843{
844 u32 tmp;
845 int i, vector = 0;
846 struct e1000_hw *hw = &adapter->hw;
847
848 adapter->eims_enable_mask = 0;
9d5c8243
AK		 849
850 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 851 switch (hw->mac.type) {
852 case e1000_82575:
9d5c8243
AK		 853 tmp = rd32(E1000_CTRL_EXT);
854 /* enable MSI-X PBA support*/
855 tmp |= E1000_CTRL_EXT_PBA_CLR;
856
857 /* Auto-Mask interrupts upon ICR read. */
858 tmp |= E1000_CTRL_EXT_EIAME;
859 tmp |= E1000_CTRL_EXT_IRCA;
860
861 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 862
863 /* enable msix_other interrupt */
864 array_wr32(E1000_MSIXBM(0), vector++,
865 E1000_EIMS_OTHER);
844290e5 866 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 867
2d064c06
AD		 868 break;
869
870 case e1000_82576:
55cac248 871 case e1000_82580:
d2ba2ed8 872 case e1000_i350:
047e0030
AD		 873 /* Turn on MSI-X capability first, or our settings
874 * won't stick. And it will take days to debug. */
875 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
876 E1000_GPIE_PBA | E1000_GPIE_EIAME |
877 E1000_GPIE_NSICR);
878
879 /* enable msix_other interrupt */
880 adapter->eims_other = 1 << vector;
2d064c06 881 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 882
047e0030 883 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 884 break;
885 default:
886 /* do nothing, since nothing else supports MSI-X */
887 break;
888 } /* switch (hw->mac.type) */
047e0030
AD		 889
890 adapter->eims_enable_mask |= adapter->eims_other;
891
26b39276
AD		 892 for (i = 0; i < adapter->num_q_vectors; i++)
893 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 894
9d5c8243
AK		 895 wrfl();
896}
897
898/**
899 * igb_request_msix - Initialize MSI-X interrupts
900 *
901 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
902 * kernel.
903 **/
904static int igb_request_msix(struct igb_adapter *adapter)
905{
906 struct net_device *netdev = adapter->netdev;
047e0030 907 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 908 int i, err = 0, vector = 0;
909
047e0030 910 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 911 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 912 if (err)
913 goto out;
914 vector++;
915
916 for (i = 0; i < adapter->num_q_vectors; i++) {
917 struct igb_q_vector *q_vector = adapter->q_vector[i];
918
919 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
920
921 if (q_vector->rx_ring && q_vector->tx_ring)
922 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
923 q_vector->rx_ring->queue_index);
924 else if (q_vector->tx_ring)
925 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
926 q_vector->tx_ring->queue_index);
927 else if (q_vector->rx_ring)
928 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
929 q_vector->rx_ring->queue_index);
9d5c8243 930 else
047e0030
AD		 931 sprintf(q_vector->name, "%s-unused", netdev->name);
932
9d5c8243 933 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 934 igb_msix_ring, 0, q_vector->name,
047e0030 935 q_vector);
9d5c8243
AK		 936 if (err)
937 goto out;
9d5c8243
AK		 938 vector++;
939 }
940
9d5c8243
AK		 941 igb_configure_msix(adapter);
942 return 0;
943out:
944 return err;
945}
946
947static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
948{
949 if (adapter->msix_entries) {
950 pci_disable_msix(adapter->pdev);
951 kfree(adapter->msix_entries);
952 adapter->msix_entries = NULL;
047e0030 953 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 954 pci_disable_msi(adapter->pdev);
047e0030 955 }
9d5c8243
AK		 956}
957
047e0030
AD		 958/**
959 * igb_free_q_vectors - Free memory allocated for interrupt vectors
960 * @adapter: board private structure to initialize
961 *
962 * This function frees the memory allocated to the q_vectors. In addition if
963 * NAPI is enabled it will delete any references to the NAPI struct prior
964 * to freeing the q_vector.
965 **/
966static void igb_free_q_vectors(struct igb_adapter *adapter)
967{
968 int v_idx;
969
970 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
971 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
972 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 973 if (!q_vector)
974 continue;
047e0030
AD		 975 netif_napi_del(&q_vector->napi);
976 kfree(q_vector);
977 }
978 adapter->num_q_vectors = 0;
979}
980
981/**
982 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
983 *
984 * This function resets the device so that it has 0 rx queues, tx queues, and
985 * MSI-X interrupts allocated.
986 */
987static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
988{
989 igb_free_queues(adapter);
990 igb_free_q_vectors(adapter);
991 igb_reset_interrupt_capability(adapter);
992}
9d5c8243
AK		 993
994/**
995 * igb_set_interrupt_capability - set MSI or MSI-X if supported
996 *
997 * Attempt to configure interrupts using the best available
998 * capabilities of the hardware and kernel.
999 **/
21adef3e 1000static int igb_set_interrupt_capability(struct igb_adapter *adapter)
9d5c8243
AK		 1001{
1002 int err;
1003 int numvecs, i;
1004
83b7180d 1005 /* Number of supported queues. */
a99955fc 1006 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1007 if (adapter->vfs_allocated_count)
1008 adapter->num_tx_queues = 1;
1009 else
1010 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1011
047e0030
AD		 1012 /* start with one vector for every rx queue */
1013 numvecs = adapter->num_rx_queues;
1014
3ad2f3fb 1015 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1016 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1017 numvecs += adapter->num_tx_queues;
047e0030
AD		 1018
1019 /* store the number of vectors reserved for queues */
1020 adapter->num_q_vectors = numvecs;
1021
1022 /* add 1 vector for link status interrupts */
1023 numvecs++;
9d5c8243
AK		 1024 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1025 GFP_KERNEL);
1026 if (!adapter->msix_entries)
1027 goto msi_only;
1028
1029 for (i = 0; i < numvecs; i++)
1030 adapter->msix_entries[i].entry = i;
1031
1032 err = pci_enable_msix(adapter->pdev,
1033 adapter->msix_entries,
1034 numvecs);
1035 if (err == 0)
34a20e89 1036 goto out;
9d5c8243
AK		 1037
1038 igb_reset_interrupt_capability(adapter);
1039
1040 /* If we can't do MSI-X, try MSI */
1041msi_only:
2a3abf6d
AD		 1042#ifdef CONFIG_PCI_IOV
1043 /* disable SR-IOV for non MSI-X configurations */
1044 if (adapter->vf_data) {
1045 struct e1000_hw *hw = &adapter->hw;
1046 /* disable iov and allow time for transactions to clear */
1047 pci_disable_sriov(adapter->pdev);
1048 msleep(500);
1049
1050 kfree(adapter->vf_data);
1051 adapter->vf_data = NULL;
1052 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1053 wrfl();
2a3abf6d
AD		 1054 msleep(100);
1055 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1056 }
1057#endif
4fc82adf 1058 adapter->vfs_allocated_count = 0;
a99955fc 1059 adapter->rss_queues = 1;
4fc82adf 1060 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1061 adapter->num_rx_queues = 1;
661086df 1062 adapter->num_tx_queues = 1;
047e0030 1063 adapter->num_q_vectors = 1;
9d5c8243 1064 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1065 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1066out:
21adef3e
BH		 1067 /* Notify the stack of the (possibly) reduced queue counts. */
1068 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
1069 return netif_set_real_num_rx_queues(adapter->netdev,
1070 adapter->num_rx_queues);
9d5c8243
AK		 1071}
1072
047e0030
AD		 1073/**
1074 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1075 * @adapter: board private structure to initialize
1076 *
1077 * We allocate one q_vector per queue interrupt. If allocation fails we
1078 * return -ENOMEM.
1079 **/
1080static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1081{
1082 struct igb_q_vector *q_vector;
1083 struct e1000_hw *hw = &adapter->hw;
1084 int v_idx;
1085
1086 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1087 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
1088 if (!q_vector)
1089 goto err_out;
1090 q_vector->adapter = adapter;
047e0030
AD		 1091 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1092 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1093 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1094 adapter->q_vector[v_idx] = q_vector;
1095 }
1096 return 0;
1097
1098err_out:
fe0592b4 1099 igb_free_q_vectors(adapter);
047e0030
AD		 1100 return -ENOMEM;
1101}
1102
1103static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1104 int ring_idx, int v_idx)
1105{
3025a446 1106 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1107
3025a446 1108 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 1109 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 1110 q_vector->itr_val = adapter->rx_itr_setting;
1111 if (q_vector->itr_val && q_vector->itr_val <= 3)
1112 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1113}
1114
1115static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1116 int ring_idx, int v_idx)
1117{
3025a446 1118 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1119
3025a446 1120 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 1121 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 1122 q_vector->itr_val = adapter->tx_itr_setting;
1123 if (q_vector->itr_val && q_vector->itr_val <= 3)
1124 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1125}
1126
1127/**
1128 * igb_map_ring_to_vector - maps allocated queues to vectors
1129 *
1130 * This function maps the recently allocated queues to vectors.
1131 **/
1132static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1133{
1134 int i;
1135 int v_idx = 0;
1136
1137 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1138 (adapter->num_q_vectors < adapter->num_tx_queues))
1139 return -ENOMEM;
1140
1141 if (adapter->num_q_vectors >=
1142 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1143 for (i = 0; i < adapter->num_rx_queues; i++)
1144 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1145 for (i = 0; i < adapter->num_tx_queues; i++)
1146 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1147 } else {
1148 for (i = 0; i < adapter->num_rx_queues; i++) {
1149 if (i < adapter->num_tx_queues)
1150 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1151 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1152 }
1153 for (; i < adapter->num_tx_queues; i++)
1154 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1155 }
1156 return 0;
1157}
1158
1159/**
1160 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1161 *
1162 * This function initializes the interrupts and allocates all of the queues.
1163 **/
1164static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1165{
1166 struct pci_dev *pdev = adapter->pdev;
1167 int err;
1168
21adef3e
BH		 1169 err = igb_set_interrupt_capability(adapter);
1170 if (err)
1171 return err;
047e0030
AD		 1172
1173 err = igb_alloc_q_vectors(adapter);
1174 if (err) {
1175 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1176 goto err_alloc_q_vectors;
1177 }
1178
1179 err = igb_alloc_queues(adapter);
1180 if (err) {
1181 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1182 goto err_alloc_queues;
1183 }
1184
1185 err = igb_map_ring_to_vector(adapter);
1186 if (err) {
1187 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1188 goto err_map_queues;
1189 }
1190
1191
1192 return 0;
1193err_map_queues:
1194 igb_free_queues(adapter);
1195err_alloc_queues:
1196 igb_free_q_vectors(adapter);
1197err_alloc_q_vectors:
1198 igb_reset_interrupt_capability(adapter);
1199 return err;
1200}
1201
9d5c8243
AK		 1202/**
1203 * igb_request_irq - initialize interrupts
1204 *
1205 * Attempts to configure interrupts using the best available
1206 * capabilities of the hardware and kernel.
1207 **/
1208static int igb_request_irq(struct igb_adapter *adapter)
1209{
1210 struct net_device *netdev = adapter->netdev;
047e0030 1211 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1212 int err = 0;
1213
1214 if (adapter->msix_entries) {
1215 err = igb_request_msix(adapter);
844290e5 1216 if (!err)
9d5c8243 1217 goto request_done;
9d5c8243 1218 /* fall back to MSI */
047e0030 1219 igb_clear_interrupt_scheme(adapter);
9d5c8243 1220 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1221 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1222 igb_free_all_tx_resources(adapter);
1223 igb_free_all_rx_resources(adapter);
047e0030 1224 adapter->num_tx_queues = 1;
9d5c8243 1225 adapter->num_rx_queues = 1;
047e0030
AD		 1226 adapter->num_q_vectors = 1;
1227 err = igb_alloc_q_vectors(adapter);
1228 if (err) {
1229 dev_err(&pdev->dev,
1230 "Unable to allocate memory for vectors\n");
1231 goto request_done;
1232 }
1233 err = igb_alloc_queues(adapter);
1234 if (err) {
1235 dev_err(&pdev->dev,
1236 "Unable to allocate memory for queues\n");
1237 igb_free_q_vectors(adapter);
1238 goto request_done;
1239 }
1240 igb_setup_all_tx_resources(adapter);
1241 igb_setup_all_rx_resources(adapter);
844290e5 1242 } else {
feeb2721 1243 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 1244 }
844290e5 1245
7dfc16fa 1246 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 1247 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 1248 netdev->name, adapter);
9d5c8243
AK		 1249 if (!err)
1250 goto request_done;
047e0030 1251
9d5c8243
AK		 1252 /* fall back to legacy interrupts */
1253 igb_reset_interrupt_capability(adapter);
7dfc16fa 1254 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1255 }
1256
a0607fd3 1257 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1258 netdev->name, adapter);
9d5c8243 1259
6cb5e577 1260 if (err)
9d5c8243
AK		 1261 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
1262 err);
9d5c8243
AK		 1263
1264request_done:
1265 return err;
1266}
1267
1268static void igb_free_irq(struct igb_adapter *adapter)
1269{
9d5c8243
AK		 1270 if (adapter->msix_entries) {
1271 int vector = 0, i;
1272
047e0030 1273 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1274
047e0030
AD		 1275 for (i = 0; i < adapter->num_q_vectors; i++) {
1276 struct igb_q_vector *q_vector = adapter->q_vector[i];
1277 free_irq(adapter->msix_entries[vector++].vector,
1278 q_vector);
1279 }
1280 } else {
1281 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1282 }
9d5c8243
AK		 1283}
1284
1285/**
1286 * igb_irq_disable - Mask off interrupt generation on the NIC
1287 * @adapter: board private structure
1288 **/
1289static void igb_irq_disable(struct igb_adapter *adapter)
1290{
1291 struct e1000_hw *hw = &adapter->hw;
1292
25568a53
AD		 1293 /*
1294 * we need to be careful when disabling interrupts. The VFs are also
1295 * mapped into these registers and so clearing the bits can cause
1296 * issues on the VF drivers so we only need to clear what we set
1297 */
9d5c8243 1298 if (adapter->msix_entries) {
2dfd1212
AD		 1299 u32 regval = rd32(E1000_EIAM);
1300 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1301 wr32(E1000_EIMC, adapter->eims_enable_mask);
1302 regval = rd32(E1000_EIAC);
1303 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1304 }
844290e5
PW		 1305
1306 wr32(E1000_IAM, 0);
9d5c8243
AK		 1307 wr32(E1000_IMC, ~0);
1308 wrfl();
81a61859
ET		 1309 if (adapter->msix_entries) {
1310 int i;
1311 for (i = 0; i < adapter->num_q_vectors; i++)
1312 synchronize_irq(adapter->msix_entries[i].vector);
1313 } else {
1314 synchronize_irq(adapter->pdev->irq);
1315 }
9d5c8243
AK		 1316}
1317
1318/**
1319 * igb_irq_enable - Enable default interrupt generation settings
1320 * @adapter: board private structure
1321 **/
1322static void igb_irq_enable(struct igb_adapter *adapter)
1323{
1324 struct e1000_hw *hw = &adapter->hw;
1325
1326 if (adapter->msix_entries) {
25568a53 1327 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 1328 u32 regval = rd32(E1000_EIAC);
1329 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1330 regval = rd32(E1000_EIAM);
1331 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1332 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1333 if (adapter->vfs_allocated_count) {
4ae196df 1334 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1335 ims |= E1000_IMS_VMMB;
1336 }
55cac248
AD		 1337 if (adapter->hw.mac.type == e1000_82580)
1338 ims |= E1000_IMS_DRSTA;
1339
25568a53 1340 wr32(E1000_IMS, ims);
844290e5 1341 } else {
55cac248
AD		 1342 wr32(E1000_IMS, IMS_ENABLE_MASK |
1343 E1000_IMS_DRSTA);
1344 wr32(E1000_IAM, IMS_ENABLE_MASK |
1345 E1000_IMS_DRSTA);
844290e5 1346 }
9d5c8243
AK		 1347}
1348
1349static void igb_update_mng_vlan(struct igb_adapter *adapter)
1350{
51466239 1351 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1352 u16 vid = adapter->hw.mng_cookie.vlan_id;
1353 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1354
1355 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1356 /* add VID to filter table */
1357 igb_vfta_set(hw, vid, true);
1358 adapter->mng_vlan_id = vid;
1359 } else {
1360 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1361 }
1362
1363 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1364 (vid != old_vid) &&
b2cb09b1 1365 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1366 /* remove VID from filter table */
1367 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1368 }
1369}
1370
1371/**
1372 * igb_release_hw_control - release control of the h/w to f/w
1373 * @adapter: address of board private structure
1374 *
1375 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1376 * For ASF and Pass Through versions of f/w this means that the
1377 * driver is no longer loaded.
1378 *
1379 **/
1380static void igb_release_hw_control(struct igb_adapter *adapter)
1381{
1382 struct e1000_hw *hw = &adapter->hw;
1383 u32 ctrl_ext;
1384
1385 /* Let firmware take over control of h/w */
1386 ctrl_ext = rd32(E1000_CTRL_EXT);
1387 wr32(E1000_CTRL_EXT,
1388 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1389}
1390
9d5c8243
AK		 1391/**
1392 * igb_get_hw_control - get control of the h/w from f/w
1393 * @adapter: address of board private structure
1394 *
1395 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1396 * For ASF and Pass Through versions of f/w this means that
1397 * the driver is loaded.
1398 *
1399 **/
1400static void igb_get_hw_control(struct igb_adapter *adapter)
1401{
1402 struct e1000_hw *hw = &adapter->hw;
1403 u32 ctrl_ext;
1404
1405 /* Let firmware know the driver has taken over */
1406 ctrl_ext = rd32(E1000_CTRL_EXT);
1407 wr32(E1000_CTRL_EXT,
1408 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1409}
1410
9d5c8243
AK		 1411/**
1412 * igb_configure - configure the hardware for RX and TX
1413 * @adapter: private board structure
1414 **/
1415static void igb_configure(struct igb_adapter *adapter)
1416{
1417 struct net_device *netdev = adapter->netdev;
1418 int i;
1419
1420 igb_get_hw_control(adapter);
ff41f8dc 1421 igb_set_rx_mode(netdev);
9d5c8243
AK		 1422
1423 igb_restore_vlan(adapter);
9d5c8243 1424
85b430b4 1425 igb_setup_tctl(adapter);
06cf2666 1426 igb_setup_mrqc(adapter);
9d5c8243 1427 igb_setup_rctl(adapter);
85b430b4
AD		 1428
1429 igb_configure_tx(adapter);
9d5c8243 1430 igb_configure_rx(adapter);
662d7205
AD		 1431
1432 igb_rx_fifo_flush_82575(&adapter->hw);
1433
c493ea45 1434 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1435 * at least 1 descriptor unused to make sure
1436 * next_to_use != next_to_clean */
1437 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1438 struct igb_ring *ring = adapter->rx_ring[i];
c493ea45 1439 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243 1440 }
9d5c8243
AK		 1441}
1442
88a268c1
NN		 1443/**
1444 * igb_power_up_link - Power up the phy/serdes link
1445 * @adapter: address of board private structure
1446 **/
1447void igb_power_up_link(struct igb_adapter *adapter)
1448{
1449 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1450 igb_power_up_phy_copper(&adapter->hw);
1451 else
1452 igb_power_up_serdes_link_82575(&adapter->hw);
1453}
1454
1455/**
1456 * igb_power_down_link - Power down the phy/serdes link
1457 * @adapter: address of board private structure
1458 */
1459static void igb_power_down_link(struct igb_adapter *adapter)
1460{
1461 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1462 igb_power_down_phy_copper_82575(&adapter->hw);
1463 else
1464 igb_shutdown_serdes_link_82575(&adapter->hw);
1465}
9d5c8243
AK		 1466
1467/**
1468 * igb_up - Open the interface and prepare it to handle traffic
1469 * @adapter: board private structure
1470 **/
9d5c8243
AK		 1471int igb_up(struct igb_adapter *adapter)
1472{
1473 struct e1000_hw *hw = &adapter->hw;
1474 int i;
1475
1476 /* hardware has been reset, we need to reload some things */
1477 igb_configure(adapter);
1478
1479 clear_bit(__IGB_DOWN, &adapter->state);
1480
047e0030
AD		 1481 for (i = 0; i < adapter->num_q_vectors; i++) {
1482 struct igb_q_vector *q_vector = adapter->q_vector[i];
1483 napi_enable(&q_vector->napi);
1484 }
844290e5 1485 if (adapter->msix_entries)
9d5c8243 1486 igb_configure_msix(adapter);
feeb2721
AD		 1487 else
1488 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1489
1490 /* Clear any pending interrupts. */
1491 rd32(E1000_ICR);
1492 igb_irq_enable(adapter);
1493
d4960307
AD		 1494 /* notify VFs that reset has been completed */
1495 if (adapter->vfs_allocated_count) {
1496 u32 reg_data = rd32(E1000_CTRL_EXT);
1497 reg_data |= E1000_CTRL_EXT_PFRSTD;
1498 wr32(E1000_CTRL_EXT, reg_data);
1499 }
1500
4cb9be7a
JB		 1501 netif_tx_start_all_queues(adapter->netdev);
1502
25568a53
AD		 1503 /* start the watchdog. */
1504 hw->mac.get_link_status = 1;
1505 schedule_work(&adapter->watchdog_task);
1506
9d5c8243
AK		 1507 return 0;
1508}
1509
1510void igb_down(struct igb_adapter *adapter)
1511{
9d5c8243 1512 struct net_device *netdev = adapter->netdev;
330a6d6a 1513 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1514 u32 tctl, rctl;
1515 int i;
1516
1517 /* signal that we're down so the interrupt handler does not
1518 * reschedule our watchdog timer */
1519 set_bit(__IGB_DOWN, &adapter->state);
1520
1521 /* disable receives in the hardware */
1522 rctl = rd32(E1000_RCTL);
1523 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1524 /* flush and sleep below */
1525
fd2ea0a7 1526 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1527
1528 /* disable transmits in the hardware */
1529 tctl = rd32(E1000_TCTL);
1530 tctl &= ~E1000_TCTL_EN;
1531 wr32(E1000_TCTL, tctl);
1532 /* flush both disables and wait for them to finish */
1533 wrfl();
1534 msleep(10);
1535
047e0030
AD		 1536 for (i = 0; i < adapter->num_q_vectors; i++) {
1537 struct igb_q_vector *q_vector = adapter->q_vector[i];
1538 napi_disable(&q_vector->napi);
1539 }
9d5c8243 1540
9d5c8243
AK		 1541 igb_irq_disable(adapter);
1542
1543 del_timer_sync(&adapter->watchdog_timer);
1544 del_timer_sync(&adapter->phy_info_timer);
1545
9d5c8243 1546 netif_carrier_off(netdev);
04fe6358
AD		 1547
1548 /* record the stats before reset*/
12dcd86b
ED		 1549 spin_lock(&adapter->stats64_lock);
1550 igb_update_stats(adapter, &adapter->stats64);
1551 spin_unlock(&adapter->stats64_lock);
04fe6358 1552
9d5c8243
AK		 1553 adapter->link_speed = 0;
1554 adapter->link_duplex = 0;
1555
3023682e
JK		 1556 if (!pci_channel_offline(adapter->pdev))
1557 igb_reset(adapter);
9d5c8243
AK		 1558 igb_clean_all_tx_rings(adapter);
1559 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1560#ifdef CONFIG_IGB_DCA
1561
1562 /* since we reset the hardware DCA settings were cleared */
1563 igb_setup_dca(adapter);
1564#endif
9d5c8243
AK		 1565}
1566
1567void igb_reinit_locked(struct igb_adapter *adapter)
1568{
1569 WARN_ON(in_interrupt());
1570 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1571 msleep(1);
1572 igb_down(adapter);
1573 igb_up(adapter);
1574 clear_bit(__IGB_RESETTING, &adapter->state);
1575}
1576
1577void igb_reset(struct igb_adapter *adapter)
1578{
090b1795 1579 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1580 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1581 struct e1000_mac_info *mac = &hw->mac;
1582 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1583 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1584 u16 hwm;
1585
1586 /* Repartition Pba for greater than 9k mtu
1587 * To take effect CTRL.RST is required.
1588 */
fa4dfae0 1589 switch (mac->type) {
d2ba2ed8 1590 case e1000_i350:
55cac248
AD		 1591 case e1000_82580:
1592 pba = rd32(E1000_RXPBS);
1593 pba = igb_rxpbs_adjust_82580(pba);
1594 break;
fa4dfae0 1595 case e1000_82576:
d249be54
AD		 1596 pba = rd32(E1000_RXPBS);
1597 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1598 break;
1599 case e1000_82575:
1600 default:
1601 pba = E1000_PBA_34K;
1602 break;
2d064c06 1603 }
9d5c8243 1604
2d064c06
AD		 1605 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1606 (mac->type < e1000_82576)) {
9d5c8243
AK		 1607 /* adjust PBA for jumbo frames */
1608 wr32(E1000_PBA, pba);
1609
1610 /* To maintain wire speed transmits, the Tx FIFO should be
1611 * large enough to accommodate two full transmit packets,
1612 * rounded up to the next 1KB and expressed in KB. Likewise,
1613 * the Rx FIFO should be large enough to accommodate at least
1614 * one full receive packet and is similarly rounded up and
1615 * expressed in KB. */
1616 pba = rd32(E1000_PBA);
1617 /* upper 16 bits has Tx packet buffer allocation size in KB */
1618 tx_space = pba >> 16;
1619 /* lower 16 bits has Rx packet buffer allocation size in KB */
1620 pba &= 0xffff;
1621 /* the tx fifo also stores 16 bytes of information about the tx
1622 * but don't include ethernet FCS because hardware appends it */
1623 min_tx_space = (adapter->max_frame_size +
85e8d004 1624 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1625 ETH_FCS_LEN) * 2;
1626 min_tx_space = ALIGN(min_tx_space, 1024);
1627 min_tx_space >>= 10;
1628 /* software strips receive CRC, so leave room for it */
1629 min_rx_space = adapter->max_frame_size;
1630 min_rx_space = ALIGN(min_rx_space, 1024);
1631 min_rx_space >>= 10;
1632
1633 /* If current Tx allocation is less than the min Tx FIFO size,
1634 * and the min Tx FIFO size is less than the current Rx FIFO
1635 * allocation, take space away from current Rx allocation */
1636 if (tx_space < min_tx_space &&
1637 ((min_tx_space - tx_space) < pba)) {
1638 pba = pba - (min_tx_space - tx_space);
1639
1640 /* if short on rx space, rx wins and must trump tx
1641 * adjustment */
1642 if (pba < min_rx_space)
1643 pba = min_rx_space;
1644 }
2d064c06 1645 wr32(E1000_PBA, pba);
9d5c8243 1646 }
9d5c8243
AK		 1647
1648 /* flow control settings */
1649 /* The high water mark must be low enough to fit one full frame
1650 * (or the size used for early receive) above it in the Rx FIFO.
1651 * Set it to the lower of:
1652 * - 90% of the Rx FIFO size, or
1653 * - the full Rx FIFO size minus one full frame */
1654 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1655 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1656
d405ea3e
AD		 1657 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1658 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1659 fc->pause_time = 0xFFFF;
1660 fc->send_xon = 1;
0cce119a 1661 fc->current_mode = fc->requested_mode;
9d5c8243 1662
4ae196df
AD		 1663 /* disable receive for all VFs and wait one second */
1664 if (adapter->vfs_allocated_count) {
1665 int i;
1666 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1667 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1668
1669 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1670 igb_ping_all_vfs(adapter);
4ae196df
AD		 1671
1672 /* disable transmits and receives */
1673 wr32(E1000_VFRE, 0);
1674 wr32(E1000_VFTE, 0);
1675 }
1676
9d5c8243 1677 /* Allow time for pending master requests to run */
330a6d6a 1678 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1679 wr32(E1000_WUC, 0);
1680
330a6d6a 1681 if (hw->mac.ops.init_hw(hw))
090b1795 1682 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4
CW		 1683 if (hw->mac.type > e1000_82580) {
1684 if (adapter->flags & IGB_FLAG_DMAC) {
1685 u32 reg;
1686
1687 /*
1688 * DMA Coalescing high water mark needs to be higher
1689 * than * the * Rx threshold. The Rx threshold is
1690 * currently * pba - 6, so we * should use a high water
1691 * mark of pba * - 4. */
1692 hwm = (pba - 4) << 10;
1693
1694 reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT)
1695 & E1000_DMACR_DMACTHR_MASK);
1696
1697 /* transition to L0x or L1 if available..*/
1698 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1699
1700 /* watchdog timer= +-1000 usec in 32usec intervals */
1701 reg |= (1000 >> 5);
1702 wr32(E1000_DMACR, reg);
1703
1704 /* no lower threshold to disable coalescing(smart fifb)
1705 * -UTRESH=0*/
1706 wr32(E1000_DMCRTRH, 0);
1707
1708 /* set hwm to PBA - 2 * max frame size */
1709 wr32(E1000_FCRTC, hwm);
1710
1711 /*
1712 * This sets the time to wait before requesting tran-
1713 * sition to * low power state to number of usecs needed
1714 * to receive 1 512 * byte frame at gigabit line rate
1715 */
1716 reg = rd32(E1000_DMCTLX);
1717 reg |= IGB_DMCTLX_DCFLUSH_DIS;
1718
1719 /* Delay 255 usec before entering Lx state. */
1720 reg |= 0xFF;
1721 wr32(E1000_DMCTLX, reg);
1722
1723 /* free space in Tx packet buffer to wake from DMAC */
1724 wr32(E1000_DMCTXTH,
1725 (IGB_MIN_TXPBSIZE -
1726 (IGB_TX_BUF_4096 + adapter->max_frame_size))
1727 >> 6);
1728
1729 /* make low power state decision controlled by DMAC */
1730 reg = rd32(E1000_PCIEMISC);
1731 reg |= E1000_PCIEMISC_LX_DECISION;
1732 wr32(E1000_PCIEMISC, reg);
1733 } /* end if IGB_FLAG_DMAC set */
1734 }
55cac248
AD		 1735 if (hw->mac.type == e1000_82580) {
1736 u32 reg = rd32(E1000_PCIEMISC);
1737 wr32(E1000_PCIEMISC,
1738 reg & ~E1000_PCIEMISC_LX_DECISION);
1739 }
88a268c1
NN		 1740 if (!netif_running(adapter->netdev))
1741 igb_power_down_link(adapter);
1742
9d5c8243
AK		 1743 igb_update_mng_vlan(adapter);
1744
1745 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1746 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1747
330a6d6a 1748 igb_get_phy_info(hw);
9d5c8243
AK		 1749}
1750
b2cb09b1
JP		 1751static u32 igb_fix_features(struct net_device *netdev, u32 features)
1752{
1753 /*
1754 * Since there is no support for separate rx/tx vlan accel
1755 * enable/disable make sure tx flag is always in same state as rx.
1756 */
1757 if (features & NETIF_F_HW_VLAN_RX)
1758 features |= NETIF_F_HW_VLAN_TX;
1759 else
1760 features &= ~NETIF_F_HW_VLAN_TX;
1761
1762 return features;
1763}
1764
ac52caa3
MM		 1765static int igb_set_features(struct net_device *netdev, u32 features)
1766{
1767 struct igb_adapter *adapter = netdev_priv(netdev);
1768 int i;
b2cb09b1 1769 u32 changed = netdev->features ^ features;
ac52caa3
MM		 1770
1771 for (i = 0; i < adapter->num_rx_queues; i++) {
1772 if (features & NETIF_F_RXCSUM)
1773 adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM;
1774 else
1775 adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM;
1776 }
1777
b2cb09b1
JP		 1778 if (changed & NETIF_F_HW_VLAN_RX)
1779 igb_vlan_mode(netdev, features);
1780
ac52caa3
MM		 1781 return 0;
1782}
1783
2e5c6922 1784static const struct net_device_ops igb_netdev_ops = {
559e9c49 1785 .ndo_open = igb_open,
2e5c6922 1786 .ndo_stop = igb_close,
00829823 1787 .ndo_start_xmit = igb_xmit_frame_adv,
12dcd86b 1788 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1789 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1790 .ndo_set_mac_address = igb_set_mac,
1791 .ndo_change_mtu = igb_change_mtu,
1792 .ndo_do_ioctl = igb_ioctl,
1793 .ndo_tx_timeout = igb_tx_timeout,
1794 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1795 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1796 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1797 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1798 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1799 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1800 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1801#ifdef CONFIG_NET_POLL_CONTROLLER
1802 .ndo_poll_controller = igb_netpoll,
1803#endif
b2cb09b1
JP		 1804 .ndo_fix_features = igb_fix_features,
1805 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1806};
1807
9d5c8243
AK		 1808/**
1809 * igb_probe - Device Initialization Routine
1810 * @pdev: PCI device information struct
1811 * @ent: entry in igb_pci_tbl
1812 *
1813 * Returns 0 on success, negative on failure
1814 *
1815 * igb_probe initializes an adapter identified by a pci_dev structure.
1816 * The OS initialization, configuring of the adapter private structure,
1817 * and a hardware reset occur.
1818 **/
1819static int __devinit igb_probe(struct pci_dev *pdev,
1820 const struct pci_device_id *ent)
1821{
1822 struct net_device *netdev;
1823 struct igb_adapter *adapter;
1824 struct e1000_hw *hw;
4337e993 1825 u16 eeprom_data = 0;
9835fd73 1826 s32 ret_val;
4337e993 1827 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1828 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1829 unsigned long mmio_start, mmio_len;
2d6a5e95 1830 int err, pci_using_dac;
9d5c8243 1831 u16 eeprom_apme_mask = IGB_EEPROM_APME;
9835fd73 1832 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1833
bded64a7
AG		 1834 /* Catch broken hardware that put the wrong VF device ID in
1835 * the PCIe SR-IOV capability.
1836 */
1837 if (pdev->is_virtfn) {
1838 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1839 pci_name(pdev), pdev->vendor, pdev->device);
1840 return -EINVAL;
1841 }
1842
aed5dec3 1843 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1844 if (err)
1845 return err;
1846
1847 pci_using_dac = 0;
59d71989 1848 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1849 if (!err) {
59d71989 1850 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1851 if (!err)
1852 pci_using_dac = 1;
1853 } else {
59d71989 1854 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1855 if (err) {
59d71989 1856 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1857 if (err) {
1858 dev_err(&pdev->dev, "No usable DMA "
1859 "configuration, aborting\n");
1860 goto err_dma;
1861 }
1862 }
1863 }
1864
aed5dec3
AD		 1865 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1866 IORESOURCE_MEM),
1867 igb_driver_name);
9d5c8243
AK		 1868 if (err)
1869 goto err_pci_reg;
1870
19d5afd4 1871 pci_enable_pcie_error_reporting(pdev);
40a914fa 1872
9d5c8243 1873 pci_set_master(pdev);
c682fc23 1874 pci_save_state(pdev);
9d5c8243
AK		 1875
1876 err = -ENOMEM;
1bfaf07b
AD		 1877 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1878 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1879 if (!netdev)
1880 goto err_alloc_etherdev;
1881
1882 SET_NETDEV_DEV(netdev, &pdev->dev);
1883
1884 pci_set_drvdata(pdev, netdev);
1885 adapter = netdev_priv(netdev);
1886 adapter->netdev = netdev;
1887 adapter->pdev = pdev;
1888 hw = &adapter->hw;
1889 hw->back = adapter;
1890 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1891
1892 mmio_start = pci_resource_start(pdev, 0);
1893 mmio_len = pci_resource_len(pdev, 0);
1894
1895 err = -EIO;
28b0759c
AD		 1896 hw->hw_addr = ioremap(mmio_start, mmio_len);
1897 if (!hw->hw_addr)
9d5c8243
AK		 1898 goto err_ioremap;
1899
2e5c6922 1900 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1901 igb_set_ethtool_ops(netdev);
9d5c8243 1902 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1903
1904 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1905
1906 netdev->mem_start = mmio_start;
1907 netdev->mem_end = mmio_start + mmio_len;
1908
9d5c8243
AK		 1909 /* PCI config space info */
1910 hw->vendor_id = pdev->vendor;
1911 hw->device_id = pdev->device;
1912 hw->revision_id = pdev->revision;
1913 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1914 hw->subsystem_device_id = pdev->subsystem_device;
1915
9d5c8243
AK		 1916 /* Copy the default MAC, PHY and NVM function pointers */
1917 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1918 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1919 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1920 /* Initialize skew-specific constants */
1921 err = ei->get_invariants(hw);
1922 if (err)
450c87c8 1923 goto err_sw_init;
9d5c8243 1924
450c87c8 1925 /* setup the private structure */
9d5c8243
AK		 1926 err = igb_sw_init(adapter);
1927 if (err)
1928 goto err_sw_init;
1929
1930 igb_get_bus_info_pcie(hw);
1931
1932 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1933
1934 /* Copper options */
1935 if (hw->phy.media_type == e1000_media_type_copper) {
1936 hw->phy.mdix = AUTO_ALL_MODES;
1937 hw->phy.disable_polarity_correction = false;
1938 hw->phy.ms_type = e1000_ms_hw_default;
1939 }
1940
1941 if (igb_check_reset_block(hw))
1942 dev_info(&pdev->dev,
1943 "PHY reset is blocked due to SOL/IDER session.\n");
1944
ac52caa3 1945 netdev->hw_features = NETIF_F_SG |
7d8eb29e 1946 NETIF_F_IP_CSUM |
ac52caa3
MM		 1947 NETIF_F_IPV6_CSUM |
1948 NETIF_F_TSO |
1949 NETIF_F_TSO6 |
b2cb09b1
JP		 1950 NETIF_F_RXCSUM |
1951 NETIF_F_HW_VLAN_RX;
ac52caa3
MM		 1952
1953 netdev->features = netdev->hw_features |
9d5c8243 1954 NETIF_F_HW_VLAN_TX |
9d5c8243
AK		 1955 NETIF_F_HW_VLAN_FILTER;
1956
48f29ffc
JK		 1957 netdev->vlan_features |= NETIF_F_TSO;
1958 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1959 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1960 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1961 netdev->vlan_features |= NETIF_F_SG;
1962
7b872a55 1963 if (pci_using_dac) {
9d5c8243 1964 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1965 netdev->vlan_features |= NETIF_F_HIGHDMA;
1966 }
9d5c8243 1967
ac52caa3
MM		 1968 if (hw->mac.type >= e1000_82576) {
1969 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1970 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 1971 }
b9473560 1972
01789349
JP		 1973 netdev->priv_flags |= IFF_UNICAST_FLT;
1974
330a6d6a 1975 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1976
1977 /* before reading the NVM, reset the controller to put the device in a
1978 * known good starting state */
1979 hw->mac.ops.reset_hw(hw);
1980
1981 /* make sure the NVM is good */
4322e561 1982 if (hw->nvm.ops.validate(hw) < 0) {
9d5c8243
AK		 1983 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1984 err = -EIO;
1985 goto err_eeprom;
1986 }
1987
1988 /* copy the MAC address out of the NVM */
1989 if (hw->mac.ops.read_mac_addr(hw))
1990 dev_err(&pdev->dev, "NVM Read Error\n");
1991
1992 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1993 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1994
1995 if (!is_valid_ether_addr(netdev->perm_addr)) {
1996 dev_err(&pdev->dev, "Invalid MAC Address\n");
1997 err = -EIO;
1998 goto err_eeprom;
1999 }
2000
c061b18d 2001 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2002 (unsigned long) adapter);
c061b18d 2003 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2004 (unsigned long) adapter);
9d5c8243
AK		 2005
2006 INIT_WORK(&adapter->reset_task, igb_reset_task);
2007 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2008
450c87c8 2009 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2010 adapter->fc_autoneg = true;
2011 hw->mac.autoneg = true;
2012 hw->phy.autoneg_advertised = 0x2f;
2013
0cce119a
AD		 2014 hw->fc.requested_mode = e1000_fc_default;
2015 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2016
9d5c8243
AK		 2017 igb_validate_mdi_setting(hw);
2018
9d5c8243
AK		 2019 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2020 * enable the ACPI Magic Packet filter
2021 */
2022
a2cf8b6c 2023 if (hw->bus.func == 0)
312c75ae 2024 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6d337dce 2025 else if (hw->mac.type >= e1000_82580)
55cac248
AD		 2026 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2027 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2028 &eeprom_data);
a2cf8b6c
AD		 2029 else if (hw->bus.func == 1)
2030 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 2031
2032 if (eeprom_data & eeprom_apme_mask)
2033 adapter->eeprom_wol |= E1000_WUFC_MAG;
2034
2035 /* now that we have the eeprom settings, apply the special cases where
2036 * the eeprom may be wrong or the board simply won't support wake on
2037 * lan on a particular port */
2038 switch (pdev->device) {
2039 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2040 adapter->eeprom_wol = 0;
2041 break;
2042 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2043 case E1000_DEV_ID_82576_FIBER:
2044 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2045 /* Wake events only supported on port A for dual fiber
2046 * regardless of eeprom setting */
2047 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2048 adapter->eeprom_wol = 0;
2049 break;
c8ea5ea9 2050 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2051 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2052 /* if quad port adapter, disable WoL on all but port A */
2053 if (global_quad_port_a != 0)
2054 adapter->eeprom_wol = 0;
2055 else
2056 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2057 /* Reset for multiple quad port adapters */
2058 if (++global_quad_port_a == 4)
2059 global_quad_port_a = 0;
2060 break;
9d5c8243
AK		 2061 }
2062
2063 /* initialize the wol settings based on the eeprom settings */
2064 adapter->wol = adapter->eeprom_wol;
e1b86d84 2065 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 2066
2067 /* reset the hardware with the new settings */
2068 igb_reset(adapter);
2069
2070 /* let the f/w know that the h/w is now under the control of the
2071 * driver. */
2072 igb_get_hw_control(adapter);
2073
9d5c8243
AK		 2074 strcpy(netdev->name, "eth%d");
2075 err = register_netdev(netdev);
2076 if (err)
2077 goto err_register;
2078
b2cb09b1
JP		 2079 igb_vlan_mode(netdev, netdev->features);
2080
b168dfc5
JB		 2081 /* carrier off reporting is important to ethtool even BEFORE open */
2082 netif_carrier_off(netdev);
2083
421e02f0 2084#ifdef CONFIG_IGB_DCA
bbd98fe4 2085 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2086 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2087 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2088 igb_setup_dca(adapter);
2089 }
fe4506b6 2090
38c845c7 2091#endif
673b8b70
AB		 2092 /* do hw tstamp init after resetting */
2093 igb_init_hw_timer(adapter);
2094
9d5c8243
AK		 2095 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2096 /* print bus type/speed/width info */
7c510e4b 2097 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2098 netdev->name,
559e9c49 2099 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2100 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2101 "unknown"),
59c3de89
AD		 2102 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2103 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2104 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2105 "unknown"),
7c510e4b 2106 netdev->dev_addr);
9d5c8243 2107
9835fd73
CW		 2108 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2109 if (ret_val)
2110 strcpy(part_str, "Unknown");
2111 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2112 dev_info(&pdev->dev,
2113 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2114 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2115 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2116 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2117 switch (hw->mac.type) {
2118 case e1000_i350:
2119 igb_set_eee_i350(hw);
2120 break;
2121 default:
2122 break;
2123 }
9d5c8243
AK		 2124 return 0;
2125
2126err_register:
2127 igb_release_hw_control(adapter);
2128err_eeprom:
2129 if (!igb_check_reset_block(hw))
f5f4cf08 2130 igb_reset_phy(hw);
9d5c8243
AK		 2131
2132 if (hw->flash_address)
2133 iounmap(hw->flash_address);
9d5c8243 2134err_sw_init:
047e0030 2135 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2136 iounmap(hw->hw_addr);
2137err_ioremap:
2138 free_netdev(netdev);
2139err_alloc_etherdev:
559e9c49
AD		 2140 pci_release_selected_regions(pdev,
2141 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2142err_pci_reg:
2143err_dma:
2144 pci_disable_device(pdev);
2145 return err;
2146}
2147
2148/**
2149 * igb_remove - Device Removal Routine
2150 * @pdev: PCI device information struct
2151 *
2152 * igb_remove is called by the PCI subsystem to alert the driver
2153 * that it should release a PCI device. The could be caused by a
2154 * Hot-Plug event, or because the driver is going to be removed from
2155 * memory.
2156 **/
2157static void __devexit igb_remove(struct pci_dev *pdev)
2158{
2159 struct net_device *netdev = pci_get_drvdata(pdev);
2160 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2161 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2162
760141a5
TH		 2163 /*
2164 * The watchdog timer may be rescheduled, so explicitly
2165 * disable watchdog from being rescheduled.
2166 */
9d5c8243
AK		 2167 set_bit(__IGB_DOWN, &adapter->state);
2168 del_timer_sync(&adapter->watchdog_timer);
2169 del_timer_sync(&adapter->phy_info_timer);
2170
760141a5
TH		 2171 cancel_work_sync(&adapter->reset_task);
2172 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2173
421e02f0 2174#ifdef CONFIG_IGB_DCA
7dfc16fa 2175 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2176 dev_info(&pdev->dev, "DCA disabled\n");
2177 dca_remove_requester(&pdev->dev);
7dfc16fa 2178 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2179 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2180 }
2181#endif
2182
9d5c8243
AK		 2183 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2184 * would have already happened in close and is redundant. */
2185 igb_release_hw_control(adapter);
2186
2187 unregister_netdev(netdev);
2188
047e0030 2189 igb_clear_interrupt_scheme(adapter);
9d5c8243 2190
37680117
AD		 2191#ifdef CONFIG_PCI_IOV
2192 /* reclaim resources allocated to VFs */
2193 if (adapter->vf_data) {
2194 /* disable iov and allow time for transactions to clear */
2195 pci_disable_sriov(pdev);
2196 msleep(500);
2197
2198 kfree(adapter->vf_data);
2199 adapter->vf_data = NULL;
2200 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2201 wrfl();
37680117
AD		 2202 msleep(100);
2203 dev_info(&pdev->dev, "IOV Disabled\n");
2204 }
2205#endif
559e9c49 2206
28b0759c
AD		 2207 iounmap(hw->hw_addr);
2208 if (hw->flash_address)
2209 iounmap(hw->flash_address);
559e9c49
AD		 2210 pci_release_selected_regions(pdev,
2211 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2212
2213 free_netdev(netdev);
2214
19d5afd4 2215 pci_disable_pcie_error_reporting(pdev);
40a914fa 2216
9d5c8243
AK		 2217 pci_disable_device(pdev);
2218}
2219
a6b623e0
AD		 2220/**
2221 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2222 * @adapter: board private structure to initialize
2223 *
2224 * This function initializes the vf specific data storage and then attempts to
2225 * allocate the VFs. The reason for ordering it this way is because it is much
2226 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2227 * the memory for the VFs.
2228 **/
2229static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2230{
2231#ifdef CONFIG_PCI_IOV
2232 struct pci_dev *pdev = adapter->pdev;
2233
a6b623e0
AD		 2234 if (adapter->vfs_allocated_count) {
2235 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2236 sizeof(struct vf_data_storage),
2237 GFP_KERNEL);
2238 /* if allocation failed then we do not support SR-IOV */
2239 if (!adapter->vf_data) {
2240 adapter->vfs_allocated_count = 0;
2241 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2242 "Data Storage\n");
2243 }
2244 }
2245
2246 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
2247 kfree(adapter->vf_data);
2248 adapter->vf_data = NULL;
2249#endif /* CONFIG_PCI_IOV */
2250 adapter->vfs_allocated_count = 0;
2251#ifdef CONFIG_PCI_IOV
2252 } else {
2253 unsigned char mac_addr[ETH_ALEN];
2254 int i;
2255 dev_info(&pdev->dev, "%d vfs allocated\n",
2256 adapter->vfs_allocated_count);
2257 for (i = 0; i < adapter->vfs_allocated_count; i++) {
2258 random_ether_addr(mac_addr);
2259 igb_set_vf_mac(adapter, i, mac_addr);
2260 }
831ec0b4
CW		 2261 /* DMA Coalescing is not supported in IOV mode. */
2262 if (adapter->flags & IGB_FLAG_DMAC)
2263 adapter->flags &= ~IGB_FLAG_DMAC;
a6b623e0
AD		 2264 }
2265#endif /* CONFIG_PCI_IOV */
2266}
2267
115f459a
AD		 2268
2269/**
2270 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2271 * @adapter: board private structure to initialize
2272 *
2273 * igb_init_hw_timer initializes the function pointer and values for the hw
2274 * timer found in hardware.
2275 **/
2276static void igb_init_hw_timer(struct igb_adapter *adapter)
2277{
2278 struct e1000_hw *hw = &adapter->hw;
2279
2280 switch (hw->mac.type) {
d2ba2ed8 2281 case e1000_i350:
55cac248
AD		 2282 case e1000_82580:
2283 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2284 adapter->cycles.read = igb_read_clock;
2285 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2286 adapter->cycles.mult = 1;
2287 /*
2288 * The 82580 timesync updates the system timer every 8ns by 8ns
2289 * and the value cannot be shifted. Instead we need to shift
2290 * the registers to generate a 64bit timer value. As a result
2291 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2292 * 24 in order to generate a larger value for synchronization.
2293 */
2294 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2295 /* disable system timer temporarily by setting bit 31 */
2296 wr32(E1000_TSAUXC, 0x80000000);
2297 wrfl();
2298
2299 /* Set registers so that rollover occurs soon to test this. */
2300 wr32(E1000_SYSTIMR, 0x00000000);
2301 wr32(E1000_SYSTIML, 0x80000000);
2302 wr32(E1000_SYSTIMH, 0x000000FF);
2303 wrfl();
2304
2305 /* enable system timer by clearing bit 31 */
2306 wr32(E1000_TSAUXC, 0x0);
2307 wrfl();
2308
2309 timecounter_init(&adapter->clock,
2310 &adapter->cycles,
2311 ktime_to_ns(ktime_get_real()));
2312 /*
2313 * Synchronize our NIC clock against system wall clock. NIC
2314 * time stamp reading requires ~3us per sample, each sample
2315 * was pretty stable even under load => only require 10
2316 * samples for each offset comparison.
2317 */
2318 memset(&adapter->compare, 0, sizeof(adapter->compare));
2319 adapter->compare.source = &adapter->clock;
2320 adapter->compare.target = ktime_get_real;
2321 adapter->compare.num_samples = 10;
2322 timecompare_update(&adapter->compare, 0);
2323 break;
115f459a
AD		 2324 case e1000_82576:
2325 /*
2326 * Initialize hardware timer: we keep it running just in case
2327 * that some program needs it later on.
2328 */
2329 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2330 adapter->cycles.read = igb_read_clock;
2331 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2332 adapter->cycles.mult = 1;
2333 /**
2334 * Scale the NIC clock cycle by a large factor so that
2335 * relatively small clock corrections can be added or
25985edc 2336 * subtracted at each clock tick. The drawbacks of a large
115f459a
AD		 2337 * factor are a) that the clock register overflows more quickly
2338 * (not such a big deal) and b) that the increment per tick has
2339 * to fit into 24 bits. As a result we need to use a shift of
2340 * 19 so we can fit a value of 16 into the TIMINCA register.
2341 */
2342 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2343 wr32(E1000_TIMINCA,
2344 (1 << E1000_TIMINCA_16NS_SHIFT) |
2345 (16 << IGB_82576_TSYNC_SHIFT));
2346
2347 /* Set registers so that rollover occurs soon to test this. */
2348 wr32(E1000_SYSTIML, 0x00000000);
2349 wr32(E1000_SYSTIMH, 0xFF800000);
2350 wrfl();
2351
2352 timecounter_init(&adapter->clock,
2353 &adapter->cycles,
2354 ktime_to_ns(ktime_get_real()));
2355 /*
2356 * Synchronize our NIC clock against system wall clock. NIC
2357 * time stamp reading requires ~3us per sample, each sample
2358 * was pretty stable even under load => only require 10
2359 * samples for each offset comparison.
2360 */
2361 memset(&adapter->compare, 0, sizeof(adapter->compare));
2362 adapter->compare.source = &adapter->clock;
2363 adapter->compare.target = ktime_get_real;
2364 adapter->compare.num_samples = 10;
2365 timecompare_update(&adapter->compare, 0);
2366 break;
2367 case e1000_82575:
2368 /* 82575 does not support timesync */
2369 default:
2370 break;
2371 }
2372
2373}
2374
9d5c8243
AK		 2375/**
2376 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2377 * @adapter: board private structure to initialize
2378 *
2379 * igb_sw_init initializes the Adapter private data structure.
2380 * Fields are initialized based on PCI device information and
2381 * OS network device settings (MTU size).
2382 **/
2383static int __devinit igb_sw_init(struct igb_adapter *adapter)
2384{
2385 struct e1000_hw *hw = &adapter->hw;
2386 struct net_device *netdev = adapter->netdev;
2387 struct pci_dev *pdev = adapter->pdev;
2388
2389 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2390
68fd9910
AD		 2391 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2392 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 2393 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2394 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2395
153285f9
AD		 2396 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2397 VLAN_HLEN;
9d5c8243
AK		 2398 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2399
12dcd86b 2400 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2401#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2402 switch (hw->mac.type) {
2403 case e1000_82576:
2404 case e1000_i350:
9b082d73
SA		 2405 if (max_vfs > 7) {
2406 dev_warn(&pdev->dev,
2407 "Maximum of 7 VFs per PF, using max\n");
2408 adapter->vfs_allocated_count = 7;
2409 } else
2410 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2411 break;
2412 default:
2413 break;
2414 }
a6b623e0 2415#endif /* CONFIG_PCI_IOV */
a99955fc 2416 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
665c8c8e
WM		 2417 /* i350 cannot do RSS and SR-IOV at the same time */
2418 if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count)
2419 adapter->rss_queues = 1;
a99955fc
AD		 2420
2421 /*
2422 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2423 * then we should combine the queues into a queue pair in order to
2424 * conserve interrupts due to limited supply
2425 */
2426 if ((adapter->rss_queues > 4) ||
2427 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2428 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2429
a6b623e0 2430 /* This call may decrease the number of queues */
047e0030 2431 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2432 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2433 return -ENOMEM;
2434 }
2435
a6b623e0
AD		 2436 igb_probe_vfs(adapter);
2437
9d5c8243
AK		 2438 /* Explicitly disable IRQ since the NIC can be in any state. */
2439 igb_irq_disable(adapter);
2440
831ec0b4
CW		 2441 if (hw->mac.type == e1000_i350)
2442 adapter->flags &= ~IGB_FLAG_DMAC;
2443
9d5c8243
AK		 2444 set_bit(__IGB_DOWN, &adapter->state);
2445 return 0;
2446}
2447
2448/**
2449 * igb_open - Called when a network interface is made active
2450 * @netdev: network interface device structure
2451 *
2452 * Returns 0 on success, negative value on failure
2453 *
2454 * The open entry point is called when a network interface is made
2455 * active by the system (IFF_UP). At this point all resources needed
2456 * for transmit and receive operations are allocated, the interrupt
2457 * handler is registered with the OS, the watchdog timer is started,
2458 * and the stack is notified that the interface is ready.
2459 **/
2460static int igb_open(struct net_device *netdev)
2461{
2462 struct igb_adapter *adapter = netdev_priv(netdev);
2463 struct e1000_hw *hw = &adapter->hw;
2464 int err;
2465 int i;
2466
2467 /* disallow open during test */
2468 if (test_bit(__IGB_TESTING, &adapter->state))
2469 return -EBUSY;
2470
b168dfc5
JB		 2471 netif_carrier_off(netdev);
2472
9d5c8243
AK		 2473 /* allocate transmit descriptors */
2474 err = igb_setup_all_tx_resources(adapter);
2475 if (err)
2476 goto err_setup_tx;
2477
2478 /* allocate receive descriptors */
2479 err = igb_setup_all_rx_resources(adapter);
2480 if (err)
2481 goto err_setup_rx;
2482
88a268c1 2483 igb_power_up_link(adapter);
9d5c8243 2484
9d5c8243
AK		 2485 /* before we allocate an interrupt, we must be ready to handle it.
2486 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2487 * as soon as we call pci_request_irq, so we have to setup our
2488 * clean_rx handler before we do so. */
2489 igb_configure(adapter);
2490
2491 err = igb_request_irq(adapter);
2492 if (err)
2493 goto err_req_irq;
2494
2495 /* From here on the code is the same as igb_up() */
2496 clear_bit(__IGB_DOWN, &adapter->state);
2497
047e0030
AD		 2498 for (i = 0; i < adapter->num_q_vectors; i++) {
2499 struct igb_q_vector *q_vector = adapter->q_vector[i];
2500 napi_enable(&q_vector->napi);
2501 }
9d5c8243
AK		 2502
2503 /* Clear any pending interrupts. */
2504 rd32(E1000_ICR);
844290e5
PW		 2505
2506 igb_irq_enable(adapter);
2507
d4960307
AD		 2508 /* notify VFs that reset has been completed */
2509 if (adapter->vfs_allocated_count) {
2510 u32 reg_data = rd32(E1000_CTRL_EXT);
2511 reg_data |= E1000_CTRL_EXT_PFRSTD;
2512 wr32(E1000_CTRL_EXT, reg_data);
2513 }
2514
d55b53ff
JK		 2515 netif_tx_start_all_queues(netdev);
2516
25568a53
AD		 2517 /* start the watchdog. */
2518 hw->mac.get_link_status = 1;
2519 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2520
2521 return 0;
2522
2523err_req_irq:
2524 igb_release_hw_control(adapter);
88a268c1 2525 igb_power_down_link(adapter);
9d5c8243
AK		 2526 igb_free_all_rx_resources(adapter);
2527err_setup_rx:
2528 igb_free_all_tx_resources(adapter);
2529err_setup_tx:
2530 igb_reset(adapter);
2531
2532 return err;
2533}
2534
2535/**
2536 * igb_close - Disables a network interface
2537 * @netdev: network interface device structure
2538 *
2539 * Returns 0, this is not allowed to fail
2540 *
2541 * The close entry point is called when an interface is de-activated
2542 * by the OS. The hardware is still under the driver's control, but
2543 * needs to be disabled. A global MAC reset is issued to stop the
2544 * hardware, and all transmit and receive resources are freed.
2545 **/
2546static int igb_close(struct net_device *netdev)
2547{
2548 struct igb_adapter *adapter = netdev_priv(netdev);
2549
2550 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2551 igb_down(adapter);
2552
2553 igb_free_irq(adapter);
2554
2555 igb_free_all_tx_resources(adapter);
2556 igb_free_all_rx_resources(adapter);
2557
9d5c8243
AK		 2558 return 0;
2559}
2560
2561/**
2562 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2563 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2564 *
2565 * Return 0 on success, negative on failure
2566 **/
80785298 2567int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2568{
59d71989 2569 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2570 int size;
2571
2572 size = sizeof(struct igb_buffer) * tx_ring->count;
89bf67f1 2573 tx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2574 if (!tx_ring->buffer_info)
2575 goto err;
9d5c8243
AK		 2576
2577 /* round up to nearest 4K */
85e8d004 2578 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2579 tx_ring->size = ALIGN(tx_ring->size, 4096);
2580
59d71989
AD		 2581 tx_ring->desc = dma_alloc_coherent(dev,
2582 tx_ring->size,
2583 &tx_ring->dma,
2584 GFP_KERNEL);
9d5c8243
AK		 2585
2586 if (!tx_ring->desc)
2587 goto err;
2588
9d5c8243
AK		 2589 tx_ring->next_to_use = 0;
2590 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2591 return 0;
2592
2593err:
2594 vfree(tx_ring->buffer_info);
59d71989 2595 dev_err(dev,
9d5c8243
AK		 2596 "Unable to allocate memory for the transmit descriptor ring\n");
2597 return -ENOMEM;
2598}
2599
2600/**
2601 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2602 * (Descriptors) for all queues
2603 * @adapter: board private structure
2604 *
2605 * Return 0 on success, negative on failure
2606 **/
2607static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2608{
439705e1 2609 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2610 int i, err = 0;
2611
2612 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2613 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2614 if (err) {
439705e1 2615 dev_err(&pdev->dev,
9d5c8243
AK		 2616 "Allocation for Tx Queue %u failed\n", i);
2617 for (i--; i >= 0; i--)
3025a446 2618 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2619 break;
2620 }
2621 }
2622
a99955fc 2623 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2624 int r_idx = i % adapter->num_tx_queues;
3025a446 2625 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2626 }
9d5c8243
AK		 2627 return err;
2628}
2629
2630/**
85b430b4
AD		 2631 * igb_setup_tctl - configure the transmit control registers
2632 * @adapter: Board private structure
9d5c8243 2633 **/
d7ee5b3a 2634void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2635{
9d5c8243
AK		 2636 struct e1000_hw *hw = &adapter->hw;
2637 u32 tctl;
9d5c8243 2638
85b430b4
AD		 2639 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2640 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2641
2642 /* Program the Transmit Control Register */
9d5c8243
AK		 2643 tctl = rd32(E1000_TCTL);
2644 tctl &= ~E1000_TCTL_CT;
2645 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2646 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2647
2648 igb_config_collision_dist(hw);
2649
9d5c8243
AK		 2650 /* Enable transmits */
2651 tctl |= E1000_TCTL_EN;
2652
2653 wr32(E1000_TCTL, tctl);
2654}
2655
85b430b4
AD		 2656/**
2657 * igb_configure_tx_ring - Configure transmit ring after Reset
2658 * @adapter: board private structure
2659 * @ring: tx ring to configure
2660 *
2661 * Configure a transmit ring after a reset.
2662 **/
d7ee5b3a
AD		 2663void igb_configure_tx_ring(struct igb_adapter *adapter,
2664 struct igb_ring *ring)
85b430b4
AD		 2665{
2666 struct e1000_hw *hw = &adapter->hw;
a74420e0 2667 u32 txdctl = 0;
85b430b4
AD		 2668 u64 tdba = ring->dma;
2669 int reg_idx = ring->reg_idx;
2670
2671 /* disable the queue */
a74420e0 2672 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2673 wrfl();
2674 mdelay(10);
2675
2676 wr32(E1000_TDLEN(reg_idx),
2677 ring->count * sizeof(union e1000_adv_tx_desc));
2678 wr32(E1000_TDBAL(reg_idx),
2679 tdba & 0x00000000ffffffffULL);
2680 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2681
fce99e34
AD		 2682 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2683 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2684 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2685 writel(0, ring->tail);
85b430b4
AD		 2686
2687 txdctl |= IGB_TX_PTHRESH;
2688 txdctl |= IGB_TX_HTHRESH << 8;
2689 txdctl |= IGB_TX_WTHRESH << 16;
2690
2691 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2692 wr32(E1000_TXDCTL(reg_idx), txdctl);
2693}
2694
2695/**
2696 * igb_configure_tx - Configure transmit Unit after Reset
2697 * @adapter: board private structure
2698 *
2699 * Configure the Tx unit of the MAC after a reset.
2700 **/
2701static void igb_configure_tx(struct igb_adapter *adapter)
2702{
2703 int i;
2704
2705 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2706 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2707}
2708
9d5c8243
AK		 2709/**
2710 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2711 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2712 *
2713 * Returns 0 on success, negative on failure
2714 **/
80785298 2715int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2716{
59d71989 2717 struct device *dev = rx_ring->dev;
9d5c8243
AK		 2718 int size, desc_len;
2719
2720 size = sizeof(struct igb_buffer) * rx_ring->count;
89bf67f1 2721 rx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2722 if (!rx_ring->buffer_info)
2723 goto err;
9d5c8243
AK		 2724
2725 desc_len = sizeof(union e1000_adv_rx_desc);
2726
2727 /* Round up to nearest 4K */
2728 rx_ring->size = rx_ring->count * desc_len;
2729 rx_ring->size = ALIGN(rx_ring->size, 4096);
2730
59d71989
AD		 2731 rx_ring->desc = dma_alloc_coherent(dev,
2732 rx_ring->size,
2733 &rx_ring->dma,
2734 GFP_KERNEL);
9d5c8243
AK		 2735
2736 if (!rx_ring->desc)
2737 goto err;
2738
2739 rx_ring->next_to_clean = 0;
2740 rx_ring->next_to_use = 0;
9d5c8243 2741
9d5c8243
AK		 2742 return 0;
2743
2744err:
2745 vfree(rx_ring->buffer_info);
439705e1 2746 rx_ring->buffer_info = NULL;
59d71989
AD		 2747 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2748 " ring\n");
9d5c8243
AK		 2749 return -ENOMEM;
2750}
2751
2752/**
2753 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2754 * (Descriptors) for all queues
2755 * @adapter: board private structure
2756 *
2757 * Return 0 on success, negative on failure
2758 **/
2759static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2760{
439705e1 2761 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2762 int i, err = 0;
2763
2764 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2765 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2766 if (err) {
439705e1 2767 dev_err(&pdev->dev,
9d5c8243
AK		 2768 "Allocation for Rx Queue %u failed\n", i);
2769 for (i--; i >= 0; i--)
3025a446 2770 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2771 break;
2772 }
2773 }
2774
2775 return err;
2776}
2777
06cf2666
AD		 2778/**
2779 * igb_setup_mrqc - configure the multiple receive queue control registers
2780 * @adapter: Board private structure
2781 **/
2782static void igb_setup_mrqc(struct igb_adapter *adapter)
2783{
2784 struct e1000_hw *hw = &adapter->hw;
2785 u32 mrqc, rxcsum;
2786 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2787 union e1000_reta {
2788 u32 dword;
2789 u8 bytes[4];
2790 } reta;
2791 static const u8 rsshash[40] = {
2792 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2793 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2794 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2795 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2796
2797 /* Fill out hash function seeds */
2798 for (j = 0; j < 10; j++) {
2799 u32 rsskey = rsshash[(j * 4)];
2800 rsskey |= rsshash[(j * 4) + 1] << 8;
2801 rsskey |= rsshash[(j * 4) + 2] << 16;
2802 rsskey |= rsshash[(j * 4) + 3] << 24;
2803 array_wr32(E1000_RSSRK(0), j, rsskey);
2804 }
2805
a99955fc 2806 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2807
2808 if (adapter->vfs_allocated_count) {
2809 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2810 switch (hw->mac.type) {
d2ba2ed8 2811 case e1000_i350:
55cac248
AD		 2812 case e1000_82580:
2813 num_rx_queues = 1;
2814 shift = 0;
2815 break;
06cf2666
AD		 2816 case e1000_82576:
2817 shift = 3;
2818 num_rx_queues = 2;
2819 break;
2820 case e1000_82575:
2821 shift = 2;
2822 shift2 = 6;
2823 default:
2824 break;
2825 }
2826 } else {
2827 if (hw->mac.type == e1000_82575)
2828 shift = 6;
2829 }
2830
2831 for (j = 0; j < (32 * 4); j++) {
2832 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2833 if (shift2)
2834 reta.bytes[j & 3] |= num_rx_queues << shift2;
2835 if ((j & 3) == 3)
2836 wr32(E1000_RETA(j >> 2), reta.dword);
2837 }
2838
2839 /*
2840 * Disable raw packet checksumming so that RSS hash is placed in
2841 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2842 * offloads as they are enabled by default
2843 */
2844 rxcsum = rd32(E1000_RXCSUM);
2845 rxcsum |= E1000_RXCSUM_PCSD;
2846
2847 if (adapter->hw.mac.type >= e1000_82576)
2848 /* Enable Receive Checksum Offload for SCTP */
2849 rxcsum |= E1000_RXCSUM_CRCOFL;
2850
2851 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2852 wr32(E1000_RXCSUM, rxcsum);
2853
2854 /* If VMDq is enabled then we set the appropriate mode for that, else
2855 * we default to RSS so that an RSS hash is calculated per packet even
2856 * if we are only using one queue */
2857 if (adapter->vfs_allocated_count) {
2858 if (hw->mac.type > e1000_82575) {
2859 /* Set the default pool for the PF's first queue */
2860 u32 vtctl = rd32(E1000_VT_CTL);
2861 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2862 E1000_VT_CTL_DISABLE_DEF_POOL);
2863 vtctl |= adapter->vfs_allocated_count <<
2864 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2865 wr32(E1000_VT_CTL, vtctl);
2866 }
a99955fc 2867 if (adapter->rss_queues > 1)
06cf2666
AD		 2868 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2869 else
2870 mrqc = E1000_MRQC_ENABLE_VMDQ;
2871 } else {
2872 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2873 }
2874 igb_vmm_control(adapter);
2875
4478a9cd
AD		 2876 /*
2877 * Generate RSS hash based on TCP port numbers and/or
2878 * IPv4/v6 src and dst addresses since UDP cannot be
2879 * hashed reliably due to IP fragmentation
2880 */
2881 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2882 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2883 E1000_MRQC_RSS_FIELD_IPV6 |
2884 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2885 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666
AD		 2886
2887 wr32(E1000_MRQC, mrqc);
2888}
2889
9d5c8243
AK		 2890/**
2891 * igb_setup_rctl - configure the receive control registers
2892 * @adapter: Board private structure
2893 **/
d7ee5b3a 2894void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2895{
2896 struct e1000_hw *hw = &adapter->hw;
2897 u32 rctl;
9d5c8243
AK		 2898
2899 rctl = rd32(E1000_RCTL);
2900
2901 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2902 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2903
69d728ba 2904 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2905 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2906
87cb7e8c
AK		 2907 /*
2908 * enable stripping of CRC. It's unlikely this will break BMC
2909 * redirection as it did with e1000. Newer features require
2910 * that the HW strips the CRC.
73cd78f1 2911 */
87cb7e8c 2912 rctl |= E1000_RCTL_SECRC;
9d5c8243 2913
559e9c49 2914 /* disable store bad packets and clear size bits. */
ec54d7d6 2915 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2916
6ec43fe6
AD		 2917 /* enable LPE to prevent packets larger than max_frame_size */
2918 rctl |= E1000_RCTL_LPE;
9d5c8243 2919
952f72a8
AD		 2920 /* disable queue 0 to prevent tail write w/o re-config */
2921 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2922
e1739522
AD		 2923 /* Attention!!! For SR-IOV PF driver operations you must enable
2924 * queue drop for all VF and PF queues to prevent head of line blocking
2925 * if an un-trusted VF does not provide descriptors to hardware.
2926 */
2927 if (adapter->vfs_allocated_count) {
e1739522
AD		 2928 /* set all queue drop enable bits */
2929 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2930 }
2931
9d5c8243
AK		 2932 wr32(E1000_RCTL, rctl);
2933}
2934
7d5753f0
AD		 2935static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2936 int vfn)
2937{
2938 struct e1000_hw *hw = &adapter->hw;
2939 u32 vmolr;
2940
2941 /* if it isn't the PF check to see if VFs are enabled and
2942 * increase the size to support vlan tags */
2943 if (vfn < adapter->vfs_allocated_count &&
2944 adapter->vf_data[vfn].vlans_enabled)
2945 size += VLAN_TAG_SIZE;
2946
2947 vmolr = rd32(E1000_VMOLR(vfn));
2948 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2949 vmolr |= size | E1000_VMOLR_LPE;
2950 wr32(E1000_VMOLR(vfn), vmolr);
2951
2952 return 0;
2953}
2954
e1739522
AD		 2955/**
2956 * igb_rlpml_set - set maximum receive packet size
2957 * @adapter: board private structure
2958 *
2959 * Configure maximum receivable packet size.
2960 **/
2961static void igb_rlpml_set(struct igb_adapter *adapter)
2962{
153285f9 2963 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 2964 struct e1000_hw *hw = &adapter->hw;
2965 u16 pf_id = adapter->vfs_allocated_count;
2966
e1739522
AD		 2967 if (pf_id) {
2968 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 2969 /*
2970 * If we're in VMDQ or SR-IOV mode, then set global RLPML
2971 * to our max jumbo frame size, in case we need to enable
2972 * jumbo frames on one of the rings later.
2973 * This will not pass over-length frames into the default
2974 * queue because it's gated by the VMOLR.RLPML.
2975 */
7d5753f0 2976 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2977 }
2978
2979 wr32(E1000_RLPML, max_frame_size);
2980}
2981
8151d294
WM		 2982static inline void igb_set_vmolr(struct igb_adapter *adapter,
2983 int vfn, bool aupe)
7d5753f0
AD		 2984{
2985 struct e1000_hw *hw = &adapter->hw;
2986 u32 vmolr;
2987
2988 /*
2989 * This register exists only on 82576 and newer so if we are older then
2990 * we should exit and do nothing
2991 */
2992 if (hw->mac.type < e1000_82576)
2993 return;
2994
2995 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2996 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2997 if (aupe)
2998 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2999 else
3000 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3001
3002 /* clear all bits that might not be set */
3003 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3004
a99955fc 3005 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3006 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3007 /*
3008 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3009 * multicast packets
3010 */
3011 if (vfn <= adapter->vfs_allocated_count)
3012 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3013
3014 wr32(E1000_VMOLR(vfn), vmolr);
3015}
3016
85b430b4
AD		 3017/**
3018 * igb_configure_rx_ring - Configure a receive ring after Reset
3019 * @adapter: board private structure
3020 * @ring: receive ring to be configured
3021 *
3022 * Configure the Rx unit of the MAC after a reset.
3023 **/
d7ee5b3a
AD		 3024void igb_configure_rx_ring(struct igb_adapter *adapter,
3025 struct igb_ring *ring)
85b430b4
AD		 3026{
3027 struct e1000_hw *hw = &adapter->hw;
3028 u64 rdba = ring->dma;
3029 int reg_idx = ring->reg_idx;
a74420e0 3030 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3031
3032 /* disable the queue */
a74420e0 3033 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3034
3035 /* Set DMA base address registers */
3036 wr32(E1000_RDBAL(reg_idx),
3037 rdba & 0x00000000ffffffffULL);
3038 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3039 wr32(E1000_RDLEN(reg_idx),
3040 ring->count * sizeof(union e1000_adv_rx_desc));
3041
3042 /* initialize head and tail */
fce99e34
AD		 3043 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
3044 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3045 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3046 writel(0, ring->tail);
85b430b4 3047
952f72a8 3048 /* set descriptor configuration */
44390ca6 3049 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
952f72a8 3050#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
44390ca6 3051 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3052#else
44390ca6 3053 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3054#endif
44390ca6 3055 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
757b77e2
NN		 3056 if (hw->mac.type == e1000_82580)
3057 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3058 /* Only set Drop Enable if we are supporting multiple queues */
3059 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3060 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3061
3062 wr32(E1000_SRRCTL(reg_idx), srrctl);
3063
7d5753f0 3064 /* set filtering for VMDQ pools */
8151d294 3065 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3066
85b430b4
AD		 3067 rxdctl |= IGB_RX_PTHRESH;
3068 rxdctl |= IGB_RX_HTHRESH << 8;
3069 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3070
3071 /* enable receive descriptor fetching */
3072 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3073 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3074}
3075
9d5c8243
AK		 3076/**
3077 * igb_configure_rx - Configure receive Unit after Reset
3078 * @adapter: board private structure
3079 *
3080 * Configure the Rx unit of the MAC after a reset.
3081 **/
3082static void igb_configure_rx(struct igb_adapter *adapter)
3083{
9107584e 3084 int i;
9d5c8243 3085
68d480c4
AD		 3086 /* set UTA to appropriate mode */
3087 igb_set_uta(adapter);
3088
26ad9178
AD		 3089 /* set the correct pool for the PF default MAC address in entry 0 */
3090 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3091 adapter->vfs_allocated_count);
3092
06cf2666
AD		 3093 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3094 * the Base and Length of the Rx Descriptor Ring */
3095 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3096 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3097}
3098
3099/**
3100 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3101 * @tx_ring: Tx descriptor ring for a specific queue
3102 *
3103 * Free all transmit software resources
3104 **/
68fd9910 3105void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3106{
3b644cf6 3107 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 3108
3109 vfree(tx_ring->buffer_info);
3110 tx_ring->buffer_info = NULL;
3111
439705e1
AD		 3112 /* if not set, then don't free */
3113 if (!tx_ring->desc)
3114 return;
3115
59d71989
AD		 3116 dma_free_coherent(tx_ring->dev, tx_ring->size,
3117 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3118
3119 tx_ring->desc = NULL;
3120}
3121
3122/**
3123 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3124 * @adapter: board private structure
3125 *
3126 * Free all transmit software resources
3127 **/
3128static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3129{
3130 int i;
3131
3132 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3133 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3134}
3135
b1a436c3
AD		 3136void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
3137 struct igb_buffer *buffer_info)
9d5c8243 3138{
6366ad33
AD		 3139 if (buffer_info->dma) {
3140 if (buffer_info->mapped_as_page)
59d71989 3141 dma_unmap_page(tx_ring->dev,
6366ad33
AD		 3142 buffer_info->dma,
3143 buffer_info->length,
59d71989 3144 DMA_TO_DEVICE);
6366ad33 3145 else
59d71989 3146 dma_unmap_single(tx_ring->dev,
6366ad33
AD		 3147 buffer_info->dma,
3148 buffer_info->length,
59d71989 3149 DMA_TO_DEVICE);
6366ad33
AD		 3150 buffer_info->dma = 0;
3151 }
9d5c8243
AK		 3152 if (buffer_info->skb) {
3153 dev_kfree_skb_any(buffer_info->skb);
3154 buffer_info->skb = NULL;
3155 }
3156 buffer_info->time_stamp = 0;
6366ad33
AD		 3157 buffer_info->length = 0;
3158 buffer_info->next_to_watch = 0;
3159 buffer_info->mapped_as_page = false;
9d5c8243
AK		 3160}
3161
3162/**
3163 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3164 * @tx_ring: ring to be cleaned
3165 **/
3b644cf6 3166static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 3167{
3168 struct igb_buffer *buffer_info;
3169 unsigned long size;
3170 unsigned int i;
3171
3172 if (!tx_ring->buffer_info)
3173 return;
3174 /* Free all the Tx ring sk_buffs */
3175
3176 for (i = 0; i < tx_ring->count; i++) {
3177 buffer_info = &tx_ring->buffer_info[i];
80785298 3178 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3179 }
3180
3181 size = sizeof(struct igb_buffer) * tx_ring->count;
3182 memset(tx_ring->buffer_info, 0, size);
3183
3184 /* Zero out the descriptor ring */
9d5c8243
AK		 3185 memset(tx_ring->desc, 0, tx_ring->size);
3186
3187 tx_ring->next_to_use = 0;
3188 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3189}
3190
3191/**
3192 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3193 * @adapter: board private structure
3194 **/
3195static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3196{
3197 int i;
3198
3199 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3200 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3201}
3202
3203/**
3204 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3205 * @rx_ring: ring to clean the resources from
3206 *
3207 * Free all receive software resources
3208 **/
68fd9910 3209void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3210{
3b644cf6 3211 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 3212
3213 vfree(rx_ring->buffer_info);
3214 rx_ring->buffer_info = NULL;
3215
439705e1
AD		 3216 /* if not set, then don't free */
3217 if (!rx_ring->desc)
3218 return;
3219
59d71989
AD		 3220 dma_free_coherent(rx_ring->dev, rx_ring->size,
3221 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3222
3223 rx_ring->desc = NULL;
3224}
3225
3226/**
3227 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3228 * @adapter: board private structure
3229 *
3230 * Free all receive software resources
3231 **/
3232static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3233{
3234 int i;
3235
3236 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3237 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3238}
3239
3240/**
3241 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3242 * @rx_ring: ring to free buffers from
3243 **/
3b644cf6 3244static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 3245{
3246 struct igb_buffer *buffer_info;
9d5c8243
AK		 3247 unsigned long size;
3248 unsigned int i;
3249
3250 if (!rx_ring->buffer_info)
3251 return;
439705e1 3252
9d5c8243
AK		 3253 /* Free all the Rx ring sk_buffs */
3254 for (i = 0; i < rx_ring->count; i++) {
3255 buffer_info = &rx_ring->buffer_info[i];
3256 if (buffer_info->dma) {
59d71989 3257 dma_unmap_single(rx_ring->dev,
80785298 3258 buffer_info->dma,
44390ca6 3259 IGB_RX_HDR_LEN,
59d71989 3260 DMA_FROM_DEVICE);
9d5c8243
AK		 3261 buffer_info->dma = 0;
3262 }
3263
3264 if (buffer_info->skb) {
3265 dev_kfree_skb(buffer_info->skb);
3266 buffer_info->skb = NULL;
3267 }
6ec43fe6 3268 if (buffer_info->page_dma) {
59d71989 3269 dma_unmap_page(rx_ring->dev,
80785298 3270 buffer_info->page_dma,
6ec43fe6 3271 PAGE_SIZE / 2,
59d71989 3272 DMA_FROM_DEVICE);
6ec43fe6
AD		 3273 buffer_info->page_dma = 0;
3274 }
9d5c8243 3275 if (buffer_info->page) {
9d5c8243
AK		 3276 put_page(buffer_info->page);
3277 buffer_info->page = NULL;
bf36c1a0 3278 buffer_info->page_offset = 0;
9d5c8243
AK		 3279 }
3280 }
3281
9d5c8243
AK		 3282 size = sizeof(struct igb_buffer) * rx_ring->count;
3283 memset(rx_ring->buffer_info, 0, size);
3284
3285 /* Zero out the descriptor ring */
3286 memset(rx_ring->desc, 0, rx_ring->size);
3287
3288 rx_ring->next_to_clean = 0;
3289 rx_ring->next_to_use = 0;
9d5c8243
AK		 3290}
3291
3292/**
3293 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3294 * @adapter: board private structure
3295 **/
3296static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3297{
3298 int i;
3299
3300 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3301 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3302}
3303
3304/**
3305 * igb_set_mac - Change the Ethernet Address of the NIC
3306 * @netdev: network interface device structure
3307 * @p: pointer to an address structure
3308 *
3309 * Returns 0 on success, negative on failure
3310 **/
3311static int igb_set_mac(struct net_device *netdev, void *p)
3312{
3313 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3314 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3315 struct sockaddr *addr = p;
3316
3317 if (!is_valid_ether_addr(addr->sa_data))
3318 return -EADDRNOTAVAIL;
3319
3320 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3321 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3322
26ad9178
AD		 3323 /* set the correct pool for the new PF MAC address in entry 0 */
3324 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3325 adapter->vfs_allocated_count);
e1739522 3326
9d5c8243
AK		 3327 return 0;
3328}
3329
3330/**
68d480c4 3331 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3332 * @netdev: network interface device structure
3333 *
68d480c4
AD		 3334 * Writes multicast address list to the MTA hash table.
3335 * Returns: -ENOMEM on failure
3336 * 0 on no addresses written
3337 * X on writing X addresses to MTA
9d5c8243 3338 **/
68d480c4 3339static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3340{
3341 struct igb_adapter *adapter = netdev_priv(netdev);
3342 struct e1000_hw *hw = &adapter->hw;
22bedad3 3343 struct netdev_hw_addr *ha;
68d480c4 3344 u8 *mta_list;
9d5c8243
AK		 3345 int i;
3346
4cd24eaf 3347 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3348 /* nothing to program, so clear mc list */
3349 igb_update_mc_addr_list(hw, NULL, 0);
3350 igb_restore_vf_multicasts(adapter);
3351 return 0;
3352 }
9d5c8243 3353
4cd24eaf 3354 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3355 if (!mta_list)
3356 return -ENOMEM;
ff41f8dc 3357
68d480c4 3358 /* The shared function expects a packed array of only addresses. */
48e2f183 3359 i = 0;
22bedad3
JP		 3360 netdev_for_each_mc_addr(ha, netdev)
3361 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3362
68d480c4
AD		 3363 igb_update_mc_addr_list(hw, mta_list, i);
3364 kfree(mta_list);
3365
4cd24eaf 3366 return netdev_mc_count(netdev);
68d480c4
AD		 3367}
3368
3369/**
3370 * igb_write_uc_addr_list - write unicast addresses to RAR table
3371 * @netdev: network interface device structure
3372 *
3373 * Writes unicast address list to the RAR table.
3374 * Returns: -ENOMEM on failure/insufficient address space
3375 * 0 on no addresses written
3376 * X on writing X addresses to the RAR table
3377 **/
3378static int igb_write_uc_addr_list(struct net_device *netdev)
3379{
3380 struct igb_adapter *adapter = netdev_priv(netdev);
3381 struct e1000_hw *hw = &adapter->hw;
3382 unsigned int vfn = adapter->vfs_allocated_count;
3383 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3384 int count = 0;
3385
3386 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3387 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3388 return -ENOMEM;
9d5c8243 3389
32e7bfc4 3390 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3391 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3392
3393 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3394 if (!rar_entries)
3395 break;
26ad9178
AD		 3396 igb_rar_set_qsel(adapter, ha->addr,
3397 rar_entries--,
68d480c4
AD		 3398 vfn);
3399 count++;
ff41f8dc
AD		 3400 }
3401 }
3402 /* write the addresses in reverse order to avoid write combining */
3403 for (; rar_entries > 0 ; rar_entries--) {
3404 wr32(E1000_RAH(rar_entries), 0);
3405 wr32(E1000_RAL(rar_entries), 0);
3406 }
3407 wrfl();
3408
68d480c4
AD		 3409 return count;
3410}
3411
3412/**
3413 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3414 * @netdev: network interface device structure
3415 *
3416 * The set_rx_mode entry point is called whenever the unicast or multicast
3417 * address lists or the network interface flags are updated. This routine is
3418 * responsible for configuring the hardware for proper unicast, multicast,
3419 * promiscuous mode, and all-multi behavior.
3420 **/
3421static void igb_set_rx_mode(struct net_device *netdev)
3422{
3423 struct igb_adapter *adapter = netdev_priv(netdev);
3424 struct e1000_hw *hw = &adapter->hw;
3425 unsigned int vfn = adapter->vfs_allocated_count;
3426 u32 rctl, vmolr = 0;
3427 int count;
3428
3429 /* Check for Promiscuous and All Multicast modes */
3430 rctl = rd32(E1000_RCTL);
3431
3432 /* clear the effected bits */
3433 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3434
3435 if (netdev->flags & IFF_PROMISC) {
3436 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3437 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3438 } else {
3439 if (netdev->flags & IFF_ALLMULTI) {
3440 rctl |= E1000_RCTL_MPE;
3441 vmolr |= E1000_VMOLR_MPME;
3442 } else {
3443 /*
3444 * Write addresses to the MTA, if the attempt fails
25985edc 3445 * then we should just turn on promiscuous mode so
68d480c4
AD		 3446 * that we can at least receive multicast traffic
3447 */
3448 count = igb_write_mc_addr_list(netdev);
3449 if (count < 0) {
3450 rctl |= E1000_RCTL_MPE;
3451 vmolr |= E1000_VMOLR_MPME;
3452 } else if (count) {
3453 vmolr |= E1000_VMOLR_ROMPE;
3454 }
3455 }
3456 /*
3457 * Write addresses to available RAR registers, if there is not
3458 * sufficient space to store all the addresses then enable
25985edc 3459 * unicast promiscuous mode
68d480c4
AD		 3460 */
3461 count = igb_write_uc_addr_list(netdev);
3462 if (count < 0) {
3463 rctl |= E1000_RCTL_UPE;
3464 vmolr |= E1000_VMOLR_ROPE;
3465 }
3466 rctl |= E1000_RCTL_VFE;
28fc06f5 3467 }
68d480c4 3468 wr32(E1000_RCTL, rctl);
28fc06f5 3469
68d480c4
AD		 3470 /*
3471 * In order to support SR-IOV and eventually VMDq it is necessary to set
3472 * the VMOLR to enable the appropriate modes. Without this workaround
3473 * we will have issues with VLAN tag stripping not being done for frames
3474 * that are only arriving because we are the default pool
3475 */
3476 if (hw->mac.type < e1000_82576)
28fc06f5 3477 return;
9d5c8243 3478
68d480c4
AD		 3479 vmolr |= rd32(E1000_VMOLR(vfn)) &
3480 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3481 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3482 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3483}
3484
13800469
GR		 3485static void igb_check_wvbr(struct igb_adapter *adapter)
3486{
3487 struct e1000_hw *hw = &adapter->hw;
3488 u32 wvbr = 0;
3489
3490 switch (hw->mac.type) {
3491 case e1000_82576:
3492 case e1000_i350:
3493 if (!(wvbr = rd32(E1000_WVBR)))
3494 return;
3495 break;
3496 default:
3497 break;
3498 }
3499
3500 adapter->wvbr |= wvbr;
3501}
3502
3503#define IGB_STAGGERED_QUEUE_OFFSET 8
3504
3505static void igb_spoof_check(struct igb_adapter *adapter)
3506{
3507 int j;
3508
3509 if (!adapter->wvbr)
3510 return;
3511
3512 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3513 if (adapter->wvbr & (1 << j) ||
3514 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3515 dev_warn(&adapter->pdev->dev,
3516 "Spoof event(s) detected on VF %d\n", j);
3517 adapter->wvbr &=
3518 ~((1 << j) |
3519 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3520 }
3521 }
3522}
3523
9d5c8243
AK		 3524/* Need to wait a few seconds after link up to get diagnostic information from
3525 * the phy */
3526static void igb_update_phy_info(unsigned long data)
3527{
3528 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3529 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3530}
3531
4d6b725e
AD		 3532/**
3533 * igb_has_link - check shared code for link and determine up/down
3534 * @adapter: pointer to driver private info
3535 **/
3145535a 3536bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3537{
3538 struct e1000_hw *hw = &adapter->hw;
3539 bool link_active = false;
3540 s32 ret_val = 0;
3541
3542 /* get_link_status is set on LSC (link status) interrupt or
3543 * rx sequence error interrupt. get_link_status will stay
3544 * false until the e1000_check_for_link establishes link
3545 * for copper adapters ONLY
3546 */
3547 switch (hw->phy.media_type) {
3548 case e1000_media_type_copper:
3549 if (hw->mac.get_link_status) {
3550 ret_val = hw->mac.ops.check_for_link(hw);
3551 link_active = !hw->mac.get_link_status;
3552 } else {
3553 link_active = true;
3554 }
3555 break;
4d6b725e
AD		 3556 case e1000_media_type_internal_serdes:
3557 ret_val = hw->mac.ops.check_for_link(hw);
3558 link_active = hw->mac.serdes_has_link;
3559 break;
3560 default:
3561 case e1000_media_type_unknown:
3562 break;
3563 }
3564
3565 return link_active;
3566}
3567
563988dc
SA		 3568static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3569{
3570 bool ret = false;
3571 u32 ctrl_ext, thstat;
3572
3573 /* check for thermal sensor event on i350, copper only */
3574 if (hw->mac.type == e1000_i350) {
3575 thstat = rd32(E1000_THSTAT);
3576 ctrl_ext = rd32(E1000_CTRL_EXT);
3577
3578 if ((hw->phy.media_type == e1000_media_type_copper) &&
3579 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3580 ret = !!(thstat & event);
3581 }
3582 }
3583
3584 return ret;
3585}
3586
9d5c8243
AK		 3587/**
3588 * igb_watchdog - Timer Call-back
3589 * @data: pointer to adapter cast into an unsigned long
3590 **/
3591static void igb_watchdog(unsigned long data)
3592{
3593 struct igb_adapter *adapter = (struct igb_adapter *)data;
3594 /* Do the rest outside of interrupt context */
3595 schedule_work(&adapter->watchdog_task);
3596}
3597
3598static void igb_watchdog_task(struct work_struct *work)
3599{
3600 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3601 struct igb_adapter,
3602 watchdog_task);
9d5c8243 3603 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3604 struct net_device *netdev = adapter->netdev;
563988dc 3605 u32 link;
7a6ea550 3606 int i;
9d5c8243 3607
4d6b725e 3608 link = igb_has_link(adapter);
9d5c8243
AK		 3609 if (link) {
3610 if (!netif_carrier_ok(netdev)) {
3611 u32 ctrl;
330a6d6a
AD		 3612 hw->mac.ops.get_speed_and_duplex(hw,
3613 &adapter->link_speed,
3614 &adapter->link_duplex);
9d5c8243
AK		 3615
3616 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3617 /* Links status message must follow this format */
3618 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3619 "Flow Control: %s\n",
559e9c49
AD		 3620 netdev->name,
3621 adapter->link_speed,
3622 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3623 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3624 ((ctrl & E1000_CTRL_TFCE) &&
3625 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3626 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3627 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243 3628
563988dc
SA		 3629 /* check for thermal sensor event */
3630 if (igb_thermal_sensor_event(hw, E1000_THSTAT_LINK_THROTTLE)) {
3631 printk(KERN_INFO "igb: %s The network adapter "
3632 "link speed was downshifted "
3633 "because it overheated.\n",
3634 netdev->name);
7ef5ed1c 3635 }
563988dc 3636
d07f3e37 3637 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3638 adapter->tx_timeout_factor = 1;
3639 switch (adapter->link_speed) {
3640 case SPEED_10:
9d5c8243
AK		 3641 adapter->tx_timeout_factor = 14;
3642 break;
3643 case SPEED_100:
9d5c8243
AK		 3644 /* maybe add some timeout factor ? */
3645 break;
3646 }
3647
3648 netif_carrier_on(netdev);
9d5c8243 3649
4ae196df 3650 igb_ping_all_vfs(adapter);
17dc566c 3651 igb_check_vf_rate_limit(adapter);
4ae196df 3652
4b1a9877 3653 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3654 if (!test_bit(__IGB_DOWN, &adapter->state))
3655 mod_timer(&adapter->phy_info_timer,
3656 round_jiffies(jiffies + 2 * HZ));
3657 }
3658 } else {
3659 if (netif_carrier_ok(netdev)) {
3660 adapter->link_speed = 0;
3661 adapter->link_duplex = 0;
563988dc
SA		 3662
3663 /* check for thermal sensor event */
3664 if (igb_thermal_sensor_event(hw, E1000_THSTAT_PWR_DOWN)) {
3665 printk(KERN_ERR "igb: %s The network adapter "
3666 "was stopped because it "
3667 "overheated.\n",
7ef5ed1c 3668 netdev->name);
7ef5ed1c 3669 }
563988dc 3670
527d47c1
AD		 3671 /* Links status message must follow this format */
3672 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3673 netdev->name);
9d5c8243 3674 netif_carrier_off(netdev);
4b1a9877 3675
4ae196df
AD		 3676 igb_ping_all_vfs(adapter);
3677
4b1a9877 3678 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3679 if (!test_bit(__IGB_DOWN, &adapter->state))
3680 mod_timer(&adapter->phy_info_timer,
3681 round_jiffies(jiffies + 2 * HZ));
3682 }
3683 }
3684
12dcd86b
ED		 3685 spin_lock(&adapter->stats64_lock);
3686 igb_update_stats(adapter, &adapter->stats64);
3687 spin_unlock(&adapter->stats64_lock);
9d5c8243 3688
dbabb065 3689 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3690 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3691 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3692 /* We've lost link, so the controller stops DMA,
3693 * but we've got queued Tx work that's never going
3694 * to get done, so reset controller to flush Tx.
3695 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3696 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3697 adapter->tx_timeout_count++;
3698 schedule_work(&adapter->reset_task);
3699 /* return immediately since reset is imminent */
3700 return;
3701 }
9d5c8243 3702 }
9d5c8243 3703
dbabb065
AD		 3704 /* Force detection of hung controller every watchdog period */
3705 tx_ring->detect_tx_hung = true;
3706 }
f7ba205e 3707
9d5c8243 3708 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3709 if (adapter->msix_entries) {
047e0030
AD		 3710 u32 eics = 0;
3711 for (i = 0; i < adapter->num_q_vectors; i++) {
3712 struct igb_q_vector *q_vector = adapter->q_vector[i];
3713 eics |= q_vector->eims_value;
3714 }
7a6ea550
AD		 3715 wr32(E1000_EICS, eics);
3716 } else {
3717 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3718 }
9d5c8243 3719
13800469
GR		 3720 igb_spoof_check(adapter);
3721
9d5c8243
AK		 3722 /* Reset the timer */
3723 if (!test_bit(__IGB_DOWN, &adapter->state))
3724 mod_timer(&adapter->watchdog_timer,
3725 round_jiffies(jiffies + 2 * HZ));
3726}
3727
3728enum latency_range {
3729 lowest_latency = 0,
3730 low_latency = 1,
3731 bulk_latency = 2,
3732 latency_invalid = 255
3733};
3734
6eb5a7f1
AD		 3735/**
3736 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3737 *
3738 * Stores a new ITR value based on strictly on packet size. This
3739 * algorithm is less sophisticated than that used in igb_update_itr,
3740 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3741 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3742 * were determined based on theoretical maximum wire speed and testing
3743 * data, in order to minimize response time while increasing bulk
3744 * throughput.
3745 * This functionality is controlled by the InterruptThrottleRate module
3746 * parameter (see igb_param.c)
3747 * NOTE: This function is called only when operating in a multiqueue
3748 * receive environment.
047e0030 3749 * @q_vector: pointer to q_vector
6eb5a7f1 3750 **/
047e0030 3751static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3752{
047e0030 3753 int new_val = q_vector->itr_val;
6eb5a7f1 3754 int avg_wire_size = 0;
047e0030 3755 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b
ED		 3756 struct igb_ring *ring;
3757 unsigned int packets;
9d5c8243 3758
6eb5a7f1
AD		 3759 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3760 * ints/sec - ITR timer value of 120 ticks.
3761 */
3762 if (adapter->link_speed != SPEED_1000) {
047e0030 3763 new_val = 976;
6eb5a7f1 3764 goto set_itr_val;
9d5c8243 3765 }
047e0030 3766
12dcd86b
ED		 3767 ring = q_vector->rx_ring;
3768 if (ring) {
3769 packets = ACCESS_ONCE(ring->total_packets);
3770
3771 if (packets)
3772 avg_wire_size = ring->total_bytes / packets;
047e0030
AD		 3773 }
3774
12dcd86b
ED		 3775 ring = q_vector->tx_ring;
3776 if (ring) {
3777 packets = ACCESS_ONCE(ring->total_packets);
3778
3779 if (packets)
3780 avg_wire_size = max_t(u32, avg_wire_size,
3781 ring->total_bytes / packets);
047e0030
AD		 3782 }
3783
3784 /* if avg_wire_size isn't set no work was done */
3785 if (!avg_wire_size)
3786 goto clear_counts;
9d5c8243 3787
6eb5a7f1
AD		 3788 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3789 avg_wire_size += 24;
3790
3791 /* Don't starve jumbo frames */
3792 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3793
6eb5a7f1
AD		 3794 /* Give a little boost to mid-size frames */
3795 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3796 new_val = avg_wire_size / 3;
3797 else
3798 new_val = avg_wire_size / 2;
9d5c8243 3799
abe1c363
NN		 3800 /* when in itr mode 3 do not exceed 20K ints/sec */
3801 if (adapter->rx_itr_setting == 3 && new_val < 196)
3802 new_val = 196;
3803
6eb5a7f1 3804set_itr_val:
047e0030
AD		 3805 if (new_val != q_vector->itr_val) {
3806 q_vector->itr_val = new_val;
3807 q_vector->set_itr = 1;
9d5c8243 3808 }
6eb5a7f1 3809clear_counts:
047e0030
AD		 3810 if (q_vector->rx_ring) {
3811 q_vector->rx_ring->total_bytes = 0;
3812 q_vector->rx_ring->total_packets = 0;
3813 }
3814 if (q_vector->tx_ring) {
3815 q_vector->tx_ring->total_bytes = 0;
3816 q_vector->tx_ring->total_packets = 0;
3817 }
9d5c8243
AK		 3818}
3819
3820/**
3821 * igb_update_itr - update the dynamic ITR value based on statistics
3822 * Stores a new ITR value based on packets and byte
3823 * counts during the last interrupt. The advantage of per interrupt
3824 * computation is faster updates and more accurate ITR for the current
3825 * traffic pattern. Constants in this function were computed
3826 * based on theoretical maximum wire speed and thresholds were set based
3827 * on testing data as well as attempting to minimize response time
3828 * while increasing bulk throughput.
3829 * this functionality is controlled by the InterruptThrottleRate module
3830 * parameter (see igb_param.c)
3831 * NOTE: These calculations are only valid when operating in a single-
3832 * queue environment.
3833 * @adapter: pointer to adapter
047e0030 3834 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3835 * @packets: the number of packets during this measurement interval
3836 * @bytes: the number of bytes during this measurement interval
3837 **/
3838static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3839 int packets, int bytes)
3840{
3841 unsigned int retval = itr_setting;
3842
3843 if (packets == 0)
3844 goto update_itr_done;
3845
3846 switch (itr_setting) {
3847 case lowest_latency:
3848 /* handle TSO and jumbo frames */
3849 if (bytes/packets > 8000)
3850 retval = bulk_latency;
3851 else if ((packets < 5) && (bytes > 512))
3852 retval = low_latency;
3853 break;
3854 case low_latency: /* 50 usec aka 20000 ints/s */
3855 if (bytes > 10000) {
3856 /* this if handles the TSO accounting */
3857 if (bytes/packets > 8000) {
3858 retval = bulk_latency;
3859 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3860 retval = bulk_latency;
3861 } else if ((packets > 35)) {
3862 retval = lowest_latency;
3863 }
3864 } else if (bytes/packets > 2000) {
3865 retval = bulk_latency;
3866 } else if (packets <= 2 && bytes < 512) {
3867 retval = lowest_latency;
3868 }
3869 break;
3870 case bulk_latency: /* 250 usec aka 4000 ints/s */
3871 if (bytes > 25000) {
3872 if (packets > 35)
3873 retval = low_latency;
1e5c3d21 3874 } else if (bytes < 1500) {
9d5c8243
AK		 3875 retval = low_latency;
3876 }
3877 break;
3878 }
3879
3880update_itr_done:
3881 return retval;
3882}
3883
6eb5a7f1 3884static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3885{
047e0030 3886 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3887 u16 current_itr;
047e0030 3888 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3889
3890 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3891 if (adapter->link_speed != SPEED_1000) {
3892 current_itr = 0;
3893 new_itr = 4000;
3894 goto set_itr_now;
3895 }
3896
3897 adapter->rx_itr = igb_update_itr(adapter,
3898 adapter->rx_itr,
3025a446
AD		 3899 q_vector->rx_ring->total_packets,
3900 q_vector->rx_ring->total_bytes);
9d5c8243 3901
047e0030
AD		 3902 adapter->tx_itr = igb_update_itr(adapter,
3903 adapter->tx_itr,
3025a446
AD		 3904 q_vector->tx_ring->total_packets,
3905 q_vector->tx_ring->total_bytes);
047e0030 3906 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3907
6eb5a7f1 3908 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3909 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3910 current_itr = low_latency;
3911
9d5c8243
AK		 3912 switch (current_itr) {
3913 /* counts and packets in update_itr are dependent on these numbers */
3914 case lowest_latency:
78b1f607 3915 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3916 break;
3917 case low_latency:
78b1f607 3918 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3919 break;
3920 case bulk_latency:
78b1f607 3921 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3922 break;
3923 default:
3924 break;
3925 }
3926
3927set_itr_now:
3025a446
AD		 3928 q_vector->rx_ring->total_bytes = 0;
3929 q_vector->rx_ring->total_packets = 0;
3930 q_vector->tx_ring->total_bytes = 0;
3931 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3932
047e0030 3933 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3934 /* this attempts to bias the interrupt rate towards Bulk
3935 * by adding intermediate steps when interrupt rate is
3936 * increasing */
047e0030
AD		 3937 new_itr = new_itr > q_vector->itr_val ?
3938 max((new_itr * q_vector->itr_val) /
3939 (new_itr + (q_vector->itr_val >> 2)),
3940 new_itr) :
9d5c8243
AK		 3941 new_itr;
3942 /* Don't write the value here; it resets the adapter's
3943 * internal timer, and causes us to delay far longer than
3944 * we should between interrupts. Instead, we write the ITR
3945 * value at the beginning of the next interrupt so the timing
3946 * ends up being correct.
3947 */
047e0030
AD		 3948 q_vector->itr_val = new_itr;
3949 q_vector->set_itr = 1;
9d5c8243 3950 }
9d5c8243
AK		 3951}
3952
9d5c8243
AK		 3953#define IGB_TX_FLAGS_CSUM 0x00000001
3954#define IGB_TX_FLAGS_VLAN 0x00000002
3955#define IGB_TX_FLAGS_TSO 0x00000004
3956#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3957#define IGB_TX_FLAGS_TSTAMP 0x00000010
3958#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3959#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3960
85ad76b2 3961static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3962 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3963{
3964 struct e1000_adv_tx_context_desc *context_desc;
3965 unsigned int i;
3966 int err;
3967 struct igb_buffer *buffer_info;
3968 u32 info = 0, tu_cmd = 0;
91d4ee33
NN		 3969 u32 mss_l4len_idx;
3970 u8 l4len;
9d5c8243
AK		 3971
3972 if (skb_header_cloned(skb)) {
3973 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3974 if (err)
3975 return err;
3976 }
3977
3978 l4len = tcp_hdrlen(skb);
3979 *hdr_len += l4len;
3980
3981 if (skb->protocol == htons(ETH_P_IP)) {
3982 struct iphdr *iph = ip_hdr(skb);
3983 iph->tot_len = 0;
3984 iph->check = 0;
3985 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3986 iph->daddr, 0,
3987 IPPROTO_TCP,
3988 0);
8e1e8a47 3989 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3990 ipv6_hdr(skb)->payload_len = 0;
3991 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3992 &ipv6_hdr(skb)->daddr,
3993 0, IPPROTO_TCP, 0);
3994 }
3995
3996 i = tx_ring->next_to_use;
3997
3998 buffer_info = &tx_ring->buffer_info[i];
3999 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
4000 /* VLAN MACLEN IPLEN */
4001 if (tx_flags & IGB_TX_FLAGS_VLAN)
4002 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
4003 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
4004 *hdr_len += skb_network_offset(skb);
4005 info |= skb_network_header_len(skb);
4006 *hdr_len += skb_network_header_len(skb);
4007 context_desc->vlan_macip_lens = cpu_to_le32(info);
4008
4009 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4010 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
4011
4012 if (skb->protocol == htons(ETH_P_IP))
4013 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
4014 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4015
4016 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
4017
4018 /* MSS L4LEN IDX */
4019 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
4020 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
4021
73cd78f1 4022 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 4023 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
4024 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4025
4026 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4027 context_desc->seqnum_seed = 0;
4028
4029 buffer_info->time_stamp = jiffies;
0e014cb1 4030 buffer_info->next_to_watch = i;
9d5c8243
AK		 4031 buffer_info->dma = 0;
4032 i++;
4033 if (i == tx_ring->count)
4034 i = 0;
4035
4036 tx_ring->next_to_use = i;
4037
4038 return true;
4039}
4040
85ad76b2
AD		 4041static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
4042 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 4043{
4044 struct e1000_adv_tx_context_desc *context_desc;
59d71989 4045 struct device *dev = tx_ring->dev;
9d5c8243
AK		 4046 struct igb_buffer *buffer_info;
4047 u32 info = 0, tu_cmd = 0;
80785298 4048 unsigned int i;
9d5c8243
AK		 4049
4050 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
4051 (tx_flags & IGB_TX_FLAGS_VLAN)) {
4052 i = tx_ring->next_to_use;
4053 buffer_info = &tx_ring->buffer_info[i];
4054 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
4055
4056 if (tx_flags & IGB_TX_FLAGS_VLAN)
4057 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 4058
9d5c8243
AK		 4059 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
4060 if (skb->ip_summed == CHECKSUM_PARTIAL)
4061 info |= skb_network_header_len(skb);
4062
4063 context_desc->vlan_macip_lens = cpu_to_le32(info);
4064
4065 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
4066
4067 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 4068 __be16 protocol;
4069
4070 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
4071 const struct vlan_ethhdr *vhdr =
4072 (const struct vlan_ethhdr*)skb->data;
4073
4074 protocol = vhdr->h_vlan_encapsulated_proto;
4075 } else {
4076 protocol = skb->protocol;
4077 }
4078
4079 switch (protocol) {
09640e63 4080 case cpu_to_be16(ETH_P_IP):
9d5c8243 4081 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 4082 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4083 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 4084 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4085 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 4086 break;
09640e63 4087 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 4088 /* XXX what about other V6 headers?? */
4089 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4090 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 4091 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4092 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 4093 break;
4094 default:
4095 if (unlikely(net_ratelimit()))
59d71989 4096 dev_warn(dev,
44b0cda3
MW		 4097 "partial checksum but proto=%x!\n",
4098 skb->protocol);
4099 break;
4100 }
9d5c8243
AK		 4101 }
4102
4103 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
4104 context_desc->seqnum_seed = 0;
85ad76b2 4105 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 4106 context_desc->mss_l4len_idx =
85ad76b2 4107 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 4108
4109 buffer_info->time_stamp = jiffies;
0e014cb1 4110 buffer_info->next_to_watch = i;
9d5c8243
AK		 4111 buffer_info->dma = 0;
4112
4113 i++;
4114 if (i == tx_ring->count)
4115 i = 0;
4116 tx_ring->next_to_use = i;
4117
4118 return true;
4119 }
9d5c8243
AK		 4120 return false;
4121}
4122
4123#define IGB_MAX_TXD_PWR 16
4124#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
4125
80785298 4126static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 4127 unsigned int first)
9d5c8243
AK		 4128{
4129 struct igb_buffer *buffer_info;
59d71989 4130 struct device *dev = tx_ring->dev;
2873957d 4131 unsigned int hlen = skb_headlen(skb);
9d5c8243
AK		 4132 unsigned int count = 0, i;
4133 unsigned int f;
2873957d 4134 u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
9d5c8243
AK		 4135
4136 i = tx_ring->next_to_use;
4137
4138 buffer_info = &tx_ring->buffer_info[i];
2873957d
NN		 4139 BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
4140 buffer_info->length = hlen;
9d5c8243
AK		 4141 /* set time_stamp *before* dma to help avoid a possible race */
4142 buffer_info->time_stamp = jiffies;
0e014cb1 4143 buffer_info->next_to_watch = i;
2873957d 4144 buffer_info->dma = dma_map_single(dev, skb->data, hlen,
59d71989
AD		 4145 DMA_TO_DEVICE);
4146 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33 4147 goto dma_error;
9d5c8243
AK		 4148
4149 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2873957d
NN		 4150 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
4151 unsigned int len = frag->size;
9d5c8243 4152
8581145f 4153 count++;
65689fef
AD		 4154 i++;
4155 if (i == tx_ring->count)
4156 i = 0;
4157
9d5c8243
AK		 4158 buffer_info = &tx_ring->buffer_info[i];
4159 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
4160 buffer_info->length = len;
4161 buffer_info->time_stamp = jiffies;
0e014cb1 4162 buffer_info->next_to_watch = i;
6366ad33 4163 buffer_info->mapped_as_page = true;
877749bf 4164 buffer_info->dma = skb_frag_dma_map(dev, frag, 0, len,
59d71989
AD		 4165 DMA_TO_DEVICE);
4166 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33
AD		 4167 goto dma_error;
4168
9d5c8243
AK		 4169 }
4170
9d5c8243 4171 tx_ring->buffer_info[i].skb = skb;
2244d07b 4172 tx_ring->buffer_info[i].tx_flags = skb_shinfo(skb)->tx_flags;
2873957d
NN		 4173 /* multiply data chunks by size of headers */
4174 tx_ring->buffer_info[i].bytecount = ((gso_segs - 1) * hlen) + skb->len;
4175 tx_ring->buffer_info[i].gso_segs = gso_segs;
0e014cb1 4176 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 4177
cdfd01fc 4178 return ++count;
6366ad33
AD		 4179
4180dma_error:
59d71989 4181 dev_err(dev, "TX DMA map failed\n");
6366ad33
AD		 4182
4183 /* clear timestamp and dma mappings for failed buffer_info mapping */
4184 buffer_info->dma = 0;
4185 buffer_info->time_stamp = 0;
4186 buffer_info->length = 0;
4187 buffer_info->next_to_watch = 0;
4188 buffer_info->mapped_as_page = false;
6366ad33
AD		 4189
4190 /* clear timestamp and dma mappings for remaining portion of packet */
a77ff709
NN		 4191 while (count--) {
4192 if (i == 0)
4193 i = tx_ring->count;
6366ad33 4194 i--;
6366ad33
AD		 4195 buffer_info = &tx_ring->buffer_info[i];
4196 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
4197 }
4198
4199 return 0;
9d5c8243
AK		 4200}
4201
85ad76b2 4202static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
91d4ee33 4203 u32 tx_flags, int count, u32 paylen,
9d5c8243
AK		 4204 u8 hdr_len)
4205{
cdfd01fc 4206 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 4207 struct igb_buffer *buffer_info;
4208 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 4209 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 4210
4211 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
4212 E1000_ADVTXD_DCMD_DEXT);
4213
4214 if (tx_flags & IGB_TX_FLAGS_VLAN)
4215 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
4216
33af6bcc
PO		 4217 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4218 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
4219
9d5c8243
AK		 4220 if (tx_flags & IGB_TX_FLAGS_TSO) {
4221 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
4222
4223 /* insert tcp checksum */
4224 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4225
4226 /* insert ip checksum */
4227 if (tx_flags & IGB_TX_FLAGS_IPV4)
4228 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4229
4230 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
4231 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4232 }
4233
85ad76b2
AD		 4234 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
4235 (tx_flags & (IGB_TX_FLAGS_CSUM |
4236 IGB_TX_FLAGS_TSO |
7dfc16fa 4237 IGB_TX_FLAGS_VLAN)))
85ad76b2 4238 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4239
4240 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
4241
cdfd01fc 4242 do {
9d5c8243
AK		 4243 buffer_info = &tx_ring->buffer_info[i];
4244 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4245 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
4246 tx_desc->read.cmd_type_len =
4247 cpu_to_le32(cmd_type_len | buffer_info->length);
4248 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 4249 count--;
9d5c8243
AK		 4250 i++;
4251 if (i == tx_ring->count)
4252 i = 0;
cdfd01fc 4253 } while (count > 0);
9d5c8243 4254
85ad76b2 4255 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 4256 /* Force memory writes to complete before letting h/w
4257 * know there are new descriptors to fetch. (Only
4258 * applicable for weak-ordered memory model archs,
4259 * such as IA-64). */
4260 wmb();
4261
4262 tx_ring->next_to_use = i;
fce99e34 4263 writel(i, tx_ring->tail);
9d5c8243
AK		 4264 /* we need this if more than one processor can write to our tail
4265 * at a time, it syncronizes IO on IA64/Altix systems */
4266 mmiowb();
4267}
4268
e694e964 4269static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4270{
e694e964
AD		 4271 struct net_device *netdev = tx_ring->netdev;
4272
661086df 4273 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4274
9d5c8243
AK		 4275 /* Herbert's original patch had:
4276 * smp_mb__after_netif_stop_queue();
4277 * but since that doesn't exist yet, just open code it. */
4278 smp_mb();
4279
4280 /* We need to check again in a case another CPU has just
4281 * made room available. */
c493ea45 4282 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4283 return -EBUSY;
4284
4285 /* A reprieve! */
661086df 4286 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4287
4288 u64_stats_update_begin(&tx_ring->tx_syncp2);
4289 tx_ring->tx_stats.restart_queue2++;
4290 u64_stats_update_end(&tx_ring->tx_syncp2);
4291
9d5c8243
AK		 4292 return 0;
4293}
4294
717ba089 4295static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4296{
c493ea45 4297 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4298 return 0;
e694e964 4299 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4300}
4301
b1a436c3
AD		 4302netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
4303 struct igb_ring *tx_ring)
9d5c8243 4304{
cdfd01fc 4305 int tso = 0, count;
91d4ee33
NN		 4306 u32 tx_flags = 0;
4307 u16 first;
4308 u8 hdr_len = 0;
9d5c8243 4309
9d5c8243
AK		 4310 /* need: 1 descriptor per page,
4311 * + 2 desc gap to keep tail from touching head,
4312 * + 1 desc for skb->data,
4313 * + 1 desc for context descriptor,
4314 * otherwise try next time */
e694e964 4315 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4316 /* this is a hard error */
9d5c8243
AK		 4317 return NETDEV_TX_BUSY;
4318 }
33af6bcc 4319
2244d07b
OH		 4320 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4321 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4322 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 4323 }
9d5c8243 4324
eab6d18d 4325 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4326 tx_flags |= IGB_TX_FLAGS_VLAN;
4327 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4328 }
4329
661086df
PWJ		 4330 if (skb->protocol == htons(ETH_P_IP))
4331 tx_flags |= IGB_TX_FLAGS_IPV4;
4332
0e014cb1 4333 first = tx_ring->next_to_use;
85ad76b2
AD		 4334 if (skb_is_gso(skb)) {
4335 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 4336
85ad76b2
AD		 4337 if (tso < 0) {
4338 dev_kfree_skb_any(skb);
4339 return NETDEV_TX_OK;
4340 }
9d5c8243
AK		 4341 }
4342
4343 if (tso)
4344 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 4345 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 4346 (skb->ip_summed == CHECKSUM_PARTIAL))
4347 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 4348
65689fef 4349 /*
cdfd01fc 4350 * count reflects descriptors mapped, if 0 or less then mapping error
25985edc 4351 * has occurred and we need to rewind the descriptor queue
65689fef 4352 */
80785298 4353 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 4354 if (!count) {
65689fef
AD		 4355 dev_kfree_skb_any(skb);
4356 tx_ring->buffer_info[first].time_stamp = 0;
4357 tx_ring->next_to_use = first;
85ad76b2 4358 return NETDEV_TX_OK;
65689fef 4359 }
9d5c8243 4360
85ad76b2
AD		 4361 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
4362
4363 /* Make sure there is space in the ring for the next send. */
e694e964 4364 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4365
9d5c8243
AK		 4366 return NETDEV_TX_OK;
4367}
4368
3b29a56d
SH		 4369static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
4370 struct net_device *netdev)
9d5c8243
AK		 4371{
4372 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 4373 struct igb_ring *tx_ring;
661086df 4374 int r_idx = 0;
b1a436c3
AD		 4375
4376 if (test_bit(__IGB_DOWN, &adapter->state)) {
4377 dev_kfree_skb_any(skb);
4378 return NETDEV_TX_OK;
4379 }
4380
4381 if (skb->len <= 0) {
4382 dev_kfree_skb_any(skb);
4383 return NETDEV_TX_OK;
4384 }
4385
1bfaf07b 4386 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 4387 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 4388
4389 /* This goes back to the question of how to logically map a tx queue
4390 * to a flow. Right now, performance is impacted slightly negatively
4391 * if using multiple tx queues. If the stack breaks away from a
4392 * single qdisc implementation, we can look at this again. */
e694e964 4393 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 4394}
4395
4396/**
4397 * igb_tx_timeout - Respond to a Tx Hang
4398 * @netdev: network interface device structure
4399 **/
4400static void igb_tx_timeout(struct net_device *netdev)
4401{
4402 struct igb_adapter *adapter = netdev_priv(netdev);
4403 struct e1000_hw *hw = &adapter->hw;
4404
4405 /* Do the reset outside of interrupt context */
4406 adapter->tx_timeout_count++;
f7ba205e 4407
55cac248
AD		 4408 if (hw->mac.type == e1000_82580)
4409 hw->dev_spec._82575.global_device_reset = true;
4410
9d5c8243 4411 schedule_work(&adapter->reset_task);
265de409
AD		 4412 wr32(E1000_EICS,
4413 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4414}
4415
4416static void igb_reset_task(struct work_struct *work)
4417{
4418 struct igb_adapter *adapter;
4419 adapter = container_of(work, struct igb_adapter, reset_task);
4420
c97ec42a
TI		 4421 igb_dump(adapter);
4422 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4423 igb_reinit_locked(adapter);
4424}
4425
4426/**
12dcd86b 4427 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4428 * @netdev: network interface device structure
12dcd86b 4429 * @stats: rtnl_link_stats64 pointer
9d5c8243 4430 *
9d5c8243 4431 **/
12dcd86b
ED		 4432static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4433 struct rtnl_link_stats64 *stats)
9d5c8243 4434{
12dcd86b
ED		 4435 struct igb_adapter *adapter = netdev_priv(netdev);
4436
4437 spin_lock(&adapter->stats64_lock);
4438 igb_update_stats(adapter, &adapter->stats64);
4439 memcpy(stats, &adapter->stats64, sizeof(*stats));
4440 spin_unlock(&adapter->stats64_lock);
4441
4442 return stats;
9d5c8243
AK		 4443}
4444
4445/**
4446 * igb_change_mtu - Change the Maximum Transfer Unit
4447 * @netdev: network interface device structure
4448 * @new_mtu: new value for maximum frame size
4449 *
4450 * Returns 0 on success, negative on failure
4451 **/
4452static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4453{
4454 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4455 struct pci_dev *pdev = adapter->pdev;
153285f9 4456 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4457
c809d227 4458 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4459 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4460 return -EINVAL;
4461 }
4462
153285f9 4463#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4464 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4465 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4466 return -EINVAL;
4467 }
4468
4469 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4470 msleep(1);
73cd78f1 4471
9d5c8243
AK		 4472 /* igb_down has a dependency on max_frame_size */
4473 adapter->max_frame_size = max_frame;
559e9c49 4474
4c844851
AD		 4475 if (netif_running(netdev))
4476 igb_down(adapter);
9d5c8243 4477
090b1795 4478 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4479 netdev->mtu, new_mtu);
4480 netdev->mtu = new_mtu;
4481
4482 if (netif_running(netdev))
4483 igb_up(adapter);
4484 else
4485 igb_reset(adapter);
4486
4487 clear_bit(__IGB_RESETTING, &adapter->state);
4488
4489 return 0;
4490}
4491
4492/**
4493 * igb_update_stats - Update the board statistics counters
4494 * @adapter: board private structure
4495 **/
4496
12dcd86b
ED		 4497void igb_update_stats(struct igb_adapter *adapter,
4498 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4499{
4500 struct e1000_hw *hw = &adapter->hw;
4501 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4502 u32 reg, mpc;
9d5c8243 4503 u16 phy_tmp;
3f9c0164
AD		 4504 int i;
4505 u64 bytes, packets;
12dcd86b
ED		 4506 unsigned int start;
4507 u64 _bytes, _packets;
9d5c8243
AK		 4508
4509#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4510
4511 /*
4512 * Prevent stats update while adapter is being reset, or if the pci
4513 * connection is down.
4514 */
4515 if (adapter->link_speed == 0)
4516 return;
4517 if (pci_channel_offline(pdev))
4518 return;
4519
3f9c0164
AD		 4520 bytes = 0;
4521 packets = 0;
4522 for (i = 0; i < adapter->num_rx_queues; i++) {
4523 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446 4524 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4525
3025a446 4526 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 4527 net_stats->rx_fifo_errors += rqdpc_tmp;
12dcd86b
ED		 4528
4529 do {
4530 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4531 _bytes = ring->rx_stats.bytes;
4532 _packets = ring->rx_stats.packets;
4533 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4534 bytes += _bytes;
4535 packets += _packets;
3f9c0164
AD		 4536 }
4537
128e45eb
AD		 4538 net_stats->rx_bytes = bytes;
4539 net_stats->rx_packets = packets;
3f9c0164
AD		 4540
4541 bytes = 0;
4542 packets = 0;
4543 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4544 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4545 do {
4546 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4547 _bytes = ring->tx_stats.bytes;
4548 _packets = ring->tx_stats.packets;
4549 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4550 bytes += _bytes;
4551 packets += _packets;
3f9c0164 4552 }
128e45eb
AD		 4553 net_stats->tx_bytes = bytes;
4554 net_stats->tx_packets = packets;
3f9c0164
AD		 4555
4556 /* read stats registers */
9d5c8243
AK		 4557 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4558 adapter->stats.gprc += rd32(E1000_GPRC);
4559 adapter->stats.gorc += rd32(E1000_GORCL);
4560 rd32(E1000_GORCH); /* clear GORCL */
4561 adapter->stats.bprc += rd32(E1000_BPRC);
4562 adapter->stats.mprc += rd32(E1000_MPRC);
4563 adapter->stats.roc += rd32(E1000_ROC);
4564
4565 adapter->stats.prc64 += rd32(E1000_PRC64);
4566 adapter->stats.prc127 += rd32(E1000_PRC127);
4567 adapter->stats.prc255 += rd32(E1000_PRC255);
4568 adapter->stats.prc511 += rd32(E1000_PRC511);
4569 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4570 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4571 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4572 adapter->stats.sec += rd32(E1000_SEC);
4573
fa3d9a6d
MW		 4574 mpc = rd32(E1000_MPC);
4575 adapter->stats.mpc += mpc;
4576 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4577 adapter->stats.scc += rd32(E1000_SCC);
4578 adapter->stats.ecol += rd32(E1000_ECOL);
4579 adapter->stats.mcc += rd32(E1000_MCC);
4580 adapter->stats.latecol += rd32(E1000_LATECOL);
4581 adapter->stats.dc += rd32(E1000_DC);
4582 adapter->stats.rlec += rd32(E1000_RLEC);
4583 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4584 adapter->stats.xontxc += rd32(E1000_XONTXC);
4585 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4586 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4587 adapter->stats.fcruc += rd32(E1000_FCRUC);
4588 adapter->stats.gptc += rd32(E1000_GPTC);
4589 adapter->stats.gotc += rd32(E1000_GOTCL);
4590 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4591 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4592 adapter->stats.ruc += rd32(E1000_RUC);
4593 adapter->stats.rfc += rd32(E1000_RFC);
4594 adapter->stats.rjc += rd32(E1000_RJC);
4595 adapter->stats.tor += rd32(E1000_TORH);
4596 adapter->stats.tot += rd32(E1000_TOTH);
4597 adapter->stats.tpr += rd32(E1000_TPR);
4598
4599 adapter->stats.ptc64 += rd32(E1000_PTC64);
4600 adapter->stats.ptc127 += rd32(E1000_PTC127);
4601 adapter->stats.ptc255 += rd32(E1000_PTC255);
4602 adapter->stats.ptc511 += rd32(E1000_PTC511);
4603 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4604 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4605
4606 adapter->stats.mptc += rd32(E1000_MPTC);
4607 adapter->stats.bptc += rd32(E1000_BPTC);
4608
2d0b0f69
NN		 4609 adapter->stats.tpt += rd32(E1000_TPT);
4610 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4611
4612 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4613 /* read internal phy specific stats */
4614 reg = rd32(E1000_CTRL_EXT);
4615 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4616 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4617 adapter->stats.tncrs += rd32(E1000_TNCRS);
4618 }
4619
9d5c8243
AK		 4620 adapter->stats.tsctc += rd32(E1000_TSCTC);
4621 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4622
4623 adapter->stats.iac += rd32(E1000_IAC);
4624 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4625 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4626 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4627 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4628 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4629 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4630 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4631 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4632
4633 /* Fill out the OS statistics structure */
128e45eb
AD		 4634 net_stats->multicast = adapter->stats.mprc;
4635 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4636
4637 /* Rx Errors */
4638
4639 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4640 * our own version based on RUC and ROC */
128e45eb 4641 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4642 adapter->stats.crcerrs + adapter->stats.algnerrc +
4643 adapter->stats.ruc + adapter->stats.roc +
4644 adapter->stats.cexterr;
128e45eb
AD		 4645 net_stats->rx_length_errors = adapter->stats.ruc +
4646 adapter->stats.roc;
4647 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4648 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4649 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4650
4651 /* Tx Errors */
128e45eb
AD		 4652 net_stats->tx_errors = adapter->stats.ecol +
4653 adapter->stats.latecol;
4654 net_stats->tx_aborted_errors = adapter->stats.ecol;
4655 net_stats->tx_window_errors = adapter->stats.latecol;
4656 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4657
4658 /* Tx Dropped needs to be maintained elsewhere */
4659
4660 /* Phy Stats */
4661 if (hw->phy.media_type == e1000_media_type_copper) {
4662 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4663 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4664 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4665 adapter->phy_stats.idle_errors += phy_tmp;
4666 }
4667 }
4668
4669 /* Management Stats */
4670 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4671 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4672 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4673
4674 /* OS2BMC Stats */
4675 reg = rd32(E1000_MANC);
4676 if (reg & E1000_MANC_EN_BMC2OS) {
4677 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4678 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4679 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4680 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4681 }
9d5c8243
AK		 4682}
4683
9d5c8243
AK		 4684static irqreturn_t igb_msix_other(int irq, void *data)
4685{
047e0030 4686 struct igb_adapter *adapter = data;
9d5c8243 4687 struct e1000_hw *hw = &adapter->hw;
844290e5 4688 u32 icr = rd32(E1000_ICR);
844290e5 4689 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4690
7f081d40
AD		 4691 if (icr & E1000_ICR_DRSTA)
4692 schedule_work(&adapter->reset_task);
4693
047e0030 4694 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4695 /* HW is reporting DMA is out of sync */
4696 adapter->stats.doosync++;
13800469
GR		 4697 /* The DMA Out of Sync is also indication of a spoof event
4698 * in IOV mode. Check the Wrong VM Behavior register to
4699 * see if it is really a spoof event. */
4700 igb_check_wvbr(adapter);
dda0e083 4701 }
eebbbdba 4702
4ae196df
AD		 4703 /* Check for a mailbox event */
4704 if (icr & E1000_ICR_VMMB)
4705 igb_msg_task(adapter);
4706
4707 if (icr & E1000_ICR_LSC) {
4708 hw->mac.get_link_status = 1;
4709 /* guard against interrupt when we're going down */
4710 if (!test_bit(__IGB_DOWN, &adapter->state))
4711 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4712 }
4713
25568a53
AD		 4714 if (adapter->vfs_allocated_count)
4715 wr32(E1000_IMS, E1000_IMS_LSC |
4716 E1000_IMS_VMMB |
4717 E1000_IMS_DOUTSYNC);
4718 else
4719 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4720 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4721
4722 return IRQ_HANDLED;
4723}
4724
047e0030 4725static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4726{
26b39276 4727 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4728 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4729
047e0030
AD		 4730 if (!q_vector->set_itr)
4731 return;
73cd78f1 4732
047e0030
AD		 4733 if (!itr_val)
4734 itr_val = 0x4;
661086df 4735
26b39276
AD		 4736 if (adapter->hw.mac.type == e1000_82575)
4737 itr_val |= itr_val << 16;
661086df 4738 else
047e0030 4739 itr_val |= 0x8000000;
661086df 4740
047e0030
AD		 4741 writel(itr_val, q_vector->itr_register);
4742 q_vector->set_itr = 0;
6eb5a7f1
AD		 4743}
4744
047e0030 4745static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4746{
047e0030 4747 struct igb_q_vector *q_vector = data;
9d5c8243 4748
047e0030
AD		 4749 /* Write the ITR value calculated from the previous interrupt. */
4750 igb_write_itr(q_vector);
9d5c8243 4751
047e0030 4752 napi_schedule(&q_vector->napi);
844290e5 4753
047e0030 4754 return IRQ_HANDLED;
fe4506b6
JC		 4755}
4756
421e02f0 4757#ifdef CONFIG_IGB_DCA
047e0030 4758static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4759{
047e0030 4760 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4761 struct e1000_hw *hw = &adapter->hw;
4762 int cpu = get_cpu();
fe4506b6 4763
047e0030
AD		 4764 if (q_vector->cpu == cpu)
4765 goto out_no_update;
4766
4767 if (q_vector->tx_ring) {
4768 int q = q_vector->tx_ring->reg_idx;
4769 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4770 if (hw->mac.type == e1000_82575) {
4771 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4772 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4773 } else {
047e0030
AD		 4774 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4775 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4776 E1000_DCA_TXCTRL_CPUID_SHIFT;
4777 }
4778 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4779 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4780 }
4781 if (q_vector->rx_ring) {
4782 int q = q_vector->rx_ring->reg_idx;
4783 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4784 if (hw->mac.type == e1000_82575) {
2d064c06 4785 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4786 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4787 } else {
4788 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4789 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4790 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4791 }
fe4506b6
JC		 4792 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4793 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4794 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4795 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4796 }
047e0030
AD		 4797 q_vector->cpu = cpu;
4798out_no_update:
fe4506b6
JC		 4799 put_cpu();
4800}
4801
4802static void igb_setup_dca(struct igb_adapter *adapter)
4803{
7e0e99ef 4804 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4805 int i;
4806
7dfc16fa 4807 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4808 return;
4809
7e0e99ef
AD		 4810 /* Always use CB2 mode, difference is masked in the CB driver. */
4811 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4812
047e0030 4813 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4814 adapter->q_vector[i]->cpu = -1;
4815 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4816 }
4817}
4818
4819static int __igb_notify_dca(struct device *dev, void *data)
4820{
4821 struct net_device *netdev = dev_get_drvdata(dev);
4822 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4823 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4824 struct e1000_hw *hw = &adapter->hw;
4825 unsigned long event = *(unsigned long *)data;
4826
4827 switch (event) {
4828 case DCA_PROVIDER_ADD:
4829 /* if already enabled, don't do it again */
7dfc16fa 4830 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4831 break;
fe4506b6 4832 if (dca_add_requester(dev) == 0) {
bbd98fe4 4833 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4834 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4835 igb_setup_dca(adapter);
4836 break;
4837 }
4838 /* Fall Through since DCA is disabled. */
4839 case DCA_PROVIDER_REMOVE:
7dfc16fa 4840 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4841 /* without this a class_device is left
047e0030 4842 * hanging around in the sysfs model */
fe4506b6 4843 dca_remove_requester(dev);
090b1795 4844 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4845 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4846 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4847 }
4848 break;
4849 }
bbd98fe4 4850
fe4506b6 4851 return 0;
9d5c8243
AK		 4852}
4853
fe4506b6
JC		 4854static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4855 void *p)
4856{
4857 int ret_val;
4858
4859 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4860 __igb_notify_dca);
4861
4862 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4863}
421e02f0 4864#endif /* CONFIG_IGB_DCA */
9d5c8243 4865
4ae196df
AD		 4866static void igb_ping_all_vfs(struct igb_adapter *adapter)
4867{
4868 struct e1000_hw *hw = &adapter->hw;
4869 u32 ping;
4870 int i;
4871
4872 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4873 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4874 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4875 ping |= E1000_VT_MSGTYPE_CTS;
4876 igb_write_mbx(hw, &ping, 1, i);
4877 }
4878}
4879
7d5753f0
AD		 4880static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4881{
4882 struct e1000_hw *hw = &adapter->hw;
4883 u32 vmolr = rd32(E1000_VMOLR(vf));
4884 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4885
d85b9004 4886 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 4887 IGB_VF_FLAG_MULTI_PROMISC);
4888 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4889
4890 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4891 vmolr |= E1000_VMOLR_MPME;
d85b9004 4892 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 4893 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4894 } else {
4895 /*
4896 * if we have hashes and we are clearing a multicast promisc
4897 * flag we need to write the hashes to the MTA as this step
4898 * was previously skipped
4899 */
4900 if (vf_data->num_vf_mc_hashes > 30) {
4901 vmolr |= E1000_VMOLR_MPME;
4902 } else if (vf_data->num_vf_mc_hashes) {
4903 int j;
4904 vmolr |= E1000_VMOLR_ROMPE;
4905 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4906 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4907 }
4908 }
4909
4910 wr32(E1000_VMOLR(vf), vmolr);
4911
4912 /* there are flags left unprocessed, likely not supported */
4913 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4914 return -EINVAL;
4915
4916 return 0;
4917
4918}
4919
4ae196df
AD		 4920static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4921 u32 *msgbuf, u32 vf)
4922{
4923 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4924 u16 *hash_list = (u16 *)&msgbuf[1];
4925 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4926 int i;
4927
7d5753f0 4928 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4929 * to this VF for later use to restore when the PF multi cast
4930 * list changes
4931 */
4932 vf_data->num_vf_mc_hashes = n;
4933
7d5753f0
AD		 4934 /* only up to 30 hash values supported */
4935 if (n > 30)
4936 n = 30;
4937
4938 /* store the hashes for later use */
4ae196df 4939 for (i = 0; i < n; i++)
a419aef8 4940 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4941
4942 /* Flush and reset the mta with the new values */
ff41f8dc 4943 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4944
4945 return 0;
4946}
4947
4948static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4949{
4950 struct e1000_hw *hw = &adapter->hw;
4951 struct vf_data_storage *vf_data;
4952 int i, j;
4953
4954 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4955 u32 vmolr = rd32(E1000_VMOLR(i));
4956 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4957
4ae196df 4958 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4959
4960 if ((vf_data->num_vf_mc_hashes > 30) ||
4961 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4962 vmolr |= E1000_VMOLR_MPME;
4963 } else if (vf_data->num_vf_mc_hashes) {
4964 vmolr |= E1000_VMOLR_ROMPE;
4965 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4966 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4967 }
4968 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4969 }
4970}
4971
4972static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4973{
4974 struct e1000_hw *hw = &adapter->hw;
4975 u32 pool_mask, reg, vid;
4976 int i;
4977
4978 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4979
4980 /* Find the vlan filter for this id */
4981 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4982 reg = rd32(E1000_VLVF(i));
4983
4984 /* remove the vf from the pool */
4985 reg &= ~pool_mask;
4986
4987 /* if pool is empty then remove entry from vfta */
4988 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4989 (reg & E1000_VLVF_VLANID_ENABLE)) {
4990 reg = 0;
4991 vid = reg & E1000_VLVF_VLANID_MASK;
4992 igb_vfta_set(hw, vid, false);
4993 }
4994
4995 wr32(E1000_VLVF(i), reg);
4996 }
ae641bdc
AD		 4997
4998 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4999}
5000
5001static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5002{
5003 struct e1000_hw *hw = &adapter->hw;
5004 u32 reg, i;
5005
51466239
AD		 5006 /* The vlvf table only exists on 82576 hardware and newer */
5007 if (hw->mac.type < e1000_82576)
5008 return -1;
5009
5010 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5011 if (!adapter->vfs_allocated_count)
5012 return -1;
5013
5014 /* Find the vlan filter for this id */
5015 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5016 reg = rd32(E1000_VLVF(i));
5017 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5018 vid == (reg & E1000_VLVF_VLANID_MASK))
5019 break;
5020 }
5021
5022 if (add) {
5023 if (i == E1000_VLVF_ARRAY_SIZE) {
5024 /* Did not find a matching VLAN ID entry that was
5025 * enabled. Search for a free filter entry, i.e.
5026 * one without the enable bit set
5027 */
5028 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5029 reg = rd32(E1000_VLVF(i));
5030 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5031 break;
5032 }
5033 }
5034 if (i < E1000_VLVF_ARRAY_SIZE) {
5035 /* Found an enabled/available entry */
5036 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5037
5038 /* if !enabled we need to set this up in vfta */
5039 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5040 /* add VID to filter table */
5041 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5042 reg |= E1000_VLVF_VLANID_ENABLE;
5043 }
cad6d05f
AD		 5044 reg &= ~E1000_VLVF_VLANID_MASK;
5045 reg |= vid;
4ae196df 5046 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5047
5048 /* do not modify RLPML for PF devices */
5049 if (vf >= adapter->vfs_allocated_count)
5050 return 0;
5051
5052 if (!adapter->vf_data[vf].vlans_enabled) {
5053 u32 size;
5054 reg = rd32(E1000_VMOLR(vf));
5055 size = reg & E1000_VMOLR_RLPML_MASK;
5056 size += 4;
5057 reg &= ~E1000_VMOLR_RLPML_MASK;
5058 reg |= size;
5059 wr32(E1000_VMOLR(vf), reg);
5060 }
ae641bdc 5061
51466239 5062 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5063 return 0;
5064 }
5065 } else {
5066 if (i < E1000_VLVF_ARRAY_SIZE) {
5067 /* remove vf from the pool */
5068 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5069 /* if pool is empty then remove entry from vfta */
5070 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5071 reg = 0;
5072 igb_vfta_set(hw, vid, false);
5073 }
5074 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5075
5076 /* do not modify RLPML for PF devices */
5077 if (vf >= adapter->vfs_allocated_count)
5078 return 0;
5079
5080 adapter->vf_data[vf].vlans_enabled--;
5081 if (!adapter->vf_data[vf].vlans_enabled) {
5082 u32 size;
5083 reg = rd32(E1000_VMOLR(vf));
5084 size = reg & E1000_VMOLR_RLPML_MASK;
5085 size -= 4;
5086 reg &= ~E1000_VMOLR_RLPML_MASK;
5087 reg |= size;
5088 wr32(E1000_VMOLR(vf), reg);
5089 }
4ae196df
AD		 5090 }
5091 }
8151d294
WM		 5092 return 0;
5093}
5094
5095static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5096{
5097 struct e1000_hw *hw = &adapter->hw;
5098
5099 if (vid)
5100 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5101 else
5102 wr32(E1000_VMVIR(vf), 0);
5103}
5104
5105static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5106 int vf, u16 vlan, u8 qos)
5107{
5108 int err = 0;
5109 struct igb_adapter *adapter = netdev_priv(netdev);
5110
5111 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5112 return -EINVAL;
5113 if (vlan || qos) {
5114 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5115 if (err)
5116 goto out;
5117 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5118 igb_set_vmolr(adapter, vf, !vlan);
5119 adapter->vf_data[vf].pf_vlan = vlan;
5120 adapter->vf_data[vf].pf_qos = qos;
5121 dev_info(&adapter->pdev->dev,
5122 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5123 if (test_bit(__IGB_DOWN, &adapter->state)) {
5124 dev_warn(&adapter->pdev->dev,
5125 "The VF VLAN has been set,"
5126 " but the PF device is not up.\n");
5127 dev_warn(&adapter->pdev->dev,
5128 "Bring the PF device up before"
5129 " attempting to use the VF device.\n");
5130 }
5131 } else {
5132 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5133 false, vf);
5134 igb_set_vmvir(adapter, vlan, vf);
5135 igb_set_vmolr(adapter, vf, true);
5136 adapter->vf_data[vf].pf_vlan = 0;
5137 adapter->vf_data[vf].pf_qos = 0;
5138 }
5139out:
5140 return err;
4ae196df
AD		 5141}
5142
5143static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5144{
5145 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5146 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5147
5148 return igb_vlvf_set(adapter, vid, add, vf);
5149}
5150
f2ca0dbe 5151static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5152{
8fa7e0f7
GR		 5153 /* clear flags - except flag that indicates PF has set the MAC */
5154 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5155 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5156
5157 /* reset offloads to defaults */
8151d294 5158 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5159
5160 /* reset vlans for device */
5161 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5162 if (adapter->vf_data[vf].pf_vlan)
5163 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5164 adapter->vf_data[vf].pf_vlan,
5165 adapter->vf_data[vf].pf_qos);
5166 else
5167 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5168
5169 /* reset multicast table array for vf */
5170 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5171
5172 /* Flush and reset the mta with the new values */
ff41f8dc 5173 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5174}
5175
f2ca0dbe
AD		 5176static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5177{
5178 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5179
5180 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 5181 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5182 random_ether_addr(vf_mac);
f2ca0dbe
AD		 5183
5184 /* process remaining reset events */
5185 igb_vf_reset(adapter, vf);
5186}
5187
5188static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5189{
5190 struct e1000_hw *hw = &adapter->hw;
5191 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5192 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5193 u32 reg, msgbuf[3];
5194 u8 *addr = (u8 *)(&msgbuf[1]);
5195
5196 /* process all the same items cleared in a function level reset */
f2ca0dbe 5197 igb_vf_reset(adapter, vf);
4ae196df
AD		 5198
5199 /* set vf mac address */
26ad9178 5200 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5201
5202 /* enable transmit and receive for vf */
5203 reg = rd32(E1000_VFTE);
5204 wr32(E1000_VFTE, reg | (1 << vf));
5205 reg = rd32(E1000_VFRE);
5206 wr32(E1000_VFRE, reg | (1 << vf));
5207
8fa7e0f7 5208 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5209
5210 /* reply to reset with ack and vf mac address */
5211 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5212 memcpy(addr, vf_mac, 6);
5213 igb_write_mbx(hw, msgbuf, 3, vf);
5214}
5215
5216static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5217{
de42edde
GR		 5218 /*
5219 * The VF MAC Address is stored in a packed array of bytes
5220 * starting at the second 32 bit word of the msg array
5221 */
f2ca0dbe
AD		 5222 unsigned char *addr = (char *)&msg[1];
5223 int err = -1;
4ae196df 5224
f2ca0dbe
AD		 5225 if (is_valid_ether_addr(addr))
5226 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5227
f2ca0dbe 5228 return err;
4ae196df
AD		 5229}
5230
5231static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5232{
5233 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5234 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5235 u32 msg = E1000_VT_MSGTYPE_NACK;
5236
5237 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5238 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5239 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5240 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5241 vf_data->last_nack = jiffies;
4ae196df
AD		 5242 }
5243}
5244
f2ca0dbe 5245static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5246{
f2ca0dbe
AD		 5247 struct pci_dev *pdev = adapter->pdev;
5248 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5249 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5250 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5251 s32 retval;
5252
f2ca0dbe 5253 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5254
fef45f4c
AD		 5255 if (retval) {
5256 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5257 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5258 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5259 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5260 return;
5261 goto out;
5262 }
4ae196df
AD		 5263
5264 /* this is a message we already processed, do nothing */
5265 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5266 return;
4ae196df
AD		 5267
5268 /*
5269 * until the vf completes a reset it should not be
5270 * allowed to start any configuration.
5271 */
5272
5273 if (msgbuf[0] == E1000_VF_RESET) {
5274 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5275 return;
4ae196df
AD		 5276 }
5277
f2ca0dbe 5278 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5279 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5280 return;
5281 retval = -1;
5282 goto out;
4ae196df
AD		 5283 }
5284
5285 switch ((msgbuf[0] & 0xFFFF)) {
5286 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5287 retval = -EINVAL;
5288 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5289 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5290 else
5291 dev_warn(&pdev->dev,
5292 "VF %d attempted to override administratively "
5293 "set MAC address\nReload the VF driver to "
5294 "resume operations\n", vf);
4ae196df 5295 break;
7d5753f0
AD		 5296 case E1000_VF_SET_PROMISC:
5297 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5298 break;
4ae196df
AD		 5299 case E1000_VF_SET_MULTICAST:
5300 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5301 break;
5302 case E1000_VF_SET_LPE:
5303 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5304 break;
5305 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5306 retval = -1;
5307 if (vf_data->pf_vlan)
5308 dev_warn(&pdev->dev,
5309 "VF %d attempted to override administratively "
5310 "set VLAN tag\nReload the VF driver to "
5311 "resume operations\n", vf);
8151d294
WM		 5312 else
5313 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5314 break;
5315 default:
090b1795 5316 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5317 retval = -1;
5318 break;
5319 }
5320
fef45f4c
AD		 5321 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5322out:
4ae196df
AD		 5323 /* notify the VF of the results of what it sent us */
5324 if (retval)
5325 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5326 else
5327 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5328
4ae196df 5329 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5330}
4ae196df 5331
f2ca0dbe
AD		 5332static void igb_msg_task(struct igb_adapter *adapter)
5333{
5334 struct e1000_hw *hw = &adapter->hw;
5335 u32 vf;
5336
5337 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5338 /* process any reset requests */
5339 if (!igb_check_for_rst(hw, vf))
5340 igb_vf_reset_event(adapter, vf);
5341
5342 /* process any messages pending */
5343 if (!igb_check_for_msg(hw, vf))
5344 igb_rcv_msg_from_vf(adapter, vf);
5345
5346 /* process any acks */
5347 if (!igb_check_for_ack(hw, vf))
5348 igb_rcv_ack_from_vf(adapter, vf);
5349 }
4ae196df
AD		 5350}
5351
68d480c4
AD		 5352/**
5353 * igb_set_uta - Set unicast filter table address
5354 * @adapter: board private structure
5355 *
5356 * The unicast table address is a register array of 32-bit registers.
5357 * The table is meant to be used in a way similar to how the MTA is used
5358 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5359 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5360 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5361 **/
5362static void igb_set_uta(struct igb_adapter *adapter)
5363{
5364 struct e1000_hw *hw = &adapter->hw;
5365 int i;
5366
5367 /* The UTA table only exists on 82576 hardware and newer */
5368 if (hw->mac.type < e1000_82576)
5369 return;
5370
5371 /* we only need to do this if VMDq is enabled */
5372 if (!adapter->vfs_allocated_count)
5373 return;
5374
5375 for (i = 0; i < hw->mac.uta_reg_count; i++)
5376 array_wr32(E1000_UTA, i, ~0);
5377}
5378
9d5c8243
AK		 5379/**
5380 * igb_intr_msi - Interrupt Handler
5381 * @irq: interrupt number
5382 * @data: pointer to a network interface device structure
5383 **/
5384static irqreturn_t igb_intr_msi(int irq, void *data)
5385{
047e0030
AD		 5386 struct igb_adapter *adapter = data;
5387 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5388 struct e1000_hw *hw = &adapter->hw;
5389 /* read ICR disables interrupts using IAM */
5390 u32 icr = rd32(E1000_ICR);
5391
047e0030 5392 igb_write_itr(q_vector);
9d5c8243 5393
7f081d40
AD		 5394 if (icr & E1000_ICR_DRSTA)
5395 schedule_work(&adapter->reset_task);
5396
047e0030 5397 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5398 /* HW is reporting DMA is out of sync */
5399 adapter->stats.doosync++;
5400 }
5401
9d5c8243
AK		 5402 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5403 hw->mac.get_link_status = 1;
5404 if (!test_bit(__IGB_DOWN, &adapter->state))
5405 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5406 }
5407
047e0030 5408 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5409
5410 return IRQ_HANDLED;
5411}
5412
5413/**
4a3c6433 5414 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5415 * @irq: interrupt number
5416 * @data: pointer to a network interface device structure
5417 **/
5418static irqreturn_t igb_intr(int irq, void *data)
5419{
047e0030
AD		 5420 struct igb_adapter *adapter = data;
5421 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5422 struct e1000_hw *hw = &adapter->hw;
5423 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5424 * need for the IMC write */
5425 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5426 if (!icr)
5427 return IRQ_NONE; /* Not our interrupt */
5428
047e0030 5429 igb_write_itr(q_vector);
9d5c8243
AK		 5430
5431 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5432 * not set, then the adapter didn't send an interrupt */
5433 if (!(icr & E1000_ICR_INT_ASSERTED))
5434 return IRQ_NONE;
5435
7f081d40
AD		 5436 if (icr & E1000_ICR_DRSTA)
5437 schedule_work(&adapter->reset_task);
5438
047e0030 5439 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5440 /* HW is reporting DMA is out of sync */
5441 adapter->stats.doosync++;
5442 }
5443
9d5c8243
AK		 5444 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5445 hw->mac.get_link_status = 1;
5446 /* guard against interrupt when we're going down */
5447 if (!test_bit(__IGB_DOWN, &adapter->state))
5448 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5449 }
5450
047e0030 5451 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5452
5453 return IRQ_HANDLED;
5454}
5455
047e0030 5456static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5457{
047e0030 5458 struct igb_adapter *adapter = q_vector->adapter;
46544258 5459 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5460
4fc82adf
AD		 5461 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
5462 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 5463 if (!adapter->msix_entries)
6eb5a7f1 5464 igb_set_itr(adapter);
46544258 5465 else
047e0030 5466 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5467 }
5468
46544258
AD		 5469 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5470 if (adapter->msix_entries)
047e0030 5471 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5472 else
5473 igb_irq_enable(adapter);
5474 }
9d5c8243
AK		 5475}
5476
46544258
AD		 5477/**
5478 * igb_poll - NAPI Rx polling callback
5479 * @napi: napi polling structure
5480 * @budget: count of how many packets we should handle
5481 **/
5482static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5483{
047e0030
AD		 5484 struct igb_q_vector *q_vector = container_of(napi,
5485 struct igb_q_vector,
5486 napi);
5487 int tx_clean_complete = 1, work_done = 0;
9d5c8243 5488
421e02f0 5489#ifdef CONFIG_IGB_DCA
047e0030
AD		 5490 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5491 igb_update_dca(q_vector);
fe4506b6 5492#endif
047e0030
AD		 5493 if (q_vector->tx_ring)
5494 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5495
047e0030
AD		 5496 if (q_vector->rx_ring)
5497 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
5498
5499 if (!tx_clean_complete)
5500 work_done = budget;
46544258 5501
9d5c8243 5502 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 5503 if (work_done < budget) {
288379f0 5504 napi_complete(napi);
047e0030 5505 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 5506 }
5507
46544258 5508 return work_done;
9d5c8243 5509}
6d8126f9 5510
33af6bcc 5511/**
c5b9bd5e 5512 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 5513 * @adapter: board private structure
c5b9bd5e
AD		 5514 * @shhwtstamps: timestamp structure to update
5515 * @regval: unsigned 64bit system time value.
5516 *
5517 * We need to convert the system time value stored in the RX/TXSTMP registers
5518 * into a hwtstamp which can be used by the upper level timestamping functions
5519 */
5520static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5521 struct skb_shared_hwtstamps *shhwtstamps,
5522 u64 regval)
5523{
5524 u64 ns;
5525
55cac248
AD		 5526 /*
5527 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5528 * 24 to match clock shift we setup earlier.
5529 */
5530 if (adapter->hw.mac.type == e1000_82580)
5531 regval <<= IGB_82580_TSYNC_SHIFT;
5532
c5b9bd5e
AD		 5533 ns = timecounter_cyc2time(&adapter->clock, regval);
5534 timecompare_update(&adapter->compare, ns);
5535 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5536 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5537 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5538}
5539
5540/**
5541 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5542 * @q_vector: pointer to q_vector containing needed info
2873957d 5543 * @buffer: pointer to igb_buffer structure
33af6bcc
PO		 5544 *
5545 * If we were asked to do hardware stamping and such a time stamp is
5546 * available, then it must have been for this skb here because we only
5547 * allow only one such packet into the queue.
5548 */
2873957d 5549static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct igb_buffer *buffer_info)
33af6bcc 5550{
c5b9bd5e 5551 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc 5552 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 5553 struct skb_shared_hwtstamps shhwtstamps;
5554 u64 regval;
33af6bcc 5555
c5b9bd5e 5556 /* if skb does not support hw timestamp or TX stamp not valid exit */
2244d07b 5557 if (likely(!(buffer_info->tx_flags & SKBTX_HW_TSTAMP)) ||
c5b9bd5e
AD		 5558 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5559 return;
5560
5561 regval = rd32(E1000_TXSTMPL);
5562 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5563
5564 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
2873957d 5565 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
33af6bcc
PO		 5566}
5567
9d5c8243
AK		 5568/**
5569 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5570 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 5571 * returns true if ring is completely cleaned
5572 **/
047e0030 5573static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5574{
047e0030
AD		 5575 struct igb_adapter *adapter = q_vector->adapter;
5576 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 5577 struct net_device *netdev = tx_ring->netdev;
0e014cb1 5578 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5579 struct igb_buffer *buffer_info;
0e014cb1 5580 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5581 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 5582 unsigned int i, eop, count = 0;
5583 bool cleaned = false;
9d5c8243 5584
9d5c8243 5585 i = tx_ring->next_to_clean;
0e014cb1
AD		 5586 eop = tx_ring->buffer_info[i].next_to_watch;
5587 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5588
5589 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
5590 (count < tx_ring->count)) {
2d0bb1c1 5591 rmb(); /* read buffer_info after eop_desc status */
0e014cb1
AD		 5592 for (cleaned = false; !cleaned; count++) {
5593 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5594 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5595 cleaned = (i == eop);
9d5c8243 5596
2873957d
NN		 5597 if (buffer_info->skb) {
5598 total_bytes += buffer_info->bytecount;
9d5c8243 5599 /* gso_segs is currently only valid for tcp */
2873957d
NN		 5600 total_packets += buffer_info->gso_segs;
5601 igb_tx_hwtstamp(q_vector, buffer_info);
9d5c8243
AK		 5602 }
5603
80785298 5604 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5605 tx_desc->wb.status = 0;
9d5c8243
AK		 5606
5607 i++;
5608 if (i == tx_ring->count)
5609 i = 0;
9d5c8243 5610 }
0e014cb1
AD		 5611 eop = tx_ring->buffer_info[i].next_to_watch;
5612 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5613 }
5614
9d5c8243
AK		 5615 tx_ring->next_to_clean = i;
5616
fc7d345d 5617 if (unlikely(count &&
9d5c8243 5618 netif_carrier_ok(netdev) &&
c493ea45 5619 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5620 /* Make sure that anybody stopping the queue after this
5621 * sees the new next_to_clean.
5622 */
5623 smp_mb();
661086df
PWJ		 5624 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5625 !(test_bit(__IGB_DOWN, &adapter->state))) {
5626 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 5627
5628 u64_stats_update_begin(&tx_ring->tx_syncp);
04a5fcaa 5629 tx_ring->tx_stats.restart_queue++;
12dcd86b 5630 u64_stats_update_end(&tx_ring->tx_syncp);
661086df 5631 }
9d5c8243
AK		 5632 }
5633
5634 if (tx_ring->detect_tx_hung) {
5635 /* Detect a transmit hang in hardware, this serializes the
5636 * check with the clearing of time_stamp and movement of i */
5637 tx_ring->detect_tx_hung = false;
5638 if (tx_ring->buffer_info[i].time_stamp &&
5639 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5640 (adapter->tx_timeout_factor * HZ)) &&
5641 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5642
9d5c8243 5643 /* detected Tx unit hang */
59d71989 5644 dev_err(tx_ring->dev,
9d5c8243 5645 "Detected Tx Unit Hang\n"
2d064c06 5646 " Tx Queue <%d>\n"
9d5c8243
AK		 5647 " TDH <%x>\n"
5648 " TDT <%x>\n"
5649 " next_to_use <%x>\n"
5650 " next_to_clean <%x>\n"
9d5c8243
AK		 5651 "buffer_info[next_to_clean]\n"
5652 " time_stamp <%lx>\n"
0e014cb1 5653 " next_to_watch <%x>\n"
9d5c8243
AK		 5654 " jiffies <%lx>\n"
5655 " desc.status <%x>\n",
2d064c06 5656 tx_ring->queue_index,
fce99e34
AD		 5657 readl(tx_ring->head),
5658 readl(tx_ring->tail),
9d5c8243
AK		 5659 tx_ring->next_to_use,
5660 tx_ring->next_to_clean,
f7ba205e 5661 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5662 eop,
9d5c8243 5663 jiffies,
0e014cb1 5664 eop_desc->wb.status);
661086df 5665 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5666 }
5667 }
5668 tx_ring->total_bytes += total_bytes;
5669 tx_ring->total_packets += total_packets;
12dcd86b 5670 u64_stats_update_begin(&tx_ring->tx_syncp);
e21ed353
AD		 5671 tx_ring->tx_stats.bytes += total_bytes;
5672 tx_ring->tx_stats.packets += total_packets;
12dcd86b 5673 u64_stats_update_end(&tx_ring->tx_syncp);
807540ba 5674 return count < tx_ring->count;
9d5c8243
AK		 5675}
5676
04a5fcaa 5677static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5678 u32 status_err, struct sk_buff *skb)
5679{
bc8acf2c 5680 skb_checksum_none_assert(skb);
9d5c8243
AK		 5681
5682 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5683 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5684 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5685 return;
85ad76b2 5686
9d5c8243
AK		 5687 /* TCP/UDP checksum error bit is set */
5688 if (status_err &
5689 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5690 /*
5691 * work around errata with sctp packets where the TCPE aka
5692 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5693 * packets, (aka let the stack check the crc32c)
5694 */
85ad76b2 5695 if ((skb->len == 60) &&
12dcd86b
ED		 5696 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) {
5697 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 5698 ring->rx_stats.csum_err++;
12dcd86b
ED		 5699 u64_stats_update_end(&ring->rx_syncp);
5700 }
9d5c8243 5701 /* let the stack verify checksum errors */
9d5c8243
AK		 5702 return;
5703 }
5704 /* It must be a TCP or UDP packet with a valid checksum */
5705 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5706 skb->ip_summed = CHECKSUM_UNNECESSARY;
5707
59d71989 5708 dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5709}
5710
757b77e2 5711static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
c5b9bd5e
AD		 5712 struct sk_buff *skb)
5713{
5714 struct igb_adapter *adapter = q_vector->adapter;
5715 struct e1000_hw *hw = &adapter->hw;
5716 u64 regval;
5717
5718 /*
5719 * If this bit is set, then the RX registers contain the time stamp. No
5720 * other packet will be time stamped until we read these registers, so
5721 * read the registers to make them available again. Because only one
5722 * packet can be time stamped at a time, we know that the register
5723 * values must belong to this one here and therefore we don't need to
5724 * compare any of the additional attributes stored for it.
5725 *
2244d07b 5726 * If nothing went wrong, then it should have a shared tx_flags that we
c5b9bd5e
AD		 5727 * can turn into a skb_shared_hwtstamps.
5728 */
757b77e2
NN		 5729 if (staterr & E1000_RXDADV_STAT_TSIP) {
5730 u32 *stamp = (u32 *)skb->data;
5731 regval = le32_to_cpu(*(stamp + 2));
5732 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5733 skb_pull(skb, IGB_TS_HDR_LEN);
5734 } else {
5735 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5736 return;
c5b9bd5e 5737
757b77e2
NN		 5738 regval = rd32(E1000_RXSTMPL);
5739 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5740 }
c5b9bd5e
AD		 5741
5742 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5743}
44390ca6 5744static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc)
2d94d8ab
AD		 5745{
5746 /* HW will not DMA in data larger than the given buffer, even if it
5747 * parses the (NFS, of course) header to be larger. In that case, it
5748 * fills the header buffer and spills the rest into the page.
5749 */
5750 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5751 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
44390ca6
AD		 5752 if (hlen > IGB_RX_HDR_LEN)
5753 hlen = IGB_RX_HDR_LEN;
2d94d8ab
AD		 5754 return hlen;
5755}
5756
047e0030
AD		 5757static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5758 int *work_done, int budget)
9d5c8243 5759{
047e0030 5760 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5761 struct net_device *netdev = rx_ring->netdev;
59d71989 5762 struct device *dev = rx_ring->dev;
9d5c8243
AK		 5763 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5764 struct igb_buffer *buffer_info , *next_buffer;
5765 struct sk_buff *skb;
9d5c8243
AK		 5766 bool cleaned = false;
5767 int cleaned_count = 0;
d1eff350 5768 int current_node = numa_node_id();
9d5c8243 5769 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5770 unsigned int i;
2d94d8ab
AD		 5771 u32 staterr;
5772 u16 length;
9d5c8243
AK		 5773
5774 i = rx_ring->next_to_clean;
69d3ca53 5775 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5776 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5777 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5778
5779 while (staterr & E1000_RXD_STAT_DD) {
5780 if (*work_done >= budget)
5781 break;
5782 (*work_done)++;
2d0bb1c1 5783 rmb(); /* read descriptor and rx_buffer_info after status DD */
9d5c8243 5784
69d3ca53
AD		 5785 skb = buffer_info->skb;
5786 prefetch(skb->data - NET_IP_ALIGN);
5787 buffer_info->skb = NULL;
5788
5789 i++;
5790 if (i == rx_ring->count)
5791 i = 0;
42d0781a 5792
69d3ca53
AD		 5793 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5794 prefetch(next_rxd);
5795 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5796
5797 length = le16_to_cpu(rx_desc->wb.upper.length);
5798 cleaned = true;
5799 cleaned_count++;
5800
2d94d8ab 5801 if (buffer_info->dma) {
59d71989 5802 dma_unmap_single(dev, buffer_info->dma,
44390ca6 5803 IGB_RX_HDR_LEN,
59d71989 5804 DMA_FROM_DEVICE);
91615f76 5805 buffer_info->dma = 0;
44390ca6 5806 skb_put(skb, igb_get_hlen(rx_desc));
bf36c1a0
AD		 5807 }
5808
5809 if (length) {
59d71989
AD		 5810 dma_unmap_page(dev, buffer_info->page_dma,
5811 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9d5c8243 5812 buffer_info->page_dma = 0;
bf36c1a0 5813
aa913403 5814 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
bf36c1a0
AD		 5815 buffer_info->page,
5816 buffer_info->page_offset,
5817 length);
5818
d1eff350
AD		 5819 if ((page_count(buffer_info->page) != 1) ||
5820 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5821 buffer_info->page = NULL;
5822 else
5823 get_page(buffer_info->page);
9d5c8243
AK		 5824
5825 skb->len += length;
5826 skb->data_len += length;
bf36c1a0 5827 skb->truesize += length;
9d5c8243 5828 }
9d5c8243 5829
bf36c1a0 5830 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5831 buffer_info->skb = next_buffer->skb;
5832 buffer_info->dma = next_buffer->dma;
5833 next_buffer->skb = skb;
5834 next_buffer->dma = 0;
bf36c1a0
AD		 5835 goto next_desc;
5836 }
44390ca6 5837
9d5c8243
AK		 5838 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5839 dev_kfree_skb_irq(skb);
5840 goto next_desc;
5841 }
9d5c8243 5842
757b77e2
NN		 5843 if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
5844 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5845 total_bytes += skb->len;
5846 total_packets++;
5847
85ad76b2 5848 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5849
5850 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5851 skb_record_rx_queue(skb, rx_ring->queue_index);
5852
b2cb09b1
JP		 5853 if (staterr & E1000_RXD_STAT_VP) {
5854 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
9d5c8243 5855
b2cb09b1
JP		 5856 __vlan_hwaccel_put_tag(skb, vid);
5857 }
5858 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 5859
9d5c8243
AK		 5860next_desc:
5861 rx_desc->wb.upper.status_error = 0;
5862
5863 /* return some buffers to hardware, one at a time is too slow */
5864 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5865 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5866 cleaned_count = 0;
5867 }
5868
5869 /* use prefetched values */
5870 rx_desc = next_rxd;
5871 buffer_info = next_buffer;
9d5c8243
AK		 5872 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5873 }
bf36c1a0 5874
9d5c8243 5875 rx_ring->next_to_clean = i;
c493ea45 5876 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5877
5878 if (cleaned_count)
3b644cf6 5879 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5880
5881 rx_ring->total_packets += total_packets;
5882 rx_ring->total_bytes += total_bytes;
12dcd86b 5883 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 5884 rx_ring->rx_stats.packets += total_packets;
5885 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 5886 u64_stats_update_end(&rx_ring->rx_syncp);
9d5c8243
AK		 5887 return cleaned;
5888}
5889
9d5c8243
AK		 5890/**
5891 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5892 * @adapter: address of board private structure
5893 **/
d7ee5b3a 5894void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5895{
e694e964 5896 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5897 union e1000_adv_rx_desc *rx_desc;
5898 struct igb_buffer *buffer_info;
5899 struct sk_buff *skb;
5900 unsigned int i;
5901
5902 i = rx_ring->next_to_use;
5903 buffer_info = &rx_ring->buffer_info[i];
5904
5905 while (cleaned_count--) {
5906 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5907
44390ca6 5908 if (!buffer_info->page_dma) {
9d5c8243 5909 if (!buffer_info->page) {
42d0781a 5910 buffer_info->page = netdev_alloc_page(netdev);
12dcd86b
ED		 5911 if (unlikely(!buffer_info->page)) {
5912 u64_stats_update_begin(&rx_ring->rx_syncp);
04a5fcaa 5913 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5914 u64_stats_update_end(&rx_ring->rx_syncp);
bf36c1a0
AD		 5915 goto no_buffers;
5916 }
5917 buffer_info->page_offset = 0;
5918 } else {
5919 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5920 }
5921 buffer_info->page_dma =
59d71989 5922 dma_map_page(rx_ring->dev, buffer_info->page,
bf36c1a0
AD		 5923 buffer_info->page_offset,
5924 PAGE_SIZE / 2,
59d71989
AD		 5925 DMA_FROM_DEVICE);
5926 if (dma_mapping_error(rx_ring->dev,
5927 buffer_info->page_dma)) {
42d0781a 5928 buffer_info->page_dma = 0;
12dcd86b 5929 u64_stats_update_begin(&rx_ring->rx_syncp);
42d0781a 5930 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5931 u64_stats_update_end(&rx_ring->rx_syncp);
42d0781a
AD		 5932 goto no_buffers;
5933 }
9d5c8243
AK		 5934 }
5935
42d0781a
AD		 5936 skb = buffer_info->skb;
5937 if (!skb) {
44390ca6 5938 skb = netdev_alloc_skb_ip_align(netdev, IGB_RX_HDR_LEN);
12dcd86b
ED		 5939 if (unlikely(!skb)) {
5940 u64_stats_update_begin(&rx_ring->rx_syncp);
04a5fcaa 5941 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5942 u64_stats_update_end(&rx_ring->rx_syncp);
9d5c8243
AK		 5943 goto no_buffers;
5944 }
5945
9d5c8243 5946 buffer_info->skb = skb;
42d0781a
AD		 5947 }
5948 if (!buffer_info->dma) {
59d71989 5949 buffer_info->dma = dma_map_single(rx_ring->dev,
80785298 5950 skb->data,
44390ca6 5951 IGB_RX_HDR_LEN,
59d71989
AD		 5952 DMA_FROM_DEVICE);
5953 if (dma_mapping_error(rx_ring->dev,
5954 buffer_info->dma)) {
42d0781a 5955 buffer_info->dma = 0;
12dcd86b 5956 u64_stats_update_begin(&rx_ring->rx_syncp);
42d0781a 5957 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5958 u64_stats_update_end(&rx_ring->rx_syncp);
42d0781a
AD		 5959 goto no_buffers;
5960 }
9d5c8243
AK		 5961 }
5962 /* Refresh the desc even if buffer_addrs didn't change because
5963 * each write-back erases this info. */
44390ca6
AD		 5964 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->page_dma);
5965 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5966
5967 i++;
5968 if (i == rx_ring->count)
5969 i = 0;
5970 buffer_info = &rx_ring->buffer_info[i];
5971 }
5972
5973no_buffers:
5974 if (rx_ring->next_to_use != i) {
5975 rx_ring->next_to_use = i;
5976 if (i == 0)
5977 i = (rx_ring->count - 1);
5978 else
5979 i--;
5980
5981 /* Force memory writes to complete before letting h/w
5982 * know there are new descriptors to fetch. (Only
5983 * applicable for weak-ordered memory model archs,
5984 * such as IA-64). */
5985 wmb();
fce99e34 5986 writel(i, rx_ring->tail);
9d5c8243
AK		 5987 }
5988}
5989
5990/**
5991 * igb_mii_ioctl -
5992 * @netdev:
5993 * @ifreq:
5994 * @cmd:
5995 **/
5996static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5997{
5998 struct igb_adapter *adapter = netdev_priv(netdev);
5999 struct mii_ioctl_data *data = if_mii(ifr);
6000
6001 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6002 return -EOPNOTSUPP;
6003
6004 switch (cmd) {
6005 case SIOCGMIIPHY:
6006 data->phy_id = adapter->hw.phy.addr;
6007 break;
6008 case SIOCGMIIREG:
f5f4cf08
AD		 6009 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6010 &data->val_out))
9d5c8243
AK		 6011 return -EIO;
6012 break;
6013 case SIOCSMIIREG:
6014 default:
6015 return -EOPNOTSUPP;
6016 }
6017 return 0;
6018}
6019
c6cb090b
PO		 6020/**
6021 * igb_hwtstamp_ioctl - control hardware time stamping
6022 * @netdev:
6023 * @ifreq:
6024 * @cmd:
6025 *
33af6bcc
PO		 6026 * Outgoing time stamping can be enabled and disabled. Play nice and
6027 * disable it when requested, although it shouldn't case any overhead
6028 * when no packet needs it. At most one packet in the queue may be
6029 * marked for time stamping, otherwise it would be impossible to tell
6030 * for sure to which packet the hardware time stamp belongs.
6031 *
6032 * Incoming time stamping has to be configured via the hardware
6033 * filters. Not all combinations are supported, in particular event
6034 * type has to be specified. Matching the kind of event packet is
6035 * not supported, with the exception of "all V2 events regardless of
6036 * level 2 or 4".
6037 *
c6cb090b
PO		 6038 **/
6039static int igb_hwtstamp_ioctl(struct net_device *netdev,
6040 struct ifreq *ifr, int cmd)
6041{
33af6bcc
PO		 6042 struct igb_adapter *adapter = netdev_priv(netdev);
6043 struct e1000_hw *hw = &adapter->hw;
c6cb090b 6044 struct hwtstamp_config config;
c5b9bd5e
AD		 6045 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
6046 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 6047 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 6048 bool is_l4 = false;
6049 bool is_l2 = false;
33af6bcc 6050 u32 regval;
c6cb090b
PO		 6051
6052 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6053 return -EFAULT;
6054
6055 /* reserved for future extensions */
6056 if (config.flags)
6057 return -EINVAL;
6058
33af6bcc
PO		 6059 switch (config.tx_type) {
6060 case HWTSTAMP_TX_OFF:
c5b9bd5e 6061 tsync_tx_ctl = 0;
33af6bcc 6062 case HWTSTAMP_TX_ON:
33af6bcc
PO		 6063 break;
6064 default:
6065 return -ERANGE;
6066 }
6067
6068 switch (config.rx_filter) {
6069 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 6070 tsync_rx_ctl = 0;
33af6bcc
PO		 6071 break;
6072 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6073 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6074 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6075 case HWTSTAMP_FILTER_ALL:
6076 /*
6077 * register TSYNCRXCFG must be set, therefore it is not
6078 * possible to time stamp both Sync and Delay_Req messages
6079 * => fall back to time stamping all packets
6080 */
c5b9bd5e 6081 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 6082 config.rx_filter = HWTSTAMP_FILTER_ALL;
6083 break;
6084 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 6085 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6086 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 6087 is_l4 = true;
33af6bcc
PO		 6088 break;
6089 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 6090 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6091 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 6092 is_l4 = true;
33af6bcc
PO		 6093 break;
6094 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6095 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 6096 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6097 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 6098 is_l2 = true;
6099 is_l4 = true;
33af6bcc
PO		 6100 config.rx_filter = HWTSTAMP_FILTER_SOME;
6101 break;
6102 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6103 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 6104 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6105 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 6106 is_l2 = true;
6107 is_l4 = true;
33af6bcc
PO		 6108 config.rx_filter = HWTSTAMP_FILTER_SOME;
6109 break;
6110 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6111 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6112 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 6113 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 6114 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 6115 is_l2 = true;
33af6bcc
PO		 6116 break;
6117 default:
6118 return -ERANGE;
6119 }
6120
c5b9bd5e
AD		 6121 if (hw->mac.type == e1000_82575) {
6122 if (tsync_rx_ctl | tsync_tx_ctl)
6123 return -EINVAL;
6124 return 0;
6125 }
6126
757b77e2
NN		 6127 /*
6128 * Per-packet timestamping only works if all packets are
6129 * timestamped, so enable timestamping in all packets as
6130 * long as one rx filter was configured.
6131 */
6132 if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
6133 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6134 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6135 }
6136
33af6bcc
PO		 6137 /* enable/disable TX */
6138 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 6139 regval &= ~E1000_TSYNCTXCTL_ENABLED;
6140 regval |= tsync_tx_ctl;
33af6bcc
PO		 6141 wr32(E1000_TSYNCTXCTL, regval);
6142
c5b9bd5e 6143 /* enable/disable RX */
33af6bcc 6144 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 6145 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
6146 regval |= tsync_rx_ctl;
33af6bcc 6147 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 6148
c5b9bd5e
AD		 6149 /* define which PTP packets are time stamped */
6150 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 6151
c5b9bd5e
AD		 6152 /* define ethertype filter for timestamped packets */
6153 if (is_l2)
6154 wr32(E1000_ETQF(3),
6155 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
6156 E1000_ETQF_1588 | /* enable timestamping */
6157 ETH_P_1588)); /* 1588 eth protocol type */
6158 else
6159 wr32(E1000_ETQF(3), 0);
6160
6161#define PTP_PORT 319
6162 /* L4 Queue Filter[3]: filter by destination port and protocol */
6163 if (is_l4) {
6164 u32 ftqf = (IPPROTO_UDP /* UDP */
6165 | E1000_FTQF_VF_BP /* VF not compared */
6166 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
6167 | E1000_FTQF_MASK); /* mask all inputs */
6168 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
6169
6170 wr32(E1000_IMIR(3), htons(PTP_PORT));
6171 wr32(E1000_IMIREXT(3),
6172 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
6173 if (hw->mac.type == e1000_82576) {
6174 /* enable source port check */
6175 wr32(E1000_SPQF(3), htons(PTP_PORT));
6176 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
6177 }
6178 wr32(E1000_FTQF(3), ftqf);
6179 } else {
6180 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
6181 }
33af6bcc
PO		 6182 wrfl();
6183
6184 adapter->hwtstamp_config = config;
6185
6186 /* clear TX/RX time stamp registers, just to be sure */
6187 regval = rd32(E1000_TXSTMPH);
6188 regval = rd32(E1000_RXSTMPH);
c6cb090b 6189
33af6bcc
PO		 6190 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
6191 -EFAULT : 0;
c6cb090b
PO		 6192}
6193
9d5c8243
AK		 6194/**
6195 * igb_ioctl -
6196 * @netdev:
6197 * @ifreq:
6198 * @cmd:
6199 **/
6200static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6201{
6202 switch (cmd) {
6203 case SIOCGMIIPHY:
6204 case SIOCGMIIREG:
6205 case SIOCSMIIREG:
6206 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 6207 case SIOCSHWTSTAMP:
6208 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6209 default:
6210 return -EOPNOTSUPP;
6211 }
6212}
6213
009bc06e
AD		 6214s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6215{
6216 struct igb_adapter *adapter = hw->back;
6217 u16 cap_offset;
6218
bdaae04c 6219 cap_offset = adapter->pdev->pcie_cap;
009bc06e
AD		 6220 if (!cap_offset)
6221 return -E1000_ERR_CONFIG;
6222
6223 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6224
6225 return 0;
6226}
6227
6228s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6229{
6230 struct igb_adapter *adapter = hw->back;
6231 u16 cap_offset;
6232
bdaae04c 6233 cap_offset = adapter->pdev->pcie_cap;
009bc06e
AD		 6234 if (!cap_offset)
6235 return -E1000_ERR_CONFIG;
6236
6237 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6238
6239 return 0;
6240}
6241
b2cb09b1 6242static void igb_vlan_mode(struct net_device *netdev, u32 features)
9d5c8243
AK		 6243{
6244 struct igb_adapter *adapter = netdev_priv(netdev);
6245 struct e1000_hw *hw = &adapter->hw;
6246 u32 ctrl, rctl;
6247
6248 igb_irq_disable(adapter);
9d5c8243 6249
b2cb09b1 6250 if (features & NETIF_F_HW_VLAN_RX) {
9d5c8243
AK		 6251 /* enable VLAN tag insert/strip */
6252 ctrl = rd32(E1000_CTRL);
6253 ctrl |= E1000_CTRL_VME;
6254 wr32(E1000_CTRL, ctrl);
6255
51466239 6256 /* Disable CFI check */
9d5c8243 6257 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6258 rctl &= ~E1000_RCTL_CFIEN;
6259 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6260 } else {
6261 /* disable VLAN tag insert/strip */
6262 ctrl = rd32(E1000_CTRL);
6263 ctrl &= ~E1000_CTRL_VME;
6264 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6265 }
6266
e1739522
AD		 6267 igb_rlpml_set(adapter);
6268
9d5c8243
AK		 6269 if (!test_bit(__IGB_DOWN, &adapter->state))
6270 igb_irq_enable(adapter);
6271}
6272
6273static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6274{
6275 struct igb_adapter *adapter = netdev_priv(netdev);
6276 struct e1000_hw *hw = &adapter->hw;
4ae196df 6277 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6278
51466239
AD		 6279 /* attempt to add filter to vlvf array */
6280 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6281
51466239
AD		 6282 /* add the filter since PF can receive vlans w/o entry in vlvf */
6283 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6284
6285 set_bit(vid, adapter->active_vlans);
9d5c8243
AK		 6286}
6287
6288static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6289{
6290 struct igb_adapter *adapter = netdev_priv(netdev);
6291 struct e1000_hw *hw = &adapter->hw;
4ae196df 6292 int pf_id = adapter->vfs_allocated_count;
51466239 6293 s32 err;
9d5c8243
AK		 6294
6295 igb_irq_disable(adapter);
9d5c8243
AK		 6296
6297 if (!test_bit(__IGB_DOWN, &adapter->state))
6298 igb_irq_enable(adapter);
6299
51466239
AD		 6300 /* remove vlan from VLVF table array */
6301 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6302
51466239
AD		 6303 /* if vid was not present in VLVF just remove it from table */
6304 if (err)
4ae196df 6305 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6306
6307 clear_bit(vid, adapter->active_vlans);
9d5c8243
AK		 6308}
6309
6310static void igb_restore_vlan(struct igb_adapter *adapter)
6311{
b2cb09b1 6312 u16 vid;
9d5c8243 6313
b2cb09b1
JP		 6314 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6315 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6316}
6317
14ad2513 6318int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6319{
090b1795 6320 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6321 struct e1000_mac_info *mac = &adapter->hw.mac;
6322
6323 mac->autoneg = 0;
6324
14ad2513
DD		 6325 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6326 * for the switch() below to work */
6327 if ((spd & 1) || (dplx & ~1))
6328 goto err_inval;
6329
cd2638a8
CW		 6330 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6331 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6332 spd != SPEED_1000 &&
6333 dplx != DUPLEX_FULL)
6334 goto err_inval;
cd2638a8 6335
14ad2513 6336 switch (spd + dplx) {
9d5c8243
AK		 6337 case SPEED_10 + DUPLEX_HALF:
6338 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6339 break;
6340 case SPEED_10 + DUPLEX_FULL:
6341 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6342 break;
6343 case SPEED_100 + DUPLEX_HALF:
6344 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6345 break;
6346 case SPEED_100 + DUPLEX_FULL:
6347 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6348 break;
6349 case SPEED_1000 + DUPLEX_FULL:
6350 mac->autoneg = 1;
6351 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6352 break;
6353 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6354 default:
14ad2513 6355 goto err_inval;
9d5c8243
AK		 6356 }
6357 return 0;
14ad2513
DD		 6358
6359err_inval:
6360 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6361 return -EINVAL;
9d5c8243
AK		 6362}
6363
3fe7c4c9 6364static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 6365{
6366 struct net_device *netdev = pci_get_drvdata(pdev);
6367 struct igb_adapter *adapter = netdev_priv(netdev);
6368 struct e1000_hw *hw = &adapter->hw;
2d064c06 6369 u32 ctrl, rctl, status;
9d5c8243
AK		 6370 u32 wufc = adapter->wol;
6371#ifdef CONFIG_PM
6372 int retval = 0;
6373#endif
6374
6375 netif_device_detach(netdev);
6376
a88f10ec
AD		 6377 if (netif_running(netdev))
6378 igb_close(netdev);
6379
047e0030 6380 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6381
6382#ifdef CONFIG_PM
6383 retval = pci_save_state(pdev);
6384 if (retval)
6385 return retval;
6386#endif
6387
6388 status = rd32(E1000_STATUS);
6389 if (status & E1000_STATUS_LU)
6390 wufc &= ~E1000_WUFC_LNKC;
6391
6392 if (wufc) {
6393 igb_setup_rctl(adapter);
ff41f8dc 6394 igb_set_rx_mode(netdev);
9d5c8243
AK		 6395
6396 /* turn on all-multi mode if wake on multicast is enabled */
6397 if (wufc & E1000_WUFC_MC) {
6398 rctl = rd32(E1000_RCTL);
6399 rctl |= E1000_RCTL_MPE;
6400 wr32(E1000_RCTL, rctl);
6401 }
6402
6403 ctrl = rd32(E1000_CTRL);
6404 /* advertise wake from D3Cold */
6405 #define E1000_CTRL_ADVD3WUC 0x00100000
6406 /* phy power management enable */
6407 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6408 ctrl |= E1000_CTRL_ADVD3WUC;
6409 wr32(E1000_CTRL, ctrl);
6410
9d5c8243 6411 /* Allow time for pending master requests to run */
330a6d6a 6412 igb_disable_pcie_master(hw);
9d5c8243
AK		 6413
6414 wr32(E1000_WUC, E1000_WUC_PME_EN);
6415 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6416 } else {
6417 wr32(E1000_WUC, 0);
6418 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6419 }
6420
3fe7c4c9
RW		 6421 *enable_wake = wufc || adapter->en_mng_pt;
6422 if (!*enable_wake)
88a268c1
NN		 6423 igb_power_down_link(adapter);
6424 else
6425 igb_power_up_link(adapter);
9d5c8243
AK		 6426
6427 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6428 * would have already happened in close and is redundant. */
6429 igb_release_hw_control(adapter);
6430
6431 pci_disable_device(pdev);
6432
9d5c8243
AK		 6433 return 0;
6434}
6435
6436#ifdef CONFIG_PM
3fe7c4c9
RW		 6437static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6438{
6439 int retval;
6440 bool wake;
6441
6442 retval = __igb_shutdown(pdev, &wake);
6443 if (retval)
6444 return retval;
6445
6446 if (wake) {
6447 pci_prepare_to_sleep(pdev);
6448 } else {
6449 pci_wake_from_d3(pdev, false);
6450 pci_set_power_state(pdev, PCI_D3hot);
6451 }
6452
6453 return 0;
6454}
6455
9d5c8243
AK		 6456static int igb_resume(struct pci_dev *pdev)
6457{
6458 struct net_device *netdev = pci_get_drvdata(pdev);
6459 struct igb_adapter *adapter = netdev_priv(netdev);
6460 struct e1000_hw *hw = &adapter->hw;
6461 u32 err;
6462
6463 pci_set_power_state(pdev, PCI_D0);
6464 pci_restore_state(pdev);
b94f2d77 6465 pci_save_state(pdev);
42bfd33a 6466
aed5dec3 6467 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6468 if (err) {
6469 dev_err(&pdev->dev,
6470 "igb: Cannot enable PCI device from suspend\n");
6471 return err;
6472 }
6473 pci_set_master(pdev);
6474
6475 pci_enable_wake(pdev, PCI_D3hot, 0);
6476 pci_enable_wake(pdev, PCI_D3cold, 0);
6477
047e0030 6478 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6479 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6480 return -ENOMEM;
9d5c8243
AK		 6481 }
6482
9d5c8243 6483 igb_reset(adapter);
a8564f03
AD		 6484
6485 /* let the f/w know that the h/w is now under the control of the
6486 * driver. */
6487 igb_get_hw_control(adapter);
6488
9d5c8243
AK		 6489 wr32(E1000_WUS, ~0);
6490
a88f10ec
AD		 6491 if (netif_running(netdev)) {
6492 err = igb_open(netdev);
6493 if (err)
6494 return err;
6495 }
9d5c8243
AK		 6496
6497 netif_device_attach(netdev);
6498
9d5c8243
AK		 6499 return 0;
6500}
6501#endif
6502
6503static void igb_shutdown(struct pci_dev *pdev)
6504{
3fe7c4c9
RW		 6505 bool wake;
6506
6507 __igb_shutdown(pdev, &wake);
6508
6509 if (system_state == SYSTEM_POWER_OFF) {
6510 pci_wake_from_d3(pdev, wake);
6511 pci_set_power_state(pdev, PCI_D3hot);
6512 }
9d5c8243
AK		 6513}
6514
6515#ifdef CONFIG_NET_POLL_CONTROLLER
6516/*
6517 * Polling 'interrupt' - used by things like netconsole to send skbs
6518 * without having to re-enable interrupts. It's not called while
6519 * the interrupt routine is executing.
6520 */
6521static void igb_netpoll(struct net_device *netdev)
6522{
6523 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6524 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6525 int i;
9d5c8243 6526
eebbbdba 6527 if (!adapter->msix_entries) {
047e0030 6528 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 6529 igb_irq_disable(adapter);
047e0030 6530 napi_schedule(&q_vector->napi);
eebbbdba
AD		 6531 return;
6532 }
9d5c8243 6533
047e0030
AD		 6534 for (i = 0; i < adapter->num_q_vectors; i++) {
6535 struct igb_q_vector *q_vector = adapter->q_vector[i];
6536 wr32(E1000_EIMC, q_vector->eims_value);
6537 napi_schedule(&q_vector->napi);
eebbbdba 6538 }
9d5c8243
AK		 6539}
6540#endif /* CONFIG_NET_POLL_CONTROLLER */
6541
6542/**
6543 * igb_io_error_detected - called when PCI error is detected
6544 * @pdev: Pointer to PCI device
6545 * @state: The current pci connection state
6546 *
6547 * This function is called after a PCI bus error affecting
6548 * this device has been detected.
6549 */
6550static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6551 pci_channel_state_t state)
6552{
6553 struct net_device *netdev = pci_get_drvdata(pdev);
6554 struct igb_adapter *adapter = netdev_priv(netdev);
6555
6556 netif_device_detach(netdev);
6557
59ed6eec
AD		 6558 if (state == pci_channel_io_perm_failure)
6559 return PCI_ERS_RESULT_DISCONNECT;
6560
9d5c8243
AK		 6561 if (netif_running(netdev))
6562 igb_down(adapter);
6563 pci_disable_device(pdev);
6564
6565 /* Request a slot slot reset. */
6566 return PCI_ERS_RESULT_NEED_RESET;
6567}
6568
6569/**
6570 * igb_io_slot_reset - called after the pci bus has been reset.
6571 * @pdev: Pointer to PCI device
6572 *
6573 * Restart the card from scratch, as if from a cold-boot. Implementation
6574 * resembles the first-half of the igb_resume routine.
6575 */
6576static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6577{
6578 struct net_device *netdev = pci_get_drvdata(pdev);
6579 struct igb_adapter *adapter = netdev_priv(netdev);
6580 struct e1000_hw *hw = &adapter->hw;
40a914fa 6581 pci_ers_result_t result;
42bfd33a 6582 int err;
9d5c8243 6583
aed5dec3 6584 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6585 dev_err(&pdev->dev,
6586 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6587 result = PCI_ERS_RESULT_DISCONNECT;
6588 } else {
6589 pci_set_master(pdev);
6590 pci_restore_state(pdev);
b94f2d77 6591 pci_save_state(pdev);
9d5c8243 6592
40a914fa
AD		 6593 pci_enable_wake(pdev, PCI_D3hot, 0);
6594 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6595
40a914fa
AD		 6596 igb_reset(adapter);
6597 wr32(E1000_WUS, ~0);
6598 result = PCI_ERS_RESULT_RECOVERED;
6599 }
9d5c8243 6600
ea943d41
JK		 6601 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6602 if (err) {
6603 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6604 "failed 0x%0x\n", err);
6605 /* non-fatal, continue */
6606 }
40a914fa
AD		 6607
6608 return result;
9d5c8243
AK		 6609}
6610
6611/**
6612 * igb_io_resume - called when traffic can start flowing again.
6613 * @pdev: Pointer to PCI device
6614 *
6615 * This callback is called when the error recovery driver tells us that
6616 * its OK to resume normal operation. Implementation resembles the
6617 * second-half of the igb_resume routine.
6618 */
6619static void igb_io_resume(struct pci_dev *pdev)
6620{
6621 struct net_device *netdev = pci_get_drvdata(pdev);
6622 struct igb_adapter *adapter = netdev_priv(netdev);
6623
9d5c8243
AK		 6624 if (netif_running(netdev)) {
6625 if (igb_up(adapter)) {
6626 dev_err(&pdev->dev, "igb_up failed after reset\n");
6627 return;
6628 }
6629 }
6630
6631 netif_device_attach(netdev);
6632
6633 /* let the f/w know that the h/w is now under the control of the
6634 * driver. */
6635 igb_get_hw_control(adapter);
9d5c8243
AK		 6636}
6637
26ad9178
AD		 6638static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6639 u8 qsel)
6640{
6641 u32 rar_low, rar_high;
6642 struct e1000_hw *hw = &adapter->hw;
6643
6644 /* HW expects these in little endian so we reverse the byte order
6645 * from network order (big endian) to little endian
6646 */
6647 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6648 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6649 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6650
6651 /* Indicate to hardware the Address is Valid. */
6652 rar_high |= E1000_RAH_AV;
6653
6654 if (hw->mac.type == e1000_82575)
6655 rar_high |= E1000_RAH_POOL_1 * qsel;
6656 else
6657 rar_high |= E1000_RAH_POOL_1 << qsel;
6658
6659 wr32(E1000_RAL(index), rar_low);
6660 wrfl();
6661 wr32(E1000_RAH(index), rar_high);
6662 wrfl();
6663}
6664
4ae196df
AD		 6665static int igb_set_vf_mac(struct igb_adapter *adapter,
6666 int vf, unsigned char *mac_addr)
6667{
6668 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6669 /* VF MAC addresses start at end of receive addresses and moves
6670 * torwards the first, as a result a collision should not be possible */
6671 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6672
37680117 6673 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6674
26ad9178 6675 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6676
6677 return 0;
6678}
6679
8151d294
WM		 6680static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6681{
6682 struct igb_adapter *adapter = netdev_priv(netdev);
6683 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6684 return -EINVAL;
6685 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6686 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6687 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6688 " change effective.");
6689 if (test_bit(__IGB_DOWN, &adapter->state)) {
6690 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6691 " but the PF device is not up.\n");
6692 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6693 " attempting to use the VF device.\n");
6694 }
6695 return igb_set_vf_mac(adapter, vf, mac);
6696}
6697
17dc566c
LL		 6698static int igb_link_mbps(int internal_link_speed)
6699{
6700 switch (internal_link_speed) {
6701 case SPEED_100:
6702 return 100;
6703 case SPEED_1000:
6704 return 1000;
6705 default:
6706 return 0;
6707 }
6708}
6709
6710static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6711 int link_speed)
6712{
6713 int rf_dec, rf_int;
6714 u32 bcnrc_val;
6715
6716 if (tx_rate != 0) {
6717 /* Calculate the rate factor values to set */
6718 rf_int = link_speed / tx_rate;
6719 rf_dec = (link_speed - (rf_int * tx_rate));
6720 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6721
6722 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6723 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6724 E1000_RTTBCNRC_RF_INT_MASK);
6725 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6726 } else {
6727 bcnrc_val = 0;
6728 }
6729
6730 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
6731 wr32(E1000_RTTBCNRC, bcnrc_val);
6732}
6733
6734static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
6735{
6736 int actual_link_speed, i;
6737 bool reset_rate = false;
6738
6739 /* VF TX rate limit was not set or not supported */
6740 if ((adapter->vf_rate_link_speed == 0) ||
6741 (adapter->hw.mac.type != e1000_82576))
6742 return;
6743
6744 actual_link_speed = igb_link_mbps(adapter->link_speed);
6745 if (actual_link_speed != adapter->vf_rate_link_speed) {
6746 reset_rate = true;
6747 adapter->vf_rate_link_speed = 0;
6748 dev_info(&adapter->pdev->dev,
6749 "Link speed has been changed. VF Transmit "
6750 "rate is disabled\n");
6751 }
6752
6753 for (i = 0; i < adapter->vfs_allocated_count; i++) {
6754 if (reset_rate)
6755 adapter->vf_data[i].tx_rate = 0;
6756
6757 igb_set_vf_rate_limit(&adapter->hw, i,
6758 adapter->vf_data[i].tx_rate,
6759 actual_link_speed);
6760 }
6761}
6762
8151d294
WM		 6763static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6764{
17dc566c
LL		 6765 struct igb_adapter *adapter = netdev_priv(netdev);
6766 struct e1000_hw *hw = &adapter->hw;
6767 int actual_link_speed;
6768
6769 if (hw->mac.type != e1000_82576)
6770 return -EOPNOTSUPP;
6771
6772 actual_link_speed = igb_link_mbps(adapter->link_speed);
6773 if ((vf >= adapter->vfs_allocated_count) ||
6774 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
6775 (tx_rate < 0) || (tx_rate > actual_link_speed))
6776 return -EINVAL;
6777
6778 adapter->vf_rate_link_speed = actual_link_speed;
6779 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
6780 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
6781
6782 return 0;
8151d294
WM		 6783}
6784
6785static int igb_ndo_get_vf_config(struct net_device *netdev,
6786 int vf, struct ifla_vf_info *ivi)
6787{
6788 struct igb_adapter *adapter = netdev_priv(netdev);
6789 if (vf >= adapter->vfs_allocated_count)
6790 return -EINVAL;
6791 ivi->vf = vf;
6792 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 6793 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 6794 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6795 ivi->qos = adapter->vf_data[vf].pf_qos;
6796 return 0;
6797}
6798
4ae196df
AD		 6799static void igb_vmm_control(struct igb_adapter *adapter)
6800{
6801 struct e1000_hw *hw = &adapter->hw;
10d8e907 6802 u32 reg;
4ae196df 6803
52a1dd4d
AD		 6804 switch (hw->mac.type) {
6805 case e1000_82575:
6806 default:
6807 /* replication is not supported for 82575 */
4ae196df 6808 return;
52a1dd4d
AD		 6809 case e1000_82576:
6810 /* notify HW that the MAC is adding vlan tags */
6811 reg = rd32(E1000_DTXCTL);
6812 reg |= E1000_DTXCTL_VLAN_ADDED;
6813 wr32(E1000_DTXCTL, reg);
6814 case e1000_82580:
6815 /* enable replication vlan tag stripping */
6816 reg = rd32(E1000_RPLOLR);
6817 reg |= E1000_RPLOLR_STRVLAN;
6818 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 6819 case e1000_i350:
6820 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 6821 break;
6822 }
10d8e907 6823
d4960307
AD		 6824 if (adapter->vfs_allocated_count) {
6825 igb_vmdq_set_loopback_pf(hw, true);
6826 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 6827 igb_vmdq_set_anti_spoofing_pf(hw, true,
6828 adapter->vfs_allocated_count);
d4960307
AD		 6829 } else {
6830 igb_vmdq_set_loopback_pf(hw, false);
6831 igb_vmdq_set_replication_pf(hw, false);
6832 }
4ae196df
AD		 6833}
6834
9d5c8243 6835/* igb_main.c */
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