]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/net/ethernet/intel/igb/igb_main.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: remove duplicate code for fallback interrupt initialization
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
9d5c8243
AK		 60#include "igb.h"
61
200e5fd5
CW		 62#define MAJ 4
63#define MIN 0
3db73804 64#define BUILD 17
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 72
9d5c8243
AK		 73static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75};
76
a3aa1884 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110};
111
112MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114void igb_reset(struct igb_adapter *);
115static int igb_setup_all_tx_resources(struct igb_adapter *);
116static int igb_setup_all_rx_resources(struct igb_adapter *);
117static void igb_free_all_tx_resources(struct igb_adapter *);
118static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 119static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 120static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 121static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 122static int igb_sw_init(struct igb_adapter *);
123static int igb_open(struct net_device *);
124static int igb_close(struct net_device *);
53c7d064 125static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 126static void igb_configure_tx(struct igb_adapter *);
127static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 128static void igb_clean_all_tx_rings(struct igb_adapter *);
129static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 130static void igb_clean_tx_ring(struct igb_ring *);
131static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 132static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 133static void igb_update_phy_info(unsigned long);
134static void igb_watchdog(unsigned long);
135static void igb_watchdog_task(struct work_struct *);
cd392f5c 136static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 137static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
138 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 139static int igb_change_mtu(struct net_device *, int);
140static int igb_set_mac(struct net_device *, void *);
68d480c4 141static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 142static irqreturn_t igb_intr(int irq, void *);
143static irqreturn_t igb_intr_msi(int irq, void *);
144static irqreturn_t igb_msix_other(int irq, void *);
047e0030 145static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 146#ifdef CONFIG_IGB_DCA
047e0030 147static void igb_update_dca(struct igb_q_vector *);
fe4506b6 148static void igb_setup_dca(struct igb_adapter *);
421e02f0 149#endif /* CONFIG_IGB_DCA */
661086df 150static int igb_poll(struct napi_struct *, int);
13fde97a 151static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 152static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 153static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
154static void igb_tx_timeout(struct net_device *);
155static void igb_reset_task(struct work_struct *);
c8f44aff 156static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 157static int igb_vlan_rx_add_vid(struct net_device *, u16);
158static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 159static void igb_restore_vlan(struct igb_adapter *);
26ad9178 160static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 161static void igb_ping_all_vfs(struct igb_adapter *);
162static void igb_msg_task(struct igb_adapter *);
4ae196df 163static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 164static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 165static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 166static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
167static int igb_ndo_set_vf_vlan(struct net_device *netdev,
168 int vf, u16 vlan, u8 qos);
169static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
170static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
17dc566c 172static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 173
174#ifdef CONFIG_PCI_IOV
0224d663 175static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 176static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 177#endif
9d5c8243 178
9d5c8243 179#ifdef CONFIG_PM
d9dd966d 180#ifdef CONFIG_PM_SLEEP
749ab2cd 181static int igb_suspend(struct device *);
d9dd966d 182#endif
749ab2cd
YZ		 183static int igb_resume(struct device *);
184#ifdef CONFIG_PM_RUNTIME
185static int igb_runtime_suspend(struct device *dev);
186static int igb_runtime_resume(struct device *dev);
187static int igb_runtime_idle(struct device *dev);
188#endif
189static const struct dev_pm_ops igb_pm_ops = {
190 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
191 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
192 igb_runtime_idle)
193};
9d5c8243
AK		 194#endif
195static void igb_shutdown(struct pci_dev *);
421e02f0 196#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 197static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
198static struct notifier_block dca_notifier = {
199 .notifier_call = igb_notify_dca,
200 .next = NULL,
201 .priority = 0
202};
203#endif
9d5c8243
AK		 204#ifdef CONFIG_NET_POLL_CONTROLLER
205/* for netdump / net console */
206static void igb_netpoll(struct net_device *);
207#endif
37680117 208#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 209static unsigned int max_vfs = 0;
210module_param(max_vfs, uint, 0);
211MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
212 "per physical function");
213#endif /* CONFIG_PCI_IOV */
214
9d5c8243
AK		 215static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
216 pci_channel_state_t);
217static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
218static void igb_io_resume(struct pci_dev *);
219
3646f0e5 220static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 221 .error_detected = igb_io_error_detected,
222 .slot_reset = igb_io_slot_reset,
223 .resume = igb_io_resume,
224};
225
b6e0c419 226static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 227
228static struct pci_driver igb_driver = {
229 .name = igb_driver_name,
230 .id_table = igb_pci_tbl,
231 .probe = igb_probe,
9f9a12f8 232 .remove = igb_remove,
9d5c8243 233#ifdef CONFIG_PM
749ab2cd 234 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 235#endif
236 .shutdown = igb_shutdown,
237 .err_handler = &igb_err_handler
238};
239
240MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
241MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
242MODULE_LICENSE("GPL");
243MODULE_VERSION(DRV_VERSION);
244
b3f4d599 245#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
246static int debug = -1;
247module_param(debug, int, 0);
248MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
249
c97ec42a
TI		 250struct igb_reg_info {
251 u32 ofs;
252 char *name;
253};
254
255static const struct igb_reg_info igb_reg_info_tbl[] = {
256
257 /* General Registers */
258 {E1000_CTRL, "CTRL"},
259 {E1000_STATUS, "STATUS"},
260 {E1000_CTRL_EXT, "CTRL_EXT"},
261
262 /* Interrupt Registers */
263 {E1000_ICR, "ICR"},
264
265 /* RX Registers */
266 {E1000_RCTL, "RCTL"},
267 {E1000_RDLEN(0), "RDLEN"},
268 {E1000_RDH(0), "RDH"},
269 {E1000_RDT(0), "RDT"},
270 {E1000_RXDCTL(0), "RXDCTL"},
271 {E1000_RDBAL(0), "RDBAL"},
272 {E1000_RDBAH(0), "RDBAH"},
273
274 /* TX Registers */
275 {E1000_TCTL, "TCTL"},
276 {E1000_TDBAL(0), "TDBAL"},
277 {E1000_TDBAH(0), "TDBAH"},
278 {E1000_TDLEN(0), "TDLEN"},
279 {E1000_TDH(0), "TDH"},
280 {E1000_TDT(0), "TDT"},
281 {E1000_TXDCTL(0), "TXDCTL"},
282 {E1000_TDFH, "TDFH"},
283 {E1000_TDFT, "TDFT"},
284 {E1000_TDFHS, "TDFHS"},
285 {E1000_TDFPC, "TDFPC"},
286
287 /* List Terminator */
288 {}
289};
290
291/*
292 * igb_regdump - register printout routine
293 */
294static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
295{
296 int n = 0;
297 char rname[16];
298 u32 regs[8];
299
300 switch (reginfo->ofs) {
301 case E1000_RDLEN(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDLEN(n));
304 break;
305 case E1000_RDH(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDH(n));
308 break;
309 case E1000_RDT(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDT(n));
312 break;
313 case E1000_RXDCTL(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RXDCTL(n));
316 break;
317 case E1000_RDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDBAL(n));
320 break;
321 case E1000_RDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAH(n));
324 break;
325 case E1000_TDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_TDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDBAH(n));
332 break;
333 case E1000_TDLEN(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDLEN(n));
336 break;
337 case E1000_TDH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDH(n));
340 break;
341 case E1000_TDT(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDT(n));
344 break;
345 case E1000_TXDCTL(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TXDCTL(n));
348 break;
349 default:
876d2d6f 350 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 351 return;
352 }
353
354 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 355 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
356 regs[2], regs[3]);
c97ec42a
TI		 357}
358
359/*
360 * igb_dump - Print registers, tx-rings and rx-rings
361 */
362static void igb_dump(struct igb_adapter *adapter)
363{
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
c97ec42a
TI		 367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
6ad4edfc 373 u16 i, n;
c97ec42a
TI		 374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 381 pr_info("Device Name state trans_start "
382 "last_rx\n");
383 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
384 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 385 }
386
387 /* Print Registers */
388 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 389 pr_info(" Register Name Value\n");
c97ec42a
TI		 390 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
391 reginfo->name; reginfo++) {
392 igb_regdump(hw, reginfo);
393 }
394
395 /* Print TX Ring Summary */
396 if (!netdev || !netif_running(netdev))
397 goto exit;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 400 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 401 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 402 struct igb_tx_buffer *buffer_info;
c97ec42a 403 tx_ring = adapter->tx_ring[n];
06034649 404 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 405 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
406 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 407 (u64)dma_unmap_addr(buffer_info, dma),
408 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 409 buffer_info->next_to_watch,
410 (u64)buffer_info->time_stamp);
c97ec42a
TI		 411 }
412
413 /* Print TX Rings */
414 if (!netif_msg_tx_done(adapter))
415 goto rx_ring_summary;
416
417 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
418
419 /* Transmit Descriptor Formats
420 *
421 * Advanced Transmit Descriptor
422 * +--------------------------------------------------------------+
423 * 0 | Buffer Address [63:0] |
424 * +--------------------------------------------------------------+
425 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
426 * +--------------------------------------------------------------+
427 * 63 46 45 40 39 38 36 35 32 31 24 15 0
428 */
429
430 for (n = 0; n < adapter->num_tx_queues; n++) {
431 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 432 pr_info("------------------------------------\n");
433 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
434 pr_info("------------------------------------\n");
435 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
436 "[bi->dma ] leng ntw timestamp "
437 "bi->skb\n");
c97ec42a
TI		 438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 440 const char *next_desc;
06034649 441 struct igb_tx_buffer *buffer_info;
60136906 442 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 443 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 444 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
455 pr_info("T [0x%03X] %016llX %016llX %016llX"
456 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
c9f14bf3
AD		 459 (u64)dma_unmap_addr(buffer_info, dma),
460 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 461 buffer_info->next_to_watch,
462 (u64)buffer_info->time_stamp,
876d2d6f 463 buffer_info->skb, next_desc);
c97ec42a 464
b669588a 465 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 466 print_hex_dump(KERN_INFO, "",
467 DUMP_PREFIX_ADDRESS,
b669588a 468 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 469 dma_unmap_len(buffer_info, len),
470 true);
c97ec42a
TI		 471 }
472 }
473
474 /* Print RX Rings Summary */
475rx_ring_summary:
476 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 477 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 478 for (n = 0; n < adapter->num_rx_queues; n++) {
479 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 480 pr_info(" %5d %5X %5X\n",
481 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 482 }
483
484 /* Print RX Rings */
485 if (!netif_msg_rx_status(adapter))
486 goto exit;
487
488 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
489
490 /* Advanced Receive Descriptor (Read) Format
491 * 63 1 0
492 * +-----------------------------------------------------+
493 * 0 | Packet Buffer Address [63:1] |A0/NSE|
494 * +----------------------------------------------+------+
495 * 8 | Header Buffer Address [63:1] | DD |
496 * +-----------------------------------------------------+
497 *
498 *
499 * Advanced Receive Descriptor (Write-Back) Format
500 *
501 * 63 48 47 32 31 30 21 20 17 16 4 3 0
502 * +------------------------------------------------------+
503 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
504 * | Checksum Ident | | | | Type | Type |
505 * +------------------------------------------------------+
506 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
507 * +------------------------------------------------------+
508 * 63 48 47 32 31 20 19 0
509 */
510
511 for (n = 0; n < adapter->num_rx_queues; n++) {
512 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 513 pr_info("------------------------------------\n");
514 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
515 pr_info("------------------------------------\n");
516 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
517 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
519 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 520
521 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 522 const char *next_desc;
06034649
AD		 523 struct igb_rx_buffer *buffer_info;
524 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 525 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 526 u0 = (struct my_u0 *)rx_desc;
527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 528
529 if (i == rx_ring->next_to_use)
530 next_desc = " NTU";
531 else if (i == rx_ring->next_to_clean)
532 next_desc = " NTC";
533 else
534 next_desc = "";
535
c97ec42a
TI		 536 if (staterr & E1000_RXD_STAT_DD) {
537 /* Descriptor Done */
1a1c225b
AD		 538 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
539 "RWB", i,
c97ec42a
TI		 540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
1a1c225b 542 next_desc);
c97ec42a 543 } else {
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
545 "R ", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
548 (u64)buffer_info->dma,
1a1c225b 549 next_desc);
c97ec42a 550
b669588a 551 if (netif_msg_pktdata(adapter) &&
1a1c225b 552 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 553 print_hex_dump(KERN_INFO, "",
554 DUMP_PREFIX_ADDRESS,
555 16, 1,
b669588a
ET		 556 page_address(buffer_info->page) +
557 buffer_info->page_offset,
de78d1f9 558 IGB_RX_BUFSZ, true);
c97ec42a
TI		 559 }
560 }
c97ec42a
TI		 561 }
562 }
563
564exit:
565 return;
566}
567
9d5c8243 568/**
c041076a 569 * igb_get_hw_dev - return device
9d5c8243
AK		 570 * used by hardware layer to print debugging information
571 **/
c041076a 572struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 573{
574 struct igb_adapter *adapter = hw->back;
c041076a 575 return adapter->netdev;
9d5c8243 576}
38c845c7 577
9d5c8243
AK		 578/**
579 * igb_init_module - Driver Registration Routine
580 *
581 * igb_init_module is the first routine called when the driver is
582 * loaded. All it does is register with the PCI subsystem.
583 **/
584static int __init igb_init_module(void)
585{
586 int ret;
876d2d6f 587 pr_info("%s - version %s\n",
9d5c8243
AK		 588 igb_driver_string, igb_driver_version);
589
876d2d6f 590 pr_info("%s\n", igb_copyright);
9d5c8243 591
421e02f0 592#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 593 dca_register_notify(&dca_notifier);
594#endif
bbd98fe4 595 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 596 return ret;
597}
598
599module_init(igb_init_module);
600
601/**
602 * igb_exit_module - Driver Exit Cleanup Routine
603 *
604 * igb_exit_module is called just before the driver is removed
605 * from memory.
606 **/
607static void __exit igb_exit_module(void)
608{
421e02f0 609#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 610 dca_unregister_notify(&dca_notifier);
611#endif
9d5c8243
AK		 612 pci_unregister_driver(&igb_driver);
613}
614
615module_exit(igb_exit_module);
616
26bc19ec
AD		 617#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
618/**
619 * igb_cache_ring_register - Descriptor ring to register mapping
620 * @adapter: board private structure to initialize
621 *
622 * Once we know the feature-set enabled for the device, we'll cache
623 * the register offset the descriptor ring is assigned to.
624 **/
625static void igb_cache_ring_register(struct igb_adapter *adapter)
626{
ee1b9f06 627 int i = 0, j = 0;
047e0030 628 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 629
630 switch (adapter->hw.mac.type) {
631 case e1000_82576:
632 /* The queues are allocated for virtualization such that VF 0
633 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
634 * In order to avoid collision we start at the first free queue
635 * and continue consuming queues in the same sequence
636 */
ee1b9f06 637 if (adapter->vfs_allocated_count) {
a99955fc 638 for (; i < adapter->rss_queues; i++)
3025a446
AD		 639 adapter->rx_ring[i]->reg_idx = rbase_offset +
640 Q_IDX_82576(i);
ee1b9f06 641 }
26bc19ec 642 case e1000_82575:
55cac248 643 case e1000_82580:
d2ba2ed8 644 case e1000_i350:
f96a8a0b
CW		 645 case e1000_i210:
646 case e1000_i211:
26bc19ec 647 default:
ee1b9f06 648 for (; i < adapter->num_rx_queues; i++)
3025a446 649 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 650 for (; j < adapter->num_tx_queues; j++)
3025a446 651 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 652 break;
653 }
654}
655
4be000c8
AD		 656/**
657 * igb_write_ivar - configure ivar for given MSI-X vector
658 * @hw: pointer to the HW structure
659 * @msix_vector: vector number we are allocating to a given ring
660 * @index: row index of IVAR register to write within IVAR table
661 * @offset: column offset of in IVAR, should be multiple of 8
662 *
663 * This function is intended to handle the writing of the IVAR register
664 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
665 * each containing an cause allocation for an Rx and Tx ring, and a
666 * variable number of rows depending on the number of queues supported.
667 **/
668static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
669 int index, int offset)
670{
671 u32 ivar = array_rd32(E1000_IVAR0, index);
672
673 /* clear any bits that are currently set */
674 ivar &= ~((u32)0xFF << offset);
675
676 /* write vector and valid bit */
677 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
678
679 array_wr32(E1000_IVAR0, index, ivar);
680}
681
9d5c8243 682#define IGB_N0_QUEUE -1
047e0030 683static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 684{
047e0030 685 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 686 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 687 int rx_queue = IGB_N0_QUEUE;
688 int tx_queue = IGB_N0_QUEUE;
4be000c8 689 u32 msixbm = 0;
047e0030 690
0ba82994
AD		 691 if (q_vector->rx.ring)
692 rx_queue = q_vector->rx.ring->reg_idx;
693 if (q_vector->tx.ring)
694 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 695
696 switch (hw->mac.type) {
697 case e1000_82575:
9d5c8243
AK		 698 /* The 82575 assigns vectors using a bitmask, which matches the
699 bitmask for the EICR/EIMS/EIMC registers. To assign one
700 or more queues to a vector, we write the appropriate bits
701 into the MSIXBM register for that vector. */
047e0030 702 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 703 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 704 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 705 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 706 if (!adapter->msix_entries && msix_vector == 0)
707 msixbm |= E1000_EIMS_OTHER;
9d5c8243 708 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 709 q_vector->eims_value = msixbm;
2d064c06
AD		 710 break;
711 case e1000_82576:
4be000c8
AD		 712 /*
713 * 82576 uses a table that essentially consists of 2 columns
714 * with 8 rows. The ordering is column-major so we use the
715 * lower 3 bits as the row index, and the 4th bit as the
716 * column offset.
717 */
718 if (rx_queue > IGB_N0_QUEUE)
719 igb_write_ivar(hw, msix_vector,
720 rx_queue & 0x7,
721 (rx_queue & 0x8) << 1);
722 if (tx_queue > IGB_N0_QUEUE)
723 igb_write_ivar(hw, msix_vector,
724 tx_queue & 0x7,
725 ((tx_queue & 0x8) << 1) + 8);
047e0030 726 q_vector->eims_value = 1 << msix_vector;
2d064c06 727 break;
55cac248 728 case e1000_82580:
d2ba2ed8 729 case e1000_i350:
f96a8a0b
CW		 730 case e1000_i210:
731 case e1000_i211:
4be000c8
AD		 732 /*
733 * On 82580 and newer adapters the scheme is similar to 82576
734 * however instead of ordering column-major we have things
735 * ordered row-major. So we traverse the table by using
736 * bit 0 as the column offset, and the remaining bits as the
737 * row index.
738 */
739 if (rx_queue > IGB_N0_QUEUE)
740 igb_write_ivar(hw, msix_vector,
741 rx_queue >> 1,
742 (rx_queue & 0x1) << 4);
743 if (tx_queue > IGB_N0_QUEUE)
744 igb_write_ivar(hw, msix_vector,
745 tx_queue >> 1,
746 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 747 q_vector->eims_value = 1 << msix_vector;
748 break;
2d064c06
AD		 749 default:
750 BUG();
751 break;
752 }
26b39276
AD		 753
754 /* add q_vector eims value to global eims_enable_mask */
755 adapter->eims_enable_mask |= q_vector->eims_value;
756
757 /* configure q_vector to set itr on first interrupt */
758 q_vector->set_itr = 1;
9d5c8243
AK		 759}
760
761/**
762 * igb_configure_msix - Configure MSI-X hardware
763 *
764 * igb_configure_msix sets up the hardware to properly
765 * generate MSI-X interrupts.
766 **/
767static void igb_configure_msix(struct igb_adapter *adapter)
768{
769 u32 tmp;
770 int i, vector = 0;
771 struct e1000_hw *hw = &adapter->hw;
772
773 adapter->eims_enable_mask = 0;
9d5c8243
AK		 774
775 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 776 switch (hw->mac.type) {
777 case e1000_82575:
9d5c8243
AK		 778 tmp = rd32(E1000_CTRL_EXT);
779 /* enable MSI-X PBA support*/
780 tmp |= E1000_CTRL_EXT_PBA_CLR;
781
782 /* Auto-Mask interrupts upon ICR read. */
783 tmp |= E1000_CTRL_EXT_EIAME;
784 tmp |= E1000_CTRL_EXT_IRCA;
785
786 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 787
788 /* enable msix_other interrupt */
789 array_wr32(E1000_MSIXBM(0), vector++,
790 E1000_EIMS_OTHER);
844290e5 791 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 792
2d064c06
AD		 793 break;
794
795 case e1000_82576:
55cac248 796 case e1000_82580:
d2ba2ed8 797 case e1000_i350:
f96a8a0b
CW		 798 case e1000_i210:
799 case e1000_i211:
047e0030
AD		 800 /* Turn on MSI-X capability first, or our settings
801 * won't stick. And it will take days to debug. */
802 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
803 E1000_GPIE_PBA | E1000_GPIE_EIAME |
804 E1000_GPIE_NSICR);
805
806 /* enable msix_other interrupt */
807 adapter->eims_other = 1 << vector;
2d064c06 808 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 809
047e0030 810 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 811 break;
812 default:
813 /* do nothing, since nothing else supports MSI-X */
814 break;
815 } /* switch (hw->mac.type) */
047e0030
AD		 816
817 adapter->eims_enable_mask |= adapter->eims_other;
818
26b39276
AD		 819 for (i = 0; i < adapter->num_q_vectors; i++)
820 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 821
9d5c8243
AK		 822 wrfl();
823}
824
825/**
826 * igb_request_msix - Initialize MSI-X interrupts
827 *
828 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
829 * kernel.
830 **/
831static int igb_request_msix(struct igb_adapter *adapter)
832{
833 struct net_device *netdev = adapter->netdev;
047e0030 834 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 835 int i, err = 0, vector = 0;
836
047e0030 837 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 838 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 839 if (err)
840 goto out;
841 vector++;
842
843 for (i = 0; i < adapter->num_q_vectors; i++) {
844 struct igb_q_vector *q_vector = adapter->q_vector[i];
845
846 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
847
0ba82994 848 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 849 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 850 q_vector->rx.ring->queue_index);
851 else if (q_vector->tx.ring)
047e0030 852 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 853 q_vector->tx.ring->queue_index);
854 else if (q_vector->rx.ring)
047e0030 855 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 856 q_vector->rx.ring->queue_index);
9d5c8243 857 else
047e0030
AD		 858 sprintf(q_vector->name, "%s-unused", netdev->name);
859
9d5c8243 860 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 861 igb_msix_ring, 0, q_vector->name,
047e0030 862 q_vector);
9d5c8243
AK		 863 if (err)
864 goto out;
9d5c8243
AK		 865 vector++;
866 }
867
9d5c8243
AK		 868 igb_configure_msix(adapter);
869 return 0;
870out:
871 return err;
872}
873
874static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
875{
876 if (adapter->msix_entries) {
877 pci_disable_msix(adapter->pdev);
878 kfree(adapter->msix_entries);
879 adapter->msix_entries = NULL;
047e0030 880 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 881 pci_disable_msi(adapter->pdev);
047e0030 882 }
9d5c8243
AK		 883}
884
5536d210
AD		 885/**
886 * igb_free_q_vector - Free memory allocated for specific interrupt vector
887 * @adapter: board private structure to initialize
888 * @v_idx: Index of vector to be freed
889 *
890 * This function frees the memory allocated to the q_vector. In addition if
891 * NAPI is enabled it will delete any references to the NAPI struct prior
892 * to freeing the q_vector.
893 **/
894static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
895{
896 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
897
898 if (q_vector->tx.ring)
899 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
900
901 if (q_vector->rx.ring)
902 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
903
904 adapter->q_vector[v_idx] = NULL;
905 netif_napi_del(&q_vector->napi);
906
907 /*
908 * ixgbe_get_stats64() might access the rings on this vector,
909 * we must wait a grace period before freeing it.
910 */
911 kfree_rcu(q_vector, rcu);
912}
913
047e0030
AD		 914/**
915 * igb_free_q_vectors - Free memory allocated for interrupt vectors
916 * @adapter: board private structure to initialize
917 *
918 * This function frees the memory allocated to the q_vectors. In addition if
919 * NAPI is enabled it will delete any references to the NAPI struct prior
920 * to freeing the q_vector.
921 **/
922static void igb_free_q_vectors(struct igb_adapter *adapter)
923{
5536d210
AD		 924 int v_idx = adapter->num_q_vectors;
925
926 adapter->num_tx_queues = 0;
927 adapter->num_rx_queues = 0;
047e0030 928 adapter->num_q_vectors = 0;
5536d210
AD		 929
930 while (v_idx--)
931 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 932}
933
934/**
935 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
936 *
937 * This function resets the device so that it has 0 rx queues, tx queues, and
938 * MSI-X interrupts allocated.
939 */
940static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
941{
047e0030
AD		 942 igb_free_q_vectors(adapter);
943 igb_reset_interrupt_capability(adapter);
944}
9d5c8243
AK		 945
946/**
947 * igb_set_interrupt_capability - set MSI or MSI-X if supported
948 *
949 * Attempt to configure interrupts using the best available
950 * capabilities of the hardware and kernel.
951 **/
53c7d064 952static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 953{
954 int err;
955 int numvecs, i;
956
53c7d064
SA		 957 if (!msix)
958 goto msi_only;
959
83b7180d 960 /* Number of supported queues. */
a99955fc 961 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 962 if (adapter->vfs_allocated_count)
963 adapter->num_tx_queues = 1;
964 else
965 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 966
047e0030
AD		 967 /* start with one vector for every rx queue */
968 numvecs = adapter->num_rx_queues;
969
3ad2f3fb 970 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 971 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
972 numvecs += adapter->num_tx_queues;
047e0030
AD		 973
974 /* store the number of vectors reserved for queues */
975 adapter->num_q_vectors = numvecs;
976
977 /* add 1 vector for link status interrupts */
978 numvecs++;
9d5c8243
AK		 979 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
980 GFP_KERNEL);
f96a8a0b 981
9d5c8243
AK		 982 if (!adapter->msix_entries)
983 goto msi_only;
984
985 for (i = 0; i < numvecs; i++)
986 adapter->msix_entries[i].entry = i;
987
988 err = pci_enable_msix(adapter->pdev,
989 adapter->msix_entries,
990 numvecs);
991 if (err == 0)
0c2cc02e 992 return;
9d5c8243
AK		 993
994 igb_reset_interrupt_capability(adapter);
995
996 /* If we can't do MSI-X, try MSI */
997msi_only:
2a3abf6d
AD		 998#ifdef CONFIG_PCI_IOV
999 /* disable SR-IOV for non MSI-X configurations */
1000 if (adapter->vf_data) {
1001 struct e1000_hw *hw = &adapter->hw;
1002 /* disable iov and allow time for transactions to clear */
1003 pci_disable_sriov(adapter->pdev);
1004 msleep(500);
1005
1006 kfree(adapter->vf_data);
1007 adapter->vf_data = NULL;
1008 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1009 wrfl();
2a3abf6d
AD		 1010 msleep(100);
1011 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1012 }
1013#endif
4fc82adf 1014 adapter->vfs_allocated_count = 0;
a99955fc 1015 adapter->rss_queues = 1;
4fc82adf 1016 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1017 adapter->num_rx_queues = 1;
661086df 1018 adapter->num_tx_queues = 1;
047e0030 1019 adapter->num_q_vectors = 1;
9d5c8243 1020 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1021 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1022}
1023
5536d210
AD		 1024static void igb_add_ring(struct igb_ring *ring,
1025 struct igb_ring_container *head)
1026{
1027 head->ring = ring;
1028 head->count++;
1029}
1030
047e0030 1031/**
5536d210 1032 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1033 * @adapter: board private structure to initialize
5536d210
AD		 1034 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1035 * @v_idx: index of vector in adapter struct
1036 * @txr_count: total number of Tx rings to allocate
1037 * @txr_idx: index of first Tx ring to allocate
1038 * @rxr_count: total number of Rx rings to allocate
1039 * @rxr_idx: index of first Rx ring to allocate
047e0030 1040 *
5536d210 1041 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1042 **/
5536d210
AD		 1043static int igb_alloc_q_vector(struct igb_adapter *adapter,
1044 int v_count, int v_idx,
1045 int txr_count, int txr_idx,
1046 int rxr_count, int rxr_idx)
047e0030
AD		 1047{
1048 struct igb_q_vector *q_vector;
5536d210
AD		 1049 struct igb_ring *ring;
1050 int ring_count, size;
047e0030 1051
5536d210
AD		 1052 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1053 if (txr_count > 1 || rxr_count > 1)
1054 return -ENOMEM;
1055
1056 ring_count = txr_count + rxr_count;
1057 size = sizeof(struct igb_q_vector) +
1058 (sizeof(struct igb_ring) * ring_count);
1059
1060 /* allocate q_vector and rings */
1061 q_vector = kzalloc(size, GFP_KERNEL);
1062 if (!q_vector)
1063 return -ENOMEM;
1064
1065 /* initialize NAPI */
1066 netif_napi_add(adapter->netdev, &q_vector->napi,
1067 igb_poll, 64);
1068
1069 /* tie q_vector and adapter together */
1070 adapter->q_vector[v_idx] = q_vector;
1071 q_vector->adapter = adapter;
1072
1073 /* initialize work limits */
1074 q_vector->tx.work_limit = adapter->tx_work_limit;
1075
1076 /* initialize ITR configuration */
1077 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1078 q_vector->itr_val = IGB_START_ITR;
1079
1080 /* initialize pointer to rings */
1081 ring = q_vector->ring;
1082
1083 if (txr_count) {
1084 /* assign generic ring traits */
1085 ring->dev = &adapter->pdev->dev;
1086 ring->netdev = adapter->netdev;
1087
1088 /* configure backlink on ring */
1089 ring->q_vector = q_vector;
1090
1091 /* update q_vector Tx values */
1092 igb_add_ring(ring, &q_vector->tx);
1093
1094 /* For 82575, context index must be unique per ring. */
1095 if (adapter->hw.mac.type == e1000_82575)
1096 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1097
1098 /* apply Tx specific ring traits */
1099 ring->count = adapter->tx_ring_count;
1100 ring->queue_index = txr_idx;
1101
1102 /* assign ring to adapter */
1103 adapter->tx_ring[txr_idx] = ring;
1104
1105 /* push pointer to next ring */
1106 ring++;
047e0030 1107 }
81c2fc22 1108
5536d210
AD		 1109 if (rxr_count) {
1110 /* assign generic ring traits */
1111 ring->dev = &adapter->pdev->dev;
1112 ring->netdev = adapter->netdev;
047e0030 1113
5536d210
AD		 1114 /* configure backlink on ring */
1115 ring->q_vector = q_vector;
047e0030 1116
5536d210
AD		 1117 /* update q_vector Rx values */
1118 igb_add_ring(ring, &q_vector->rx);
047e0030 1119
5536d210
AD		 1120 /* set flag indicating ring supports SCTP checksum offload */
1121 if (adapter->hw.mac.type >= e1000_82576)
1122 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1123
5536d210
AD		 1124 /*
1125 * On i350, i210, and i211, loopback VLAN packets
1126 * have the tag byte-swapped.
1127 * */
1128 if (adapter->hw.mac.type >= e1000_i350)
1129 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1130
5536d210
AD		 1131 /* apply Rx specific ring traits */
1132 ring->count = adapter->rx_ring_count;
1133 ring->queue_index = rxr_idx;
1134
1135 /* assign ring to adapter */
1136 adapter->rx_ring[rxr_idx] = ring;
1137 }
1138
1139 return 0;
047e0030
AD		 1140}
1141
5536d210 1142
047e0030 1143/**
5536d210
AD		 1144 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1145 * @adapter: board private structure to initialize
047e0030 1146 *
5536d210
AD		 1147 * We allocate one q_vector per queue interrupt. If allocation fails we
1148 * return -ENOMEM.
047e0030 1149 **/
5536d210 1150static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1151{
5536d210
AD		 1152 int q_vectors = adapter->num_q_vectors;
1153 int rxr_remaining = adapter->num_rx_queues;
1154 int txr_remaining = adapter->num_tx_queues;
1155 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1156 int err;
047e0030 1157
5536d210
AD		 1158 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1159 for (; rxr_remaining; v_idx++) {
1160 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1161 0, 0, 1, rxr_idx);
047e0030 1162
5536d210
AD		 1163 if (err)
1164 goto err_out;
1165
1166 /* update counts and index */
1167 rxr_remaining--;
1168 rxr_idx++;
047e0030 1169 }
047e0030 1170 }
5536d210
AD		 1171
1172 for (; v_idx < q_vectors; v_idx++) {
1173 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1174 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1175 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1176 tqpv, txr_idx, rqpv, rxr_idx);
1177
1178 if (err)
1179 goto err_out;
1180
1181 /* update counts and index */
1182 rxr_remaining -= rqpv;
1183 txr_remaining -= tqpv;
1184 rxr_idx++;
1185 txr_idx++;
1186 }
1187
047e0030 1188 return 0;
5536d210
AD		 1189
1190err_out:
1191 adapter->num_tx_queues = 0;
1192 adapter->num_rx_queues = 0;
1193 adapter->num_q_vectors = 0;
1194
1195 while (v_idx--)
1196 igb_free_q_vector(adapter, v_idx);
1197
1198 return -ENOMEM;
047e0030
AD		 1199}
1200
1201/**
1202 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1203 *
1204 * This function initializes the interrupts and allocates all of the queues.
1205 **/
53c7d064 1206static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1207{
1208 struct pci_dev *pdev = adapter->pdev;
1209 int err;
1210
53c7d064 1211 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1212
1213 err = igb_alloc_q_vectors(adapter);
1214 if (err) {
1215 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1216 goto err_alloc_q_vectors;
1217 }
1218
5536d210 1219 igb_cache_ring_register(adapter);
047e0030
AD		 1220
1221 return 0;
5536d210 1222
047e0030
AD		 1223err_alloc_q_vectors:
1224 igb_reset_interrupt_capability(adapter);
1225 return err;
1226}
1227
9d5c8243
AK		 1228/**
1229 * igb_request_irq - initialize interrupts
1230 *
1231 * Attempts to configure interrupts using the best available
1232 * capabilities of the hardware and kernel.
1233 **/
1234static int igb_request_irq(struct igb_adapter *adapter)
1235{
1236 struct net_device *netdev = adapter->netdev;
047e0030 1237 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1238 int err = 0;
1239
1240 if (adapter->msix_entries) {
1241 err = igb_request_msix(adapter);
844290e5 1242 if (!err)
9d5c8243 1243 goto request_done;
9d5c8243 1244 /* fall back to MSI */
5536d210
AD		 1245 igb_free_all_tx_resources(adapter);
1246 igb_free_all_rx_resources(adapter);
53c7d064 1247
047e0030 1248 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1249 err = igb_init_interrupt_scheme(adapter, false);
1250 if (err)
047e0030 1251 goto request_done;
53c7d064 1252
047e0030
AD		 1253 igb_setup_all_tx_resources(adapter);
1254 igb_setup_all_rx_resources(adapter);
53c7d064 1255 igb_configure(adapter);
9d5c8243 1256 }
844290e5 1257
c74d588e
AD		 1258 igb_assign_vector(adapter->q_vector[0], 0);
1259
7dfc16fa 1260 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1261 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1262 netdev->name, adapter);
9d5c8243
AK		 1263 if (!err)
1264 goto request_done;
047e0030 1265
9d5c8243
AK		 1266 /* fall back to legacy interrupts */
1267 igb_reset_interrupt_capability(adapter);
7dfc16fa 1268 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1269 }
1270
c74d588e 1271 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1272 netdev->name, adapter);
9d5c8243 1273
6cb5e577 1274 if (err)
c74d588e 1275 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1276 err);
9d5c8243
AK		 1277
1278request_done:
1279 return err;
1280}
1281
1282static void igb_free_irq(struct igb_adapter *adapter)
1283{
9d5c8243
AK		 1284 if (adapter->msix_entries) {
1285 int vector = 0, i;
1286
047e0030 1287 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1288
0d1ae7f4 1289 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1290 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1291 adapter->q_vector[i]);
047e0030
AD		 1292 } else {
1293 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1294 }
9d5c8243
AK		 1295}
1296
1297/**
1298 * igb_irq_disable - Mask off interrupt generation on the NIC
1299 * @adapter: board private structure
1300 **/
1301static void igb_irq_disable(struct igb_adapter *adapter)
1302{
1303 struct e1000_hw *hw = &adapter->hw;
1304
25568a53
AD		 1305 /*
1306 * we need to be careful when disabling interrupts. The VFs are also
1307 * mapped into these registers and so clearing the bits can cause
1308 * issues on the VF drivers so we only need to clear what we set
1309 */
9d5c8243 1310 if (adapter->msix_entries) {
2dfd1212
AD		 1311 u32 regval = rd32(E1000_EIAM);
1312 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1313 wr32(E1000_EIMC, adapter->eims_enable_mask);
1314 regval = rd32(E1000_EIAC);
1315 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1316 }
844290e5
PW		 1317
1318 wr32(E1000_IAM, 0);
9d5c8243
AK		 1319 wr32(E1000_IMC, ~0);
1320 wrfl();
81a61859
ET		 1321 if (adapter->msix_entries) {
1322 int i;
1323 for (i = 0; i < adapter->num_q_vectors; i++)
1324 synchronize_irq(adapter->msix_entries[i].vector);
1325 } else {
1326 synchronize_irq(adapter->pdev->irq);
1327 }
9d5c8243
AK		 1328}
1329
1330/**
1331 * igb_irq_enable - Enable default interrupt generation settings
1332 * @adapter: board private structure
1333 **/
1334static void igb_irq_enable(struct igb_adapter *adapter)
1335{
1336 struct e1000_hw *hw = &adapter->hw;
1337
1338 if (adapter->msix_entries) {
06218a8d 1339 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1340 u32 regval = rd32(E1000_EIAC);
1341 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1342 regval = rd32(E1000_EIAM);
1343 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1344 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1345 if (adapter->vfs_allocated_count) {
4ae196df 1346 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1347 ims |= E1000_IMS_VMMB;
1348 }
1349 wr32(E1000_IMS, ims);
844290e5 1350 } else {
55cac248
AD		 1351 wr32(E1000_IMS, IMS_ENABLE_MASK |
1352 E1000_IMS_DRSTA);
1353 wr32(E1000_IAM, IMS_ENABLE_MASK |
1354 E1000_IMS_DRSTA);
844290e5 1355 }
9d5c8243
AK		 1356}
1357
1358static void igb_update_mng_vlan(struct igb_adapter *adapter)
1359{
51466239 1360 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1361 u16 vid = adapter->hw.mng_cookie.vlan_id;
1362 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1363
1364 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1365 /* add VID to filter table */
1366 igb_vfta_set(hw, vid, true);
1367 adapter->mng_vlan_id = vid;
1368 } else {
1369 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1370 }
1371
1372 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1373 (vid != old_vid) &&
b2cb09b1 1374 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1375 /* remove VID from filter table */
1376 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1377 }
1378}
1379
1380/**
1381 * igb_release_hw_control - release control of the h/w to f/w
1382 * @adapter: address of board private structure
1383 *
1384 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1385 * For ASF and Pass Through versions of f/w this means that the
1386 * driver is no longer loaded.
1387 *
1388 **/
1389static void igb_release_hw_control(struct igb_adapter *adapter)
1390{
1391 struct e1000_hw *hw = &adapter->hw;
1392 u32 ctrl_ext;
1393
1394 /* Let firmware take over control of h/w */
1395 ctrl_ext = rd32(E1000_CTRL_EXT);
1396 wr32(E1000_CTRL_EXT,
1397 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1398}
1399
9d5c8243
AK		 1400/**
1401 * igb_get_hw_control - get control of the h/w from f/w
1402 * @adapter: address of board private structure
1403 *
1404 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1405 * For ASF and Pass Through versions of f/w this means that
1406 * the driver is loaded.
1407 *
1408 **/
1409static void igb_get_hw_control(struct igb_adapter *adapter)
1410{
1411 struct e1000_hw *hw = &adapter->hw;
1412 u32 ctrl_ext;
1413
1414 /* Let firmware know the driver has taken over */
1415 ctrl_ext = rd32(E1000_CTRL_EXT);
1416 wr32(E1000_CTRL_EXT,
1417 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1418}
1419
9d5c8243
AK		 1420/**
1421 * igb_configure - configure the hardware for RX and TX
1422 * @adapter: private board structure
1423 **/
1424static void igb_configure(struct igb_adapter *adapter)
1425{
1426 struct net_device *netdev = adapter->netdev;
1427 int i;
1428
1429 igb_get_hw_control(adapter);
ff41f8dc 1430 igb_set_rx_mode(netdev);
9d5c8243
AK		 1431
1432 igb_restore_vlan(adapter);
9d5c8243 1433
85b430b4 1434 igb_setup_tctl(adapter);
06cf2666 1435 igb_setup_mrqc(adapter);
9d5c8243 1436 igb_setup_rctl(adapter);
85b430b4
AD		 1437
1438 igb_configure_tx(adapter);
9d5c8243 1439 igb_configure_rx(adapter);
662d7205
AD		 1440
1441 igb_rx_fifo_flush_82575(&adapter->hw);
1442
c493ea45 1443 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1444 * at least 1 descriptor unused to make sure
1445 * next_to_use != next_to_clean */
1446 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1447 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1448 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1449 }
9d5c8243
AK		 1450}
1451
88a268c1
NN		 1452/**
1453 * igb_power_up_link - Power up the phy/serdes link
1454 * @adapter: address of board private structure
1455 **/
1456void igb_power_up_link(struct igb_adapter *adapter)
1457{
76886596
AA		 1458 igb_reset_phy(&adapter->hw);
1459
88a268c1
NN		 1460 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1461 igb_power_up_phy_copper(&adapter->hw);
1462 else
1463 igb_power_up_serdes_link_82575(&adapter->hw);
1464}
1465
1466/**
1467 * igb_power_down_link - Power down the phy/serdes link
1468 * @adapter: address of board private structure
1469 */
1470static void igb_power_down_link(struct igb_adapter *adapter)
1471{
1472 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1473 igb_power_down_phy_copper_82575(&adapter->hw);
1474 else
1475 igb_shutdown_serdes_link_82575(&adapter->hw);
1476}
9d5c8243
AK		 1477
1478/**
1479 * igb_up - Open the interface and prepare it to handle traffic
1480 * @adapter: board private structure
1481 **/
9d5c8243
AK		 1482int igb_up(struct igb_adapter *adapter)
1483{
1484 struct e1000_hw *hw = &adapter->hw;
1485 int i;
1486
1487 /* hardware has been reset, we need to reload some things */
1488 igb_configure(adapter);
1489
1490 clear_bit(__IGB_DOWN, &adapter->state);
1491
0d1ae7f4
AD		 1492 for (i = 0; i < adapter->num_q_vectors; i++)
1493 napi_enable(&(adapter->q_vector[i]->napi));
1494
844290e5 1495 if (adapter->msix_entries)
9d5c8243 1496 igb_configure_msix(adapter);
feeb2721
AD		 1497 else
1498 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1499
1500 /* Clear any pending interrupts. */
1501 rd32(E1000_ICR);
1502 igb_irq_enable(adapter);
1503
d4960307
AD		 1504 /* notify VFs that reset has been completed */
1505 if (adapter->vfs_allocated_count) {
1506 u32 reg_data = rd32(E1000_CTRL_EXT);
1507 reg_data |= E1000_CTRL_EXT_PFRSTD;
1508 wr32(E1000_CTRL_EXT, reg_data);
1509 }
1510
4cb9be7a
JB		 1511 netif_tx_start_all_queues(adapter->netdev);
1512
25568a53
AD		 1513 /* start the watchdog. */
1514 hw->mac.get_link_status = 1;
1515 schedule_work(&adapter->watchdog_task);
1516
9d5c8243
AK		 1517 return 0;
1518}
1519
1520void igb_down(struct igb_adapter *adapter)
1521{
9d5c8243 1522 struct net_device *netdev = adapter->netdev;
330a6d6a 1523 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1524 u32 tctl, rctl;
1525 int i;
1526
1527 /* signal that we're down so the interrupt handler does not
1528 * reschedule our watchdog timer */
1529 set_bit(__IGB_DOWN, &adapter->state);
1530
1531 /* disable receives in the hardware */
1532 rctl = rd32(E1000_RCTL);
1533 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1534 /* flush and sleep below */
1535
fd2ea0a7 1536 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1537
1538 /* disable transmits in the hardware */
1539 tctl = rd32(E1000_TCTL);
1540 tctl &= ~E1000_TCTL_EN;
1541 wr32(E1000_TCTL, tctl);
1542 /* flush both disables and wait for them to finish */
1543 wrfl();
1544 msleep(10);
1545
0d1ae7f4
AD		 1546 for (i = 0; i < adapter->num_q_vectors; i++)
1547 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1548
9d5c8243
AK		 1549 igb_irq_disable(adapter);
1550
1551 del_timer_sync(&adapter->watchdog_timer);
1552 del_timer_sync(&adapter->phy_info_timer);
1553
9d5c8243 1554 netif_carrier_off(netdev);
04fe6358
AD		 1555
1556 /* record the stats before reset*/
12dcd86b
ED		 1557 spin_lock(&adapter->stats64_lock);
1558 igb_update_stats(adapter, &adapter->stats64);
1559 spin_unlock(&adapter->stats64_lock);
04fe6358 1560
9d5c8243
AK		 1561 adapter->link_speed = 0;
1562 adapter->link_duplex = 0;
1563
3023682e
JK		 1564 if (!pci_channel_offline(adapter->pdev))
1565 igb_reset(adapter);
9d5c8243
AK		 1566 igb_clean_all_tx_rings(adapter);
1567 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1568#ifdef CONFIG_IGB_DCA
1569
1570 /* since we reset the hardware DCA settings were cleared */
1571 igb_setup_dca(adapter);
1572#endif
9d5c8243
AK		 1573}
1574
1575void igb_reinit_locked(struct igb_adapter *adapter)
1576{
1577 WARN_ON(in_interrupt());
1578 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1579 msleep(1);
1580 igb_down(adapter);
1581 igb_up(adapter);
1582 clear_bit(__IGB_RESETTING, &adapter->state);
1583}
1584
1585void igb_reset(struct igb_adapter *adapter)
1586{
090b1795 1587 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1588 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1589 struct e1000_mac_info *mac = &hw->mac;
1590 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1591 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1592
1593 /* Repartition Pba for greater than 9k mtu
1594 * To take effect CTRL.RST is required.
1595 */
fa4dfae0 1596 switch (mac->type) {
d2ba2ed8 1597 case e1000_i350:
55cac248
AD		 1598 case e1000_82580:
1599 pba = rd32(E1000_RXPBS);
1600 pba = igb_rxpbs_adjust_82580(pba);
1601 break;
fa4dfae0 1602 case e1000_82576:
d249be54
AD		 1603 pba = rd32(E1000_RXPBS);
1604 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1605 break;
1606 case e1000_82575:
f96a8a0b
CW		 1607 case e1000_i210:
1608 case e1000_i211:
fa4dfae0
AD		 1609 default:
1610 pba = E1000_PBA_34K;
1611 break;
2d064c06 1612 }
9d5c8243 1613
2d064c06
AD		 1614 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1615 (mac->type < e1000_82576)) {
9d5c8243
AK		 1616 /* adjust PBA for jumbo frames */
1617 wr32(E1000_PBA, pba);
1618
1619 /* To maintain wire speed transmits, the Tx FIFO should be
1620 * large enough to accommodate two full transmit packets,
1621 * rounded up to the next 1KB and expressed in KB. Likewise,
1622 * the Rx FIFO should be large enough to accommodate at least
1623 * one full receive packet and is similarly rounded up and
1624 * expressed in KB. */
1625 pba = rd32(E1000_PBA);
1626 /* upper 16 bits has Tx packet buffer allocation size in KB */
1627 tx_space = pba >> 16;
1628 /* lower 16 bits has Rx packet buffer allocation size in KB */
1629 pba &= 0xffff;
1630 /* the tx fifo also stores 16 bytes of information about the tx
1631 * but don't include ethernet FCS because hardware appends it */
1632 min_tx_space = (adapter->max_frame_size +
85e8d004 1633 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1634 ETH_FCS_LEN) * 2;
1635 min_tx_space = ALIGN(min_tx_space, 1024);
1636 min_tx_space >>= 10;
1637 /* software strips receive CRC, so leave room for it */
1638 min_rx_space = adapter->max_frame_size;
1639 min_rx_space = ALIGN(min_rx_space, 1024);
1640 min_rx_space >>= 10;
1641
1642 /* If current Tx allocation is less than the min Tx FIFO size,
1643 * and the min Tx FIFO size is less than the current Rx FIFO
1644 * allocation, take space away from current Rx allocation */
1645 if (tx_space < min_tx_space &&
1646 ((min_tx_space - tx_space) < pba)) {
1647 pba = pba - (min_tx_space - tx_space);
1648
1649 /* if short on rx space, rx wins and must trump tx
1650 * adjustment */
1651 if (pba < min_rx_space)
1652 pba = min_rx_space;
1653 }
2d064c06 1654 wr32(E1000_PBA, pba);
9d5c8243 1655 }
9d5c8243
AK		 1656
1657 /* flow control settings */
1658 /* The high water mark must be low enough to fit one full frame
1659 * (or the size used for early receive) above it in the Rx FIFO.
1660 * Set it to the lower of:
1661 * - 90% of the Rx FIFO size, or
1662 * - the full Rx FIFO size minus one full frame */
1663 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1664 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1665
d48507fe 1666 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1667 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1668 fc->pause_time = 0xFFFF;
1669 fc->send_xon = 1;
0cce119a 1670 fc->current_mode = fc->requested_mode;
9d5c8243 1671
4ae196df
AD		 1672 /* disable receive for all VFs and wait one second */
1673 if (adapter->vfs_allocated_count) {
1674 int i;
1675 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1676 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1677
1678 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1679 igb_ping_all_vfs(adapter);
4ae196df
AD		 1680
1681 /* disable transmits and receives */
1682 wr32(E1000_VFRE, 0);
1683 wr32(E1000_VFTE, 0);
1684 }
1685
9d5c8243 1686 /* Allow time for pending master requests to run */
330a6d6a 1687 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1688 wr32(E1000_WUC, 0);
1689
330a6d6a 1690 if (hw->mac.ops.init_hw(hw))
090b1795 1691 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1692
a27416bb
MV		 1693 /*
1694 * Flow control settings reset on hardware reset, so guarantee flow
1695 * control is off when forcing speed.
1696 */
1697 if (!hw->mac.autoneg)
1698 igb_force_mac_fc(hw);
1699
b6e0c419 1700 igb_init_dmac(adapter, pba);
88a268c1
NN		 1701 if (!netif_running(adapter->netdev))
1702 igb_power_down_link(adapter);
1703
9d5c8243
AK		 1704 igb_update_mng_vlan(adapter);
1705
1706 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1707 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1708
1f6e8178
MV		 1709 /* Re-enable PTP, where applicable. */
1710 igb_ptp_reset(adapter);
1f6e8178 1711
330a6d6a 1712 igb_get_phy_info(hw);
9d5c8243
AK		 1713}
1714
c8f44aff
MM		 1715static netdev_features_t igb_fix_features(struct net_device *netdev,
1716 netdev_features_t features)
b2cb09b1
JP		 1717{
1718 /*
1719 * Since there is no support for separate rx/tx vlan accel
1720 * enable/disable make sure tx flag is always in same state as rx.
1721 */
1722 if (features & NETIF_F_HW_VLAN_RX)
1723 features |= NETIF_F_HW_VLAN_TX;
1724 else
1725 features &= ~NETIF_F_HW_VLAN_TX;
1726
1727 return features;
1728}
1729
c8f44aff
MM		 1730static int igb_set_features(struct net_device *netdev,
1731 netdev_features_t features)
ac52caa3 1732{
c8f44aff 1733 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1734 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1735
b2cb09b1
JP		 1736 if (changed & NETIF_F_HW_VLAN_RX)
1737 igb_vlan_mode(netdev, features);
1738
89eaefb6
BG		 1739 if (!(changed & NETIF_F_RXALL))
1740 return 0;
1741
1742 netdev->features = features;
1743
1744 if (netif_running(netdev))
1745 igb_reinit_locked(adapter);
1746 else
1747 igb_reset(adapter);
1748
ac52caa3
MM		 1749 return 0;
1750}
1751
2e5c6922 1752static const struct net_device_ops igb_netdev_ops = {
559e9c49 1753 .ndo_open = igb_open,
2e5c6922 1754 .ndo_stop = igb_close,
cd392f5c 1755 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1756 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1757 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1758 .ndo_set_mac_address = igb_set_mac,
1759 .ndo_change_mtu = igb_change_mtu,
1760 .ndo_do_ioctl = igb_ioctl,
1761 .ndo_tx_timeout = igb_tx_timeout,
1762 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1763 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1764 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1765 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1766 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1767 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1768 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1769#ifdef CONFIG_NET_POLL_CONTROLLER
1770 .ndo_poll_controller = igb_netpoll,
1771#endif
b2cb09b1
JP		 1772 .ndo_fix_features = igb_fix_features,
1773 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1774};
1775
d67974f0
CW		 1776/**
1777 * igb_set_fw_version - Configure version string for ethtool
1778 * @adapter: adapter struct
1779 *
1780 **/
1781void igb_set_fw_version(struct igb_adapter *adapter)
1782{
1783 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1784 struct e1000_fw_version fw;
1785
1786 igb_get_fw_version(hw, &fw);
1787
1788 switch (hw->mac.type) {
1789 case e1000_i211:
d67974f0 1790 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1791 "%2d.%2d-%d",
1792 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1793 break;
1794
1795 default:
1796 /* if option is rom valid, display its version too */
1797 if (fw.or_valid) {
1798 snprintf(adapter->fw_version,
1799 sizeof(adapter->fw_version),
1800 "%d.%d, 0x%08x, %d.%d.%d",
1801 fw.eep_major, fw.eep_minor, fw.etrack_id,
1802 fw.or_major, fw.or_build, fw.or_patch);
1803 /* no option rom */
1804 } else {
1805 snprintf(adapter->fw_version,
1806 sizeof(adapter->fw_version),
1807 "%d.%d, 0x%08x",
1808 fw.eep_major, fw.eep_minor, fw.etrack_id);
1809 }
1810 break;
d67974f0 1811 }
d67974f0
CW		 1812 return;
1813}
1814
9d5c8243
AK		 1815/**
1816 * igb_probe - Device Initialization Routine
1817 * @pdev: PCI device information struct
1818 * @ent: entry in igb_pci_tbl
1819 *
1820 * Returns 0 on success, negative on failure
1821 *
1822 * igb_probe initializes an adapter identified by a pci_dev structure.
1823 * The OS initialization, configuring of the adapter private structure,
1824 * and a hardware reset occur.
1825 **/
9f9a12f8 1826static int igb_probe(struct pci_dev *pdev,
9d5c8243
AK		 1827 const struct pci_device_id *ent)
1828{
1829 struct net_device *netdev;
1830 struct igb_adapter *adapter;
1831 struct e1000_hw *hw;
4337e993 1832 u16 eeprom_data = 0;
9835fd73 1833 s32 ret_val;
4337e993 1834 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1835 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1836 unsigned long mmio_start, mmio_len;
2d6a5e95 1837 int err, pci_using_dac;
9835fd73 1838 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1839
bded64a7
AG		 1840 /* Catch broken hardware that put the wrong VF device ID in
1841 * the PCIe SR-IOV capability.
1842 */
1843 if (pdev->is_virtfn) {
1844 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1845 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1846 return -EINVAL;
1847 }
1848
aed5dec3 1849 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1850 if (err)
1851 return err;
1852
1853 pci_using_dac = 0;
59d71989 1854 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1855 if (!err) {
59d71989 1856 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1857 if (!err)
1858 pci_using_dac = 1;
1859 } else {
59d71989 1860 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1861 if (err) {
59d71989 1862 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1863 if (err) {
1864 dev_err(&pdev->dev, "No usable DMA "
1865 "configuration, aborting\n");
1866 goto err_dma;
1867 }
1868 }
1869 }
1870
aed5dec3
AD		 1871 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1872 IORESOURCE_MEM),
1873 igb_driver_name);
9d5c8243
AK		 1874 if (err)
1875 goto err_pci_reg;
1876
19d5afd4 1877 pci_enable_pcie_error_reporting(pdev);
40a914fa 1878
9d5c8243 1879 pci_set_master(pdev);
c682fc23 1880 pci_save_state(pdev);
9d5c8243
AK		 1881
1882 err = -ENOMEM;
1bfaf07b 1883 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 1884 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1885 if (!netdev)
1886 goto err_alloc_etherdev;
1887
1888 SET_NETDEV_DEV(netdev, &pdev->dev);
1889
1890 pci_set_drvdata(pdev, netdev);
1891 adapter = netdev_priv(netdev);
1892 adapter->netdev = netdev;
1893 adapter->pdev = pdev;
1894 hw = &adapter->hw;
1895 hw->back = adapter;
b3f4d599 1896 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 1897
1898 mmio_start = pci_resource_start(pdev, 0);
1899 mmio_len = pci_resource_len(pdev, 0);
1900
1901 err = -EIO;
28b0759c
AD		 1902 hw->hw_addr = ioremap(mmio_start, mmio_len);
1903 if (!hw->hw_addr)
9d5c8243
AK		 1904 goto err_ioremap;
1905
2e5c6922 1906 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1907 igb_set_ethtool_ops(netdev);
9d5c8243 1908 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1909
1910 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1911
1912 netdev->mem_start = mmio_start;
1913 netdev->mem_end = mmio_start + mmio_len;
1914
9d5c8243
AK		 1915 /* PCI config space info */
1916 hw->vendor_id = pdev->vendor;
1917 hw->device_id = pdev->device;
1918 hw->revision_id = pdev->revision;
1919 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1920 hw->subsystem_device_id = pdev->subsystem_device;
1921
9d5c8243
AK		 1922 /* Copy the default MAC, PHY and NVM function pointers */
1923 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1924 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1925 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1926 /* Initialize skew-specific constants */
1927 err = ei->get_invariants(hw);
1928 if (err)
450c87c8 1929 goto err_sw_init;
9d5c8243 1930
450c87c8 1931 /* setup the private structure */
9d5c8243
AK		 1932 err = igb_sw_init(adapter);
1933 if (err)
1934 goto err_sw_init;
1935
1936 igb_get_bus_info_pcie(hw);
1937
1938 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1939
1940 /* Copper options */
1941 if (hw->phy.media_type == e1000_media_type_copper) {
1942 hw->phy.mdix = AUTO_ALL_MODES;
1943 hw->phy.disable_polarity_correction = false;
1944 hw->phy.ms_type = e1000_ms_hw_default;
1945 }
1946
1947 if (igb_check_reset_block(hw))
1948 dev_info(&pdev->dev,
1949 "PHY reset is blocked due to SOL/IDER session.\n");
1950
077887c3
AD		 1951 /*
1952 * features is initialized to 0 in allocation, it might have bits
1953 * set by igb_sw_init so we should use an or instead of an
1954 * assignment.
1955 */
1956 netdev->features |= NETIF_F_SG |
1957 NETIF_F_IP_CSUM |
1958 NETIF_F_IPV6_CSUM |
1959 NETIF_F_TSO |
1960 NETIF_F_TSO6 |
1961 NETIF_F_RXHASH |
1962 NETIF_F_RXCSUM |
1963 NETIF_F_HW_VLAN_RX |
1964 NETIF_F_HW_VLAN_TX;
1965
1966 /* copy netdev features into list of user selectable features */
1967 netdev->hw_features |= netdev->features;
89eaefb6 1968 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 1969
1970 /* set this bit last since it cannot be part of hw_features */
1971 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1972
1973 netdev->vlan_features |= NETIF_F_TSO |
1974 NETIF_F_TSO6 |
1975 NETIF_F_IP_CSUM |
1976 NETIF_F_IPV6_CSUM |
1977 NETIF_F_SG;
48f29ffc 1978
6b8f0922
BG		 1979 netdev->priv_flags |= IFF_SUPP_NOFCS;
1980
7b872a55 1981 if (pci_using_dac) {
9d5c8243 1982 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1983 netdev->vlan_features |= NETIF_F_HIGHDMA;
1984 }
9d5c8243 1985
ac52caa3
MM		 1986 if (hw->mac.type >= e1000_82576) {
1987 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1988 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 1989 }
b9473560 1990
01789349
JP		 1991 netdev->priv_flags |= IFF_UNICAST_FLT;
1992
330a6d6a 1993 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1994
1995 /* before reading the NVM, reset the controller to put the device in a
1996 * known good starting state */
1997 hw->mac.ops.reset_hw(hw);
1998
f96a8a0b
CW		 1999 /*
2000 * make sure the NVM is good , i211 parts have special NVM that
2001 * doesn't contain a checksum
2002 */
2003 if (hw->mac.type != e1000_i211) {
2004 if (hw->nvm.ops.validate(hw) < 0) {
2005 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2006 err = -EIO;
2007 goto err_eeprom;
2008 }
9d5c8243
AK		 2009 }
2010
2011 /* copy the MAC address out of the NVM */
2012 if (hw->mac.ops.read_mac_addr(hw))
2013 dev_err(&pdev->dev, "NVM Read Error\n");
2014
2015 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2016 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2017
2018 if (!is_valid_ether_addr(netdev->perm_addr)) {
2019 dev_err(&pdev->dev, "Invalid MAC Address\n");
2020 err = -EIO;
2021 goto err_eeprom;
2022 }
2023
d67974f0
CW		 2024 /* get firmware version for ethtool -i */
2025 igb_set_fw_version(adapter);
2026
c061b18d 2027 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2028 (unsigned long) adapter);
c061b18d 2029 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2030 (unsigned long) adapter);
9d5c8243
AK		 2031
2032 INIT_WORK(&adapter->reset_task, igb_reset_task);
2033 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2034
450c87c8 2035 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2036 adapter->fc_autoneg = true;
2037 hw->mac.autoneg = true;
2038 hw->phy.autoneg_advertised = 0x2f;
2039
0cce119a
AD		 2040 hw->fc.requested_mode = e1000_fc_default;
2041 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2042
9d5c8243
AK		 2043 igb_validate_mdi_setting(hw);
2044
63d4a8f9 2045 /* By default, support wake on port A */
a2cf8b6c 2046 if (hw->bus.func == 0)
63d4a8f9
MV		 2047 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2048
2049 /* Check the NVM for wake support on non-port A ports */
2050 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2051 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2052 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2053 &eeprom_data);
a2cf8b6c
AD		 2054 else if (hw->bus.func == 1)
2055 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2056
63d4a8f9
MV		 2057 if (eeprom_data & IGB_EEPROM_APME)
2058 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2059
2060 /* now that we have the eeprom settings, apply the special cases where
2061 * the eeprom may be wrong or the board simply won't support wake on
2062 * lan on a particular port */
2063 switch (pdev->device) {
2064 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2065 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2066 break;
2067 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2068 case E1000_DEV_ID_82576_FIBER:
2069 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2070 /* Wake events only supported on port A for dual fiber
2071 * regardless of eeprom setting */
2072 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2073 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2074 break;
c8ea5ea9 2075 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2076 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2077 /* if quad port adapter, disable WoL on all but port A */
2078 if (global_quad_port_a != 0)
63d4a8f9 2079 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2080 else
2081 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2082 /* Reset for multiple quad port adapters */
2083 if (++global_quad_port_a == 4)
2084 global_quad_port_a = 0;
2085 break;
63d4a8f9
MV		 2086 default:
2087 /* If the device can't wake, don't set software support */
2088 if (!device_can_wakeup(&adapter->pdev->dev))
2089 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2090 }
2091
2092 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2093 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2094 adapter->wol |= E1000_WUFC_MAG;
2095
2096 /* Some vendors want WoL disabled by default, but still supported */
2097 if ((hw->mac.type == e1000_i350) &&
2098 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2099 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2100 adapter->wol = 0;
2101 }
2102
2103 device_set_wakeup_enable(&adapter->pdev->dev,
2104 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2105
2106 /* reset the hardware with the new settings */
2107 igb_reset(adapter);
2108
2109 /* let the f/w know that the h/w is now under the control of the
2110 * driver. */
2111 igb_get_hw_control(adapter);
2112
9d5c8243
AK		 2113 strcpy(netdev->name, "eth%d");
2114 err = register_netdev(netdev);
2115 if (err)
2116 goto err_register;
2117
b168dfc5
JB		 2118 /* carrier off reporting is important to ethtool even BEFORE open */
2119 netif_carrier_off(netdev);
2120
421e02f0 2121#ifdef CONFIG_IGB_DCA
bbd98fe4 2122 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2123 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2124 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2125 igb_setup_dca(adapter);
2126 }
fe4506b6 2127
38c845c7 2128#endif
3c89f6d0 2129
673b8b70 2130 /* do hw tstamp init after resetting */
7ebae817 2131 igb_ptp_init(adapter);
673b8b70 2132
9d5c8243
AK		 2133 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2134 /* print bus type/speed/width info */
7c510e4b 2135 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2136 netdev->name,
559e9c49 2137 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2138 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2139 "unknown"),
59c3de89
AD		 2140 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2141 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2142 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2143 "unknown"),
7c510e4b 2144 netdev->dev_addr);
9d5c8243 2145
9835fd73
CW		 2146 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2147 if (ret_val)
2148 strcpy(part_str, "Unknown");
2149 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2150 dev_info(&pdev->dev,
2151 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2152 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2153 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2154 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2155 switch (hw->mac.type) {
2156 case e1000_i350:
f96a8a0b
CW		 2157 case e1000_i210:
2158 case e1000_i211:
09b068d4
CW		 2159 igb_set_eee_i350(hw);
2160 break;
2161 default:
2162 break;
2163 }
749ab2cd
YZ		 2164
2165 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2166 return 0;
2167
2168err_register:
2169 igb_release_hw_control(adapter);
2170err_eeprom:
2171 if (!igb_check_reset_block(hw))
f5f4cf08 2172 igb_reset_phy(hw);
9d5c8243
AK		 2173
2174 if (hw->flash_address)
2175 iounmap(hw->flash_address);
9d5c8243 2176err_sw_init:
047e0030 2177 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2178 iounmap(hw->hw_addr);
2179err_ioremap:
2180 free_netdev(netdev);
2181err_alloc_etherdev:
559e9c49
AD		 2182 pci_release_selected_regions(pdev,
2183 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2184err_pci_reg:
2185err_dma:
2186 pci_disable_device(pdev);
2187 return err;
2188}
2189
2190/**
2191 * igb_remove - Device Removal Routine
2192 * @pdev: PCI device information struct
2193 *
2194 * igb_remove is called by the PCI subsystem to alert the driver
2195 * that it should release a PCI device. The could be caused by a
2196 * Hot-Plug event, or because the driver is going to be removed from
2197 * memory.
2198 **/
9f9a12f8 2199static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2200{
2201 struct net_device *netdev = pci_get_drvdata(pdev);
2202 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2203 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2204
749ab2cd 2205 pm_runtime_get_noresume(&pdev->dev);
a79f4f88 2206 igb_ptp_stop(adapter);
749ab2cd 2207
760141a5
TH		 2208 /*
2209 * The watchdog timer may be rescheduled, so explicitly
2210 * disable watchdog from being rescheduled.
2211 */
9d5c8243
AK		 2212 set_bit(__IGB_DOWN, &adapter->state);
2213 del_timer_sync(&adapter->watchdog_timer);
2214 del_timer_sync(&adapter->phy_info_timer);
2215
760141a5
TH		 2216 cancel_work_sync(&adapter->reset_task);
2217 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2218
421e02f0 2219#ifdef CONFIG_IGB_DCA
7dfc16fa 2220 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2221 dev_info(&pdev->dev, "DCA disabled\n");
2222 dca_remove_requester(&pdev->dev);
7dfc16fa 2223 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2224 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2225 }
2226#endif
2227
9d5c8243
AK		 2228 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2229 * would have already happened in close and is redundant. */
2230 igb_release_hw_control(adapter);
2231
2232 unregister_netdev(netdev);
2233
047e0030 2234 igb_clear_interrupt_scheme(adapter);
9d5c8243 2235
37680117
AD		 2236#ifdef CONFIG_PCI_IOV
2237 /* reclaim resources allocated to VFs */
2238 if (adapter->vf_data) {
2239 /* disable iov and allow time for transactions to clear */
f557147c
SA		 2240 if (igb_vfs_are_assigned(adapter)) {
2241 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2242 } else {
0224d663
GR		 2243 pci_disable_sriov(pdev);
2244 msleep(500);
0224d663 2245 }
37680117
AD		 2246
2247 kfree(adapter->vf_data);
2248 adapter->vf_data = NULL;
2249 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2250 wrfl();
37680117
AD		 2251 msleep(100);
2252 dev_info(&pdev->dev, "IOV Disabled\n");
2253 }
2254#endif
559e9c49 2255
28b0759c
AD		 2256 iounmap(hw->hw_addr);
2257 if (hw->flash_address)
2258 iounmap(hw->flash_address);
559e9c49
AD		 2259 pci_release_selected_regions(pdev,
2260 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2261
1128c756 2262 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2263 free_netdev(netdev);
2264
19d5afd4 2265 pci_disable_pcie_error_reporting(pdev);
40a914fa 2266
9d5c8243
AK		 2267 pci_disable_device(pdev);
2268}
2269
a6b623e0
AD		 2270/**
2271 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2272 * @adapter: board private structure to initialize
2273 *
2274 * This function initializes the vf specific data storage and then attempts to
2275 * allocate the VFs. The reason for ordering it this way is because it is much
2276 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2277 * the memory for the VFs.
2278 **/
9f9a12f8 2279static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2280{
2281#ifdef CONFIG_PCI_IOV
2282 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2283 struct e1000_hw *hw = &adapter->hw;
f557147c 2284 int old_vfs = pci_num_vf(adapter->pdev);
0224d663 2285 int i;
a6b623e0 2286
f96a8a0b
CW		 2287 /* Virtualization features not supported on i210 family. */
2288 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2289 return;
2290
0224d663
GR		 2291 if (old_vfs) {
2292 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2293 "max_vfs setting of %d\n", old_vfs, max_vfs);
2294 adapter->vfs_allocated_count = old_vfs;
a6b623e0
AD		 2295 }
2296
0224d663
GR		 2297 if (!adapter->vfs_allocated_count)
2298 return;
2299
2300 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2301 sizeof(struct vf_data_storage), GFP_KERNEL);
f96a8a0b 2302
0224d663
GR		 2303 /* if allocation failed then we do not support SR-IOV */
2304 if (!adapter->vf_data) {
a6b623e0 2305 adapter->vfs_allocated_count = 0;
0224d663
GR		 2306 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2307 "Data Storage\n");
2308 goto out;
a6b623e0 2309 }
0224d663
GR		 2310
2311 if (!old_vfs) {
2312 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2313 goto err_out;
2314 }
2315 dev_info(&pdev->dev, "%d VFs allocated\n",
2316 adapter->vfs_allocated_count);
2317 for (i = 0; i < adapter->vfs_allocated_count; i++)
2318 igb_vf_configure(adapter, i);
2319
2320 /* DMA Coalescing is not supported in IOV mode. */
2321 adapter->flags &= ~IGB_FLAG_DMAC;
2322 goto out;
2323err_out:
2324 kfree(adapter->vf_data);
2325 adapter->vf_data = NULL;
2326 adapter->vfs_allocated_count = 0;
2327out:
2328 return;
a6b623e0
AD		 2329#endif /* CONFIG_PCI_IOV */
2330}
2331
9d5c8243
AK		 2332/**
2333 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2334 * @adapter: board private structure to initialize
2335 *
2336 * igb_sw_init initializes the Adapter private data structure.
2337 * Fields are initialized based on PCI device information and
2338 * OS network device settings (MTU size).
2339 **/
9f9a12f8 2340static int igb_sw_init(struct igb_adapter *adapter)
9d5c8243
AK		 2341{
2342 struct e1000_hw *hw = &adapter->hw;
2343 struct net_device *netdev = adapter->netdev;
2344 struct pci_dev *pdev = adapter->pdev;
374a542d 2345 u32 max_rss_queues;
9d5c8243
AK		 2346
2347 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2348
13fde97a 2349 /* set default ring sizes */
68fd9910
AD		 2350 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2351 adapter->rx_ring_count = IGB_DEFAULT_RXD;
13fde97a
AD		 2352
2353 /* set default ITR values */
4fc82adf
AD		 2354 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2355 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2356
13fde97a
AD		 2357 /* set default work limits */
2358 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2359
153285f9
AD		 2360 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2361 VLAN_HLEN;
9d5c8243
AK		 2362 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2363
12dcd86b 2364 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2365#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2366 switch (hw->mac.type) {
2367 case e1000_82576:
2368 case e1000_i350:
9b082d73
SA		 2369 if (max_vfs > 7) {
2370 dev_warn(&pdev->dev,
2371 "Maximum of 7 VFs per PF, using max\n");
2372 adapter->vfs_allocated_count = 7;
2373 } else
2374 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2375 break;
2376 default:
2377 break;
2378 }
a6b623e0 2379#endif /* CONFIG_PCI_IOV */
374a542d
MV		 2380
2381 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2382 switch (hw->mac.type) {
374a542d
MV		 2383 case e1000_i211:
2384 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2385 break;
2386 case e1000_82575:
f96a8a0b 2387 case e1000_i210:
374a542d
MV		 2388 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2389 break;
2390 case e1000_i350:
2391 /* I350 cannot do RSS and SR-IOV at the same time */
2392 if (!!adapter->vfs_allocated_count) {
2393 max_rss_queues = 1;
2394 break;
2395 }
2396 /* fall through */
2397 case e1000_82576:
2398 if (!!adapter->vfs_allocated_count) {
2399 max_rss_queues = 2;
2400 break;
2401 }
2402 /* fall through */
2403 case e1000_82580:
2404 default:
2405 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2406 break;
374a542d
MV		 2407 }
2408
2409 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2410
2411 /* Determine if we need to pair queues. */
2412 switch (hw->mac.type) {
2413 case e1000_82575:
f96a8a0b 2414 case e1000_i211:
374a542d 2415 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2416 break;
374a542d
MV		 2417 case e1000_82576:
2418 /*
2419 * If VFs are going to be allocated with RSS queues then we
2420 * should pair the queues in order to conserve interrupts due
2421 * to limited supply.
2422 */
2423 if ((adapter->rss_queues > 1) &&
2424 (adapter->vfs_allocated_count > 6))
2425 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2426 /* fall through */
2427 case e1000_82580:
2428 case e1000_i350:
2429 case e1000_i210:
f96a8a0b 2430 default:
374a542d
MV		 2431 /*
2432 * If rss_queues > half of max_rss_queues, pair the queues in
2433 * order to conserve interrupts due to limited supply.
2434 */
2435 if (adapter->rss_queues > (max_rss_queues / 2))
2436 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2437 break;
2438 }
a99955fc 2439
1128c756
CW		 2440 /* Setup and initialize a copy of the hw vlan table array */
2441 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2442 E1000_VLAN_FILTER_TBL_SIZE,
2443 GFP_ATOMIC);
2444
a6b623e0 2445 /* This call may decrease the number of queues */
53c7d064 2446 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2447 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2448 return -ENOMEM;
2449 }
2450
a6b623e0
AD		 2451 igb_probe_vfs(adapter);
2452
9d5c8243
AK		 2453 /* Explicitly disable IRQ since the NIC can be in any state. */
2454 igb_irq_disable(adapter);
2455
f96a8a0b 2456 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2457 adapter->flags &= ~IGB_FLAG_DMAC;
2458
9d5c8243
AK		 2459 set_bit(__IGB_DOWN, &adapter->state);
2460 return 0;
2461}
2462
2463/**
2464 * igb_open - Called when a network interface is made active
2465 * @netdev: network interface device structure
2466 *
2467 * Returns 0 on success, negative value on failure
2468 *
2469 * The open entry point is called when a network interface is made
2470 * active by the system (IFF_UP). At this point all resources needed
2471 * for transmit and receive operations are allocated, the interrupt
2472 * handler is registered with the OS, the watchdog timer is started,
2473 * and the stack is notified that the interface is ready.
2474 **/
749ab2cd 2475static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2476{
2477 struct igb_adapter *adapter = netdev_priv(netdev);
2478 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2479 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2480 int err;
2481 int i;
2482
2483 /* disallow open during test */
749ab2cd
YZ		 2484 if (test_bit(__IGB_TESTING, &adapter->state)) {
2485 WARN_ON(resuming);
9d5c8243 2486 return -EBUSY;
749ab2cd
YZ		 2487 }
2488
2489 if (!resuming)
2490 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2491
b168dfc5
JB		 2492 netif_carrier_off(netdev);
2493
9d5c8243
AK		 2494 /* allocate transmit descriptors */
2495 err = igb_setup_all_tx_resources(adapter);
2496 if (err)
2497 goto err_setup_tx;
2498
2499 /* allocate receive descriptors */
2500 err = igb_setup_all_rx_resources(adapter);
2501 if (err)
2502 goto err_setup_rx;
2503
88a268c1 2504 igb_power_up_link(adapter);
9d5c8243 2505
9d5c8243
AK		 2506 /* before we allocate an interrupt, we must be ready to handle it.
2507 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2508 * as soon as we call pci_request_irq, so we have to setup our
2509 * clean_rx handler before we do so. */
2510 igb_configure(adapter);
2511
2512 err = igb_request_irq(adapter);
2513 if (err)
2514 goto err_req_irq;
2515
0c2cc02e
AD		 2516 /* Notify the stack of the actual queue counts. */
2517 err = netif_set_real_num_tx_queues(adapter->netdev,
2518 adapter->num_tx_queues);
2519 if (err)
2520 goto err_set_queues;
2521
2522 err = netif_set_real_num_rx_queues(adapter->netdev,
2523 adapter->num_rx_queues);
2524 if (err)
2525 goto err_set_queues;
2526
9d5c8243
AK		 2527 /* From here on the code is the same as igb_up() */
2528 clear_bit(__IGB_DOWN, &adapter->state);
2529
0d1ae7f4
AD		 2530 for (i = 0; i < adapter->num_q_vectors; i++)
2531 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2532
2533 /* Clear any pending interrupts. */
2534 rd32(E1000_ICR);
844290e5
PW		 2535
2536 igb_irq_enable(adapter);
2537
d4960307
AD		 2538 /* notify VFs that reset has been completed */
2539 if (adapter->vfs_allocated_count) {
2540 u32 reg_data = rd32(E1000_CTRL_EXT);
2541 reg_data |= E1000_CTRL_EXT_PFRSTD;
2542 wr32(E1000_CTRL_EXT, reg_data);
2543 }
2544
d55b53ff
JK		 2545 netif_tx_start_all_queues(netdev);
2546
749ab2cd
YZ		 2547 if (!resuming)
2548 pm_runtime_put(&pdev->dev);
2549
25568a53
AD		 2550 /* start the watchdog. */
2551 hw->mac.get_link_status = 1;
2552 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2553
2554 return 0;
2555
0c2cc02e
AD		 2556err_set_queues:
2557 igb_free_irq(adapter);
9d5c8243
AK		 2558err_req_irq:
2559 igb_release_hw_control(adapter);
88a268c1 2560 igb_power_down_link(adapter);
9d5c8243
AK		 2561 igb_free_all_rx_resources(adapter);
2562err_setup_rx:
2563 igb_free_all_tx_resources(adapter);
2564err_setup_tx:
2565 igb_reset(adapter);
749ab2cd
YZ		 2566 if (!resuming)
2567 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2568
2569 return err;
2570}
2571
749ab2cd
YZ		 2572static int igb_open(struct net_device *netdev)
2573{
2574 return __igb_open(netdev, false);
2575}
2576
9d5c8243
AK		 2577/**
2578 * igb_close - Disables a network interface
2579 * @netdev: network interface device structure
2580 *
2581 * Returns 0, this is not allowed to fail
2582 *
2583 * The close entry point is called when an interface is de-activated
2584 * by the OS. The hardware is still under the driver's control, but
2585 * needs to be disabled. A global MAC reset is issued to stop the
2586 * hardware, and all transmit and receive resources are freed.
2587 **/
749ab2cd 2588static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2589{
2590 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2591 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2592
2593 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2594
749ab2cd
YZ		 2595 if (!suspending)
2596 pm_runtime_get_sync(&pdev->dev);
2597
2598 igb_down(adapter);
9d5c8243
AK		 2599 igb_free_irq(adapter);
2600
2601 igb_free_all_tx_resources(adapter);
2602 igb_free_all_rx_resources(adapter);
2603
749ab2cd
YZ		 2604 if (!suspending)
2605 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2606 return 0;
2607}
2608
749ab2cd
YZ		 2609static int igb_close(struct net_device *netdev)
2610{
2611 return __igb_close(netdev, false);
2612}
2613
9d5c8243
AK		 2614/**
2615 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2616 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2617 *
2618 * Return 0 on success, negative on failure
2619 **/
80785298 2620int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2621{
59d71989 2622 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2623 int size;
2624
06034649 2625 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2626
2627 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2628 if (!tx_ring->tx_buffer_info)
9d5c8243 2629 goto err;
9d5c8243
AK		 2630
2631 /* round up to nearest 4K */
85e8d004 2632 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2633 tx_ring->size = ALIGN(tx_ring->size, 4096);
2634
5536d210
AD		 2635 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2636 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2637 if (!tx_ring->desc)
2638 goto err;
2639
9d5c8243
AK		 2640 tx_ring->next_to_use = 0;
2641 tx_ring->next_to_clean = 0;
81c2fc22 2642
9d5c8243
AK		 2643 return 0;
2644
2645err:
06034649 2646 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2647 tx_ring->tx_buffer_info = NULL;
2648 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2649 return -ENOMEM;
2650}
2651
2652/**
2653 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2654 * (Descriptors) for all queues
2655 * @adapter: board private structure
2656 *
2657 * Return 0 on success, negative on failure
2658 **/
2659static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2660{
439705e1 2661 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2662 int i, err = 0;
2663
2664 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2665 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2666 if (err) {
439705e1 2667 dev_err(&pdev->dev,
9d5c8243
AK		 2668 "Allocation for Tx Queue %u failed\n", i);
2669 for (i--; i >= 0; i--)
3025a446 2670 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2671 break;
2672 }
2673 }
2674
2675 return err;
2676}
2677
2678/**
85b430b4
AD		 2679 * igb_setup_tctl - configure the transmit control registers
2680 * @adapter: Board private structure
9d5c8243 2681 **/
d7ee5b3a 2682void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2683{
9d5c8243
AK		 2684 struct e1000_hw *hw = &adapter->hw;
2685 u32 tctl;
9d5c8243 2686
85b430b4
AD		 2687 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2688 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2689
2690 /* Program the Transmit Control Register */
9d5c8243
AK		 2691 tctl = rd32(E1000_TCTL);
2692 tctl &= ~E1000_TCTL_CT;
2693 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2694 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2695
2696 igb_config_collision_dist(hw);
2697
9d5c8243
AK		 2698 /* Enable transmits */
2699 tctl |= E1000_TCTL_EN;
2700
2701 wr32(E1000_TCTL, tctl);
2702}
2703
85b430b4
AD		 2704/**
2705 * igb_configure_tx_ring - Configure transmit ring after Reset
2706 * @adapter: board private structure
2707 * @ring: tx ring to configure
2708 *
2709 * Configure a transmit ring after a reset.
2710 **/
d7ee5b3a
AD		 2711void igb_configure_tx_ring(struct igb_adapter *adapter,
2712 struct igb_ring *ring)
85b430b4
AD		 2713{
2714 struct e1000_hw *hw = &adapter->hw;
a74420e0 2715 u32 txdctl = 0;
85b430b4
AD		 2716 u64 tdba = ring->dma;
2717 int reg_idx = ring->reg_idx;
2718
2719 /* disable the queue */
a74420e0 2720 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2721 wrfl();
2722 mdelay(10);
2723
2724 wr32(E1000_TDLEN(reg_idx),
2725 ring->count * sizeof(union e1000_adv_tx_desc));
2726 wr32(E1000_TDBAL(reg_idx),
2727 tdba & 0x00000000ffffffffULL);
2728 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2729
fce99e34 2730 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2731 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2732 writel(0, ring->tail);
85b430b4
AD		 2733
2734 txdctl |= IGB_TX_PTHRESH;
2735 txdctl |= IGB_TX_HTHRESH << 8;
2736 txdctl |= IGB_TX_WTHRESH << 16;
2737
2738 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2739 wr32(E1000_TXDCTL(reg_idx), txdctl);
2740}
2741
2742/**
2743 * igb_configure_tx - Configure transmit Unit after Reset
2744 * @adapter: board private structure
2745 *
2746 * Configure the Tx unit of the MAC after a reset.
2747 **/
2748static void igb_configure_tx(struct igb_adapter *adapter)
2749{
2750 int i;
2751
2752 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2753 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2754}
2755
9d5c8243
AK		 2756/**
2757 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2758 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2759 *
2760 * Returns 0 on success, negative on failure
2761 **/
80785298 2762int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2763{
59d71989 2764 struct device *dev = rx_ring->dev;
f33005a6 2765 int size;
9d5c8243 2766
06034649 2767 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 2768
2769 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2770 if (!rx_ring->rx_buffer_info)
9d5c8243 2771 goto err;
9d5c8243 2772
9d5c8243 2773 /* Round up to nearest 4K */
f33005a6 2774 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 2775 rx_ring->size = ALIGN(rx_ring->size, 4096);
2776
5536d210
AD		 2777 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2778 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2779 if (!rx_ring->desc)
2780 goto err;
2781
cbc8e55f 2782 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 2783 rx_ring->next_to_clean = 0;
2784 rx_ring->next_to_use = 0;
9d5c8243 2785
9d5c8243
AK		 2786 return 0;
2787
2788err:
06034649
AD		 2789 vfree(rx_ring->rx_buffer_info);
2790 rx_ring->rx_buffer_info = NULL;
f33005a6 2791 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 2792 return -ENOMEM;
2793}
2794
2795/**
2796 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2797 * (Descriptors) for all queues
2798 * @adapter: board private structure
2799 *
2800 * Return 0 on success, negative on failure
2801 **/
2802static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2803{
439705e1 2804 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2805 int i, err = 0;
2806
2807 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2808 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2809 if (err) {
439705e1 2810 dev_err(&pdev->dev,
9d5c8243
AK		 2811 "Allocation for Rx Queue %u failed\n", i);
2812 for (i--; i >= 0; i--)
3025a446 2813 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2814 break;
2815 }
2816 }
2817
2818 return err;
2819}
2820
06cf2666
AD		 2821/**
2822 * igb_setup_mrqc - configure the multiple receive queue control registers
2823 * @adapter: Board private structure
2824 **/
2825static void igb_setup_mrqc(struct igb_adapter *adapter)
2826{
2827 struct e1000_hw *hw = &adapter->hw;
2828 u32 mrqc, rxcsum;
797fd4be 2829 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 2830 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2831 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2832 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2833 0xFA01ACBE };
06cf2666
AD		 2834
2835 /* Fill out hash function seeds */
a57fe23e
AD		 2836 for (j = 0; j < 10; j++)
2837 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 2838
a99955fc 2839 num_rx_queues = adapter->rss_queues;
06cf2666 2840
797fd4be
AD		 2841 switch (hw->mac.type) {
2842 case e1000_82575:
2843 shift = 6;
2844 break;
2845 case e1000_82576:
2846 /* 82576 supports 2 RSS queues for SR-IOV */
2847 if (adapter->vfs_allocated_count) {
06cf2666
AD		 2848 shift = 3;
2849 num_rx_queues = 2;
06cf2666 2850 }
797fd4be
AD		 2851 break;
2852 default:
2853 break;
06cf2666
AD		 2854 }
2855
797fd4be
AD		 2856 /*
2857 * Populate the indirection table 4 entries at a time. To do this
2858 * we are generating the results for n and n+2 and then interleaving
2859 * those with the results with n+1 and n+3.
2860 */
2861 for (j = 0; j < 32; j++) {
2862 /* first pass generates n and n+2 */
2863 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2864 u32 reta = (base & 0x07800780) >> (7 - shift);
2865
2866 /* second pass generates n+1 and n+3 */
2867 base += 0x00010001 * num_rx_queues;
2868 reta |= (base & 0x07800780) << (1 + shift);
2869
2870 wr32(E1000_RETA(j), reta);
06cf2666
AD		 2871 }
2872
2873 /*
2874 * Disable raw packet checksumming so that RSS hash is placed in
2875 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2876 * offloads as they are enabled by default
2877 */
2878 rxcsum = rd32(E1000_RXCSUM);
2879 rxcsum |= E1000_RXCSUM_PCSD;
2880
2881 if (adapter->hw.mac.type >= e1000_82576)
2882 /* Enable Receive Checksum Offload for SCTP */
2883 rxcsum |= E1000_RXCSUM_CRCOFL;
2884
2885 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2886 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 2887
039454a8
AA		 2888 /* Generate RSS hash based on packet types, TCP/UDP
2889 * port numbers and/or IPv4/v6 src and dst addresses
2890 */
f96a8a0b
CW		 2891 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2892 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2893 E1000_MRQC_RSS_FIELD_IPV6 |
2894 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2895 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 2896
039454a8
AA		 2897 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2898 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2899 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2900 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2901
06cf2666
AD		 2902 /* If VMDq is enabled then we set the appropriate mode for that, else
2903 * we default to RSS so that an RSS hash is calculated per packet even
2904 * if we are only using one queue */
2905 if (adapter->vfs_allocated_count) {
2906 if (hw->mac.type > e1000_82575) {
2907 /* Set the default pool for the PF's first queue */
2908 u32 vtctl = rd32(E1000_VT_CTL);
2909 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2910 E1000_VT_CTL_DISABLE_DEF_POOL);
2911 vtctl |= adapter->vfs_allocated_count <<
2912 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2913 wr32(E1000_VT_CTL, vtctl);
2914 }
a99955fc 2915 if (adapter->rss_queues > 1)
f96a8a0b 2916 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 2917 else
f96a8a0b 2918 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 2919 } else {
f96a8a0b
CW		 2920 if (hw->mac.type != e1000_i211)
2921 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 2922 }
2923 igb_vmm_control(adapter);
2924
06cf2666
AD		 2925 wr32(E1000_MRQC, mrqc);
2926}
2927
9d5c8243
AK		 2928/**
2929 * igb_setup_rctl - configure the receive control registers
2930 * @adapter: Board private structure
2931 **/
d7ee5b3a 2932void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2933{
2934 struct e1000_hw *hw = &adapter->hw;
2935 u32 rctl;
9d5c8243
AK		 2936
2937 rctl = rd32(E1000_RCTL);
2938
2939 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2940 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2941
69d728ba 2942 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2943 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2944
87cb7e8c
AK		 2945 /*
2946 * enable stripping of CRC. It's unlikely this will break BMC
2947 * redirection as it did with e1000. Newer features require
2948 * that the HW strips the CRC.
73cd78f1 2949 */
87cb7e8c 2950 rctl |= E1000_RCTL_SECRC;
9d5c8243 2951
559e9c49 2952 /* disable store bad packets and clear size bits. */
ec54d7d6 2953 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2954
6ec43fe6
AD		 2955 /* enable LPE to prevent packets larger than max_frame_size */
2956 rctl |= E1000_RCTL_LPE;
9d5c8243 2957
952f72a8
AD		 2958 /* disable queue 0 to prevent tail write w/o re-config */
2959 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2960
e1739522
AD		 2961 /* Attention!!! For SR-IOV PF driver operations you must enable
2962 * queue drop for all VF and PF queues to prevent head of line blocking
2963 * if an un-trusted VF does not provide descriptors to hardware.
2964 */
2965 if (adapter->vfs_allocated_count) {
e1739522
AD		 2966 /* set all queue drop enable bits */
2967 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2968 }
2969
89eaefb6
BG		 2970 /* This is useful for sniffing bad packets. */
2971 if (adapter->netdev->features & NETIF_F_RXALL) {
2972 /* UPE and MPE will be handled by normal PROMISC logic
2973 * in e1000e_set_rx_mode */
2974 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2975 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2976 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2977
2978 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2979 E1000_RCTL_DPF | /* Allow filtered pause */
2980 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2981 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2982 * and that breaks VLANs.
2983 */
2984 }
2985
9d5c8243
AK		 2986 wr32(E1000_RCTL, rctl);
2987}
2988
7d5753f0
AD		 2989static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2990 int vfn)
2991{
2992 struct e1000_hw *hw = &adapter->hw;
2993 u32 vmolr;
2994
2995 /* if it isn't the PF check to see if VFs are enabled and
2996 * increase the size to support vlan tags */
2997 if (vfn < adapter->vfs_allocated_count &&
2998 adapter->vf_data[vfn].vlans_enabled)
2999 size += VLAN_TAG_SIZE;
3000
3001 vmolr = rd32(E1000_VMOLR(vfn));
3002 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3003 vmolr |= size | E1000_VMOLR_LPE;
3004 wr32(E1000_VMOLR(vfn), vmolr);
3005
3006 return 0;
3007}
3008
e1739522
AD		 3009/**
3010 * igb_rlpml_set - set maximum receive packet size
3011 * @adapter: board private structure
3012 *
3013 * Configure maximum receivable packet size.
3014 **/
3015static void igb_rlpml_set(struct igb_adapter *adapter)
3016{
153285f9 3017 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3018 struct e1000_hw *hw = &adapter->hw;
3019 u16 pf_id = adapter->vfs_allocated_count;
3020
e1739522
AD		 3021 if (pf_id) {
3022 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3023 /*
3024 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3025 * to our max jumbo frame size, in case we need to enable
3026 * jumbo frames on one of the rings later.
3027 * This will not pass over-length frames into the default
3028 * queue because it's gated by the VMOLR.RLPML.
3029 */
7d5753f0 3030 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3031 }
3032
3033 wr32(E1000_RLPML, max_frame_size);
3034}
3035
8151d294
WM		 3036static inline void igb_set_vmolr(struct igb_adapter *adapter,
3037 int vfn, bool aupe)
7d5753f0
AD		 3038{
3039 struct e1000_hw *hw = &adapter->hw;
3040 u32 vmolr;
3041
3042 /*
3043 * This register exists only on 82576 and newer so if we are older then
3044 * we should exit and do nothing
3045 */
3046 if (hw->mac.type < e1000_82576)
3047 return;
3048
3049 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3050 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3051 if (aupe)
3052 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3053 else
3054 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3055
3056 /* clear all bits that might not be set */
3057 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3058
a99955fc 3059 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3060 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3061 /*
3062 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3063 * multicast packets
3064 */
3065 if (vfn <= adapter->vfs_allocated_count)
3066 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3067
3068 wr32(E1000_VMOLR(vfn), vmolr);
3069}
3070
85b430b4
AD		 3071/**
3072 * igb_configure_rx_ring - Configure a receive ring after Reset
3073 * @adapter: board private structure
3074 * @ring: receive ring to be configured
3075 *
3076 * Configure the Rx unit of the MAC after a reset.
3077 **/
d7ee5b3a
AD		 3078void igb_configure_rx_ring(struct igb_adapter *adapter,
3079 struct igb_ring *ring)
85b430b4
AD		 3080{
3081 struct e1000_hw *hw = &adapter->hw;
3082 u64 rdba = ring->dma;
3083 int reg_idx = ring->reg_idx;
a74420e0 3084 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3085
3086 /* disable the queue */
a74420e0 3087 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3088
3089 /* Set DMA base address registers */
3090 wr32(E1000_RDBAL(reg_idx),
3091 rdba & 0x00000000ffffffffULL);
3092 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3093 wr32(E1000_RDLEN(reg_idx),
3094 ring->count * sizeof(union e1000_adv_rx_desc));
3095
3096 /* initialize head and tail */
fce99e34 3097 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3098 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3099 writel(0, ring->tail);
85b430b4 3100
952f72a8 3101 /* set descriptor configuration */
44390ca6 3102 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3103 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3104 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3105 if (hw->mac.type >= e1000_82580)
757b77e2 3106 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3107 /* Only set Drop Enable if we are supporting multiple queues */
3108 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3109 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3110
3111 wr32(E1000_SRRCTL(reg_idx), srrctl);
3112
7d5753f0 3113 /* set filtering for VMDQ pools */
8151d294 3114 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3115
85b430b4
AD		 3116 rxdctl |= IGB_RX_PTHRESH;
3117 rxdctl |= IGB_RX_HTHRESH << 8;
3118 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3119
3120 /* enable receive descriptor fetching */
3121 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3122 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3123}
3124
9d5c8243
AK		 3125/**
3126 * igb_configure_rx - Configure receive Unit after Reset
3127 * @adapter: board private structure
3128 *
3129 * Configure the Rx unit of the MAC after a reset.
3130 **/
3131static void igb_configure_rx(struct igb_adapter *adapter)
3132{
9107584e 3133 int i;
9d5c8243 3134
68d480c4
AD		 3135 /* set UTA to appropriate mode */
3136 igb_set_uta(adapter);
3137
26ad9178
AD		 3138 /* set the correct pool for the PF default MAC address in entry 0 */
3139 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3140 adapter->vfs_allocated_count);
3141
06cf2666
AD		 3142 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3143 * the Base and Length of the Rx Descriptor Ring */
3144 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3145 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3146}
3147
3148/**
3149 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3150 * @tx_ring: Tx descriptor ring for a specific queue
3151 *
3152 * Free all transmit software resources
3153 **/
68fd9910 3154void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3155{
3b644cf6 3156 igb_clean_tx_ring(tx_ring);
9d5c8243 3157
06034649
AD		 3158 vfree(tx_ring->tx_buffer_info);
3159 tx_ring->tx_buffer_info = NULL;
9d5c8243 3160
439705e1
AD		 3161 /* if not set, then don't free */
3162 if (!tx_ring->desc)
3163 return;
3164
59d71989
AD		 3165 dma_free_coherent(tx_ring->dev, tx_ring->size,
3166 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3167
3168 tx_ring->desc = NULL;
3169}
3170
3171/**
3172 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3173 * @adapter: board private structure
3174 *
3175 * Free all transmit software resources
3176 **/
3177static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3178{
3179 int i;
3180
3181 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3182 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3183}
3184
ebe42d16
AD		 3185void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3186 struct igb_tx_buffer *tx_buffer)
3187{
3188 if (tx_buffer->skb) {
3189 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3190 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3191 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3192 dma_unmap_addr(tx_buffer, dma),
3193 dma_unmap_len(tx_buffer, len),
ebe42d16 3194 DMA_TO_DEVICE);
c9f14bf3 3195 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3196 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3197 dma_unmap_addr(tx_buffer, dma),
3198 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3199 DMA_TO_DEVICE);
3200 }
3201 tx_buffer->next_to_watch = NULL;
3202 tx_buffer->skb = NULL;
c9f14bf3 3203 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3204 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3205}
3206
3207/**
3208 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3209 * @tx_ring: ring to be cleaned
3210 **/
3b644cf6 3211static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3212{
06034649 3213 struct igb_tx_buffer *buffer_info;
9d5c8243 3214 unsigned long size;
6ad4edfc 3215 u16 i;
9d5c8243 3216
06034649 3217 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3218 return;
3219 /* Free all the Tx ring sk_buffs */
3220
3221 for (i = 0; i < tx_ring->count; i++) {
06034649 3222 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3223 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3224 }
3225
dad8a3b3
JF		 3226 netdev_tx_reset_queue(txring_txq(tx_ring));
3227
06034649
AD		 3228 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3229 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3230
3231 /* Zero out the descriptor ring */
9d5c8243
AK		 3232 memset(tx_ring->desc, 0, tx_ring->size);
3233
3234 tx_ring->next_to_use = 0;
3235 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3236}
3237
3238/**
3239 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3240 * @adapter: board private structure
3241 **/
3242static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3243{
3244 int i;
3245
3246 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3247 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3248}
3249
3250/**
3251 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3252 * @rx_ring: ring to clean the resources from
3253 *
3254 * Free all receive software resources
3255 **/
68fd9910 3256void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3257{
3b644cf6 3258 igb_clean_rx_ring(rx_ring);
9d5c8243 3259
06034649
AD		 3260 vfree(rx_ring->rx_buffer_info);
3261 rx_ring->rx_buffer_info = NULL;
9d5c8243 3262
439705e1
AD		 3263 /* if not set, then don't free */
3264 if (!rx_ring->desc)
3265 return;
3266
59d71989
AD		 3267 dma_free_coherent(rx_ring->dev, rx_ring->size,
3268 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3269
3270 rx_ring->desc = NULL;
3271}
3272
3273/**
3274 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3275 * @adapter: board private structure
3276 *
3277 * Free all receive software resources
3278 **/
3279static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3280{
3281 int i;
3282
3283 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3284 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3285}
3286
3287/**
3288 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3289 * @rx_ring: ring to free buffers from
3290 **/
3b644cf6 3291static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3292{
9d5c8243 3293 unsigned long size;
c023cd88 3294 u16 i;
9d5c8243 3295
1a1c225b
AD		 3296 if (rx_ring->skb)
3297 dev_kfree_skb(rx_ring->skb);
3298 rx_ring->skb = NULL;
3299
06034649 3300 if (!rx_ring->rx_buffer_info)
9d5c8243 3301 return;
439705e1 3302
9d5c8243
AK		 3303 /* Free all the Rx ring sk_buffs */
3304 for (i = 0; i < rx_ring->count; i++) {
06034649 3305 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3306
cbc8e55f
AD		 3307 if (!buffer_info->page)
3308 continue;
3309
3310 dma_unmap_page(rx_ring->dev,
3311 buffer_info->dma,
3312 PAGE_SIZE,
3313 DMA_FROM_DEVICE);
3314 __free_page(buffer_info->page);
3315
1a1c225b 3316 buffer_info->page = NULL;
9d5c8243
AK		 3317 }
3318
06034649
AD		 3319 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3320 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3321
3322 /* Zero out the descriptor ring */
3323 memset(rx_ring->desc, 0, rx_ring->size);
3324
cbc8e55f 3325 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3326 rx_ring->next_to_clean = 0;
3327 rx_ring->next_to_use = 0;
9d5c8243
AK		 3328}
3329
3330/**
3331 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3332 * @adapter: board private structure
3333 **/
3334static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3335{
3336 int i;
3337
3338 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3339 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3340}
3341
3342/**
3343 * igb_set_mac - Change the Ethernet Address of the NIC
3344 * @netdev: network interface device structure
3345 * @p: pointer to an address structure
3346 *
3347 * Returns 0 on success, negative on failure
3348 **/
3349static int igb_set_mac(struct net_device *netdev, void *p)
3350{
3351 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3352 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3353 struct sockaddr *addr = p;
3354
3355 if (!is_valid_ether_addr(addr->sa_data))
3356 return -EADDRNOTAVAIL;
3357
3358 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3359 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3360
26ad9178
AD		 3361 /* set the correct pool for the new PF MAC address in entry 0 */
3362 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3363 adapter->vfs_allocated_count);
e1739522 3364
9d5c8243
AK		 3365 return 0;
3366}
3367
3368/**
68d480c4 3369 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3370 * @netdev: network interface device structure
3371 *
68d480c4
AD		 3372 * Writes multicast address list to the MTA hash table.
3373 * Returns: -ENOMEM on failure
3374 * 0 on no addresses written
3375 * X on writing X addresses to MTA
9d5c8243 3376 **/
68d480c4 3377static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3378{
3379 struct igb_adapter *adapter = netdev_priv(netdev);
3380 struct e1000_hw *hw = &adapter->hw;
22bedad3 3381 struct netdev_hw_addr *ha;
68d480c4 3382 u8 *mta_list;
9d5c8243
AK		 3383 int i;
3384
4cd24eaf 3385 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3386 /* nothing to program, so clear mc list */
3387 igb_update_mc_addr_list(hw, NULL, 0);
3388 igb_restore_vf_multicasts(adapter);
3389 return 0;
3390 }
9d5c8243 3391
4cd24eaf 3392 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3393 if (!mta_list)
3394 return -ENOMEM;
ff41f8dc 3395
68d480c4 3396 /* The shared function expects a packed array of only addresses. */
48e2f183 3397 i = 0;
22bedad3
JP		 3398 netdev_for_each_mc_addr(ha, netdev)
3399 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3400
68d480c4
AD		 3401 igb_update_mc_addr_list(hw, mta_list, i);
3402 kfree(mta_list);
3403
4cd24eaf 3404 return netdev_mc_count(netdev);
68d480c4
AD		 3405}
3406
3407/**
3408 * igb_write_uc_addr_list - write unicast addresses to RAR table
3409 * @netdev: network interface device structure
3410 *
3411 * Writes unicast address list to the RAR table.
3412 * Returns: -ENOMEM on failure/insufficient address space
3413 * 0 on no addresses written
3414 * X on writing X addresses to the RAR table
3415 **/
3416static int igb_write_uc_addr_list(struct net_device *netdev)
3417{
3418 struct igb_adapter *adapter = netdev_priv(netdev);
3419 struct e1000_hw *hw = &adapter->hw;
3420 unsigned int vfn = adapter->vfs_allocated_count;
3421 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3422 int count = 0;
3423
3424 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3425 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3426 return -ENOMEM;
9d5c8243 3427
32e7bfc4 3428 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3429 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3430
3431 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3432 if (!rar_entries)
3433 break;
26ad9178
AD		 3434 igb_rar_set_qsel(adapter, ha->addr,
3435 rar_entries--,
68d480c4
AD		 3436 vfn);
3437 count++;
ff41f8dc
AD		 3438 }
3439 }
3440 /* write the addresses in reverse order to avoid write combining */
3441 for (; rar_entries > 0 ; rar_entries--) {
3442 wr32(E1000_RAH(rar_entries), 0);
3443 wr32(E1000_RAL(rar_entries), 0);
3444 }
3445 wrfl();
3446
68d480c4
AD		 3447 return count;
3448}
3449
3450/**
3451 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3452 * @netdev: network interface device structure
3453 *
3454 * The set_rx_mode entry point is called whenever the unicast or multicast
3455 * address lists or the network interface flags are updated. This routine is
3456 * responsible for configuring the hardware for proper unicast, multicast,
3457 * promiscuous mode, and all-multi behavior.
3458 **/
3459static void igb_set_rx_mode(struct net_device *netdev)
3460{
3461 struct igb_adapter *adapter = netdev_priv(netdev);
3462 struct e1000_hw *hw = &adapter->hw;
3463 unsigned int vfn = adapter->vfs_allocated_count;
3464 u32 rctl, vmolr = 0;
3465 int count;
3466
3467 /* Check for Promiscuous and All Multicast modes */
3468 rctl = rd32(E1000_RCTL);
3469
3470 /* clear the effected bits */
3471 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3472
3473 if (netdev->flags & IFF_PROMISC) {
3474 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3475 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3476 } else {
3477 if (netdev->flags & IFF_ALLMULTI) {
3478 rctl |= E1000_RCTL_MPE;
3479 vmolr |= E1000_VMOLR_MPME;
3480 } else {
3481 /*
3482 * Write addresses to the MTA, if the attempt fails
25985edc 3483 * then we should just turn on promiscuous mode so
68d480c4
AD		 3484 * that we can at least receive multicast traffic
3485 */
3486 count = igb_write_mc_addr_list(netdev);
3487 if (count < 0) {
3488 rctl |= E1000_RCTL_MPE;
3489 vmolr |= E1000_VMOLR_MPME;
3490 } else if (count) {
3491 vmolr |= E1000_VMOLR_ROMPE;
3492 }
3493 }
3494 /*
3495 * Write addresses to available RAR registers, if there is not
3496 * sufficient space to store all the addresses then enable
25985edc 3497 * unicast promiscuous mode
68d480c4
AD		 3498 */
3499 count = igb_write_uc_addr_list(netdev);
3500 if (count < 0) {
3501 rctl |= E1000_RCTL_UPE;
3502 vmolr |= E1000_VMOLR_ROPE;
3503 }
3504 rctl |= E1000_RCTL_VFE;
28fc06f5 3505 }
68d480c4 3506 wr32(E1000_RCTL, rctl);
28fc06f5 3507
68d480c4
AD		 3508 /*
3509 * In order to support SR-IOV and eventually VMDq it is necessary to set
3510 * the VMOLR to enable the appropriate modes. Without this workaround
3511 * we will have issues with VLAN tag stripping not being done for frames
3512 * that are only arriving because we are the default pool
3513 */
f96a8a0b 3514 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3515 return;
9d5c8243 3516
68d480c4
AD		 3517 vmolr |= rd32(E1000_VMOLR(vfn)) &
3518 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3519 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3520 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3521}
3522
13800469
GR		 3523static void igb_check_wvbr(struct igb_adapter *adapter)
3524{
3525 struct e1000_hw *hw = &adapter->hw;
3526 u32 wvbr = 0;
3527
3528 switch (hw->mac.type) {
3529 case e1000_82576:
3530 case e1000_i350:
3531 if (!(wvbr = rd32(E1000_WVBR)))
3532 return;
3533 break;
3534 default:
3535 break;
3536 }
3537
3538 adapter->wvbr |= wvbr;
3539}
3540
3541#define IGB_STAGGERED_QUEUE_OFFSET 8
3542
3543static void igb_spoof_check(struct igb_adapter *adapter)
3544{
3545 int j;
3546
3547 if (!adapter->wvbr)
3548 return;
3549
3550 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3551 if (adapter->wvbr & (1 << j) ||
3552 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3553 dev_warn(&adapter->pdev->dev,
3554 "Spoof event(s) detected on VF %d\n", j);
3555 adapter->wvbr &=
3556 ~((1 << j) |
3557 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3558 }
3559 }
3560}
3561
9d5c8243
AK		 3562/* Need to wait a few seconds after link up to get diagnostic information from
3563 * the phy */
3564static void igb_update_phy_info(unsigned long data)
3565{
3566 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3567 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3568}
3569
4d6b725e
AD		 3570/**
3571 * igb_has_link - check shared code for link and determine up/down
3572 * @adapter: pointer to driver private info
3573 **/
3145535a 3574bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3575{
3576 struct e1000_hw *hw = &adapter->hw;
3577 bool link_active = false;
3578 s32 ret_val = 0;
3579
3580 /* get_link_status is set on LSC (link status) interrupt or
3581 * rx sequence error interrupt. get_link_status will stay
3582 * false until the e1000_check_for_link establishes link
3583 * for copper adapters ONLY
3584 */
3585 switch (hw->phy.media_type) {
3586 case e1000_media_type_copper:
3587 if (hw->mac.get_link_status) {
3588 ret_val = hw->mac.ops.check_for_link(hw);
3589 link_active = !hw->mac.get_link_status;
3590 } else {
3591 link_active = true;
3592 }
3593 break;
4d6b725e
AD		 3594 case e1000_media_type_internal_serdes:
3595 ret_val = hw->mac.ops.check_for_link(hw);
3596 link_active = hw->mac.serdes_has_link;
3597 break;
3598 default:
3599 case e1000_media_type_unknown:
3600 break;
3601 }
3602
3603 return link_active;
3604}
3605
563988dc
SA		 3606static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3607{
3608 bool ret = false;
3609 u32 ctrl_ext, thstat;
3610
f96a8a0b 3611 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3612 if (hw->mac.type == e1000_i350) {
3613 thstat = rd32(E1000_THSTAT);
3614 ctrl_ext = rd32(E1000_CTRL_EXT);
3615
3616 if ((hw->phy.media_type == e1000_media_type_copper) &&
3617 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3618 ret = !!(thstat & event);
3619 }
3620 }
3621
3622 return ret;
3623}
3624
9d5c8243
AK		 3625/**
3626 * igb_watchdog - Timer Call-back
3627 * @data: pointer to adapter cast into an unsigned long
3628 **/
3629static void igb_watchdog(unsigned long data)
3630{
3631 struct igb_adapter *adapter = (struct igb_adapter *)data;
3632 /* Do the rest outside of interrupt context */
3633 schedule_work(&adapter->watchdog_task);
3634}
3635
3636static void igb_watchdog_task(struct work_struct *work)
3637{
3638 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3639 struct igb_adapter,
3640 watchdog_task);
9d5c8243 3641 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3642 struct net_device *netdev = adapter->netdev;
563988dc 3643 u32 link;
7a6ea550 3644 int i;
9d5c8243 3645
4d6b725e 3646 link = igb_has_link(adapter);
9d5c8243 3647 if (link) {
749ab2cd
YZ		 3648 /* Cancel scheduled suspend requests. */
3649 pm_runtime_resume(netdev->dev.parent);
3650
9d5c8243
AK		 3651 if (!netif_carrier_ok(netdev)) {
3652 u32 ctrl;
330a6d6a
AD		 3653 hw->mac.ops.get_speed_and_duplex(hw,
3654 &adapter->link_speed,
3655 &adapter->link_duplex);
9d5c8243
AK		 3656
3657 ctrl = rd32(E1000_CTRL);
527d47c1 3658 /* Links status message must follow this format */
876d2d6f
JK		 3659 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3660 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3661 netdev->name,
3662 adapter->link_speed,
3663 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3664 "Full" : "Half",
3665 (ctrl & E1000_CTRL_TFCE) &&
3666 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3667 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3668 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3669
563988dc 3670 /* check for thermal sensor event */
876d2d6f
JK		 3671 if (igb_thermal_sensor_event(hw,
3672 E1000_THSTAT_LINK_THROTTLE)) {
3673 netdev_info(netdev, "The network adapter link "
3674 "speed was downshifted because it "
3675 "overheated\n");
7ef5ed1c 3676 }
563988dc 3677
d07f3e37 3678 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3679 adapter->tx_timeout_factor = 1;
3680 switch (adapter->link_speed) {
3681 case SPEED_10:
9d5c8243
AK		 3682 adapter->tx_timeout_factor = 14;
3683 break;
3684 case SPEED_100:
9d5c8243
AK		 3685 /* maybe add some timeout factor ? */
3686 break;
3687 }
3688
3689 netif_carrier_on(netdev);
9d5c8243 3690
4ae196df 3691 igb_ping_all_vfs(adapter);
17dc566c 3692 igb_check_vf_rate_limit(adapter);
4ae196df 3693
4b1a9877 3694 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3695 if (!test_bit(__IGB_DOWN, &adapter->state))
3696 mod_timer(&adapter->phy_info_timer,
3697 round_jiffies(jiffies + 2 * HZ));
3698 }
3699 } else {
3700 if (netif_carrier_ok(netdev)) {
3701 adapter->link_speed = 0;
3702 adapter->link_duplex = 0;
563988dc
SA		 3703
3704 /* check for thermal sensor event */
876d2d6f
JK		 3705 if (igb_thermal_sensor_event(hw,
3706 E1000_THSTAT_PWR_DOWN)) {
3707 netdev_err(netdev, "The network adapter was "
3708 "stopped because it overheated\n");
7ef5ed1c 3709 }
563988dc 3710
527d47c1
AD		 3711 /* Links status message must follow this format */
3712 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3713 netdev->name);
9d5c8243 3714 netif_carrier_off(netdev);
4b1a9877 3715
4ae196df
AD		 3716 igb_ping_all_vfs(adapter);
3717
4b1a9877 3718 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3719 if (!test_bit(__IGB_DOWN, &adapter->state))
3720 mod_timer(&adapter->phy_info_timer,
3721 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3722
3723 pm_schedule_suspend(netdev->dev.parent,
3724 MSEC_PER_SEC * 5);
9d5c8243
AK		 3725 }
3726 }
3727
12dcd86b
ED		 3728 spin_lock(&adapter->stats64_lock);
3729 igb_update_stats(adapter, &adapter->stats64);
3730 spin_unlock(&adapter->stats64_lock);
9d5c8243 3731
dbabb065 3732 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3733 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3734 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3735 /* We've lost link, so the controller stops DMA,
3736 * but we've got queued Tx work that's never going
3737 * to get done, so reset controller to flush Tx.
3738 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3739 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3740 adapter->tx_timeout_count++;
3741 schedule_work(&adapter->reset_task);
3742 /* return immediately since reset is imminent */
3743 return;
3744 }
9d5c8243 3745 }
9d5c8243 3746
dbabb065 3747 /* Force detection of hung controller every watchdog period */
6d095fa8 3748 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3749 }
f7ba205e 3750
9d5c8243 3751 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3752 if (adapter->msix_entries) {
047e0030 3753 u32 eics = 0;
0d1ae7f4
AD		 3754 for (i = 0; i < adapter->num_q_vectors; i++)
3755 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3756 wr32(E1000_EICS, eics);
3757 } else {
3758 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3759 }
9d5c8243 3760
13800469
GR		 3761 igb_spoof_check(adapter);
3762
9d5c8243
AK		 3763 /* Reset the timer */
3764 if (!test_bit(__IGB_DOWN, &adapter->state))
3765 mod_timer(&adapter->watchdog_timer,
3766 round_jiffies(jiffies + 2 * HZ));
3767}
3768
3769enum latency_range {
3770 lowest_latency = 0,
3771 low_latency = 1,
3772 bulk_latency = 2,
3773 latency_invalid = 255
3774};
3775
6eb5a7f1
AD		 3776/**
3777 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3778 *
3779 * Stores a new ITR value based on strictly on packet size. This
3780 * algorithm is less sophisticated than that used in igb_update_itr,
3781 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3782 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3783 * were determined based on theoretical maximum wire speed and testing
3784 * data, in order to minimize response time while increasing bulk
3785 * throughput.
3786 * This functionality is controlled by the InterruptThrottleRate module
3787 * parameter (see igb_param.c)
3788 * NOTE: This function is called only when operating in a multiqueue
3789 * receive environment.
047e0030 3790 * @q_vector: pointer to q_vector
6eb5a7f1 3791 **/
047e0030 3792static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3793{
047e0030 3794 int new_val = q_vector->itr_val;
6eb5a7f1 3795 int avg_wire_size = 0;
047e0030 3796 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3797 unsigned int packets;
9d5c8243 3798
6eb5a7f1
AD		 3799 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3800 * ints/sec - ITR timer value of 120 ticks.
3801 */
3802 if (adapter->link_speed != SPEED_1000) {
0ba82994 3803 new_val = IGB_4K_ITR;
6eb5a7f1 3804 goto set_itr_val;
9d5c8243 3805 }
047e0030 3806
0ba82994
AD		 3807 packets = q_vector->rx.total_packets;
3808 if (packets)
3809 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 3810
0ba82994
AD		 3811 packets = q_vector->tx.total_packets;
3812 if (packets)
3813 avg_wire_size = max_t(u32, avg_wire_size,
3814 q_vector->tx.total_bytes / packets);
047e0030
AD		 3815
3816 /* if avg_wire_size isn't set no work was done */
3817 if (!avg_wire_size)
3818 goto clear_counts;
9d5c8243 3819
6eb5a7f1
AD		 3820 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3821 avg_wire_size += 24;
3822
3823 /* Don't starve jumbo frames */
3824 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3825
6eb5a7f1
AD		 3826 /* Give a little boost to mid-size frames */
3827 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3828 new_val = avg_wire_size / 3;
3829 else
3830 new_val = avg_wire_size / 2;
9d5c8243 3831
0ba82994
AD		 3832 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3833 if (new_val < IGB_20K_ITR &&
3834 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3835 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3836 new_val = IGB_20K_ITR;
abe1c363 3837
6eb5a7f1 3838set_itr_val:
047e0030
AD		 3839 if (new_val != q_vector->itr_val) {
3840 q_vector->itr_val = new_val;
3841 q_vector->set_itr = 1;
9d5c8243 3842 }
6eb5a7f1 3843clear_counts:
0ba82994
AD		 3844 q_vector->rx.total_bytes = 0;
3845 q_vector->rx.total_packets = 0;
3846 q_vector->tx.total_bytes = 0;
3847 q_vector->tx.total_packets = 0;
9d5c8243
AK		 3848}
3849
3850/**
3851 * igb_update_itr - update the dynamic ITR value based on statistics
3852 * Stores a new ITR value based on packets and byte
3853 * counts during the last interrupt. The advantage of per interrupt
3854 * computation is faster updates and more accurate ITR for the current
3855 * traffic pattern. Constants in this function were computed
3856 * based on theoretical maximum wire speed and thresholds were set based
3857 * on testing data as well as attempting to minimize response time
3858 * while increasing bulk throughput.
3859 * this functionality is controlled by the InterruptThrottleRate module
3860 * parameter (see igb_param.c)
3861 * NOTE: These calculations are only valid when operating in a single-
3862 * queue environment.
0ba82994
AD		 3863 * @q_vector: pointer to q_vector
3864 * @ring_container: ring info to update the itr for
9d5c8243 3865 **/
0ba82994
AD		 3866static void igb_update_itr(struct igb_q_vector *q_vector,
3867 struct igb_ring_container *ring_container)
9d5c8243 3868{
0ba82994
AD		 3869 unsigned int packets = ring_container->total_packets;
3870 unsigned int bytes = ring_container->total_bytes;
3871 u8 itrval = ring_container->itr;
9d5c8243 3872
0ba82994 3873 /* no packets, exit with status unchanged */
9d5c8243 3874 if (packets == 0)
0ba82994 3875 return;
9d5c8243 3876
0ba82994 3877 switch (itrval) {
9d5c8243
AK		 3878 case lowest_latency:
3879 /* handle TSO and jumbo frames */
3880 if (bytes/packets > 8000)
0ba82994 3881 itrval = bulk_latency;
9d5c8243 3882 else if ((packets < 5) && (bytes > 512))
0ba82994 3883 itrval = low_latency;
9d5c8243
AK		 3884 break;
3885 case low_latency: /* 50 usec aka 20000 ints/s */
3886 if (bytes > 10000) {
3887 /* this if handles the TSO accounting */
3888 if (bytes/packets > 8000) {
0ba82994 3889 itrval = bulk_latency;
9d5c8243 3890 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 3891 itrval = bulk_latency;
9d5c8243 3892 } else if ((packets > 35)) {
0ba82994 3893 itrval = lowest_latency;
9d5c8243
AK		 3894 }
3895 } else if (bytes/packets > 2000) {
0ba82994 3896 itrval = bulk_latency;
9d5c8243 3897 } else if (packets <= 2 && bytes < 512) {
0ba82994 3898 itrval = lowest_latency;
9d5c8243
AK		 3899 }
3900 break;
3901 case bulk_latency: /* 250 usec aka 4000 ints/s */
3902 if (bytes > 25000) {
3903 if (packets > 35)
0ba82994 3904 itrval = low_latency;
1e5c3d21 3905 } else if (bytes < 1500) {
0ba82994 3906 itrval = low_latency;
9d5c8243
AK		 3907 }
3908 break;
3909 }
3910
0ba82994
AD		 3911 /* clear work counters since we have the values we need */
3912 ring_container->total_bytes = 0;
3913 ring_container->total_packets = 0;
3914
3915 /* write updated itr to ring container */
3916 ring_container->itr = itrval;
9d5c8243
AK		 3917}
3918
0ba82994 3919static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 3920{
0ba82994 3921 struct igb_adapter *adapter = q_vector->adapter;
047e0030 3922 u32 new_itr = q_vector->itr_val;
0ba82994 3923 u8 current_itr = 0;
9d5c8243
AK		 3924
3925 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3926 if (adapter->link_speed != SPEED_1000) {
3927 current_itr = 0;
0ba82994 3928 new_itr = IGB_4K_ITR;
9d5c8243
AK		 3929 goto set_itr_now;
3930 }
3931
0ba82994
AD		 3932 igb_update_itr(q_vector, &q_vector->tx);
3933 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 3934
0ba82994 3935 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 3936
6eb5a7f1 3937 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 3938 if (current_itr == lowest_latency &&
3939 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3940 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 3941 current_itr = low_latency;
3942
9d5c8243
AK		 3943 switch (current_itr) {
3944 /* counts and packets in update_itr are dependent on these numbers */
3945 case lowest_latency:
0ba82994 3946 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 3947 break;
3948 case low_latency:
0ba82994 3949 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 3950 break;
3951 case bulk_latency:
0ba82994 3952 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 3953 break;
3954 default:
3955 break;
3956 }
3957
3958set_itr_now:
047e0030 3959 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3960 /* this attempts to bias the interrupt rate towards Bulk
3961 * by adding intermediate steps when interrupt rate is
3962 * increasing */
047e0030
AD		 3963 new_itr = new_itr > q_vector->itr_val ?
3964 max((new_itr * q_vector->itr_val) /
3965 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 3966 new_itr) :
9d5c8243
AK		 3967 new_itr;
3968 /* Don't write the value here; it resets the adapter's
3969 * internal timer, and causes us to delay far longer than
3970 * we should between interrupts. Instead, we write the ITR
3971 * value at the beginning of the next interrupt so the timing
3972 * ends up being correct.
3973 */
047e0030
AD		 3974 q_vector->itr_val = new_itr;
3975 q_vector->set_itr = 1;
9d5c8243 3976 }
9d5c8243
AK		 3977}
3978
c50b52a0
SH		 3979static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3980 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 3981{
3982 struct e1000_adv_tx_context_desc *context_desc;
3983 u16 i = tx_ring->next_to_use;
3984
3985 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3986
3987 i++;
3988 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3989
3990 /* set bits to identify this as an advanced context descriptor */
3991 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3992
3993 /* For 82575, context index must be unique per ring. */
866cff06 3994 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 3995 mss_l4len_idx |= tx_ring->reg_idx << 4;
3996
3997 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3998 context_desc->seqnum_seed = 0;
3999 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4000 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4001}
4002
7af40ad9
AD		 4003static int igb_tso(struct igb_ring *tx_ring,
4004 struct igb_tx_buffer *first,
4005 u8 *hdr_len)
9d5c8243 4006{
7af40ad9 4007 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4008 u32 vlan_macip_lens, type_tucmd;
4009 u32 mss_l4len_idx, l4len;
4010
ed6aa105
AD		 4011 if (skb->ip_summed != CHECKSUM_PARTIAL)
4012 return 0;
4013
7d13a7d0
AD		 4014 if (!skb_is_gso(skb))
4015 return 0;
9d5c8243
AK		 4016
4017 if (skb_header_cloned(skb)) {
7af40ad9 4018 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4019 if (err)
4020 return err;
4021 }
4022
7d13a7d0
AD		 4023 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4024 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4025
7af40ad9 4026 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4027 struct iphdr *iph = ip_hdr(skb);
4028 iph->tot_len = 0;
4029 iph->check = 0;
4030 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4031 iph->daddr, 0,
4032 IPPROTO_TCP,
4033 0);
7d13a7d0 4034 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4035 first->tx_flags |= IGB_TX_FLAGS_TSO |
4036 IGB_TX_FLAGS_CSUM |
4037 IGB_TX_FLAGS_IPV4;
8e1e8a47 4038 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4039 ipv6_hdr(skb)->payload_len = 0;
4040 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4041 &ipv6_hdr(skb)->daddr,
4042 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4043 first->tx_flags |= IGB_TX_FLAGS_TSO |
4044 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4045 }
4046
7af40ad9 4047 /* compute header lengths */
7d13a7d0
AD		 4048 l4len = tcp_hdrlen(skb);
4049 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4050
7af40ad9
AD		 4051 /* update gso size and bytecount with header size */
4052 first->gso_segs = skb_shinfo(skb)->gso_segs;
4053 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4054
9d5c8243 4055 /* MSS L4LEN IDX */
7d13a7d0
AD		 4056 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4057 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4058
7d13a7d0
AD		 4059 /* VLAN MACLEN IPLEN */
4060 vlan_macip_lens = skb_network_header_len(skb);
4061 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4062 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4063
7d13a7d0 4064 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4065
7d13a7d0 4066 return 1;
9d5c8243
AK		 4067}
4068
7af40ad9 4069static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4070{
7af40ad9 4071 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4072 u32 vlan_macip_lens = 0;
4073 u32 mss_l4len_idx = 0;
4074 u32 type_tucmd = 0;
9d5c8243 4075
7d13a7d0 4076 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4077 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4078 return;
7d13a7d0
AD		 4079 } else {
4080 u8 l4_hdr = 0;
7af40ad9 4081 switch (first->protocol) {
7d13a7d0
AD		 4082 case __constant_htons(ETH_P_IP):
4083 vlan_macip_lens |= skb_network_header_len(skb);
4084 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4085 l4_hdr = ip_hdr(skb)->protocol;
4086 break;
4087 case __constant_htons(ETH_P_IPV6):
4088 vlan_macip_lens |= skb_network_header_len(skb);
4089 l4_hdr = ipv6_hdr(skb)->nexthdr;
4090 break;
4091 default:
4092 if (unlikely(net_ratelimit())) {
4093 dev_warn(tx_ring->dev,
4094 "partial checksum but proto=%x!\n",
7af40ad9 4095 first->protocol);
fa4a7ef3 4096 }
7d13a7d0
AD		 4097 break;
4098 }
fa4a7ef3 4099
7d13a7d0
AD		 4100 switch (l4_hdr) {
4101 case IPPROTO_TCP:
4102 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4103 mss_l4len_idx = tcp_hdrlen(skb) <<
4104 E1000_ADVTXD_L4LEN_SHIFT;
4105 break;
4106 case IPPROTO_SCTP:
4107 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4108 mss_l4len_idx = sizeof(struct sctphdr) <<
4109 E1000_ADVTXD_L4LEN_SHIFT;
4110 break;
4111 case IPPROTO_UDP:
4112 mss_l4len_idx = sizeof(struct udphdr) <<
4113 E1000_ADVTXD_L4LEN_SHIFT;
4114 break;
4115 default:
4116 if (unlikely(net_ratelimit())) {
4117 dev_warn(tx_ring->dev,
4118 "partial checksum but l4 proto=%x!\n",
4119 l4_hdr);
44b0cda3 4120 }
7d13a7d0 4121 break;
9d5c8243 4122 }
7af40ad9
AD		 4123
4124 /* update TX checksum flag */
4125 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4126 }
9d5c8243 4127
7d13a7d0 4128 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4129 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4130
7d13a7d0 4131 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4132}
4133
1d9daf45
AD		 4134#define IGB_SET_FLAG(_input, _flag, _result) \
4135 ((_flag <= _result) ? \
4136 ((u32)(_input & _flag) * (_result / _flag)) : \
4137 ((u32)(_input & _flag) / (_flag / _result)))
4138
4139static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4140{
4141 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4142 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4143 E1000_ADVTXD_DCMD_DEXT |
4144 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4145
4146 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4147 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4148 (E1000_ADVTXD_DCMD_VLE));
4149
4150 /* set segmentation bits for TSO */
4151 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4152 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4153
4154 /* set timestamp bit if present */
1d9daf45
AD		 4155 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4156 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4157
1d9daf45
AD		 4158 /* insert frame checksum */
4159 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4160
4161 return cmd_type;
4162}
4163
7af40ad9
AD		 4164static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4165 union e1000_adv_tx_desc *tx_desc,
4166 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4167{
4168 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4169
1d9daf45
AD		 4170 /* 82575 requires a unique index per ring */
4171 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4172 olinfo_status |= tx_ring->reg_idx << 4;
4173
4174 /* insert L4 checksum */
1d9daf45
AD		 4175 olinfo_status |= IGB_SET_FLAG(tx_flags,
4176 IGB_TX_FLAGS_CSUM,
4177 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4178
1d9daf45
AD		 4179 /* insert IPv4 checksum */
4180 olinfo_status |= IGB_SET_FLAG(tx_flags,
4181 IGB_TX_FLAGS_IPV4,
4182 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4183
7af40ad9 4184 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4185}
4186
ebe42d16
AD		 4187/*
4188 * The largest size we can write to the descriptor is 65535. In order to
4189 * maintain a power of two alignment we have to limit ourselves to 32K.
4190 */
4191#define IGB_MAX_TXD_PWR 15
7af40ad9 4192#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4193
7af40ad9
AD		 4194static void igb_tx_map(struct igb_ring *tx_ring,
4195 struct igb_tx_buffer *first,
ebe42d16 4196 const u8 hdr_len)
9d5c8243 4197{
7af40ad9 4198 struct sk_buff *skb = first->skb;
c9f14bf3 4199 struct igb_tx_buffer *tx_buffer;
ebe42d16 4200 union e1000_adv_tx_desc *tx_desc;
80d0759e 4201 struct skb_frag_struct *frag;
ebe42d16 4202 dma_addr_t dma;
80d0759e 4203 unsigned int data_len, size;
7af40ad9 4204 u32 tx_flags = first->tx_flags;
1d9daf45 4205 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4206 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4207
4208 tx_desc = IGB_TX_DESC(tx_ring, i);
4209
80d0759e
AD		 4210 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4211
4212 size = skb_headlen(skb);
4213 data_len = skb->data_len;
ebe42d16
AD		 4214
4215 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4216
80d0759e
AD		 4217 tx_buffer = first;
4218
4219 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4220 if (dma_mapping_error(tx_ring->dev, dma))
4221 goto dma_error;
4222
4223 /* record length, and DMA address */
4224 dma_unmap_len_set(tx_buffer, len, size);
4225 dma_unmap_addr_set(tx_buffer, dma, dma);
4226
4227 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4228
ebe42d16
AD		 4229 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4230 tx_desc->read.cmd_type_len =
1d9daf45 4231 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4232
4233 i++;
4234 tx_desc++;
4235 if (i == tx_ring->count) {
4236 tx_desc = IGB_TX_DESC(tx_ring, 0);
4237 i = 0;
4238 }
80d0759e 4239 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4240
4241 dma += IGB_MAX_DATA_PER_TXD;
4242 size -= IGB_MAX_DATA_PER_TXD;
4243
ebe42d16
AD		 4244 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4245 }
4246
4247 if (likely(!data_len))
4248 break;
2bbfebe2 4249
1d9daf45 4250 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4251
65689fef 4252 i++;
ebe42d16
AD		 4253 tx_desc++;
4254 if (i == tx_ring->count) {
4255 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4256 i = 0;
ebe42d16 4257 }
80d0759e 4258 tx_desc->read.olinfo_status = 0;
65689fef 4259
9e903e08 4260 size = skb_frag_size(frag);
ebe42d16
AD		 4261 data_len -= size;
4262
4263 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4264 size, DMA_TO_DEVICE);
6366ad33 4265
c9f14bf3 4266 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4267 }
4268
ebe42d16 4269 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4270 cmd_type |= size | IGB_TXD_DCMD;
4271 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4272
80d0759e
AD		 4273 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4274
8542db05
AD		 4275 /* set the timestamp */
4276 first->time_stamp = jiffies;
4277
ebe42d16
AD		 4278 /*
4279 * Force memory writes to complete before letting h/w know there
4280 * are new descriptors to fetch. (Only applicable for weak-ordered
4281 * memory model archs, such as IA-64).
4282 *
4283 * We also need this memory barrier to make certain all of the
4284 * status bits have been updated before next_to_watch is written.
4285 */
4286 wmb();
4287
8542db05 4288 /* set next_to_watch value indicating a packet is present */
ebe42d16 4289 first->next_to_watch = tx_desc;
9d5c8243 4290
ebe42d16
AD		 4291 i++;
4292 if (i == tx_ring->count)
4293 i = 0;
6366ad33 4294
ebe42d16 4295 tx_ring->next_to_use = i;
6366ad33 4296
ebe42d16 4297 writel(i, tx_ring->tail);
6366ad33 4298
ebe42d16
AD		 4299 /* we need this if more than one processor can write to our tail
4300 * at a time, it syncronizes IO on IA64/Altix systems */
4301 mmiowb();
4302
4303 return;
4304
4305dma_error:
4306 dev_err(tx_ring->dev, "TX DMA map failed\n");
4307
4308 /* clear dma mappings for failed tx_buffer_info map */
4309 for (;;) {
c9f14bf3
AD		 4310 tx_buffer = &tx_ring->tx_buffer_info[i];
4311 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4312 if (tx_buffer == first)
ebe42d16 4313 break;
a77ff709
NN		 4314 if (i == 0)
4315 i = tx_ring->count;
6366ad33 4316 i--;
6366ad33
AD		 4317 }
4318
9d5c8243 4319 tx_ring->next_to_use = i;
9d5c8243
AK		 4320}
4321
6ad4edfc 4322static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4323{
e694e964
AD		 4324 struct net_device *netdev = tx_ring->netdev;
4325
661086df 4326 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4327
9d5c8243
AK		 4328 /* Herbert's original patch had:
4329 * smp_mb__after_netif_stop_queue();
4330 * but since that doesn't exist yet, just open code it. */
4331 smp_mb();
4332
4333 /* We need to check again in a case another CPU has just
4334 * made room available. */
c493ea45 4335 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4336 return -EBUSY;
4337
4338 /* A reprieve! */
661086df 4339 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4340
4341 u64_stats_update_begin(&tx_ring->tx_syncp2);
4342 tx_ring->tx_stats.restart_queue2++;
4343 u64_stats_update_end(&tx_ring->tx_syncp2);
4344
9d5c8243
AK		 4345 return 0;
4346}
4347
6ad4edfc 4348static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4349{
c493ea45 4350 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4351 return 0;
e694e964 4352 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4353}
4354
cd392f5c
AD		 4355netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4356 struct igb_ring *tx_ring)
9d5c8243 4357{
1f6e8178 4358 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4359 struct igb_tx_buffer *first;
ebe42d16 4360 int tso;
91d4ee33 4361 u32 tx_flags = 0;
31f6adbb 4362 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4363 u8 hdr_len = 0;
9d5c8243 4364
9d5c8243
AK		 4365 /* need: 1 descriptor per page,
4366 * + 2 desc gap to keep tail from touching head,
4367 * + 1 desc for skb->data,
4368 * + 1 desc for context descriptor,
4369 * otherwise try next time */
e694e964 4370 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4371 /* this is a hard error */
9d5c8243
AK		 4372 return NETDEV_TX_BUSY;
4373 }
33af6bcc 4374
7af40ad9
AD		 4375 /* record the location of the first descriptor for this packet */
4376 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4377 first->skb = skb;
4378 first->bytecount = skb->len;
4379 first->gso_segs = 1;
4380
1f6e8178
MV		 4381 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4382 !(adapter->ptp_tx_skb))) {
2244d07b 4383 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4384 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4385
4386 adapter->ptp_tx_skb = skb_get(skb);
4387 if (adapter->hw.mac.type == e1000_82576)
4388 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4389 }
9d5c8243 4390
eab6d18d 4391 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4392 tx_flags |= IGB_TX_FLAGS_VLAN;
4393 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4394 }
4395
7af40ad9
AD		 4396 /* record initial flags and protocol */
4397 first->tx_flags = tx_flags;
4398 first->protocol = protocol;
cdfd01fc 4399
7af40ad9
AD		 4400 tso = igb_tso(tx_ring, first, &hdr_len);
4401 if (tso < 0)
7d13a7d0 4402 goto out_drop;
7af40ad9
AD		 4403 else if (!tso)
4404 igb_tx_csum(tx_ring, first);
9d5c8243 4405
7af40ad9 4406 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4407
4408 /* Make sure there is space in the ring for the next send. */
e694e964 4409 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4410
9d5c8243 4411 return NETDEV_TX_OK;
7d13a7d0
AD		 4412
4413out_drop:
7af40ad9
AD		 4414 igb_unmap_and_free_tx_resource(tx_ring, first);
4415
7d13a7d0 4416 return NETDEV_TX_OK;
9d5c8243
AK		 4417}
4418
1cc3bd87
AD		 4419static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4420 struct sk_buff *skb)
4421{
4422 unsigned int r_idx = skb->queue_mapping;
4423
4424 if (r_idx >= adapter->num_tx_queues)
4425 r_idx = r_idx % adapter->num_tx_queues;
4426
4427 return adapter->tx_ring[r_idx];
4428}
4429
cd392f5c
AD		 4430static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4431 struct net_device *netdev)
9d5c8243
AK		 4432{
4433 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4434
4435 if (test_bit(__IGB_DOWN, &adapter->state)) {
4436 dev_kfree_skb_any(skb);
4437 return NETDEV_TX_OK;
4438 }
4439
4440 if (skb->len <= 0) {
4441 dev_kfree_skb_any(skb);
4442 return NETDEV_TX_OK;
4443 }
4444
1cc3bd87
AD		 4445 /*
4446 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4447 * in order to meet this minimum size requirement.
4448 */
ea5ceeab
TD		 4449 if (unlikely(skb->len < 17)) {
4450 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4451 return NETDEV_TX_OK;
4452 skb->len = 17;
ea5ceeab 4453 skb_set_tail_pointer(skb, 17);
1cc3bd87 4454 }
9d5c8243 4455
1cc3bd87 4456 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4457}
4458
4459/**
4460 * igb_tx_timeout - Respond to a Tx Hang
4461 * @netdev: network interface device structure
4462 **/
4463static void igb_tx_timeout(struct net_device *netdev)
4464{
4465 struct igb_adapter *adapter = netdev_priv(netdev);
4466 struct e1000_hw *hw = &adapter->hw;
4467
4468 /* Do the reset outside of interrupt context */
4469 adapter->tx_timeout_count++;
f7ba205e 4470
06218a8d 4471 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4472 hw->dev_spec._82575.global_device_reset = true;
4473
9d5c8243 4474 schedule_work(&adapter->reset_task);
265de409
AD		 4475 wr32(E1000_EICS,
4476 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4477}
4478
4479static void igb_reset_task(struct work_struct *work)
4480{
4481 struct igb_adapter *adapter;
4482 adapter = container_of(work, struct igb_adapter, reset_task);
4483
c97ec42a
TI		 4484 igb_dump(adapter);
4485 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4486 igb_reinit_locked(adapter);
4487}
4488
4489/**
12dcd86b 4490 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4491 * @netdev: network interface device structure
12dcd86b 4492 * @stats: rtnl_link_stats64 pointer
9d5c8243 4493 *
9d5c8243 4494 **/
12dcd86b
ED		 4495static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4496 struct rtnl_link_stats64 *stats)
9d5c8243 4497{
12dcd86b
ED		 4498 struct igb_adapter *adapter = netdev_priv(netdev);
4499
4500 spin_lock(&adapter->stats64_lock);
4501 igb_update_stats(adapter, &adapter->stats64);
4502 memcpy(stats, &adapter->stats64, sizeof(*stats));
4503 spin_unlock(&adapter->stats64_lock);
4504
4505 return stats;
9d5c8243
AK		 4506}
4507
4508/**
4509 * igb_change_mtu - Change the Maximum Transfer Unit
4510 * @netdev: network interface device structure
4511 * @new_mtu: new value for maximum frame size
4512 *
4513 * Returns 0 on success, negative on failure
4514 **/
4515static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4516{
4517 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4518 struct pci_dev *pdev = adapter->pdev;
153285f9 4519 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4520
c809d227 4521 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4522 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4523 return -EINVAL;
4524 }
4525
153285f9 4526#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4527 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4528 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4529 return -EINVAL;
4530 }
4531
4532 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4533 msleep(1);
73cd78f1 4534
9d5c8243
AK		 4535 /* igb_down has a dependency on max_frame_size */
4536 adapter->max_frame_size = max_frame;
559e9c49 4537
4c844851
AD		 4538 if (netif_running(netdev))
4539 igb_down(adapter);
9d5c8243 4540
090b1795 4541 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4542 netdev->mtu, new_mtu);
4543 netdev->mtu = new_mtu;
4544
4545 if (netif_running(netdev))
4546 igb_up(adapter);
4547 else
4548 igb_reset(adapter);
4549
4550 clear_bit(__IGB_RESETTING, &adapter->state);
4551
4552 return 0;
4553}
4554
4555/**
4556 * igb_update_stats - Update the board statistics counters
4557 * @adapter: board private structure
4558 **/
4559
12dcd86b
ED		 4560void igb_update_stats(struct igb_adapter *adapter,
4561 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4562{
4563 struct e1000_hw *hw = &adapter->hw;
4564 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4565 u32 reg, mpc;
9d5c8243 4566 u16 phy_tmp;
3f9c0164
AD		 4567 int i;
4568 u64 bytes, packets;
12dcd86b
ED		 4569 unsigned int start;
4570 u64 _bytes, _packets;
9d5c8243
AK		 4571
4572#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4573
4574 /*
4575 * Prevent stats update while adapter is being reset, or if the pci
4576 * connection is down.
4577 */
4578 if (adapter->link_speed == 0)
4579 return;
4580 if (pci_channel_offline(pdev))
4581 return;
4582
3f9c0164
AD		 4583 bytes = 0;
4584 packets = 0;
4585 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4586 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4587 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4588
ae1c07a6
AD		 4589 if (rqdpc) {
4590 ring->rx_stats.drops += rqdpc;
4591 net_stats->rx_fifo_errors += rqdpc;
4592 }
12dcd86b
ED		 4593
4594 do {
4595 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4596 _bytes = ring->rx_stats.bytes;
4597 _packets = ring->rx_stats.packets;
4598 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4599 bytes += _bytes;
4600 packets += _packets;
3f9c0164
AD		 4601 }
4602
128e45eb
AD		 4603 net_stats->rx_bytes = bytes;
4604 net_stats->rx_packets = packets;
3f9c0164
AD		 4605
4606 bytes = 0;
4607 packets = 0;
4608 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4609 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4610 do {
4611 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4612 _bytes = ring->tx_stats.bytes;
4613 _packets = ring->tx_stats.packets;
4614 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4615 bytes += _bytes;
4616 packets += _packets;
3f9c0164 4617 }
128e45eb
AD		 4618 net_stats->tx_bytes = bytes;
4619 net_stats->tx_packets = packets;
3f9c0164
AD		 4620
4621 /* read stats registers */
9d5c8243
AK		 4622 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4623 adapter->stats.gprc += rd32(E1000_GPRC);
4624 adapter->stats.gorc += rd32(E1000_GORCL);
4625 rd32(E1000_GORCH); /* clear GORCL */
4626 adapter->stats.bprc += rd32(E1000_BPRC);
4627 adapter->stats.mprc += rd32(E1000_MPRC);
4628 adapter->stats.roc += rd32(E1000_ROC);
4629
4630 adapter->stats.prc64 += rd32(E1000_PRC64);
4631 adapter->stats.prc127 += rd32(E1000_PRC127);
4632 adapter->stats.prc255 += rd32(E1000_PRC255);
4633 adapter->stats.prc511 += rd32(E1000_PRC511);
4634 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4635 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4636 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4637 adapter->stats.sec += rd32(E1000_SEC);
4638
fa3d9a6d
MW		 4639 mpc = rd32(E1000_MPC);
4640 adapter->stats.mpc += mpc;
4641 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4642 adapter->stats.scc += rd32(E1000_SCC);
4643 adapter->stats.ecol += rd32(E1000_ECOL);
4644 adapter->stats.mcc += rd32(E1000_MCC);
4645 adapter->stats.latecol += rd32(E1000_LATECOL);
4646 adapter->stats.dc += rd32(E1000_DC);
4647 adapter->stats.rlec += rd32(E1000_RLEC);
4648 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4649 adapter->stats.xontxc += rd32(E1000_XONTXC);
4650 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4651 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4652 adapter->stats.fcruc += rd32(E1000_FCRUC);
4653 adapter->stats.gptc += rd32(E1000_GPTC);
4654 adapter->stats.gotc += rd32(E1000_GOTCL);
4655 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4656 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4657 adapter->stats.ruc += rd32(E1000_RUC);
4658 adapter->stats.rfc += rd32(E1000_RFC);
4659 adapter->stats.rjc += rd32(E1000_RJC);
4660 adapter->stats.tor += rd32(E1000_TORH);
4661 adapter->stats.tot += rd32(E1000_TOTH);
4662 adapter->stats.tpr += rd32(E1000_TPR);
4663
4664 adapter->stats.ptc64 += rd32(E1000_PTC64);
4665 adapter->stats.ptc127 += rd32(E1000_PTC127);
4666 adapter->stats.ptc255 += rd32(E1000_PTC255);
4667 adapter->stats.ptc511 += rd32(E1000_PTC511);
4668 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4669 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4670
4671 adapter->stats.mptc += rd32(E1000_MPTC);
4672 adapter->stats.bptc += rd32(E1000_BPTC);
4673
2d0b0f69
NN		 4674 adapter->stats.tpt += rd32(E1000_TPT);
4675 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4676
4677 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4678 /* read internal phy specific stats */
4679 reg = rd32(E1000_CTRL_EXT);
4680 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4681 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4682
4683 /* this stat has invalid values on i210/i211 */
4684 if ((hw->mac.type != e1000_i210) &&
4685 (hw->mac.type != e1000_i211))
4686 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4687 }
4688
9d5c8243
AK		 4689 adapter->stats.tsctc += rd32(E1000_TSCTC);
4690 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4691
4692 adapter->stats.iac += rd32(E1000_IAC);
4693 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4694 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4695 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4696 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4697 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4698 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4699 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4700 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4701
4702 /* Fill out the OS statistics structure */
128e45eb
AD		 4703 net_stats->multicast = adapter->stats.mprc;
4704 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4705
4706 /* Rx Errors */
4707
4708 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4709 * our own version based on RUC and ROC */
128e45eb 4710 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4711 adapter->stats.crcerrs + adapter->stats.algnerrc +
4712 adapter->stats.ruc + adapter->stats.roc +
4713 adapter->stats.cexterr;
128e45eb
AD		 4714 net_stats->rx_length_errors = adapter->stats.ruc +
4715 adapter->stats.roc;
4716 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4717 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4718 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4719
4720 /* Tx Errors */
128e45eb
AD		 4721 net_stats->tx_errors = adapter->stats.ecol +
4722 adapter->stats.latecol;
4723 net_stats->tx_aborted_errors = adapter->stats.ecol;
4724 net_stats->tx_window_errors = adapter->stats.latecol;
4725 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4726
4727 /* Tx Dropped needs to be maintained elsewhere */
4728
4729 /* Phy Stats */
4730 if (hw->phy.media_type == e1000_media_type_copper) {
4731 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4732 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4733 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4734 adapter->phy_stats.idle_errors += phy_tmp;
4735 }
4736 }
4737
4738 /* Management Stats */
4739 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4740 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4741 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4742
4743 /* OS2BMC Stats */
4744 reg = rd32(E1000_MANC);
4745 if (reg & E1000_MANC_EN_BMC2OS) {
4746 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4747 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4748 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4749 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4750 }
9d5c8243
AK		 4751}
4752
9d5c8243
AK		 4753static irqreturn_t igb_msix_other(int irq, void *data)
4754{
047e0030 4755 struct igb_adapter *adapter = data;
9d5c8243 4756 struct e1000_hw *hw = &adapter->hw;
844290e5 4757 u32 icr = rd32(E1000_ICR);
844290e5 4758 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4759
7f081d40
AD		 4760 if (icr & E1000_ICR_DRSTA)
4761 schedule_work(&adapter->reset_task);
4762
047e0030 4763 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4764 /* HW is reporting DMA is out of sync */
4765 adapter->stats.doosync++;
13800469
GR		 4766 /* The DMA Out of Sync is also indication of a spoof event
4767 * in IOV mode. Check the Wrong VM Behavior register to
4768 * see if it is really a spoof event. */
4769 igb_check_wvbr(adapter);
dda0e083 4770 }
eebbbdba 4771
4ae196df
AD		 4772 /* Check for a mailbox event */
4773 if (icr & E1000_ICR_VMMB)
4774 igb_msg_task(adapter);
4775
4776 if (icr & E1000_ICR_LSC) {
4777 hw->mac.get_link_status = 1;
4778 /* guard against interrupt when we're going down */
4779 if (!test_bit(__IGB_DOWN, &adapter->state))
4780 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4781 }
4782
1f6e8178
MV		 4783 if (icr & E1000_ICR_TS) {
4784 u32 tsicr = rd32(E1000_TSICR);
4785
4786 if (tsicr & E1000_TSICR_TXTS) {
4787 /* acknowledge the interrupt */
4788 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4789 /* retrieve hardware timestamp */
4790 schedule_work(&adapter->ptp_tx_work);
4791 }
4792 }
1f6e8178 4793
844290e5 4794 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4795
4796 return IRQ_HANDLED;
4797}
4798
047e0030 4799static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4800{
26b39276 4801 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4802 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4803
047e0030
AD		 4804 if (!q_vector->set_itr)
4805 return;
73cd78f1 4806
047e0030
AD		 4807 if (!itr_val)
4808 itr_val = 0x4;
661086df 4809
26b39276
AD		 4810 if (adapter->hw.mac.type == e1000_82575)
4811 itr_val |= itr_val << 16;
661086df 4812 else
0ba82994 4813 itr_val |= E1000_EITR_CNT_IGNR;
661086df 4814
047e0030
AD		 4815 writel(itr_val, q_vector->itr_register);
4816 q_vector->set_itr = 0;
6eb5a7f1
AD		 4817}
4818
047e0030 4819static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4820{
047e0030 4821 struct igb_q_vector *q_vector = data;
9d5c8243 4822
047e0030
AD		 4823 /* Write the ITR value calculated from the previous interrupt. */
4824 igb_write_itr(q_vector);
9d5c8243 4825
047e0030 4826 napi_schedule(&q_vector->napi);
844290e5 4827
047e0030 4828 return IRQ_HANDLED;
fe4506b6
JC		 4829}
4830
421e02f0 4831#ifdef CONFIG_IGB_DCA
6a05004a
AD		 4832static void igb_update_tx_dca(struct igb_adapter *adapter,
4833 struct igb_ring *tx_ring,
4834 int cpu)
4835{
4836 struct e1000_hw *hw = &adapter->hw;
4837 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4838
4839 if (hw->mac.type != e1000_82575)
4840 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4841
4842 /*
4843 * We can enable relaxed ordering for reads, but not writes when
4844 * DCA is enabled. This is due to a known issue in some chipsets
4845 * which will cause the DCA tag to be cleared.
4846 */
4847 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4848 E1000_DCA_TXCTRL_DATA_RRO_EN |
4849 E1000_DCA_TXCTRL_DESC_DCA_EN;
4850
4851 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4852}
4853
4854static void igb_update_rx_dca(struct igb_adapter *adapter,
4855 struct igb_ring *rx_ring,
4856 int cpu)
4857{
4858 struct e1000_hw *hw = &adapter->hw;
4859 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4860
4861 if (hw->mac.type != e1000_82575)
4862 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4863
4864 /*
4865 * We can enable relaxed ordering for reads, but not writes when
4866 * DCA is enabled. This is due to a known issue in some chipsets
4867 * which will cause the DCA tag to be cleared.
4868 */
4869 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4870 E1000_DCA_RXCTRL_DESC_DCA_EN;
4871
4872 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4873}
4874
047e0030 4875static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4876{
047e0030 4877 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 4878 int cpu = get_cpu();
fe4506b6 4879
047e0030
AD		 4880 if (q_vector->cpu == cpu)
4881 goto out_no_update;
4882
6a05004a
AD		 4883 if (q_vector->tx.ring)
4884 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4885
4886 if (q_vector->rx.ring)
4887 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4888
047e0030
AD		 4889 q_vector->cpu = cpu;
4890out_no_update:
fe4506b6
JC		 4891 put_cpu();
4892}
4893
4894static void igb_setup_dca(struct igb_adapter *adapter)
4895{
7e0e99ef 4896 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4897 int i;
4898
7dfc16fa 4899 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4900 return;
4901
7e0e99ef
AD		 4902 /* Always use CB2 mode, difference is masked in the CB driver. */
4903 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4904
047e0030 4905 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4906 adapter->q_vector[i]->cpu = -1;
4907 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4908 }
4909}
4910
4911static int __igb_notify_dca(struct device *dev, void *data)
4912{
4913 struct net_device *netdev = dev_get_drvdata(dev);
4914 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4915 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4916 struct e1000_hw *hw = &adapter->hw;
4917 unsigned long event = *(unsigned long *)data;
4918
4919 switch (event) {
4920 case DCA_PROVIDER_ADD:
4921 /* if already enabled, don't do it again */
7dfc16fa 4922 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4923 break;
fe4506b6 4924 if (dca_add_requester(dev) == 0) {
bbd98fe4 4925 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4926 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4927 igb_setup_dca(adapter);
4928 break;
4929 }
4930 /* Fall Through since DCA is disabled. */
4931 case DCA_PROVIDER_REMOVE:
7dfc16fa 4932 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4933 /* without this a class_device is left
047e0030 4934 * hanging around in the sysfs model */
fe4506b6 4935 dca_remove_requester(dev);
090b1795 4936 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4937 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4938 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4939 }
4940 break;
4941 }
bbd98fe4 4942
fe4506b6 4943 return 0;
9d5c8243
AK		 4944}
4945
fe4506b6
JC		 4946static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4947 void *p)
4948{
4949 int ret_val;
4950
4951 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4952 __igb_notify_dca);
4953
4954 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4955}
421e02f0 4956#endif /* CONFIG_IGB_DCA */
9d5c8243 4957
0224d663
GR		 4958#ifdef CONFIG_PCI_IOV
4959static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4960{
4961 unsigned char mac_addr[ETH_ALEN];
0224d663 4962
7efd26d0 4963 eth_random_addr(mac_addr);
0224d663
GR		 4964 igb_set_vf_mac(adapter, vf, mac_addr);
4965
f557147c 4966 return 0;
0224d663
GR		 4967}
4968
f557147c 4969static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 4970{
0224d663 4971 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 4972 struct pci_dev *vfdev;
4973 int dev_id;
0224d663
GR		 4974
4975 switch (adapter->hw.mac.type) {
4976 case e1000_82576:
f557147c 4977 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 4978 break;
4979 case e1000_i350:
f557147c 4980 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 4981 break;
4982 default:
f557147c 4983 return false;
0224d663
GR		 4984 }
4985
f557147c
SA		 4986 /* loop through all the VFs to see if we own any that are assigned */
4987 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4988 while (vfdev) {
4989 /* if we don't own it we don't care */
4990 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
4991 /* if it is assigned we cannot release it */
4992 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 4993 return true;
4994 }
f557147c
SA		 4995
4996 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 4997 }
f557147c 4998
0224d663
GR		 4999 return false;
5000}
5001
5002#endif
4ae196df
AD		 5003static void igb_ping_all_vfs(struct igb_adapter *adapter)
5004{
5005 struct e1000_hw *hw = &adapter->hw;
5006 u32 ping;
5007 int i;
5008
5009 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5010 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5011 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5012 ping |= E1000_VT_MSGTYPE_CTS;
5013 igb_write_mbx(hw, &ping, 1, i);
5014 }
5015}
5016
7d5753f0
AD		 5017static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5018{
5019 struct e1000_hw *hw = &adapter->hw;
5020 u32 vmolr = rd32(E1000_VMOLR(vf));
5021 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5022
d85b9004 5023 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5024 IGB_VF_FLAG_MULTI_PROMISC);
5025 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5026
5027 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5028 vmolr |= E1000_VMOLR_MPME;
d85b9004 5029 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5030 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5031 } else {
5032 /*
5033 * if we have hashes and we are clearing a multicast promisc
5034 * flag we need to write the hashes to the MTA as this step
5035 * was previously skipped
5036 */
5037 if (vf_data->num_vf_mc_hashes > 30) {
5038 vmolr |= E1000_VMOLR_MPME;
5039 } else if (vf_data->num_vf_mc_hashes) {
5040 int j;
5041 vmolr |= E1000_VMOLR_ROMPE;
5042 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5043 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5044 }
5045 }
5046
5047 wr32(E1000_VMOLR(vf), vmolr);
5048
5049 /* there are flags left unprocessed, likely not supported */
5050 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5051 return -EINVAL;
5052
5053 return 0;
5054
5055}
5056
4ae196df
AD		 5057static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5058 u32 *msgbuf, u32 vf)
5059{
5060 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5061 u16 *hash_list = (u16 *)&msgbuf[1];
5062 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5063 int i;
5064
7d5753f0 5065 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5066 * to this VF for later use to restore when the PF multi cast
5067 * list changes
5068 */
5069 vf_data->num_vf_mc_hashes = n;
5070
7d5753f0
AD		 5071 /* only up to 30 hash values supported */
5072 if (n > 30)
5073 n = 30;
5074
5075 /* store the hashes for later use */
4ae196df 5076 for (i = 0; i < n; i++)
a419aef8 5077 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5078
5079 /* Flush and reset the mta with the new values */
ff41f8dc 5080 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5081
5082 return 0;
5083}
5084
5085static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5086{
5087 struct e1000_hw *hw = &adapter->hw;
5088 struct vf_data_storage *vf_data;
5089 int i, j;
5090
5091 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5092 u32 vmolr = rd32(E1000_VMOLR(i));
5093 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5094
4ae196df 5095 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5096
5097 if ((vf_data->num_vf_mc_hashes > 30) ||
5098 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5099 vmolr |= E1000_VMOLR_MPME;
5100 } else if (vf_data->num_vf_mc_hashes) {
5101 vmolr |= E1000_VMOLR_ROMPE;
5102 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5103 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5104 }
5105 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5106 }
5107}
5108
5109static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5110{
5111 struct e1000_hw *hw = &adapter->hw;
5112 u32 pool_mask, reg, vid;
5113 int i;
5114
5115 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5116
5117 /* Find the vlan filter for this id */
5118 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5119 reg = rd32(E1000_VLVF(i));
5120
5121 /* remove the vf from the pool */
5122 reg &= ~pool_mask;
5123
5124 /* if pool is empty then remove entry from vfta */
5125 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5126 (reg & E1000_VLVF_VLANID_ENABLE)) {
5127 reg = 0;
5128 vid = reg & E1000_VLVF_VLANID_MASK;
5129 igb_vfta_set(hw, vid, false);
5130 }
5131
5132 wr32(E1000_VLVF(i), reg);
5133 }
ae641bdc
AD		 5134
5135 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5136}
5137
5138static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5139{
5140 struct e1000_hw *hw = &adapter->hw;
5141 u32 reg, i;
5142
51466239
AD		 5143 /* The vlvf table only exists on 82576 hardware and newer */
5144 if (hw->mac.type < e1000_82576)
5145 return -1;
5146
5147 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5148 if (!adapter->vfs_allocated_count)
5149 return -1;
5150
5151 /* Find the vlan filter for this id */
5152 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5153 reg = rd32(E1000_VLVF(i));
5154 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5155 vid == (reg & E1000_VLVF_VLANID_MASK))
5156 break;
5157 }
5158
5159 if (add) {
5160 if (i == E1000_VLVF_ARRAY_SIZE) {
5161 /* Did not find a matching VLAN ID entry that was
5162 * enabled. Search for a free filter entry, i.e.
5163 * one without the enable bit set
5164 */
5165 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5166 reg = rd32(E1000_VLVF(i));
5167 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5168 break;
5169 }
5170 }
5171 if (i < E1000_VLVF_ARRAY_SIZE) {
5172 /* Found an enabled/available entry */
5173 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5174
5175 /* if !enabled we need to set this up in vfta */
5176 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5177 /* add VID to filter table */
5178 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5179 reg |= E1000_VLVF_VLANID_ENABLE;
5180 }
cad6d05f
AD		 5181 reg &= ~E1000_VLVF_VLANID_MASK;
5182 reg |= vid;
4ae196df 5183 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5184
5185 /* do not modify RLPML for PF devices */
5186 if (vf >= adapter->vfs_allocated_count)
5187 return 0;
5188
5189 if (!adapter->vf_data[vf].vlans_enabled) {
5190 u32 size;
5191 reg = rd32(E1000_VMOLR(vf));
5192 size = reg & E1000_VMOLR_RLPML_MASK;
5193 size += 4;
5194 reg &= ~E1000_VMOLR_RLPML_MASK;
5195 reg |= size;
5196 wr32(E1000_VMOLR(vf), reg);
5197 }
ae641bdc 5198
51466239 5199 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5200 }
5201 } else {
5202 if (i < E1000_VLVF_ARRAY_SIZE) {
5203 /* remove vf from the pool */
5204 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5205 /* if pool is empty then remove entry from vfta */
5206 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5207 reg = 0;
5208 igb_vfta_set(hw, vid, false);
5209 }
5210 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5211
5212 /* do not modify RLPML for PF devices */
5213 if (vf >= adapter->vfs_allocated_count)
5214 return 0;
5215
5216 adapter->vf_data[vf].vlans_enabled--;
5217 if (!adapter->vf_data[vf].vlans_enabled) {
5218 u32 size;
5219 reg = rd32(E1000_VMOLR(vf));
5220 size = reg & E1000_VMOLR_RLPML_MASK;
5221 size -= 4;
5222 reg &= ~E1000_VMOLR_RLPML_MASK;
5223 reg |= size;
5224 wr32(E1000_VMOLR(vf), reg);
5225 }
4ae196df
AD		 5226 }
5227 }
8151d294
WM		 5228 return 0;
5229}
5230
5231static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5232{
5233 struct e1000_hw *hw = &adapter->hw;
5234
5235 if (vid)
5236 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5237 else
5238 wr32(E1000_VMVIR(vf), 0);
5239}
5240
5241static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5242 int vf, u16 vlan, u8 qos)
5243{
5244 int err = 0;
5245 struct igb_adapter *adapter = netdev_priv(netdev);
5246
5247 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5248 return -EINVAL;
5249 if (vlan || qos) {
5250 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5251 if (err)
5252 goto out;
5253 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5254 igb_set_vmolr(adapter, vf, !vlan);
5255 adapter->vf_data[vf].pf_vlan = vlan;
5256 adapter->vf_data[vf].pf_qos = qos;
5257 dev_info(&adapter->pdev->dev,
5258 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5259 if (test_bit(__IGB_DOWN, &adapter->state)) {
5260 dev_warn(&adapter->pdev->dev,
5261 "The VF VLAN has been set,"
5262 " but the PF device is not up.\n");
5263 dev_warn(&adapter->pdev->dev,
5264 "Bring the PF device up before"
5265 " attempting to use the VF device.\n");
5266 }
5267 } else {
5268 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5269 false, vf);
5270 igb_set_vmvir(adapter, vlan, vf);
5271 igb_set_vmolr(adapter, vf, true);
5272 adapter->vf_data[vf].pf_vlan = 0;
5273 adapter->vf_data[vf].pf_qos = 0;
5274 }
5275out:
5276 return err;
4ae196df
AD		 5277}
5278
5279static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5280{
5281 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5282 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5283
5284 return igb_vlvf_set(adapter, vid, add, vf);
5285}
5286
f2ca0dbe 5287static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5288{
8fa7e0f7
GR		 5289 /* clear flags - except flag that indicates PF has set the MAC */
5290 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5291 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5292
5293 /* reset offloads to defaults */
8151d294 5294 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5295
5296 /* reset vlans for device */
5297 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5298 if (adapter->vf_data[vf].pf_vlan)
5299 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5300 adapter->vf_data[vf].pf_vlan,
5301 adapter->vf_data[vf].pf_qos);
5302 else
5303 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5304
5305 /* reset multicast table array for vf */
5306 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5307
5308 /* Flush and reset the mta with the new values */
ff41f8dc 5309 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5310}
5311
f2ca0dbe
AD		 5312static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5313{
5314 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5315
5316 /* generate a new mac address as we were hotplug removed/added */
8151d294 5317 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5318 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5319
5320 /* process remaining reset events */
5321 igb_vf_reset(adapter, vf);
5322}
5323
5324static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5325{
5326 struct e1000_hw *hw = &adapter->hw;
5327 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5328 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5329 u32 reg, msgbuf[3];
5330 u8 *addr = (u8 *)(&msgbuf[1]);
5331
5332 /* process all the same items cleared in a function level reset */
f2ca0dbe 5333 igb_vf_reset(adapter, vf);
4ae196df
AD		 5334
5335 /* set vf mac address */
26ad9178 5336 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5337
5338 /* enable transmit and receive for vf */
5339 reg = rd32(E1000_VFTE);
5340 wr32(E1000_VFTE, reg | (1 << vf));
5341 reg = rd32(E1000_VFRE);
5342 wr32(E1000_VFRE, reg | (1 << vf));
5343
8fa7e0f7 5344 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5345
5346 /* reply to reset with ack and vf mac address */
5347 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5348 memcpy(addr, vf_mac, 6);
5349 igb_write_mbx(hw, msgbuf, 3, vf);
5350}
5351
5352static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5353{
de42edde
GR		 5354 /*
5355 * The VF MAC Address is stored in a packed array of bytes
5356 * starting at the second 32 bit word of the msg array
5357 */
f2ca0dbe
AD		 5358 unsigned char *addr = (char *)&msg[1];
5359 int err = -1;
4ae196df 5360
f2ca0dbe
AD		 5361 if (is_valid_ether_addr(addr))
5362 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5363
f2ca0dbe 5364 return err;
4ae196df
AD		 5365}
5366
5367static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5368{
5369 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5370 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5371 u32 msg = E1000_VT_MSGTYPE_NACK;
5372
5373 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5374 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5375 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5376 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5377 vf_data->last_nack = jiffies;
4ae196df
AD		 5378 }
5379}
5380
f2ca0dbe 5381static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5382{
f2ca0dbe
AD		 5383 struct pci_dev *pdev = adapter->pdev;
5384 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5385 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5386 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5387 s32 retval;
5388
f2ca0dbe 5389 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5390
fef45f4c
AD		 5391 if (retval) {
5392 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5393 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5394 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5395 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5396 return;
5397 goto out;
5398 }
4ae196df
AD		 5399
5400 /* this is a message we already processed, do nothing */
5401 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5402 return;
4ae196df
AD		 5403
5404 /*
5405 * until the vf completes a reset it should not be
5406 * allowed to start any configuration.
5407 */
5408
5409 if (msgbuf[0] == E1000_VF_RESET) {
5410 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5411 return;
4ae196df
AD		 5412 }
5413
f2ca0dbe 5414 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5415 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5416 return;
5417 retval = -1;
5418 goto out;
4ae196df
AD		 5419 }
5420
5421 switch ((msgbuf[0] & 0xFFFF)) {
5422 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5423 retval = -EINVAL;
5424 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5425 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5426 else
5427 dev_warn(&pdev->dev,
5428 "VF %d attempted to override administratively "
5429 "set MAC address\nReload the VF driver to "
5430 "resume operations\n", vf);
4ae196df 5431 break;
7d5753f0
AD		 5432 case E1000_VF_SET_PROMISC:
5433 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5434 break;
4ae196df
AD		 5435 case E1000_VF_SET_MULTICAST:
5436 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5437 break;
5438 case E1000_VF_SET_LPE:
5439 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5440 break;
5441 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5442 retval = -1;
5443 if (vf_data->pf_vlan)
5444 dev_warn(&pdev->dev,
5445 "VF %d attempted to override administratively "
5446 "set VLAN tag\nReload the VF driver to "
5447 "resume operations\n", vf);
8151d294
WM		 5448 else
5449 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5450 break;
5451 default:
090b1795 5452 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5453 retval = -1;
5454 break;
5455 }
5456
fef45f4c
AD		 5457 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5458out:
4ae196df
AD		 5459 /* notify the VF of the results of what it sent us */
5460 if (retval)
5461 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5462 else
5463 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5464
4ae196df 5465 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5466}
4ae196df 5467
f2ca0dbe
AD		 5468static void igb_msg_task(struct igb_adapter *adapter)
5469{
5470 struct e1000_hw *hw = &adapter->hw;
5471 u32 vf;
5472
5473 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5474 /* process any reset requests */
5475 if (!igb_check_for_rst(hw, vf))
5476 igb_vf_reset_event(adapter, vf);
5477
5478 /* process any messages pending */
5479 if (!igb_check_for_msg(hw, vf))
5480 igb_rcv_msg_from_vf(adapter, vf);
5481
5482 /* process any acks */
5483 if (!igb_check_for_ack(hw, vf))
5484 igb_rcv_ack_from_vf(adapter, vf);
5485 }
4ae196df
AD		 5486}
5487
68d480c4
AD		 5488/**
5489 * igb_set_uta - Set unicast filter table address
5490 * @adapter: board private structure
5491 *
5492 * The unicast table address is a register array of 32-bit registers.
5493 * The table is meant to be used in a way similar to how the MTA is used
5494 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5495 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5496 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5497 **/
5498static void igb_set_uta(struct igb_adapter *adapter)
5499{
5500 struct e1000_hw *hw = &adapter->hw;
5501 int i;
5502
5503 /* The UTA table only exists on 82576 hardware and newer */
5504 if (hw->mac.type < e1000_82576)
5505 return;
5506
5507 /* we only need to do this if VMDq is enabled */
5508 if (!adapter->vfs_allocated_count)
5509 return;
5510
5511 for (i = 0; i < hw->mac.uta_reg_count; i++)
5512 array_wr32(E1000_UTA, i, ~0);
5513}
5514
9d5c8243
AK		 5515/**
5516 * igb_intr_msi - Interrupt Handler
5517 * @irq: interrupt number
5518 * @data: pointer to a network interface device structure
5519 **/
5520static irqreturn_t igb_intr_msi(int irq, void *data)
5521{
047e0030
AD		 5522 struct igb_adapter *adapter = data;
5523 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5524 struct e1000_hw *hw = &adapter->hw;
5525 /* read ICR disables interrupts using IAM */
5526 u32 icr = rd32(E1000_ICR);
5527
047e0030 5528 igb_write_itr(q_vector);
9d5c8243 5529
7f081d40
AD		 5530 if (icr & E1000_ICR_DRSTA)
5531 schedule_work(&adapter->reset_task);
5532
047e0030 5533 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5534 /* HW is reporting DMA is out of sync */
5535 adapter->stats.doosync++;
5536 }
5537
9d5c8243
AK		 5538 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5539 hw->mac.get_link_status = 1;
5540 if (!test_bit(__IGB_DOWN, &adapter->state))
5541 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5542 }
5543
1f6e8178
MV		 5544 if (icr & E1000_ICR_TS) {
5545 u32 tsicr = rd32(E1000_TSICR);
5546
5547 if (tsicr & E1000_TSICR_TXTS) {
5548 /* acknowledge the interrupt */
5549 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5550 /* retrieve hardware timestamp */
5551 schedule_work(&adapter->ptp_tx_work);
5552 }
5553 }
1f6e8178 5554
047e0030 5555 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5556
5557 return IRQ_HANDLED;
5558}
5559
5560/**
4a3c6433 5561 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5562 * @irq: interrupt number
5563 * @data: pointer to a network interface device structure
5564 **/
5565static irqreturn_t igb_intr(int irq, void *data)
5566{
047e0030
AD		 5567 struct igb_adapter *adapter = data;
5568 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5569 struct e1000_hw *hw = &adapter->hw;
5570 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5571 * need for the IMC write */
5572 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5573
5574 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5575 * not set, then the adapter didn't send an interrupt */
5576 if (!(icr & E1000_ICR_INT_ASSERTED))
5577 return IRQ_NONE;
5578
0ba82994
AD		 5579 igb_write_itr(q_vector);
5580
7f081d40
AD		 5581 if (icr & E1000_ICR_DRSTA)
5582 schedule_work(&adapter->reset_task);
5583
047e0030 5584 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5585 /* HW is reporting DMA is out of sync */
5586 adapter->stats.doosync++;
5587 }
5588
9d5c8243
AK		 5589 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5590 hw->mac.get_link_status = 1;
5591 /* guard against interrupt when we're going down */
5592 if (!test_bit(__IGB_DOWN, &adapter->state))
5593 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5594 }
5595
1f6e8178
MV		 5596 if (icr & E1000_ICR_TS) {
5597 u32 tsicr = rd32(E1000_TSICR);
5598
5599 if (tsicr & E1000_TSICR_TXTS) {
5600 /* acknowledge the interrupt */
5601 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5602 /* retrieve hardware timestamp */
5603 schedule_work(&adapter->ptp_tx_work);
5604 }
5605 }
1f6e8178 5606
047e0030 5607 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5608
5609 return IRQ_HANDLED;
5610}
5611
c50b52a0 5612static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5613{
047e0030 5614 struct igb_adapter *adapter = q_vector->adapter;
46544258 5615 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5616
0ba82994
AD		 5617 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5618 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5619 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5620 igb_set_itr(q_vector);
46544258 5621 else
047e0030 5622 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5623 }
5624
46544258
AD		 5625 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5626 if (adapter->msix_entries)
047e0030 5627 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5628 else
5629 igb_irq_enable(adapter);
5630 }
9d5c8243
AK		 5631}
5632
46544258
AD		 5633/**
5634 * igb_poll - NAPI Rx polling callback
5635 * @napi: napi polling structure
5636 * @budget: count of how many packets we should handle
5637 **/
5638static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5639{
047e0030
AD		 5640 struct igb_q_vector *q_vector = container_of(napi,
5641 struct igb_q_vector,
5642 napi);
16eb8815 5643 bool clean_complete = true;
9d5c8243 5644
421e02f0 5645#ifdef CONFIG_IGB_DCA
047e0030
AD		 5646 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5647 igb_update_dca(q_vector);
fe4506b6 5648#endif
0ba82994 5649 if (q_vector->tx.ring)
13fde97a 5650 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5651
0ba82994 5652 if (q_vector->rx.ring)
cd392f5c 5653 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5654
16eb8815
AD		 5655 /* If all work not completed, return budget and keep polling */
5656 if (!clean_complete)
5657 return budget;
46544258 5658
9d5c8243 5659 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5660 napi_complete(napi);
5661 igb_ring_irq_enable(q_vector);
9d5c8243 5662
16eb8815 5663 return 0;
9d5c8243 5664}
6d8126f9 5665
9d5c8243
AK		 5666/**
5667 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5668 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5669 *
9d5c8243
AK		 5670 * returns true if ring is completely cleaned
5671 **/
047e0030 5672static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5673{
047e0030 5674 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5675 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5676 struct igb_tx_buffer *tx_buffer;
f4128785 5677 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5678 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5679 unsigned int budget = q_vector->tx.work_limit;
8542db05 5680 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5681
13fde97a
AD		 5682 if (test_bit(__IGB_DOWN, &adapter->state))
5683 return true;
0e014cb1 5684
06034649 5685 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5686 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5687 i -= tx_ring->count;
9d5c8243 5688
f4128785
AD		 5689 do {
5690 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5691
5692 /* if next_to_watch is not set then there is no work pending */
5693 if (!eop_desc)
5694 break;
13fde97a 5695
f4128785
AD		 5696 /* prevent any other reads prior to eop_desc */
5697 rmb();
5698
13fde97a
AD		 5699 /* if DD is not set pending work has not been completed */
5700 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5701 break;
5702
8542db05
AD		 5703 /* clear next_to_watch to prevent false hangs */
5704 tx_buffer->next_to_watch = NULL;
9d5c8243 5705
ebe42d16
AD		 5706 /* update the statistics for this packet */
5707 total_bytes += tx_buffer->bytecount;
5708 total_packets += tx_buffer->gso_segs;
13fde97a 5709
ebe42d16
AD		 5710 /* free the skb */
5711 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5712
ebe42d16
AD		 5713 /* unmap skb header data */
5714 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5715 dma_unmap_addr(tx_buffer, dma),
5716 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5717 DMA_TO_DEVICE);
5718
c9f14bf3
AD		 5719 /* clear tx_buffer data */
5720 tx_buffer->skb = NULL;
5721 dma_unmap_len_set(tx_buffer, len, 0);
5722
ebe42d16
AD		 5723 /* clear last DMA location and unmap remaining buffers */
5724 while (tx_desc != eop_desc) {
13fde97a
AD		 5725 tx_buffer++;
5726 tx_desc++;
9d5c8243 5727 i++;
8542db05
AD		 5728 if (unlikely(!i)) {
5729 i -= tx_ring->count;
06034649 5730 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5731 tx_desc = IGB_TX_DESC(tx_ring, 0);
5732 }
ebe42d16
AD		 5733
5734 /* unmap any remaining paged data */
c9f14bf3 5735 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5736 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5737 dma_unmap_addr(tx_buffer, dma),
5738 dma_unmap_len(tx_buffer, len),
ebe42d16 5739 DMA_TO_DEVICE);
c9f14bf3 5740 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5741 }
5742 }
5743
ebe42d16
AD		 5744 /* move us one more past the eop_desc for start of next pkt */
5745 tx_buffer++;
5746 tx_desc++;
5747 i++;
5748 if (unlikely(!i)) {
5749 i -= tx_ring->count;
5750 tx_buffer = tx_ring->tx_buffer_info;
5751 tx_desc = IGB_TX_DESC(tx_ring, 0);
5752 }
f4128785
AD		 5753
5754 /* issue prefetch for next Tx descriptor */
5755 prefetch(tx_desc);
5756
5757 /* update budget accounting */
5758 budget--;
5759 } while (likely(budget));
0e014cb1 5760
bdbc0631
ED		 5761 netdev_tx_completed_queue(txring_txq(tx_ring),
5762 total_packets, total_bytes);
8542db05 5763 i += tx_ring->count;
9d5c8243 5764 tx_ring->next_to_clean = i;
13fde97a
AD		 5765 u64_stats_update_begin(&tx_ring->tx_syncp);
5766 tx_ring->tx_stats.bytes += total_bytes;
5767 tx_ring->tx_stats.packets += total_packets;
5768 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5769 q_vector->tx.total_bytes += total_bytes;
5770 q_vector->tx.total_packets += total_packets;
9d5c8243 5771
6d095fa8 5772 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5773 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5774
9d5c8243
AK		 5775 /* Detect a transmit hang in hardware, this serializes the
5776 * check with the clearing of time_stamp and movement of i */
6d095fa8 5777 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 5778 if (tx_buffer->next_to_watch &&
8542db05 5779 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5780 (adapter->tx_timeout_factor * HZ)) &&
5781 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5782
9d5c8243 5783 /* detected Tx unit hang */
59d71989 5784 dev_err(tx_ring->dev,
9d5c8243 5785 "Detected Tx Unit Hang\n"
2d064c06 5786 " Tx Queue <%d>\n"
9d5c8243
AK		 5787 " TDH <%x>\n"
5788 " TDT <%x>\n"
5789 " next_to_use <%x>\n"
5790 " next_to_clean <%x>\n"
9d5c8243
AK		 5791 "buffer_info[next_to_clean]\n"
5792 " time_stamp <%lx>\n"
8542db05 5793 " next_to_watch <%p>\n"
9d5c8243
AK		 5794 " jiffies <%lx>\n"
5795 " desc.status <%x>\n",
2d064c06 5796 tx_ring->queue_index,
238ac817 5797 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5798 readl(tx_ring->tail),
9d5c8243
AK		 5799 tx_ring->next_to_use,
5800 tx_ring->next_to_clean,
8542db05 5801 tx_buffer->time_stamp,
f4128785 5802 tx_buffer->next_to_watch,
9d5c8243 5803 jiffies,
f4128785 5804 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 5805 netif_stop_subqueue(tx_ring->netdev,
5806 tx_ring->queue_index);
5807
5808 /* we are about to reset, no point in enabling stuff */
5809 return true;
9d5c8243
AK		 5810 }
5811 }
13fde97a
AD		 5812
5813 if (unlikely(total_packets &&
5814 netif_carrier_ok(tx_ring->netdev) &&
5815 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5816 /* Make sure that anybody stopping the queue after this
5817 * sees the new next_to_clean.
5818 */
5819 smp_mb();
5820 if (__netif_subqueue_stopped(tx_ring->netdev,
5821 tx_ring->queue_index) &&
5822 !(test_bit(__IGB_DOWN, &adapter->state))) {
5823 netif_wake_subqueue(tx_ring->netdev,
5824 tx_ring->queue_index);
5825
5826 u64_stats_update_begin(&tx_ring->tx_syncp);
5827 tx_ring->tx_stats.restart_queue++;
5828 u64_stats_update_end(&tx_ring->tx_syncp);
5829 }
5830 }
5831
5832 return !!budget;
9d5c8243
AK		 5833}
5834
cbc8e55f
AD		 5835/**
5836 * igb_reuse_rx_page - page flip buffer and store it back on the ring
5837 * @rx_ring: rx descriptor ring to store buffers on
5838 * @old_buff: donor buffer to have page reused
5839 *
5840 * Synchronizes page for reuse by the adapter
5841 **/
5842static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5843 struct igb_rx_buffer *old_buff)
5844{
5845 struct igb_rx_buffer *new_buff;
5846 u16 nta = rx_ring->next_to_alloc;
5847
5848 new_buff = &rx_ring->rx_buffer_info[nta];
5849
5850 /* update, and store next to alloc */
5851 nta++;
5852 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5853
5854 /* transfer page from old buffer to new buffer */
5855 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5856
5857 /* sync the buffer for use by the device */
5858 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5859 old_buff->page_offset,
de78d1f9 5860 IGB_RX_BUFSZ,
cbc8e55f
AD		 5861 DMA_FROM_DEVICE);
5862}
5863
5864/**
5865 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5866 * @rx_ring: rx descriptor ring to transact packets on
5867 * @rx_buffer: buffer containing page to add
5868 * @rx_desc: descriptor containing length of buffer written by hardware
5869 * @skb: sk_buff to place the data into
5870 *
5871 * This function will add the data contained in rx_buffer->page to the skb.
5872 * This is done either through a direct copy if the data in the buffer is
5873 * less than the skb header size, otherwise it will just attach the page as
5874 * a frag to the skb.
5875 *
5876 * The function will then update the page offset if necessary and return
5877 * true if the buffer can be reused by the adapter.
5878 **/
5879static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5880 struct igb_rx_buffer *rx_buffer,
5881 union e1000_adv_rx_desc *rx_desc,
5882 struct sk_buff *skb)
5883{
5884 struct page *page = rx_buffer->page;
5885 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5886
5887 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5888 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5889
cbc8e55f
AD		 5890 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5891 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5892 va += IGB_TS_HDR_LEN;
5893 size -= IGB_TS_HDR_LEN;
5894 }
5895
cbc8e55f
AD		 5896 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5897
5898 /* we can reuse buffer as-is, just make sure it is local */
5899 if (likely(page_to_nid(page) == numa_node_id()))
5900 return true;
5901
5902 /* this page cannot be reused so discard it */
5903 put_page(page);
5904 return false;
5905 }
5906
5907 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 5908 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 5909
5910 /* avoid re-using remote pages */
5911 if (unlikely(page_to_nid(page) != numa_node_id()))
5912 return false;
5913
de78d1f9 5914#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 5915 /* if we are only owner of page we can reuse it */
5916 if (unlikely(page_count(page) != 1))
5917 return false;
5918
5919 /* flip page offset to other buffer */
de78d1f9 5920 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 5921
5922 /*
5923 * since we are the only owner of the page and we need to
5924 * increment it, just set the value to 2 in order to avoid
5925 * an unnecessary locked operation
5926 */
5927 atomic_set(&page->_count, 2);
de78d1f9
AD		 5928#else
5929 /* move offset up to the next cache line */
5930 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5931
5932 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5933 return false;
5934
5935 /* bump ref count on page before it is given to the stack */
5936 get_page(page);
5937#endif
cbc8e55f
AD		 5938
5939 return true;
5940}
5941
2e334eee
AD		 5942static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5943 union e1000_adv_rx_desc *rx_desc,
5944 struct sk_buff *skb)
5945{
5946 struct igb_rx_buffer *rx_buffer;
5947 struct page *page;
5948
5949 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5950
5951 /*
5952 * This memory barrier is needed to keep us from reading
5953 * any other fields out of the rx_desc until we know the
5954 * RXD_STAT_DD bit is set
5955 */
5956 rmb();
5957
5958 page = rx_buffer->page;
5959 prefetchw(page);
5960
5961 if (likely(!skb)) {
5962 void *page_addr = page_address(page) +
5963 rx_buffer->page_offset;
5964
5965 /* prefetch first cache line of first page */
5966 prefetch(page_addr);
5967#if L1_CACHE_BYTES < 128
5968 prefetch(page_addr + L1_CACHE_BYTES);
5969#endif
5970
5971 /* allocate a skb to store the frags */
5972 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5973 IGB_RX_HDR_LEN);
5974 if (unlikely(!skb)) {
5975 rx_ring->rx_stats.alloc_failed++;
5976 return NULL;
5977 }
5978
5979 /*
5980 * we will be copying header into skb->data in
5981 * pskb_may_pull so it is in our interest to prefetch
5982 * it now to avoid a possible cache miss
5983 */
5984 prefetchw(skb->data);
5985 }
5986
5987 /* we are reusing so sync this buffer for CPU use */
5988 dma_sync_single_range_for_cpu(rx_ring->dev,
5989 rx_buffer->dma,
5990 rx_buffer->page_offset,
de78d1f9 5991 IGB_RX_BUFSZ,
2e334eee
AD		 5992 DMA_FROM_DEVICE);
5993
5994 /* pull page into skb */
5995 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
5996 /* hand second half of page back to the ring */
5997 igb_reuse_rx_page(rx_ring, rx_buffer);
5998 } else {
5999 /* we are not reusing the buffer so unmap it */
6000 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6001 PAGE_SIZE, DMA_FROM_DEVICE);
6002 }
6003
6004 /* clear contents of rx_buffer */
6005 rx_buffer->page = NULL;
6006
6007 return skb;
6008}
6009
cd392f5c 6010static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6011 union e1000_adv_rx_desc *rx_desc,
6012 struct sk_buff *skb)
9d5c8243 6013{
bc8acf2c 6014 skb_checksum_none_assert(skb);
9d5c8243 6015
294e7d78 6016 /* Ignore Checksum bit is set */
3ceb90fd 6017 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6018 return;
6019
6020 /* Rx checksum disabled via ethtool */
6021 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6022 return;
85ad76b2 6023
9d5c8243 6024 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6025 if (igb_test_staterr(rx_desc,
6026 E1000_RXDEXT_STATERR_TCPE |
6027 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6028 /*
6029 * work around errata with sctp packets where the TCPE aka
6030 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6031 * packets, (aka let the stack check the crc32c)
6032 */
866cff06
AD		 6033 if (!((skb->len == 60) &&
6034 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6035 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6036 ring->rx_stats.csum_err++;
12dcd86b
ED		 6037 u64_stats_update_end(&ring->rx_syncp);
6038 }
9d5c8243 6039 /* let the stack verify checksum errors */
9d5c8243
AK		 6040 return;
6041 }
6042 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6043 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6044 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6045 skb->ip_summed = CHECKSUM_UNNECESSARY;
6046
3ceb90fd
AD		 6047 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6048 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6049}
6050
077887c3
AD		 6051static inline void igb_rx_hash(struct igb_ring *ring,
6052 union e1000_adv_rx_desc *rx_desc,
6053 struct sk_buff *skb)
6054{
6055 if (ring->netdev->features & NETIF_F_RXHASH)
6056 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6057}
6058
2e334eee
AD		 6059/**
6060 * igb_is_non_eop - process handling of non-EOP buffers
6061 * @rx_ring: Rx ring being processed
6062 * @rx_desc: Rx descriptor for current buffer
6063 * @skb: current socket buffer containing buffer in progress
6064 *
6065 * This function updates next to clean. If the buffer is an EOP buffer
6066 * this function exits returning false, otherwise it will place the
6067 * sk_buff in the next buffer to be chained and return true indicating
6068 * that this is in fact a non-EOP buffer.
6069 **/
6070static bool igb_is_non_eop(struct igb_ring *rx_ring,
6071 union e1000_adv_rx_desc *rx_desc)
6072{
6073 u32 ntc = rx_ring->next_to_clean + 1;
6074
6075 /* fetch, update, and store next to clean */
6076 ntc = (ntc < rx_ring->count) ? ntc : 0;
6077 rx_ring->next_to_clean = ntc;
6078
6079 prefetch(IGB_RX_DESC(rx_ring, ntc));
6080
6081 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6082 return false;
6083
6084 return true;
6085}
6086
1a1c225b
AD		 6087/**
6088 * igb_get_headlen - determine size of header for LRO/GRO
6089 * @data: pointer to the start of the headers
6090 * @max_len: total length of section to find headers in
6091 *
6092 * This function is meant to determine the length of headers that will
6093 * be recognized by hardware for LRO, and GRO offloads. The main
6094 * motivation of doing this is to only perform one pull for IPv4 TCP
6095 * packets so that we can do basic things like calculating the gso_size
6096 * based on the average data per packet.
6097 **/
6098static unsigned int igb_get_headlen(unsigned char *data,
6099 unsigned int max_len)
6100{
6101 union {
6102 unsigned char *network;
6103 /* l2 headers */
6104 struct ethhdr *eth;
6105 struct vlan_hdr *vlan;
6106 /* l3 headers */
6107 struct iphdr *ipv4;
6108 struct ipv6hdr *ipv6;
6109 } hdr;
6110 __be16 protocol;
6111 u8 nexthdr = 0; /* default to not TCP */
6112 u8 hlen;
6113
6114 /* this should never happen, but better safe than sorry */
6115 if (max_len < ETH_HLEN)
6116 return max_len;
6117
6118 /* initialize network frame pointer */
6119 hdr.network = data;
6120
6121 /* set first protocol and move network header forward */
6122 protocol = hdr.eth->h_proto;
6123 hdr.network += ETH_HLEN;
6124
6125 /* handle any vlan tag if present */
6126 if (protocol == __constant_htons(ETH_P_8021Q)) {
6127 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6128 return max_len;
6129
6130 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6131 hdr.network += VLAN_HLEN;
6132 }
6133
6134 /* handle L3 protocols */
6135 if (protocol == __constant_htons(ETH_P_IP)) {
6136 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6137 return max_len;
6138
6139 /* access ihl as a u8 to avoid unaligned access on ia64 */
6140 hlen = (hdr.network[0] & 0x0F) << 2;
6141
6142 /* verify hlen meets minimum size requirements */
6143 if (hlen < sizeof(struct iphdr))
6144 return hdr.network - data;
6145
f2fb4ab2
AD		 6146 /* record next protocol if header is present */
6147 if (!hdr.ipv4->frag_off)
6148 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6149 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6150 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6151 return max_len;
6152
6153 /* record next protocol */
6154 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6155 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6156 } else {
6157 return hdr.network - data;
6158 }
6159
f2fb4ab2
AD		 6160 /* relocate pointer to start of L4 header */
6161 hdr.network += hlen;
6162
1a1c225b
AD		 6163 /* finally sort out TCP */
6164 if (nexthdr == IPPROTO_TCP) {
6165 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6166 return max_len;
6167
6168 /* access doff as a u8 to avoid unaligned access on ia64 */
6169 hlen = (hdr.network[12] & 0xF0) >> 2;
6170
6171 /* verify hlen meets minimum size requirements */
6172 if (hlen < sizeof(struct tcphdr))
6173 return hdr.network - data;
6174
6175 hdr.network += hlen;
6176 } else if (nexthdr == IPPROTO_UDP) {
6177 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6178 return max_len;
6179
6180 hdr.network += sizeof(struct udphdr);
6181 }
6182
6183 /*
6184 * If everything has gone correctly hdr.network should be the
6185 * data section of the packet and will be the end of the header.
6186 * If not then it probably represents the end of the last recognized
6187 * header.
6188 */
6189 if ((hdr.network - data) < max_len)
6190 return hdr.network - data;
6191 else
6192 return max_len;
6193}
6194
6195/**
6196 * igb_pull_tail - igb specific version of skb_pull_tail
6197 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6198 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6199 * @skb: pointer to current skb being adjusted
6200 *
6201 * This function is an igb specific version of __pskb_pull_tail. The
6202 * main difference between this version and the original function is that
6203 * this function can make several assumptions about the state of things
6204 * that allow for significant optimizations versus the standard function.
6205 * As a result we can do things like drop a frag and maintain an accurate
6206 * truesize for the skb.
6207 */
6208static void igb_pull_tail(struct igb_ring *rx_ring,
6209 union e1000_adv_rx_desc *rx_desc,
6210 struct sk_buff *skb)
2d94d8ab 6211{
1a1c225b
AD		 6212 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6213 unsigned char *va;
6214 unsigned int pull_len;
6215
6216 /*
6217 * it is valid to use page_address instead of kmap since we are
6218 * working with pages allocated out of the lomem pool per
6219 * alloc_page(GFP_ATOMIC)
2d94d8ab 6220 */
1a1c225b
AD		 6221 va = skb_frag_address(frag);
6222
1a1c225b
AD		 6223 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6224 /* retrieve timestamp from buffer */
6225 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6226
6227 /* update pointers to remove timestamp header */
6228 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6229 frag->page_offset += IGB_TS_HDR_LEN;
6230 skb->data_len -= IGB_TS_HDR_LEN;
6231 skb->len -= IGB_TS_HDR_LEN;
6232
6233 /* move va to start of packet data */
6234 va += IGB_TS_HDR_LEN;
6235 }
6236
1a1c225b
AD		 6237 /*
6238 * we need the header to contain the greater of either ETH_HLEN or
6239 * 60 bytes if the skb->len is less than 60 for skb_pad.
6240 */
6241 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6242
6243 /* align pull length to size of long to optimize memcpy performance */
6244 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6245
6246 /* update all of the pointers */
6247 skb_frag_size_sub(frag, pull_len);
6248 frag->page_offset += pull_len;
6249 skb->data_len -= pull_len;
6250 skb->tail += pull_len;
6251}
6252
6253/**
6254 * igb_cleanup_headers - Correct corrupted or empty headers
6255 * @rx_ring: rx descriptor ring packet is being transacted on
6256 * @rx_desc: pointer to the EOP Rx descriptor
6257 * @skb: pointer to current skb being fixed
6258 *
6259 * Address the case where we are pulling data in on pages only
6260 * and as such no data is present in the skb header.
6261 *
6262 * In addition if skb is not at least 60 bytes we need to pad it so that
6263 * it is large enough to qualify as a valid Ethernet frame.
6264 *
6265 * Returns true if an error was encountered and skb was freed.
6266 **/
6267static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6268 union e1000_adv_rx_desc *rx_desc,
6269 struct sk_buff *skb)
6270{
6271
6272 if (unlikely((igb_test_staterr(rx_desc,
6273 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6274 struct net_device *netdev = rx_ring->netdev;
6275 if (!(netdev->features & NETIF_F_RXALL)) {
6276 dev_kfree_skb_any(skb);
6277 return true;
6278 }
6279 }
6280
6281 /* place header in linear portion of buffer */
6282 if (skb_is_nonlinear(skb))
6283 igb_pull_tail(rx_ring, rx_desc, skb);
6284
6285 /* if skb_pad returns an error the skb was freed */
6286 if (unlikely(skb->len < 60)) {
6287 int pad_len = 60 - skb->len;
6288
6289 if (skb_pad(skb, pad_len))
6290 return true;
6291 __skb_put(skb, pad_len);
6292 }
6293
6294 return false;
2d94d8ab
AD		 6295}
6296
db2ee5bd
AD		 6297/**
6298 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6299 * @rx_ring: rx descriptor ring packet is being transacted on
6300 * @rx_desc: pointer to the EOP Rx descriptor
6301 * @skb: pointer to current skb being populated
6302 *
6303 * This function checks the ring, descriptor, and packet information in
6304 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6305 * other fields within the skb.
6306 **/
6307static void igb_process_skb_fields(struct igb_ring *rx_ring,
6308 union e1000_adv_rx_desc *rx_desc,
6309 struct sk_buff *skb)
6310{
6311 struct net_device *dev = rx_ring->netdev;
6312
6313 igb_rx_hash(rx_ring, rx_desc, skb);
6314
6315 igb_rx_checksum(rx_ring, rx_desc, skb);
6316
db2ee5bd 6317 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6318
6319 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6320 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6321 u16 vid;
6322 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6323 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6324 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6325 else
6326 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6327
6328 __vlan_hwaccel_put_tag(skb, vid);
6329 }
6330
6331 skb_record_rx_queue(skb, rx_ring->queue_index);
6332
6333 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6334}
6335
2e334eee 6336static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6337{
0ba82994 6338 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6339 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6340 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6341 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6342
2e334eee
AD		 6343 do {
6344 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6345
2e334eee
AD		 6346 /* return some buffers to hardware, one at a time is too slow */
6347 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6348 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6349 cleaned_count = 0;
6350 }
bf36c1a0 6351
2e334eee 6352 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6353
2e334eee
AD		 6354 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6355 break;
9d5c8243 6356
2e334eee
AD		 6357 /* retrieve a buffer from the ring */
6358 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6359
2e334eee
AD		 6360 /* exit if we failed to retrieve a buffer */
6361 if (!skb)
6362 break;
1a1c225b 6363
2e334eee 6364 cleaned_count++;
1a1c225b 6365
2e334eee
AD		 6366 /* fetch next buffer in frame if non-eop */
6367 if (igb_is_non_eop(rx_ring, rx_desc))
6368 continue;
1a1c225b
AD		 6369
6370 /* verify the packet layout is correct */
6371 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6372 skb = NULL;
6373 continue;
9d5c8243 6374 }
9d5c8243 6375
db2ee5bd 6376 /* probably a little skewed due to removing CRC */
3ceb90fd 6377 total_bytes += skb->len;
3ceb90fd 6378
db2ee5bd
AD		 6379 /* populate checksum, timestamp, VLAN, and protocol */
6380 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6381
b2cb09b1 6382 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6383
1a1c225b
AD		 6384 /* reset skb pointer */
6385 skb = NULL;
6386
2e334eee
AD		 6387 /* update budget accounting */
6388 total_packets++;
6389 } while (likely(total_packets < budget));
bf36c1a0 6390
1a1c225b
AD		 6391 /* place incomplete frames back on ring for completion */
6392 rx_ring->skb = skb;
6393
12dcd86b 6394 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6395 rx_ring->rx_stats.packets += total_packets;
6396 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6397 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6398 q_vector->rx.total_packets += total_packets;
6399 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6400
6401 if (cleaned_count)
cd392f5c 6402 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6403
2e334eee 6404 return (total_packets < budget);
9d5c8243
AK		 6405}
6406
c023cd88 6407static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6408 struct igb_rx_buffer *bi)
c023cd88
AD		 6409{
6410 struct page *page = bi->page;
cbc8e55f 6411 dma_addr_t dma;
c023cd88 6412
cbc8e55f
AD		 6413 /* since we are recycling buffers we should seldom need to alloc */
6414 if (likely(page))
c023cd88
AD		 6415 return true;
6416
cbc8e55f
AD		 6417 /* alloc new page for storage */
6418 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6419 if (unlikely(!page)) {
6420 rx_ring->rx_stats.alloc_failed++;
6421 return false;
c023cd88
AD		 6422 }
6423
cbc8e55f
AD		 6424 /* map page for use */
6425 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6426
cbc8e55f
AD		 6427 /*
6428 * if mapping failed free memory back to system since
6429 * there isn't much point in holding memory we can't use
6430 */
1a1c225b 6431 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6432 __free_page(page);
6433
c023cd88
AD		 6434 rx_ring->rx_stats.alloc_failed++;
6435 return false;
6436 }
6437
1a1c225b 6438 bi->dma = dma;
cbc8e55f
AD		 6439 bi->page = page;
6440 bi->page_offset = 0;
1a1c225b 6441
c023cd88
AD		 6442 return true;
6443}
6444
9d5c8243 6445/**
cd392f5c 6446 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6447 * @adapter: address of board private structure
6448 **/
cd392f5c 6449void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6450{
9d5c8243 6451 union e1000_adv_rx_desc *rx_desc;
06034649 6452 struct igb_rx_buffer *bi;
c023cd88 6453 u16 i = rx_ring->next_to_use;
9d5c8243 6454
cbc8e55f
AD		 6455 /* nothing to do */
6456 if (!cleaned_count)
6457 return;
6458
60136906 6459 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6460 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6461 i -= rx_ring->count;
9d5c8243 6462
cbc8e55f 6463 do {
1a1c225b 6464 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6465 break;
9d5c8243 6466
cbc8e55f
AD		 6467 /*
6468 * Refresh the desc even if buffer_addrs didn't change
6469 * because each write-back erases this info.
6470 */
6471 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6472
c023cd88
AD		 6473 rx_desc++;
6474 bi++;
9d5c8243 6475 i++;
c023cd88 6476 if (unlikely(!i)) {
60136906 6477 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6478 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6479 i -= rx_ring->count;
6480 }
6481
6482 /* clear the hdr_addr for the next_to_use descriptor */
6483 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6484
6485 cleaned_count--;
6486 } while (cleaned_count);
9d5c8243 6487
c023cd88
AD		 6488 i += rx_ring->count;
6489
9d5c8243 6490 if (rx_ring->next_to_use != i) {
cbc8e55f 6491 /* record the next descriptor to use */
9d5c8243 6492 rx_ring->next_to_use = i;
9d5c8243 6493
cbc8e55f
AD		 6494 /* update next to alloc since we have filled the ring */
6495 rx_ring->next_to_alloc = i;
6496
6497 /*
6498 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6499 * know there are new descriptors to fetch. (Only
6500 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6501 * such as IA-64).
6502 */
9d5c8243 6503 wmb();
fce99e34 6504 writel(i, rx_ring->tail);
9d5c8243
AK		 6505 }
6506}
6507
6508/**
6509 * igb_mii_ioctl -
6510 * @netdev:
6511 * @ifreq:
6512 * @cmd:
6513 **/
6514static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6515{
6516 struct igb_adapter *adapter = netdev_priv(netdev);
6517 struct mii_ioctl_data *data = if_mii(ifr);
6518
6519 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6520 return -EOPNOTSUPP;
6521
6522 switch (cmd) {
6523 case SIOCGMIIPHY:
6524 data->phy_id = adapter->hw.phy.addr;
6525 break;
6526 case SIOCGMIIREG:
f5f4cf08
AD		 6527 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6528 &data->val_out))
9d5c8243
AK		 6529 return -EIO;
6530 break;
6531 case SIOCSMIIREG:
6532 default:
6533 return -EOPNOTSUPP;
6534 }
6535 return 0;
6536}
6537
6538/**
6539 * igb_ioctl -
6540 * @netdev:
6541 * @ifreq:
6542 * @cmd:
6543 **/
6544static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6545{
6546 switch (cmd) {
6547 case SIOCGMIIPHY:
6548 case SIOCGMIIREG:
6549 case SIOCSMIIREG:
6550 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6551 case SIOCSHWTSTAMP:
a79f4f88 6552 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6553 default:
6554 return -EOPNOTSUPP;
6555 }
6556}
6557
009bc06e
AD		 6558s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6559{
6560 struct igb_adapter *adapter = hw->back;
009bc06e 6561
23d028cc 6562 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6563 return -E1000_ERR_CONFIG;
6564
009bc06e
AD		 6565 return 0;
6566}
6567
6568s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6569{
6570 struct igb_adapter *adapter = hw->back;
009bc06e 6571
23d028cc 6572 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6573 return -E1000_ERR_CONFIG;
6574
009bc06e
AD		 6575 return 0;
6576}
6577
c8f44aff 6578static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6579{
6580 struct igb_adapter *adapter = netdev_priv(netdev);
6581 struct e1000_hw *hw = &adapter->hw;
6582 u32 ctrl, rctl;
5faf030c 6583 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6584
5faf030c 6585 if (enable) {
9d5c8243
AK		 6586 /* enable VLAN tag insert/strip */
6587 ctrl = rd32(E1000_CTRL);
6588 ctrl |= E1000_CTRL_VME;
6589 wr32(E1000_CTRL, ctrl);
6590
51466239 6591 /* Disable CFI check */
9d5c8243 6592 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6593 rctl &= ~E1000_RCTL_CFIEN;
6594 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6595 } else {
6596 /* disable VLAN tag insert/strip */
6597 ctrl = rd32(E1000_CTRL);
6598 ctrl &= ~E1000_CTRL_VME;
6599 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6600 }
6601
e1739522 6602 igb_rlpml_set(adapter);
9d5c8243
AK		 6603}
6604
8e586137 6605static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6606{
6607 struct igb_adapter *adapter = netdev_priv(netdev);
6608 struct e1000_hw *hw = &adapter->hw;
4ae196df 6609 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6610
51466239
AD		 6611 /* attempt to add filter to vlvf array */
6612 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6613
51466239
AD		 6614 /* add the filter since PF can receive vlans w/o entry in vlvf */
6615 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6616
6617 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6618
6619 return 0;
9d5c8243
AK		 6620}
6621
8e586137 6622static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6623{
6624 struct igb_adapter *adapter = netdev_priv(netdev);
6625 struct e1000_hw *hw = &adapter->hw;
4ae196df 6626 int pf_id = adapter->vfs_allocated_count;
51466239 6627 s32 err;
9d5c8243 6628
51466239
AD		 6629 /* remove vlan from VLVF table array */
6630 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6631
51466239
AD		 6632 /* if vid was not present in VLVF just remove it from table */
6633 if (err)
4ae196df 6634 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6635
6636 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6637
6638 return 0;
9d5c8243
AK		 6639}
6640
6641static void igb_restore_vlan(struct igb_adapter *adapter)
6642{
b2cb09b1 6643 u16 vid;
9d5c8243 6644
5faf030c
AD		 6645 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6646
b2cb09b1
JP		 6647 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6648 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6649}
6650
14ad2513 6651int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6652{
090b1795 6653 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6654 struct e1000_mac_info *mac = &adapter->hw.mac;
6655
6656 mac->autoneg = 0;
6657
14ad2513
DD		 6658 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6659 * for the switch() below to work */
6660 if ((spd & 1) || (dplx & ~1))
6661 goto err_inval;
6662
cd2638a8
CW		 6663 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6664 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6665 spd != SPEED_1000 &&
6666 dplx != DUPLEX_FULL)
6667 goto err_inval;
cd2638a8 6668
14ad2513 6669 switch (spd + dplx) {
9d5c8243
AK		 6670 case SPEED_10 + DUPLEX_HALF:
6671 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6672 break;
6673 case SPEED_10 + DUPLEX_FULL:
6674 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6675 break;
6676 case SPEED_100 + DUPLEX_HALF:
6677 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6678 break;
6679 case SPEED_100 + DUPLEX_FULL:
6680 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6681 break;
6682 case SPEED_1000 + DUPLEX_FULL:
6683 mac->autoneg = 1;
6684 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6685 break;
6686 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6687 default:
14ad2513 6688 goto err_inval;
9d5c8243 6689 }
8376dad0
JB		 6690
6691 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6692 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6693
9d5c8243 6694 return 0;
14ad2513
DD		 6695
6696err_inval:
6697 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6698 return -EINVAL;
9d5c8243
AK		 6699}
6700
749ab2cd
YZ		 6701static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6702 bool runtime)
9d5c8243
AK		 6703{
6704 struct net_device *netdev = pci_get_drvdata(pdev);
6705 struct igb_adapter *adapter = netdev_priv(netdev);
6706 struct e1000_hw *hw = &adapter->hw;
2d064c06 6707 u32 ctrl, rctl, status;
749ab2cd 6708 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6709#ifdef CONFIG_PM
6710 int retval = 0;
6711#endif
6712
6713 netif_device_detach(netdev);
6714
a88f10ec 6715 if (netif_running(netdev))
749ab2cd 6716 __igb_close(netdev, true);
a88f10ec 6717
047e0030 6718 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6719
6720#ifdef CONFIG_PM
6721 retval = pci_save_state(pdev);
6722 if (retval)
6723 return retval;
6724#endif
6725
6726 status = rd32(E1000_STATUS);
6727 if (status & E1000_STATUS_LU)
6728 wufc &= ~E1000_WUFC_LNKC;
6729
6730 if (wufc) {
6731 igb_setup_rctl(adapter);
ff41f8dc 6732 igb_set_rx_mode(netdev);
9d5c8243
AK		 6733
6734 /* turn on all-multi mode if wake on multicast is enabled */
6735 if (wufc & E1000_WUFC_MC) {
6736 rctl = rd32(E1000_RCTL);
6737 rctl |= E1000_RCTL_MPE;
6738 wr32(E1000_RCTL, rctl);
6739 }
6740
6741 ctrl = rd32(E1000_CTRL);
6742 /* advertise wake from D3Cold */
6743 #define E1000_CTRL_ADVD3WUC 0x00100000
6744 /* phy power management enable */
6745 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6746 ctrl |= E1000_CTRL_ADVD3WUC;
6747 wr32(E1000_CTRL, ctrl);
6748
9d5c8243 6749 /* Allow time for pending master requests to run */
330a6d6a 6750 igb_disable_pcie_master(hw);
9d5c8243
AK		 6751
6752 wr32(E1000_WUC, E1000_WUC_PME_EN);
6753 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6754 } else {
6755 wr32(E1000_WUC, 0);
6756 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6757 }
6758
3fe7c4c9
RW		 6759 *enable_wake = wufc || adapter->en_mng_pt;
6760 if (!*enable_wake)
88a268c1
NN		 6761 igb_power_down_link(adapter);
6762 else
6763 igb_power_up_link(adapter);
9d5c8243
AK		 6764
6765 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6766 * would have already happened in close and is redundant. */
6767 igb_release_hw_control(adapter);
6768
6769 pci_disable_device(pdev);
6770
9d5c8243
AK		 6771 return 0;
6772}
6773
6774#ifdef CONFIG_PM
d9dd966d 6775#ifdef CONFIG_PM_SLEEP
749ab2cd 6776static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 6777{
6778 int retval;
6779 bool wake;
749ab2cd 6780 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 6781
749ab2cd 6782 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6783 if (retval)
6784 return retval;
6785
6786 if (wake) {
6787 pci_prepare_to_sleep(pdev);
6788 } else {
6789 pci_wake_from_d3(pdev, false);
6790 pci_set_power_state(pdev, PCI_D3hot);
6791 }
6792
6793 return 0;
6794}
d9dd966d 6795#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 6796
749ab2cd 6797static int igb_resume(struct device *dev)
9d5c8243 6798{
749ab2cd 6799 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 6800 struct net_device *netdev = pci_get_drvdata(pdev);
6801 struct igb_adapter *adapter = netdev_priv(netdev);
6802 struct e1000_hw *hw = &adapter->hw;
6803 u32 err;
6804
6805 pci_set_power_state(pdev, PCI_D0);
6806 pci_restore_state(pdev);
b94f2d77 6807 pci_save_state(pdev);
42bfd33a 6808
aed5dec3 6809 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6810 if (err) {
6811 dev_err(&pdev->dev,
6812 "igb: Cannot enable PCI device from suspend\n");
6813 return err;
6814 }
6815 pci_set_master(pdev);
6816
6817 pci_enable_wake(pdev, PCI_D3hot, 0);
6818 pci_enable_wake(pdev, PCI_D3cold, 0);
6819
53c7d064 6820 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 6821 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6822 return -ENOMEM;
9d5c8243
AK		 6823 }
6824
9d5c8243 6825 igb_reset(adapter);
a8564f03
AD		 6826
6827 /* let the f/w know that the h/w is now under the control of the
6828 * driver. */
6829 igb_get_hw_control(adapter);
6830
9d5c8243
AK		 6831 wr32(E1000_WUS, ~0);
6832
749ab2cd 6833 if (netdev->flags & IFF_UP) {
0c2cc02e 6834 rtnl_lock();
749ab2cd 6835 err = __igb_open(netdev, true);
0c2cc02e 6836 rtnl_unlock();
a88f10ec
AD		 6837 if (err)
6838 return err;
6839 }
9d5c8243
AK		 6840
6841 netif_device_attach(netdev);
749ab2cd
YZ		 6842 return 0;
6843}
6844
6845#ifdef CONFIG_PM_RUNTIME
6846static int igb_runtime_idle(struct device *dev)
6847{
6848 struct pci_dev *pdev = to_pci_dev(dev);
6849 struct net_device *netdev = pci_get_drvdata(pdev);
6850 struct igb_adapter *adapter = netdev_priv(netdev);
6851
6852 if (!igb_has_link(adapter))
6853 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6854
6855 return -EBUSY;
6856}
6857
6858static int igb_runtime_suspend(struct device *dev)
6859{
6860 struct pci_dev *pdev = to_pci_dev(dev);
6861 int retval;
6862 bool wake;
6863
6864 retval = __igb_shutdown(pdev, &wake, 1);
6865 if (retval)
6866 return retval;
6867
6868 if (wake) {
6869 pci_prepare_to_sleep(pdev);
6870 } else {
6871 pci_wake_from_d3(pdev, false);
6872 pci_set_power_state(pdev, PCI_D3hot);
6873 }
9d5c8243 6874
9d5c8243
AK		 6875 return 0;
6876}
749ab2cd
YZ		 6877
6878static int igb_runtime_resume(struct device *dev)
6879{
6880 return igb_resume(dev);
6881}
6882#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 6883#endif
6884
6885static void igb_shutdown(struct pci_dev *pdev)
6886{
3fe7c4c9
RW		 6887 bool wake;
6888
749ab2cd 6889 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6890
6891 if (system_state == SYSTEM_POWER_OFF) {
6892 pci_wake_from_d3(pdev, wake);
6893 pci_set_power_state(pdev, PCI_D3hot);
6894 }
9d5c8243
AK		 6895}
6896
6897#ifdef CONFIG_NET_POLL_CONTROLLER
6898/*
6899 * Polling 'interrupt' - used by things like netconsole to send skbs
6900 * without having to re-enable interrupts. It's not called while
6901 * the interrupt routine is executing.
6902 */
6903static void igb_netpoll(struct net_device *netdev)
6904{
6905 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6906 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 6907 struct igb_q_vector *q_vector;
9d5c8243 6908 int i;
9d5c8243 6909
047e0030 6910 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 6911 q_vector = adapter->q_vector[i];
6912 if (adapter->msix_entries)
6913 wr32(E1000_EIMC, q_vector->eims_value);
6914 else
6915 igb_irq_disable(adapter);
047e0030 6916 napi_schedule(&q_vector->napi);
eebbbdba 6917 }
9d5c8243
AK		 6918}
6919#endif /* CONFIG_NET_POLL_CONTROLLER */
6920
6921/**
6922 * igb_io_error_detected - called when PCI error is detected
6923 * @pdev: Pointer to PCI device
6924 * @state: The current pci connection state
6925 *
6926 * This function is called after a PCI bus error affecting
6927 * this device has been detected.
6928 */
6929static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6930 pci_channel_state_t state)
6931{
6932 struct net_device *netdev = pci_get_drvdata(pdev);
6933 struct igb_adapter *adapter = netdev_priv(netdev);
6934
6935 netif_device_detach(netdev);
6936
59ed6eec
AD		 6937 if (state == pci_channel_io_perm_failure)
6938 return PCI_ERS_RESULT_DISCONNECT;
6939
9d5c8243
AK		 6940 if (netif_running(netdev))
6941 igb_down(adapter);
6942 pci_disable_device(pdev);
6943
6944 /* Request a slot slot reset. */
6945 return PCI_ERS_RESULT_NEED_RESET;
6946}
6947
6948/**
6949 * igb_io_slot_reset - called after the pci bus has been reset.
6950 * @pdev: Pointer to PCI device
6951 *
6952 * Restart the card from scratch, as if from a cold-boot. Implementation
6953 * resembles the first-half of the igb_resume routine.
6954 */
6955static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6956{
6957 struct net_device *netdev = pci_get_drvdata(pdev);
6958 struct igb_adapter *adapter = netdev_priv(netdev);
6959 struct e1000_hw *hw = &adapter->hw;
40a914fa 6960 pci_ers_result_t result;
42bfd33a 6961 int err;
9d5c8243 6962
aed5dec3 6963 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6964 dev_err(&pdev->dev,
6965 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6966 result = PCI_ERS_RESULT_DISCONNECT;
6967 } else {
6968 pci_set_master(pdev);
6969 pci_restore_state(pdev);
b94f2d77 6970 pci_save_state(pdev);
9d5c8243 6971
40a914fa
AD		 6972 pci_enable_wake(pdev, PCI_D3hot, 0);
6973 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6974
40a914fa
AD		 6975 igb_reset(adapter);
6976 wr32(E1000_WUS, ~0);
6977 result = PCI_ERS_RESULT_RECOVERED;
6978 }
9d5c8243 6979
ea943d41
JK		 6980 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6981 if (err) {
6982 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6983 "failed 0x%0x\n", err);
6984 /* non-fatal, continue */
6985 }
40a914fa
AD		 6986
6987 return result;
9d5c8243
AK		 6988}
6989
6990/**
6991 * igb_io_resume - called when traffic can start flowing again.
6992 * @pdev: Pointer to PCI device
6993 *
6994 * This callback is called when the error recovery driver tells us that
6995 * its OK to resume normal operation. Implementation resembles the
6996 * second-half of the igb_resume routine.
6997 */
6998static void igb_io_resume(struct pci_dev *pdev)
6999{
7000 struct net_device *netdev = pci_get_drvdata(pdev);
7001 struct igb_adapter *adapter = netdev_priv(netdev);
7002
9d5c8243
AK		 7003 if (netif_running(netdev)) {
7004 if (igb_up(adapter)) {
7005 dev_err(&pdev->dev, "igb_up failed after reset\n");
7006 return;
7007 }
7008 }
7009
7010 netif_device_attach(netdev);
7011
7012 /* let the f/w know that the h/w is now under the control of the
7013 * driver. */
7014 igb_get_hw_control(adapter);
9d5c8243
AK		 7015}
7016
26ad9178
AD		 7017static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7018 u8 qsel)
7019{
7020 u32 rar_low, rar_high;
7021 struct e1000_hw *hw = &adapter->hw;
7022
7023 /* HW expects these in little endian so we reverse the byte order
7024 * from network order (big endian) to little endian
7025 */
7026 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7027 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7028 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7029
7030 /* Indicate to hardware the Address is Valid. */
7031 rar_high |= E1000_RAH_AV;
7032
7033 if (hw->mac.type == e1000_82575)
7034 rar_high |= E1000_RAH_POOL_1 * qsel;
7035 else
7036 rar_high |= E1000_RAH_POOL_1 << qsel;
7037
7038 wr32(E1000_RAL(index), rar_low);
7039 wrfl();
7040 wr32(E1000_RAH(index), rar_high);
7041 wrfl();
7042}
7043
4ae196df
AD		 7044static int igb_set_vf_mac(struct igb_adapter *adapter,
7045 int vf, unsigned char *mac_addr)
7046{
7047 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7048 /* VF MAC addresses start at end of receive addresses and moves
7049 * torwards the first, as a result a collision should not be possible */
7050 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7051
37680117 7052 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7053
26ad9178 7054 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7055
7056 return 0;
7057}
7058
8151d294
WM		 7059static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7060{
7061 struct igb_adapter *adapter = netdev_priv(netdev);
7062 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7063 return -EINVAL;
7064 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7065 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7066 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7067 " change effective.");
7068 if (test_bit(__IGB_DOWN, &adapter->state)) {
7069 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7070 " but the PF device is not up.\n");
7071 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7072 " attempting to use the VF device.\n");
7073 }
7074 return igb_set_vf_mac(adapter, vf, mac);
7075}
7076
17dc566c
LL		 7077static int igb_link_mbps(int internal_link_speed)
7078{
7079 switch (internal_link_speed) {
7080 case SPEED_100:
7081 return 100;
7082 case SPEED_1000:
7083 return 1000;
7084 default:
7085 return 0;
7086 }
7087}
7088
7089static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7090 int link_speed)
7091{
7092 int rf_dec, rf_int;
7093 u32 bcnrc_val;
7094
7095 if (tx_rate != 0) {
7096 /* Calculate the rate factor values to set */
7097 rf_int = link_speed / tx_rate;
7098 rf_dec = (link_speed - (rf_int * tx_rate));
7099 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7100
7101 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7102 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7103 E1000_RTTBCNRC_RF_INT_MASK);
7104 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7105 } else {
7106 bcnrc_val = 0;
7107 }
7108
7109 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7110 /*
7111 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7112 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7113 */
7114 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7115 wr32(E1000_RTTBCNRC, bcnrc_val);
7116}
7117
7118static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7119{
7120 int actual_link_speed, i;
7121 bool reset_rate = false;
7122
7123 /* VF TX rate limit was not set or not supported */
7124 if ((adapter->vf_rate_link_speed == 0) ||
7125 (adapter->hw.mac.type != e1000_82576))
7126 return;
7127
7128 actual_link_speed = igb_link_mbps(adapter->link_speed);
7129 if (actual_link_speed != adapter->vf_rate_link_speed) {
7130 reset_rate = true;
7131 adapter->vf_rate_link_speed = 0;
7132 dev_info(&adapter->pdev->dev,
7133 "Link speed has been changed. VF Transmit "
7134 "rate is disabled\n");
7135 }
7136
7137 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7138 if (reset_rate)
7139 adapter->vf_data[i].tx_rate = 0;
7140
7141 igb_set_vf_rate_limit(&adapter->hw, i,
7142 adapter->vf_data[i].tx_rate,
7143 actual_link_speed);
7144 }
7145}
7146
8151d294
WM		 7147static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7148{
17dc566c
LL		 7149 struct igb_adapter *adapter = netdev_priv(netdev);
7150 struct e1000_hw *hw = &adapter->hw;
7151 int actual_link_speed;
7152
7153 if (hw->mac.type != e1000_82576)
7154 return -EOPNOTSUPP;
7155
7156 actual_link_speed = igb_link_mbps(adapter->link_speed);
7157 if ((vf >= adapter->vfs_allocated_count) ||
7158 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7159 (tx_rate < 0) || (tx_rate > actual_link_speed))
7160 return -EINVAL;
7161
7162 adapter->vf_rate_link_speed = actual_link_speed;
7163 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7164 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7165
7166 return 0;
8151d294
WM		 7167}
7168
7169static int igb_ndo_get_vf_config(struct net_device *netdev,
7170 int vf, struct ifla_vf_info *ivi)
7171{
7172 struct igb_adapter *adapter = netdev_priv(netdev);
7173 if (vf >= adapter->vfs_allocated_count)
7174 return -EINVAL;
7175 ivi->vf = vf;
7176 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7177 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7178 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7179 ivi->qos = adapter->vf_data[vf].pf_qos;
7180 return 0;
7181}
7182
4ae196df
AD		 7183static void igb_vmm_control(struct igb_adapter *adapter)
7184{
7185 struct e1000_hw *hw = &adapter->hw;
10d8e907 7186 u32 reg;
4ae196df 7187
52a1dd4d
AD		 7188 switch (hw->mac.type) {
7189 case e1000_82575:
f96a8a0b
CW		 7190 case e1000_i210:
7191 case e1000_i211:
52a1dd4d
AD		 7192 default:
7193 /* replication is not supported for 82575 */
4ae196df 7194 return;
52a1dd4d
AD		 7195 case e1000_82576:
7196 /* notify HW that the MAC is adding vlan tags */
7197 reg = rd32(E1000_DTXCTL);
7198 reg |= E1000_DTXCTL_VLAN_ADDED;
7199 wr32(E1000_DTXCTL, reg);
7200 case e1000_82580:
7201 /* enable replication vlan tag stripping */
7202 reg = rd32(E1000_RPLOLR);
7203 reg |= E1000_RPLOLR_STRVLAN;
7204 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7205 case e1000_i350:
7206 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7207 break;
7208 }
10d8e907 7209
d4960307
AD		 7210 if (adapter->vfs_allocated_count) {
7211 igb_vmdq_set_loopback_pf(hw, true);
7212 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7213 igb_vmdq_set_anti_spoofing_pf(hw, true,
7214 adapter->vfs_allocated_count);
d4960307
AD		 7215 } else {
7216 igb_vmdq_set_loopback_pf(hw, false);
7217 igb_vmdq_set_replication_pf(hw, false);
7218 }
4ae196df
AD		 7219}
7220
b6e0c419
CW		 7221static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7222{
7223 struct e1000_hw *hw = &adapter->hw;
7224 u32 dmac_thr;
7225 u16 hwm;
7226
7227 if (hw->mac.type > e1000_82580) {
7228 if (adapter->flags & IGB_FLAG_DMAC) {
7229 u32 reg;
7230
7231 /* force threshold to 0. */
7232 wr32(E1000_DMCTXTH, 0);
7233
7234 /*
e8c626e9
MV		 7235 * DMA Coalescing high water mark needs to be greater
7236 * than the Rx threshold. Set hwm to PBA - max frame
7237 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7238 */
e8c626e9
MV		 7239 hwm = 64 * pba - adapter->max_frame_size / 16;
7240 if (hwm < 64 * (pba - 6))
7241 hwm = 64 * (pba - 6);
7242 reg = rd32(E1000_FCRTC);
7243 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7244 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7245 & E1000_FCRTC_RTH_COAL_MASK);
7246 wr32(E1000_FCRTC, reg);
7247
7248 /*
7249 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7250 * frame size, capping it at PBA - 10KB.
7251 */
7252 dmac_thr = pba - adapter->max_frame_size / 512;
7253 if (dmac_thr < pba - 10)
7254 dmac_thr = pba - 10;
b6e0c419
CW		 7255 reg = rd32(E1000_DMACR);
7256 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7257 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7258 & E1000_DMACR_DMACTHR_MASK);
7259
7260 /* transition to L0x or L1 if available..*/
7261 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7262
7263 /* watchdog timer= +-1000 usec in 32usec intervals */
7264 reg |= (1000 >> 5);
0c02dd98
MV		 7265
7266 /* Disable BMC-to-OS Watchdog Enable */
7267 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7268 wr32(E1000_DMACR, reg);
7269
7270 /*
7271 * no lower threshold to disable
7272 * coalescing(smart fifb)-UTRESH=0
7273 */
7274 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7275
7276 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7277
7278 wr32(E1000_DMCTLX, reg);
7279
7280 /*
7281 * free space in tx packet buffer to wake from
7282 * DMA coal
7283 */
7284 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7285 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7286
7287 /*
7288 * make low power state decision controlled
7289 * by DMA coal
7290 */
7291 reg = rd32(E1000_PCIEMISC);
7292 reg &= ~E1000_PCIEMISC_LX_DECISION;
7293 wr32(E1000_PCIEMISC, reg);
7294 } /* endif adapter->dmac is not disabled */
7295 } else if (hw->mac.type == e1000_82580) {
7296 u32 reg = rd32(E1000_PCIEMISC);
7297 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7298 wr32(E1000_DMACR, 0);
7299 }
7300}
7301
9d5c8243 7302/* igb_main.c */
ubuntu-zesty-kernel mirror