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Commit | Line | Data |
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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
6e861326 | 4 | Copyright(c) 2007-2012 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
876d2d6f JK |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
9d5c8243 AK |
30 | #include <linux/module.h> |
31 | #include <linux/types.h> | |
32 | #include <linux/init.h> | |
b2cb09b1 | 33 | #include <linux/bitops.h> |
9d5c8243 AK |
34 | #include <linux/vmalloc.h> |
35 | #include <linux/pagemap.h> | |
36 | #include <linux/netdevice.h> | |
9d5c8243 | 37 | #include <linux/ipv6.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
9d5c8243 AK |
39 | #include <net/checksum.h> |
40 | #include <net/ip6_checksum.h> | |
c6cb090b | 41 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
42 | #include <linux/mii.h> |
43 | #include <linux/ethtool.h> | |
01789349 | 44 | #include <linux/if.h> |
9d5c8243 AK |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/pci.h> | |
c54106bb | 47 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
48 | #include <linux/delay.h> |
49 | #include <linux/interrupt.h> | |
7d13a7d0 AD |
50 | #include <linux/ip.h> |
51 | #include <linux/tcp.h> | |
52 | #include <linux/sctp.h> | |
9d5c8243 | 53 | #include <linux/if_ether.h> |
40a914fa | 54 | #include <linux/aer.h> |
70c71606 | 55 | #include <linux/prefetch.h> |
749ab2cd | 56 | #include <linux/pm_runtime.h> |
421e02f0 | 57 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
58 | #include <linux/dca.h> |
59 | #endif | |
9d5c8243 AK |
60 | #include "igb.h" |
61 | ||
200e5fd5 CW |
62 | #define MAJ 4 |
63 | #define MIN 0 | |
3db73804 | 64 | #define BUILD 17 |
0d1fe82d | 65 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
929dd047 | 66 | __stringify(BUILD) "-k" |
9d5c8243 AK |
67 | char igb_driver_name[] = "igb"; |
68 | char igb_driver_version[] = DRV_VERSION; | |
69 | static const char igb_driver_string[] = | |
70 | "Intel(R) Gigabit Ethernet Network Driver"; | |
6e861326 | 71 | static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation."; |
9d5c8243 | 72 | |
9d5c8243 AK |
73 | static const struct e1000_info *igb_info_tbl[] = { |
74 | [board_82575] = &e1000_82575_info, | |
75 | }; | |
76 | ||
a3aa1884 | 77 | static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { |
f96a8a0b CW |
78 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, |
79 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, | |
80 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, | |
81 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, | |
82 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, | |
d2ba2ed8 AD |
83 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, |
84 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, | |
85 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, | |
86 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, | |
55cac248 AD |
87 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
88 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | |
6493d24f | 89 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, |
55cac248 AD |
90 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, |
91 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | |
92 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | |
308fb39a JG |
93 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, |
94 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, | |
1b5dda33 GJ |
95 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, |
96 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, | |
2d064c06 | 97 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 98 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
747d49ba | 99 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
2d064c06 AD |
100 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
101 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
4703bf73 | 102 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
b894fa26 | 103 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, |
c8ea5ea9 | 104 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
105 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
106 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
107 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
108 | /* required last entry */ | |
109 | {0, } | |
110 | }; | |
111 | ||
112 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
113 | ||
114 | void igb_reset(struct igb_adapter *); | |
115 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
116 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
117 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
118 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
06cf2666 | 119 | static void igb_setup_mrqc(struct igb_adapter *); |
9d5c8243 AK |
120 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); |
121 | static void __devexit igb_remove(struct pci_dev *pdev); | |
122 | static int igb_sw_init(struct igb_adapter *); | |
123 | static int igb_open(struct net_device *); | |
124 | static int igb_close(struct net_device *); | |
125 | static void igb_configure_tx(struct igb_adapter *); | |
126 | static void igb_configure_rx(struct igb_adapter *); | |
9d5c8243 AK |
127 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
128 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
129 | static void igb_clean_tx_ring(struct igb_ring *); |
130 | static void igb_clean_rx_ring(struct igb_ring *); | |
ff41f8dc | 131 | static void igb_set_rx_mode(struct net_device *); |
9d5c8243 AK |
132 | static void igb_update_phy_info(unsigned long); |
133 | static void igb_watchdog(unsigned long); | |
134 | static void igb_watchdog_task(struct work_struct *); | |
cd392f5c | 135 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); |
12dcd86b ED |
136 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, |
137 | struct rtnl_link_stats64 *stats); | |
9d5c8243 AK |
138 | static int igb_change_mtu(struct net_device *, int); |
139 | static int igb_set_mac(struct net_device *, void *); | |
68d480c4 | 140 | static void igb_set_uta(struct igb_adapter *adapter); |
9d5c8243 AK |
141 | static irqreturn_t igb_intr(int irq, void *); |
142 | static irqreturn_t igb_intr_msi(int irq, void *); | |
143 | static irqreturn_t igb_msix_other(int irq, void *); | |
047e0030 | 144 | static irqreturn_t igb_msix_ring(int irq, void *); |
421e02f0 | 145 | #ifdef CONFIG_IGB_DCA |
047e0030 | 146 | static void igb_update_dca(struct igb_q_vector *); |
fe4506b6 | 147 | static void igb_setup_dca(struct igb_adapter *); |
421e02f0 | 148 | #endif /* CONFIG_IGB_DCA */ |
661086df | 149 | static int igb_poll(struct napi_struct *, int); |
13fde97a | 150 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
cd392f5c | 151 | static bool igb_clean_rx_irq(struct igb_q_vector *, int); |
9d5c8243 AK |
152 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
153 | static void igb_tx_timeout(struct net_device *); | |
154 | static void igb_reset_task(struct work_struct *); | |
c8f44aff | 155 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); |
8e586137 JP |
156 | static int igb_vlan_rx_add_vid(struct net_device *, u16); |
157 | static int igb_vlan_rx_kill_vid(struct net_device *, u16); | |
9d5c8243 | 158 | static void igb_restore_vlan(struct igb_adapter *); |
26ad9178 | 159 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
4ae196df AD |
160 | static void igb_ping_all_vfs(struct igb_adapter *); |
161 | static void igb_msg_task(struct igb_adapter *); | |
4ae196df | 162 | static void igb_vmm_control(struct igb_adapter *); |
f2ca0dbe | 163 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
4ae196df | 164 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
8151d294 WM |
165 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); |
166 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
167 | int vf, u16 vlan, u8 qos); | |
168 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); | |
169 | static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, | |
170 | struct ifla_vf_info *ivi); | |
17dc566c | 171 | static void igb_check_vf_rate_limit(struct igb_adapter *); |
46a01698 RL |
172 | |
173 | #ifdef CONFIG_PCI_IOV | |
0224d663 | 174 | static int igb_vf_configure(struct igb_adapter *adapter, int vf); |
f557147c | 175 | static bool igb_vfs_are_assigned(struct igb_adapter *adapter); |
46a01698 | 176 | #endif |
9d5c8243 | 177 | |
9d5c8243 | 178 | #ifdef CONFIG_PM |
d9dd966d | 179 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 180 | static int igb_suspend(struct device *); |
d9dd966d | 181 | #endif |
749ab2cd YZ |
182 | static int igb_resume(struct device *); |
183 | #ifdef CONFIG_PM_RUNTIME | |
184 | static int igb_runtime_suspend(struct device *dev); | |
185 | static int igb_runtime_resume(struct device *dev); | |
186 | static int igb_runtime_idle(struct device *dev); | |
187 | #endif | |
188 | static const struct dev_pm_ops igb_pm_ops = { | |
189 | SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) | |
190 | SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, | |
191 | igb_runtime_idle) | |
192 | }; | |
9d5c8243 AK |
193 | #endif |
194 | static void igb_shutdown(struct pci_dev *); | |
421e02f0 | 195 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
196 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
197 | static struct notifier_block dca_notifier = { | |
198 | .notifier_call = igb_notify_dca, | |
199 | .next = NULL, | |
200 | .priority = 0 | |
201 | }; | |
202 | #endif | |
9d5c8243 AK |
203 | #ifdef CONFIG_NET_POLL_CONTROLLER |
204 | /* for netdump / net console */ | |
205 | static void igb_netpoll(struct net_device *); | |
206 | #endif | |
37680117 | 207 | #ifdef CONFIG_PCI_IOV |
2a3abf6d AD |
208 | static unsigned int max_vfs = 0; |
209 | module_param(max_vfs, uint, 0); | |
210 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
211 | "per physical function"); | |
212 | #endif /* CONFIG_PCI_IOV */ | |
213 | ||
9d5c8243 AK |
214 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
215 | pci_channel_state_t); | |
216 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
217 | static void igb_io_resume(struct pci_dev *); | |
218 | ||
3646f0e5 | 219 | static const struct pci_error_handlers igb_err_handler = { |
9d5c8243 AK |
220 | .error_detected = igb_io_error_detected, |
221 | .slot_reset = igb_io_slot_reset, | |
222 | .resume = igb_io_resume, | |
223 | }; | |
224 | ||
b6e0c419 | 225 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); |
9d5c8243 AK |
226 | |
227 | static struct pci_driver igb_driver = { | |
228 | .name = igb_driver_name, | |
229 | .id_table = igb_pci_tbl, | |
230 | .probe = igb_probe, | |
231 | .remove = __devexit_p(igb_remove), | |
232 | #ifdef CONFIG_PM | |
749ab2cd | 233 | .driver.pm = &igb_pm_ops, |
9d5c8243 AK |
234 | #endif |
235 | .shutdown = igb_shutdown, | |
236 | .err_handler = &igb_err_handler | |
237 | }; | |
238 | ||
239 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
240 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
241 | MODULE_LICENSE("GPL"); | |
242 | MODULE_VERSION(DRV_VERSION); | |
243 | ||
b3f4d599 | 244 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
245 | static int debug = -1; | |
246 | module_param(debug, int, 0); | |
247 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
248 | ||
c97ec42a TI |
249 | struct igb_reg_info { |
250 | u32 ofs; | |
251 | char *name; | |
252 | }; | |
253 | ||
254 | static const struct igb_reg_info igb_reg_info_tbl[] = { | |
255 | ||
256 | /* General Registers */ | |
257 | {E1000_CTRL, "CTRL"}, | |
258 | {E1000_STATUS, "STATUS"}, | |
259 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
260 | ||
261 | /* Interrupt Registers */ | |
262 | {E1000_ICR, "ICR"}, | |
263 | ||
264 | /* RX Registers */ | |
265 | {E1000_RCTL, "RCTL"}, | |
266 | {E1000_RDLEN(0), "RDLEN"}, | |
267 | {E1000_RDH(0), "RDH"}, | |
268 | {E1000_RDT(0), "RDT"}, | |
269 | {E1000_RXDCTL(0), "RXDCTL"}, | |
270 | {E1000_RDBAL(0), "RDBAL"}, | |
271 | {E1000_RDBAH(0), "RDBAH"}, | |
272 | ||
273 | /* TX Registers */ | |
274 | {E1000_TCTL, "TCTL"}, | |
275 | {E1000_TDBAL(0), "TDBAL"}, | |
276 | {E1000_TDBAH(0), "TDBAH"}, | |
277 | {E1000_TDLEN(0), "TDLEN"}, | |
278 | {E1000_TDH(0), "TDH"}, | |
279 | {E1000_TDT(0), "TDT"}, | |
280 | {E1000_TXDCTL(0), "TXDCTL"}, | |
281 | {E1000_TDFH, "TDFH"}, | |
282 | {E1000_TDFT, "TDFT"}, | |
283 | {E1000_TDFHS, "TDFHS"}, | |
284 | {E1000_TDFPC, "TDFPC"}, | |
285 | ||
286 | /* List Terminator */ | |
287 | {} | |
288 | }; | |
289 | ||
290 | /* | |
291 | * igb_regdump - register printout routine | |
292 | */ | |
293 | static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) | |
294 | { | |
295 | int n = 0; | |
296 | char rname[16]; | |
297 | u32 regs[8]; | |
298 | ||
299 | switch (reginfo->ofs) { | |
300 | case E1000_RDLEN(0): | |
301 | for (n = 0; n < 4; n++) | |
302 | regs[n] = rd32(E1000_RDLEN(n)); | |
303 | break; | |
304 | case E1000_RDH(0): | |
305 | for (n = 0; n < 4; n++) | |
306 | regs[n] = rd32(E1000_RDH(n)); | |
307 | break; | |
308 | case E1000_RDT(0): | |
309 | for (n = 0; n < 4; n++) | |
310 | regs[n] = rd32(E1000_RDT(n)); | |
311 | break; | |
312 | case E1000_RXDCTL(0): | |
313 | for (n = 0; n < 4; n++) | |
314 | regs[n] = rd32(E1000_RXDCTL(n)); | |
315 | break; | |
316 | case E1000_RDBAL(0): | |
317 | for (n = 0; n < 4; n++) | |
318 | regs[n] = rd32(E1000_RDBAL(n)); | |
319 | break; | |
320 | case E1000_RDBAH(0): | |
321 | for (n = 0; n < 4; n++) | |
322 | regs[n] = rd32(E1000_RDBAH(n)); | |
323 | break; | |
324 | case E1000_TDBAL(0): | |
325 | for (n = 0; n < 4; n++) | |
326 | regs[n] = rd32(E1000_RDBAL(n)); | |
327 | break; | |
328 | case E1000_TDBAH(0): | |
329 | for (n = 0; n < 4; n++) | |
330 | regs[n] = rd32(E1000_TDBAH(n)); | |
331 | break; | |
332 | case E1000_TDLEN(0): | |
333 | for (n = 0; n < 4; n++) | |
334 | regs[n] = rd32(E1000_TDLEN(n)); | |
335 | break; | |
336 | case E1000_TDH(0): | |
337 | for (n = 0; n < 4; n++) | |
338 | regs[n] = rd32(E1000_TDH(n)); | |
339 | break; | |
340 | case E1000_TDT(0): | |
341 | for (n = 0; n < 4; n++) | |
342 | regs[n] = rd32(E1000_TDT(n)); | |
343 | break; | |
344 | case E1000_TXDCTL(0): | |
345 | for (n = 0; n < 4; n++) | |
346 | regs[n] = rd32(E1000_TXDCTL(n)); | |
347 | break; | |
348 | default: | |
876d2d6f | 349 | pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); |
c97ec42a TI |
350 | return; |
351 | } | |
352 | ||
353 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); | |
876d2d6f JK |
354 | pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], |
355 | regs[2], regs[3]); | |
c97ec42a TI |
356 | } |
357 | ||
358 | /* | |
359 | * igb_dump - Print registers, tx-rings and rx-rings | |
360 | */ | |
361 | static void igb_dump(struct igb_adapter *adapter) | |
362 | { | |
363 | struct net_device *netdev = adapter->netdev; | |
364 | struct e1000_hw *hw = &adapter->hw; | |
365 | struct igb_reg_info *reginfo; | |
c97ec42a TI |
366 | struct igb_ring *tx_ring; |
367 | union e1000_adv_tx_desc *tx_desc; | |
368 | struct my_u0 { u64 a; u64 b; } *u0; | |
c97ec42a TI |
369 | struct igb_ring *rx_ring; |
370 | union e1000_adv_rx_desc *rx_desc; | |
371 | u32 staterr; | |
6ad4edfc | 372 | u16 i, n; |
c97ec42a TI |
373 | |
374 | if (!netif_msg_hw(adapter)) | |
375 | return; | |
376 | ||
377 | /* Print netdevice Info */ | |
378 | if (netdev) { | |
379 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
876d2d6f JK |
380 | pr_info("Device Name state trans_start " |
381 | "last_rx\n"); | |
382 | pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, | |
383 | netdev->state, netdev->trans_start, netdev->last_rx); | |
c97ec42a TI |
384 | } |
385 | ||
386 | /* Print Registers */ | |
387 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
876d2d6f | 388 | pr_info(" Register Name Value\n"); |
c97ec42a TI |
389 | for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; |
390 | reginfo->name; reginfo++) { | |
391 | igb_regdump(hw, reginfo); | |
392 | } | |
393 | ||
394 | /* Print TX Ring Summary */ | |
395 | if (!netdev || !netif_running(netdev)) | |
396 | goto exit; | |
397 | ||
398 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
876d2d6f | 399 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
c97ec42a | 400 | for (n = 0; n < adapter->num_tx_queues; n++) { |
06034649 | 401 | struct igb_tx_buffer *buffer_info; |
c97ec42a | 402 | tx_ring = adapter->tx_ring[n]; |
06034649 | 403 | buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
876d2d6f JK |
404 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
405 | n, tx_ring->next_to_use, tx_ring->next_to_clean, | |
c9f14bf3 AD |
406 | (u64)dma_unmap_addr(buffer_info, dma), |
407 | dma_unmap_len(buffer_info, len), | |
876d2d6f JK |
408 | buffer_info->next_to_watch, |
409 | (u64)buffer_info->time_stamp); | |
c97ec42a TI |
410 | } |
411 | ||
412 | /* Print TX Rings */ | |
413 | if (!netif_msg_tx_done(adapter)) | |
414 | goto rx_ring_summary; | |
415 | ||
416 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
417 | ||
418 | /* Transmit Descriptor Formats | |
419 | * | |
420 | * Advanced Transmit Descriptor | |
421 | * +--------------------------------------------------------------+ | |
422 | * 0 | Buffer Address [63:0] | | |
423 | * +--------------------------------------------------------------+ | |
424 | * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | | |
425 | * +--------------------------------------------------------------+ | |
426 | * 63 46 45 40 39 38 36 35 32 31 24 15 0 | |
427 | */ | |
428 | ||
429 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
430 | tx_ring = adapter->tx_ring[n]; | |
876d2d6f JK |
431 | pr_info("------------------------------------\n"); |
432 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
433 | pr_info("------------------------------------\n"); | |
434 | pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " | |
435 | "[bi->dma ] leng ntw timestamp " | |
436 | "bi->skb\n"); | |
c97ec42a TI |
437 | |
438 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
876d2d6f | 439 | const char *next_desc; |
06034649 | 440 | struct igb_tx_buffer *buffer_info; |
60136906 | 441 | tx_desc = IGB_TX_DESC(tx_ring, i); |
06034649 | 442 | buffer_info = &tx_ring->tx_buffer_info[i]; |
c97ec42a | 443 | u0 = (struct my_u0 *)tx_desc; |
876d2d6f JK |
444 | if (i == tx_ring->next_to_use && |
445 | i == tx_ring->next_to_clean) | |
446 | next_desc = " NTC/U"; | |
447 | else if (i == tx_ring->next_to_use) | |
448 | next_desc = " NTU"; | |
449 | else if (i == tx_ring->next_to_clean) | |
450 | next_desc = " NTC"; | |
451 | else | |
452 | next_desc = ""; | |
453 | ||
454 | pr_info("T [0x%03X] %016llX %016llX %016llX" | |
455 | " %04X %p %016llX %p%s\n", i, | |
c97ec42a TI |
456 | le64_to_cpu(u0->a), |
457 | le64_to_cpu(u0->b), | |
c9f14bf3 AD |
458 | (u64)dma_unmap_addr(buffer_info, dma), |
459 | dma_unmap_len(buffer_info, len), | |
c97ec42a TI |
460 | buffer_info->next_to_watch, |
461 | (u64)buffer_info->time_stamp, | |
876d2d6f | 462 | buffer_info->skb, next_desc); |
c97ec42a | 463 | |
b669588a | 464 | if (netif_msg_pktdata(adapter) && buffer_info->skb) |
c97ec42a TI |
465 | print_hex_dump(KERN_INFO, "", |
466 | DUMP_PREFIX_ADDRESS, | |
b669588a | 467 | 16, 1, buffer_info->skb->data, |
c9f14bf3 AD |
468 | dma_unmap_len(buffer_info, len), |
469 | true); | |
c97ec42a TI |
470 | } |
471 | } | |
472 | ||
473 | /* Print RX Rings Summary */ | |
474 | rx_ring_summary: | |
475 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
876d2d6f | 476 | pr_info("Queue [NTU] [NTC]\n"); |
c97ec42a TI |
477 | for (n = 0; n < adapter->num_rx_queues; n++) { |
478 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
479 | pr_info(" %5d %5X %5X\n", |
480 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
c97ec42a TI |
481 | } |
482 | ||
483 | /* Print RX Rings */ | |
484 | if (!netif_msg_rx_status(adapter)) | |
485 | goto exit; | |
486 | ||
487 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
488 | ||
489 | /* Advanced Receive Descriptor (Read) Format | |
490 | * 63 1 0 | |
491 | * +-----------------------------------------------------+ | |
492 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
493 | * +----------------------------------------------+------+ | |
494 | * 8 | Header Buffer Address [63:1] | DD | | |
495 | * +-----------------------------------------------------+ | |
496 | * | |
497 | * | |
498 | * Advanced Receive Descriptor (Write-Back) Format | |
499 | * | |
500 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
501 | * +------------------------------------------------------+ | |
502 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
503 | * | Checksum Ident | | | | Type | Type | | |
504 | * +------------------------------------------------------+ | |
505 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
506 | * +------------------------------------------------------+ | |
507 | * 63 48 47 32 31 20 19 0 | |
508 | */ | |
509 | ||
510 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
511 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
512 | pr_info("------------------------------------\n"); |
513 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
514 | pr_info("------------------------------------\n"); | |
515 | pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " | |
516 | "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); | |
517 | pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" | |
518 | "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); | |
c97ec42a TI |
519 | |
520 | for (i = 0; i < rx_ring->count; i++) { | |
876d2d6f | 521 | const char *next_desc; |
06034649 AD |
522 | struct igb_rx_buffer *buffer_info; |
523 | buffer_info = &rx_ring->rx_buffer_info[i]; | |
60136906 | 524 | rx_desc = IGB_RX_DESC(rx_ring, i); |
c97ec42a TI |
525 | u0 = (struct my_u0 *)rx_desc; |
526 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
876d2d6f JK |
527 | |
528 | if (i == rx_ring->next_to_use) | |
529 | next_desc = " NTU"; | |
530 | else if (i == rx_ring->next_to_clean) | |
531 | next_desc = " NTC"; | |
532 | else | |
533 | next_desc = ""; | |
534 | ||
c97ec42a TI |
535 | if (staterr & E1000_RXD_STAT_DD) { |
536 | /* Descriptor Done */ | |
1a1c225b AD |
537 | pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", |
538 | "RWB", i, | |
c97ec42a TI |
539 | le64_to_cpu(u0->a), |
540 | le64_to_cpu(u0->b), | |
1a1c225b | 541 | next_desc); |
c97ec42a | 542 | } else { |
1a1c225b AD |
543 | pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", |
544 | "R ", i, | |
c97ec42a TI |
545 | le64_to_cpu(u0->a), |
546 | le64_to_cpu(u0->b), | |
547 | (u64)buffer_info->dma, | |
1a1c225b | 548 | next_desc); |
c97ec42a | 549 | |
b669588a | 550 | if (netif_msg_pktdata(adapter) && |
1a1c225b | 551 | buffer_info->dma && buffer_info->page) { |
44390ca6 AD |
552 | print_hex_dump(KERN_INFO, "", |
553 | DUMP_PREFIX_ADDRESS, | |
554 | 16, 1, | |
b669588a ET |
555 | page_address(buffer_info->page) + |
556 | buffer_info->page_offset, | |
de78d1f9 | 557 | IGB_RX_BUFSZ, true); |
c97ec42a TI |
558 | } |
559 | } | |
c97ec42a TI |
560 | } |
561 | } | |
562 | ||
563 | exit: | |
564 | return; | |
565 | } | |
566 | ||
9d5c8243 | 567 | /** |
c041076a | 568 | * igb_get_hw_dev - return device |
9d5c8243 AK |
569 | * used by hardware layer to print debugging information |
570 | **/ | |
c041076a | 571 | struct net_device *igb_get_hw_dev(struct e1000_hw *hw) |
9d5c8243 AK |
572 | { |
573 | struct igb_adapter *adapter = hw->back; | |
c041076a | 574 | return adapter->netdev; |
9d5c8243 | 575 | } |
38c845c7 | 576 | |
9d5c8243 AK |
577 | /** |
578 | * igb_init_module - Driver Registration Routine | |
579 | * | |
580 | * igb_init_module is the first routine called when the driver is | |
581 | * loaded. All it does is register with the PCI subsystem. | |
582 | **/ | |
583 | static int __init igb_init_module(void) | |
584 | { | |
585 | int ret; | |
876d2d6f | 586 | pr_info("%s - version %s\n", |
9d5c8243 AK |
587 | igb_driver_string, igb_driver_version); |
588 | ||
876d2d6f | 589 | pr_info("%s\n", igb_copyright); |
9d5c8243 | 590 | |
421e02f0 | 591 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
592 | dca_register_notify(&dca_notifier); |
593 | #endif | |
bbd98fe4 | 594 | ret = pci_register_driver(&igb_driver); |
9d5c8243 AK |
595 | return ret; |
596 | } | |
597 | ||
598 | module_init(igb_init_module); | |
599 | ||
600 | /** | |
601 | * igb_exit_module - Driver Exit Cleanup Routine | |
602 | * | |
603 | * igb_exit_module is called just before the driver is removed | |
604 | * from memory. | |
605 | **/ | |
606 | static void __exit igb_exit_module(void) | |
607 | { | |
421e02f0 | 608 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
609 | dca_unregister_notify(&dca_notifier); |
610 | #endif | |
9d5c8243 AK |
611 | pci_unregister_driver(&igb_driver); |
612 | } | |
613 | ||
614 | module_exit(igb_exit_module); | |
615 | ||
26bc19ec AD |
616 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
617 | /** | |
618 | * igb_cache_ring_register - Descriptor ring to register mapping | |
619 | * @adapter: board private structure to initialize | |
620 | * | |
621 | * Once we know the feature-set enabled for the device, we'll cache | |
622 | * the register offset the descriptor ring is assigned to. | |
623 | **/ | |
624 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
625 | { | |
ee1b9f06 | 626 | int i = 0, j = 0; |
047e0030 | 627 | u32 rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
628 | |
629 | switch (adapter->hw.mac.type) { | |
630 | case e1000_82576: | |
631 | /* The queues are allocated for virtualization such that VF 0 | |
632 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
633 | * In order to avoid collision we start at the first free queue | |
634 | * and continue consuming queues in the same sequence | |
635 | */ | |
ee1b9f06 | 636 | if (adapter->vfs_allocated_count) { |
a99955fc | 637 | for (; i < adapter->rss_queues; i++) |
3025a446 AD |
638 | adapter->rx_ring[i]->reg_idx = rbase_offset + |
639 | Q_IDX_82576(i); | |
ee1b9f06 | 640 | } |
26bc19ec | 641 | case e1000_82575: |
55cac248 | 642 | case e1000_82580: |
d2ba2ed8 | 643 | case e1000_i350: |
f96a8a0b CW |
644 | case e1000_i210: |
645 | case e1000_i211: | |
26bc19ec | 646 | default: |
ee1b9f06 | 647 | for (; i < adapter->num_rx_queues; i++) |
3025a446 | 648 | adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
ee1b9f06 | 649 | for (; j < adapter->num_tx_queues; j++) |
3025a446 | 650 | adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
26bc19ec AD |
651 | break; |
652 | } | |
653 | } | |
654 | ||
4be000c8 AD |
655 | /** |
656 | * igb_write_ivar - configure ivar for given MSI-X vector | |
657 | * @hw: pointer to the HW structure | |
658 | * @msix_vector: vector number we are allocating to a given ring | |
659 | * @index: row index of IVAR register to write within IVAR table | |
660 | * @offset: column offset of in IVAR, should be multiple of 8 | |
661 | * | |
662 | * This function is intended to handle the writing of the IVAR register | |
663 | * for adapters 82576 and newer. The IVAR table consists of 2 columns, | |
664 | * each containing an cause allocation for an Rx and Tx ring, and a | |
665 | * variable number of rows depending on the number of queues supported. | |
666 | **/ | |
667 | static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, | |
668 | int index, int offset) | |
669 | { | |
670 | u32 ivar = array_rd32(E1000_IVAR0, index); | |
671 | ||
672 | /* clear any bits that are currently set */ | |
673 | ivar &= ~((u32)0xFF << offset); | |
674 | ||
675 | /* write vector and valid bit */ | |
676 | ivar |= (msix_vector | E1000_IVAR_VALID) << offset; | |
677 | ||
678 | array_wr32(E1000_IVAR0, index, ivar); | |
679 | } | |
680 | ||
9d5c8243 | 681 | #define IGB_N0_QUEUE -1 |
047e0030 | 682 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
9d5c8243 | 683 | { |
047e0030 | 684 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 685 | struct e1000_hw *hw = &adapter->hw; |
047e0030 AD |
686 | int rx_queue = IGB_N0_QUEUE; |
687 | int tx_queue = IGB_N0_QUEUE; | |
4be000c8 | 688 | u32 msixbm = 0; |
047e0030 | 689 | |
0ba82994 AD |
690 | if (q_vector->rx.ring) |
691 | rx_queue = q_vector->rx.ring->reg_idx; | |
692 | if (q_vector->tx.ring) | |
693 | tx_queue = q_vector->tx.ring->reg_idx; | |
2d064c06 AD |
694 | |
695 | switch (hw->mac.type) { | |
696 | case e1000_82575: | |
9d5c8243 AK |
697 | /* The 82575 assigns vectors using a bitmask, which matches the |
698 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
699 | or more queues to a vector, we write the appropriate bits | |
700 | into the MSIXBM register for that vector. */ | |
047e0030 | 701 | if (rx_queue > IGB_N0_QUEUE) |
9d5c8243 | 702 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
047e0030 | 703 | if (tx_queue > IGB_N0_QUEUE) |
9d5c8243 | 704 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
feeb2721 AD |
705 | if (!adapter->msix_entries && msix_vector == 0) |
706 | msixbm |= E1000_EIMS_OTHER; | |
9d5c8243 | 707 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
047e0030 | 708 | q_vector->eims_value = msixbm; |
2d064c06 AD |
709 | break; |
710 | case e1000_82576: | |
4be000c8 AD |
711 | /* |
712 | * 82576 uses a table that essentially consists of 2 columns | |
713 | * with 8 rows. The ordering is column-major so we use the | |
714 | * lower 3 bits as the row index, and the 4th bit as the | |
715 | * column offset. | |
716 | */ | |
717 | if (rx_queue > IGB_N0_QUEUE) | |
718 | igb_write_ivar(hw, msix_vector, | |
719 | rx_queue & 0x7, | |
720 | (rx_queue & 0x8) << 1); | |
721 | if (tx_queue > IGB_N0_QUEUE) | |
722 | igb_write_ivar(hw, msix_vector, | |
723 | tx_queue & 0x7, | |
724 | ((tx_queue & 0x8) << 1) + 8); | |
047e0030 | 725 | q_vector->eims_value = 1 << msix_vector; |
2d064c06 | 726 | break; |
55cac248 | 727 | case e1000_82580: |
d2ba2ed8 | 728 | case e1000_i350: |
f96a8a0b CW |
729 | case e1000_i210: |
730 | case e1000_i211: | |
4be000c8 AD |
731 | /* |
732 | * On 82580 and newer adapters the scheme is similar to 82576 | |
733 | * however instead of ordering column-major we have things | |
734 | * ordered row-major. So we traverse the table by using | |
735 | * bit 0 as the column offset, and the remaining bits as the | |
736 | * row index. | |
737 | */ | |
738 | if (rx_queue > IGB_N0_QUEUE) | |
739 | igb_write_ivar(hw, msix_vector, | |
740 | rx_queue >> 1, | |
741 | (rx_queue & 0x1) << 4); | |
742 | if (tx_queue > IGB_N0_QUEUE) | |
743 | igb_write_ivar(hw, msix_vector, | |
744 | tx_queue >> 1, | |
745 | ((tx_queue & 0x1) << 4) + 8); | |
55cac248 AD |
746 | q_vector->eims_value = 1 << msix_vector; |
747 | break; | |
2d064c06 AD |
748 | default: |
749 | BUG(); | |
750 | break; | |
751 | } | |
26b39276 AD |
752 | |
753 | /* add q_vector eims value to global eims_enable_mask */ | |
754 | adapter->eims_enable_mask |= q_vector->eims_value; | |
755 | ||
756 | /* configure q_vector to set itr on first interrupt */ | |
757 | q_vector->set_itr = 1; | |
9d5c8243 AK |
758 | } |
759 | ||
760 | /** | |
761 | * igb_configure_msix - Configure MSI-X hardware | |
762 | * | |
763 | * igb_configure_msix sets up the hardware to properly | |
764 | * generate MSI-X interrupts. | |
765 | **/ | |
766 | static void igb_configure_msix(struct igb_adapter *adapter) | |
767 | { | |
768 | u32 tmp; | |
769 | int i, vector = 0; | |
770 | struct e1000_hw *hw = &adapter->hw; | |
771 | ||
772 | adapter->eims_enable_mask = 0; | |
9d5c8243 AK |
773 | |
774 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
775 | switch (hw->mac.type) { |
776 | case e1000_82575: | |
9d5c8243 AK |
777 | tmp = rd32(E1000_CTRL_EXT); |
778 | /* enable MSI-X PBA support*/ | |
779 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
780 | ||
781 | /* Auto-Mask interrupts upon ICR read. */ | |
782 | tmp |= E1000_CTRL_EXT_EIAME; | |
783 | tmp |= E1000_CTRL_EXT_IRCA; | |
784 | ||
785 | wr32(E1000_CTRL_EXT, tmp); | |
047e0030 AD |
786 | |
787 | /* enable msix_other interrupt */ | |
788 | array_wr32(E1000_MSIXBM(0), vector++, | |
789 | E1000_EIMS_OTHER); | |
844290e5 | 790 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 791 | |
2d064c06 AD |
792 | break; |
793 | ||
794 | case e1000_82576: | |
55cac248 | 795 | case e1000_82580: |
d2ba2ed8 | 796 | case e1000_i350: |
f96a8a0b CW |
797 | case e1000_i210: |
798 | case e1000_i211: | |
047e0030 AD |
799 | /* Turn on MSI-X capability first, or our settings |
800 | * won't stick. And it will take days to debug. */ | |
801 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
802 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | |
803 | E1000_GPIE_NSICR); | |
804 | ||
805 | /* enable msix_other interrupt */ | |
806 | adapter->eims_other = 1 << vector; | |
2d064c06 | 807 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
2d064c06 | 808 | |
047e0030 | 809 | wr32(E1000_IVAR_MISC, tmp); |
2d064c06 AD |
810 | break; |
811 | default: | |
812 | /* do nothing, since nothing else supports MSI-X */ | |
813 | break; | |
814 | } /* switch (hw->mac.type) */ | |
047e0030 AD |
815 | |
816 | adapter->eims_enable_mask |= adapter->eims_other; | |
817 | ||
26b39276 AD |
818 | for (i = 0; i < adapter->num_q_vectors; i++) |
819 | igb_assign_vector(adapter->q_vector[i], vector++); | |
047e0030 | 820 | |
9d5c8243 AK |
821 | wrfl(); |
822 | } | |
823 | ||
824 | /** | |
825 | * igb_request_msix - Initialize MSI-X interrupts | |
826 | * | |
827 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
828 | * kernel. | |
829 | **/ | |
830 | static int igb_request_msix(struct igb_adapter *adapter) | |
831 | { | |
832 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 833 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
834 | int i, err = 0, vector = 0; |
835 | ||
047e0030 | 836 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 837 | igb_msix_other, 0, netdev->name, adapter); |
047e0030 AD |
838 | if (err) |
839 | goto out; | |
840 | vector++; | |
841 | ||
842 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
843 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
844 | ||
845 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); | |
846 | ||
0ba82994 | 847 | if (q_vector->rx.ring && q_vector->tx.ring) |
047e0030 | 848 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, |
0ba82994 AD |
849 | q_vector->rx.ring->queue_index); |
850 | else if (q_vector->tx.ring) | |
047e0030 | 851 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, |
0ba82994 AD |
852 | q_vector->tx.ring->queue_index); |
853 | else if (q_vector->rx.ring) | |
047e0030 | 854 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, |
0ba82994 | 855 | q_vector->rx.ring->queue_index); |
9d5c8243 | 856 | else |
047e0030 AD |
857 | sprintf(q_vector->name, "%s-unused", netdev->name); |
858 | ||
9d5c8243 | 859 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 860 | igb_msix_ring, 0, q_vector->name, |
047e0030 | 861 | q_vector); |
9d5c8243 AK |
862 | if (err) |
863 | goto out; | |
9d5c8243 AK |
864 | vector++; |
865 | } | |
866 | ||
9d5c8243 AK |
867 | igb_configure_msix(adapter); |
868 | return 0; | |
869 | out: | |
870 | return err; | |
871 | } | |
872 | ||
873 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
874 | { | |
875 | if (adapter->msix_entries) { | |
876 | pci_disable_msix(adapter->pdev); | |
877 | kfree(adapter->msix_entries); | |
878 | adapter->msix_entries = NULL; | |
047e0030 | 879 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 880 | pci_disable_msi(adapter->pdev); |
047e0030 | 881 | } |
9d5c8243 AK |
882 | } |
883 | ||
5536d210 AD |
884 | /** |
885 | * igb_free_q_vector - Free memory allocated for specific interrupt vector | |
886 | * @adapter: board private structure to initialize | |
887 | * @v_idx: Index of vector to be freed | |
888 | * | |
889 | * This function frees the memory allocated to the q_vector. In addition if | |
890 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
891 | * to freeing the q_vector. | |
892 | **/ | |
893 | static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) | |
894 | { | |
895 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | |
896 | ||
897 | if (q_vector->tx.ring) | |
898 | adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; | |
899 | ||
900 | if (q_vector->rx.ring) | |
901 | adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; | |
902 | ||
903 | adapter->q_vector[v_idx] = NULL; | |
904 | netif_napi_del(&q_vector->napi); | |
905 | ||
906 | /* | |
907 | * ixgbe_get_stats64() might access the rings on this vector, | |
908 | * we must wait a grace period before freeing it. | |
909 | */ | |
910 | kfree_rcu(q_vector, rcu); | |
911 | } | |
912 | ||
047e0030 AD |
913 | /** |
914 | * igb_free_q_vectors - Free memory allocated for interrupt vectors | |
915 | * @adapter: board private structure to initialize | |
916 | * | |
917 | * This function frees the memory allocated to the q_vectors. In addition if | |
918 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
919 | * to freeing the q_vector. | |
920 | **/ | |
921 | static void igb_free_q_vectors(struct igb_adapter *adapter) | |
922 | { | |
5536d210 AD |
923 | int v_idx = adapter->num_q_vectors; |
924 | ||
925 | adapter->num_tx_queues = 0; | |
926 | adapter->num_rx_queues = 0; | |
047e0030 | 927 | adapter->num_q_vectors = 0; |
5536d210 AD |
928 | |
929 | while (v_idx--) | |
930 | igb_free_q_vector(adapter, v_idx); | |
047e0030 AD |
931 | } |
932 | ||
933 | /** | |
934 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts | |
935 | * | |
936 | * This function resets the device so that it has 0 rx queues, tx queues, and | |
937 | * MSI-X interrupts allocated. | |
938 | */ | |
939 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | |
940 | { | |
047e0030 AD |
941 | igb_free_q_vectors(adapter); |
942 | igb_reset_interrupt_capability(adapter); | |
943 | } | |
9d5c8243 AK |
944 | |
945 | /** | |
946 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
947 | * | |
948 | * Attempt to configure interrupts using the best available | |
949 | * capabilities of the hardware and kernel. | |
950 | **/ | |
0c2cc02e | 951 | static void igb_set_interrupt_capability(struct igb_adapter *adapter) |
9d5c8243 AK |
952 | { |
953 | int err; | |
954 | int numvecs, i; | |
955 | ||
83b7180d | 956 | /* Number of supported queues. */ |
a99955fc | 957 | adapter->num_rx_queues = adapter->rss_queues; |
5fa8517f GR |
958 | if (adapter->vfs_allocated_count) |
959 | adapter->num_tx_queues = 1; | |
960 | else | |
961 | adapter->num_tx_queues = adapter->rss_queues; | |
83b7180d | 962 | |
047e0030 AD |
963 | /* start with one vector for every rx queue */ |
964 | numvecs = adapter->num_rx_queues; | |
965 | ||
3ad2f3fb | 966 | /* if tx handler is separate add 1 for every tx queue */ |
a99955fc AD |
967 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
968 | numvecs += adapter->num_tx_queues; | |
047e0030 AD |
969 | |
970 | /* store the number of vectors reserved for queues */ | |
971 | adapter->num_q_vectors = numvecs; | |
972 | ||
973 | /* add 1 vector for link status interrupts */ | |
974 | numvecs++; | |
9d5c8243 AK |
975 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
976 | GFP_KERNEL); | |
f96a8a0b | 977 | |
9d5c8243 AK |
978 | if (!adapter->msix_entries) |
979 | goto msi_only; | |
980 | ||
981 | for (i = 0; i < numvecs; i++) | |
982 | adapter->msix_entries[i].entry = i; | |
983 | ||
984 | err = pci_enable_msix(adapter->pdev, | |
985 | adapter->msix_entries, | |
986 | numvecs); | |
987 | if (err == 0) | |
0c2cc02e | 988 | return; |
9d5c8243 AK |
989 | |
990 | igb_reset_interrupt_capability(adapter); | |
991 | ||
992 | /* If we can't do MSI-X, try MSI */ | |
993 | msi_only: | |
2a3abf6d AD |
994 | #ifdef CONFIG_PCI_IOV |
995 | /* disable SR-IOV for non MSI-X configurations */ | |
996 | if (adapter->vf_data) { | |
997 | struct e1000_hw *hw = &adapter->hw; | |
998 | /* disable iov and allow time for transactions to clear */ | |
999 | pci_disable_sriov(adapter->pdev); | |
1000 | msleep(500); | |
1001 | ||
1002 | kfree(adapter->vf_data); | |
1003 | adapter->vf_data = NULL; | |
1004 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
945a5151 | 1005 | wrfl(); |
2a3abf6d AD |
1006 | msleep(100); |
1007 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | |
1008 | } | |
1009 | #endif | |
4fc82adf | 1010 | adapter->vfs_allocated_count = 0; |
a99955fc | 1011 | adapter->rss_queues = 1; |
4fc82adf | 1012 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
9d5c8243 | 1013 | adapter->num_rx_queues = 1; |
661086df | 1014 | adapter->num_tx_queues = 1; |
047e0030 | 1015 | adapter->num_q_vectors = 1; |
9d5c8243 | 1016 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1017 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1018 | } |
1019 | ||
5536d210 AD |
1020 | static void igb_add_ring(struct igb_ring *ring, |
1021 | struct igb_ring_container *head) | |
1022 | { | |
1023 | head->ring = ring; | |
1024 | head->count++; | |
1025 | } | |
1026 | ||
047e0030 | 1027 | /** |
5536d210 | 1028 | * igb_alloc_q_vector - Allocate memory for a single interrupt vector |
047e0030 | 1029 | * @adapter: board private structure to initialize |
5536d210 AD |
1030 | * @v_count: q_vectors allocated on adapter, used for ring interleaving |
1031 | * @v_idx: index of vector in adapter struct | |
1032 | * @txr_count: total number of Tx rings to allocate | |
1033 | * @txr_idx: index of first Tx ring to allocate | |
1034 | * @rxr_count: total number of Rx rings to allocate | |
1035 | * @rxr_idx: index of first Rx ring to allocate | |
047e0030 | 1036 | * |
5536d210 | 1037 | * We allocate one q_vector. If allocation fails we return -ENOMEM. |
047e0030 | 1038 | **/ |
5536d210 AD |
1039 | static int igb_alloc_q_vector(struct igb_adapter *adapter, |
1040 | int v_count, int v_idx, | |
1041 | int txr_count, int txr_idx, | |
1042 | int rxr_count, int rxr_idx) | |
047e0030 AD |
1043 | { |
1044 | struct igb_q_vector *q_vector; | |
5536d210 AD |
1045 | struct igb_ring *ring; |
1046 | int ring_count, size; | |
047e0030 | 1047 | |
5536d210 AD |
1048 | /* igb only supports 1 Tx and/or 1 Rx queue per vector */ |
1049 | if (txr_count > 1 || rxr_count > 1) | |
1050 | return -ENOMEM; | |
1051 | ||
1052 | ring_count = txr_count + rxr_count; | |
1053 | size = sizeof(struct igb_q_vector) + | |
1054 | (sizeof(struct igb_ring) * ring_count); | |
1055 | ||
1056 | /* allocate q_vector and rings */ | |
1057 | q_vector = kzalloc(size, GFP_KERNEL); | |
1058 | if (!q_vector) | |
1059 | return -ENOMEM; | |
1060 | ||
1061 | /* initialize NAPI */ | |
1062 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
1063 | igb_poll, 64); | |
1064 | ||
1065 | /* tie q_vector and adapter together */ | |
1066 | adapter->q_vector[v_idx] = q_vector; | |
1067 | q_vector->adapter = adapter; | |
1068 | ||
1069 | /* initialize work limits */ | |
1070 | q_vector->tx.work_limit = adapter->tx_work_limit; | |
1071 | ||
1072 | /* initialize ITR configuration */ | |
1073 | q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); | |
1074 | q_vector->itr_val = IGB_START_ITR; | |
1075 | ||
1076 | /* initialize pointer to rings */ | |
1077 | ring = q_vector->ring; | |
1078 | ||
1079 | if (txr_count) { | |
1080 | /* assign generic ring traits */ | |
1081 | ring->dev = &adapter->pdev->dev; | |
1082 | ring->netdev = adapter->netdev; | |
1083 | ||
1084 | /* configure backlink on ring */ | |
1085 | ring->q_vector = q_vector; | |
1086 | ||
1087 | /* update q_vector Tx values */ | |
1088 | igb_add_ring(ring, &q_vector->tx); | |
1089 | ||
1090 | /* For 82575, context index must be unique per ring. */ | |
1091 | if (adapter->hw.mac.type == e1000_82575) | |
1092 | set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); | |
1093 | ||
1094 | /* apply Tx specific ring traits */ | |
1095 | ring->count = adapter->tx_ring_count; | |
1096 | ring->queue_index = txr_idx; | |
1097 | ||
1098 | /* assign ring to adapter */ | |
1099 | adapter->tx_ring[txr_idx] = ring; | |
1100 | ||
1101 | /* push pointer to next ring */ | |
1102 | ring++; | |
047e0030 | 1103 | } |
81c2fc22 | 1104 | |
5536d210 AD |
1105 | if (rxr_count) { |
1106 | /* assign generic ring traits */ | |
1107 | ring->dev = &adapter->pdev->dev; | |
1108 | ring->netdev = adapter->netdev; | |
047e0030 | 1109 | |
5536d210 AD |
1110 | /* configure backlink on ring */ |
1111 | ring->q_vector = q_vector; | |
047e0030 | 1112 | |
5536d210 AD |
1113 | /* update q_vector Rx values */ |
1114 | igb_add_ring(ring, &q_vector->rx); | |
047e0030 | 1115 | |
5536d210 AD |
1116 | /* set flag indicating ring supports SCTP checksum offload */ |
1117 | if (adapter->hw.mac.type >= e1000_82576) | |
1118 | set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); | |
047e0030 | 1119 | |
5536d210 AD |
1120 | /* |
1121 | * On i350, i210, and i211, loopback VLAN packets | |
1122 | * have the tag byte-swapped. | |
1123 | * */ | |
1124 | if (adapter->hw.mac.type >= e1000_i350) | |
1125 | set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); | |
047e0030 | 1126 | |
5536d210 AD |
1127 | /* apply Rx specific ring traits */ |
1128 | ring->count = adapter->rx_ring_count; | |
1129 | ring->queue_index = rxr_idx; | |
1130 | ||
1131 | /* assign ring to adapter */ | |
1132 | adapter->rx_ring[rxr_idx] = ring; | |
1133 | } | |
1134 | ||
1135 | return 0; | |
047e0030 AD |
1136 | } |
1137 | ||
5536d210 | 1138 | |
047e0030 | 1139 | /** |
5536d210 AD |
1140 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors |
1141 | * @adapter: board private structure to initialize | |
047e0030 | 1142 | * |
5536d210 AD |
1143 | * We allocate one q_vector per queue interrupt. If allocation fails we |
1144 | * return -ENOMEM. | |
047e0030 | 1145 | **/ |
5536d210 | 1146 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) |
047e0030 | 1147 | { |
5536d210 AD |
1148 | int q_vectors = adapter->num_q_vectors; |
1149 | int rxr_remaining = adapter->num_rx_queues; | |
1150 | int txr_remaining = adapter->num_tx_queues; | |
1151 | int rxr_idx = 0, txr_idx = 0, v_idx = 0; | |
1152 | int err; | |
047e0030 | 1153 | |
5536d210 AD |
1154 | if (q_vectors >= (rxr_remaining + txr_remaining)) { |
1155 | for (; rxr_remaining; v_idx++) { | |
1156 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1157 | 0, 0, 1, rxr_idx); | |
047e0030 | 1158 | |
5536d210 AD |
1159 | if (err) |
1160 | goto err_out; | |
1161 | ||
1162 | /* update counts and index */ | |
1163 | rxr_remaining--; | |
1164 | rxr_idx++; | |
047e0030 | 1165 | } |
047e0030 | 1166 | } |
5536d210 AD |
1167 | |
1168 | for (; v_idx < q_vectors; v_idx++) { | |
1169 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); | |
1170 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); | |
1171 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1172 | tqpv, txr_idx, rqpv, rxr_idx); | |
1173 | ||
1174 | if (err) | |
1175 | goto err_out; | |
1176 | ||
1177 | /* update counts and index */ | |
1178 | rxr_remaining -= rqpv; | |
1179 | txr_remaining -= tqpv; | |
1180 | rxr_idx++; | |
1181 | txr_idx++; | |
1182 | } | |
1183 | ||
047e0030 | 1184 | return 0; |
5536d210 AD |
1185 | |
1186 | err_out: | |
1187 | adapter->num_tx_queues = 0; | |
1188 | adapter->num_rx_queues = 0; | |
1189 | adapter->num_q_vectors = 0; | |
1190 | ||
1191 | while (v_idx--) | |
1192 | igb_free_q_vector(adapter, v_idx); | |
1193 | ||
1194 | return -ENOMEM; | |
047e0030 AD |
1195 | } |
1196 | ||
1197 | /** | |
1198 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors | |
1199 | * | |
1200 | * This function initializes the interrupts and allocates all of the queues. | |
1201 | **/ | |
1202 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter) | |
1203 | { | |
1204 | struct pci_dev *pdev = adapter->pdev; | |
1205 | int err; | |
1206 | ||
0c2cc02e | 1207 | igb_set_interrupt_capability(adapter); |
047e0030 AD |
1208 | |
1209 | err = igb_alloc_q_vectors(adapter); | |
1210 | if (err) { | |
1211 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | |
1212 | goto err_alloc_q_vectors; | |
1213 | } | |
1214 | ||
5536d210 | 1215 | igb_cache_ring_register(adapter); |
047e0030 AD |
1216 | |
1217 | return 0; | |
5536d210 | 1218 | |
047e0030 AD |
1219 | err_alloc_q_vectors: |
1220 | igb_reset_interrupt_capability(adapter); | |
1221 | return err; | |
1222 | } | |
1223 | ||
9d5c8243 AK |
1224 | /** |
1225 | * igb_request_irq - initialize interrupts | |
1226 | * | |
1227 | * Attempts to configure interrupts using the best available | |
1228 | * capabilities of the hardware and kernel. | |
1229 | **/ | |
1230 | static int igb_request_irq(struct igb_adapter *adapter) | |
1231 | { | |
1232 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 1233 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
1234 | int err = 0; |
1235 | ||
1236 | if (adapter->msix_entries) { | |
1237 | err = igb_request_msix(adapter); | |
844290e5 | 1238 | if (!err) |
9d5c8243 | 1239 | goto request_done; |
9d5c8243 | 1240 | /* fall back to MSI */ |
5536d210 AD |
1241 | igb_free_all_tx_resources(adapter); |
1242 | igb_free_all_rx_resources(adapter); | |
047e0030 | 1243 | igb_clear_interrupt_scheme(adapter); |
c74d588e | 1244 | if (!pci_enable_msi(pdev)) |
7dfc16fa | 1245 | adapter->flags |= IGB_FLAG_HAS_MSI; |
047e0030 | 1246 | adapter->num_tx_queues = 1; |
9d5c8243 | 1247 | adapter->num_rx_queues = 1; |
047e0030 AD |
1248 | adapter->num_q_vectors = 1; |
1249 | err = igb_alloc_q_vectors(adapter); | |
1250 | if (err) { | |
1251 | dev_err(&pdev->dev, | |
1252 | "Unable to allocate memory for vectors\n"); | |
1253 | goto request_done; | |
1254 | } | |
047e0030 AD |
1255 | igb_setup_all_tx_resources(adapter); |
1256 | igb_setup_all_rx_resources(adapter); | |
9d5c8243 | 1257 | } |
844290e5 | 1258 | |
c74d588e AD |
1259 | igb_assign_vector(adapter->q_vector[0], 0); |
1260 | ||
7dfc16fa | 1261 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
c74d588e | 1262 | err = request_irq(pdev->irq, igb_intr_msi, 0, |
047e0030 | 1263 | netdev->name, adapter); |
9d5c8243 AK |
1264 | if (!err) |
1265 | goto request_done; | |
047e0030 | 1266 | |
9d5c8243 AK |
1267 | /* fall back to legacy interrupts */ |
1268 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 1269 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1270 | } |
1271 | ||
c74d588e | 1272 | err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, |
047e0030 | 1273 | netdev->name, adapter); |
9d5c8243 | 1274 | |
6cb5e577 | 1275 | if (err) |
c74d588e | 1276 | dev_err(&pdev->dev, "Error %d getting interrupt\n", |
9d5c8243 | 1277 | err); |
9d5c8243 AK |
1278 | |
1279 | request_done: | |
1280 | return err; | |
1281 | } | |
1282 | ||
1283 | static void igb_free_irq(struct igb_adapter *adapter) | |
1284 | { | |
9d5c8243 AK |
1285 | if (adapter->msix_entries) { |
1286 | int vector = 0, i; | |
1287 | ||
047e0030 | 1288 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
9d5c8243 | 1289 | |
0d1ae7f4 | 1290 | for (i = 0; i < adapter->num_q_vectors; i++) |
047e0030 | 1291 | free_irq(adapter->msix_entries[vector++].vector, |
0d1ae7f4 | 1292 | adapter->q_vector[i]); |
047e0030 AD |
1293 | } else { |
1294 | free_irq(adapter->pdev->irq, adapter); | |
9d5c8243 | 1295 | } |
9d5c8243 AK |
1296 | } |
1297 | ||
1298 | /** | |
1299 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
1300 | * @adapter: board private structure | |
1301 | **/ | |
1302 | static void igb_irq_disable(struct igb_adapter *adapter) | |
1303 | { | |
1304 | struct e1000_hw *hw = &adapter->hw; | |
1305 | ||
25568a53 AD |
1306 | /* |
1307 | * we need to be careful when disabling interrupts. The VFs are also | |
1308 | * mapped into these registers and so clearing the bits can cause | |
1309 | * issues on the VF drivers so we only need to clear what we set | |
1310 | */ | |
9d5c8243 | 1311 | if (adapter->msix_entries) { |
2dfd1212 AD |
1312 | u32 regval = rd32(E1000_EIAM); |
1313 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | |
1314 | wr32(E1000_EIMC, adapter->eims_enable_mask); | |
1315 | regval = rd32(E1000_EIAC); | |
1316 | wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); | |
9d5c8243 | 1317 | } |
844290e5 PW |
1318 | |
1319 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
1320 | wr32(E1000_IMC, ~0); |
1321 | wrfl(); | |
81a61859 ET |
1322 | if (adapter->msix_entries) { |
1323 | int i; | |
1324 | for (i = 0; i < adapter->num_q_vectors; i++) | |
1325 | synchronize_irq(adapter->msix_entries[i].vector); | |
1326 | } else { | |
1327 | synchronize_irq(adapter->pdev->irq); | |
1328 | } | |
9d5c8243 AK |
1329 | } |
1330 | ||
1331 | /** | |
1332 | * igb_irq_enable - Enable default interrupt generation settings | |
1333 | * @adapter: board private structure | |
1334 | **/ | |
1335 | static void igb_irq_enable(struct igb_adapter *adapter) | |
1336 | { | |
1337 | struct e1000_hw *hw = &adapter->hw; | |
1338 | ||
1339 | if (adapter->msix_entries) { | |
06218a8d | 1340 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; |
2dfd1212 AD |
1341 | u32 regval = rd32(E1000_EIAC); |
1342 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | |
1343 | regval = rd32(E1000_EIAM); | |
1344 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | |
844290e5 | 1345 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
25568a53 | 1346 | if (adapter->vfs_allocated_count) { |
4ae196df | 1347 | wr32(E1000_MBVFIMR, 0xFF); |
25568a53 AD |
1348 | ims |= E1000_IMS_VMMB; |
1349 | } | |
1350 | wr32(E1000_IMS, ims); | |
844290e5 | 1351 | } else { |
55cac248 AD |
1352 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
1353 | E1000_IMS_DRSTA); | |
1354 | wr32(E1000_IAM, IMS_ENABLE_MASK | | |
1355 | E1000_IMS_DRSTA); | |
844290e5 | 1356 | } |
9d5c8243 AK |
1357 | } |
1358 | ||
1359 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
1360 | { | |
51466239 | 1361 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1362 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
1363 | u16 old_vid = adapter->mng_vlan_id; | |
51466239 AD |
1364 | |
1365 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
1366 | /* add VID to filter table */ | |
1367 | igb_vfta_set(hw, vid, true); | |
1368 | adapter->mng_vlan_id = vid; | |
1369 | } else { | |
1370 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1371 | } | |
1372 | ||
1373 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
1374 | (vid != old_vid) && | |
b2cb09b1 | 1375 | !test_bit(old_vid, adapter->active_vlans)) { |
51466239 AD |
1376 | /* remove VID from filter table */ |
1377 | igb_vfta_set(hw, old_vid, false); | |
9d5c8243 AK |
1378 | } |
1379 | } | |
1380 | ||
1381 | /** | |
1382 | * igb_release_hw_control - release control of the h/w to f/w | |
1383 | * @adapter: address of board private structure | |
1384 | * | |
1385 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
1386 | * For ASF and Pass Through versions of f/w this means that the | |
1387 | * driver is no longer loaded. | |
1388 | * | |
1389 | **/ | |
1390 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
1391 | { | |
1392 | struct e1000_hw *hw = &adapter->hw; | |
1393 | u32 ctrl_ext; | |
1394 | ||
1395 | /* Let firmware take over control of h/w */ | |
1396 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1397 | wr32(E1000_CTRL_EXT, | |
1398 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
1399 | } | |
1400 | ||
9d5c8243 AK |
1401 | /** |
1402 | * igb_get_hw_control - get control of the h/w from f/w | |
1403 | * @adapter: address of board private structure | |
1404 | * | |
1405 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
1406 | * For ASF and Pass Through versions of f/w this means that | |
1407 | * the driver is loaded. | |
1408 | * | |
1409 | **/ | |
1410 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
1411 | { | |
1412 | struct e1000_hw *hw = &adapter->hw; | |
1413 | u32 ctrl_ext; | |
1414 | ||
1415 | /* Let firmware know the driver has taken over */ | |
1416 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1417 | wr32(E1000_CTRL_EXT, | |
1418 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
1419 | } | |
1420 | ||
9d5c8243 AK |
1421 | /** |
1422 | * igb_configure - configure the hardware for RX and TX | |
1423 | * @adapter: private board structure | |
1424 | **/ | |
1425 | static void igb_configure(struct igb_adapter *adapter) | |
1426 | { | |
1427 | struct net_device *netdev = adapter->netdev; | |
1428 | int i; | |
1429 | ||
1430 | igb_get_hw_control(adapter); | |
ff41f8dc | 1431 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
1432 | |
1433 | igb_restore_vlan(adapter); | |
9d5c8243 | 1434 | |
85b430b4 | 1435 | igb_setup_tctl(adapter); |
06cf2666 | 1436 | igb_setup_mrqc(adapter); |
9d5c8243 | 1437 | igb_setup_rctl(adapter); |
85b430b4 AD |
1438 | |
1439 | igb_configure_tx(adapter); | |
9d5c8243 | 1440 | igb_configure_rx(adapter); |
662d7205 AD |
1441 | |
1442 | igb_rx_fifo_flush_82575(&adapter->hw); | |
1443 | ||
c493ea45 | 1444 | /* call igb_desc_unused which always leaves |
9d5c8243 AK |
1445 | * at least 1 descriptor unused to make sure |
1446 | * next_to_use != next_to_clean */ | |
1447 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 1448 | struct igb_ring *ring = adapter->rx_ring[i]; |
cd392f5c | 1449 | igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); |
9d5c8243 | 1450 | } |
9d5c8243 AK |
1451 | } |
1452 | ||
88a268c1 NN |
1453 | /** |
1454 | * igb_power_up_link - Power up the phy/serdes link | |
1455 | * @adapter: address of board private structure | |
1456 | **/ | |
1457 | void igb_power_up_link(struct igb_adapter *adapter) | |
1458 | { | |
76886596 AA |
1459 | igb_reset_phy(&adapter->hw); |
1460 | ||
88a268c1 NN |
1461 | if (adapter->hw.phy.media_type == e1000_media_type_copper) |
1462 | igb_power_up_phy_copper(&adapter->hw); | |
1463 | else | |
1464 | igb_power_up_serdes_link_82575(&adapter->hw); | |
1465 | } | |
1466 | ||
1467 | /** | |
1468 | * igb_power_down_link - Power down the phy/serdes link | |
1469 | * @adapter: address of board private structure | |
1470 | */ | |
1471 | static void igb_power_down_link(struct igb_adapter *adapter) | |
1472 | { | |
1473 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1474 | igb_power_down_phy_copper_82575(&adapter->hw); | |
1475 | else | |
1476 | igb_shutdown_serdes_link_82575(&adapter->hw); | |
1477 | } | |
9d5c8243 AK |
1478 | |
1479 | /** | |
1480 | * igb_up - Open the interface and prepare it to handle traffic | |
1481 | * @adapter: board private structure | |
1482 | **/ | |
9d5c8243 AK |
1483 | int igb_up(struct igb_adapter *adapter) |
1484 | { | |
1485 | struct e1000_hw *hw = &adapter->hw; | |
1486 | int i; | |
1487 | ||
1488 | /* hardware has been reset, we need to reload some things */ | |
1489 | igb_configure(adapter); | |
1490 | ||
1491 | clear_bit(__IGB_DOWN, &adapter->state); | |
1492 | ||
0d1ae7f4 AD |
1493 | for (i = 0; i < adapter->num_q_vectors; i++) |
1494 | napi_enable(&(adapter->q_vector[i]->napi)); | |
1495 | ||
844290e5 | 1496 | if (adapter->msix_entries) |
9d5c8243 | 1497 | igb_configure_msix(adapter); |
feeb2721 AD |
1498 | else |
1499 | igb_assign_vector(adapter->q_vector[0], 0); | |
9d5c8243 AK |
1500 | |
1501 | /* Clear any pending interrupts. */ | |
1502 | rd32(E1000_ICR); | |
1503 | igb_irq_enable(adapter); | |
1504 | ||
d4960307 AD |
1505 | /* notify VFs that reset has been completed */ |
1506 | if (adapter->vfs_allocated_count) { | |
1507 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
1508 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
1509 | wr32(E1000_CTRL_EXT, reg_data); | |
1510 | } | |
1511 | ||
4cb9be7a JB |
1512 | netif_tx_start_all_queues(adapter->netdev); |
1513 | ||
25568a53 AD |
1514 | /* start the watchdog. */ |
1515 | hw->mac.get_link_status = 1; | |
1516 | schedule_work(&adapter->watchdog_task); | |
1517 | ||
9d5c8243 AK |
1518 | return 0; |
1519 | } | |
1520 | ||
1521 | void igb_down(struct igb_adapter *adapter) | |
1522 | { | |
9d5c8243 | 1523 | struct net_device *netdev = adapter->netdev; |
330a6d6a | 1524 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1525 | u32 tctl, rctl; |
1526 | int i; | |
1527 | ||
1528 | /* signal that we're down so the interrupt handler does not | |
1529 | * reschedule our watchdog timer */ | |
1530 | set_bit(__IGB_DOWN, &adapter->state); | |
1531 | ||
1532 | /* disable receives in the hardware */ | |
1533 | rctl = rd32(E1000_RCTL); | |
1534 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1535 | /* flush and sleep below */ | |
1536 | ||
fd2ea0a7 | 1537 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1538 | |
1539 | /* disable transmits in the hardware */ | |
1540 | tctl = rd32(E1000_TCTL); | |
1541 | tctl &= ~E1000_TCTL_EN; | |
1542 | wr32(E1000_TCTL, tctl); | |
1543 | /* flush both disables and wait for them to finish */ | |
1544 | wrfl(); | |
1545 | msleep(10); | |
1546 | ||
0d1ae7f4 AD |
1547 | for (i = 0; i < adapter->num_q_vectors; i++) |
1548 | napi_disable(&(adapter->q_vector[i]->napi)); | |
9d5c8243 | 1549 | |
9d5c8243 AK |
1550 | igb_irq_disable(adapter); |
1551 | ||
1552 | del_timer_sync(&adapter->watchdog_timer); | |
1553 | del_timer_sync(&adapter->phy_info_timer); | |
1554 | ||
9d5c8243 | 1555 | netif_carrier_off(netdev); |
04fe6358 AD |
1556 | |
1557 | /* record the stats before reset*/ | |
12dcd86b ED |
1558 | spin_lock(&adapter->stats64_lock); |
1559 | igb_update_stats(adapter, &adapter->stats64); | |
1560 | spin_unlock(&adapter->stats64_lock); | |
04fe6358 | 1561 | |
9d5c8243 AK |
1562 | adapter->link_speed = 0; |
1563 | adapter->link_duplex = 0; | |
1564 | ||
3023682e JK |
1565 | if (!pci_channel_offline(adapter->pdev)) |
1566 | igb_reset(adapter); | |
9d5c8243 AK |
1567 | igb_clean_all_tx_rings(adapter); |
1568 | igb_clean_all_rx_rings(adapter); | |
7e0e99ef AD |
1569 | #ifdef CONFIG_IGB_DCA |
1570 | ||
1571 | /* since we reset the hardware DCA settings were cleared */ | |
1572 | igb_setup_dca(adapter); | |
1573 | #endif | |
9d5c8243 AK |
1574 | } |
1575 | ||
1576 | void igb_reinit_locked(struct igb_adapter *adapter) | |
1577 | { | |
1578 | WARN_ON(in_interrupt()); | |
1579 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
1580 | msleep(1); | |
1581 | igb_down(adapter); | |
1582 | igb_up(adapter); | |
1583 | clear_bit(__IGB_RESETTING, &adapter->state); | |
1584 | } | |
1585 | ||
1586 | void igb_reset(struct igb_adapter *adapter) | |
1587 | { | |
090b1795 | 1588 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 1589 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 AD |
1590 | struct e1000_mac_info *mac = &hw->mac; |
1591 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
1592 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
1593 | u16 hwm; | |
1594 | ||
1595 | /* Repartition Pba for greater than 9k mtu | |
1596 | * To take effect CTRL.RST is required. | |
1597 | */ | |
fa4dfae0 | 1598 | switch (mac->type) { |
d2ba2ed8 | 1599 | case e1000_i350: |
55cac248 AD |
1600 | case e1000_82580: |
1601 | pba = rd32(E1000_RXPBS); | |
1602 | pba = igb_rxpbs_adjust_82580(pba); | |
1603 | break; | |
fa4dfae0 | 1604 | case e1000_82576: |
d249be54 AD |
1605 | pba = rd32(E1000_RXPBS); |
1606 | pba &= E1000_RXPBS_SIZE_MASK_82576; | |
fa4dfae0 AD |
1607 | break; |
1608 | case e1000_82575: | |
f96a8a0b CW |
1609 | case e1000_i210: |
1610 | case e1000_i211: | |
fa4dfae0 AD |
1611 | default: |
1612 | pba = E1000_PBA_34K; | |
1613 | break; | |
2d064c06 | 1614 | } |
9d5c8243 | 1615 | |
2d064c06 AD |
1616 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1617 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1618 | /* adjust PBA for jumbo frames */ |
1619 | wr32(E1000_PBA, pba); | |
1620 | ||
1621 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1622 | * large enough to accommodate two full transmit packets, | |
1623 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1624 | * the Rx FIFO should be large enough to accommodate at least | |
1625 | * one full receive packet and is similarly rounded up and | |
1626 | * expressed in KB. */ | |
1627 | pba = rd32(E1000_PBA); | |
1628 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1629 | tx_space = pba >> 16; | |
1630 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1631 | pba &= 0xffff; | |
1632 | /* the tx fifo also stores 16 bytes of information about the tx | |
1633 | * but don't include ethernet FCS because hardware appends it */ | |
1634 | min_tx_space = (adapter->max_frame_size + | |
85e8d004 | 1635 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1636 | ETH_FCS_LEN) * 2; |
1637 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1638 | min_tx_space >>= 10; | |
1639 | /* software strips receive CRC, so leave room for it */ | |
1640 | min_rx_space = adapter->max_frame_size; | |
1641 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1642 | min_rx_space >>= 10; | |
1643 | ||
1644 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1645 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1646 | * allocation, take space away from current Rx allocation */ | |
1647 | if (tx_space < min_tx_space && | |
1648 | ((min_tx_space - tx_space) < pba)) { | |
1649 | pba = pba - (min_tx_space - tx_space); | |
1650 | ||
1651 | /* if short on rx space, rx wins and must trump tx | |
1652 | * adjustment */ | |
1653 | if (pba < min_rx_space) | |
1654 | pba = min_rx_space; | |
1655 | } | |
2d064c06 | 1656 | wr32(E1000_PBA, pba); |
9d5c8243 | 1657 | } |
9d5c8243 AK |
1658 | |
1659 | /* flow control settings */ | |
1660 | /* The high water mark must be low enough to fit one full frame | |
1661 | * (or the size used for early receive) above it in the Rx FIFO. | |
1662 | * Set it to the lower of: | |
1663 | * - 90% of the Rx FIFO size, or | |
1664 | * - the full Rx FIFO size minus one full frame */ | |
1665 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1666 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1667 | |
d405ea3e AD |
1668 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ |
1669 | fc->low_water = fc->high_water - 16; | |
9d5c8243 AK |
1670 | fc->pause_time = 0xFFFF; |
1671 | fc->send_xon = 1; | |
0cce119a | 1672 | fc->current_mode = fc->requested_mode; |
9d5c8243 | 1673 | |
4ae196df AD |
1674 | /* disable receive for all VFs and wait one second */ |
1675 | if (adapter->vfs_allocated_count) { | |
1676 | int i; | |
1677 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
8fa7e0f7 | 1678 | adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; |
4ae196df AD |
1679 | |
1680 | /* ping all the active vfs to let them know we are going down */ | |
f2ca0dbe | 1681 | igb_ping_all_vfs(adapter); |
4ae196df AD |
1682 | |
1683 | /* disable transmits and receives */ | |
1684 | wr32(E1000_VFRE, 0); | |
1685 | wr32(E1000_VFTE, 0); | |
1686 | } | |
1687 | ||
9d5c8243 | 1688 | /* Allow time for pending master requests to run */ |
330a6d6a | 1689 | hw->mac.ops.reset_hw(hw); |
9d5c8243 AK |
1690 | wr32(E1000_WUC, 0); |
1691 | ||
330a6d6a | 1692 | if (hw->mac.ops.init_hw(hw)) |
090b1795 | 1693 | dev_err(&pdev->dev, "Hardware Error\n"); |
831ec0b4 | 1694 | |
a27416bb MV |
1695 | /* |
1696 | * Flow control settings reset on hardware reset, so guarantee flow | |
1697 | * control is off when forcing speed. | |
1698 | */ | |
1699 | if (!hw->mac.autoneg) | |
1700 | igb_force_mac_fc(hw); | |
1701 | ||
b6e0c419 | 1702 | igb_init_dmac(adapter, pba); |
88a268c1 NN |
1703 | if (!netif_running(adapter->netdev)) |
1704 | igb_power_down_link(adapter); | |
1705 | ||
9d5c8243 AK |
1706 | igb_update_mng_vlan(adapter); |
1707 | ||
1708 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1709 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1710 | ||
1f6e8178 MV |
1711 | /* Re-enable PTP, where applicable. */ |
1712 | igb_ptp_reset(adapter); | |
1f6e8178 | 1713 | |
330a6d6a | 1714 | igb_get_phy_info(hw); |
9d5c8243 AK |
1715 | } |
1716 | ||
c8f44aff MM |
1717 | static netdev_features_t igb_fix_features(struct net_device *netdev, |
1718 | netdev_features_t features) | |
b2cb09b1 JP |
1719 | { |
1720 | /* | |
1721 | * Since there is no support for separate rx/tx vlan accel | |
1722 | * enable/disable make sure tx flag is always in same state as rx. | |
1723 | */ | |
1724 | if (features & NETIF_F_HW_VLAN_RX) | |
1725 | features |= NETIF_F_HW_VLAN_TX; | |
1726 | else | |
1727 | features &= ~NETIF_F_HW_VLAN_TX; | |
1728 | ||
1729 | return features; | |
1730 | } | |
1731 | ||
c8f44aff MM |
1732 | static int igb_set_features(struct net_device *netdev, |
1733 | netdev_features_t features) | |
ac52caa3 | 1734 | { |
c8f44aff | 1735 | netdev_features_t changed = netdev->features ^ features; |
89eaefb6 | 1736 | struct igb_adapter *adapter = netdev_priv(netdev); |
ac52caa3 | 1737 | |
b2cb09b1 JP |
1738 | if (changed & NETIF_F_HW_VLAN_RX) |
1739 | igb_vlan_mode(netdev, features); | |
1740 | ||
89eaefb6 BG |
1741 | if (!(changed & NETIF_F_RXALL)) |
1742 | return 0; | |
1743 | ||
1744 | netdev->features = features; | |
1745 | ||
1746 | if (netif_running(netdev)) | |
1747 | igb_reinit_locked(adapter); | |
1748 | else | |
1749 | igb_reset(adapter); | |
1750 | ||
ac52caa3 MM |
1751 | return 0; |
1752 | } | |
1753 | ||
2e5c6922 | 1754 | static const struct net_device_ops igb_netdev_ops = { |
559e9c49 | 1755 | .ndo_open = igb_open, |
2e5c6922 | 1756 | .ndo_stop = igb_close, |
cd392f5c | 1757 | .ndo_start_xmit = igb_xmit_frame, |
12dcd86b | 1758 | .ndo_get_stats64 = igb_get_stats64, |
ff41f8dc | 1759 | .ndo_set_rx_mode = igb_set_rx_mode, |
2e5c6922 SH |
1760 | .ndo_set_mac_address = igb_set_mac, |
1761 | .ndo_change_mtu = igb_change_mtu, | |
1762 | .ndo_do_ioctl = igb_ioctl, | |
1763 | .ndo_tx_timeout = igb_tx_timeout, | |
1764 | .ndo_validate_addr = eth_validate_addr, | |
2e5c6922 SH |
1765 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, |
1766 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
8151d294 WM |
1767 | .ndo_set_vf_mac = igb_ndo_set_vf_mac, |
1768 | .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, | |
1769 | .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, | |
1770 | .ndo_get_vf_config = igb_ndo_get_vf_config, | |
2e5c6922 SH |
1771 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1772 | .ndo_poll_controller = igb_netpoll, | |
1773 | #endif | |
b2cb09b1 JP |
1774 | .ndo_fix_features = igb_fix_features, |
1775 | .ndo_set_features = igb_set_features, | |
2e5c6922 SH |
1776 | }; |
1777 | ||
d67974f0 CW |
1778 | /** |
1779 | * igb_set_fw_version - Configure version string for ethtool | |
1780 | * @adapter: adapter struct | |
1781 | * | |
1782 | **/ | |
1783 | void igb_set_fw_version(struct igb_adapter *adapter) | |
1784 | { | |
1785 | struct e1000_hw *hw = &adapter->hw; | |
0b1a6f2e CW |
1786 | struct e1000_fw_version fw; |
1787 | ||
1788 | igb_get_fw_version(hw, &fw); | |
1789 | ||
1790 | switch (hw->mac.type) { | |
1791 | case e1000_i211: | |
d67974f0 | 1792 | snprintf(adapter->fw_version, sizeof(adapter->fw_version), |
0b1a6f2e CW |
1793 | "%2d.%2d-%d", |
1794 | fw.invm_major, fw.invm_minor, fw.invm_img_type); | |
1795 | break; | |
1796 | ||
1797 | default: | |
1798 | /* if option is rom valid, display its version too */ | |
1799 | if (fw.or_valid) { | |
1800 | snprintf(adapter->fw_version, | |
1801 | sizeof(adapter->fw_version), | |
1802 | "%d.%d, 0x%08x, %d.%d.%d", | |
1803 | fw.eep_major, fw.eep_minor, fw.etrack_id, | |
1804 | fw.or_major, fw.or_build, fw.or_patch); | |
1805 | /* no option rom */ | |
1806 | } else { | |
1807 | snprintf(adapter->fw_version, | |
1808 | sizeof(adapter->fw_version), | |
1809 | "%d.%d, 0x%08x", | |
1810 | fw.eep_major, fw.eep_minor, fw.etrack_id); | |
1811 | } | |
1812 | break; | |
d67974f0 | 1813 | } |
d67974f0 CW |
1814 | return; |
1815 | } | |
1816 | ||
9d5c8243 AK |
1817 | /** |
1818 | * igb_probe - Device Initialization Routine | |
1819 | * @pdev: PCI device information struct | |
1820 | * @ent: entry in igb_pci_tbl | |
1821 | * | |
1822 | * Returns 0 on success, negative on failure | |
1823 | * | |
1824 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1825 | * The OS initialization, configuring of the adapter private structure, | |
1826 | * and a hardware reset occur. | |
1827 | **/ | |
1828 | static int __devinit igb_probe(struct pci_dev *pdev, | |
1829 | const struct pci_device_id *ent) | |
1830 | { | |
1831 | struct net_device *netdev; | |
1832 | struct igb_adapter *adapter; | |
1833 | struct e1000_hw *hw; | |
4337e993 | 1834 | u16 eeprom_data = 0; |
9835fd73 | 1835 | s32 ret_val; |
4337e993 | 1836 | static int global_quad_port_a; /* global quad port a indication */ |
9d5c8243 AK |
1837 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1838 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 1839 | int err, pci_using_dac; |
9d5c8243 | 1840 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
9835fd73 | 1841 | u8 part_str[E1000_PBANUM_LENGTH]; |
9d5c8243 | 1842 | |
bded64a7 AG |
1843 | /* Catch broken hardware that put the wrong VF device ID in |
1844 | * the PCIe SR-IOV capability. | |
1845 | */ | |
1846 | if (pdev->is_virtfn) { | |
1847 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
f96a8a0b | 1848 | pci_name(pdev), pdev->vendor, pdev->device); |
bded64a7 AG |
1849 | return -EINVAL; |
1850 | } | |
1851 | ||
aed5dec3 | 1852 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1853 | if (err) |
1854 | return err; | |
1855 | ||
1856 | pci_using_dac = 0; | |
59d71989 | 1857 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 | 1858 | if (!err) { |
59d71989 | 1859 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 AK |
1860 | if (!err) |
1861 | pci_using_dac = 1; | |
1862 | } else { | |
59d71989 | 1863 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 | 1864 | if (err) { |
59d71989 | 1865 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 AK |
1866 | if (err) { |
1867 | dev_err(&pdev->dev, "No usable DMA " | |
1868 | "configuration, aborting\n"); | |
1869 | goto err_dma; | |
1870 | } | |
1871 | } | |
1872 | } | |
1873 | ||
aed5dec3 AD |
1874 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
1875 | IORESOURCE_MEM), | |
1876 | igb_driver_name); | |
9d5c8243 AK |
1877 | if (err) |
1878 | goto err_pci_reg; | |
1879 | ||
19d5afd4 | 1880 | pci_enable_pcie_error_reporting(pdev); |
40a914fa | 1881 | |
9d5c8243 | 1882 | pci_set_master(pdev); |
c682fc23 | 1883 | pci_save_state(pdev); |
9d5c8243 AK |
1884 | |
1885 | err = -ENOMEM; | |
1bfaf07b | 1886 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1cc3bd87 | 1887 | IGB_MAX_TX_QUEUES); |
9d5c8243 AK |
1888 | if (!netdev) |
1889 | goto err_alloc_etherdev; | |
1890 | ||
1891 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1892 | ||
1893 | pci_set_drvdata(pdev, netdev); | |
1894 | adapter = netdev_priv(netdev); | |
1895 | adapter->netdev = netdev; | |
1896 | adapter->pdev = pdev; | |
1897 | hw = &adapter->hw; | |
1898 | hw->back = adapter; | |
b3f4d599 | 1899 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9d5c8243 AK |
1900 | |
1901 | mmio_start = pci_resource_start(pdev, 0); | |
1902 | mmio_len = pci_resource_len(pdev, 0); | |
1903 | ||
1904 | err = -EIO; | |
28b0759c AD |
1905 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
1906 | if (!hw->hw_addr) | |
9d5c8243 AK |
1907 | goto err_ioremap; |
1908 | ||
2e5c6922 | 1909 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 1910 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 1911 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
1912 | |
1913 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1914 | ||
1915 | netdev->mem_start = mmio_start; | |
1916 | netdev->mem_end = mmio_start + mmio_len; | |
1917 | ||
9d5c8243 AK |
1918 | /* PCI config space info */ |
1919 | hw->vendor_id = pdev->vendor; | |
1920 | hw->device_id = pdev->device; | |
1921 | hw->revision_id = pdev->revision; | |
1922 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1923 | hw->subsystem_device_id = pdev->subsystem_device; | |
1924 | ||
9d5c8243 AK |
1925 | /* Copy the default MAC, PHY and NVM function pointers */ |
1926 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1927 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1928 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1929 | /* Initialize skew-specific constants */ | |
1930 | err = ei->get_invariants(hw); | |
1931 | if (err) | |
450c87c8 | 1932 | goto err_sw_init; |
9d5c8243 | 1933 | |
450c87c8 | 1934 | /* setup the private structure */ |
9d5c8243 AK |
1935 | err = igb_sw_init(adapter); |
1936 | if (err) | |
1937 | goto err_sw_init; | |
1938 | ||
1939 | igb_get_bus_info_pcie(hw); | |
1940 | ||
1941 | hw->phy.autoneg_wait_to_complete = false; | |
9d5c8243 AK |
1942 | |
1943 | /* Copper options */ | |
1944 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1945 | hw->phy.mdix = AUTO_ALL_MODES; | |
1946 | hw->phy.disable_polarity_correction = false; | |
1947 | hw->phy.ms_type = e1000_ms_hw_default; | |
1948 | } | |
1949 | ||
1950 | if (igb_check_reset_block(hw)) | |
1951 | dev_info(&pdev->dev, | |
1952 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1953 | ||
077887c3 AD |
1954 | /* |
1955 | * features is initialized to 0 in allocation, it might have bits | |
1956 | * set by igb_sw_init so we should use an or instead of an | |
1957 | * assignment. | |
1958 | */ | |
1959 | netdev->features |= NETIF_F_SG | | |
1960 | NETIF_F_IP_CSUM | | |
1961 | NETIF_F_IPV6_CSUM | | |
1962 | NETIF_F_TSO | | |
1963 | NETIF_F_TSO6 | | |
1964 | NETIF_F_RXHASH | | |
1965 | NETIF_F_RXCSUM | | |
1966 | NETIF_F_HW_VLAN_RX | | |
1967 | NETIF_F_HW_VLAN_TX; | |
1968 | ||
1969 | /* copy netdev features into list of user selectable features */ | |
1970 | netdev->hw_features |= netdev->features; | |
89eaefb6 | 1971 | netdev->hw_features |= NETIF_F_RXALL; |
077887c3 AD |
1972 | |
1973 | /* set this bit last since it cannot be part of hw_features */ | |
1974 | netdev->features |= NETIF_F_HW_VLAN_FILTER; | |
1975 | ||
1976 | netdev->vlan_features |= NETIF_F_TSO | | |
1977 | NETIF_F_TSO6 | | |
1978 | NETIF_F_IP_CSUM | | |
1979 | NETIF_F_IPV6_CSUM | | |
1980 | NETIF_F_SG; | |
48f29ffc | 1981 | |
6b8f0922 BG |
1982 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
1983 | ||
7b872a55 | 1984 | if (pci_using_dac) { |
9d5c8243 | 1985 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
1986 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
1987 | } | |
9d5c8243 | 1988 | |
ac52caa3 MM |
1989 | if (hw->mac.type >= e1000_82576) { |
1990 | netdev->hw_features |= NETIF_F_SCTP_CSUM; | |
b9473560 | 1991 | netdev->features |= NETIF_F_SCTP_CSUM; |
ac52caa3 | 1992 | } |
b9473560 | 1993 | |
01789349 JP |
1994 | netdev->priv_flags |= IFF_UNICAST_FLT; |
1995 | ||
330a6d6a | 1996 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
9d5c8243 AK |
1997 | |
1998 | /* before reading the NVM, reset the controller to put the device in a | |
1999 | * known good starting state */ | |
2000 | hw->mac.ops.reset_hw(hw); | |
2001 | ||
f96a8a0b CW |
2002 | /* |
2003 | * make sure the NVM is good , i211 parts have special NVM that | |
2004 | * doesn't contain a checksum | |
2005 | */ | |
2006 | if (hw->mac.type != e1000_i211) { | |
2007 | if (hw->nvm.ops.validate(hw) < 0) { | |
2008 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
2009 | err = -EIO; | |
2010 | goto err_eeprom; | |
2011 | } | |
9d5c8243 AK |
2012 | } |
2013 | ||
2014 | /* copy the MAC address out of the NVM */ | |
2015 | if (hw->mac.ops.read_mac_addr(hw)) | |
2016 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
2017 | ||
2018 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
2019 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
2020 | ||
2021 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
2022 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
2023 | err = -EIO; | |
2024 | goto err_eeprom; | |
2025 | } | |
2026 | ||
d67974f0 CW |
2027 | /* get firmware version for ethtool -i */ |
2028 | igb_set_fw_version(adapter); | |
2029 | ||
c061b18d | 2030 | setup_timer(&adapter->watchdog_timer, igb_watchdog, |
0e340485 | 2031 | (unsigned long) adapter); |
c061b18d | 2032 | setup_timer(&adapter->phy_info_timer, igb_update_phy_info, |
0e340485 | 2033 | (unsigned long) adapter); |
9d5c8243 AK |
2034 | |
2035 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
2036 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
2037 | ||
450c87c8 | 2038 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
2039 | adapter->fc_autoneg = true; |
2040 | hw->mac.autoneg = true; | |
2041 | hw->phy.autoneg_advertised = 0x2f; | |
2042 | ||
0cce119a AD |
2043 | hw->fc.requested_mode = e1000_fc_default; |
2044 | hw->fc.current_mode = e1000_fc_default; | |
9d5c8243 | 2045 | |
9d5c8243 AK |
2046 | igb_validate_mdi_setting(hw); |
2047 | ||
9d5c8243 AK |
2048 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, |
2049 | * enable the ACPI Magic Packet filter | |
2050 | */ | |
2051 | ||
a2cf8b6c | 2052 | if (hw->bus.func == 0) |
312c75ae | 2053 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
6d337dce | 2054 | else if (hw->mac.type >= e1000_82580) |
55cac248 AD |
2055 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + |
2056 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
2057 | &eeprom_data); | |
a2cf8b6c AD |
2058 | else if (hw->bus.func == 1) |
2059 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 AK |
2060 | |
2061 | if (eeprom_data & eeprom_apme_mask) | |
2062 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
2063 | ||
2064 | /* now that we have the eeprom settings, apply the special cases where | |
2065 | * the eeprom may be wrong or the board simply won't support wake on | |
2066 | * lan on a particular port */ | |
2067 | switch (pdev->device) { | |
2068 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
2069 | adapter->eeprom_wol = 0; | |
2070 | break; | |
2071 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
2072 | case E1000_DEV_ID_82576_FIBER: |
2073 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
2074 | /* Wake events only supported on port A for dual fiber |
2075 | * regardless of eeprom setting */ | |
2076 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
2077 | adapter->eeprom_wol = 0; | |
2078 | break; | |
c8ea5ea9 | 2079 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 2080 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
2081 | /* if quad port adapter, disable WoL on all but port A */ |
2082 | if (global_quad_port_a != 0) | |
2083 | adapter->eeprom_wol = 0; | |
2084 | else | |
2085 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
2086 | /* Reset for multiple quad port adapters */ | |
2087 | if (++global_quad_port_a == 4) | |
2088 | global_quad_port_a = 0; | |
2089 | break; | |
9d5c8243 AK |
2090 | } |
2091 | ||
2092 | /* initialize the wol settings based on the eeprom settings */ | |
2093 | adapter->wol = adapter->eeprom_wol; | |
e1b86d84 | 2094 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9d5c8243 AK |
2095 | |
2096 | /* reset the hardware with the new settings */ | |
2097 | igb_reset(adapter); | |
2098 | ||
2099 | /* let the f/w know that the h/w is now under the control of the | |
2100 | * driver. */ | |
2101 | igb_get_hw_control(adapter); | |
2102 | ||
9d5c8243 AK |
2103 | strcpy(netdev->name, "eth%d"); |
2104 | err = register_netdev(netdev); | |
2105 | if (err) | |
2106 | goto err_register; | |
2107 | ||
b168dfc5 JB |
2108 | /* carrier off reporting is important to ethtool even BEFORE open */ |
2109 | netif_carrier_off(netdev); | |
2110 | ||
421e02f0 | 2111 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 2112 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 2113 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 | 2114 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
2115 | igb_setup_dca(adapter); |
2116 | } | |
fe4506b6 | 2117 | |
38c845c7 | 2118 | #endif |
3c89f6d0 | 2119 | |
673b8b70 | 2120 | /* do hw tstamp init after resetting */ |
7ebae817 | 2121 | igb_ptp_init(adapter); |
673b8b70 | 2122 | |
9d5c8243 AK |
2123 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
2124 | /* print bus type/speed/width info */ | |
7c510e4b | 2125 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 | 2126 | netdev->name, |
559e9c49 | 2127 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : |
ff846f52 | 2128 | (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : |
559e9c49 | 2129 | "unknown"), |
59c3de89 AD |
2130 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : |
2131 | (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : | |
2132 | (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : | |
2133 | "unknown"), | |
7c510e4b | 2134 | netdev->dev_addr); |
9d5c8243 | 2135 | |
9835fd73 CW |
2136 | ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); |
2137 | if (ret_val) | |
2138 | strcpy(part_str, "Unknown"); | |
2139 | dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); | |
9d5c8243 AK |
2140 | dev_info(&pdev->dev, |
2141 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
2142 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 2143 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 | 2144 | adapter->num_rx_queues, adapter->num_tx_queues); |
09b068d4 CW |
2145 | switch (hw->mac.type) { |
2146 | case e1000_i350: | |
f96a8a0b CW |
2147 | case e1000_i210: |
2148 | case e1000_i211: | |
09b068d4 CW |
2149 | igb_set_eee_i350(hw); |
2150 | break; | |
2151 | default: | |
2152 | break; | |
2153 | } | |
749ab2cd YZ |
2154 | |
2155 | pm_runtime_put_noidle(&pdev->dev); | |
9d5c8243 AK |
2156 | return 0; |
2157 | ||
2158 | err_register: | |
2159 | igb_release_hw_control(adapter); | |
2160 | err_eeprom: | |
2161 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 2162 | igb_reset_phy(hw); |
9d5c8243 AK |
2163 | |
2164 | if (hw->flash_address) | |
2165 | iounmap(hw->flash_address); | |
9d5c8243 | 2166 | err_sw_init: |
047e0030 | 2167 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
2168 | iounmap(hw->hw_addr); |
2169 | err_ioremap: | |
2170 | free_netdev(netdev); | |
2171 | err_alloc_etherdev: | |
559e9c49 AD |
2172 | pci_release_selected_regions(pdev, |
2173 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
2174 | err_pci_reg: |
2175 | err_dma: | |
2176 | pci_disable_device(pdev); | |
2177 | return err; | |
2178 | } | |
2179 | ||
2180 | /** | |
2181 | * igb_remove - Device Removal Routine | |
2182 | * @pdev: PCI device information struct | |
2183 | * | |
2184 | * igb_remove is called by the PCI subsystem to alert the driver | |
2185 | * that it should release a PCI device. The could be caused by a | |
2186 | * Hot-Plug event, or because the driver is going to be removed from | |
2187 | * memory. | |
2188 | **/ | |
2189 | static void __devexit igb_remove(struct pci_dev *pdev) | |
2190 | { | |
2191 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2192 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 2193 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 2194 | |
749ab2cd | 2195 | pm_runtime_get_noresume(&pdev->dev); |
a79f4f88 | 2196 | igb_ptp_stop(adapter); |
749ab2cd | 2197 | |
760141a5 TH |
2198 | /* |
2199 | * The watchdog timer may be rescheduled, so explicitly | |
2200 | * disable watchdog from being rescheduled. | |
2201 | */ | |
9d5c8243 AK |
2202 | set_bit(__IGB_DOWN, &adapter->state); |
2203 | del_timer_sync(&adapter->watchdog_timer); | |
2204 | del_timer_sync(&adapter->phy_info_timer); | |
2205 | ||
760141a5 TH |
2206 | cancel_work_sync(&adapter->reset_task); |
2207 | cancel_work_sync(&adapter->watchdog_task); | |
9d5c8243 | 2208 | |
421e02f0 | 2209 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 2210 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
2211 | dev_info(&pdev->dev, "DCA disabled\n"); |
2212 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 2213 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 2214 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
2215 | } |
2216 | #endif | |
2217 | ||
9d5c8243 AK |
2218 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
2219 | * would have already happened in close and is redundant. */ | |
2220 | igb_release_hw_control(adapter); | |
2221 | ||
2222 | unregister_netdev(netdev); | |
2223 | ||
047e0030 | 2224 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 2225 | |
37680117 AD |
2226 | #ifdef CONFIG_PCI_IOV |
2227 | /* reclaim resources allocated to VFs */ | |
2228 | if (adapter->vf_data) { | |
2229 | /* disable iov and allow time for transactions to clear */ | |
f557147c SA |
2230 | if (igb_vfs_are_assigned(adapter)) { |
2231 | dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); | |
2232 | } else { | |
0224d663 GR |
2233 | pci_disable_sriov(pdev); |
2234 | msleep(500); | |
0224d663 | 2235 | } |
37680117 AD |
2236 | |
2237 | kfree(adapter->vf_data); | |
2238 | adapter->vf_data = NULL; | |
2239 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
945a5151 | 2240 | wrfl(); |
37680117 AD |
2241 | msleep(100); |
2242 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
2243 | } | |
2244 | #endif | |
559e9c49 | 2245 | |
28b0759c AD |
2246 | iounmap(hw->hw_addr); |
2247 | if (hw->flash_address) | |
2248 | iounmap(hw->flash_address); | |
559e9c49 AD |
2249 | pci_release_selected_regions(pdev, |
2250 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 | 2251 | |
1128c756 | 2252 | kfree(adapter->shadow_vfta); |
9d5c8243 AK |
2253 | free_netdev(netdev); |
2254 | ||
19d5afd4 | 2255 | pci_disable_pcie_error_reporting(pdev); |
40a914fa | 2256 | |
9d5c8243 AK |
2257 | pci_disable_device(pdev); |
2258 | } | |
2259 | ||
a6b623e0 AD |
2260 | /** |
2261 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space | |
2262 | * @adapter: board private structure to initialize | |
2263 | * | |
2264 | * This function initializes the vf specific data storage and then attempts to | |
2265 | * allocate the VFs. The reason for ordering it this way is because it is much | |
2266 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | |
2267 | * the memory for the VFs. | |
2268 | **/ | |
2269 | static void __devinit igb_probe_vfs(struct igb_adapter * adapter) | |
2270 | { | |
2271 | #ifdef CONFIG_PCI_IOV | |
2272 | struct pci_dev *pdev = adapter->pdev; | |
f96a8a0b | 2273 | struct e1000_hw *hw = &adapter->hw; |
f557147c | 2274 | int old_vfs = pci_num_vf(adapter->pdev); |
0224d663 | 2275 | int i; |
a6b623e0 | 2276 | |
f96a8a0b CW |
2277 | /* Virtualization features not supported on i210 family. */ |
2278 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) | |
2279 | return; | |
2280 | ||
0224d663 GR |
2281 | if (old_vfs) { |
2282 | dev_info(&pdev->dev, "%d pre-allocated VFs found - override " | |
2283 | "max_vfs setting of %d\n", old_vfs, max_vfs); | |
2284 | adapter->vfs_allocated_count = old_vfs; | |
a6b623e0 AD |
2285 | } |
2286 | ||
0224d663 GR |
2287 | if (!adapter->vfs_allocated_count) |
2288 | return; | |
2289 | ||
2290 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | |
2291 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
f96a8a0b | 2292 | |
0224d663 GR |
2293 | /* if allocation failed then we do not support SR-IOV */ |
2294 | if (!adapter->vf_data) { | |
a6b623e0 | 2295 | adapter->vfs_allocated_count = 0; |
0224d663 GR |
2296 | dev_err(&pdev->dev, "Unable to allocate memory for VF " |
2297 | "Data Storage\n"); | |
2298 | goto out; | |
a6b623e0 | 2299 | } |
0224d663 GR |
2300 | |
2301 | if (!old_vfs) { | |
2302 | if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) | |
2303 | goto err_out; | |
2304 | } | |
2305 | dev_info(&pdev->dev, "%d VFs allocated\n", | |
2306 | adapter->vfs_allocated_count); | |
2307 | for (i = 0; i < adapter->vfs_allocated_count; i++) | |
2308 | igb_vf_configure(adapter, i); | |
2309 | ||
2310 | /* DMA Coalescing is not supported in IOV mode. */ | |
2311 | adapter->flags &= ~IGB_FLAG_DMAC; | |
2312 | goto out; | |
2313 | err_out: | |
2314 | kfree(adapter->vf_data); | |
2315 | adapter->vf_data = NULL; | |
2316 | adapter->vfs_allocated_count = 0; | |
2317 | out: | |
2318 | return; | |
a6b623e0 AD |
2319 | #endif /* CONFIG_PCI_IOV */ |
2320 | } | |
2321 | ||
9d5c8243 AK |
2322 | /** |
2323 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
2324 | * @adapter: board private structure to initialize | |
2325 | * | |
2326 | * igb_sw_init initializes the Adapter private data structure. | |
2327 | * Fields are initialized based on PCI device information and | |
2328 | * OS network device settings (MTU size). | |
2329 | **/ | |
2330 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
2331 | { | |
2332 | struct e1000_hw *hw = &adapter->hw; | |
2333 | struct net_device *netdev = adapter->netdev; | |
2334 | struct pci_dev *pdev = adapter->pdev; | |
374a542d | 2335 | u32 max_rss_queues; |
9d5c8243 AK |
2336 | |
2337 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
2338 | ||
13fde97a | 2339 | /* set default ring sizes */ |
68fd9910 AD |
2340 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
2341 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
13fde97a AD |
2342 | |
2343 | /* set default ITR values */ | |
4fc82adf AD |
2344 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; |
2345 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; | |
2346 | ||
13fde97a AD |
2347 | /* set default work limits */ |
2348 | adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; | |
2349 | ||
153285f9 AD |
2350 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + |
2351 | VLAN_HLEN; | |
9d5c8243 AK |
2352 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; |
2353 | ||
12dcd86b | 2354 | spin_lock_init(&adapter->stats64_lock); |
a6b623e0 | 2355 | #ifdef CONFIG_PCI_IOV |
6b78bb1d CW |
2356 | switch (hw->mac.type) { |
2357 | case e1000_82576: | |
2358 | case e1000_i350: | |
9b082d73 SA |
2359 | if (max_vfs > 7) { |
2360 | dev_warn(&pdev->dev, | |
2361 | "Maximum of 7 VFs per PF, using max\n"); | |
2362 | adapter->vfs_allocated_count = 7; | |
2363 | } else | |
2364 | adapter->vfs_allocated_count = max_vfs; | |
6b78bb1d CW |
2365 | break; |
2366 | default: | |
2367 | break; | |
2368 | } | |
a6b623e0 | 2369 | #endif /* CONFIG_PCI_IOV */ |
374a542d MV |
2370 | |
2371 | /* Determine the maximum number of RSS queues supported. */ | |
f96a8a0b | 2372 | switch (hw->mac.type) { |
374a542d MV |
2373 | case e1000_i211: |
2374 | max_rss_queues = IGB_MAX_RX_QUEUES_I211; | |
2375 | break; | |
2376 | case e1000_82575: | |
f96a8a0b | 2377 | case e1000_i210: |
374a542d MV |
2378 | max_rss_queues = IGB_MAX_RX_QUEUES_82575; |
2379 | break; | |
2380 | case e1000_i350: | |
2381 | /* I350 cannot do RSS and SR-IOV at the same time */ | |
2382 | if (!!adapter->vfs_allocated_count) { | |
2383 | max_rss_queues = 1; | |
2384 | break; | |
2385 | } | |
2386 | /* fall through */ | |
2387 | case e1000_82576: | |
2388 | if (!!adapter->vfs_allocated_count) { | |
2389 | max_rss_queues = 2; | |
2390 | break; | |
2391 | } | |
2392 | /* fall through */ | |
2393 | case e1000_82580: | |
2394 | default: | |
2395 | max_rss_queues = IGB_MAX_RX_QUEUES; | |
f96a8a0b | 2396 | break; |
374a542d MV |
2397 | } |
2398 | ||
2399 | adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); | |
2400 | ||
2401 | /* Determine if we need to pair queues. */ | |
2402 | switch (hw->mac.type) { | |
2403 | case e1000_82575: | |
f96a8a0b | 2404 | case e1000_i211: |
374a542d | 2405 | /* Device supports enough interrupts without queue pairing. */ |
f96a8a0b | 2406 | break; |
374a542d MV |
2407 | case e1000_82576: |
2408 | /* | |
2409 | * If VFs are going to be allocated with RSS queues then we | |
2410 | * should pair the queues in order to conserve interrupts due | |
2411 | * to limited supply. | |
2412 | */ | |
2413 | if ((adapter->rss_queues > 1) && | |
2414 | (adapter->vfs_allocated_count > 6)) | |
2415 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
2416 | /* fall through */ | |
2417 | case e1000_82580: | |
2418 | case e1000_i350: | |
2419 | case e1000_i210: | |
f96a8a0b | 2420 | default: |
374a542d MV |
2421 | /* |
2422 | * If rss_queues > half of max_rss_queues, pair the queues in | |
2423 | * order to conserve interrupts due to limited supply. | |
2424 | */ | |
2425 | if (adapter->rss_queues > (max_rss_queues / 2)) | |
2426 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
f96a8a0b CW |
2427 | break; |
2428 | } | |
a99955fc | 2429 | |
1128c756 CW |
2430 | /* Setup and initialize a copy of the hw vlan table array */ |
2431 | adapter->shadow_vfta = kzalloc(sizeof(u32) * | |
2432 | E1000_VLAN_FILTER_TBL_SIZE, | |
2433 | GFP_ATOMIC); | |
2434 | ||
a6b623e0 | 2435 | /* This call may decrease the number of queues */ |
047e0030 | 2436 | if (igb_init_interrupt_scheme(adapter)) { |
9d5c8243 AK |
2437 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
2438 | return -ENOMEM; | |
2439 | } | |
2440 | ||
a6b623e0 AD |
2441 | igb_probe_vfs(adapter); |
2442 | ||
9d5c8243 AK |
2443 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
2444 | igb_irq_disable(adapter); | |
2445 | ||
f96a8a0b | 2446 | if (hw->mac.type >= e1000_i350) |
831ec0b4 CW |
2447 | adapter->flags &= ~IGB_FLAG_DMAC; |
2448 | ||
9d5c8243 AK |
2449 | set_bit(__IGB_DOWN, &adapter->state); |
2450 | return 0; | |
2451 | } | |
2452 | ||
2453 | /** | |
2454 | * igb_open - Called when a network interface is made active | |
2455 | * @netdev: network interface device structure | |
2456 | * | |
2457 | * Returns 0 on success, negative value on failure | |
2458 | * | |
2459 | * The open entry point is called when a network interface is made | |
2460 | * active by the system (IFF_UP). At this point all resources needed | |
2461 | * for transmit and receive operations are allocated, the interrupt | |
2462 | * handler is registered with the OS, the watchdog timer is started, | |
2463 | * and the stack is notified that the interface is ready. | |
2464 | **/ | |
749ab2cd | 2465 | static int __igb_open(struct net_device *netdev, bool resuming) |
9d5c8243 AK |
2466 | { |
2467 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2468 | struct e1000_hw *hw = &adapter->hw; | |
749ab2cd | 2469 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2470 | int err; |
2471 | int i; | |
2472 | ||
2473 | /* disallow open during test */ | |
749ab2cd YZ |
2474 | if (test_bit(__IGB_TESTING, &adapter->state)) { |
2475 | WARN_ON(resuming); | |
9d5c8243 | 2476 | return -EBUSY; |
749ab2cd YZ |
2477 | } |
2478 | ||
2479 | if (!resuming) | |
2480 | pm_runtime_get_sync(&pdev->dev); | |
9d5c8243 | 2481 | |
b168dfc5 JB |
2482 | netif_carrier_off(netdev); |
2483 | ||
9d5c8243 AK |
2484 | /* allocate transmit descriptors */ |
2485 | err = igb_setup_all_tx_resources(adapter); | |
2486 | if (err) | |
2487 | goto err_setup_tx; | |
2488 | ||
2489 | /* allocate receive descriptors */ | |
2490 | err = igb_setup_all_rx_resources(adapter); | |
2491 | if (err) | |
2492 | goto err_setup_rx; | |
2493 | ||
88a268c1 | 2494 | igb_power_up_link(adapter); |
9d5c8243 | 2495 | |
9d5c8243 AK |
2496 | /* before we allocate an interrupt, we must be ready to handle it. |
2497 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
2498 | * as soon as we call pci_request_irq, so we have to setup our | |
2499 | * clean_rx handler before we do so. */ | |
2500 | igb_configure(adapter); | |
2501 | ||
2502 | err = igb_request_irq(adapter); | |
2503 | if (err) | |
2504 | goto err_req_irq; | |
2505 | ||
0c2cc02e AD |
2506 | /* Notify the stack of the actual queue counts. */ |
2507 | err = netif_set_real_num_tx_queues(adapter->netdev, | |
2508 | adapter->num_tx_queues); | |
2509 | if (err) | |
2510 | goto err_set_queues; | |
2511 | ||
2512 | err = netif_set_real_num_rx_queues(adapter->netdev, | |
2513 | adapter->num_rx_queues); | |
2514 | if (err) | |
2515 | goto err_set_queues; | |
2516 | ||
9d5c8243 AK |
2517 | /* From here on the code is the same as igb_up() */ |
2518 | clear_bit(__IGB_DOWN, &adapter->state); | |
2519 | ||
0d1ae7f4 AD |
2520 | for (i = 0; i < adapter->num_q_vectors; i++) |
2521 | napi_enable(&(adapter->q_vector[i]->napi)); | |
9d5c8243 AK |
2522 | |
2523 | /* Clear any pending interrupts. */ | |
2524 | rd32(E1000_ICR); | |
844290e5 PW |
2525 | |
2526 | igb_irq_enable(adapter); | |
2527 | ||
d4960307 AD |
2528 | /* notify VFs that reset has been completed */ |
2529 | if (adapter->vfs_allocated_count) { | |
2530 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
2531 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
2532 | wr32(E1000_CTRL_EXT, reg_data); | |
2533 | } | |
2534 | ||
d55b53ff JK |
2535 | netif_tx_start_all_queues(netdev); |
2536 | ||
749ab2cd YZ |
2537 | if (!resuming) |
2538 | pm_runtime_put(&pdev->dev); | |
2539 | ||
25568a53 AD |
2540 | /* start the watchdog. */ |
2541 | hw->mac.get_link_status = 1; | |
2542 | schedule_work(&adapter->watchdog_task); | |
9d5c8243 AK |
2543 | |
2544 | return 0; | |
2545 | ||
0c2cc02e AD |
2546 | err_set_queues: |
2547 | igb_free_irq(adapter); | |
9d5c8243 AK |
2548 | err_req_irq: |
2549 | igb_release_hw_control(adapter); | |
88a268c1 | 2550 | igb_power_down_link(adapter); |
9d5c8243 AK |
2551 | igb_free_all_rx_resources(adapter); |
2552 | err_setup_rx: | |
2553 | igb_free_all_tx_resources(adapter); | |
2554 | err_setup_tx: | |
2555 | igb_reset(adapter); | |
749ab2cd YZ |
2556 | if (!resuming) |
2557 | pm_runtime_put(&pdev->dev); | |
9d5c8243 AK |
2558 | |
2559 | return err; | |
2560 | } | |
2561 | ||
749ab2cd YZ |
2562 | static int igb_open(struct net_device *netdev) |
2563 | { | |
2564 | return __igb_open(netdev, false); | |
2565 | } | |
2566 | ||
9d5c8243 AK |
2567 | /** |
2568 | * igb_close - Disables a network interface | |
2569 | * @netdev: network interface device structure | |
2570 | * | |
2571 | * Returns 0, this is not allowed to fail | |
2572 | * | |
2573 | * The close entry point is called when an interface is de-activated | |
2574 | * by the OS. The hardware is still under the driver's control, but | |
2575 | * needs to be disabled. A global MAC reset is issued to stop the | |
2576 | * hardware, and all transmit and receive resources are freed. | |
2577 | **/ | |
749ab2cd | 2578 | static int __igb_close(struct net_device *netdev, bool suspending) |
9d5c8243 AK |
2579 | { |
2580 | struct igb_adapter *adapter = netdev_priv(netdev); | |
749ab2cd | 2581 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2582 | |
2583 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
9d5c8243 | 2584 | |
749ab2cd YZ |
2585 | if (!suspending) |
2586 | pm_runtime_get_sync(&pdev->dev); | |
2587 | ||
2588 | igb_down(adapter); | |
9d5c8243 AK |
2589 | igb_free_irq(adapter); |
2590 | ||
2591 | igb_free_all_tx_resources(adapter); | |
2592 | igb_free_all_rx_resources(adapter); | |
2593 | ||
749ab2cd YZ |
2594 | if (!suspending) |
2595 | pm_runtime_put_sync(&pdev->dev); | |
9d5c8243 AK |
2596 | return 0; |
2597 | } | |
2598 | ||
749ab2cd YZ |
2599 | static int igb_close(struct net_device *netdev) |
2600 | { | |
2601 | return __igb_close(netdev, false); | |
2602 | } | |
2603 | ||
9d5c8243 AK |
2604 | /** |
2605 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
9d5c8243 AK |
2606 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
2607 | * | |
2608 | * Return 0 on success, negative on failure | |
2609 | **/ | |
80785298 | 2610 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2611 | { |
59d71989 | 2612 | struct device *dev = tx_ring->dev; |
9d5c8243 AK |
2613 | int size; |
2614 | ||
06034649 | 2615 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
f33005a6 AD |
2616 | |
2617 | tx_ring->tx_buffer_info = vzalloc(size); | |
06034649 | 2618 | if (!tx_ring->tx_buffer_info) |
9d5c8243 | 2619 | goto err; |
9d5c8243 AK |
2620 | |
2621 | /* round up to nearest 4K */ | |
85e8d004 | 2622 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
2623 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
2624 | ||
5536d210 AD |
2625 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
2626 | &tx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
2627 | if (!tx_ring->desc) |
2628 | goto err; | |
2629 | ||
9d5c8243 AK |
2630 | tx_ring->next_to_use = 0; |
2631 | tx_ring->next_to_clean = 0; | |
81c2fc22 | 2632 | |
9d5c8243 AK |
2633 | return 0; |
2634 | ||
2635 | err: | |
06034649 | 2636 | vfree(tx_ring->tx_buffer_info); |
f33005a6 AD |
2637 | tx_ring->tx_buffer_info = NULL; |
2638 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); | |
9d5c8243 AK |
2639 | return -ENOMEM; |
2640 | } | |
2641 | ||
2642 | /** | |
2643 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
2644 | * (Descriptors) for all queues | |
2645 | * @adapter: board private structure | |
2646 | * | |
2647 | * Return 0 on success, negative on failure | |
2648 | **/ | |
2649 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
2650 | { | |
439705e1 | 2651 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2652 | int i, err = 0; |
2653 | ||
2654 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 2655 | err = igb_setup_tx_resources(adapter->tx_ring[i]); |
9d5c8243 | 2656 | if (err) { |
439705e1 | 2657 | dev_err(&pdev->dev, |
9d5c8243 AK |
2658 | "Allocation for Tx Queue %u failed\n", i); |
2659 | for (i--; i >= 0; i--) | |
3025a446 | 2660 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
2661 | break; |
2662 | } | |
2663 | } | |
2664 | ||
2665 | return err; | |
2666 | } | |
2667 | ||
2668 | /** | |
85b430b4 AD |
2669 | * igb_setup_tctl - configure the transmit control registers |
2670 | * @adapter: Board private structure | |
9d5c8243 | 2671 | **/ |
d7ee5b3a | 2672 | void igb_setup_tctl(struct igb_adapter *adapter) |
9d5c8243 | 2673 | { |
9d5c8243 AK |
2674 | struct e1000_hw *hw = &adapter->hw; |
2675 | u32 tctl; | |
9d5c8243 | 2676 | |
85b430b4 AD |
2677 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
2678 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
2679 | |
2680 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
2681 | tctl = rd32(E1000_TCTL); |
2682 | tctl &= ~E1000_TCTL_CT; | |
2683 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2684 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2685 | ||
2686 | igb_config_collision_dist(hw); | |
2687 | ||
9d5c8243 AK |
2688 | /* Enable transmits */ |
2689 | tctl |= E1000_TCTL_EN; | |
2690 | ||
2691 | wr32(E1000_TCTL, tctl); | |
2692 | } | |
2693 | ||
85b430b4 AD |
2694 | /** |
2695 | * igb_configure_tx_ring - Configure transmit ring after Reset | |
2696 | * @adapter: board private structure | |
2697 | * @ring: tx ring to configure | |
2698 | * | |
2699 | * Configure a transmit ring after a reset. | |
2700 | **/ | |
d7ee5b3a AD |
2701 | void igb_configure_tx_ring(struct igb_adapter *adapter, |
2702 | struct igb_ring *ring) | |
85b430b4 AD |
2703 | { |
2704 | struct e1000_hw *hw = &adapter->hw; | |
a74420e0 | 2705 | u32 txdctl = 0; |
85b430b4 AD |
2706 | u64 tdba = ring->dma; |
2707 | int reg_idx = ring->reg_idx; | |
2708 | ||
2709 | /* disable the queue */ | |
a74420e0 | 2710 | wr32(E1000_TXDCTL(reg_idx), 0); |
85b430b4 AD |
2711 | wrfl(); |
2712 | mdelay(10); | |
2713 | ||
2714 | wr32(E1000_TDLEN(reg_idx), | |
2715 | ring->count * sizeof(union e1000_adv_tx_desc)); | |
2716 | wr32(E1000_TDBAL(reg_idx), | |
2717 | tdba & 0x00000000ffffffffULL); | |
2718 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); | |
2719 | ||
fce99e34 | 2720 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); |
a74420e0 | 2721 | wr32(E1000_TDH(reg_idx), 0); |
fce99e34 | 2722 | writel(0, ring->tail); |
85b430b4 AD |
2723 | |
2724 | txdctl |= IGB_TX_PTHRESH; | |
2725 | txdctl |= IGB_TX_HTHRESH << 8; | |
2726 | txdctl |= IGB_TX_WTHRESH << 16; | |
2727 | ||
2728 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
2729 | wr32(E1000_TXDCTL(reg_idx), txdctl); | |
2730 | } | |
2731 | ||
2732 | /** | |
2733 | * igb_configure_tx - Configure transmit Unit after Reset | |
2734 | * @adapter: board private structure | |
2735 | * | |
2736 | * Configure the Tx unit of the MAC after a reset. | |
2737 | **/ | |
2738 | static void igb_configure_tx(struct igb_adapter *adapter) | |
2739 | { | |
2740 | int i; | |
2741 | ||
2742 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 2743 | igb_configure_tx_ring(adapter, adapter->tx_ring[i]); |
85b430b4 AD |
2744 | } |
2745 | ||
9d5c8243 AK |
2746 | /** |
2747 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
9d5c8243 AK |
2748 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
2749 | * | |
2750 | * Returns 0 on success, negative on failure | |
2751 | **/ | |
80785298 | 2752 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2753 | { |
59d71989 | 2754 | struct device *dev = rx_ring->dev; |
f33005a6 | 2755 | int size; |
9d5c8243 | 2756 | |
06034649 | 2757 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
f33005a6 AD |
2758 | |
2759 | rx_ring->rx_buffer_info = vzalloc(size); | |
06034649 | 2760 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 2761 | goto err; |
9d5c8243 | 2762 | |
9d5c8243 | 2763 | /* Round up to nearest 4K */ |
f33005a6 | 2764 | rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); |
9d5c8243 AK |
2765 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
2766 | ||
5536d210 AD |
2767 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
2768 | &rx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
2769 | if (!rx_ring->desc) |
2770 | goto err; | |
2771 | ||
cbc8e55f | 2772 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
2773 | rx_ring->next_to_clean = 0; |
2774 | rx_ring->next_to_use = 0; | |
9d5c8243 | 2775 | |
9d5c8243 AK |
2776 | return 0; |
2777 | ||
2778 | err: | |
06034649 AD |
2779 | vfree(rx_ring->rx_buffer_info); |
2780 | rx_ring->rx_buffer_info = NULL; | |
f33005a6 | 2781 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); |
9d5c8243 AK |
2782 | return -ENOMEM; |
2783 | } | |
2784 | ||
2785 | /** | |
2786 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
2787 | * (Descriptors) for all queues | |
2788 | * @adapter: board private structure | |
2789 | * | |
2790 | * Return 0 on success, negative on failure | |
2791 | **/ | |
2792 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
2793 | { | |
439705e1 | 2794 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2795 | int i, err = 0; |
2796 | ||
2797 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 2798 | err = igb_setup_rx_resources(adapter->rx_ring[i]); |
9d5c8243 | 2799 | if (err) { |
439705e1 | 2800 | dev_err(&pdev->dev, |
9d5c8243 AK |
2801 | "Allocation for Rx Queue %u failed\n", i); |
2802 | for (i--; i >= 0; i--) | |
3025a446 | 2803 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
2804 | break; |
2805 | } | |
2806 | } | |
2807 | ||
2808 | return err; | |
2809 | } | |
2810 | ||
06cf2666 AD |
2811 | /** |
2812 | * igb_setup_mrqc - configure the multiple receive queue control registers | |
2813 | * @adapter: Board private structure | |
2814 | **/ | |
2815 | static void igb_setup_mrqc(struct igb_adapter *adapter) | |
2816 | { | |
2817 | struct e1000_hw *hw = &adapter->hw; | |
2818 | u32 mrqc, rxcsum; | |
797fd4be | 2819 | u32 j, num_rx_queues, shift = 0; |
a57fe23e AD |
2820 | static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, |
2821 | 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, | |
2822 | 0xA32DCB77, 0x0CF23080, 0x3BB7426A, | |
2823 | 0xFA01ACBE }; | |
06cf2666 AD |
2824 | |
2825 | /* Fill out hash function seeds */ | |
a57fe23e AD |
2826 | for (j = 0; j < 10; j++) |
2827 | wr32(E1000_RSSRK(j), rsskey[j]); | |
06cf2666 | 2828 | |
a99955fc | 2829 | num_rx_queues = adapter->rss_queues; |
06cf2666 | 2830 | |
797fd4be AD |
2831 | switch (hw->mac.type) { |
2832 | case e1000_82575: | |
2833 | shift = 6; | |
2834 | break; | |
2835 | case e1000_82576: | |
2836 | /* 82576 supports 2 RSS queues for SR-IOV */ | |
2837 | if (adapter->vfs_allocated_count) { | |
06cf2666 AD |
2838 | shift = 3; |
2839 | num_rx_queues = 2; | |
06cf2666 | 2840 | } |
797fd4be AD |
2841 | break; |
2842 | default: | |
2843 | break; | |
06cf2666 AD |
2844 | } |
2845 | ||
797fd4be AD |
2846 | /* |
2847 | * Populate the indirection table 4 entries at a time. To do this | |
2848 | * we are generating the results for n and n+2 and then interleaving | |
2849 | * those with the results with n+1 and n+3. | |
2850 | */ | |
2851 | for (j = 0; j < 32; j++) { | |
2852 | /* first pass generates n and n+2 */ | |
2853 | u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; | |
2854 | u32 reta = (base & 0x07800780) >> (7 - shift); | |
2855 | ||
2856 | /* second pass generates n+1 and n+3 */ | |
2857 | base += 0x00010001 * num_rx_queues; | |
2858 | reta |= (base & 0x07800780) << (1 + shift); | |
2859 | ||
2860 | wr32(E1000_RETA(j), reta); | |
06cf2666 AD |
2861 | } |
2862 | ||
2863 | /* | |
2864 | * Disable raw packet checksumming so that RSS hash is placed in | |
2865 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum | |
2866 | * offloads as they are enabled by default | |
2867 | */ | |
2868 | rxcsum = rd32(E1000_RXCSUM); | |
2869 | rxcsum |= E1000_RXCSUM_PCSD; | |
2870 | ||
2871 | if (adapter->hw.mac.type >= e1000_82576) | |
2872 | /* Enable Receive Checksum Offload for SCTP */ | |
2873 | rxcsum |= E1000_RXCSUM_CRCOFL; | |
2874 | ||
2875 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | |
2876 | wr32(E1000_RXCSUM, rxcsum); | |
f96a8a0b CW |
2877 | /* |
2878 | * Generate RSS hash based on TCP port numbers and/or | |
2879 | * IPv4/v6 src and dst addresses since UDP cannot be | |
2880 | * hashed reliably due to IP fragmentation | |
2881 | */ | |
2882 | ||
2883 | mrqc = E1000_MRQC_RSS_FIELD_IPV4 | | |
2884 | E1000_MRQC_RSS_FIELD_IPV4_TCP | | |
2885 | E1000_MRQC_RSS_FIELD_IPV6 | | |
2886 | E1000_MRQC_RSS_FIELD_IPV6_TCP | | |
2887 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; | |
06cf2666 AD |
2888 | |
2889 | /* If VMDq is enabled then we set the appropriate mode for that, else | |
2890 | * we default to RSS so that an RSS hash is calculated per packet even | |
2891 | * if we are only using one queue */ | |
2892 | if (adapter->vfs_allocated_count) { | |
2893 | if (hw->mac.type > e1000_82575) { | |
2894 | /* Set the default pool for the PF's first queue */ | |
2895 | u32 vtctl = rd32(E1000_VT_CTL); | |
2896 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
2897 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
2898 | vtctl |= adapter->vfs_allocated_count << | |
2899 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
2900 | wr32(E1000_VT_CTL, vtctl); | |
2901 | } | |
a99955fc | 2902 | if (adapter->rss_queues > 1) |
f96a8a0b | 2903 | mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
06cf2666 | 2904 | else |
f96a8a0b | 2905 | mrqc |= E1000_MRQC_ENABLE_VMDQ; |
06cf2666 | 2906 | } else { |
f96a8a0b CW |
2907 | if (hw->mac.type != e1000_i211) |
2908 | mrqc |= E1000_MRQC_ENABLE_RSS_4Q; | |
06cf2666 AD |
2909 | } |
2910 | igb_vmm_control(adapter); | |
2911 | ||
06cf2666 AD |
2912 | wr32(E1000_MRQC, mrqc); |
2913 | } | |
2914 | ||
9d5c8243 AK |
2915 | /** |
2916 | * igb_setup_rctl - configure the receive control registers | |
2917 | * @adapter: Board private structure | |
2918 | **/ | |
d7ee5b3a | 2919 | void igb_setup_rctl(struct igb_adapter *adapter) |
9d5c8243 AK |
2920 | { |
2921 | struct e1000_hw *hw = &adapter->hw; | |
2922 | u32 rctl; | |
9d5c8243 AK |
2923 | |
2924 | rctl = rd32(E1000_RCTL); | |
2925 | ||
2926 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 2927 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 2928 | |
69d728ba | 2929 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 2930 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 2931 | |
87cb7e8c AK |
2932 | /* |
2933 | * enable stripping of CRC. It's unlikely this will break BMC | |
2934 | * redirection as it did with e1000. Newer features require | |
2935 | * that the HW strips the CRC. | |
73cd78f1 | 2936 | */ |
87cb7e8c | 2937 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 2938 | |
559e9c49 | 2939 | /* disable store bad packets and clear size bits. */ |
ec54d7d6 | 2940 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 2941 | |
6ec43fe6 AD |
2942 | /* enable LPE to prevent packets larger than max_frame_size */ |
2943 | rctl |= E1000_RCTL_LPE; | |
9d5c8243 | 2944 | |
952f72a8 AD |
2945 | /* disable queue 0 to prevent tail write w/o re-config */ |
2946 | wr32(E1000_RXDCTL(0), 0); | |
9d5c8243 | 2947 | |
e1739522 AD |
2948 | /* Attention!!! For SR-IOV PF driver operations you must enable |
2949 | * queue drop for all VF and PF queues to prevent head of line blocking | |
2950 | * if an un-trusted VF does not provide descriptors to hardware. | |
2951 | */ | |
2952 | if (adapter->vfs_allocated_count) { | |
e1739522 AD |
2953 | /* set all queue drop enable bits */ |
2954 | wr32(E1000_QDE, ALL_QUEUES); | |
e1739522 AD |
2955 | } |
2956 | ||
89eaefb6 BG |
2957 | /* This is useful for sniffing bad packets. */ |
2958 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
2959 | /* UPE and MPE will be handled by normal PROMISC logic | |
2960 | * in e1000e_set_rx_mode */ | |
2961 | rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ | |
2962 | E1000_RCTL_BAM | /* RX All Bcast Pkts */ | |
2963 | E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ | |
2964 | ||
2965 | rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ | |
2966 | E1000_RCTL_DPF | /* Allow filtered pause */ | |
2967 | E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ | |
2968 | /* Do not mess with E1000_CTRL_VME, it affects transmit as well, | |
2969 | * and that breaks VLANs. | |
2970 | */ | |
2971 | } | |
2972 | ||
9d5c8243 AK |
2973 | wr32(E1000_RCTL, rctl); |
2974 | } | |
2975 | ||
7d5753f0 AD |
2976 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
2977 | int vfn) | |
2978 | { | |
2979 | struct e1000_hw *hw = &adapter->hw; | |
2980 | u32 vmolr; | |
2981 | ||
2982 | /* if it isn't the PF check to see if VFs are enabled and | |
2983 | * increase the size to support vlan tags */ | |
2984 | if (vfn < adapter->vfs_allocated_count && | |
2985 | adapter->vf_data[vfn].vlans_enabled) | |
2986 | size += VLAN_TAG_SIZE; | |
2987 | ||
2988 | vmolr = rd32(E1000_VMOLR(vfn)); | |
2989 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
2990 | vmolr |= size | E1000_VMOLR_LPE; | |
2991 | wr32(E1000_VMOLR(vfn), vmolr); | |
2992 | ||
2993 | return 0; | |
2994 | } | |
2995 | ||
e1739522 AD |
2996 | /** |
2997 | * igb_rlpml_set - set maximum receive packet size | |
2998 | * @adapter: board private structure | |
2999 | * | |
3000 | * Configure maximum receivable packet size. | |
3001 | **/ | |
3002 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
3003 | { | |
153285f9 | 3004 | u32 max_frame_size = adapter->max_frame_size; |
e1739522 AD |
3005 | struct e1000_hw *hw = &adapter->hw; |
3006 | u16 pf_id = adapter->vfs_allocated_count; | |
3007 | ||
e1739522 AD |
3008 | if (pf_id) { |
3009 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
153285f9 AD |
3010 | /* |
3011 | * If we're in VMDQ or SR-IOV mode, then set global RLPML | |
3012 | * to our max jumbo frame size, in case we need to enable | |
3013 | * jumbo frames on one of the rings later. | |
3014 | * This will not pass over-length frames into the default | |
3015 | * queue because it's gated by the VMOLR.RLPML. | |
3016 | */ | |
7d5753f0 | 3017 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
e1739522 AD |
3018 | } |
3019 | ||
3020 | wr32(E1000_RLPML, max_frame_size); | |
3021 | } | |
3022 | ||
8151d294 WM |
3023 | static inline void igb_set_vmolr(struct igb_adapter *adapter, |
3024 | int vfn, bool aupe) | |
7d5753f0 AD |
3025 | { |
3026 | struct e1000_hw *hw = &adapter->hw; | |
3027 | u32 vmolr; | |
3028 | ||
3029 | /* | |
3030 | * This register exists only on 82576 and newer so if we are older then | |
3031 | * we should exit and do nothing | |
3032 | */ | |
3033 | if (hw->mac.type < e1000_82576) | |
3034 | return; | |
3035 | ||
3036 | vmolr = rd32(E1000_VMOLR(vfn)); | |
8151d294 WM |
3037 | vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ |
3038 | if (aupe) | |
3039 | vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ | |
3040 | else | |
3041 | vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ | |
7d5753f0 AD |
3042 | |
3043 | /* clear all bits that might not be set */ | |
3044 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | |
3045 | ||
a99955fc | 3046 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
7d5753f0 AD |
3047 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
3048 | /* | |
3049 | * for VMDq only allow the VFs and pool 0 to accept broadcast and | |
3050 | * multicast packets | |
3051 | */ | |
3052 | if (vfn <= adapter->vfs_allocated_count) | |
3053 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ | |
3054 | ||
3055 | wr32(E1000_VMOLR(vfn), vmolr); | |
3056 | } | |
3057 | ||
85b430b4 AD |
3058 | /** |
3059 | * igb_configure_rx_ring - Configure a receive ring after Reset | |
3060 | * @adapter: board private structure | |
3061 | * @ring: receive ring to be configured | |
3062 | * | |
3063 | * Configure the Rx unit of the MAC after a reset. | |
3064 | **/ | |
d7ee5b3a AD |
3065 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
3066 | struct igb_ring *ring) | |
85b430b4 AD |
3067 | { |
3068 | struct e1000_hw *hw = &adapter->hw; | |
3069 | u64 rdba = ring->dma; | |
3070 | int reg_idx = ring->reg_idx; | |
a74420e0 | 3071 | u32 srrctl = 0, rxdctl = 0; |
85b430b4 AD |
3072 | |
3073 | /* disable the queue */ | |
a74420e0 | 3074 | wr32(E1000_RXDCTL(reg_idx), 0); |
85b430b4 AD |
3075 | |
3076 | /* Set DMA base address registers */ | |
3077 | wr32(E1000_RDBAL(reg_idx), | |
3078 | rdba & 0x00000000ffffffffULL); | |
3079 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | |
3080 | wr32(E1000_RDLEN(reg_idx), | |
3081 | ring->count * sizeof(union e1000_adv_rx_desc)); | |
3082 | ||
3083 | /* initialize head and tail */ | |
fce99e34 | 3084 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); |
a74420e0 | 3085 | wr32(E1000_RDH(reg_idx), 0); |
fce99e34 | 3086 | writel(0, ring->tail); |
85b430b4 | 3087 | |
952f72a8 | 3088 | /* set descriptor configuration */ |
44390ca6 | 3089 | srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
de78d1f9 | 3090 | srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; |
1a1c225b | 3091 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; |
06218a8d | 3092 | if (hw->mac.type >= e1000_82580) |
757b77e2 | 3093 | srrctl |= E1000_SRRCTL_TIMESTAMP; |
e6bdb6fe NN |
3094 | /* Only set Drop Enable if we are supporting multiple queues */ |
3095 | if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) | |
3096 | srrctl |= E1000_SRRCTL_DROP_EN; | |
952f72a8 AD |
3097 | |
3098 | wr32(E1000_SRRCTL(reg_idx), srrctl); | |
3099 | ||
7d5753f0 | 3100 | /* set filtering for VMDQ pools */ |
8151d294 | 3101 | igb_set_vmolr(adapter, reg_idx & 0x7, true); |
7d5753f0 | 3102 | |
85b430b4 AD |
3103 | rxdctl |= IGB_RX_PTHRESH; |
3104 | rxdctl |= IGB_RX_HTHRESH << 8; | |
3105 | rxdctl |= IGB_RX_WTHRESH << 16; | |
a74420e0 AD |
3106 | |
3107 | /* enable receive descriptor fetching */ | |
3108 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
85b430b4 AD |
3109 | wr32(E1000_RXDCTL(reg_idx), rxdctl); |
3110 | } | |
3111 | ||
9d5c8243 AK |
3112 | /** |
3113 | * igb_configure_rx - Configure receive Unit after Reset | |
3114 | * @adapter: board private structure | |
3115 | * | |
3116 | * Configure the Rx unit of the MAC after a reset. | |
3117 | **/ | |
3118 | static void igb_configure_rx(struct igb_adapter *adapter) | |
3119 | { | |
9107584e | 3120 | int i; |
9d5c8243 | 3121 | |
68d480c4 AD |
3122 | /* set UTA to appropriate mode */ |
3123 | igb_set_uta(adapter); | |
3124 | ||
26ad9178 AD |
3125 | /* set the correct pool for the PF default MAC address in entry 0 */ |
3126 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, | |
3127 | adapter->vfs_allocated_count); | |
3128 | ||
06cf2666 AD |
3129 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
3130 | * the Base and Length of the Rx Descriptor Ring */ | |
3131 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3132 | igb_configure_rx_ring(adapter, adapter->rx_ring[i]); |
9d5c8243 AK |
3133 | } |
3134 | ||
3135 | /** | |
3136 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
3137 | * @tx_ring: Tx descriptor ring for a specific queue |
3138 | * | |
3139 | * Free all transmit software resources | |
3140 | **/ | |
68fd9910 | 3141 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 3142 | { |
3b644cf6 | 3143 | igb_clean_tx_ring(tx_ring); |
9d5c8243 | 3144 | |
06034649 AD |
3145 | vfree(tx_ring->tx_buffer_info); |
3146 | tx_ring->tx_buffer_info = NULL; | |
9d5c8243 | 3147 | |
439705e1 AD |
3148 | /* if not set, then don't free */ |
3149 | if (!tx_ring->desc) | |
3150 | return; | |
3151 | ||
59d71989 AD |
3152 | dma_free_coherent(tx_ring->dev, tx_ring->size, |
3153 | tx_ring->desc, tx_ring->dma); | |
9d5c8243 AK |
3154 | |
3155 | tx_ring->desc = NULL; | |
3156 | } | |
3157 | ||
3158 | /** | |
3159 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
3160 | * @adapter: board private structure | |
3161 | * | |
3162 | * Free all transmit software resources | |
3163 | **/ | |
3164 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
3165 | { | |
3166 | int i; | |
3167 | ||
3168 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3169 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
3170 | } |
3171 | ||
ebe42d16 AD |
3172 | void igb_unmap_and_free_tx_resource(struct igb_ring *ring, |
3173 | struct igb_tx_buffer *tx_buffer) | |
3174 | { | |
3175 | if (tx_buffer->skb) { | |
3176 | dev_kfree_skb_any(tx_buffer->skb); | |
c9f14bf3 | 3177 | if (dma_unmap_len(tx_buffer, len)) |
ebe42d16 | 3178 | dma_unmap_single(ring->dev, |
c9f14bf3 AD |
3179 | dma_unmap_addr(tx_buffer, dma), |
3180 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 3181 | DMA_TO_DEVICE); |
c9f14bf3 | 3182 | } else if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 3183 | dma_unmap_page(ring->dev, |
c9f14bf3 AD |
3184 | dma_unmap_addr(tx_buffer, dma), |
3185 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
3186 | DMA_TO_DEVICE); |
3187 | } | |
3188 | tx_buffer->next_to_watch = NULL; | |
3189 | tx_buffer->skb = NULL; | |
c9f14bf3 | 3190 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 | 3191 | /* buffer_info must be completely set up in the transmit path */ |
9d5c8243 AK |
3192 | } |
3193 | ||
3194 | /** | |
3195 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
3196 | * @tx_ring: ring to be cleaned |
3197 | **/ | |
3b644cf6 | 3198 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 3199 | { |
06034649 | 3200 | struct igb_tx_buffer *buffer_info; |
9d5c8243 | 3201 | unsigned long size; |
6ad4edfc | 3202 | u16 i; |
9d5c8243 | 3203 | |
06034649 | 3204 | if (!tx_ring->tx_buffer_info) |
9d5c8243 AK |
3205 | return; |
3206 | /* Free all the Tx ring sk_buffs */ | |
3207 | ||
3208 | for (i = 0; i < tx_ring->count; i++) { | |
06034649 | 3209 | buffer_info = &tx_ring->tx_buffer_info[i]; |
80785298 | 3210 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
9d5c8243 AK |
3211 | } |
3212 | ||
dad8a3b3 JF |
3213 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
3214 | ||
06034649 AD |
3215 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
3216 | memset(tx_ring->tx_buffer_info, 0, size); | |
9d5c8243 AK |
3217 | |
3218 | /* Zero out the descriptor ring */ | |
9d5c8243 AK |
3219 | memset(tx_ring->desc, 0, tx_ring->size); |
3220 | ||
3221 | tx_ring->next_to_use = 0; | |
3222 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
3223 | } |
3224 | ||
3225 | /** | |
3226 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
3227 | * @adapter: board private structure | |
3228 | **/ | |
3229 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
3230 | { | |
3231 | int i; | |
3232 | ||
3233 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3234 | igb_clean_tx_ring(adapter->tx_ring[i]); |
9d5c8243 AK |
3235 | } |
3236 | ||
3237 | /** | |
3238 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
3239 | * @rx_ring: ring to clean the resources from |
3240 | * | |
3241 | * Free all receive software resources | |
3242 | **/ | |
68fd9910 | 3243 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3244 | { |
3b644cf6 | 3245 | igb_clean_rx_ring(rx_ring); |
9d5c8243 | 3246 | |
06034649 AD |
3247 | vfree(rx_ring->rx_buffer_info); |
3248 | rx_ring->rx_buffer_info = NULL; | |
9d5c8243 | 3249 | |
439705e1 AD |
3250 | /* if not set, then don't free */ |
3251 | if (!rx_ring->desc) | |
3252 | return; | |
3253 | ||
59d71989 AD |
3254 | dma_free_coherent(rx_ring->dev, rx_ring->size, |
3255 | rx_ring->desc, rx_ring->dma); | |
9d5c8243 AK |
3256 | |
3257 | rx_ring->desc = NULL; | |
3258 | } | |
3259 | ||
3260 | /** | |
3261 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
3262 | * @adapter: board private structure | |
3263 | * | |
3264 | * Free all receive software resources | |
3265 | **/ | |
3266 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
3267 | { | |
3268 | int i; | |
3269 | ||
3270 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3271 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3272 | } |
3273 | ||
3274 | /** | |
3275 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
3276 | * @rx_ring: ring to free buffers from |
3277 | **/ | |
3b644cf6 | 3278 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 3279 | { |
9d5c8243 | 3280 | unsigned long size; |
c023cd88 | 3281 | u16 i; |
9d5c8243 | 3282 | |
1a1c225b AD |
3283 | if (rx_ring->skb) |
3284 | dev_kfree_skb(rx_ring->skb); | |
3285 | rx_ring->skb = NULL; | |
3286 | ||
06034649 | 3287 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3288 | return; |
439705e1 | 3289 | |
9d5c8243 AK |
3290 | /* Free all the Rx ring sk_buffs */ |
3291 | for (i = 0; i < rx_ring->count; i++) { | |
06034649 | 3292 | struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; |
9d5c8243 | 3293 | |
cbc8e55f AD |
3294 | if (!buffer_info->page) |
3295 | continue; | |
3296 | ||
3297 | dma_unmap_page(rx_ring->dev, | |
3298 | buffer_info->dma, | |
3299 | PAGE_SIZE, | |
3300 | DMA_FROM_DEVICE); | |
3301 | __free_page(buffer_info->page); | |
3302 | ||
1a1c225b | 3303 | buffer_info->page = NULL; |
9d5c8243 AK |
3304 | } |
3305 | ||
06034649 AD |
3306 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
3307 | memset(rx_ring->rx_buffer_info, 0, size); | |
9d5c8243 AK |
3308 | |
3309 | /* Zero out the descriptor ring */ | |
3310 | memset(rx_ring->desc, 0, rx_ring->size); | |
3311 | ||
cbc8e55f | 3312 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
3313 | rx_ring->next_to_clean = 0; |
3314 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
3315 | } |
3316 | ||
3317 | /** | |
3318 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
3319 | * @adapter: board private structure | |
3320 | **/ | |
3321 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
3322 | { | |
3323 | int i; | |
3324 | ||
3325 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3326 | igb_clean_rx_ring(adapter->rx_ring[i]); |
9d5c8243 AK |
3327 | } |
3328 | ||
3329 | /** | |
3330 | * igb_set_mac - Change the Ethernet Address of the NIC | |
3331 | * @netdev: network interface device structure | |
3332 | * @p: pointer to an address structure | |
3333 | * | |
3334 | * Returns 0 on success, negative on failure | |
3335 | **/ | |
3336 | static int igb_set_mac(struct net_device *netdev, void *p) | |
3337 | { | |
3338 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 3339 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3340 | struct sockaddr *addr = p; |
3341 | ||
3342 | if (!is_valid_ether_addr(addr->sa_data)) | |
3343 | return -EADDRNOTAVAIL; | |
3344 | ||
3345 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 3346 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 3347 | |
26ad9178 AD |
3348 | /* set the correct pool for the new PF MAC address in entry 0 */ |
3349 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, | |
3350 | adapter->vfs_allocated_count); | |
e1739522 | 3351 | |
9d5c8243 AK |
3352 | return 0; |
3353 | } | |
3354 | ||
3355 | /** | |
68d480c4 | 3356 | * igb_write_mc_addr_list - write multicast addresses to MTA |
9d5c8243 AK |
3357 | * @netdev: network interface device structure |
3358 | * | |
68d480c4 AD |
3359 | * Writes multicast address list to the MTA hash table. |
3360 | * Returns: -ENOMEM on failure | |
3361 | * 0 on no addresses written | |
3362 | * X on writing X addresses to MTA | |
9d5c8243 | 3363 | **/ |
68d480c4 | 3364 | static int igb_write_mc_addr_list(struct net_device *netdev) |
9d5c8243 AK |
3365 | { |
3366 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3367 | struct e1000_hw *hw = &adapter->hw; | |
22bedad3 | 3368 | struct netdev_hw_addr *ha; |
68d480c4 | 3369 | u8 *mta_list; |
9d5c8243 AK |
3370 | int i; |
3371 | ||
4cd24eaf | 3372 | if (netdev_mc_empty(netdev)) { |
68d480c4 AD |
3373 | /* nothing to program, so clear mc list */ |
3374 | igb_update_mc_addr_list(hw, NULL, 0); | |
3375 | igb_restore_vf_multicasts(adapter); | |
3376 | return 0; | |
3377 | } | |
9d5c8243 | 3378 | |
4cd24eaf | 3379 | mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
68d480c4 AD |
3380 | if (!mta_list) |
3381 | return -ENOMEM; | |
ff41f8dc | 3382 | |
68d480c4 | 3383 | /* The shared function expects a packed array of only addresses. */ |
48e2f183 | 3384 | i = 0; |
22bedad3 JP |
3385 | netdev_for_each_mc_addr(ha, netdev) |
3386 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); | |
68d480c4 | 3387 | |
68d480c4 AD |
3388 | igb_update_mc_addr_list(hw, mta_list, i); |
3389 | kfree(mta_list); | |
3390 | ||
4cd24eaf | 3391 | return netdev_mc_count(netdev); |
68d480c4 AD |
3392 | } |
3393 | ||
3394 | /** | |
3395 | * igb_write_uc_addr_list - write unicast addresses to RAR table | |
3396 | * @netdev: network interface device structure | |
3397 | * | |
3398 | * Writes unicast address list to the RAR table. | |
3399 | * Returns: -ENOMEM on failure/insufficient address space | |
3400 | * 0 on no addresses written | |
3401 | * X on writing X addresses to the RAR table | |
3402 | **/ | |
3403 | static int igb_write_uc_addr_list(struct net_device *netdev) | |
3404 | { | |
3405 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3406 | struct e1000_hw *hw = &adapter->hw; | |
3407 | unsigned int vfn = adapter->vfs_allocated_count; | |
3408 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | |
3409 | int count = 0; | |
3410 | ||
3411 | /* return ENOMEM indicating insufficient memory for addresses */ | |
32e7bfc4 | 3412 | if (netdev_uc_count(netdev) > rar_entries) |
68d480c4 | 3413 | return -ENOMEM; |
9d5c8243 | 3414 | |
32e7bfc4 | 3415 | if (!netdev_uc_empty(netdev) && rar_entries) { |
ff41f8dc | 3416 | struct netdev_hw_addr *ha; |
32e7bfc4 JP |
3417 | |
3418 | netdev_for_each_uc_addr(ha, netdev) { | |
ff41f8dc AD |
3419 | if (!rar_entries) |
3420 | break; | |
26ad9178 AD |
3421 | igb_rar_set_qsel(adapter, ha->addr, |
3422 | rar_entries--, | |
68d480c4 AD |
3423 | vfn); |
3424 | count++; | |
ff41f8dc AD |
3425 | } |
3426 | } | |
3427 | /* write the addresses in reverse order to avoid write combining */ | |
3428 | for (; rar_entries > 0 ; rar_entries--) { | |
3429 | wr32(E1000_RAH(rar_entries), 0); | |
3430 | wr32(E1000_RAL(rar_entries), 0); | |
3431 | } | |
3432 | wrfl(); | |
3433 | ||
68d480c4 AD |
3434 | return count; |
3435 | } | |
3436 | ||
3437 | /** | |
3438 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set | |
3439 | * @netdev: network interface device structure | |
3440 | * | |
3441 | * The set_rx_mode entry point is called whenever the unicast or multicast | |
3442 | * address lists or the network interface flags are updated. This routine is | |
3443 | * responsible for configuring the hardware for proper unicast, multicast, | |
3444 | * promiscuous mode, and all-multi behavior. | |
3445 | **/ | |
3446 | static void igb_set_rx_mode(struct net_device *netdev) | |
3447 | { | |
3448 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3449 | struct e1000_hw *hw = &adapter->hw; | |
3450 | unsigned int vfn = adapter->vfs_allocated_count; | |
3451 | u32 rctl, vmolr = 0; | |
3452 | int count; | |
3453 | ||
3454 | /* Check for Promiscuous and All Multicast modes */ | |
3455 | rctl = rd32(E1000_RCTL); | |
3456 | ||
3457 | /* clear the effected bits */ | |
3458 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | |
3459 | ||
3460 | if (netdev->flags & IFF_PROMISC) { | |
3461 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
3462 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | |
3463 | } else { | |
3464 | if (netdev->flags & IFF_ALLMULTI) { | |
3465 | rctl |= E1000_RCTL_MPE; | |
3466 | vmolr |= E1000_VMOLR_MPME; | |
3467 | } else { | |
3468 | /* | |
3469 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3470 | * then we should just turn on promiscuous mode so |
68d480c4 AD |
3471 | * that we can at least receive multicast traffic |
3472 | */ | |
3473 | count = igb_write_mc_addr_list(netdev); | |
3474 | if (count < 0) { | |
3475 | rctl |= E1000_RCTL_MPE; | |
3476 | vmolr |= E1000_VMOLR_MPME; | |
3477 | } else if (count) { | |
3478 | vmolr |= E1000_VMOLR_ROMPE; | |
3479 | } | |
3480 | } | |
3481 | /* | |
3482 | * Write addresses to available RAR registers, if there is not | |
3483 | * sufficient space to store all the addresses then enable | |
25985edc | 3484 | * unicast promiscuous mode |
68d480c4 AD |
3485 | */ |
3486 | count = igb_write_uc_addr_list(netdev); | |
3487 | if (count < 0) { | |
3488 | rctl |= E1000_RCTL_UPE; | |
3489 | vmolr |= E1000_VMOLR_ROPE; | |
3490 | } | |
3491 | rctl |= E1000_RCTL_VFE; | |
28fc06f5 | 3492 | } |
68d480c4 | 3493 | wr32(E1000_RCTL, rctl); |
28fc06f5 | 3494 | |
68d480c4 AD |
3495 | /* |
3496 | * In order to support SR-IOV and eventually VMDq it is necessary to set | |
3497 | * the VMOLR to enable the appropriate modes. Without this workaround | |
3498 | * we will have issues with VLAN tag stripping not being done for frames | |
3499 | * that are only arriving because we are the default pool | |
3500 | */ | |
f96a8a0b | 3501 | if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) |
28fc06f5 | 3502 | return; |
9d5c8243 | 3503 | |
68d480c4 AD |
3504 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
3505 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); | |
3506 | wr32(E1000_VMOLR(vfn), vmolr); | |
28fc06f5 | 3507 | igb_restore_vf_multicasts(adapter); |
9d5c8243 AK |
3508 | } |
3509 | ||
13800469 GR |
3510 | static void igb_check_wvbr(struct igb_adapter *adapter) |
3511 | { | |
3512 | struct e1000_hw *hw = &adapter->hw; | |
3513 | u32 wvbr = 0; | |
3514 | ||
3515 | switch (hw->mac.type) { | |
3516 | case e1000_82576: | |
3517 | case e1000_i350: | |
3518 | if (!(wvbr = rd32(E1000_WVBR))) | |
3519 | return; | |
3520 | break; | |
3521 | default: | |
3522 | break; | |
3523 | } | |
3524 | ||
3525 | adapter->wvbr |= wvbr; | |
3526 | } | |
3527 | ||
3528 | #define IGB_STAGGERED_QUEUE_OFFSET 8 | |
3529 | ||
3530 | static void igb_spoof_check(struct igb_adapter *adapter) | |
3531 | { | |
3532 | int j; | |
3533 | ||
3534 | if (!adapter->wvbr) | |
3535 | return; | |
3536 | ||
3537 | for(j = 0; j < adapter->vfs_allocated_count; j++) { | |
3538 | if (adapter->wvbr & (1 << j) || | |
3539 | adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { | |
3540 | dev_warn(&adapter->pdev->dev, | |
3541 | "Spoof event(s) detected on VF %d\n", j); | |
3542 | adapter->wvbr &= | |
3543 | ~((1 << j) | | |
3544 | (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); | |
3545 | } | |
3546 | } | |
3547 | } | |
3548 | ||
9d5c8243 AK |
3549 | /* Need to wait a few seconds after link up to get diagnostic information from |
3550 | * the phy */ | |
3551 | static void igb_update_phy_info(unsigned long data) | |
3552 | { | |
3553 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 3554 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
3555 | } |
3556 | ||
4d6b725e AD |
3557 | /** |
3558 | * igb_has_link - check shared code for link and determine up/down | |
3559 | * @adapter: pointer to driver private info | |
3560 | **/ | |
3145535a | 3561 | bool igb_has_link(struct igb_adapter *adapter) |
4d6b725e AD |
3562 | { |
3563 | struct e1000_hw *hw = &adapter->hw; | |
3564 | bool link_active = false; | |
3565 | s32 ret_val = 0; | |
3566 | ||
3567 | /* get_link_status is set on LSC (link status) interrupt or | |
3568 | * rx sequence error interrupt. get_link_status will stay | |
3569 | * false until the e1000_check_for_link establishes link | |
3570 | * for copper adapters ONLY | |
3571 | */ | |
3572 | switch (hw->phy.media_type) { | |
3573 | case e1000_media_type_copper: | |
3574 | if (hw->mac.get_link_status) { | |
3575 | ret_val = hw->mac.ops.check_for_link(hw); | |
3576 | link_active = !hw->mac.get_link_status; | |
3577 | } else { | |
3578 | link_active = true; | |
3579 | } | |
3580 | break; | |
4d6b725e AD |
3581 | case e1000_media_type_internal_serdes: |
3582 | ret_val = hw->mac.ops.check_for_link(hw); | |
3583 | link_active = hw->mac.serdes_has_link; | |
3584 | break; | |
3585 | default: | |
3586 | case e1000_media_type_unknown: | |
3587 | break; | |
3588 | } | |
3589 | ||
3590 | return link_active; | |
3591 | } | |
3592 | ||
563988dc SA |
3593 | static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) |
3594 | { | |
3595 | bool ret = false; | |
3596 | u32 ctrl_ext, thstat; | |
3597 | ||
f96a8a0b | 3598 | /* check for thermal sensor event on i350 copper only */ |
563988dc SA |
3599 | if (hw->mac.type == e1000_i350) { |
3600 | thstat = rd32(E1000_THSTAT); | |
3601 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
3602 | ||
3603 | if ((hw->phy.media_type == e1000_media_type_copper) && | |
3604 | !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { | |
3605 | ret = !!(thstat & event); | |
3606 | } | |
3607 | } | |
3608 | ||
3609 | return ret; | |
3610 | } | |
3611 | ||
9d5c8243 AK |
3612 | /** |
3613 | * igb_watchdog - Timer Call-back | |
3614 | * @data: pointer to adapter cast into an unsigned long | |
3615 | **/ | |
3616 | static void igb_watchdog(unsigned long data) | |
3617 | { | |
3618 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
3619 | /* Do the rest outside of interrupt context */ | |
3620 | schedule_work(&adapter->watchdog_task); | |
3621 | } | |
3622 | ||
3623 | static void igb_watchdog_task(struct work_struct *work) | |
3624 | { | |
3625 | struct igb_adapter *adapter = container_of(work, | |
559e9c49 AD |
3626 | struct igb_adapter, |
3627 | watchdog_task); | |
9d5c8243 | 3628 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 3629 | struct net_device *netdev = adapter->netdev; |
563988dc | 3630 | u32 link; |
7a6ea550 | 3631 | int i; |
9d5c8243 | 3632 | |
4d6b725e | 3633 | link = igb_has_link(adapter); |
9d5c8243 | 3634 | if (link) { |
749ab2cd YZ |
3635 | /* Cancel scheduled suspend requests. */ |
3636 | pm_runtime_resume(netdev->dev.parent); | |
3637 | ||
9d5c8243 AK |
3638 | if (!netif_carrier_ok(netdev)) { |
3639 | u32 ctrl; | |
330a6d6a AD |
3640 | hw->mac.ops.get_speed_and_duplex(hw, |
3641 | &adapter->link_speed, | |
3642 | &adapter->link_duplex); | |
9d5c8243 AK |
3643 | |
3644 | ctrl = rd32(E1000_CTRL); | |
527d47c1 | 3645 | /* Links status message must follow this format */ |
876d2d6f JK |
3646 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " |
3647 | "Duplex, Flow Control: %s\n", | |
559e9c49 AD |
3648 | netdev->name, |
3649 | adapter->link_speed, | |
3650 | adapter->link_duplex == FULL_DUPLEX ? | |
876d2d6f JK |
3651 | "Full" : "Half", |
3652 | (ctrl & E1000_CTRL_TFCE) && | |
3653 | (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : | |
3654 | (ctrl & E1000_CTRL_RFCE) ? "RX" : | |
3655 | (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); | |
9d5c8243 | 3656 | |
563988dc | 3657 | /* check for thermal sensor event */ |
876d2d6f JK |
3658 | if (igb_thermal_sensor_event(hw, |
3659 | E1000_THSTAT_LINK_THROTTLE)) { | |
3660 | netdev_info(netdev, "The network adapter link " | |
3661 | "speed was downshifted because it " | |
3662 | "overheated\n"); | |
7ef5ed1c | 3663 | } |
563988dc | 3664 | |
d07f3e37 | 3665 | /* adjust timeout factor according to speed/duplex */ |
9d5c8243 AK |
3666 | adapter->tx_timeout_factor = 1; |
3667 | switch (adapter->link_speed) { | |
3668 | case SPEED_10: | |
9d5c8243 AK |
3669 | adapter->tx_timeout_factor = 14; |
3670 | break; | |
3671 | case SPEED_100: | |
9d5c8243 AK |
3672 | /* maybe add some timeout factor ? */ |
3673 | break; | |
3674 | } | |
3675 | ||
3676 | netif_carrier_on(netdev); | |
9d5c8243 | 3677 | |
4ae196df | 3678 | igb_ping_all_vfs(adapter); |
17dc566c | 3679 | igb_check_vf_rate_limit(adapter); |
4ae196df | 3680 | |
4b1a9877 | 3681 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3682 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3683 | mod_timer(&adapter->phy_info_timer, | |
3684 | round_jiffies(jiffies + 2 * HZ)); | |
3685 | } | |
3686 | } else { | |
3687 | if (netif_carrier_ok(netdev)) { | |
3688 | adapter->link_speed = 0; | |
3689 | adapter->link_duplex = 0; | |
563988dc SA |
3690 | |
3691 | /* check for thermal sensor event */ | |
876d2d6f JK |
3692 | if (igb_thermal_sensor_event(hw, |
3693 | E1000_THSTAT_PWR_DOWN)) { | |
3694 | netdev_err(netdev, "The network adapter was " | |
3695 | "stopped because it overheated\n"); | |
7ef5ed1c | 3696 | } |
563988dc | 3697 | |
527d47c1 AD |
3698 | /* Links status message must follow this format */ |
3699 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
3700 | netdev->name); | |
9d5c8243 | 3701 | netif_carrier_off(netdev); |
4b1a9877 | 3702 | |
4ae196df AD |
3703 | igb_ping_all_vfs(adapter); |
3704 | ||
4b1a9877 | 3705 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3706 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3707 | mod_timer(&adapter->phy_info_timer, | |
3708 | round_jiffies(jiffies + 2 * HZ)); | |
749ab2cd YZ |
3709 | |
3710 | pm_schedule_suspend(netdev->dev.parent, | |
3711 | MSEC_PER_SEC * 5); | |
9d5c8243 AK |
3712 | } |
3713 | } | |
3714 | ||
12dcd86b ED |
3715 | spin_lock(&adapter->stats64_lock); |
3716 | igb_update_stats(adapter, &adapter->stats64); | |
3717 | spin_unlock(&adapter->stats64_lock); | |
9d5c8243 | 3718 | |
dbabb065 | 3719 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 | 3720 | struct igb_ring *tx_ring = adapter->tx_ring[i]; |
dbabb065 | 3721 | if (!netif_carrier_ok(netdev)) { |
9d5c8243 AK |
3722 | /* We've lost link, so the controller stops DMA, |
3723 | * but we've got queued Tx work that's never going | |
3724 | * to get done, so reset controller to flush Tx. | |
3725 | * (Do the reset outside of interrupt context). */ | |
dbabb065 AD |
3726 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
3727 | adapter->tx_timeout_count++; | |
3728 | schedule_work(&adapter->reset_task); | |
3729 | /* return immediately since reset is imminent */ | |
3730 | return; | |
3731 | } | |
9d5c8243 | 3732 | } |
9d5c8243 | 3733 | |
dbabb065 | 3734 | /* Force detection of hung controller every watchdog period */ |
6d095fa8 | 3735 | set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
dbabb065 | 3736 | } |
f7ba205e | 3737 | |
9d5c8243 | 3738 | /* Cause software interrupt to ensure rx ring is cleaned */ |
7a6ea550 | 3739 | if (adapter->msix_entries) { |
047e0030 | 3740 | u32 eics = 0; |
0d1ae7f4 AD |
3741 | for (i = 0; i < adapter->num_q_vectors; i++) |
3742 | eics |= adapter->q_vector[i]->eims_value; | |
7a6ea550 AD |
3743 | wr32(E1000_EICS, eics); |
3744 | } else { | |
3745 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
3746 | } | |
9d5c8243 | 3747 | |
13800469 GR |
3748 | igb_spoof_check(adapter); |
3749 | ||
9d5c8243 AK |
3750 | /* Reset the timer */ |
3751 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3752 | mod_timer(&adapter->watchdog_timer, | |
3753 | round_jiffies(jiffies + 2 * HZ)); | |
3754 | } | |
3755 | ||
3756 | enum latency_range { | |
3757 | lowest_latency = 0, | |
3758 | low_latency = 1, | |
3759 | bulk_latency = 2, | |
3760 | latency_invalid = 255 | |
3761 | }; | |
3762 | ||
6eb5a7f1 AD |
3763 | /** |
3764 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
3765 | * | |
3766 | * Stores a new ITR value based on strictly on packet size. This | |
3767 | * algorithm is less sophisticated than that used in igb_update_itr, | |
3768 | * due to the difficulty of synchronizing statistics across multiple | |
eef35c2d | 3769 | * receive rings. The divisors and thresholds used by this function |
6eb5a7f1 AD |
3770 | * were determined based on theoretical maximum wire speed and testing |
3771 | * data, in order to minimize response time while increasing bulk | |
3772 | * throughput. | |
3773 | * This functionality is controlled by the InterruptThrottleRate module | |
3774 | * parameter (see igb_param.c) | |
3775 | * NOTE: This function is called only when operating in a multiqueue | |
3776 | * receive environment. | |
047e0030 | 3777 | * @q_vector: pointer to q_vector |
6eb5a7f1 | 3778 | **/ |
047e0030 | 3779 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 3780 | { |
047e0030 | 3781 | int new_val = q_vector->itr_val; |
6eb5a7f1 | 3782 | int avg_wire_size = 0; |
047e0030 | 3783 | struct igb_adapter *adapter = q_vector->adapter; |
12dcd86b | 3784 | unsigned int packets; |
9d5c8243 | 3785 | |
6eb5a7f1 AD |
3786 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
3787 | * ints/sec - ITR timer value of 120 ticks. | |
3788 | */ | |
3789 | if (adapter->link_speed != SPEED_1000) { | |
0ba82994 | 3790 | new_val = IGB_4K_ITR; |
6eb5a7f1 | 3791 | goto set_itr_val; |
9d5c8243 | 3792 | } |
047e0030 | 3793 | |
0ba82994 AD |
3794 | packets = q_vector->rx.total_packets; |
3795 | if (packets) | |
3796 | avg_wire_size = q_vector->rx.total_bytes / packets; | |
047e0030 | 3797 | |
0ba82994 AD |
3798 | packets = q_vector->tx.total_packets; |
3799 | if (packets) | |
3800 | avg_wire_size = max_t(u32, avg_wire_size, | |
3801 | q_vector->tx.total_bytes / packets); | |
047e0030 AD |
3802 | |
3803 | /* if avg_wire_size isn't set no work was done */ | |
3804 | if (!avg_wire_size) | |
3805 | goto clear_counts; | |
9d5c8243 | 3806 | |
6eb5a7f1 AD |
3807 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
3808 | avg_wire_size += 24; | |
3809 | ||
3810 | /* Don't starve jumbo frames */ | |
3811 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 3812 | |
6eb5a7f1 AD |
3813 | /* Give a little boost to mid-size frames */ |
3814 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
3815 | new_val = avg_wire_size / 3; | |
3816 | else | |
3817 | new_val = avg_wire_size / 2; | |
9d5c8243 | 3818 | |
0ba82994 AD |
3819 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
3820 | if (new_val < IGB_20K_ITR && | |
3821 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
3822 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
3823 | new_val = IGB_20K_ITR; | |
abe1c363 | 3824 | |
6eb5a7f1 | 3825 | set_itr_val: |
047e0030 AD |
3826 | if (new_val != q_vector->itr_val) { |
3827 | q_vector->itr_val = new_val; | |
3828 | q_vector->set_itr = 1; | |
9d5c8243 | 3829 | } |
6eb5a7f1 | 3830 | clear_counts: |
0ba82994 AD |
3831 | q_vector->rx.total_bytes = 0; |
3832 | q_vector->rx.total_packets = 0; | |
3833 | q_vector->tx.total_bytes = 0; | |
3834 | q_vector->tx.total_packets = 0; | |
9d5c8243 AK |
3835 | } |
3836 | ||
3837 | /** | |
3838 | * igb_update_itr - update the dynamic ITR value based on statistics | |
3839 | * Stores a new ITR value based on packets and byte | |
3840 | * counts during the last interrupt. The advantage of per interrupt | |
3841 | * computation is faster updates and more accurate ITR for the current | |
3842 | * traffic pattern. Constants in this function were computed | |
3843 | * based on theoretical maximum wire speed and thresholds were set based | |
3844 | * on testing data as well as attempting to minimize response time | |
3845 | * while increasing bulk throughput. | |
3846 | * this functionality is controlled by the InterruptThrottleRate module | |
3847 | * parameter (see igb_param.c) | |
3848 | * NOTE: These calculations are only valid when operating in a single- | |
3849 | * queue environment. | |
0ba82994 AD |
3850 | * @q_vector: pointer to q_vector |
3851 | * @ring_container: ring info to update the itr for | |
9d5c8243 | 3852 | **/ |
0ba82994 AD |
3853 | static void igb_update_itr(struct igb_q_vector *q_vector, |
3854 | struct igb_ring_container *ring_container) | |
9d5c8243 | 3855 | { |
0ba82994 AD |
3856 | unsigned int packets = ring_container->total_packets; |
3857 | unsigned int bytes = ring_container->total_bytes; | |
3858 | u8 itrval = ring_container->itr; | |
9d5c8243 | 3859 | |
0ba82994 | 3860 | /* no packets, exit with status unchanged */ |
9d5c8243 | 3861 | if (packets == 0) |
0ba82994 | 3862 | return; |
9d5c8243 | 3863 | |
0ba82994 | 3864 | switch (itrval) { |
9d5c8243 AK |
3865 | case lowest_latency: |
3866 | /* handle TSO and jumbo frames */ | |
3867 | if (bytes/packets > 8000) | |
0ba82994 | 3868 | itrval = bulk_latency; |
9d5c8243 | 3869 | else if ((packets < 5) && (bytes > 512)) |
0ba82994 | 3870 | itrval = low_latency; |
9d5c8243 AK |
3871 | break; |
3872 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
3873 | if (bytes > 10000) { | |
3874 | /* this if handles the TSO accounting */ | |
3875 | if (bytes/packets > 8000) { | |
0ba82994 | 3876 | itrval = bulk_latency; |
9d5c8243 | 3877 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { |
0ba82994 | 3878 | itrval = bulk_latency; |
9d5c8243 | 3879 | } else if ((packets > 35)) { |
0ba82994 | 3880 | itrval = lowest_latency; |
9d5c8243 AK |
3881 | } |
3882 | } else if (bytes/packets > 2000) { | |
0ba82994 | 3883 | itrval = bulk_latency; |
9d5c8243 | 3884 | } else if (packets <= 2 && bytes < 512) { |
0ba82994 | 3885 | itrval = lowest_latency; |
9d5c8243 AK |
3886 | } |
3887 | break; | |
3888 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
3889 | if (bytes > 25000) { | |
3890 | if (packets > 35) | |
0ba82994 | 3891 | itrval = low_latency; |
1e5c3d21 | 3892 | } else if (bytes < 1500) { |
0ba82994 | 3893 | itrval = low_latency; |
9d5c8243 AK |
3894 | } |
3895 | break; | |
3896 | } | |
3897 | ||
0ba82994 AD |
3898 | /* clear work counters since we have the values we need */ |
3899 | ring_container->total_bytes = 0; | |
3900 | ring_container->total_packets = 0; | |
3901 | ||
3902 | /* write updated itr to ring container */ | |
3903 | ring_container->itr = itrval; | |
9d5c8243 AK |
3904 | } |
3905 | ||
0ba82994 | 3906 | static void igb_set_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 3907 | { |
0ba82994 | 3908 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 3909 | u32 new_itr = q_vector->itr_val; |
0ba82994 | 3910 | u8 current_itr = 0; |
9d5c8243 AK |
3911 | |
3912 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
3913 | if (adapter->link_speed != SPEED_1000) { | |
3914 | current_itr = 0; | |
0ba82994 | 3915 | new_itr = IGB_4K_ITR; |
9d5c8243 AK |
3916 | goto set_itr_now; |
3917 | } | |
3918 | ||
0ba82994 AD |
3919 | igb_update_itr(q_vector, &q_vector->tx); |
3920 | igb_update_itr(q_vector, &q_vector->rx); | |
9d5c8243 | 3921 | |
0ba82994 | 3922 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
9d5c8243 | 3923 | |
6eb5a7f1 | 3924 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
0ba82994 AD |
3925 | if (current_itr == lowest_latency && |
3926 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
3927 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
6eb5a7f1 AD |
3928 | current_itr = low_latency; |
3929 | ||
9d5c8243 AK |
3930 | switch (current_itr) { |
3931 | /* counts and packets in update_itr are dependent on these numbers */ | |
3932 | case lowest_latency: | |
0ba82994 | 3933 | new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ |
9d5c8243 AK |
3934 | break; |
3935 | case low_latency: | |
0ba82994 | 3936 | new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ |
9d5c8243 AK |
3937 | break; |
3938 | case bulk_latency: | |
0ba82994 | 3939 | new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ |
9d5c8243 AK |
3940 | break; |
3941 | default: | |
3942 | break; | |
3943 | } | |
3944 | ||
3945 | set_itr_now: | |
047e0030 | 3946 | if (new_itr != q_vector->itr_val) { |
9d5c8243 AK |
3947 | /* this attempts to bias the interrupt rate towards Bulk |
3948 | * by adding intermediate steps when interrupt rate is | |
3949 | * increasing */ | |
047e0030 AD |
3950 | new_itr = new_itr > q_vector->itr_val ? |
3951 | max((new_itr * q_vector->itr_val) / | |
3952 | (new_itr + (q_vector->itr_val >> 2)), | |
0ba82994 | 3953 | new_itr) : |
9d5c8243 AK |
3954 | new_itr; |
3955 | /* Don't write the value here; it resets the adapter's | |
3956 | * internal timer, and causes us to delay far longer than | |
3957 | * we should between interrupts. Instead, we write the ITR | |
3958 | * value at the beginning of the next interrupt so the timing | |
3959 | * ends up being correct. | |
3960 | */ | |
047e0030 AD |
3961 | q_vector->itr_val = new_itr; |
3962 | q_vector->set_itr = 1; | |
9d5c8243 | 3963 | } |
9d5c8243 AK |
3964 | } |
3965 | ||
c50b52a0 SH |
3966 | static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, |
3967 | u32 type_tucmd, u32 mss_l4len_idx) | |
7d13a7d0 AD |
3968 | { |
3969 | struct e1000_adv_tx_context_desc *context_desc; | |
3970 | u16 i = tx_ring->next_to_use; | |
3971 | ||
3972 | context_desc = IGB_TX_CTXTDESC(tx_ring, i); | |
3973 | ||
3974 | i++; | |
3975 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
3976 | ||
3977 | /* set bits to identify this as an advanced context descriptor */ | |
3978 | type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; | |
3979 | ||
3980 | /* For 82575, context index must be unique per ring. */ | |
866cff06 | 3981 | if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) |
7d13a7d0 AD |
3982 | mss_l4len_idx |= tx_ring->reg_idx << 4; |
3983 | ||
3984 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3985 | context_desc->seqnum_seed = 0; | |
3986 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
3987 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
3988 | } | |
3989 | ||
7af40ad9 AD |
3990 | static int igb_tso(struct igb_ring *tx_ring, |
3991 | struct igb_tx_buffer *first, | |
3992 | u8 *hdr_len) | |
9d5c8243 | 3993 | { |
7af40ad9 | 3994 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
3995 | u32 vlan_macip_lens, type_tucmd; |
3996 | u32 mss_l4len_idx, l4len; | |
3997 | ||
3998 | if (!skb_is_gso(skb)) | |
3999 | return 0; | |
9d5c8243 AK |
4000 | |
4001 | if (skb_header_cloned(skb)) { | |
7af40ad9 | 4002 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
9d5c8243 AK |
4003 | if (err) |
4004 | return err; | |
4005 | } | |
4006 | ||
7d13a7d0 AD |
4007 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
4008 | type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; | |
9d5c8243 | 4009 | |
7af40ad9 | 4010 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
9d5c8243 AK |
4011 | struct iphdr *iph = ip_hdr(skb); |
4012 | iph->tot_len = 0; | |
4013 | iph->check = 0; | |
4014 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
4015 | iph->daddr, 0, | |
4016 | IPPROTO_TCP, | |
4017 | 0); | |
7d13a7d0 | 4018 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; |
7af40ad9 AD |
4019 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4020 | IGB_TX_FLAGS_CSUM | | |
4021 | IGB_TX_FLAGS_IPV4; | |
8e1e8a47 | 4022 | } else if (skb_is_gso_v6(skb)) { |
9d5c8243 AK |
4023 | ipv6_hdr(skb)->payload_len = 0; |
4024 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
4025 | &ipv6_hdr(skb)->daddr, | |
4026 | 0, IPPROTO_TCP, 0); | |
7af40ad9 AD |
4027 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4028 | IGB_TX_FLAGS_CSUM; | |
9d5c8243 AK |
4029 | } |
4030 | ||
7af40ad9 | 4031 | /* compute header lengths */ |
7d13a7d0 AD |
4032 | l4len = tcp_hdrlen(skb); |
4033 | *hdr_len = skb_transport_offset(skb) + l4len; | |
9d5c8243 | 4034 | |
7af40ad9 AD |
4035 | /* update gso size and bytecount with header size */ |
4036 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
4037 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
4038 | ||
9d5c8243 | 4039 | /* MSS L4LEN IDX */ |
7d13a7d0 AD |
4040 | mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; |
4041 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; | |
9d5c8243 | 4042 | |
7d13a7d0 AD |
4043 | /* VLAN MACLEN IPLEN */ |
4044 | vlan_macip_lens = skb_network_header_len(skb); | |
4045 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; | |
7af40ad9 | 4046 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4047 | |
7d13a7d0 | 4048 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 | 4049 | |
7d13a7d0 | 4050 | return 1; |
9d5c8243 AK |
4051 | } |
4052 | ||
7af40ad9 | 4053 | static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) |
9d5c8243 | 4054 | { |
7af40ad9 | 4055 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4056 | u32 vlan_macip_lens = 0; |
4057 | u32 mss_l4len_idx = 0; | |
4058 | u32 type_tucmd = 0; | |
9d5c8243 | 4059 | |
7d13a7d0 | 4060 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
7af40ad9 AD |
4061 | if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) |
4062 | return; | |
7d13a7d0 AD |
4063 | } else { |
4064 | u8 l4_hdr = 0; | |
7af40ad9 | 4065 | switch (first->protocol) { |
7d13a7d0 AD |
4066 | case __constant_htons(ETH_P_IP): |
4067 | vlan_macip_lens |= skb_network_header_len(skb); | |
4068 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; | |
4069 | l4_hdr = ip_hdr(skb)->protocol; | |
4070 | break; | |
4071 | case __constant_htons(ETH_P_IPV6): | |
4072 | vlan_macip_lens |= skb_network_header_len(skb); | |
4073 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
4074 | break; | |
4075 | default: | |
4076 | if (unlikely(net_ratelimit())) { | |
4077 | dev_warn(tx_ring->dev, | |
4078 | "partial checksum but proto=%x!\n", | |
7af40ad9 | 4079 | first->protocol); |
fa4a7ef3 | 4080 | } |
7d13a7d0 AD |
4081 | break; |
4082 | } | |
fa4a7ef3 | 4083 | |
7d13a7d0 AD |
4084 | switch (l4_hdr) { |
4085 | case IPPROTO_TCP: | |
4086 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
4087 | mss_l4len_idx = tcp_hdrlen(skb) << | |
4088 | E1000_ADVTXD_L4LEN_SHIFT; | |
4089 | break; | |
4090 | case IPPROTO_SCTP: | |
4091 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
4092 | mss_l4len_idx = sizeof(struct sctphdr) << | |
4093 | E1000_ADVTXD_L4LEN_SHIFT; | |
4094 | break; | |
4095 | case IPPROTO_UDP: | |
4096 | mss_l4len_idx = sizeof(struct udphdr) << | |
4097 | E1000_ADVTXD_L4LEN_SHIFT; | |
4098 | break; | |
4099 | default: | |
4100 | if (unlikely(net_ratelimit())) { | |
4101 | dev_warn(tx_ring->dev, | |
4102 | "partial checksum but l4 proto=%x!\n", | |
4103 | l4_hdr); | |
44b0cda3 | 4104 | } |
7d13a7d0 | 4105 | break; |
9d5c8243 | 4106 | } |
7af40ad9 AD |
4107 | |
4108 | /* update TX checksum flag */ | |
4109 | first->tx_flags |= IGB_TX_FLAGS_CSUM; | |
7d13a7d0 | 4110 | } |
9d5c8243 | 4111 | |
7d13a7d0 | 4112 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; |
7af40ad9 | 4113 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4114 | |
7d13a7d0 | 4115 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 AK |
4116 | } |
4117 | ||
e032afc8 AD |
4118 | static __le32 igb_tx_cmd_type(u32 tx_flags) |
4119 | { | |
4120 | /* set type for advanced descriptor with frame checksum insertion */ | |
4121 | __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA | | |
4122 | E1000_ADVTXD_DCMD_IFCS | | |
4123 | E1000_ADVTXD_DCMD_DEXT); | |
4124 | ||
4125 | /* set HW vlan bit if vlan is present */ | |
4126 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
4127 | cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE); | |
4128 | ||
4129 | /* set timestamp bit if present */ | |
1f6e8178 | 4130 | if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) |
e032afc8 AD |
4131 | cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP); |
4132 | ||
4133 | /* set segmentation bits for TSO */ | |
4134 | if (tx_flags & IGB_TX_FLAGS_TSO) | |
4135 | cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE); | |
4136 | ||
4137 | return cmd_type; | |
4138 | } | |
4139 | ||
7af40ad9 AD |
4140 | static void igb_tx_olinfo_status(struct igb_ring *tx_ring, |
4141 | union e1000_adv_tx_desc *tx_desc, | |
4142 | u32 tx_flags, unsigned int paylen) | |
e032afc8 AD |
4143 | { |
4144 | u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; | |
4145 | ||
4146 | /* 82575 requires a unique index per ring if any offload is enabled */ | |
4147 | if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) && | |
866cff06 | 4148 | test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) |
e032afc8 AD |
4149 | olinfo_status |= tx_ring->reg_idx << 4; |
4150 | ||
4151 | /* insert L4 checksum */ | |
4152 | if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
4153 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
4154 | ||
4155 | /* insert IPv4 checksum */ | |
4156 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
4157 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
4158 | } | |
4159 | ||
7af40ad9 | 4160 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
e032afc8 AD |
4161 | } |
4162 | ||
ebe42d16 AD |
4163 | /* |
4164 | * The largest size we can write to the descriptor is 65535. In order to | |
4165 | * maintain a power of two alignment we have to limit ourselves to 32K. | |
4166 | */ | |
4167 | #define IGB_MAX_TXD_PWR 15 | |
7af40ad9 | 4168 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) |
9d5c8243 | 4169 | |
7af40ad9 AD |
4170 | static void igb_tx_map(struct igb_ring *tx_ring, |
4171 | struct igb_tx_buffer *first, | |
ebe42d16 | 4172 | const u8 hdr_len) |
9d5c8243 | 4173 | { |
7af40ad9 | 4174 | struct sk_buff *skb = first->skb; |
c9f14bf3 | 4175 | struct igb_tx_buffer *tx_buffer; |
ebe42d16 AD |
4176 | union e1000_adv_tx_desc *tx_desc; |
4177 | dma_addr_t dma; | |
4178 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
4179 | unsigned int data_len = skb->data_len; | |
4180 | unsigned int size = skb_headlen(skb); | |
4181 | unsigned int paylen = skb->len - hdr_len; | |
4182 | __le32 cmd_type; | |
7af40ad9 | 4183 | u32 tx_flags = first->tx_flags; |
ebe42d16 | 4184 | u16 i = tx_ring->next_to_use; |
ebe42d16 AD |
4185 | |
4186 | tx_desc = IGB_TX_DESC(tx_ring, i); | |
4187 | ||
7af40ad9 | 4188 | igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen); |
ebe42d16 AD |
4189 | cmd_type = igb_tx_cmd_type(tx_flags); |
4190 | ||
4191 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
4192 | if (dma_mapping_error(tx_ring->dev, dma)) | |
6366ad33 | 4193 | goto dma_error; |
9d5c8243 | 4194 | |
ebe42d16 | 4195 | /* record length, and DMA address */ |
c9f14bf3 AD |
4196 | dma_unmap_len_set(first, len, size); |
4197 | dma_unmap_addr_set(first, dma, dma); | |
ebe42d16 AD |
4198 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
4199 | ||
4200 | for (;;) { | |
4201 | while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { | |
4202 | tx_desc->read.cmd_type_len = | |
4203 | cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD); | |
4204 | ||
4205 | i++; | |
4206 | tx_desc++; | |
4207 | if (i == tx_ring->count) { | |
4208 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
4209 | i = 0; | |
4210 | } | |
4211 | ||
4212 | dma += IGB_MAX_DATA_PER_TXD; | |
4213 | size -= IGB_MAX_DATA_PER_TXD; | |
4214 | ||
4215 | tx_desc->read.olinfo_status = 0; | |
4216 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
4217 | } | |
4218 | ||
4219 | if (likely(!data_len)) | |
4220 | break; | |
2bbfebe2 | 4221 | |
ebe42d16 | 4222 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9d5c8243 | 4223 | |
65689fef | 4224 | i++; |
ebe42d16 AD |
4225 | tx_desc++; |
4226 | if (i == tx_ring->count) { | |
4227 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
65689fef | 4228 | i = 0; |
ebe42d16 | 4229 | } |
65689fef | 4230 | |
9e903e08 | 4231 | size = skb_frag_size(frag); |
ebe42d16 AD |
4232 | data_len -= size; |
4233 | ||
4234 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, | |
4235 | size, DMA_TO_DEVICE); | |
4236 | if (dma_mapping_error(tx_ring->dev, dma)) | |
6366ad33 AD |
4237 | goto dma_error; |
4238 | ||
c9f14bf3 AD |
4239 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
4240 | dma_unmap_len_set(tx_buffer, len, size); | |
4241 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
ebe42d16 AD |
4242 | |
4243 | tx_desc->read.olinfo_status = 0; | |
4244 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
4245 | ||
4246 | frag++; | |
9d5c8243 AK |
4247 | } |
4248 | ||
bdbc0631 ED |
4249 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
4250 | ||
ebe42d16 AD |
4251 | /* write last descriptor with RS and EOP bits */ |
4252 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD); | |
6b8f0922 BG |
4253 | if (unlikely(skb->no_fcs)) |
4254 | cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS)); | |
ebe42d16 | 4255 | tx_desc->read.cmd_type_len = cmd_type; |
8542db05 AD |
4256 | |
4257 | /* set the timestamp */ | |
4258 | first->time_stamp = jiffies; | |
4259 | ||
ebe42d16 AD |
4260 | /* |
4261 | * Force memory writes to complete before letting h/w know there | |
4262 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
4263 | * memory model archs, such as IA-64). | |
4264 | * | |
4265 | * We also need this memory barrier to make certain all of the | |
4266 | * status bits have been updated before next_to_watch is written. | |
4267 | */ | |
4268 | wmb(); | |
4269 | ||
8542db05 | 4270 | /* set next_to_watch value indicating a packet is present */ |
ebe42d16 | 4271 | first->next_to_watch = tx_desc; |
9d5c8243 | 4272 | |
ebe42d16 AD |
4273 | i++; |
4274 | if (i == tx_ring->count) | |
4275 | i = 0; | |
6366ad33 | 4276 | |
ebe42d16 | 4277 | tx_ring->next_to_use = i; |
6366ad33 | 4278 | |
ebe42d16 | 4279 | writel(i, tx_ring->tail); |
6366ad33 | 4280 | |
ebe42d16 AD |
4281 | /* we need this if more than one processor can write to our tail |
4282 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
4283 | mmiowb(); | |
4284 | ||
4285 | return; | |
4286 | ||
4287 | dma_error: | |
4288 | dev_err(tx_ring->dev, "TX DMA map failed\n"); | |
4289 | ||
4290 | /* clear dma mappings for failed tx_buffer_info map */ | |
4291 | for (;;) { | |
c9f14bf3 AD |
4292 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
4293 | igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
4294 | if (tx_buffer == first) | |
ebe42d16 | 4295 | break; |
a77ff709 NN |
4296 | if (i == 0) |
4297 | i = tx_ring->count; | |
6366ad33 | 4298 | i--; |
6366ad33 AD |
4299 | } |
4300 | ||
9d5c8243 | 4301 | tx_ring->next_to_use = i; |
9d5c8243 AK |
4302 | } |
4303 | ||
6ad4edfc | 4304 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4305 | { |
e694e964 AD |
4306 | struct net_device *netdev = tx_ring->netdev; |
4307 | ||
661086df | 4308 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 4309 | |
9d5c8243 AK |
4310 | /* Herbert's original patch had: |
4311 | * smp_mb__after_netif_stop_queue(); | |
4312 | * but since that doesn't exist yet, just open code it. */ | |
4313 | smp_mb(); | |
4314 | ||
4315 | /* We need to check again in a case another CPU has just | |
4316 | * made room available. */ | |
c493ea45 | 4317 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
4318 | return -EBUSY; |
4319 | ||
4320 | /* A reprieve! */ | |
661086df | 4321 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
12dcd86b ED |
4322 | |
4323 | u64_stats_update_begin(&tx_ring->tx_syncp2); | |
4324 | tx_ring->tx_stats.restart_queue2++; | |
4325 | u64_stats_update_end(&tx_ring->tx_syncp2); | |
4326 | ||
9d5c8243 AK |
4327 | return 0; |
4328 | } | |
4329 | ||
6ad4edfc | 4330 | static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4331 | { |
c493ea45 | 4332 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 | 4333 | return 0; |
e694e964 | 4334 | return __igb_maybe_stop_tx(tx_ring, size); |
9d5c8243 AK |
4335 | } |
4336 | ||
cd392f5c AD |
4337 | netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, |
4338 | struct igb_ring *tx_ring) | |
9d5c8243 | 4339 | { |
1f6e8178 | 4340 | struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); |
8542db05 | 4341 | struct igb_tx_buffer *first; |
ebe42d16 | 4342 | int tso; |
91d4ee33 | 4343 | u32 tx_flags = 0; |
31f6adbb | 4344 | __be16 protocol = vlan_get_protocol(skb); |
91d4ee33 | 4345 | u8 hdr_len = 0; |
9d5c8243 | 4346 | |
9d5c8243 AK |
4347 | /* need: 1 descriptor per page, |
4348 | * + 2 desc gap to keep tail from touching head, | |
4349 | * + 1 desc for skb->data, | |
4350 | * + 1 desc for context descriptor, | |
4351 | * otherwise try next time */ | |
e694e964 | 4352 | if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { |
9d5c8243 | 4353 | /* this is a hard error */ |
9d5c8243 AK |
4354 | return NETDEV_TX_BUSY; |
4355 | } | |
33af6bcc | 4356 | |
7af40ad9 AD |
4357 | /* record the location of the first descriptor for this packet */ |
4358 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
4359 | first->skb = skb; | |
4360 | first->bytecount = skb->len; | |
4361 | first->gso_segs = 1; | |
4362 | ||
1f6e8178 MV |
4363 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
4364 | !(adapter->ptp_tx_skb))) { | |
2244d07b | 4365 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
33af6bcc | 4366 | tx_flags |= IGB_TX_FLAGS_TSTAMP; |
1f6e8178 MV |
4367 | |
4368 | adapter->ptp_tx_skb = skb_get(skb); | |
4369 | if (adapter->hw.mac.type == e1000_82576) | |
4370 | schedule_work(&adapter->ptp_tx_work); | |
33af6bcc | 4371 | } |
9d5c8243 | 4372 | |
eab6d18d | 4373 | if (vlan_tx_tag_present(skb)) { |
9d5c8243 AK |
4374 | tx_flags |= IGB_TX_FLAGS_VLAN; |
4375 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
4376 | } | |
4377 | ||
7af40ad9 AD |
4378 | /* record initial flags and protocol */ |
4379 | first->tx_flags = tx_flags; | |
4380 | first->protocol = protocol; | |
cdfd01fc | 4381 | |
7af40ad9 AD |
4382 | tso = igb_tso(tx_ring, first, &hdr_len); |
4383 | if (tso < 0) | |
7d13a7d0 | 4384 | goto out_drop; |
7af40ad9 AD |
4385 | else if (!tso) |
4386 | igb_tx_csum(tx_ring, first); | |
9d5c8243 | 4387 | |
7af40ad9 | 4388 | igb_tx_map(tx_ring, first, hdr_len); |
85ad76b2 AD |
4389 | |
4390 | /* Make sure there is space in the ring for the next send. */ | |
e694e964 | 4391 | igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); |
85ad76b2 | 4392 | |
9d5c8243 | 4393 | return NETDEV_TX_OK; |
7d13a7d0 AD |
4394 | |
4395 | out_drop: | |
7af40ad9 AD |
4396 | igb_unmap_and_free_tx_resource(tx_ring, first); |
4397 | ||
7d13a7d0 | 4398 | return NETDEV_TX_OK; |
9d5c8243 AK |
4399 | } |
4400 | ||
1cc3bd87 AD |
4401 | static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, |
4402 | struct sk_buff *skb) | |
4403 | { | |
4404 | unsigned int r_idx = skb->queue_mapping; | |
4405 | ||
4406 | if (r_idx >= adapter->num_tx_queues) | |
4407 | r_idx = r_idx % adapter->num_tx_queues; | |
4408 | ||
4409 | return adapter->tx_ring[r_idx]; | |
4410 | } | |
4411 | ||
cd392f5c AD |
4412 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, |
4413 | struct net_device *netdev) | |
9d5c8243 AK |
4414 | { |
4415 | struct igb_adapter *adapter = netdev_priv(netdev); | |
b1a436c3 AD |
4416 | |
4417 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
4418 | dev_kfree_skb_any(skb); | |
4419 | return NETDEV_TX_OK; | |
4420 | } | |
4421 | ||
4422 | if (skb->len <= 0) { | |
4423 | dev_kfree_skb_any(skb); | |
4424 | return NETDEV_TX_OK; | |
4425 | } | |
4426 | ||
1cc3bd87 AD |
4427 | /* |
4428 | * The minimum packet size with TCTL.PSP set is 17 so pad the skb | |
4429 | * in order to meet this minimum size requirement. | |
4430 | */ | |
ea5ceeab TD |
4431 | if (unlikely(skb->len < 17)) { |
4432 | if (skb_pad(skb, 17 - skb->len)) | |
1cc3bd87 AD |
4433 | return NETDEV_TX_OK; |
4434 | skb->len = 17; | |
ea5ceeab | 4435 | skb_set_tail_pointer(skb, 17); |
1cc3bd87 | 4436 | } |
9d5c8243 | 4437 | |
1cc3bd87 | 4438 | return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); |
9d5c8243 AK |
4439 | } |
4440 | ||
4441 | /** | |
4442 | * igb_tx_timeout - Respond to a Tx Hang | |
4443 | * @netdev: network interface device structure | |
4444 | **/ | |
4445 | static void igb_tx_timeout(struct net_device *netdev) | |
4446 | { | |
4447 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4448 | struct e1000_hw *hw = &adapter->hw; | |
4449 | ||
4450 | /* Do the reset outside of interrupt context */ | |
4451 | adapter->tx_timeout_count++; | |
f7ba205e | 4452 | |
06218a8d | 4453 | if (hw->mac.type >= e1000_82580) |
55cac248 AD |
4454 | hw->dev_spec._82575.global_device_reset = true; |
4455 | ||
9d5c8243 | 4456 | schedule_work(&adapter->reset_task); |
265de409 AD |
4457 | wr32(E1000_EICS, |
4458 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
4459 | } |
4460 | ||
4461 | static void igb_reset_task(struct work_struct *work) | |
4462 | { | |
4463 | struct igb_adapter *adapter; | |
4464 | adapter = container_of(work, struct igb_adapter, reset_task); | |
4465 | ||
c97ec42a TI |
4466 | igb_dump(adapter); |
4467 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
9d5c8243 AK |
4468 | igb_reinit_locked(adapter); |
4469 | } | |
4470 | ||
4471 | /** | |
12dcd86b | 4472 | * igb_get_stats64 - Get System Network Statistics |
9d5c8243 | 4473 | * @netdev: network interface device structure |
12dcd86b | 4474 | * @stats: rtnl_link_stats64 pointer |
9d5c8243 | 4475 | * |
9d5c8243 | 4476 | **/ |
12dcd86b ED |
4477 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, |
4478 | struct rtnl_link_stats64 *stats) | |
9d5c8243 | 4479 | { |
12dcd86b ED |
4480 | struct igb_adapter *adapter = netdev_priv(netdev); |
4481 | ||
4482 | spin_lock(&adapter->stats64_lock); | |
4483 | igb_update_stats(adapter, &adapter->stats64); | |
4484 | memcpy(stats, &adapter->stats64, sizeof(*stats)); | |
4485 | spin_unlock(&adapter->stats64_lock); | |
4486 | ||
4487 | return stats; | |
9d5c8243 AK |
4488 | } |
4489 | ||
4490 | /** | |
4491 | * igb_change_mtu - Change the Maximum Transfer Unit | |
4492 | * @netdev: network interface device structure | |
4493 | * @new_mtu: new value for maximum frame size | |
4494 | * | |
4495 | * Returns 0 on success, negative on failure | |
4496 | **/ | |
4497 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
4498 | { | |
4499 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4500 | struct pci_dev *pdev = adapter->pdev; |
153285f9 | 4501 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
9d5c8243 | 4502 | |
c809d227 | 4503 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
090b1795 | 4504 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
9d5c8243 AK |
4505 | return -EINVAL; |
4506 | } | |
4507 | ||
153285f9 | 4508 | #define MAX_STD_JUMBO_FRAME_SIZE 9238 |
9d5c8243 | 4509 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
090b1795 | 4510 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
9d5c8243 AK |
4511 | return -EINVAL; |
4512 | } | |
4513 | ||
4514 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
4515 | msleep(1); | |
73cd78f1 | 4516 | |
9d5c8243 AK |
4517 | /* igb_down has a dependency on max_frame_size */ |
4518 | adapter->max_frame_size = max_frame; | |
559e9c49 | 4519 | |
4c844851 AD |
4520 | if (netif_running(netdev)) |
4521 | igb_down(adapter); | |
9d5c8243 | 4522 | |
090b1795 | 4523 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
9d5c8243 AK |
4524 | netdev->mtu, new_mtu); |
4525 | netdev->mtu = new_mtu; | |
4526 | ||
4527 | if (netif_running(netdev)) | |
4528 | igb_up(adapter); | |
4529 | else | |
4530 | igb_reset(adapter); | |
4531 | ||
4532 | clear_bit(__IGB_RESETTING, &adapter->state); | |
4533 | ||
4534 | return 0; | |
4535 | } | |
4536 | ||
4537 | /** | |
4538 | * igb_update_stats - Update the board statistics counters | |
4539 | * @adapter: board private structure | |
4540 | **/ | |
4541 | ||
12dcd86b ED |
4542 | void igb_update_stats(struct igb_adapter *adapter, |
4543 | struct rtnl_link_stats64 *net_stats) | |
9d5c8243 AK |
4544 | { |
4545 | struct e1000_hw *hw = &adapter->hw; | |
4546 | struct pci_dev *pdev = adapter->pdev; | |
fa3d9a6d | 4547 | u32 reg, mpc; |
9d5c8243 | 4548 | u16 phy_tmp; |
3f9c0164 AD |
4549 | int i; |
4550 | u64 bytes, packets; | |
12dcd86b ED |
4551 | unsigned int start; |
4552 | u64 _bytes, _packets; | |
9d5c8243 AK |
4553 | |
4554 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
4555 | ||
4556 | /* | |
4557 | * Prevent stats update while adapter is being reset, or if the pci | |
4558 | * connection is down. | |
4559 | */ | |
4560 | if (adapter->link_speed == 0) | |
4561 | return; | |
4562 | if (pci_channel_offline(pdev)) | |
4563 | return; | |
4564 | ||
3f9c0164 AD |
4565 | bytes = 0; |
4566 | packets = 0; | |
4567 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
ae1c07a6 | 4568 | u32 rqdpc = rd32(E1000_RQDPC(i)); |
3025a446 | 4569 | struct igb_ring *ring = adapter->rx_ring[i]; |
12dcd86b | 4570 | |
ae1c07a6 AD |
4571 | if (rqdpc) { |
4572 | ring->rx_stats.drops += rqdpc; | |
4573 | net_stats->rx_fifo_errors += rqdpc; | |
4574 | } | |
12dcd86b ED |
4575 | |
4576 | do { | |
4577 | start = u64_stats_fetch_begin_bh(&ring->rx_syncp); | |
4578 | _bytes = ring->rx_stats.bytes; | |
4579 | _packets = ring->rx_stats.packets; | |
4580 | } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); | |
4581 | bytes += _bytes; | |
4582 | packets += _packets; | |
3f9c0164 AD |
4583 | } |
4584 | ||
128e45eb AD |
4585 | net_stats->rx_bytes = bytes; |
4586 | net_stats->rx_packets = packets; | |
3f9c0164 AD |
4587 | |
4588 | bytes = 0; | |
4589 | packets = 0; | |
4590 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 4591 | struct igb_ring *ring = adapter->tx_ring[i]; |
12dcd86b ED |
4592 | do { |
4593 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp); | |
4594 | _bytes = ring->tx_stats.bytes; | |
4595 | _packets = ring->tx_stats.packets; | |
4596 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); | |
4597 | bytes += _bytes; | |
4598 | packets += _packets; | |
3f9c0164 | 4599 | } |
128e45eb AD |
4600 | net_stats->tx_bytes = bytes; |
4601 | net_stats->tx_packets = packets; | |
3f9c0164 AD |
4602 | |
4603 | /* read stats registers */ | |
9d5c8243 AK |
4604 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
4605 | adapter->stats.gprc += rd32(E1000_GPRC); | |
4606 | adapter->stats.gorc += rd32(E1000_GORCL); | |
4607 | rd32(E1000_GORCH); /* clear GORCL */ | |
4608 | adapter->stats.bprc += rd32(E1000_BPRC); | |
4609 | adapter->stats.mprc += rd32(E1000_MPRC); | |
4610 | adapter->stats.roc += rd32(E1000_ROC); | |
4611 | ||
4612 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
4613 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
4614 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
4615 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
4616 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
4617 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
4618 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
4619 | adapter->stats.sec += rd32(E1000_SEC); | |
4620 | ||
fa3d9a6d MW |
4621 | mpc = rd32(E1000_MPC); |
4622 | adapter->stats.mpc += mpc; | |
4623 | net_stats->rx_fifo_errors += mpc; | |
9d5c8243 AK |
4624 | adapter->stats.scc += rd32(E1000_SCC); |
4625 | adapter->stats.ecol += rd32(E1000_ECOL); | |
4626 | adapter->stats.mcc += rd32(E1000_MCC); | |
4627 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
4628 | adapter->stats.dc += rd32(E1000_DC); | |
4629 | adapter->stats.rlec += rd32(E1000_RLEC); | |
4630 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
4631 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
4632 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
4633 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
4634 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
4635 | adapter->stats.gptc += rd32(E1000_GPTC); | |
4636 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
4637 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
fa3d9a6d | 4638 | adapter->stats.rnbc += rd32(E1000_RNBC); |
9d5c8243 AK |
4639 | adapter->stats.ruc += rd32(E1000_RUC); |
4640 | adapter->stats.rfc += rd32(E1000_RFC); | |
4641 | adapter->stats.rjc += rd32(E1000_RJC); | |
4642 | adapter->stats.tor += rd32(E1000_TORH); | |
4643 | adapter->stats.tot += rd32(E1000_TOTH); | |
4644 | adapter->stats.tpr += rd32(E1000_TPR); | |
4645 | ||
4646 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
4647 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
4648 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
4649 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
4650 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
4651 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
4652 | ||
4653 | adapter->stats.mptc += rd32(E1000_MPTC); | |
4654 | adapter->stats.bptc += rd32(E1000_BPTC); | |
4655 | ||
2d0b0f69 NN |
4656 | adapter->stats.tpt += rd32(E1000_TPT); |
4657 | adapter->stats.colc += rd32(E1000_COLC); | |
9d5c8243 AK |
4658 | |
4659 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
43915c7c NN |
4660 | /* read internal phy specific stats */ |
4661 | reg = rd32(E1000_CTRL_EXT); | |
4662 | if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { | |
4663 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3dbdf969 CW |
4664 | |
4665 | /* this stat has invalid values on i210/i211 */ | |
4666 | if ((hw->mac.type != e1000_i210) && | |
4667 | (hw->mac.type != e1000_i211)) | |
4668 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
43915c7c NN |
4669 | } |
4670 | ||
9d5c8243 AK |
4671 | adapter->stats.tsctc += rd32(E1000_TSCTC); |
4672 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
4673 | ||
4674 | adapter->stats.iac += rd32(E1000_IAC); | |
4675 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
4676 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
4677 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
4678 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
4679 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
4680 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
4681 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
4682 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
4683 | ||
4684 | /* Fill out the OS statistics structure */ | |
128e45eb AD |
4685 | net_stats->multicast = adapter->stats.mprc; |
4686 | net_stats->collisions = adapter->stats.colc; | |
9d5c8243 AK |
4687 | |
4688 | /* Rx Errors */ | |
4689 | ||
4690 | /* RLEC on some newer hardware can be incorrect so build | |
8c0ab70a | 4691 | * our own version based on RUC and ROC */ |
128e45eb | 4692 | net_stats->rx_errors = adapter->stats.rxerrc + |
9d5c8243 AK |
4693 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
4694 | adapter->stats.ruc + adapter->stats.roc + | |
4695 | adapter->stats.cexterr; | |
128e45eb AD |
4696 | net_stats->rx_length_errors = adapter->stats.ruc + |
4697 | adapter->stats.roc; | |
4698 | net_stats->rx_crc_errors = adapter->stats.crcerrs; | |
4699 | net_stats->rx_frame_errors = adapter->stats.algnerrc; | |
4700 | net_stats->rx_missed_errors = adapter->stats.mpc; | |
9d5c8243 AK |
4701 | |
4702 | /* Tx Errors */ | |
128e45eb AD |
4703 | net_stats->tx_errors = adapter->stats.ecol + |
4704 | adapter->stats.latecol; | |
4705 | net_stats->tx_aborted_errors = adapter->stats.ecol; | |
4706 | net_stats->tx_window_errors = adapter->stats.latecol; | |
4707 | net_stats->tx_carrier_errors = adapter->stats.tncrs; | |
9d5c8243 AK |
4708 | |
4709 | /* Tx Dropped needs to be maintained elsewhere */ | |
4710 | ||
4711 | /* Phy Stats */ | |
4712 | if (hw->phy.media_type == e1000_media_type_copper) { | |
4713 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 4714 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
4715 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
4716 | adapter->phy_stats.idle_errors += phy_tmp; | |
4717 | } | |
4718 | } | |
4719 | ||
4720 | /* Management Stats */ | |
4721 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
4722 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
4723 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
0a915b95 CW |
4724 | |
4725 | /* OS2BMC Stats */ | |
4726 | reg = rd32(E1000_MANC); | |
4727 | if (reg & E1000_MANC_EN_BMC2OS) { | |
4728 | adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); | |
4729 | adapter->stats.o2bspc += rd32(E1000_O2BSPC); | |
4730 | adapter->stats.b2ospc += rd32(E1000_B2OSPC); | |
4731 | adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); | |
4732 | } | |
9d5c8243 AK |
4733 | } |
4734 | ||
9d5c8243 AK |
4735 | static irqreturn_t igb_msix_other(int irq, void *data) |
4736 | { | |
047e0030 | 4737 | struct igb_adapter *adapter = data; |
9d5c8243 | 4738 | struct e1000_hw *hw = &adapter->hw; |
844290e5 | 4739 | u32 icr = rd32(E1000_ICR); |
844290e5 | 4740 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 | 4741 | |
7f081d40 AD |
4742 | if (icr & E1000_ICR_DRSTA) |
4743 | schedule_work(&adapter->reset_task); | |
4744 | ||
047e0030 | 4745 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
4746 | /* HW is reporting DMA is out of sync */ |
4747 | adapter->stats.doosync++; | |
13800469 GR |
4748 | /* The DMA Out of Sync is also indication of a spoof event |
4749 | * in IOV mode. Check the Wrong VM Behavior register to | |
4750 | * see if it is really a spoof event. */ | |
4751 | igb_check_wvbr(adapter); | |
dda0e083 | 4752 | } |
eebbbdba | 4753 | |
4ae196df AD |
4754 | /* Check for a mailbox event */ |
4755 | if (icr & E1000_ICR_VMMB) | |
4756 | igb_msg_task(adapter); | |
4757 | ||
4758 | if (icr & E1000_ICR_LSC) { | |
4759 | hw->mac.get_link_status = 1; | |
4760 | /* guard against interrupt when we're going down */ | |
4761 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4762 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4763 | } | |
4764 | ||
1f6e8178 MV |
4765 | if (icr & E1000_ICR_TS) { |
4766 | u32 tsicr = rd32(E1000_TSICR); | |
4767 | ||
4768 | if (tsicr & E1000_TSICR_TXTS) { | |
4769 | /* acknowledge the interrupt */ | |
4770 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
4771 | /* retrieve hardware timestamp */ | |
4772 | schedule_work(&adapter->ptp_tx_work); | |
4773 | } | |
4774 | } | |
1f6e8178 | 4775 | |
844290e5 | 4776 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
4777 | |
4778 | return IRQ_HANDLED; | |
4779 | } | |
4780 | ||
047e0030 | 4781 | static void igb_write_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4782 | { |
26b39276 | 4783 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 4784 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
9d5c8243 | 4785 | |
047e0030 AD |
4786 | if (!q_vector->set_itr) |
4787 | return; | |
73cd78f1 | 4788 | |
047e0030 AD |
4789 | if (!itr_val) |
4790 | itr_val = 0x4; | |
661086df | 4791 | |
26b39276 AD |
4792 | if (adapter->hw.mac.type == e1000_82575) |
4793 | itr_val |= itr_val << 16; | |
661086df | 4794 | else |
0ba82994 | 4795 | itr_val |= E1000_EITR_CNT_IGNR; |
661086df | 4796 | |
047e0030 AD |
4797 | writel(itr_val, q_vector->itr_register); |
4798 | q_vector->set_itr = 0; | |
6eb5a7f1 AD |
4799 | } |
4800 | ||
047e0030 | 4801 | static irqreturn_t igb_msix_ring(int irq, void *data) |
9d5c8243 | 4802 | { |
047e0030 | 4803 | struct igb_q_vector *q_vector = data; |
9d5c8243 | 4804 | |
047e0030 AD |
4805 | /* Write the ITR value calculated from the previous interrupt. */ |
4806 | igb_write_itr(q_vector); | |
9d5c8243 | 4807 | |
047e0030 | 4808 | napi_schedule(&q_vector->napi); |
844290e5 | 4809 | |
047e0030 | 4810 | return IRQ_HANDLED; |
fe4506b6 JC |
4811 | } |
4812 | ||
421e02f0 | 4813 | #ifdef CONFIG_IGB_DCA |
6a05004a AD |
4814 | static void igb_update_tx_dca(struct igb_adapter *adapter, |
4815 | struct igb_ring *tx_ring, | |
4816 | int cpu) | |
4817 | { | |
4818 | struct e1000_hw *hw = &adapter->hw; | |
4819 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); | |
4820 | ||
4821 | if (hw->mac.type != e1000_82575) | |
4822 | txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; | |
4823 | ||
4824 | /* | |
4825 | * We can enable relaxed ordering for reads, but not writes when | |
4826 | * DCA is enabled. This is due to a known issue in some chipsets | |
4827 | * which will cause the DCA tag to be cleared. | |
4828 | */ | |
4829 | txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | | |
4830 | E1000_DCA_TXCTRL_DATA_RRO_EN | | |
4831 | E1000_DCA_TXCTRL_DESC_DCA_EN; | |
4832 | ||
4833 | wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); | |
4834 | } | |
4835 | ||
4836 | static void igb_update_rx_dca(struct igb_adapter *adapter, | |
4837 | struct igb_ring *rx_ring, | |
4838 | int cpu) | |
4839 | { | |
4840 | struct e1000_hw *hw = &adapter->hw; | |
4841 | u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); | |
4842 | ||
4843 | if (hw->mac.type != e1000_82575) | |
4844 | rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; | |
4845 | ||
4846 | /* | |
4847 | * We can enable relaxed ordering for reads, but not writes when | |
4848 | * DCA is enabled. This is due to a known issue in some chipsets | |
4849 | * which will cause the DCA tag to be cleared. | |
4850 | */ | |
4851 | rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | | |
4852 | E1000_DCA_RXCTRL_DESC_DCA_EN; | |
4853 | ||
4854 | wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); | |
4855 | } | |
4856 | ||
047e0030 | 4857 | static void igb_update_dca(struct igb_q_vector *q_vector) |
fe4506b6 | 4858 | { |
047e0030 | 4859 | struct igb_adapter *adapter = q_vector->adapter; |
fe4506b6 | 4860 | int cpu = get_cpu(); |
fe4506b6 | 4861 | |
047e0030 AD |
4862 | if (q_vector->cpu == cpu) |
4863 | goto out_no_update; | |
4864 | ||
6a05004a AD |
4865 | if (q_vector->tx.ring) |
4866 | igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); | |
4867 | ||
4868 | if (q_vector->rx.ring) | |
4869 | igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); | |
4870 | ||
047e0030 AD |
4871 | q_vector->cpu = cpu; |
4872 | out_no_update: | |
fe4506b6 JC |
4873 | put_cpu(); |
4874 | } | |
4875 | ||
4876 | static void igb_setup_dca(struct igb_adapter *adapter) | |
4877 | { | |
7e0e99ef | 4878 | struct e1000_hw *hw = &adapter->hw; |
fe4506b6 JC |
4879 | int i; |
4880 | ||
7dfc16fa | 4881 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
4882 | return; |
4883 | ||
7e0e99ef AD |
4884 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
4885 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | |
4886 | ||
047e0030 | 4887 | for (i = 0; i < adapter->num_q_vectors; i++) { |
26b39276 AD |
4888 | adapter->q_vector[i]->cpu = -1; |
4889 | igb_update_dca(adapter->q_vector[i]); | |
fe4506b6 JC |
4890 | } |
4891 | } | |
4892 | ||
4893 | static int __igb_notify_dca(struct device *dev, void *data) | |
4894 | { | |
4895 | struct net_device *netdev = dev_get_drvdata(dev); | |
4896 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4897 | struct pci_dev *pdev = adapter->pdev; |
fe4506b6 JC |
4898 | struct e1000_hw *hw = &adapter->hw; |
4899 | unsigned long event = *(unsigned long *)data; | |
4900 | ||
4901 | switch (event) { | |
4902 | case DCA_PROVIDER_ADD: | |
4903 | /* if already enabled, don't do it again */ | |
7dfc16fa | 4904 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 4905 | break; |
fe4506b6 | 4906 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 4907 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
090b1795 | 4908 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
4909 | igb_setup_dca(adapter); |
4910 | break; | |
4911 | } | |
4912 | /* Fall Through since DCA is disabled. */ | |
4913 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 4914 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 | 4915 | /* without this a class_device is left |
047e0030 | 4916 | * hanging around in the sysfs model */ |
fe4506b6 | 4917 | dca_remove_requester(dev); |
090b1795 | 4918 | dev_info(&pdev->dev, "DCA disabled\n"); |
7dfc16fa | 4919 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 4920 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
4921 | } |
4922 | break; | |
4923 | } | |
bbd98fe4 | 4924 | |
fe4506b6 | 4925 | return 0; |
9d5c8243 AK |
4926 | } |
4927 | ||
fe4506b6 JC |
4928 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
4929 | void *p) | |
4930 | { | |
4931 | int ret_val; | |
4932 | ||
4933 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
4934 | __igb_notify_dca); | |
4935 | ||
4936 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4937 | } | |
421e02f0 | 4938 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 4939 | |
0224d663 GR |
4940 | #ifdef CONFIG_PCI_IOV |
4941 | static int igb_vf_configure(struct igb_adapter *adapter, int vf) | |
4942 | { | |
4943 | unsigned char mac_addr[ETH_ALEN]; | |
0224d663 | 4944 | |
7efd26d0 | 4945 | eth_random_addr(mac_addr); |
0224d663 GR |
4946 | igb_set_vf_mac(adapter, vf, mac_addr); |
4947 | ||
f557147c | 4948 | return 0; |
0224d663 GR |
4949 | } |
4950 | ||
f557147c | 4951 | static bool igb_vfs_are_assigned(struct igb_adapter *adapter) |
0224d663 | 4952 | { |
0224d663 | 4953 | struct pci_dev *pdev = adapter->pdev; |
f557147c SA |
4954 | struct pci_dev *vfdev; |
4955 | int dev_id; | |
0224d663 GR |
4956 | |
4957 | switch (adapter->hw.mac.type) { | |
4958 | case e1000_82576: | |
f557147c | 4959 | dev_id = IGB_82576_VF_DEV_ID; |
0224d663 GR |
4960 | break; |
4961 | case e1000_i350: | |
f557147c | 4962 | dev_id = IGB_I350_VF_DEV_ID; |
0224d663 GR |
4963 | break; |
4964 | default: | |
f557147c | 4965 | return false; |
0224d663 GR |
4966 | } |
4967 | ||
f557147c SA |
4968 | /* loop through all the VFs to see if we own any that are assigned */ |
4969 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); | |
4970 | while (vfdev) { | |
4971 | /* if we don't own it we don't care */ | |
4972 | if (vfdev->is_virtfn && vfdev->physfn == pdev) { | |
4973 | /* if it is assigned we cannot release it */ | |
4974 | if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) | |
0224d663 GR |
4975 | return true; |
4976 | } | |
f557147c SA |
4977 | |
4978 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); | |
0224d663 | 4979 | } |
f557147c | 4980 | |
0224d663 GR |
4981 | return false; |
4982 | } | |
4983 | ||
4984 | #endif | |
4ae196df AD |
4985 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
4986 | { | |
4987 | struct e1000_hw *hw = &adapter->hw; | |
4988 | u32 ping; | |
4989 | int i; | |
4990 | ||
4991 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
4992 | ping = E1000_PF_CONTROL_MSG; | |
f2ca0dbe | 4993 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
4ae196df AD |
4994 | ping |= E1000_VT_MSGTYPE_CTS; |
4995 | igb_write_mbx(hw, &ping, 1, i); | |
4996 | } | |
4997 | } | |
4998 | ||
7d5753f0 AD |
4999 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
5000 | { | |
5001 | struct e1000_hw *hw = &adapter->hw; | |
5002 | u32 vmolr = rd32(E1000_VMOLR(vf)); | |
5003 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5004 | ||
d85b9004 | 5005 | vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | |
7d5753f0 AD |
5006 | IGB_VF_FLAG_MULTI_PROMISC); |
5007 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
5008 | ||
5009 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | |
5010 | vmolr |= E1000_VMOLR_MPME; | |
d85b9004 | 5011 | vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; |
7d5753f0 AD |
5012 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; |
5013 | } else { | |
5014 | /* | |
5015 | * if we have hashes and we are clearing a multicast promisc | |
5016 | * flag we need to write the hashes to the MTA as this step | |
5017 | * was previously skipped | |
5018 | */ | |
5019 | if (vf_data->num_vf_mc_hashes > 30) { | |
5020 | vmolr |= E1000_VMOLR_MPME; | |
5021 | } else if (vf_data->num_vf_mc_hashes) { | |
5022 | int j; | |
5023 | vmolr |= E1000_VMOLR_ROMPE; | |
5024 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5025 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5026 | } | |
5027 | } | |
5028 | ||
5029 | wr32(E1000_VMOLR(vf), vmolr); | |
5030 | ||
5031 | /* there are flags left unprocessed, likely not supported */ | |
5032 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | |
5033 | return -EINVAL; | |
5034 | ||
5035 | return 0; | |
5036 | ||
5037 | } | |
5038 | ||
4ae196df AD |
5039 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
5040 | u32 *msgbuf, u32 vf) | |
5041 | { | |
5042 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5043 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
5044 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5045 | int i; | |
5046 | ||
7d5753f0 | 5047 | /* salt away the number of multicast addresses assigned |
4ae196df AD |
5048 | * to this VF for later use to restore when the PF multi cast |
5049 | * list changes | |
5050 | */ | |
5051 | vf_data->num_vf_mc_hashes = n; | |
5052 | ||
7d5753f0 AD |
5053 | /* only up to 30 hash values supported */ |
5054 | if (n > 30) | |
5055 | n = 30; | |
5056 | ||
5057 | /* store the hashes for later use */ | |
4ae196df | 5058 | for (i = 0; i < n; i++) |
a419aef8 | 5059 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
4ae196df AD |
5060 | |
5061 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5062 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5063 | |
5064 | return 0; | |
5065 | } | |
5066 | ||
5067 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
5068 | { | |
5069 | struct e1000_hw *hw = &adapter->hw; | |
5070 | struct vf_data_storage *vf_data; | |
5071 | int i, j; | |
5072 | ||
5073 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7d5753f0 AD |
5074 | u32 vmolr = rd32(E1000_VMOLR(i)); |
5075 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
5076 | ||
4ae196df | 5077 | vf_data = &adapter->vf_data[i]; |
7d5753f0 AD |
5078 | |
5079 | if ((vf_data->num_vf_mc_hashes > 30) || | |
5080 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | |
5081 | vmolr |= E1000_VMOLR_MPME; | |
5082 | } else if (vf_data->num_vf_mc_hashes) { | |
5083 | vmolr |= E1000_VMOLR_ROMPE; | |
5084 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5085 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5086 | } | |
5087 | wr32(E1000_VMOLR(i), vmolr); | |
4ae196df AD |
5088 | } |
5089 | } | |
5090 | ||
5091 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
5092 | { | |
5093 | struct e1000_hw *hw = &adapter->hw; | |
5094 | u32 pool_mask, reg, vid; | |
5095 | int i; | |
5096 | ||
5097 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5098 | ||
5099 | /* Find the vlan filter for this id */ | |
5100 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5101 | reg = rd32(E1000_VLVF(i)); | |
5102 | ||
5103 | /* remove the vf from the pool */ | |
5104 | reg &= ~pool_mask; | |
5105 | ||
5106 | /* if pool is empty then remove entry from vfta */ | |
5107 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
5108 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
5109 | reg = 0; | |
5110 | vid = reg & E1000_VLVF_VLANID_MASK; | |
5111 | igb_vfta_set(hw, vid, false); | |
5112 | } | |
5113 | ||
5114 | wr32(E1000_VLVF(i), reg); | |
5115 | } | |
ae641bdc AD |
5116 | |
5117 | adapter->vf_data[vf].vlans_enabled = 0; | |
4ae196df AD |
5118 | } |
5119 | ||
5120 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
5121 | { | |
5122 | struct e1000_hw *hw = &adapter->hw; | |
5123 | u32 reg, i; | |
5124 | ||
51466239 AD |
5125 | /* The vlvf table only exists on 82576 hardware and newer */ |
5126 | if (hw->mac.type < e1000_82576) | |
5127 | return -1; | |
5128 | ||
5129 | /* we only need to do this if VMDq is enabled */ | |
4ae196df AD |
5130 | if (!adapter->vfs_allocated_count) |
5131 | return -1; | |
5132 | ||
5133 | /* Find the vlan filter for this id */ | |
5134 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5135 | reg = rd32(E1000_VLVF(i)); | |
5136 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
5137 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
5138 | break; | |
5139 | } | |
5140 | ||
5141 | if (add) { | |
5142 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
5143 | /* Did not find a matching VLAN ID entry that was | |
5144 | * enabled. Search for a free filter entry, i.e. | |
5145 | * one without the enable bit set | |
5146 | */ | |
5147 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5148 | reg = rd32(E1000_VLVF(i)); | |
5149 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
5150 | break; | |
5151 | } | |
5152 | } | |
5153 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5154 | /* Found an enabled/available entry */ | |
5155 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5156 | ||
5157 | /* if !enabled we need to set this up in vfta */ | |
5158 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
51466239 AD |
5159 | /* add VID to filter table */ |
5160 | igb_vfta_set(hw, vid, true); | |
4ae196df AD |
5161 | reg |= E1000_VLVF_VLANID_ENABLE; |
5162 | } | |
cad6d05f AD |
5163 | reg &= ~E1000_VLVF_VLANID_MASK; |
5164 | reg |= vid; | |
4ae196df | 5165 | wr32(E1000_VLVF(i), reg); |
ae641bdc AD |
5166 | |
5167 | /* do not modify RLPML for PF devices */ | |
5168 | if (vf >= adapter->vfs_allocated_count) | |
5169 | return 0; | |
5170 | ||
5171 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5172 | u32 size; | |
5173 | reg = rd32(E1000_VMOLR(vf)); | |
5174 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5175 | size += 4; | |
5176 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5177 | reg |= size; | |
5178 | wr32(E1000_VMOLR(vf), reg); | |
5179 | } | |
ae641bdc | 5180 | |
51466239 | 5181 | adapter->vf_data[vf].vlans_enabled++; |
4ae196df AD |
5182 | } |
5183 | } else { | |
5184 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5185 | /* remove vf from the pool */ | |
5186 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
5187 | /* if pool is empty then remove entry from vfta */ | |
5188 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
5189 | reg = 0; | |
5190 | igb_vfta_set(hw, vid, false); | |
5191 | } | |
5192 | wr32(E1000_VLVF(i), reg); | |
ae641bdc AD |
5193 | |
5194 | /* do not modify RLPML for PF devices */ | |
5195 | if (vf >= adapter->vfs_allocated_count) | |
5196 | return 0; | |
5197 | ||
5198 | adapter->vf_data[vf].vlans_enabled--; | |
5199 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5200 | u32 size; | |
5201 | reg = rd32(E1000_VMOLR(vf)); | |
5202 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5203 | size -= 4; | |
5204 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5205 | reg |= size; | |
5206 | wr32(E1000_VMOLR(vf), reg); | |
5207 | } | |
4ae196df AD |
5208 | } |
5209 | } | |
8151d294 WM |
5210 | return 0; |
5211 | } | |
5212 | ||
5213 | static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) | |
5214 | { | |
5215 | struct e1000_hw *hw = &adapter->hw; | |
5216 | ||
5217 | if (vid) | |
5218 | wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); | |
5219 | else | |
5220 | wr32(E1000_VMVIR(vf), 0); | |
5221 | } | |
5222 | ||
5223 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
5224 | int vf, u16 vlan, u8 qos) | |
5225 | { | |
5226 | int err = 0; | |
5227 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5228 | ||
5229 | if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) | |
5230 | return -EINVAL; | |
5231 | if (vlan || qos) { | |
5232 | err = igb_vlvf_set(adapter, vlan, !!vlan, vf); | |
5233 | if (err) | |
5234 | goto out; | |
5235 | igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); | |
5236 | igb_set_vmolr(adapter, vf, !vlan); | |
5237 | adapter->vf_data[vf].pf_vlan = vlan; | |
5238 | adapter->vf_data[vf].pf_qos = qos; | |
5239 | dev_info(&adapter->pdev->dev, | |
5240 | "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); | |
5241 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
5242 | dev_warn(&adapter->pdev->dev, | |
5243 | "The VF VLAN has been set," | |
5244 | " but the PF device is not up.\n"); | |
5245 | dev_warn(&adapter->pdev->dev, | |
5246 | "Bring the PF device up before" | |
5247 | " attempting to use the VF device.\n"); | |
5248 | } | |
5249 | } else { | |
5250 | igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, | |
5251 | false, vf); | |
5252 | igb_set_vmvir(adapter, vlan, vf); | |
5253 | igb_set_vmolr(adapter, vf, true); | |
5254 | adapter->vf_data[vf].pf_vlan = 0; | |
5255 | adapter->vf_data[vf].pf_qos = 0; | |
5256 | } | |
5257 | out: | |
5258 | return err; | |
4ae196df AD |
5259 | } |
5260 | ||
5261 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |
5262 | { | |
5263 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5264 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
5265 | ||
5266 | return igb_vlvf_set(adapter, vid, add, vf); | |
5267 | } | |
5268 | ||
f2ca0dbe | 5269 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5270 | { |
8fa7e0f7 GR |
5271 | /* clear flags - except flag that indicates PF has set the MAC */ |
5272 | adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; | |
f2ca0dbe | 5273 | adapter->vf_data[vf].last_nack = jiffies; |
4ae196df AD |
5274 | |
5275 | /* reset offloads to defaults */ | |
8151d294 | 5276 | igb_set_vmolr(adapter, vf, true); |
4ae196df AD |
5277 | |
5278 | /* reset vlans for device */ | |
5279 | igb_clear_vf_vfta(adapter, vf); | |
8151d294 WM |
5280 | if (adapter->vf_data[vf].pf_vlan) |
5281 | igb_ndo_set_vf_vlan(adapter->netdev, vf, | |
5282 | adapter->vf_data[vf].pf_vlan, | |
5283 | adapter->vf_data[vf].pf_qos); | |
5284 | else | |
5285 | igb_clear_vf_vfta(adapter, vf); | |
4ae196df AD |
5286 | |
5287 | /* reset multicast table array for vf */ | |
5288 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
5289 | ||
5290 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5291 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5292 | } |
5293 | ||
f2ca0dbe AD |
5294 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
5295 | { | |
5296 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
5297 | ||
5298 | /* generate a new mac address as we were hotplug removed/added */ | |
8151d294 | 5299 | if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) |
7efd26d0 | 5300 | eth_random_addr(vf_mac); |
f2ca0dbe AD |
5301 | |
5302 | /* process remaining reset events */ | |
5303 | igb_vf_reset(adapter, vf); | |
5304 | } | |
5305 | ||
5306 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
4ae196df AD |
5307 | { |
5308 | struct e1000_hw *hw = &adapter->hw; | |
5309 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
ff41f8dc | 5310 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df AD |
5311 | u32 reg, msgbuf[3]; |
5312 | u8 *addr = (u8 *)(&msgbuf[1]); | |
5313 | ||
5314 | /* process all the same items cleared in a function level reset */ | |
f2ca0dbe | 5315 | igb_vf_reset(adapter, vf); |
4ae196df AD |
5316 | |
5317 | /* set vf mac address */ | |
26ad9178 | 5318 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4ae196df AD |
5319 | |
5320 | /* enable transmit and receive for vf */ | |
5321 | reg = rd32(E1000_VFTE); | |
5322 | wr32(E1000_VFTE, reg | (1 << vf)); | |
5323 | reg = rd32(E1000_VFRE); | |
5324 | wr32(E1000_VFRE, reg | (1 << vf)); | |
5325 | ||
8fa7e0f7 | 5326 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; |
4ae196df AD |
5327 | |
5328 | /* reply to reset with ack and vf mac address */ | |
5329 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
5330 | memcpy(addr, vf_mac, 6); | |
5331 | igb_write_mbx(hw, msgbuf, 3, vf); | |
5332 | } | |
5333 | ||
5334 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
5335 | { | |
de42edde GR |
5336 | /* |
5337 | * The VF MAC Address is stored in a packed array of bytes | |
5338 | * starting at the second 32 bit word of the msg array | |
5339 | */ | |
f2ca0dbe AD |
5340 | unsigned char *addr = (char *)&msg[1]; |
5341 | int err = -1; | |
4ae196df | 5342 | |
f2ca0dbe AD |
5343 | if (is_valid_ether_addr(addr)) |
5344 | err = igb_set_vf_mac(adapter, vf, addr); | |
4ae196df | 5345 | |
f2ca0dbe | 5346 | return err; |
4ae196df AD |
5347 | } |
5348 | ||
5349 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
5350 | { | |
5351 | struct e1000_hw *hw = &adapter->hw; | |
f2ca0dbe | 5352 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5353 | u32 msg = E1000_VT_MSGTYPE_NACK; |
5354 | ||
5355 | /* if device isn't clear to send it shouldn't be reading either */ | |
f2ca0dbe AD |
5356 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
5357 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4ae196df | 5358 | igb_write_mbx(hw, &msg, 1, vf); |
f2ca0dbe | 5359 | vf_data->last_nack = jiffies; |
4ae196df AD |
5360 | } |
5361 | } | |
5362 | ||
f2ca0dbe | 5363 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5364 | { |
f2ca0dbe AD |
5365 | struct pci_dev *pdev = adapter->pdev; |
5366 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; | |
4ae196df | 5367 | struct e1000_hw *hw = &adapter->hw; |
f2ca0dbe | 5368 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5369 | s32 retval; |
5370 | ||
f2ca0dbe | 5371 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4ae196df | 5372 | |
fef45f4c AD |
5373 | if (retval) { |
5374 | /* if receive failed revoke VF CTS stats and restart init */ | |
f2ca0dbe | 5375 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
fef45f4c AD |
5376 | vf_data->flags &= ~IGB_VF_FLAG_CTS; |
5377 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) | |
5378 | return; | |
5379 | goto out; | |
5380 | } | |
4ae196df AD |
5381 | |
5382 | /* this is a message we already processed, do nothing */ | |
5383 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
f2ca0dbe | 5384 | return; |
4ae196df AD |
5385 | |
5386 | /* | |
5387 | * until the vf completes a reset it should not be | |
5388 | * allowed to start any configuration. | |
5389 | */ | |
5390 | ||
5391 | if (msgbuf[0] == E1000_VF_RESET) { | |
5392 | igb_vf_reset_msg(adapter, vf); | |
f2ca0dbe | 5393 | return; |
4ae196df AD |
5394 | } |
5395 | ||
f2ca0dbe | 5396 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
fef45f4c AD |
5397 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
5398 | return; | |
5399 | retval = -1; | |
5400 | goto out; | |
4ae196df AD |
5401 | } |
5402 | ||
5403 | switch ((msgbuf[0] & 0xFFFF)) { | |
5404 | case E1000_VF_SET_MAC_ADDR: | |
a6b5ea35 GR |
5405 | retval = -EINVAL; |
5406 | if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) | |
5407 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
5408 | else | |
5409 | dev_warn(&pdev->dev, | |
5410 | "VF %d attempted to override administratively " | |
5411 | "set MAC address\nReload the VF driver to " | |
5412 | "resume operations\n", vf); | |
4ae196df | 5413 | break; |
7d5753f0 AD |
5414 | case E1000_VF_SET_PROMISC: |
5415 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | |
5416 | break; | |
4ae196df AD |
5417 | case E1000_VF_SET_MULTICAST: |
5418 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
5419 | break; | |
5420 | case E1000_VF_SET_LPE: | |
5421 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
5422 | break; | |
5423 | case E1000_VF_SET_VLAN: | |
a6b5ea35 GR |
5424 | retval = -1; |
5425 | if (vf_data->pf_vlan) | |
5426 | dev_warn(&pdev->dev, | |
5427 | "VF %d attempted to override administratively " | |
5428 | "set VLAN tag\nReload the VF driver to " | |
5429 | "resume operations\n", vf); | |
8151d294 WM |
5430 | else |
5431 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4ae196df AD |
5432 | break; |
5433 | default: | |
090b1795 | 5434 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4ae196df AD |
5435 | retval = -1; |
5436 | break; | |
5437 | } | |
5438 | ||
fef45f4c AD |
5439 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; |
5440 | out: | |
4ae196df AD |
5441 | /* notify the VF of the results of what it sent us */ |
5442 | if (retval) | |
5443 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
5444 | else | |
5445 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
5446 | ||
4ae196df | 5447 | igb_write_mbx(hw, msgbuf, 1, vf); |
f2ca0dbe | 5448 | } |
4ae196df | 5449 | |
f2ca0dbe AD |
5450 | static void igb_msg_task(struct igb_adapter *adapter) |
5451 | { | |
5452 | struct e1000_hw *hw = &adapter->hw; | |
5453 | u32 vf; | |
5454 | ||
5455 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
5456 | /* process any reset requests */ | |
5457 | if (!igb_check_for_rst(hw, vf)) | |
5458 | igb_vf_reset_event(adapter, vf); | |
5459 | ||
5460 | /* process any messages pending */ | |
5461 | if (!igb_check_for_msg(hw, vf)) | |
5462 | igb_rcv_msg_from_vf(adapter, vf); | |
5463 | ||
5464 | /* process any acks */ | |
5465 | if (!igb_check_for_ack(hw, vf)) | |
5466 | igb_rcv_ack_from_vf(adapter, vf); | |
5467 | } | |
4ae196df AD |
5468 | } |
5469 | ||
68d480c4 AD |
5470 | /** |
5471 | * igb_set_uta - Set unicast filter table address | |
5472 | * @adapter: board private structure | |
5473 | * | |
5474 | * The unicast table address is a register array of 32-bit registers. | |
5475 | * The table is meant to be used in a way similar to how the MTA is used | |
5476 | * however due to certain limitations in the hardware it is necessary to | |
25985edc LDM |
5477 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous |
5478 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
68d480c4 AD |
5479 | **/ |
5480 | static void igb_set_uta(struct igb_adapter *adapter) | |
5481 | { | |
5482 | struct e1000_hw *hw = &adapter->hw; | |
5483 | int i; | |
5484 | ||
5485 | /* The UTA table only exists on 82576 hardware and newer */ | |
5486 | if (hw->mac.type < e1000_82576) | |
5487 | return; | |
5488 | ||
5489 | /* we only need to do this if VMDq is enabled */ | |
5490 | if (!adapter->vfs_allocated_count) | |
5491 | return; | |
5492 | ||
5493 | for (i = 0; i < hw->mac.uta_reg_count; i++) | |
5494 | array_wr32(E1000_UTA, i, ~0); | |
5495 | } | |
5496 | ||
9d5c8243 AK |
5497 | /** |
5498 | * igb_intr_msi - Interrupt Handler | |
5499 | * @irq: interrupt number | |
5500 | * @data: pointer to a network interface device structure | |
5501 | **/ | |
5502 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
5503 | { | |
047e0030 AD |
5504 | struct igb_adapter *adapter = data; |
5505 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5506 | struct e1000_hw *hw = &adapter->hw; |
5507 | /* read ICR disables interrupts using IAM */ | |
5508 | u32 icr = rd32(E1000_ICR); | |
5509 | ||
047e0030 | 5510 | igb_write_itr(q_vector); |
9d5c8243 | 5511 | |
7f081d40 AD |
5512 | if (icr & E1000_ICR_DRSTA) |
5513 | schedule_work(&adapter->reset_task); | |
5514 | ||
047e0030 | 5515 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5516 | /* HW is reporting DMA is out of sync */ |
5517 | adapter->stats.doosync++; | |
5518 | } | |
5519 | ||
9d5c8243 AK |
5520 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5521 | hw->mac.get_link_status = 1; | |
5522 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5523 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5524 | } | |
5525 | ||
1f6e8178 MV |
5526 | if (icr & E1000_ICR_TS) { |
5527 | u32 tsicr = rd32(E1000_TSICR); | |
5528 | ||
5529 | if (tsicr & E1000_TSICR_TXTS) { | |
5530 | /* acknowledge the interrupt */ | |
5531 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5532 | /* retrieve hardware timestamp */ | |
5533 | schedule_work(&adapter->ptp_tx_work); | |
5534 | } | |
5535 | } | |
1f6e8178 | 5536 | |
047e0030 | 5537 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5538 | |
5539 | return IRQ_HANDLED; | |
5540 | } | |
5541 | ||
5542 | /** | |
4a3c6433 | 5543 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
5544 | * @irq: interrupt number |
5545 | * @data: pointer to a network interface device structure | |
5546 | **/ | |
5547 | static irqreturn_t igb_intr(int irq, void *data) | |
5548 | { | |
047e0030 AD |
5549 | struct igb_adapter *adapter = data; |
5550 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5551 | struct e1000_hw *hw = &adapter->hw; |
5552 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
5553 | * need for the IMC write */ | |
5554 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
5555 | |
5556 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
5557 | * not set, then the adapter didn't send an interrupt */ | |
5558 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
5559 | return IRQ_NONE; | |
5560 | ||
0ba82994 AD |
5561 | igb_write_itr(q_vector); |
5562 | ||
7f081d40 AD |
5563 | if (icr & E1000_ICR_DRSTA) |
5564 | schedule_work(&adapter->reset_task); | |
5565 | ||
047e0030 | 5566 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5567 | /* HW is reporting DMA is out of sync */ |
5568 | adapter->stats.doosync++; | |
5569 | } | |
5570 | ||
9d5c8243 AK |
5571 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5572 | hw->mac.get_link_status = 1; | |
5573 | /* guard against interrupt when we're going down */ | |
5574 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5575 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5576 | } | |
5577 | ||
1f6e8178 MV |
5578 | if (icr & E1000_ICR_TS) { |
5579 | u32 tsicr = rd32(E1000_TSICR); | |
5580 | ||
5581 | if (tsicr & E1000_TSICR_TXTS) { | |
5582 | /* acknowledge the interrupt */ | |
5583 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5584 | /* retrieve hardware timestamp */ | |
5585 | schedule_work(&adapter->ptp_tx_work); | |
5586 | } | |
5587 | } | |
1f6e8178 | 5588 | |
047e0030 | 5589 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5590 | |
5591 | return IRQ_HANDLED; | |
5592 | } | |
5593 | ||
c50b52a0 | 5594 | static void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
9d5c8243 | 5595 | { |
047e0030 | 5596 | struct igb_adapter *adapter = q_vector->adapter; |
46544258 | 5597 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5598 | |
0ba82994 AD |
5599 | if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || |
5600 | (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { | |
5601 | if ((adapter->num_q_vectors == 1) && !adapter->vf_data) | |
5602 | igb_set_itr(q_vector); | |
46544258 | 5603 | else |
047e0030 | 5604 | igb_update_ring_itr(q_vector); |
9d5c8243 AK |
5605 | } |
5606 | ||
46544258 AD |
5607 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
5608 | if (adapter->msix_entries) | |
047e0030 | 5609 | wr32(E1000_EIMS, q_vector->eims_value); |
46544258 AD |
5610 | else |
5611 | igb_irq_enable(adapter); | |
5612 | } | |
9d5c8243 AK |
5613 | } |
5614 | ||
46544258 AD |
5615 | /** |
5616 | * igb_poll - NAPI Rx polling callback | |
5617 | * @napi: napi polling structure | |
5618 | * @budget: count of how many packets we should handle | |
5619 | **/ | |
5620 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 | 5621 | { |
047e0030 AD |
5622 | struct igb_q_vector *q_vector = container_of(napi, |
5623 | struct igb_q_vector, | |
5624 | napi); | |
16eb8815 | 5625 | bool clean_complete = true; |
9d5c8243 | 5626 | |
421e02f0 | 5627 | #ifdef CONFIG_IGB_DCA |
047e0030 AD |
5628 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
5629 | igb_update_dca(q_vector); | |
fe4506b6 | 5630 | #endif |
0ba82994 | 5631 | if (q_vector->tx.ring) |
13fde97a | 5632 | clean_complete = igb_clean_tx_irq(q_vector); |
9d5c8243 | 5633 | |
0ba82994 | 5634 | if (q_vector->rx.ring) |
cd392f5c | 5635 | clean_complete &= igb_clean_rx_irq(q_vector, budget); |
047e0030 | 5636 | |
16eb8815 AD |
5637 | /* If all work not completed, return budget and keep polling */ |
5638 | if (!clean_complete) | |
5639 | return budget; | |
46544258 | 5640 | |
9d5c8243 | 5641 | /* If not enough Rx work done, exit the polling mode */ |
16eb8815 AD |
5642 | napi_complete(napi); |
5643 | igb_ring_irq_enable(q_vector); | |
9d5c8243 | 5644 | |
16eb8815 | 5645 | return 0; |
9d5c8243 | 5646 | } |
6d8126f9 | 5647 | |
9d5c8243 AK |
5648 | /** |
5649 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
047e0030 | 5650 | * @q_vector: pointer to q_vector containing needed info |
49ce9c2c | 5651 | * |
9d5c8243 AK |
5652 | * returns true if ring is completely cleaned |
5653 | **/ | |
047e0030 | 5654 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
9d5c8243 | 5655 | { |
047e0030 | 5656 | struct igb_adapter *adapter = q_vector->adapter; |
0ba82994 | 5657 | struct igb_ring *tx_ring = q_vector->tx.ring; |
06034649 | 5658 | struct igb_tx_buffer *tx_buffer; |
f4128785 | 5659 | union e1000_adv_tx_desc *tx_desc; |
9d5c8243 | 5660 | unsigned int total_bytes = 0, total_packets = 0; |
0ba82994 | 5661 | unsigned int budget = q_vector->tx.work_limit; |
8542db05 | 5662 | unsigned int i = tx_ring->next_to_clean; |
9d5c8243 | 5663 | |
13fde97a AD |
5664 | if (test_bit(__IGB_DOWN, &adapter->state)) |
5665 | return true; | |
0e014cb1 | 5666 | |
06034649 | 5667 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
13fde97a | 5668 | tx_desc = IGB_TX_DESC(tx_ring, i); |
8542db05 | 5669 | i -= tx_ring->count; |
9d5c8243 | 5670 | |
f4128785 AD |
5671 | do { |
5672 | union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; | |
8542db05 AD |
5673 | |
5674 | /* if next_to_watch is not set then there is no work pending */ | |
5675 | if (!eop_desc) | |
5676 | break; | |
13fde97a | 5677 | |
f4128785 AD |
5678 | /* prevent any other reads prior to eop_desc */ |
5679 | rmb(); | |
5680 | ||
13fde97a AD |
5681 | /* if DD is not set pending work has not been completed */ |
5682 | if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) | |
5683 | break; | |
5684 | ||
8542db05 AD |
5685 | /* clear next_to_watch to prevent false hangs */ |
5686 | tx_buffer->next_to_watch = NULL; | |
9d5c8243 | 5687 | |
ebe42d16 AD |
5688 | /* update the statistics for this packet */ |
5689 | total_bytes += tx_buffer->bytecount; | |
5690 | total_packets += tx_buffer->gso_segs; | |
13fde97a | 5691 | |
ebe42d16 AD |
5692 | /* free the skb */ |
5693 | dev_kfree_skb_any(tx_buffer->skb); | |
13fde97a | 5694 | |
ebe42d16 AD |
5695 | /* unmap skb header data */ |
5696 | dma_unmap_single(tx_ring->dev, | |
c9f14bf3 AD |
5697 | dma_unmap_addr(tx_buffer, dma), |
5698 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
5699 | DMA_TO_DEVICE); |
5700 | ||
c9f14bf3 AD |
5701 | /* clear tx_buffer data */ |
5702 | tx_buffer->skb = NULL; | |
5703 | dma_unmap_len_set(tx_buffer, len, 0); | |
5704 | ||
ebe42d16 AD |
5705 | /* clear last DMA location and unmap remaining buffers */ |
5706 | while (tx_desc != eop_desc) { | |
13fde97a AD |
5707 | tx_buffer++; |
5708 | tx_desc++; | |
9d5c8243 | 5709 | i++; |
8542db05 AD |
5710 | if (unlikely(!i)) { |
5711 | i -= tx_ring->count; | |
06034649 | 5712 | tx_buffer = tx_ring->tx_buffer_info; |
13fde97a AD |
5713 | tx_desc = IGB_TX_DESC(tx_ring, 0); |
5714 | } | |
ebe42d16 AD |
5715 | |
5716 | /* unmap any remaining paged data */ | |
c9f14bf3 | 5717 | if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 5718 | dma_unmap_page(tx_ring->dev, |
c9f14bf3 AD |
5719 | dma_unmap_addr(tx_buffer, dma), |
5720 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 5721 | DMA_TO_DEVICE); |
c9f14bf3 | 5722 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 AD |
5723 | } |
5724 | } | |
5725 | ||
ebe42d16 AD |
5726 | /* move us one more past the eop_desc for start of next pkt */ |
5727 | tx_buffer++; | |
5728 | tx_desc++; | |
5729 | i++; | |
5730 | if (unlikely(!i)) { | |
5731 | i -= tx_ring->count; | |
5732 | tx_buffer = tx_ring->tx_buffer_info; | |
5733 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
5734 | } | |
f4128785 AD |
5735 | |
5736 | /* issue prefetch for next Tx descriptor */ | |
5737 | prefetch(tx_desc); | |
5738 | ||
5739 | /* update budget accounting */ | |
5740 | budget--; | |
5741 | } while (likely(budget)); | |
0e014cb1 | 5742 | |
bdbc0631 ED |
5743 | netdev_tx_completed_queue(txring_txq(tx_ring), |
5744 | total_packets, total_bytes); | |
8542db05 | 5745 | i += tx_ring->count; |
9d5c8243 | 5746 | tx_ring->next_to_clean = i; |
13fde97a AD |
5747 | u64_stats_update_begin(&tx_ring->tx_syncp); |
5748 | tx_ring->tx_stats.bytes += total_bytes; | |
5749 | tx_ring->tx_stats.packets += total_packets; | |
5750 | u64_stats_update_end(&tx_ring->tx_syncp); | |
0ba82994 AD |
5751 | q_vector->tx.total_bytes += total_bytes; |
5752 | q_vector->tx.total_packets += total_packets; | |
9d5c8243 | 5753 | |
6d095fa8 | 5754 | if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { |
13fde97a | 5755 | struct e1000_hw *hw = &adapter->hw; |
12dcd86b | 5756 | |
9d5c8243 AK |
5757 | /* Detect a transmit hang in hardware, this serializes the |
5758 | * check with the clearing of time_stamp and movement of i */ | |
6d095fa8 | 5759 | clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
f4128785 | 5760 | if (tx_buffer->next_to_watch && |
8542db05 | 5761 | time_after(jiffies, tx_buffer->time_stamp + |
8e95a202 JP |
5762 | (adapter->tx_timeout_factor * HZ)) && |
5763 | !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { | |
9d5c8243 | 5764 | |
9d5c8243 | 5765 | /* detected Tx unit hang */ |
59d71989 | 5766 | dev_err(tx_ring->dev, |
9d5c8243 | 5767 | "Detected Tx Unit Hang\n" |
2d064c06 | 5768 | " Tx Queue <%d>\n" |
9d5c8243 AK |
5769 | " TDH <%x>\n" |
5770 | " TDT <%x>\n" | |
5771 | " next_to_use <%x>\n" | |
5772 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
5773 | "buffer_info[next_to_clean]\n" |
5774 | " time_stamp <%lx>\n" | |
8542db05 | 5775 | " next_to_watch <%p>\n" |
9d5c8243 AK |
5776 | " jiffies <%lx>\n" |
5777 | " desc.status <%x>\n", | |
2d064c06 | 5778 | tx_ring->queue_index, |
238ac817 | 5779 | rd32(E1000_TDH(tx_ring->reg_idx)), |
fce99e34 | 5780 | readl(tx_ring->tail), |
9d5c8243 AK |
5781 | tx_ring->next_to_use, |
5782 | tx_ring->next_to_clean, | |
8542db05 | 5783 | tx_buffer->time_stamp, |
f4128785 | 5784 | tx_buffer->next_to_watch, |
9d5c8243 | 5785 | jiffies, |
f4128785 | 5786 | tx_buffer->next_to_watch->wb.status); |
13fde97a AD |
5787 | netif_stop_subqueue(tx_ring->netdev, |
5788 | tx_ring->queue_index); | |
5789 | ||
5790 | /* we are about to reset, no point in enabling stuff */ | |
5791 | return true; | |
9d5c8243 AK |
5792 | } |
5793 | } | |
13fde97a AD |
5794 | |
5795 | if (unlikely(total_packets && | |
5796 | netif_carrier_ok(tx_ring->netdev) && | |
5797 | igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { | |
5798 | /* Make sure that anybody stopping the queue after this | |
5799 | * sees the new next_to_clean. | |
5800 | */ | |
5801 | smp_mb(); | |
5802 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
5803 | tx_ring->queue_index) && | |
5804 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
5805 | netif_wake_subqueue(tx_ring->netdev, | |
5806 | tx_ring->queue_index); | |
5807 | ||
5808 | u64_stats_update_begin(&tx_ring->tx_syncp); | |
5809 | tx_ring->tx_stats.restart_queue++; | |
5810 | u64_stats_update_end(&tx_ring->tx_syncp); | |
5811 | } | |
5812 | } | |
5813 | ||
5814 | return !!budget; | |
9d5c8243 AK |
5815 | } |
5816 | ||
cbc8e55f AD |
5817 | /** |
5818 | * igb_reuse_rx_page - page flip buffer and store it back on the ring | |
5819 | * @rx_ring: rx descriptor ring to store buffers on | |
5820 | * @old_buff: donor buffer to have page reused | |
5821 | * | |
5822 | * Synchronizes page for reuse by the adapter | |
5823 | **/ | |
5824 | static void igb_reuse_rx_page(struct igb_ring *rx_ring, | |
5825 | struct igb_rx_buffer *old_buff) | |
5826 | { | |
5827 | struct igb_rx_buffer *new_buff; | |
5828 | u16 nta = rx_ring->next_to_alloc; | |
5829 | ||
5830 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
5831 | ||
5832 | /* update, and store next to alloc */ | |
5833 | nta++; | |
5834 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
5835 | ||
5836 | /* transfer page from old buffer to new buffer */ | |
5837 | memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); | |
5838 | ||
5839 | /* sync the buffer for use by the device */ | |
5840 | dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, | |
5841 | old_buff->page_offset, | |
de78d1f9 | 5842 | IGB_RX_BUFSZ, |
cbc8e55f AD |
5843 | DMA_FROM_DEVICE); |
5844 | } | |
5845 | ||
5846 | /** | |
5847 | * igb_add_rx_frag - Add contents of Rx buffer to sk_buff | |
5848 | * @rx_ring: rx descriptor ring to transact packets on | |
5849 | * @rx_buffer: buffer containing page to add | |
5850 | * @rx_desc: descriptor containing length of buffer written by hardware | |
5851 | * @skb: sk_buff to place the data into | |
5852 | * | |
5853 | * This function will add the data contained in rx_buffer->page to the skb. | |
5854 | * This is done either through a direct copy if the data in the buffer is | |
5855 | * less than the skb header size, otherwise it will just attach the page as | |
5856 | * a frag to the skb. | |
5857 | * | |
5858 | * The function will then update the page offset if necessary and return | |
5859 | * true if the buffer can be reused by the adapter. | |
5860 | **/ | |
5861 | static bool igb_add_rx_frag(struct igb_ring *rx_ring, | |
5862 | struct igb_rx_buffer *rx_buffer, | |
5863 | union e1000_adv_rx_desc *rx_desc, | |
5864 | struct sk_buff *skb) | |
5865 | { | |
5866 | struct page *page = rx_buffer->page; | |
5867 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
5868 | ||
5869 | if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { | |
5870 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
5871 | ||
cbc8e55f AD |
5872 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
5873 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
5874 | va += IGB_TS_HDR_LEN; | |
5875 | size -= IGB_TS_HDR_LEN; | |
5876 | } | |
5877 | ||
cbc8e55f AD |
5878 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
5879 | ||
5880 | /* we can reuse buffer as-is, just make sure it is local */ | |
5881 | if (likely(page_to_nid(page) == numa_node_id())) | |
5882 | return true; | |
5883 | ||
5884 | /* this page cannot be reused so discard it */ | |
5885 | put_page(page); | |
5886 | return false; | |
5887 | } | |
5888 | ||
5889 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, | |
de78d1f9 | 5890 | rx_buffer->page_offset, size, IGB_RX_BUFSZ); |
cbc8e55f AD |
5891 | |
5892 | /* avoid re-using remote pages */ | |
5893 | if (unlikely(page_to_nid(page) != numa_node_id())) | |
5894 | return false; | |
5895 | ||
de78d1f9 | 5896 | #if (PAGE_SIZE < 8192) |
cbc8e55f AD |
5897 | /* if we are only owner of page we can reuse it */ |
5898 | if (unlikely(page_count(page) != 1)) | |
5899 | return false; | |
5900 | ||
5901 | /* flip page offset to other buffer */ | |
de78d1f9 | 5902 | rx_buffer->page_offset ^= IGB_RX_BUFSZ; |
cbc8e55f AD |
5903 | |
5904 | /* | |
5905 | * since we are the only owner of the page and we need to | |
5906 | * increment it, just set the value to 2 in order to avoid | |
5907 | * an unnecessary locked operation | |
5908 | */ | |
5909 | atomic_set(&page->_count, 2); | |
de78d1f9 AD |
5910 | #else |
5911 | /* move offset up to the next cache line */ | |
5912 | rx_buffer->page_offset += SKB_DATA_ALIGN(size); | |
5913 | ||
5914 | if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) | |
5915 | return false; | |
5916 | ||
5917 | /* bump ref count on page before it is given to the stack */ | |
5918 | get_page(page); | |
5919 | #endif | |
cbc8e55f AD |
5920 | |
5921 | return true; | |
5922 | } | |
5923 | ||
2e334eee AD |
5924 | static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, |
5925 | union e1000_adv_rx_desc *rx_desc, | |
5926 | struct sk_buff *skb) | |
5927 | { | |
5928 | struct igb_rx_buffer *rx_buffer; | |
5929 | struct page *page; | |
5930 | ||
5931 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
5932 | ||
5933 | /* | |
5934 | * This memory barrier is needed to keep us from reading | |
5935 | * any other fields out of the rx_desc until we know the | |
5936 | * RXD_STAT_DD bit is set | |
5937 | */ | |
5938 | rmb(); | |
5939 | ||
5940 | page = rx_buffer->page; | |
5941 | prefetchw(page); | |
5942 | ||
5943 | if (likely(!skb)) { | |
5944 | void *page_addr = page_address(page) + | |
5945 | rx_buffer->page_offset; | |
5946 | ||
5947 | /* prefetch first cache line of first page */ | |
5948 | prefetch(page_addr); | |
5949 | #if L1_CACHE_BYTES < 128 | |
5950 | prefetch(page_addr + L1_CACHE_BYTES); | |
5951 | #endif | |
5952 | ||
5953 | /* allocate a skb to store the frags */ | |
5954 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
5955 | IGB_RX_HDR_LEN); | |
5956 | if (unlikely(!skb)) { | |
5957 | rx_ring->rx_stats.alloc_failed++; | |
5958 | return NULL; | |
5959 | } | |
5960 | ||
5961 | /* | |
5962 | * we will be copying header into skb->data in | |
5963 | * pskb_may_pull so it is in our interest to prefetch | |
5964 | * it now to avoid a possible cache miss | |
5965 | */ | |
5966 | prefetchw(skb->data); | |
5967 | } | |
5968 | ||
5969 | /* we are reusing so sync this buffer for CPU use */ | |
5970 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
5971 | rx_buffer->dma, | |
5972 | rx_buffer->page_offset, | |
de78d1f9 | 5973 | IGB_RX_BUFSZ, |
2e334eee AD |
5974 | DMA_FROM_DEVICE); |
5975 | ||
5976 | /* pull page into skb */ | |
5977 | if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
5978 | /* hand second half of page back to the ring */ | |
5979 | igb_reuse_rx_page(rx_ring, rx_buffer); | |
5980 | } else { | |
5981 | /* we are not reusing the buffer so unmap it */ | |
5982 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
5983 | PAGE_SIZE, DMA_FROM_DEVICE); | |
5984 | } | |
5985 | ||
5986 | /* clear contents of rx_buffer */ | |
5987 | rx_buffer->page = NULL; | |
5988 | ||
5989 | return skb; | |
5990 | } | |
5991 | ||
cd392f5c | 5992 | static inline void igb_rx_checksum(struct igb_ring *ring, |
3ceb90fd AD |
5993 | union e1000_adv_rx_desc *rx_desc, |
5994 | struct sk_buff *skb) | |
9d5c8243 | 5995 | { |
bc8acf2c | 5996 | skb_checksum_none_assert(skb); |
9d5c8243 | 5997 | |
294e7d78 | 5998 | /* Ignore Checksum bit is set */ |
3ceb90fd | 5999 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) |
294e7d78 AD |
6000 | return; |
6001 | ||
6002 | /* Rx checksum disabled via ethtool */ | |
6003 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) | |
9d5c8243 | 6004 | return; |
85ad76b2 | 6005 | |
9d5c8243 | 6006 | /* TCP/UDP checksum error bit is set */ |
3ceb90fd AD |
6007 | if (igb_test_staterr(rx_desc, |
6008 | E1000_RXDEXT_STATERR_TCPE | | |
6009 | E1000_RXDEXT_STATERR_IPE)) { | |
b9473560 JB |
6010 | /* |
6011 | * work around errata with sctp packets where the TCPE aka | |
6012 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) | |
6013 | * packets, (aka let the stack check the crc32c) | |
6014 | */ | |
866cff06 AD |
6015 | if (!((skb->len == 60) && |
6016 | test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { | |
12dcd86b | 6017 | u64_stats_update_begin(&ring->rx_syncp); |
04a5fcaa | 6018 | ring->rx_stats.csum_err++; |
12dcd86b ED |
6019 | u64_stats_update_end(&ring->rx_syncp); |
6020 | } | |
9d5c8243 | 6021 | /* let the stack verify checksum errors */ |
9d5c8243 AK |
6022 | return; |
6023 | } | |
6024 | /* It must be a TCP or UDP packet with a valid checksum */ | |
3ceb90fd AD |
6025 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | |
6026 | E1000_RXD_STAT_UDPCS)) | |
9d5c8243 AK |
6027 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
6028 | ||
3ceb90fd AD |
6029 | dev_dbg(ring->dev, "cksum success: bits %08X\n", |
6030 | le32_to_cpu(rx_desc->wb.upper.status_error)); | |
9d5c8243 AK |
6031 | } |
6032 | ||
077887c3 AD |
6033 | static inline void igb_rx_hash(struct igb_ring *ring, |
6034 | union e1000_adv_rx_desc *rx_desc, | |
6035 | struct sk_buff *skb) | |
6036 | { | |
6037 | if (ring->netdev->features & NETIF_F_RXHASH) | |
6038 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
6039 | } | |
6040 | ||
2e334eee AD |
6041 | /** |
6042 | * igb_is_non_eop - process handling of non-EOP buffers | |
6043 | * @rx_ring: Rx ring being processed | |
6044 | * @rx_desc: Rx descriptor for current buffer | |
6045 | * @skb: current socket buffer containing buffer in progress | |
6046 | * | |
6047 | * This function updates next to clean. If the buffer is an EOP buffer | |
6048 | * this function exits returning false, otherwise it will place the | |
6049 | * sk_buff in the next buffer to be chained and return true indicating | |
6050 | * that this is in fact a non-EOP buffer. | |
6051 | **/ | |
6052 | static bool igb_is_non_eop(struct igb_ring *rx_ring, | |
6053 | union e1000_adv_rx_desc *rx_desc) | |
6054 | { | |
6055 | u32 ntc = rx_ring->next_to_clean + 1; | |
6056 | ||
6057 | /* fetch, update, and store next to clean */ | |
6058 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
6059 | rx_ring->next_to_clean = ntc; | |
6060 | ||
6061 | prefetch(IGB_RX_DESC(rx_ring, ntc)); | |
6062 | ||
6063 | if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) | |
6064 | return false; | |
6065 | ||
6066 | return true; | |
6067 | } | |
6068 | ||
1a1c225b AD |
6069 | /** |
6070 | * igb_get_headlen - determine size of header for LRO/GRO | |
6071 | * @data: pointer to the start of the headers | |
6072 | * @max_len: total length of section to find headers in | |
6073 | * | |
6074 | * This function is meant to determine the length of headers that will | |
6075 | * be recognized by hardware for LRO, and GRO offloads. The main | |
6076 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
6077 | * packets so that we can do basic things like calculating the gso_size | |
6078 | * based on the average data per packet. | |
6079 | **/ | |
6080 | static unsigned int igb_get_headlen(unsigned char *data, | |
6081 | unsigned int max_len) | |
6082 | { | |
6083 | union { | |
6084 | unsigned char *network; | |
6085 | /* l2 headers */ | |
6086 | struct ethhdr *eth; | |
6087 | struct vlan_hdr *vlan; | |
6088 | /* l3 headers */ | |
6089 | struct iphdr *ipv4; | |
6090 | struct ipv6hdr *ipv6; | |
6091 | } hdr; | |
6092 | __be16 protocol; | |
6093 | u8 nexthdr = 0; /* default to not TCP */ | |
6094 | u8 hlen; | |
6095 | ||
6096 | /* this should never happen, but better safe than sorry */ | |
6097 | if (max_len < ETH_HLEN) | |
6098 | return max_len; | |
6099 | ||
6100 | /* initialize network frame pointer */ | |
6101 | hdr.network = data; | |
6102 | ||
6103 | /* set first protocol and move network header forward */ | |
6104 | protocol = hdr.eth->h_proto; | |
6105 | hdr.network += ETH_HLEN; | |
6106 | ||
6107 | /* handle any vlan tag if present */ | |
6108 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6109 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
6110 | return max_len; | |
6111 | ||
6112 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
6113 | hdr.network += VLAN_HLEN; | |
6114 | } | |
6115 | ||
6116 | /* handle L3 protocols */ | |
6117 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6118 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
6119 | return max_len; | |
6120 | ||
6121 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
6122 | hlen = (hdr.network[0] & 0x0F) << 2; | |
6123 | ||
6124 | /* verify hlen meets minimum size requirements */ | |
6125 | if (hlen < sizeof(struct iphdr)) | |
6126 | return hdr.network - data; | |
6127 | ||
6128 | /* record next protocol */ | |
6129 | nexthdr = hdr.ipv4->protocol; | |
6130 | hdr.network += hlen; | |
6131 | } else if (protocol == __constant_htons(ETH_P_IPV6)) { | |
6132 | if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) | |
6133 | return max_len; | |
6134 | ||
6135 | /* record next protocol */ | |
6136 | nexthdr = hdr.ipv6->nexthdr; | |
6137 | hdr.network += sizeof(struct ipv6hdr); | |
6138 | } else { | |
6139 | return hdr.network - data; | |
6140 | } | |
6141 | ||
6142 | /* finally sort out TCP */ | |
6143 | if (nexthdr == IPPROTO_TCP) { | |
6144 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
6145 | return max_len; | |
6146 | ||
6147 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
6148 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
6149 | ||
6150 | /* verify hlen meets minimum size requirements */ | |
6151 | if (hlen < sizeof(struct tcphdr)) | |
6152 | return hdr.network - data; | |
6153 | ||
6154 | hdr.network += hlen; | |
6155 | } else if (nexthdr == IPPROTO_UDP) { | |
6156 | if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) | |
6157 | return max_len; | |
6158 | ||
6159 | hdr.network += sizeof(struct udphdr); | |
6160 | } | |
6161 | ||
6162 | /* | |
6163 | * If everything has gone correctly hdr.network should be the | |
6164 | * data section of the packet and will be the end of the header. | |
6165 | * If not then it probably represents the end of the last recognized | |
6166 | * header. | |
6167 | */ | |
6168 | if ((hdr.network - data) < max_len) | |
6169 | return hdr.network - data; | |
6170 | else | |
6171 | return max_len; | |
6172 | } | |
6173 | ||
6174 | /** | |
6175 | * igb_pull_tail - igb specific version of skb_pull_tail | |
6176 | * @rx_ring: rx descriptor ring packet is being transacted on | |
cbc8e55f | 6177 | * @rx_desc: pointer to the EOP Rx descriptor |
1a1c225b AD |
6178 | * @skb: pointer to current skb being adjusted |
6179 | * | |
6180 | * This function is an igb specific version of __pskb_pull_tail. The | |
6181 | * main difference between this version and the original function is that | |
6182 | * this function can make several assumptions about the state of things | |
6183 | * that allow for significant optimizations versus the standard function. | |
6184 | * As a result we can do things like drop a frag and maintain an accurate | |
6185 | * truesize for the skb. | |
6186 | */ | |
6187 | static void igb_pull_tail(struct igb_ring *rx_ring, | |
6188 | union e1000_adv_rx_desc *rx_desc, | |
6189 | struct sk_buff *skb) | |
2d94d8ab | 6190 | { |
1a1c225b AD |
6191 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
6192 | unsigned char *va; | |
6193 | unsigned int pull_len; | |
6194 | ||
6195 | /* | |
6196 | * it is valid to use page_address instead of kmap since we are | |
6197 | * working with pages allocated out of the lomem pool per | |
6198 | * alloc_page(GFP_ATOMIC) | |
2d94d8ab | 6199 | */ |
1a1c225b AD |
6200 | va = skb_frag_address(frag); |
6201 | ||
1a1c225b AD |
6202 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
6203 | /* retrieve timestamp from buffer */ | |
6204 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
6205 | ||
6206 | /* update pointers to remove timestamp header */ | |
6207 | skb_frag_size_sub(frag, IGB_TS_HDR_LEN); | |
6208 | frag->page_offset += IGB_TS_HDR_LEN; | |
6209 | skb->data_len -= IGB_TS_HDR_LEN; | |
6210 | skb->len -= IGB_TS_HDR_LEN; | |
6211 | ||
6212 | /* move va to start of packet data */ | |
6213 | va += IGB_TS_HDR_LEN; | |
6214 | } | |
6215 | ||
1a1c225b AD |
6216 | /* |
6217 | * we need the header to contain the greater of either ETH_HLEN or | |
6218 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
6219 | */ | |
6220 | pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); | |
6221 | ||
6222 | /* align pull length to size of long to optimize memcpy performance */ | |
6223 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
6224 | ||
6225 | /* update all of the pointers */ | |
6226 | skb_frag_size_sub(frag, pull_len); | |
6227 | frag->page_offset += pull_len; | |
6228 | skb->data_len -= pull_len; | |
6229 | skb->tail += pull_len; | |
6230 | } | |
6231 | ||
6232 | /** | |
6233 | * igb_cleanup_headers - Correct corrupted or empty headers | |
6234 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6235 | * @rx_desc: pointer to the EOP Rx descriptor | |
6236 | * @skb: pointer to current skb being fixed | |
6237 | * | |
6238 | * Address the case where we are pulling data in on pages only | |
6239 | * and as such no data is present in the skb header. | |
6240 | * | |
6241 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
6242 | * it is large enough to qualify as a valid Ethernet frame. | |
6243 | * | |
6244 | * Returns true if an error was encountered and skb was freed. | |
6245 | **/ | |
6246 | static bool igb_cleanup_headers(struct igb_ring *rx_ring, | |
6247 | union e1000_adv_rx_desc *rx_desc, | |
6248 | struct sk_buff *skb) | |
6249 | { | |
6250 | ||
6251 | if (unlikely((igb_test_staterr(rx_desc, | |
6252 | E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { | |
6253 | struct net_device *netdev = rx_ring->netdev; | |
6254 | if (!(netdev->features & NETIF_F_RXALL)) { | |
6255 | dev_kfree_skb_any(skb); | |
6256 | return true; | |
6257 | } | |
6258 | } | |
6259 | ||
6260 | /* place header in linear portion of buffer */ | |
6261 | if (skb_is_nonlinear(skb)) | |
6262 | igb_pull_tail(rx_ring, rx_desc, skb); | |
6263 | ||
6264 | /* if skb_pad returns an error the skb was freed */ | |
6265 | if (unlikely(skb->len < 60)) { | |
6266 | int pad_len = 60 - skb->len; | |
6267 | ||
6268 | if (skb_pad(skb, pad_len)) | |
6269 | return true; | |
6270 | __skb_put(skb, pad_len); | |
6271 | } | |
6272 | ||
6273 | return false; | |
2d94d8ab AD |
6274 | } |
6275 | ||
db2ee5bd AD |
6276 | /** |
6277 | * igb_process_skb_fields - Populate skb header fields from Rx descriptor | |
6278 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6279 | * @rx_desc: pointer to the EOP Rx descriptor | |
6280 | * @skb: pointer to current skb being populated | |
6281 | * | |
6282 | * This function checks the ring, descriptor, and packet information in | |
6283 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
6284 | * other fields within the skb. | |
6285 | **/ | |
6286 | static void igb_process_skb_fields(struct igb_ring *rx_ring, | |
6287 | union e1000_adv_rx_desc *rx_desc, | |
6288 | struct sk_buff *skb) | |
6289 | { | |
6290 | struct net_device *dev = rx_ring->netdev; | |
6291 | ||
6292 | igb_rx_hash(rx_ring, rx_desc, skb); | |
6293 | ||
6294 | igb_rx_checksum(rx_ring, rx_desc, skb); | |
6295 | ||
db2ee5bd | 6296 | igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); |
db2ee5bd AD |
6297 | |
6298 | if ((dev->features & NETIF_F_HW_VLAN_RX) && | |
6299 | igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { | |
6300 | u16 vid; | |
6301 | if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && | |
6302 | test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) | |
6303 | vid = be16_to_cpu(rx_desc->wb.upper.vlan); | |
6304 | else | |
6305 | vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
6306 | ||
6307 | __vlan_hwaccel_put_tag(skb, vid); | |
6308 | } | |
6309 | ||
6310 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
6311 | ||
6312 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
6313 | } | |
6314 | ||
2e334eee | 6315 | static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) |
9d5c8243 | 6316 | { |
0ba82994 | 6317 | struct igb_ring *rx_ring = q_vector->rx.ring; |
1a1c225b | 6318 | struct sk_buff *skb = rx_ring->skb; |
9d5c8243 | 6319 | unsigned int total_bytes = 0, total_packets = 0; |
16eb8815 | 6320 | u16 cleaned_count = igb_desc_unused(rx_ring); |
9d5c8243 | 6321 | |
2e334eee AD |
6322 | do { |
6323 | union e1000_adv_rx_desc *rx_desc; | |
bf36c1a0 | 6324 | |
2e334eee AD |
6325 | /* return some buffers to hardware, one at a time is too slow */ |
6326 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
6327 | igb_alloc_rx_buffers(rx_ring, cleaned_count); | |
6328 | cleaned_count = 0; | |
6329 | } | |
bf36c1a0 | 6330 | |
2e334eee | 6331 | rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); |
16eb8815 | 6332 | |
2e334eee AD |
6333 | if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) |
6334 | break; | |
9d5c8243 | 6335 | |
2e334eee AD |
6336 | /* retrieve a buffer from the ring */ |
6337 | skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); | |
9d5c8243 | 6338 | |
2e334eee AD |
6339 | /* exit if we failed to retrieve a buffer */ |
6340 | if (!skb) | |
6341 | break; | |
1a1c225b | 6342 | |
2e334eee | 6343 | cleaned_count++; |
1a1c225b | 6344 | |
2e334eee AD |
6345 | /* fetch next buffer in frame if non-eop */ |
6346 | if (igb_is_non_eop(rx_ring, rx_desc)) | |
6347 | continue; | |
1a1c225b AD |
6348 | |
6349 | /* verify the packet layout is correct */ | |
6350 | if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { | |
6351 | skb = NULL; | |
6352 | continue; | |
9d5c8243 | 6353 | } |
9d5c8243 | 6354 | |
db2ee5bd | 6355 | /* probably a little skewed due to removing CRC */ |
3ceb90fd | 6356 | total_bytes += skb->len; |
3ceb90fd | 6357 | |
db2ee5bd AD |
6358 | /* populate checksum, timestamp, VLAN, and protocol */ |
6359 | igb_process_skb_fields(rx_ring, rx_desc, skb); | |
3ceb90fd | 6360 | |
b2cb09b1 | 6361 | napi_gro_receive(&q_vector->napi, skb); |
9d5c8243 | 6362 | |
1a1c225b AD |
6363 | /* reset skb pointer */ |
6364 | skb = NULL; | |
6365 | ||
2e334eee AD |
6366 | /* update budget accounting */ |
6367 | total_packets++; | |
6368 | } while (likely(total_packets < budget)); | |
bf36c1a0 | 6369 | |
1a1c225b AD |
6370 | /* place incomplete frames back on ring for completion */ |
6371 | rx_ring->skb = skb; | |
6372 | ||
12dcd86b | 6373 | u64_stats_update_begin(&rx_ring->rx_syncp); |
9d5c8243 AK |
6374 | rx_ring->rx_stats.packets += total_packets; |
6375 | rx_ring->rx_stats.bytes += total_bytes; | |
12dcd86b | 6376 | u64_stats_update_end(&rx_ring->rx_syncp); |
0ba82994 AD |
6377 | q_vector->rx.total_packets += total_packets; |
6378 | q_vector->rx.total_bytes += total_bytes; | |
c023cd88 AD |
6379 | |
6380 | if (cleaned_count) | |
cd392f5c | 6381 | igb_alloc_rx_buffers(rx_ring, cleaned_count); |
c023cd88 | 6382 | |
2e334eee | 6383 | return (total_packets < budget); |
9d5c8243 AK |
6384 | } |
6385 | ||
c023cd88 | 6386 | static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, |
06034649 | 6387 | struct igb_rx_buffer *bi) |
c023cd88 AD |
6388 | { |
6389 | struct page *page = bi->page; | |
cbc8e55f | 6390 | dma_addr_t dma; |
c023cd88 | 6391 | |
cbc8e55f AD |
6392 | /* since we are recycling buffers we should seldom need to alloc */ |
6393 | if (likely(page)) | |
c023cd88 AD |
6394 | return true; |
6395 | ||
cbc8e55f AD |
6396 | /* alloc new page for storage */ |
6397 | page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); | |
6398 | if (unlikely(!page)) { | |
6399 | rx_ring->rx_stats.alloc_failed++; | |
6400 | return false; | |
c023cd88 AD |
6401 | } |
6402 | ||
cbc8e55f AD |
6403 | /* map page for use */ |
6404 | dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
c023cd88 | 6405 | |
cbc8e55f AD |
6406 | /* |
6407 | * if mapping failed free memory back to system since | |
6408 | * there isn't much point in holding memory we can't use | |
6409 | */ | |
1a1c225b | 6410 | if (dma_mapping_error(rx_ring->dev, dma)) { |
cbc8e55f AD |
6411 | __free_page(page); |
6412 | ||
c023cd88 AD |
6413 | rx_ring->rx_stats.alloc_failed++; |
6414 | return false; | |
6415 | } | |
6416 | ||
1a1c225b | 6417 | bi->dma = dma; |
cbc8e55f AD |
6418 | bi->page = page; |
6419 | bi->page_offset = 0; | |
1a1c225b | 6420 | |
c023cd88 AD |
6421 | return true; |
6422 | } | |
6423 | ||
9d5c8243 | 6424 | /** |
cd392f5c | 6425 | * igb_alloc_rx_buffers - Replace used receive buffers; packet split |
9d5c8243 AK |
6426 | * @adapter: address of board private structure |
6427 | **/ | |
cd392f5c | 6428 | void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) |
9d5c8243 | 6429 | { |
9d5c8243 | 6430 | union e1000_adv_rx_desc *rx_desc; |
06034649 | 6431 | struct igb_rx_buffer *bi; |
c023cd88 | 6432 | u16 i = rx_ring->next_to_use; |
9d5c8243 | 6433 | |
cbc8e55f AD |
6434 | /* nothing to do */ |
6435 | if (!cleaned_count) | |
6436 | return; | |
6437 | ||
60136906 | 6438 | rx_desc = IGB_RX_DESC(rx_ring, i); |
06034649 | 6439 | bi = &rx_ring->rx_buffer_info[i]; |
c023cd88 | 6440 | i -= rx_ring->count; |
9d5c8243 | 6441 | |
cbc8e55f | 6442 | do { |
1a1c225b | 6443 | if (!igb_alloc_mapped_page(rx_ring, bi)) |
c023cd88 | 6444 | break; |
9d5c8243 | 6445 | |
cbc8e55f AD |
6446 | /* |
6447 | * Refresh the desc even if buffer_addrs didn't change | |
6448 | * because each write-back erases this info. | |
6449 | */ | |
6450 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9d5c8243 | 6451 | |
c023cd88 AD |
6452 | rx_desc++; |
6453 | bi++; | |
9d5c8243 | 6454 | i++; |
c023cd88 | 6455 | if (unlikely(!i)) { |
60136906 | 6456 | rx_desc = IGB_RX_DESC(rx_ring, 0); |
06034649 | 6457 | bi = rx_ring->rx_buffer_info; |
c023cd88 AD |
6458 | i -= rx_ring->count; |
6459 | } | |
6460 | ||
6461 | /* clear the hdr_addr for the next_to_use descriptor */ | |
6462 | rx_desc->read.hdr_addr = 0; | |
cbc8e55f AD |
6463 | |
6464 | cleaned_count--; | |
6465 | } while (cleaned_count); | |
9d5c8243 | 6466 | |
c023cd88 AD |
6467 | i += rx_ring->count; |
6468 | ||
9d5c8243 | 6469 | if (rx_ring->next_to_use != i) { |
cbc8e55f | 6470 | /* record the next descriptor to use */ |
9d5c8243 | 6471 | rx_ring->next_to_use = i; |
9d5c8243 | 6472 | |
cbc8e55f AD |
6473 | /* update next to alloc since we have filled the ring */ |
6474 | rx_ring->next_to_alloc = i; | |
6475 | ||
6476 | /* | |
6477 | * Force memory writes to complete before letting h/w | |
9d5c8243 AK |
6478 | * know there are new descriptors to fetch. (Only |
6479 | * applicable for weak-ordered memory model archs, | |
cbc8e55f AD |
6480 | * such as IA-64). |
6481 | */ | |
9d5c8243 | 6482 | wmb(); |
fce99e34 | 6483 | writel(i, rx_ring->tail); |
9d5c8243 AK |
6484 | } |
6485 | } | |
6486 | ||
6487 | /** | |
6488 | * igb_mii_ioctl - | |
6489 | * @netdev: | |
6490 | * @ifreq: | |
6491 | * @cmd: | |
6492 | **/ | |
6493 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6494 | { | |
6495 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6496 | struct mii_ioctl_data *data = if_mii(ifr); | |
6497 | ||
6498 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
6499 | return -EOPNOTSUPP; | |
6500 | ||
6501 | switch (cmd) { | |
6502 | case SIOCGMIIPHY: | |
6503 | data->phy_id = adapter->hw.phy.addr; | |
6504 | break; | |
6505 | case SIOCGMIIREG: | |
f5f4cf08 AD |
6506 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
6507 | &data->val_out)) | |
9d5c8243 AK |
6508 | return -EIO; |
6509 | break; | |
6510 | case SIOCSMIIREG: | |
6511 | default: | |
6512 | return -EOPNOTSUPP; | |
6513 | } | |
6514 | return 0; | |
6515 | } | |
6516 | ||
6517 | /** | |
6518 | * igb_ioctl - | |
6519 | * @netdev: | |
6520 | * @ifreq: | |
6521 | * @cmd: | |
6522 | **/ | |
6523 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6524 | { | |
6525 | switch (cmd) { | |
6526 | case SIOCGMIIPHY: | |
6527 | case SIOCGMIIREG: | |
6528 | case SIOCSMIIREG: | |
6529 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b | 6530 | case SIOCSHWTSTAMP: |
a79f4f88 | 6531 | return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); |
9d5c8243 AK |
6532 | default: |
6533 | return -EOPNOTSUPP; | |
6534 | } | |
6535 | } | |
6536 | ||
009bc06e AD |
6537 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
6538 | { | |
6539 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6540 | |
23d028cc | 6541 | if (pcie_capability_read_word(adapter->pdev, reg, value)) |
009bc06e AD |
6542 | return -E1000_ERR_CONFIG; |
6543 | ||
009bc06e AD |
6544 | return 0; |
6545 | } | |
6546 | ||
6547 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | |
6548 | { | |
6549 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6550 | |
23d028cc | 6551 | if (pcie_capability_write_word(adapter->pdev, reg, *value)) |
009bc06e AD |
6552 | return -E1000_ERR_CONFIG; |
6553 | ||
009bc06e AD |
6554 | return 0; |
6555 | } | |
6556 | ||
c8f44aff | 6557 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) |
9d5c8243 AK |
6558 | { |
6559 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6560 | struct e1000_hw *hw = &adapter->hw; | |
6561 | u32 ctrl, rctl; | |
5faf030c | 6562 | bool enable = !!(features & NETIF_F_HW_VLAN_RX); |
9d5c8243 | 6563 | |
5faf030c | 6564 | if (enable) { |
9d5c8243 AK |
6565 | /* enable VLAN tag insert/strip */ |
6566 | ctrl = rd32(E1000_CTRL); | |
6567 | ctrl |= E1000_CTRL_VME; | |
6568 | wr32(E1000_CTRL, ctrl); | |
6569 | ||
51466239 | 6570 | /* Disable CFI check */ |
9d5c8243 | 6571 | rctl = rd32(E1000_RCTL); |
9d5c8243 AK |
6572 | rctl &= ~E1000_RCTL_CFIEN; |
6573 | wr32(E1000_RCTL, rctl); | |
9d5c8243 AK |
6574 | } else { |
6575 | /* disable VLAN tag insert/strip */ | |
6576 | ctrl = rd32(E1000_CTRL); | |
6577 | ctrl &= ~E1000_CTRL_VME; | |
6578 | wr32(E1000_CTRL, ctrl); | |
9d5c8243 AK |
6579 | } |
6580 | ||
e1739522 | 6581 | igb_rlpml_set(adapter); |
9d5c8243 AK |
6582 | } |
6583 | ||
8e586137 | 6584 | static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
9d5c8243 AK |
6585 | { |
6586 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6587 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6588 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 6589 | |
51466239 AD |
6590 | /* attempt to add filter to vlvf array */ |
6591 | igb_vlvf_set(adapter, vid, true, pf_id); | |
4ae196df | 6592 | |
51466239 AD |
6593 | /* add the filter since PF can receive vlans w/o entry in vlvf */ |
6594 | igb_vfta_set(hw, vid, true); | |
b2cb09b1 JP |
6595 | |
6596 | set_bit(vid, adapter->active_vlans); | |
8e586137 JP |
6597 | |
6598 | return 0; | |
9d5c8243 AK |
6599 | } |
6600 | ||
8e586137 | 6601 | static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
9d5c8243 AK |
6602 | { |
6603 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6604 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6605 | int pf_id = adapter->vfs_allocated_count; |
51466239 | 6606 | s32 err; |
9d5c8243 | 6607 | |
51466239 AD |
6608 | /* remove vlan from VLVF table array */ |
6609 | err = igb_vlvf_set(adapter, vid, false, pf_id); | |
9d5c8243 | 6610 | |
51466239 AD |
6611 | /* if vid was not present in VLVF just remove it from table */ |
6612 | if (err) | |
4ae196df | 6613 | igb_vfta_set(hw, vid, false); |
b2cb09b1 JP |
6614 | |
6615 | clear_bit(vid, adapter->active_vlans); | |
8e586137 JP |
6616 | |
6617 | return 0; | |
9d5c8243 AK |
6618 | } |
6619 | ||
6620 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
6621 | { | |
b2cb09b1 | 6622 | u16 vid; |
9d5c8243 | 6623 | |
5faf030c AD |
6624 | igb_vlan_mode(adapter->netdev, adapter->netdev->features); |
6625 | ||
b2cb09b1 JP |
6626 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
6627 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
9d5c8243 AK |
6628 | } |
6629 | ||
14ad2513 | 6630 | int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) |
9d5c8243 | 6631 | { |
090b1795 | 6632 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
6633 | struct e1000_mac_info *mac = &adapter->hw.mac; |
6634 | ||
6635 | mac->autoneg = 0; | |
6636 | ||
14ad2513 DD |
6637 | /* Make sure dplx is at most 1 bit and lsb of speed is not set |
6638 | * for the switch() below to work */ | |
6639 | if ((spd & 1) || (dplx & ~1)) | |
6640 | goto err_inval; | |
6641 | ||
cd2638a8 CW |
6642 | /* Fiber NIC's only allow 1000 Gbps Full duplex */ |
6643 | if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && | |
14ad2513 DD |
6644 | spd != SPEED_1000 && |
6645 | dplx != DUPLEX_FULL) | |
6646 | goto err_inval; | |
cd2638a8 | 6647 | |
14ad2513 | 6648 | switch (spd + dplx) { |
9d5c8243 AK |
6649 | case SPEED_10 + DUPLEX_HALF: |
6650 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
6651 | break; | |
6652 | case SPEED_10 + DUPLEX_FULL: | |
6653 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
6654 | break; | |
6655 | case SPEED_100 + DUPLEX_HALF: | |
6656 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
6657 | break; | |
6658 | case SPEED_100 + DUPLEX_FULL: | |
6659 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
6660 | break; | |
6661 | case SPEED_1000 + DUPLEX_FULL: | |
6662 | mac->autoneg = 1; | |
6663 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
6664 | break; | |
6665 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
6666 | default: | |
14ad2513 | 6667 | goto err_inval; |
9d5c8243 | 6668 | } |
8376dad0 JB |
6669 | |
6670 | /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ | |
6671 | adapter->hw.phy.mdix = AUTO_ALL_MODES; | |
6672 | ||
9d5c8243 | 6673 | return 0; |
14ad2513 DD |
6674 | |
6675 | err_inval: | |
6676 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); | |
6677 | return -EINVAL; | |
9d5c8243 AK |
6678 | } |
6679 | ||
749ab2cd YZ |
6680 | static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, |
6681 | bool runtime) | |
9d5c8243 AK |
6682 | { |
6683 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6684 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6685 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 6686 | u32 ctrl, rctl, status; |
749ab2cd | 6687 | u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; |
9d5c8243 AK |
6688 | #ifdef CONFIG_PM |
6689 | int retval = 0; | |
6690 | #endif | |
6691 | ||
6692 | netif_device_detach(netdev); | |
6693 | ||
a88f10ec | 6694 | if (netif_running(netdev)) |
749ab2cd | 6695 | __igb_close(netdev, true); |
a88f10ec | 6696 | |
047e0030 | 6697 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
6698 | |
6699 | #ifdef CONFIG_PM | |
6700 | retval = pci_save_state(pdev); | |
6701 | if (retval) | |
6702 | return retval; | |
6703 | #endif | |
6704 | ||
6705 | status = rd32(E1000_STATUS); | |
6706 | if (status & E1000_STATUS_LU) | |
6707 | wufc &= ~E1000_WUFC_LNKC; | |
6708 | ||
6709 | if (wufc) { | |
6710 | igb_setup_rctl(adapter); | |
ff41f8dc | 6711 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
6712 | |
6713 | /* turn on all-multi mode if wake on multicast is enabled */ | |
6714 | if (wufc & E1000_WUFC_MC) { | |
6715 | rctl = rd32(E1000_RCTL); | |
6716 | rctl |= E1000_RCTL_MPE; | |
6717 | wr32(E1000_RCTL, rctl); | |
6718 | } | |
6719 | ||
6720 | ctrl = rd32(E1000_CTRL); | |
6721 | /* advertise wake from D3Cold */ | |
6722 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
6723 | /* phy power management enable */ | |
6724 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
6725 | ctrl |= E1000_CTRL_ADVD3WUC; | |
6726 | wr32(E1000_CTRL, ctrl); | |
6727 | ||
9d5c8243 | 6728 | /* Allow time for pending master requests to run */ |
330a6d6a | 6729 | igb_disable_pcie_master(hw); |
9d5c8243 AK |
6730 | |
6731 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
6732 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
6733 | } else { |
6734 | wr32(E1000_WUC, 0); | |
6735 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
6736 | } |
6737 | ||
3fe7c4c9 RW |
6738 | *enable_wake = wufc || adapter->en_mng_pt; |
6739 | if (!*enable_wake) | |
88a268c1 NN |
6740 | igb_power_down_link(adapter); |
6741 | else | |
6742 | igb_power_up_link(adapter); | |
9d5c8243 AK |
6743 | |
6744 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
6745 | * would have already happened in close and is redundant. */ | |
6746 | igb_release_hw_control(adapter); | |
6747 | ||
6748 | pci_disable_device(pdev); | |
6749 | ||
9d5c8243 AK |
6750 | return 0; |
6751 | } | |
6752 | ||
6753 | #ifdef CONFIG_PM | |
d9dd966d | 6754 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 6755 | static int igb_suspend(struct device *dev) |
3fe7c4c9 RW |
6756 | { |
6757 | int retval; | |
6758 | bool wake; | |
749ab2cd | 6759 | struct pci_dev *pdev = to_pci_dev(dev); |
3fe7c4c9 | 6760 | |
749ab2cd | 6761 | retval = __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
6762 | if (retval) |
6763 | return retval; | |
6764 | ||
6765 | if (wake) { | |
6766 | pci_prepare_to_sleep(pdev); | |
6767 | } else { | |
6768 | pci_wake_from_d3(pdev, false); | |
6769 | pci_set_power_state(pdev, PCI_D3hot); | |
6770 | } | |
6771 | ||
6772 | return 0; | |
6773 | } | |
d9dd966d | 6774 | #endif /* CONFIG_PM_SLEEP */ |
3fe7c4c9 | 6775 | |
749ab2cd | 6776 | static int igb_resume(struct device *dev) |
9d5c8243 | 6777 | { |
749ab2cd | 6778 | struct pci_dev *pdev = to_pci_dev(dev); |
9d5c8243 AK |
6779 | struct net_device *netdev = pci_get_drvdata(pdev); |
6780 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6781 | struct e1000_hw *hw = &adapter->hw; | |
6782 | u32 err; | |
6783 | ||
6784 | pci_set_power_state(pdev, PCI_D0); | |
6785 | pci_restore_state(pdev); | |
b94f2d77 | 6786 | pci_save_state(pdev); |
42bfd33a | 6787 | |
aed5dec3 | 6788 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
6789 | if (err) { |
6790 | dev_err(&pdev->dev, | |
6791 | "igb: Cannot enable PCI device from suspend\n"); | |
6792 | return err; | |
6793 | } | |
6794 | pci_set_master(pdev); | |
6795 | ||
6796 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
6797 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
6798 | ||
cfb8c3aa | 6799 | if (igb_init_interrupt_scheme(adapter)) { |
a88f10ec AD |
6800 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
6801 | return -ENOMEM; | |
9d5c8243 AK |
6802 | } |
6803 | ||
9d5c8243 | 6804 | igb_reset(adapter); |
a8564f03 AD |
6805 | |
6806 | /* let the f/w know that the h/w is now under the control of the | |
6807 | * driver. */ | |
6808 | igb_get_hw_control(adapter); | |
6809 | ||
9d5c8243 AK |
6810 | wr32(E1000_WUS, ~0); |
6811 | ||
749ab2cd | 6812 | if (netdev->flags & IFF_UP) { |
0c2cc02e | 6813 | rtnl_lock(); |
749ab2cd | 6814 | err = __igb_open(netdev, true); |
0c2cc02e | 6815 | rtnl_unlock(); |
a88f10ec AD |
6816 | if (err) |
6817 | return err; | |
6818 | } | |
9d5c8243 AK |
6819 | |
6820 | netif_device_attach(netdev); | |
749ab2cd YZ |
6821 | return 0; |
6822 | } | |
6823 | ||
6824 | #ifdef CONFIG_PM_RUNTIME | |
6825 | static int igb_runtime_idle(struct device *dev) | |
6826 | { | |
6827 | struct pci_dev *pdev = to_pci_dev(dev); | |
6828 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6829 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6830 | ||
6831 | if (!igb_has_link(adapter)) | |
6832 | pm_schedule_suspend(dev, MSEC_PER_SEC * 5); | |
6833 | ||
6834 | return -EBUSY; | |
6835 | } | |
6836 | ||
6837 | static int igb_runtime_suspend(struct device *dev) | |
6838 | { | |
6839 | struct pci_dev *pdev = to_pci_dev(dev); | |
6840 | int retval; | |
6841 | bool wake; | |
6842 | ||
6843 | retval = __igb_shutdown(pdev, &wake, 1); | |
6844 | if (retval) | |
6845 | return retval; | |
6846 | ||
6847 | if (wake) { | |
6848 | pci_prepare_to_sleep(pdev); | |
6849 | } else { | |
6850 | pci_wake_from_d3(pdev, false); | |
6851 | pci_set_power_state(pdev, PCI_D3hot); | |
6852 | } | |
9d5c8243 | 6853 | |
9d5c8243 AK |
6854 | return 0; |
6855 | } | |
749ab2cd YZ |
6856 | |
6857 | static int igb_runtime_resume(struct device *dev) | |
6858 | { | |
6859 | return igb_resume(dev); | |
6860 | } | |
6861 | #endif /* CONFIG_PM_RUNTIME */ | |
9d5c8243 AK |
6862 | #endif |
6863 | ||
6864 | static void igb_shutdown(struct pci_dev *pdev) | |
6865 | { | |
3fe7c4c9 RW |
6866 | bool wake; |
6867 | ||
749ab2cd | 6868 | __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
6869 | |
6870 | if (system_state == SYSTEM_POWER_OFF) { | |
6871 | pci_wake_from_d3(pdev, wake); | |
6872 | pci_set_power_state(pdev, PCI_D3hot); | |
6873 | } | |
9d5c8243 AK |
6874 | } |
6875 | ||
6876 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
6877 | /* | |
6878 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6879 | * without having to re-enable interrupts. It's not called while | |
6880 | * the interrupt routine is executing. | |
6881 | */ | |
6882 | static void igb_netpoll(struct net_device *netdev) | |
6883 | { | |
6884 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 6885 | struct e1000_hw *hw = &adapter->hw; |
0d1ae7f4 | 6886 | struct igb_q_vector *q_vector; |
9d5c8243 | 6887 | int i; |
9d5c8243 | 6888 | |
047e0030 | 6889 | for (i = 0; i < adapter->num_q_vectors; i++) { |
0d1ae7f4 AD |
6890 | q_vector = adapter->q_vector[i]; |
6891 | if (adapter->msix_entries) | |
6892 | wr32(E1000_EIMC, q_vector->eims_value); | |
6893 | else | |
6894 | igb_irq_disable(adapter); | |
047e0030 | 6895 | napi_schedule(&q_vector->napi); |
eebbbdba | 6896 | } |
9d5c8243 AK |
6897 | } |
6898 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
6899 | ||
6900 | /** | |
6901 | * igb_io_error_detected - called when PCI error is detected | |
6902 | * @pdev: Pointer to PCI device | |
6903 | * @state: The current pci connection state | |
6904 | * | |
6905 | * This function is called after a PCI bus error affecting | |
6906 | * this device has been detected. | |
6907 | */ | |
6908 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
6909 | pci_channel_state_t state) | |
6910 | { | |
6911 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6912 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6913 | ||
6914 | netif_device_detach(netdev); | |
6915 | ||
59ed6eec AD |
6916 | if (state == pci_channel_io_perm_failure) |
6917 | return PCI_ERS_RESULT_DISCONNECT; | |
6918 | ||
9d5c8243 AK |
6919 | if (netif_running(netdev)) |
6920 | igb_down(adapter); | |
6921 | pci_disable_device(pdev); | |
6922 | ||
6923 | /* Request a slot slot reset. */ | |
6924 | return PCI_ERS_RESULT_NEED_RESET; | |
6925 | } | |
6926 | ||
6927 | /** | |
6928 | * igb_io_slot_reset - called after the pci bus has been reset. | |
6929 | * @pdev: Pointer to PCI device | |
6930 | * | |
6931 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
6932 | * resembles the first-half of the igb_resume routine. | |
6933 | */ | |
6934 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
6935 | { | |
6936 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6937 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6938 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 6939 | pci_ers_result_t result; |
42bfd33a | 6940 | int err; |
9d5c8243 | 6941 | |
aed5dec3 | 6942 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
6943 | dev_err(&pdev->dev, |
6944 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
6945 | result = PCI_ERS_RESULT_DISCONNECT; |
6946 | } else { | |
6947 | pci_set_master(pdev); | |
6948 | pci_restore_state(pdev); | |
b94f2d77 | 6949 | pci_save_state(pdev); |
9d5c8243 | 6950 | |
40a914fa AD |
6951 | pci_enable_wake(pdev, PCI_D3hot, 0); |
6952 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 6953 | |
40a914fa AD |
6954 | igb_reset(adapter); |
6955 | wr32(E1000_WUS, ~0); | |
6956 | result = PCI_ERS_RESULT_RECOVERED; | |
6957 | } | |
9d5c8243 | 6958 | |
ea943d41 JK |
6959 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
6960 | if (err) { | |
6961 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
6962 | "failed 0x%0x\n", err); | |
6963 | /* non-fatal, continue */ | |
6964 | } | |
40a914fa AD |
6965 | |
6966 | return result; | |
9d5c8243 AK |
6967 | } |
6968 | ||
6969 | /** | |
6970 | * igb_io_resume - called when traffic can start flowing again. | |
6971 | * @pdev: Pointer to PCI device | |
6972 | * | |
6973 | * This callback is called when the error recovery driver tells us that | |
6974 | * its OK to resume normal operation. Implementation resembles the | |
6975 | * second-half of the igb_resume routine. | |
6976 | */ | |
6977 | static void igb_io_resume(struct pci_dev *pdev) | |
6978 | { | |
6979 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6980 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6981 | ||
9d5c8243 AK |
6982 | if (netif_running(netdev)) { |
6983 | if (igb_up(adapter)) { | |
6984 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
6985 | return; | |
6986 | } | |
6987 | } | |
6988 | ||
6989 | netif_device_attach(netdev); | |
6990 | ||
6991 | /* let the f/w know that the h/w is now under the control of the | |
6992 | * driver. */ | |
6993 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
6994 | } |
6995 | ||
26ad9178 AD |
6996 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
6997 | u8 qsel) | |
6998 | { | |
6999 | u32 rar_low, rar_high; | |
7000 | struct e1000_hw *hw = &adapter->hw; | |
7001 | ||
7002 | /* HW expects these in little endian so we reverse the byte order | |
7003 | * from network order (big endian) to little endian | |
7004 | */ | |
7005 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
7006 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
7007 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
7008 | ||
7009 | /* Indicate to hardware the Address is Valid. */ | |
7010 | rar_high |= E1000_RAH_AV; | |
7011 | ||
7012 | if (hw->mac.type == e1000_82575) | |
7013 | rar_high |= E1000_RAH_POOL_1 * qsel; | |
7014 | else | |
7015 | rar_high |= E1000_RAH_POOL_1 << qsel; | |
7016 | ||
7017 | wr32(E1000_RAL(index), rar_low); | |
7018 | wrfl(); | |
7019 | wr32(E1000_RAH(index), rar_high); | |
7020 | wrfl(); | |
7021 | } | |
7022 | ||
4ae196df AD |
7023 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
7024 | int vf, unsigned char *mac_addr) | |
7025 | { | |
7026 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc AD |
7027 | /* VF MAC addresses start at end of receive addresses and moves |
7028 | * torwards the first, as a result a collision should not be possible */ | |
7029 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); | |
4ae196df | 7030 | |
37680117 | 7031 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df | 7032 | |
26ad9178 | 7033 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
4ae196df AD |
7034 | |
7035 | return 0; | |
7036 | } | |
7037 | ||
8151d294 WM |
7038 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
7039 | { | |
7040 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7041 | if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) | |
7042 | return -EINVAL; | |
7043 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; | |
7044 | dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); | |
7045 | dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" | |
7046 | " change effective."); | |
7047 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
7048 | dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," | |
7049 | " but the PF device is not up.\n"); | |
7050 | dev_warn(&adapter->pdev->dev, "Bring the PF device up before" | |
7051 | " attempting to use the VF device.\n"); | |
7052 | } | |
7053 | return igb_set_vf_mac(adapter, vf, mac); | |
7054 | } | |
7055 | ||
17dc566c LL |
7056 | static int igb_link_mbps(int internal_link_speed) |
7057 | { | |
7058 | switch (internal_link_speed) { | |
7059 | case SPEED_100: | |
7060 | return 100; | |
7061 | case SPEED_1000: | |
7062 | return 1000; | |
7063 | default: | |
7064 | return 0; | |
7065 | } | |
7066 | } | |
7067 | ||
7068 | static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, | |
7069 | int link_speed) | |
7070 | { | |
7071 | int rf_dec, rf_int; | |
7072 | u32 bcnrc_val; | |
7073 | ||
7074 | if (tx_rate != 0) { | |
7075 | /* Calculate the rate factor values to set */ | |
7076 | rf_int = link_speed / tx_rate; | |
7077 | rf_dec = (link_speed - (rf_int * tx_rate)); | |
7078 | rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; | |
7079 | ||
7080 | bcnrc_val = E1000_RTTBCNRC_RS_ENA; | |
7081 | bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & | |
7082 | E1000_RTTBCNRC_RF_INT_MASK); | |
7083 | bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); | |
7084 | } else { | |
7085 | bcnrc_val = 0; | |
7086 | } | |
7087 | ||
7088 | wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ | |
f00b0da7 LL |
7089 | /* |
7090 | * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM | |
7091 | * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. | |
7092 | */ | |
7093 | wr32(E1000_RTTBCNRM, 0x14); | |
17dc566c LL |
7094 | wr32(E1000_RTTBCNRC, bcnrc_val); |
7095 | } | |
7096 | ||
7097 | static void igb_check_vf_rate_limit(struct igb_adapter *adapter) | |
7098 | { | |
7099 | int actual_link_speed, i; | |
7100 | bool reset_rate = false; | |
7101 | ||
7102 | /* VF TX rate limit was not set or not supported */ | |
7103 | if ((adapter->vf_rate_link_speed == 0) || | |
7104 | (adapter->hw.mac.type != e1000_82576)) | |
7105 | return; | |
7106 | ||
7107 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7108 | if (actual_link_speed != adapter->vf_rate_link_speed) { | |
7109 | reset_rate = true; | |
7110 | adapter->vf_rate_link_speed = 0; | |
7111 | dev_info(&adapter->pdev->dev, | |
7112 | "Link speed has been changed. VF Transmit " | |
7113 | "rate is disabled\n"); | |
7114 | } | |
7115 | ||
7116 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7117 | if (reset_rate) | |
7118 | adapter->vf_data[i].tx_rate = 0; | |
7119 | ||
7120 | igb_set_vf_rate_limit(&adapter->hw, i, | |
7121 | adapter->vf_data[i].tx_rate, | |
7122 | actual_link_speed); | |
7123 | } | |
7124 | } | |
7125 | ||
8151d294 WM |
7126 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) |
7127 | { | |
17dc566c LL |
7128 | struct igb_adapter *adapter = netdev_priv(netdev); |
7129 | struct e1000_hw *hw = &adapter->hw; | |
7130 | int actual_link_speed; | |
7131 | ||
7132 | if (hw->mac.type != e1000_82576) | |
7133 | return -EOPNOTSUPP; | |
7134 | ||
7135 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7136 | if ((vf >= adapter->vfs_allocated_count) || | |
7137 | (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || | |
7138 | (tx_rate < 0) || (tx_rate > actual_link_speed)) | |
7139 | return -EINVAL; | |
7140 | ||
7141 | adapter->vf_rate_link_speed = actual_link_speed; | |
7142 | adapter->vf_data[vf].tx_rate = (u16)tx_rate; | |
7143 | igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); | |
7144 | ||
7145 | return 0; | |
8151d294 WM |
7146 | } |
7147 | ||
7148 | static int igb_ndo_get_vf_config(struct net_device *netdev, | |
7149 | int vf, struct ifla_vf_info *ivi) | |
7150 | { | |
7151 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7152 | if (vf >= adapter->vfs_allocated_count) | |
7153 | return -EINVAL; | |
7154 | ivi->vf = vf; | |
7155 | memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); | |
17dc566c | 7156 | ivi->tx_rate = adapter->vf_data[vf].tx_rate; |
8151d294 WM |
7157 | ivi->vlan = adapter->vf_data[vf].pf_vlan; |
7158 | ivi->qos = adapter->vf_data[vf].pf_qos; | |
7159 | return 0; | |
7160 | } | |
7161 | ||
4ae196df AD |
7162 | static void igb_vmm_control(struct igb_adapter *adapter) |
7163 | { | |
7164 | struct e1000_hw *hw = &adapter->hw; | |
10d8e907 | 7165 | u32 reg; |
4ae196df | 7166 | |
52a1dd4d AD |
7167 | switch (hw->mac.type) { |
7168 | case e1000_82575: | |
f96a8a0b CW |
7169 | case e1000_i210: |
7170 | case e1000_i211: | |
52a1dd4d AD |
7171 | default: |
7172 | /* replication is not supported for 82575 */ | |
4ae196df | 7173 | return; |
52a1dd4d AD |
7174 | case e1000_82576: |
7175 | /* notify HW that the MAC is adding vlan tags */ | |
7176 | reg = rd32(E1000_DTXCTL); | |
7177 | reg |= E1000_DTXCTL_VLAN_ADDED; | |
7178 | wr32(E1000_DTXCTL, reg); | |
7179 | case e1000_82580: | |
7180 | /* enable replication vlan tag stripping */ | |
7181 | reg = rd32(E1000_RPLOLR); | |
7182 | reg |= E1000_RPLOLR_STRVLAN; | |
7183 | wr32(E1000_RPLOLR, reg); | |
d2ba2ed8 AD |
7184 | case e1000_i350: |
7185 | /* none of the above registers are supported by i350 */ | |
52a1dd4d AD |
7186 | break; |
7187 | } | |
10d8e907 | 7188 | |
d4960307 AD |
7189 | if (adapter->vfs_allocated_count) { |
7190 | igb_vmdq_set_loopback_pf(hw, true); | |
7191 | igb_vmdq_set_replication_pf(hw, true); | |
13800469 GR |
7192 | igb_vmdq_set_anti_spoofing_pf(hw, true, |
7193 | adapter->vfs_allocated_count); | |
d4960307 AD |
7194 | } else { |
7195 | igb_vmdq_set_loopback_pf(hw, false); | |
7196 | igb_vmdq_set_replication_pf(hw, false); | |
7197 | } | |
4ae196df AD |
7198 | } |
7199 | ||
b6e0c419 CW |
7200 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) |
7201 | { | |
7202 | struct e1000_hw *hw = &adapter->hw; | |
7203 | u32 dmac_thr; | |
7204 | u16 hwm; | |
7205 | ||
7206 | if (hw->mac.type > e1000_82580) { | |
7207 | if (adapter->flags & IGB_FLAG_DMAC) { | |
7208 | u32 reg; | |
7209 | ||
7210 | /* force threshold to 0. */ | |
7211 | wr32(E1000_DMCTXTH, 0); | |
7212 | ||
7213 | /* | |
e8c626e9 MV |
7214 | * DMA Coalescing high water mark needs to be greater |
7215 | * than the Rx threshold. Set hwm to PBA - max frame | |
7216 | * size in 16B units, capping it at PBA - 6KB. | |
b6e0c419 | 7217 | */ |
e8c626e9 MV |
7218 | hwm = 64 * pba - adapter->max_frame_size / 16; |
7219 | if (hwm < 64 * (pba - 6)) | |
7220 | hwm = 64 * (pba - 6); | |
7221 | reg = rd32(E1000_FCRTC); | |
7222 | reg &= ~E1000_FCRTC_RTH_COAL_MASK; | |
7223 | reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) | |
7224 | & E1000_FCRTC_RTH_COAL_MASK); | |
7225 | wr32(E1000_FCRTC, reg); | |
7226 | ||
7227 | /* | |
7228 | * Set the DMA Coalescing Rx threshold to PBA - 2 * max | |
7229 | * frame size, capping it at PBA - 10KB. | |
7230 | */ | |
7231 | dmac_thr = pba - adapter->max_frame_size / 512; | |
7232 | if (dmac_thr < pba - 10) | |
7233 | dmac_thr = pba - 10; | |
b6e0c419 CW |
7234 | reg = rd32(E1000_DMACR); |
7235 | reg &= ~E1000_DMACR_DMACTHR_MASK; | |
b6e0c419 CW |
7236 | reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) |
7237 | & E1000_DMACR_DMACTHR_MASK); | |
7238 | ||
7239 | /* transition to L0x or L1 if available..*/ | |
7240 | reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); | |
7241 | ||
7242 | /* watchdog timer= +-1000 usec in 32usec intervals */ | |
7243 | reg |= (1000 >> 5); | |
0c02dd98 MV |
7244 | |
7245 | /* Disable BMC-to-OS Watchdog Enable */ | |
7246 | reg &= ~E1000_DMACR_DC_BMC2OSW_EN; | |
b6e0c419 CW |
7247 | wr32(E1000_DMACR, reg); |
7248 | ||
7249 | /* | |
7250 | * no lower threshold to disable | |
7251 | * coalescing(smart fifb)-UTRESH=0 | |
7252 | */ | |
7253 | wr32(E1000_DMCRTRH, 0); | |
b6e0c419 CW |
7254 | |
7255 | reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); | |
7256 | ||
7257 | wr32(E1000_DMCTLX, reg); | |
7258 | ||
7259 | /* | |
7260 | * free space in tx packet buffer to wake from | |
7261 | * DMA coal | |
7262 | */ | |
7263 | wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - | |
7264 | (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); | |
7265 | ||
7266 | /* | |
7267 | * make low power state decision controlled | |
7268 | * by DMA coal | |
7269 | */ | |
7270 | reg = rd32(E1000_PCIEMISC); | |
7271 | reg &= ~E1000_PCIEMISC_LX_DECISION; | |
7272 | wr32(E1000_PCIEMISC, reg); | |
7273 | } /* endif adapter->dmac is not disabled */ | |
7274 | } else if (hw->mac.type == e1000_82580) { | |
7275 | u32 reg = rd32(E1000_PCIEMISC); | |
7276 | wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); | |
7277 | wr32(E1000_DMACR, 0); | |
7278 | } | |
7279 | } | |
7280 | ||
9d5c8243 | 7281 | /* igb_main.c */ |