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Commit | Line | Data |
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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4b9ea462 | 4 | Copyright(c) 2007-2013 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
876d2d6f JK |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
9d5c8243 AK |
30 | #include <linux/module.h> |
31 | #include <linux/types.h> | |
32 | #include <linux/init.h> | |
b2cb09b1 | 33 | #include <linux/bitops.h> |
9d5c8243 AK |
34 | #include <linux/vmalloc.h> |
35 | #include <linux/pagemap.h> | |
36 | #include <linux/netdevice.h> | |
9d5c8243 | 37 | #include <linux/ipv6.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
9d5c8243 AK |
39 | #include <net/checksum.h> |
40 | #include <net/ip6_checksum.h> | |
c6cb090b | 41 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
42 | #include <linux/mii.h> |
43 | #include <linux/ethtool.h> | |
01789349 | 44 | #include <linux/if.h> |
9d5c8243 AK |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/pci.h> | |
c54106bb | 47 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
48 | #include <linux/delay.h> |
49 | #include <linux/interrupt.h> | |
7d13a7d0 AD |
50 | #include <linux/ip.h> |
51 | #include <linux/tcp.h> | |
52 | #include <linux/sctp.h> | |
9d5c8243 | 53 | #include <linux/if_ether.h> |
40a914fa | 54 | #include <linux/aer.h> |
70c71606 | 55 | #include <linux/prefetch.h> |
749ab2cd | 56 | #include <linux/pm_runtime.h> |
421e02f0 | 57 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
58 | #include <linux/dca.h> |
59 | #endif | |
441fc6fd | 60 | #include <linux/i2c.h> |
9d5c8243 AK |
61 | #include "igb.h" |
62 | ||
200e5fd5 | 63 | #define MAJ 4 |
6699938b CW |
64 | #define MIN 1 |
65 | #define BUILD 2 | |
0d1fe82d | 66 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
929dd047 | 67 | __stringify(BUILD) "-k" |
9d5c8243 AK |
68 | char igb_driver_name[] = "igb"; |
69 | char igb_driver_version[] = DRV_VERSION; | |
70 | static const char igb_driver_string[] = | |
71 | "Intel(R) Gigabit Ethernet Network Driver"; | |
4b9ea462 AA |
72 | static const char igb_copyright[] = |
73 | "Copyright (c) 2007-2013 Intel Corporation."; | |
9d5c8243 | 74 | |
9d5c8243 AK |
75 | static const struct e1000_info *igb_info_tbl[] = { |
76 | [board_82575] = &e1000_82575_info, | |
77 | }; | |
78 | ||
a3aa1884 | 79 | static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { |
ceb5f13b CW |
80 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, |
81 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, | |
82 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, | |
f96a8a0b CW |
83 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, |
84 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, | |
85 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, | |
86 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, | |
87 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, | |
d2ba2ed8 AD |
88 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, |
89 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, | |
90 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, | |
91 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, | |
55cac248 AD |
92 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
93 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | |
6493d24f | 94 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, |
55cac248 AD |
95 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, |
96 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | |
97 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | |
308fb39a JG |
98 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, |
99 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, | |
1b5dda33 GJ |
100 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, |
101 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, | |
2d064c06 | 102 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 103 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
747d49ba | 104 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
2d064c06 AD |
105 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
106 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
4703bf73 | 107 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
b894fa26 | 108 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, |
c8ea5ea9 | 109 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
110 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
111 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
112 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
113 | /* required last entry */ | |
114 | {0, } | |
115 | }; | |
116 | ||
117 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
118 | ||
119 | void igb_reset(struct igb_adapter *); | |
120 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
121 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
122 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
123 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
06cf2666 | 124 | static void igb_setup_mrqc(struct igb_adapter *); |
9d5c8243 | 125 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); |
9f9a12f8 | 126 | static void igb_remove(struct pci_dev *pdev); |
9d5c8243 AK |
127 | static int igb_sw_init(struct igb_adapter *); |
128 | static int igb_open(struct net_device *); | |
129 | static int igb_close(struct net_device *); | |
53c7d064 | 130 | static void igb_configure(struct igb_adapter *); |
9d5c8243 AK |
131 | static void igb_configure_tx(struct igb_adapter *); |
132 | static void igb_configure_rx(struct igb_adapter *); | |
9d5c8243 AK |
133 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
134 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
135 | static void igb_clean_tx_ring(struct igb_ring *); |
136 | static void igb_clean_rx_ring(struct igb_ring *); | |
ff41f8dc | 137 | static void igb_set_rx_mode(struct net_device *); |
9d5c8243 AK |
138 | static void igb_update_phy_info(unsigned long); |
139 | static void igb_watchdog(unsigned long); | |
140 | static void igb_watchdog_task(struct work_struct *); | |
cd392f5c | 141 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); |
12dcd86b ED |
142 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, |
143 | struct rtnl_link_stats64 *stats); | |
9d5c8243 AK |
144 | static int igb_change_mtu(struct net_device *, int); |
145 | static int igb_set_mac(struct net_device *, void *); | |
68d480c4 | 146 | static void igb_set_uta(struct igb_adapter *adapter); |
9d5c8243 AK |
147 | static irqreturn_t igb_intr(int irq, void *); |
148 | static irqreturn_t igb_intr_msi(int irq, void *); | |
149 | static irqreturn_t igb_msix_other(int irq, void *); | |
047e0030 | 150 | static irqreturn_t igb_msix_ring(int irq, void *); |
421e02f0 | 151 | #ifdef CONFIG_IGB_DCA |
047e0030 | 152 | static void igb_update_dca(struct igb_q_vector *); |
fe4506b6 | 153 | static void igb_setup_dca(struct igb_adapter *); |
421e02f0 | 154 | #endif /* CONFIG_IGB_DCA */ |
661086df | 155 | static int igb_poll(struct napi_struct *, int); |
13fde97a | 156 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
cd392f5c | 157 | static bool igb_clean_rx_irq(struct igb_q_vector *, int); |
9d5c8243 AK |
158 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
159 | static void igb_tx_timeout(struct net_device *); | |
160 | static void igb_reset_task(struct work_struct *); | |
c8f44aff | 161 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); |
80d5c368 PM |
162 | static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); |
163 | static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); | |
9d5c8243 | 164 | static void igb_restore_vlan(struct igb_adapter *); |
26ad9178 | 165 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
4ae196df AD |
166 | static void igb_ping_all_vfs(struct igb_adapter *); |
167 | static void igb_msg_task(struct igb_adapter *); | |
4ae196df | 168 | static void igb_vmm_control(struct igb_adapter *); |
f2ca0dbe | 169 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
4ae196df | 170 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
8151d294 WM |
171 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); |
172 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
173 | int vf, u16 vlan, u8 qos); | |
174 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); | |
70ea4783 LL |
175 | static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, |
176 | bool setting); | |
8151d294 WM |
177 | static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, |
178 | struct ifla_vf_info *ivi); | |
17dc566c | 179 | static void igb_check_vf_rate_limit(struct igb_adapter *); |
46a01698 RL |
180 | |
181 | #ifdef CONFIG_PCI_IOV | |
0224d663 | 182 | static int igb_vf_configure(struct igb_adapter *adapter, int vf); |
f557147c | 183 | static bool igb_vfs_are_assigned(struct igb_adapter *adapter); |
46a01698 | 184 | #endif |
9d5c8243 | 185 | |
9d5c8243 | 186 | #ifdef CONFIG_PM |
d9dd966d | 187 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 188 | static int igb_suspend(struct device *); |
d9dd966d | 189 | #endif |
749ab2cd YZ |
190 | static int igb_resume(struct device *); |
191 | #ifdef CONFIG_PM_RUNTIME | |
192 | static int igb_runtime_suspend(struct device *dev); | |
193 | static int igb_runtime_resume(struct device *dev); | |
194 | static int igb_runtime_idle(struct device *dev); | |
195 | #endif | |
196 | static const struct dev_pm_ops igb_pm_ops = { | |
197 | SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) | |
198 | SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, | |
199 | igb_runtime_idle) | |
200 | }; | |
9d5c8243 AK |
201 | #endif |
202 | static void igb_shutdown(struct pci_dev *); | |
fa44f2f1 | 203 | static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); |
421e02f0 | 204 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
205 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
206 | static struct notifier_block dca_notifier = { | |
207 | .notifier_call = igb_notify_dca, | |
208 | .next = NULL, | |
209 | .priority = 0 | |
210 | }; | |
211 | #endif | |
9d5c8243 AK |
212 | #ifdef CONFIG_NET_POLL_CONTROLLER |
213 | /* for netdump / net console */ | |
214 | static void igb_netpoll(struct net_device *); | |
215 | #endif | |
37680117 | 216 | #ifdef CONFIG_PCI_IOV |
2a3abf6d AD |
217 | static unsigned int max_vfs = 0; |
218 | module_param(max_vfs, uint, 0); | |
219 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
220 | "per physical function"); | |
221 | #endif /* CONFIG_PCI_IOV */ | |
222 | ||
9d5c8243 AK |
223 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
224 | pci_channel_state_t); | |
225 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
226 | static void igb_io_resume(struct pci_dev *); | |
227 | ||
3646f0e5 | 228 | static const struct pci_error_handlers igb_err_handler = { |
9d5c8243 AK |
229 | .error_detected = igb_io_error_detected, |
230 | .slot_reset = igb_io_slot_reset, | |
231 | .resume = igb_io_resume, | |
232 | }; | |
233 | ||
b6e0c419 | 234 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); |
9d5c8243 AK |
235 | |
236 | static struct pci_driver igb_driver = { | |
237 | .name = igb_driver_name, | |
238 | .id_table = igb_pci_tbl, | |
239 | .probe = igb_probe, | |
9f9a12f8 | 240 | .remove = igb_remove, |
9d5c8243 | 241 | #ifdef CONFIG_PM |
749ab2cd | 242 | .driver.pm = &igb_pm_ops, |
9d5c8243 AK |
243 | #endif |
244 | .shutdown = igb_shutdown, | |
fa44f2f1 | 245 | .sriov_configure = igb_pci_sriov_configure, |
9d5c8243 AK |
246 | .err_handler = &igb_err_handler |
247 | }; | |
248 | ||
249 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
250 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
251 | MODULE_LICENSE("GPL"); | |
252 | MODULE_VERSION(DRV_VERSION); | |
253 | ||
b3f4d599 | 254 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
255 | static int debug = -1; | |
256 | module_param(debug, int, 0); | |
257 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
258 | ||
c97ec42a TI |
259 | struct igb_reg_info { |
260 | u32 ofs; | |
261 | char *name; | |
262 | }; | |
263 | ||
264 | static const struct igb_reg_info igb_reg_info_tbl[] = { | |
265 | ||
266 | /* General Registers */ | |
267 | {E1000_CTRL, "CTRL"}, | |
268 | {E1000_STATUS, "STATUS"}, | |
269 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
270 | ||
271 | /* Interrupt Registers */ | |
272 | {E1000_ICR, "ICR"}, | |
273 | ||
274 | /* RX Registers */ | |
275 | {E1000_RCTL, "RCTL"}, | |
276 | {E1000_RDLEN(0), "RDLEN"}, | |
277 | {E1000_RDH(0), "RDH"}, | |
278 | {E1000_RDT(0), "RDT"}, | |
279 | {E1000_RXDCTL(0), "RXDCTL"}, | |
280 | {E1000_RDBAL(0), "RDBAL"}, | |
281 | {E1000_RDBAH(0), "RDBAH"}, | |
282 | ||
283 | /* TX Registers */ | |
284 | {E1000_TCTL, "TCTL"}, | |
285 | {E1000_TDBAL(0), "TDBAL"}, | |
286 | {E1000_TDBAH(0), "TDBAH"}, | |
287 | {E1000_TDLEN(0), "TDLEN"}, | |
288 | {E1000_TDH(0), "TDH"}, | |
289 | {E1000_TDT(0), "TDT"}, | |
290 | {E1000_TXDCTL(0), "TXDCTL"}, | |
291 | {E1000_TDFH, "TDFH"}, | |
292 | {E1000_TDFT, "TDFT"}, | |
293 | {E1000_TDFHS, "TDFHS"}, | |
294 | {E1000_TDFPC, "TDFPC"}, | |
295 | ||
296 | /* List Terminator */ | |
297 | {} | |
298 | }; | |
299 | ||
b980ac18 | 300 | /* igb_regdump - register printout routine */ |
c97ec42a TI |
301 | static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) |
302 | { | |
303 | int n = 0; | |
304 | char rname[16]; | |
305 | u32 regs[8]; | |
306 | ||
307 | switch (reginfo->ofs) { | |
308 | case E1000_RDLEN(0): | |
309 | for (n = 0; n < 4; n++) | |
310 | regs[n] = rd32(E1000_RDLEN(n)); | |
311 | break; | |
312 | case E1000_RDH(0): | |
313 | for (n = 0; n < 4; n++) | |
314 | regs[n] = rd32(E1000_RDH(n)); | |
315 | break; | |
316 | case E1000_RDT(0): | |
317 | for (n = 0; n < 4; n++) | |
318 | regs[n] = rd32(E1000_RDT(n)); | |
319 | break; | |
320 | case E1000_RXDCTL(0): | |
321 | for (n = 0; n < 4; n++) | |
322 | regs[n] = rd32(E1000_RXDCTL(n)); | |
323 | break; | |
324 | case E1000_RDBAL(0): | |
325 | for (n = 0; n < 4; n++) | |
326 | regs[n] = rd32(E1000_RDBAL(n)); | |
327 | break; | |
328 | case E1000_RDBAH(0): | |
329 | for (n = 0; n < 4; n++) | |
330 | regs[n] = rd32(E1000_RDBAH(n)); | |
331 | break; | |
332 | case E1000_TDBAL(0): | |
333 | for (n = 0; n < 4; n++) | |
334 | regs[n] = rd32(E1000_RDBAL(n)); | |
335 | break; | |
336 | case E1000_TDBAH(0): | |
337 | for (n = 0; n < 4; n++) | |
338 | regs[n] = rd32(E1000_TDBAH(n)); | |
339 | break; | |
340 | case E1000_TDLEN(0): | |
341 | for (n = 0; n < 4; n++) | |
342 | regs[n] = rd32(E1000_TDLEN(n)); | |
343 | break; | |
344 | case E1000_TDH(0): | |
345 | for (n = 0; n < 4; n++) | |
346 | regs[n] = rd32(E1000_TDH(n)); | |
347 | break; | |
348 | case E1000_TDT(0): | |
349 | for (n = 0; n < 4; n++) | |
350 | regs[n] = rd32(E1000_TDT(n)); | |
351 | break; | |
352 | case E1000_TXDCTL(0): | |
353 | for (n = 0; n < 4; n++) | |
354 | regs[n] = rd32(E1000_TXDCTL(n)); | |
355 | break; | |
356 | default: | |
876d2d6f | 357 | pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); |
c97ec42a TI |
358 | return; |
359 | } | |
360 | ||
361 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); | |
876d2d6f JK |
362 | pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], |
363 | regs[2], regs[3]); | |
c97ec42a TI |
364 | } |
365 | ||
b980ac18 | 366 | /* igb_dump - Print registers, Tx-rings and Rx-rings */ |
c97ec42a TI |
367 | static void igb_dump(struct igb_adapter *adapter) |
368 | { | |
369 | struct net_device *netdev = adapter->netdev; | |
370 | struct e1000_hw *hw = &adapter->hw; | |
371 | struct igb_reg_info *reginfo; | |
c97ec42a TI |
372 | struct igb_ring *tx_ring; |
373 | union e1000_adv_tx_desc *tx_desc; | |
374 | struct my_u0 { u64 a; u64 b; } *u0; | |
c97ec42a TI |
375 | struct igb_ring *rx_ring; |
376 | union e1000_adv_rx_desc *rx_desc; | |
377 | u32 staterr; | |
6ad4edfc | 378 | u16 i, n; |
c97ec42a TI |
379 | |
380 | if (!netif_msg_hw(adapter)) | |
381 | return; | |
382 | ||
383 | /* Print netdevice Info */ | |
384 | if (netdev) { | |
385 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
876d2d6f JK |
386 | pr_info("Device Name state trans_start " |
387 | "last_rx\n"); | |
388 | pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, | |
389 | netdev->state, netdev->trans_start, netdev->last_rx); | |
c97ec42a TI |
390 | } |
391 | ||
392 | /* Print Registers */ | |
393 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
876d2d6f | 394 | pr_info(" Register Name Value\n"); |
c97ec42a TI |
395 | for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; |
396 | reginfo->name; reginfo++) { | |
397 | igb_regdump(hw, reginfo); | |
398 | } | |
399 | ||
400 | /* Print TX Ring Summary */ | |
401 | if (!netdev || !netif_running(netdev)) | |
402 | goto exit; | |
403 | ||
404 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
876d2d6f | 405 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
c97ec42a | 406 | for (n = 0; n < adapter->num_tx_queues; n++) { |
06034649 | 407 | struct igb_tx_buffer *buffer_info; |
c97ec42a | 408 | tx_ring = adapter->tx_ring[n]; |
06034649 | 409 | buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
876d2d6f JK |
410 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
411 | n, tx_ring->next_to_use, tx_ring->next_to_clean, | |
c9f14bf3 AD |
412 | (u64)dma_unmap_addr(buffer_info, dma), |
413 | dma_unmap_len(buffer_info, len), | |
876d2d6f JK |
414 | buffer_info->next_to_watch, |
415 | (u64)buffer_info->time_stamp); | |
c97ec42a TI |
416 | } |
417 | ||
418 | /* Print TX Rings */ | |
419 | if (!netif_msg_tx_done(adapter)) | |
420 | goto rx_ring_summary; | |
421 | ||
422 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
423 | ||
424 | /* Transmit Descriptor Formats | |
425 | * | |
426 | * Advanced Transmit Descriptor | |
427 | * +--------------------------------------------------------------+ | |
428 | * 0 | Buffer Address [63:0] | | |
429 | * +--------------------------------------------------------------+ | |
430 | * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | | |
431 | * +--------------------------------------------------------------+ | |
432 | * 63 46 45 40 39 38 36 35 32 31 24 15 0 | |
433 | */ | |
434 | ||
435 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
436 | tx_ring = adapter->tx_ring[n]; | |
876d2d6f JK |
437 | pr_info("------------------------------------\n"); |
438 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
439 | pr_info("------------------------------------\n"); | |
440 | pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " | |
441 | "[bi->dma ] leng ntw timestamp " | |
442 | "bi->skb\n"); | |
c97ec42a TI |
443 | |
444 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
876d2d6f | 445 | const char *next_desc; |
06034649 | 446 | struct igb_tx_buffer *buffer_info; |
60136906 | 447 | tx_desc = IGB_TX_DESC(tx_ring, i); |
06034649 | 448 | buffer_info = &tx_ring->tx_buffer_info[i]; |
c97ec42a | 449 | u0 = (struct my_u0 *)tx_desc; |
876d2d6f JK |
450 | if (i == tx_ring->next_to_use && |
451 | i == tx_ring->next_to_clean) | |
452 | next_desc = " NTC/U"; | |
453 | else if (i == tx_ring->next_to_use) | |
454 | next_desc = " NTU"; | |
455 | else if (i == tx_ring->next_to_clean) | |
456 | next_desc = " NTC"; | |
457 | else | |
458 | next_desc = ""; | |
459 | ||
460 | pr_info("T [0x%03X] %016llX %016llX %016llX" | |
461 | " %04X %p %016llX %p%s\n", i, | |
c97ec42a TI |
462 | le64_to_cpu(u0->a), |
463 | le64_to_cpu(u0->b), | |
c9f14bf3 AD |
464 | (u64)dma_unmap_addr(buffer_info, dma), |
465 | dma_unmap_len(buffer_info, len), | |
c97ec42a TI |
466 | buffer_info->next_to_watch, |
467 | (u64)buffer_info->time_stamp, | |
876d2d6f | 468 | buffer_info->skb, next_desc); |
c97ec42a | 469 | |
b669588a | 470 | if (netif_msg_pktdata(adapter) && buffer_info->skb) |
c97ec42a TI |
471 | print_hex_dump(KERN_INFO, "", |
472 | DUMP_PREFIX_ADDRESS, | |
b669588a | 473 | 16, 1, buffer_info->skb->data, |
c9f14bf3 AD |
474 | dma_unmap_len(buffer_info, len), |
475 | true); | |
c97ec42a TI |
476 | } |
477 | } | |
478 | ||
479 | /* Print RX Rings Summary */ | |
480 | rx_ring_summary: | |
481 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
876d2d6f | 482 | pr_info("Queue [NTU] [NTC]\n"); |
c97ec42a TI |
483 | for (n = 0; n < adapter->num_rx_queues; n++) { |
484 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
485 | pr_info(" %5d %5X %5X\n", |
486 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
c97ec42a TI |
487 | } |
488 | ||
489 | /* Print RX Rings */ | |
490 | if (!netif_msg_rx_status(adapter)) | |
491 | goto exit; | |
492 | ||
493 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
494 | ||
495 | /* Advanced Receive Descriptor (Read) Format | |
496 | * 63 1 0 | |
497 | * +-----------------------------------------------------+ | |
498 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
499 | * +----------------------------------------------+------+ | |
500 | * 8 | Header Buffer Address [63:1] | DD | | |
501 | * +-----------------------------------------------------+ | |
502 | * | |
503 | * | |
504 | * Advanced Receive Descriptor (Write-Back) Format | |
505 | * | |
506 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
507 | * +------------------------------------------------------+ | |
508 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
509 | * | Checksum Ident | | | | Type | Type | | |
510 | * +------------------------------------------------------+ | |
511 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
512 | * +------------------------------------------------------+ | |
513 | * 63 48 47 32 31 20 19 0 | |
514 | */ | |
515 | ||
516 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
517 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
518 | pr_info("------------------------------------\n"); |
519 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
520 | pr_info("------------------------------------\n"); | |
521 | pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " | |
522 | "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); | |
523 | pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" | |
524 | "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); | |
c97ec42a TI |
525 | |
526 | for (i = 0; i < rx_ring->count; i++) { | |
876d2d6f | 527 | const char *next_desc; |
06034649 AD |
528 | struct igb_rx_buffer *buffer_info; |
529 | buffer_info = &rx_ring->rx_buffer_info[i]; | |
60136906 | 530 | rx_desc = IGB_RX_DESC(rx_ring, i); |
c97ec42a TI |
531 | u0 = (struct my_u0 *)rx_desc; |
532 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
876d2d6f JK |
533 | |
534 | if (i == rx_ring->next_to_use) | |
535 | next_desc = " NTU"; | |
536 | else if (i == rx_ring->next_to_clean) | |
537 | next_desc = " NTC"; | |
538 | else | |
539 | next_desc = ""; | |
540 | ||
c97ec42a TI |
541 | if (staterr & E1000_RXD_STAT_DD) { |
542 | /* Descriptor Done */ | |
1a1c225b AD |
543 | pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", |
544 | "RWB", i, | |
c97ec42a TI |
545 | le64_to_cpu(u0->a), |
546 | le64_to_cpu(u0->b), | |
1a1c225b | 547 | next_desc); |
c97ec42a | 548 | } else { |
1a1c225b AD |
549 | pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", |
550 | "R ", i, | |
c97ec42a TI |
551 | le64_to_cpu(u0->a), |
552 | le64_to_cpu(u0->b), | |
553 | (u64)buffer_info->dma, | |
1a1c225b | 554 | next_desc); |
c97ec42a | 555 | |
b669588a | 556 | if (netif_msg_pktdata(adapter) && |
1a1c225b | 557 | buffer_info->dma && buffer_info->page) { |
44390ca6 AD |
558 | print_hex_dump(KERN_INFO, "", |
559 | DUMP_PREFIX_ADDRESS, | |
560 | 16, 1, | |
b669588a ET |
561 | page_address(buffer_info->page) + |
562 | buffer_info->page_offset, | |
de78d1f9 | 563 | IGB_RX_BUFSZ, true); |
c97ec42a TI |
564 | } |
565 | } | |
c97ec42a TI |
566 | } |
567 | } | |
568 | ||
569 | exit: | |
570 | return; | |
571 | } | |
572 | ||
b980ac18 JK |
573 | /** |
574 | * igb_get_i2c_data - Reads the I2C SDA data bit | |
441fc6fd CW |
575 | * @hw: pointer to hardware structure |
576 | * @i2cctl: Current value of I2CCTL register | |
577 | * | |
578 | * Returns the I2C data bit value | |
b980ac18 | 579 | **/ |
441fc6fd CW |
580 | static int igb_get_i2c_data(void *data) |
581 | { | |
582 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
583 | struct e1000_hw *hw = &adapter->hw; | |
584 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
585 | ||
586 | return ((i2cctl & E1000_I2C_DATA_IN) != 0); | |
587 | } | |
588 | ||
b980ac18 JK |
589 | /** |
590 | * igb_set_i2c_data - Sets the I2C data bit | |
441fc6fd CW |
591 | * @data: pointer to hardware structure |
592 | * @state: I2C data value (0 or 1) to set | |
593 | * | |
594 | * Sets the I2C data bit | |
b980ac18 | 595 | **/ |
441fc6fd CW |
596 | static void igb_set_i2c_data(void *data, int state) |
597 | { | |
598 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
599 | struct e1000_hw *hw = &adapter->hw; | |
600 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
601 | ||
602 | if (state) | |
603 | i2cctl |= E1000_I2C_DATA_OUT; | |
604 | else | |
605 | i2cctl &= ~E1000_I2C_DATA_OUT; | |
606 | ||
607 | i2cctl &= ~E1000_I2C_DATA_OE_N; | |
608 | i2cctl |= E1000_I2C_CLK_OE_N; | |
609 | wr32(E1000_I2CPARAMS, i2cctl); | |
610 | wrfl(); | |
611 | ||
612 | } | |
613 | ||
b980ac18 JK |
614 | /** |
615 | * igb_set_i2c_clk - Sets the I2C SCL clock | |
441fc6fd CW |
616 | * @data: pointer to hardware structure |
617 | * @state: state to set clock | |
618 | * | |
619 | * Sets the I2C clock line to state | |
b980ac18 | 620 | **/ |
441fc6fd CW |
621 | static void igb_set_i2c_clk(void *data, int state) |
622 | { | |
623 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
624 | struct e1000_hw *hw = &adapter->hw; | |
625 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
626 | ||
627 | if (state) { | |
628 | i2cctl |= E1000_I2C_CLK_OUT; | |
629 | i2cctl &= ~E1000_I2C_CLK_OE_N; | |
630 | } else { | |
631 | i2cctl &= ~E1000_I2C_CLK_OUT; | |
632 | i2cctl &= ~E1000_I2C_CLK_OE_N; | |
633 | } | |
634 | wr32(E1000_I2CPARAMS, i2cctl); | |
635 | wrfl(); | |
636 | } | |
637 | ||
b980ac18 JK |
638 | /** |
639 | * igb_get_i2c_clk - Gets the I2C SCL clock state | |
441fc6fd CW |
640 | * @data: pointer to hardware structure |
641 | * | |
642 | * Gets the I2C clock state | |
b980ac18 | 643 | **/ |
441fc6fd CW |
644 | static int igb_get_i2c_clk(void *data) |
645 | { | |
646 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
647 | struct e1000_hw *hw = &adapter->hw; | |
648 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
649 | ||
650 | return ((i2cctl & E1000_I2C_CLK_IN) != 0); | |
651 | } | |
652 | ||
653 | static const struct i2c_algo_bit_data igb_i2c_algo = { | |
654 | .setsda = igb_set_i2c_data, | |
655 | .setscl = igb_set_i2c_clk, | |
656 | .getsda = igb_get_i2c_data, | |
657 | .getscl = igb_get_i2c_clk, | |
658 | .udelay = 5, | |
659 | .timeout = 20, | |
660 | }; | |
661 | ||
9d5c8243 | 662 | /** |
b980ac18 JK |
663 | * igb_get_hw_dev - return device |
664 | * @hw: pointer to hardware structure | |
665 | * | |
666 | * used by hardware layer to print debugging information | |
9d5c8243 | 667 | **/ |
c041076a | 668 | struct net_device *igb_get_hw_dev(struct e1000_hw *hw) |
9d5c8243 AK |
669 | { |
670 | struct igb_adapter *adapter = hw->back; | |
c041076a | 671 | return adapter->netdev; |
9d5c8243 | 672 | } |
38c845c7 | 673 | |
9d5c8243 | 674 | /** |
b980ac18 | 675 | * igb_init_module - Driver Registration Routine |
9d5c8243 | 676 | * |
b980ac18 JK |
677 | * igb_init_module is the first routine called when the driver is |
678 | * loaded. All it does is register with the PCI subsystem. | |
9d5c8243 AK |
679 | **/ |
680 | static int __init igb_init_module(void) | |
681 | { | |
682 | int ret; | |
876d2d6f | 683 | pr_info("%s - version %s\n", |
9d5c8243 AK |
684 | igb_driver_string, igb_driver_version); |
685 | ||
876d2d6f | 686 | pr_info("%s\n", igb_copyright); |
9d5c8243 | 687 | |
421e02f0 | 688 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
689 | dca_register_notify(&dca_notifier); |
690 | #endif | |
bbd98fe4 | 691 | ret = pci_register_driver(&igb_driver); |
9d5c8243 AK |
692 | return ret; |
693 | } | |
694 | ||
695 | module_init(igb_init_module); | |
696 | ||
697 | /** | |
b980ac18 | 698 | * igb_exit_module - Driver Exit Cleanup Routine |
9d5c8243 | 699 | * |
b980ac18 JK |
700 | * igb_exit_module is called just before the driver is removed |
701 | * from memory. | |
9d5c8243 AK |
702 | **/ |
703 | static void __exit igb_exit_module(void) | |
704 | { | |
421e02f0 | 705 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
706 | dca_unregister_notify(&dca_notifier); |
707 | #endif | |
9d5c8243 AK |
708 | pci_unregister_driver(&igb_driver); |
709 | } | |
710 | ||
711 | module_exit(igb_exit_module); | |
712 | ||
26bc19ec AD |
713 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
714 | /** | |
b980ac18 JK |
715 | * igb_cache_ring_register - Descriptor ring to register mapping |
716 | * @adapter: board private structure to initialize | |
26bc19ec | 717 | * |
b980ac18 JK |
718 | * Once we know the feature-set enabled for the device, we'll cache |
719 | * the register offset the descriptor ring is assigned to. | |
26bc19ec AD |
720 | **/ |
721 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
722 | { | |
ee1b9f06 | 723 | int i = 0, j = 0; |
047e0030 | 724 | u32 rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
725 | |
726 | switch (adapter->hw.mac.type) { | |
727 | case e1000_82576: | |
728 | /* The queues are allocated for virtualization such that VF 0 | |
729 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
730 | * In order to avoid collision we start at the first free queue | |
731 | * and continue consuming queues in the same sequence | |
732 | */ | |
ee1b9f06 | 733 | if (adapter->vfs_allocated_count) { |
a99955fc | 734 | for (; i < adapter->rss_queues; i++) |
3025a446 | 735 | adapter->rx_ring[i]->reg_idx = rbase_offset + |
b980ac18 | 736 | Q_IDX_82576(i); |
ee1b9f06 | 737 | } |
26bc19ec | 738 | case e1000_82575: |
55cac248 | 739 | case e1000_82580: |
d2ba2ed8 | 740 | case e1000_i350: |
ceb5f13b | 741 | case e1000_i354: |
f96a8a0b CW |
742 | case e1000_i210: |
743 | case e1000_i211: | |
26bc19ec | 744 | default: |
ee1b9f06 | 745 | for (; i < adapter->num_rx_queues; i++) |
3025a446 | 746 | adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
ee1b9f06 | 747 | for (; j < adapter->num_tx_queues; j++) |
3025a446 | 748 | adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
26bc19ec AD |
749 | break; |
750 | } | |
751 | } | |
752 | ||
4be000c8 AD |
753 | /** |
754 | * igb_write_ivar - configure ivar for given MSI-X vector | |
755 | * @hw: pointer to the HW structure | |
756 | * @msix_vector: vector number we are allocating to a given ring | |
757 | * @index: row index of IVAR register to write within IVAR table | |
758 | * @offset: column offset of in IVAR, should be multiple of 8 | |
759 | * | |
760 | * This function is intended to handle the writing of the IVAR register | |
761 | * for adapters 82576 and newer. The IVAR table consists of 2 columns, | |
762 | * each containing an cause allocation for an Rx and Tx ring, and a | |
763 | * variable number of rows depending on the number of queues supported. | |
764 | **/ | |
765 | static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, | |
766 | int index, int offset) | |
767 | { | |
768 | u32 ivar = array_rd32(E1000_IVAR0, index); | |
769 | ||
770 | /* clear any bits that are currently set */ | |
771 | ivar &= ~((u32)0xFF << offset); | |
772 | ||
773 | /* write vector and valid bit */ | |
774 | ivar |= (msix_vector | E1000_IVAR_VALID) << offset; | |
775 | ||
776 | array_wr32(E1000_IVAR0, index, ivar); | |
777 | } | |
778 | ||
9d5c8243 | 779 | #define IGB_N0_QUEUE -1 |
047e0030 | 780 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
9d5c8243 | 781 | { |
047e0030 | 782 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 783 | struct e1000_hw *hw = &adapter->hw; |
047e0030 AD |
784 | int rx_queue = IGB_N0_QUEUE; |
785 | int tx_queue = IGB_N0_QUEUE; | |
4be000c8 | 786 | u32 msixbm = 0; |
047e0030 | 787 | |
0ba82994 AD |
788 | if (q_vector->rx.ring) |
789 | rx_queue = q_vector->rx.ring->reg_idx; | |
790 | if (q_vector->tx.ring) | |
791 | tx_queue = q_vector->tx.ring->reg_idx; | |
2d064c06 AD |
792 | |
793 | switch (hw->mac.type) { | |
794 | case e1000_82575: | |
9d5c8243 | 795 | /* The 82575 assigns vectors using a bitmask, which matches the |
b980ac18 JK |
796 | * bitmask for the EICR/EIMS/EIMC registers. To assign one |
797 | * or more queues to a vector, we write the appropriate bits | |
798 | * into the MSIXBM register for that vector. | |
799 | */ | |
047e0030 | 800 | if (rx_queue > IGB_N0_QUEUE) |
9d5c8243 | 801 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
047e0030 | 802 | if (tx_queue > IGB_N0_QUEUE) |
9d5c8243 | 803 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
feeb2721 AD |
804 | if (!adapter->msix_entries && msix_vector == 0) |
805 | msixbm |= E1000_EIMS_OTHER; | |
9d5c8243 | 806 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
047e0030 | 807 | q_vector->eims_value = msixbm; |
2d064c06 AD |
808 | break; |
809 | case e1000_82576: | |
b980ac18 | 810 | /* 82576 uses a table that essentially consists of 2 columns |
4be000c8 AD |
811 | * with 8 rows. The ordering is column-major so we use the |
812 | * lower 3 bits as the row index, and the 4th bit as the | |
813 | * column offset. | |
814 | */ | |
815 | if (rx_queue > IGB_N0_QUEUE) | |
816 | igb_write_ivar(hw, msix_vector, | |
817 | rx_queue & 0x7, | |
818 | (rx_queue & 0x8) << 1); | |
819 | if (tx_queue > IGB_N0_QUEUE) | |
820 | igb_write_ivar(hw, msix_vector, | |
821 | tx_queue & 0x7, | |
822 | ((tx_queue & 0x8) << 1) + 8); | |
047e0030 | 823 | q_vector->eims_value = 1 << msix_vector; |
2d064c06 | 824 | break; |
55cac248 | 825 | case e1000_82580: |
d2ba2ed8 | 826 | case e1000_i350: |
ceb5f13b | 827 | case e1000_i354: |
f96a8a0b CW |
828 | case e1000_i210: |
829 | case e1000_i211: | |
b980ac18 | 830 | /* On 82580 and newer adapters the scheme is similar to 82576 |
4be000c8 AD |
831 | * however instead of ordering column-major we have things |
832 | * ordered row-major. So we traverse the table by using | |
833 | * bit 0 as the column offset, and the remaining bits as the | |
834 | * row index. | |
835 | */ | |
836 | if (rx_queue > IGB_N0_QUEUE) | |
837 | igb_write_ivar(hw, msix_vector, | |
838 | rx_queue >> 1, | |
839 | (rx_queue & 0x1) << 4); | |
840 | if (tx_queue > IGB_N0_QUEUE) | |
841 | igb_write_ivar(hw, msix_vector, | |
842 | tx_queue >> 1, | |
843 | ((tx_queue & 0x1) << 4) + 8); | |
55cac248 AD |
844 | q_vector->eims_value = 1 << msix_vector; |
845 | break; | |
2d064c06 AD |
846 | default: |
847 | BUG(); | |
848 | break; | |
849 | } | |
26b39276 AD |
850 | |
851 | /* add q_vector eims value to global eims_enable_mask */ | |
852 | adapter->eims_enable_mask |= q_vector->eims_value; | |
853 | ||
854 | /* configure q_vector to set itr on first interrupt */ | |
855 | q_vector->set_itr = 1; | |
9d5c8243 AK |
856 | } |
857 | ||
858 | /** | |
b980ac18 JK |
859 | * igb_configure_msix - Configure MSI-X hardware |
860 | * @adapter: board private structure to initialize | |
9d5c8243 | 861 | * |
b980ac18 JK |
862 | * igb_configure_msix sets up the hardware to properly |
863 | * generate MSI-X interrupts. | |
9d5c8243 AK |
864 | **/ |
865 | static void igb_configure_msix(struct igb_adapter *adapter) | |
866 | { | |
867 | u32 tmp; | |
868 | int i, vector = 0; | |
869 | struct e1000_hw *hw = &adapter->hw; | |
870 | ||
871 | adapter->eims_enable_mask = 0; | |
9d5c8243 AK |
872 | |
873 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
874 | switch (hw->mac.type) { |
875 | case e1000_82575: | |
9d5c8243 AK |
876 | tmp = rd32(E1000_CTRL_EXT); |
877 | /* enable MSI-X PBA support*/ | |
878 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
879 | ||
880 | /* Auto-Mask interrupts upon ICR read. */ | |
881 | tmp |= E1000_CTRL_EXT_EIAME; | |
882 | tmp |= E1000_CTRL_EXT_IRCA; | |
883 | ||
884 | wr32(E1000_CTRL_EXT, tmp); | |
047e0030 AD |
885 | |
886 | /* enable msix_other interrupt */ | |
b980ac18 | 887 | array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); |
844290e5 | 888 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 889 | |
2d064c06 AD |
890 | break; |
891 | ||
892 | case e1000_82576: | |
55cac248 | 893 | case e1000_82580: |
d2ba2ed8 | 894 | case e1000_i350: |
ceb5f13b | 895 | case e1000_i354: |
f96a8a0b CW |
896 | case e1000_i210: |
897 | case e1000_i211: | |
047e0030 | 898 | /* Turn on MSI-X capability first, or our settings |
b980ac18 JK |
899 | * won't stick. And it will take days to debug. |
900 | */ | |
047e0030 | 901 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | |
b980ac18 JK |
902 | E1000_GPIE_PBA | E1000_GPIE_EIAME | |
903 | E1000_GPIE_NSICR); | |
047e0030 AD |
904 | |
905 | /* enable msix_other interrupt */ | |
906 | adapter->eims_other = 1 << vector; | |
2d064c06 | 907 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
2d064c06 | 908 | |
047e0030 | 909 | wr32(E1000_IVAR_MISC, tmp); |
2d064c06 AD |
910 | break; |
911 | default: | |
912 | /* do nothing, since nothing else supports MSI-X */ | |
913 | break; | |
914 | } /* switch (hw->mac.type) */ | |
047e0030 AD |
915 | |
916 | adapter->eims_enable_mask |= adapter->eims_other; | |
917 | ||
26b39276 AD |
918 | for (i = 0; i < adapter->num_q_vectors; i++) |
919 | igb_assign_vector(adapter->q_vector[i], vector++); | |
047e0030 | 920 | |
9d5c8243 AK |
921 | wrfl(); |
922 | } | |
923 | ||
924 | /** | |
b980ac18 JK |
925 | * igb_request_msix - Initialize MSI-X interrupts |
926 | * @adapter: board private structure to initialize | |
9d5c8243 | 927 | * |
b980ac18 JK |
928 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the |
929 | * kernel. | |
9d5c8243 AK |
930 | **/ |
931 | static int igb_request_msix(struct igb_adapter *adapter) | |
932 | { | |
933 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 934 | struct e1000_hw *hw = &adapter->hw; |
52285b76 | 935 | int i, err = 0, vector = 0, free_vector = 0; |
9d5c8243 | 936 | |
047e0030 | 937 | err = request_irq(adapter->msix_entries[vector].vector, |
b980ac18 | 938 | igb_msix_other, 0, netdev->name, adapter); |
047e0030 | 939 | if (err) |
52285b76 | 940 | goto err_out; |
047e0030 AD |
941 | |
942 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
943 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
944 | ||
52285b76 SA |
945 | vector++; |
946 | ||
047e0030 AD |
947 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); |
948 | ||
0ba82994 | 949 | if (q_vector->rx.ring && q_vector->tx.ring) |
047e0030 | 950 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, |
0ba82994 AD |
951 | q_vector->rx.ring->queue_index); |
952 | else if (q_vector->tx.ring) | |
047e0030 | 953 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, |
0ba82994 AD |
954 | q_vector->tx.ring->queue_index); |
955 | else if (q_vector->rx.ring) | |
047e0030 | 956 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, |
0ba82994 | 957 | q_vector->rx.ring->queue_index); |
9d5c8243 | 958 | else |
047e0030 AD |
959 | sprintf(q_vector->name, "%s-unused", netdev->name); |
960 | ||
9d5c8243 | 961 | err = request_irq(adapter->msix_entries[vector].vector, |
b980ac18 JK |
962 | igb_msix_ring, 0, q_vector->name, |
963 | q_vector); | |
9d5c8243 | 964 | if (err) |
52285b76 | 965 | goto err_free; |
9d5c8243 AK |
966 | } |
967 | ||
9d5c8243 AK |
968 | igb_configure_msix(adapter); |
969 | return 0; | |
52285b76 SA |
970 | |
971 | err_free: | |
972 | /* free already assigned IRQs */ | |
973 | free_irq(adapter->msix_entries[free_vector++].vector, adapter); | |
974 | ||
975 | vector--; | |
976 | for (i = 0; i < vector; i++) { | |
977 | free_irq(adapter->msix_entries[free_vector++].vector, | |
978 | adapter->q_vector[i]); | |
979 | } | |
980 | err_out: | |
9d5c8243 AK |
981 | return err; |
982 | } | |
983 | ||
984 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
985 | { | |
986 | if (adapter->msix_entries) { | |
987 | pci_disable_msix(adapter->pdev); | |
988 | kfree(adapter->msix_entries); | |
989 | adapter->msix_entries = NULL; | |
047e0030 | 990 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 991 | pci_disable_msi(adapter->pdev); |
047e0030 | 992 | } |
9d5c8243 AK |
993 | } |
994 | ||
5536d210 | 995 | /** |
b980ac18 JK |
996 | * igb_free_q_vector - Free memory allocated for specific interrupt vector |
997 | * @adapter: board private structure to initialize | |
998 | * @v_idx: Index of vector to be freed | |
5536d210 | 999 | * |
b980ac18 JK |
1000 | * This function frees the memory allocated to the q_vector. In addition if |
1001 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1002 | * to freeing the q_vector. | |
5536d210 AD |
1003 | **/ |
1004 | static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) | |
1005 | { | |
1006 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | |
1007 | ||
1008 | if (q_vector->tx.ring) | |
1009 | adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; | |
1010 | ||
1011 | if (q_vector->rx.ring) | |
1012 | adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; | |
1013 | ||
1014 | adapter->q_vector[v_idx] = NULL; | |
1015 | netif_napi_del(&q_vector->napi); | |
1016 | ||
b980ac18 | 1017 | /* ixgbe_get_stats64() might access the rings on this vector, |
5536d210 AD |
1018 | * we must wait a grace period before freeing it. |
1019 | */ | |
1020 | kfree_rcu(q_vector, rcu); | |
1021 | } | |
1022 | ||
047e0030 | 1023 | /** |
b980ac18 JK |
1024 | * igb_free_q_vectors - Free memory allocated for interrupt vectors |
1025 | * @adapter: board private structure to initialize | |
047e0030 | 1026 | * |
b980ac18 JK |
1027 | * This function frees the memory allocated to the q_vectors. In addition if |
1028 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1029 | * to freeing the q_vector. | |
047e0030 AD |
1030 | **/ |
1031 | static void igb_free_q_vectors(struct igb_adapter *adapter) | |
1032 | { | |
5536d210 AD |
1033 | int v_idx = adapter->num_q_vectors; |
1034 | ||
1035 | adapter->num_tx_queues = 0; | |
1036 | adapter->num_rx_queues = 0; | |
047e0030 | 1037 | adapter->num_q_vectors = 0; |
5536d210 AD |
1038 | |
1039 | while (v_idx--) | |
1040 | igb_free_q_vector(adapter, v_idx); | |
047e0030 AD |
1041 | } |
1042 | ||
1043 | /** | |
b980ac18 JK |
1044 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts |
1045 | * @adapter: board private structure to initialize | |
047e0030 | 1046 | * |
b980ac18 JK |
1047 | * This function resets the device so that it has 0 Rx queues, Tx queues, and |
1048 | * MSI-X interrupts allocated. | |
047e0030 AD |
1049 | */ |
1050 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | |
1051 | { | |
047e0030 AD |
1052 | igb_free_q_vectors(adapter); |
1053 | igb_reset_interrupt_capability(adapter); | |
1054 | } | |
9d5c8243 AK |
1055 | |
1056 | /** | |
b980ac18 JK |
1057 | * igb_set_interrupt_capability - set MSI or MSI-X if supported |
1058 | * @adapter: board private structure to initialize | |
1059 | * @msix: boolean value of MSIX capability | |
9d5c8243 | 1060 | * |
b980ac18 JK |
1061 | * Attempt to configure interrupts using the best available |
1062 | * capabilities of the hardware and kernel. | |
9d5c8243 | 1063 | **/ |
53c7d064 | 1064 | static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) |
9d5c8243 AK |
1065 | { |
1066 | int err; | |
1067 | int numvecs, i; | |
1068 | ||
53c7d064 SA |
1069 | if (!msix) |
1070 | goto msi_only; | |
1071 | ||
83b7180d | 1072 | /* Number of supported queues. */ |
a99955fc | 1073 | adapter->num_rx_queues = adapter->rss_queues; |
5fa8517f GR |
1074 | if (adapter->vfs_allocated_count) |
1075 | adapter->num_tx_queues = 1; | |
1076 | else | |
1077 | adapter->num_tx_queues = adapter->rss_queues; | |
83b7180d | 1078 | |
b980ac18 | 1079 | /* start with one vector for every Rx queue */ |
047e0030 AD |
1080 | numvecs = adapter->num_rx_queues; |
1081 | ||
b980ac18 | 1082 | /* if Tx handler is separate add 1 for every Tx queue */ |
a99955fc AD |
1083 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
1084 | numvecs += adapter->num_tx_queues; | |
047e0030 AD |
1085 | |
1086 | /* store the number of vectors reserved for queues */ | |
1087 | adapter->num_q_vectors = numvecs; | |
1088 | ||
1089 | /* add 1 vector for link status interrupts */ | |
1090 | numvecs++; | |
9d5c8243 AK |
1091 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
1092 | GFP_KERNEL); | |
f96a8a0b | 1093 | |
9d5c8243 AK |
1094 | if (!adapter->msix_entries) |
1095 | goto msi_only; | |
1096 | ||
1097 | for (i = 0; i < numvecs; i++) | |
1098 | adapter->msix_entries[i].entry = i; | |
1099 | ||
1100 | err = pci_enable_msix(adapter->pdev, | |
1101 | adapter->msix_entries, | |
1102 | numvecs); | |
1103 | if (err == 0) | |
0c2cc02e | 1104 | return; |
9d5c8243 AK |
1105 | |
1106 | igb_reset_interrupt_capability(adapter); | |
1107 | ||
1108 | /* If we can't do MSI-X, try MSI */ | |
1109 | msi_only: | |
2a3abf6d AD |
1110 | #ifdef CONFIG_PCI_IOV |
1111 | /* disable SR-IOV for non MSI-X configurations */ | |
1112 | if (adapter->vf_data) { | |
1113 | struct e1000_hw *hw = &adapter->hw; | |
1114 | /* disable iov and allow time for transactions to clear */ | |
1115 | pci_disable_sriov(adapter->pdev); | |
1116 | msleep(500); | |
1117 | ||
1118 | kfree(adapter->vf_data); | |
1119 | adapter->vf_data = NULL; | |
1120 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
945a5151 | 1121 | wrfl(); |
2a3abf6d AD |
1122 | msleep(100); |
1123 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | |
1124 | } | |
1125 | #endif | |
4fc82adf | 1126 | adapter->vfs_allocated_count = 0; |
a99955fc | 1127 | adapter->rss_queues = 1; |
4fc82adf | 1128 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
9d5c8243 | 1129 | adapter->num_rx_queues = 1; |
661086df | 1130 | adapter->num_tx_queues = 1; |
047e0030 | 1131 | adapter->num_q_vectors = 1; |
9d5c8243 | 1132 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1133 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1134 | } |
1135 | ||
5536d210 AD |
1136 | static void igb_add_ring(struct igb_ring *ring, |
1137 | struct igb_ring_container *head) | |
1138 | { | |
1139 | head->ring = ring; | |
1140 | head->count++; | |
1141 | } | |
1142 | ||
047e0030 | 1143 | /** |
b980ac18 JK |
1144 | * igb_alloc_q_vector - Allocate memory for a single interrupt vector |
1145 | * @adapter: board private structure to initialize | |
1146 | * @v_count: q_vectors allocated on adapter, used for ring interleaving | |
1147 | * @v_idx: index of vector in adapter struct | |
1148 | * @txr_count: total number of Tx rings to allocate | |
1149 | * @txr_idx: index of first Tx ring to allocate | |
1150 | * @rxr_count: total number of Rx rings to allocate | |
1151 | * @rxr_idx: index of first Rx ring to allocate | |
047e0030 | 1152 | * |
b980ac18 | 1153 | * We allocate one q_vector. If allocation fails we return -ENOMEM. |
047e0030 | 1154 | **/ |
5536d210 AD |
1155 | static int igb_alloc_q_vector(struct igb_adapter *adapter, |
1156 | int v_count, int v_idx, | |
1157 | int txr_count, int txr_idx, | |
1158 | int rxr_count, int rxr_idx) | |
047e0030 AD |
1159 | { |
1160 | struct igb_q_vector *q_vector; | |
5536d210 AD |
1161 | struct igb_ring *ring; |
1162 | int ring_count, size; | |
047e0030 | 1163 | |
5536d210 AD |
1164 | /* igb only supports 1 Tx and/or 1 Rx queue per vector */ |
1165 | if (txr_count > 1 || rxr_count > 1) | |
1166 | return -ENOMEM; | |
1167 | ||
1168 | ring_count = txr_count + rxr_count; | |
1169 | size = sizeof(struct igb_q_vector) + | |
1170 | (sizeof(struct igb_ring) * ring_count); | |
1171 | ||
1172 | /* allocate q_vector and rings */ | |
1173 | q_vector = kzalloc(size, GFP_KERNEL); | |
1174 | if (!q_vector) | |
1175 | return -ENOMEM; | |
1176 | ||
1177 | /* initialize NAPI */ | |
1178 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
1179 | igb_poll, 64); | |
1180 | ||
1181 | /* tie q_vector and adapter together */ | |
1182 | adapter->q_vector[v_idx] = q_vector; | |
1183 | q_vector->adapter = adapter; | |
1184 | ||
1185 | /* initialize work limits */ | |
1186 | q_vector->tx.work_limit = adapter->tx_work_limit; | |
1187 | ||
1188 | /* initialize ITR configuration */ | |
1189 | q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); | |
1190 | q_vector->itr_val = IGB_START_ITR; | |
1191 | ||
1192 | /* initialize pointer to rings */ | |
1193 | ring = q_vector->ring; | |
1194 | ||
4e227667 AD |
1195 | /* intialize ITR */ |
1196 | if (rxr_count) { | |
1197 | /* rx or rx/tx vector */ | |
1198 | if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) | |
1199 | q_vector->itr_val = adapter->rx_itr_setting; | |
1200 | } else { | |
1201 | /* tx only vector */ | |
1202 | if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) | |
1203 | q_vector->itr_val = adapter->tx_itr_setting; | |
1204 | } | |
1205 | ||
5536d210 AD |
1206 | if (txr_count) { |
1207 | /* assign generic ring traits */ | |
1208 | ring->dev = &adapter->pdev->dev; | |
1209 | ring->netdev = adapter->netdev; | |
1210 | ||
1211 | /* configure backlink on ring */ | |
1212 | ring->q_vector = q_vector; | |
1213 | ||
1214 | /* update q_vector Tx values */ | |
1215 | igb_add_ring(ring, &q_vector->tx); | |
1216 | ||
1217 | /* For 82575, context index must be unique per ring. */ | |
1218 | if (adapter->hw.mac.type == e1000_82575) | |
1219 | set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); | |
1220 | ||
1221 | /* apply Tx specific ring traits */ | |
1222 | ring->count = adapter->tx_ring_count; | |
1223 | ring->queue_index = txr_idx; | |
1224 | ||
1225 | /* assign ring to adapter */ | |
1226 | adapter->tx_ring[txr_idx] = ring; | |
1227 | ||
1228 | /* push pointer to next ring */ | |
1229 | ring++; | |
047e0030 | 1230 | } |
81c2fc22 | 1231 | |
5536d210 AD |
1232 | if (rxr_count) { |
1233 | /* assign generic ring traits */ | |
1234 | ring->dev = &adapter->pdev->dev; | |
1235 | ring->netdev = adapter->netdev; | |
047e0030 | 1236 | |
5536d210 AD |
1237 | /* configure backlink on ring */ |
1238 | ring->q_vector = q_vector; | |
047e0030 | 1239 | |
5536d210 AD |
1240 | /* update q_vector Rx values */ |
1241 | igb_add_ring(ring, &q_vector->rx); | |
047e0030 | 1242 | |
5536d210 AD |
1243 | /* set flag indicating ring supports SCTP checksum offload */ |
1244 | if (adapter->hw.mac.type >= e1000_82576) | |
1245 | set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); | |
047e0030 | 1246 | |
ceb5f13b CW |
1247 | /* |
1248 | * On i350, i354, i210, and i211, loopback VLAN packets | |
5536d210 | 1249 | * have the tag byte-swapped. |
b980ac18 | 1250 | */ |
5536d210 AD |
1251 | if (adapter->hw.mac.type >= e1000_i350) |
1252 | set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); | |
047e0030 | 1253 | |
5536d210 AD |
1254 | /* apply Rx specific ring traits */ |
1255 | ring->count = adapter->rx_ring_count; | |
1256 | ring->queue_index = rxr_idx; | |
1257 | ||
1258 | /* assign ring to adapter */ | |
1259 | adapter->rx_ring[rxr_idx] = ring; | |
1260 | } | |
1261 | ||
1262 | return 0; | |
047e0030 AD |
1263 | } |
1264 | ||
5536d210 | 1265 | |
047e0030 | 1266 | /** |
b980ac18 JK |
1267 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors |
1268 | * @adapter: board private structure to initialize | |
047e0030 | 1269 | * |
b980ac18 JK |
1270 | * We allocate one q_vector per queue interrupt. If allocation fails we |
1271 | * return -ENOMEM. | |
047e0030 | 1272 | **/ |
5536d210 | 1273 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) |
047e0030 | 1274 | { |
5536d210 AD |
1275 | int q_vectors = adapter->num_q_vectors; |
1276 | int rxr_remaining = adapter->num_rx_queues; | |
1277 | int txr_remaining = adapter->num_tx_queues; | |
1278 | int rxr_idx = 0, txr_idx = 0, v_idx = 0; | |
1279 | int err; | |
047e0030 | 1280 | |
5536d210 AD |
1281 | if (q_vectors >= (rxr_remaining + txr_remaining)) { |
1282 | for (; rxr_remaining; v_idx++) { | |
1283 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1284 | 0, 0, 1, rxr_idx); | |
047e0030 | 1285 | |
5536d210 AD |
1286 | if (err) |
1287 | goto err_out; | |
1288 | ||
1289 | /* update counts and index */ | |
1290 | rxr_remaining--; | |
1291 | rxr_idx++; | |
047e0030 | 1292 | } |
047e0030 | 1293 | } |
5536d210 AD |
1294 | |
1295 | for (; v_idx < q_vectors; v_idx++) { | |
1296 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); | |
1297 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); | |
1298 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1299 | tqpv, txr_idx, rqpv, rxr_idx); | |
1300 | ||
1301 | if (err) | |
1302 | goto err_out; | |
1303 | ||
1304 | /* update counts and index */ | |
1305 | rxr_remaining -= rqpv; | |
1306 | txr_remaining -= tqpv; | |
1307 | rxr_idx++; | |
1308 | txr_idx++; | |
1309 | } | |
1310 | ||
047e0030 | 1311 | return 0; |
5536d210 AD |
1312 | |
1313 | err_out: | |
1314 | adapter->num_tx_queues = 0; | |
1315 | adapter->num_rx_queues = 0; | |
1316 | adapter->num_q_vectors = 0; | |
1317 | ||
1318 | while (v_idx--) | |
1319 | igb_free_q_vector(adapter, v_idx); | |
1320 | ||
1321 | return -ENOMEM; | |
047e0030 AD |
1322 | } |
1323 | ||
1324 | /** | |
b980ac18 JK |
1325 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors |
1326 | * @adapter: board private structure to initialize | |
1327 | * @msix: boolean value of MSIX capability | |
047e0030 | 1328 | * |
b980ac18 | 1329 | * This function initializes the interrupts and allocates all of the queues. |
047e0030 | 1330 | **/ |
53c7d064 | 1331 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) |
047e0030 AD |
1332 | { |
1333 | struct pci_dev *pdev = adapter->pdev; | |
1334 | int err; | |
1335 | ||
53c7d064 | 1336 | igb_set_interrupt_capability(adapter, msix); |
047e0030 AD |
1337 | |
1338 | err = igb_alloc_q_vectors(adapter); | |
1339 | if (err) { | |
1340 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | |
1341 | goto err_alloc_q_vectors; | |
1342 | } | |
1343 | ||
5536d210 | 1344 | igb_cache_ring_register(adapter); |
047e0030 AD |
1345 | |
1346 | return 0; | |
5536d210 | 1347 | |
047e0030 AD |
1348 | err_alloc_q_vectors: |
1349 | igb_reset_interrupt_capability(adapter); | |
1350 | return err; | |
1351 | } | |
1352 | ||
9d5c8243 | 1353 | /** |
b980ac18 JK |
1354 | * igb_request_irq - initialize interrupts |
1355 | * @adapter: board private structure to initialize | |
9d5c8243 | 1356 | * |
b980ac18 JK |
1357 | * Attempts to configure interrupts using the best available |
1358 | * capabilities of the hardware and kernel. | |
9d5c8243 AK |
1359 | **/ |
1360 | static int igb_request_irq(struct igb_adapter *adapter) | |
1361 | { | |
1362 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 1363 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
1364 | int err = 0; |
1365 | ||
1366 | if (adapter->msix_entries) { | |
1367 | err = igb_request_msix(adapter); | |
844290e5 | 1368 | if (!err) |
9d5c8243 | 1369 | goto request_done; |
9d5c8243 | 1370 | /* fall back to MSI */ |
5536d210 AD |
1371 | igb_free_all_tx_resources(adapter); |
1372 | igb_free_all_rx_resources(adapter); | |
53c7d064 | 1373 | |
047e0030 | 1374 | igb_clear_interrupt_scheme(adapter); |
53c7d064 SA |
1375 | err = igb_init_interrupt_scheme(adapter, false); |
1376 | if (err) | |
047e0030 | 1377 | goto request_done; |
53c7d064 | 1378 | |
047e0030 AD |
1379 | igb_setup_all_tx_resources(adapter); |
1380 | igb_setup_all_rx_resources(adapter); | |
53c7d064 | 1381 | igb_configure(adapter); |
9d5c8243 | 1382 | } |
844290e5 | 1383 | |
c74d588e AD |
1384 | igb_assign_vector(adapter->q_vector[0], 0); |
1385 | ||
7dfc16fa | 1386 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
c74d588e | 1387 | err = request_irq(pdev->irq, igb_intr_msi, 0, |
047e0030 | 1388 | netdev->name, adapter); |
9d5c8243 AK |
1389 | if (!err) |
1390 | goto request_done; | |
047e0030 | 1391 | |
9d5c8243 AK |
1392 | /* fall back to legacy interrupts */ |
1393 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 1394 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1395 | } |
1396 | ||
c74d588e | 1397 | err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, |
047e0030 | 1398 | netdev->name, adapter); |
9d5c8243 | 1399 | |
6cb5e577 | 1400 | if (err) |
c74d588e | 1401 | dev_err(&pdev->dev, "Error %d getting interrupt\n", |
9d5c8243 | 1402 | err); |
9d5c8243 AK |
1403 | |
1404 | request_done: | |
1405 | return err; | |
1406 | } | |
1407 | ||
1408 | static void igb_free_irq(struct igb_adapter *adapter) | |
1409 | { | |
9d5c8243 AK |
1410 | if (adapter->msix_entries) { |
1411 | int vector = 0, i; | |
1412 | ||
047e0030 | 1413 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
9d5c8243 | 1414 | |
0d1ae7f4 | 1415 | for (i = 0; i < adapter->num_q_vectors; i++) |
047e0030 | 1416 | free_irq(adapter->msix_entries[vector++].vector, |
0d1ae7f4 | 1417 | adapter->q_vector[i]); |
047e0030 AD |
1418 | } else { |
1419 | free_irq(adapter->pdev->irq, adapter); | |
9d5c8243 | 1420 | } |
9d5c8243 AK |
1421 | } |
1422 | ||
1423 | /** | |
b980ac18 JK |
1424 | * igb_irq_disable - Mask off interrupt generation on the NIC |
1425 | * @adapter: board private structure | |
9d5c8243 AK |
1426 | **/ |
1427 | static void igb_irq_disable(struct igb_adapter *adapter) | |
1428 | { | |
1429 | struct e1000_hw *hw = &adapter->hw; | |
1430 | ||
b980ac18 | 1431 | /* we need to be careful when disabling interrupts. The VFs are also |
25568a53 AD |
1432 | * mapped into these registers and so clearing the bits can cause |
1433 | * issues on the VF drivers so we only need to clear what we set | |
1434 | */ | |
9d5c8243 | 1435 | if (adapter->msix_entries) { |
2dfd1212 AD |
1436 | u32 regval = rd32(E1000_EIAM); |
1437 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | |
1438 | wr32(E1000_EIMC, adapter->eims_enable_mask); | |
1439 | regval = rd32(E1000_EIAC); | |
1440 | wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); | |
9d5c8243 | 1441 | } |
844290e5 PW |
1442 | |
1443 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
1444 | wr32(E1000_IMC, ~0); |
1445 | wrfl(); | |
81a61859 ET |
1446 | if (adapter->msix_entries) { |
1447 | int i; | |
1448 | for (i = 0; i < adapter->num_q_vectors; i++) | |
1449 | synchronize_irq(adapter->msix_entries[i].vector); | |
1450 | } else { | |
1451 | synchronize_irq(adapter->pdev->irq); | |
1452 | } | |
9d5c8243 AK |
1453 | } |
1454 | ||
1455 | /** | |
b980ac18 JK |
1456 | * igb_irq_enable - Enable default interrupt generation settings |
1457 | * @adapter: board private structure | |
9d5c8243 AK |
1458 | **/ |
1459 | static void igb_irq_enable(struct igb_adapter *adapter) | |
1460 | { | |
1461 | struct e1000_hw *hw = &adapter->hw; | |
1462 | ||
1463 | if (adapter->msix_entries) { | |
06218a8d | 1464 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; |
2dfd1212 AD |
1465 | u32 regval = rd32(E1000_EIAC); |
1466 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | |
1467 | regval = rd32(E1000_EIAM); | |
1468 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | |
844290e5 | 1469 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
25568a53 | 1470 | if (adapter->vfs_allocated_count) { |
4ae196df | 1471 | wr32(E1000_MBVFIMR, 0xFF); |
25568a53 AD |
1472 | ims |= E1000_IMS_VMMB; |
1473 | } | |
1474 | wr32(E1000_IMS, ims); | |
844290e5 | 1475 | } else { |
55cac248 AD |
1476 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
1477 | E1000_IMS_DRSTA); | |
1478 | wr32(E1000_IAM, IMS_ENABLE_MASK | | |
1479 | E1000_IMS_DRSTA); | |
844290e5 | 1480 | } |
9d5c8243 AK |
1481 | } |
1482 | ||
1483 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
1484 | { | |
51466239 | 1485 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1486 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
1487 | u16 old_vid = adapter->mng_vlan_id; | |
51466239 AD |
1488 | |
1489 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
1490 | /* add VID to filter table */ | |
1491 | igb_vfta_set(hw, vid, true); | |
1492 | adapter->mng_vlan_id = vid; | |
1493 | } else { | |
1494 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1495 | } | |
1496 | ||
1497 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
1498 | (vid != old_vid) && | |
b2cb09b1 | 1499 | !test_bit(old_vid, adapter->active_vlans)) { |
51466239 AD |
1500 | /* remove VID from filter table */ |
1501 | igb_vfta_set(hw, old_vid, false); | |
9d5c8243 AK |
1502 | } |
1503 | } | |
1504 | ||
1505 | /** | |
b980ac18 JK |
1506 | * igb_release_hw_control - release control of the h/w to f/w |
1507 | * @adapter: address of board private structure | |
9d5c8243 | 1508 | * |
b980ac18 JK |
1509 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. |
1510 | * For ASF and Pass Through versions of f/w this means that the | |
1511 | * driver is no longer loaded. | |
9d5c8243 AK |
1512 | **/ |
1513 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
1514 | { | |
1515 | struct e1000_hw *hw = &adapter->hw; | |
1516 | u32 ctrl_ext; | |
1517 | ||
1518 | /* Let firmware take over control of h/w */ | |
1519 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1520 | wr32(E1000_CTRL_EXT, | |
1521 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
1522 | } | |
1523 | ||
9d5c8243 | 1524 | /** |
b980ac18 JK |
1525 | * igb_get_hw_control - get control of the h/w from f/w |
1526 | * @adapter: address of board private structure | |
9d5c8243 | 1527 | * |
b980ac18 JK |
1528 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. |
1529 | * For ASF and Pass Through versions of f/w this means that | |
1530 | * the driver is loaded. | |
9d5c8243 AK |
1531 | **/ |
1532 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
1533 | { | |
1534 | struct e1000_hw *hw = &adapter->hw; | |
1535 | u32 ctrl_ext; | |
1536 | ||
1537 | /* Let firmware know the driver has taken over */ | |
1538 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1539 | wr32(E1000_CTRL_EXT, | |
1540 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
1541 | } | |
1542 | ||
9d5c8243 | 1543 | /** |
b980ac18 JK |
1544 | * igb_configure - configure the hardware for RX and TX |
1545 | * @adapter: private board structure | |
9d5c8243 AK |
1546 | **/ |
1547 | static void igb_configure(struct igb_adapter *adapter) | |
1548 | { | |
1549 | struct net_device *netdev = adapter->netdev; | |
1550 | int i; | |
1551 | ||
1552 | igb_get_hw_control(adapter); | |
ff41f8dc | 1553 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
1554 | |
1555 | igb_restore_vlan(adapter); | |
9d5c8243 | 1556 | |
85b430b4 | 1557 | igb_setup_tctl(adapter); |
06cf2666 | 1558 | igb_setup_mrqc(adapter); |
9d5c8243 | 1559 | igb_setup_rctl(adapter); |
85b430b4 AD |
1560 | |
1561 | igb_configure_tx(adapter); | |
9d5c8243 | 1562 | igb_configure_rx(adapter); |
662d7205 AD |
1563 | |
1564 | igb_rx_fifo_flush_82575(&adapter->hw); | |
1565 | ||
c493ea45 | 1566 | /* call igb_desc_unused which always leaves |
9d5c8243 | 1567 | * at least 1 descriptor unused to make sure |
b980ac18 JK |
1568 | * next_to_use != next_to_clean |
1569 | */ | |
9d5c8243 | 1570 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3025a446 | 1571 | struct igb_ring *ring = adapter->rx_ring[i]; |
cd392f5c | 1572 | igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); |
9d5c8243 | 1573 | } |
9d5c8243 AK |
1574 | } |
1575 | ||
88a268c1 | 1576 | /** |
b980ac18 JK |
1577 | * igb_power_up_link - Power up the phy/serdes link |
1578 | * @adapter: address of board private structure | |
88a268c1 NN |
1579 | **/ |
1580 | void igb_power_up_link(struct igb_adapter *adapter) | |
1581 | { | |
76886596 AA |
1582 | igb_reset_phy(&adapter->hw); |
1583 | ||
88a268c1 NN |
1584 | if (adapter->hw.phy.media_type == e1000_media_type_copper) |
1585 | igb_power_up_phy_copper(&adapter->hw); | |
1586 | else | |
1587 | igb_power_up_serdes_link_82575(&adapter->hw); | |
1588 | } | |
1589 | ||
1590 | /** | |
b980ac18 JK |
1591 | * igb_power_down_link - Power down the phy/serdes link |
1592 | * @adapter: address of board private structure | |
88a268c1 NN |
1593 | */ |
1594 | static void igb_power_down_link(struct igb_adapter *adapter) | |
1595 | { | |
1596 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1597 | igb_power_down_phy_copper_82575(&adapter->hw); | |
1598 | else | |
1599 | igb_shutdown_serdes_link_82575(&adapter->hw); | |
1600 | } | |
9d5c8243 AK |
1601 | |
1602 | /** | |
b980ac18 JK |
1603 | * igb_up - Open the interface and prepare it to handle traffic |
1604 | * @adapter: board private structure | |
9d5c8243 | 1605 | **/ |
9d5c8243 AK |
1606 | int igb_up(struct igb_adapter *adapter) |
1607 | { | |
1608 | struct e1000_hw *hw = &adapter->hw; | |
1609 | int i; | |
1610 | ||
1611 | /* hardware has been reset, we need to reload some things */ | |
1612 | igb_configure(adapter); | |
1613 | ||
1614 | clear_bit(__IGB_DOWN, &adapter->state); | |
1615 | ||
0d1ae7f4 AD |
1616 | for (i = 0; i < adapter->num_q_vectors; i++) |
1617 | napi_enable(&(adapter->q_vector[i]->napi)); | |
1618 | ||
844290e5 | 1619 | if (adapter->msix_entries) |
9d5c8243 | 1620 | igb_configure_msix(adapter); |
feeb2721 AD |
1621 | else |
1622 | igb_assign_vector(adapter->q_vector[0], 0); | |
9d5c8243 AK |
1623 | |
1624 | /* Clear any pending interrupts. */ | |
1625 | rd32(E1000_ICR); | |
1626 | igb_irq_enable(adapter); | |
1627 | ||
d4960307 AD |
1628 | /* notify VFs that reset has been completed */ |
1629 | if (adapter->vfs_allocated_count) { | |
1630 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
1631 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
1632 | wr32(E1000_CTRL_EXT, reg_data); | |
1633 | } | |
1634 | ||
4cb9be7a JB |
1635 | netif_tx_start_all_queues(adapter->netdev); |
1636 | ||
25568a53 AD |
1637 | /* start the watchdog. */ |
1638 | hw->mac.get_link_status = 1; | |
1639 | schedule_work(&adapter->watchdog_task); | |
1640 | ||
9d5c8243 AK |
1641 | return 0; |
1642 | } | |
1643 | ||
1644 | void igb_down(struct igb_adapter *adapter) | |
1645 | { | |
9d5c8243 | 1646 | struct net_device *netdev = adapter->netdev; |
330a6d6a | 1647 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1648 | u32 tctl, rctl; |
1649 | int i; | |
1650 | ||
1651 | /* signal that we're down so the interrupt handler does not | |
b980ac18 JK |
1652 | * reschedule our watchdog timer |
1653 | */ | |
9d5c8243 AK |
1654 | set_bit(__IGB_DOWN, &adapter->state); |
1655 | ||
1656 | /* disable receives in the hardware */ | |
1657 | rctl = rd32(E1000_RCTL); | |
1658 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1659 | /* flush and sleep below */ | |
1660 | ||
fd2ea0a7 | 1661 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1662 | |
1663 | /* disable transmits in the hardware */ | |
1664 | tctl = rd32(E1000_TCTL); | |
1665 | tctl &= ~E1000_TCTL_EN; | |
1666 | wr32(E1000_TCTL, tctl); | |
1667 | /* flush both disables and wait for them to finish */ | |
1668 | wrfl(); | |
1669 | msleep(10); | |
1670 | ||
0d1ae7f4 AD |
1671 | for (i = 0; i < adapter->num_q_vectors; i++) |
1672 | napi_disable(&(adapter->q_vector[i]->napi)); | |
9d5c8243 | 1673 | |
9d5c8243 AK |
1674 | igb_irq_disable(adapter); |
1675 | ||
1676 | del_timer_sync(&adapter->watchdog_timer); | |
1677 | del_timer_sync(&adapter->phy_info_timer); | |
1678 | ||
9d5c8243 | 1679 | netif_carrier_off(netdev); |
04fe6358 AD |
1680 | |
1681 | /* record the stats before reset*/ | |
12dcd86b ED |
1682 | spin_lock(&adapter->stats64_lock); |
1683 | igb_update_stats(adapter, &adapter->stats64); | |
1684 | spin_unlock(&adapter->stats64_lock); | |
04fe6358 | 1685 | |
9d5c8243 AK |
1686 | adapter->link_speed = 0; |
1687 | adapter->link_duplex = 0; | |
1688 | ||
3023682e JK |
1689 | if (!pci_channel_offline(adapter->pdev)) |
1690 | igb_reset(adapter); | |
9d5c8243 AK |
1691 | igb_clean_all_tx_rings(adapter); |
1692 | igb_clean_all_rx_rings(adapter); | |
7e0e99ef AD |
1693 | #ifdef CONFIG_IGB_DCA |
1694 | ||
1695 | /* since we reset the hardware DCA settings were cleared */ | |
1696 | igb_setup_dca(adapter); | |
1697 | #endif | |
9d5c8243 AK |
1698 | } |
1699 | ||
1700 | void igb_reinit_locked(struct igb_adapter *adapter) | |
1701 | { | |
1702 | WARN_ON(in_interrupt()); | |
1703 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
1704 | msleep(1); | |
1705 | igb_down(adapter); | |
1706 | igb_up(adapter); | |
1707 | clear_bit(__IGB_RESETTING, &adapter->state); | |
1708 | } | |
1709 | ||
1710 | void igb_reset(struct igb_adapter *adapter) | |
1711 | { | |
090b1795 | 1712 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 1713 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 AD |
1714 | struct e1000_mac_info *mac = &hw->mac; |
1715 | struct e1000_fc_info *fc = &hw->fc; | |
d48507fe | 1716 | u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; |
9d5c8243 AK |
1717 | |
1718 | /* Repartition Pba for greater than 9k mtu | |
1719 | * To take effect CTRL.RST is required. | |
1720 | */ | |
fa4dfae0 | 1721 | switch (mac->type) { |
d2ba2ed8 | 1722 | case e1000_i350: |
ceb5f13b | 1723 | case e1000_i354: |
55cac248 AD |
1724 | case e1000_82580: |
1725 | pba = rd32(E1000_RXPBS); | |
1726 | pba = igb_rxpbs_adjust_82580(pba); | |
1727 | break; | |
fa4dfae0 | 1728 | case e1000_82576: |
d249be54 AD |
1729 | pba = rd32(E1000_RXPBS); |
1730 | pba &= E1000_RXPBS_SIZE_MASK_82576; | |
fa4dfae0 AD |
1731 | break; |
1732 | case e1000_82575: | |
f96a8a0b CW |
1733 | case e1000_i210: |
1734 | case e1000_i211: | |
fa4dfae0 AD |
1735 | default: |
1736 | pba = E1000_PBA_34K; | |
1737 | break; | |
2d064c06 | 1738 | } |
9d5c8243 | 1739 | |
2d064c06 AD |
1740 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1741 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1742 | /* adjust PBA for jumbo frames */ |
1743 | wr32(E1000_PBA, pba); | |
1744 | ||
1745 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1746 | * large enough to accommodate two full transmit packets, | |
1747 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1748 | * the Rx FIFO should be large enough to accommodate at least | |
1749 | * one full receive packet and is similarly rounded up and | |
b980ac18 JK |
1750 | * expressed in KB. |
1751 | */ | |
9d5c8243 AK |
1752 | pba = rd32(E1000_PBA); |
1753 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1754 | tx_space = pba >> 16; | |
1755 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1756 | pba &= 0xffff; | |
b980ac18 JK |
1757 | /* the Tx fifo also stores 16 bytes of information about the Tx |
1758 | * but don't include ethernet FCS because hardware appends it | |
1759 | */ | |
9d5c8243 | 1760 | min_tx_space = (adapter->max_frame_size + |
85e8d004 | 1761 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1762 | ETH_FCS_LEN) * 2; |
1763 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1764 | min_tx_space >>= 10; | |
1765 | /* software strips receive CRC, so leave room for it */ | |
1766 | min_rx_space = adapter->max_frame_size; | |
1767 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1768 | min_rx_space >>= 10; | |
1769 | ||
1770 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1771 | * and the min Tx FIFO size is less than the current Rx FIFO | |
b980ac18 JK |
1772 | * allocation, take space away from current Rx allocation |
1773 | */ | |
9d5c8243 AK |
1774 | if (tx_space < min_tx_space && |
1775 | ((min_tx_space - tx_space) < pba)) { | |
1776 | pba = pba - (min_tx_space - tx_space); | |
1777 | ||
b980ac18 JK |
1778 | /* if short on Rx space, Rx wins and must trump Tx |
1779 | * adjustment | |
1780 | */ | |
9d5c8243 AK |
1781 | if (pba < min_rx_space) |
1782 | pba = min_rx_space; | |
1783 | } | |
2d064c06 | 1784 | wr32(E1000_PBA, pba); |
9d5c8243 | 1785 | } |
9d5c8243 AK |
1786 | |
1787 | /* flow control settings */ | |
1788 | /* The high water mark must be low enough to fit one full frame | |
1789 | * (or the size used for early receive) above it in the Rx FIFO. | |
1790 | * Set it to the lower of: | |
1791 | * - 90% of the Rx FIFO size, or | |
b980ac18 JK |
1792 | * - the full Rx FIFO size minus one full frame |
1793 | */ | |
9d5c8243 | 1794 | hwm = min(((pba << 10) * 9 / 10), |
2d064c06 | 1795 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1796 | |
d48507fe | 1797 | fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ |
d405ea3e | 1798 | fc->low_water = fc->high_water - 16; |
9d5c8243 AK |
1799 | fc->pause_time = 0xFFFF; |
1800 | fc->send_xon = 1; | |
0cce119a | 1801 | fc->current_mode = fc->requested_mode; |
9d5c8243 | 1802 | |
4ae196df AD |
1803 | /* disable receive for all VFs and wait one second */ |
1804 | if (adapter->vfs_allocated_count) { | |
1805 | int i; | |
1806 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
8fa7e0f7 | 1807 | adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; |
4ae196df AD |
1808 | |
1809 | /* ping all the active vfs to let them know we are going down */ | |
f2ca0dbe | 1810 | igb_ping_all_vfs(adapter); |
4ae196df AD |
1811 | |
1812 | /* disable transmits and receives */ | |
1813 | wr32(E1000_VFRE, 0); | |
1814 | wr32(E1000_VFTE, 0); | |
1815 | } | |
1816 | ||
9d5c8243 | 1817 | /* Allow time for pending master requests to run */ |
330a6d6a | 1818 | hw->mac.ops.reset_hw(hw); |
9d5c8243 AK |
1819 | wr32(E1000_WUC, 0); |
1820 | ||
330a6d6a | 1821 | if (hw->mac.ops.init_hw(hw)) |
090b1795 | 1822 | dev_err(&pdev->dev, "Hardware Error\n"); |
831ec0b4 | 1823 | |
b980ac18 | 1824 | /* Flow control settings reset on hardware reset, so guarantee flow |
a27416bb MV |
1825 | * control is off when forcing speed. |
1826 | */ | |
1827 | if (!hw->mac.autoneg) | |
1828 | igb_force_mac_fc(hw); | |
1829 | ||
b6e0c419 | 1830 | igb_init_dmac(adapter, pba); |
e428893b CW |
1831 | #ifdef CONFIG_IGB_HWMON |
1832 | /* Re-initialize the thermal sensor on i350 devices. */ | |
1833 | if (!test_bit(__IGB_DOWN, &adapter->state)) { | |
1834 | if (mac->type == e1000_i350 && hw->bus.func == 0) { | |
1835 | /* If present, re-initialize the external thermal sensor | |
1836 | * interface. | |
1837 | */ | |
1838 | if (adapter->ets) | |
1839 | mac->ops.init_thermal_sensor_thresh(hw); | |
1840 | } | |
1841 | } | |
1842 | #endif | |
88a268c1 NN |
1843 | if (!netif_running(adapter->netdev)) |
1844 | igb_power_down_link(adapter); | |
1845 | ||
9d5c8243 AK |
1846 | igb_update_mng_vlan(adapter); |
1847 | ||
1848 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1849 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1850 | ||
1f6e8178 MV |
1851 | /* Re-enable PTP, where applicable. */ |
1852 | igb_ptp_reset(adapter); | |
1f6e8178 | 1853 | |
330a6d6a | 1854 | igb_get_phy_info(hw); |
9d5c8243 AK |
1855 | } |
1856 | ||
c8f44aff MM |
1857 | static netdev_features_t igb_fix_features(struct net_device *netdev, |
1858 | netdev_features_t features) | |
b2cb09b1 | 1859 | { |
b980ac18 JK |
1860 | /* Since there is no support for separate Rx/Tx vlan accel |
1861 | * enable/disable make sure Tx flag is always in same state as Rx. | |
b2cb09b1 | 1862 | */ |
f646968f PM |
1863 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
1864 | features |= NETIF_F_HW_VLAN_CTAG_TX; | |
b2cb09b1 | 1865 | else |
f646968f | 1866 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
b2cb09b1 JP |
1867 | |
1868 | return features; | |
1869 | } | |
1870 | ||
c8f44aff MM |
1871 | static int igb_set_features(struct net_device *netdev, |
1872 | netdev_features_t features) | |
ac52caa3 | 1873 | { |
c8f44aff | 1874 | netdev_features_t changed = netdev->features ^ features; |
89eaefb6 | 1875 | struct igb_adapter *adapter = netdev_priv(netdev); |
ac52caa3 | 1876 | |
f646968f | 1877 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
b2cb09b1 JP |
1878 | igb_vlan_mode(netdev, features); |
1879 | ||
89eaefb6 BG |
1880 | if (!(changed & NETIF_F_RXALL)) |
1881 | return 0; | |
1882 | ||
1883 | netdev->features = features; | |
1884 | ||
1885 | if (netif_running(netdev)) | |
1886 | igb_reinit_locked(adapter); | |
1887 | else | |
1888 | igb_reset(adapter); | |
1889 | ||
ac52caa3 MM |
1890 | return 0; |
1891 | } | |
1892 | ||
2e5c6922 | 1893 | static const struct net_device_ops igb_netdev_ops = { |
559e9c49 | 1894 | .ndo_open = igb_open, |
2e5c6922 | 1895 | .ndo_stop = igb_close, |
cd392f5c | 1896 | .ndo_start_xmit = igb_xmit_frame, |
12dcd86b | 1897 | .ndo_get_stats64 = igb_get_stats64, |
ff41f8dc | 1898 | .ndo_set_rx_mode = igb_set_rx_mode, |
2e5c6922 SH |
1899 | .ndo_set_mac_address = igb_set_mac, |
1900 | .ndo_change_mtu = igb_change_mtu, | |
1901 | .ndo_do_ioctl = igb_ioctl, | |
1902 | .ndo_tx_timeout = igb_tx_timeout, | |
1903 | .ndo_validate_addr = eth_validate_addr, | |
2e5c6922 SH |
1904 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, |
1905 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
8151d294 WM |
1906 | .ndo_set_vf_mac = igb_ndo_set_vf_mac, |
1907 | .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, | |
1908 | .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, | |
70ea4783 | 1909 | .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, |
8151d294 | 1910 | .ndo_get_vf_config = igb_ndo_get_vf_config, |
2e5c6922 SH |
1911 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1912 | .ndo_poll_controller = igb_netpoll, | |
1913 | #endif | |
b2cb09b1 JP |
1914 | .ndo_fix_features = igb_fix_features, |
1915 | .ndo_set_features = igb_set_features, | |
2e5c6922 SH |
1916 | }; |
1917 | ||
d67974f0 CW |
1918 | /** |
1919 | * igb_set_fw_version - Configure version string for ethtool | |
1920 | * @adapter: adapter struct | |
d67974f0 CW |
1921 | **/ |
1922 | void igb_set_fw_version(struct igb_adapter *adapter) | |
1923 | { | |
1924 | struct e1000_hw *hw = &adapter->hw; | |
0b1a6f2e CW |
1925 | struct e1000_fw_version fw; |
1926 | ||
1927 | igb_get_fw_version(hw, &fw); | |
1928 | ||
1929 | switch (hw->mac.type) { | |
1930 | case e1000_i211: | |
d67974f0 | 1931 | snprintf(adapter->fw_version, sizeof(adapter->fw_version), |
0b1a6f2e CW |
1932 | "%2d.%2d-%d", |
1933 | fw.invm_major, fw.invm_minor, fw.invm_img_type); | |
1934 | break; | |
1935 | ||
1936 | default: | |
1937 | /* if option is rom valid, display its version too */ | |
1938 | if (fw.or_valid) { | |
1939 | snprintf(adapter->fw_version, | |
1940 | sizeof(adapter->fw_version), | |
1941 | "%d.%d, 0x%08x, %d.%d.%d", | |
1942 | fw.eep_major, fw.eep_minor, fw.etrack_id, | |
1943 | fw.or_major, fw.or_build, fw.or_patch); | |
1944 | /* no option rom */ | |
1945 | } else { | |
1946 | snprintf(adapter->fw_version, | |
1947 | sizeof(adapter->fw_version), | |
1948 | "%d.%d, 0x%08x", | |
1949 | fw.eep_major, fw.eep_minor, fw.etrack_id); | |
1950 | } | |
1951 | break; | |
d67974f0 | 1952 | } |
d67974f0 CW |
1953 | return; |
1954 | } | |
1955 | ||
b980ac18 JK |
1956 | /** |
1957 | * igb_init_i2c - Init I2C interface | |
441fc6fd | 1958 | * @adapter: pointer to adapter structure |
b980ac18 | 1959 | **/ |
441fc6fd CW |
1960 | static s32 igb_init_i2c(struct igb_adapter *adapter) |
1961 | { | |
1962 | s32 status = E1000_SUCCESS; | |
1963 | ||
1964 | /* I2C interface supported on i350 devices */ | |
1965 | if (adapter->hw.mac.type != e1000_i350) | |
1966 | return E1000_SUCCESS; | |
1967 | ||
1968 | /* Initialize the i2c bus which is controlled by the registers. | |
1969 | * This bus will use the i2c_algo_bit structue that implements | |
1970 | * the protocol through toggling of the 4 bits in the register. | |
1971 | */ | |
1972 | adapter->i2c_adap.owner = THIS_MODULE; | |
1973 | adapter->i2c_algo = igb_i2c_algo; | |
1974 | adapter->i2c_algo.data = adapter; | |
1975 | adapter->i2c_adap.algo_data = &adapter->i2c_algo; | |
1976 | adapter->i2c_adap.dev.parent = &adapter->pdev->dev; | |
1977 | strlcpy(adapter->i2c_adap.name, "igb BB", | |
1978 | sizeof(adapter->i2c_adap.name)); | |
1979 | status = i2c_bit_add_bus(&adapter->i2c_adap); | |
1980 | return status; | |
1981 | } | |
1982 | ||
9d5c8243 | 1983 | /** |
b980ac18 JK |
1984 | * igb_probe - Device Initialization Routine |
1985 | * @pdev: PCI device information struct | |
1986 | * @ent: entry in igb_pci_tbl | |
9d5c8243 | 1987 | * |
b980ac18 | 1988 | * Returns 0 on success, negative on failure |
9d5c8243 | 1989 | * |
b980ac18 JK |
1990 | * igb_probe initializes an adapter identified by a pci_dev structure. |
1991 | * The OS initialization, configuring of the adapter private structure, | |
1992 | * and a hardware reset occur. | |
9d5c8243 | 1993 | **/ |
1dd06ae8 | 1994 | static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
9d5c8243 AK |
1995 | { |
1996 | struct net_device *netdev; | |
1997 | struct igb_adapter *adapter; | |
1998 | struct e1000_hw *hw; | |
4337e993 | 1999 | u16 eeprom_data = 0; |
9835fd73 | 2000 | s32 ret_val; |
4337e993 | 2001 | static int global_quad_port_a; /* global quad port a indication */ |
9d5c8243 AK |
2002 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
2003 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 2004 | int err, pci_using_dac; |
9835fd73 | 2005 | u8 part_str[E1000_PBANUM_LENGTH]; |
9d5c8243 | 2006 | |
bded64a7 AG |
2007 | /* Catch broken hardware that put the wrong VF device ID in |
2008 | * the PCIe SR-IOV capability. | |
2009 | */ | |
2010 | if (pdev->is_virtfn) { | |
2011 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
f96a8a0b | 2012 | pci_name(pdev), pdev->vendor, pdev->device); |
bded64a7 AG |
2013 | return -EINVAL; |
2014 | } | |
2015 | ||
aed5dec3 | 2016 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
2017 | if (err) |
2018 | return err; | |
2019 | ||
2020 | pci_using_dac = 0; | |
59d71989 | 2021 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 | 2022 | if (!err) { |
59d71989 | 2023 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 AK |
2024 | if (!err) |
2025 | pci_using_dac = 1; | |
2026 | } else { | |
59d71989 | 2027 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 | 2028 | if (err) { |
b980ac18 JK |
2029 | err = dma_set_coherent_mask(&pdev->dev, |
2030 | DMA_BIT_MASK(32)); | |
9d5c8243 | 2031 | if (err) { |
b980ac18 JK |
2032 | dev_err(&pdev->dev, |
2033 | "No usable DMA configuration, aborting\n"); | |
9d5c8243 AK |
2034 | goto err_dma; |
2035 | } | |
2036 | } | |
2037 | } | |
2038 | ||
aed5dec3 | 2039 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
b980ac18 JK |
2040 | IORESOURCE_MEM), |
2041 | igb_driver_name); | |
9d5c8243 AK |
2042 | if (err) |
2043 | goto err_pci_reg; | |
2044 | ||
19d5afd4 | 2045 | pci_enable_pcie_error_reporting(pdev); |
40a914fa | 2046 | |
9d5c8243 | 2047 | pci_set_master(pdev); |
c682fc23 | 2048 | pci_save_state(pdev); |
9d5c8243 AK |
2049 | |
2050 | err = -ENOMEM; | |
1bfaf07b | 2051 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1cc3bd87 | 2052 | IGB_MAX_TX_QUEUES); |
9d5c8243 AK |
2053 | if (!netdev) |
2054 | goto err_alloc_etherdev; | |
2055 | ||
2056 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
2057 | ||
2058 | pci_set_drvdata(pdev, netdev); | |
2059 | adapter = netdev_priv(netdev); | |
2060 | adapter->netdev = netdev; | |
2061 | adapter->pdev = pdev; | |
2062 | hw = &adapter->hw; | |
2063 | hw->back = adapter; | |
b3f4d599 | 2064 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9d5c8243 AK |
2065 | |
2066 | mmio_start = pci_resource_start(pdev, 0); | |
2067 | mmio_len = pci_resource_len(pdev, 0); | |
2068 | ||
2069 | err = -EIO; | |
28b0759c AD |
2070 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
2071 | if (!hw->hw_addr) | |
9d5c8243 AK |
2072 | goto err_ioremap; |
2073 | ||
2e5c6922 | 2074 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 2075 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 2076 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
2077 | |
2078 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
2079 | ||
2080 | netdev->mem_start = mmio_start; | |
2081 | netdev->mem_end = mmio_start + mmio_len; | |
2082 | ||
9d5c8243 AK |
2083 | /* PCI config space info */ |
2084 | hw->vendor_id = pdev->vendor; | |
2085 | hw->device_id = pdev->device; | |
2086 | hw->revision_id = pdev->revision; | |
2087 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
2088 | hw->subsystem_device_id = pdev->subsystem_device; | |
2089 | ||
9d5c8243 AK |
2090 | /* Copy the default MAC, PHY and NVM function pointers */ |
2091 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
2092 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
2093 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
2094 | /* Initialize skew-specific constants */ | |
2095 | err = ei->get_invariants(hw); | |
2096 | if (err) | |
450c87c8 | 2097 | goto err_sw_init; |
9d5c8243 | 2098 | |
450c87c8 | 2099 | /* setup the private structure */ |
9d5c8243 AK |
2100 | err = igb_sw_init(adapter); |
2101 | if (err) | |
2102 | goto err_sw_init; | |
2103 | ||
2104 | igb_get_bus_info_pcie(hw); | |
2105 | ||
2106 | hw->phy.autoneg_wait_to_complete = false; | |
9d5c8243 AK |
2107 | |
2108 | /* Copper options */ | |
2109 | if (hw->phy.media_type == e1000_media_type_copper) { | |
2110 | hw->phy.mdix = AUTO_ALL_MODES; | |
2111 | hw->phy.disable_polarity_correction = false; | |
2112 | hw->phy.ms_type = e1000_ms_hw_default; | |
2113 | } | |
2114 | ||
2115 | if (igb_check_reset_block(hw)) | |
2116 | dev_info(&pdev->dev, | |
2117 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
2118 | ||
b980ac18 | 2119 | /* features is initialized to 0 in allocation, it might have bits |
077887c3 AD |
2120 | * set by igb_sw_init so we should use an or instead of an |
2121 | * assignment. | |
2122 | */ | |
2123 | netdev->features |= NETIF_F_SG | | |
2124 | NETIF_F_IP_CSUM | | |
2125 | NETIF_F_IPV6_CSUM | | |
2126 | NETIF_F_TSO | | |
2127 | NETIF_F_TSO6 | | |
2128 | NETIF_F_RXHASH | | |
2129 | NETIF_F_RXCSUM | | |
f646968f PM |
2130 | NETIF_F_HW_VLAN_CTAG_RX | |
2131 | NETIF_F_HW_VLAN_CTAG_TX; | |
077887c3 AD |
2132 | |
2133 | /* copy netdev features into list of user selectable features */ | |
2134 | netdev->hw_features |= netdev->features; | |
89eaefb6 | 2135 | netdev->hw_features |= NETIF_F_RXALL; |
077887c3 AD |
2136 | |
2137 | /* set this bit last since it cannot be part of hw_features */ | |
f646968f | 2138 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
077887c3 AD |
2139 | |
2140 | netdev->vlan_features |= NETIF_F_TSO | | |
2141 | NETIF_F_TSO6 | | |
2142 | NETIF_F_IP_CSUM | | |
2143 | NETIF_F_IPV6_CSUM | | |
2144 | NETIF_F_SG; | |
48f29ffc | 2145 | |
6b8f0922 BG |
2146 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
2147 | ||
7b872a55 | 2148 | if (pci_using_dac) { |
9d5c8243 | 2149 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
2150 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
2151 | } | |
9d5c8243 | 2152 | |
ac52caa3 MM |
2153 | if (hw->mac.type >= e1000_82576) { |
2154 | netdev->hw_features |= NETIF_F_SCTP_CSUM; | |
b9473560 | 2155 | netdev->features |= NETIF_F_SCTP_CSUM; |
ac52caa3 | 2156 | } |
b9473560 | 2157 | |
01789349 JP |
2158 | netdev->priv_flags |= IFF_UNICAST_FLT; |
2159 | ||
330a6d6a | 2160 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
9d5c8243 AK |
2161 | |
2162 | /* before reading the NVM, reset the controller to put the device in a | |
b980ac18 JK |
2163 | * known good starting state |
2164 | */ | |
9d5c8243 AK |
2165 | hw->mac.ops.reset_hw(hw); |
2166 | ||
b980ac18 | 2167 | /* make sure the NVM is good , i211 parts have special NVM that |
f96a8a0b CW |
2168 | * doesn't contain a checksum |
2169 | */ | |
2170 | if (hw->mac.type != e1000_i211) { | |
2171 | if (hw->nvm.ops.validate(hw) < 0) { | |
2172 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
2173 | err = -EIO; | |
2174 | goto err_eeprom; | |
2175 | } | |
9d5c8243 AK |
2176 | } |
2177 | ||
2178 | /* copy the MAC address out of the NVM */ | |
2179 | if (hw->mac.ops.read_mac_addr(hw)) | |
2180 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
2181 | ||
2182 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
9d5c8243 | 2183 | |
aaeb6cdf | 2184 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
9d5c8243 AK |
2185 | dev_err(&pdev->dev, "Invalid MAC Address\n"); |
2186 | err = -EIO; | |
2187 | goto err_eeprom; | |
2188 | } | |
2189 | ||
d67974f0 CW |
2190 | /* get firmware version for ethtool -i */ |
2191 | igb_set_fw_version(adapter); | |
2192 | ||
c061b18d | 2193 | setup_timer(&adapter->watchdog_timer, igb_watchdog, |
b980ac18 | 2194 | (unsigned long) adapter); |
c061b18d | 2195 | setup_timer(&adapter->phy_info_timer, igb_update_phy_info, |
b980ac18 | 2196 | (unsigned long) adapter); |
9d5c8243 AK |
2197 | |
2198 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
2199 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
2200 | ||
450c87c8 | 2201 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
2202 | adapter->fc_autoneg = true; |
2203 | hw->mac.autoneg = true; | |
2204 | hw->phy.autoneg_advertised = 0x2f; | |
2205 | ||
0cce119a AD |
2206 | hw->fc.requested_mode = e1000_fc_default; |
2207 | hw->fc.current_mode = e1000_fc_default; | |
9d5c8243 | 2208 | |
9d5c8243 AK |
2209 | igb_validate_mdi_setting(hw); |
2210 | ||
63d4a8f9 | 2211 | /* By default, support wake on port A */ |
a2cf8b6c | 2212 | if (hw->bus.func == 0) |
63d4a8f9 MV |
2213 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; |
2214 | ||
2215 | /* Check the NVM for wake support on non-port A ports */ | |
2216 | if (hw->mac.type >= e1000_82580) | |
55cac248 | 2217 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + |
b980ac18 JK |
2218 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, |
2219 | &eeprom_data); | |
a2cf8b6c AD |
2220 | else if (hw->bus.func == 1) |
2221 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 | 2222 | |
63d4a8f9 MV |
2223 | if (eeprom_data & IGB_EEPROM_APME) |
2224 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; | |
9d5c8243 AK |
2225 | |
2226 | /* now that we have the eeprom settings, apply the special cases where | |
2227 | * the eeprom may be wrong or the board simply won't support wake on | |
b980ac18 JK |
2228 | * lan on a particular port |
2229 | */ | |
9d5c8243 AK |
2230 | switch (pdev->device) { |
2231 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
63d4a8f9 | 2232 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
9d5c8243 AK |
2233 | break; |
2234 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
2235 | case E1000_DEV_ID_82576_FIBER: |
2236 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 | 2237 | /* Wake events only supported on port A for dual fiber |
b980ac18 JK |
2238 | * regardless of eeprom setting |
2239 | */ | |
9d5c8243 | 2240 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) |
63d4a8f9 | 2241 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
9d5c8243 | 2242 | break; |
c8ea5ea9 | 2243 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 2244 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
2245 | /* if quad port adapter, disable WoL on all but port A */ |
2246 | if (global_quad_port_a != 0) | |
63d4a8f9 | 2247 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
c8ea5ea9 AD |
2248 | else |
2249 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
2250 | /* Reset for multiple quad port adapters */ | |
2251 | if (++global_quad_port_a == 4) | |
2252 | global_quad_port_a = 0; | |
2253 | break; | |
63d4a8f9 MV |
2254 | default: |
2255 | /* If the device can't wake, don't set software support */ | |
2256 | if (!device_can_wakeup(&adapter->pdev->dev)) | |
2257 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; | |
9d5c8243 AK |
2258 | } |
2259 | ||
2260 | /* initialize the wol settings based on the eeprom settings */ | |
63d4a8f9 MV |
2261 | if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) |
2262 | adapter->wol |= E1000_WUFC_MAG; | |
2263 | ||
2264 | /* Some vendors want WoL disabled by default, but still supported */ | |
2265 | if ((hw->mac.type == e1000_i350) && | |
2266 | (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { | |
2267 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; | |
2268 | adapter->wol = 0; | |
2269 | } | |
2270 | ||
2271 | device_set_wakeup_enable(&adapter->pdev->dev, | |
2272 | adapter->flags & IGB_FLAG_WOL_SUPPORTED); | |
9d5c8243 AK |
2273 | |
2274 | /* reset the hardware with the new settings */ | |
2275 | igb_reset(adapter); | |
2276 | ||
441fc6fd CW |
2277 | /* Init the I2C interface */ |
2278 | err = igb_init_i2c(adapter); | |
2279 | if (err) { | |
2280 | dev_err(&pdev->dev, "failed to init i2c interface\n"); | |
2281 | goto err_eeprom; | |
2282 | } | |
2283 | ||
9d5c8243 AK |
2284 | /* let the f/w know that the h/w is now under the control of the |
2285 | * driver. */ | |
2286 | igb_get_hw_control(adapter); | |
2287 | ||
9d5c8243 AK |
2288 | strcpy(netdev->name, "eth%d"); |
2289 | err = register_netdev(netdev); | |
2290 | if (err) | |
2291 | goto err_register; | |
2292 | ||
b168dfc5 JB |
2293 | /* carrier off reporting is important to ethtool even BEFORE open */ |
2294 | netif_carrier_off(netdev); | |
2295 | ||
421e02f0 | 2296 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 2297 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 2298 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 | 2299 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
2300 | igb_setup_dca(adapter); |
2301 | } | |
fe4506b6 | 2302 | |
38c845c7 | 2303 | #endif |
e428893b CW |
2304 | #ifdef CONFIG_IGB_HWMON |
2305 | /* Initialize the thermal sensor on i350 devices. */ | |
2306 | if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { | |
2307 | u16 ets_word; | |
3c89f6d0 | 2308 | |
b980ac18 | 2309 | /* Read the NVM to determine if this i350 device supports an |
e428893b CW |
2310 | * external thermal sensor. |
2311 | */ | |
2312 | hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); | |
2313 | if (ets_word != 0x0000 && ets_word != 0xFFFF) | |
2314 | adapter->ets = true; | |
2315 | else | |
2316 | adapter->ets = false; | |
2317 | if (igb_sysfs_init(adapter)) | |
2318 | dev_err(&pdev->dev, | |
2319 | "failed to allocate sysfs resources\n"); | |
2320 | } else { | |
2321 | adapter->ets = false; | |
2322 | } | |
2323 | #endif | |
673b8b70 | 2324 | /* do hw tstamp init after resetting */ |
7ebae817 | 2325 | igb_ptp_init(adapter); |
673b8b70 | 2326 | |
9d5c8243 | 2327 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
ceb5f13b CW |
2328 | /* print bus type/speed/width info, not applicable to i354 */ |
2329 | if (hw->mac.type != e1000_i354) { | |
2330 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", | |
2331 | netdev->name, | |
2332 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : | |
2333 | (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : | |
2334 | "unknown"), | |
2335 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? | |
2336 | "Width x4" : | |
2337 | (hw->bus.width == e1000_bus_width_pcie_x2) ? | |
2338 | "Width x2" : | |
2339 | (hw->bus.width == e1000_bus_width_pcie_x1) ? | |
2340 | "Width x1" : "unknown"), netdev->dev_addr); | |
2341 | } | |
9d5c8243 | 2342 | |
9835fd73 CW |
2343 | ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); |
2344 | if (ret_val) | |
2345 | strcpy(part_str, "Unknown"); | |
2346 | dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); | |
9d5c8243 AK |
2347 | dev_info(&pdev->dev, |
2348 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
2349 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 2350 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 | 2351 | adapter->num_rx_queues, adapter->num_tx_queues); |
09b068d4 CW |
2352 | switch (hw->mac.type) { |
2353 | case e1000_i350: | |
f96a8a0b CW |
2354 | case e1000_i210: |
2355 | case e1000_i211: | |
09b068d4 CW |
2356 | igb_set_eee_i350(hw); |
2357 | break; | |
ceb5f13b CW |
2358 | case e1000_i354: |
2359 | if (hw->phy.media_type == e1000_media_type_copper) { | |
2360 | if ((rd32(E1000_CTRL_EXT) & | |
2361 | E1000_CTRL_EXT_LINK_MODE_SGMII)) | |
2362 | igb_set_eee_i354(hw); | |
2363 | } | |
2364 | break; | |
09b068d4 CW |
2365 | default: |
2366 | break; | |
2367 | } | |
749ab2cd YZ |
2368 | |
2369 | pm_runtime_put_noidle(&pdev->dev); | |
9d5c8243 AK |
2370 | return 0; |
2371 | ||
2372 | err_register: | |
2373 | igb_release_hw_control(adapter); | |
441fc6fd | 2374 | memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); |
9d5c8243 AK |
2375 | err_eeprom: |
2376 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 2377 | igb_reset_phy(hw); |
9d5c8243 AK |
2378 | |
2379 | if (hw->flash_address) | |
2380 | iounmap(hw->flash_address); | |
9d5c8243 | 2381 | err_sw_init: |
047e0030 | 2382 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
2383 | iounmap(hw->hw_addr); |
2384 | err_ioremap: | |
2385 | free_netdev(netdev); | |
2386 | err_alloc_etherdev: | |
559e9c49 | 2387 | pci_release_selected_regions(pdev, |
b980ac18 | 2388 | pci_select_bars(pdev, IORESOURCE_MEM)); |
9d5c8243 AK |
2389 | err_pci_reg: |
2390 | err_dma: | |
2391 | pci_disable_device(pdev); | |
2392 | return err; | |
2393 | } | |
2394 | ||
fa44f2f1 GR |
2395 | #ifdef CONFIG_PCI_IOV |
2396 | static int igb_disable_sriov(struct pci_dev *pdev) | |
2397 | { | |
2398 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2399 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2400 | struct e1000_hw *hw = &adapter->hw; | |
2401 | ||
2402 | /* reclaim resources allocated to VFs */ | |
2403 | if (adapter->vf_data) { | |
2404 | /* disable iov and allow time for transactions to clear */ | |
2405 | if (igb_vfs_are_assigned(adapter)) { | |
2406 | dev_warn(&pdev->dev, | |
2407 | "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); | |
2408 | return -EPERM; | |
2409 | } else { | |
2410 | pci_disable_sriov(pdev); | |
2411 | msleep(500); | |
2412 | } | |
2413 | ||
2414 | kfree(adapter->vf_data); | |
2415 | adapter->vf_data = NULL; | |
2416 | adapter->vfs_allocated_count = 0; | |
2417 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
2418 | wrfl(); | |
2419 | msleep(100); | |
2420 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
2421 | ||
2422 | /* Re-enable DMA Coalescing flag since IOV is turned off */ | |
2423 | adapter->flags |= IGB_FLAG_DMAC; | |
2424 | } | |
2425 | ||
2426 | return 0; | |
2427 | } | |
2428 | ||
2429 | static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) | |
2430 | { | |
2431 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2432 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2433 | int old_vfs = pci_num_vf(pdev); | |
2434 | int err = 0; | |
2435 | int i; | |
2436 | ||
2437 | if (!num_vfs) | |
2438 | goto out; | |
2439 | else if (old_vfs && old_vfs == num_vfs) | |
2440 | goto out; | |
2441 | else if (old_vfs && old_vfs != num_vfs) | |
2442 | err = igb_disable_sriov(pdev); | |
2443 | ||
2444 | if (err) | |
2445 | goto out; | |
2446 | ||
2447 | if (num_vfs > 7) { | |
2448 | err = -EPERM; | |
2449 | goto out; | |
2450 | } | |
2451 | ||
2452 | adapter->vfs_allocated_count = num_vfs; | |
2453 | ||
2454 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | |
2455 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
2456 | ||
2457 | /* if allocation failed then we do not support SR-IOV */ | |
2458 | if (!adapter->vf_data) { | |
2459 | adapter->vfs_allocated_count = 0; | |
2460 | dev_err(&pdev->dev, | |
2461 | "Unable to allocate memory for VF Data Storage\n"); | |
2462 | err = -ENOMEM; | |
2463 | goto out; | |
2464 | } | |
2465 | ||
2466 | err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); | |
2467 | if (err) | |
2468 | goto err_out; | |
2469 | ||
2470 | dev_info(&pdev->dev, "%d VFs allocated\n", | |
2471 | adapter->vfs_allocated_count); | |
2472 | for (i = 0; i < adapter->vfs_allocated_count; i++) | |
2473 | igb_vf_configure(adapter, i); | |
2474 | ||
2475 | /* DMA Coalescing is not supported in IOV mode. */ | |
2476 | adapter->flags &= ~IGB_FLAG_DMAC; | |
2477 | goto out; | |
2478 | ||
2479 | err_out: | |
2480 | kfree(adapter->vf_data); | |
2481 | adapter->vf_data = NULL; | |
2482 | adapter->vfs_allocated_count = 0; | |
2483 | out: | |
2484 | return err; | |
2485 | } | |
2486 | ||
2487 | #endif | |
b980ac18 | 2488 | /** |
441fc6fd CW |
2489 | * igb_remove_i2c - Cleanup I2C interface |
2490 | * @adapter: pointer to adapter structure | |
b980ac18 | 2491 | **/ |
441fc6fd CW |
2492 | static void igb_remove_i2c(struct igb_adapter *adapter) |
2493 | { | |
441fc6fd CW |
2494 | /* free the adapter bus structure */ |
2495 | i2c_del_adapter(&adapter->i2c_adap); | |
2496 | } | |
2497 | ||
9d5c8243 | 2498 | /** |
b980ac18 JK |
2499 | * igb_remove - Device Removal Routine |
2500 | * @pdev: PCI device information struct | |
9d5c8243 | 2501 | * |
b980ac18 JK |
2502 | * igb_remove is called by the PCI subsystem to alert the driver |
2503 | * that it should release a PCI device. The could be caused by a | |
2504 | * Hot-Plug event, or because the driver is going to be removed from | |
2505 | * memory. | |
9d5c8243 | 2506 | **/ |
9f9a12f8 | 2507 | static void igb_remove(struct pci_dev *pdev) |
9d5c8243 AK |
2508 | { |
2509 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2510 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 2511 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 2512 | |
749ab2cd | 2513 | pm_runtime_get_noresume(&pdev->dev); |
e428893b CW |
2514 | #ifdef CONFIG_IGB_HWMON |
2515 | igb_sysfs_exit(adapter); | |
2516 | #endif | |
441fc6fd | 2517 | igb_remove_i2c(adapter); |
a79f4f88 | 2518 | igb_ptp_stop(adapter); |
b980ac18 | 2519 | /* The watchdog timer may be rescheduled, so explicitly |
760141a5 TH |
2520 | * disable watchdog from being rescheduled. |
2521 | */ | |
9d5c8243 AK |
2522 | set_bit(__IGB_DOWN, &adapter->state); |
2523 | del_timer_sync(&adapter->watchdog_timer); | |
2524 | del_timer_sync(&adapter->phy_info_timer); | |
2525 | ||
760141a5 TH |
2526 | cancel_work_sync(&adapter->reset_task); |
2527 | cancel_work_sync(&adapter->watchdog_task); | |
9d5c8243 | 2528 | |
421e02f0 | 2529 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 2530 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
2531 | dev_info(&pdev->dev, "DCA disabled\n"); |
2532 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 2533 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 2534 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
2535 | } |
2536 | #endif | |
2537 | ||
9d5c8243 | 2538 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
b980ac18 JK |
2539 | * would have already happened in close and is redundant. |
2540 | */ | |
9d5c8243 AK |
2541 | igb_release_hw_control(adapter); |
2542 | ||
2543 | unregister_netdev(netdev); | |
2544 | ||
047e0030 | 2545 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 2546 | |
37680117 | 2547 | #ifdef CONFIG_PCI_IOV |
fa44f2f1 | 2548 | igb_disable_sriov(pdev); |
37680117 | 2549 | #endif |
559e9c49 | 2550 | |
28b0759c AD |
2551 | iounmap(hw->hw_addr); |
2552 | if (hw->flash_address) | |
2553 | iounmap(hw->flash_address); | |
559e9c49 | 2554 | pci_release_selected_regions(pdev, |
b980ac18 | 2555 | pci_select_bars(pdev, IORESOURCE_MEM)); |
9d5c8243 | 2556 | |
1128c756 | 2557 | kfree(adapter->shadow_vfta); |
9d5c8243 AK |
2558 | free_netdev(netdev); |
2559 | ||
19d5afd4 | 2560 | pci_disable_pcie_error_reporting(pdev); |
40a914fa | 2561 | |
9d5c8243 AK |
2562 | pci_disable_device(pdev); |
2563 | } | |
2564 | ||
a6b623e0 | 2565 | /** |
b980ac18 JK |
2566 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space |
2567 | * @adapter: board private structure to initialize | |
a6b623e0 | 2568 | * |
b980ac18 JK |
2569 | * This function initializes the vf specific data storage and then attempts to |
2570 | * allocate the VFs. The reason for ordering it this way is because it is much | |
2571 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | |
2572 | * the memory for the VFs. | |
a6b623e0 | 2573 | **/ |
9f9a12f8 | 2574 | static void igb_probe_vfs(struct igb_adapter *adapter) |
a6b623e0 AD |
2575 | { |
2576 | #ifdef CONFIG_PCI_IOV | |
2577 | struct pci_dev *pdev = adapter->pdev; | |
f96a8a0b | 2578 | struct e1000_hw *hw = &adapter->hw; |
a6b623e0 | 2579 | |
f96a8a0b CW |
2580 | /* Virtualization features not supported on i210 family. */ |
2581 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) | |
2582 | return; | |
2583 | ||
fa44f2f1 | 2584 | pci_sriov_set_totalvfs(pdev, 7); |
d5e51a10 | 2585 | igb_enable_sriov(pdev, max_vfs); |
0224d663 | 2586 | |
a6b623e0 AD |
2587 | #endif /* CONFIG_PCI_IOV */ |
2588 | } | |
2589 | ||
fa44f2f1 | 2590 | static void igb_init_queue_configuration(struct igb_adapter *adapter) |
9d5c8243 AK |
2591 | { |
2592 | struct e1000_hw *hw = &adapter->hw; | |
374a542d | 2593 | u32 max_rss_queues; |
9d5c8243 | 2594 | |
374a542d | 2595 | /* Determine the maximum number of RSS queues supported. */ |
f96a8a0b | 2596 | switch (hw->mac.type) { |
374a542d MV |
2597 | case e1000_i211: |
2598 | max_rss_queues = IGB_MAX_RX_QUEUES_I211; | |
2599 | break; | |
2600 | case e1000_82575: | |
f96a8a0b | 2601 | case e1000_i210: |
374a542d MV |
2602 | max_rss_queues = IGB_MAX_RX_QUEUES_82575; |
2603 | break; | |
2604 | case e1000_i350: | |
2605 | /* I350 cannot do RSS and SR-IOV at the same time */ | |
2606 | if (!!adapter->vfs_allocated_count) { | |
2607 | max_rss_queues = 1; | |
2608 | break; | |
2609 | } | |
2610 | /* fall through */ | |
2611 | case e1000_82576: | |
2612 | if (!!adapter->vfs_allocated_count) { | |
2613 | max_rss_queues = 2; | |
2614 | break; | |
2615 | } | |
2616 | /* fall through */ | |
2617 | case e1000_82580: | |
ceb5f13b | 2618 | case e1000_i354: |
374a542d MV |
2619 | default: |
2620 | max_rss_queues = IGB_MAX_RX_QUEUES; | |
f96a8a0b | 2621 | break; |
374a542d MV |
2622 | } |
2623 | ||
2624 | adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); | |
2625 | ||
2626 | /* Determine if we need to pair queues. */ | |
2627 | switch (hw->mac.type) { | |
2628 | case e1000_82575: | |
f96a8a0b | 2629 | case e1000_i211: |
374a542d | 2630 | /* Device supports enough interrupts without queue pairing. */ |
f96a8a0b | 2631 | break; |
374a542d | 2632 | case e1000_82576: |
b980ac18 | 2633 | /* If VFs are going to be allocated with RSS queues then we |
374a542d MV |
2634 | * should pair the queues in order to conserve interrupts due |
2635 | * to limited supply. | |
2636 | */ | |
2637 | if ((adapter->rss_queues > 1) && | |
2638 | (adapter->vfs_allocated_count > 6)) | |
2639 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
2640 | /* fall through */ | |
2641 | case e1000_82580: | |
2642 | case e1000_i350: | |
ceb5f13b | 2643 | case e1000_i354: |
374a542d | 2644 | case e1000_i210: |
f96a8a0b | 2645 | default: |
b980ac18 | 2646 | /* If rss_queues > half of max_rss_queues, pair the queues in |
374a542d MV |
2647 | * order to conserve interrupts due to limited supply. |
2648 | */ | |
2649 | if (adapter->rss_queues > (max_rss_queues / 2)) | |
2650 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
f96a8a0b CW |
2651 | break; |
2652 | } | |
fa44f2f1 GR |
2653 | } |
2654 | ||
2655 | /** | |
b980ac18 JK |
2656 | * igb_sw_init - Initialize general software structures (struct igb_adapter) |
2657 | * @adapter: board private structure to initialize | |
fa44f2f1 | 2658 | * |
b980ac18 JK |
2659 | * igb_sw_init initializes the Adapter private data structure. |
2660 | * Fields are initialized based on PCI device information and | |
2661 | * OS network device settings (MTU size). | |
fa44f2f1 GR |
2662 | **/ |
2663 | static int igb_sw_init(struct igb_adapter *adapter) | |
2664 | { | |
2665 | struct e1000_hw *hw = &adapter->hw; | |
2666 | struct net_device *netdev = adapter->netdev; | |
2667 | struct pci_dev *pdev = adapter->pdev; | |
2668 | ||
2669 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
2670 | ||
2671 | /* set default ring sizes */ | |
2672 | adapter->tx_ring_count = IGB_DEFAULT_TXD; | |
2673 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
2674 | ||
2675 | /* set default ITR values */ | |
2676 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; | |
2677 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; | |
2678 | ||
2679 | /* set default work limits */ | |
2680 | adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; | |
2681 | ||
2682 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + | |
2683 | VLAN_HLEN; | |
2684 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
2685 | ||
2686 | spin_lock_init(&adapter->stats64_lock); | |
2687 | #ifdef CONFIG_PCI_IOV | |
2688 | switch (hw->mac.type) { | |
2689 | case e1000_82576: | |
2690 | case e1000_i350: | |
2691 | if (max_vfs > 7) { | |
2692 | dev_warn(&pdev->dev, | |
2693 | "Maximum of 7 VFs per PF, using max\n"); | |
d0f63acc | 2694 | max_vfs = adapter->vfs_allocated_count = 7; |
fa44f2f1 GR |
2695 | } else |
2696 | adapter->vfs_allocated_count = max_vfs; | |
2697 | if (adapter->vfs_allocated_count) | |
2698 | dev_warn(&pdev->dev, | |
2699 | "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); | |
2700 | break; | |
2701 | default: | |
2702 | break; | |
2703 | } | |
2704 | #endif /* CONFIG_PCI_IOV */ | |
2705 | ||
2706 | igb_init_queue_configuration(adapter); | |
a99955fc | 2707 | |
1128c756 | 2708 | /* Setup and initialize a copy of the hw vlan table array */ |
b2adaca9 JP |
2709 | adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), |
2710 | GFP_ATOMIC); | |
1128c756 | 2711 | |
a6b623e0 | 2712 | /* This call may decrease the number of queues */ |
53c7d064 | 2713 | if (igb_init_interrupt_scheme(adapter, true)) { |
9d5c8243 AK |
2714 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
2715 | return -ENOMEM; | |
2716 | } | |
2717 | ||
a6b623e0 AD |
2718 | igb_probe_vfs(adapter); |
2719 | ||
9d5c8243 AK |
2720 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
2721 | igb_irq_disable(adapter); | |
2722 | ||
f96a8a0b | 2723 | if (hw->mac.type >= e1000_i350) |
831ec0b4 CW |
2724 | adapter->flags &= ~IGB_FLAG_DMAC; |
2725 | ||
9d5c8243 AK |
2726 | set_bit(__IGB_DOWN, &adapter->state); |
2727 | return 0; | |
2728 | } | |
2729 | ||
2730 | /** | |
b980ac18 JK |
2731 | * igb_open - Called when a network interface is made active |
2732 | * @netdev: network interface device structure | |
9d5c8243 | 2733 | * |
b980ac18 | 2734 | * Returns 0 on success, negative value on failure |
9d5c8243 | 2735 | * |
b980ac18 JK |
2736 | * The open entry point is called when a network interface is made |
2737 | * active by the system (IFF_UP). At this point all resources needed | |
2738 | * for transmit and receive operations are allocated, the interrupt | |
2739 | * handler is registered with the OS, the watchdog timer is started, | |
2740 | * and the stack is notified that the interface is ready. | |
9d5c8243 | 2741 | **/ |
749ab2cd | 2742 | static int __igb_open(struct net_device *netdev, bool resuming) |
9d5c8243 AK |
2743 | { |
2744 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2745 | struct e1000_hw *hw = &adapter->hw; | |
749ab2cd | 2746 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2747 | int err; |
2748 | int i; | |
2749 | ||
2750 | /* disallow open during test */ | |
749ab2cd YZ |
2751 | if (test_bit(__IGB_TESTING, &adapter->state)) { |
2752 | WARN_ON(resuming); | |
9d5c8243 | 2753 | return -EBUSY; |
749ab2cd YZ |
2754 | } |
2755 | ||
2756 | if (!resuming) | |
2757 | pm_runtime_get_sync(&pdev->dev); | |
9d5c8243 | 2758 | |
b168dfc5 JB |
2759 | netif_carrier_off(netdev); |
2760 | ||
9d5c8243 AK |
2761 | /* allocate transmit descriptors */ |
2762 | err = igb_setup_all_tx_resources(adapter); | |
2763 | if (err) | |
2764 | goto err_setup_tx; | |
2765 | ||
2766 | /* allocate receive descriptors */ | |
2767 | err = igb_setup_all_rx_resources(adapter); | |
2768 | if (err) | |
2769 | goto err_setup_rx; | |
2770 | ||
88a268c1 | 2771 | igb_power_up_link(adapter); |
9d5c8243 | 2772 | |
9d5c8243 AK |
2773 | /* before we allocate an interrupt, we must be ready to handle it. |
2774 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
2775 | * as soon as we call pci_request_irq, so we have to setup our | |
b980ac18 JK |
2776 | * clean_rx handler before we do so. |
2777 | */ | |
9d5c8243 AK |
2778 | igb_configure(adapter); |
2779 | ||
2780 | err = igb_request_irq(adapter); | |
2781 | if (err) | |
2782 | goto err_req_irq; | |
2783 | ||
0c2cc02e AD |
2784 | /* Notify the stack of the actual queue counts. */ |
2785 | err = netif_set_real_num_tx_queues(adapter->netdev, | |
2786 | adapter->num_tx_queues); | |
2787 | if (err) | |
2788 | goto err_set_queues; | |
2789 | ||
2790 | err = netif_set_real_num_rx_queues(adapter->netdev, | |
2791 | adapter->num_rx_queues); | |
2792 | if (err) | |
2793 | goto err_set_queues; | |
2794 | ||
9d5c8243 AK |
2795 | /* From here on the code is the same as igb_up() */ |
2796 | clear_bit(__IGB_DOWN, &adapter->state); | |
2797 | ||
0d1ae7f4 AD |
2798 | for (i = 0; i < adapter->num_q_vectors; i++) |
2799 | napi_enable(&(adapter->q_vector[i]->napi)); | |
9d5c8243 AK |
2800 | |
2801 | /* Clear any pending interrupts. */ | |
2802 | rd32(E1000_ICR); | |
844290e5 PW |
2803 | |
2804 | igb_irq_enable(adapter); | |
2805 | ||
d4960307 AD |
2806 | /* notify VFs that reset has been completed */ |
2807 | if (adapter->vfs_allocated_count) { | |
2808 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
2809 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
2810 | wr32(E1000_CTRL_EXT, reg_data); | |
2811 | } | |
2812 | ||
d55b53ff JK |
2813 | netif_tx_start_all_queues(netdev); |
2814 | ||
749ab2cd YZ |
2815 | if (!resuming) |
2816 | pm_runtime_put(&pdev->dev); | |
2817 | ||
25568a53 AD |
2818 | /* start the watchdog. */ |
2819 | hw->mac.get_link_status = 1; | |
2820 | schedule_work(&adapter->watchdog_task); | |
9d5c8243 AK |
2821 | |
2822 | return 0; | |
2823 | ||
0c2cc02e AD |
2824 | err_set_queues: |
2825 | igb_free_irq(adapter); | |
9d5c8243 AK |
2826 | err_req_irq: |
2827 | igb_release_hw_control(adapter); | |
88a268c1 | 2828 | igb_power_down_link(adapter); |
9d5c8243 AK |
2829 | igb_free_all_rx_resources(adapter); |
2830 | err_setup_rx: | |
2831 | igb_free_all_tx_resources(adapter); | |
2832 | err_setup_tx: | |
2833 | igb_reset(adapter); | |
749ab2cd YZ |
2834 | if (!resuming) |
2835 | pm_runtime_put(&pdev->dev); | |
9d5c8243 AK |
2836 | |
2837 | return err; | |
2838 | } | |
2839 | ||
749ab2cd YZ |
2840 | static int igb_open(struct net_device *netdev) |
2841 | { | |
2842 | return __igb_open(netdev, false); | |
2843 | } | |
2844 | ||
9d5c8243 | 2845 | /** |
b980ac18 JK |
2846 | * igb_close - Disables a network interface |
2847 | * @netdev: network interface device structure | |
9d5c8243 | 2848 | * |
b980ac18 | 2849 | * Returns 0, this is not allowed to fail |
9d5c8243 | 2850 | * |
b980ac18 JK |
2851 | * The close entry point is called when an interface is de-activated |
2852 | * by the OS. The hardware is still under the driver's control, but | |
2853 | * needs to be disabled. A global MAC reset is issued to stop the | |
2854 | * hardware, and all transmit and receive resources are freed. | |
9d5c8243 | 2855 | **/ |
749ab2cd | 2856 | static int __igb_close(struct net_device *netdev, bool suspending) |
9d5c8243 AK |
2857 | { |
2858 | struct igb_adapter *adapter = netdev_priv(netdev); | |
749ab2cd | 2859 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2860 | |
2861 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
9d5c8243 | 2862 | |
749ab2cd YZ |
2863 | if (!suspending) |
2864 | pm_runtime_get_sync(&pdev->dev); | |
2865 | ||
2866 | igb_down(adapter); | |
9d5c8243 AK |
2867 | igb_free_irq(adapter); |
2868 | ||
2869 | igb_free_all_tx_resources(adapter); | |
2870 | igb_free_all_rx_resources(adapter); | |
2871 | ||
749ab2cd YZ |
2872 | if (!suspending) |
2873 | pm_runtime_put_sync(&pdev->dev); | |
9d5c8243 AK |
2874 | return 0; |
2875 | } | |
2876 | ||
749ab2cd YZ |
2877 | static int igb_close(struct net_device *netdev) |
2878 | { | |
2879 | return __igb_close(netdev, false); | |
2880 | } | |
2881 | ||
9d5c8243 | 2882 | /** |
b980ac18 JK |
2883 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) |
2884 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | |
9d5c8243 | 2885 | * |
b980ac18 | 2886 | * Return 0 on success, negative on failure |
9d5c8243 | 2887 | **/ |
80785298 | 2888 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2889 | { |
59d71989 | 2890 | struct device *dev = tx_ring->dev; |
9d5c8243 AK |
2891 | int size; |
2892 | ||
06034649 | 2893 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
f33005a6 AD |
2894 | |
2895 | tx_ring->tx_buffer_info = vzalloc(size); | |
06034649 | 2896 | if (!tx_ring->tx_buffer_info) |
9d5c8243 | 2897 | goto err; |
9d5c8243 AK |
2898 | |
2899 | /* round up to nearest 4K */ | |
85e8d004 | 2900 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
2901 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
2902 | ||
5536d210 AD |
2903 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
2904 | &tx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
2905 | if (!tx_ring->desc) |
2906 | goto err; | |
2907 | ||
9d5c8243 AK |
2908 | tx_ring->next_to_use = 0; |
2909 | tx_ring->next_to_clean = 0; | |
81c2fc22 | 2910 | |
9d5c8243 AK |
2911 | return 0; |
2912 | ||
2913 | err: | |
06034649 | 2914 | vfree(tx_ring->tx_buffer_info); |
f33005a6 AD |
2915 | tx_ring->tx_buffer_info = NULL; |
2916 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); | |
9d5c8243 AK |
2917 | return -ENOMEM; |
2918 | } | |
2919 | ||
2920 | /** | |
b980ac18 JK |
2921 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources |
2922 | * (Descriptors) for all queues | |
2923 | * @adapter: board private structure | |
9d5c8243 | 2924 | * |
b980ac18 | 2925 | * Return 0 on success, negative on failure |
9d5c8243 AK |
2926 | **/ |
2927 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
2928 | { | |
439705e1 | 2929 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2930 | int i, err = 0; |
2931 | ||
2932 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 2933 | err = igb_setup_tx_resources(adapter->tx_ring[i]); |
9d5c8243 | 2934 | if (err) { |
439705e1 | 2935 | dev_err(&pdev->dev, |
9d5c8243 AK |
2936 | "Allocation for Tx Queue %u failed\n", i); |
2937 | for (i--; i >= 0; i--) | |
3025a446 | 2938 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
2939 | break; |
2940 | } | |
2941 | } | |
2942 | ||
2943 | return err; | |
2944 | } | |
2945 | ||
2946 | /** | |
b980ac18 JK |
2947 | * igb_setup_tctl - configure the transmit control registers |
2948 | * @adapter: Board private structure | |
9d5c8243 | 2949 | **/ |
d7ee5b3a | 2950 | void igb_setup_tctl(struct igb_adapter *adapter) |
9d5c8243 | 2951 | { |
9d5c8243 AK |
2952 | struct e1000_hw *hw = &adapter->hw; |
2953 | u32 tctl; | |
9d5c8243 | 2954 | |
85b430b4 AD |
2955 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
2956 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
2957 | |
2958 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
2959 | tctl = rd32(E1000_TCTL); |
2960 | tctl &= ~E1000_TCTL_CT; | |
2961 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2962 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2963 | ||
2964 | igb_config_collision_dist(hw); | |
2965 | ||
9d5c8243 AK |
2966 | /* Enable transmits */ |
2967 | tctl |= E1000_TCTL_EN; | |
2968 | ||
2969 | wr32(E1000_TCTL, tctl); | |
2970 | } | |
2971 | ||
85b430b4 | 2972 | /** |
b980ac18 JK |
2973 | * igb_configure_tx_ring - Configure transmit ring after Reset |
2974 | * @adapter: board private structure | |
2975 | * @ring: tx ring to configure | |
85b430b4 | 2976 | * |
b980ac18 | 2977 | * Configure a transmit ring after a reset. |
85b430b4 | 2978 | **/ |
d7ee5b3a AD |
2979 | void igb_configure_tx_ring(struct igb_adapter *adapter, |
2980 | struct igb_ring *ring) | |
85b430b4 AD |
2981 | { |
2982 | struct e1000_hw *hw = &adapter->hw; | |
a74420e0 | 2983 | u32 txdctl = 0; |
85b430b4 AD |
2984 | u64 tdba = ring->dma; |
2985 | int reg_idx = ring->reg_idx; | |
2986 | ||
2987 | /* disable the queue */ | |
a74420e0 | 2988 | wr32(E1000_TXDCTL(reg_idx), 0); |
85b430b4 AD |
2989 | wrfl(); |
2990 | mdelay(10); | |
2991 | ||
2992 | wr32(E1000_TDLEN(reg_idx), | |
b980ac18 | 2993 | ring->count * sizeof(union e1000_adv_tx_desc)); |
85b430b4 | 2994 | wr32(E1000_TDBAL(reg_idx), |
b980ac18 | 2995 | tdba & 0x00000000ffffffffULL); |
85b430b4 AD |
2996 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); |
2997 | ||
fce99e34 | 2998 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); |
a74420e0 | 2999 | wr32(E1000_TDH(reg_idx), 0); |
fce99e34 | 3000 | writel(0, ring->tail); |
85b430b4 AD |
3001 | |
3002 | txdctl |= IGB_TX_PTHRESH; | |
3003 | txdctl |= IGB_TX_HTHRESH << 8; | |
3004 | txdctl |= IGB_TX_WTHRESH << 16; | |
3005 | ||
3006 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
3007 | wr32(E1000_TXDCTL(reg_idx), txdctl); | |
3008 | } | |
3009 | ||
3010 | /** | |
b980ac18 JK |
3011 | * igb_configure_tx - Configure transmit Unit after Reset |
3012 | * @adapter: board private structure | |
85b430b4 | 3013 | * |
b980ac18 | 3014 | * Configure the Tx unit of the MAC after a reset. |
85b430b4 AD |
3015 | **/ |
3016 | static void igb_configure_tx(struct igb_adapter *adapter) | |
3017 | { | |
3018 | int i; | |
3019 | ||
3020 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3021 | igb_configure_tx_ring(adapter, adapter->tx_ring[i]); |
85b430b4 AD |
3022 | } |
3023 | ||
9d5c8243 | 3024 | /** |
b980ac18 JK |
3025 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) |
3026 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
9d5c8243 | 3027 | * |
b980ac18 | 3028 | * Returns 0 on success, negative on failure |
9d5c8243 | 3029 | **/ |
80785298 | 3030 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3031 | { |
59d71989 | 3032 | struct device *dev = rx_ring->dev; |
f33005a6 | 3033 | int size; |
9d5c8243 | 3034 | |
06034649 | 3035 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
f33005a6 AD |
3036 | |
3037 | rx_ring->rx_buffer_info = vzalloc(size); | |
06034649 | 3038 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3039 | goto err; |
9d5c8243 | 3040 | |
9d5c8243 | 3041 | /* Round up to nearest 4K */ |
f33005a6 | 3042 | rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); |
9d5c8243 AK |
3043 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
3044 | ||
5536d210 AD |
3045 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
3046 | &rx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
3047 | if (!rx_ring->desc) |
3048 | goto err; | |
3049 | ||
cbc8e55f | 3050 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
3051 | rx_ring->next_to_clean = 0; |
3052 | rx_ring->next_to_use = 0; | |
9d5c8243 | 3053 | |
9d5c8243 AK |
3054 | return 0; |
3055 | ||
3056 | err: | |
06034649 AD |
3057 | vfree(rx_ring->rx_buffer_info); |
3058 | rx_ring->rx_buffer_info = NULL; | |
f33005a6 | 3059 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); |
9d5c8243 AK |
3060 | return -ENOMEM; |
3061 | } | |
3062 | ||
3063 | /** | |
b980ac18 JK |
3064 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources |
3065 | * (Descriptors) for all queues | |
3066 | * @adapter: board private structure | |
9d5c8243 | 3067 | * |
b980ac18 | 3068 | * Return 0 on success, negative on failure |
9d5c8243 AK |
3069 | **/ |
3070 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
3071 | { | |
439705e1 | 3072 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
3073 | int i, err = 0; |
3074 | ||
3075 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 3076 | err = igb_setup_rx_resources(adapter->rx_ring[i]); |
9d5c8243 | 3077 | if (err) { |
439705e1 | 3078 | dev_err(&pdev->dev, |
9d5c8243 AK |
3079 | "Allocation for Rx Queue %u failed\n", i); |
3080 | for (i--; i >= 0; i--) | |
3025a446 | 3081 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3082 | break; |
3083 | } | |
3084 | } | |
3085 | ||
3086 | return err; | |
3087 | } | |
3088 | ||
06cf2666 | 3089 | /** |
b980ac18 JK |
3090 | * igb_setup_mrqc - configure the multiple receive queue control registers |
3091 | * @adapter: Board private structure | |
06cf2666 AD |
3092 | **/ |
3093 | static void igb_setup_mrqc(struct igb_adapter *adapter) | |
3094 | { | |
3095 | struct e1000_hw *hw = &adapter->hw; | |
3096 | u32 mrqc, rxcsum; | |
797fd4be | 3097 | u32 j, num_rx_queues, shift = 0; |
a57fe23e AD |
3098 | static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, |
3099 | 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, | |
3100 | 0xA32DCB77, 0x0CF23080, 0x3BB7426A, | |
3101 | 0xFA01ACBE }; | |
06cf2666 AD |
3102 | |
3103 | /* Fill out hash function seeds */ | |
a57fe23e AD |
3104 | for (j = 0; j < 10; j++) |
3105 | wr32(E1000_RSSRK(j), rsskey[j]); | |
06cf2666 | 3106 | |
a99955fc | 3107 | num_rx_queues = adapter->rss_queues; |
06cf2666 | 3108 | |
797fd4be AD |
3109 | switch (hw->mac.type) { |
3110 | case e1000_82575: | |
3111 | shift = 6; | |
3112 | break; | |
3113 | case e1000_82576: | |
3114 | /* 82576 supports 2 RSS queues for SR-IOV */ | |
3115 | if (adapter->vfs_allocated_count) { | |
06cf2666 AD |
3116 | shift = 3; |
3117 | num_rx_queues = 2; | |
06cf2666 | 3118 | } |
797fd4be AD |
3119 | break; |
3120 | default: | |
3121 | break; | |
06cf2666 AD |
3122 | } |
3123 | ||
b980ac18 | 3124 | /* Populate the indirection table 4 entries at a time. To do this |
797fd4be AD |
3125 | * we are generating the results for n and n+2 and then interleaving |
3126 | * those with the results with n+1 and n+3. | |
3127 | */ | |
3128 | for (j = 0; j < 32; j++) { | |
3129 | /* first pass generates n and n+2 */ | |
3130 | u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; | |
3131 | u32 reta = (base & 0x07800780) >> (7 - shift); | |
3132 | ||
3133 | /* second pass generates n+1 and n+3 */ | |
3134 | base += 0x00010001 * num_rx_queues; | |
3135 | reta |= (base & 0x07800780) << (1 + shift); | |
3136 | ||
3137 | wr32(E1000_RETA(j), reta); | |
06cf2666 AD |
3138 | } |
3139 | ||
b980ac18 | 3140 | /* Disable raw packet checksumming so that RSS hash is placed in |
06cf2666 AD |
3141 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum |
3142 | * offloads as they are enabled by default | |
3143 | */ | |
3144 | rxcsum = rd32(E1000_RXCSUM); | |
3145 | rxcsum |= E1000_RXCSUM_PCSD; | |
3146 | ||
3147 | if (adapter->hw.mac.type >= e1000_82576) | |
3148 | /* Enable Receive Checksum Offload for SCTP */ | |
3149 | rxcsum |= E1000_RXCSUM_CRCOFL; | |
3150 | ||
3151 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | |
3152 | wr32(E1000_RXCSUM, rxcsum); | |
f96a8a0b | 3153 | |
039454a8 AA |
3154 | /* Generate RSS hash based on packet types, TCP/UDP |
3155 | * port numbers and/or IPv4/v6 src and dst addresses | |
3156 | */ | |
f96a8a0b CW |
3157 | mrqc = E1000_MRQC_RSS_FIELD_IPV4 | |
3158 | E1000_MRQC_RSS_FIELD_IPV4_TCP | | |
3159 | E1000_MRQC_RSS_FIELD_IPV6 | | |
3160 | E1000_MRQC_RSS_FIELD_IPV6_TCP | | |
3161 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; | |
06cf2666 | 3162 | |
039454a8 AA |
3163 | if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) |
3164 | mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; | |
3165 | if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) | |
3166 | mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; | |
3167 | ||
06cf2666 AD |
3168 | /* If VMDq is enabled then we set the appropriate mode for that, else |
3169 | * we default to RSS so that an RSS hash is calculated per packet even | |
b980ac18 JK |
3170 | * if we are only using one queue |
3171 | */ | |
06cf2666 AD |
3172 | if (adapter->vfs_allocated_count) { |
3173 | if (hw->mac.type > e1000_82575) { | |
3174 | /* Set the default pool for the PF's first queue */ | |
3175 | u32 vtctl = rd32(E1000_VT_CTL); | |
3176 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
3177 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
3178 | vtctl |= adapter->vfs_allocated_count << | |
3179 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
3180 | wr32(E1000_VT_CTL, vtctl); | |
3181 | } | |
a99955fc | 3182 | if (adapter->rss_queues > 1) |
f96a8a0b | 3183 | mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
06cf2666 | 3184 | else |
f96a8a0b | 3185 | mrqc |= E1000_MRQC_ENABLE_VMDQ; |
06cf2666 | 3186 | } else { |
f96a8a0b CW |
3187 | if (hw->mac.type != e1000_i211) |
3188 | mrqc |= E1000_MRQC_ENABLE_RSS_4Q; | |
06cf2666 AD |
3189 | } |
3190 | igb_vmm_control(adapter); | |
3191 | ||
06cf2666 AD |
3192 | wr32(E1000_MRQC, mrqc); |
3193 | } | |
3194 | ||
9d5c8243 | 3195 | /** |
b980ac18 JK |
3196 | * igb_setup_rctl - configure the receive control registers |
3197 | * @adapter: Board private structure | |
9d5c8243 | 3198 | **/ |
d7ee5b3a | 3199 | void igb_setup_rctl(struct igb_adapter *adapter) |
9d5c8243 AK |
3200 | { |
3201 | struct e1000_hw *hw = &adapter->hw; | |
3202 | u32 rctl; | |
9d5c8243 AK |
3203 | |
3204 | rctl = rd32(E1000_RCTL); | |
3205 | ||
3206 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 3207 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 3208 | |
69d728ba | 3209 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 3210 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 3211 | |
b980ac18 | 3212 | /* enable stripping of CRC. It's unlikely this will break BMC |
87cb7e8c AK |
3213 | * redirection as it did with e1000. Newer features require |
3214 | * that the HW strips the CRC. | |
73cd78f1 | 3215 | */ |
87cb7e8c | 3216 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 3217 | |
559e9c49 | 3218 | /* disable store bad packets and clear size bits. */ |
ec54d7d6 | 3219 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 3220 | |
6ec43fe6 AD |
3221 | /* enable LPE to prevent packets larger than max_frame_size */ |
3222 | rctl |= E1000_RCTL_LPE; | |
9d5c8243 | 3223 | |
952f72a8 AD |
3224 | /* disable queue 0 to prevent tail write w/o re-config */ |
3225 | wr32(E1000_RXDCTL(0), 0); | |
9d5c8243 | 3226 | |
e1739522 AD |
3227 | /* Attention!!! For SR-IOV PF driver operations you must enable |
3228 | * queue drop for all VF and PF queues to prevent head of line blocking | |
3229 | * if an un-trusted VF does not provide descriptors to hardware. | |
3230 | */ | |
3231 | if (adapter->vfs_allocated_count) { | |
e1739522 AD |
3232 | /* set all queue drop enable bits */ |
3233 | wr32(E1000_QDE, ALL_QUEUES); | |
e1739522 AD |
3234 | } |
3235 | ||
89eaefb6 BG |
3236 | /* This is useful for sniffing bad packets. */ |
3237 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3238 | /* UPE and MPE will be handled by normal PROMISC logic | |
b980ac18 JK |
3239 | * in e1000e_set_rx_mode |
3240 | */ | |
89eaefb6 BG |
3241 | rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ |
3242 | E1000_RCTL_BAM | /* RX All Bcast Pkts */ | |
3243 | E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3244 | ||
3245 | rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ | |
3246 | E1000_RCTL_DPF | /* Allow filtered pause */ | |
3247 | E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ | |
3248 | /* Do not mess with E1000_CTRL_VME, it affects transmit as well, | |
3249 | * and that breaks VLANs. | |
3250 | */ | |
3251 | } | |
3252 | ||
9d5c8243 AK |
3253 | wr32(E1000_RCTL, rctl); |
3254 | } | |
3255 | ||
7d5753f0 AD |
3256 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
3257 | int vfn) | |
3258 | { | |
3259 | struct e1000_hw *hw = &adapter->hw; | |
3260 | u32 vmolr; | |
3261 | ||
3262 | /* if it isn't the PF check to see if VFs are enabled and | |
b980ac18 JK |
3263 | * increase the size to support vlan tags |
3264 | */ | |
7d5753f0 AD |
3265 | if (vfn < adapter->vfs_allocated_count && |
3266 | adapter->vf_data[vfn].vlans_enabled) | |
3267 | size += VLAN_TAG_SIZE; | |
3268 | ||
3269 | vmolr = rd32(E1000_VMOLR(vfn)); | |
3270 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
3271 | vmolr |= size | E1000_VMOLR_LPE; | |
3272 | wr32(E1000_VMOLR(vfn), vmolr); | |
3273 | ||
3274 | return 0; | |
3275 | } | |
3276 | ||
e1739522 | 3277 | /** |
b980ac18 JK |
3278 | * igb_rlpml_set - set maximum receive packet size |
3279 | * @adapter: board private structure | |
e1739522 | 3280 | * |
b980ac18 | 3281 | * Configure maximum receivable packet size. |
e1739522 AD |
3282 | **/ |
3283 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
3284 | { | |
153285f9 | 3285 | u32 max_frame_size = adapter->max_frame_size; |
e1739522 AD |
3286 | struct e1000_hw *hw = &adapter->hw; |
3287 | u16 pf_id = adapter->vfs_allocated_count; | |
3288 | ||
e1739522 AD |
3289 | if (pf_id) { |
3290 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
b980ac18 | 3291 | /* If we're in VMDQ or SR-IOV mode, then set global RLPML |
153285f9 AD |
3292 | * to our max jumbo frame size, in case we need to enable |
3293 | * jumbo frames on one of the rings later. | |
3294 | * This will not pass over-length frames into the default | |
3295 | * queue because it's gated by the VMOLR.RLPML. | |
3296 | */ | |
7d5753f0 | 3297 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
e1739522 AD |
3298 | } |
3299 | ||
3300 | wr32(E1000_RLPML, max_frame_size); | |
3301 | } | |
3302 | ||
8151d294 WM |
3303 | static inline void igb_set_vmolr(struct igb_adapter *adapter, |
3304 | int vfn, bool aupe) | |
7d5753f0 AD |
3305 | { |
3306 | struct e1000_hw *hw = &adapter->hw; | |
3307 | u32 vmolr; | |
3308 | ||
b980ac18 | 3309 | /* This register exists only on 82576 and newer so if we are older then |
7d5753f0 AD |
3310 | * we should exit and do nothing |
3311 | */ | |
3312 | if (hw->mac.type < e1000_82576) | |
3313 | return; | |
3314 | ||
3315 | vmolr = rd32(E1000_VMOLR(vfn)); | |
b980ac18 | 3316 | vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ |
8151d294 | 3317 | if (aupe) |
b980ac18 | 3318 | vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ |
8151d294 WM |
3319 | else |
3320 | vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ | |
7d5753f0 AD |
3321 | |
3322 | /* clear all bits that might not be set */ | |
3323 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | |
3324 | ||
a99955fc | 3325 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
7d5753f0 | 3326 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
b980ac18 | 3327 | /* for VMDq only allow the VFs and pool 0 to accept broadcast and |
7d5753f0 AD |
3328 | * multicast packets |
3329 | */ | |
3330 | if (vfn <= adapter->vfs_allocated_count) | |
b980ac18 | 3331 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ |
7d5753f0 AD |
3332 | |
3333 | wr32(E1000_VMOLR(vfn), vmolr); | |
3334 | } | |
3335 | ||
85b430b4 | 3336 | /** |
b980ac18 JK |
3337 | * igb_configure_rx_ring - Configure a receive ring after Reset |
3338 | * @adapter: board private structure | |
3339 | * @ring: receive ring to be configured | |
85b430b4 | 3340 | * |
b980ac18 | 3341 | * Configure the Rx unit of the MAC after a reset. |
85b430b4 | 3342 | **/ |
d7ee5b3a | 3343 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
b980ac18 | 3344 | struct igb_ring *ring) |
85b430b4 AD |
3345 | { |
3346 | struct e1000_hw *hw = &adapter->hw; | |
3347 | u64 rdba = ring->dma; | |
3348 | int reg_idx = ring->reg_idx; | |
a74420e0 | 3349 | u32 srrctl = 0, rxdctl = 0; |
85b430b4 AD |
3350 | |
3351 | /* disable the queue */ | |
a74420e0 | 3352 | wr32(E1000_RXDCTL(reg_idx), 0); |
85b430b4 AD |
3353 | |
3354 | /* Set DMA base address registers */ | |
3355 | wr32(E1000_RDBAL(reg_idx), | |
3356 | rdba & 0x00000000ffffffffULL); | |
3357 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | |
3358 | wr32(E1000_RDLEN(reg_idx), | |
b980ac18 | 3359 | ring->count * sizeof(union e1000_adv_rx_desc)); |
85b430b4 AD |
3360 | |
3361 | /* initialize head and tail */ | |
fce99e34 | 3362 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); |
a74420e0 | 3363 | wr32(E1000_RDH(reg_idx), 0); |
fce99e34 | 3364 | writel(0, ring->tail); |
85b430b4 | 3365 | |
952f72a8 | 3366 | /* set descriptor configuration */ |
44390ca6 | 3367 | srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
de78d1f9 | 3368 | srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; |
1a1c225b | 3369 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; |
06218a8d | 3370 | if (hw->mac.type >= e1000_82580) |
757b77e2 | 3371 | srrctl |= E1000_SRRCTL_TIMESTAMP; |
e6bdb6fe NN |
3372 | /* Only set Drop Enable if we are supporting multiple queues */ |
3373 | if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) | |
3374 | srrctl |= E1000_SRRCTL_DROP_EN; | |
952f72a8 AD |
3375 | |
3376 | wr32(E1000_SRRCTL(reg_idx), srrctl); | |
3377 | ||
7d5753f0 | 3378 | /* set filtering for VMDQ pools */ |
8151d294 | 3379 | igb_set_vmolr(adapter, reg_idx & 0x7, true); |
7d5753f0 | 3380 | |
85b430b4 AD |
3381 | rxdctl |= IGB_RX_PTHRESH; |
3382 | rxdctl |= IGB_RX_HTHRESH << 8; | |
3383 | rxdctl |= IGB_RX_WTHRESH << 16; | |
a74420e0 AD |
3384 | |
3385 | /* enable receive descriptor fetching */ | |
3386 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
85b430b4 AD |
3387 | wr32(E1000_RXDCTL(reg_idx), rxdctl); |
3388 | } | |
3389 | ||
74e238ea AD |
3390 | static void igb_set_rx_buffer_len(struct igb_adapter *adapter, |
3391 | struct igb_ring *rx_ring) | |
3392 | { | |
3393 | #define IGB_MAX_BUILD_SKB_SIZE \ | |
3394 | (SKB_WITH_OVERHEAD(IGB_RX_BUFSZ) - \ | |
3395 | (NET_SKB_PAD + NET_IP_ALIGN + IGB_TS_HDR_LEN)) | |
3396 | ||
3397 | /* set build_skb flag */ | |
3398 | if (adapter->max_frame_size <= IGB_MAX_BUILD_SKB_SIZE) | |
3399 | set_ring_build_skb_enabled(rx_ring); | |
3400 | else | |
3401 | clear_ring_build_skb_enabled(rx_ring); | |
3402 | } | |
3403 | ||
9d5c8243 | 3404 | /** |
b980ac18 JK |
3405 | * igb_configure_rx - Configure receive Unit after Reset |
3406 | * @adapter: board private structure | |
9d5c8243 | 3407 | * |
b980ac18 | 3408 | * Configure the Rx unit of the MAC after a reset. |
9d5c8243 AK |
3409 | **/ |
3410 | static void igb_configure_rx(struct igb_adapter *adapter) | |
3411 | { | |
9107584e | 3412 | int i; |
9d5c8243 | 3413 | |
68d480c4 AD |
3414 | /* set UTA to appropriate mode */ |
3415 | igb_set_uta(adapter); | |
3416 | ||
26ad9178 AD |
3417 | /* set the correct pool for the PF default MAC address in entry 0 */ |
3418 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, | |
b980ac18 | 3419 | adapter->vfs_allocated_count); |
26ad9178 | 3420 | |
06cf2666 | 3421 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
b980ac18 JK |
3422 | * the Base and Length of the Rx Descriptor Ring |
3423 | */ | |
74e238ea AD |
3424 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3425 | struct igb_ring *rx_ring = adapter->rx_ring[i]; | |
3426 | igb_set_rx_buffer_len(adapter, rx_ring); | |
3427 | igb_configure_rx_ring(adapter, rx_ring); | |
3428 | } | |
9d5c8243 AK |
3429 | } |
3430 | ||
3431 | /** | |
b980ac18 JK |
3432 | * igb_free_tx_resources - Free Tx Resources per Queue |
3433 | * @tx_ring: Tx descriptor ring for a specific queue | |
9d5c8243 | 3434 | * |
b980ac18 | 3435 | * Free all transmit software resources |
9d5c8243 | 3436 | **/ |
68fd9910 | 3437 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 3438 | { |
3b644cf6 | 3439 | igb_clean_tx_ring(tx_ring); |
9d5c8243 | 3440 | |
06034649 AD |
3441 | vfree(tx_ring->tx_buffer_info); |
3442 | tx_ring->tx_buffer_info = NULL; | |
9d5c8243 | 3443 | |
439705e1 AD |
3444 | /* if not set, then don't free */ |
3445 | if (!tx_ring->desc) | |
3446 | return; | |
3447 | ||
59d71989 AD |
3448 | dma_free_coherent(tx_ring->dev, tx_ring->size, |
3449 | tx_ring->desc, tx_ring->dma); | |
9d5c8243 AK |
3450 | |
3451 | tx_ring->desc = NULL; | |
3452 | } | |
3453 | ||
3454 | /** | |
b980ac18 JK |
3455 | * igb_free_all_tx_resources - Free Tx Resources for All Queues |
3456 | * @adapter: board private structure | |
9d5c8243 | 3457 | * |
b980ac18 | 3458 | * Free all transmit software resources |
9d5c8243 AK |
3459 | **/ |
3460 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
3461 | { | |
3462 | int i; | |
3463 | ||
3464 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3465 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
3466 | } |
3467 | ||
ebe42d16 AD |
3468 | void igb_unmap_and_free_tx_resource(struct igb_ring *ring, |
3469 | struct igb_tx_buffer *tx_buffer) | |
3470 | { | |
3471 | if (tx_buffer->skb) { | |
3472 | dev_kfree_skb_any(tx_buffer->skb); | |
c9f14bf3 | 3473 | if (dma_unmap_len(tx_buffer, len)) |
ebe42d16 | 3474 | dma_unmap_single(ring->dev, |
c9f14bf3 AD |
3475 | dma_unmap_addr(tx_buffer, dma), |
3476 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 3477 | DMA_TO_DEVICE); |
c9f14bf3 | 3478 | } else if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 3479 | dma_unmap_page(ring->dev, |
c9f14bf3 AD |
3480 | dma_unmap_addr(tx_buffer, dma), |
3481 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
3482 | DMA_TO_DEVICE); |
3483 | } | |
3484 | tx_buffer->next_to_watch = NULL; | |
3485 | tx_buffer->skb = NULL; | |
c9f14bf3 | 3486 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 | 3487 | /* buffer_info must be completely set up in the transmit path */ |
9d5c8243 AK |
3488 | } |
3489 | ||
3490 | /** | |
b980ac18 JK |
3491 | * igb_clean_tx_ring - Free Tx Buffers |
3492 | * @tx_ring: ring to be cleaned | |
9d5c8243 | 3493 | **/ |
3b644cf6 | 3494 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 3495 | { |
06034649 | 3496 | struct igb_tx_buffer *buffer_info; |
9d5c8243 | 3497 | unsigned long size; |
6ad4edfc | 3498 | u16 i; |
9d5c8243 | 3499 | |
06034649 | 3500 | if (!tx_ring->tx_buffer_info) |
9d5c8243 AK |
3501 | return; |
3502 | /* Free all the Tx ring sk_buffs */ | |
3503 | ||
3504 | for (i = 0; i < tx_ring->count; i++) { | |
06034649 | 3505 | buffer_info = &tx_ring->tx_buffer_info[i]; |
80785298 | 3506 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
9d5c8243 AK |
3507 | } |
3508 | ||
dad8a3b3 JF |
3509 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
3510 | ||
06034649 AD |
3511 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
3512 | memset(tx_ring->tx_buffer_info, 0, size); | |
9d5c8243 AK |
3513 | |
3514 | /* Zero out the descriptor ring */ | |
9d5c8243 AK |
3515 | memset(tx_ring->desc, 0, tx_ring->size); |
3516 | ||
3517 | tx_ring->next_to_use = 0; | |
3518 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
3519 | } |
3520 | ||
3521 | /** | |
b980ac18 JK |
3522 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues |
3523 | * @adapter: board private structure | |
9d5c8243 AK |
3524 | **/ |
3525 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
3526 | { | |
3527 | int i; | |
3528 | ||
3529 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3530 | igb_clean_tx_ring(adapter->tx_ring[i]); |
9d5c8243 AK |
3531 | } |
3532 | ||
3533 | /** | |
b980ac18 JK |
3534 | * igb_free_rx_resources - Free Rx Resources |
3535 | * @rx_ring: ring to clean the resources from | |
9d5c8243 | 3536 | * |
b980ac18 | 3537 | * Free all receive software resources |
9d5c8243 | 3538 | **/ |
68fd9910 | 3539 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3540 | { |
3b644cf6 | 3541 | igb_clean_rx_ring(rx_ring); |
9d5c8243 | 3542 | |
06034649 AD |
3543 | vfree(rx_ring->rx_buffer_info); |
3544 | rx_ring->rx_buffer_info = NULL; | |
9d5c8243 | 3545 | |
439705e1 AD |
3546 | /* if not set, then don't free */ |
3547 | if (!rx_ring->desc) | |
3548 | return; | |
3549 | ||
59d71989 AD |
3550 | dma_free_coherent(rx_ring->dev, rx_ring->size, |
3551 | rx_ring->desc, rx_ring->dma); | |
9d5c8243 AK |
3552 | |
3553 | rx_ring->desc = NULL; | |
3554 | } | |
3555 | ||
3556 | /** | |
b980ac18 JK |
3557 | * igb_free_all_rx_resources - Free Rx Resources for All Queues |
3558 | * @adapter: board private structure | |
9d5c8243 | 3559 | * |
b980ac18 | 3560 | * Free all receive software resources |
9d5c8243 AK |
3561 | **/ |
3562 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
3563 | { | |
3564 | int i; | |
3565 | ||
3566 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3567 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3568 | } |
3569 | ||
3570 | /** | |
b980ac18 JK |
3571 | * igb_clean_rx_ring - Free Rx Buffers per Queue |
3572 | * @rx_ring: ring to free buffers from | |
9d5c8243 | 3573 | **/ |
3b644cf6 | 3574 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 3575 | { |
9d5c8243 | 3576 | unsigned long size; |
c023cd88 | 3577 | u16 i; |
9d5c8243 | 3578 | |
1a1c225b AD |
3579 | if (rx_ring->skb) |
3580 | dev_kfree_skb(rx_ring->skb); | |
3581 | rx_ring->skb = NULL; | |
3582 | ||
06034649 | 3583 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3584 | return; |
439705e1 | 3585 | |
9d5c8243 AK |
3586 | /* Free all the Rx ring sk_buffs */ |
3587 | for (i = 0; i < rx_ring->count; i++) { | |
06034649 | 3588 | struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; |
9d5c8243 | 3589 | |
cbc8e55f AD |
3590 | if (!buffer_info->page) |
3591 | continue; | |
3592 | ||
3593 | dma_unmap_page(rx_ring->dev, | |
3594 | buffer_info->dma, | |
3595 | PAGE_SIZE, | |
3596 | DMA_FROM_DEVICE); | |
3597 | __free_page(buffer_info->page); | |
3598 | ||
1a1c225b | 3599 | buffer_info->page = NULL; |
9d5c8243 AK |
3600 | } |
3601 | ||
06034649 AD |
3602 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
3603 | memset(rx_ring->rx_buffer_info, 0, size); | |
9d5c8243 AK |
3604 | |
3605 | /* Zero out the descriptor ring */ | |
3606 | memset(rx_ring->desc, 0, rx_ring->size); | |
3607 | ||
cbc8e55f | 3608 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
3609 | rx_ring->next_to_clean = 0; |
3610 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
3611 | } |
3612 | ||
3613 | /** | |
b980ac18 JK |
3614 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues |
3615 | * @adapter: board private structure | |
9d5c8243 AK |
3616 | **/ |
3617 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
3618 | { | |
3619 | int i; | |
3620 | ||
3621 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3622 | igb_clean_rx_ring(adapter->rx_ring[i]); |
9d5c8243 AK |
3623 | } |
3624 | ||
3625 | /** | |
b980ac18 JK |
3626 | * igb_set_mac - Change the Ethernet Address of the NIC |
3627 | * @netdev: network interface device structure | |
3628 | * @p: pointer to an address structure | |
9d5c8243 | 3629 | * |
b980ac18 | 3630 | * Returns 0 on success, negative on failure |
9d5c8243 AK |
3631 | **/ |
3632 | static int igb_set_mac(struct net_device *netdev, void *p) | |
3633 | { | |
3634 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 3635 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3636 | struct sockaddr *addr = p; |
3637 | ||
3638 | if (!is_valid_ether_addr(addr->sa_data)) | |
3639 | return -EADDRNOTAVAIL; | |
3640 | ||
3641 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 3642 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 3643 | |
26ad9178 AD |
3644 | /* set the correct pool for the new PF MAC address in entry 0 */ |
3645 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, | |
b980ac18 | 3646 | adapter->vfs_allocated_count); |
e1739522 | 3647 | |
9d5c8243 AK |
3648 | return 0; |
3649 | } | |
3650 | ||
3651 | /** | |
b980ac18 JK |
3652 | * igb_write_mc_addr_list - write multicast addresses to MTA |
3653 | * @netdev: network interface device structure | |
9d5c8243 | 3654 | * |
b980ac18 JK |
3655 | * Writes multicast address list to the MTA hash table. |
3656 | * Returns: -ENOMEM on failure | |
3657 | * 0 on no addresses written | |
3658 | * X on writing X addresses to MTA | |
9d5c8243 | 3659 | **/ |
68d480c4 | 3660 | static int igb_write_mc_addr_list(struct net_device *netdev) |
9d5c8243 AK |
3661 | { |
3662 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3663 | struct e1000_hw *hw = &adapter->hw; | |
22bedad3 | 3664 | struct netdev_hw_addr *ha; |
68d480c4 | 3665 | u8 *mta_list; |
9d5c8243 AK |
3666 | int i; |
3667 | ||
4cd24eaf | 3668 | if (netdev_mc_empty(netdev)) { |
68d480c4 AD |
3669 | /* nothing to program, so clear mc list */ |
3670 | igb_update_mc_addr_list(hw, NULL, 0); | |
3671 | igb_restore_vf_multicasts(adapter); | |
3672 | return 0; | |
3673 | } | |
9d5c8243 | 3674 | |
4cd24eaf | 3675 | mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
68d480c4 AD |
3676 | if (!mta_list) |
3677 | return -ENOMEM; | |
ff41f8dc | 3678 | |
68d480c4 | 3679 | /* The shared function expects a packed array of only addresses. */ |
48e2f183 | 3680 | i = 0; |
22bedad3 JP |
3681 | netdev_for_each_mc_addr(ha, netdev) |
3682 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); | |
68d480c4 | 3683 | |
68d480c4 AD |
3684 | igb_update_mc_addr_list(hw, mta_list, i); |
3685 | kfree(mta_list); | |
3686 | ||
4cd24eaf | 3687 | return netdev_mc_count(netdev); |
68d480c4 AD |
3688 | } |
3689 | ||
3690 | /** | |
b980ac18 JK |
3691 | * igb_write_uc_addr_list - write unicast addresses to RAR table |
3692 | * @netdev: network interface device structure | |
68d480c4 | 3693 | * |
b980ac18 JK |
3694 | * Writes unicast address list to the RAR table. |
3695 | * Returns: -ENOMEM on failure/insufficient address space | |
3696 | * 0 on no addresses written | |
3697 | * X on writing X addresses to the RAR table | |
68d480c4 AD |
3698 | **/ |
3699 | static int igb_write_uc_addr_list(struct net_device *netdev) | |
3700 | { | |
3701 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3702 | struct e1000_hw *hw = &adapter->hw; | |
3703 | unsigned int vfn = adapter->vfs_allocated_count; | |
3704 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | |
3705 | int count = 0; | |
3706 | ||
3707 | /* return ENOMEM indicating insufficient memory for addresses */ | |
32e7bfc4 | 3708 | if (netdev_uc_count(netdev) > rar_entries) |
68d480c4 | 3709 | return -ENOMEM; |
9d5c8243 | 3710 | |
32e7bfc4 | 3711 | if (!netdev_uc_empty(netdev) && rar_entries) { |
ff41f8dc | 3712 | struct netdev_hw_addr *ha; |
32e7bfc4 JP |
3713 | |
3714 | netdev_for_each_uc_addr(ha, netdev) { | |
ff41f8dc AD |
3715 | if (!rar_entries) |
3716 | break; | |
26ad9178 | 3717 | igb_rar_set_qsel(adapter, ha->addr, |
b980ac18 JK |
3718 | rar_entries--, |
3719 | vfn); | |
68d480c4 | 3720 | count++; |
ff41f8dc AD |
3721 | } |
3722 | } | |
3723 | /* write the addresses in reverse order to avoid write combining */ | |
3724 | for (; rar_entries > 0 ; rar_entries--) { | |
3725 | wr32(E1000_RAH(rar_entries), 0); | |
3726 | wr32(E1000_RAL(rar_entries), 0); | |
3727 | } | |
3728 | wrfl(); | |
3729 | ||
68d480c4 AD |
3730 | return count; |
3731 | } | |
3732 | ||
3733 | /** | |
b980ac18 JK |
3734 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set |
3735 | * @netdev: network interface device structure | |
68d480c4 | 3736 | * |
b980ac18 JK |
3737 | * The set_rx_mode entry point is called whenever the unicast or multicast |
3738 | * address lists or the network interface flags are updated. This routine is | |
3739 | * responsible for configuring the hardware for proper unicast, multicast, | |
3740 | * promiscuous mode, and all-multi behavior. | |
68d480c4 AD |
3741 | **/ |
3742 | static void igb_set_rx_mode(struct net_device *netdev) | |
3743 | { | |
3744 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3745 | struct e1000_hw *hw = &adapter->hw; | |
3746 | unsigned int vfn = adapter->vfs_allocated_count; | |
3747 | u32 rctl, vmolr = 0; | |
3748 | int count; | |
3749 | ||
3750 | /* Check for Promiscuous and All Multicast modes */ | |
3751 | rctl = rd32(E1000_RCTL); | |
3752 | ||
3753 | /* clear the effected bits */ | |
3754 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | |
3755 | ||
3756 | if (netdev->flags & IFF_PROMISC) { | |
3757 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
3758 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | |
3759 | } else { | |
3760 | if (netdev->flags & IFF_ALLMULTI) { | |
3761 | rctl |= E1000_RCTL_MPE; | |
3762 | vmolr |= E1000_VMOLR_MPME; | |
3763 | } else { | |
b980ac18 | 3764 | /* Write addresses to the MTA, if the attempt fails |
25985edc | 3765 | * then we should just turn on promiscuous mode so |
68d480c4 AD |
3766 | * that we can at least receive multicast traffic |
3767 | */ | |
3768 | count = igb_write_mc_addr_list(netdev); | |
3769 | if (count < 0) { | |
3770 | rctl |= E1000_RCTL_MPE; | |
3771 | vmolr |= E1000_VMOLR_MPME; | |
3772 | } else if (count) { | |
3773 | vmolr |= E1000_VMOLR_ROMPE; | |
3774 | } | |
3775 | } | |
b980ac18 | 3776 | /* Write addresses to available RAR registers, if there is not |
68d480c4 | 3777 | * sufficient space to store all the addresses then enable |
25985edc | 3778 | * unicast promiscuous mode |
68d480c4 AD |
3779 | */ |
3780 | count = igb_write_uc_addr_list(netdev); | |
3781 | if (count < 0) { | |
3782 | rctl |= E1000_RCTL_UPE; | |
3783 | vmolr |= E1000_VMOLR_ROPE; | |
3784 | } | |
3785 | rctl |= E1000_RCTL_VFE; | |
28fc06f5 | 3786 | } |
68d480c4 | 3787 | wr32(E1000_RCTL, rctl); |
28fc06f5 | 3788 | |
b980ac18 | 3789 | /* In order to support SR-IOV and eventually VMDq it is necessary to set |
68d480c4 AD |
3790 | * the VMOLR to enable the appropriate modes. Without this workaround |
3791 | * we will have issues with VLAN tag stripping not being done for frames | |
3792 | * that are only arriving because we are the default pool | |
3793 | */ | |
f96a8a0b | 3794 | if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) |
28fc06f5 | 3795 | return; |
9d5c8243 | 3796 | |
68d480c4 | 3797 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
b980ac18 | 3798 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); |
68d480c4 | 3799 | wr32(E1000_VMOLR(vfn), vmolr); |
28fc06f5 | 3800 | igb_restore_vf_multicasts(adapter); |
9d5c8243 AK |
3801 | } |
3802 | ||
13800469 GR |
3803 | static void igb_check_wvbr(struct igb_adapter *adapter) |
3804 | { | |
3805 | struct e1000_hw *hw = &adapter->hw; | |
3806 | u32 wvbr = 0; | |
3807 | ||
3808 | switch (hw->mac.type) { | |
3809 | case e1000_82576: | |
3810 | case e1000_i350: | |
3811 | if (!(wvbr = rd32(E1000_WVBR))) | |
3812 | return; | |
3813 | break; | |
3814 | default: | |
3815 | break; | |
3816 | } | |
3817 | ||
3818 | adapter->wvbr |= wvbr; | |
3819 | } | |
3820 | ||
3821 | #define IGB_STAGGERED_QUEUE_OFFSET 8 | |
3822 | ||
3823 | static void igb_spoof_check(struct igb_adapter *adapter) | |
3824 | { | |
3825 | int j; | |
3826 | ||
3827 | if (!adapter->wvbr) | |
3828 | return; | |
3829 | ||
3830 | for(j = 0; j < adapter->vfs_allocated_count; j++) { | |
3831 | if (adapter->wvbr & (1 << j) || | |
3832 | adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { | |
3833 | dev_warn(&adapter->pdev->dev, | |
3834 | "Spoof event(s) detected on VF %d\n", j); | |
3835 | adapter->wvbr &= | |
3836 | ~((1 << j) | | |
3837 | (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); | |
3838 | } | |
3839 | } | |
3840 | } | |
3841 | ||
9d5c8243 | 3842 | /* Need to wait a few seconds after link up to get diagnostic information from |
b980ac18 JK |
3843 | * the phy |
3844 | */ | |
9d5c8243 AK |
3845 | static void igb_update_phy_info(unsigned long data) |
3846 | { | |
3847 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 3848 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
3849 | } |
3850 | ||
4d6b725e | 3851 | /** |
b980ac18 JK |
3852 | * igb_has_link - check shared code for link and determine up/down |
3853 | * @adapter: pointer to driver private info | |
4d6b725e | 3854 | **/ |
3145535a | 3855 | bool igb_has_link(struct igb_adapter *adapter) |
4d6b725e AD |
3856 | { |
3857 | struct e1000_hw *hw = &adapter->hw; | |
3858 | bool link_active = false; | |
3859 | s32 ret_val = 0; | |
3860 | ||
3861 | /* get_link_status is set on LSC (link status) interrupt or | |
3862 | * rx sequence error interrupt. get_link_status will stay | |
3863 | * false until the e1000_check_for_link establishes link | |
3864 | * for copper adapters ONLY | |
3865 | */ | |
3866 | switch (hw->phy.media_type) { | |
3867 | case e1000_media_type_copper: | |
3868 | if (hw->mac.get_link_status) { | |
3869 | ret_val = hw->mac.ops.check_for_link(hw); | |
3870 | link_active = !hw->mac.get_link_status; | |
3871 | } else { | |
3872 | link_active = true; | |
3873 | } | |
3874 | break; | |
4d6b725e AD |
3875 | case e1000_media_type_internal_serdes: |
3876 | ret_val = hw->mac.ops.check_for_link(hw); | |
3877 | link_active = hw->mac.serdes_has_link; | |
3878 | break; | |
3879 | default: | |
3880 | case e1000_media_type_unknown: | |
3881 | break; | |
3882 | } | |
3883 | ||
3884 | return link_active; | |
3885 | } | |
3886 | ||
563988dc SA |
3887 | static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) |
3888 | { | |
3889 | bool ret = false; | |
3890 | u32 ctrl_ext, thstat; | |
3891 | ||
f96a8a0b | 3892 | /* check for thermal sensor event on i350 copper only */ |
563988dc SA |
3893 | if (hw->mac.type == e1000_i350) { |
3894 | thstat = rd32(E1000_THSTAT); | |
3895 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
3896 | ||
3897 | if ((hw->phy.media_type == e1000_media_type_copper) && | |
5c17a203 | 3898 | !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) |
563988dc | 3899 | ret = !!(thstat & event); |
563988dc SA |
3900 | } |
3901 | ||
3902 | return ret; | |
3903 | } | |
3904 | ||
9d5c8243 | 3905 | /** |
b980ac18 JK |
3906 | * igb_watchdog - Timer Call-back |
3907 | * @data: pointer to adapter cast into an unsigned long | |
9d5c8243 AK |
3908 | **/ |
3909 | static void igb_watchdog(unsigned long data) | |
3910 | { | |
3911 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
3912 | /* Do the rest outside of interrupt context */ | |
3913 | schedule_work(&adapter->watchdog_task); | |
3914 | } | |
3915 | ||
3916 | static void igb_watchdog_task(struct work_struct *work) | |
3917 | { | |
3918 | struct igb_adapter *adapter = container_of(work, | |
b980ac18 JK |
3919 | struct igb_adapter, |
3920 | watchdog_task); | |
9d5c8243 | 3921 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 3922 | struct net_device *netdev = adapter->netdev; |
563988dc | 3923 | u32 link; |
7a6ea550 | 3924 | int i; |
9d5c8243 | 3925 | |
4d6b725e | 3926 | link = igb_has_link(adapter); |
9d5c8243 | 3927 | if (link) { |
749ab2cd YZ |
3928 | /* Cancel scheduled suspend requests. */ |
3929 | pm_runtime_resume(netdev->dev.parent); | |
3930 | ||
9d5c8243 AK |
3931 | if (!netif_carrier_ok(netdev)) { |
3932 | u32 ctrl; | |
330a6d6a | 3933 | hw->mac.ops.get_speed_and_duplex(hw, |
b980ac18 JK |
3934 | &adapter->link_speed, |
3935 | &adapter->link_duplex); | |
9d5c8243 AK |
3936 | |
3937 | ctrl = rd32(E1000_CTRL); | |
527d47c1 | 3938 | /* Links status message must follow this format */ |
876d2d6f JK |
3939 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " |
3940 | "Duplex, Flow Control: %s\n", | |
559e9c49 AD |
3941 | netdev->name, |
3942 | adapter->link_speed, | |
3943 | adapter->link_duplex == FULL_DUPLEX ? | |
876d2d6f JK |
3944 | "Full" : "Half", |
3945 | (ctrl & E1000_CTRL_TFCE) && | |
3946 | (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : | |
3947 | (ctrl & E1000_CTRL_RFCE) ? "RX" : | |
3948 | (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); | |
9d5c8243 | 3949 | |
563988dc | 3950 | /* check for thermal sensor event */ |
876d2d6f JK |
3951 | if (igb_thermal_sensor_event(hw, |
3952 | E1000_THSTAT_LINK_THROTTLE)) { | |
3953 | netdev_info(netdev, "The network adapter link " | |
3954 | "speed was downshifted because it " | |
3955 | "overheated\n"); | |
7ef5ed1c | 3956 | } |
563988dc | 3957 | |
d07f3e37 | 3958 | /* adjust timeout factor according to speed/duplex */ |
9d5c8243 AK |
3959 | adapter->tx_timeout_factor = 1; |
3960 | switch (adapter->link_speed) { | |
3961 | case SPEED_10: | |
9d5c8243 AK |
3962 | adapter->tx_timeout_factor = 14; |
3963 | break; | |
3964 | case SPEED_100: | |
9d5c8243 AK |
3965 | /* maybe add some timeout factor ? */ |
3966 | break; | |
3967 | } | |
3968 | ||
3969 | netif_carrier_on(netdev); | |
9d5c8243 | 3970 | |
4ae196df | 3971 | igb_ping_all_vfs(adapter); |
17dc566c | 3972 | igb_check_vf_rate_limit(adapter); |
4ae196df | 3973 | |
4b1a9877 | 3974 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3975 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3976 | mod_timer(&adapter->phy_info_timer, | |
3977 | round_jiffies(jiffies + 2 * HZ)); | |
3978 | } | |
3979 | } else { | |
3980 | if (netif_carrier_ok(netdev)) { | |
3981 | adapter->link_speed = 0; | |
3982 | adapter->link_duplex = 0; | |
563988dc SA |
3983 | |
3984 | /* check for thermal sensor event */ | |
876d2d6f JK |
3985 | if (igb_thermal_sensor_event(hw, |
3986 | E1000_THSTAT_PWR_DOWN)) { | |
3987 | netdev_err(netdev, "The network adapter was " | |
3988 | "stopped because it overheated\n"); | |
7ef5ed1c | 3989 | } |
563988dc | 3990 | |
527d47c1 AD |
3991 | /* Links status message must follow this format */ |
3992 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
3993 | netdev->name); | |
9d5c8243 | 3994 | netif_carrier_off(netdev); |
4b1a9877 | 3995 | |
4ae196df AD |
3996 | igb_ping_all_vfs(adapter); |
3997 | ||
4b1a9877 | 3998 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3999 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
4000 | mod_timer(&adapter->phy_info_timer, | |
4001 | round_jiffies(jiffies + 2 * HZ)); | |
749ab2cd YZ |
4002 | |
4003 | pm_schedule_suspend(netdev->dev.parent, | |
4004 | MSEC_PER_SEC * 5); | |
9d5c8243 AK |
4005 | } |
4006 | } | |
4007 | ||
12dcd86b ED |
4008 | spin_lock(&adapter->stats64_lock); |
4009 | igb_update_stats(adapter, &adapter->stats64); | |
4010 | spin_unlock(&adapter->stats64_lock); | |
9d5c8243 | 4011 | |
dbabb065 | 4012 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 | 4013 | struct igb_ring *tx_ring = adapter->tx_ring[i]; |
dbabb065 | 4014 | if (!netif_carrier_ok(netdev)) { |
9d5c8243 AK |
4015 | /* We've lost link, so the controller stops DMA, |
4016 | * but we've got queued Tx work that's never going | |
4017 | * to get done, so reset controller to flush Tx. | |
b980ac18 JK |
4018 | * (Do the reset outside of interrupt context). |
4019 | */ | |
dbabb065 AD |
4020 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
4021 | adapter->tx_timeout_count++; | |
4022 | schedule_work(&adapter->reset_task); | |
4023 | /* return immediately since reset is imminent */ | |
4024 | return; | |
4025 | } | |
9d5c8243 | 4026 | } |
9d5c8243 | 4027 | |
dbabb065 | 4028 | /* Force detection of hung controller every watchdog period */ |
6d095fa8 | 4029 | set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
dbabb065 | 4030 | } |
f7ba205e | 4031 | |
b980ac18 | 4032 | /* Cause software interrupt to ensure Rx ring is cleaned */ |
7a6ea550 | 4033 | if (adapter->msix_entries) { |
047e0030 | 4034 | u32 eics = 0; |
0d1ae7f4 AD |
4035 | for (i = 0; i < adapter->num_q_vectors; i++) |
4036 | eics |= adapter->q_vector[i]->eims_value; | |
7a6ea550 AD |
4037 | wr32(E1000_EICS, eics); |
4038 | } else { | |
4039 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
4040 | } | |
9d5c8243 | 4041 | |
13800469 | 4042 | igb_spoof_check(adapter); |
fc580751 | 4043 | igb_ptp_rx_hang(adapter); |
13800469 | 4044 | |
9d5c8243 AK |
4045 | /* Reset the timer */ |
4046 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4047 | mod_timer(&adapter->watchdog_timer, | |
4048 | round_jiffies(jiffies + 2 * HZ)); | |
4049 | } | |
4050 | ||
4051 | enum latency_range { | |
4052 | lowest_latency = 0, | |
4053 | low_latency = 1, | |
4054 | bulk_latency = 2, | |
4055 | latency_invalid = 255 | |
4056 | }; | |
4057 | ||
6eb5a7f1 | 4058 | /** |
b980ac18 JK |
4059 | * igb_update_ring_itr - update the dynamic ITR value based on packet size |
4060 | * @q_vector: pointer to q_vector | |
6eb5a7f1 | 4061 | * |
b980ac18 JK |
4062 | * Stores a new ITR value based on strictly on packet size. This |
4063 | * algorithm is less sophisticated than that used in igb_update_itr, | |
4064 | * due to the difficulty of synchronizing statistics across multiple | |
4065 | * receive rings. The divisors and thresholds used by this function | |
4066 | * were determined based on theoretical maximum wire speed and testing | |
4067 | * data, in order to minimize response time while increasing bulk | |
4068 | * throughput. | |
4069 | * This functionality is controlled by the InterruptThrottleRate module | |
4070 | * parameter (see igb_param.c) | |
4071 | * NOTE: This function is called only when operating in a multiqueue | |
4072 | * receive environment. | |
6eb5a7f1 | 4073 | **/ |
047e0030 | 4074 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4075 | { |
047e0030 | 4076 | int new_val = q_vector->itr_val; |
6eb5a7f1 | 4077 | int avg_wire_size = 0; |
047e0030 | 4078 | struct igb_adapter *adapter = q_vector->adapter; |
12dcd86b | 4079 | unsigned int packets; |
9d5c8243 | 4080 | |
6eb5a7f1 AD |
4081 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
4082 | * ints/sec - ITR timer value of 120 ticks. | |
4083 | */ | |
4084 | if (adapter->link_speed != SPEED_1000) { | |
0ba82994 | 4085 | new_val = IGB_4K_ITR; |
6eb5a7f1 | 4086 | goto set_itr_val; |
9d5c8243 | 4087 | } |
047e0030 | 4088 | |
0ba82994 AD |
4089 | packets = q_vector->rx.total_packets; |
4090 | if (packets) | |
4091 | avg_wire_size = q_vector->rx.total_bytes / packets; | |
047e0030 | 4092 | |
0ba82994 AD |
4093 | packets = q_vector->tx.total_packets; |
4094 | if (packets) | |
4095 | avg_wire_size = max_t(u32, avg_wire_size, | |
4096 | q_vector->tx.total_bytes / packets); | |
047e0030 AD |
4097 | |
4098 | /* if avg_wire_size isn't set no work was done */ | |
4099 | if (!avg_wire_size) | |
4100 | goto clear_counts; | |
9d5c8243 | 4101 | |
6eb5a7f1 AD |
4102 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
4103 | avg_wire_size += 24; | |
4104 | ||
4105 | /* Don't starve jumbo frames */ | |
4106 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 4107 | |
6eb5a7f1 AD |
4108 | /* Give a little boost to mid-size frames */ |
4109 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
4110 | new_val = avg_wire_size / 3; | |
4111 | else | |
4112 | new_val = avg_wire_size / 2; | |
9d5c8243 | 4113 | |
0ba82994 AD |
4114 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
4115 | if (new_val < IGB_20K_ITR && | |
4116 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
4117 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
4118 | new_val = IGB_20K_ITR; | |
abe1c363 | 4119 | |
6eb5a7f1 | 4120 | set_itr_val: |
047e0030 AD |
4121 | if (new_val != q_vector->itr_val) { |
4122 | q_vector->itr_val = new_val; | |
4123 | q_vector->set_itr = 1; | |
9d5c8243 | 4124 | } |
6eb5a7f1 | 4125 | clear_counts: |
0ba82994 AD |
4126 | q_vector->rx.total_bytes = 0; |
4127 | q_vector->rx.total_packets = 0; | |
4128 | q_vector->tx.total_bytes = 0; | |
4129 | q_vector->tx.total_packets = 0; | |
9d5c8243 AK |
4130 | } |
4131 | ||
4132 | /** | |
b980ac18 JK |
4133 | * igb_update_itr - update the dynamic ITR value based on statistics |
4134 | * @q_vector: pointer to q_vector | |
4135 | * @ring_container: ring info to update the itr for | |
4136 | * | |
4137 | * Stores a new ITR value based on packets and byte | |
4138 | * counts during the last interrupt. The advantage of per interrupt | |
4139 | * computation is faster updates and more accurate ITR for the current | |
4140 | * traffic pattern. Constants in this function were computed | |
4141 | * based on theoretical maximum wire speed and thresholds were set based | |
4142 | * on testing data as well as attempting to minimize response time | |
4143 | * while increasing bulk throughput. | |
4144 | * this functionality is controlled by the InterruptThrottleRate module | |
4145 | * parameter (see igb_param.c) | |
4146 | * NOTE: These calculations are only valid when operating in a single- | |
4147 | * queue environment. | |
9d5c8243 | 4148 | **/ |
0ba82994 AD |
4149 | static void igb_update_itr(struct igb_q_vector *q_vector, |
4150 | struct igb_ring_container *ring_container) | |
9d5c8243 | 4151 | { |
0ba82994 AD |
4152 | unsigned int packets = ring_container->total_packets; |
4153 | unsigned int bytes = ring_container->total_bytes; | |
4154 | u8 itrval = ring_container->itr; | |
9d5c8243 | 4155 | |
0ba82994 | 4156 | /* no packets, exit with status unchanged */ |
9d5c8243 | 4157 | if (packets == 0) |
0ba82994 | 4158 | return; |
9d5c8243 | 4159 | |
0ba82994 | 4160 | switch (itrval) { |
9d5c8243 AK |
4161 | case lowest_latency: |
4162 | /* handle TSO and jumbo frames */ | |
4163 | if (bytes/packets > 8000) | |
0ba82994 | 4164 | itrval = bulk_latency; |
9d5c8243 | 4165 | else if ((packets < 5) && (bytes > 512)) |
0ba82994 | 4166 | itrval = low_latency; |
9d5c8243 AK |
4167 | break; |
4168 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
4169 | if (bytes > 10000) { | |
4170 | /* this if handles the TSO accounting */ | |
4171 | if (bytes/packets > 8000) { | |
0ba82994 | 4172 | itrval = bulk_latency; |
9d5c8243 | 4173 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { |
0ba82994 | 4174 | itrval = bulk_latency; |
9d5c8243 | 4175 | } else if ((packets > 35)) { |
0ba82994 | 4176 | itrval = lowest_latency; |
9d5c8243 AK |
4177 | } |
4178 | } else if (bytes/packets > 2000) { | |
0ba82994 | 4179 | itrval = bulk_latency; |
9d5c8243 | 4180 | } else if (packets <= 2 && bytes < 512) { |
0ba82994 | 4181 | itrval = lowest_latency; |
9d5c8243 AK |
4182 | } |
4183 | break; | |
4184 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
4185 | if (bytes > 25000) { | |
4186 | if (packets > 35) | |
0ba82994 | 4187 | itrval = low_latency; |
1e5c3d21 | 4188 | } else if (bytes < 1500) { |
0ba82994 | 4189 | itrval = low_latency; |
9d5c8243 AK |
4190 | } |
4191 | break; | |
4192 | } | |
4193 | ||
0ba82994 AD |
4194 | /* clear work counters since we have the values we need */ |
4195 | ring_container->total_bytes = 0; | |
4196 | ring_container->total_packets = 0; | |
4197 | ||
4198 | /* write updated itr to ring container */ | |
4199 | ring_container->itr = itrval; | |
9d5c8243 AK |
4200 | } |
4201 | ||
0ba82994 | 4202 | static void igb_set_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4203 | { |
0ba82994 | 4204 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 4205 | u32 new_itr = q_vector->itr_val; |
0ba82994 | 4206 | u8 current_itr = 0; |
9d5c8243 AK |
4207 | |
4208 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
4209 | if (adapter->link_speed != SPEED_1000) { | |
4210 | current_itr = 0; | |
0ba82994 | 4211 | new_itr = IGB_4K_ITR; |
9d5c8243 AK |
4212 | goto set_itr_now; |
4213 | } | |
4214 | ||
0ba82994 AD |
4215 | igb_update_itr(q_vector, &q_vector->tx); |
4216 | igb_update_itr(q_vector, &q_vector->rx); | |
9d5c8243 | 4217 | |
0ba82994 | 4218 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
9d5c8243 | 4219 | |
6eb5a7f1 | 4220 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
0ba82994 AD |
4221 | if (current_itr == lowest_latency && |
4222 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
4223 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
6eb5a7f1 AD |
4224 | current_itr = low_latency; |
4225 | ||
9d5c8243 AK |
4226 | switch (current_itr) { |
4227 | /* counts and packets in update_itr are dependent on these numbers */ | |
4228 | case lowest_latency: | |
0ba82994 | 4229 | new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ |
9d5c8243 AK |
4230 | break; |
4231 | case low_latency: | |
0ba82994 | 4232 | new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ |
9d5c8243 AK |
4233 | break; |
4234 | case bulk_latency: | |
0ba82994 | 4235 | new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ |
9d5c8243 AK |
4236 | break; |
4237 | default: | |
4238 | break; | |
4239 | } | |
4240 | ||
4241 | set_itr_now: | |
047e0030 | 4242 | if (new_itr != q_vector->itr_val) { |
9d5c8243 AK |
4243 | /* this attempts to bias the interrupt rate towards Bulk |
4244 | * by adding intermediate steps when interrupt rate is | |
b980ac18 JK |
4245 | * increasing |
4246 | */ | |
047e0030 | 4247 | new_itr = new_itr > q_vector->itr_val ? |
b980ac18 JK |
4248 | max((new_itr * q_vector->itr_val) / |
4249 | (new_itr + (q_vector->itr_val >> 2)), | |
4250 | new_itr) : new_itr; | |
9d5c8243 AK |
4251 | /* Don't write the value here; it resets the adapter's |
4252 | * internal timer, and causes us to delay far longer than | |
4253 | * we should between interrupts. Instead, we write the ITR | |
4254 | * value at the beginning of the next interrupt so the timing | |
4255 | * ends up being correct. | |
4256 | */ | |
047e0030 AD |
4257 | q_vector->itr_val = new_itr; |
4258 | q_vector->set_itr = 1; | |
9d5c8243 | 4259 | } |
9d5c8243 AK |
4260 | } |
4261 | ||
c50b52a0 SH |
4262 | static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, |
4263 | u32 type_tucmd, u32 mss_l4len_idx) | |
7d13a7d0 AD |
4264 | { |
4265 | struct e1000_adv_tx_context_desc *context_desc; | |
4266 | u16 i = tx_ring->next_to_use; | |
4267 | ||
4268 | context_desc = IGB_TX_CTXTDESC(tx_ring, i); | |
4269 | ||
4270 | i++; | |
4271 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
4272 | ||
4273 | /* set bits to identify this as an advanced context descriptor */ | |
4274 | type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; | |
4275 | ||
4276 | /* For 82575, context index must be unique per ring. */ | |
866cff06 | 4277 | if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) |
7d13a7d0 AD |
4278 | mss_l4len_idx |= tx_ring->reg_idx << 4; |
4279 | ||
4280 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4281 | context_desc->seqnum_seed = 0; | |
4282 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
4283 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
4284 | } | |
4285 | ||
7af40ad9 AD |
4286 | static int igb_tso(struct igb_ring *tx_ring, |
4287 | struct igb_tx_buffer *first, | |
4288 | u8 *hdr_len) | |
9d5c8243 | 4289 | { |
7af40ad9 | 4290 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4291 | u32 vlan_macip_lens, type_tucmd; |
4292 | u32 mss_l4len_idx, l4len; | |
4293 | ||
ed6aa105 AD |
4294 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
4295 | return 0; | |
4296 | ||
7d13a7d0 AD |
4297 | if (!skb_is_gso(skb)) |
4298 | return 0; | |
9d5c8243 AK |
4299 | |
4300 | if (skb_header_cloned(skb)) { | |
7af40ad9 | 4301 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
9d5c8243 AK |
4302 | if (err) |
4303 | return err; | |
4304 | } | |
4305 | ||
7d13a7d0 AD |
4306 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
4307 | type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; | |
9d5c8243 | 4308 | |
7af40ad9 | 4309 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
9d5c8243 AK |
4310 | struct iphdr *iph = ip_hdr(skb); |
4311 | iph->tot_len = 0; | |
4312 | iph->check = 0; | |
4313 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
4314 | iph->daddr, 0, | |
4315 | IPPROTO_TCP, | |
4316 | 0); | |
7d13a7d0 | 4317 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; |
7af40ad9 AD |
4318 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4319 | IGB_TX_FLAGS_CSUM | | |
4320 | IGB_TX_FLAGS_IPV4; | |
8e1e8a47 | 4321 | } else if (skb_is_gso_v6(skb)) { |
9d5c8243 AK |
4322 | ipv6_hdr(skb)->payload_len = 0; |
4323 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
4324 | &ipv6_hdr(skb)->daddr, | |
4325 | 0, IPPROTO_TCP, 0); | |
7af40ad9 AD |
4326 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4327 | IGB_TX_FLAGS_CSUM; | |
9d5c8243 AK |
4328 | } |
4329 | ||
7af40ad9 | 4330 | /* compute header lengths */ |
7d13a7d0 AD |
4331 | l4len = tcp_hdrlen(skb); |
4332 | *hdr_len = skb_transport_offset(skb) + l4len; | |
9d5c8243 | 4333 | |
7af40ad9 AD |
4334 | /* update gso size and bytecount with header size */ |
4335 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
4336 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
4337 | ||
9d5c8243 | 4338 | /* MSS L4LEN IDX */ |
7d13a7d0 AD |
4339 | mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; |
4340 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; | |
9d5c8243 | 4341 | |
7d13a7d0 AD |
4342 | /* VLAN MACLEN IPLEN */ |
4343 | vlan_macip_lens = skb_network_header_len(skb); | |
4344 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; | |
7af40ad9 | 4345 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4346 | |
7d13a7d0 | 4347 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 | 4348 | |
7d13a7d0 | 4349 | return 1; |
9d5c8243 AK |
4350 | } |
4351 | ||
7af40ad9 | 4352 | static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) |
9d5c8243 | 4353 | { |
7af40ad9 | 4354 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4355 | u32 vlan_macip_lens = 0; |
4356 | u32 mss_l4len_idx = 0; | |
4357 | u32 type_tucmd = 0; | |
9d5c8243 | 4358 | |
7d13a7d0 | 4359 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
7af40ad9 AD |
4360 | if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) |
4361 | return; | |
7d13a7d0 AD |
4362 | } else { |
4363 | u8 l4_hdr = 0; | |
7af40ad9 | 4364 | switch (first->protocol) { |
7d13a7d0 AD |
4365 | case __constant_htons(ETH_P_IP): |
4366 | vlan_macip_lens |= skb_network_header_len(skb); | |
4367 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; | |
4368 | l4_hdr = ip_hdr(skb)->protocol; | |
4369 | break; | |
4370 | case __constant_htons(ETH_P_IPV6): | |
4371 | vlan_macip_lens |= skb_network_header_len(skb); | |
4372 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
4373 | break; | |
4374 | default: | |
4375 | if (unlikely(net_ratelimit())) { | |
4376 | dev_warn(tx_ring->dev, | |
b980ac18 JK |
4377 | "partial checksum but proto=%x!\n", |
4378 | first->protocol); | |
fa4a7ef3 | 4379 | } |
7d13a7d0 AD |
4380 | break; |
4381 | } | |
fa4a7ef3 | 4382 | |
7d13a7d0 AD |
4383 | switch (l4_hdr) { |
4384 | case IPPROTO_TCP: | |
4385 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
4386 | mss_l4len_idx = tcp_hdrlen(skb) << | |
4387 | E1000_ADVTXD_L4LEN_SHIFT; | |
4388 | break; | |
4389 | case IPPROTO_SCTP: | |
4390 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
4391 | mss_l4len_idx = sizeof(struct sctphdr) << | |
4392 | E1000_ADVTXD_L4LEN_SHIFT; | |
4393 | break; | |
4394 | case IPPROTO_UDP: | |
4395 | mss_l4len_idx = sizeof(struct udphdr) << | |
4396 | E1000_ADVTXD_L4LEN_SHIFT; | |
4397 | break; | |
4398 | default: | |
4399 | if (unlikely(net_ratelimit())) { | |
4400 | dev_warn(tx_ring->dev, | |
b980ac18 JK |
4401 | "partial checksum but l4 proto=%x!\n", |
4402 | l4_hdr); | |
44b0cda3 | 4403 | } |
7d13a7d0 | 4404 | break; |
9d5c8243 | 4405 | } |
7af40ad9 AD |
4406 | |
4407 | /* update TX checksum flag */ | |
4408 | first->tx_flags |= IGB_TX_FLAGS_CSUM; | |
7d13a7d0 | 4409 | } |
9d5c8243 | 4410 | |
7d13a7d0 | 4411 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; |
7af40ad9 | 4412 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4413 | |
7d13a7d0 | 4414 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 AK |
4415 | } |
4416 | ||
1d9daf45 AD |
4417 | #define IGB_SET_FLAG(_input, _flag, _result) \ |
4418 | ((_flag <= _result) ? \ | |
4419 | ((u32)(_input & _flag) * (_result / _flag)) : \ | |
4420 | ((u32)(_input & _flag) / (_flag / _result))) | |
4421 | ||
4422 | static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) | |
e032afc8 AD |
4423 | { |
4424 | /* set type for advanced descriptor with frame checksum insertion */ | |
1d9daf45 AD |
4425 | u32 cmd_type = E1000_ADVTXD_DTYP_DATA | |
4426 | E1000_ADVTXD_DCMD_DEXT | | |
4427 | E1000_ADVTXD_DCMD_IFCS; | |
e032afc8 AD |
4428 | |
4429 | /* set HW vlan bit if vlan is present */ | |
1d9daf45 AD |
4430 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, |
4431 | (E1000_ADVTXD_DCMD_VLE)); | |
4432 | ||
4433 | /* set segmentation bits for TSO */ | |
4434 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, | |
4435 | (E1000_ADVTXD_DCMD_TSE)); | |
e032afc8 AD |
4436 | |
4437 | /* set timestamp bit if present */ | |
1d9daf45 AD |
4438 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, |
4439 | (E1000_ADVTXD_MAC_TSTAMP)); | |
e032afc8 | 4440 | |
1d9daf45 AD |
4441 | /* insert frame checksum */ |
4442 | cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); | |
e032afc8 AD |
4443 | |
4444 | return cmd_type; | |
4445 | } | |
4446 | ||
7af40ad9 AD |
4447 | static void igb_tx_olinfo_status(struct igb_ring *tx_ring, |
4448 | union e1000_adv_tx_desc *tx_desc, | |
4449 | u32 tx_flags, unsigned int paylen) | |
e032afc8 AD |
4450 | { |
4451 | u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; | |
4452 | ||
1d9daf45 AD |
4453 | /* 82575 requires a unique index per ring */ |
4454 | if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) | |
e032afc8 AD |
4455 | olinfo_status |= tx_ring->reg_idx << 4; |
4456 | ||
4457 | /* insert L4 checksum */ | |
1d9daf45 AD |
4458 | olinfo_status |= IGB_SET_FLAG(tx_flags, |
4459 | IGB_TX_FLAGS_CSUM, | |
4460 | (E1000_TXD_POPTS_TXSM << 8)); | |
e032afc8 | 4461 | |
1d9daf45 AD |
4462 | /* insert IPv4 checksum */ |
4463 | olinfo_status |= IGB_SET_FLAG(tx_flags, | |
4464 | IGB_TX_FLAGS_IPV4, | |
4465 | (E1000_TXD_POPTS_IXSM << 8)); | |
e032afc8 | 4466 | |
7af40ad9 | 4467 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
e032afc8 AD |
4468 | } |
4469 | ||
7af40ad9 AD |
4470 | static void igb_tx_map(struct igb_ring *tx_ring, |
4471 | struct igb_tx_buffer *first, | |
ebe42d16 | 4472 | const u8 hdr_len) |
9d5c8243 | 4473 | { |
7af40ad9 | 4474 | struct sk_buff *skb = first->skb; |
c9f14bf3 | 4475 | struct igb_tx_buffer *tx_buffer; |
ebe42d16 | 4476 | union e1000_adv_tx_desc *tx_desc; |
80d0759e | 4477 | struct skb_frag_struct *frag; |
ebe42d16 | 4478 | dma_addr_t dma; |
80d0759e | 4479 | unsigned int data_len, size; |
7af40ad9 | 4480 | u32 tx_flags = first->tx_flags; |
1d9daf45 | 4481 | u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); |
ebe42d16 | 4482 | u16 i = tx_ring->next_to_use; |
ebe42d16 AD |
4483 | |
4484 | tx_desc = IGB_TX_DESC(tx_ring, i); | |
4485 | ||
80d0759e AD |
4486 | igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); |
4487 | ||
4488 | size = skb_headlen(skb); | |
4489 | data_len = skb->data_len; | |
ebe42d16 AD |
4490 | |
4491 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
9d5c8243 | 4492 | |
80d0759e AD |
4493 | tx_buffer = first; |
4494 | ||
4495 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
4496 | if (dma_mapping_error(tx_ring->dev, dma)) | |
4497 | goto dma_error; | |
4498 | ||
4499 | /* record length, and DMA address */ | |
4500 | dma_unmap_len_set(tx_buffer, len, size); | |
4501 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
4502 | ||
4503 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
ebe42d16 | 4504 | |
ebe42d16 AD |
4505 | while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { |
4506 | tx_desc->read.cmd_type_len = | |
1d9daf45 | 4507 | cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); |
ebe42d16 AD |
4508 | |
4509 | i++; | |
4510 | tx_desc++; | |
4511 | if (i == tx_ring->count) { | |
4512 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
4513 | i = 0; | |
4514 | } | |
80d0759e | 4515 | tx_desc->read.olinfo_status = 0; |
ebe42d16 AD |
4516 | |
4517 | dma += IGB_MAX_DATA_PER_TXD; | |
4518 | size -= IGB_MAX_DATA_PER_TXD; | |
4519 | ||
ebe42d16 AD |
4520 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
4521 | } | |
4522 | ||
4523 | if (likely(!data_len)) | |
4524 | break; | |
2bbfebe2 | 4525 | |
1d9daf45 | 4526 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); |
9d5c8243 | 4527 | |
65689fef | 4528 | i++; |
ebe42d16 AD |
4529 | tx_desc++; |
4530 | if (i == tx_ring->count) { | |
4531 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
65689fef | 4532 | i = 0; |
ebe42d16 | 4533 | } |
80d0759e | 4534 | tx_desc->read.olinfo_status = 0; |
65689fef | 4535 | |
9e903e08 | 4536 | size = skb_frag_size(frag); |
ebe42d16 AD |
4537 | data_len -= size; |
4538 | ||
4539 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, | |
80d0759e | 4540 | size, DMA_TO_DEVICE); |
6366ad33 | 4541 | |
c9f14bf3 | 4542 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
9d5c8243 AK |
4543 | } |
4544 | ||
ebe42d16 | 4545 | /* write last descriptor with RS and EOP bits */ |
1d9daf45 AD |
4546 | cmd_type |= size | IGB_TXD_DCMD; |
4547 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); | |
8542db05 | 4548 | |
80d0759e AD |
4549 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
4550 | ||
8542db05 AD |
4551 | /* set the timestamp */ |
4552 | first->time_stamp = jiffies; | |
4553 | ||
b980ac18 | 4554 | /* Force memory writes to complete before letting h/w know there |
ebe42d16 AD |
4555 | * are new descriptors to fetch. (Only applicable for weak-ordered |
4556 | * memory model archs, such as IA-64). | |
4557 | * | |
4558 | * We also need this memory barrier to make certain all of the | |
4559 | * status bits have been updated before next_to_watch is written. | |
4560 | */ | |
4561 | wmb(); | |
4562 | ||
8542db05 | 4563 | /* set next_to_watch value indicating a packet is present */ |
ebe42d16 | 4564 | first->next_to_watch = tx_desc; |
9d5c8243 | 4565 | |
ebe42d16 AD |
4566 | i++; |
4567 | if (i == tx_ring->count) | |
4568 | i = 0; | |
6366ad33 | 4569 | |
ebe42d16 | 4570 | tx_ring->next_to_use = i; |
6366ad33 | 4571 | |
ebe42d16 | 4572 | writel(i, tx_ring->tail); |
6366ad33 | 4573 | |
ebe42d16 | 4574 | /* we need this if more than one processor can write to our tail |
b980ac18 JK |
4575 | * at a time, it synchronizes IO on IA64/Altix systems |
4576 | */ | |
ebe42d16 AD |
4577 | mmiowb(); |
4578 | ||
4579 | return; | |
4580 | ||
4581 | dma_error: | |
4582 | dev_err(tx_ring->dev, "TX DMA map failed\n"); | |
4583 | ||
4584 | /* clear dma mappings for failed tx_buffer_info map */ | |
4585 | for (;;) { | |
c9f14bf3 AD |
4586 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
4587 | igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
4588 | if (tx_buffer == first) | |
ebe42d16 | 4589 | break; |
a77ff709 NN |
4590 | if (i == 0) |
4591 | i = tx_ring->count; | |
6366ad33 | 4592 | i--; |
6366ad33 AD |
4593 | } |
4594 | ||
9d5c8243 | 4595 | tx_ring->next_to_use = i; |
9d5c8243 AK |
4596 | } |
4597 | ||
6ad4edfc | 4598 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4599 | { |
e694e964 AD |
4600 | struct net_device *netdev = tx_ring->netdev; |
4601 | ||
661086df | 4602 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 4603 | |
9d5c8243 AK |
4604 | /* Herbert's original patch had: |
4605 | * smp_mb__after_netif_stop_queue(); | |
b980ac18 JK |
4606 | * but since that doesn't exist yet, just open code it. |
4607 | */ | |
9d5c8243 AK |
4608 | smp_mb(); |
4609 | ||
4610 | /* We need to check again in a case another CPU has just | |
b980ac18 JK |
4611 | * made room available. |
4612 | */ | |
c493ea45 | 4613 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
4614 | return -EBUSY; |
4615 | ||
4616 | /* A reprieve! */ | |
661086df | 4617 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
12dcd86b ED |
4618 | |
4619 | u64_stats_update_begin(&tx_ring->tx_syncp2); | |
4620 | tx_ring->tx_stats.restart_queue2++; | |
4621 | u64_stats_update_end(&tx_ring->tx_syncp2); | |
4622 | ||
9d5c8243 AK |
4623 | return 0; |
4624 | } | |
4625 | ||
6ad4edfc | 4626 | static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4627 | { |
c493ea45 | 4628 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 | 4629 | return 0; |
e694e964 | 4630 | return __igb_maybe_stop_tx(tx_ring, size); |
9d5c8243 AK |
4631 | } |
4632 | ||
cd392f5c AD |
4633 | netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, |
4634 | struct igb_ring *tx_ring) | |
9d5c8243 | 4635 | { |
8542db05 | 4636 | struct igb_tx_buffer *first; |
ebe42d16 | 4637 | int tso; |
91d4ee33 | 4638 | u32 tx_flags = 0; |
21ba6fe1 | 4639 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
31f6adbb | 4640 | __be16 protocol = vlan_get_protocol(skb); |
91d4ee33 | 4641 | u8 hdr_len = 0; |
9d5c8243 | 4642 | |
21ba6fe1 AD |
4643 | /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, |
4644 | * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, | |
9d5c8243 | 4645 | * + 2 desc gap to keep tail from touching head, |
9d5c8243 | 4646 | * + 1 desc for context descriptor, |
21ba6fe1 AD |
4647 | * otherwise try next time |
4648 | */ | |
4649 | if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { | |
4650 | unsigned short f; | |
4651 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
4652 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
4653 | } else { | |
4654 | count += skb_shinfo(skb)->nr_frags; | |
4655 | } | |
4656 | ||
4657 | if (igb_maybe_stop_tx(tx_ring, count + 3)) { | |
9d5c8243 | 4658 | /* this is a hard error */ |
9d5c8243 AK |
4659 | return NETDEV_TX_BUSY; |
4660 | } | |
33af6bcc | 4661 | |
7af40ad9 AD |
4662 | /* record the location of the first descriptor for this packet */ |
4663 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
4664 | first->skb = skb; | |
4665 | first->bytecount = skb->len; | |
4666 | first->gso_segs = 1; | |
4667 | ||
b66e2397 MV |
4668 | skb_tx_timestamp(skb); |
4669 | ||
b646c22e AD |
4670 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { |
4671 | struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); | |
1f6e8178 | 4672 | |
b646c22e AD |
4673 | if (!(adapter->ptp_tx_skb)) { |
4674 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
4675 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | |
4676 | ||
4677 | adapter->ptp_tx_skb = skb_get(skb); | |
4678 | adapter->ptp_tx_start = jiffies; | |
4679 | if (adapter->hw.mac.type == e1000_82576) | |
4680 | schedule_work(&adapter->ptp_tx_work); | |
4681 | } | |
33af6bcc | 4682 | } |
9d5c8243 | 4683 | |
eab6d18d | 4684 | if (vlan_tx_tag_present(skb)) { |
9d5c8243 AK |
4685 | tx_flags |= IGB_TX_FLAGS_VLAN; |
4686 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
4687 | } | |
4688 | ||
7af40ad9 AD |
4689 | /* record initial flags and protocol */ |
4690 | first->tx_flags = tx_flags; | |
4691 | first->protocol = protocol; | |
cdfd01fc | 4692 | |
7af40ad9 AD |
4693 | tso = igb_tso(tx_ring, first, &hdr_len); |
4694 | if (tso < 0) | |
7d13a7d0 | 4695 | goto out_drop; |
7af40ad9 AD |
4696 | else if (!tso) |
4697 | igb_tx_csum(tx_ring, first); | |
9d5c8243 | 4698 | |
7af40ad9 | 4699 | igb_tx_map(tx_ring, first, hdr_len); |
85ad76b2 AD |
4700 | |
4701 | /* Make sure there is space in the ring for the next send. */ | |
21ba6fe1 | 4702 | igb_maybe_stop_tx(tx_ring, DESC_NEEDED); |
85ad76b2 | 4703 | |
9d5c8243 | 4704 | return NETDEV_TX_OK; |
7d13a7d0 AD |
4705 | |
4706 | out_drop: | |
7af40ad9 AD |
4707 | igb_unmap_and_free_tx_resource(tx_ring, first); |
4708 | ||
7d13a7d0 | 4709 | return NETDEV_TX_OK; |
9d5c8243 AK |
4710 | } |
4711 | ||
1cc3bd87 AD |
4712 | static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, |
4713 | struct sk_buff *skb) | |
4714 | { | |
4715 | unsigned int r_idx = skb->queue_mapping; | |
4716 | ||
4717 | if (r_idx >= adapter->num_tx_queues) | |
4718 | r_idx = r_idx % adapter->num_tx_queues; | |
4719 | ||
4720 | return adapter->tx_ring[r_idx]; | |
4721 | } | |
4722 | ||
cd392f5c AD |
4723 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, |
4724 | struct net_device *netdev) | |
9d5c8243 AK |
4725 | { |
4726 | struct igb_adapter *adapter = netdev_priv(netdev); | |
b1a436c3 AD |
4727 | |
4728 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
4729 | dev_kfree_skb_any(skb); | |
4730 | return NETDEV_TX_OK; | |
4731 | } | |
4732 | ||
4733 | if (skb->len <= 0) { | |
4734 | dev_kfree_skb_any(skb); | |
4735 | return NETDEV_TX_OK; | |
4736 | } | |
4737 | ||
b980ac18 | 4738 | /* The minimum packet size with TCTL.PSP set is 17 so pad the skb |
1cc3bd87 AD |
4739 | * in order to meet this minimum size requirement. |
4740 | */ | |
ea5ceeab TD |
4741 | if (unlikely(skb->len < 17)) { |
4742 | if (skb_pad(skb, 17 - skb->len)) | |
1cc3bd87 AD |
4743 | return NETDEV_TX_OK; |
4744 | skb->len = 17; | |
ea5ceeab | 4745 | skb_set_tail_pointer(skb, 17); |
1cc3bd87 | 4746 | } |
9d5c8243 | 4747 | |
1cc3bd87 | 4748 | return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); |
9d5c8243 AK |
4749 | } |
4750 | ||
4751 | /** | |
b980ac18 JK |
4752 | * igb_tx_timeout - Respond to a Tx Hang |
4753 | * @netdev: network interface device structure | |
9d5c8243 AK |
4754 | **/ |
4755 | static void igb_tx_timeout(struct net_device *netdev) | |
4756 | { | |
4757 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4758 | struct e1000_hw *hw = &adapter->hw; | |
4759 | ||
4760 | /* Do the reset outside of interrupt context */ | |
4761 | adapter->tx_timeout_count++; | |
f7ba205e | 4762 | |
06218a8d | 4763 | if (hw->mac.type >= e1000_82580) |
55cac248 AD |
4764 | hw->dev_spec._82575.global_device_reset = true; |
4765 | ||
9d5c8243 | 4766 | schedule_work(&adapter->reset_task); |
265de409 AD |
4767 | wr32(E1000_EICS, |
4768 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
4769 | } |
4770 | ||
4771 | static void igb_reset_task(struct work_struct *work) | |
4772 | { | |
4773 | struct igb_adapter *adapter; | |
4774 | adapter = container_of(work, struct igb_adapter, reset_task); | |
4775 | ||
c97ec42a TI |
4776 | igb_dump(adapter); |
4777 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
9d5c8243 AK |
4778 | igb_reinit_locked(adapter); |
4779 | } | |
4780 | ||
4781 | /** | |
b980ac18 JK |
4782 | * igb_get_stats64 - Get System Network Statistics |
4783 | * @netdev: network interface device structure | |
4784 | * @stats: rtnl_link_stats64 pointer | |
9d5c8243 | 4785 | **/ |
12dcd86b | 4786 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, |
b980ac18 | 4787 | struct rtnl_link_stats64 *stats) |
9d5c8243 | 4788 | { |
12dcd86b ED |
4789 | struct igb_adapter *adapter = netdev_priv(netdev); |
4790 | ||
4791 | spin_lock(&adapter->stats64_lock); | |
4792 | igb_update_stats(adapter, &adapter->stats64); | |
4793 | memcpy(stats, &adapter->stats64, sizeof(*stats)); | |
4794 | spin_unlock(&adapter->stats64_lock); | |
4795 | ||
4796 | return stats; | |
9d5c8243 AK |
4797 | } |
4798 | ||
4799 | /** | |
b980ac18 JK |
4800 | * igb_change_mtu - Change the Maximum Transfer Unit |
4801 | * @netdev: network interface device structure | |
4802 | * @new_mtu: new value for maximum frame size | |
9d5c8243 | 4803 | * |
b980ac18 | 4804 | * Returns 0 on success, negative on failure |
9d5c8243 AK |
4805 | **/ |
4806 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
4807 | { | |
4808 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4809 | struct pci_dev *pdev = adapter->pdev; |
153285f9 | 4810 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
9d5c8243 | 4811 | |
c809d227 | 4812 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
090b1795 | 4813 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
9d5c8243 AK |
4814 | return -EINVAL; |
4815 | } | |
4816 | ||
153285f9 | 4817 | #define MAX_STD_JUMBO_FRAME_SIZE 9238 |
9d5c8243 | 4818 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
090b1795 | 4819 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
9d5c8243 AK |
4820 | return -EINVAL; |
4821 | } | |
4822 | ||
4823 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
4824 | msleep(1); | |
73cd78f1 | 4825 | |
9d5c8243 AK |
4826 | /* igb_down has a dependency on max_frame_size */ |
4827 | adapter->max_frame_size = max_frame; | |
559e9c49 | 4828 | |
4c844851 AD |
4829 | if (netif_running(netdev)) |
4830 | igb_down(adapter); | |
9d5c8243 | 4831 | |
090b1795 | 4832 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
9d5c8243 AK |
4833 | netdev->mtu, new_mtu); |
4834 | netdev->mtu = new_mtu; | |
4835 | ||
4836 | if (netif_running(netdev)) | |
4837 | igb_up(adapter); | |
4838 | else | |
4839 | igb_reset(adapter); | |
4840 | ||
4841 | clear_bit(__IGB_RESETTING, &adapter->state); | |
4842 | ||
4843 | return 0; | |
4844 | } | |
4845 | ||
4846 | /** | |
b980ac18 JK |
4847 | * igb_update_stats - Update the board statistics counters |
4848 | * @adapter: board private structure | |
9d5c8243 | 4849 | **/ |
12dcd86b ED |
4850 | void igb_update_stats(struct igb_adapter *adapter, |
4851 | struct rtnl_link_stats64 *net_stats) | |
9d5c8243 AK |
4852 | { |
4853 | struct e1000_hw *hw = &adapter->hw; | |
4854 | struct pci_dev *pdev = adapter->pdev; | |
fa3d9a6d | 4855 | u32 reg, mpc; |
9d5c8243 | 4856 | u16 phy_tmp; |
3f9c0164 AD |
4857 | int i; |
4858 | u64 bytes, packets; | |
12dcd86b ED |
4859 | unsigned int start; |
4860 | u64 _bytes, _packets; | |
9d5c8243 AK |
4861 | |
4862 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
4863 | ||
b980ac18 | 4864 | /* Prevent stats update while adapter is being reset, or if the pci |
9d5c8243 AK |
4865 | * connection is down. |
4866 | */ | |
4867 | if (adapter->link_speed == 0) | |
4868 | return; | |
4869 | if (pci_channel_offline(pdev)) | |
4870 | return; | |
4871 | ||
3f9c0164 AD |
4872 | bytes = 0; |
4873 | packets = 0; | |
4874 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
ae1c07a6 | 4875 | u32 rqdpc = rd32(E1000_RQDPC(i)); |
3025a446 | 4876 | struct igb_ring *ring = adapter->rx_ring[i]; |
12dcd86b | 4877 | |
ae1c07a6 AD |
4878 | if (rqdpc) { |
4879 | ring->rx_stats.drops += rqdpc; | |
4880 | net_stats->rx_fifo_errors += rqdpc; | |
4881 | } | |
12dcd86b ED |
4882 | |
4883 | do { | |
4884 | start = u64_stats_fetch_begin_bh(&ring->rx_syncp); | |
4885 | _bytes = ring->rx_stats.bytes; | |
4886 | _packets = ring->rx_stats.packets; | |
4887 | } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); | |
4888 | bytes += _bytes; | |
4889 | packets += _packets; | |
3f9c0164 AD |
4890 | } |
4891 | ||
128e45eb AD |
4892 | net_stats->rx_bytes = bytes; |
4893 | net_stats->rx_packets = packets; | |
3f9c0164 AD |
4894 | |
4895 | bytes = 0; | |
4896 | packets = 0; | |
4897 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 4898 | struct igb_ring *ring = adapter->tx_ring[i]; |
12dcd86b ED |
4899 | do { |
4900 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp); | |
4901 | _bytes = ring->tx_stats.bytes; | |
4902 | _packets = ring->tx_stats.packets; | |
4903 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); | |
4904 | bytes += _bytes; | |
4905 | packets += _packets; | |
3f9c0164 | 4906 | } |
128e45eb AD |
4907 | net_stats->tx_bytes = bytes; |
4908 | net_stats->tx_packets = packets; | |
3f9c0164 AD |
4909 | |
4910 | /* read stats registers */ | |
9d5c8243 AK |
4911 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
4912 | adapter->stats.gprc += rd32(E1000_GPRC); | |
4913 | adapter->stats.gorc += rd32(E1000_GORCL); | |
4914 | rd32(E1000_GORCH); /* clear GORCL */ | |
4915 | adapter->stats.bprc += rd32(E1000_BPRC); | |
4916 | adapter->stats.mprc += rd32(E1000_MPRC); | |
4917 | adapter->stats.roc += rd32(E1000_ROC); | |
4918 | ||
4919 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
4920 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
4921 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
4922 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
4923 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
4924 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
4925 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
4926 | adapter->stats.sec += rd32(E1000_SEC); | |
4927 | ||
fa3d9a6d MW |
4928 | mpc = rd32(E1000_MPC); |
4929 | adapter->stats.mpc += mpc; | |
4930 | net_stats->rx_fifo_errors += mpc; | |
9d5c8243 AK |
4931 | adapter->stats.scc += rd32(E1000_SCC); |
4932 | adapter->stats.ecol += rd32(E1000_ECOL); | |
4933 | adapter->stats.mcc += rd32(E1000_MCC); | |
4934 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
4935 | adapter->stats.dc += rd32(E1000_DC); | |
4936 | adapter->stats.rlec += rd32(E1000_RLEC); | |
4937 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
4938 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
4939 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
4940 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
4941 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
4942 | adapter->stats.gptc += rd32(E1000_GPTC); | |
4943 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
4944 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
fa3d9a6d | 4945 | adapter->stats.rnbc += rd32(E1000_RNBC); |
9d5c8243 AK |
4946 | adapter->stats.ruc += rd32(E1000_RUC); |
4947 | adapter->stats.rfc += rd32(E1000_RFC); | |
4948 | adapter->stats.rjc += rd32(E1000_RJC); | |
4949 | adapter->stats.tor += rd32(E1000_TORH); | |
4950 | adapter->stats.tot += rd32(E1000_TOTH); | |
4951 | adapter->stats.tpr += rd32(E1000_TPR); | |
4952 | ||
4953 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
4954 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
4955 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
4956 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
4957 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
4958 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
4959 | ||
4960 | adapter->stats.mptc += rd32(E1000_MPTC); | |
4961 | adapter->stats.bptc += rd32(E1000_BPTC); | |
4962 | ||
2d0b0f69 NN |
4963 | adapter->stats.tpt += rd32(E1000_TPT); |
4964 | adapter->stats.colc += rd32(E1000_COLC); | |
9d5c8243 AK |
4965 | |
4966 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
43915c7c NN |
4967 | /* read internal phy specific stats */ |
4968 | reg = rd32(E1000_CTRL_EXT); | |
4969 | if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { | |
4970 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3dbdf969 CW |
4971 | |
4972 | /* this stat has invalid values on i210/i211 */ | |
4973 | if ((hw->mac.type != e1000_i210) && | |
4974 | (hw->mac.type != e1000_i211)) | |
4975 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
43915c7c NN |
4976 | } |
4977 | ||
9d5c8243 AK |
4978 | adapter->stats.tsctc += rd32(E1000_TSCTC); |
4979 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
4980 | ||
4981 | adapter->stats.iac += rd32(E1000_IAC); | |
4982 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
4983 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
4984 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
4985 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
4986 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
4987 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
4988 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
4989 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
4990 | ||
4991 | /* Fill out the OS statistics structure */ | |
128e45eb AD |
4992 | net_stats->multicast = adapter->stats.mprc; |
4993 | net_stats->collisions = adapter->stats.colc; | |
9d5c8243 AK |
4994 | |
4995 | /* Rx Errors */ | |
4996 | ||
4997 | /* RLEC on some newer hardware can be incorrect so build | |
b980ac18 JK |
4998 | * our own version based on RUC and ROC |
4999 | */ | |
128e45eb | 5000 | net_stats->rx_errors = adapter->stats.rxerrc + |
9d5c8243 AK |
5001 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
5002 | adapter->stats.ruc + adapter->stats.roc + | |
5003 | adapter->stats.cexterr; | |
128e45eb AD |
5004 | net_stats->rx_length_errors = adapter->stats.ruc + |
5005 | adapter->stats.roc; | |
5006 | net_stats->rx_crc_errors = adapter->stats.crcerrs; | |
5007 | net_stats->rx_frame_errors = adapter->stats.algnerrc; | |
5008 | net_stats->rx_missed_errors = adapter->stats.mpc; | |
9d5c8243 AK |
5009 | |
5010 | /* Tx Errors */ | |
128e45eb AD |
5011 | net_stats->tx_errors = adapter->stats.ecol + |
5012 | adapter->stats.latecol; | |
5013 | net_stats->tx_aborted_errors = adapter->stats.ecol; | |
5014 | net_stats->tx_window_errors = adapter->stats.latecol; | |
5015 | net_stats->tx_carrier_errors = adapter->stats.tncrs; | |
9d5c8243 AK |
5016 | |
5017 | /* Tx Dropped needs to be maintained elsewhere */ | |
5018 | ||
5019 | /* Phy Stats */ | |
5020 | if (hw->phy.media_type == e1000_media_type_copper) { | |
5021 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 5022 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
5023 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
5024 | adapter->phy_stats.idle_errors += phy_tmp; | |
5025 | } | |
5026 | } | |
5027 | ||
5028 | /* Management Stats */ | |
5029 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
5030 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
5031 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
0a915b95 CW |
5032 | |
5033 | /* OS2BMC Stats */ | |
5034 | reg = rd32(E1000_MANC); | |
5035 | if (reg & E1000_MANC_EN_BMC2OS) { | |
5036 | adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); | |
5037 | adapter->stats.o2bspc += rd32(E1000_O2BSPC); | |
5038 | adapter->stats.b2ospc += rd32(E1000_B2OSPC); | |
5039 | adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); | |
5040 | } | |
9d5c8243 AK |
5041 | } |
5042 | ||
9d5c8243 AK |
5043 | static irqreturn_t igb_msix_other(int irq, void *data) |
5044 | { | |
047e0030 | 5045 | struct igb_adapter *adapter = data; |
9d5c8243 | 5046 | struct e1000_hw *hw = &adapter->hw; |
844290e5 | 5047 | u32 icr = rd32(E1000_ICR); |
844290e5 | 5048 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 | 5049 | |
7f081d40 AD |
5050 | if (icr & E1000_ICR_DRSTA) |
5051 | schedule_work(&adapter->reset_task); | |
5052 | ||
047e0030 | 5053 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5054 | /* HW is reporting DMA is out of sync */ |
5055 | adapter->stats.doosync++; | |
13800469 GR |
5056 | /* The DMA Out of Sync is also indication of a spoof event |
5057 | * in IOV mode. Check the Wrong VM Behavior register to | |
b980ac18 JK |
5058 | * see if it is really a spoof event. |
5059 | */ | |
13800469 | 5060 | igb_check_wvbr(adapter); |
dda0e083 | 5061 | } |
eebbbdba | 5062 | |
4ae196df AD |
5063 | /* Check for a mailbox event */ |
5064 | if (icr & E1000_ICR_VMMB) | |
5065 | igb_msg_task(adapter); | |
5066 | ||
5067 | if (icr & E1000_ICR_LSC) { | |
5068 | hw->mac.get_link_status = 1; | |
5069 | /* guard against interrupt when we're going down */ | |
5070 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5071 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5072 | } | |
5073 | ||
1f6e8178 MV |
5074 | if (icr & E1000_ICR_TS) { |
5075 | u32 tsicr = rd32(E1000_TSICR); | |
5076 | ||
5077 | if (tsicr & E1000_TSICR_TXTS) { | |
5078 | /* acknowledge the interrupt */ | |
5079 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5080 | /* retrieve hardware timestamp */ | |
5081 | schedule_work(&adapter->ptp_tx_work); | |
5082 | } | |
5083 | } | |
1f6e8178 | 5084 | |
844290e5 | 5085 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
5086 | |
5087 | return IRQ_HANDLED; | |
5088 | } | |
5089 | ||
047e0030 | 5090 | static void igb_write_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 5091 | { |
26b39276 | 5092 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 5093 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
9d5c8243 | 5094 | |
047e0030 AD |
5095 | if (!q_vector->set_itr) |
5096 | return; | |
73cd78f1 | 5097 | |
047e0030 AD |
5098 | if (!itr_val) |
5099 | itr_val = 0x4; | |
661086df | 5100 | |
26b39276 AD |
5101 | if (adapter->hw.mac.type == e1000_82575) |
5102 | itr_val |= itr_val << 16; | |
661086df | 5103 | else |
0ba82994 | 5104 | itr_val |= E1000_EITR_CNT_IGNR; |
661086df | 5105 | |
047e0030 AD |
5106 | writel(itr_val, q_vector->itr_register); |
5107 | q_vector->set_itr = 0; | |
6eb5a7f1 AD |
5108 | } |
5109 | ||
047e0030 | 5110 | static irqreturn_t igb_msix_ring(int irq, void *data) |
9d5c8243 | 5111 | { |
047e0030 | 5112 | struct igb_q_vector *q_vector = data; |
9d5c8243 | 5113 | |
047e0030 AD |
5114 | /* Write the ITR value calculated from the previous interrupt. */ |
5115 | igb_write_itr(q_vector); | |
9d5c8243 | 5116 | |
047e0030 | 5117 | napi_schedule(&q_vector->napi); |
844290e5 | 5118 | |
047e0030 | 5119 | return IRQ_HANDLED; |
fe4506b6 JC |
5120 | } |
5121 | ||
421e02f0 | 5122 | #ifdef CONFIG_IGB_DCA |
6a05004a AD |
5123 | static void igb_update_tx_dca(struct igb_adapter *adapter, |
5124 | struct igb_ring *tx_ring, | |
5125 | int cpu) | |
5126 | { | |
5127 | struct e1000_hw *hw = &adapter->hw; | |
5128 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); | |
5129 | ||
5130 | if (hw->mac.type != e1000_82575) | |
5131 | txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; | |
5132 | ||
b980ac18 | 5133 | /* We can enable relaxed ordering for reads, but not writes when |
6a05004a AD |
5134 | * DCA is enabled. This is due to a known issue in some chipsets |
5135 | * which will cause the DCA tag to be cleared. | |
5136 | */ | |
5137 | txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | | |
5138 | E1000_DCA_TXCTRL_DATA_RRO_EN | | |
5139 | E1000_DCA_TXCTRL_DESC_DCA_EN; | |
5140 | ||
5141 | wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); | |
5142 | } | |
5143 | ||
5144 | static void igb_update_rx_dca(struct igb_adapter *adapter, | |
5145 | struct igb_ring *rx_ring, | |
5146 | int cpu) | |
5147 | { | |
5148 | struct e1000_hw *hw = &adapter->hw; | |
5149 | u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); | |
5150 | ||
5151 | if (hw->mac.type != e1000_82575) | |
5152 | rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; | |
5153 | ||
b980ac18 | 5154 | /* We can enable relaxed ordering for reads, but not writes when |
6a05004a AD |
5155 | * DCA is enabled. This is due to a known issue in some chipsets |
5156 | * which will cause the DCA tag to be cleared. | |
5157 | */ | |
5158 | rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | | |
5159 | E1000_DCA_RXCTRL_DESC_DCA_EN; | |
5160 | ||
5161 | wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); | |
5162 | } | |
5163 | ||
047e0030 | 5164 | static void igb_update_dca(struct igb_q_vector *q_vector) |
fe4506b6 | 5165 | { |
047e0030 | 5166 | struct igb_adapter *adapter = q_vector->adapter; |
fe4506b6 | 5167 | int cpu = get_cpu(); |
fe4506b6 | 5168 | |
047e0030 AD |
5169 | if (q_vector->cpu == cpu) |
5170 | goto out_no_update; | |
5171 | ||
6a05004a AD |
5172 | if (q_vector->tx.ring) |
5173 | igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); | |
5174 | ||
5175 | if (q_vector->rx.ring) | |
5176 | igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); | |
5177 | ||
047e0030 AD |
5178 | q_vector->cpu = cpu; |
5179 | out_no_update: | |
fe4506b6 JC |
5180 | put_cpu(); |
5181 | } | |
5182 | ||
5183 | static void igb_setup_dca(struct igb_adapter *adapter) | |
5184 | { | |
7e0e99ef | 5185 | struct e1000_hw *hw = &adapter->hw; |
fe4506b6 JC |
5186 | int i; |
5187 | ||
7dfc16fa | 5188 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
5189 | return; |
5190 | ||
7e0e99ef AD |
5191 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
5192 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | |
5193 | ||
047e0030 | 5194 | for (i = 0; i < adapter->num_q_vectors; i++) { |
26b39276 AD |
5195 | adapter->q_vector[i]->cpu = -1; |
5196 | igb_update_dca(adapter->q_vector[i]); | |
fe4506b6 JC |
5197 | } |
5198 | } | |
5199 | ||
5200 | static int __igb_notify_dca(struct device *dev, void *data) | |
5201 | { | |
5202 | struct net_device *netdev = dev_get_drvdata(dev); | |
5203 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 5204 | struct pci_dev *pdev = adapter->pdev; |
fe4506b6 JC |
5205 | struct e1000_hw *hw = &adapter->hw; |
5206 | unsigned long event = *(unsigned long *)data; | |
5207 | ||
5208 | switch (event) { | |
5209 | case DCA_PROVIDER_ADD: | |
5210 | /* if already enabled, don't do it again */ | |
7dfc16fa | 5211 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 5212 | break; |
fe4506b6 | 5213 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 5214 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
090b1795 | 5215 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
5216 | igb_setup_dca(adapter); |
5217 | break; | |
5218 | } | |
5219 | /* Fall Through since DCA is disabled. */ | |
5220 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 5221 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 | 5222 | /* without this a class_device is left |
b980ac18 JK |
5223 | * hanging around in the sysfs model |
5224 | */ | |
fe4506b6 | 5225 | dca_remove_requester(dev); |
090b1795 | 5226 | dev_info(&pdev->dev, "DCA disabled\n"); |
7dfc16fa | 5227 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 5228 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
5229 | } |
5230 | break; | |
5231 | } | |
bbd98fe4 | 5232 | |
fe4506b6 | 5233 | return 0; |
9d5c8243 AK |
5234 | } |
5235 | ||
fe4506b6 | 5236 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
b980ac18 | 5237 | void *p) |
fe4506b6 JC |
5238 | { |
5239 | int ret_val; | |
5240 | ||
5241 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
b980ac18 | 5242 | __igb_notify_dca); |
fe4506b6 JC |
5243 | |
5244 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5245 | } | |
421e02f0 | 5246 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 5247 | |
0224d663 GR |
5248 | #ifdef CONFIG_PCI_IOV |
5249 | static int igb_vf_configure(struct igb_adapter *adapter, int vf) | |
5250 | { | |
5251 | unsigned char mac_addr[ETH_ALEN]; | |
0224d663 | 5252 | |
5ac6f91d | 5253 | eth_zero_addr(mac_addr); |
0224d663 GR |
5254 | igb_set_vf_mac(adapter, vf, mac_addr); |
5255 | ||
70ea4783 LL |
5256 | /* By default spoof check is enabled for all VFs */ |
5257 | adapter->vf_data[vf].spoofchk_enabled = true; | |
5258 | ||
f557147c | 5259 | return 0; |
0224d663 GR |
5260 | } |
5261 | ||
f557147c | 5262 | static bool igb_vfs_are_assigned(struct igb_adapter *adapter) |
0224d663 | 5263 | { |
0224d663 | 5264 | struct pci_dev *pdev = adapter->pdev; |
f557147c SA |
5265 | struct pci_dev *vfdev; |
5266 | int dev_id; | |
0224d663 GR |
5267 | |
5268 | switch (adapter->hw.mac.type) { | |
5269 | case e1000_82576: | |
f557147c | 5270 | dev_id = IGB_82576_VF_DEV_ID; |
0224d663 GR |
5271 | break; |
5272 | case e1000_i350: | |
f557147c | 5273 | dev_id = IGB_I350_VF_DEV_ID; |
0224d663 GR |
5274 | break; |
5275 | default: | |
f557147c | 5276 | return false; |
0224d663 GR |
5277 | } |
5278 | ||
f557147c SA |
5279 | /* loop through all the VFs to see if we own any that are assigned */ |
5280 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); | |
5281 | while (vfdev) { | |
5282 | /* if we don't own it we don't care */ | |
5283 | if (vfdev->is_virtfn && vfdev->physfn == pdev) { | |
5284 | /* if it is assigned we cannot release it */ | |
5285 | if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) | |
0224d663 GR |
5286 | return true; |
5287 | } | |
f557147c SA |
5288 | |
5289 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); | |
0224d663 | 5290 | } |
f557147c | 5291 | |
0224d663 GR |
5292 | return false; |
5293 | } | |
5294 | ||
5295 | #endif | |
4ae196df AD |
5296 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
5297 | { | |
5298 | struct e1000_hw *hw = &adapter->hw; | |
5299 | u32 ping; | |
5300 | int i; | |
5301 | ||
5302 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
5303 | ping = E1000_PF_CONTROL_MSG; | |
f2ca0dbe | 5304 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
4ae196df AD |
5305 | ping |= E1000_VT_MSGTYPE_CTS; |
5306 | igb_write_mbx(hw, &ping, 1, i); | |
5307 | } | |
5308 | } | |
5309 | ||
7d5753f0 AD |
5310 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
5311 | { | |
5312 | struct e1000_hw *hw = &adapter->hw; | |
5313 | u32 vmolr = rd32(E1000_VMOLR(vf)); | |
5314 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5315 | ||
d85b9004 | 5316 | vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | |
b980ac18 | 5317 | IGB_VF_FLAG_MULTI_PROMISC); |
7d5753f0 AD |
5318 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); |
5319 | ||
5320 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | |
5321 | vmolr |= E1000_VMOLR_MPME; | |
d85b9004 | 5322 | vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; |
7d5753f0 AD |
5323 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; |
5324 | } else { | |
b980ac18 | 5325 | /* if we have hashes and we are clearing a multicast promisc |
7d5753f0 AD |
5326 | * flag we need to write the hashes to the MTA as this step |
5327 | * was previously skipped | |
5328 | */ | |
5329 | if (vf_data->num_vf_mc_hashes > 30) { | |
5330 | vmolr |= E1000_VMOLR_MPME; | |
5331 | } else if (vf_data->num_vf_mc_hashes) { | |
5332 | int j; | |
5333 | vmolr |= E1000_VMOLR_ROMPE; | |
5334 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5335 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5336 | } | |
5337 | } | |
5338 | ||
5339 | wr32(E1000_VMOLR(vf), vmolr); | |
5340 | ||
5341 | /* there are flags left unprocessed, likely not supported */ | |
5342 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | |
5343 | return -EINVAL; | |
5344 | ||
5345 | return 0; | |
7d5753f0 AD |
5346 | } |
5347 | ||
4ae196df AD |
5348 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
5349 | u32 *msgbuf, u32 vf) | |
5350 | { | |
5351 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5352 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
5353 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5354 | int i; | |
5355 | ||
7d5753f0 | 5356 | /* salt away the number of multicast addresses assigned |
4ae196df AD |
5357 | * to this VF for later use to restore when the PF multi cast |
5358 | * list changes | |
5359 | */ | |
5360 | vf_data->num_vf_mc_hashes = n; | |
5361 | ||
7d5753f0 AD |
5362 | /* only up to 30 hash values supported */ |
5363 | if (n > 30) | |
5364 | n = 30; | |
5365 | ||
5366 | /* store the hashes for later use */ | |
4ae196df | 5367 | for (i = 0; i < n; i++) |
a419aef8 | 5368 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
4ae196df AD |
5369 | |
5370 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5371 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5372 | |
5373 | return 0; | |
5374 | } | |
5375 | ||
5376 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
5377 | { | |
5378 | struct e1000_hw *hw = &adapter->hw; | |
5379 | struct vf_data_storage *vf_data; | |
5380 | int i, j; | |
5381 | ||
5382 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7d5753f0 AD |
5383 | u32 vmolr = rd32(E1000_VMOLR(i)); |
5384 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
5385 | ||
4ae196df | 5386 | vf_data = &adapter->vf_data[i]; |
7d5753f0 AD |
5387 | |
5388 | if ((vf_data->num_vf_mc_hashes > 30) || | |
5389 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | |
5390 | vmolr |= E1000_VMOLR_MPME; | |
5391 | } else if (vf_data->num_vf_mc_hashes) { | |
5392 | vmolr |= E1000_VMOLR_ROMPE; | |
5393 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5394 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5395 | } | |
5396 | wr32(E1000_VMOLR(i), vmolr); | |
4ae196df AD |
5397 | } |
5398 | } | |
5399 | ||
5400 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
5401 | { | |
5402 | struct e1000_hw *hw = &adapter->hw; | |
5403 | u32 pool_mask, reg, vid; | |
5404 | int i; | |
5405 | ||
5406 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5407 | ||
5408 | /* Find the vlan filter for this id */ | |
5409 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5410 | reg = rd32(E1000_VLVF(i)); | |
5411 | ||
5412 | /* remove the vf from the pool */ | |
5413 | reg &= ~pool_mask; | |
5414 | ||
5415 | /* if pool is empty then remove entry from vfta */ | |
5416 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
5417 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
5418 | reg = 0; | |
5419 | vid = reg & E1000_VLVF_VLANID_MASK; | |
5420 | igb_vfta_set(hw, vid, false); | |
5421 | } | |
5422 | ||
5423 | wr32(E1000_VLVF(i), reg); | |
5424 | } | |
ae641bdc AD |
5425 | |
5426 | adapter->vf_data[vf].vlans_enabled = 0; | |
4ae196df AD |
5427 | } |
5428 | ||
5429 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
5430 | { | |
5431 | struct e1000_hw *hw = &adapter->hw; | |
5432 | u32 reg, i; | |
5433 | ||
51466239 AD |
5434 | /* The vlvf table only exists on 82576 hardware and newer */ |
5435 | if (hw->mac.type < e1000_82576) | |
5436 | return -1; | |
5437 | ||
5438 | /* we only need to do this if VMDq is enabled */ | |
4ae196df AD |
5439 | if (!adapter->vfs_allocated_count) |
5440 | return -1; | |
5441 | ||
5442 | /* Find the vlan filter for this id */ | |
5443 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5444 | reg = rd32(E1000_VLVF(i)); | |
5445 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
5446 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
5447 | break; | |
5448 | } | |
5449 | ||
5450 | if (add) { | |
5451 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
5452 | /* Did not find a matching VLAN ID entry that was | |
5453 | * enabled. Search for a free filter entry, i.e. | |
5454 | * one without the enable bit set | |
5455 | */ | |
5456 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5457 | reg = rd32(E1000_VLVF(i)); | |
5458 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
5459 | break; | |
5460 | } | |
5461 | } | |
5462 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5463 | /* Found an enabled/available entry */ | |
5464 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5465 | ||
5466 | /* if !enabled we need to set this up in vfta */ | |
5467 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
51466239 AD |
5468 | /* add VID to filter table */ |
5469 | igb_vfta_set(hw, vid, true); | |
4ae196df AD |
5470 | reg |= E1000_VLVF_VLANID_ENABLE; |
5471 | } | |
cad6d05f AD |
5472 | reg &= ~E1000_VLVF_VLANID_MASK; |
5473 | reg |= vid; | |
4ae196df | 5474 | wr32(E1000_VLVF(i), reg); |
ae641bdc AD |
5475 | |
5476 | /* do not modify RLPML for PF devices */ | |
5477 | if (vf >= adapter->vfs_allocated_count) | |
5478 | return 0; | |
5479 | ||
5480 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5481 | u32 size; | |
5482 | reg = rd32(E1000_VMOLR(vf)); | |
5483 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5484 | size += 4; | |
5485 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5486 | reg |= size; | |
5487 | wr32(E1000_VMOLR(vf), reg); | |
5488 | } | |
ae641bdc | 5489 | |
51466239 | 5490 | adapter->vf_data[vf].vlans_enabled++; |
4ae196df AD |
5491 | } |
5492 | } else { | |
5493 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5494 | /* remove vf from the pool */ | |
5495 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
5496 | /* if pool is empty then remove entry from vfta */ | |
5497 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
5498 | reg = 0; | |
5499 | igb_vfta_set(hw, vid, false); | |
5500 | } | |
5501 | wr32(E1000_VLVF(i), reg); | |
ae641bdc AD |
5502 | |
5503 | /* do not modify RLPML for PF devices */ | |
5504 | if (vf >= adapter->vfs_allocated_count) | |
5505 | return 0; | |
5506 | ||
5507 | adapter->vf_data[vf].vlans_enabled--; | |
5508 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5509 | u32 size; | |
5510 | reg = rd32(E1000_VMOLR(vf)); | |
5511 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5512 | size -= 4; | |
5513 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5514 | reg |= size; | |
5515 | wr32(E1000_VMOLR(vf), reg); | |
5516 | } | |
4ae196df AD |
5517 | } |
5518 | } | |
8151d294 WM |
5519 | return 0; |
5520 | } | |
5521 | ||
5522 | static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) | |
5523 | { | |
5524 | struct e1000_hw *hw = &adapter->hw; | |
5525 | ||
5526 | if (vid) | |
5527 | wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); | |
5528 | else | |
5529 | wr32(E1000_VMVIR(vf), 0); | |
5530 | } | |
5531 | ||
5532 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
5533 | int vf, u16 vlan, u8 qos) | |
5534 | { | |
5535 | int err = 0; | |
5536 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5537 | ||
5538 | if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) | |
5539 | return -EINVAL; | |
5540 | if (vlan || qos) { | |
5541 | err = igb_vlvf_set(adapter, vlan, !!vlan, vf); | |
5542 | if (err) | |
5543 | goto out; | |
5544 | igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); | |
5545 | igb_set_vmolr(adapter, vf, !vlan); | |
5546 | adapter->vf_data[vf].pf_vlan = vlan; | |
5547 | adapter->vf_data[vf].pf_qos = qos; | |
5548 | dev_info(&adapter->pdev->dev, | |
5549 | "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); | |
5550 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
5551 | dev_warn(&adapter->pdev->dev, | |
b980ac18 | 5552 | "The VF VLAN has been set, but the PF device is not up.\n"); |
8151d294 | 5553 | dev_warn(&adapter->pdev->dev, |
b980ac18 | 5554 | "Bring the PF device up before attempting to use the VF device.\n"); |
8151d294 WM |
5555 | } |
5556 | } else { | |
5557 | igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, | |
b980ac18 | 5558 | false, vf); |
8151d294 WM |
5559 | igb_set_vmvir(adapter, vlan, vf); |
5560 | igb_set_vmolr(adapter, vf, true); | |
5561 | adapter->vf_data[vf].pf_vlan = 0; | |
5562 | adapter->vf_data[vf].pf_qos = 0; | |
b980ac18 | 5563 | } |
8151d294 | 5564 | out: |
b980ac18 | 5565 | return err; |
4ae196df AD |
5566 | } |
5567 | ||
5568 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |
5569 | { | |
5570 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5571 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
5572 | ||
5573 | return igb_vlvf_set(adapter, vid, add, vf); | |
5574 | } | |
5575 | ||
f2ca0dbe | 5576 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5577 | { |
8fa7e0f7 GR |
5578 | /* clear flags - except flag that indicates PF has set the MAC */ |
5579 | adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; | |
f2ca0dbe | 5580 | adapter->vf_data[vf].last_nack = jiffies; |
4ae196df AD |
5581 | |
5582 | /* reset offloads to defaults */ | |
8151d294 | 5583 | igb_set_vmolr(adapter, vf, true); |
4ae196df AD |
5584 | |
5585 | /* reset vlans for device */ | |
5586 | igb_clear_vf_vfta(adapter, vf); | |
8151d294 WM |
5587 | if (adapter->vf_data[vf].pf_vlan) |
5588 | igb_ndo_set_vf_vlan(adapter->netdev, vf, | |
5589 | adapter->vf_data[vf].pf_vlan, | |
5590 | adapter->vf_data[vf].pf_qos); | |
5591 | else | |
5592 | igb_clear_vf_vfta(adapter, vf); | |
4ae196df AD |
5593 | |
5594 | /* reset multicast table array for vf */ | |
5595 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
5596 | ||
5597 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5598 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5599 | } |
5600 | ||
f2ca0dbe AD |
5601 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
5602 | { | |
5603 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
5604 | ||
5ac6f91d | 5605 | /* clear mac address as we were hotplug removed/added */ |
8151d294 | 5606 | if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) |
5ac6f91d | 5607 | eth_zero_addr(vf_mac); |
f2ca0dbe AD |
5608 | |
5609 | /* process remaining reset events */ | |
5610 | igb_vf_reset(adapter, vf); | |
5611 | } | |
5612 | ||
5613 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
4ae196df AD |
5614 | { |
5615 | struct e1000_hw *hw = &adapter->hw; | |
5616 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
ff41f8dc | 5617 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df AD |
5618 | u32 reg, msgbuf[3]; |
5619 | u8 *addr = (u8 *)(&msgbuf[1]); | |
5620 | ||
5621 | /* process all the same items cleared in a function level reset */ | |
f2ca0dbe | 5622 | igb_vf_reset(adapter, vf); |
4ae196df AD |
5623 | |
5624 | /* set vf mac address */ | |
26ad9178 | 5625 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4ae196df AD |
5626 | |
5627 | /* enable transmit and receive for vf */ | |
5628 | reg = rd32(E1000_VFTE); | |
5629 | wr32(E1000_VFTE, reg | (1 << vf)); | |
5630 | reg = rd32(E1000_VFRE); | |
5631 | wr32(E1000_VFRE, reg | (1 << vf)); | |
5632 | ||
8fa7e0f7 | 5633 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; |
4ae196df AD |
5634 | |
5635 | /* reply to reset with ack and vf mac address */ | |
5636 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
5637 | memcpy(addr, vf_mac, 6); | |
5638 | igb_write_mbx(hw, msgbuf, 3, vf); | |
5639 | } | |
5640 | ||
5641 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
5642 | { | |
b980ac18 | 5643 | /* The VF MAC Address is stored in a packed array of bytes |
de42edde GR |
5644 | * starting at the second 32 bit word of the msg array |
5645 | */ | |
f2ca0dbe AD |
5646 | unsigned char *addr = (char *)&msg[1]; |
5647 | int err = -1; | |
4ae196df | 5648 | |
f2ca0dbe AD |
5649 | if (is_valid_ether_addr(addr)) |
5650 | err = igb_set_vf_mac(adapter, vf, addr); | |
4ae196df | 5651 | |
f2ca0dbe | 5652 | return err; |
4ae196df AD |
5653 | } |
5654 | ||
5655 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
5656 | { | |
5657 | struct e1000_hw *hw = &adapter->hw; | |
f2ca0dbe | 5658 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5659 | u32 msg = E1000_VT_MSGTYPE_NACK; |
5660 | ||
5661 | /* if device isn't clear to send it shouldn't be reading either */ | |
f2ca0dbe AD |
5662 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
5663 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4ae196df | 5664 | igb_write_mbx(hw, &msg, 1, vf); |
f2ca0dbe | 5665 | vf_data->last_nack = jiffies; |
4ae196df AD |
5666 | } |
5667 | } | |
5668 | ||
f2ca0dbe | 5669 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5670 | { |
f2ca0dbe AD |
5671 | struct pci_dev *pdev = adapter->pdev; |
5672 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; | |
4ae196df | 5673 | struct e1000_hw *hw = &adapter->hw; |
f2ca0dbe | 5674 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5675 | s32 retval; |
5676 | ||
f2ca0dbe | 5677 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4ae196df | 5678 | |
fef45f4c AD |
5679 | if (retval) { |
5680 | /* if receive failed revoke VF CTS stats and restart init */ | |
f2ca0dbe | 5681 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
fef45f4c AD |
5682 | vf_data->flags &= ~IGB_VF_FLAG_CTS; |
5683 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) | |
5684 | return; | |
5685 | goto out; | |
5686 | } | |
4ae196df AD |
5687 | |
5688 | /* this is a message we already processed, do nothing */ | |
5689 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
f2ca0dbe | 5690 | return; |
4ae196df | 5691 | |
b980ac18 | 5692 | /* until the vf completes a reset it should not be |
4ae196df AD |
5693 | * allowed to start any configuration. |
5694 | */ | |
4ae196df AD |
5695 | if (msgbuf[0] == E1000_VF_RESET) { |
5696 | igb_vf_reset_msg(adapter, vf); | |
f2ca0dbe | 5697 | return; |
4ae196df AD |
5698 | } |
5699 | ||
f2ca0dbe | 5700 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
fef45f4c AD |
5701 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
5702 | return; | |
5703 | retval = -1; | |
5704 | goto out; | |
4ae196df AD |
5705 | } |
5706 | ||
5707 | switch ((msgbuf[0] & 0xFFFF)) { | |
5708 | case E1000_VF_SET_MAC_ADDR: | |
a6b5ea35 GR |
5709 | retval = -EINVAL; |
5710 | if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) | |
5711 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
5712 | else | |
5713 | dev_warn(&pdev->dev, | |
b980ac18 JK |
5714 | "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", |
5715 | vf); | |
4ae196df | 5716 | break; |
7d5753f0 AD |
5717 | case E1000_VF_SET_PROMISC: |
5718 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | |
5719 | break; | |
4ae196df AD |
5720 | case E1000_VF_SET_MULTICAST: |
5721 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
5722 | break; | |
5723 | case E1000_VF_SET_LPE: | |
5724 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
5725 | break; | |
5726 | case E1000_VF_SET_VLAN: | |
a6b5ea35 GR |
5727 | retval = -1; |
5728 | if (vf_data->pf_vlan) | |
5729 | dev_warn(&pdev->dev, | |
b980ac18 JK |
5730 | "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", |
5731 | vf); | |
8151d294 WM |
5732 | else |
5733 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4ae196df AD |
5734 | break; |
5735 | default: | |
090b1795 | 5736 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4ae196df AD |
5737 | retval = -1; |
5738 | break; | |
5739 | } | |
5740 | ||
fef45f4c AD |
5741 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; |
5742 | out: | |
4ae196df AD |
5743 | /* notify the VF of the results of what it sent us */ |
5744 | if (retval) | |
5745 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
5746 | else | |
5747 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
5748 | ||
4ae196df | 5749 | igb_write_mbx(hw, msgbuf, 1, vf); |
f2ca0dbe | 5750 | } |
4ae196df | 5751 | |
f2ca0dbe AD |
5752 | static void igb_msg_task(struct igb_adapter *adapter) |
5753 | { | |
5754 | struct e1000_hw *hw = &adapter->hw; | |
5755 | u32 vf; | |
5756 | ||
5757 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
5758 | /* process any reset requests */ | |
5759 | if (!igb_check_for_rst(hw, vf)) | |
5760 | igb_vf_reset_event(adapter, vf); | |
5761 | ||
5762 | /* process any messages pending */ | |
5763 | if (!igb_check_for_msg(hw, vf)) | |
5764 | igb_rcv_msg_from_vf(adapter, vf); | |
5765 | ||
5766 | /* process any acks */ | |
5767 | if (!igb_check_for_ack(hw, vf)) | |
5768 | igb_rcv_ack_from_vf(adapter, vf); | |
5769 | } | |
4ae196df AD |
5770 | } |
5771 | ||
68d480c4 AD |
5772 | /** |
5773 | * igb_set_uta - Set unicast filter table address | |
5774 | * @adapter: board private structure | |
5775 | * | |
5776 | * The unicast table address is a register array of 32-bit registers. | |
5777 | * The table is meant to be used in a way similar to how the MTA is used | |
5778 | * however due to certain limitations in the hardware it is necessary to | |
25985edc LDM |
5779 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous |
5780 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
68d480c4 AD |
5781 | **/ |
5782 | static void igb_set_uta(struct igb_adapter *adapter) | |
5783 | { | |
5784 | struct e1000_hw *hw = &adapter->hw; | |
5785 | int i; | |
5786 | ||
5787 | /* The UTA table only exists on 82576 hardware and newer */ | |
5788 | if (hw->mac.type < e1000_82576) | |
5789 | return; | |
5790 | ||
5791 | /* we only need to do this if VMDq is enabled */ | |
5792 | if (!adapter->vfs_allocated_count) | |
5793 | return; | |
5794 | ||
5795 | for (i = 0; i < hw->mac.uta_reg_count; i++) | |
5796 | array_wr32(E1000_UTA, i, ~0); | |
5797 | } | |
5798 | ||
9d5c8243 | 5799 | /** |
b980ac18 JK |
5800 | * igb_intr_msi - Interrupt Handler |
5801 | * @irq: interrupt number | |
5802 | * @data: pointer to a network interface device structure | |
9d5c8243 AK |
5803 | **/ |
5804 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
5805 | { | |
047e0030 AD |
5806 | struct igb_adapter *adapter = data; |
5807 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5808 | struct e1000_hw *hw = &adapter->hw; |
5809 | /* read ICR disables interrupts using IAM */ | |
5810 | u32 icr = rd32(E1000_ICR); | |
5811 | ||
047e0030 | 5812 | igb_write_itr(q_vector); |
9d5c8243 | 5813 | |
7f081d40 AD |
5814 | if (icr & E1000_ICR_DRSTA) |
5815 | schedule_work(&adapter->reset_task); | |
5816 | ||
047e0030 | 5817 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5818 | /* HW is reporting DMA is out of sync */ |
5819 | adapter->stats.doosync++; | |
5820 | } | |
5821 | ||
9d5c8243 AK |
5822 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5823 | hw->mac.get_link_status = 1; | |
5824 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5825 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5826 | } | |
5827 | ||
1f6e8178 MV |
5828 | if (icr & E1000_ICR_TS) { |
5829 | u32 tsicr = rd32(E1000_TSICR); | |
5830 | ||
5831 | if (tsicr & E1000_TSICR_TXTS) { | |
5832 | /* acknowledge the interrupt */ | |
5833 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5834 | /* retrieve hardware timestamp */ | |
5835 | schedule_work(&adapter->ptp_tx_work); | |
5836 | } | |
5837 | } | |
1f6e8178 | 5838 | |
047e0030 | 5839 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5840 | |
5841 | return IRQ_HANDLED; | |
5842 | } | |
5843 | ||
5844 | /** | |
b980ac18 JK |
5845 | * igb_intr - Legacy Interrupt Handler |
5846 | * @irq: interrupt number | |
5847 | * @data: pointer to a network interface device structure | |
9d5c8243 AK |
5848 | **/ |
5849 | static irqreturn_t igb_intr(int irq, void *data) | |
5850 | { | |
047e0030 AD |
5851 | struct igb_adapter *adapter = data; |
5852 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5853 | struct e1000_hw *hw = &adapter->hw; |
5854 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
b980ac18 JK |
5855 | * need for the IMC write |
5856 | */ | |
9d5c8243 | 5857 | u32 icr = rd32(E1000_ICR); |
9d5c8243 AK |
5858 | |
5859 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
b980ac18 JK |
5860 | * not set, then the adapter didn't send an interrupt |
5861 | */ | |
9d5c8243 AK |
5862 | if (!(icr & E1000_ICR_INT_ASSERTED)) |
5863 | return IRQ_NONE; | |
5864 | ||
0ba82994 AD |
5865 | igb_write_itr(q_vector); |
5866 | ||
7f081d40 AD |
5867 | if (icr & E1000_ICR_DRSTA) |
5868 | schedule_work(&adapter->reset_task); | |
5869 | ||
047e0030 | 5870 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5871 | /* HW is reporting DMA is out of sync */ |
5872 | adapter->stats.doosync++; | |
5873 | } | |
5874 | ||
9d5c8243 AK |
5875 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5876 | hw->mac.get_link_status = 1; | |
5877 | /* guard against interrupt when we're going down */ | |
5878 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5879 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5880 | } | |
5881 | ||
1f6e8178 MV |
5882 | if (icr & E1000_ICR_TS) { |
5883 | u32 tsicr = rd32(E1000_TSICR); | |
5884 | ||
5885 | if (tsicr & E1000_TSICR_TXTS) { | |
5886 | /* acknowledge the interrupt */ | |
5887 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5888 | /* retrieve hardware timestamp */ | |
5889 | schedule_work(&adapter->ptp_tx_work); | |
5890 | } | |
5891 | } | |
1f6e8178 | 5892 | |
047e0030 | 5893 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5894 | |
5895 | return IRQ_HANDLED; | |
5896 | } | |
5897 | ||
c50b52a0 | 5898 | static void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
9d5c8243 | 5899 | { |
047e0030 | 5900 | struct igb_adapter *adapter = q_vector->adapter; |
46544258 | 5901 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5902 | |
0ba82994 AD |
5903 | if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || |
5904 | (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { | |
5905 | if ((adapter->num_q_vectors == 1) && !adapter->vf_data) | |
5906 | igb_set_itr(q_vector); | |
46544258 | 5907 | else |
047e0030 | 5908 | igb_update_ring_itr(q_vector); |
9d5c8243 AK |
5909 | } |
5910 | ||
46544258 AD |
5911 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
5912 | if (adapter->msix_entries) | |
047e0030 | 5913 | wr32(E1000_EIMS, q_vector->eims_value); |
46544258 AD |
5914 | else |
5915 | igb_irq_enable(adapter); | |
5916 | } | |
9d5c8243 AK |
5917 | } |
5918 | ||
46544258 | 5919 | /** |
b980ac18 JK |
5920 | * igb_poll - NAPI Rx polling callback |
5921 | * @napi: napi polling structure | |
5922 | * @budget: count of how many packets we should handle | |
46544258 AD |
5923 | **/ |
5924 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 | 5925 | { |
047e0030 | 5926 | struct igb_q_vector *q_vector = container_of(napi, |
b980ac18 JK |
5927 | struct igb_q_vector, |
5928 | napi); | |
16eb8815 | 5929 | bool clean_complete = true; |
9d5c8243 | 5930 | |
421e02f0 | 5931 | #ifdef CONFIG_IGB_DCA |
047e0030 AD |
5932 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
5933 | igb_update_dca(q_vector); | |
fe4506b6 | 5934 | #endif |
0ba82994 | 5935 | if (q_vector->tx.ring) |
13fde97a | 5936 | clean_complete = igb_clean_tx_irq(q_vector); |
9d5c8243 | 5937 | |
0ba82994 | 5938 | if (q_vector->rx.ring) |
cd392f5c | 5939 | clean_complete &= igb_clean_rx_irq(q_vector, budget); |
047e0030 | 5940 | |
16eb8815 AD |
5941 | /* If all work not completed, return budget and keep polling */ |
5942 | if (!clean_complete) | |
5943 | return budget; | |
46544258 | 5944 | |
9d5c8243 | 5945 | /* If not enough Rx work done, exit the polling mode */ |
16eb8815 AD |
5946 | napi_complete(napi); |
5947 | igb_ring_irq_enable(q_vector); | |
9d5c8243 | 5948 | |
16eb8815 | 5949 | return 0; |
9d5c8243 | 5950 | } |
6d8126f9 | 5951 | |
9d5c8243 | 5952 | /** |
b980ac18 JK |
5953 | * igb_clean_tx_irq - Reclaim resources after transmit completes |
5954 | * @q_vector: pointer to q_vector containing needed info | |
49ce9c2c | 5955 | * |
b980ac18 | 5956 | * returns true if ring is completely cleaned |
9d5c8243 | 5957 | **/ |
047e0030 | 5958 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
9d5c8243 | 5959 | { |
047e0030 | 5960 | struct igb_adapter *adapter = q_vector->adapter; |
0ba82994 | 5961 | struct igb_ring *tx_ring = q_vector->tx.ring; |
06034649 | 5962 | struct igb_tx_buffer *tx_buffer; |
f4128785 | 5963 | union e1000_adv_tx_desc *tx_desc; |
9d5c8243 | 5964 | unsigned int total_bytes = 0, total_packets = 0; |
0ba82994 | 5965 | unsigned int budget = q_vector->tx.work_limit; |
8542db05 | 5966 | unsigned int i = tx_ring->next_to_clean; |
9d5c8243 | 5967 | |
13fde97a AD |
5968 | if (test_bit(__IGB_DOWN, &adapter->state)) |
5969 | return true; | |
0e014cb1 | 5970 | |
06034649 | 5971 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
13fde97a | 5972 | tx_desc = IGB_TX_DESC(tx_ring, i); |
8542db05 | 5973 | i -= tx_ring->count; |
9d5c8243 | 5974 | |
f4128785 AD |
5975 | do { |
5976 | union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; | |
8542db05 AD |
5977 | |
5978 | /* if next_to_watch is not set then there is no work pending */ | |
5979 | if (!eop_desc) | |
5980 | break; | |
13fde97a | 5981 | |
f4128785 | 5982 | /* prevent any other reads prior to eop_desc */ |
70d289bc | 5983 | read_barrier_depends(); |
f4128785 | 5984 | |
13fde97a AD |
5985 | /* if DD is not set pending work has not been completed */ |
5986 | if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) | |
5987 | break; | |
5988 | ||
8542db05 AD |
5989 | /* clear next_to_watch to prevent false hangs */ |
5990 | tx_buffer->next_to_watch = NULL; | |
9d5c8243 | 5991 | |
ebe42d16 AD |
5992 | /* update the statistics for this packet */ |
5993 | total_bytes += tx_buffer->bytecount; | |
5994 | total_packets += tx_buffer->gso_segs; | |
13fde97a | 5995 | |
ebe42d16 AD |
5996 | /* free the skb */ |
5997 | dev_kfree_skb_any(tx_buffer->skb); | |
13fde97a | 5998 | |
ebe42d16 AD |
5999 | /* unmap skb header data */ |
6000 | dma_unmap_single(tx_ring->dev, | |
c9f14bf3 AD |
6001 | dma_unmap_addr(tx_buffer, dma), |
6002 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
6003 | DMA_TO_DEVICE); |
6004 | ||
c9f14bf3 AD |
6005 | /* clear tx_buffer data */ |
6006 | tx_buffer->skb = NULL; | |
6007 | dma_unmap_len_set(tx_buffer, len, 0); | |
6008 | ||
ebe42d16 AD |
6009 | /* clear last DMA location and unmap remaining buffers */ |
6010 | while (tx_desc != eop_desc) { | |
13fde97a AD |
6011 | tx_buffer++; |
6012 | tx_desc++; | |
9d5c8243 | 6013 | i++; |
8542db05 AD |
6014 | if (unlikely(!i)) { |
6015 | i -= tx_ring->count; | |
06034649 | 6016 | tx_buffer = tx_ring->tx_buffer_info; |
13fde97a AD |
6017 | tx_desc = IGB_TX_DESC(tx_ring, 0); |
6018 | } | |
ebe42d16 AD |
6019 | |
6020 | /* unmap any remaining paged data */ | |
c9f14bf3 | 6021 | if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 6022 | dma_unmap_page(tx_ring->dev, |
c9f14bf3 AD |
6023 | dma_unmap_addr(tx_buffer, dma), |
6024 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 6025 | DMA_TO_DEVICE); |
c9f14bf3 | 6026 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 AD |
6027 | } |
6028 | } | |
6029 | ||
ebe42d16 AD |
6030 | /* move us one more past the eop_desc for start of next pkt */ |
6031 | tx_buffer++; | |
6032 | tx_desc++; | |
6033 | i++; | |
6034 | if (unlikely(!i)) { | |
6035 | i -= tx_ring->count; | |
6036 | tx_buffer = tx_ring->tx_buffer_info; | |
6037 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
6038 | } | |
f4128785 AD |
6039 | |
6040 | /* issue prefetch for next Tx descriptor */ | |
6041 | prefetch(tx_desc); | |
6042 | ||
6043 | /* update budget accounting */ | |
6044 | budget--; | |
6045 | } while (likely(budget)); | |
0e014cb1 | 6046 | |
bdbc0631 ED |
6047 | netdev_tx_completed_queue(txring_txq(tx_ring), |
6048 | total_packets, total_bytes); | |
8542db05 | 6049 | i += tx_ring->count; |
9d5c8243 | 6050 | tx_ring->next_to_clean = i; |
13fde97a AD |
6051 | u64_stats_update_begin(&tx_ring->tx_syncp); |
6052 | tx_ring->tx_stats.bytes += total_bytes; | |
6053 | tx_ring->tx_stats.packets += total_packets; | |
6054 | u64_stats_update_end(&tx_ring->tx_syncp); | |
0ba82994 AD |
6055 | q_vector->tx.total_bytes += total_bytes; |
6056 | q_vector->tx.total_packets += total_packets; | |
9d5c8243 | 6057 | |
6d095fa8 | 6058 | if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { |
13fde97a | 6059 | struct e1000_hw *hw = &adapter->hw; |
12dcd86b | 6060 | |
9d5c8243 | 6061 | /* Detect a transmit hang in hardware, this serializes the |
b980ac18 JK |
6062 | * check with the clearing of time_stamp and movement of i |
6063 | */ | |
6d095fa8 | 6064 | clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
f4128785 | 6065 | if (tx_buffer->next_to_watch && |
8542db05 | 6066 | time_after(jiffies, tx_buffer->time_stamp + |
8e95a202 JP |
6067 | (adapter->tx_timeout_factor * HZ)) && |
6068 | !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { | |
9d5c8243 | 6069 | |
9d5c8243 | 6070 | /* detected Tx unit hang */ |
59d71989 | 6071 | dev_err(tx_ring->dev, |
9d5c8243 | 6072 | "Detected Tx Unit Hang\n" |
2d064c06 | 6073 | " Tx Queue <%d>\n" |
9d5c8243 AK |
6074 | " TDH <%x>\n" |
6075 | " TDT <%x>\n" | |
6076 | " next_to_use <%x>\n" | |
6077 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
6078 | "buffer_info[next_to_clean]\n" |
6079 | " time_stamp <%lx>\n" | |
8542db05 | 6080 | " next_to_watch <%p>\n" |
9d5c8243 AK |
6081 | " jiffies <%lx>\n" |
6082 | " desc.status <%x>\n", | |
2d064c06 | 6083 | tx_ring->queue_index, |
238ac817 | 6084 | rd32(E1000_TDH(tx_ring->reg_idx)), |
fce99e34 | 6085 | readl(tx_ring->tail), |
9d5c8243 AK |
6086 | tx_ring->next_to_use, |
6087 | tx_ring->next_to_clean, | |
8542db05 | 6088 | tx_buffer->time_stamp, |
f4128785 | 6089 | tx_buffer->next_to_watch, |
9d5c8243 | 6090 | jiffies, |
f4128785 | 6091 | tx_buffer->next_to_watch->wb.status); |
13fde97a AD |
6092 | netif_stop_subqueue(tx_ring->netdev, |
6093 | tx_ring->queue_index); | |
6094 | ||
6095 | /* we are about to reset, no point in enabling stuff */ | |
6096 | return true; | |
9d5c8243 AK |
6097 | } |
6098 | } | |
13fde97a | 6099 | |
21ba6fe1 | 6100 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
13fde97a | 6101 | if (unlikely(total_packets && |
b980ac18 JK |
6102 | netif_carrier_ok(tx_ring->netdev) && |
6103 | igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { | |
13fde97a AD |
6104 | /* Make sure that anybody stopping the queue after this |
6105 | * sees the new next_to_clean. | |
6106 | */ | |
6107 | smp_mb(); | |
6108 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
6109 | tx_ring->queue_index) && | |
6110 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
6111 | netif_wake_subqueue(tx_ring->netdev, | |
6112 | tx_ring->queue_index); | |
6113 | ||
6114 | u64_stats_update_begin(&tx_ring->tx_syncp); | |
6115 | tx_ring->tx_stats.restart_queue++; | |
6116 | u64_stats_update_end(&tx_ring->tx_syncp); | |
6117 | } | |
6118 | } | |
6119 | ||
6120 | return !!budget; | |
9d5c8243 AK |
6121 | } |
6122 | ||
cbc8e55f | 6123 | /** |
b980ac18 JK |
6124 | * igb_reuse_rx_page - page flip buffer and store it back on the ring |
6125 | * @rx_ring: rx descriptor ring to store buffers on | |
6126 | * @old_buff: donor buffer to have page reused | |
cbc8e55f | 6127 | * |
b980ac18 | 6128 | * Synchronizes page for reuse by the adapter |
cbc8e55f AD |
6129 | **/ |
6130 | static void igb_reuse_rx_page(struct igb_ring *rx_ring, | |
6131 | struct igb_rx_buffer *old_buff) | |
6132 | { | |
6133 | struct igb_rx_buffer *new_buff; | |
6134 | u16 nta = rx_ring->next_to_alloc; | |
6135 | ||
6136 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
6137 | ||
6138 | /* update, and store next to alloc */ | |
6139 | nta++; | |
6140 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
6141 | ||
6142 | /* transfer page from old buffer to new buffer */ | |
6143 | memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); | |
6144 | ||
6145 | /* sync the buffer for use by the device */ | |
6146 | dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, | |
6147 | old_buff->page_offset, | |
de78d1f9 | 6148 | IGB_RX_BUFSZ, |
cbc8e55f AD |
6149 | DMA_FROM_DEVICE); |
6150 | } | |
6151 | ||
74e238ea AD |
6152 | static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, |
6153 | struct page *page, | |
6154 | unsigned int truesize) | |
6155 | { | |
6156 | /* avoid re-using remote pages */ | |
6157 | if (unlikely(page_to_nid(page) != numa_node_id())) | |
6158 | return false; | |
6159 | ||
6160 | #if (PAGE_SIZE < 8192) | |
6161 | /* if we are only owner of page we can reuse it */ | |
6162 | if (unlikely(page_count(page) != 1)) | |
6163 | return false; | |
6164 | ||
6165 | /* flip page offset to other buffer */ | |
6166 | rx_buffer->page_offset ^= IGB_RX_BUFSZ; | |
6167 | ||
6168 | /* since we are the only owner of the page and we need to | |
6169 | * increment it, just set the value to 2 in order to avoid | |
6170 | * an unnecessary locked operation | |
6171 | */ | |
6172 | atomic_set(&page->_count, 2); | |
6173 | #else | |
6174 | /* move offset up to the next cache line */ | |
6175 | rx_buffer->page_offset += truesize; | |
6176 | ||
6177 | if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) | |
6178 | return false; | |
6179 | ||
6180 | /* bump ref count on page before it is given to the stack */ | |
6181 | get_page(page); | |
6182 | #endif | |
6183 | ||
6184 | return true; | |
6185 | } | |
6186 | ||
cbc8e55f | 6187 | /** |
b980ac18 JK |
6188 | * igb_add_rx_frag - Add contents of Rx buffer to sk_buff |
6189 | * @rx_ring: rx descriptor ring to transact packets on | |
6190 | * @rx_buffer: buffer containing page to add | |
6191 | * @rx_desc: descriptor containing length of buffer written by hardware | |
6192 | * @skb: sk_buff to place the data into | |
cbc8e55f | 6193 | * |
b980ac18 JK |
6194 | * This function will add the data contained in rx_buffer->page to the skb. |
6195 | * This is done either through a direct copy if the data in the buffer is | |
6196 | * less than the skb header size, otherwise it will just attach the page as | |
6197 | * a frag to the skb. | |
cbc8e55f | 6198 | * |
b980ac18 JK |
6199 | * The function will then update the page offset if necessary and return |
6200 | * true if the buffer can be reused by the adapter. | |
cbc8e55f AD |
6201 | **/ |
6202 | static bool igb_add_rx_frag(struct igb_ring *rx_ring, | |
6203 | struct igb_rx_buffer *rx_buffer, | |
6204 | union e1000_adv_rx_desc *rx_desc, | |
6205 | struct sk_buff *skb) | |
6206 | { | |
6207 | struct page *page = rx_buffer->page; | |
6208 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
74e238ea AD |
6209 | #if (PAGE_SIZE < 8192) |
6210 | unsigned int truesize = IGB_RX_BUFSZ; | |
6211 | #else | |
6212 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
6213 | #endif | |
cbc8e55f AD |
6214 | |
6215 | if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { | |
6216 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
6217 | ||
cbc8e55f AD |
6218 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
6219 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
6220 | va += IGB_TS_HDR_LEN; | |
6221 | size -= IGB_TS_HDR_LEN; | |
6222 | } | |
6223 | ||
cbc8e55f AD |
6224 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
6225 | ||
6226 | /* we can reuse buffer as-is, just make sure it is local */ | |
6227 | if (likely(page_to_nid(page) == numa_node_id())) | |
6228 | return true; | |
6229 | ||
6230 | /* this page cannot be reused so discard it */ | |
6231 | put_page(page); | |
6232 | return false; | |
6233 | } | |
6234 | ||
6235 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, | |
74e238ea | 6236 | rx_buffer->page_offset, size, truesize); |
cbc8e55f | 6237 | |
74e238ea AD |
6238 | return igb_can_reuse_rx_page(rx_buffer, page, truesize); |
6239 | } | |
cbc8e55f | 6240 | |
74e238ea AD |
6241 | static struct sk_buff *igb_build_rx_buffer(struct igb_ring *rx_ring, |
6242 | union e1000_adv_rx_desc *rx_desc) | |
6243 | { | |
6244 | struct igb_rx_buffer *rx_buffer; | |
6245 | struct sk_buff *skb; | |
6246 | struct page *page; | |
6247 | void *page_addr; | |
6248 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
de78d1f9 | 6249 | #if (PAGE_SIZE < 8192) |
74e238ea AD |
6250 | unsigned int truesize = IGB_RX_BUFSZ; |
6251 | #else | |
6252 | unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + | |
6253 | SKB_DATA_ALIGN(NET_SKB_PAD + | |
6254 | NET_IP_ALIGN + | |
6255 | size); | |
6256 | #endif | |
cbc8e55f | 6257 | |
74e238ea AD |
6258 | /* If we spanned a buffer we have a huge mess so test for it */ |
6259 | BUG_ON(unlikely(!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))); | |
cbc8e55f | 6260 | |
74e238ea AD |
6261 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; |
6262 | page = rx_buffer->page; | |
6263 | prefetchw(page); | |
de78d1f9 | 6264 | |
74e238ea AD |
6265 | page_addr = page_address(page) + rx_buffer->page_offset; |
6266 | ||
6267 | /* prefetch first cache line of first page */ | |
6268 | prefetch(page_addr + NET_SKB_PAD + NET_IP_ALIGN); | |
6269 | #if L1_CACHE_BYTES < 128 | |
6270 | prefetch(page_addr + L1_CACHE_BYTES + NET_SKB_PAD + NET_IP_ALIGN); | |
de78d1f9 | 6271 | #endif |
cbc8e55f | 6272 | |
74e238ea AD |
6273 | /* build an skb to around the page buffer */ |
6274 | skb = build_skb(page_addr, truesize); | |
6275 | if (unlikely(!skb)) { | |
6276 | rx_ring->rx_stats.alloc_failed++; | |
6277 | return NULL; | |
6278 | } | |
6279 | ||
6280 | /* we are reusing so sync this buffer for CPU use */ | |
6281 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
6282 | rx_buffer->dma, | |
6283 | rx_buffer->page_offset, | |
6284 | IGB_RX_BUFSZ, | |
6285 | DMA_FROM_DEVICE); | |
6286 | ||
6287 | /* update pointers within the skb to store the data */ | |
6288 | skb_reserve(skb, NET_IP_ALIGN + NET_SKB_PAD); | |
6289 | __skb_put(skb, size); | |
6290 | ||
6291 | /* pull timestamp out of packet data */ | |
6292 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { | |
6293 | igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); | |
6294 | __skb_pull(skb, IGB_TS_HDR_LEN); | |
6295 | } | |
6296 | ||
6297 | if (igb_can_reuse_rx_page(rx_buffer, page, truesize)) { | |
6298 | /* hand second half of page back to the ring */ | |
6299 | igb_reuse_rx_page(rx_ring, rx_buffer); | |
6300 | } else { | |
6301 | /* we are not reusing the buffer so unmap it */ | |
6302 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
6303 | PAGE_SIZE, DMA_FROM_DEVICE); | |
6304 | } | |
6305 | ||
6306 | /* clear contents of buffer_info */ | |
6307 | rx_buffer->dma = 0; | |
6308 | rx_buffer->page = NULL; | |
6309 | ||
6310 | return skb; | |
cbc8e55f AD |
6311 | } |
6312 | ||
2e334eee AD |
6313 | static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, |
6314 | union e1000_adv_rx_desc *rx_desc, | |
6315 | struct sk_buff *skb) | |
6316 | { | |
6317 | struct igb_rx_buffer *rx_buffer; | |
6318 | struct page *page; | |
6319 | ||
6320 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
6321 | ||
2e334eee AD |
6322 | page = rx_buffer->page; |
6323 | prefetchw(page); | |
6324 | ||
6325 | if (likely(!skb)) { | |
6326 | void *page_addr = page_address(page) + | |
6327 | rx_buffer->page_offset; | |
6328 | ||
6329 | /* prefetch first cache line of first page */ | |
6330 | prefetch(page_addr); | |
6331 | #if L1_CACHE_BYTES < 128 | |
6332 | prefetch(page_addr + L1_CACHE_BYTES); | |
6333 | #endif | |
6334 | ||
6335 | /* allocate a skb to store the frags */ | |
6336 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
6337 | IGB_RX_HDR_LEN); | |
6338 | if (unlikely(!skb)) { | |
6339 | rx_ring->rx_stats.alloc_failed++; | |
6340 | return NULL; | |
6341 | } | |
6342 | ||
b980ac18 | 6343 | /* we will be copying header into skb->data in |
2e334eee AD |
6344 | * pskb_may_pull so it is in our interest to prefetch |
6345 | * it now to avoid a possible cache miss | |
6346 | */ | |
6347 | prefetchw(skb->data); | |
6348 | } | |
6349 | ||
6350 | /* we are reusing so sync this buffer for CPU use */ | |
6351 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
6352 | rx_buffer->dma, | |
6353 | rx_buffer->page_offset, | |
de78d1f9 | 6354 | IGB_RX_BUFSZ, |
2e334eee AD |
6355 | DMA_FROM_DEVICE); |
6356 | ||
6357 | /* pull page into skb */ | |
6358 | if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
6359 | /* hand second half of page back to the ring */ | |
6360 | igb_reuse_rx_page(rx_ring, rx_buffer); | |
6361 | } else { | |
6362 | /* we are not reusing the buffer so unmap it */ | |
6363 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
6364 | PAGE_SIZE, DMA_FROM_DEVICE); | |
6365 | } | |
6366 | ||
6367 | /* clear contents of rx_buffer */ | |
6368 | rx_buffer->page = NULL; | |
6369 | ||
6370 | return skb; | |
6371 | } | |
6372 | ||
cd392f5c | 6373 | static inline void igb_rx_checksum(struct igb_ring *ring, |
3ceb90fd AD |
6374 | union e1000_adv_rx_desc *rx_desc, |
6375 | struct sk_buff *skb) | |
9d5c8243 | 6376 | { |
bc8acf2c | 6377 | skb_checksum_none_assert(skb); |
9d5c8243 | 6378 | |
294e7d78 | 6379 | /* Ignore Checksum bit is set */ |
3ceb90fd | 6380 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) |
294e7d78 AD |
6381 | return; |
6382 | ||
6383 | /* Rx checksum disabled via ethtool */ | |
6384 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) | |
9d5c8243 | 6385 | return; |
85ad76b2 | 6386 | |
9d5c8243 | 6387 | /* TCP/UDP checksum error bit is set */ |
3ceb90fd AD |
6388 | if (igb_test_staterr(rx_desc, |
6389 | E1000_RXDEXT_STATERR_TCPE | | |
6390 | E1000_RXDEXT_STATERR_IPE)) { | |
b980ac18 | 6391 | /* work around errata with sctp packets where the TCPE aka |
b9473560 JB |
6392 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) |
6393 | * packets, (aka let the stack check the crc32c) | |
6394 | */ | |
866cff06 AD |
6395 | if (!((skb->len == 60) && |
6396 | test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { | |
12dcd86b | 6397 | u64_stats_update_begin(&ring->rx_syncp); |
04a5fcaa | 6398 | ring->rx_stats.csum_err++; |
12dcd86b ED |
6399 | u64_stats_update_end(&ring->rx_syncp); |
6400 | } | |
9d5c8243 | 6401 | /* let the stack verify checksum errors */ |
9d5c8243 AK |
6402 | return; |
6403 | } | |
6404 | /* It must be a TCP or UDP packet with a valid checksum */ | |
3ceb90fd AD |
6405 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | |
6406 | E1000_RXD_STAT_UDPCS)) | |
9d5c8243 AK |
6407 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
6408 | ||
3ceb90fd AD |
6409 | dev_dbg(ring->dev, "cksum success: bits %08X\n", |
6410 | le32_to_cpu(rx_desc->wb.upper.status_error)); | |
9d5c8243 AK |
6411 | } |
6412 | ||
077887c3 AD |
6413 | static inline void igb_rx_hash(struct igb_ring *ring, |
6414 | union e1000_adv_rx_desc *rx_desc, | |
6415 | struct sk_buff *skb) | |
6416 | { | |
6417 | if (ring->netdev->features & NETIF_F_RXHASH) | |
6418 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
6419 | } | |
6420 | ||
2e334eee | 6421 | /** |
b980ac18 JK |
6422 | * igb_is_non_eop - process handling of non-EOP buffers |
6423 | * @rx_ring: Rx ring being processed | |
6424 | * @rx_desc: Rx descriptor for current buffer | |
6425 | * @skb: current socket buffer containing buffer in progress | |
2e334eee | 6426 | * |
b980ac18 JK |
6427 | * This function updates next to clean. If the buffer is an EOP buffer |
6428 | * this function exits returning false, otherwise it will place the | |
6429 | * sk_buff in the next buffer to be chained and return true indicating | |
6430 | * that this is in fact a non-EOP buffer. | |
2e334eee AD |
6431 | **/ |
6432 | static bool igb_is_non_eop(struct igb_ring *rx_ring, | |
6433 | union e1000_adv_rx_desc *rx_desc) | |
6434 | { | |
6435 | u32 ntc = rx_ring->next_to_clean + 1; | |
6436 | ||
6437 | /* fetch, update, and store next to clean */ | |
6438 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
6439 | rx_ring->next_to_clean = ntc; | |
6440 | ||
6441 | prefetch(IGB_RX_DESC(rx_ring, ntc)); | |
6442 | ||
6443 | if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) | |
6444 | return false; | |
6445 | ||
6446 | return true; | |
6447 | } | |
6448 | ||
1a1c225b | 6449 | /** |
b980ac18 JK |
6450 | * igb_get_headlen - determine size of header for LRO/GRO |
6451 | * @data: pointer to the start of the headers | |
6452 | * @max_len: total length of section to find headers in | |
1a1c225b | 6453 | * |
b980ac18 JK |
6454 | * This function is meant to determine the length of headers that will |
6455 | * be recognized by hardware for LRO, and GRO offloads. The main | |
6456 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
6457 | * packets so that we can do basic things like calculating the gso_size | |
6458 | * based on the average data per packet. | |
1a1c225b AD |
6459 | **/ |
6460 | static unsigned int igb_get_headlen(unsigned char *data, | |
6461 | unsigned int max_len) | |
6462 | { | |
6463 | union { | |
6464 | unsigned char *network; | |
6465 | /* l2 headers */ | |
6466 | struct ethhdr *eth; | |
6467 | struct vlan_hdr *vlan; | |
6468 | /* l3 headers */ | |
6469 | struct iphdr *ipv4; | |
6470 | struct ipv6hdr *ipv6; | |
6471 | } hdr; | |
6472 | __be16 protocol; | |
6473 | u8 nexthdr = 0; /* default to not TCP */ | |
6474 | u8 hlen; | |
6475 | ||
6476 | /* this should never happen, but better safe than sorry */ | |
6477 | if (max_len < ETH_HLEN) | |
6478 | return max_len; | |
6479 | ||
6480 | /* initialize network frame pointer */ | |
6481 | hdr.network = data; | |
6482 | ||
6483 | /* set first protocol and move network header forward */ | |
6484 | protocol = hdr.eth->h_proto; | |
6485 | hdr.network += ETH_HLEN; | |
6486 | ||
6487 | /* handle any vlan tag if present */ | |
6488 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6489 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
6490 | return max_len; | |
6491 | ||
6492 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
6493 | hdr.network += VLAN_HLEN; | |
6494 | } | |
6495 | ||
6496 | /* handle L3 protocols */ | |
6497 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6498 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
6499 | return max_len; | |
6500 | ||
6501 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
6502 | hlen = (hdr.network[0] & 0x0F) << 2; | |
6503 | ||
6504 | /* verify hlen meets minimum size requirements */ | |
6505 | if (hlen < sizeof(struct iphdr)) | |
6506 | return hdr.network - data; | |
6507 | ||
f2fb4ab2 | 6508 | /* record next protocol if header is present */ |
b9555f66 | 6509 | if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) |
f2fb4ab2 | 6510 | nexthdr = hdr.ipv4->protocol; |
1a1c225b AD |
6511 | } else if (protocol == __constant_htons(ETH_P_IPV6)) { |
6512 | if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) | |
6513 | return max_len; | |
6514 | ||
6515 | /* record next protocol */ | |
6516 | nexthdr = hdr.ipv6->nexthdr; | |
f2fb4ab2 | 6517 | hlen = sizeof(struct ipv6hdr); |
1a1c225b AD |
6518 | } else { |
6519 | return hdr.network - data; | |
6520 | } | |
6521 | ||
f2fb4ab2 AD |
6522 | /* relocate pointer to start of L4 header */ |
6523 | hdr.network += hlen; | |
6524 | ||
1a1c225b AD |
6525 | /* finally sort out TCP */ |
6526 | if (nexthdr == IPPROTO_TCP) { | |
6527 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
6528 | return max_len; | |
6529 | ||
6530 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
6531 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
6532 | ||
6533 | /* verify hlen meets minimum size requirements */ | |
6534 | if (hlen < sizeof(struct tcphdr)) | |
6535 | return hdr.network - data; | |
6536 | ||
6537 | hdr.network += hlen; | |
6538 | } else if (nexthdr == IPPROTO_UDP) { | |
6539 | if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) | |
6540 | return max_len; | |
6541 | ||
6542 | hdr.network += sizeof(struct udphdr); | |
6543 | } | |
6544 | ||
b980ac18 | 6545 | /* If everything has gone correctly hdr.network should be the |
1a1c225b AD |
6546 | * data section of the packet and will be the end of the header. |
6547 | * If not then it probably represents the end of the last recognized | |
6548 | * header. | |
6549 | */ | |
6550 | if ((hdr.network - data) < max_len) | |
6551 | return hdr.network - data; | |
6552 | else | |
6553 | return max_len; | |
6554 | } | |
6555 | ||
6556 | /** | |
b980ac18 JK |
6557 | * igb_pull_tail - igb specific version of skb_pull_tail |
6558 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6559 | * @rx_desc: pointer to the EOP Rx descriptor | |
6560 | * @skb: pointer to current skb being adjusted | |
1a1c225b | 6561 | * |
b980ac18 JK |
6562 | * This function is an igb specific version of __pskb_pull_tail. The |
6563 | * main difference between this version and the original function is that | |
6564 | * this function can make several assumptions about the state of things | |
6565 | * that allow for significant optimizations versus the standard function. | |
6566 | * As a result we can do things like drop a frag and maintain an accurate | |
6567 | * truesize for the skb. | |
1a1c225b AD |
6568 | */ |
6569 | static void igb_pull_tail(struct igb_ring *rx_ring, | |
6570 | union e1000_adv_rx_desc *rx_desc, | |
6571 | struct sk_buff *skb) | |
2d94d8ab | 6572 | { |
1a1c225b AD |
6573 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
6574 | unsigned char *va; | |
6575 | unsigned int pull_len; | |
6576 | ||
b980ac18 | 6577 | /* it is valid to use page_address instead of kmap since we are |
1a1c225b AD |
6578 | * working with pages allocated out of the lomem pool per |
6579 | * alloc_page(GFP_ATOMIC) | |
2d94d8ab | 6580 | */ |
1a1c225b AD |
6581 | va = skb_frag_address(frag); |
6582 | ||
1a1c225b AD |
6583 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
6584 | /* retrieve timestamp from buffer */ | |
6585 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
6586 | ||
6587 | /* update pointers to remove timestamp header */ | |
6588 | skb_frag_size_sub(frag, IGB_TS_HDR_LEN); | |
6589 | frag->page_offset += IGB_TS_HDR_LEN; | |
6590 | skb->data_len -= IGB_TS_HDR_LEN; | |
6591 | skb->len -= IGB_TS_HDR_LEN; | |
6592 | ||
6593 | /* move va to start of packet data */ | |
6594 | va += IGB_TS_HDR_LEN; | |
6595 | } | |
6596 | ||
b980ac18 | 6597 | /* we need the header to contain the greater of either ETH_HLEN or |
1a1c225b AD |
6598 | * 60 bytes if the skb->len is less than 60 for skb_pad. |
6599 | */ | |
6600 | pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); | |
6601 | ||
6602 | /* align pull length to size of long to optimize memcpy performance */ | |
6603 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
6604 | ||
6605 | /* update all of the pointers */ | |
6606 | skb_frag_size_sub(frag, pull_len); | |
6607 | frag->page_offset += pull_len; | |
6608 | skb->data_len -= pull_len; | |
6609 | skb->tail += pull_len; | |
6610 | } | |
6611 | ||
6612 | /** | |
b980ac18 JK |
6613 | * igb_cleanup_headers - Correct corrupted or empty headers |
6614 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6615 | * @rx_desc: pointer to the EOP Rx descriptor | |
6616 | * @skb: pointer to current skb being fixed | |
1a1c225b | 6617 | * |
b980ac18 JK |
6618 | * Address the case where we are pulling data in on pages only |
6619 | * and as such no data is present in the skb header. | |
1a1c225b | 6620 | * |
b980ac18 JK |
6621 | * In addition if skb is not at least 60 bytes we need to pad it so that |
6622 | * it is large enough to qualify as a valid Ethernet frame. | |
1a1c225b | 6623 | * |
b980ac18 | 6624 | * Returns true if an error was encountered and skb was freed. |
1a1c225b AD |
6625 | **/ |
6626 | static bool igb_cleanup_headers(struct igb_ring *rx_ring, | |
6627 | union e1000_adv_rx_desc *rx_desc, | |
6628 | struct sk_buff *skb) | |
6629 | { | |
1a1c225b AD |
6630 | if (unlikely((igb_test_staterr(rx_desc, |
6631 | E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { | |
6632 | struct net_device *netdev = rx_ring->netdev; | |
6633 | if (!(netdev->features & NETIF_F_RXALL)) { | |
6634 | dev_kfree_skb_any(skb); | |
6635 | return true; | |
6636 | } | |
6637 | } | |
6638 | ||
6639 | /* place header in linear portion of buffer */ | |
6640 | if (skb_is_nonlinear(skb)) | |
6641 | igb_pull_tail(rx_ring, rx_desc, skb); | |
6642 | ||
6643 | /* if skb_pad returns an error the skb was freed */ | |
6644 | if (unlikely(skb->len < 60)) { | |
6645 | int pad_len = 60 - skb->len; | |
6646 | ||
6647 | if (skb_pad(skb, pad_len)) | |
6648 | return true; | |
6649 | __skb_put(skb, pad_len); | |
6650 | } | |
6651 | ||
6652 | return false; | |
2d94d8ab AD |
6653 | } |
6654 | ||
db2ee5bd | 6655 | /** |
b980ac18 JK |
6656 | * igb_process_skb_fields - Populate skb header fields from Rx descriptor |
6657 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6658 | * @rx_desc: pointer to the EOP Rx descriptor | |
6659 | * @skb: pointer to current skb being populated | |
db2ee5bd | 6660 | * |
b980ac18 JK |
6661 | * This function checks the ring, descriptor, and packet information in |
6662 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
6663 | * other fields within the skb. | |
db2ee5bd AD |
6664 | **/ |
6665 | static void igb_process_skb_fields(struct igb_ring *rx_ring, | |
6666 | union e1000_adv_rx_desc *rx_desc, | |
6667 | struct sk_buff *skb) | |
6668 | { | |
6669 | struct net_device *dev = rx_ring->netdev; | |
6670 | ||
6671 | igb_rx_hash(rx_ring, rx_desc, skb); | |
6672 | ||
6673 | igb_rx_checksum(rx_ring, rx_desc, skb); | |
6674 | ||
db2ee5bd | 6675 | igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); |
db2ee5bd | 6676 | |
f646968f | 6677 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
db2ee5bd AD |
6678 | igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { |
6679 | u16 vid; | |
6680 | if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && | |
6681 | test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) | |
6682 | vid = be16_to_cpu(rx_desc->wb.upper.vlan); | |
6683 | else | |
6684 | vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
6685 | ||
86a9bad3 | 6686 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
db2ee5bd AD |
6687 | } |
6688 | ||
6689 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
6690 | ||
6691 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
6692 | } | |
6693 | ||
2e334eee | 6694 | static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) |
9d5c8243 | 6695 | { |
0ba82994 | 6696 | struct igb_ring *rx_ring = q_vector->rx.ring; |
1a1c225b | 6697 | struct sk_buff *skb = rx_ring->skb; |
9d5c8243 | 6698 | unsigned int total_bytes = 0, total_packets = 0; |
16eb8815 | 6699 | u16 cleaned_count = igb_desc_unused(rx_ring); |
9d5c8243 | 6700 | |
2e334eee AD |
6701 | do { |
6702 | union e1000_adv_rx_desc *rx_desc; | |
bf36c1a0 | 6703 | |
2e334eee AD |
6704 | /* return some buffers to hardware, one at a time is too slow */ |
6705 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
6706 | igb_alloc_rx_buffers(rx_ring, cleaned_count); | |
6707 | cleaned_count = 0; | |
6708 | } | |
bf36c1a0 | 6709 | |
2e334eee | 6710 | rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); |
16eb8815 | 6711 | |
2e334eee AD |
6712 | if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) |
6713 | break; | |
9d5c8243 | 6714 | |
74e238ea AD |
6715 | /* This memory barrier is needed to keep us from reading |
6716 | * any other fields out of the rx_desc until we know the | |
6717 | * RXD_STAT_DD bit is set | |
6718 | */ | |
6719 | rmb(); | |
6720 | ||
2e334eee | 6721 | /* retrieve a buffer from the ring */ |
74e238ea AD |
6722 | if (ring_uses_build_skb(rx_ring)) |
6723 | skb = igb_build_rx_buffer(rx_ring, rx_desc); | |
6724 | else | |
6725 | skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); | |
9d5c8243 | 6726 | |
2e334eee AD |
6727 | /* exit if we failed to retrieve a buffer */ |
6728 | if (!skb) | |
6729 | break; | |
1a1c225b | 6730 | |
2e334eee | 6731 | cleaned_count++; |
1a1c225b | 6732 | |
2e334eee AD |
6733 | /* fetch next buffer in frame if non-eop */ |
6734 | if (igb_is_non_eop(rx_ring, rx_desc)) | |
6735 | continue; | |
1a1c225b AD |
6736 | |
6737 | /* verify the packet layout is correct */ | |
6738 | if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { | |
6739 | skb = NULL; | |
6740 | continue; | |
9d5c8243 | 6741 | } |
9d5c8243 | 6742 | |
db2ee5bd | 6743 | /* probably a little skewed due to removing CRC */ |
3ceb90fd | 6744 | total_bytes += skb->len; |
3ceb90fd | 6745 | |
db2ee5bd AD |
6746 | /* populate checksum, timestamp, VLAN, and protocol */ |
6747 | igb_process_skb_fields(rx_ring, rx_desc, skb); | |
3ceb90fd | 6748 | |
b2cb09b1 | 6749 | napi_gro_receive(&q_vector->napi, skb); |
9d5c8243 | 6750 | |
1a1c225b AD |
6751 | /* reset skb pointer */ |
6752 | skb = NULL; | |
6753 | ||
2e334eee AD |
6754 | /* update budget accounting */ |
6755 | total_packets++; | |
6756 | } while (likely(total_packets < budget)); | |
bf36c1a0 | 6757 | |
1a1c225b AD |
6758 | /* place incomplete frames back on ring for completion */ |
6759 | rx_ring->skb = skb; | |
6760 | ||
12dcd86b | 6761 | u64_stats_update_begin(&rx_ring->rx_syncp); |
9d5c8243 AK |
6762 | rx_ring->rx_stats.packets += total_packets; |
6763 | rx_ring->rx_stats.bytes += total_bytes; | |
12dcd86b | 6764 | u64_stats_update_end(&rx_ring->rx_syncp); |
0ba82994 AD |
6765 | q_vector->rx.total_packets += total_packets; |
6766 | q_vector->rx.total_bytes += total_bytes; | |
c023cd88 AD |
6767 | |
6768 | if (cleaned_count) | |
cd392f5c | 6769 | igb_alloc_rx_buffers(rx_ring, cleaned_count); |
c023cd88 | 6770 | |
2e334eee | 6771 | return (total_packets < budget); |
9d5c8243 AK |
6772 | } |
6773 | ||
c023cd88 | 6774 | static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, |
06034649 | 6775 | struct igb_rx_buffer *bi) |
c023cd88 AD |
6776 | { |
6777 | struct page *page = bi->page; | |
cbc8e55f | 6778 | dma_addr_t dma; |
c023cd88 | 6779 | |
cbc8e55f AD |
6780 | /* since we are recycling buffers we should seldom need to alloc */ |
6781 | if (likely(page)) | |
c023cd88 AD |
6782 | return true; |
6783 | ||
cbc8e55f AD |
6784 | /* alloc new page for storage */ |
6785 | page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); | |
6786 | if (unlikely(!page)) { | |
6787 | rx_ring->rx_stats.alloc_failed++; | |
6788 | return false; | |
c023cd88 AD |
6789 | } |
6790 | ||
cbc8e55f AD |
6791 | /* map page for use */ |
6792 | dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
c023cd88 | 6793 | |
b980ac18 | 6794 | /* if mapping failed free memory back to system since |
cbc8e55f AD |
6795 | * there isn't much point in holding memory we can't use |
6796 | */ | |
1a1c225b | 6797 | if (dma_mapping_error(rx_ring->dev, dma)) { |
cbc8e55f AD |
6798 | __free_page(page); |
6799 | ||
c023cd88 AD |
6800 | rx_ring->rx_stats.alloc_failed++; |
6801 | return false; | |
6802 | } | |
6803 | ||
1a1c225b | 6804 | bi->dma = dma; |
cbc8e55f AD |
6805 | bi->page = page; |
6806 | bi->page_offset = 0; | |
1a1c225b | 6807 | |
c023cd88 AD |
6808 | return true; |
6809 | } | |
6810 | ||
74e238ea AD |
6811 | static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) |
6812 | { | |
6813 | if (ring_uses_build_skb(rx_ring)) | |
6814 | return NET_SKB_PAD + NET_IP_ALIGN; | |
6815 | else | |
6816 | return 0; | |
6817 | } | |
6818 | ||
9d5c8243 | 6819 | /** |
b980ac18 JK |
6820 | * igb_alloc_rx_buffers - Replace used receive buffers; packet split |
6821 | * @adapter: address of board private structure | |
9d5c8243 | 6822 | **/ |
cd392f5c | 6823 | void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) |
9d5c8243 | 6824 | { |
9d5c8243 | 6825 | union e1000_adv_rx_desc *rx_desc; |
06034649 | 6826 | struct igb_rx_buffer *bi; |
c023cd88 | 6827 | u16 i = rx_ring->next_to_use; |
9d5c8243 | 6828 | |
cbc8e55f AD |
6829 | /* nothing to do */ |
6830 | if (!cleaned_count) | |
6831 | return; | |
6832 | ||
60136906 | 6833 | rx_desc = IGB_RX_DESC(rx_ring, i); |
06034649 | 6834 | bi = &rx_ring->rx_buffer_info[i]; |
c023cd88 | 6835 | i -= rx_ring->count; |
9d5c8243 | 6836 | |
cbc8e55f | 6837 | do { |
1a1c225b | 6838 | if (!igb_alloc_mapped_page(rx_ring, bi)) |
c023cd88 | 6839 | break; |
9d5c8243 | 6840 | |
b980ac18 | 6841 | /* Refresh the desc even if buffer_addrs didn't change |
cbc8e55f AD |
6842 | * because each write-back erases this info. |
6843 | */ | |
74e238ea AD |
6844 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + |
6845 | bi->page_offset + | |
6846 | igb_rx_offset(rx_ring)); | |
9d5c8243 | 6847 | |
c023cd88 AD |
6848 | rx_desc++; |
6849 | bi++; | |
9d5c8243 | 6850 | i++; |
c023cd88 | 6851 | if (unlikely(!i)) { |
60136906 | 6852 | rx_desc = IGB_RX_DESC(rx_ring, 0); |
06034649 | 6853 | bi = rx_ring->rx_buffer_info; |
c023cd88 AD |
6854 | i -= rx_ring->count; |
6855 | } | |
6856 | ||
6857 | /* clear the hdr_addr for the next_to_use descriptor */ | |
6858 | rx_desc->read.hdr_addr = 0; | |
cbc8e55f AD |
6859 | |
6860 | cleaned_count--; | |
6861 | } while (cleaned_count); | |
9d5c8243 | 6862 | |
c023cd88 AD |
6863 | i += rx_ring->count; |
6864 | ||
9d5c8243 | 6865 | if (rx_ring->next_to_use != i) { |
cbc8e55f | 6866 | /* record the next descriptor to use */ |
9d5c8243 | 6867 | rx_ring->next_to_use = i; |
9d5c8243 | 6868 | |
cbc8e55f AD |
6869 | /* update next to alloc since we have filled the ring */ |
6870 | rx_ring->next_to_alloc = i; | |
6871 | ||
b980ac18 | 6872 | /* Force memory writes to complete before letting h/w |
9d5c8243 AK |
6873 | * know there are new descriptors to fetch. (Only |
6874 | * applicable for weak-ordered memory model archs, | |
cbc8e55f AD |
6875 | * such as IA-64). |
6876 | */ | |
9d5c8243 | 6877 | wmb(); |
fce99e34 | 6878 | writel(i, rx_ring->tail); |
9d5c8243 AK |
6879 | } |
6880 | } | |
6881 | ||
6882 | /** | |
6883 | * igb_mii_ioctl - | |
6884 | * @netdev: | |
6885 | * @ifreq: | |
6886 | * @cmd: | |
6887 | **/ | |
6888 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6889 | { | |
6890 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6891 | struct mii_ioctl_data *data = if_mii(ifr); | |
6892 | ||
6893 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
6894 | return -EOPNOTSUPP; | |
6895 | ||
6896 | switch (cmd) { | |
6897 | case SIOCGMIIPHY: | |
6898 | data->phy_id = adapter->hw.phy.addr; | |
6899 | break; | |
6900 | case SIOCGMIIREG: | |
f5f4cf08 AD |
6901 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
6902 | &data->val_out)) | |
9d5c8243 AK |
6903 | return -EIO; |
6904 | break; | |
6905 | case SIOCSMIIREG: | |
6906 | default: | |
6907 | return -EOPNOTSUPP; | |
6908 | } | |
6909 | return 0; | |
6910 | } | |
6911 | ||
6912 | /** | |
6913 | * igb_ioctl - | |
6914 | * @netdev: | |
6915 | * @ifreq: | |
6916 | * @cmd: | |
6917 | **/ | |
6918 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6919 | { | |
6920 | switch (cmd) { | |
6921 | case SIOCGMIIPHY: | |
6922 | case SIOCGMIIREG: | |
6923 | case SIOCSMIIREG: | |
6924 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b | 6925 | case SIOCSHWTSTAMP: |
a79f4f88 | 6926 | return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); |
9d5c8243 AK |
6927 | default: |
6928 | return -EOPNOTSUPP; | |
6929 | } | |
6930 | } | |
6931 | ||
009bc06e AD |
6932 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
6933 | { | |
6934 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6935 | |
23d028cc | 6936 | if (pcie_capability_read_word(adapter->pdev, reg, value)) |
009bc06e AD |
6937 | return -E1000_ERR_CONFIG; |
6938 | ||
009bc06e AD |
6939 | return 0; |
6940 | } | |
6941 | ||
6942 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | |
6943 | { | |
6944 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6945 | |
23d028cc | 6946 | if (pcie_capability_write_word(adapter->pdev, reg, *value)) |
009bc06e AD |
6947 | return -E1000_ERR_CONFIG; |
6948 | ||
009bc06e AD |
6949 | return 0; |
6950 | } | |
6951 | ||
c8f44aff | 6952 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) |
9d5c8243 AK |
6953 | { |
6954 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6955 | struct e1000_hw *hw = &adapter->hw; | |
6956 | u32 ctrl, rctl; | |
f646968f | 6957 | bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); |
9d5c8243 | 6958 | |
5faf030c | 6959 | if (enable) { |
9d5c8243 AK |
6960 | /* enable VLAN tag insert/strip */ |
6961 | ctrl = rd32(E1000_CTRL); | |
6962 | ctrl |= E1000_CTRL_VME; | |
6963 | wr32(E1000_CTRL, ctrl); | |
6964 | ||
51466239 | 6965 | /* Disable CFI check */ |
9d5c8243 | 6966 | rctl = rd32(E1000_RCTL); |
9d5c8243 AK |
6967 | rctl &= ~E1000_RCTL_CFIEN; |
6968 | wr32(E1000_RCTL, rctl); | |
9d5c8243 AK |
6969 | } else { |
6970 | /* disable VLAN tag insert/strip */ | |
6971 | ctrl = rd32(E1000_CTRL); | |
6972 | ctrl &= ~E1000_CTRL_VME; | |
6973 | wr32(E1000_CTRL, ctrl); | |
9d5c8243 AK |
6974 | } |
6975 | ||
e1739522 | 6976 | igb_rlpml_set(adapter); |
9d5c8243 AK |
6977 | } |
6978 | ||
80d5c368 PM |
6979 | static int igb_vlan_rx_add_vid(struct net_device *netdev, |
6980 | __be16 proto, u16 vid) | |
9d5c8243 AK |
6981 | { |
6982 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6983 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6984 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 6985 | |
51466239 AD |
6986 | /* attempt to add filter to vlvf array */ |
6987 | igb_vlvf_set(adapter, vid, true, pf_id); | |
4ae196df | 6988 | |
51466239 AD |
6989 | /* add the filter since PF can receive vlans w/o entry in vlvf */ |
6990 | igb_vfta_set(hw, vid, true); | |
b2cb09b1 JP |
6991 | |
6992 | set_bit(vid, adapter->active_vlans); | |
8e586137 JP |
6993 | |
6994 | return 0; | |
9d5c8243 AK |
6995 | } |
6996 | ||
80d5c368 PM |
6997 | static int igb_vlan_rx_kill_vid(struct net_device *netdev, |
6998 | __be16 proto, u16 vid) | |
9d5c8243 AK |
6999 | { |
7000 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7001 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 7002 | int pf_id = adapter->vfs_allocated_count; |
51466239 | 7003 | s32 err; |
9d5c8243 | 7004 | |
51466239 AD |
7005 | /* remove vlan from VLVF table array */ |
7006 | err = igb_vlvf_set(adapter, vid, false, pf_id); | |
9d5c8243 | 7007 | |
51466239 AD |
7008 | /* if vid was not present in VLVF just remove it from table */ |
7009 | if (err) | |
4ae196df | 7010 | igb_vfta_set(hw, vid, false); |
b2cb09b1 JP |
7011 | |
7012 | clear_bit(vid, adapter->active_vlans); | |
8e586137 JP |
7013 | |
7014 | return 0; | |
9d5c8243 AK |
7015 | } |
7016 | ||
7017 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
7018 | { | |
b2cb09b1 | 7019 | u16 vid; |
9d5c8243 | 7020 | |
5faf030c AD |
7021 | igb_vlan_mode(adapter->netdev, adapter->netdev->features); |
7022 | ||
b2cb09b1 | 7023 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
80d5c368 | 7024 | igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
9d5c8243 AK |
7025 | } |
7026 | ||
14ad2513 | 7027 | int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) |
9d5c8243 | 7028 | { |
090b1795 | 7029 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
7030 | struct e1000_mac_info *mac = &adapter->hw.mac; |
7031 | ||
7032 | mac->autoneg = 0; | |
7033 | ||
14ad2513 | 7034 | /* Make sure dplx is at most 1 bit and lsb of speed is not set |
b980ac18 JK |
7035 | * for the switch() below to work |
7036 | */ | |
14ad2513 DD |
7037 | if ((spd & 1) || (dplx & ~1)) |
7038 | goto err_inval; | |
7039 | ||
f502ef7d AA |
7040 | /* Fiber NIC's only allow 1000 gbps Full duplex |
7041 | * and 100Mbps Full duplex for 100baseFx sfp | |
7042 | */ | |
7043 | if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { | |
7044 | switch (spd + dplx) { | |
7045 | case SPEED_10 + DUPLEX_HALF: | |
7046 | case SPEED_10 + DUPLEX_FULL: | |
7047 | case SPEED_100 + DUPLEX_HALF: | |
7048 | goto err_inval; | |
7049 | default: | |
7050 | break; | |
7051 | } | |
7052 | } | |
cd2638a8 | 7053 | |
14ad2513 | 7054 | switch (spd + dplx) { |
9d5c8243 AK |
7055 | case SPEED_10 + DUPLEX_HALF: |
7056 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
7057 | break; | |
7058 | case SPEED_10 + DUPLEX_FULL: | |
7059 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
7060 | break; | |
7061 | case SPEED_100 + DUPLEX_HALF: | |
7062 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
7063 | break; | |
7064 | case SPEED_100 + DUPLEX_FULL: | |
7065 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
7066 | break; | |
7067 | case SPEED_1000 + DUPLEX_FULL: | |
7068 | mac->autoneg = 1; | |
7069 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
7070 | break; | |
7071 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
7072 | default: | |
14ad2513 | 7073 | goto err_inval; |
9d5c8243 | 7074 | } |
8376dad0 JB |
7075 | |
7076 | /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ | |
7077 | adapter->hw.phy.mdix = AUTO_ALL_MODES; | |
7078 | ||
9d5c8243 | 7079 | return 0; |
14ad2513 DD |
7080 | |
7081 | err_inval: | |
7082 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); | |
7083 | return -EINVAL; | |
9d5c8243 AK |
7084 | } |
7085 | ||
749ab2cd YZ |
7086 | static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, |
7087 | bool runtime) | |
9d5c8243 AK |
7088 | { |
7089 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7090 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7091 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 7092 | u32 ctrl, rctl, status; |
749ab2cd | 7093 | u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; |
9d5c8243 AK |
7094 | #ifdef CONFIG_PM |
7095 | int retval = 0; | |
7096 | #endif | |
7097 | ||
7098 | netif_device_detach(netdev); | |
7099 | ||
a88f10ec | 7100 | if (netif_running(netdev)) |
749ab2cd | 7101 | __igb_close(netdev, true); |
a88f10ec | 7102 | |
047e0030 | 7103 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
7104 | |
7105 | #ifdef CONFIG_PM | |
7106 | retval = pci_save_state(pdev); | |
7107 | if (retval) | |
7108 | return retval; | |
7109 | #endif | |
7110 | ||
7111 | status = rd32(E1000_STATUS); | |
7112 | if (status & E1000_STATUS_LU) | |
7113 | wufc &= ~E1000_WUFC_LNKC; | |
7114 | ||
7115 | if (wufc) { | |
7116 | igb_setup_rctl(adapter); | |
ff41f8dc | 7117 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
7118 | |
7119 | /* turn on all-multi mode if wake on multicast is enabled */ | |
7120 | if (wufc & E1000_WUFC_MC) { | |
7121 | rctl = rd32(E1000_RCTL); | |
7122 | rctl |= E1000_RCTL_MPE; | |
7123 | wr32(E1000_RCTL, rctl); | |
7124 | } | |
7125 | ||
7126 | ctrl = rd32(E1000_CTRL); | |
7127 | /* advertise wake from D3Cold */ | |
7128 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
7129 | /* phy power management enable */ | |
7130 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
7131 | ctrl |= E1000_CTRL_ADVD3WUC; | |
7132 | wr32(E1000_CTRL, ctrl); | |
7133 | ||
9d5c8243 | 7134 | /* Allow time for pending master requests to run */ |
330a6d6a | 7135 | igb_disable_pcie_master(hw); |
9d5c8243 AK |
7136 | |
7137 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
7138 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
7139 | } else { |
7140 | wr32(E1000_WUC, 0); | |
7141 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
7142 | } |
7143 | ||
3fe7c4c9 RW |
7144 | *enable_wake = wufc || adapter->en_mng_pt; |
7145 | if (!*enable_wake) | |
88a268c1 NN |
7146 | igb_power_down_link(adapter); |
7147 | else | |
7148 | igb_power_up_link(adapter); | |
9d5c8243 AK |
7149 | |
7150 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
b980ac18 JK |
7151 | * would have already happened in close and is redundant. |
7152 | */ | |
9d5c8243 AK |
7153 | igb_release_hw_control(adapter); |
7154 | ||
7155 | pci_disable_device(pdev); | |
7156 | ||
9d5c8243 AK |
7157 | return 0; |
7158 | } | |
7159 | ||
7160 | #ifdef CONFIG_PM | |
d9dd966d | 7161 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 7162 | static int igb_suspend(struct device *dev) |
3fe7c4c9 RW |
7163 | { |
7164 | int retval; | |
7165 | bool wake; | |
749ab2cd | 7166 | struct pci_dev *pdev = to_pci_dev(dev); |
3fe7c4c9 | 7167 | |
749ab2cd | 7168 | retval = __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
7169 | if (retval) |
7170 | return retval; | |
7171 | ||
7172 | if (wake) { | |
7173 | pci_prepare_to_sleep(pdev); | |
7174 | } else { | |
7175 | pci_wake_from_d3(pdev, false); | |
7176 | pci_set_power_state(pdev, PCI_D3hot); | |
7177 | } | |
7178 | ||
7179 | return 0; | |
7180 | } | |
d9dd966d | 7181 | #endif /* CONFIG_PM_SLEEP */ |
3fe7c4c9 | 7182 | |
749ab2cd | 7183 | static int igb_resume(struct device *dev) |
9d5c8243 | 7184 | { |
749ab2cd | 7185 | struct pci_dev *pdev = to_pci_dev(dev); |
9d5c8243 AK |
7186 | struct net_device *netdev = pci_get_drvdata(pdev); |
7187 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7188 | struct e1000_hw *hw = &adapter->hw; | |
7189 | u32 err; | |
7190 | ||
7191 | pci_set_power_state(pdev, PCI_D0); | |
7192 | pci_restore_state(pdev); | |
b94f2d77 | 7193 | pci_save_state(pdev); |
42bfd33a | 7194 | |
aed5dec3 | 7195 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
7196 | if (err) { |
7197 | dev_err(&pdev->dev, | |
7198 | "igb: Cannot enable PCI device from suspend\n"); | |
7199 | return err; | |
7200 | } | |
7201 | pci_set_master(pdev); | |
7202 | ||
7203 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
7204 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
7205 | ||
53c7d064 | 7206 | if (igb_init_interrupt_scheme(adapter, true)) { |
a88f10ec AD |
7207 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
7208 | return -ENOMEM; | |
9d5c8243 AK |
7209 | } |
7210 | ||
9d5c8243 | 7211 | igb_reset(adapter); |
a8564f03 AD |
7212 | |
7213 | /* let the f/w know that the h/w is now under the control of the | |
b980ac18 JK |
7214 | * driver. |
7215 | */ | |
a8564f03 AD |
7216 | igb_get_hw_control(adapter); |
7217 | ||
9d5c8243 AK |
7218 | wr32(E1000_WUS, ~0); |
7219 | ||
749ab2cd | 7220 | if (netdev->flags & IFF_UP) { |
0c2cc02e | 7221 | rtnl_lock(); |
749ab2cd | 7222 | err = __igb_open(netdev, true); |
0c2cc02e | 7223 | rtnl_unlock(); |
a88f10ec AD |
7224 | if (err) |
7225 | return err; | |
7226 | } | |
9d5c8243 AK |
7227 | |
7228 | netif_device_attach(netdev); | |
749ab2cd YZ |
7229 | return 0; |
7230 | } | |
7231 | ||
7232 | #ifdef CONFIG_PM_RUNTIME | |
7233 | static int igb_runtime_idle(struct device *dev) | |
7234 | { | |
7235 | struct pci_dev *pdev = to_pci_dev(dev); | |
7236 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7237 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7238 | ||
7239 | if (!igb_has_link(adapter)) | |
7240 | pm_schedule_suspend(dev, MSEC_PER_SEC * 5); | |
7241 | ||
7242 | return -EBUSY; | |
7243 | } | |
7244 | ||
7245 | static int igb_runtime_suspend(struct device *dev) | |
7246 | { | |
7247 | struct pci_dev *pdev = to_pci_dev(dev); | |
7248 | int retval; | |
7249 | bool wake; | |
7250 | ||
7251 | retval = __igb_shutdown(pdev, &wake, 1); | |
7252 | if (retval) | |
7253 | return retval; | |
7254 | ||
7255 | if (wake) { | |
7256 | pci_prepare_to_sleep(pdev); | |
7257 | } else { | |
7258 | pci_wake_from_d3(pdev, false); | |
7259 | pci_set_power_state(pdev, PCI_D3hot); | |
7260 | } | |
9d5c8243 | 7261 | |
9d5c8243 AK |
7262 | return 0; |
7263 | } | |
749ab2cd YZ |
7264 | |
7265 | static int igb_runtime_resume(struct device *dev) | |
7266 | { | |
7267 | return igb_resume(dev); | |
7268 | } | |
7269 | #endif /* CONFIG_PM_RUNTIME */ | |
9d5c8243 AK |
7270 | #endif |
7271 | ||
7272 | static void igb_shutdown(struct pci_dev *pdev) | |
7273 | { | |
3fe7c4c9 RW |
7274 | bool wake; |
7275 | ||
749ab2cd | 7276 | __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
7277 | |
7278 | if (system_state == SYSTEM_POWER_OFF) { | |
7279 | pci_wake_from_d3(pdev, wake); | |
7280 | pci_set_power_state(pdev, PCI_D3hot); | |
7281 | } | |
9d5c8243 AK |
7282 | } |
7283 | ||
fa44f2f1 GR |
7284 | #ifdef CONFIG_PCI_IOV |
7285 | static int igb_sriov_reinit(struct pci_dev *dev) | |
7286 | { | |
7287 | struct net_device *netdev = pci_get_drvdata(dev); | |
7288 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7289 | struct pci_dev *pdev = adapter->pdev; | |
7290 | ||
7291 | rtnl_lock(); | |
7292 | ||
7293 | if (netif_running(netdev)) | |
7294 | igb_close(netdev); | |
7295 | ||
7296 | igb_clear_interrupt_scheme(adapter); | |
7297 | ||
7298 | igb_init_queue_configuration(adapter); | |
7299 | ||
7300 | if (igb_init_interrupt_scheme(adapter, true)) { | |
7301 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
7302 | return -ENOMEM; | |
7303 | } | |
7304 | ||
7305 | if (netif_running(netdev)) | |
7306 | igb_open(netdev); | |
7307 | ||
7308 | rtnl_unlock(); | |
7309 | ||
7310 | return 0; | |
7311 | } | |
7312 | ||
7313 | static int igb_pci_disable_sriov(struct pci_dev *dev) | |
7314 | { | |
7315 | int err = igb_disable_sriov(dev); | |
7316 | ||
7317 | if (!err) | |
7318 | err = igb_sriov_reinit(dev); | |
7319 | ||
7320 | return err; | |
7321 | } | |
7322 | ||
7323 | static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) | |
7324 | { | |
7325 | int err = igb_enable_sriov(dev, num_vfs); | |
7326 | ||
7327 | if (err) | |
7328 | goto out; | |
7329 | ||
7330 | err = igb_sriov_reinit(dev); | |
7331 | if (!err) | |
7332 | return num_vfs; | |
7333 | ||
7334 | out: | |
7335 | return err; | |
7336 | } | |
7337 | ||
7338 | #endif | |
7339 | static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) | |
7340 | { | |
7341 | #ifdef CONFIG_PCI_IOV | |
7342 | if (num_vfs == 0) | |
7343 | return igb_pci_disable_sriov(dev); | |
7344 | else | |
7345 | return igb_pci_enable_sriov(dev, num_vfs); | |
7346 | #endif | |
7347 | return 0; | |
7348 | } | |
7349 | ||
9d5c8243 | 7350 | #ifdef CONFIG_NET_POLL_CONTROLLER |
b980ac18 | 7351 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
9d5c8243 AK |
7352 | * without having to re-enable interrupts. It's not called while |
7353 | * the interrupt routine is executing. | |
7354 | */ | |
7355 | static void igb_netpoll(struct net_device *netdev) | |
7356 | { | |
7357 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 7358 | struct e1000_hw *hw = &adapter->hw; |
0d1ae7f4 | 7359 | struct igb_q_vector *q_vector; |
9d5c8243 | 7360 | int i; |
9d5c8243 | 7361 | |
047e0030 | 7362 | for (i = 0; i < adapter->num_q_vectors; i++) { |
0d1ae7f4 AD |
7363 | q_vector = adapter->q_vector[i]; |
7364 | if (adapter->msix_entries) | |
7365 | wr32(E1000_EIMC, q_vector->eims_value); | |
7366 | else | |
7367 | igb_irq_disable(adapter); | |
047e0030 | 7368 | napi_schedule(&q_vector->napi); |
eebbbdba | 7369 | } |
9d5c8243 AK |
7370 | } |
7371 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
7372 | ||
7373 | /** | |
b980ac18 JK |
7374 | * igb_io_error_detected - called when PCI error is detected |
7375 | * @pdev: Pointer to PCI device | |
7376 | * @state: The current pci connection state | |
9d5c8243 | 7377 | * |
b980ac18 JK |
7378 | * This function is called after a PCI bus error affecting |
7379 | * this device has been detected. | |
7380 | **/ | |
9d5c8243 AK |
7381 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, |
7382 | pci_channel_state_t state) | |
7383 | { | |
7384 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7385 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7386 | ||
7387 | netif_device_detach(netdev); | |
7388 | ||
59ed6eec AD |
7389 | if (state == pci_channel_io_perm_failure) |
7390 | return PCI_ERS_RESULT_DISCONNECT; | |
7391 | ||
9d5c8243 AK |
7392 | if (netif_running(netdev)) |
7393 | igb_down(adapter); | |
7394 | pci_disable_device(pdev); | |
7395 | ||
7396 | /* Request a slot slot reset. */ | |
7397 | return PCI_ERS_RESULT_NEED_RESET; | |
7398 | } | |
7399 | ||
7400 | /** | |
b980ac18 JK |
7401 | * igb_io_slot_reset - called after the pci bus has been reset. |
7402 | * @pdev: Pointer to PCI device | |
9d5c8243 | 7403 | * |
b980ac18 JK |
7404 | * Restart the card from scratch, as if from a cold-boot. Implementation |
7405 | * resembles the first-half of the igb_resume routine. | |
7406 | **/ | |
9d5c8243 AK |
7407 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) |
7408 | { | |
7409 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7410 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7411 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 7412 | pci_ers_result_t result; |
42bfd33a | 7413 | int err; |
9d5c8243 | 7414 | |
aed5dec3 | 7415 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
7416 | dev_err(&pdev->dev, |
7417 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
7418 | result = PCI_ERS_RESULT_DISCONNECT; |
7419 | } else { | |
7420 | pci_set_master(pdev); | |
7421 | pci_restore_state(pdev); | |
b94f2d77 | 7422 | pci_save_state(pdev); |
9d5c8243 | 7423 | |
40a914fa AD |
7424 | pci_enable_wake(pdev, PCI_D3hot, 0); |
7425 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 7426 | |
40a914fa AD |
7427 | igb_reset(adapter); |
7428 | wr32(E1000_WUS, ~0); | |
7429 | result = PCI_ERS_RESULT_RECOVERED; | |
7430 | } | |
9d5c8243 | 7431 | |
ea943d41 JK |
7432 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
7433 | if (err) { | |
b980ac18 JK |
7434 | dev_err(&pdev->dev, |
7435 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
7436 | err); | |
ea943d41 JK |
7437 | /* non-fatal, continue */ |
7438 | } | |
40a914fa AD |
7439 | |
7440 | return result; | |
9d5c8243 AK |
7441 | } |
7442 | ||
7443 | /** | |
b980ac18 JK |
7444 | * igb_io_resume - called when traffic can start flowing again. |
7445 | * @pdev: Pointer to PCI device | |
9d5c8243 | 7446 | * |
b980ac18 JK |
7447 | * This callback is called when the error recovery driver tells us that |
7448 | * its OK to resume normal operation. Implementation resembles the | |
7449 | * second-half of the igb_resume routine. | |
9d5c8243 AK |
7450 | */ |
7451 | static void igb_io_resume(struct pci_dev *pdev) | |
7452 | { | |
7453 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7454 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7455 | ||
9d5c8243 AK |
7456 | if (netif_running(netdev)) { |
7457 | if (igb_up(adapter)) { | |
7458 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
7459 | return; | |
7460 | } | |
7461 | } | |
7462 | ||
7463 | netif_device_attach(netdev); | |
7464 | ||
7465 | /* let the f/w know that the h/w is now under the control of the | |
b980ac18 JK |
7466 | * driver. |
7467 | */ | |
9d5c8243 | 7468 | igb_get_hw_control(adapter); |
9d5c8243 AK |
7469 | } |
7470 | ||
26ad9178 | 7471 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
b980ac18 | 7472 | u8 qsel) |
26ad9178 AD |
7473 | { |
7474 | u32 rar_low, rar_high; | |
7475 | struct e1000_hw *hw = &adapter->hw; | |
7476 | ||
7477 | /* HW expects these in little endian so we reverse the byte order | |
7478 | * from network order (big endian) to little endian | |
7479 | */ | |
7480 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
b980ac18 | 7481 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
26ad9178 AD |
7482 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
7483 | ||
7484 | /* Indicate to hardware the Address is Valid. */ | |
7485 | rar_high |= E1000_RAH_AV; | |
7486 | ||
7487 | if (hw->mac.type == e1000_82575) | |
7488 | rar_high |= E1000_RAH_POOL_1 * qsel; | |
7489 | else | |
7490 | rar_high |= E1000_RAH_POOL_1 << qsel; | |
7491 | ||
7492 | wr32(E1000_RAL(index), rar_low); | |
7493 | wrfl(); | |
7494 | wr32(E1000_RAH(index), rar_high); | |
7495 | wrfl(); | |
7496 | } | |
7497 | ||
4ae196df | 7498 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
b980ac18 | 7499 | int vf, unsigned char *mac_addr) |
4ae196df AD |
7500 | { |
7501 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc | 7502 | /* VF MAC addresses start at end of receive addresses and moves |
b980ac18 JK |
7503 | * towards the first, as a result a collision should not be possible |
7504 | */ | |
ff41f8dc | 7505 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df | 7506 | |
37680117 | 7507 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df | 7508 | |
26ad9178 | 7509 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
4ae196df AD |
7510 | |
7511 | return 0; | |
7512 | } | |
7513 | ||
8151d294 WM |
7514 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
7515 | { | |
7516 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7517 | if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) | |
7518 | return -EINVAL; | |
7519 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; | |
7520 | dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); | |
b980ac18 JK |
7521 | dev_info(&adapter->pdev->dev, |
7522 | "Reload the VF driver to make this change effective."); | |
8151d294 | 7523 | if (test_bit(__IGB_DOWN, &adapter->state)) { |
b980ac18 JK |
7524 | dev_warn(&adapter->pdev->dev, |
7525 | "The VF MAC address has been set, but the PF device is not up.\n"); | |
7526 | dev_warn(&adapter->pdev->dev, | |
7527 | "Bring the PF device up before attempting to use the VF device.\n"); | |
8151d294 WM |
7528 | } |
7529 | return igb_set_vf_mac(adapter, vf, mac); | |
7530 | } | |
7531 | ||
17dc566c LL |
7532 | static int igb_link_mbps(int internal_link_speed) |
7533 | { | |
7534 | switch (internal_link_speed) { | |
7535 | case SPEED_100: | |
7536 | return 100; | |
7537 | case SPEED_1000: | |
7538 | return 1000; | |
7539 | default: | |
7540 | return 0; | |
7541 | } | |
7542 | } | |
7543 | ||
7544 | static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, | |
7545 | int link_speed) | |
7546 | { | |
7547 | int rf_dec, rf_int; | |
7548 | u32 bcnrc_val; | |
7549 | ||
7550 | if (tx_rate != 0) { | |
7551 | /* Calculate the rate factor values to set */ | |
7552 | rf_int = link_speed / tx_rate; | |
7553 | rf_dec = (link_speed - (rf_int * tx_rate)); | |
b980ac18 JK |
7554 | rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / |
7555 | tx_rate; | |
17dc566c LL |
7556 | |
7557 | bcnrc_val = E1000_RTTBCNRC_RS_ENA; | |
b980ac18 JK |
7558 | bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & |
7559 | E1000_RTTBCNRC_RF_INT_MASK); | |
17dc566c LL |
7560 | bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); |
7561 | } else { | |
7562 | bcnrc_val = 0; | |
7563 | } | |
7564 | ||
7565 | wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ | |
b980ac18 | 7566 | /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM |
f00b0da7 LL |
7567 | * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. |
7568 | */ | |
7569 | wr32(E1000_RTTBCNRM, 0x14); | |
17dc566c LL |
7570 | wr32(E1000_RTTBCNRC, bcnrc_val); |
7571 | } | |
7572 | ||
7573 | static void igb_check_vf_rate_limit(struct igb_adapter *adapter) | |
7574 | { | |
7575 | int actual_link_speed, i; | |
7576 | bool reset_rate = false; | |
7577 | ||
7578 | /* VF TX rate limit was not set or not supported */ | |
7579 | if ((adapter->vf_rate_link_speed == 0) || | |
7580 | (adapter->hw.mac.type != e1000_82576)) | |
7581 | return; | |
7582 | ||
7583 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7584 | if (actual_link_speed != adapter->vf_rate_link_speed) { | |
7585 | reset_rate = true; | |
7586 | adapter->vf_rate_link_speed = 0; | |
7587 | dev_info(&adapter->pdev->dev, | |
b980ac18 | 7588 | "Link speed has been changed. VF Transmit rate is disabled\n"); |
17dc566c LL |
7589 | } |
7590 | ||
7591 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7592 | if (reset_rate) | |
7593 | adapter->vf_data[i].tx_rate = 0; | |
7594 | ||
7595 | igb_set_vf_rate_limit(&adapter->hw, i, | |
b980ac18 JK |
7596 | adapter->vf_data[i].tx_rate, |
7597 | actual_link_speed); | |
17dc566c LL |
7598 | } |
7599 | } | |
7600 | ||
8151d294 WM |
7601 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) |
7602 | { | |
17dc566c LL |
7603 | struct igb_adapter *adapter = netdev_priv(netdev); |
7604 | struct e1000_hw *hw = &adapter->hw; | |
7605 | int actual_link_speed; | |
7606 | ||
7607 | if (hw->mac.type != e1000_82576) | |
7608 | return -EOPNOTSUPP; | |
7609 | ||
7610 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7611 | if ((vf >= adapter->vfs_allocated_count) || | |
7612 | (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || | |
7613 | (tx_rate < 0) || (tx_rate > actual_link_speed)) | |
7614 | return -EINVAL; | |
7615 | ||
7616 | adapter->vf_rate_link_speed = actual_link_speed; | |
7617 | adapter->vf_data[vf].tx_rate = (u16)tx_rate; | |
7618 | igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); | |
7619 | ||
7620 | return 0; | |
8151d294 WM |
7621 | } |
7622 | ||
70ea4783 LL |
7623 | static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, |
7624 | bool setting) | |
7625 | { | |
7626 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7627 | struct e1000_hw *hw = &adapter->hw; | |
7628 | u32 reg_val, reg_offset; | |
7629 | ||
7630 | if (!adapter->vfs_allocated_count) | |
7631 | return -EOPNOTSUPP; | |
7632 | ||
7633 | if (vf >= adapter->vfs_allocated_count) | |
7634 | return -EINVAL; | |
7635 | ||
7636 | reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; | |
7637 | reg_val = rd32(reg_offset); | |
7638 | if (setting) | |
7639 | reg_val |= ((1 << vf) | | |
7640 | (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); | |
7641 | else | |
7642 | reg_val &= ~((1 << vf) | | |
7643 | (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); | |
7644 | wr32(reg_offset, reg_val); | |
7645 | ||
7646 | adapter->vf_data[vf].spoofchk_enabled = setting; | |
7647 | return E1000_SUCCESS; | |
7648 | } | |
7649 | ||
8151d294 WM |
7650 | static int igb_ndo_get_vf_config(struct net_device *netdev, |
7651 | int vf, struct ifla_vf_info *ivi) | |
7652 | { | |
7653 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7654 | if (vf >= adapter->vfs_allocated_count) | |
7655 | return -EINVAL; | |
7656 | ivi->vf = vf; | |
7657 | memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); | |
17dc566c | 7658 | ivi->tx_rate = adapter->vf_data[vf].tx_rate; |
8151d294 WM |
7659 | ivi->vlan = adapter->vf_data[vf].pf_vlan; |
7660 | ivi->qos = adapter->vf_data[vf].pf_qos; | |
70ea4783 | 7661 | ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; |
8151d294 WM |
7662 | return 0; |
7663 | } | |
7664 | ||
4ae196df AD |
7665 | static void igb_vmm_control(struct igb_adapter *adapter) |
7666 | { | |
7667 | struct e1000_hw *hw = &adapter->hw; | |
10d8e907 | 7668 | u32 reg; |
4ae196df | 7669 | |
52a1dd4d AD |
7670 | switch (hw->mac.type) { |
7671 | case e1000_82575: | |
f96a8a0b CW |
7672 | case e1000_i210: |
7673 | case e1000_i211: | |
ceb5f13b | 7674 | case e1000_i354: |
52a1dd4d AD |
7675 | default: |
7676 | /* replication is not supported for 82575 */ | |
4ae196df | 7677 | return; |
52a1dd4d AD |
7678 | case e1000_82576: |
7679 | /* notify HW that the MAC is adding vlan tags */ | |
7680 | reg = rd32(E1000_DTXCTL); | |
7681 | reg |= E1000_DTXCTL_VLAN_ADDED; | |
7682 | wr32(E1000_DTXCTL, reg); | |
7683 | case e1000_82580: | |
7684 | /* enable replication vlan tag stripping */ | |
7685 | reg = rd32(E1000_RPLOLR); | |
7686 | reg |= E1000_RPLOLR_STRVLAN; | |
7687 | wr32(E1000_RPLOLR, reg); | |
d2ba2ed8 AD |
7688 | case e1000_i350: |
7689 | /* none of the above registers are supported by i350 */ | |
52a1dd4d AD |
7690 | break; |
7691 | } | |
10d8e907 | 7692 | |
d4960307 AD |
7693 | if (adapter->vfs_allocated_count) { |
7694 | igb_vmdq_set_loopback_pf(hw, true); | |
7695 | igb_vmdq_set_replication_pf(hw, true); | |
13800469 | 7696 | igb_vmdq_set_anti_spoofing_pf(hw, true, |
b980ac18 | 7697 | adapter->vfs_allocated_count); |
d4960307 AD |
7698 | } else { |
7699 | igb_vmdq_set_loopback_pf(hw, false); | |
7700 | igb_vmdq_set_replication_pf(hw, false); | |
7701 | } | |
4ae196df AD |
7702 | } |
7703 | ||
b6e0c419 CW |
7704 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) |
7705 | { | |
7706 | struct e1000_hw *hw = &adapter->hw; | |
7707 | u32 dmac_thr; | |
7708 | u16 hwm; | |
7709 | ||
7710 | if (hw->mac.type > e1000_82580) { | |
7711 | if (adapter->flags & IGB_FLAG_DMAC) { | |
7712 | u32 reg; | |
7713 | ||
7714 | /* force threshold to 0. */ | |
7715 | wr32(E1000_DMCTXTH, 0); | |
7716 | ||
b980ac18 | 7717 | /* DMA Coalescing high water mark needs to be greater |
e8c626e9 MV |
7718 | * than the Rx threshold. Set hwm to PBA - max frame |
7719 | * size in 16B units, capping it at PBA - 6KB. | |
b6e0c419 | 7720 | */ |
e8c626e9 MV |
7721 | hwm = 64 * pba - adapter->max_frame_size / 16; |
7722 | if (hwm < 64 * (pba - 6)) | |
7723 | hwm = 64 * (pba - 6); | |
7724 | reg = rd32(E1000_FCRTC); | |
7725 | reg &= ~E1000_FCRTC_RTH_COAL_MASK; | |
7726 | reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) | |
7727 | & E1000_FCRTC_RTH_COAL_MASK); | |
7728 | wr32(E1000_FCRTC, reg); | |
7729 | ||
b980ac18 | 7730 | /* Set the DMA Coalescing Rx threshold to PBA - 2 * max |
e8c626e9 MV |
7731 | * frame size, capping it at PBA - 10KB. |
7732 | */ | |
7733 | dmac_thr = pba - adapter->max_frame_size / 512; | |
7734 | if (dmac_thr < pba - 10) | |
7735 | dmac_thr = pba - 10; | |
b6e0c419 CW |
7736 | reg = rd32(E1000_DMACR); |
7737 | reg &= ~E1000_DMACR_DMACTHR_MASK; | |
b6e0c419 CW |
7738 | reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) |
7739 | & E1000_DMACR_DMACTHR_MASK); | |
7740 | ||
7741 | /* transition to L0x or L1 if available..*/ | |
7742 | reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); | |
7743 | ||
7744 | /* watchdog timer= +-1000 usec in 32usec intervals */ | |
7745 | reg |= (1000 >> 5); | |
0c02dd98 MV |
7746 | |
7747 | /* Disable BMC-to-OS Watchdog Enable */ | |
ceb5f13b CW |
7748 | if (hw->mac.type != e1000_i354) |
7749 | reg &= ~E1000_DMACR_DC_BMC2OSW_EN; | |
7750 | ||
b6e0c419 CW |
7751 | wr32(E1000_DMACR, reg); |
7752 | ||
b980ac18 | 7753 | /* no lower threshold to disable |
b6e0c419 CW |
7754 | * coalescing(smart fifb)-UTRESH=0 |
7755 | */ | |
7756 | wr32(E1000_DMCRTRH, 0); | |
b6e0c419 CW |
7757 | |
7758 | reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); | |
7759 | ||
7760 | wr32(E1000_DMCTLX, reg); | |
7761 | ||
b980ac18 | 7762 | /* free space in tx packet buffer to wake from |
b6e0c419 CW |
7763 | * DMA coal |
7764 | */ | |
7765 | wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - | |
7766 | (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); | |
7767 | ||
b980ac18 | 7768 | /* make low power state decision controlled |
b6e0c419 CW |
7769 | * by DMA coal |
7770 | */ | |
7771 | reg = rd32(E1000_PCIEMISC); | |
7772 | reg &= ~E1000_PCIEMISC_LX_DECISION; | |
7773 | wr32(E1000_PCIEMISC, reg); | |
7774 | } /* endif adapter->dmac is not disabled */ | |
7775 | } else if (hw->mac.type == e1000_82580) { | |
7776 | u32 reg = rd32(E1000_PCIEMISC); | |
7777 | wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); | |
7778 | wr32(E1000_DMACR, 0); | |
7779 | } | |
7780 | } | |
7781 | ||
b980ac18 JK |
7782 | /** |
7783 | * igb_read_i2c_byte - Reads 8 bit word over I2C | |
441fc6fd CW |
7784 | * @hw: pointer to hardware structure |
7785 | * @byte_offset: byte offset to read | |
7786 | * @dev_addr: device address | |
7787 | * @data: value read | |
7788 | * | |
7789 | * Performs byte read operation over I2C interface at | |
7790 | * a specified device address. | |
b980ac18 | 7791 | **/ |
441fc6fd | 7792 | s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, |
b980ac18 | 7793 | u8 dev_addr, u8 *data) |
441fc6fd CW |
7794 | { |
7795 | struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); | |
603e86fa | 7796 | struct i2c_client *this_client = adapter->i2c_client; |
441fc6fd CW |
7797 | s32 status; |
7798 | u16 swfw_mask = 0; | |
7799 | ||
7800 | if (!this_client) | |
7801 | return E1000_ERR_I2C; | |
7802 | ||
7803 | swfw_mask = E1000_SWFW_PHY0_SM; | |
7804 | ||
7805 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) | |
7806 | != E1000_SUCCESS) | |
7807 | return E1000_ERR_SWFW_SYNC; | |
7808 | ||
7809 | status = i2c_smbus_read_byte_data(this_client, byte_offset); | |
7810 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | |
7811 | ||
7812 | if (status < 0) | |
7813 | return E1000_ERR_I2C; | |
7814 | else { | |
7815 | *data = status; | |
7816 | return E1000_SUCCESS; | |
7817 | } | |
7818 | } | |
7819 | ||
b980ac18 JK |
7820 | /** |
7821 | * igb_write_i2c_byte - Writes 8 bit word over I2C | |
441fc6fd CW |
7822 | * @hw: pointer to hardware structure |
7823 | * @byte_offset: byte offset to write | |
7824 | * @dev_addr: device address | |
7825 | * @data: value to write | |
7826 | * | |
7827 | * Performs byte write operation over I2C interface at | |
7828 | * a specified device address. | |
b980ac18 | 7829 | **/ |
441fc6fd | 7830 | s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, |
b980ac18 | 7831 | u8 dev_addr, u8 data) |
441fc6fd CW |
7832 | { |
7833 | struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); | |
603e86fa | 7834 | struct i2c_client *this_client = adapter->i2c_client; |
441fc6fd CW |
7835 | s32 status; |
7836 | u16 swfw_mask = E1000_SWFW_PHY0_SM; | |
7837 | ||
7838 | if (!this_client) | |
7839 | return E1000_ERR_I2C; | |
7840 | ||
7841 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) | |
7842 | return E1000_ERR_SWFW_SYNC; | |
7843 | status = i2c_smbus_write_byte_data(this_client, byte_offset, data); | |
7844 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | |
7845 | ||
7846 | if (status) | |
7847 | return E1000_ERR_I2C; | |
7848 | else | |
7849 | return E1000_SUCCESS; | |
7850 | ||
7851 | } | |
9d5c8243 | 7852 | /* igb_main.c */ |