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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
200e5fd5 63#define MAJ 4
6699938b
CW		 64#define MIN 1
65#define BUILD 2
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
110 /* required last entry */
111 {0, }
112};
113
114MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
115
116void igb_reset(struct igb_adapter *);
117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c8f44aff 158static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 159static int igb_vlan_rx_add_vid(struct net_device *, u16);
160static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 161static void igb_restore_vlan(struct igb_adapter *);
26ad9178 162static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 163static void igb_ping_all_vfs(struct igb_adapter *);
164static void igb_msg_task(struct igb_adapter *);
4ae196df 165static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 166static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 167static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 168static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
169static int igb_ndo_set_vf_vlan(struct net_device *netdev,
170 int vf, u16 vlan, u8 qos);
171static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
172static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
173 struct ifla_vf_info *ivi);
17dc566c 174static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 175
176#ifdef CONFIG_PCI_IOV
0224d663 177static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 178static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 179#endif
9d5c8243 180
9d5c8243 181#ifdef CONFIG_PM
d9dd966d 182#ifdef CONFIG_PM_SLEEP
749ab2cd 183static int igb_suspend(struct device *);
d9dd966d 184#endif
749ab2cd
YZ		 185static int igb_resume(struct device *);
186#ifdef CONFIG_PM_RUNTIME
187static int igb_runtime_suspend(struct device *dev);
188static int igb_runtime_resume(struct device *dev);
189static int igb_runtime_idle(struct device *dev);
190#endif
191static const struct dev_pm_ops igb_pm_ops = {
192 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
193 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
194 igb_runtime_idle)
195};
9d5c8243
AK		 196#endif
197static void igb_shutdown(struct pci_dev *);
fa44f2f1 198static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 199#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 200static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
201static struct notifier_block dca_notifier = {
202 .notifier_call = igb_notify_dca,
203 .next = NULL,
204 .priority = 0
205};
206#endif
9d5c8243
AK		 207#ifdef CONFIG_NET_POLL_CONTROLLER
208/* for netdump / net console */
209static void igb_netpoll(struct net_device *);
210#endif
37680117 211#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 212static unsigned int max_vfs = 0;
213module_param(max_vfs, uint, 0);
214MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
215 "per physical function");
216#endif /* CONFIG_PCI_IOV */
217
9d5c8243
AK		 218static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221static void igb_io_resume(struct pci_dev *);
222
3646f0e5 223static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227};
228
b6e0c419 229static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 230
231static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
9f9a12f8 235 .remove = igb_remove,
9d5c8243 236#ifdef CONFIG_PM
749ab2cd 237 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 238#endif
239 .shutdown = igb_shutdown,
fa44f2f1 240 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 241 .err_handler = &igb_err_handler
242};
243
244MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246MODULE_LICENSE("GPL");
247MODULE_VERSION(DRV_VERSION);
248
b3f4d599 249#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250static int debug = -1;
251module_param(debug, int, 0);
252MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
c97ec42a
TI		 254struct igb_reg_info {
255 u32 ofs;
256 char *name;
257};
258
259static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293};
294
295/*
296 * igb_regdump - register printout routine
297 */
298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
363/*
364 * igb_dump - Print registers, tx-rings and rx-rings
365 */
366static void igb_dump(struct igb_adapter *adapter)
367{
368 struct net_device *netdev = adapter->netdev;
369 struct e1000_hw *hw = &adapter->hw;
370 struct igb_reg_info *reginfo;
c97ec42a
TI		 371 struct igb_ring *tx_ring;
372 union e1000_adv_tx_desc *tx_desc;
373 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 374 struct igb_ring *rx_ring;
375 union e1000_adv_rx_desc *rx_desc;
376 u32 staterr;
6ad4edfc 377 u16 i, n;
c97ec42a
TI		 378
379 if (!netif_msg_hw(adapter))
380 return;
381
382 /* Print netdevice Info */
383 if (netdev) {
384 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 385 pr_info("Device Name state trans_start "
386 "last_rx\n");
387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
388 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 389 }
390
391 /* Print Registers */
392 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 393 pr_info(" Register Name Value\n");
c97ec42a
TI		 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
395 reginfo->name; reginfo++) {
396 igb_regdump(hw, reginfo);
397 }
398
399 /* Print TX Ring Summary */
400 if (!netdev || !netif_running(netdev))
401 goto exit;
402
403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 405 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 406 struct igb_tx_buffer *buffer_info;
c97ec42a 407 tx_ring = adapter->tx_ring[n];
06034649 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
410 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 411 (u64)dma_unmap_addr(buffer_info, dma),
412 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp);
c97ec42a
TI		 415 }
416
417 /* Print TX Rings */
418 if (!netif_msg_tx_done(adapter))
419 goto rx_ring_summary;
420
421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
422
423 /* Transmit Descriptor Formats
424 *
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
432 */
433
434 for (n = 0; n < adapter->num_tx_queues; n++) {
435 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 436 pr_info("------------------------------------\n");
437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
438 pr_info("------------------------------------\n");
439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
440 "[bi->dma ] leng ntw timestamp "
441 "bi->skb\n");
c97ec42a
TI		 442
443 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 444 const char *next_desc;
06034649 445 struct igb_tx_buffer *buffer_info;
60136906 446 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 447 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 448 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 449 if (i == tx_ring->next_to_use &&
450 i == tx_ring->next_to_clean)
451 next_desc = " NTC/U";
452 else if (i == tx_ring->next_to_use)
453 next_desc = " NTU";
454 else if (i == tx_ring->next_to_clean)
455 next_desc = " NTC";
456 else
457 next_desc = "";
458
459 pr_info("T [0x%03X] %016llX %016llX %016llX"
460 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 461 le64_to_cpu(u0->a),
462 le64_to_cpu(u0->b),
c9f14bf3
AD		 463 (u64)dma_unmap_addr(buffer_info, dma),
464 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 465 buffer_info->next_to_watch,
466 (u64)buffer_info->time_stamp,
876d2d6f 467 buffer_info->skb, next_desc);
c97ec42a 468
b669588a 469 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 470 print_hex_dump(KERN_INFO, "",
471 DUMP_PREFIX_ADDRESS,
b669588a 472 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 473 dma_unmap_len(buffer_info, len),
474 true);
c97ec42a
TI		 475 }
476 }
477
478 /* Print RX Rings Summary */
479rx_ring_summary:
480 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 481 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 482 for (n = 0; n < adapter->num_rx_queues; n++) {
483 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 484 pr_info(" %5d %5X %5X\n",
485 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 486 }
487
488 /* Print RX Rings */
489 if (!netif_msg_rx_status(adapter))
490 goto exit;
491
492 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
493
494 /* Advanced Receive Descriptor (Read) Format
495 * 63 1 0
496 * +-----------------------------------------------------+
497 * 0 | Packet Buffer Address [63:1] |A0/NSE|
498 * +----------------------------------------------+------+
499 * 8 | Header Buffer Address [63:1] | DD |
500 * +-----------------------------------------------------+
501 *
502 *
503 * Advanced Receive Descriptor (Write-Back) Format
504 *
505 * 63 48 47 32 31 30 21 20 17 16 4 3 0
506 * +------------------------------------------------------+
507 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
508 * | Checksum Ident | | | | Type | Type |
509 * +------------------------------------------------------+
510 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
511 * +------------------------------------------------------+
512 * 63 48 47 32 31 20 19 0
513 */
514
515 for (n = 0; n < adapter->num_rx_queues; n++) {
516 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 517 pr_info("------------------------------------\n");
518 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
521 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
522 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
523 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 524
525 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 526 const char *next_desc;
06034649
AD		 527 struct igb_rx_buffer *buffer_info;
528 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 529 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 530 u0 = (struct my_u0 *)rx_desc;
531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 532
533 if (i == rx_ring->next_to_use)
534 next_desc = " NTU";
535 else if (i == rx_ring->next_to_clean)
536 next_desc = " NTC";
537 else
538 next_desc = "";
539
c97ec42a
TI		 540 if (staterr & E1000_RXD_STAT_DD) {
541 /* Descriptor Done */
1a1c225b
AD		 542 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
543 "RWB", i,
c97ec42a
TI		 544 le64_to_cpu(u0->a),
545 le64_to_cpu(u0->b),
1a1c225b 546 next_desc);
c97ec42a 547 } else {
1a1c225b
AD		 548 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
549 "R ", i,
c97ec42a
TI		 550 le64_to_cpu(u0->a),
551 le64_to_cpu(u0->b),
552 (u64)buffer_info->dma,
1a1c225b 553 next_desc);
c97ec42a 554
b669588a 555 if (netif_msg_pktdata(adapter) &&
1a1c225b 556 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 557 print_hex_dump(KERN_INFO, "",
558 DUMP_PREFIX_ADDRESS,
559 16, 1,
b669588a
ET		 560 page_address(buffer_info->page) +
561 buffer_info->page_offset,
de78d1f9 562 IGB_RX_BUFSZ, true);
c97ec42a
TI		 563 }
564 }
c97ec42a
TI		 565 }
566 }
567
568exit:
569 return;
570}
571
441fc6fd
CW		 572/* igb_get_i2c_data - Reads the I2C SDA data bit
573 * @hw: pointer to hardware structure
574 * @i2cctl: Current value of I2CCTL register
575 *
576 * Returns the I2C data bit value
577 */
578static int igb_get_i2c_data(void *data)
579{
580 struct igb_adapter *adapter = (struct igb_adapter *)data;
581 struct e1000_hw *hw = &adapter->hw;
582 s32 i2cctl = rd32(E1000_I2CPARAMS);
583
584 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
585}
586
587/* igb_set_i2c_data - Sets the I2C data bit
588 * @data: pointer to hardware structure
589 * @state: I2C data value (0 or 1) to set
590 *
591 * Sets the I2C data bit
592 */
593static void igb_set_i2c_data(void *data, int state)
594{
595 struct igb_adapter *adapter = (struct igb_adapter *)data;
596 struct e1000_hw *hw = &adapter->hw;
597 s32 i2cctl = rd32(E1000_I2CPARAMS);
598
599 if (state)
600 i2cctl |= E1000_I2C_DATA_OUT;
601 else
602 i2cctl &= ~E1000_I2C_DATA_OUT;
603
604 i2cctl &= ~E1000_I2C_DATA_OE_N;
605 i2cctl |= E1000_I2C_CLK_OE_N;
606 wr32(E1000_I2CPARAMS, i2cctl);
607 wrfl();
608
609}
610
611/* igb_set_i2c_clk - Sets the I2C SCL clock
612 * @data: pointer to hardware structure
613 * @state: state to set clock
614 *
615 * Sets the I2C clock line to state
616 */
617static void igb_set_i2c_clk(void *data, int state)
618{
619 struct igb_adapter *adapter = (struct igb_adapter *)data;
620 struct e1000_hw *hw = &adapter->hw;
621 s32 i2cctl = rd32(E1000_I2CPARAMS);
622
623 if (state) {
624 i2cctl |= E1000_I2C_CLK_OUT;
625 i2cctl &= ~E1000_I2C_CLK_OE_N;
626 } else {
627 i2cctl &= ~E1000_I2C_CLK_OUT;
628 i2cctl &= ~E1000_I2C_CLK_OE_N;
629 }
630 wr32(E1000_I2CPARAMS, i2cctl);
631 wrfl();
632}
633
634/* igb_get_i2c_clk - Gets the I2C SCL clock state
635 * @data: pointer to hardware structure
636 *
637 * Gets the I2C clock state
638 */
639static int igb_get_i2c_clk(void *data)
640{
641 struct igb_adapter *adapter = (struct igb_adapter *)data;
642 struct e1000_hw *hw = &adapter->hw;
643 s32 i2cctl = rd32(E1000_I2CPARAMS);
644
645 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
646}
647
648static const struct i2c_algo_bit_data igb_i2c_algo = {
649 .setsda = igb_set_i2c_data,
650 .setscl = igb_set_i2c_clk,
651 .getsda = igb_get_i2c_data,
652 .getscl = igb_get_i2c_clk,
653 .udelay = 5,
654 .timeout = 20,
655};
656
9d5c8243 657/**
c041076a 658 * igb_get_hw_dev - return device
9d5c8243
AK		 659 * used by hardware layer to print debugging information
660 **/
c041076a 661struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 662{
663 struct igb_adapter *adapter = hw->back;
c041076a 664 return adapter->netdev;
9d5c8243 665}
38c845c7 666
9d5c8243
AK		 667/**
668 * igb_init_module - Driver Registration Routine
669 *
670 * igb_init_module is the first routine called when the driver is
671 * loaded. All it does is register with the PCI subsystem.
672 **/
673static int __init igb_init_module(void)
674{
675 int ret;
876d2d6f 676 pr_info("%s - version %s\n",
9d5c8243
AK		 677 igb_driver_string, igb_driver_version);
678
876d2d6f 679 pr_info("%s\n", igb_copyright);
9d5c8243 680
421e02f0 681#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 682 dca_register_notify(&dca_notifier);
683#endif
bbd98fe4 684 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 685 return ret;
686}
687
688module_init(igb_init_module);
689
690/**
691 * igb_exit_module - Driver Exit Cleanup Routine
692 *
693 * igb_exit_module is called just before the driver is removed
694 * from memory.
695 **/
696static void __exit igb_exit_module(void)
697{
421e02f0 698#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 699 dca_unregister_notify(&dca_notifier);
700#endif
9d5c8243
AK		 701 pci_unregister_driver(&igb_driver);
702}
703
704module_exit(igb_exit_module);
705
26bc19ec
AD		 706#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
707/**
708 * igb_cache_ring_register - Descriptor ring to register mapping
709 * @adapter: board private structure to initialize
710 *
711 * Once we know the feature-set enabled for the device, we'll cache
712 * the register offset the descriptor ring is assigned to.
713 **/
714static void igb_cache_ring_register(struct igb_adapter *adapter)
715{
ee1b9f06 716 int i = 0, j = 0;
047e0030 717 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 718
719 switch (adapter->hw.mac.type) {
720 case e1000_82576:
721 /* The queues are allocated for virtualization such that VF 0
722 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
723 * In order to avoid collision we start at the first free queue
724 * and continue consuming queues in the same sequence
725 */
ee1b9f06 726 if (adapter->vfs_allocated_count) {
a99955fc 727 for (; i < adapter->rss_queues; i++)
3025a446
AD		 728 adapter->rx_ring[i]->reg_idx = rbase_offset +
729 Q_IDX_82576(i);
ee1b9f06 730 }
26bc19ec 731 case e1000_82575:
55cac248 732 case e1000_82580:
d2ba2ed8 733 case e1000_i350:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
26bc19ec 736 default:
ee1b9f06 737 for (; i < adapter->num_rx_queues; i++)
3025a446 738 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 739 for (; j < adapter->num_tx_queues; j++)
3025a446 740 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 741 break;
742 }
743}
744
4be000c8
AD		 745/**
746 * igb_write_ivar - configure ivar for given MSI-X vector
747 * @hw: pointer to the HW structure
748 * @msix_vector: vector number we are allocating to a given ring
749 * @index: row index of IVAR register to write within IVAR table
750 * @offset: column offset of in IVAR, should be multiple of 8
751 *
752 * This function is intended to handle the writing of the IVAR register
753 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
754 * each containing an cause allocation for an Rx and Tx ring, and a
755 * variable number of rows depending on the number of queues supported.
756 **/
757static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
758 int index, int offset)
759{
760 u32 ivar = array_rd32(E1000_IVAR0, index);
761
762 /* clear any bits that are currently set */
763 ivar &= ~((u32)0xFF << offset);
764
765 /* write vector and valid bit */
766 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
767
768 array_wr32(E1000_IVAR0, index, ivar);
769}
770
9d5c8243 771#define IGB_N0_QUEUE -1
047e0030 772static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 773{
047e0030 774 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 775 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 776 int rx_queue = IGB_N0_QUEUE;
777 int tx_queue = IGB_N0_QUEUE;
4be000c8 778 u32 msixbm = 0;
047e0030 779
0ba82994
AD		 780 if (q_vector->rx.ring)
781 rx_queue = q_vector->rx.ring->reg_idx;
782 if (q_vector->tx.ring)
783 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 784
785 switch (hw->mac.type) {
786 case e1000_82575:
9d5c8243
AK		 787 /* The 82575 assigns vectors using a bitmask, which matches the
788 bitmask for the EICR/EIMS/EIMC registers. To assign one
789 or more queues to a vector, we write the appropriate bits
790 into the MSIXBM register for that vector. */
047e0030 791 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 792 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 793 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 794 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 795 if (!adapter->msix_entries && msix_vector == 0)
796 msixbm |= E1000_EIMS_OTHER;
9d5c8243 797 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 798 q_vector->eims_value = msixbm;
2d064c06
AD		 799 break;
800 case e1000_82576:
4be000c8
AD		 801 /*
802 * 82576 uses a table that essentially consists of 2 columns
803 * with 8 rows. The ordering is column-major so we use the
804 * lower 3 bits as the row index, and the 4th bit as the
805 * column offset.
806 */
807 if (rx_queue > IGB_N0_QUEUE)
808 igb_write_ivar(hw, msix_vector,
809 rx_queue & 0x7,
810 (rx_queue & 0x8) << 1);
811 if (tx_queue > IGB_N0_QUEUE)
812 igb_write_ivar(hw, msix_vector,
813 tx_queue & 0x7,
814 ((tx_queue & 0x8) << 1) + 8);
047e0030 815 q_vector->eims_value = 1 << msix_vector;
2d064c06 816 break;
55cac248 817 case e1000_82580:
d2ba2ed8 818 case e1000_i350:
f96a8a0b
CW		 819 case e1000_i210:
820 case e1000_i211:
4be000c8
AD		 821 /*
822 * On 82580 and newer adapters the scheme is similar to 82576
823 * however instead of ordering column-major we have things
824 * ordered row-major. So we traverse the table by using
825 * bit 0 as the column offset, and the remaining bits as the
826 * row index.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue >> 1,
831 (rx_queue & 0x1) << 4);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue >> 1,
835 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 836 q_vector->eims_value = 1 << msix_vector;
837 break;
2d064c06
AD		 838 default:
839 BUG();
840 break;
841 }
26b39276
AD		 842
843 /* add q_vector eims value to global eims_enable_mask */
844 adapter->eims_enable_mask |= q_vector->eims_value;
845
846 /* configure q_vector to set itr on first interrupt */
847 q_vector->set_itr = 1;
9d5c8243
AK		 848}
849
850/**
851 * igb_configure_msix - Configure MSI-X hardware
852 *
853 * igb_configure_msix sets up the hardware to properly
854 * generate MSI-X interrupts.
855 **/
856static void igb_configure_msix(struct igb_adapter *adapter)
857{
858 u32 tmp;
859 int i, vector = 0;
860 struct e1000_hw *hw = &adapter->hw;
861
862 adapter->eims_enable_mask = 0;
9d5c8243
AK		 863
864 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 865 switch (hw->mac.type) {
866 case e1000_82575:
9d5c8243
AK		 867 tmp = rd32(E1000_CTRL_EXT);
868 /* enable MSI-X PBA support*/
869 tmp |= E1000_CTRL_EXT_PBA_CLR;
870
871 /* Auto-Mask interrupts upon ICR read. */
872 tmp |= E1000_CTRL_EXT_EIAME;
873 tmp |= E1000_CTRL_EXT_IRCA;
874
875 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 876
877 /* enable msix_other interrupt */
878 array_wr32(E1000_MSIXBM(0), vector++,
879 E1000_EIMS_OTHER);
844290e5 880 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 881
2d064c06
AD		 882 break;
883
884 case e1000_82576:
55cac248 885 case e1000_82580:
d2ba2ed8 886 case e1000_i350:
f96a8a0b
CW		 887 case e1000_i210:
888 case e1000_i211:
047e0030
AD		 889 /* Turn on MSI-X capability first, or our settings
890 * won't stick. And it will take days to debug. */
891 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
892 E1000_GPIE_PBA | E1000_GPIE_EIAME |
893 E1000_GPIE_NSICR);
894
895 /* enable msix_other interrupt */
896 adapter->eims_other = 1 << vector;
2d064c06 897 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 898
047e0030 899 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 900 break;
901 default:
902 /* do nothing, since nothing else supports MSI-X */
903 break;
904 } /* switch (hw->mac.type) */
047e0030
AD		 905
906 adapter->eims_enable_mask |= adapter->eims_other;
907
26b39276
AD		 908 for (i = 0; i < adapter->num_q_vectors; i++)
909 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 910
9d5c8243
AK		 911 wrfl();
912}
913
914/**
915 * igb_request_msix - Initialize MSI-X interrupts
916 *
917 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
918 * kernel.
919 **/
920static int igb_request_msix(struct igb_adapter *adapter)
921{
922 struct net_device *netdev = adapter->netdev;
047e0030 923 struct e1000_hw *hw = &adapter->hw;
52285b76 924 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 925
047e0030 926 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 927 igb_msix_other, 0, netdev->name, adapter);
047e0030 928 if (err)
52285b76 929 goto err_out;
047e0030
AD		 930
931 for (i = 0; i < adapter->num_q_vectors; i++) {
932 struct igb_q_vector *q_vector = adapter->q_vector[i];
933
52285b76
SA		 934 vector++;
935
047e0030
AD		 936 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
937
0ba82994 938 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 939 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 940 q_vector->rx.ring->queue_index);
941 else if (q_vector->tx.ring)
047e0030 942 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 943 q_vector->tx.ring->queue_index);
944 else if (q_vector->rx.ring)
047e0030 945 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 946 q_vector->rx.ring->queue_index);
9d5c8243 947 else
047e0030
AD		 948 sprintf(q_vector->name, "%s-unused", netdev->name);
949
9d5c8243 950 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 951 igb_msix_ring, 0, q_vector->name,
047e0030 952 q_vector);
9d5c8243 953 if (err)
52285b76 954 goto err_free;
9d5c8243
AK		 955 }
956
9d5c8243
AK		 957 igb_configure_msix(adapter);
958 return 0;
52285b76
SA		 959
960err_free:
961 /* free already assigned IRQs */
962 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
963
964 vector--;
965 for (i = 0; i < vector; i++) {
966 free_irq(adapter->msix_entries[free_vector++].vector,
967 adapter->q_vector[i]);
968 }
969err_out:
9d5c8243
AK		 970 return err;
971}
972
973static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
974{
975 if (adapter->msix_entries) {
976 pci_disable_msix(adapter->pdev);
977 kfree(adapter->msix_entries);
978 adapter->msix_entries = NULL;
047e0030 979 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 980 pci_disable_msi(adapter->pdev);
047e0030 981 }
9d5c8243
AK		 982}
983
5536d210
AD		 984/**
985 * igb_free_q_vector - Free memory allocated for specific interrupt vector
986 * @adapter: board private structure to initialize
987 * @v_idx: Index of vector to be freed
988 *
989 * This function frees the memory allocated to the q_vector. In addition if
990 * NAPI is enabled it will delete any references to the NAPI struct prior
991 * to freeing the q_vector.
992 **/
993static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
994{
995 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
996
997 if (q_vector->tx.ring)
998 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
999
1000 if (q_vector->rx.ring)
1001 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1002
1003 adapter->q_vector[v_idx] = NULL;
1004 netif_napi_del(&q_vector->napi);
1005
1006 /*
1007 * ixgbe_get_stats64() might access the rings on this vector,
1008 * we must wait a grace period before freeing it.
1009 */
1010 kfree_rcu(q_vector, rcu);
1011}
1012
047e0030
AD		 1013/**
1014 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1015 * @adapter: board private structure to initialize
1016 *
1017 * This function frees the memory allocated to the q_vectors. In addition if
1018 * NAPI is enabled it will delete any references to the NAPI struct prior
1019 * to freeing the q_vector.
1020 **/
1021static void igb_free_q_vectors(struct igb_adapter *adapter)
1022{
5536d210
AD		 1023 int v_idx = adapter->num_q_vectors;
1024
1025 adapter->num_tx_queues = 0;
1026 adapter->num_rx_queues = 0;
047e0030 1027 adapter->num_q_vectors = 0;
5536d210
AD		 1028
1029 while (v_idx--)
1030 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1031}
1032
1033/**
1034 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1035 *
1036 * This function resets the device so that it has 0 rx queues, tx queues, and
1037 * MSI-X interrupts allocated.
1038 */
1039static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1040{
047e0030
AD		 1041 igb_free_q_vectors(adapter);
1042 igb_reset_interrupt_capability(adapter);
1043}
9d5c8243
AK		 1044
1045/**
1046 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1047 *
1048 * Attempt to configure interrupts using the best available
1049 * capabilities of the hardware and kernel.
1050 **/
53c7d064 1051static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1052{
1053 int err;
1054 int numvecs, i;
1055
53c7d064
SA		 1056 if (!msix)
1057 goto msi_only;
1058
83b7180d 1059 /* Number of supported queues. */
a99955fc 1060 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1061 if (adapter->vfs_allocated_count)
1062 adapter->num_tx_queues = 1;
1063 else
1064 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1065
047e0030
AD		 1066 /* start with one vector for every rx queue */
1067 numvecs = adapter->num_rx_queues;
1068
3ad2f3fb 1069 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1070 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1071 numvecs += adapter->num_tx_queues;
047e0030
AD		 1072
1073 /* store the number of vectors reserved for queues */
1074 adapter->num_q_vectors = numvecs;
1075
1076 /* add 1 vector for link status interrupts */
1077 numvecs++;
9d5c8243
AK		 1078 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1079 GFP_KERNEL);
f96a8a0b 1080
9d5c8243
AK		 1081 if (!adapter->msix_entries)
1082 goto msi_only;
1083
1084 for (i = 0; i < numvecs; i++)
1085 adapter->msix_entries[i].entry = i;
1086
1087 err = pci_enable_msix(adapter->pdev,
1088 adapter->msix_entries,
1089 numvecs);
1090 if (err == 0)
0c2cc02e 1091 return;
9d5c8243
AK		 1092
1093 igb_reset_interrupt_capability(adapter);
1094
1095 /* If we can't do MSI-X, try MSI */
1096msi_only:
2a3abf6d
AD		 1097#ifdef CONFIG_PCI_IOV
1098 /* disable SR-IOV for non MSI-X configurations */
1099 if (adapter->vf_data) {
1100 struct e1000_hw *hw = &adapter->hw;
1101 /* disable iov and allow time for transactions to clear */
1102 pci_disable_sriov(adapter->pdev);
1103 msleep(500);
1104
1105 kfree(adapter->vf_data);
1106 adapter->vf_data = NULL;
1107 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1108 wrfl();
2a3abf6d
AD		 1109 msleep(100);
1110 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1111 }
1112#endif
4fc82adf 1113 adapter->vfs_allocated_count = 0;
a99955fc 1114 adapter->rss_queues = 1;
4fc82adf 1115 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1116 adapter->num_rx_queues = 1;
661086df 1117 adapter->num_tx_queues = 1;
047e0030 1118 adapter->num_q_vectors = 1;
9d5c8243 1119 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1120 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1121}
1122
5536d210
AD		 1123static void igb_add_ring(struct igb_ring *ring,
1124 struct igb_ring_container *head)
1125{
1126 head->ring = ring;
1127 head->count++;
1128}
1129
047e0030 1130/**
5536d210 1131 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1132 * @adapter: board private structure to initialize
5536d210
AD		 1133 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1134 * @v_idx: index of vector in adapter struct
1135 * @txr_count: total number of Tx rings to allocate
1136 * @txr_idx: index of first Tx ring to allocate
1137 * @rxr_count: total number of Rx rings to allocate
1138 * @rxr_idx: index of first Rx ring to allocate
047e0030 1139 *
5536d210 1140 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1141 **/
5536d210
AD		 1142static int igb_alloc_q_vector(struct igb_adapter *adapter,
1143 int v_count, int v_idx,
1144 int txr_count, int txr_idx,
1145 int rxr_count, int rxr_idx)
047e0030
AD		 1146{
1147 struct igb_q_vector *q_vector;
5536d210
AD		 1148 struct igb_ring *ring;
1149 int ring_count, size;
047e0030 1150
5536d210
AD		 1151 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1152 if (txr_count > 1 || rxr_count > 1)
1153 return -ENOMEM;
1154
1155 ring_count = txr_count + rxr_count;
1156 size = sizeof(struct igb_q_vector) +
1157 (sizeof(struct igb_ring) * ring_count);
1158
1159 /* allocate q_vector and rings */
1160 q_vector = kzalloc(size, GFP_KERNEL);
1161 if (!q_vector)
1162 return -ENOMEM;
1163
1164 /* initialize NAPI */
1165 netif_napi_add(adapter->netdev, &q_vector->napi,
1166 igb_poll, 64);
1167
1168 /* tie q_vector and adapter together */
1169 adapter->q_vector[v_idx] = q_vector;
1170 q_vector->adapter = adapter;
1171
1172 /* initialize work limits */
1173 q_vector->tx.work_limit = adapter->tx_work_limit;
1174
1175 /* initialize ITR configuration */
1176 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1177 q_vector->itr_val = IGB_START_ITR;
1178
1179 /* initialize pointer to rings */
1180 ring = q_vector->ring;
1181
1182 if (txr_count) {
1183 /* assign generic ring traits */
1184 ring->dev = &adapter->pdev->dev;
1185 ring->netdev = adapter->netdev;
1186
1187 /* configure backlink on ring */
1188 ring->q_vector = q_vector;
1189
1190 /* update q_vector Tx values */
1191 igb_add_ring(ring, &q_vector->tx);
1192
1193 /* For 82575, context index must be unique per ring. */
1194 if (adapter->hw.mac.type == e1000_82575)
1195 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1196
1197 /* apply Tx specific ring traits */
1198 ring->count = adapter->tx_ring_count;
1199 ring->queue_index = txr_idx;
1200
1201 /* assign ring to adapter */
1202 adapter->tx_ring[txr_idx] = ring;
1203
1204 /* push pointer to next ring */
1205 ring++;
047e0030 1206 }
81c2fc22 1207
5536d210
AD		 1208 if (rxr_count) {
1209 /* assign generic ring traits */
1210 ring->dev = &adapter->pdev->dev;
1211 ring->netdev = adapter->netdev;
047e0030 1212
5536d210
AD		 1213 /* configure backlink on ring */
1214 ring->q_vector = q_vector;
047e0030 1215
5536d210
AD		 1216 /* update q_vector Rx values */
1217 igb_add_ring(ring, &q_vector->rx);
047e0030 1218
5536d210
AD		 1219 /* set flag indicating ring supports SCTP checksum offload */
1220 if (adapter->hw.mac.type >= e1000_82576)
1221 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1222
5536d210
AD		 1223 /*
1224 * On i350, i210, and i211, loopback VLAN packets
1225 * have the tag byte-swapped.
1226 * */
1227 if (adapter->hw.mac.type >= e1000_i350)
1228 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1229
5536d210
AD		 1230 /* apply Rx specific ring traits */
1231 ring->count = adapter->rx_ring_count;
1232 ring->queue_index = rxr_idx;
1233
1234 /* assign ring to adapter */
1235 adapter->rx_ring[rxr_idx] = ring;
1236 }
1237
1238 return 0;
047e0030
AD		 1239}
1240
5536d210 1241
047e0030 1242/**
5536d210
AD		 1243 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1244 * @adapter: board private structure to initialize
047e0030 1245 *
5536d210
AD		 1246 * We allocate one q_vector per queue interrupt. If allocation fails we
1247 * return -ENOMEM.
047e0030 1248 **/
5536d210 1249static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1250{
5536d210
AD		 1251 int q_vectors = adapter->num_q_vectors;
1252 int rxr_remaining = adapter->num_rx_queues;
1253 int txr_remaining = adapter->num_tx_queues;
1254 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1255 int err;
047e0030 1256
5536d210
AD		 1257 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1258 for (; rxr_remaining; v_idx++) {
1259 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1260 0, 0, 1, rxr_idx);
047e0030 1261
5536d210
AD		 1262 if (err)
1263 goto err_out;
1264
1265 /* update counts and index */
1266 rxr_remaining--;
1267 rxr_idx++;
047e0030 1268 }
047e0030 1269 }
5536d210
AD		 1270
1271 for (; v_idx < q_vectors; v_idx++) {
1272 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1273 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1274 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1275 tqpv, txr_idx, rqpv, rxr_idx);
1276
1277 if (err)
1278 goto err_out;
1279
1280 /* update counts and index */
1281 rxr_remaining -= rqpv;
1282 txr_remaining -= tqpv;
1283 rxr_idx++;
1284 txr_idx++;
1285 }
1286
047e0030 1287 return 0;
5536d210
AD		 1288
1289err_out:
1290 adapter->num_tx_queues = 0;
1291 adapter->num_rx_queues = 0;
1292 adapter->num_q_vectors = 0;
1293
1294 while (v_idx--)
1295 igb_free_q_vector(adapter, v_idx);
1296
1297 return -ENOMEM;
047e0030
AD		 1298}
1299
1300/**
1301 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1302 *
1303 * This function initializes the interrupts and allocates all of the queues.
1304 **/
53c7d064 1305static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1306{
1307 struct pci_dev *pdev = adapter->pdev;
1308 int err;
1309
53c7d064 1310 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1311
1312 err = igb_alloc_q_vectors(adapter);
1313 if (err) {
1314 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1315 goto err_alloc_q_vectors;
1316 }
1317
5536d210 1318 igb_cache_ring_register(adapter);
047e0030
AD		 1319
1320 return 0;
5536d210 1321
047e0030
AD		 1322err_alloc_q_vectors:
1323 igb_reset_interrupt_capability(adapter);
1324 return err;
1325}
1326
9d5c8243
AK		 1327/**
1328 * igb_request_irq - initialize interrupts
1329 *
1330 * Attempts to configure interrupts using the best available
1331 * capabilities of the hardware and kernel.
1332 **/
1333static int igb_request_irq(struct igb_adapter *adapter)
1334{
1335 struct net_device *netdev = adapter->netdev;
047e0030 1336 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1337 int err = 0;
1338
1339 if (adapter->msix_entries) {
1340 err = igb_request_msix(adapter);
844290e5 1341 if (!err)
9d5c8243 1342 goto request_done;
9d5c8243 1343 /* fall back to MSI */
5536d210
AD		 1344 igb_free_all_tx_resources(adapter);
1345 igb_free_all_rx_resources(adapter);
53c7d064 1346
047e0030 1347 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1348 err = igb_init_interrupt_scheme(adapter, false);
1349 if (err)
047e0030 1350 goto request_done;
53c7d064 1351
047e0030
AD		 1352 igb_setup_all_tx_resources(adapter);
1353 igb_setup_all_rx_resources(adapter);
53c7d064 1354 igb_configure(adapter);
9d5c8243 1355 }
844290e5 1356
c74d588e
AD		 1357 igb_assign_vector(adapter->q_vector[0], 0);
1358
7dfc16fa 1359 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1360 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1361 netdev->name, adapter);
9d5c8243
AK		 1362 if (!err)
1363 goto request_done;
047e0030 1364
9d5c8243
AK		 1365 /* fall back to legacy interrupts */
1366 igb_reset_interrupt_capability(adapter);
7dfc16fa 1367 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1368 }
1369
c74d588e 1370 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1371 netdev->name, adapter);
9d5c8243 1372
6cb5e577 1373 if (err)
c74d588e 1374 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1375 err);
9d5c8243
AK		 1376
1377request_done:
1378 return err;
1379}
1380
1381static void igb_free_irq(struct igb_adapter *adapter)
1382{
9d5c8243
AK		 1383 if (adapter->msix_entries) {
1384 int vector = 0, i;
1385
047e0030 1386 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1387
0d1ae7f4 1388 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1389 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1390 adapter->q_vector[i]);
047e0030
AD		 1391 } else {
1392 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1393 }
9d5c8243
AK		 1394}
1395
1396/**
1397 * igb_irq_disable - Mask off interrupt generation on the NIC
1398 * @adapter: board private structure
1399 **/
1400static void igb_irq_disable(struct igb_adapter *adapter)
1401{
1402 struct e1000_hw *hw = &adapter->hw;
1403
25568a53
AD		 1404 /*
1405 * we need to be careful when disabling interrupts. The VFs are also
1406 * mapped into these registers and so clearing the bits can cause
1407 * issues on the VF drivers so we only need to clear what we set
1408 */
9d5c8243 1409 if (adapter->msix_entries) {
2dfd1212
AD		 1410 u32 regval = rd32(E1000_EIAM);
1411 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1412 wr32(E1000_EIMC, adapter->eims_enable_mask);
1413 regval = rd32(E1000_EIAC);
1414 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1415 }
844290e5
PW		 1416
1417 wr32(E1000_IAM, 0);
9d5c8243
AK		 1418 wr32(E1000_IMC, ~0);
1419 wrfl();
81a61859
ET		 1420 if (adapter->msix_entries) {
1421 int i;
1422 for (i = 0; i < adapter->num_q_vectors; i++)
1423 synchronize_irq(adapter->msix_entries[i].vector);
1424 } else {
1425 synchronize_irq(adapter->pdev->irq);
1426 }
9d5c8243
AK		 1427}
1428
1429/**
1430 * igb_irq_enable - Enable default interrupt generation settings
1431 * @adapter: board private structure
1432 **/
1433static void igb_irq_enable(struct igb_adapter *adapter)
1434{
1435 struct e1000_hw *hw = &adapter->hw;
1436
1437 if (adapter->msix_entries) {
06218a8d 1438 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1439 u32 regval = rd32(E1000_EIAC);
1440 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1441 regval = rd32(E1000_EIAM);
1442 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1443 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1444 if (adapter->vfs_allocated_count) {
4ae196df 1445 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1446 ims |= E1000_IMS_VMMB;
1447 }
1448 wr32(E1000_IMS, ims);
844290e5 1449 } else {
55cac248
AD		 1450 wr32(E1000_IMS, IMS_ENABLE_MASK |
1451 E1000_IMS_DRSTA);
1452 wr32(E1000_IAM, IMS_ENABLE_MASK |
1453 E1000_IMS_DRSTA);
844290e5 1454 }
9d5c8243
AK		 1455}
1456
1457static void igb_update_mng_vlan(struct igb_adapter *adapter)
1458{
51466239 1459 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1460 u16 vid = adapter->hw.mng_cookie.vlan_id;
1461 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1462
1463 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1464 /* add VID to filter table */
1465 igb_vfta_set(hw, vid, true);
1466 adapter->mng_vlan_id = vid;
1467 } else {
1468 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1469 }
1470
1471 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1472 (vid != old_vid) &&
b2cb09b1 1473 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1474 /* remove VID from filter table */
1475 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1476 }
1477}
1478
1479/**
1480 * igb_release_hw_control - release control of the h/w to f/w
1481 * @adapter: address of board private structure
1482 *
1483 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1484 * For ASF and Pass Through versions of f/w this means that the
1485 * driver is no longer loaded.
1486 *
1487 **/
1488static void igb_release_hw_control(struct igb_adapter *adapter)
1489{
1490 struct e1000_hw *hw = &adapter->hw;
1491 u32 ctrl_ext;
1492
1493 /* Let firmware take over control of h/w */
1494 ctrl_ext = rd32(E1000_CTRL_EXT);
1495 wr32(E1000_CTRL_EXT,
1496 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1497}
1498
9d5c8243
AK		 1499/**
1500 * igb_get_hw_control - get control of the h/w from f/w
1501 * @adapter: address of board private structure
1502 *
1503 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1504 * For ASF and Pass Through versions of f/w this means that
1505 * the driver is loaded.
1506 *
1507 **/
1508static void igb_get_hw_control(struct igb_adapter *adapter)
1509{
1510 struct e1000_hw *hw = &adapter->hw;
1511 u32 ctrl_ext;
1512
1513 /* Let firmware know the driver has taken over */
1514 ctrl_ext = rd32(E1000_CTRL_EXT);
1515 wr32(E1000_CTRL_EXT,
1516 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1517}
1518
9d5c8243
AK		 1519/**
1520 * igb_configure - configure the hardware for RX and TX
1521 * @adapter: private board structure
1522 **/
1523static void igb_configure(struct igb_adapter *adapter)
1524{
1525 struct net_device *netdev = adapter->netdev;
1526 int i;
1527
1528 igb_get_hw_control(adapter);
ff41f8dc 1529 igb_set_rx_mode(netdev);
9d5c8243
AK		 1530
1531 igb_restore_vlan(adapter);
9d5c8243 1532
85b430b4 1533 igb_setup_tctl(adapter);
06cf2666 1534 igb_setup_mrqc(adapter);
9d5c8243 1535 igb_setup_rctl(adapter);
85b430b4
AD		 1536
1537 igb_configure_tx(adapter);
9d5c8243 1538 igb_configure_rx(adapter);
662d7205
AD		 1539
1540 igb_rx_fifo_flush_82575(&adapter->hw);
1541
c493ea45 1542 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1543 * at least 1 descriptor unused to make sure
1544 * next_to_use != next_to_clean */
1545 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1546 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1547 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1548 }
9d5c8243
AK		 1549}
1550
88a268c1
NN		 1551/**
1552 * igb_power_up_link - Power up the phy/serdes link
1553 * @adapter: address of board private structure
1554 **/
1555void igb_power_up_link(struct igb_adapter *adapter)
1556{
76886596
AA		 1557 igb_reset_phy(&adapter->hw);
1558
88a268c1
NN		 1559 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1560 igb_power_up_phy_copper(&adapter->hw);
1561 else
1562 igb_power_up_serdes_link_82575(&adapter->hw);
1563}
1564
1565/**
1566 * igb_power_down_link - Power down the phy/serdes link
1567 * @adapter: address of board private structure
1568 */
1569static void igb_power_down_link(struct igb_adapter *adapter)
1570{
1571 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1572 igb_power_down_phy_copper_82575(&adapter->hw);
1573 else
1574 igb_shutdown_serdes_link_82575(&adapter->hw);
1575}
9d5c8243
AK		 1576
1577/**
1578 * igb_up - Open the interface and prepare it to handle traffic
1579 * @adapter: board private structure
1580 **/
9d5c8243
AK		 1581int igb_up(struct igb_adapter *adapter)
1582{
1583 struct e1000_hw *hw = &adapter->hw;
1584 int i;
1585
1586 /* hardware has been reset, we need to reload some things */
1587 igb_configure(adapter);
1588
1589 clear_bit(__IGB_DOWN, &adapter->state);
1590
0d1ae7f4
AD		 1591 for (i = 0; i < adapter->num_q_vectors; i++)
1592 napi_enable(&(adapter->q_vector[i]->napi));
1593
844290e5 1594 if (adapter->msix_entries)
9d5c8243 1595 igb_configure_msix(adapter);
feeb2721
AD		 1596 else
1597 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1598
1599 /* Clear any pending interrupts. */
1600 rd32(E1000_ICR);
1601 igb_irq_enable(adapter);
1602
d4960307
AD		 1603 /* notify VFs that reset has been completed */
1604 if (adapter->vfs_allocated_count) {
1605 u32 reg_data = rd32(E1000_CTRL_EXT);
1606 reg_data |= E1000_CTRL_EXT_PFRSTD;
1607 wr32(E1000_CTRL_EXT, reg_data);
1608 }
1609
4cb9be7a
JB		 1610 netif_tx_start_all_queues(adapter->netdev);
1611
25568a53
AD		 1612 /* start the watchdog. */
1613 hw->mac.get_link_status = 1;
1614 schedule_work(&adapter->watchdog_task);
1615
9d5c8243
AK		 1616 return 0;
1617}
1618
1619void igb_down(struct igb_adapter *adapter)
1620{
9d5c8243 1621 struct net_device *netdev = adapter->netdev;
330a6d6a 1622 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1623 u32 tctl, rctl;
1624 int i;
1625
1626 /* signal that we're down so the interrupt handler does not
1627 * reschedule our watchdog timer */
1628 set_bit(__IGB_DOWN, &adapter->state);
1629
1630 /* disable receives in the hardware */
1631 rctl = rd32(E1000_RCTL);
1632 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1633 /* flush and sleep below */
1634
fd2ea0a7 1635 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1636
1637 /* disable transmits in the hardware */
1638 tctl = rd32(E1000_TCTL);
1639 tctl &= ~E1000_TCTL_EN;
1640 wr32(E1000_TCTL, tctl);
1641 /* flush both disables and wait for them to finish */
1642 wrfl();
1643 msleep(10);
1644
0d1ae7f4
AD		 1645 for (i = 0; i < adapter->num_q_vectors; i++)
1646 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1647
9d5c8243
AK		 1648 igb_irq_disable(adapter);
1649
1650 del_timer_sync(&adapter->watchdog_timer);
1651 del_timer_sync(&adapter->phy_info_timer);
1652
9d5c8243 1653 netif_carrier_off(netdev);
04fe6358
AD		 1654
1655 /* record the stats before reset*/
12dcd86b
ED		 1656 spin_lock(&adapter->stats64_lock);
1657 igb_update_stats(adapter, &adapter->stats64);
1658 spin_unlock(&adapter->stats64_lock);
04fe6358 1659
9d5c8243
AK		 1660 adapter->link_speed = 0;
1661 adapter->link_duplex = 0;
1662
3023682e
JK		 1663 if (!pci_channel_offline(adapter->pdev))
1664 igb_reset(adapter);
9d5c8243
AK		 1665 igb_clean_all_tx_rings(adapter);
1666 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1667#ifdef CONFIG_IGB_DCA
1668
1669 /* since we reset the hardware DCA settings were cleared */
1670 igb_setup_dca(adapter);
1671#endif
9d5c8243
AK		 1672}
1673
1674void igb_reinit_locked(struct igb_adapter *adapter)
1675{
1676 WARN_ON(in_interrupt());
1677 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1678 msleep(1);
1679 igb_down(adapter);
1680 igb_up(adapter);
1681 clear_bit(__IGB_RESETTING, &adapter->state);
1682}
1683
1684void igb_reset(struct igb_adapter *adapter)
1685{
090b1795 1686 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1687 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1688 struct e1000_mac_info *mac = &hw->mac;
1689 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1690 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1691
1692 /* Repartition Pba for greater than 9k mtu
1693 * To take effect CTRL.RST is required.
1694 */
fa4dfae0 1695 switch (mac->type) {
d2ba2ed8 1696 case e1000_i350:
55cac248
AD		 1697 case e1000_82580:
1698 pba = rd32(E1000_RXPBS);
1699 pba = igb_rxpbs_adjust_82580(pba);
1700 break;
fa4dfae0 1701 case e1000_82576:
d249be54
AD		 1702 pba = rd32(E1000_RXPBS);
1703 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1704 break;
1705 case e1000_82575:
f96a8a0b
CW		 1706 case e1000_i210:
1707 case e1000_i211:
fa4dfae0
AD		 1708 default:
1709 pba = E1000_PBA_34K;
1710 break;
2d064c06 1711 }
9d5c8243 1712
2d064c06
AD		 1713 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1714 (mac->type < e1000_82576)) {
9d5c8243
AK		 1715 /* adjust PBA for jumbo frames */
1716 wr32(E1000_PBA, pba);
1717
1718 /* To maintain wire speed transmits, the Tx FIFO should be
1719 * large enough to accommodate two full transmit packets,
1720 * rounded up to the next 1KB and expressed in KB. Likewise,
1721 * the Rx FIFO should be large enough to accommodate at least
1722 * one full receive packet and is similarly rounded up and
1723 * expressed in KB. */
1724 pba = rd32(E1000_PBA);
1725 /* upper 16 bits has Tx packet buffer allocation size in KB */
1726 tx_space = pba >> 16;
1727 /* lower 16 bits has Rx packet buffer allocation size in KB */
1728 pba &= 0xffff;
1729 /* the tx fifo also stores 16 bytes of information about the tx
1730 * but don't include ethernet FCS because hardware appends it */
1731 min_tx_space = (adapter->max_frame_size +
85e8d004 1732 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1733 ETH_FCS_LEN) * 2;
1734 min_tx_space = ALIGN(min_tx_space, 1024);
1735 min_tx_space >>= 10;
1736 /* software strips receive CRC, so leave room for it */
1737 min_rx_space = adapter->max_frame_size;
1738 min_rx_space = ALIGN(min_rx_space, 1024);
1739 min_rx_space >>= 10;
1740
1741 /* If current Tx allocation is less than the min Tx FIFO size,
1742 * and the min Tx FIFO size is less than the current Rx FIFO
1743 * allocation, take space away from current Rx allocation */
1744 if (tx_space < min_tx_space &&
1745 ((min_tx_space - tx_space) < pba)) {
1746 pba = pba - (min_tx_space - tx_space);
1747
1748 /* if short on rx space, rx wins and must trump tx
1749 * adjustment */
1750 if (pba < min_rx_space)
1751 pba = min_rx_space;
1752 }
2d064c06 1753 wr32(E1000_PBA, pba);
9d5c8243 1754 }
9d5c8243
AK		 1755
1756 /* flow control settings */
1757 /* The high water mark must be low enough to fit one full frame
1758 * (or the size used for early receive) above it in the Rx FIFO.
1759 * Set it to the lower of:
1760 * - 90% of the Rx FIFO size, or
1761 * - the full Rx FIFO size minus one full frame */
1762 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1763 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1764
d48507fe 1765 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1766 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1767 fc->pause_time = 0xFFFF;
1768 fc->send_xon = 1;
0cce119a 1769 fc->current_mode = fc->requested_mode;
9d5c8243 1770
4ae196df
AD		 1771 /* disable receive for all VFs and wait one second */
1772 if (adapter->vfs_allocated_count) {
1773 int i;
1774 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1775 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1776
1777 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1778 igb_ping_all_vfs(adapter);
4ae196df
AD		 1779
1780 /* disable transmits and receives */
1781 wr32(E1000_VFRE, 0);
1782 wr32(E1000_VFTE, 0);
1783 }
1784
9d5c8243 1785 /* Allow time for pending master requests to run */
330a6d6a 1786 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1787 wr32(E1000_WUC, 0);
1788
330a6d6a 1789 if (hw->mac.ops.init_hw(hw))
090b1795 1790 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1791
a27416bb
MV		 1792 /*
1793 * Flow control settings reset on hardware reset, so guarantee flow
1794 * control is off when forcing speed.
1795 */
1796 if (!hw->mac.autoneg)
1797 igb_force_mac_fc(hw);
1798
b6e0c419 1799 igb_init_dmac(adapter, pba);
e428893b
CW		 1800#ifdef CONFIG_IGB_HWMON
1801 /* Re-initialize the thermal sensor on i350 devices. */
1802 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1803 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1804 /* If present, re-initialize the external thermal sensor
1805 * interface.
1806 */
1807 if (adapter->ets)
1808 mac->ops.init_thermal_sensor_thresh(hw);
1809 }
1810 }
1811#endif
88a268c1
NN		 1812 if (!netif_running(adapter->netdev))
1813 igb_power_down_link(adapter);
1814
9d5c8243
AK		 1815 igb_update_mng_vlan(adapter);
1816
1817 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1818 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1819
1f6e8178
MV		 1820 /* Re-enable PTP, where applicable. */
1821 igb_ptp_reset(adapter);
1f6e8178 1822
330a6d6a 1823 igb_get_phy_info(hw);
9d5c8243
AK		 1824}
1825
c8f44aff
MM		 1826static netdev_features_t igb_fix_features(struct net_device *netdev,
1827 netdev_features_t features)
b2cb09b1
JP		 1828{
1829 /*
1830 * Since there is no support for separate rx/tx vlan accel
1831 * enable/disable make sure tx flag is always in same state as rx.
1832 */
1833 if (features & NETIF_F_HW_VLAN_RX)
1834 features |= NETIF_F_HW_VLAN_TX;
1835 else
1836 features &= ~NETIF_F_HW_VLAN_TX;
1837
1838 return features;
1839}
1840
c8f44aff
MM		 1841static int igb_set_features(struct net_device *netdev,
1842 netdev_features_t features)
ac52caa3 1843{
c8f44aff 1844 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1845 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1846
b2cb09b1
JP		 1847 if (changed & NETIF_F_HW_VLAN_RX)
1848 igb_vlan_mode(netdev, features);
1849
89eaefb6
BG		 1850 if (!(changed & NETIF_F_RXALL))
1851 return 0;
1852
1853 netdev->features = features;
1854
1855 if (netif_running(netdev))
1856 igb_reinit_locked(adapter);
1857 else
1858 igb_reset(adapter);
1859
ac52caa3
MM		 1860 return 0;
1861}
1862
2e5c6922 1863static const struct net_device_ops igb_netdev_ops = {
559e9c49 1864 .ndo_open = igb_open,
2e5c6922 1865 .ndo_stop = igb_close,
cd392f5c 1866 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1867 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1868 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1869 .ndo_set_mac_address = igb_set_mac,
1870 .ndo_change_mtu = igb_change_mtu,
1871 .ndo_do_ioctl = igb_ioctl,
1872 .ndo_tx_timeout = igb_tx_timeout,
1873 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1874 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1875 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1876 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1877 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1878 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1879 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1880#ifdef CONFIG_NET_POLL_CONTROLLER
1881 .ndo_poll_controller = igb_netpoll,
1882#endif
b2cb09b1
JP		 1883 .ndo_fix_features = igb_fix_features,
1884 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1885};
1886
d67974f0
CW		 1887/**
1888 * igb_set_fw_version - Configure version string for ethtool
1889 * @adapter: adapter struct
1890 *
1891 **/
1892void igb_set_fw_version(struct igb_adapter *adapter)
1893{
1894 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1895 struct e1000_fw_version fw;
1896
1897 igb_get_fw_version(hw, &fw);
1898
1899 switch (hw->mac.type) {
1900 case e1000_i211:
d67974f0 1901 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1902 "%2d.%2d-%d",
1903 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1904 break;
1905
1906 default:
1907 /* if option is rom valid, display its version too */
1908 if (fw.or_valid) {
1909 snprintf(adapter->fw_version,
1910 sizeof(adapter->fw_version),
1911 "%d.%d, 0x%08x, %d.%d.%d",
1912 fw.eep_major, fw.eep_minor, fw.etrack_id,
1913 fw.or_major, fw.or_build, fw.or_patch);
1914 /* no option rom */
1915 } else {
1916 snprintf(adapter->fw_version,
1917 sizeof(adapter->fw_version),
1918 "%d.%d, 0x%08x",
1919 fw.eep_major, fw.eep_minor, fw.etrack_id);
1920 }
1921 break;
d67974f0 1922 }
d67974f0
CW		 1923 return;
1924}
1925
441fc6fd
CW		 1926static const struct i2c_board_info i350_sensor_info = {
1927 I2C_BOARD_INFO("i350bb", 0Xf8),
1928};
1929
1930/* igb_init_i2c - Init I2C interface
1931 * @adapter: pointer to adapter structure
1932 *
1933 */
1934static s32 igb_init_i2c(struct igb_adapter *adapter)
1935{
1936 s32 status = E1000_SUCCESS;
1937
1938 /* I2C interface supported on i350 devices */
1939 if (adapter->hw.mac.type != e1000_i350)
1940 return E1000_SUCCESS;
1941
1942 /* Initialize the i2c bus which is controlled by the registers.
1943 * This bus will use the i2c_algo_bit structue that implements
1944 * the protocol through toggling of the 4 bits in the register.
1945 */
1946 adapter->i2c_adap.owner = THIS_MODULE;
1947 adapter->i2c_algo = igb_i2c_algo;
1948 adapter->i2c_algo.data = adapter;
1949 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1950 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1951 strlcpy(adapter->i2c_adap.name, "igb BB",
1952 sizeof(adapter->i2c_adap.name));
1953 status = i2c_bit_add_bus(&adapter->i2c_adap);
1954 return status;
1955}
1956
9d5c8243
AK		 1957/**
1958 * igb_probe - Device Initialization Routine
1959 * @pdev: PCI device information struct
1960 * @ent: entry in igb_pci_tbl
1961 *
1962 * Returns 0 on success, negative on failure
1963 *
1964 * igb_probe initializes an adapter identified by a pci_dev structure.
1965 * The OS initialization, configuring of the adapter private structure,
1966 * and a hardware reset occur.
1967 **/
1dd06ae8 1968static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1969{
1970 struct net_device *netdev;
1971 struct igb_adapter *adapter;
1972 struct e1000_hw *hw;
4337e993 1973 u16 eeprom_data = 0;
9835fd73 1974 s32 ret_val;
4337e993 1975 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1976 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1977 unsigned long mmio_start, mmio_len;
2d6a5e95 1978 int err, pci_using_dac;
9835fd73 1979 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1980
bded64a7
AG		 1981 /* Catch broken hardware that put the wrong VF device ID in
1982 * the PCIe SR-IOV capability.
1983 */
1984 if (pdev->is_virtfn) {
1985 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1986 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1987 return -EINVAL;
1988 }
1989
aed5dec3 1990 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1991 if (err)
1992 return err;
1993
1994 pci_using_dac = 0;
59d71989 1995 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1996 if (!err) {
59d71989 1997 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1998 if (!err)
1999 pci_using_dac = 1;
2000 } else {
59d71989 2001 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2002 if (err) {
59d71989 2003 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 2004 if (err) {
2005 dev_err(&pdev->dev, "No usable DMA "
2006 "configuration, aborting\n");
2007 goto err_dma;
2008 }
2009 }
2010 }
2011
aed5dec3
AD		 2012 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2013 IORESOURCE_MEM),
2014 igb_driver_name);
9d5c8243
AK		 2015 if (err)
2016 goto err_pci_reg;
2017
19d5afd4 2018 pci_enable_pcie_error_reporting(pdev);
40a914fa 2019
9d5c8243 2020 pci_set_master(pdev);
c682fc23 2021 pci_save_state(pdev);
9d5c8243
AK		 2022
2023 err = -ENOMEM;
1bfaf07b 2024 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2025 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2026 if (!netdev)
2027 goto err_alloc_etherdev;
2028
2029 SET_NETDEV_DEV(netdev, &pdev->dev);
2030
2031 pci_set_drvdata(pdev, netdev);
2032 adapter = netdev_priv(netdev);
2033 adapter->netdev = netdev;
2034 adapter->pdev = pdev;
2035 hw = &adapter->hw;
2036 hw->back = adapter;
b3f4d599 2037 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2038
2039 mmio_start = pci_resource_start(pdev, 0);
2040 mmio_len = pci_resource_len(pdev, 0);
2041
2042 err = -EIO;
28b0759c
AD		 2043 hw->hw_addr = ioremap(mmio_start, mmio_len);
2044 if (!hw->hw_addr)
9d5c8243
AK		 2045 goto err_ioremap;
2046
2e5c6922 2047 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2048 igb_set_ethtool_ops(netdev);
9d5c8243 2049 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2050
2051 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2052
2053 netdev->mem_start = mmio_start;
2054 netdev->mem_end = mmio_start + mmio_len;
2055
9d5c8243
AK		 2056 /* PCI config space info */
2057 hw->vendor_id = pdev->vendor;
2058 hw->device_id = pdev->device;
2059 hw->revision_id = pdev->revision;
2060 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2061 hw->subsystem_device_id = pdev->subsystem_device;
2062
9d5c8243
AK		 2063 /* Copy the default MAC, PHY and NVM function pointers */
2064 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2065 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2066 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2067 /* Initialize skew-specific constants */
2068 err = ei->get_invariants(hw);
2069 if (err)
450c87c8 2070 goto err_sw_init;
9d5c8243 2071
450c87c8 2072 /* setup the private structure */
9d5c8243
AK		 2073 err = igb_sw_init(adapter);
2074 if (err)
2075 goto err_sw_init;
2076
2077 igb_get_bus_info_pcie(hw);
2078
2079 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2080
2081 /* Copper options */
2082 if (hw->phy.media_type == e1000_media_type_copper) {
2083 hw->phy.mdix = AUTO_ALL_MODES;
2084 hw->phy.disable_polarity_correction = false;
2085 hw->phy.ms_type = e1000_ms_hw_default;
2086 }
2087
2088 if (igb_check_reset_block(hw))
2089 dev_info(&pdev->dev,
2090 "PHY reset is blocked due to SOL/IDER session.\n");
2091
077887c3
AD		 2092 /*
2093 * features is initialized to 0 in allocation, it might have bits
2094 * set by igb_sw_init so we should use an or instead of an
2095 * assignment.
2096 */
2097 netdev->features |= NETIF_F_SG |
2098 NETIF_F_IP_CSUM |
2099 NETIF_F_IPV6_CSUM |
2100 NETIF_F_TSO |
2101 NETIF_F_TSO6 |
2102 NETIF_F_RXHASH |
2103 NETIF_F_RXCSUM |
2104 NETIF_F_HW_VLAN_RX |
2105 NETIF_F_HW_VLAN_TX;
2106
2107 /* copy netdev features into list of user selectable features */
2108 netdev->hw_features |= netdev->features;
89eaefb6 2109 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2110
2111 /* set this bit last since it cannot be part of hw_features */
2112 netdev->features |= NETIF_F_HW_VLAN_FILTER;
2113
2114 netdev->vlan_features |= NETIF_F_TSO |
2115 NETIF_F_TSO6 |
2116 NETIF_F_IP_CSUM |
2117 NETIF_F_IPV6_CSUM |
2118 NETIF_F_SG;
48f29ffc 2119
6b8f0922
BG		 2120 netdev->priv_flags |= IFF_SUPP_NOFCS;
2121
7b872a55 2122 if (pci_using_dac) {
9d5c8243 2123 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2124 netdev->vlan_features |= NETIF_F_HIGHDMA;
2125 }
9d5c8243 2126
ac52caa3
MM		 2127 if (hw->mac.type >= e1000_82576) {
2128 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2129 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2130 }
b9473560 2131
01789349
JP		 2132 netdev->priv_flags |= IFF_UNICAST_FLT;
2133
330a6d6a 2134 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2135
2136 /* before reading the NVM, reset the controller to put the device in a
2137 * known good starting state */
2138 hw->mac.ops.reset_hw(hw);
2139
f96a8a0b
CW		 2140 /*
2141 * make sure the NVM is good , i211 parts have special NVM that
2142 * doesn't contain a checksum
2143 */
2144 if (hw->mac.type != e1000_i211) {
2145 if (hw->nvm.ops.validate(hw) < 0) {
2146 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2147 err = -EIO;
2148 goto err_eeprom;
2149 }
9d5c8243
AK		 2150 }
2151
2152 /* copy the MAC address out of the NVM */
2153 if (hw->mac.ops.read_mac_addr(hw))
2154 dev_err(&pdev->dev, "NVM Read Error\n");
2155
2156 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2157
aaeb6cdf 2158 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2159 dev_err(&pdev->dev, "Invalid MAC Address\n");
2160 err = -EIO;
2161 goto err_eeprom;
2162 }
2163
d67974f0
CW		 2164 /* get firmware version for ethtool -i */
2165 igb_set_fw_version(adapter);
2166
c061b18d 2167 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2168 (unsigned long) adapter);
c061b18d 2169 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2170 (unsigned long) adapter);
9d5c8243
AK		 2171
2172 INIT_WORK(&adapter->reset_task, igb_reset_task);
2173 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2174
450c87c8 2175 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2176 adapter->fc_autoneg = true;
2177 hw->mac.autoneg = true;
2178 hw->phy.autoneg_advertised = 0x2f;
2179
0cce119a
AD		 2180 hw->fc.requested_mode = e1000_fc_default;
2181 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2182
9d5c8243
AK		 2183 igb_validate_mdi_setting(hw);
2184
63d4a8f9 2185 /* By default, support wake on port A */
a2cf8b6c 2186 if (hw->bus.func == 0)
63d4a8f9
MV		 2187 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2188
2189 /* Check the NVM for wake support on non-port A ports */
2190 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2191 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2192 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2193 &eeprom_data);
a2cf8b6c
AD		 2194 else if (hw->bus.func == 1)
2195 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2196
63d4a8f9
MV		 2197 if (eeprom_data & IGB_EEPROM_APME)
2198 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2199
2200 /* now that we have the eeprom settings, apply the special cases where
2201 * the eeprom may be wrong or the board simply won't support wake on
2202 * lan on a particular port */
2203 switch (pdev->device) {
2204 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2205 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2206 break;
2207 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2208 case E1000_DEV_ID_82576_FIBER:
2209 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2210 /* Wake events only supported on port A for dual fiber
2211 * regardless of eeprom setting */
2212 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2213 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2214 break;
c8ea5ea9 2215 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2216 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2217 /* if quad port adapter, disable WoL on all but port A */
2218 if (global_quad_port_a != 0)
63d4a8f9 2219 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2220 else
2221 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2222 /* Reset for multiple quad port adapters */
2223 if (++global_quad_port_a == 4)
2224 global_quad_port_a = 0;
2225 break;
63d4a8f9
MV		 2226 default:
2227 /* If the device can't wake, don't set software support */
2228 if (!device_can_wakeup(&adapter->pdev->dev))
2229 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2230 }
2231
2232 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2233 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2234 adapter->wol |= E1000_WUFC_MAG;
2235
2236 /* Some vendors want WoL disabled by default, but still supported */
2237 if ((hw->mac.type == e1000_i350) &&
2238 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2239 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2240 adapter->wol = 0;
2241 }
2242
2243 device_set_wakeup_enable(&adapter->pdev->dev,
2244 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2245
2246 /* reset the hardware with the new settings */
2247 igb_reset(adapter);
2248
441fc6fd
CW		 2249 /* Init the I2C interface */
2250 err = igb_init_i2c(adapter);
2251 if (err) {
2252 dev_err(&pdev->dev, "failed to init i2c interface\n");
2253 goto err_eeprom;
2254 }
2255
9d5c8243
AK		 2256 /* let the f/w know that the h/w is now under the control of the
2257 * driver. */
2258 igb_get_hw_control(adapter);
2259
9d5c8243
AK		 2260 strcpy(netdev->name, "eth%d");
2261 err = register_netdev(netdev);
2262 if (err)
2263 goto err_register;
2264
b168dfc5
JB		 2265 /* carrier off reporting is important to ethtool even BEFORE open */
2266 netif_carrier_off(netdev);
2267
421e02f0 2268#ifdef CONFIG_IGB_DCA
bbd98fe4 2269 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2270 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2271 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2272 igb_setup_dca(adapter);
2273 }
fe4506b6 2274
38c845c7 2275#endif
e428893b
CW		 2276#ifdef CONFIG_IGB_HWMON
2277 /* Initialize the thermal sensor on i350 devices. */
2278 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2279 u16 ets_word;
3c89f6d0 2280
e428893b
CW		 2281 /*
2282 * Read the NVM to determine if this i350 device supports an
2283 * external thermal sensor.
2284 */
2285 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2286 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2287 adapter->ets = true;
2288 else
2289 adapter->ets = false;
2290 if (igb_sysfs_init(adapter))
2291 dev_err(&pdev->dev,
2292 "failed to allocate sysfs resources\n");
2293 } else {
2294 adapter->ets = false;
2295 }
2296#endif
673b8b70 2297 /* do hw tstamp init after resetting */
7ebae817 2298 igb_ptp_init(adapter);
673b8b70 2299
9d5c8243
AK		 2300 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2301 /* print bus type/speed/width info */
7c510e4b 2302 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2303 netdev->name,
559e9c49 2304 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2305 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2306 "unknown"),
59c3de89
AD		 2307 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2308 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2309 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2310 "unknown"),
7c510e4b 2311 netdev->dev_addr);
9d5c8243 2312
9835fd73
CW		 2313 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2314 if (ret_val)
2315 strcpy(part_str, "Unknown");
2316 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2317 dev_info(&pdev->dev,
2318 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2319 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2320 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2321 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2322 switch (hw->mac.type) {
2323 case e1000_i350:
f96a8a0b
CW		 2324 case e1000_i210:
2325 case e1000_i211:
09b068d4
CW		 2326 igb_set_eee_i350(hw);
2327 break;
2328 default:
2329 break;
2330 }
749ab2cd
YZ		 2331
2332 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2333 return 0;
2334
2335err_register:
2336 igb_release_hw_control(adapter);
441fc6fd 2337 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2338err_eeprom:
2339 if (!igb_check_reset_block(hw))
f5f4cf08 2340 igb_reset_phy(hw);
9d5c8243
AK		 2341
2342 if (hw->flash_address)
2343 iounmap(hw->flash_address);
9d5c8243 2344err_sw_init:
047e0030 2345 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2346 iounmap(hw->hw_addr);
2347err_ioremap:
2348 free_netdev(netdev);
2349err_alloc_etherdev:
559e9c49
AD		 2350 pci_release_selected_regions(pdev,
2351 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2352err_pci_reg:
2353err_dma:
2354 pci_disable_device(pdev);
2355 return err;
2356}
2357
fa44f2f1
GR		 2358#ifdef CONFIG_PCI_IOV
2359static int igb_disable_sriov(struct pci_dev *pdev)
2360{
2361 struct net_device *netdev = pci_get_drvdata(pdev);
2362 struct igb_adapter *adapter = netdev_priv(netdev);
2363 struct e1000_hw *hw = &adapter->hw;
2364
2365 /* reclaim resources allocated to VFs */
2366 if (adapter->vf_data) {
2367 /* disable iov and allow time for transactions to clear */
2368 if (igb_vfs_are_assigned(adapter)) {
2369 dev_warn(&pdev->dev,
2370 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2371 return -EPERM;
2372 } else {
2373 pci_disable_sriov(pdev);
2374 msleep(500);
2375 }
2376
2377 kfree(adapter->vf_data);
2378 adapter->vf_data = NULL;
2379 adapter->vfs_allocated_count = 0;
2380 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2381 wrfl();
2382 msleep(100);
2383 dev_info(&pdev->dev, "IOV Disabled\n");
2384
2385 /* Re-enable DMA Coalescing flag since IOV is turned off */
2386 adapter->flags |= IGB_FLAG_DMAC;
2387 }
2388
2389 return 0;
2390}
2391
2392static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2393{
2394 struct net_device *netdev = pci_get_drvdata(pdev);
2395 struct igb_adapter *adapter = netdev_priv(netdev);
2396 int old_vfs = pci_num_vf(pdev);
2397 int err = 0;
2398 int i;
2399
2400 if (!num_vfs)
2401 goto out;
2402 else if (old_vfs && old_vfs == num_vfs)
2403 goto out;
2404 else if (old_vfs && old_vfs != num_vfs)
2405 err = igb_disable_sriov(pdev);
2406
2407 if (err)
2408 goto out;
2409
2410 if (num_vfs > 7) {
2411 err = -EPERM;
2412 goto out;
2413 }
2414
2415 adapter->vfs_allocated_count = num_vfs;
2416
2417 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2418 sizeof(struct vf_data_storage), GFP_KERNEL);
2419
2420 /* if allocation failed then we do not support SR-IOV */
2421 if (!adapter->vf_data) {
2422 adapter->vfs_allocated_count = 0;
2423 dev_err(&pdev->dev,
2424 "Unable to allocate memory for VF Data Storage\n");
2425 err = -ENOMEM;
2426 goto out;
2427 }
2428
2429 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2430 if (err)
2431 goto err_out;
2432
2433 dev_info(&pdev->dev, "%d VFs allocated\n",
2434 adapter->vfs_allocated_count);
2435 for (i = 0; i < adapter->vfs_allocated_count; i++)
2436 igb_vf_configure(adapter, i);
2437
2438 /* DMA Coalescing is not supported in IOV mode. */
2439 adapter->flags &= ~IGB_FLAG_DMAC;
2440 goto out;
2441
2442err_out:
2443 kfree(adapter->vf_data);
2444 adapter->vf_data = NULL;
2445 adapter->vfs_allocated_count = 0;
2446out:
2447 return err;
2448}
2449
2450#endif
441fc6fd
CW		 2451/*
2452 * igb_remove_i2c - Cleanup I2C interface
2453 * @adapter: pointer to adapter structure
2454 *
2455 */
2456static void igb_remove_i2c(struct igb_adapter *adapter)
2457{
2458
2459 /* free the adapter bus structure */
2460 i2c_del_adapter(&adapter->i2c_adap);
2461}
2462
9d5c8243
AK		 2463/**
2464 * igb_remove - Device Removal Routine
2465 * @pdev: PCI device information struct
2466 *
2467 * igb_remove is called by the PCI subsystem to alert the driver
2468 * that it should release a PCI device. The could be caused by a
2469 * Hot-Plug event, or because the driver is going to be removed from
2470 * memory.
2471 **/
9f9a12f8 2472static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2473{
2474 struct net_device *netdev = pci_get_drvdata(pdev);
2475 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2476 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2477
749ab2cd 2478 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2479#ifdef CONFIG_IGB_HWMON
2480 igb_sysfs_exit(adapter);
2481#endif
441fc6fd 2482 igb_remove_i2c(adapter);
a79f4f88 2483 igb_ptp_stop(adapter);
760141a5
TH		 2484 /*
2485 * The watchdog timer may be rescheduled, so explicitly
2486 * disable watchdog from being rescheduled.
2487 */
9d5c8243
AK		 2488 set_bit(__IGB_DOWN, &adapter->state);
2489 del_timer_sync(&adapter->watchdog_timer);
2490 del_timer_sync(&adapter->phy_info_timer);
2491
760141a5
TH		 2492 cancel_work_sync(&adapter->reset_task);
2493 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2494
421e02f0 2495#ifdef CONFIG_IGB_DCA
7dfc16fa 2496 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2497 dev_info(&pdev->dev, "DCA disabled\n");
2498 dca_remove_requester(&pdev->dev);
7dfc16fa 2499 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2500 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2501 }
2502#endif
2503
9d5c8243
AK		 2504 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2505 * would have already happened in close and is redundant. */
2506 igb_release_hw_control(adapter);
2507
2508 unregister_netdev(netdev);
2509
047e0030 2510 igb_clear_interrupt_scheme(adapter);
9d5c8243 2511
37680117 2512#ifdef CONFIG_PCI_IOV
fa44f2f1 2513 igb_disable_sriov(pdev);
37680117 2514#endif
559e9c49 2515
28b0759c
AD		 2516 iounmap(hw->hw_addr);
2517 if (hw->flash_address)
2518 iounmap(hw->flash_address);
559e9c49
AD		 2519 pci_release_selected_regions(pdev,
2520 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2521
1128c756 2522 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2523 free_netdev(netdev);
2524
19d5afd4 2525 pci_disable_pcie_error_reporting(pdev);
40a914fa 2526
9d5c8243
AK		 2527 pci_disable_device(pdev);
2528}
2529
a6b623e0
AD		 2530/**
2531 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2532 * @adapter: board private structure to initialize
2533 *
2534 * This function initializes the vf specific data storage and then attempts to
2535 * allocate the VFs. The reason for ordering it this way is because it is much
2536 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2537 * the memory for the VFs.
2538 **/
9f9a12f8 2539static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2540{
2541#ifdef CONFIG_PCI_IOV
2542 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2543 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2544
f96a8a0b
CW		 2545 /* Virtualization features not supported on i210 family. */
2546 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2547 return;
2548
fa44f2f1
GR		 2549 igb_enable_sriov(pdev, max_vfs);
2550 pci_sriov_set_totalvfs(pdev, 7);
0224d663 2551
a6b623e0
AD		 2552#endif /* CONFIG_PCI_IOV */
2553}
2554
fa44f2f1 2555static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2556{
2557 struct e1000_hw *hw = &adapter->hw;
374a542d 2558 u32 max_rss_queues;
9d5c8243 2559
374a542d 2560 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2561 switch (hw->mac.type) {
374a542d
MV		 2562 case e1000_i211:
2563 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2564 break;
2565 case e1000_82575:
f96a8a0b 2566 case e1000_i210:
374a542d
MV		 2567 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2568 break;
2569 case e1000_i350:
2570 /* I350 cannot do RSS and SR-IOV at the same time */
2571 if (!!adapter->vfs_allocated_count) {
2572 max_rss_queues = 1;
2573 break;
2574 }
2575 /* fall through */
2576 case e1000_82576:
2577 if (!!adapter->vfs_allocated_count) {
2578 max_rss_queues = 2;
2579 break;
2580 }
2581 /* fall through */
2582 case e1000_82580:
2583 default:
2584 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2585 break;
374a542d
MV		 2586 }
2587
2588 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2589
2590 /* Determine if we need to pair queues. */
2591 switch (hw->mac.type) {
2592 case e1000_82575:
f96a8a0b 2593 case e1000_i211:
374a542d 2594 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2595 break;
374a542d
MV		 2596 case e1000_82576:
2597 /*
2598 * If VFs are going to be allocated with RSS queues then we
2599 * should pair the queues in order to conserve interrupts due
2600 * to limited supply.
2601 */
2602 if ((adapter->rss_queues > 1) &&
2603 (adapter->vfs_allocated_count > 6))
2604 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2605 /* fall through */
2606 case e1000_82580:
2607 case e1000_i350:
2608 case e1000_i210:
f96a8a0b 2609 default:
374a542d
MV		 2610 /*
2611 * If rss_queues > half of max_rss_queues, pair the queues in
2612 * order to conserve interrupts due to limited supply.
2613 */
2614 if (adapter->rss_queues > (max_rss_queues / 2))
2615 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2616 break;
2617 }
fa44f2f1
GR		 2618}
2619
2620/**
2621 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2622 * @adapter: board private structure to initialize
2623 *
2624 * igb_sw_init initializes the Adapter private data structure.
2625 * Fields are initialized based on PCI device information and
2626 * OS network device settings (MTU size).
2627 **/
2628static int igb_sw_init(struct igb_adapter *adapter)
2629{
2630 struct e1000_hw *hw = &adapter->hw;
2631 struct net_device *netdev = adapter->netdev;
2632 struct pci_dev *pdev = adapter->pdev;
2633
2634 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2635
2636 /* set default ring sizes */
2637 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2638 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2639
2640 /* set default ITR values */
2641 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2642 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2643
2644 /* set default work limits */
2645 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2646
2647 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2648 VLAN_HLEN;
2649 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2650
2651 spin_lock_init(&adapter->stats64_lock);
2652#ifdef CONFIG_PCI_IOV
2653 switch (hw->mac.type) {
2654 case e1000_82576:
2655 case e1000_i350:
2656 if (max_vfs > 7) {
2657 dev_warn(&pdev->dev,
2658 "Maximum of 7 VFs per PF, using max\n");
2659 adapter->vfs_allocated_count = 7;
2660 } else
2661 adapter->vfs_allocated_count = max_vfs;
2662 if (adapter->vfs_allocated_count)
2663 dev_warn(&pdev->dev,
2664 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2665 break;
2666 default:
2667 break;
2668 }
2669#endif /* CONFIG_PCI_IOV */
2670
2671 igb_init_queue_configuration(adapter);
a99955fc 2672
1128c756
CW		 2673 /* Setup and initialize a copy of the hw vlan table array */
2674 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2675 E1000_VLAN_FILTER_TBL_SIZE,
2676 GFP_ATOMIC);
2677
a6b623e0 2678 /* This call may decrease the number of queues */
53c7d064 2679 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2680 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2681 return -ENOMEM;
2682 }
2683
a6b623e0
AD		 2684 igb_probe_vfs(adapter);
2685
9d5c8243
AK		 2686 /* Explicitly disable IRQ since the NIC can be in any state. */
2687 igb_irq_disable(adapter);
2688
f96a8a0b 2689 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2690 adapter->flags &= ~IGB_FLAG_DMAC;
2691
9d5c8243
AK		 2692 set_bit(__IGB_DOWN, &adapter->state);
2693 return 0;
2694}
2695
2696/**
2697 * igb_open - Called when a network interface is made active
2698 * @netdev: network interface device structure
2699 *
2700 * Returns 0 on success, negative value on failure
2701 *
2702 * The open entry point is called when a network interface is made
2703 * active by the system (IFF_UP). At this point all resources needed
2704 * for transmit and receive operations are allocated, the interrupt
2705 * handler is registered with the OS, the watchdog timer is started,
2706 * and the stack is notified that the interface is ready.
2707 **/
749ab2cd 2708static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2709{
2710 struct igb_adapter *adapter = netdev_priv(netdev);
2711 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2712 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2713 int err;
2714 int i;
2715
2716 /* disallow open during test */
749ab2cd
YZ		 2717 if (test_bit(__IGB_TESTING, &adapter->state)) {
2718 WARN_ON(resuming);
9d5c8243 2719 return -EBUSY;
749ab2cd
YZ		 2720 }
2721
2722 if (!resuming)
2723 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2724
b168dfc5
JB		 2725 netif_carrier_off(netdev);
2726
9d5c8243
AK		 2727 /* allocate transmit descriptors */
2728 err = igb_setup_all_tx_resources(adapter);
2729 if (err)
2730 goto err_setup_tx;
2731
2732 /* allocate receive descriptors */
2733 err = igb_setup_all_rx_resources(adapter);
2734 if (err)
2735 goto err_setup_rx;
2736
88a268c1 2737 igb_power_up_link(adapter);
9d5c8243 2738
9d5c8243
AK		 2739 /* before we allocate an interrupt, we must be ready to handle it.
2740 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2741 * as soon as we call pci_request_irq, so we have to setup our
2742 * clean_rx handler before we do so. */
2743 igb_configure(adapter);
2744
2745 err = igb_request_irq(adapter);
2746 if (err)
2747 goto err_req_irq;
2748
0c2cc02e
AD		 2749 /* Notify the stack of the actual queue counts. */
2750 err = netif_set_real_num_tx_queues(adapter->netdev,
2751 adapter->num_tx_queues);
2752 if (err)
2753 goto err_set_queues;
2754
2755 err = netif_set_real_num_rx_queues(adapter->netdev,
2756 adapter->num_rx_queues);
2757 if (err)
2758 goto err_set_queues;
2759
9d5c8243
AK		 2760 /* From here on the code is the same as igb_up() */
2761 clear_bit(__IGB_DOWN, &adapter->state);
2762
0d1ae7f4
AD		 2763 for (i = 0; i < adapter->num_q_vectors; i++)
2764 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2765
2766 /* Clear any pending interrupts. */
2767 rd32(E1000_ICR);
844290e5
PW		 2768
2769 igb_irq_enable(adapter);
2770
d4960307
AD		 2771 /* notify VFs that reset has been completed */
2772 if (adapter->vfs_allocated_count) {
2773 u32 reg_data = rd32(E1000_CTRL_EXT);
2774 reg_data |= E1000_CTRL_EXT_PFRSTD;
2775 wr32(E1000_CTRL_EXT, reg_data);
2776 }
2777
d55b53ff
JK		 2778 netif_tx_start_all_queues(netdev);
2779
749ab2cd
YZ		 2780 if (!resuming)
2781 pm_runtime_put(&pdev->dev);
2782
25568a53
AD		 2783 /* start the watchdog. */
2784 hw->mac.get_link_status = 1;
2785 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2786
2787 return 0;
2788
0c2cc02e
AD		 2789err_set_queues:
2790 igb_free_irq(adapter);
9d5c8243
AK		 2791err_req_irq:
2792 igb_release_hw_control(adapter);
88a268c1 2793 igb_power_down_link(adapter);
9d5c8243
AK		 2794 igb_free_all_rx_resources(adapter);
2795err_setup_rx:
2796 igb_free_all_tx_resources(adapter);
2797err_setup_tx:
2798 igb_reset(adapter);
749ab2cd
YZ		 2799 if (!resuming)
2800 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2801
2802 return err;
2803}
2804
749ab2cd
YZ		 2805static int igb_open(struct net_device *netdev)
2806{
2807 return __igb_open(netdev, false);
2808}
2809
9d5c8243
AK		 2810/**
2811 * igb_close - Disables a network interface
2812 * @netdev: network interface device structure
2813 *
2814 * Returns 0, this is not allowed to fail
2815 *
2816 * The close entry point is called when an interface is de-activated
2817 * by the OS. The hardware is still under the driver's control, but
2818 * needs to be disabled. A global MAC reset is issued to stop the
2819 * hardware, and all transmit and receive resources are freed.
2820 **/
749ab2cd 2821static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2822{
2823 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2824 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2825
2826 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2827
749ab2cd
YZ		 2828 if (!suspending)
2829 pm_runtime_get_sync(&pdev->dev);
2830
2831 igb_down(adapter);
9d5c8243
AK		 2832 igb_free_irq(adapter);
2833
2834 igb_free_all_tx_resources(adapter);
2835 igb_free_all_rx_resources(adapter);
2836
749ab2cd
YZ		 2837 if (!suspending)
2838 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2839 return 0;
2840}
2841
749ab2cd
YZ		 2842static int igb_close(struct net_device *netdev)
2843{
2844 return __igb_close(netdev, false);
2845}
2846
9d5c8243
AK		 2847/**
2848 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2849 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2850 *
2851 * Return 0 on success, negative on failure
2852 **/
80785298 2853int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2854{
59d71989 2855 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2856 int size;
2857
06034649 2858 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2859
2860 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2861 if (!tx_ring->tx_buffer_info)
9d5c8243 2862 goto err;
9d5c8243
AK		 2863
2864 /* round up to nearest 4K */
85e8d004 2865 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2866 tx_ring->size = ALIGN(tx_ring->size, 4096);
2867
5536d210
AD		 2868 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2869 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2870 if (!tx_ring->desc)
2871 goto err;
2872
9d5c8243
AK		 2873 tx_ring->next_to_use = 0;
2874 tx_ring->next_to_clean = 0;
81c2fc22 2875
9d5c8243
AK		 2876 return 0;
2877
2878err:
06034649 2879 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2880 tx_ring->tx_buffer_info = NULL;
2881 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2882 return -ENOMEM;
2883}
2884
2885/**
2886 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2887 * (Descriptors) for all queues
2888 * @adapter: board private structure
2889 *
2890 * Return 0 on success, negative on failure
2891 **/
2892static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2893{
439705e1 2894 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2895 int i, err = 0;
2896
2897 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2898 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2899 if (err) {
439705e1 2900 dev_err(&pdev->dev,
9d5c8243
AK		 2901 "Allocation for Tx Queue %u failed\n", i);
2902 for (i--; i >= 0; i--)
3025a446 2903 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2904 break;
2905 }
2906 }
2907
2908 return err;
2909}
2910
2911/**
85b430b4
AD		 2912 * igb_setup_tctl - configure the transmit control registers
2913 * @adapter: Board private structure
9d5c8243 2914 **/
d7ee5b3a 2915void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2916{
9d5c8243
AK		 2917 struct e1000_hw *hw = &adapter->hw;
2918 u32 tctl;
9d5c8243 2919
85b430b4
AD		 2920 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2921 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2922
2923 /* Program the Transmit Control Register */
9d5c8243
AK		 2924 tctl = rd32(E1000_TCTL);
2925 tctl &= ~E1000_TCTL_CT;
2926 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2927 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2928
2929 igb_config_collision_dist(hw);
2930
9d5c8243
AK		 2931 /* Enable transmits */
2932 tctl |= E1000_TCTL_EN;
2933
2934 wr32(E1000_TCTL, tctl);
2935}
2936
85b430b4
AD		 2937/**
2938 * igb_configure_tx_ring - Configure transmit ring after Reset
2939 * @adapter: board private structure
2940 * @ring: tx ring to configure
2941 *
2942 * Configure a transmit ring after a reset.
2943 **/
d7ee5b3a
AD		 2944void igb_configure_tx_ring(struct igb_adapter *adapter,
2945 struct igb_ring *ring)
85b430b4
AD		 2946{
2947 struct e1000_hw *hw = &adapter->hw;
a74420e0 2948 u32 txdctl = 0;
85b430b4
AD		 2949 u64 tdba = ring->dma;
2950 int reg_idx = ring->reg_idx;
2951
2952 /* disable the queue */
a74420e0 2953 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2954 wrfl();
2955 mdelay(10);
2956
2957 wr32(E1000_TDLEN(reg_idx),
2958 ring->count * sizeof(union e1000_adv_tx_desc));
2959 wr32(E1000_TDBAL(reg_idx),
2960 tdba & 0x00000000ffffffffULL);
2961 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2962
fce99e34 2963 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2964 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2965 writel(0, ring->tail);
85b430b4
AD		 2966
2967 txdctl |= IGB_TX_PTHRESH;
2968 txdctl |= IGB_TX_HTHRESH << 8;
2969 txdctl |= IGB_TX_WTHRESH << 16;
2970
2971 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2972 wr32(E1000_TXDCTL(reg_idx), txdctl);
2973}
2974
2975/**
2976 * igb_configure_tx - Configure transmit Unit after Reset
2977 * @adapter: board private structure
2978 *
2979 * Configure the Tx unit of the MAC after a reset.
2980 **/
2981static void igb_configure_tx(struct igb_adapter *adapter)
2982{
2983 int i;
2984
2985 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2986 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2987}
2988
9d5c8243
AK		 2989/**
2990 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2991 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2992 *
2993 * Returns 0 on success, negative on failure
2994 **/
80785298 2995int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2996{
59d71989 2997 struct device *dev = rx_ring->dev;
f33005a6 2998 int size;
9d5c8243 2999
06034649 3000 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3001
3002 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3003 if (!rx_ring->rx_buffer_info)
9d5c8243 3004 goto err;
9d5c8243 3005
9d5c8243 3006 /* Round up to nearest 4K */
f33005a6 3007 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3008 rx_ring->size = ALIGN(rx_ring->size, 4096);
3009
5536d210
AD		 3010 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3011 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3012 if (!rx_ring->desc)
3013 goto err;
3014
cbc8e55f 3015 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3016 rx_ring->next_to_clean = 0;
3017 rx_ring->next_to_use = 0;
9d5c8243 3018
9d5c8243
AK		 3019 return 0;
3020
3021err:
06034649
AD		 3022 vfree(rx_ring->rx_buffer_info);
3023 rx_ring->rx_buffer_info = NULL;
f33005a6 3024 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3025 return -ENOMEM;
3026}
3027
3028/**
3029 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3030 * (Descriptors) for all queues
3031 * @adapter: board private structure
3032 *
3033 * Return 0 on success, negative on failure
3034 **/
3035static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3036{
439705e1 3037 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3038 int i, err = 0;
3039
3040 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3041 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3042 if (err) {
439705e1 3043 dev_err(&pdev->dev,
9d5c8243
AK		 3044 "Allocation for Rx Queue %u failed\n", i);
3045 for (i--; i >= 0; i--)
3025a446 3046 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3047 break;
3048 }
3049 }
3050
3051 return err;
3052}
3053
06cf2666
AD		 3054/**
3055 * igb_setup_mrqc - configure the multiple receive queue control registers
3056 * @adapter: Board private structure
3057 **/
3058static void igb_setup_mrqc(struct igb_adapter *adapter)
3059{
3060 struct e1000_hw *hw = &adapter->hw;
3061 u32 mrqc, rxcsum;
797fd4be 3062 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3063 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3064 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3065 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3066 0xFA01ACBE };
06cf2666
AD		 3067
3068 /* Fill out hash function seeds */
a57fe23e
AD		 3069 for (j = 0; j < 10; j++)
3070 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3071
a99955fc 3072 num_rx_queues = adapter->rss_queues;
06cf2666 3073
797fd4be
AD		 3074 switch (hw->mac.type) {
3075 case e1000_82575:
3076 shift = 6;
3077 break;
3078 case e1000_82576:
3079 /* 82576 supports 2 RSS queues for SR-IOV */
3080 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3081 shift = 3;
3082 num_rx_queues = 2;
06cf2666 3083 }
797fd4be
AD		 3084 break;
3085 default:
3086 break;
06cf2666
AD		 3087 }
3088
797fd4be
AD		 3089 /*
3090 * Populate the indirection table 4 entries at a time. To do this
3091 * we are generating the results for n and n+2 and then interleaving
3092 * those with the results with n+1 and n+3.
3093 */
3094 for (j = 0; j < 32; j++) {
3095 /* first pass generates n and n+2 */
3096 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3097 u32 reta = (base & 0x07800780) >> (7 - shift);
3098
3099 /* second pass generates n+1 and n+3 */
3100 base += 0x00010001 * num_rx_queues;
3101 reta |= (base & 0x07800780) << (1 + shift);
3102
3103 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3104 }
3105
3106 /*
3107 * Disable raw packet checksumming so that RSS hash is placed in
3108 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3109 * offloads as they are enabled by default
3110 */
3111 rxcsum = rd32(E1000_RXCSUM);
3112 rxcsum |= E1000_RXCSUM_PCSD;
3113
3114 if (adapter->hw.mac.type >= e1000_82576)
3115 /* Enable Receive Checksum Offload for SCTP */
3116 rxcsum |= E1000_RXCSUM_CRCOFL;
3117
3118 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3119 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3120
039454a8
AA		 3121 /* Generate RSS hash based on packet types, TCP/UDP
3122 * port numbers and/or IPv4/v6 src and dst addresses
3123 */
f96a8a0b
CW		 3124 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3125 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3126 E1000_MRQC_RSS_FIELD_IPV6 |
3127 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3128 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3129
039454a8
AA		 3130 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3131 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3132 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3133 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3134
06cf2666
AD		 3135 /* If VMDq is enabled then we set the appropriate mode for that, else
3136 * we default to RSS so that an RSS hash is calculated per packet even
3137 * if we are only using one queue */
3138 if (adapter->vfs_allocated_count) {
3139 if (hw->mac.type > e1000_82575) {
3140 /* Set the default pool for the PF's first queue */
3141 u32 vtctl = rd32(E1000_VT_CTL);
3142 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3143 E1000_VT_CTL_DISABLE_DEF_POOL);
3144 vtctl |= adapter->vfs_allocated_count <<
3145 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3146 wr32(E1000_VT_CTL, vtctl);
3147 }
a99955fc 3148 if (adapter->rss_queues > 1)
f96a8a0b 3149 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3150 else
f96a8a0b 3151 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3152 } else {
f96a8a0b
CW		 3153 if (hw->mac.type != e1000_i211)
3154 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3155 }
3156 igb_vmm_control(adapter);
3157
06cf2666
AD		 3158 wr32(E1000_MRQC, mrqc);
3159}
3160
9d5c8243
AK		 3161/**
3162 * igb_setup_rctl - configure the receive control registers
3163 * @adapter: Board private structure
3164 **/
d7ee5b3a 3165void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3166{
3167 struct e1000_hw *hw = &adapter->hw;
3168 u32 rctl;
9d5c8243
AK		 3169
3170 rctl = rd32(E1000_RCTL);
3171
3172 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3173 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3174
69d728ba 3175 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3176 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3177
87cb7e8c
AK		 3178 /*
3179 * enable stripping of CRC. It's unlikely this will break BMC
3180 * redirection as it did with e1000. Newer features require
3181 * that the HW strips the CRC.
73cd78f1 3182 */
87cb7e8c 3183 rctl |= E1000_RCTL_SECRC;
9d5c8243 3184
559e9c49 3185 /* disable store bad packets and clear size bits. */
ec54d7d6 3186 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3187
6ec43fe6
AD		 3188 /* enable LPE to prevent packets larger than max_frame_size */
3189 rctl |= E1000_RCTL_LPE;
9d5c8243 3190
952f72a8
AD		 3191 /* disable queue 0 to prevent tail write w/o re-config */
3192 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3193
e1739522
AD		 3194 /* Attention!!! For SR-IOV PF driver operations you must enable
3195 * queue drop for all VF and PF queues to prevent head of line blocking
3196 * if an un-trusted VF does not provide descriptors to hardware.
3197 */
3198 if (adapter->vfs_allocated_count) {
e1739522
AD		 3199 /* set all queue drop enable bits */
3200 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3201 }
3202
89eaefb6
BG		 3203 /* This is useful for sniffing bad packets. */
3204 if (adapter->netdev->features & NETIF_F_RXALL) {
3205 /* UPE and MPE will be handled by normal PROMISC logic
3206 * in e1000e_set_rx_mode */
3207 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3208 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3209 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3210
3211 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3212 E1000_RCTL_DPF | /* Allow filtered pause */
3213 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3214 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3215 * and that breaks VLANs.
3216 */
3217 }
3218
9d5c8243
AK		 3219 wr32(E1000_RCTL, rctl);
3220}
3221
7d5753f0
AD		 3222static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3223 int vfn)
3224{
3225 struct e1000_hw *hw = &adapter->hw;
3226 u32 vmolr;
3227
3228 /* if it isn't the PF check to see if VFs are enabled and
3229 * increase the size to support vlan tags */
3230 if (vfn < adapter->vfs_allocated_count &&
3231 adapter->vf_data[vfn].vlans_enabled)
3232 size += VLAN_TAG_SIZE;
3233
3234 vmolr = rd32(E1000_VMOLR(vfn));
3235 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3236 vmolr |= size | E1000_VMOLR_LPE;
3237 wr32(E1000_VMOLR(vfn), vmolr);
3238
3239 return 0;
3240}
3241
e1739522
AD		 3242/**
3243 * igb_rlpml_set - set maximum receive packet size
3244 * @adapter: board private structure
3245 *
3246 * Configure maximum receivable packet size.
3247 **/
3248static void igb_rlpml_set(struct igb_adapter *adapter)
3249{
153285f9 3250 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3251 struct e1000_hw *hw = &adapter->hw;
3252 u16 pf_id = adapter->vfs_allocated_count;
3253
e1739522
AD		 3254 if (pf_id) {
3255 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3256 /*
3257 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3258 * to our max jumbo frame size, in case we need to enable
3259 * jumbo frames on one of the rings later.
3260 * This will not pass over-length frames into the default
3261 * queue because it's gated by the VMOLR.RLPML.
3262 */
7d5753f0 3263 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3264 }
3265
3266 wr32(E1000_RLPML, max_frame_size);
3267}
3268
8151d294
WM		 3269static inline void igb_set_vmolr(struct igb_adapter *adapter,
3270 int vfn, bool aupe)
7d5753f0
AD		 3271{
3272 struct e1000_hw *hw = &adapter->hw;
3273 u32 vmolr;
3274
3275 /*
3276 * This register exists only on 82576 and newer so if we are older then
3277 * we should exit and do nothing
3278 */
3279 if (hw->mac.type < e1000_82576)
3280 return;
3281
3282 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3283 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3284 if (aupe)
3285 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3286 else
3287 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3288
3289 /* clear all bits that might not be set */
3290 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3291
a99955fc 3292 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3293 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3294 /*
3295 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3296 * multicast packets
3297 */
3298 if (vfn <= adapter->vfs_allocated_count)
3299 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3300
3301 wr32(E1000_VMOLR(vfn), vmolr);
3302}
3303
85b430b4
AD		 3304/**
3305 * igb_configure_rx_ring - Configure a receive ring after Reset
3306 * @adapter: board private structure
3307 * @ring: receive ring to be configured
3308 *
3309 * Configure the Rx unit of the MAC after a reset.
3310 **/
d7ee5b3a
AD		 3311void igb_configure_rx_ring(struct igb_adapter *adapter,
3312 struct igb_ring *ring)
85b430b4
AD		 3313{
3314 struct e1000_hw *hw = &adapter->hw;
3315 u64 rdba = ring->dma;
3316 int reg_idx = ring->reg_idx;
a74420e0 3317 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3318
3319 /* disable the queue */
a74420e0 3320 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3321
3322 /* Set DMA base address registers */
3323 wr32(E1000_RDBAL(reg_idx),
3324 rdba & 0x00000000ffffffffULL);
3325 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3326 wr32(E1000_RDLEN(reg_idx),
3327 ring->count * sizeof(union e1000_adv_rx_desc));
3328
3329 /* initialize head and tail */
fce99e34 3330 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3331 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3332 writel(0, ring->tail);
85b430b4 3333
952f72a8 3334 /* set descriptor configuration */
44390ca6 3335 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3336 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3337 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3338 if (hw->mac.type >= e1000_82580)
757b77e2 3339 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3340 /* Only set Drop Enable if we are supporting multiple queues */
3341 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3342 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3343
3344 wr32(E1000_SRRCTL(reg_idx), srrctl);
3345
7d5753f0 3346 /* set filtering for VMDQ pools */
8151d294 3347 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3348
85b430b4
AD		 3349 rxdctl |= IGB_RX_PTHRESH;
3350 rxdctl |= IGB_RX_HTHRESH << 8;
3351 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3352
3353 /* enable receive descriptor fetching */
3354 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3355 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3356}
3357
9d5c8243
AK		 3358/**
3359 * igb_configure_rx - Configure receive Unit after Reset
3360 * @adapter: board private structure
3361 *
3362 * Configure the Rx unit of the MAC after a reset.
3363 **/
3364static void igb_configure_rx(struct igb_adapter *adapter)
3365{
9107584e 3366 int i;
9d5c8243 3367
68d480c4
AD		 3368 /* set UTA to appropriate mode */
3369 igb_set_uta(adapter);
3370
26ad9178
AD		 3371 /* set the correct pool for the PF default MAC address in entry 0 */
3372 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3373 adapter->vfs_allocated_count);
3374
06cf2666
AD		 3375 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3376 * the Base and Length of the Rx Descriptor Ring */
3377 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3378 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3379}
3380
3381/**
3382 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3383 * @tx_ring: Tx descriptor ring for a specific queue
3384 *
3385 * Free all transmit software resources
3386 **/
68fd9910 3387void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3388{
3b644cf6 3389 igb_clean_tx_ring(tx_ring);
9d5c8243 3390
06034649
AD		 3391 vfree(tx_ring->tx_buffer_info);
3392 tx_ring->tx_buffer_info = NULL;
9d5c8243 3393
439705e1
AD		 3394 /* if not set, then don't free */
3395 if (!tx_ring->desc)
3396 return;
3397
59d71989
AD		 3398 dma_free_coherent(tx_ring->dev, tx_ring->size,
3399 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3400
3401 tx_ring->desc = NULL;
3402}
3403
3404/**
3405 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3406 * @adapter: board private structure
3407 *
3408 * Free all transmit software resources
3409 **/
3410static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3411{
3412 int i;
3413
3414 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3415 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3416}
3417
ebe42d16
AD		 3418void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3419 struct igb_tx_buffer *tx_buffer)
3420{
3421 if (tx_buffer->skb) {
3422 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3423 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3424 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3425 dma_unmap_addr(tx_buffer, dma),
3426 dma_unmap_len(tx_buffer, len),
ebe42d16 3427 DMA_TO_DEVICE);
c9f14bf3 3428 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3429 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3430 dma_unmap_addr(tx_buffer, dma),
3431 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3432 DMA_TO_DEVICE);
3433 }
3434 tx_buffer->next_to_watch = NULL;
3435 tx_buffer->skb = NULL;
c9f14bf3 3436 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3437 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3438}
3439
3440/**
3441 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3442 * @tx_ring: ring to be cleaned
3443 **/
3b644cf6 3444static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3445{
06034649 3446 struct igb_tx_buffer *buffer_info;
9d5c8243 3447 unsigned long size;
6ad4edfc 3448 u16 i;
9d5c8243 3449
06034649 3450 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3451 return;
3452 /* Free all the Tx ring sk_buffs */
3453
3454 for (i = 0; i < tx_ring->count; i++) {
06034649 3455 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3456 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3457 }
3458
dad8a3b3
JF		 3459 netdev_tx_reset_queue(txring_txq(tx_ring));
3460
06034649
AD		 3461 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3462 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3463
3464 /* Zero out the descriptor ring */
9d5c8243
AK		 3465 memset(tx_ring->desc, 0, tx_ring->size);
3466
3467 tx_ring->next_to_use = 0;
3468 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3469}
3470
3471/**
3472 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3473 * @adapter: board private structure
3474 **/
3475static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3476{
3477 int i;
3478
3479 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3480 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3481}
3482
3483/**
3484 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3485 * @rx_ring: ring to clean the resources from
3486 *
3487 * Free all receive software resources
3488 **/
68fd9910 3489void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3490{
3b644cf6 3491 igb_clean_rx_ring(rx_ring);
9d5c8243 3492
06034649
AD		 3493 vfree(rx_ring->rx_buffer_info);
3494 rx_ring->rx_buffer_info = NULL;
9d5c8243 3495
439705e1
AD		 3496 /* if not set, then don't free */
3497 if (!rx_ring->desc)
3498 return;
3499
59d71989
AD		 3500 dma_free_coherent(rx_ring->dev, rx_ring->size,
3501 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3502
3503 rx_ring->desc = NULL;
3504}
3505
3506/**
3507 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3508 * @adapter: board private structure
3509 *
3510 * Free all receive software resources
3511 **/
3512static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3513{
3514 int i;
3515
3516 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3517 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3518}
3519
3520/**
3521 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3522 * @rx_ring: ring to free buffers from
3523 **/
3b644cf6 3524static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3525{
9d5c8243 3526 unsigned long size;
c023cd88 3527 u16 i;
9d5c8243 3528
1a1c225b
AD		 3529 if (rx_ring->skb)
3530 dev_kfree_skb(rx_ring->skb);
3531 rx_ring->skb = NULL;
3532
06034649 3533 if (!rx_ring->rx_buffer_info)
9d5c8243 3534 return;
439705e1 3535
9d5c8243
AK		 3536 /* Free all the Rx ring sk_buffs */
3537 for (i = 0; i < rx_ring->count; i++) {
06034649 3538 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3539
cbc8e55f
AD		 3540 if (!buffer_info->page)
3541 continue;
3542
3543 dma_unmap_page(rx_ring->dev,
3544 buffer_info->dma,
3545 PAGE_SIZE,
3546 DMA_FROM_DEVICE);
3547 __free_page(buffer_info->page);
3548
1a1c225b 3549 buffer_info->page = NULL;
9d5c8243
AK		 3550 }
3551
06034649
AD		 3552 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3553 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3554
3555 /* Zero out the descriptor ring */
3556 memset(rx_ring->desc, 0, rx_ring->size);
3557
cbc8e55f 3558 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3559 rx_ring->next_to_clean = 0;
3560 rx_ring->next_to_use = 0;
9d5c8243
AK		 3561}
3562
3563/**
3564 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3565 * @adapter: board private structure
3566 **/
3567static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3568{
3569 int i;
3570
3571 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3572 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3573}
3574
3575/**
3576 * igb_set_mac - Change the Ethernet Address of the NIC
3577 * @netdev: network interface device structure
3578 * @p: pointer to an address structure
3579 *
3580 * Returns 0 on success, negative on failure
3581 **/
3582static int igb_set_mac(struct net_device *netdev, void *p)
3583{
3584 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3585 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3586 struct sockaddr *addr = p;
3587
3588 if (!is_valid_ether_addr(addr->sa_data))
3589 return -EADDRNOTAVAIL;
3590
3591 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3592 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3593
26ad9178
AD		 3594 /* set the correct pool for the new PF MAC address in entry 0 */
3595 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3596 adapter->vfs_allocated_count);
e1739522 3597
9d5c8243
AK		 3598 return 0;
3599}
3600
3601/**
68d480c4 3602 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3603 * @netdev: network interface device structure
3604 *
68d480c4
AD		 3605 * Writes multicast address list to the MTA hash table.
3606 * Returns: -ENOMEM on failure
3607 * 0 on no addresses written
3608 * X on writing X addresses to MTA
9d5c8243 3609 **/
68d480c4 3610static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3611{
3612 struct igb_adapter *adapter = netdev_priv(netdev);
3613 struct e1000_hw *hw = &adapter->hw;
22bedad3 3614 struct netdev_hw_addr *ha;
68d480c4 3615 u8 *mta_list;
9d5c8243
AK		 3616 int i;
3617
4cd24eaf 3618 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3619 /* nothing to program, so clear mc list */
3620 igb_update_mc_addr_list(hw, NULL, 0);
3621 igb_restore_vf_multicasts(adapter);
3622 return 0;
3623 }
9d5c8243 3624
4cd24eaf 3625 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3626 if (!mta_list)
3627 return -ENOMEM;
ff41f8dc 3628
68d480c4 3629 /* The shared function expects a packed array of only addresses. */
48e2f183 3630 i = 0;
22bedad3
JP		 3631 netdev_for_each_mc_addr(ha, netdev)
3632 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3633
68d480c4
AD		 3634 igb_update_mc_addr_list(hw, mta_list, i);
3635 kfree(mta_list);
3636
4cd24eaf 3637 return netdev_mc_count(netdev);
68d480c4
AD		 3638}
3639
3640/**
3641 * igb_write_uc_addr_list - write unicast addresses to RAR table
3642 * @netdev: network interface device structure
3643 *
3644 * Writes unicast address list to the RAR table.
3645 * Returns: -ENOMEM on failure/insufficient address space
3646 * 0 on no addresses written
3647 * X on writing X addresses to the RAR table
3648 **/
3649static int igb_write_uc_addr_list(struct net_device *netdev)
3650{
3651 struct igb_adapter *adapter = netdev_priv(netdev);
3652 struct e1000_hw *hw = &adapter->hw;
3653 unsigned int vfn = adapter->vfs_allocated_count;
3654 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3655 int count = 0;
3656
3657 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3658 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3659 return -ENOMEM;
9d5c8243 3660
32e7bfc4 3661 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3662 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3663
3664 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3665 if (!rar_entries)
3666 break;
26ad9178
AD		 3667 igb_rar_set_qsel(adapter, ha->addr,
3668 rar_entries--,
68d480c4
AD		 3669 vfn);
3670 count++;
ff41f8dc
AD		 3671 }
3672 }
3673 /* write the addresses in reverse order to avoid write combining */
3674 for (; rar_entries > 0 ; rar_entries--) {
3675 wr32(E1000_RAH(rar_entries), 0);
3676 wr32(E1000_RAL(rar_entries), 0);
3677 }
3678 wrfl();
3679
68d480c4
AD		 3680 return count;
3681}
3682
3683/**
3684 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3685 * @netdev: network interface device structure
3686 *
3687 * The set_rx_mode entry point is called whenever the unicast or multicast
3688 * address lists or the network interface flags are updated. This routine is
3689 * responsible for configuring the hardware for proper unicast, multicast,
3690 * promiscuous mode, and all-multi behavior.
3691 **/
3692static void igb_set_rx_mode(struct net_device *netdev)
3693{
3694 struct igb_adapter *adapter = netdev_priv(netdev);
3695 struct e1000_hw *hw = &adapter->hw;
3696 unsigned int vfn = adapter->vfs_allocated_count;
3697 u32 rctl, vmolr = 0;
3698 int count;
3699
3700 /* Check for Promiscuous and All Multicast modes */
3701 rctl = rd32(E1000_RCTL);
3702
3703 /* clear the effected bits */
3704 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3705
3706 if (netdev->flags & IFF_PROMISC) {
3707 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3708 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3709 } else {
3710 if (netdev->flags & IFF_ALLMULTI) {
3711 rctl |= E1000_RCTL_MPE;
3712 vmolr |= E1000_VMOLR_MPME;
3713 } else {
3714 /*
3715 * Write addresses to the MTA, if the attempt fails
25985edc 3716 * then we should just turn on promiscuous mode so
68d480c4
AD		 3717 * that we can at least receive multicast traffic
3718 */
3719 count = igb_write_mc_addr_list(netdev);
3720 if (count < 0) {
3721 rctl |= E1000_RCTL_MPE;
3722 vmolr |= E1000_VMOLR_MPME;
3723 } else if (count) {
3724 vmolr |= E1000_VMOLR_ROMPE;
3725 }
3726 }
3727 /*
3728 * Write addresses to available RAR registers, if there is not
3729 * sufficient space to store all the addresses then enable
25985edc 3730 * unicast promiscuous mode
68d480c4
AD		 3731 */
3732 count = igb_write_uc_addr_list(netdev);
3733 if (count < 0) {
3734 rctl |= E1000_RCTL_UPE;
3735 vmolr |= E1000_VMOLR_ROPE;
3736 }
3737 rctl |= E1000_RCTL_VFE;
28fc06f5 3738 }
68d480c4 3739 wr32(E1000_RCTL, rctl);
28fc06f5 3740
68d480c4
AD		 3741 /*
3742 * In order to support SR-IOV and eventually VMDq it is necessary to set
3743 * the VMOLR to enable the appropriate modes. Without this workaround
3744 * we will have issues with VLAN tag stripping not being done for frames
3745 * that are only arriving because we are the default pool
3746 */
f96a8a0b 3747 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3748 return;
9d5c8243 3749
68d480c4
AD		 3750 vmolr |= rd32(E1000_VMOLR(vfn)) &
3751 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3752 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3753 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3754}
3755
13800469
GR		 3756static void igb_check_wvbr(struct igb_adapter *adapter)
3757{
3758 struct e1000_hw *hw = &adapter->hw;
3759 u32 wvbr = 0;
3760
3761 switch (hw->mac.type) {
3762 case e1000_82576:
3763 case e1000_i350:
3764 if (!(wvbr = rd32(E1000_WVBR)))
3765 return;
3766 break;
3767 default:
3768 break;
3769 }
3770
3771 adapter->wvbr |= wvbr;
3772}
3773
3774#define IGB_STAGGERED_QUEUE_OFFSET 8
3775
3776static void igb_spoof_check(struct igb_adapter *adapter)
3777{
3778 int j;
3779
3780 if (!adapter->wvbr)
3781 return;
3782
3783 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3784 if (adapter->wvbr & (1 << j) ||
3785 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3786 dev_warn(&adapter->pdev->dev,
3787 "Spoof event(s) detected on VF %d\n", j);
3788 adapter->wvbr &=
3789 ~((1 << j) |
3790 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3791 }
3792 }
3793}
3794
9d5c8243
AK		 3795/* Need to wait a few seconds after link up to get diagnostic information from
3796 * the phy */
3797static void igb_update_phy_info(unsigned long data)
3798{
3799 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3800 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3801}
3802
4d6b725e
AD		 3803/**
3804 * igb_has_link - check shared code for link and determine up/down
3805 * @adapter: pointer to driver private info
3806 **/
3145535a 3807bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3808{
3809 struct e1000_hw *hw = &adapter->hw;
3810 bool link_active = false;
3811 s32 ret_val = 0;
3812
3813 /* get_link_status is set on LSC (link status) interrupt or
3814 * rx sequence error interrupt. get_link_status will stay
3815 * false until the e1000_check_for_link establishes link
3816 * for copper adapters ONLY
3817 */
3818 switch (hw->phy.media_type) {
3819 case e1000_media_type_copper:
3820 if (hw->mac.get_link_status) {
3821 ret_val = hw->mac.ops.check_for_link(hw);
3822 link_active = !hw->mac.get_link_status;
3823 } else {
3824 link_active = true;
3825 }
3826 break;
4d6b725e
AD		 3827 case e1000_media_type_internal_serdes:
3828 ret_val = hw->mac.ops.check_for_link(hw);
3829 link_active = hw->mac.serdes_has_link;
3830 break;
3831 default:
3832 case e1000_media_type_unknown:
3833 break;
3834 }
3835
3836 return link_active;
3837}
3838
563988dc
SA		 3839static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3840{
3841 bool ret = false;
3842 u32 ctrl_ext, thstat;
3843
f96a8a0b 3844 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3845 if (hw->mac.type == e1000_i350) {
3846 thstat = rd32(E1000_THSTAT);
3847 ctrl_ext = rd32(E1000_CTRL_EXT);
3848
3849 if ((hw->phy.media_type == e1000_media_type_copper) &&
3850 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3851 ret = !!(thstat & event);
3852 }
3853 }
3854
3855 return ret;
3856}
3857
9d5c8243
AK		 3858/**
3859 * igb_watchdog - Timer Call-back
3860 * @data: pointer to adapter cast into an unsigned long
3861 **/
3862static void igb_watchdog(unsigned long data)
3863{
3864 struct igb_adapter *adapter = (struct igb_adapter *)data;
3865 /* Do the rest outside of interrupt context */
3866 schedule_work(&adapter->watchdog_task);
3867}
3868
3869static void igb_watchdog_task(struct work_struct *work)
3870{
3871 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3872 struct igb_adapter,
3873 watchdog_task);
9d5c8243 3874 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3875 struct net_device *netdev = adapter->netdev;
563988dc 3876 u32 link;
7a6ea550 3877 int i;
9d5c8243 3878
4d6b725e 3879 link = igb_has_link(adapter);
9d5c8243 3880 if (link) {
749ab2cd
YZ		 3881 /* Cancel scheduled suspend requests. */
3882 pm_runtime_resume(netdev->dev.parent);
3883
9d5c8243
AK		 3884 if (!netif_carrier_ok(netdev)) {
3885 u32 ctrl;
330a6d6a
AD		 3886 hw->mac.ops.get_speed_and_duplex(hw,
3887 &adapter->link_speed,
3888 &adapter->link_duplex);
9d5c8243
AK		 3889
3890 ctrl = rd32(E1000_CTRL);
527d47c1 3891 /* Links status message must follow this format */
876d2d6f
JK		 3892 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3893 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3894 netdev->name,
3895 adapter->link_speed,
3896 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3897 "Full" : "Half",
3898 (ctrl & E1000_CTRL_TFCE) &&
3899 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3900 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3901 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3902
563988dc 3903 /* check for thermal sensor event */
876d2d6f
JK		 3904 if (igb_thermal_sensor_event(hw,
3905 E1000_THSTAT_LINK_THROTTLE)) {
3906 netdev_info(netdev, "The network adapter link "
3907 "speed was downshifted because it "
3908 "overheated\n");
7ef5ed1c 3909 }
563988dc 3910
d07f3e37 3911 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3912 adapter->tx_timeout_factor = 1;
3913 switch (adapter->link_speed) {
3914 case SPEED_10:
9d5c8243
AK		 3915 adapter->tx_timeout_factor = 14;
3916 break;
3917 case SPEED_100:
9d5c8243
AK		 3918 /* maybe add some timeout factor ? */
3919 break;
3920 }
3921
3922 netif_carrier_on(netdev);
9d5c8243 3923
4ae196df 3924 igb_ping_all_vfs(adapter);
17dc566c 3925 igb_check_vf_rate_limit(adapter);
4ae196df 3926
4b1a9877 3927 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3928 if (!test_bit(__IGB_DOWN, &adapter->state))
3929 mod_timer(&adapter->phy_info_timer,
3930 round_jiffies(jiffies + 2 * HZ));
3931 }
3932 } else {
3933 if (netif_carrier_ok(netdev)) {
3934 adapter->link_speed = 0;
3935 adapter->link_duplex = 0;
563988dc
SA		 3936
3937 /* check for thermal sensor event */
876d2d6f
JK		 3938 if (igb_thermal_sensor_event(hw,
3939 E1000_THSTAT_PWR_DOWN)) {
3940 netdev_err(netdev, "The network adapter was "
3941 "stopped because it overheated\n");
7ef5ed1c 3942 }
563988dc 3943
527d47c1
AD		 3944 /* Links status message must follow this format */
3945 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3946 netdev->name);
9d5c8243 3947 netif_carrier_off(netdev);
4b1a9877 3948
4ae196df
AD		 3949 igb_ping_all_vfs(adapter);
3950
4b1a9877 3951 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3952 if (!test_bit(__IGB_DOWN, &adapter->state))
3953 mod_timer(&adapter->phy_info_timer,
3954 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3955
3956 pm_schedule_suspend(netdev->dev.parent,
3957 MSEC_PER_SEC * 5);
9d5c8243
AK		 3958 }
3959 }
3960
12dcd86b
ED		 3961 spin_lock(&adapter->stats64_lock);
3962 igb_update_stats(adapter, &adapter->stats64);
3963 spin_unlock(&adapter->stats64_lock);
9d5c8243 3964
dbabb065 3965 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3966 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3967 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3968 /* We've lost link, so the controller stops DMA,
3969 * but we've got queued Tx work that's never going
3970 * to get done, so reset controller to flush Tx.
3971 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3972 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3973 adapter->tx_timeout_count++;
3974 schedule_work(&adapter->reset_task);
3975 /* return immediately since reset is imminent */
3976 return;
3977 }
9d5c8243 3978 }
9d5c8243 3979
dbabb065 3980 /* Force detection of hung controller every watchdog period */
6d095fa8 3981 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3982 }
f7ba205e 3983
9d5c8243 3984 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3985 if (adapter->msix_entries) {
047e0030 3986 u32 eics = 0;
0d1ae7f4
AD		 3987 for (i = 0; i < adapter->num_q_vectors; i++)
3988 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3989 wr32(E1000_EICS, eics);
3990 } else {
3991 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3992 }
9d5c8243 3993
13800469 3994 igb_spoof_check(adapter);
fc580751 3995 igb_ptp_rx_hang(adapter);
13800469 3996
9d5c8243
AK		 3997 /* Reset the timer */
3998 if (!test_bit(__IGB_DOWN, &adapter->state))
3999 mod_timer(&adapter->watchdog_timer,
4000 round_jiffies(jiffies + 2 * HZ));
4001}
4002
4003enum latency_range {
4004 lowest_latency = 0,
4005 low_latency = 1,
4006 bulk_latency = 2,
4007 latency_invalid = 255
4008};
4009
6eb5a7f1
AD		 4010/**
4011 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4012 *
4013 * Stores a new ITR value based on strictly on packet size. This
4014 * algorithm is less sophisticated than that used in igb_update_itr,
4015 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 4016 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 4017 * were determined based on theoretical maximum wire speed and testing
4018 * data, in order to minimize response time while increasing bulk
4019 * throughput.
4020 * This functionality is controlled by the InterruptThrottleRate module
4021 * parameter (see igb_param.c)
4022 * NOTE: This function is called only when operating in a multiqueue
4023 * receive environment.
047e0030 4024 * @q_vector: pointer to q_vector
6eb5a7f1 4025 **/
047e0030 4026static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4027{
047e0030 4028 int new_val = q_vector->itr_val;
6eb5a7f1 4029 int avg_wire_size = 0;
047e0030 4030 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4031 unsigned int packets;
9d5c8243 4032
6eb5a7f1
AD		 4033 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4034 * ints/sec - ITR timer value of 120 ticks.
4035 */
4036 if (adapter->link_speed != SPEED_1000) {
0ba82994 4037 new_val = IGB_4K_ITR;
6eb5a7f1 4038 goto set_itr_val;
9d5c8243 4039 }
047e0030 4040
0ba82994
AD		 4041 packets = q_vector->rx.total_packets;
4042 if (packets)
4043 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4044
0ba82994
AD		 4045 packets = q_vector->tx.total_packets;
4046 if (packets)
4047 avg_wire_size = max_t(u32, avg_wire_size,
4048 q_vector->tx.total_bytes / packets);
047e0030
AD		 4049
4050 /* if avg_wire_size isn't set no work was done */
4051 if (!avg_wire_size)
4052 goto clear_counts;
9d5c8243 4053
6eb5a7f1
AD		 4054 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4055 avg_wire_size += 24;
4056
4057 /* Don't starve jumbo frames */
4058 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4059
6eb5a7f1
AD		 4060 /* Give a little boost to mid-size frames */
4061 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4062 new_val = avg_wire_size / 3;
4063 else
4064 new_val = avg_wire_size / 2;
9d5c8243 4065
0ba82994
AD		 4066 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4067 if (new_val < IGB_20K_ITR &&
4068 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4069 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4070 new_val = IGB_20K_ITR;
abe1c363 4071
6eb5a7f1 4072set_itr_val:
047e0030
AD		 4073 if (new_val != q_vector->itr_val) {
4074 q_vector->itr_val = new_val;
4075 q_vector->set_itr = 1;
9d5c8243 4076 }
6eb5a7f1 4077clear_counts:
0ba82994
AD		 4078 q_vector->rx.total_bytes = 0;
4079 q_vector->rx.total_packets = 0;
4080 q_vector->tx.total_bytes = 0;
4081 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4082}
4083
4084/**
4085 * igb_update_itr - update the dynamic ITR value based on statistics
4086 * Stores a new ITR value based on packets and byte
4087 * counts during the last interrupt. The advantage of per interrupt
4088 * computation is faster updates and more accurate ITR for the current
4089 * traffic pattern. Constants in this function were computed
4090 * based on theoretical maximum wire speed and thresholds were set based
4091 * on testing data as well as attempting to minimize response time
4092 * while increasing bulk throughput.
4093 * this functionality is controlled by the InterruptThrottleRate module
4094 * parameter (see igb_param.c)
4095 * NOTE: These calculations are only valid when operating in a single-
4096 * queue environment.
0ba82994
AD		 4097 * @q_vector: pointer to q_vector
4098 * @ring_container: ring info to update the itr for
9d5c8243 4099 **/
0ba82994
AD		 4100static void igb_update_itr(struct igb_q_vector *q_vector,
4101 struct igb_ring_container *ring_container)
9d5c8243 4102{
0ba82994
AD		 4103 unsigned int packets = ring_container->total_packets;
4104 unsigned int bytes = ring_container->total_bytes;
4105 u8 itrval = ring_container->itr;
9d5c8243 4106
0ba82994 4107 /* no packets, exit with status unchanged */
9d5c8243 4108 if (packets == 0)
0ba82994 4109 return;
9d5c8243 4110
0ba82994 4111 switch (itrval) {
9d5c8243
AK		 4112 case lowest_latency:
4113 /* handle TSO and jumbo frames */
4114 if (bytes/packets > 8000)
0ba82994 4115 itrval = bulk_latency;
9d5c8243 4116 else if ((packets < 5) && (bytes > 512))
0ba82994 4117 itrval = low_latency;
9d5c8243
AK		 4118 break;
4119 case low_latency: /* 50 usec aka 20000 ints/s */
4120 if (bytes > 10000) {
4121 /* this if handles the TSO accounting */
4122 if (bytes/packets > 8000) {
0ba82994 4123 itrval = bulk_latency;
9d5c8243 4124 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4125 itrval = bulk_latency;
9d5c8243 4126 } else if ((packets > 35)) {
0ba82994 4127 itrval = lowest_latency;
9d5c8243
AK		 4128 }
4129 } else if (bytes/packets > 2000) {
0ba82994 4130 itrval = bulk_latency;
9d5c8243 4131 } else if (packets <= 2 && bytes < 512) {
0ba82994 4132 itrval = lowest_latency;
9d5c8243
AK		 4133 }
4134 break;
4135 case bulk_latency: /* 250 usec aka 4000 ints/s */
4136 if (bytes > 25000) {
4137 if (packets > 35)
0ba82994 4138 itrval = low_latency;
1e5c3d21 4139 } else if (bytes < 1500) {
0ba82994 4140 itrval = low_latency;
9d5c8243
AK		 4141 }
4142 break;
4143 }
4144
0ba82994
AD		 4145 /* clear work counters since we have the values we need */
4146 ring_container->total_bytes = 0;
4147 ring_container->total_packets = 0;
4148
4149 /* write updated itr to ring container */
4150 ring_container->itr = itrval;
9d5c8243
AK		 4151}
4152
0ba82994 4153static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4154{
0ba82994 4155 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4156 u32 new_itr = q_vector->itr_val;
0ba82994 4157 u8 current_itr = 0;
9d5c8243
AK		 4158
4159 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4160 if (adapter->link_speed != SPEED_1000) {
4161 current_itr = 0;
0ba82994 4162 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4163 goto set_itr_now;
4164 }
4165
0ba82994
AD		 4166 igb_update_itr(q_vector, &q_vector->tx);
4167 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4168
0ba82994 4169 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4170
6eb5a7f1 4171 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4172 if (current_itr == lowest_latency &&
4173 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4174 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4175 current_itr = low_latency;
4176
9d5c8243
AK		 4177 switch (current_itr) {
4178 /* counts and packets in update_itr are dependent on these numbers */
4179 case lowest_latency:
0ba82994 4180 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4181 break;
4182 case low_latency:
0ba82994 4183 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4184 break;
4185 case bulk_latency:
0ba82994 4186 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4187 break;
4188 default:
4189 break;
4190 }
4191
4192set_itr_now:
047e0030 4193 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4194 /* this attempts to bias the interrupt rate towards Bulk
4195 * by adding intermediate steps when interrupt rate is
4196 * increasing */
047e0030
AD		 4197 new_itr = new_itr > q_vector->itr_val ?
4198 max((new_itr * q_vector->itr_val) /
4199 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 4200 new_itr) :
9d5c8243
AK		 4201 new_itr;
4202 /* Don't write the value here; it resets the adapter's
4203 * internal timer, and causes us to delay far longer than
4204 * we should between interrupts. Instead, we write the ITR
4205 * value at the beginning of the next interrupt so the timing
4206 * ends up being correct.
4207 */
047e0030
AD		 4208 q_vector->itr_val = new_itr;
4209 q_vector->set_itr = 1;
9d5c8243 4210 }
9d5c8243
AK		 4211}
4212
c50b52a0
SH		 4213static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4214 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4215{
4216 struct e1000_adv_tx_context_desc *context_desc;
4217 u16 i = tx_ring->next_to_use;
4218
4219 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4220
4221 i++;
4222 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4223
4224 /* set bits to identify this as an advanced context descriptor */
4225 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4226
4227 /* For 82575, context index must be unique per ring. */
866cff06 4228 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4229 mss_l4len_idx |= tx_ring->reg_idx << 4;
4230
4231 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4232 context_desc->seqnum_seed = 0;
4233 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4234 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4235}
4236
7af40ad9
AD		 4237static int igb_tso(struct igb_ring *tx_ring,
4238 struct igb_tx_buffer *first,
4239 u8 *hdr_len)
9d5c8243 4240{
7af40ad9 4241 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4242 u32 vlan_macip_lens, type_tucmd;
4243 u32 mss_l4len_idx, l4len;
4244
ed6aa105
AD		 4245 if (skb->ip_summed != CHECKSUM_PARTIAL)
4246 return 0;
4247
7d13a7d0
AD		 4248 if (!skb_is_gso(skb))
4249 return 0;
9d5c8243
AK		 4250
4251 if (skb_header_cloned(skb)) {
7af40ad9 4252 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4253 if (err)
4254 return err;
4255 }
4256
7d13a7d0
AD		 4257 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4258 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4259
7af40ad9 4260 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4261 struct iphdr *iph = ip_hdr(skb);
4262 iph->tot_len = 0;
4263 iph->check = 0;
4264 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4265 iph->daddr, 0,
4266 IPPROTO_TCP,
4267 0);
7d13a7d0 4268 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4269 first->tx_flags |= IGB_TX_FLAGS_TSO |
4270 IGB_TX_FLAGS_CSUM |
4271 IGB_TX_FLAGS_IPV4;
8e1e8a47 4272 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4273 ipv6_hdr(skb)->payload_len = 0;
4274 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4275 &ipv6_hdr(skb)->daddr,
4276 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4277 first->tx_flags |= IGB_TX_FLAGS_TSO |
4278 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4279 }
4280
7af40ad9 4281 /* compute header lengths */
7d13a7d0
AD		 4282 l4len = tcp_hdrlen(skb);
4283 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4284
7af40ad9
AD		 4285 /* update gso size and bytecount with header size */
4286 first->gso_segs = skb_shinfo(skb)->gso_segs;
4287 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4288
9d5c8243 4289 /* MSS L4LEN IDX */
7d13a7d0
AD		 4290 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4291 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4292
7d13a7d0
AD		 4293 /* VLAN MACLEN IPLEN */
4294 vlan_macip_lens = skb_network_header_len(skb);
4295 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4296 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4297
7d13a7d0 4298 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4299
7d13a7d0 4300 return 1;
9d5c8243
AK		 4301}
4302
7af40ad9 4303static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4304{
7af40ad9 4305 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4306 u32 vlan_macip_lens = 0;
4307 u32 mss_l4len_idx = 0;
4308 u32 type_tucmd = 0;
9d5c8243 4309
7d13a7d0 4310 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4311 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4312 return;
7d13a7d0
AD		 4313 } else {
4314 u8 l4_hdr = 0;
7af40ad9 4315 switch (first->protocol) {
7d13a7d0
AD		 4316 case __constant_htons(ETH_P_IP):
4317 vlan_macip_lens |= skb_network_header_len(skb);
4318 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4319 l4_hdr = ip_hdr(skb)->protocol;
4320 break;
4321 case __constant_htons(ETH_P_IPV6):
4322 vlan_macip_lens |= skb_network_header_len(skb);
4323 l4_hdr = ipv6_hdr(skb)->nexthdr;
4324 break;
4325 default:
4326 if (unlikely(net_ratelimit())) {
4327 dev_warn(tx_ring->dev,
4328 "partial checksum but proto=%x!\n",
7af40ad9 4329 first->protocol);
fa4a7ef3 4330 }
7d13a7d0
AD		 4331 break;
4332 }
fa4a7ef3 4333
7d13a7d0
AD		 4334 switch (l4_hdr) {
4335 case IPPROTO_TCP:
4336 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4337 mss_l4len_idx = tcp_hdrlen(skb) <<
4338 E1000_ADVTXD_L4LEN_SHIFT;
4339 break;
4340 case IPPROTO_SCTP:
4341 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4342 mss_l4len_idx = sizeof(struct sctphdr) <<
4343 E1000_ADVTXD_L4LEN_SHIFT;
4344 break;
4345 case IPPROTO_UDP:
4346 mss_l4len_idx = sizeof(struct udphdr) <<
4347 E1000_ADVTXD_L4LEN_SHIFT;
4348 break;
4349 default:
4350 if (unlikely(net_ratelimit())) {
4351 dev_warn(tx_ring->dev,
4352 "partial checksum but l4 proto=%x!\n",
4353 l4_hdr);
44b0cda3 4354 }
7d13a7d0 4355 break;
9d5c8243 4356 }
7af40ad9
AD		 4357
4358 /* update TX checksum flag */
4359 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4360 }
9d5c8243 4361
7d13a7d0 4362 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4363 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4364
7d13a7d0 4365 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4366}
4367
1d9daf45
AD		 4368#define IGB_SET_FLAG(_input, _flag, _result) \
4369 ((_flag <= _result) ? \
4370 ((u32)(_input & _flag) * (_result / _flag)) : \
4371 ((u32)(_input & _flag) / (_flag / _result)))
4372
4373static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4374{
4375 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4376 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4377 E1000_ADVTXD_DCMD_DEXT |
4378 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4379
4380 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4381 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4382 (E1000_ADVTXD_DCMD_VLE));
4383
4384 /* set segmentation bits for TSO */
4385 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4386 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4387
4388 /* set timestamp bit if present */
1d9daf45
AD		 4389 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4390 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4391
1d9daf45
AD		 4392 /* insert frame checksum */
4393 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4394
4395 return cmd_type;
4396}
4397
7af40ad9
AD		 4398static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4399 union e1000_adv_tx_desc *tx_desc,
4400 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4401{
4402 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4403
1d9daf45
AD		 4404 /* 82575 requires a unique index per ring */
4405 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4406 olinfo_status |= tx_ring->reg_idx << 4;
4407
4408 /* insert L4 checksum */
1d9daf45
AD		 4409 olinfo_status |= IGB_SET_FLAG(tx_flags,
4410 IGB_TX_FLAGS_CSUM,
4411 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4412
1d9daf45
AD		 4413 /* insert IPv4 checksum */
4414 olinfo_status |= IGB_SET_FLAG(tx_flags,
4415 IGB_TX_FLAGS_IPV4,
4416 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4417
7af40ad9 4418 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4419}
4420
ebe42d16
AD		 4421/*
4422 * The largest size we can write to the descriptor is 65535. In order to
4423 * maintain a power of two alignment we have to limit ourselves to 32K.
4424 */
4425#define IGB_MAX_TXD_PWR 15
7af40ad9 4426#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4427
7af40ad9
AD		 4428static void igb_tx_map(struct igb_ring *tx_ring,
4429 struct igb_tx_buffer *first,
ebe42d16 4430 const u8 hdr_len)
9d5c8243 4431{
7af40ad9 4432 struct sk_buff *skb = first->skb;
c9f14bf3 4433 struct igb_tx_buffer *tx_buffer;
ebe42d16 4434 union e1000_adv_tx_desc *tx_desc;
80d0759e 4435 struct skb_frag_struct *frag;
ebe42d16 4436 dma_addr_t dma;
80d0759e 4437 unsigned int data_len, size;
7af40ad9 4438 u32 tx_flags = first->tx_flags;
1d9daf45 4439 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4440 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4441
4442 tx_desc = IGB_TX_DESC(tx_ring, i);
4443
80d0759e
AD		 4444 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4445
4446 size = skb_headlen(skb);
4447 data_len = skb->data_len;
ebe42d16
AD		 4448
4449 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4450
80d0759e
AD		 4451 tx_buffer = first;
4452
4453 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4454 if (dma_mapping_error(tx_ring->dev, dma))
4455 goto dma_error;
4456
4457 /* record length, and DMA address */
4458 dma_unmap_len_set(tx_buffer, len, size);
4459 dma_unmap_addr_set(tx_buffer, dma, dma);
4460
4461 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4462
ebe42d16
AD		 4463 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4464 tx_desc->read.cmd_type_len =
1d9daf45 4465 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4466
4467 i++;
4468 tx_desc++;
4469 if (i == tx_ring->count) {
4470 tx_desc = IGB_TX_DESC(tx_ring, 0);
4471 i = 0;
4472 }
80d0759e 4473 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4474
4475 dma += IGB_MAX_DATA_PER_TXD;
4476 size -= IGB_MAX_DATA_PER_TXD;
4477
ebe42d16
AD		 4478 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4479 }
4480
4481 if (likely(!data_len))
4482 break;
2bbfebe2 4483
1d9daf45 4484 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4485
65689fef 4486 i++;
ebe42d16
AD		 4487 tx_desc++;
4488 if (i == tx_ring->count) {
4489 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4490 i = 0;
ebe42d16 4491 }
80d0759e 4492 tx_desc->read.olinfo_status = 0;
65689fef 4493
9e903e08 4494 size = skb_frag_size(frag);
ebe42d16
AD		 4495 data_len -= size;
4496
4497 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4498 size, DMA_TO_DEVICE);
6366ad33 4499
c9f14bf3 4500 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4501 }
4502
ebe42d16 4503 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4504 cmd_type |= size | IGB_TXD_DCMD;
4505 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4506
80d0759e
AD		 4507 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4508
8542db05
AD		 4509 /* set the timestamp */
4510 first->time_stamp = jiffies;
4511
ebe42d16
AD		 4512 /*
4513 * Force memory writes to complete before letting h/w know there
4514 * are new descriptors to fetch. (Only applicable for weak-ordered
4515 * memory model archs, such as IA-64).
4516 *
4517 * We also need this memory barrier to make certain all of the
4518 * status bits have been updated before next_to_watch is written.
4519 */
4520 wmb();
4521
8542db05 4522 /* set next_to_watch value indicating a packet is present */
ebe42d16 4523 first->next_to_watch = tx_desc;
9d5c8243 4524
ebe42d16
AD		 4525 i++;
4526 if (i == tx_ring->count)
4527 i = 0;
6366ad33 4528
ebe42d16 4529 tx_ring->next_to_use = i;
6366ad33 4530
ebe42d16 4531 writel(i, tx_ring->tail);
6366ad33 4532
ebe42d16
AD		 4533 /* we need this if more than one processor can write to our tail
4534 * at a time, it syncronizes IO on IA64/Altix systems */
4535 mmiowb();
4536
4537 return;
4538
4539dma_error:
4540 dev_err(tx_ring->dev, "TX DMA map failed\n");
4541
4542 /* clear dma mappings for failed tx_buffer_info map */
4543 for (;;) {
c9f14bf3
AD		 4544 tx_buffer = &tx_ring->tx_buffer_info[i];
4545 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4546 if (tx_buffer == first)
ebe42d16 4547 break;
a77ff709
NN		 4548 if (i == 0)
4549 i = tx_ring->count;
6366ad33 4550 i--;
6366ad33
AD		 4551 }
4552
9d5c8243 4553 tx_ring->next_to_use = i;
9d5c8243
AK		 4554}
4555
6ad4edfc 4556static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4557{
e694e964
AD		 4558 struct net_device *netdev = tx_ring->netdev;
4559
661086df 4560 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4561
9d5c8243
AK		 4562 /* Herbert's original patch had:
4563 * smp_mb__after_netif_stop_queue();
4564 * but since that doesn't exist yet, just open code it. */
4565 smp_mb();
4566
4567 /* We need to check again in a case another CPU has just
4568 * made room available. */
c493ea45 4569 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4570 return -EBUSY;
4571
4572 /* A reprieve! */
661086df 4573 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4574
4575 u64_stats_update_begin(&tx_ring->tx_syncp2);
4576 tx_ring->tx_stats.restart_queue2++;
4577 u64_stats_update_end(&tx_ring->tx_syncp2);
4578
9d5c8243
AK		 4579 return 0;
4580}
4581
6ad4edfc 4582static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4583{
c493ea45 4584 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4585 return 0;
e694e964 4586 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4587}
4588
cd392f5c
AD		 4589netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4590 struct igb_ring *tx_ring)
9d5c8243 4591{
1f6e8178 4592 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4593 struct igb_tx_buffer *first;
ebe42d16 4594 int tso;
91d4ee33 4595 u32 tx_flags = 0;
31f6adbb 4596 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4597 u8 hdr_len = 0;
9d5c8243 4598
9d5c8243
AK		 4599 /* need: 1 descriptor per page,
4600 * + 2 desc gap to keep tail from touching head,
4601 * + 1 desc for skb->data,
4602 * + 1 desc for context descriptor,
4603 * otherwise try next time */
e694e964 4604 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4605 /* this is a hard error */
9d5c8243
AK		 4606 return NETDEV_TX_BUSY;
4607 }
33af6bcc 4608
7af40ad9
AD		 4609 /* record the location of the first descriptor for this packet */
4610 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4611 first->skb = skb;
4612 first->bytecount = skb->len;
4613 first->gso_segs = 1;
4614
b66e2397
MV		 4615 skb_tx_timestamp(skb);
4616
1f6e8178
MV		 4617 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4618 !(adapter->ptp_tx_skb))) {
2244d07b 4619 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4620 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4621
4622 adapter->ptp_tx_skb = skb_get(skb);
428f1f71 4623 adapter->ptp_tx_start = jiffies;
1f6e8178
MV		 4624 if (adapter->hw.mac.type == e1000_82576)
4625 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4626 }
9d5c8243 4627
eab6d18d 4628 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4629 tx_flags |= IGB_TX_FLAGS_VLAN;
4630 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4631 }
4632
7af40ad9
AD		 4633 /* record initial flags and protocol */
4634 first->tx_flags = tx_flags;
4635 first->protocol = protocol;
cdfd01fc 4636
7af40ad9
AD		 4637 tso = igb_tso(tx_ring, first, &hdr_len);
4638 if (tso < 0)
7d13a7d0 4639 goto out_drop;
7af40ad9
AD		 4640 else if (!tso)
4641 igb_tx_csum(tx_ring, first);
9d5c8243 4642
7af40ad9 4643 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4644
4645 /* Make sure there is space in the ring for the next send. */
e694e964 4646 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4647
9d5c8243 4648 return NETDEV_TX_OK;
7d13a7d0
AD		 4649
4650out_drop:
7af40ad9
AD		 4651 igb_unmap_and_free_tx_resource(tx_ring, first);
4652
7d13a7d0 4653 return NETDEV_TX_OK;
9d5c8243
AK		 4654}
4655
1cc3bd87
AD		 4656static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4657 struct sk_buff *skb)
4658{
4659 unsigned int r_idx = skb->queue_mapping;
4660
4661 if (r_idx >= adapter->num_tx_queues)
4662 r_idx = r_idx % adapter->num_tx_queues;
4663
4664 return adapter->tx_ring[r_idx];
4665}
4666
cd392f5c
AD		 4667static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4668 struct net_device *netdev)
9d5c8243
AK		 4669{
4670 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4671
4672 if (test_bit(__IGB_DOWN, &adapter->state)) {
4673 dev_kfree_skb_any(skb);
4674 return NETDEV_TX_OK;
4675 }
4676
4677 if (skb->len <= 0) {
4678 dev_kfree_skb_any(skb);
4679 return NETDEV_TX_OK;
4680 }
4681
1cc3bd87
AD		 4682 /*
4683 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4684 * in order to meet this minimum size requirement.
4685 */
ea5ceeab
TD		 4686 if (unlikely(skb->len < 17)) {
4687 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4688 return NETDEV_TX_OK;
4689 skb->len = 17;
ea5ceeab 4690 skb_set_tail_pointer(skb, 17);
1cc3bd87 4691 }
9d5c8243 4692
1cc3bd87 4693 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4694}
4695
4696/**
4697 * igb_tx_timeout - Respond to a Tx Hang
4698 * @netdev: network interface device structure
4699 **/
4700static void igb_tx_timeout(struct net_device *netdev)
4701{
4702 struct igb_adapter *adapter = netdev_priv(netdev);
4703 struct e1000_hw *hw = &adapter->hw;
4704
4705 /* Do the reset outside of interrupt context */
4706 adapter->tx_timeout_count++;
f7ba205e 4707
06218a8d 4708 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4709 hw->dev_spec._82575.global_device_reset = true;
4710
9d5c8243 4711 schedule_work(&adapter->reset_task);
265de409
AD		 4712 wr32(E1000_EICS,
4713 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4714}
4715
4716static void igb_reset_task(struct work_struct *work)
4717{
4718 struct igb_adapter *adapter;
4719 adapter = container_of(work, struct igb_adapter, reset_task);
4720
c97ec42a
TI		 4721 igb_dump(adapter);
4722 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4723 igb_reinit_locked(adapter);
4724}
4725
4726/**
12dcd86b 4727 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4728 * @netdev: network interface device structure
12dcd86b 4729 * @stats: rtnl_link_stats64 pointer
9d5c8243 4730 *
9d5c8243 4731 **/
12dcd86b
ED		 4732static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4733 struct rtnl_link_stats64 *stats)
9d5c8243 4734{
12dcd86b
ED		 4735 struct igb_adapter *adapter = netdev_priv(netdev);
4736
4737 spin_lock(&adapter->stats64_lock);
4738 igb_update_stats(adapter, &adapter->stats64);
4739 memcpy(stats, &adapter->stats64, sizeof(*stats));
4740 spin_unlock(&adapter->stats64_lock);
4741
4742 return stats;
9d5c8243
AK		 4743}
4744
4745/**
4746 * igb_change_mtu - Change the Maximum Transfer Unit
4747 * @netdev: network interface device structure
4748 * @new_mtu: new value for maximum frame size
4749 *
4750 * Returns 0 on success, negative on failure
4751 **/
4752static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4753{
4754 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4755 struct pci_dev *pdev = adapter->pdev;
153285f9 4756 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4757
c809d227 4758 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4759 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4760 return -EINVAL;
4761 }
4762
153285f9 4763#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4764 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4765 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4766 return -EINVAL;
4767 }
4768
4769 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4770 msleep(1);
73cd78f1 4771
9d5c8243
AK		 4772 /* igb_down has a dependency on max_frame_size */
4773 adapter->max_frame_size = max_frame;
559e9c49 4774
4c844851
AD		 4775 if (netif_running(netdev))
4776 igb_down(adapter);
9d5c8243 4777
090b1795 4778 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4779 netdev->mtu, new_mtu);
4780 netdev->mtu = new_mtu;
4781
4782 if (netif_running(netdev))
4783 igb_up(adapter);
4784 else
4785 igb_reset(adapter);
4786
4787 clear_bit(__IGB_RESETTING, &adapter->state);
4788
4789 return 0;
4790}
4791
4792/**
4793 * igb_update_stats - Update the board statistics counters
4794 * @adapter: board private structure
4795 **/
4796
12dcd86b
ED		 4797void igb_update_stats(struct igb_adapter *adapter,
4798 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4799{
4800 struct e1000_hw *hw = &adapter->hw;
4801 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4802 u32 reg, mpc;
9d5c8243 4803 u16 phy_tmp;
3f9c0164
AD		 4804 int i;
4805 u64 bytes, packets;
12dcd86b
ED		 4806 unsigned int start;
4807 u64 _bytes, _packets;
9d5c8243
AK		 4808
4809#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4810
4811 /*
4812 * Prevent stats update while adapter is being reset, or if the pci
4813 * connection is down.
4814 */
4815 if (adapter->link_speed == 0)
4816 return;
4817 if (pci_channel_offline(pdev))
4818 return;
4819
3f9c0164
AD		 4820 bytes = 0;
4821 packets = 0;
4822 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4823 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4824 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4825
ae1c07a6
AD		 4826 if (rqdpc) {
4827 ring->rx_stats.drops += rqdpc;
4828 net_stats->rx_fifo_errors += rqdpc;
4829 }
12dcd86b
ED		 4830
4831 do {
4832 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4833 _bytes = ring->rx_stats.bytes;
4834 _packets = ring->rx_stats.packets;
4835 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4836 bytes += _bytes;
4837 packets += _packets;
3f9c0164
AD		 4838 }
4839
128e45eb
AD		 4840 net_stats->rx_bytes = bytes;
4841 net_stats->rx_packets = packets;
3f9c0164
AD		 4842
4843 bytes = 0;
4844 packets = 0;
4845 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4846 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4847 do {
4848 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4849 _bytes = ring->tx_stats.bytes;
4850 _packets = ring->tx_stats.packets;
4851 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4852 bytes += _bytes;
4853 packets += _packets;
3f9c0164 4854 }
128e45eb
AD		 4855 net_stats->tx_bytes = bytes;
4856 net_stats->tx_packets = packets;
3f9c0164
AD		 4857
4858 /* read stats registers */
9d5c8243
AK		 4859 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4860 adapter->stats.gprc += rd32(E1000_GPRC);
4861 adapter->stats.gorc += rd32(E1000_GORCL);
4862 rd32(E1000_GORCH); /* clear GORCL */
4863 adapter->stats.bprc += rd32(E1000_BPRC);
4864 adapter->stats.mprc += rd32(E1000_MPRC);
4865 adapter->stats.roc += rd32(E1000_ROC);
4866
4867 adapter->stats.prc64 += rd32(E1000_PRC64);
4868 adapter->stats.prc127 += rd32(E1000_PRC127);
4869 adapter->stats.prc255 += rd32(E1000_PRC255);
4870 adapter->stats.prc511 += rd32(E1000_PRC511);
4871 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4872 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4873 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4874 adapter->stats.sec += rd32(E1000_SEC);
4875
fa3d9a6d
MW		 4876 mpc = rd32(E1000_MPC);
4877 adapter->stats.mpc += mpc;
4878 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4879 adapter->stats.scc += rd32(E1000_SCC);
4880 adapter->stats.ecol += rd32(E1000_ECOL);
4881 adapter->stats.mcc += rd32(E1000_MCC);
4882 adapter->stats.latecol += rd32(E1000_LATECOL);
4883 adapter->stats.dc += rd32(E1000_DC);
4884 adapter->stats.rlec += rd32(E1000_RLEC);
4885 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4886 adapter->stats.xontxc += rd32(E1000_XONTXC);
4887 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4888 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4889 adapter->stats.fcruc += rd32(E1000_FCRUC);
4890 adapter->stats.gptc += rd32(E1000_GPTC);
4891 adapter->stats.gotc += rd32(E1000_GOTCL);
4892 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4893 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4894 adapter->stats.ruc += rd32(E1000_RUC);
4895 adapter->stats.rfc += rd32(E1000_RFC);
4896 adapter->stats.rjc += rd32(E1000_RJC);
4897 adapter->stats.tor += rd32(E1000_TORH);
4898 adapter->stats.tot += rd32(E1000_TOTH);
4899 adapter->stats.tpr += rd32(E1000_TPR);
4900
4901 adapter->stats.ptc64 += rd32(E1000_PTC64);
4902 adapter->stats.ptc127 += rd32(E1000_PTC127);
4903 adapter->stats.ptc255 += rd32(E1000_PTC255);
4904 adapter->stats.ptc511 += rd32(E1000_PTC511);
4905 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4906 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4907
4908 adapter->stats.mptc += rd32(E1000_MPTC);
4909 adapter->stats.bptc += rd32(E1000_BPTC);
4910
2d0b0f69
NN		 4911 adapter->stats.tpt += rd32(E1000_TPT);
4912 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4913
4914 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4915 /* read internal phy specific stats */
4916 reg = rd32(E1000_CTRL_EXT);
4917 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4918 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4919
4920 /* this stat has invalid values on i210/i211 */
4921 if ((hw->mac.type != e1000_i210) &&
4922 (hw->mac.type != e1000_i211))
4923 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4924 }
4925
9d5c8243
AK		 4926 adapter->stats.tsctc += rd32(E1000_TSCTC);
4927 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4928
4929 adapter->stats.iac += rd32(E1000_IAC);
4930 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4931 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4932 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4933 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4934 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4935 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4936 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4937 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4938
4939 /* Fill out the OS statistics structure */
128e45eb
AD		 4940 net_stats->multicast = adapter->stats.mprc;
4941 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4942
4943 /* Rx Errors */
4944
4945 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4946 * our own version based on RUC and ROC */
128e45eb 4947 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4948 adapter->stats.crcerrs + adapter->stats.algnerrc +
4949 adapter->stats.ruc + adapter->stats.roc +
4950 adapter->stats.cexterr;
128e45eb
AD		 4951 net_stats->rx_length_errors = adapter->stats.ruc +
4952 adapter->stats.roc;
4953 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4954 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4955 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4956
4957 /* Tx Errors */
128e45eb
AD		 4958 net_stats->tx_errors = adapter->stats.ecol +
4959 adapter->stats.latecol;
4960 net_stats->tx_aborted_errors = adapter->stats.ecol;
4961 net_stats->tx_window_errors = adapter->stats.latecol;
4962 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4963
4964 /* Tx Dropped needs to be maintained elsewhere */
4965
4966 /* Phy Stats */
4967 if (hw->phy.media_type == e1000_media_type_copper) {
4968 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4969 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4970 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4971 adapter->phy_stats.idle_errors += phy_tmp;
4972 }
4973 }
4974
4975 /* Management Stats */
4976 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4977 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4978 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4979
4980 /* OS2BMC Stats */
4981 reg = rd32(E1000_MANC);
4982 if (reg & E1000_MANC_EN_BMC2OS) {
4983 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4984 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4985 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4986 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4987 }
9d5c8243
AK		 4988}
4989
9d5c8243
AK		 4990static irqreturn_t igb_msix_other(int irq, void *data)
4991{
047e0030 4992 struct igb_adapter *adapter = data;
9d5c8243 4993 struct e1000_hw *hw = &adapter->hw;
844290e5 4994 u32 icr = rd32(E1000_ICR);
844290e5 4995 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4996
7f081d40
AD		 4997 if (icr & E1000_ICR_DRSTA)
4998 schedule_work(&adapter->reset_task);
4999
047e0030 5000 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5001 /* HW is reporting DMA is out of sync */
5002 adapter->stats.doosync++;
13800469
GR		 5003 /* The DMA Out of Sync is also indication of a spoof event
5004 * in IOV mode. Check the Wrong VM Behavior register to
5005 * see if it is really a spoof event. */
5006 igb_check_wvbr(adapter);
dda0e083 5007 }
eebbbdba 5008
4ae196df
AD		 5009 /* Check for a mailbox event */
5010 if (icr & E1000_ICR_VMMB)
5011 igb_msg_task(adapter);
5012
5013 if (icr & E1000_ICR_LSC) {
5014 hw->mac.get_link_status = 1;
5015 /* guard against interrupt when we're going down */
5016 if (!test_bit(__IGB_DOWN, &adapter->state))
5017 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5018 }
5019
1f6e8178
MV		 5020 if (icr & E1000_ICR_TS) {
5021 u32 tsicr = rd32(E1000_TSICR);
5022
5023 if (tsicr & E1000_TSICR_TXTS) {
5024 /* acknowledge the interrupt */
5025 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5026 /* retrieve hardware timestamp */
5027 schedule_work(&adapter->ptp_tx_work);
5028 }
5029 }
1f6e8178 5030
844290e5 5031 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5032
5033 return IRQ_HANDLED;
5034}
5035
047e0030 5036static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5037{
26b39276 5038 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5039 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5040
047e0030
AD		 5041 if (!q_vector->set_itr)
5042 return;
73cd78f1 5043
047e0030
AD		 5044 if (!itr_val)
5045 itr_val = 0x4;
661086df 5046
26b39276
AD		 5047 if (adapter->hw.mac.type == e1000_82575)
5048 itr_val |= itr_val << 16;
661086df 5049 else
0ba82994 5050 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5051
047e0030
AD		 5052 writel(itr_val, q_vector->itr_register);
5053 q_vector->set_itr = 0;
6eb5a7f1
AD		 5054}
5055
047e0030 5056static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5057{
047e0030 5058 struct igb_q_vector *q_vector = data;
9d5c8243 5059
047e0030
AD		 5060 /* Write the ITR value calculated from the previous interrupt. */
5061 igb_write_itr(q_vector);
9d5c8243 5062
047e0030 5063 napi_schedule(&q_vector->napi);
844290e5 5064
047e0030 5065 return IRQ_HANDLED;
fe4506b6
JC		 5066}
5067
421e02f0 5068#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5069static void igb_update_tx_dca(struct igb_adapter *adapter,
5070 struct igb_ring *tx_ring,
5071 int cpu)
5072{
5073 struct e1000_hw *hw = &adapter->hw;
5074 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5075
5076 if (hw->mac.type != e1000_82575)
5077 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5078
5079 /*
5080 * We can enable relaxed ordering for reads, but not writes when
5081 * DCA is enabled. This is due to a known issue in some chipsets
5082 * which will cause the DCA tag to be cleared.
5083 */
5084 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5085 E1000_DCA_TXCTRL_DATA_RRO_EN |
5086 E1000_DCA_TXCTRL_DESC_DCA_EN;
5087
5088 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5089}
5090
5091static void igb_update_rx_dca(struct igb_adapter *adapter,
5092 struct igb_ring *rx_ring,
5093 int cpu)
5094{
5095 struct e1000_hw *hw = &adapter->hw;
5096 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5097
5098 if (hw->mac.type != e1000_82575)
5099 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5100
5101 /*
5102 * We can enable relaxed ordering for reads, but not writes when
5103 * DCA is enabled. This is due to a known issue in some chipsets
5104 * which will cause the DCA tag to be cleared.
5105 */
5106 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5107 E1000_DCA_RXCTRL_DESC_DCA_EN;
5108
5109 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5110}
5111
047e0030 5112static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5113{
047e0030 5114 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5115 int cpu = get_cpu();
fe4506b6 5116
047e0030
AD		 5117 if (q_vector->cpu == cpu)
5118 goto out_no_update;
5119
6a05004a
AD		 5120 if (q_vector->tx.ring)
5121 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5122
5123 if (q_vector->rx.ring)
5124 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5125
047e0030
AD		 5126 q_vector->cpu = cpu;
5127out_no_update:
fe4506b6
JC		 5128 put_cpu();
5129}
5130
5131static void igb_setup_dca(struct igb_adapter *adapter)
5132{
7e0e99ef 5133 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5134 int i;
5135
7dfc16fa 5136 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5137 return;
5138
7e0e99ef
AD		 5139 /* Always use CB2 mode, difference is masked in the CB driver. */
5140 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5141
047e0030 5142 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5143 adapter->q_vector[i]->cpu = -1;
5144 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5145 }
5146}
5147
5148static int __igb_notify_dca(struct device *dev, void *data)
5149{
5150 struct net_device *netdev = dev_get_drvdata(dev);
5151 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5152 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5153 struct e1000_hw *hw = &adapter->hw;
5154 unsigned long event = *(unsigned long *)data;
5155
5156 switch (event) {
5157 case DCA_PROVIDER_ADD:
5158 /* if already enabled, don't do it again */
7dfc16fa 5159 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5160 break;
fe4506b6 5161 if (dca_add_requester(dev) == 0) {
bbd98fe4 5162 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5163 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5164 igb_setup_dca(adapter);
5165 break;
5166 }
5167 /* Fall Through since DCA is disabled. */
5168 case DCA_PROVIDER_REMOVE:
7dfc16fa 5169 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5170 /* without this a class_device is left
047e0030 5171 * hanging around in the sysfs model */
fe4506b6 5172 dca_remove_requester(dev);
090b1795 5173 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5174 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5175 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5176 }
5177 break;
5178 }
bbd98fe4 5179
fe4506b6 5180 return 0;
9d5c8243
AK		 5181}
5182
fe4506b6
JC		 5183static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5184 void *p)
5185{
5186 int ret_val;
5187
5188 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5189 __igb_notify_dca);
5190
5191 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5192}
421e02f0 5193#endif /* CONFIG_IGB_DCA */
9d5c8243 5194
0224d663
GR		 5195#ifdef CONFIG_PCI_IOV
5196static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5197{
5198 unsigned char mac_addr[ETH_ALEN];
0224d663 5199
7efd26d0 5200 eth_random_addr(mac_addr);
0224d663
GR		 5201 igb_set_vf_mac(adapter, vf, mac_addr);
5202
f557147c 5203 return 0;
0224d663
GR		 5204}
5205
f557147c 5206static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 5207{
0224d663 5208 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 5209 struct pci_dev *vfdev;
5210 int dev_id;
0224d663
GR		 5211
5212 switch (adapter->hw.mac.type) {
5213 case e1000_82576:
f557147c 5214 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 5215 break;
5216 case e1000_i350:
f557147c 5217 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 5218 break;
5219 default:
f557147c 5220 return false;
0224d663
GR		 5221 }
5222
f557147c
SA		 5223 /* loop through all the VFs to see if we own any that are assigned */
5224 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5225 while (vfdev) {
5226 /* if we don't own it we don't care */
5227 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5228 /* if it is assigned we cannot release it */
5229 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5230 return true;
5231 }
f557147c
SA		 5232
5233 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5234 }
f557147c 5235
0224d663
GR		 5236 return false;
5237}
5238
5239#endif
4ae196df
AD		 5240static void igb_ping_all_vfs(struct igb_adapter *adapter)
5241{
5242 struct e1000_hw *hw = &adapter->hw;
5243 u32 ping;
5244 int i;
5245
5246 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5247 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5248 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5249 ping |= E1000_VT_MSGTYPE_CTS;
5250 igb_write_mbx(hw, &ping, 1, i);
5251 }
5252}
5253
7d5753f0
AD		 5254static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5255{
5256 struct e1000_hw *hw = &adapter->hw;
5257 u32 vmolr = rd32(E1000_VMOLR(vf));
5258 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5259
d85b9004 5260 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5261 IGB_VF_FLAG_MULTI_PROMISC);
5262 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5263
5264 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5265 vmolr |= E1000_VMOLR_MPME;
d85b9004 5266 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5267 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5268 } else {
5269 /*
5270 * if we have hashes and we are clearing a multicast promisc
5271 * flag we need to write the hashes to the MTA as this step
5272 * was previously skipped
5273 */
5274 if (vf_data->num_vf_mc_hashes > 30) {
5275 vmolr |= E1000_VMOLR_MPME;
5276 } else if (vf_data->num_vf_mc_hashes) {
5277 int j;
5278 vmolr |= E1000_VMOLR_ROMPE;
5279 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5280 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5281 }
5282 }
5283
5284 wr32(E1000_VMOLR(vf), vmolr);
5285
5286 /* there are flags left unprocessed, likely not supported */
5287 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5288 return -EINVAL;
5289
5290 return 0;
5291
5292}
5293
4ae196df
AD		 5294static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5295 u32 *msgbuf, u32 vf)
5296{
5297 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5298 u16 *hash_list = (u16 *)&msgbuf[1];
5299 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5300 int i;
5301
7d5753f0 5302 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5303 * to this VF for later use to restore when the PF multi cast
5304 * list changes
5305 */
5306 vf_data->num_vf_mc_hashes = n;
5307
7d5753f0
AD		 5308 /* only up to 30 hash values supported */
5309 if (n > 30)
5310 n = 30;
5311
5312 /* store the hashes for later use */
4ae196df 5313 for (i = 0; i < n; i++)
a419aef8 5314 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5315
5316 /* Flush and reset the mta with the new values */
ff41f8dc 5317 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5318
5319 return 0;
5320}
5321
5322static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5323{
5324 struct e1000_hw *hw = &adapter->hw;
5325 struct vf_data_storage *vf_data;
5326 int i, j;
5327
5328 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5329 u32 vmolr = rd32(E1000_VMOLR(i));
5330 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5331
4ae196df 5332 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5333
5334 if ((vf_data->num_vf_mc_hashes > 30) ||
5335 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5336 vmolr |= E1000_VMOLR_MPME;
5337 } else if (vf_data->num_vf_mc_hashes) {
5338 vmolr |= E1000_VMOLR_ROMPE;
5339 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5340 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5341 }
5342 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5343 }
5344}
5345
5346static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5347{
5348 struct e1000_hw *hw = &adapter->hw;
5349 u32 pool_mask, reg, vid;
5350 int i;
5351
5352 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5353
5354 /* Find the vlan filter for this id */
5355 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5356 reg = rd32(E1000_VLVF(i));
5357
5358 /* remove the vf from the pool */
5359 reg &= ~pool_mask;
5360
5361 /* if pool is empty then remove entry from vfta */
5362 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5363 (reg & E1000_VLVF_VLANID_ENABLE)) {
5364 reg = 0;
5365 vid = reg & E1000_VLVF_VLANID_MASK;
5366 igb_vfta_set(hw, vid, false);
5367 }
5368
5369 wr32(E1000_VLVF(i), reg);
5370 }
ae641bdc
AD		 5371
5372 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5373}
5374
5375static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5376{
5377 struct e1000_hw *hw = &adapter->hw;
5378 u32 reg, i;
5379
51466239
AD		 5380 /* The vlvf table only exists on 82576 hardware and newer */
5381 if (hw->mac.type < e1000_82576)
5382 return -1;
5383
5384 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5385 if (!adapter->vfs_allocated_count)
5386 return -1;
5387
5388 /* Find the vlan filter for this id */
5389 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5390 reg = rd32(E1000_VLVF(i));
5391 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5392 vid == (reg & E1000_VLVF_VLANID_MASK))
5393 break;
5394 }
5395
5396 if (add) {
5397 if (i == E1000_VLVF_ARRAY_SIZE) {
5398 /* Did not find a matching VLAN ID entry that was
5399 * enabled. Search for a free filter entry, i.e.
5400 * one without the enable bit set
5401 */
5402 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5403 reg = rd32(E1000_VLVF(i));
5404 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5405 break;
5406 }
5407 }
5408 if (i < E1000_VLVF_ARRAY_SIZE) {
5409 /* Found an enabled/available entry */
5410 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5411
5412 /* if !enabled we need to set this up in vfta */
5413 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5414 /* add VID to filter table */
5415 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5416 reg |= E1000_VLVF_VLANID_ENABLE;
5417 }
cad6d05f
AD		 5418 reg &= ~E1000_VLVF_VLANID_MASK;
5419 reg |= vid;
4ae196df 5420 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5421
5422 /* do not modify RLPML for PF devices */
5423 if (vf >= adapter->vfs_allocated_count)
5424 return 0;
5425
5426 if (!adapter->vf_data[vf].vlans_enabled) {
5427 u32 size;
5428 reg = rd32(E1000_VMOLR(vf));
5429 size = reg & E1000_VMOLR_RLPML_MASK;
5430 size += 4;
5431 reg &= ~E1000_VMOLR_RLPML_MASK;
5432 reg |= size;
5433 wr32(E1000_VMOLR(vf), reg);
5434 }
ae641bdc 5435
51466239 5436 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5437 }
5438 } else {
5439 if (i < E1000_VLVF_ARRAY_SIZE) {
5440 /* remove vf from the pool */
5441 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5442 /* if pool is empty then remove entry from vfta */
5443 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5444 reg = 0;
5445 igb_vfta_set(hw, vid, false);
5446 }
5447 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5448
5449 /* do not modify RLPML for PF devices */
5450 if (vf >= adapter->vfs_allocated_count)
5451 return 0;
5452
5453 adapter->vf_data[vf].vlans_enabled--;
5454 if (!adapter->vf_data[vf].vlans_enabled) {
5455 u32 size;
5456 reg = rd32(E1000_VMOLR(vf));
5457 size = reg & E1000_VMOLR_RLPML_MASK;
5458 size -= 4;
5459 reg &= ~E1000_VMOLR_RLPML_MASK;
5460 reg |= size;
5461 wr32(E1000_VMOLR(vf), reg);
5462 }
4ae196df
AD		 5463 }
5464 }
8151d294
WM		 5465 return 0;
5466}
5467
5468static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5469{
5470 struct e1000_hw *hw = &adapter->hw;
5471
5472 if (vid)
5473 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5474 else
5475 wr32(E1000_VMVIR(vf), 0);
5476}
5477
5478static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5479 int vf, u16 vlan, u8 qos)
5480{
5481 int err = 0;
5482 struct igb_adapter *adapter = netdev_priv(netdev);
5483
5484 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5485 return -EINVAL;
5486 if (vlan || qos) {
5487 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5488 if (err)
5489 goto out;
5490 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5491 igb_set_vmolr(adapter, vf, !vlan);
5492 adapter->vf_data[vf].pf_vlan = vlan;
5493 adapter->vf_data[vf].pf_qos = qos;
5494 dev_info(&adapter->pdev->dev,
5495 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5496 if (test_bit(__IGB_DOWN, &adapter->state)) {
5497 dev_warn(&adapter->pdev->dev,
5498 "The VF VLAN has been set,"
5499 " but the PF device is not up.\n");
5500 dev_warn(&adapter->pdev->dev,
5501 "Bring the PF device up before"
5502 " attempting to use the VF device.\n");
5503 }
5504 } else {
5505 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5506 false, vf);
5507 igb_set_vmvir(adapter, vlan, vf);
5508 igb_set_vmolr(adapter, vf, true);
5509 adapter->vf_data[vf].pf_vlan = 0;
5510 adapter->vf_data[vf].pf_qos = 0;
5511 }
5512out:
5513 return err;
4ae196df
AD		 5514}
5515
5516static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5517{
5518 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5519 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5520
5521 return igb_vlvf_set(adapter, vid, add, vf);
5522}
5523
f2ca0dbe 5524static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5525{
8fa7e0f7
GR		 5526 /* clear flags - except flag that indicates PF has set the MAC */
5527 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5528 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5529
5530 /* reset offloads to defaults */
8151d294 5531 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5532
5533 /* reset vlans for device */
5534 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5535 if (adapter->vf_data[vf].pf_vlan)
5536 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5537 adapter->vf_data[vf].pf_vlan,
5538 adapter->vf_data[vf].pf_qos);
5539 else
5540 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5541
5542 /* reset multicast table array for vf */
5543 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5544
5545 /* Flush and reset the mta with the new values */
ff41f8dc 5546 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5547}
5548
f2ca0dbe
AD		 5549static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5550{
5551 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5552
5553 /* generate a new mac address as we were hotplug removed/added */
8151d294 5554 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5555 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5556
5557 /* process remaining reset events */
5558 igb_vf_reset(adapter, vf);
5559}
5560
5561static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5562{
5563 struct e1000_hw *hw = &adapter->hw;
5564 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5565 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5566 u32 reg, msgbuf[3];
5567 u8 *addr = (u8 *)(&msgbuf[1]);
5568
5569 /* process all the same items cleared in a function level reset */
f2ca0dbe 5570 igb_vf_reset(adapter, vf);
4ae196df
AD		 5571
5572 /* set vf mac address */
26ad9178 5573 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5574
5575 /* enable transmit and receive for vf */
5576 reg = rd32(E1000_VFTE);
5577 wr32(E1000_VFTE, reg | (1 << vf));
5578 reg = rd32(E1000_VFRE);
5579 wr32(E1000_VFRE, reg | (1 << vf));
5580
8fa7e0f7 5581 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5582
5583 /* reply to reset with ack and vf mac address */
5584 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5585 memcpy(addr, vf_mac, 6);
5586 igb_write_mbx(hw, msgbuf, 3, vf);
5587}
5588
5589static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5590{
de42edde
GR		 5591 /*
5592 * The VF MAC Address is stored in a packed array of bytes
5593 * starting at the second 32 bit word of the msg array
5594 */
f2ca0dbe
AD		 5595 unsigned char *addr = (char *)&msg[1];
5596 int err = -1;
4ae196df 5597
f2ca0dbe
AD		 5598 if (is_valid_ether_addr(addr))
5599 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5600
f2ca0dbe 5601 return err;
4ae196df
AD		 5602}
5603
5604static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5605{
5606 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5607 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5608 u32 msg = E1000_VT_MSGTYPE_NACK;
5609
5610 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5611 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5612 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5613 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5614 vf_data->last_nack = jiffies;
4ae196df
AD		 5615 }
5616}
5617
f2ca0dbe 5618static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5619{
f2ca0dbe
AD		 5620 struct pci_dev *pdev = adapter->pdev;
5621 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5622 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5623 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5624 s32 retval;
5625
f2ca0dbe 5626 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5627
fef45f4c
AD		 5628 if (retval) {
5629 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5630 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5631 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5632 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5633 return;
5634 goto out;
5635 }
4ae196df
AD		 5636
5637 /* this is a message we already processed, do nothing */
5638 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5639 return;
4ae196df
AD		 5640
5641 /*
5642 * until the vf completes a reset it should not be
5643 * allowed to start any configuration.
5644 */
5645
5646 if (msgbuf[0] == E1000_VF_RESET) {
5647 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5648 return;
4ae196df
AD		 5649 }
5650
f2ca0dbe 5651 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5652 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5653 return;
5654 retval = -1;
5655 goto out;
4ae196df
AD		 5656 }
5657
5658 switch ((msgbuf[0] & 0xFFFF)) {
5659 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5660 retval = -EINVAL;
5661 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5662 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5663 else
5664 dev_warn(&pdev->dev,
5665 "VF %d attempted to override administratively "
5666 "set MAC address\nReload the VF driver to "
5667 "resume operations\n", vf);
4ae196df 5668 break;
7d5753f0
AD		 5669 case E1000_VF_SET_PROMISC:
5670 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5671 break;
4ae196df
AD		 5672 case E1000_VF_SET_MULTICAST:
5673 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5674 break;
5675 case E1000_VF_SET_LPE:
5676 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5677 break;
5678 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5679 retval = -1;
5680 if (vf_data->pf_vlan)
5681 dev_warn(&pdev->dev,
5682 "VF %d attempted to override administratively "
5683 "set VLAN tag\nReload the VF driver to "
5684 "resume operations\n", vf);
8151d294
WM		 5685 else
5686 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5687 break;
5688 default:
090b1795 5689 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5690 retval = -1;
5691 break;
5692 }
5693
fef45f4c
AD		 5694 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5695out:
4ae196df
AD		 5696 /* notify the VF of the results of what it sent us */
5697 if (retval)
5698 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5699 else
5700 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5701
4ae196df 5702 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5703}
4ae196df 5704
f2ca0dbe
AD		 5705static void igb_msg_task(struct igb_adapter *adapter)
5706{
5707 struct e1000_hw *hw = &adapter->hw;
5708 u32 vf;
5709
5710 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5711 /* process any reset requests */
5712 if (!igb_check_for_rst(hw, vf))
5713 igb_vf_reset_event(adapter, vf);
5714
5715 /* process any messages pending */
5716 if (!igb_check_for_msg(hw, vf))
5717 igb_rcv_msg_from_vf(adapter, vf);
5718
5719 /* process any acks */
5720 if (!igb_check_for_ack(hw, vf))
5721 igb_rcv_ack_from_vf(adapter, vf);
5722 }
4ae196df
AD		 5723}
5724
68d480c4
AD		 5725/**
5726 * igb_set_uta - Set unicast filter table address
5727 * @adapter: board private structure
5728 *
5729 * The unicast table address is a register array of 32-bit registers.
5730 * The table is meant to be used in a way similar to how the MTA is used
5731 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5732 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5733 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5734 **/
5735static void igb_set_uta(struct igb_adapter *adapter)
5736{
5737 struct e1000_hw *hw = &adapter->hw;
5738 int i;
5739
5740 /* The UTA table only exists on 82576 hardware and newer */
5741 if (hw->mac.type < e1000_82576)
5742 return;
5743
5744 /* we only need to do this if VMDq is enabled */
5745 if (!adapter->vfs_allocated_count)
5746 return;
5747
5748 for (i = 0; i < hw->mac.uta_reg_count; i++)
5749 array_wr32(E1000_UTA, i, ~0);
5750}
5751
9d5c8243
AK		 5752/**
5753 * igb_intr_msi - Interrupt Handler
5754 * @irq: interrupt number
5755 * @data: pointer to a network interface device structure
5756 **/
5757static irqreturn_t igb_intr_msi(int irq, void *data)
5758{
047e0030
AD		 5759 struct igb_adapter *adapter = data;
5760 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5761 struct e1000_hw *hw = &adapter->hw;
5762 /* read ICR disables interrupts using IAM */
5763 u32 icr = rd32(E1000_ICR);
5764
047e0030 5765 igb_write_itr(q_vector);
9d5c8243 5766
7f081d40
AD		 5767 if (icr & E1000_ICR_DRSTA)
5768 schedule_work(&adapter->reset_task);
5769
047e0030 5770 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5771 /* HW is reporting DMA is out of sync */
5772 adapter->stats.doosync++;
5773 }
5774
9d5c8243
AK		 5775 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5776 hw->mac.get_link_status = 1;
5777 if (!test_bit(__IGB_DOWN, &adapter->state))
5778 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5779 }
5780
1f6e8178
MV		 5781 if (icr & E1000_ICR_TS) {
5782 u32 tsicr = rd32(E1000_TSICR);
5783
5784 if (tsicr & E1000_TSICR_TXTS) {
5785 /* acknowledge the interrupt */
5786 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5787 /* retrieve hardware timestamp */
5788 schedule_work(&adapter->ptp_tx_work);
5789 }
5790 }
1f6e8178 5791
047e0030 5792 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5793
5794 return IRQ_HANDLED;
5795}
5796
5797/**
4a3c6433 5798 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5799 * @irq: interrupt number
5800 * @data: pointer to a network interface device structure
5801 **/
5802static irqreturn_t igb_intr(int irq, void *data)
5803{
047e0030
AD		 5804 struct igb_adapter *adapter = data;
5805 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5806 struct e1000_hw *hw = &adapter->hw;
5807 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5808 * need for the IMC write */
5809 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5810
5811 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5812 * not set, then the adapter didn't send an interrupt */
5813 if (!(icr & E1000_ICR_INT_ASSERTED))
5814 return IRQ_NONE;
5815
0ba82994
AD		 5816 igb_write_itr(q_vector);
5817
7f081d40
AD		 5818 if (icr & E1000_ICR_DRSTA)
5819 schedule_work(&adapter->reset_task);
5820
047e0030 5821 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5822 /* HW is reporting DMA is out of sync */
5823 adapter->stats.doosync++;
5824 }
5825
9d5c8243
AK		 5826 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5827 hw->mac.get_link_status = 1;
5828 /* guard against interrupt when we're going down */
5829 if (!test_bit(__IGB_DOWN, &adapter->state))
5830 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5831 }
5832
1f6e8178
MV		 5833 if (icr & E1000_ICR_TS) {
5834 u32 tsicr = rd32(E1000_TSICR);
5835
5836 if (tsicr & E1000_TSICR_TXTS) {
5837 /* acknowledge the interrupt */
5838 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5839 /* retrieve hardware timestamp */
5840 schedule_work(&adapter->ptp_tx_work);
5841 }
5842 }
1f6e8178 5843
047e0030 5844 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5845
5846 return IRQ_HANDLED;
5847}
5848
c50b52a0 5849static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5850{
047e0030 5851 struct igb_adapter *adapter = q_vector->adapter;
46544258 5852 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5853
0ba82994
AD		 5854 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5855 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5856 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5857 igb_set_itr(q_vector);
46544258 5858 else
047e0030 5859 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5860 }
5861
46544258
AD		 5862 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5863 if (adapter->msix_entries)
047e0030 5864 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5865 else
5866 igb_irq_enable(adapter);
5867 }
9d5c8243
AK		 5868}
5869
46544258
AD		 5870/**
5871 * igb_poll - NAPI Rx polling callback
5872 * @napi: napi polling structure
5873 * @budget: count of how many packets we should handle
5874 **/
5875static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5876{
047e0030
AD		 5877 struct igb_q_vector *q_vector = container_of(napi,
5878 struct igb_q_vector,
5879 napi);
16eb8815 5880 bool clean_complete = true;
9d5c8243 5881
421e02f0 5882#ifdef CONFIG_IGB_DCA
047e0030
AD		 5883 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5884 igb_update_dca(q_vector);
fe4506b6 5885#endif
0ba82994 5886 if (q_vector->tx.ring)
13fde97a 5887 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5888
0ba82994 5889 if (q_vector->rx.ring)
cd392f5c 5890 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5891
16eb8815
AD		 5892 /* If all work not completed, return budget and keep polling */
5893 if (!clean_complete)
5894 return budget;
46544258 5895
9d5c8243 5896 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5897 napi_complete(napi);
5898 igb_ring_irq_enable(q_vector);
9d5c8243 5899
16eb8815 5900 return 0;
9d5c8243 5901}
6d8126f9 5902
9d5c8243
AK		 5903/**
5904 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5905 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5906 *
9d5c8243
AK		 5907 * returns true if ring is completely cleaned
5908 **/
047e0030 5909static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5910{
047e0030 5911 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5912 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5913 struct igb_tx_buffer *tx_buffer;
f4128785 5914 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5915 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5916 unsigned int budget = q_vector->tx.work_limit;
8542db05 5917 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5918
13fde97a
AD		 5919 if (test_bit(__IGB_DOWN, &adapter->state))
5920 return true;
0e014cb1 5921
06034649 5922 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5923 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5924 i -= tx_ring->count;
9d5c8243 5925
f4128785
AD		 5926 do {
5927 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5928
5929 /* if next_to_watch is not set then there is no work pending */
5930 if (!eop_desc)
5931 break;
13fde97a 5932
f4128785 5933 /* prevent any other reads prior to eop_desc */
70d289bc 5934 read_barrier_depends();
f4128785 5935
13fde97a
AD		 5936 /* if DD is not set pending work has not been completed */
5937 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5938 break;
5939
8542db05
AD		 5940 /* clear next_to_watch to prevent false hangs */
5941 tx_buffer->next_to_watch = NULL;
9d5c8243 5942
ebe42d16
AD		 5943 /* update the statistics for this packet */
5944 total_bytes += tx_buffer->bytecount;
5945 total_packets += tx_buffer->gso_segs;
13fde97a 5946
ebe42d16
AD		 5947 /* free the skb */
5948 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5949
ebe42d16
AD		 5950 /* unmap skb header data */
5951 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5952 dma_unmap_addr(tx_buffer, dma),
5953 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5954 DMA_TO_DEVICE);
5955
c9f14bf3
AD		 5956 /* clear tx_buffer data */
5957 tx_buffer->skb = NULL;
5958 dma_unmap_len_set(tx_buffer, len, 0);
5959
ebe42d16
AD		 5960 /* clear last DMA location and unmap remaining buffers */
5961 while (tx_desc != eop_desc) {
13fde97a
AD		 5962 tx_buffer++;
5963 tx_desc++;
9d5c8243 5964 i++;
8542db05
AD		 5965 if (unlikely(!i)) {
5966 i -= tx_ring->count;
06034649 5967 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5968 tx_desc = IGB_TX_DESC(tx_ring, 0);
5969 }
ebe42d16
AD		 5970
5971 /* unmap any remaining paged data */
c9f14bf3 5972 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5973 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5974 dma_unmap_addr(tx_buffer, dma),
5975 dma_unmap_len(tx_buffer, len),
ebe42d16 5976 DMA_TO_DEVICE);
c9f14bf3 5977 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5978 }
5979 }
5980
ebe42d16
AD		 5981 /* move us one more past the eop_desc for start of next pkt */
5982 tx_buffer++;
5983 tx_desc++;
5984 i++;
5985 if (unlikely(!i)) {
5986 i -= tx_ring->count;
5987 tx_buffer = tx_ring->tx_buffer_info;
5988 tx_desc = IGB_TX_DESC(tx_ring, 0);
5989 }
f4128785
AD		 5990
5991 /* issue prefetch for next Tx descriptor */
5992 prefetch(tx_desc);
5993
5994 /* update budget accounting */
5995 budget--;
5996 } while (likely(budget));
0e014cb1 5997
bdbc0631
ED		 5998 netdev_tx_completed_queue(txring_txq(tx_ring),
5999 total_packets, total_bytes);
8542db05 6000 i += tx_ring->count;
9d5c8243 6001 tx_ring->next_to_clean = i;
13fde97a
AD		 6002 u64_stats_update_begin(&tx_ring->tx_syncp);
6003 tx_ring->tx_stats.bytes += total_bytes;
6004 tx_ring->tx_stats.packets += total_packets;
6005 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6006 q_vector->tx.total_bytes += total_bytes;
6007 q_vector->tx.total_packets += total_packets;
9d5c8243 6008
6d095fa8 6009 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6010 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6011
9d5c8243
AK		 6012 /* Detect a transmit hang in hardware, this serializes the
6013 * check with the clearing of time_stamp and movement of i */
6d095fa8 6014 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6015 if (tx_buffer->next_to_watch &&
8542db05 6016 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6017 (adapter->tx_timeout_factor * HZ)) &&
6018 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6019
9d5c8243 6020 /* detected Tx unit hang */
59d71989 6021 dev_err(tx_ring->dev,
9d5c8243 6022 "Detected Tx Unit Hang\n"
2d064c06 6023 " Tx Queue <%d>\n"
9d5c8243
AK		 6024 " TDH <%x>\n"
6025 " TDT <%x>\n"
6026 " next_to_use <%x>\n"
6027 " next_to_clean <%x>\n"
9d5c8243
AK		 6028 "buffer_info[next_to_clean]\n"
6029 " time_stamp <%lx>\n"
8542db05 6030 " next_to_watch <%p>\n"
9d5c8243
AK		 6031 " jiffies <%lx>\n"
6032 " desc.status <%x>\n",
2d064c06 6033 tx_ring->queue_index,
238ac817 6034 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6035 readl(tx_ring->tail),
9d5c8243
AK		 6036 tx_ring->next_to_use,
6037 tx_ring->next_to_clean,
8542db05 6038 tx_buffer->time_stamp,
f4128785 6039 tx_buffer->next_to_watch,
9d5c8243 6040 jiffies,
f4128785 6041 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6042 netif_stop_subqueue(tx_ring->netdev,
6043 tx_ring->queue_index);
6044
6045 /* we are about to reset, no point in enabling stuff */
6046 return true;
9d5c8243
AK		 6047 }
6048 }
13fde97a
AD		 6049
6050 if (unlikely(total_packets &&
6051 netif_carrier_ok(tx_ring->netdev) &&
6052 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
6053 /* Make sure that anybody stopping the queue after this
6054 * sees the new next_to_clean.
6055 */
6056 smp_mb();
6057 if (__netif_subqueue_stopped(tx_ring->netdev,
6058 tx_ring->queue_index) &&
6059 !(test_bit(__IGB_DOWN, &adapter->state))) {
6060 netif_wake_subqueue(tx_ring->netdev,
6061 tx_ring->queue_index);
6062
6063 u64_stats_update_begin(&tx_ring->tx_syncp);
6064 tx_ring->tx_stats.restart_queue++;
6065 u64_stats_update_end(&tx_ring->tx_syncp);
6066 }
6067 }
6068
6069 return !!budget;
9d5c8243
AK		 6070}
6071
cbc8e55f
AD		 6072/**
6073 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6074 * @rx_ring: rx descriptor ring to store buffers on
6075 * @old_buff: donor buffer to have page reused
6076 *
6077 * Synchronizes page for reuse by the adapter
6078 **/
6079static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6080 struct igb_rx_buffer *old_buff)
6081{
6082 struct igb_rx_buffer *new_buff;
6083 u16 nta = rx_ring->next_to_alloc;
6084
6085 new_buff = &rx_ring->rx_buffer_info[nta];
6086
6087 /* update, and store next to alloc */
6088 nta++;
6089 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6090
6091 /* transfer page from old buffer to new buffer */
6092 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6093
6094 /* sync the buffer for use by the device */
6095 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6096 old_buff->page_offset,
de78d1f9 6097 IGB_RX_BUFSZ,
cbc8e55f
AD		 6098 DMA_FROM_DEVICE);
6099}
6100
6101/**
6102 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6103 * @rx_ring: rx descriptor ring to transact packets on
6104 * @rx_buffer: buffer containing page to add
6105 * @rx_desc: descriptor containing length of buffer written by hardware
6106 * @skb: sk_buff to place the data into
6107 *
6108 * This function will add the data contained in rx_buffer->page to the skb.
6109 * This is done either through a direct copy if the data in the buffer is
6110 * less than the skb header size, otherwise it will just attach the page as
6111 * a frag to the skb.
6112 *
6113 * The function will then update the page offset if necessary and return
6114 * true if the buffer can be reused by the adapter.
6115 **/
6116static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6117 struct igb_rx_buffer *rx_buffer,
6118 union e1000_adv_rx_desc *rx_desc,
6119 struct sk_buff *skb)
6120{
6121 struct page *page = rx_buffer->page;
6122 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6123
6124 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6125 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6126
cbc8e55f
AD		 6127 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6128 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6129 va += IGB_TS_HDR_LEN;
6130 size -= IGB_TS_HDR_LEN;
6131 }
6132
cbc8e55f
AD		 6133 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6134
6135 /* we can reuse buffer as-is, just make sure it is local */
6136 if (likely(page_to_nid(page) == numa_node_id()))
6137 return true;
6138
6139 /* this page cannot be reused so discard it */
6140 put_page(page);
6141 return false;
6142 }
6143
6144 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 6145 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 6146
6147 /* avoid re-using remote pages */
6148 if (unlikely(page_to_nid(page) != numa_node_id()))
6149 return false;
6150
de78d1f9 6151#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 6152 /* if we are only owner of page we can reuse it */
6153 if (unlikely(page_count(page) != 1))
6154 return false;
6155
6156 /* flip page offset to other buffer */
de78d1f9 6157 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 6158
6159 /*
6160 * since we are the only owner of the page and we need to
6161 * increment it, just set the value to 2 in order to avoid
6162 * an unnecessary locked operation
6163 */
6164 atomic_set(&page->_count, 2);
de78d1f9
AD		 6165#else
6166 /* move offset up to the next cache line */
6167 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
6168
6169 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6170 return false;
6171
6172 /* bump ref count on page before it is given to the stack */
6173 get_page(page);
6174#endif
cbc8e55f
AD		 6175
6176 return true;
6177}
6178
2e334eee
AD		 6179static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6180 union e1000_adv_rx_desc *rx_desc,
6181 struct sk_buff *skb)
6182{
6183 struct igb_rx_buffer *rx_buffer;
6184 struct page *page;
6185
6186 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6187
6188 /*
6189 * This memory barrier is needed to keep us from reading
6190 * any other fields out of the rx_desc until we know the
6191 * RXD_STAT_DD bit is set
6192 */
6193 rmb();
6194
6195 page = rx_buffer->page;
6196 prefetchw(page);
6197
6198 if (likely(!skb)) {
6199 void *page_addr = page_address(page) +
6200 rx_buffer->page_offset;
6201
6202 /* prefetch first cache line of first page */
6203 prefetch(page_addr);
6204#if L1_CACHE_BYTES < 128
6205 prefetch(page_addr + L1_CACHE_BYTES);
6206#endif
6207
6208 /* allocate a skb to store the frags */
6209 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6210 IGB_RX_HDR_LEN);
6211 if (unlikely(!skb)) {
6212 rx_ring->rx_stats.alloc_failed++;
6213 return NULL;
6214 }
6215
6216 /*
6217 * we will be copying header into skb->data in
6218 * pskb_may_pull so it is in our interest to prefetch
6219 * it now to avoid a possible cache miss
6220 */
6221 prefetchw(skb->data);
6222 }
6223
6224 /* we are reusing so sync this buffer for CPU use */
6225 dma_sync_single_range_for_cpu(rx_ring->dev,
6226 rx_buffer->dma,
6227 rx_buffer->page_offset,
de78d1f9 6228 IGB_RX_BUFSZ,
2e334eee
AD		 6229 DMA_FROM_DEVICE);
6230
6231 /* pull page into skb */
6232 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6233 /* hand second half of page back to the ring */
6234 igb_reuse_rx_page(rx_ring, rx_buffer);
6235 } else {
6236 /* we are not reusing the buffer so unmap it */
6237 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6238 PAGE_SIZE, DMA_FROM_DEVICE);
6239 }
6240
6241 /* clear contents of rx_buffer */
6242 rx_buffer->page = NULL;
6243
6244 return skb;
6245}
6246
cd392f5c 6247static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6248 union e1000_adv_rx_desc *rx_desc,
6249 struct sk_buff *skb)
9d5c8243 6250{
bc8acf2c 6251 skb_checksum_none_assert(skb);
9d5c8243 6252
294e7d78 6253 /* Ignore Checksum bit is set */
3ceb90fd 6254 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6255 return;
6256
6257 /* Rx checksum disabled via ethtool */
6258 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6259 return;
85ad76b2 6260
9d5c8243 6261 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6262 if (igb_test_staterr(rx_desc,
6263 E1000_RXDEXT_STATERR_TCPE |
6264 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6265 /*
6266 * work around errata with sctp packets where the TCPE aka
6267 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6268 * packets, (aka let the stack check the crc32c)
6269 */
866cff06
AD		 6270 if (!((skb->len == 60) &&
6271 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6272 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6273 ring->rx_stats.csum_err++;
12dcd86b
ED		 6274 u64_stats_update_end(&ring->rx_syncp);
6275 }
9d5c8243 6276 /* let the stack verify checksum errors */
9d5c8243
AK		 6277 return;
6278 }
6279 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6280 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6281 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6282 skb->ip_summed = CHECKSUM_UNNECESSARY;
6283
3ceb90fd
AD		 6284 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6285 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6286}
6287
077887c3
AD		 6288static inline void igb_rx_hash(struct igb_ring *ring,
6289 union e1000_adv_rx_desc *rx_desc,
6290 struct sk_buff *skb)
6291{
6292 if (ring->netdev->features & NETIF_F_RXHASH)
6293 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6294}
6295
2e334eee
AD		 6296/**
6297 * igb_is_non_eop - process handling of non-EOP buffers
6298 * @rx_ring: Rx ring being processed
6299 * @rx_desc: Rx descriptor for current buffer
6300 * @skb: current socket buffer containing buffer in progress
6301 *
6302 * This function updates next to clean. If the buffer is an EOP buffer
6303 * this function exits returning false, otherwise it will place the
6304 * sk_buff in the next buffer to be chained and return true indicating
6305 * that this is in fact a non-EOP buffer.
6306 **/
6307static bool igb_is_non_eop(struct igb_ring *rx_ring,
6308 union e1000_adv_rx_desc *rx_desc)
6309{
6310 u32 ntc = rx_ring->next_to_clean + 1;
6311
6312 /* fetch, update, and store next to clean */
6313 ntc = (ntc < rx_ring->count) ? ntc : 0;
6314 rx_ring->next_to_clean = ntc;
6315
6316 prefetch(IGB_RX_DESC(rx_ring, ntc));
6317
6318 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6319 return false;
6320
6321 return true;
6322}
6323
1a1c225b
AD		 6324/**
6325 * igb_get_headlen - determine size of header for LRO/GRO
6326 * @data: pointer to the start of the headers
6327 * @max_len: total length of section to find headers in
6328 *
6329 * This function is meant to determine the length of headers that will
6330 * be recognized by hardware for LRO, and GRO offloads. The main
6331 * motivation of doing this is to only perform one pull for IPv4 TCP
6332 * packets so that we can do basic things like calculating the gso_size
6333 * based on the average data per packet.
6334 **/
6335static unsigned int igb_get_headlen(unsigned char *data,
6336 unsigned int max_len)
6337{
6338 union {
6339 unsigned char *network;
6340 /* l2 headers */
6341 struct ethhdr *eth;
6342 struct vlan_hdr *vlan;
6343 /* l3 headers */
6344 struct iphdr *ipv4;
6345 struct ipv6hdr *ipv6;
6346 } hdr;
6347 __be16 protocol;
6348 u8 nexthdr = 0; /* default to not TCP */
6349 u8 hlen;
6350
6351 /* this should never happen, but better safe than sorry */
6352 if (max_len < ETH_HLEN)
6353 return max_len;
6354
6355 /* initialize network frame pointer */
6356 hdr.network = data;
6357
6358 /* set first protocol and move network header forward */
6359 protocol = hdr.eth->h_proto;
6360 hdr.network += ETH_HLEN;
6361
6362 /* handle any vlan tag if present */
6363 if (protocol == __constant_htons(ETH_P_8021Q)) {
6364 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6365 return max_len;
6366
6367 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6368 hdr.network += VLAN_HLEN;
6369 }
6370
6371 /* handle L3 protocols */
6372 if (protocol == __constant_htons(ETH_P_IP)) {
6373 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6374 return max_len;
6375
6376 /* access ihl as a u8 to avoid unaligned access on ia64 */
6377 hlen = (hdr.network[0] & 0x0F) << 2;
6378
6379 /* verify hlen meets minimum size requirements */
6380 if (hlen < sizeof(struct iphdr))
6381 return hdr.network - data;
6382
f2fb4ab2
AD		 6383 /* record next protocol if header is present */
6384 if (!hdr.ipv4->frag_off)
6385 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6386 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6387 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6388 return max_len;
6389
6390 /* record next protocol */
6391 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6392 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6393 } else {
6394 return hdr.network - data;
6395 }
6396
f2fb4ab2
AD		 6397 /* relocate pointer to start of L4 header */
6398 hdr.network += hlen;
6399
1a1c225b
AD		 6400 /* finally sort out TCP */
6401 if (nexthdr == IPPROTO_TCP) {
6402 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6403 return max_len;
6404
6405 /* access doff as a u8 to avoid unaligned access on ia64 */
6406 hlen = (hdr.network[12] & 0xF0) >> 2;
6407
6408 /* verify hlen meets minimum size requirements */
6409 if (hlen < sizeof(struct tcphdr))
6410 return hdr.network - data;
6411
6412 hdr.network += hlen;
6413 } else if (nexthdr == IPPROTO_UDP) {
6414 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6415 return max_len;
6416
6417 hdr.network += sizeof(struct udphdr);
6418 }
6419
6420 /*
6421 * If everything has gone correctly hdr.network should be the
6422 * data section of the packet and will be the end of the header.
6423 * If not then it probably represents the end of the last recognized
6424 * header.
6425 */
6426 if ((hdr.network - data) < max_len)
6427 return hdr.network - data;
6428 else
6429 return max_len;
6430}
6431
6432/**
6433 * igb_pull_tail - igb specific version of skb_pull_tail
6434 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6435 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6436 * @skb: pointer to current skb being adjusted
6437 *
6438 * This function is an igb specific version of __pskb_pull_tail. The
6439 * main difference between this version and the original function is that
6440 * this function can make several assumptions about the state of things
6441 * that allow for significant optimizations versus the standard function.
6442 * As a result we can do things like drop a frag and maintain an accurate
6443 * truesize for the skb.
6444 */
6445static void igb_pull_tail(struct igb_ring *rx_ring,
6446 union e1000_adv_rx_desc *rx_desc,
6447 struct sk_buff *skb)
2d94d8ab 6448{
1a1c225b
AD		 6449 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6450 unsigned char *va;
6451 unsigned int pull_len;
6452
6453 /*
6454 * it is valid to use page_address instead of kmap since we are
6455 * working with pages allocated out of the lomem pool per
6456 * alloc_page(GFP_ATOMIC)
2d94d8ab 6457 */
1a1c225b
AD		 6458 va = skb_frag_address(frag);
6459
1a1c225b
AD		 6460 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6461 /* retrieve timestamp from buffer */
6462 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6463
6464 /* update pointers to remove timestamp header */
6465 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6466 frag->page_offset += IGB_TS_HDR_LEN;
6467 skb->data_len -= IGB_TS_HDR_LEN;
6468 skb->len -= IGB_TS_HDR_LEN;
6469
6470 /* move va to start of packet data */
6471 va += IGB_TS_HDR_LEN;
6472 }
6473
1a1c225b
AD		 6474 /*
6475 * we need the header to contain the greater of either ETH_HLEN or
6476 * 60 bytes if the skb->len is less than 60 for skb_pad.
6477 */
6478 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6479
6480 /* align pull length to size of long to optimize memcpy performance */
6481 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6482
6483 /* update all of the pointers */
6484 skb_frag_size_sub(frag, pull_len);
6485 frag->page_offset += pull_len;
6486 skb->data_len -= pull_len;
6487 skb->tail += pull_len;
6488}
6489
6490/**
6491 * igb_cleanup_headers - Correct corrupted or empty headers
6492 * @rx_ring: rx descriptor ring packet is being transacted on
6493 * @rx_desc: pointer to the EOP Rx descriptor
6494 * @skb: pointer to current skb being fixed
6495 *
6496 * Address the case where we are pulling data in on pages only
6497 * and as such no data is present in the skb header.
6498 *
6499 * In addition if skb is not at least 60 bytes we need to pad it so that
6500 * it is large enough to qualify as a valid Ethernet frame.
6501 *
6502 * Returns true if an error was encountered and skb was freed.
6503 **/
6504static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6505 union e1000_adv_rx_desc *rx_desc,
6506 struct sk_buff *skb)
6507{
6508
6509 if (unlikely((igb_test_staterr(rx_desc,
6510 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6511 struct net_device *netdev = rx_ring->netdev;
6512 if (!(netdev->features & NETIF_F_RXALL)) {
6513 dev_kfree_skb_any(skb);
6514 return true;
6515 }
6516 }
6517
6518 /* place header in linear portion of buffer */
6519 if (skb_is_nonlinear(skb))
6520 igb_pull_tail(rx_ring, rx_desc, skb);
6521
6522 /* if skb_pad returns an error the skb was freed */
6523 if (unlikely(skb->len < 60)) {
6524 int pad_len = 60 - skb->len;
6525
6526 if (skb_pad(skb, pad_len))
6527 return true;
6528 __skb_put(skb, pad_len);
6529 }
6530
6531 return false;
2d94d8ab
AD		 6532}
6533
db2ee5bd
AD		 6534/**
6535 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6536 * @rx_ring: rx descriptor ring packet is being transacted on
6537 * @rx_desc: pointer to the EOP Rx descriptor
6538 * @skb: pointer to current skb being populated
6539 *
6540 * This function checks the ring, descriptor, and packet information in
6541 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6542 * other fields within the skb.
6543 **/
6544static void igb_process_skb_fields(struct igb_ring *rx_ring,
6545 union e1000_adv_rx_desc *rx_desc,
6546 struct sk_buff *skb)
6547{
6548 struct net_device *dev = rx_ring->netdev;
6549
6550 igb_rx_hash(rx_ring, rx_desc, skb);
6551
6552 igb_rx_checksum(rx_ring, rx_desc, skb);
6553
db2ee5bd 6554 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6555
6556 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6557 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6558 u16 vid;
6559 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6560 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6561 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6562 else
6563 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6564
6565 __vlan_hwaccel_put_tag(skb, vid);
6566 }
6567
6568 skb_record_rx_queue(skb, rx_ring->queue_index);
6569
6570 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6571}
6572
2e334eee 6573static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6574{
0ba82994 6575 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6576 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6577 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6578 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6579
2e334eee
AD		 6580 do {
6581 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6582
2e334eee
AD		 6583 /* return some buffers to hardware, one at a time is too slow */
6584 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6585 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6586 cleaned_count = 0;
6587 }
bf36c1a0 6588
2e334eee 6589 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6590
2e334eee
AD		 6591 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6592 break;
9d5c8243 6593
2e334eee
AD		 6594 /* retrieve a buffer from the ring */
6595 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6596
2e334eee
AD		 6597 /* exit if we failed to retrieve a buffer */
6598 if (!skb)
6599 break;
1a1c225b 6600
2e334eee 6601 cleaned_count++;
1a1c225b 6602
2e334eee
AD		 6603 /* fetch next buffer in frame if non-eop */
6604 if (igb_is_non_eop(rx_ring, rx_desc))
6605 continue;
1a1c225b
AD		 6606
6607 /* verify the packet layout is correct */
6608 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6609 skb = NULL;
6610 continue;
9d5c8243 6611 }
9d5c8243 6612
db2ee5bd 6613 /* probably a little skewed due to removing CRC */
3ceb90fd 6614 total_bytes += skb->len;
3ceb90fd 6615
db2ee5bd
AD		 6616 /* populate checksum, timestamp, VLAN, and protocol */
6617 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6618
b2cb09b1 6619 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6620
1a1c225b
AD		 6621 /* reset skb pointer */
6622 skb = NULL;
6623
2e334eee
AD		 6624 /* update budget accounting */
6625 total_packets++;
6626 } while (likely(total_packets < budget));
bf36c1a0 6627
1a1c225b
AD		 6628 /* place incomplete frames back on ring for completion */
6629 rx_ring->skb = skb;
6630
12dcd86b 6631 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6632 rx_ring->rx_stats.packets += total_packets;
6633 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6634 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6635 q_vector->rx.total_packets += total_packets;
6636 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6637
6638 if (cleaned_count)
cd392f5c 6639 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6640
2e334eee 6641 return (total_packets < budget);
9d5c8243
AK		 6642}
6643
c023cd88 6644static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6645 struct igb_rx_buffer *bi)
c023cd88
AD		 6646{
6647 struct page *page = bi->page;
cbc8e55f 6648 dma_addr_t dma;
c023cd88 6649
cbc8e55f
AD		 6650 /* since we are recycling buffers we should seldom need to alloc */
6651 if (likely(page))
c023cd88
AD		 6652 return true;
6653
cbc8e55f
AD		 6654 /* alloc new page for storage */
6655 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6656 if (unlikely(!page)) {
6657 rx_ring->rx_stats.alloc_failed++;
6658 return false;
c023cd88
AD		 6659 }
6660
cbc8e55f
AD		 6661 /* map page for use */
6662 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6663
cbc8e55f
AD		 6664 /*
6665 * if mapping failed free memory back to system since
6666 * there isn't much point in holding memory we can't use
6667 */
1a1c225b 6668 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6669 __free_page(page);
6670
c023cd88
AD		 6671 rx_ring->rx_stats.alloc_failed++;
6672 return false;
6673 }
6674
1a1c225b 6675 bi->dma = dma;
cbc8e55f
AD		 6676 bi->page = page;
6677 bi->page_offset = 0;
1a1c225b 6678
c023cd88
AD		 6679 return true;
6680}
6681
9d5c8243 6682/**
cd392f5c 6683 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6684 * @adapter: address of board private structure
6685 **/
cd392f5c 6686void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6687{
9d5c8243 6688 union e1000_adv_rx_desc *rx_desc;
06034649 6689 struct igb_rx_buffer *bi;
c023cd88 6690 u16 i = rx_ring->next_to_use;
9d5c8243 6691
cbc8e55f
AD		 6692 /* nothing to do */
6693 if (!cleaned_count)
6694 return;
6695
60136906 6696 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6697 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6698 i -= rx_ring->count;
9d5c8243 6699
cbc8e55f 6700 do {
1a1c225b 6701 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6702 break;
9d5c8243 6703
cbc8e55f
AD		 6704 /*
6705 * Refresh the desc even if buffer_addrs didn't change
6706 * because each write-back erases this info.
6707 */
6708 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6709
c023cd88
AD		 6710 rx_desc++;
6711 bi++;
9d5c8243 6712 i++;
c023cd88 6713 if (unlikely(!i)) {
60136906 6714 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6715 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6716 i -= rx_ring->count;
6717 }
6718
6719 /* clear the hdr_addr for the next_to_use descriptor */
6720 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6721
6722 cleaned_count--;
6723 } while (cleaned_count);
9d5c8243 6724
c023cd88
AD		 6725 i += rx_ring->count;
6726
9d5c8243 6727 if (rx_ring->next_to_use != i) {
cbc8e55f 6728 /* record the next descriptor to use */
9d5c8243 6729 rx_ring->next_to_use = i;
9d5c8243 6730
cbc8e55f
AD		 6731 /* update next to alloc since we have filled the ring */
6732 rx_ring->next_to_alloc = i;
6733
6734 /*
6735 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6736 * know there are new descriptors to fetch. (Only
6737 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6738 * such as IA-64).
6739 */
9d5c8243 6740 wmb();
fce99e34 6741 writel(i, rx_ring->tail);
9d5c8243
AK		 6742 }
6743}
6744
6745/**
6746 * igb_mii_ioctl -
6747 * @netdev:
6748 * @ifreq:
6749 * @cmd:
6750 **/
6751static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6752{
6753 struct igb_adapter *adapter = netdev_priv(netdev);
6754 struct mii_ioctl_data *data = if_mii(ifr);
6755
6756 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6757 return -EOPNOTSUPP;
6758
6759 switch (cmd) {
6760 case SIOCGMIIPHY:
6761 data->phy_id = adapter->hw.phy.addr;
6762 break;
6763 case SIOCGMIIREG:
f5f4cf08
AD		 6764 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6765 &data->val_out))
9d5c8243
AK		 6766 return -EIO;
6767 break;
6768 case SIOCSMIIREG:
6769 default:
6770 return -EOPNOTSUPP;
6771 }
6772 return 0;
6773}
6774
6775/**
6776 * igb_ioctl -
6777 * @netdev:
6778 * @ifreq:
6779 * @cmd:
6780 **/
6781static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6782{
6783 switch (cmd) {
6784 case SIOCGMIIPHY:
6785 case SIOCGMIIREG:
6786 case SIOCSMIIREG:
6787 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6788 case SIOCSHWTSTAMP:
a79f4f88 6789 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6790 default:
6791 return -EOPNOTSUPP;
6792 }
6793}
6794
009bc06e
AD		 6795s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6796{
6797 struct igb_adapter *adapter = hw->back;
009bc06e 6798
23d028cc 6799 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6800 return -E1000_ERR_CONFIG;
6801
009bc06e
AD		 6802 return 0;
6803}
6804
6805s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6806{
6807 struct igb_adapter *adapter = hw->back;
009bc06e 6808
23d028cc 6809 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6810 return -E1000_ERR_CONFIG;
6811
009bc06e
AD		 6812 return 0;
6813}
6814
c8f44aff 6815static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6816{
6817 struct igb_adapter *adapter = netdev_priv(netdev);
6818 struct e1000_hw *hw = &adapter->hw;
6819 u32 ctrl, rctl;
5faf030c 6820 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6821
5faf030c 6822 if (enable) {
9d5c8243
AK		 6823 /* enable VLAN tag insert/strip */
6824 ctrl = rd32(E1000_CTRL);
6825 ctrl |= E1000_CTRL_VME;
6826 wr32(E1000_CTRL, ctrl);
6827
51466239 6828 /* Disable CFI check */
9d5c8243 6829 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6830 rctl &= ~E1000_RCTL_CFIEN;
6831 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6832 } else {
6833 /* disable VLAN tag insert/strip */
6834 ctrl = rd32(E1000_CTRL);
6835 ctrl &= ~E1000_CTRL_VME;
6836 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6837 }
6838
e1739522 6839 igb_rlpml_set(adapter);
9d5c8243
AK		 6840}
6841
8e586137 6842static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6843{
6844 struct igb_adapter *adapter = netdev_priv(netdev);
6845 struct e1000_hw *hw = &adapter->hw;
4ae196df 6846 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6847
51466239
AD		 6848 /* attempt to add filter to vlvf array */
6849 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6850
51466239
AD		 6851 /* add the filter since PF can receive vlans w/o entry in vlvf */
6852 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6853
6854 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6855
6856 return 0;
9d5c8243
AK		 6857}
6858
8e586137 6859static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6860{
6861 struct igb_adapter *adapter = netdev_priv(netdev);
6862 struct e1000_hw *hw = &adapter->hw;
4ae196df 6863 int pf_id = adapter->vfs_allocated_count;
51466239 6864 s32 err;
9d5c8243 6865
51466239
AD		 6866 /* remove vlan from VLVF table array */
6867 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6868
51466239
AD		 6869 /* if vid was not present in VLVF just remove it from table */
6870 if (err)
4ae196df 6871 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6872
6873 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6874
6875 return 0;
9d5c8243
AK		 6876}
6877
6878static void igb_restore_vlan(struct igb_adapter *adapter)
6879{
b2cb09b1 6880 u16 vid;
9d5c8243 6881
5faf030c
AD		 6882 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6883
b2cb09b1
JP		 6884 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6885 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6886}
6887
14ad2513 6888int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6889{
090b1795 6890 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6891 struct e1000_mac_info *mac = &adapter->hw.mac;
6892
6893 mac->autoneg = 0;
6894
14ad2513
DD		 6895 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6896 * for the switch() below to work */
6897 if ((spd & 1) || (dplx & ~1))
6898 goto err_inval;
6899
cd2638a8
CW		 6900 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6901 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6902 spd != SPEED_1000 &&
6903 dplx != DUPLEX_FULL)
6904 goto err_inval;
cd2638a8 6905
14ad2513 6906 switch (spd + dplx) {
9d5c8243
AK		 6907 case SPEED_10 + DUPLEX_HALF:
6908 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6909 break;
6910 case SPEED_10 + DUPLEX_FULL:
6911 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6912 break;
6913 case SPEED_100 + DUPLEX_HALF:
6914 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6915 break;
6916 case SPEED_100 + DUPLEX_FULL:
6917 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6918 break;
6919 case SPEED_1000 + DUPLEX_FULL:
6920 mac->autoneg = 1;
6921 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6922 break;
6923 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6924 default:
14ad2513 6925 goto err_inval;
9d5c8243 6926 }
8376dad0
JB		 6927
6928 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6929 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6930
9d5c8243 6931 return 0;
14ad2513
DD		 6932
6933err_inval:
6934 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6935 return -EINVAL;
9d5c8243
AK		 6936}
6937
749ab2cd
YZ		 6938static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6939 bool runtime)
9d5c8243
AK		 6940{
6941 struct net_device *netdev = pci_get_drvdata(pdev);
6942 struct igb_adapter *adapter = netdev_priv(netdev);
6943 struct e1000_hw *hw = &adapter->hw;
2d064c06 6944 u32 ctrl, rctl, status;
749ab2cd 6945 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6946#ifdef CONFIG_PM
6947 int retval = 0;
6948#endif
6949
6950 netif_device_detach(netdev);
6951
a88f10ec 6952 if (netif_running(netdev))
749ab2cd 6953 __igb_close(netdev, true);
a88f10ec 6954
047e0030 6955 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6956
6957#ifdef CONFIG_PM
6958 retval = pci_save_state(pdev);
6959 if (retval)
6960 return retval;
6961#endif
6962
6963 status = rd32(E1000_STATUS);
6964 if (status & E1000_STATUS_LU)
6965 wufc &= ~E1000_WUFC_LNKC;
6966
6967 if (wufc) {
6968 igb_setup_rctl(adapter);
ff41f8dc 6969 igb_set_rx_mode(netdev);
9d5c8243
AK		 6970
6971 /* turn on all-multi mode if wake on multicast is enabled */
6972 if (wufc & E1000_WUFC_MC) {
6973 rctl = rd32(E1000_RCTL);
6974 rctl |= E1000_RCTL_MPE;
6975 wr32(E1000_RCTL, rctl);
6976 }
6977
6978 ctrl = rd32(E1000_CTRL);
6979 /* advertise wake from D3Cold */
6980 #define E1000_CTRL_ADVD3WUC 0x00100000
6981 /* phy power management enable */
6982 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6983 ctrl |= E1000_CTRL_ADVD3WUC;
6984 wr32(E1000_CTRL, ctrl);
6985
9d5c8243 6986 /* Allow time for pending master requests to run */
330a6d6a 6987 igb_disable_pcie_master(hw);
9d5c8243
AK		 6988
6989 wr32(E1000_WUC, E1000_WUC_PME_EN);
6990 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6991 } else {
6992 wr32(E1000_WUC, 0);
6993 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6994 }
6995
3fe7c4c9
RW		 6996 *enable_wake = wufc || adapter->en_mng_pt;
6997 if (!*enable_wake)
88a268c1
NN		 6998 igb_power_down_link(adapter);
6999 else
7000 igb_power_up_link(adapter);
9d5c8243
AK		 7001
7002 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7003 * would have already happened in close and is redundant. */
7004 igb_release_hw_control(adapter);
7005
7006 pci_disable_device(pdev);
7007
9d5c8243
AK		 7008 return 0;
7009}
7010
7011#ifdef CONFIG_PM
d9dd966d 7012#ifdef CONFIG_PM_SLEEP
749ab2cd 7013static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7014{
7015 int retval;
7016 bool wake;
749ab2cd 7017 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7018
749ab2cd 7019 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7020 if (retval)
7021 return retval;
7022
7023 if (wake) {
7024 pci_prepare_to_sleep(pdev);
7025 } else {
7026 pci_wake_from_d3(pdev, false);
7027 pci_set_power_state(pdev, PCI_D3hot);
7028 }
7029
7030 return 0;
7031}
d9dd966d 7032#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7033
749ab2cd 7034static int igb_resume(struct device *dev)
9d5c8243 7035{
749ab2cd 7036 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7037 struct net_device *netdev = pci_get_drvdata(pdev);
7038 struct igb_adapter *adapter = netdev_priv(netdev);
7039 struct e1000_hw *hw = &adapter->hw;
7040 u32 err;
7041
7042 pci_set_power_state(pdev, PCI_D0);
7043 pci_restore_state(pdev);
b94f2d77 7044 pci_save_state(pdev);
42bfd33a 7045
aed5dec3 7046 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7047 if (err) {
7048 dev_err(&pdev->dev,
7049 "igb: Cannot enable PCI device from suspend\n");
7050 return err;
7051 }
7052 pci_set_master(pdev);
7053
7054 pci_enable_wake(pdev, PCI_D3hot, 0);
7055 pci_enable_wake(pdev, PCI_D3cold, 0);
7056
53c7d064 7057 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7058 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7059 return -ENOMEM;
9d5c8243
AK		 7060 }
7061
9d5c8243 7062 igb_reset(adapter);
a8564f03
AD		 7063
7064 /* let the f/w know that the h/w is now under the control of the
7065 * driver. */
7066 igb_get_hw_control(adapter);
7067
9d5c8243
AK		 7068 wr32(E1000_WUS, ~0);
7069
749ab2cd 7070 if (netdev->flags & IFF_UP) {
0c2cc02e 7071 rtnl_lock();
749ab2cd 7072 err = __igb_open(netdev, true);
0c2cc02e 7073 rtnl_unlock();
a88f10ec
AD		 7074 if (err)
7075 return err;
7076 }
9d5c8243
AK		 7077
7078 netif_device_attach(netdev);
749ab2cd
YZ		 7079 return 0;
7080}
7081
7082#ifdef CONFIG_PM_RUNTIME
7083static int igb_runtime_idle(struct device *dev)
7084{
7085 struct pci_dev *pdev = to_pci_dev(dev);
7086 struct net_device *netdev = pci_get_drvdata(pdev);
7087 struct igb_adapter *adapter = netdev_priv(netdev);
7088
7089 if (!igb_has_link(adapter))
7090 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7091
7092 return -EBUSY;
7093}
7094
7095static int igb_runtime_suspend(struct device *dev)
7096{
7097 struct pci_dev *pdev = to_pci_dev(dev);
7098 int retval;
7099 bool wake;
7100
7101 retval = __igb_shutdown(pdev, &wake, 1);
7102 if (retval)
7103 return retval;
7104
7105 if (wake) {
7106 pci_prepare_to_sleep(pdev);
7107 } else {
7108 pci_wake_from_d3(pdev, false);
7109 pci_set_power_state(pdev, PCI_D3hot);
7110 }
9d5c8243 7111
9d5c8243
AK		 7112 return 0;
7113}
749ab2cd
YZ		 7114
7115static int igb_runtime_resume(struct device *dev)
7116{
7117 return igb_resume(dev);
7118}
7119#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7120#endif
7121
7122static void igb_shutdown(struct pci_dev *pdev)
7123{
3fe7c4c9
RW		 7124 bool wake;
7125
749ab2cd 7126 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7127
7128 if (system_state == SYSTEM_POWER_OFF) {
7129 pci_wake_from_d3(pdev, wake);
7130 pci_set_power_state(pdev, PCI_D3hot);
7131 }
9d5c8243
AK		 7132}
7133
fa44f2f1
GR		 7134#ifdef CONFIG_PCI_IOV
7135static int igb_sriov_reinit(struct pci_dev *dev)
7136{
7137 struct net_device *netdev = pci_get_drvdata(dev);
7138 struct igb_adapter *adapter = netdev_priv(netdev);
7139 struct pci_dev *pdev = adapter->pdev;
7140
7141 rtnl_lock();
7142
7143 if (netif_running(netdev))
7144 igb_close(netdev);
7145
7146 igb_clear_interrupt_scheme(adapter);
7147
7148 igb_init_queue_configuration(adapter);
7149
7150 if (igb_init_interrupt_scheme(adapter, true)) {
7151 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7152 return -ENOMEM;
7153 }
7154
7155 if (netif_running(netdev))
7156 igb_open(netdev);
7157
7158 rtnl_unlock();
7159
7160 return 0;
7161}
7162
7163static int igb_pci_disable_sriov(struct pci_dev *dev)
7164{
7165 int err = igb_disable_sriov(dev);
7166
7167 if (!err)
7168 err = igb_sriov_reinit(dev);
7169
7170 return err;
7171}
7172
7173static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7174{
7175 int err = igb_enable_sriov(dev, num_vfs);
7176
7177 if (err)
7178 goto out;
7179
7180 err = igb_sriov_reinit(dev);
7181 if (!err)
7182 return num_vfs;
7183
7184out:
7185 return err;
7186}
7187
7188#endif
7189static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7190{
7191#ifdef CONFIG_PCI_IOV
7192 if (num_vfs == 0)
7193 return igb_pci_disable_sriov(dev);
7194 else
7195 return igb_pci_enable_sriov(dev, num_vfs);
7196#endif
7197 return 0;
7198}
7199
9d5c8243
AK		 7200#ifdef CONFIG_NET_POLL_CONTROLLER
7201/*
7202 * Polling 'interrupt' - used by things like netconsole to send skbs
7203 * without having to re-enable interrupts. It's not called while
7204 * the interrupt routine is executing.
7205 */
7206static void igb_netpoll(struct net_device *netdev)
7207{
7208 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7209 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7210 struct igb_q_vector *q_vector;
9d5c8243 7211 int i;
9d5c8243 7212
047e0030 7213 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7214 q_vector = adapter->q_vector[i];
7215 if (adapter->msix_entries)
7216 wr32(E1000_EIMC, q_vector->eims_value);
7217 else
7218 igb_irq_disable(adapter);
047e0030 7219 napi_schedule(&q_vector->napi);
eebbbdba 7220 }
9d5c8243
AK		 7221}
7222#endif /* CONFIG_NET_POLL_CONTROLLER */
7223
7224/**
7225 * igb_io_error_detected - called when PCI error is detected
7226 * @pdev: Pointer to PCI device
7227 * @state: The current pci connection state
7228 *
7229 * This function is called after a PCI bus error affecting
7230 * this device has been detected.
7231 */
7232static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7233 pci_channel_state_t state)
7234{
7235 struct net_device *netdev = pci_get_drvdata(pdev);
7236 struct igb_adapter *adapter = netdev_priv(netdev);
7237
7238 netif_device_detach(netdev);
7239
59ed6eec
AD		 7240 if (state == pci_channel_io_perm_failure)
7241 return PCI_ERS_RESULT_DISCONNECT;
7242
9d5c8243
AK		 7243 if (netif_running(netdev))
7244 igb_down(adapter);
7245 pci_disable_device(pdev);
7246
7247 /* Request a slot slot reset. */
7248 return PCI_ERS_RESULT_NEED_RESET;
7249}
7250
7251/**
7252 * igb_io_slot_reset - called after the pci bus has been reset.
7253 * @pdev: Pointer to PCI device
7254 *
7255 * Restart the card from scratch, as if from a cold-boot. Implementation
7256 * resembles the first-half of the igb_resume routine.
7257 */
7258static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7259{
7260 struct net_device *netdev = pci_get_drvdata(pdev);
7261 struct igb_adapter *adapter = netdev_priv(netdev);
7262 struct e1000_hw *hw = &adapter->hw;
40a914fa 7263 pci_ers_result_t result;
42bfd33a 7264 int err;
9d5c8243 7265
aed5dec3 7266 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7267 dev_err(&pdev->dev,
7268 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7269 result = PCI_ERS_RESULT_DISCONNECT;
7270 } else {
7271 pci_set_master(pdev);
7272 pci_restore_state(pdev);
b94f2d77 7273 pci_save_state(pdev);
9d5c8243 7274
40a914fa
AD		 7275 pci_enable_wake(pdev, PCI_D3hot, 0);
7276 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7277
40a914fa
AD		 7278 igb_reset(adapter);
7279 wr32(E1000_WUS, ~0);
7280 result = PCI_ERS_RESULT_RECOVERED;
7281 }
9d5c8243 7282
ea943d41
JK		 7283 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7284 if (err) {
7285 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7286 "failed 0x%0x\n", err);
7287 /* non-fatal, continue */
7288 }
40a914fa
AD		 7289
7290 return result;
9d5c8243
AK		 7291}
7292
7293/**
7294 * igb_io_resume - called when traffic can start flowing again.
7295 * @pdev: Pointer to PCI device
7296 *
7297 * This callback is called when the error recovery driver tells us that
7298 * its OK to resume normal operation. Implementation resembles the
7299 * second-half of the igb_resume routine.
7300 */
7301static void igb_io_resume(struct pci_dev *pdev)
7302{
7303 struct net_device *netdev = pci_get_drvdata(pdev);
7304 struct igb_adapter *adapter = netdev_priv(netdev);
7305
9d5c8243
AK		 7306 if (netif_running(netdev)) {
7307 if (igb_up(adapter)) {
7308 dev_err(&pdev->dev, "igb_up failed after reset\n");
7309 return;
7310 }
7311 }
7312
7313 netif_device_attach(netdev);
7314
7315 /* let the f/w know that the h/w is now under the control of the
7316 * driver. */
7317 igb_get_hw_control(adapter);
9d5c8243
AK		 7318}
7319
26ad9178
AD		 7320static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7321 u8 qsel)
7322{
7323 u32 rar_low, rar_high;
7324 struct e1000_hw *hw = &adapter->hw;
7325
7326 /* HW expects these in little endian so we reverse the byte order
7327 * from network order (big endian) to little endian
7328 */
7329 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7330 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7331 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7332
7333 /* Indicate to hardware the Address is Valid. */
7334 rar_high |= E1000_RAH_AV;
7335
7336 if (hw->mac.type == e1000_82575)
7337 rar_high |= E1000_RAH_POOL_1 * qsel;
7338 else
7339 rar_high |= E1000_RAH_POOL_1 << qsel;
7340
7341 wr32(E1000_RAL(index), rar_low);
7342 wrfl();
7343 wr32(E1000_RAH(index), rar_high);
7344 wrfl();
7345}
7346
4ae196df
AD		 7347static int igb_set_vf_mac(struct igb_adapter *adapter,
7348 int vf, unsigned char *mac_addr)
7349{
7350 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7351 /* VF MAC addresses start at end of receive addresses and moves
7352 * torwards the first, as a result a collision should not be possible */
7353 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7354
37680117 7355 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7356
26ad9178 7357 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7358
7359 return 0;
7360}
7361
8151d294
WM		 7362static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7363{
7364 struct igb_adapter *adapter = netdev_priv(netdev);
7365 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7366 return -EINVAL;
7367 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7368 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7369 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7370 " change effective.");
7371 if (test_bit(__IGB_DOWN, &adapter->state)) {
7372 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7373 " but the PF device is not up.\n");
7374 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7375 " attempting to use the VF device.\n");
7376 }
7377 return igb_set_vf_mac(adapter, vf, mac);
7378}
7379
17dc566c
LL		 7380static int igb_link_mbps(int internal_link_speed)
7381{
7382 switch (internal_link_speed) {
7383 case SPEED_100:
7384 return 100;
7385 case SPEED_1000:
7386 return 1000;
7387 default:
7388 return 0;
7389 }
7390}
7391
7392static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7393 int link_speed)
7394{
7395 int rf_dec, rf_int;
7396 u32 bcnrc_val;
7397
7398 if (tx_rate != 0) {
7399 /* Calculate the rate factor values to set */
7400 rf_int = link_speed / tx_rate;
7401 rf_dec = (link_speed - (rf_int * tx_rate));
7402 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7403
7404 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7405 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7406 E1000_RTTBCNRC_RF_INT_MASK);
7407 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7408 } else {
7409 bcnrc_val = 0;
7410 }
7411
7412 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7413 /*
7414 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7415 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7416 */
7417 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7418 wr32(E1000_RTTBCNRC, bcnrc_val);
7419}
7420
7421static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7422{
7423 int actual_link_speed, i;
7424 bool reset_rate = false;
7425
7426 /* VF TX rate limit was not set or not supported */
7427 if ((adapter->vf_rate_link_speed == 0) ||
7428 (adapter->hw.mac.type != e1000_82576))
7429 return;
7430
7431 actual_link_speed = igb_link_mbps(adapter->link_speed);
7432 if (actual_link_speed != adapter->vf_rate_link_speed) {
7433 reset_rate = true;
7434 adapter->vf_rate_link_speed = 0;
7435 dev_info(&adapter->pdev->dev,
7436 "Link speed has been changed. VF Transmit "
7437 "rate is disabled\n");
7438 }
7439
7440 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7441 if (reset_rate)
7442 adapter->vf_data[i].tx_rate = 0;
7443
7444 igb_set_vf_rate_limit(&adapter->hw, i,
7445 adapter->vf_data[i].tx_rate,
7446 actual_link_speed);
7447 }
7448}
7449
8151d294
WM		 7450static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7451{
17dc566c
LL		 7452 struct igb_adapter *adapter = netdev_priv(netdev);
7453 struct e1000_hw *hw = &adapter->hw;
7454 int actual_link_speed;
7455
7456 if (hw->mac.type != e1000_82576)
7457 return -EOPNOTSUPP;
7458
7459 actual_link_speed = igb_link_mbps(adapter->link_speed);
7460 if ((vf >= adapter->vfs_allocated_count) ||
7461 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7462 (tx_rate < 0) || (tx_rate > actual_link_speed))
7463 return -EINVAL;
7464
7465 adapter->vf_rate_link_speed = actual_link_speed;
7466 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7467 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7468
7469 return 0;
8151d294
WM		 7470}
7471
7472static int igb_ndo_get_vf_config(struct net_device *netdev,
7473 int vf, struct ifla_vf_info *ivi)
7474{
7475 struct igb_adapter *adapter = netdev_priv(netdev);
7476 if (vf >= adapter->vfs_allocated_count)
7477 return -EINVAL;
7478 ivi->vf = vf;
7479 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7480 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7481 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7482 ivi->qos = adapter->vf_data[vf].pf_qos;
7483 return 0;
7484}
7485
4ae196df
AD		 7486static void igb_vmm_control(struct igb_adapter *adapter)
7487{
7488 struct e1000_hw *hw = &adapter->hw;
10d8e907 7489 u32 reg;
4ae196df 7490
52a1dd4d
AD		 7491 switch (hw->mac.type) {
7492 case e1000_82575:
f96a8a0b
CW		 7493 case e1000_i210:
7494 case e1000_i211:
52a1dd4d
AD		 7495 default:
7496 /* replication is not supported for 82575 */
4ae196df 7497 return;
52a1dd4d
AD		 7498 case e1000_82576:
7499 /* notify HW that the MAC is adding vlan tags */
7500 reg = rd32(E1000_DTXCTL);
7501 reg |= E1000_DTXCTL_VLAN_ADDED;
7502 wr32(E1000_DTXCTL, reg);
7503 case e1000_82580:
7504 /* enable replication vlan tag stripping */
7505 reg = rd32(E1000_RPLOLR);
7506 reg |= E1000_RPLOLR_STRVLAN;
7507 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7508 case e1000_i350:
7509 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7510 break;
7511 }
10d8e907 7512
d4960307
AD		 7513 if (adapter->vfs_allocated_count) {
7514 igb_vmdq_set_loopback_pf(hw, true);
7515 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7516 igb_vmdq_set_anti_spoofing_pf(hw, true,
7517 adapter->vfs_allocated_count);
d4960307
AD		 7518 } else {
7519 igb_vmdq_set_loopback_pf(hw, false);
7520 igb_vmdq_set_replication_pf(hw, false);
7521 }
4ae196df
AD		 7522}
7523
b6e0c419
CW		 7524static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7525{
7526 struct e1000_hw *hw = &adapter->hw;
7527 u32 dmac_thr;
7528 u16 hwm;
7529
7530 if (hw->mac.type > e1000_82580) {
7531 if (adapter->flags & IGB_FLAG_DMAC) {
7532 u32 reg;
7533
7534 /* force threshold to 0. */
7535 wr32(E1000_DMCTXTH, 0);
7536
7537 /*
e8c626e9
MV		 7538 * DMA Coalescing high water mark needs to be greater
7539 * than the Rx threshold. Set hwm to PBA - max frame
7540 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7541 */
e8c626e9
MV		 7542 hwm = 64 * pba - adapter->max_frame_size / 16;
7543 if (hwm < 64 * (pba - 6))
7544 hwm = 64 * (pba - 6);
7545 reg = rd32(E1000_FCRTC);
7546 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7547 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7548 & E1000_FCRTC_RTH_COAL_MASK);
7549 wr32(E1000_FCRTC, reg);
7550
7551 /*
7552 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7553 * frame size, capping it at PBA - 10KB.
7554 */
7555 dmac_thr = pba - adapter->max_frame_size / 512;
7556 if (dmac_thr < pba - 10)
7557 dmac_thr = pba - 10;
b6e0c419
CW		 7558 reg = rd32(E1000_DMACR);
7559 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7560 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7561 & E1000_DMACR_DMACTHR_MASK);
7562
7563 /* transition to L0x or L1 if available..*/
7564 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7565
7566 /* watchdog timer= +-1000 usec in 32usec intervals */
7567 reg |= (1000 >> 5);
0c02dd98
MV		 7568
7569 /* Disable BMC-to-OS Watchdog Enable */
7570 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7571 wr32(E1000_DMACR, reg);
7572
7573 /*
7574 * no lower threshold to disable
7575 * coalescing(smart fifb)-UTRESH=0
7576 */
7577 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7578
7579 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7580
7581 wr32(E1000_DMCTLX, reg);
7582
7583 /*
7584 * free space in tx packet buffer to wake from
7585 * DMA coal
7586 */
7587 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7588 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7589
7590 /*
7591 * make low power state decision controlled
7592 * by DMA coal
7593 */
7594 reg = rd32(E1000_PCIEMISC);
7595 reg &= ~E1000_PCIEMISC_LX_DECISION;
7596 wr32(E1000_PCIEMISC, reg);
7597 } /* endif adapter->dmac is not disabled */
7598 } else if (hw->mac.type == e1000_82580) {
7599 u32 reg = rd32(E1000_PCIEMISC);
7600 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7601 wr32(E1000_DMACR, 0);
7602 }
7603}
7604
441fc6fd
CW		 7605static DEFINE_SPINLOCK(i2c_clients_lock);
7606
7607/* igb_get_i2c_client - returns matching client
7608 * in adapters's client list.
7609 * @adapter: adapter struct
7610 * @dev_addr: device address of i2c needed.
7611 */
7612struct i2c_client *
7613igb_get_i2c_client(struct igb_adapter *adapter, u8 dev_addr)
7614{
7615 ulong flags;
7616 struct igb_i2c_client_list *client_list;
7617 struct i2c_client *client = NULL;
7618 struct i2c_board_info client_info = {
7619 I2C_BOARD_INFO("igb", 0x00),
7620 };
7621
7622 spin_lock_irqsave(&i2c_clients_lock, flags);
7623 client_list = adapter->i2c_clients;
7624
7625 /* See if we already have an i2c_client */
7626 while (client_list) {
7627 if (client_list->client->addr == (dev_addr >> 1)) {
7628 client = client_list->client;
7629 goto exit;
7630 } else {
7631 client_list = client_list->next;
7632 }
7633 }
7634
e428893b
CW		 7635 /* no client_list found, create a new one as long as
7636 * irqs are not disabled
7637 */
7638 if (unlikely(irqs_disabled()))
7639 goto exit;
7640
441fc6fd
CW		 7641 client_list = kzalloc(sizeof(*client_list), GFP_KERNEL);
7642 if (client_list == NULL)
7643 goto exit;
7644
7645 /* dev_addr passed to us is left-shifted by 1 bit
7646 * i2c_new_device call expects it to be flush to the right.
7647 */
7648 client_info.addr = dev_addr >> 1;
7649 client_info.platform_data = adapter;
7650 client_list->client = i2c_new_device(&adapter->i2c_adap, &client_info);
7651 if (client_list->client == NULL) {
e428893b
CW		 7652 dev_info(&adapter->pdev->dev,
7653 "Failed to create new i2c device..\n");
441fc6fd
CW		 7654 goto err_no_client;
7655 }
7656
7657 /* insert new client at head of list */
7658 client_list->next = adapter->i2c_clients;
7659 adapter->i2c_clients = client_list;
7660
441fc6fd
CW		 7661 client = client_list->client;
7662 goto exit;
7663
7664err_no_client:
7665 kfree(client_list);
7666exit:
7667 spin_unlock_irqrestore(&i2c_clients_lock, flags);
7668 return client;
7669}
7670
7671/* igb_read_i2c_byte - Reads 8 bit word over I2C
7672 * @hw: pointer to hardware structure
7673 * @byte_offset: byte offset to read
7674 * @dev_addr: device address
7675 * @data: value read
7676 *
7677 * Performs byte read operation over I2C interface at
7678 * a specified device address.
7679 */
7680s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7681 u8 dev_addr, u8 *data)
7682{
7683 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7684 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7685 s32 status;
7686 u16 swfw_mask = 0;
7687
7688 if (!this_client)
7689 return E1000_ERR_I2C;
7690
7691 swfw_mask = E1000_SWFW_PHY0_SM;
7692
7693 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7694 != E1000_SUCCESS)
7695 return E1000_ERR_SWFW_SYNC;
7696
7697 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7698 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7699
7700 if (status < 0)
7701 return E1000_ERR_I2C;
7702 else {
7703 *data = status;
7704 return E1000_SUCCESS;
7705 }
7706}
7707
7708/* igb_write_i2c_byte - Writes 8 bit word over I2C
7709 * @hw: pointer to hardware structure
7710 * @byte_offset: byte offset to write
7711 * @dev_addr: device address
7712 * @data: value to write
7713 *
7714 * Performs byte write operation over I2C interface at
7715 * a specified device address.
7716 */
7717s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7718 u8 dev_addr, u8 data)
7719{
7720 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7721 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7722 s32 status;
7723 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7724
7725 if (!this_client)
7726 return E1000_ERR_I2C;
7727
7728 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7729 return E1000_ERR_SWFW_SYNC;
7730 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7731 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7732
7733 if (status)
7734 return E1000_ERR_I2C;
7735 else
7736 return E1000_SUCCESS;
7737
7738}
9d5c8243 7739/* igb_main.c */
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