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igb: drop the "adv" off function names relating to descriptors
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
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9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4297f99b 4 Copyright(c) 2007-2011 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
b2cb09b1 31#include <linux/bitops.h>
9d5c8243
AK		 32#include <linux/vmalloc.h>
33#include <linux/pagemap.h>
34#include <linux/netdevice.h>
9d5c8243 35#include <linux/ipv6.h>
5a0e3ad6 36#include <linux/slab.h>
9d5c8243
AK		 37#include <net/checksum.h>
38#include <net/ip6_checksum.h>
c6cb090b 39#include <linux/net_tstamp.h>
9d5c8243
AK		 40#include <linux/mii.h>
41#include <linux/ethtool.h>
01789349 42#include <linux/if.h>
9d5c8243
AK		 43#include <linux/if_vlan.h>
44#include <linux/pci.h>
c54106bb 45#include <linux/pci-aspm.h>
9d5c8243
AK		 46#include <linux/delay.h>
47#include <linux/interrupt.h>
48#include <linux/if_ether.h>
40a914fa 49#include <linux/aer.h>
70c71606 50#include <linux/prefetch.h>
421e02f0 51#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 52#include <linux/dca.h>
53#endif
9d5c8243
AK		 54#include "igb.h"
55
0d1fe82d
CW		 56#define MAJ 3
57#define MIN 0
58#define BUILD 6
0d1fe82d 59#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 60__stringify(BUILD) "-k"
9d5c8243
AK		 61char igb_driver_name[] = "igb";
62char igb_driver_version[] = DRV_VERSION;
63static const char igb_driver_string[] =
64 "Intel(R) Gigabit Ethernet Network Driver";
4c4b42cb 65static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
9d5c8243 66
9d5c8243
AK		 67static const struct e1000_info *igb_info_tbl[] = {
68 [board_82575] = &e1000_82575_info,
69};
70
a3aa1884 71static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
97 /* required last entry */
98 {0, }
99};
100
101MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
102
103void igb_reset(struct igb_adapter *);
104static int igb_setup_all_tx_resources(struct igb_adapter *);
105static int igb_setup_all_rx_resources(struct igb_adapter *);
106static void igb_free_all_tx_resources(struct igb_adapter *);
107static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 108static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 109static int igb_probe(struct pci_dev *, const struct pci_device_id *);
110static void __devexit igb_remove(struct pci_dev *pdev);
673b8b70 111static void igb_init_hw_timer(struct igb_adapter *adapter);
9d5c8243
AK		 112static int igb_sw_init(struct igb_adapter *);
113static int igb_open(struct net_device *);
114static int igb_close(struct net_device *);
115static void igb_configure_tx(struct igb_adapter *);
116static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 117static void igb_clean_all_tx_rings(struct igb_adapter *);
118static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 119static void igb_clean_tx_ring(struct igb_ring *);
120static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 121static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 122static void igb_update_phy_info(unsigned long);
123static void igb_watchdog(unsigned long);
124static void igb_watchdog_task(struct work_struct *);
cd392f5c 125static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 126static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
127 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 128static int igb_change_mtu(struct net_device *, int);
129static int igb_set_mac(struct net_device *, void *);
68d480c4 130static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 131static irqreturn_t igb_intr(int irq, void *);
132static irqreturn_t igb_intr_msi(int irq, void *);
133static irqreturn_t igb_msix_other(int irq, void *);
047e0030 134static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 135#ifdef CONFIG_IGB_DCA
047e0030 136static void igb_update_dca(struct igb_q_vector *);
fe4506b6 137static void igb_setup_dca(struct igb_adapter *);
421e02f0 138#endif /* CONFIG_IGB_DCA */
047e0030 139static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 140static int igb_poll(struct napi_struct *, int);
cd392f5c 141static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 142static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
143static void igb_tx_timeout(struct net_device *);
144static void igb_reset_task(struct work_struct *);
b2cb09b1 145static void igb_vlan_mode(struct net_device *netdev, u32 features);
9d5c8243
AK		 146static void igb_vlan_rx_add_vid(struct net_device *, u16);
147static void igb_vlan_rx_kill_vid(struct net_device *, u16);
148static void igb_restore_vlan(struct igb_adapter *);
26ad9178 149static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 150static void igb_ping_all_vfs(struct igb_adapter *);
151static void igb_msg_task(struct igb_adapter *);
4ae196df 152static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 153static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 154static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 155static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
156static int igb_ndo_set_vf_vlan(struct net_device *netdev,
157 int vf, u16 vlan, u8 qos);
158static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
159static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
160 struct ifla_vf_info *ivi);
17dc566c 161static void igb_check_vf_rate_limit(struct igb_adapter *);
9d5c8243 162
9d5c8243 163#ifdef CONFIG_PM
3fe7c4c9 164static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 165static int igb_resume(struct pci_dev *);
166#endif
167static void igb_shutdown(struct pci_dev *);
421e02f0 168#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 169static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
170static struct notifier_block dca_notifier = {
171 .notifier_call = igb_notify_dca,
172 .next = NULL,
173 .priority = 0
174};
175#endif
9d5c8243
AK		 176#ifdef CONFIG_NET_POLL_CONTROLLER
177/* for netdump / net console */
178static void igb_netpoll(struct net_device *);
179#endif
37680117 180#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 181static unsigned int max_vfs = 0;
182module_param(max_vfs, uint, 0);
183MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
184 "per physical function");
185#endif /* CONFIG_PCI_IOV */
186
9d5c8243
AK		 187static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
188 pci_channel_state_t);
189static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
190static void igb_io_resume(struct pci_dev *);
191
192static struct pci_error_handlers igb_err_handler = {
193 .error_detected = igb_io_error_detected,
194 .slot_reset = igb_io_slot_reset,
195 .resume = igb_io_resume,
196};
197
198
199static struct pci_driver igb_driver = {
200 .name = igb_driver_name,
201 .id_table = igb_pci_tbl,
202 .probe = igb_probe,
203 .remove = __devexit_p(igb_remove),
204#ifdef CONFIG_PM
25985edc 205 /* Power Management Hooks */
9d5c8243
AK		 206 .suspend = igb_suspend,
207 .resume = igb_resume,
208#endif
209 .shutdown = igb_shutdown,
210 .err_handler = &igb_err_handler
211};
212
213MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
214MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
215MODULE_LICENSE("GPL");
216MODULE_VERSION(DRV_VERSION);
217
c97ec42a
TI		 218struct igb_reg_info {
219 u32 ofs;
220 char *name;
221};
222
223static const struct igb_reg_info igb_reg_info_tbl[] = {
224
225 /* General Registers */
226 {E1000_CTRL, "CTRL"},
227 {E1000_STATUS, "STATUS"},
228 {E1000_CTRL_EXT, "CTRL_EXT"},
229
230 /* Interrupt Registers */
231 {E1000_ICR, "ICR"},
232
233 /* RX Registers */
234 {E1000_RCTL, "RCTL"},
235 {E1000_RDLEN(0), "RDLEN"},
236 {E1000_RDH(0), "RDH"},
237 {E1000_RDT(0), "RDT"},
238 {E1000_RXDCTL(0), "RXDCTL"},
239 {E1000_RDBAL(0), "RDBAL"},
240 {E1000_RDBAH(0), "RDBAH"},
241
242 /* TX Registers */
243 {E1000_TCTL, "TCTL"},
244 {E1000_TDBAL(0), "TDBAL"},
245 {E1000_TDBAH(0), "TDBAH"},
246 {E1000_TDLEN(0), "TDLEN"},
247 {E1000_TDH(0), "TDH"},
248 {E1000_TDT(0), "TDT"},
249 {E1000_TXDCTL(0), "TXDCTL"},
250 {E1000_TDFH, "TDFH"},
251 {E1000_TDFT, "TDFT"},
252 {E1000_TDFHS, "TDFHS"},
253 {E1000_TDFPC, "TDFPC"},
254
255 /* List Terminator */
256 {}
257};
258
259/*
260 * igb_regdump - register printout routine
261 */
262static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
263{
264 int n = 0;
265 char rname[16];
266 u32 regs[8];
267
268 switch (reginfo->ofs) {
269 case E1000_RDLEN(0):
270 for (n = 0; n < 4; n++)
271 regs[n] = rd32(E1000_RDLEN(n));
272 break;
273 case E1000_RDH(0):
274 for (n = 0; n < 4; n++)
275 regs[n] = rd32(E1000_RDH(n));
276 break;
277 case E1000_RDT(0):
278 for (n = 0; n < 4; n++)
279 regs[n] = rd32(E1000_RDT(n));
280 break;
281 case E1000_RXDCTL(0):
282 for (n = 0; n < 4; n++)
283 regs[n] = rd32(E1000_RXDCTL(n));
284 break;
285 case E1000_RDBAL(0):
286 for (n = 0; n < 4; n++)
287 regs[n] = rd32(E1000_RDBAL(n));
288 break;
289 case E1000_RDBAH(0):
290 for (n = 0; n < 4; n++)
291 regs[n] = rd32(E1000_RDBAH(n));
292 break;
293 case E1000_TDBAL(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RDBAL(n));
296 break;
297 case E1000_TDBAH(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_TDBAH(n));
300 break;
301 case E1000_TDLEN(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_TDLEN(n));
304 break;
305 case E1000_TDH(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_TDH(n));
308 break;
309 case E1000_TDT(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_TDT(n));
312 break;
313 case E1000_TXDCTL(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_TXDCTL(n));
316 break;
317 default:
318 printk(KERN_INFO "%-15s %08x\n",
319 reginfo->name, rd32(reginfo->ofs));
320 return;
321 }
322
323 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
324 printk(KERN_INFO "%-15s ", rname);
325 for (n = 0; n < 4; n++)
326 printk(KERN_CONT "%08x ", regs[n]);
327 printk(KERN_CONT "\n");
328}
329
330/*
331 * igb_dump - Print registers, tx-rings and rx-rings
332 */
333static void igb_dump(struct igb_adapter *adapter)
334{
335 struct net_device *netdev = adapter->netdev;
336 struct e1000_hw *hw = &adapter->hw;
337 struct igb_reg_info *reginfo;
338 int n = 0;
339 struct igb_ring *tx_ring;
340 union e1000_adv_tx_desc *tx_desc;
341 struct my_u0 { u64 a; u64 b; } *u0;
342 struct igb_buffer *buffer_info;
343 struct igb_ring *rx_ring;
344 union e1000_adv_rx_desc *rx_desc;
345 u32 staterr;
346 int i = 0;
347
348 if (!netif_msg_hw(adapter))
349 return;
350
351 /* Print netdevice Info */
352 if (netdev) {
353 dev_info(&adapter->pdev->dev, "Net device Info\n");
354 printk(KERN_INFO "Device Name state "
355 "trans_start last_rx\n");
356 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
357 netdev->name,
358 netdev->state,
359 netdev->trans_start,
360 netdev->last_rx);
361 }
362
363 /* Print Registers */
364 dev_info(&adapter->pdev->dev, "Register Dump\n");
365 printk(KERN_INFO " Register Name Value\n");
366 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
367 reginfo->name; reginfo++) {
368 igb_regdump(hw, reginfo);
369 }
370
371 /* Print TX Ring Summary */
372 if (!netdev || !netif_running(netdev))
373 goto exit;
374
375 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
376 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]"
377 " leng ntw timestamp\n");
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
381 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
382 n, tx_ring->next_to_use, tx_ring->next_to_clean,
383 (u64)buffer_info->dma,
384 buffer_info->length,
385 buffer_info->next_to_watch,
386 (u64)buffer_info->time_stamp);
387 }
388
389 /* Print TX Rings */
390 if (!netif_msg_tx_done(adapter))
391 goto rx_ring_summary;
392
393 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
394
395 /* Transmit Descriptor Formats
396 *
397 * Advanced Transmit Descriptor
398 * +--------------------------------------------------------------+
399 * 0 | Buffer Address [63:0] |
400 * +--------------------------------------------------------------+
401 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
402 * +--------------------------------------------------------------+
403 * 63 46 45 40 39 38 36 35 32 31 24 15 0
404 */
405
406 for (n = 0; n < adapter->num_tx_queues; n++) {
407 tx_ring = adapter->tx_ring[n];
408 printk(KERN_INFO "------------------------------------\n");
409 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
410 printk(KERN_INFO "------------------------------------\n");
411 printk(KERN_INFO "T [desc] [address 63:0 ] "
412 "[PlPOCIStDDM Ln] [bi->dma ] "
413 "leng ntw timestamp bi->skb\n");
414
415 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
416 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
417 buffer_info = &tx_ring->buffer_info[i];
418 u0 = (struct my_u0 *)tx_desc;
419 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
420 " %04X %3X %016llX %p", i,
421 le64_to_cpu(u0->a),
422 le64_to_cpu(u0->b),
423 (u64)buffer_info->dma,
424 buffer_info->length,
425 buffer_info->next_to_watch,
426 (u64)buffer_info->time_stamp,
427 buffer_info->skb);
428 if (i == tx_ring->next_to_use &&
429 i == tx_ring->next_to_clean)
430 printk(KERN_CONT " NTC/U\n");
431 else if (i == tx_ring->next_to_use)
432 printk(KERN_CONT " NTU\n");
433 else if (i == tx_ring->next_to_clean)
434 printk(KERN_CONT " NTC\n");
435 else
436 printk(KERN_CONT "\n");
437
438 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
439 print_hex_dump(KERN_INFO, "",
440 DUMP_PREFIX_ADDRESS,
441 16, 1, phys_to_virt(buffer_info->dma),
442 buffer_info->length, true);
443 }
444 }
445
446 /* Print RX Rings Summary */
447rx_ring_summary:
448 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
449 printk(KERN_INFO "Queue [NTU] [NTC]\n");
450 for (n = 0; n < adapter->num_rx_queues; n++) {
451 rx_ring = adapter->rx_ring[n];
452 printk(KERN_INFO " %5d %5X %5X\n", n,
453 rx_ring->next_to_use, rx_ring->next_to_clean);
454 }
455
456 /* Print RX Rings */
457 if (!netif_msg_rx_status(adapter))
458 goto exit;
459
460 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
461
462 /* Advanced Receive Descriptor (Read) Format
463 * 63 1 0
464 * +-----------------------------------------------------+
465 * 0 | Packet Buffer Address [63:1] |A0/NSE|
466 * +----------------------------------------------+------+
467 * 8 | Header Buffer Address [63:1] | DD |
468 * +-----------------------------------------------------+
469 *
470 *
471 * Advanced Receive Descriptor (Write-Back) Format
472 *
473 * 63 48 47 32 31 30 21 20 17 16 4 3 0
474 * +------------------------------------------------------+
475 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
476 * | Checksum Ident | | | | Type | Type |
477 * +------------------------------------------------------+
478 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
479 * +------------------------------------------------------+
480 * 63 48 47 32 31 20 19 0
481 */
482
483 for (n = 0; n < adapter->num_rx_queues; n++) {
484 rx_ring = adapter->rx_ring[n];
485 printk(KERN_INFO "------------------------------------\n");
486 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
487 printk(KERN_INFO "------------------------------------\n");
488 printk(KERN_INFO "R [desc] [ PktBuf A0] "
489 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
490 "<-- Adv Rx Read format\n");
491 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
492 "[vl er S cks ln] ---------------- [bi->skb] "
493 "<-- Adv Rx Write-Back format\n");
494
495 for (i = 0; i < rx_ring->count; i++) {
496 buffer_info = &rx_ring->buffer_info[i];
497 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
498 u0 = (struct my_u0 *)rx_desc;
499 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
500 if (staterr & E1000_RXD_STAT_DD) {
501 /* Descriptor Done */
502 printk(KERN_INFO "RWB[0x%03X] %016llX "
503 "%016llX ---------------- %p", i,
504 le64_to_cpu(u0->a),
505 le64_to_cpu(u0->b),
506 buffer_info->skb);
507 } else {
508 printk(KERN_INFO "R [0x%03X] %016llX "
509 "%016llX %016llX %p", i,
510 le64_to_cpu(u0->a),
511 le64_to_cpu(u0->b),
512 (u64)buffer_info->dma,
513 buffer_info->skb);
514
515 if (netif_msg_pktdata(adapter)) {
516 print_hex_dump(KERN_INFO, "",
517 DUMP_PREFIX_ADDRESS,
518 16, 1,
519 phys_to_virt(buffer_info->dma),
44390ca6
AD		 520 IGB_RX_HDR_LEN, true);
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS,
523 16, 1,
524 phys_to_virt(
525 buffer_info->page_dma +
526 buffer_info->page_offset),
527 PAGE_SIZE/2, true);
c97ec42a
TI		 528 }
529 }
530
531 if (i == rx_ring->next_to_use)
532 printk(KERN_CONT " NTU\n");
533 else if (i == rx_ring->next_to_clean)
534 printk(KERN_CONT " NTC\n");
535 else
536 printk(KERN_CONT "\n");
537
538 }
539 }
540
541exit:
542 return;
543}
544
545
38c845c7
PO		 546/**
547 * igb_read_clock - read raw cycle counter (to be used by time counter)
548 */
549static cycle_t igb_read_clock(const struct cyclecounter *tc)
550{
551 struct igb_adapter *adapter =
552 container_of(tc, struct igb_adapter, cycles);
553 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 554 u64 stamp = 0;
555 int shift = 0;
38c845c7 556
55cac248
AD		 557 /*
558 * The timestamp latches on lowest register read. For the 82580
559 * the lowest register is SYSTIMR instead of SYSTIML. However we never
560 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
561 */
562 if (hw->mac.type == e1000_82580) {
563 stamp = rd32(E1000_SYSTIMR) >> 8;
564 shift = IGB_82580_TSYNC_SHIFT;
565 }
566
c5b9bd5e
AD		 567 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
568 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 569 return stamp;
570}
571
9d5c8243 572/**
c041076a 573 * igb_get_hw_dev - return device
9d5c8243
AK		 574 * used by hardware layer to print debugging information
575 **/
c041076a 576struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 577{
578 struct igb_adapter *adapter = hw->back;
c041076a 579 return adapter->netdev;
9d5c8243 580}
38c845c7 581
9d5c8243
AK		 582/**
583 * igb_init_module - Driver Registration Routine
584 *
585 * igb_init_module is the first routine called when the driver is
586 * loaded. All it does is register with the PCI subsystem.
587 **/
588static int __init igb_init_module(void)
589{
590 int ret;
591 printk(KERN_INFO "%s - version %s\n",
592 igb_driver_string, igb_driver_version);
593
594 printk(KERN_INFO "%s\n", igb_copyright);
595
421e02f0 596#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 597 dca_register_notify(&dca_notifier);
598#endif
bbd98fe4 599 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 600 return ret;
601}
602
603module_init(igb_init_module);
604
605/**
606 * igb_exit_module - Driver Exit Cleanup Routine
607 *
608 * igb_exit_module is called just before the driver is removed
609 * from memory.
610 **/
611static void __exit igb_exit_module(void)
612{
421e02f0 613#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 614 dca_unregister_notify(&dca_notifier);
615#endif
9d5c8243
AK		 616 pci_unregister_driver(&igb_driver);
617}
618
619module_exit(igb_exit_module);
620
26bc19ec
AD		 621#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
622/**
623 * igb_cache_ring_register - Descriptor ring to register mapping
624 * @adapter: board private structure to initialize
625 *
626 * Once we know the feature-set enabled for the device, we'll cache
627 * the register offset the descriptor ring is assigned to.
628 **/
629static void igb_cache_ring_register(struct igb_adapter *adapter)
630{
ee1b9f06 631 int i = 0, j = 0;
047e0030 632 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 633
634 switch (adapter->hw.mac.type) {
635 case e1000_82576:
636 /* The queues are allocated for virtualization such that VF 0
637 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
638 * In order to avoid collision we start at the first free queue
639 * and continue consuming queues in the same sequence
640 */
ee1b9f06 641 if (adapter->vfs_allocated_count) {
a99955fc 642 for (; i < adapter->rss_queues; i++)
3025a446
AD		 643 adapter->rx_ring[i]->reg_idx = rbase_offset +
644 Q_IDX_82576(i);
ee1b9f06 645 }
26bc19ec 646 case e1000_82575:
55cac248 647 case e1000_82580:
d2ba2ed8 648 case e1000_i350:
26bc19ec 649 default:
ee1b9f06 650 for (; i < adapter->num_rx_queues; i++)
3025a446 651 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 652 for (; j < adapter->num_tx_queues; j++)
3025a446 653 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 654 break;
655 }
656}
657
047e0030
AD		 658static void igb_free_queues(struct igb_adapter *adapter)
659{
3025a446 660 int i;
047e0030 661
3025a446
AD		 662 for (i = 0; i < adapter->num_tx_queues; i++) {
663 kfree(adapter->tx_ring[i]);
664 adapter->tx_ring[i] = NULL;
665 }
666 for (i = 0; i < adapter->num_rx_queues; i++) {
667 kfree(adapter->rx_ring[i]);
668 adapter->rx_ring[i] = NULL;
669 }
047e0030
AD		 670 adapter->num_rx_queues = 0;
671 adapter->num_tx_queues = 0;
672}
673
9d5c8243
AK		 674/**
675 * igb_alloc_queues - Allocate memory for all rings
676 * @adapter: board private structure to initialize
677 *
678 * We allocate one ring per queue at run-time since we don't know the
679 * number of queues at compile-time.
680 **/
681static int igb_alloc_queues(struct igb_adapter *adapter)
682{
3025a446 683 struct igb_ring *ring;
9d5c8243
AK		 684 int i;
685
661086df 686 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 687 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
688 if (!ring)
689 goto err;
68fd9910 690 ring->count = adapter->tx_ring_count;
661086df 691 ring->queue_index = i;
59d71989 692 ring->dev = &adapter->pdev->dev;
e694e964 693 ring->netdev = adapter->netdev;
85ad76b2
AD		 694 /* For 82575, context index must be unique per ring. */
695 if (adapter->hw.mac.type == e1000_82575)
696 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 697 adapter->tx_ring[i] = ring;
661086df 698 }
85ad76b2 699
9d5c8243 700 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 701 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
702 if (!ring)
703 goto err;
68fd9910 704 ring->count = adapter->rx_ring_count;
844290e5 705 ring->queue_index = i;
59d71989 706 ring->dev = &adapter->pdev->dev;
e694e964 707 ring->netdev = adapter->netdev;
85ad76b2
AD		 708 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
709 /* set flag indicating ring supports SCTP checksum offload */
710 if (adapter->hw.mac.type >= e1000_82576)
711 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 712 adapter->rx_ring[i] = ring;
9d5c8243 713 }
26bc19ec
AD		 714
715 igb_cache_ring_register(adapter);
9d5c8243 716
047e0030 717 return 0;
a88f10ec 718
047e0030
AD		 719err:
720 igb_free_queues(adapter);
d1a8c9e1 721
047e0030 722 return -ENOMEM;
a88f10ec
AD		 723}
724
9d5c8243 725#define IGB_N0_QUEUE -1
047e0030 726static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 727{
728 u32 msixbm = 0;
047e0030 729 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 730 struct e1000_hw *hw = &adapter->hw;
2d064c06 731 u32 ivar, index;
047e0030
AD		 732 int rx_queue = IGB_N0_QUEUE;
733 int tx_queue = IGB_N0_QUEUE;
734
735 if (q_vector->rx_ring)
736 rx_queue = q_vector->rx_ring->reg_idx;
737 if (q_vector->tx_ring)
738 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 739
740 switch (hw->mac.type) {
741 case e1000_82575:
9d5c8243
AK		 742 /* The 82575 assigns vectors using a bitmask, which matches the
743 bitmask for the EICR/EIMS/EIMC registers. To assign one
744 or more queues to a vector, we write the appropriate bits
745 into the MSIXBM register for that vector. */
047e0030 746 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 747 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 748 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 749 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 750 if (!adapter->msix_entries && msix_vector == 0)
751 msixbm |= E1000_EIMS_OTHER;
9d5c8243 752 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 753 q_vector->eims_value = msixbm;
2d064c06
AD		 754 break;
755 case e1000_82576:
26bc19ec 756 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 757 Each queue has a single entry in the table to which we write
758 a vector number along with a "valid" bit. Sadly, the layout
759 of the table is somewhat counterintuitive. */
760 if (rx_queue > IGB_N0_QUEUE) {
047e0030 761 index = (rx_queue & 0x7);
2d064c06 762 ivar = array_rd32(E1000_IVAR0, index);
047e0030 763 if (rx_queue < 8) {
26bc19ec
AD		 764 /* vector goes into low byte of register */
765 ivar = ivar & 0xFFFFFF00;
766 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 767 } else {
768 /* vector goes into third byte of register */
769 ivar = ivar & 0xFF00FFFF;
770 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 771 }
2d064c06
AD		 772 array_wr32(E1000_IVAR0, index, ivar);
773 }
774 if (tx_queue > IGB_N0_QUEUE) {
047e0030 775 index = (tx_queue & 0x7);
2d064c06 776 ivar = array_rd32(E1000_IVAR0, index);
047e0030 777 if (tx_queue < 8) {
26bc19ec
AD		 778 /* vector goes into second byte of register */
779 ivar = ivar & 0xFFFF00FF;
780 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 781 } else {
782 /* vector goes into high byte of register */
783 ivar = ivar & 0x00FFFFFF;
784 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 785 }
2d064c06
AD		 786 array_wr32(E1000_IVAR0, index, ivar);
787 }
047e0030 788 q_vector->eims_value = 1 << msix_vector;
2d064c06 789 break;
55cac248 790 case e1000_82580:
d2ba2ed8 791 case e1000_i350:
55cac248
AD		 792 /* 82580 uses the same table-based approach as 82576 but has fewer
793 entries as a result we carry over for queues greater than 4. */
794 if (rx_queue > IGB_N0_QUEUE) {
795 index = (rx_queue >> 1);
796 ivar = array_rd32(E1000_IVAR0, index);
797 if (rx_queue & 0x1) {
798 /* vector goes into third byte of register */
799 ivar = ivar & 0xFF00FFFF;
800 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
801 } else {
802 /* vector goes into low byte of register */
803 ivar = ivar & 0xFFFFFF00;
804 ivar |= msix_vector | E1000_IVAR_VALID;
805 }
806 array_wr32(E1000_IVAR0, index, ivar);
807 }
808 if (tx_queue > IGB_N0_QUEUE) {
809 index = (tx_queue >> 1);
810 ivar = array_rd32(E1000_IVAR0, index);
811 if (tx_queue & 0x1) {
812 /* vector goes into high byte of register */
813 ivar = ivar & 0x00FFFFFF;
814 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
815 } else {
816 /* vector goes into second byte of register */
817 ivar = ivar & 0xFFFF00FF;
818 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
819 }
820 array_wr32(E1000_IVAR0, index, ivar);
821 }
822 q_vector->eims_value = 1 << msix_vector;
823 break;
2d064c06
AD		 824 default:
825 BUG();
826 break;
827 }
26b39276
AD		 828
829 /* add q_vector eims value to global eims_enable_mask */
830 adapter->eims_enable_mask |= q_vector->eims_value;
831
832 /* configure q_vector to set itr on first interrupt */
833 q_vector->set_itr = 1;
9d5c8243
AK		 834}
835
836/**
837 * igb_configure_msix - Configure MSI-X hardware
838 *
839 * igb_configure_msix sets up the hardware to properly
840 * generate MSI-X interrupts.
841 **/
842static void igb_configure_msix(struct igb_adapter *adapter)
843{
844 u32 tmp;
845 int i, vector = 0;
846 struct e1000_hw *hw = &adapter->hw;
847
848 adapter->eims_enable_mask = 0;
9d5c8243
AK		 849
850 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 851 switch (hw->mac.type) {
852 case e1000_82575:
9d5c8243
AK		 853 tmp = rd32(E1000_CTRL_EXT);
854 /* enable MSI-X PBA support*/
855 tmp |= E1000_CTRL_EXT_PBA_CLR;
856
857 /* Auto-Mask interrupts upon ICR read. */
858 tmp |= E1000_CTRL_EXT_EIAME;
859 tmp |= E1000_CTRL_EXT_IRCA;
860
861 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 862
863 /* enable msix_other interrupt */
864 array_wr32(E1000_MSIXBM(0), vector++,
865 E1000_EIMS_OTHER);
844290e5 866 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 867
2d064c06
AD		 868 break;
869
870 case e1000_82576:
55cac248 871 case e1000_82580:
d2ba2ed8 872 case e1000_i350:
047e0030
AD		 873 /* Turn on MSI-X capability first, or our settings
874 * won't stick. And it will take days to debug. */
875 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
876 E1000_GPIE_PBA | E1000_GPIE_EIAME |
877 E1000_GPIE_NSICR);
878
879 /* enable msix_other interrupt */
880 adapter->eims_other = 1 << vector;
2d064c06 881 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 882
047e0030 883 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 884 break;
885 default:
886 /* do nothing, since nothing else supports MSI-X */
887 break;
888 } /* switch (hw->mac.type) */
047e0030
AD		 889
890 adapter->eims_enable_mask |= adapter->eims_other;
891
26b39276
AD		 892 for (i = 0; i < adapter->num_q_vectors; i++)
893 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 894
9d5c8243
AK		 895 wrfl();
896}
897
898/**
899 * igb_request_msix - Initialize MSI-X interrupts
900 *
901 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
902 * kernel.
903 **/
904static int igb_request_msix(struct igb_adapter *adapter)
905{
906 struct net_device *netdev = adapter->netdev;
047e0030 907 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 908 int i, err = 0, vector = 0;
909
047e0030 910 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 911 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 912 if (err)
913 goto out;
914 vector++;
915
916 for (i = 0; i < adapter->num_q_vectors; i++) {
917 struct igb_q_vector *q_vector = adapter->q_vector[i];
918
919 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
920
921 if (q_vector->rx_ring && q_vector->tx_ring)
922 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
923 q_vector->rx_ring->queue_index);
924 else if (q_vector->tx_ring)
925 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
926 q_vector->tx_ring->queue_index);
927 else if (q_vector->rx_ring)
928 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
929 q_vector->rx_ring->queue_index);
9d5c8243 930 else
047e0030
AD		 931 sprintf(q_vector->name, "%s-unused", netdev->name);
932
9d5c8243 933 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 934 igb_msix_ring, 0, q_vector->name,
047e0030 935 q_vector);
9d5c8243
AK		 936 if (err)
937 goto out;
9d5c8243
AK		 938 vector++;
939 }
940
9d5c8243
AK		 941 igb_configure_msix(adapter);
942 return 0;
943out:
944 return err;
945}
946
947static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
948{
949 if (adapter->msix_entries) {
950 pci_disable_msix(adapter->pdev);
951 kfree(adapter->msix_entries);
952 adapter->msix_entries = NULL;
047e0030 953 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 954 pci_disable_msi(adapter->pdev);
047e0030 955 }
9d5c8243
AK		 956}
957
047e0030
AD		 958/**
959 * igb_free_q_vectors - Free memory allocated for interrupt vectors
960 * @adapter: board private structure to initialize
961 *
962 * This function frees the memory allocated to the q_vectors. In addition if
963 * NAPI is enabled it will delete any references to the NAPI struct prior
964 * to freeing the q_vector.
965 **/
966static void igb_free_q_vectors(struct igb_adapter *adapter)
967{
968 int v_idx;
969
970 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
971 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
972 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 973 if (!q_vector)
974 continue;
047e0030
AD		 975 netif_napi_del(&q_vector->napi);
976 kfree(q_vector);
977 }
978 adapter->num_q_vectors = 0;
979}
980
981/**
982 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
983 *
984 * This function resets the device so that it has 0 rx queues, tx queues, and
985 * MSI-X interrupts allocated.
986 */
987static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
988{
989 igb_free_queues(adapter);
990 igb_free_q_vectors(adapter);
991 igb_reset_interrupt_capability(adapter);
992}
9d5c8243
AK		 993
994/**
995 * igb_set_interrupt_capability - set MSI or MSI-X if supported
996 *
997 * Attempt to configure interrupts using the best available
998 * capabilities of the hardware and kernel.
999 **/
21adef3e 1000static int igb_set_interrupt_capability(struct igb_adapter *adapter)
9d5c8243
AK		 1001{
1002 int err;
1003 int numvecs, i;
1004
83b7180d 1005 /* Number of supported queues. */
a99955fc 1006 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1007 if (adapter->vfs_allocated_count)
1008 adapter->num_tx_queues = 1;
1009 else
1010 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1011
047e0030
AD		 1012 /* start with one vector for every rx queue */
1013 numvecs = adapter->num_rx_queues;
1014
3ad2f3fb 1015 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1016 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1017 numvecs += adapter->num_tx_queues;
047e0030
AD		 1018
1019 /* store the number of vectors reserved for queues */
1020 adapter->num_q_vectors = numvecs;
1021
1022 /* add 1 vector for link status interrupts */
1023 numvecs++;
9d5c8243
AK		 1024 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1025 GFP_KERNEL);
1026 if (!adapter->msix_entries)
1027 goto msi_only;
1028
1029 for (i = 0; i < numvecs; i++)
1030 adapter->msix_entries[i].entry = i;
1031
1032 err = pci_enable_msix(adapter->pdev,
1033 adapter->msix_entries,
1034 numvecs);
1035 if (err == 0)
34a20e89 1036 goto out;
9d5c8243
AK		 1037
1038 igb_reset_interrupt_capability(adapter);
1039
1040 /* If we can't do MSI-X, try MSI */
1041msi_only:
2a3abf6d
AD		 1042#ifdef CONFIG_PCI_IOV
1043 /* disable SR-IOV for non MSI-X configurations */
1044 if (adapter->vf_data) {
1045 struct e1000_hw *hw = &adapter->hw;
1046 /* disable iov and allow time for transactions to clear */
1047 pci_disable_sriov(adapter->pdev);
1048 msleep(500);
1049
1050 kfree(adapter->vf_data);
1051 adapter->vf_data = NULL;
1052 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1053 wrfl();
2a3abf6d
AD		 1054 msleep(100);
1055 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1056 }
1057#endif
4fc82adf 1058 adapter->vfs_allocated_count = 0;
a99955fc 1059 adapter->rss_queues = 1;
4fc82adf 1060 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1061 adapter->num_rx_queues = 1;
661086df 1062 adapter->num_tx_queues = 1;
047e0030 1063 adapter->num_q_vectors = 1;
9d5c8243 1064 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1065 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1066out:
21adef3e
BH		 1067 /* Notify the stack of the (possibly) reduced queue counts. */
1068 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
1069 return netif_set_real_num_rx_queues(adapter->netdev,
1070 adapter->num_rx_queues);
9d5c8243
AK		 1071}
1072
047e0030
AD		 1073/**
1074 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1075 * @adapter: board private structure to initialize
1076 *
1077 * We allocate one q_vector per queue interrupt. If allocation fails we
1078 * return -ENOMEM.
1079 **/
1080static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1081{
1082 struct igb_q_vector *q_vector;
1083 struct e1000_hw *hw = &adapter->hw;
1084 int v_idx;
1085
1086 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1087 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
1088 if (!q_vector)
1089 goto err_out;
1090 q_vector->adapter = adapter;
047e0030
AD		 1091 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1092 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1093 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1094 adapter->q_vector[v_idx] = q_vector;
1095 }
1096 return 0;
1097
1098err_out:
fe0592b4 1099 igb_free_q_vectors(adapter);
047e0030
AD		 1100 return -ENOMEM;
1101}
1102
1103static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1104 int ring_idx, int v_idx)
1105{
3025a446 1106 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1107
3025a446 1108 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 1109 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 1110 q_vector->itr_val = adapter->rx_itr_setting;
1111 if (q_vector->itr_val && q_vector->itr_val <= 3)
1112 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1113}
1114
1115static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1116 int ring_idx, int v_idx)
1117{
3025a446 1118 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1119
3025a446 1120 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 1121 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 1122 q_vector->itr_val = adapter->tx_itr_setting;
1123 if (q_vector->itr_val && q_vector->itr_val <= 3)
1124 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1125}
1126
1127/**
1128 * igb_map_ring_to_vector - maps allocated queues to vectors
1129 *
1130 * This function maps the recently allocated queues to vectors.
1131 **/
1132static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1133{
1134 int i;
1135 int v_idx = 0;
1136
1137 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1138 (adapter->num_q_vectors < adapter->num_tx_queues))
1139 return -ENOMEM;
1140
1141 if (adapter->num_q_vectors >=
1142 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1143 for (i = 0; i < adapter->num_rx_queues; i++)
1144 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1145 for (i = 0; i < adapter->num_tx_queues; i++)
1146 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1147 } else {
1148 for (i = 0; i < adapter->num_rx_queues; i++) {
1149 if (i < adapter->num_tx_queues)
1150 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1151 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1152 }
1153 for (; i < adapter->num_tx_queues; i++)
1154 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1155 }
1156 return 0;
1157}
1158
1159/**
1160 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1161 *
1162 * This function initializes the interrupts and allocates all of the queues.
1163 **/
1164static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1165{
1166 struct pci_dev *pdev = adapter->pdev;
1167 int err;
1168
21adef3e
BH		 1169 err = igb_set_interrupt_capability(adapter);
1170 if (err)
1171 return err;
047e0030
AD		 1172
1173 err = igb_alloc_q_vectors(adapter);
1174 if (err) {
1175 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1176 goto err_alloc_q_vectors;
1177 }
1178
1179 err = igb_alloc_queues(adapter);
1180 if (err) {
1181 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1182 goto err_alloc_queues;
1183 }
1184
1185 err = igb_map_ring_to_vector(adapter);
1186 if (err) {
1187 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1188 goto err_map_queues;
1189 }
1190
1191
1192 return 0;
1193err_map_queues:
1194 igb_free_queues(adapter);
1195err_alloc_queues:
1196 igb_free_q_vectors(adapter);
1197err_alloc_q_vectors:
1198 igb_reset_interrupt_capability(adapter);
1199 return err;
1200}
1201
9d5c8243
AK		 1202/**
1203 * igb_request_irq - initialize interrupts
1204 *
1205 * Attempts to configure interrupts using the best available
1206 * capabilities of the hardware and kernel.
1207 **/
1208static int igb_request_irq(struct igb_adapter *adapter)
1209{
1210 struct net_device *netdev = adapter->netdev;
047e0030 1211 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1212 int err = 0;
1213
1214 if (adapter->msix_entries) {
1215 err = igb_request_msix(adapter);
844290e5 1216 if (!err)
9d5c8243 1217 goto request_done;
9d5c8243 1218 /* fall back to MSI */
047e0030 1219 igb_clear_interrupt_scheme(adapter);
9d5c8243 1220 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1221 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1222 igb_free_all_tx_resources(adapter);
1223 igb_free_all_rx_resources(adapter);
047e0030 1224 adapter->num_tx_queues = 1;
9d5c8243 1225 adapter->num_rx_queues = 1;
047e0030
AD		 1226 adapter->num_q_vectors = 1;
1227 err = igb_alloc_q_vectors(adapter);
1228 if (err) {
1229 dev_err(&pdev->dev,
1230 "Unable to allocate memory for vectors\n");
1231 goto request_done;
1232 }
1233 err = igb_alloc_queues(adapter);
1234 if (err) {
1235 dev_err(&pdev->dev,
1236 "Unable to allocate memory for queues\n");
1237 igb_free_q_vectors(adapter);
1238 goto request_done;
1239 }
1240 igb_setup_all_tx_resources(adapter);
1241 igb_setup_all_rx_resources(adapter);
844290e5 1242 } else {
feeb2721 1243 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 1244 }
844290e5 1245
7dfc16fa 1246 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 1247 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 1248 netdev->name, adapter);
9d5c8243
AK		 1249 if (!err)
1250 goto request_done;
047e0030 1251
9d5c8243
AK		 1252 /* fall back to legacy interrupts */
1253 igb_reset_interrupt_capability(adapter);
7dfc16fa 1254 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1255 }
1256
a0607fd3 1257 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1258 netdev->name, adapter);
9d5c8243 1259
6cb5e577 1260 if (err)
9d5c8243
AK		 1261 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
1262 err);
9d5c8243
AK		 1263
1264request_done:
1265 return err;
1266}
1267
1268static void igb_free_irq(struct igb_adapter *adapter)
1269{
9d5c8243
AK		 1270 if (adapter->msix_entries) {
1271 int vector = 0, i;
1272
047e0030 1273 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1274
047e0030
AD		 1275 for (i = 0; i < adapter->num_q_vectors; i++) {
1276 struct igb_q_vector *q_vector = adapter->q_vector[i];
1277 free_irq(adapter->msix_entries[vector++].vector,
1278 q_vector);
1279 }
1280 } else {
1281 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1282 }
9d5c8243
AK		 1283}
1284
1285/**
1286 * igb_irq_disable - Mask off interrupt generation on the NIC
1287 * @adapter: board private structure
1288 **/
1289static void igb_irq_disable(struct igb_adapter *adapter)
1290{
1291 struct e1000_hw *hw = &adapter->hw;
1292
25568a53
AD		 1293 /*
1294 * we need to be careful when disabling interrupts. The VFs are also
1295 * mapped into these registers and so clearing the bits can cause
1296 * issues on the VF drivers so we only need to clear what we set
1297 */
9d5c8243 1298 if (adapter->msix_entries) {
2dfd1212
AD		 1299 u32 regval = rd32(E1000_EIAM);
1300 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1301 wr32(E1000_EIMC, adapter->eims_enable_mask);
1302 regval = rd32(E1000_EIAC);
1303 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1304 }
844290e5
PW		 1305
1306 wr32(E1000_IAM, 0);
9d5c8243
AK		 1307 wr32(E1000_IMC, ~0);
1308 wrfl();
81a61859
ET		 1309 if (adapter->msix_entries) {
1310 int i;
1311 for (i = 0; i < adapter->num_q_vectors; i++)
1312 synchronize_irq(adapter->msix_entries[i].vector);
1313 } else {
1314 synchronize_irq(adapter->pdev->irq);
1315 }
9d5c8243
AK		 1316}
1317
1318/**
1319 * igb_irq_enable - Enable default interrupt generation settings
1320 * @adapter: board private structure
1321 **/
1322static void igb_irq_enable(struct igb_adapter *adapter)
1323{
1324 struct e1000_hw *hw = &adapter->hw;
1325
1326 if (adapter->msix_entries) {
25568a53 1327 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 1328 u32 regval = rd32(E1000_EIAC);
1329 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1330 regval = rd32(E1000_EIAM);
1331 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1332 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1333 if (adapter->vfs_allocated_count) {
4ae196df 1334 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1335 ims |= E1000_IMS_VMMB;
1336 }
55cac248
AD		 1337 if (adapter->hw.mac.type == e1000_82580)
1338 ims |= E1000_IMS_DRSTA;
1339
25568a53 1340 wr32(E1000_IMS, ims);
844290e5 1341 } else {
55cac248
AD		 1342 wr32(E1000_IMS, IMS_ENABLE_MASK |
1343 E1000_IMS_DRSTA);
1344 wr32(E1000_IAM, IMS_ENABLE_MASK |
1345 E1000_IMS_DRSTA);
844290e5 1346 }
9d5c8243
AK		 1347}
1348
1349static void igb_update_mng_vlan(struct igb_adapter *adapter)
1350{
51466239 1351 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1352 u16 vid = adapter->hw.mng_cookie.vlan_id;
1353 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1354
1355 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1356 /* add VID to filter table */
1357 igb_vfta_set(hw, vid, true);
1358 adapter->mng_vlan_id = vid;
1359 } else {
1360 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1361 }
1362
1363 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1364 (vid != old_vid) &&
b2cb09b1 1365 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1366 /* remove VID from filter table */
1367 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1368 }
1369}
1370
1371/**
1372 * igb_release_hw_control - release control of the h/w to f/w
1373 * @adapter: address of board private structure
1374 *
1375 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1376 * For ASF and Pass Through versions of f/w this means that the
1377 * driver is no longer loaded.
1378 *
1379 **/
1380static void igb_release_hw_control(struct igb_adapter *adapter)
1381{
1382 struct e1000_hw *hw = &adapter->hw;
1383 u32 ctrl_ext;
1384
1385 /* Let firmware take over control of h/w */
1386 ctrl_ext = rd32(E1000_CTRL_EXT);
1387 wr32(E1000_CTRL_EXT,
1388 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1389}
1390
9d5c8243
AK		 1391/**
1392 * igb_get_hw_control - get control of the h/w from f/w
1393 * @adapter: address of board private structure
1394 *
1395 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1396 * For ASF and Pass Through versions of f/w this means that
1397 * the driver is loaded.
1398 *
1399 **/
1400static void igb_get_hw_control(struct igb_adapter *adapter)
1401{
1402 struct e1000_hw *hw = &adapter->hw;
1403 u32 ctrl_ext;
1404
1405 /* Let firmware know the driver has taken over */
1406 ctrl_ext = rd32(E1000_CTRL_EXT);
1407 wr32(E1000_CTRL_EXT,
1408 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1409}
1410
9d5c8243
AK		 1411/**
1412 * igb_configure - configure the hardware for RX and TX
1413 * @adapter: private board structure
1414 **/
1415static void igb_configure(struct igb_adapter *adapter)
1416{
1417 struct net_device *netdev = adapter->netdev;
1418 int i;
1419
1420 igb_get_hw_control(adapter);
ff41f8dc 1421 igb_set_rx_mode(netdev);
9d5c8243
AK		 1422
1423 igb_restore_vlan(adapter);
9d5c8243 1424
85b430b4 1425 igb_setup_tctl(adapter);
06cf2666 1426 igb_setup_mrqc(adapter);
9d5c8243 1427 igb_setup_rctl(adapter);
85b430b4
AD		 1428
1429 igb_configure_tx(adapter);
9d5c8243 1430 igb_configure_rx(adapter);
662d7205
AD		 1431
1432 igb_rx_fifo_flush_82575(&adapter->hw);
1433
c493ea45 1434 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1435 * at least 1 descriptor unused to make sure
1436 * next_to_use != next_to_clean */
1437 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1438 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1439 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1440 }
9d5c8243
AK		 1441}
1442
88a268c1
NN		 1443/**
1444 * igb_power_up_link - Power up the phy/serdes link
1445 * @adapter: address of board private structure
1446 **/
1447void igb_power_up_link(struct igb_adapter *adapter)
1448{
1449 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1450 igb_power_up_phy_copper(&adapter->hw);
1451 else
1452 igb_power_up_serdes_link_82575(&adapter->hw);
1453}
1454
1455/**
1456 * igb_power_down_link - Power down the phy/serdes link
1457 * @adapter: address of board private structure
1458 */
1459static void igb_power_down_link(struct igb_adapter *adapter)
1460{
1461 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1462 igb_power_down_phy_copper_82575(&adapter->hw);
1463 else
1464 igb_shutdown_serdes_link_82575(&adapter->hw);
1465}
9d5c8243
AK		 1466
1467/**
1468 * igb_up - Open the interface and prepare it to handle traffic
1469 * @adapter: board private structure
1470 **/
9d5c8243
AK		 1471int igb_up(struct igb_adapter *adapter)
1472{
1473 struct e1000_hw *hw = &adapter->hw;
1474 int i;
1475
1476 /* hardware has been reset, we need to reload some things */
1477 igb_configure(adapter);
1478
1479 clear_bit(__IGB_DOWN, &adapter->state);
1480
047e0030
AD		 1481 for (i = 0; i < adapter->num_q_vectors; i++) {
1482 struct igb_q_vector *q_vector = adapter->q_vector[i];
1483 napi_enable(&q_vector->napi);
1484 }
844290e5 1485 if (adapter->msix_entries)
9d5c8243 1486 igb_configure_msix(adapter);
feeb2721
AD		 1487 else
1488 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1489
1490 /* Clear any pending interrupts. */
1491 rd32(E1000_ICR);
1492 igb_irq_enable(adapter);
1493
d4960307
AD		 1494 /* notify VFs that reset has been completed */
1495 if (adapter->vfs_allocated_count) {
1496 u32 reg_data = rd32(E1000_CTRL_EXT);
1497 reg_data |= E1000_CTRL_EXT_PFRSTD;
1498 wr32(E1000_CTRL_EXT, reg_data);
1499 }
1500
4cb9be7a
JB		 1501 netif_tx_start_all_queues(adapter->netdev);
1502
25568a53
AD		 1503 /* start the watchdog. */
1504 hw->mac.get_link_status = 1;
1505 schedule_work(&adapter->watchdog_task);
1506
9d5c8243
AK		 1507 return 0;
1508}
1509
1510void igb_down(struct igb_adapter *adapter)
1511{
9d5c8243 1512 struct net_device *netdev = adapter->netdev;
330a6d6a 1513 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1514 u32 tctl, rctl;
1515 int i;
1516
1517 /* signal that we're down so the interrupt handler does not
1518 * reschedule our watchdog timer */
1519 set_bit(__IGB_DOWN, &adapter->state);
1520
1521 /* disable receives in the hardware */
1522 rctl = rd32(E1000_RCTL);
1523 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1524 /* flush and sleep below */
1525
fd2ea0a7 1526 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1527
1528 /* disable transmits in the hardware */
1529 tctl = rd32(E1000_TCTL);
1530 tctl &= ~E1000_TCTL_EN;
1531 wr32(E1000_TCTL, tctl);
1532 /* flush both disables and wait for them to finish */
1533 wrfl();
1534 msleep(10);
1535
047e0030
AD		 1536 for (i = 0; i < adapter->num_q_vectors; i++) {
1537 struct igb_q_vector *q_vector = adapter->q_vector[i];
1538 napi_disable(&q_vector->napi);
1539 }
9d5c8243 1540
9d5c8243
AK		 1541 igb_irq_disable(adapter);
1542
1543 del_timer_sync(&adapter->watchdog_timer);
1544 del_timer_sync(&adapter->phy_info_timer);
1545
9d5c8243 1546 netif_carrier_off(netdev);
04fe6358
AD		 1547
1548 /* record the stats before reset*/
12dcd86b
ED		 1549 spin_lock(&adapter->stats64_lock);
1550 igb_update_stats(adapter, &adapter->stats64);
1551 spin_unlock(&adapter->stats64_lock);
04fe6358 1552
9d5c8243
AK		 1553 adapter->link_speed = 0;
1554 adapter->link_duplex = 0;
1555
3023682e
JK		 1556 if (!pci_channel_offline(adapter->pdev))
1557 igb_reset(adapter);
9d5c8243
AK		 1558 igb_clean_all_tx_rings(adapter);
1559 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1560#ifdef CONFIG_IGB_DCA
1561
1562 /* since we reset the hardware DCA settings were cleared */
1563 igb_setup_dca(adapter);
1564#endif
9d5c8243
AK		 1565}
1566
1567void igb_reinit_locked(struct igb_adapter *adapter)
1568{
1569 WARN_ON(in_interrupt());
1570 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1571 msleep(1);
1572 igb_down(adapter);
1573 igb_up(adapter);
1574 clear_bit(__IGB_RESETTING, &adapter->state);
1575}
1576
1577void igb_reset(struct igb_adapter *adapter)
1578{
090b1795 1579 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1580 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1581 struct e1000_mac_info *mac = &hw->mac;
1582 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1583 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1584 u16 hwm;
1585
1586 /* Repartition Pba for greater than 9k mtu
1587 * To take effect CTRL.RST is required.
1588 */
fa4dfae0 1589 switch (mac->type) {
d2ba2ed8 1590 case e1000_i350:
55cac248
AD		 1591 case e1000_82580:
1592 pba = rd32(E1000_RXPBS);
1593 pba = igb_rxpbs_adjust_82580(pba);
1594 break;
fa4dfae0 1595 case e1000_82576:
d249be54
AD		 1596 pba = rd32(E1000_RXPBS);
1597 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1598 break;
1599 case e1000_82575:
1600 default:
1601 pba = E1000_PBA_34K;
1602 break;
2d064c06 1603 }
9d5c8243 1604
2d064c06
AD		 1605 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1606 (mac->type < e1000_82576)) {
9d5c8243
AK		 1607 /* adjust PBA for jumbo frames */
1608 wr32(E1000_PBA, pba);
1609
1610 /* To maintain wire speed transmits, the Tx FIFO should be
1611 * large enough to accommodate two full transmit packets,
1612 * rounded up to the next 1KB and expressed in KB. Likewise,
1613 * the Rx FIFO should be large enough to accommodate at least
1614 * one full receive packet and is similarly rounded up and
1615 * expressed in KB. */
1616 pba = rd32(E1000_PBA);
1617 /* upper 16 bits has Tx packet buffer allocation size in KB */
1618 tx_space = pba >> 16;
1619 /* lower 16 bits has Rx packet buffer allocation size in KB */
1620 pba &= 0xffff;
1621 /* the tx fifo also stores 16 bytes of information about the tx
1622 * but don't include ethernet FCS because hardware appends it */
1623 min_tx_space = (adapter->max_frame_size +
85e8d004 1624 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1625 ETH_FCS_LEN) * 2;
1626 min_tx_space = ALIGN(min_tx_space, 1024);
1627 min_tx_space >>= 10;
1628 /* software strips receive CRC, so leave room for it */
1629 min_rx_space = adapter->max_frame_size;
1630 min_rx_space = ALIGN(min_rx_space, 1024);
1631 min_rx_space >>= 10;
1632
1633 /* If current Tx allocation is less than the min Tx FIFO size,
1634 * and the min Tx FIFO size is less than the current Rx FIFO
1635 * allocation, take space away from current Rx allocation */
1636 if (tx_space < min_tx_space &&
1637 ((min_tx_space - tx_space) < pba)) {
1638 pba = pba - (min_tx_space - tx_space);
1639
1640 /* if short on rx space, rx wins and must trump tx
1641 * adjustment */
1642 if (pba < min_rx_space)
1643 pba = min_rx_space;
1644 }
2d064c06 1645 wr32(E1000_PBA, pba);
9d5c8243 1646 }
9d5c8243
AK		 1647
1648 /* flow control settings */
1649 /* The high water mark must be low enough to fit one full frame
1650 * (or the size used for early receive) above it in the Rx FIFO.
1651 * Set it to the lower of:
1652 * - 90% of the Rx FIFO size, or
1653 * - the full Rx FIFO size minus one full frame */
1654 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1655 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1656
d405ea3e
AD		 1657 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1658 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1659 fc->pause_time = 0xFFFF;
1660 fc->send_xon = 1;
0cce119a 1661 fc->current_mode = fc->requested_mode;
9d5c8243 1662
4ae196df
AD		 1663 /* disable receive for all VFs and wait one second */
1664 if (adapter->vfs_allocated_count) {
1665 int i;
1666 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1667 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1668
1669 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1670 igb_ping_all_vfs(adapter);
4ae196df
AD		 1671
1672 /* disable transmits and receives */
1673 wr32(E1000_VFRE, 0);
1674 wr32(E1000_VFTE, 0);
1675 }
1676
9d5c8243 1677 /* Allow time for pending master requests to run */
330a6d6a 1678 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1679 wr32(E1000_WUC, 0);
1680
330a6d6a 1681 if (hw->mac.ops.init_hw(hw))
090b1795 1682 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4
CW		 1683 if (hw->mac.type > e1000_82580) {
1684 if (adapter->flags & IGB_FLAG_DMAC) {
1685 u32 reg;
1686
1687 /*
1688 * DMA Coalescing high water mark needs to be higher
1689 * than * the * Rx threshold. The Rx threshold is
1690 * currently * pba - 6, so we * should use a high water
1691 * mark of pba * - 4. */
1692 hwm = (pba - 4) << 10;
1693
1694 reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT)
1695 & E1000_DMACR_DMACTHR_MASK);
1696
1697 /* transition to L0x or L1 if available..*/
1698 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1699
1700 /* watchdog timer= +-1000 usec in 32usec intervals */
1701 reg |= (1000 >> 5);
1702 wr32(E1000_DMACR, reg);
1703
1704 /* no lower threshold to disable coalescing(smart fifb)
1705 * -UTRESH=0*/
1706 wr32(E1000_DMCRTRH, 0);
1707
1708 /* set hwm to PBA - 2 * max frame size */
1709 wr32(E1000_FCRTC, hwm);
1710
1711 /*
1712 * This sets the time to wait before requesting tran-
1713 * sition to * low power state to number of usecs needed
1714 * to receive 1 512 * byte frame at gigabit line rate
1715 */
1716 reg = rd32(E1000_DMCTLX);
1717 reg |= IGB_DMCTLX_DCFLUSH_DIS;
1718
1719 /* Delay 255 usec before entering Lx state. */
1720 reg |= 0xFF;
1721 wr32(E1000_DMCTLX, reg);
1722
1723 /* free space in Tx packet buffer to wake from DMAC */
1724 wr32(E1000_DMCTXTH,
1725 (IGB_MIN_TXPBSIZE -
1726 (IGB_TX_BUF_4096 + adapter->max_frame_size))
1727 >> 6);
1728
1729 /* make low power state decision controlled by DMAC */
1730 reg = rd32(E1000_PCIEMISC);
1731 reg |= E1000_PCIEMISC_LX_DECISION;
1732 wr32(E1000_PCIEMISC, reg);
1733 } /* end if IGB_FLAG_DMAC set */
1734 }
55cac248
AD		 1735 if (hw->mac.type == e1000_82580) {
1736 u32 reg = rd32(E1000_PCIEMISC);
1737 wr32(E1000_PCIEMISC,
1738 reg & ~E1000_PCIEMISC_LX_DECISION);
1739 }
88a268c1
NN		 1740 if (!netif_running(adapter->netdev))
1741 igb_power_down_link(adapter);
1742
9d5c8243
AK		 1743 igb_update_mng_vlan(adapter);
1744
1745 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1746 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1747
330a6d6a 1748 igb_get_phy_info(hw);
9d5c8243
AK		 1749}
1750
b2cb09b1
JP		 1751static u32 igb_fix_features(struct net_device *netdev, u32 features)
1752{
1753 /*
1754 * Since there is no support for separate rx/tx vlan accel
1755 * enable/disable make sure tx flag is always in same state as rx.
1756 */
1757 if (features & NETIF_F_HW_VLAN_RX)
1758 features |= NETIF_F_HW_VLAN_TX;
1759 else
1760 features &= ~NETIF_F_HW_VLAN_TX;
1761
1762 return features;
1763}
1764
ac52caa3
MM		 1765static int igb_set_features(struct net_device *netdev, u32 features)
1766{
1767 struct igb_adapter *adapter = netdev_priv(netdev);
1768 int i;
b2cb09b1 1769 u32 changed = netdev->features ^ features;
ac52caa3
MM		 1770
1771 for (i = 0; i < adapter->num_rx_queues; i++) {
1772 if (features & NETIF_F_RXCSUM)
1773 adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM;
1774 else
1775 adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM;
1776 }
1777
b2cb09b1
JP		 1778 if (changed & NETIF_F_HW_VLAN_RX)
1779 igb_vlan_mode(netdev, features);
1780
ac52caa3
MM		 1781 return 0;
1782}
1783
2e5c6922 1784static const struct net_device_ops igb_netdev_ops = {
559e9c49 1785 .ndo_open = igb_open,
2e5c6922 1786 .ndo_stop = igb_close,
cd392f5c 1787 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1788 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1789 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1790 .ndo_set_mac_address = igb_set_mac,
1791 .ndo_change_mtu = igb_change_mtu,
1792 .ndo_do_ioctl = igb_ioctl,
1793 .ndo_tx_timeout = igb_tx_timeout,
1794 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1795 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1796 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1797 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1798 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1799 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1800 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1801#ifdef CONFIG_NET_POLL_CONTROLLER
1802 .ndo_poll_controller = igb_netpoll,
1803#endif
b2cb09b1
JP		 1804 .ndo_fix_features = igb_fix_features,
1805 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1806};
1807
9d5c8243
AK		 1808/**
1809 * igb_probe - Device Initialization Routine
1810 * @pdev: PCI device information struct
1811 * @ent: entry in igb_pci_tbl
1812 *
1813 * Returns 0 on success, negative on failure
1814 *
1815 * igb_probe initializes an adapter identified by a pci_dev structure.
1816 * The OS initialization, configuring of the adapter private structure,
1817 * and a hardware reset occur.
1818 **/
1819static int __devinit igb_probe(struct pci_dev *pdev,
1820 const struct pci_device_id *ent)
1821{
1822 struct net_device *netdev;
1823 struct igb_adapter *adapter;
1824 struct e1000_hw *hw;
4337e993 1825 u16 eeprom_data = 0;
9835fd73 1826 s32 ret_val;
4337e993 1827 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1828 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1829 unsigned long mmio_start, mmio_len;
2d6a5e95 1830 int err, pci_using_dac;
9d5c8243 1831 u16 eeprom_apme_mask = IGB_EEPROM_APME;
9835fd73 1832 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1833
bded64a7
AG		 1834 /* Catch broken hardware that put the wrong VF device ID in
1835 * the PCIe SR-IOV capability.
1836 */
1837 if (pdev->is_virtfn) {
1838 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1839 pci_name(pdev), pdev->vendor, pdev->device);
1840 return -EINVAL;
1841 }
1842
aed5dec3 1843 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1844 if (err)
1845 return err;
1846
1847 pci_using_dac = 0;
59d71989 1848 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1849 if (!err) {
59d71989 1850 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1851 if (!err)
1852 pci_using_dac = 1;
1853 } else {
59d71989 1854 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1855 if (err) {
59d71989 1856 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1857 if (err) {
1858 dev_err(&pdev->dev, "No usable DMA "
1859 "configuration, aborting\n");
1860 goto err_dma;
1861 }
1862 }
1863 }
1864
aed5dec3
AD		 1865 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1866 IORESOURCE_MEM),
1867 igb_driver_name);
9d5c8243
AK		 1868 if (err)
1869 goto err_pci_reg;
1870
19d5afd4 1871 pci_enable_pcie_error_reporting(pdev);
40a914fa 1872
9d5c8243 1873 pci_set_master(pdev);
c682fc23 1874 pci_save_state(pdev);
9d5c8243
AK		 1875
1876 err = -ENOMEM;
1bfaf07b
AD		 1877 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1878 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1879 if (!netdev)
1880 goto err_alloc_etherdev;
1881
1882 SET_NETDEV_DEV(netdev, &pdev->dev);
1883
1884 pci_set_drvdata(pdev, netdev);
1885 adapter = netdev_priv(netdev);
1886 adapter->netdev = netdev;
1887 adapter->pdev = pdev;
1888 hw = &adapter->hw;
1889 hw->back = adapter;
1890 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1891
1892 mmio_start = pci_resource_start(pdev, 0);
1893 mmio_len = pci_resource_len(pdev, 0);
1894
1895 err = -EIO;
28b0759c
AD		 1896 hw->hw_addr = ioremap(mmio_start, mmio_len);
1897 if (!hw->hw_addr)
9d5c8243
AK		 1898 goto err_ioremap;
1899
2e5c6922 1900 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1901 igb_set_ethtool_ops(netdev);
9d5c8243 1902 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1903
1904 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1905
1906 netdev->mem_start = mmio_start;
1907 netdev->mem_end = mmio_start + mmio_len;
1908
9d5c8243
AK		 1909 /* PCI config space info */
1910 hw->vendor_id = pdev->vendor;
1911 hw->device_id = pdev->device;
1912 hw->revision_id = pdev->revision;
1913 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1914 hw->subsystem_device_id = pdev->subsystem_device;
1915
9d5c8243
AK		 1916 /* Copy the default MAC, PHY and NVM function pointers */
1917 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1918 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1919 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1920 /* Initialize skew-specific constants */
1921 err = ei->get_invariants(hw);
1922 if (err)
450c87c8 1923 goto err_sw_init;
9d5c8243 1924
450c87c8 1925 /* setup the private structure */
9d5c8243
AK		 1926 err = igb_sw_init(adapter);
1927 if (err)
1928 goto err_sw_init;
1929
1930 igb_get_bus_info_pcie(hw);
1931
1932 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1933
1934 /* Copper options */
1935 if (hw->phy.media_type == e1000_media_type_copper) {
1936 hw->phy.mdix = AUTO_ALL_MODES;
1937 hw->phy.disable_polarity_correction = false;
1938 hw->phy.ms_type = e1000_ms_hw_default;
1939 }
1940
1941 if (igb_check_reset_block(hw))
1942 dev_info(&pdev->dev,
1943 "PHY reset is blocked due to SOL/IDER session.\n");
1944
ac52caa3 1945 netdev->hw_features = NETIF_F_SG |
7d8eb29e 1946 NETIF_F_IP_CSUM |
ac52caa3
MM		 1947 NETIF_F_IPV6_CSUM |
1948 NETIF_F_TSO |
1949 NETIF_F_TSO6 |
b2cb09b1
JP		 1950 NETIF_F_RXCSUM |
1951 NETIF_F_HW_VLAN_RX;
ac52caa3
MM		 1952
1953 netdev->features = netdev->hw_features |
9d5c8243 1954 NETIF_F_HW_VLAN_TX |
9d5c8243
AK		 1955 NETIF_F_HW_VLAN_FILTER;
1956
48f29ffc
JK		 1957 netdev->vlan_features |= NETIF_F_TSO;
1958 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1959 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1960 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1961 netdev->vlan_features |= NETIF_F_SG;
1962
7b872a55 1963 if (pci_using_dac) {
9d5c8243 1964 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1965 netdev->vlan_features |= NETIF_F_HIGHDMA;
1966 }
9d5c8243 1967
ac52caa3
MM		 1968 if (hw->mac.type >= e1000_82576) {
1969 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1970 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 1971 }
b9473560 1972
01789349
JP		 1973 netdev->priv_flags |= IFF_UNICAST_FLT;
1974
330a6d6a 1975 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1976
1977 /* before reading the NVM, reset the controller to put the device in a
1978 * known good starting state */
1979 hw->mac.ops.reset_hw(hw);
1980
1981 /* make sure the NVM is good */
4322e561 1982 if (hw->nvm.ops.validate(hw) < 0) {
9d5c8243
AK		 1983 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1984 err = -EIO;
1985 goto err_eeprom;
1986 }
1987
1988 /* copy the MAC address out of the NVM */
1989 if (hw->mac.ops.read_mac_addr(hw))
1990 dev_err(&pdev->dev, "NVM Read Error\n");
1991
1992 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1993 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1994
1995 if (!is_valid_ether_addr(netdev->perm_addr)) {
1996 dev_err(&pdev->dev, "Invalid MAC Address\n");
1997 err = -EIO;
1998 goto err_eeprom;
1999 }
2000
c061b18d 2001 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2002 (unsigned long) adapter);
c061b18d 2003 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2004 (unsigned long) adapter);
9d5c8243
AK		 2005
2006 INIT_WORK(&adapter->reset_task, igb_reset_task);
2007 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2008
450c87c8 2009 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2010 adapter->fc_autoneg = true;
2011 hw->mac.autoneg = true;
2012 hw->phy.autoneg_advertised = 0x2f;
2013
0cce119a
AD		 2014 hw->fc.requested_mode = e1000_fc_default;
2015 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2016
9d5c8243
AK		 2017 igb_validate_mdi_setting(hw);
2018
9d5c8243
AK		 2019 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2020 * enable the ACPI Magic Packet filter
2021 */
2022
a2cf8b6c 2023 if (hw->bus.func == 0)
312c75ae 2024 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6d337dce 2025 else if (hw->mac.type >= e1000_82580)
55cac248
AD		 2026 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2027 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2028 &eeprom_data);
a2cf8b6c
AD		 2029 else if (hw->bus.func == 1)
2030 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 2031
2032 if (eeprom_data & eeprom_apme_mask)
2033 adapter->eeprom_wol |= E1000_WUFC_MAG;
2034
2035 /* now that we have the eeprom settings, apply the special cases where
2036 * the eeprom may be wrong or the board simply won't support wake on
2037 * lan on a particular port */
2038 switch (pdev->device) {
2039 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2040 adapter->eeprom_wol = 0;
2041 break;
2042 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2043 case E1000_DEV_ID_82576_FIBER:
2044 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2045 /* Wake events only supported on port A for dual fiber
2046 * regardless of eeprom setting */
2047 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2048 adapter->eeprom_wol = 0;
2049 break;
c8ea5ea9 2050 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2051 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2052 /* if quad port adapter, disable WoL on all but port A */
2053 if (global_quad_port_a != 0)
2054 adapter->eeprom_wol = 0;
2055 else
2056 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2057 /* Reset for multiple quad port adapters */
2058 if (++global_quad_port_a == 4)
2059 global_quad_port_a = 0;
2060 break;
9d5c8243
AK		 2061 }
2062
2063 /* initialize the wol settings based on the eeprom settings */
2064 adapter->wol = adapter->eeprom_wol;
e1b86d84 2065 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 2066
2067 /* reset the hardware with the new settings */
2068 igb_reset(adapter);
2069
2070 /* let the f/w know that the h/w is now under the control of the
2071 * driver. */
2072 igb_get_hw_control(adapter);
2073
9d5c8243
AK		 2074 strcpy(netdev->name, "eth%d");
2075 err = register_netdev(netdev);
2076 if (err)
2077 goto err_register;
2078
b2cb09b1
JP		 2079 igb_vlan_mode(netdev, netdev->features);
2080
b168dfc5
JB		 2081 /* carrier off reporting is important to ethtool even BEFORE open */
2082 netif_carrier_off(netdev);
2083
421e02f0 2084#ifdef CONFIG_IGB_DCA
bbd98fe4 2085 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2086 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2087 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2088 igb_setup_dca(adapter);
2089 }
fe4506b6 2090
38c845c7 2091#endif
673b8b70
AB		 2092 /* do hw tstamp init after resetting */
2093 igb_init_hw_timer(adapter);
2094
9d5c8243
AK		 2095 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2096 /* print bus type/speed/width info */
7c510e4b 2097 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2098 netdev->name,
559e9c49 2099 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2100 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2101 "unknown"),
59c3de89
AD		 2102 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2103 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2104 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2105 "unknown"),
7c510e4b 2106 netdev->dev_addr);
9d5c8243 2107
9835fd73
CW		 2108 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2109 if (ret_val)
2110 strcpy(part_str, "Unknown");
2111 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2112 dev_info(&pdev->dev,
2113 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2114 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2115 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2116 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2117 switch (hw->mac.type) {
2118 case e1000_i350:
2119 igb_set_eee_i350(hw);
2120 break;
2121 default:
2122 break;
2123 }
9d5c8243
AK		 2124 return 0;
2125
2126err_register:
2127 igb_release_hw_control(adapter);
2128err_eeprom:
2129 if (!igb_check_reset_block(hw))
f5f4cf08 2130 igb_reset_phy(hw);
9d5c8243
AK		 2131
2132 if (hw->flash_address)
2133 iounmap(hw->flash_address);
9d5c8243 2134err_sw_init:
047e0030 2135 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2136 iounmap(hw->hw_addr);
2137err_ioremap:
2138 free_netdev(netdev);
2139err_alloc_etherdev:
559e9c49
AD		 2140 pci_release_selected_regions(pdev,
2141 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2142err_pci_reg:
2143err_dma:
2144 pci_disable_device(pdev);
2145 return err;
2146}
2147
2148/**
2149 * igb_remove - Device Removal Routine
2150 * @pdev: PCI device information struct
2151 *
2152 * igb_remove is called by the PCI subsystem to alert the driver
2153 * that it should release a PCI device. The could be caused by a
2154 * Hot-Plug event, or because the driver is going to be removed from
2155 * memory.
2156 **/
2157static void __devexit igb_remove(struct pci_dev *pdev)
2158{
2159 struct net_device *netdev = pci_get_drvdata(pdev);
2160 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2161 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2162
760141a5
TH		 2163 /*
2164 * The watchdog timer may be rescheduled, so explicitly
2165 * disable watchdog from being rescheduled.
2166 */
9d5c8243
AK		 2167 set_bit(__IGB_DOWN, &adapter->state);
2168 del_timer_sync(&adapter->watchdog_timer);
2169 del_timer_sync(&adapter->phy_info_timer);
2170
760141a5
TH		 2171 cancel_work_sync(&adapter->reset_task);
2172 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2173
421e02f0 2174#ifdef CONFIG_IGB_DCA
7dfc16fa 2175 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2176 dev_info(&pdev->dev, "DCA disabled\n");
2177 dca_remove_requester(&pdev->dev);
7dfc16fa 2178 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2179 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2180 }
2181#endif
2182
9d5c8243
AK		 2183 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2184 * would have already happened in close and is redundant. */
2185 igb_release_hw_control(adapter);
2186
2187 unregister_netdev(netdev);
2188
047e0030 2189 igb_clear_interrupt_scheme(adapter);
9d5c8243 2190
37680117
AD		 2191#ifdef CONFIG_PCI_IOV
2192 /* reclaim resources allocated to VFs */
2193 if (adapter->vf_data) {
2194 /* disable iov and allow time for transactions to clear */
2195 pci_disable_sriov(pdev);
2196 msleep(500);
2197
2198 kfree(adapter->vf_data);
2199 adapter->vf_data = NULL;
2200 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2201 wrfl();
37680117
AD		 2202 msleep(100);
2203 dev_info(&pdev->dev, "IOV Disabled\n");
2204 }
2205#endif
559e9c49 2206
28b0759c
AD		 2207 iounmap(hw->hw_addr);
2208 if (hw->flash_address)
2209 iounmap(hw->flash_address);
559e9c49
AD		 2210 pci_release_selected_regions(pdev,
2211 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2212
2213 free_netdev(netdev);
2214
19d5afd4 2215 pci_disable_pcie_error_reporting(pdev);
40a914fa 2216
9d5c8243
AK		 2217 pci_disable_device(pdev);
2218}
2219
a6b623e0
AD		 2220/**
2221 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2222 * @adapter: board private structure to initialize
2223 *
2224 * This function initializes the vf specific data storage and then attempts to
2225 * allocate the VFs. The reason for ordering it this way is because it is much
2226 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2227 * the memory for the VFs.
2228 **/
2229static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2230{
2231#ifdef CONFIG_PCI_IOV
2232 struct pci_dev *pdev = adapter->pdev;
2233
a6b623e0
AD		 2234 if (adapter->vfs_allocated_count) {
2235 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2236 sizeof(struct vf_data_storage),
2237 GFP_KERNEL);
2238 /* if allocation failed then we do not support SR-IOV */
2239 if (!adapter->vf_data) {
2240 adapter->vfs_allocated_count = 0;
2241 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2242 "Data Storage\n");
2243 }
2244 }
2245
2246 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
2247 kfree(adapter->vf_data);
2248 adapter->vf_data = NULL;
2249#endif /* CONFIG_PCI_IOV */
2250 adapter->vfs_allocated_count = 0;
2251#ifdef CONFIG_PCI_IOV
2252 } else {
2253 unsigned char mac_addr[ETH_ALEN];
2254 int i;
2255 dev_info(&pdev->dev, "%d vfs allocated\n",
2256 adapter->vfs_allocated_count);
2257 for (i = 0; i < adapter->vfs_allocated_count; i++) {
2258 random_ether_addr(mac_addr);
2259 igb_set_vf_mac(adapter, i, mac_addr);
2260 }
831ec0b4
CW		 2261 /* DMA Coalescing is not supported in IOV mode. */
2262 if (adapter->flags & IGB_FLAG_DMAC)
2263 adapter->flags &= ~IGB_FLAG_DMAC;
a6b623e0
AD		 2264 }
2265#endif /* CONFIG_PCI_IOV */
2266}
2267
115f459a
AD		 2268
2269/**
2270 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2271 * @adapter: board private structure to initialize
2272 *
2273 * igb_init_hw_timer initializes the function pointer and values for the hw
2274 * timer found in hardware.
2275 **/
2276static void igb_init_hw_timer(struct igb_adapter *adapter)
2277{
2278 struct e1000_hw *hw = &adapter->hw;
2279
2280 switch (hw->mac.type) {
d2ba2ed8 2281 case e1000_i350:
55cac248
AD		 2282 case e1000_82580:
2283 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2284 adapter->cycles.read = igb_read_clock;
2285 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2286 adapter->cycles.mult = 1;
2287 /*
2288 * The 82580 timesync updates the system timer every 8ns by 8ns
2289 * and the value cannot be shifted. Instead we need to shift
2290 * the registers to generate a 64bit timer value. As a result
2291 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2292 * 24 in order to generate a larger value for synchronization.
2293 */
2294 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2295 /* disable system timer temporarily by setting bit 31 */
2296 wr32(E1000_TSAUXC, 0x80000000);
2297 wrfl();
2298
2299 /* Set registers so that rollover occurs soon to test this. */
2300 wr32(E1000_SYSTIMR, 0x00000000);
2301 wr32(E1000_SYSTIML, 0x80000000);
2302 wr32(E1000_SYSTIMH, 0x000000FF);
2303 wrfl();
2304
2305 /* enable system timer by clearing bit 31 */
2306 wr32(E1000_TSAUXC, 0x0);
2307 wrfl();
2308
2309 timecounter_init(&adapter->clock,
2310 &adapter->cycles,
2311 ktime_to_ns(ktime_get_real()));
2312 /*
2313 * Synchronize our NIC clock against system wall clock. NIC
2314 * time stamp reading requires ~3us per sample, each sample
2315 * was pretty stable even under load => only require 10
2316 * samples for each offset comparison.
2317 */
2318 memset(&adapter->compare, 0, sizeof(adapter->compare));
2319 adapter->compare.source = &adapter->clock;
2320 adapter->compare.target = ktime_get_real;
2321 adapter->compare.num_samples = 10;
2322 timecompare_update(&adapter->compare, 0);
2323 break;
115f459a
AD		 2324 case e1000_82576:
2325 /*
2326 * Initialize hardware timer: we keep it running just in case
2327 * that some program needs it later on.
2328 */
2329 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2330 adapter->cycles.read = igb_read_clock;
2331 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2332 adapter->cycles.mult = 1;
2333 /**
2334 * Scale the NIC clock cycle by a large factor so that
2335 * relatively small clock corrections can be added or
25985edc 2336 * subtracted at each clock tick. The drawbacks of a large
115f459a
AD		 2337 * factor are a) that the clock register overflows more quickly
2338 * (not such a big deal) and b) that the increment per tick has
2339 * to fit into 24 bits. As a result we need to use a shift of
2340 * 19 so we can fit a value of 16 into the TIMINCA register.
2341 */
2342 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2343 wr32(E1000_TIMINCA,
2344 (1 << E1000_TIMINCA_16NS_SHIFT) |
2345 (16 << IGB_82576_TSYNC_SHIFT));
2346
2347 /* Set registers so that rollover occurs soon to test this. */
2348 wr32(E1000_SYSTIML, 0x00000000);
2349 wr32(E1000_SYSTIMH, 0xFF800000);
2350 wrfl();
2351
2352 timecounter_init(&adapter->clock,
2353 &adapter->cycles,
2354 ktime_to_ns(ktime_get_real()));
2355 /*
2356 * Synchronize our NIC clock against system wall clock. NIC
2357 * time stamp reading requires ~3us per sample, each sample
2358 * was pretty stable even under load => only require 10
2359 * samples for each offset comparison.
2360 */
2361 memset(&adapter->compare, 0, sizeof(adapter->compare));
2362 adapter->compare.source = &adapter->clock;
2363 adapter->compare.target = ktime_get_real;
2364 adapter->compare.num_samples = 10;
2365 timecompare_update(&adapter->compare, 0);
2366 break;
2367 case e1000_82575:
2368 /* 82575 does not support timesync */
2369 default:
2370 break;
2371 }
2372
2373}
2374
9d5c8243
AK		 2375/**
2376 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2377 * @adapter: board private structure to initialize
2378 *
2379 * igb_sw_init initializes the Adapter private data structure.
2380 * Fields are initialized based on PCI device information and
2381 * OS network device settings (MTU size).
2382 **/
2383static int __devinit igb_sw_init(struct igb_adapter *adapter)
2384{
2385 struct e1000_hw *hw = &adapter->hw;
2386 struct net_device *netdev = adapter->netdev;
2387 struct pci_dev *pdev = adapter->pdev;
2388
2389 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2390
68fd9910
AD		 2391 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2392 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 2393 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2394 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2395
153285f9
AD		 2396 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2397 VLAN_HLEN;
9d5c8243
AK		 2398 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2399
12dcd86b 2400 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2401#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2402 switch (hw->mac.type) {
2403 case e1000_82576:
2404 case e1000_i350:
9b082d73
SA		 2405 if (max_vfs > 7) {
2406 dev_warn(&pdev->dev,
2407 "Maximum of 7 VFs per PF, using max\n");
2408 adapter->vfs_allocated_count = 7;
2409 } else
2410 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2411 break;
2412 default:
2413 break;
2414 }
a6b623e0 2415#endif /* CONFIG_PCI_IOV */
a99955fc 2416 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
665c8c8e
WM		 2417 /* i350 cannot do RSS and SR-IOV at the same time */
2418 if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count)
2419 adapter->rss_queues = 1;
a99955fc
AD		 2420
2421 /*
2422 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2423 * then we should combine the queues into a queue pair in order to
2424 * conserve interrupts due to limited supply
2425 */
2426 if ((adapter->rss_queues > 4) ||
2427 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2428 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2429
a6b623e0 2430 /* This call may decrease the number of queues */
047e0030 2431 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2432 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2433 return -ENOMEM;
2434 }
2435
a6b623e0
AD		 2436 igb_probe_vfs(adapter);
2437
9d5c8243
AK		 2438 /* Explicitly disable IRQ since the NIC can be in any state. */
2439 igb_irq_disable(adapter);
2440
831ec0b4
CW		 2441 if (hw->mac.type == e1000_i350)
2442 adapter->flags &= ~IGB_FLAG_DMAC;
2443
9d5c8243
AK		 2444 set_bit(__IGB_DOWN, &adapter->state);
2445 return 0;
2446}
2447
2448/**
2449 * igb_open - Called when a network interface is made active
2450 * @netdev: network interface device structure
2451 *
2452 * Returns 0 on success, negative value on failure
2453 *
2454 * The open entry point is called when a network interface is made
2455 * active by the system (IFF_UP). At this point all resources needed
2456 * for transmit and receive operations are allocated, the interrupt
2457 * handler is registered with the OS, the watchdog timer is started,
2458 * and the stack is notified that the interface is ready.
2459 **/
2460static int igb_open(struct net_device *netdev)
2461{
2462 struct igb_adapter *adapter = netdev_priv(netdev);
2463 struct e1000_hw *hw = &adapter->hw;
2464 int err;
2465 int i;
2466
2467 /* disallow open during test */
2468 if (test_bit(__IGB_TESTING, &adapter->state))
2469 return -EBUSY;
2470
b168dfc5
JB		 2471 netif_carrier_off(netdev);
2472
9d5c8243
AK		 2473 /* allocate transmit descriptors */
2474 err = igb_setup_all_tx_resources(adapter);
2475 if (err)
2476 goto err_setup_tx;
2477
2478 /* allocate receive descriptors */
2479 err = igb_setup_all_rx_resources(adapter);
2480 if (err)
2481 goto err_setup_rx;
2482
88a268c1 2483 igb_power_up_link(adapter);
9d5c8243 2484
9d5c8243
AK		 2485 /* before we allocate an interrupt, we must be ready to handle it.
2486 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2487 * as soon as we call pci_request_irq, so we have to setup our
2488 * clean_rx handler before we do so. */
2489 igb_configure(adapter);
2490
2491 err = igb_request_irq(adapter);
2492 if (err)
2493 goto err_req_irq;
2494
2495 /* From here on the code is the same as igb_up() */
2496 clear_bit(__IGB_DOWN, &adapter->state);
2497
047e0030
AD		 2498 for (i = 0; i < adapter->num_q_vectors; i++) {
2499 struct igb_q_vector *q_vector = adapter->q_vector[i];
2500 napi_enable(&q_vector->napi);
2501 }
9d5c8243
AK		 2502
2503 /* Clear any pending interrupts. */
2504 rd32(E1000_ICR);
844290e5
PW		 2505
2506 igb_irq_enable(adapter);
2507
d4960307
AD		 2508 /* notify VFs that reset has been completed */
2509 if (adapter->vfs_allocated_count) {
2510 u32 reg_data = rd32(E1000_CTRL_EXT);
2511 reg_data |= E1000_CTRL_EXT_PFRSTD;
2512 wr32(E1000_CTRL_EXT, reg_data);
2513 }
2514
d55b53ff
JK		 2515 netif_tx_start_all_queues(netdev);
2516
25568a53
AD		 2517 /* start the watchdog. */
2518 hw->mac.get_link_status = 1;
2519 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2520
2521 return 0;
2522
2523err_req_irq:
2524 igb_release_hw_control(adapter);
88a268c1 2525 igb_power_down_link(adapter);
9d5c8243
AK		 2526 igb_free_all_rx_resources(adapter);
2527err_setup_rx:
2528 igb_free_all_tx_resources(adapter);
2529err_setup_tx:
2530 igb_reset(adapter);
2531
2532 return err;
2533}
2534
2535/**
2536 * igb_close - Disables a network interface
2537 * @netdev: network interface device structure
2538 *
2539 * Returns 0, this is not allowed to fail
2540 *
2541 * The close entry point is called when an interface is de-activated
2542 * by the OS. The hardware is still under the driver's control, but
2543 * needs to be disabled. A global MAC reset is issued to stop the
2544 * hardware, and all transmit and receive resources are freed.
2545 **/
2546static int igb_close(struct net_device *netdev)
2547{
2548 struct igb_adapter *adapter = netdev_priv(netdev);
2549
2550 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2551 igb_down(adapter);
2552
2553 igb_free_irq(adapter);
2554
2555 igb_free_all_tx_resources(adapter);
2556 igb_free_all_rx_resources(adapter);
2557
9d5c8243
AK		 2558 return 0;
2559}
2560
2561/**
2562 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2563 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2564 *
2565 * Return 0 on success, negative on failure
2566 **/
80785298 2567int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2568{
59d71989 2569 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2570 int size;
2571
2572 size = sizeof(struct igb_buffer) * tx_ring->count;
89bf67f1 2573 tx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2574 if (!tx_ring->buffer_info)
2575 goto err;
9d5c8243
AK		 2576
2577 /* round up to nearest 4K */
85e8d004 2578 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2579 tx_ring->size = ALIGN(tx_ring->size, 4096);
2580
59d71989
AD		 2581 tx_ring->desc = dma_alloc_coherent(dev,
2582 tx_ring->size,
2583 &tx_ring->dma,
2584 GFP_KERNEL);
9d5c8243
AK		 2585
2586 if (!tx_ring->desc)
2587 goto err;
2588
9d5c8243
AK		 2589 tx_ring->next_to_use = 0;
2590 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2591 return 0;
2592
2593err:
2594 vfree(tx_ring->buffer_info);
59d71989 2595 dev_err(dev,
9d5c8243
AK		 2596 "Unable to allocate memory for the transmit descriptor ring\n");
2597 return -ENOMEM;
2598}
2599
2600/**
2601 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2602 * (Descriptors) for all queues
2603 * @adapter: board private structure
2604 *
2605 * Return 0 on success, negative on failure
2606 **/
2607static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2608{
439705e1 2609 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2610 int i, err = 0;
2611
2612 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2613 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2614 if (err) {
439705e1 2615 dev_err(&pdev->dev,
9d5c8243
AK		 2616 "Allocation for Tx Queue %u failed\n", i);
2617 for (i--; i >= 0; i--)
3025a446 2618 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2619 break;
2620 }
2621 }
2622
a99955fc 2623 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2624 int r_idx = i % adapter->num_tx_queues;
3025a446 2625 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2626 }
9d5c8243
AK		 2627 return err;
2628}
2629
2630/**
85b430b4
AD		 2631 * igb_setup_tctl - configure the transmit control registers
2632 * @adapter: Board private structure
9d5c8243 2633 **/
d7ee5b3a 2634void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2635{
9d5c8243
AK		 2636 struct e1000_hw *hw = &adapter->hw;
2637 u32 tctl;
9d5c8243 2638
85b430b4
AD		 2639 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2640 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2641
2642 /* Program the Transmit Control Register */
9d5c8243
AK		 2643 tctl = rd32(E1000_TCTL);
2644 tctl &= ~E1000_TCTL_CT;
2645 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2646 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2647
2648 igb_config_collision_dist(hw);
2649
9d5c8243
AK		 2650 /* Enable transmits */
2651 tctl |= E1000_TCTL_EN;
2652
2653 wr32(E1000_TCTL, tctl);
2654}
2655
85b430b4
AD		 2656/**
2657 * igb_configure_tx_ring - Configure transmit ring after Reset
2658 * @adapter: board private structure
2659 * @ring: tx ring to configure
2660 *
2661 * Configure a transmit ring after a reset.
2662 **/
d7ee5b3a
AD		 2663void igb_configure_tx_ring(struct igb_adapter *adapter,
2664 struct igb_ring *ring)
85b430b4
AD		 2665{
2666 struct e1000_hw *hw = &adapter->hw;
a74420e0 2667 u32 txdctl = 0;
85b430b4
AD		 2668 u64 tdba = ring->dma;
2669 int reg_idx = ring->reg_idx;
2670
2671 /* disable the queue */
a74420e0 2672 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2673 wrfl();
2674 mdelay(10);
2675
2676 wr32(E1000_TDLEN(reg_idx),
2677 ring->count * sizeof(union e1000_adv_tx_desc));
2678 wr32(E1000_TDBAL(reg_idx),
2679 tdba & 0x00000000ffffffffULL);
2680 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2681
fce99e34 2682 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2683 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2684 writel(0, ring->tail);
85b430b4
AD		 2685
2686 txdctl |= IGB_TX_PTHRESH;
2687 txdctl |= IGB_TX_HTHRESH << 8;
2688 txdctl |= IGB_TX_WTHRESH << 16;
2689
2690 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2691 wr32(E1000_TXDCTL(reg_idx), txdctl);
2692}
2693
2694/**
2695 * igb_configure_tx - Configure transmit Unit after Reset
2696 * @adapter: board private structure
2697 *
2698 * Configure the Tx unit of the MAC after a reset.
2699 **/
2700static void igb_configure_tx(struct igb_adapter *adapter)
2701{
2702 int i;
2703
2704 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2705 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2706}
2707
9d5c8243
AK		 2708/**
2709 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2710 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2711 *
2712 * Returns 0 on success, negative on failure
2713 **/
80785298 2714int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2715{
59d71989 2716 struct device *dev = rx_ring->dev;
9d5c8243
AK		 2717 int size, desc_len;
2718
2719 size = sizeof(struct igb_buffer) * rx_ring->count;
89bf67f1 2720 rx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2721 if (!rx_ring->buffer_info)
2722 goto err;
9d5c8243
AK		 2723
2724 desc_len = sizeof(union e1000_adv_rx_desc);
2725
2726 /* Round up to nearest 4K */
2727 rx_ring->size = rx_ring->count * desc_len;
2728 rx_ring->size = ALIGN(rx_ring->size, 4096);
2729
59d71989
AD		 2730 rx_ring->desc = dma_alloc_coherent(dev,
2731 rx_ring->size,
2732 &rx_ring->dma,
2733 GFP_KERNEL);
9d5c8243
AK		 2734
2735 if (!rx_ring->desc)
2736 goto err;
2737
2738 rx_ring->next_to_clean = 0;
2739 rx_ring->next_to_use = 0;
9d5c8243 2740
9d5c8243
AK		 2741 return 0;
2742
2743err:
2744 vfree(rx_ring->buffer_info);
439705e1 2745 rx_ring->buffer_info = NULL;
59d71989
AD		 2746 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2747 " ring\n");
9d5c8243
AK		 2748 return -ENOMEM;
2749}
2750
2751/**
2752 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2753 * (Descriptors) for all queues
2754 * @adapter: board private structure
2755 *
2756 * Return 0 on success, negative on failure
2757 **/
2758static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2759{
439705e1 2760 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2761 int i, err = 0;
2762
2763 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2764 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2765 if (err) {
439705e1 2766 dev_err(&pdev->dev,
9d5c8243
AK		 2767 "Allocation for Rx Queue %u failed\n", i);
2768 for (i--; i >= 0; i--)
3025a446 2769 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2770 break;
2771 }
2772 }
2773
2774 return err;
2775}
2776
06cf2666
AD		 2777/**
2778 * igb_setup_mrqc - configure the multiple receive queue control registers
2779 * @adapter: Board private structure
2780 **/
2781static void igb_setup_mrqc(struct igb_adapter *adapter)
2782{
2783 struct e1000_hw *hw = &adapter->hw;
2784 u32 mrqc, rxcsum;
2785 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2786 union e1000_reta {
2787 u32 dword;
2788 u8 bytes[4];
2789 } reta;
2790 static const u8 rsshash[40] = {
2791 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2792 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2793 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2794 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2795
2796 /* Fill out hash function seeds */
2797 for (j = 0; j < 10; j++) {
2798 u32 rsskey = rsshash[(j * 4)];
2799 rsskey |= rsshash[(j * 4) + 1] << 8;
2800 rsskey |= rsshash[(j * 4) + 2] << 16;
2801 rsskey |= rsshash[(j * 4) + 3] << 24;
2802 array_wr32(E1000_RSSRK(0), j, rsskey);
2803 }
2804
a99955fc 2805 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2806
2807 if (adapter->vfs_allocated_count) {
2808 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2809 switch (hw->mac.type) {
d2ba2ed8 2810 case e1000_i350:
55cac248
AD		 2811 case e1000_82580:
2812 num_rx_queues = 1;
2813 shift = 0;
2814 break;
06cf2666
AD		 2815 case e1000_82576:
2816 shift = 3;
2817 num_rx_queues = 2;
2818 break;
2819 case e1000_82575:
2820 shift = 2;
2821 shift2 = 6;
2822 default:
2823 break;
2824 }
2825 } else {
2826 if (hw->mac.type == e1000_82575)
2827 shift = 6;
2828 }
2829
2830 for (j = 0; j < (32 * 4); j++) {
2831 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2832 if (shift2)
2833 reta.bytes[j & 3] |= num_rx_queues << shift2;
2834 if ((j & 3) == 3)
2835 wr32(E1000_RETA(j >> 2), reta.dword);
2836 }
2837
2838 /*
2839 * Disable raw packet checksumming so that RSS hash is placed in
2840 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2841 * offloads as they are enabled by default
2842 */
2843 rxcsum = rd32(E1000_RXCSUM);
2844 rxcsum |= E1000_RXCSUM_PCSD;
2845
2846 if (adapter->hw.mac.type >= e1000_82576)
2847 /* Enable Receive Checksum Offload for SCTP */
2848 rxcsum |= E1000_RXCSUM_CRCOFL;
2849
2850 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2851 wr32(E1000_RXCSUM, rxcsum);
2852
2853 /* If VMDq is enabled then we set the appropriate mode for that, else
2854 * we default to RSS so that an RSS hash is calculated per packet even
2855 * if we are only using one queue */
2856 if (adapter->vfs_allocated_count) {
2857 if (hw->mac.type > e1000_82575) {
2858 /* Set the default pool for the PF's first queue */
2859 u32 vtctl = rd32(E1000_VT_CTL);
2860 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2861 E1000_VT_CTL_DISABLE_DEF_POOL);
2862 vtctl |= adapter->vfs_allocated_count <<
2863 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2864 wr32(E1000_VT_CTL, vtctl);
2865 }
a99955fc 2866 if (adapter->rss_queues > 1)
06cf2666
AD		 2867 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2868 else
2869 mrqc = E1000_MRQC_ENABLE_VMDQ;
2870 } else {
2871 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2872 }
2873 igb_vmm_control(adapter);
2874
4478a9cd
AD		 2875 /*
2876 * Generate RSS hash based on TCP port numbers and/or
2877 * IPv4/v6 src and dst addresses since UDP cannot be
2878 * hashed reliably due to IP fragmentation
2879 */
2880 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2881 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2882 E1000_MRQC_RSS_FIELD_IPV6 |
2883 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2884 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666
AD		 2885
2886 wr32(E1000_MRQC, mrqc);
2887}
2888
9d5c8243
AK		 2889/**
2890 * igb_setup_rctl - configure the receive control registers
2891 * @adapter: Board private structure
2892 **/
d7ee5b3a 2893void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2894{
2895 struct e1000_hw *hw = &adapter->hw;
2896 u32 rctl;
9d5c8243
AK		 2897
2898 rctl = rd32(E1000_RCTL);
2899
2900 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2901 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2902
69d728ba 2903 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2904 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2905
87cb7e8c
AK		 2906 /*
2907 * enable stripping of CRC. It's unlikely this will break BMC
2908 * redirection as it did with e1000. Newer features require
2909 * that the HW strips the CRC.
73cd78f1 2910 */
87cb7e8c 2911 rctl |= E1000_RCTL_SECRC;
9d5c8243 2912
559e9c49 2913 /* disable store bad packets and clear size bits. */
ec54d7d6 2914 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2915
6ec43fe6
AD		 2916 /* enable LPE to prevent packets larger than max_frame_size */
2917 rctl |= E1000_RCTL_LPE;
9d5c8243 2918
952f72a8
AD		 2919 /* disable queue 0 to prevent tail write w/o re-config */
2920 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2921
e1739522
AD		 2922 /* Attention!!! For SR-IOV PF driver operations you must enable
2923 * queue drop for all VF and PF queues to prevent head of line blocking
2924 * if an un-trusted VF does not provide descriptors to hardware.
2925 */
2926 if (adapter->vfs_allocated_count) {
e1739522
AD		 2927 /* set all queue drop enable bits */
2928 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2929 }
2930
9d5c8243
AK		 2931 wr32(E1000_RCTL, rctl);
2932}
2933
7d5753f0
AD		 2934static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2935 int vfn)
2936{
2937 struct e1000_hw *hw = &adapter->hw;
2938 u32 vmolr;
2939
2940 /* if it isn't the PF check to see if VFs are enabled and
2941 * increase the size to support vlan tags */
2942 if (vfn < adapter->vfs_allocated_count &&
2943 adapter->vf_data[vfn].vlans_enabled)
2944 size += VLAN_TAG_SIZE;
2945
2946 vmolr = rd32(E1000_VMOLR(vfn));
2947 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2948 vmolr |= size | E1000_VMOLR_LPE;
2949 wr32(E1000_VMOLR(vfn), vmolr);
2950
2951 return 0;
2952}
2953
e1739522
AD		 2954/**
2955 * igb_rlpml_set - set maximum receive packet size
2956 * @adapter: board private structure
2957 *
2958 * Configure maximum receivable packet size.
2959 **/
2960static void igb_rlpml_set(struct igb_adapter *adapter)
2961{
153285f9 2962 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 2963 struct e1000_hw *hw = &adapter->hw;
2964 u16 pf_id = adapter->vfs_allocated_count;
2965
e1739522
AD		 2966 if (pf_id) {
2967 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 2968 /*
2969 * If we're in VMDQ or SR-IOV mode, then set global RLPML
2970 * to our max jumbo frame size, in case we need to enable
2971 * jumbo frames on one of the rings later.
2972 * This will not pass over-length frames into the default
2973 * queue because it's gated by the VMOLR.RLPML.
2974 */
7d5753f0 2975 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2976 }
2977
2978 wr32(E1000_RLPML, max_frame_size);
2979}
2980
8151d294
WM		 2981static inline void igb_set_vmolr(struct igb_adapter *adapter,
2982 int vfn, bool aupe)
7d5753f0
AD		 2983{
2984 struct e1000_hw *hw = &adapter->hw;
2985 u32 vmolr;
2986
2987 /*
2988 * This register exists only on 82576 and newer so if we are older then
2989 * we should exit and do nothing
2990 */
2991 if (hw->mac.type < e1000_82576)
2992 return;
2993
2994 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2995 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2996 if (aupe)
2997 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2998 else
2999 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3000
3001 /* clear all bits that might not be set */
3002 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3003
a99955fc 3004 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3005 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3006 /*
3007 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3008 * multicast packets
3009 */
3010 if (vfn <= adapter->vfs_allocated_count)
3011 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3012
3013 wr32(E1000_VMOLR(vfn), vmolr);
3014}
3015
85b430b4
AD		 3016/**
3017 * igb_configure_rx_ring - Configure a receive ring after Reset
3018 * @adapter: board private structure
3019 * @ring: receive ring to be configured
3020 *
3021 * Configure the Rx unit of the MAC after a reset.
3022 **/
d7ee5b3a
AD		 3023void igb_configure_rx_ring(struct igb_adapter *adapter,
3024 struct igb_ring *ring)
85b430b4
AD		 3025{
3026 struct e1000_hw *hw = &adapter->hw;
3027 u64 rdba = ring->dma;
3028 int reg_idx = ring->reg_idx;
a74420e0 3029 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3030
3031 /* disable the queue */
a74420e0 3032 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3033
3034 /* Set DMA base address registers */
3035 wr32(E1000_RDBAL(reg_idx),
3036 rdba & 0x00000000ffffffffULL);
3037 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3038 wr32(E1000_RDLEN(reg_idx),
3039 ring->count * sizeof(union e1000_adv_rx_desc));
3040
3041 /* initialize head and tail */
fce99e34 3042 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3043 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3044 writel(0, ring->tail);
85b430b4 3045
952f72a8 3046 /* set descriptor configuration */
44390ca6 3047 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
952f72a8 3048#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
44390ca6 3049 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3050#else
44390ca6 3051 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3052#endif
44390ca6 3053 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
757b77e2
NN		 3054 if (hw->mac.type == e1000_82580)
3055 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3056 /* Only set Drop Enable if we are supporting multiple queues */
3057 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3058 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3059
3060 wr32(E1000_SRRCTL(reg_idx), srrctl);
3061
7d5753f0 3062 /* set filtering for VMDQ pools */
8151d294 3063 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3064
85b430b4
AD		 3065 rxdctl |= IGB_RX_PTHRESH;
3066 rxdctl |= IGB_RX_HTHRESH << 8;
3067 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3068
3069 /* enable receive descriptor fetching */
3070 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3071 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3072}
3073
9d5c8243
AK		 3074/**
3075 * igb_configure_rx - Configure receive Unit after Reset
3076 * @adapter: board private structure
3077 *
3078 * Configure the Rx unit of the MAC after a reset.
3079 **/
3080static void igb_configure_rx(struct igb_adapter *adapter)
3081{
9107584e 3082 int i;
9d5c8243 3083
68d480c4
AD		 3084 /* set UTA to appropriate mode */
3085 igb_set_uta(adapter);
3086
26ad9178
AD		 3087 /* set the correct pool for the PF default MAC address in entry 0 */
3088 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3089 adapter->vfs_allocated_count);
3090
06cf2666
AD		 3091 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3092 * the Base and Length of the Rx Descriptor Ring */
3093 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3094 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3095}
3096
3097/**
3098 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3099 * @tx_ring: Tx descriptor ring for a specific queue
3100 *
3101 * Free all transmit software resources
3102 **/
68fd9910 3103void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3104{
3b644cf6 3105 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 3106
3107 vfree(tx_ring->buffer_info);
3108 tx_ring->buffer_info = NULL;
3109
439705e1
AD		 3110 /* if not set, then don't free */
3111 if (!tx_ring->desc)
3112 return;
3113
59d71989
AD		 3114 dma_free_coherent(tx_ring->dev, tx_ring->size,
3115 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3116
3117 tx_ring->desc = NULL;
3118}
3119
3120/**
3121 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3122 * @adapter: board private structure
3123 *
3124 * Free all transmit software resources
3125 **/
3126static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3127{
3128 int i;
3129
3130 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3131 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3132}
3133
b1a436c3
AD		 3134void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
3135 struct igb_buffer *buffer_info)
9d5c8243 3136{
6366ad33
AD		 3137 if (buffer_info->dma) {
3138 if (buffer_info->mapped_as_page)
59d71989 3139 dma_unmap_page(tx_ring->dev,
6366ad33
AD		 3140 buffer_info->dma,
3141 buffer_info->length,
59d71989 3142 DMA_TO_DEVICE);
6366ad33 3143 else
59d71989 3144 dma_unmap_single(tx_ring->dev,
6366ad33
AD		 3145 buffer_info->dma,
3146 buffer_info->length,
59d71989 3147 DMA_TO_DEVICE);
6366ad33
AD		 3148 buffer_info->dma = 0;
3149 }
9d5c8243
AK		 3150 if (buffer_info->skb) {
3151 dev_kfree_skb_any(buffer_info->skb);
3152 buffer_info->skb = NULL;
3153 }
3154 buffer_info->time_stamp = 0;
6366ad33
AD		 3155 buffer_info->length = 0;
3156 buffer_info->next_to_watch = 0;
3157 buffer_info->mapped_as_page = false;
9d5c8243
AK		 3158}
3159
3160/**
3161 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3162 * @tx_ring: ring to be cleaned
3163 **/
3b644cf6 3164static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 3165{
3166 struct igb_buffer *buffer_info;
3167 unsigned long size;
3168 unsigned int i;
3169
3170 if (!tx_ring->buffer_info)
3171 return;
3172 /* Free all the Tx ring sk_buffs */
3173
3174 for (i = 0; i < tx_ring->count; i++) {
3175 buffer_info = &tx_ring->buffer_info[i];
80785298 3176 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3177 }
3178
3179 size = sizeof(struct igb_buffer) * tx_ring->count;
3180 memset(tx_ring->buffer_info, 0, size);
3181
3182 /* Zero out the descriptor ring */
9d5c8243
AK		 3183 memset(tx_ring->desc, 0, tx_ring->size);
3184
3185 tx_ring->next_to_use = 0;
3186 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3187}
3188
3189/**
3190 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3191 * @adapter: board private structure
3192 **/
3193static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3194{
3195 int i;
3196
3197 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3198 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3199}
3200
3201/**
3202 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3203 * @rx_ring: ring to clean the resources from
3204 *
3205 * Free all receive software resources
3206 **/
68fd9910 3207void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3208{
3b644cf6 3209 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 3210
3211 vfree(rx_ring->buffer_info);
3212 rx_ring->buffer_info = NULL;
3213
439705e1
AD		 3214 /* if not set, then don't free */
3215 if (!rx_ring->desc)
3216 return;
3217
59d71989
AD		 3218 dma_free_coherent(rx_ring->dev, rx_ring->size,
3219 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3220
3221 rx_ring->desc = NULL;
3222}
3223
3224/**
3225 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3226 * @adapter: board private structure
3227 *
3228 * Free all receive software resources
3229 **/
3230static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3231{
3232 int i;
3233
3234 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3235 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3236}
3237
3238/**
3239 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3240 * @rx_ring: ring to free buffers from
3241 **/
3b644cf6 3242static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3243{
9d5c8243 3244 unsigned long size;
c023cd88 3245 u16 i;
9d5c8243
AK		 3246
3247 if (!rx_ring->buffer_info)
3248 return;
439705e1 3249
9d5c8243
AK		 3250 /* Free all the Rx ring sk_buffs */
3251 for (i = 0; i < rx_ring->count; i++) {
c023cd88 3252 struct igb_buffer *buffer_info = &rx_ring->buffer_info[i];
9d5c8243 3253 if (buffer_info->dma) {
59d71989 3254 dma_unmap_single(rx_ring->dev,
80785298 3255 buffer_info->dma,
44390ca6 3256 IGB_RX_HDR_LEN,
59d71989 3257 DMA_FROM_DEVICE);
9d5c8243
AK		 3258 buffer_info->dma = 0;
3259 }
3260
3261 if (buffer_info->skb) {
3262 dev_kfree_skb(buffer_info->skb);
3263 buffer_info->skb = NULL;
3264 }
6ec43fe6 3265 if (buffer_info->page_dma) {
59d71989 3266 dma_unmap_page(rx_ring->dev,
80785298 3267 buffer_info->page_dma,
6ec43fe6 3268 PAGE_SIZE / 2,
59d71989 3269 DMA_FROM_DEVICE);
6ec43fe6
AD		 3270 buffer_info->page_dma = 0;
3271 }
9d5c8243 3272 if (buffer_info->page) {
9d5c8243
AK		 3273 put_page(buffer_info->page);
3274 buffer_info->page = NULL;
bf36c1a0 3275 buffer_info->page_offset = 0;
9d5c8243
AK		 3276 }
3277 }
3278
9d5c8243
AK		 3279 size = sizeof(struct igb_buffer) * rx_ring->count;
3280 memset(rx_ring->buffer_info, 0, size);
3281
3282 /* Zero out the descriptor ring */
3283 memset(rx_ring->desc, 0, rx_ring->size);
3284
3285 rx_ring->next_to_clean = 0;
3286 rx_ring->next_to_use = 0;
9d5c8243
AK		 3287}
3288
3289/**
3290 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3291 * @adapter: board private structure
3292 **/
3293static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3294{
3295 int i;
3296
3297 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3298 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3299}
3300
3301/**
3302 * igb_set_mac - Change the Ethernet Address of the NIC
3303 * @netdev: network interface device structure
3304 * @p: pointer to an address structure
3305 *
3306 * Returns 0 on success, negative on failure
3307 **/
3308static int igb_set_mac(struct net_device *netdev, void *p)
3309{
3310 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3311 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3312 struct sockaddr *addr = p;
3313
3314 if (!is_valid_ether_addr(addr->sa_data))
3315 return -EADDRNOTAVAIL;
3316
3317 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3318 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3319
26ad9178
AD		 3320 /* set the correct pool for the new PF MAC address in entry 0 */
3321 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3322 adapter->vfs_allocated_count);
e1739522 3323
9d5c8243
AK		 3324 return 0;
3325}
3326
3327/**
68d480c4 3328 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3329 * @netdev: network interface device structure
3330 *
68d480c4
AD		 3331 * Writes multicast address list to the MTA hash table.
3332 * Returns: -ENOMEM on failure
3333 * 0 on no addresses written
3334 * X on writing X addresses to MTA
9d5c8243 3335 **/
68d480c4 3336static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3337{
3338 struct igb_adapter *adapter = netdev_priv(netdev);
3339 struct e1000_hw *hw = &adapter->hw;
22bedad3 3340 struct netdev_hw_addr *ha;
68d480c4 3341 u8 *mta_list;
9d5c8243
AK		 3342 int i;
3343
4cd24eaf 3344 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3345 /* nothing to program, so clear mc list */
3346 igb_update_mc_addr_list(hw, NULL, 0);
3347 igb_restore_vf_multicasts(adapter);
3348 return 0;
3349 }
9d5c8243 3350
4cd24eaf 3351 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3352 if (!mta_list)
3353 return -ENOMEM;
ff41f8dc 3354
68d480c4 3355 /* The shared function expects a packed array of only addresses. */
48e2f183 3356 i = 0;
22bedad3
JP		 3357 netdev_for_each_mc_addr(ha, netdev)
3358 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3359
68d480c4
AD		 3360 igb_update_mc_addr_list(hw, mta_list, i);
3361 kfree(mta_list);
3362
4cd24eaf 3363 return netdev_mc_count(netdev);
68d480c4
AD		 3364}
3365
3366/**
3367 * igb_write_uc_addr_list - write unicast addresses to RAR table
3368 * @netdev: network interface device structure
3369 *
3370 * Writes unicast address list to the RAR table.
3371 * Returns: -ENOMEM on failure/insufficient address space
3372 * 0 on no addresses written
3373 * X on writing X addresses to the RAR table
3374 **/
3375static int igb_write_uc_addr_list(struct net_device *netdev)
3376{
3377 struct igb_adapter *adapter = netdev_priv(netdev);
3378 struct e1000_hw *hw = &adapter->hw;
3379 unsigned int vfn = adapter->vfs_allocated_count;
3380 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3381 int count = 0;
3382
3383 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3384 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3385 return -ENOMEM;
9d5c8243 3386
32e7bfc4 3387 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3388 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3389
3390 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3391 if (!rar_entries)
3392 break;
26ad9178
AD		 3393 igb_rar_set_qsel(adapter, ha->addr,
3394 rar_entries--,
68d480c4
AD		 3395 vfn);
3396 count++;
ff41f8dc
AD		 3397 }
3398 }
3399 /* write the addresses in reverse order to avoid write combining */
3400 for (; rar_entries > 0 ; rar_entries--) {
3401 wr32(E1000_RAH(rar_entries), 0);
3402 wr32(E1000_RAL(rar_entries), 0);
3403 }
3404 wrfl();
3405
68d480c4
AD		 3406 return count;
3407}
3408
3409/**
3410 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3411 * @netdev: network interface device structure
3412 *
3413 * The set_rx_mode entry point is called whenever the unicast or multicast
3414 * address lists or the network interface flags are updated. This routine is
3415 * responsible for configuring the hardware for proper unicast, multicast,
3416 * promiscuous mode, and all-multi behavior.
3417 **/
3418static void igb_set_rx_mode(struct net_device *netdev)
3419{
3420 struct igb_adapter *adapter = netdev_priv(netdev);
3421 struct e1000_hw *hw = &adapter->hw;
3422 unsigned int vfn = adapter->vfs_allocated_count;
3423 u32 rctl, vmolr = 0;
3424 int count;
3425
3426 /* Check for Promiscuous and All Multicast modes */
3427 rctl = rd32(E1000_RCTL);
3428
3429 /* clear the effected bits */
3430 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3431
3432 if (netdev->flags & IFF_PROMISC) {
3433 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3434 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3435 } else {
3436 if (netdev->flags & IFF_ALLMULTI) {
3437 rctl |= E1000_RCTL_MPE;
3438 vmolr |= E1000_VMOLR_MPME;
3439 } else {
3440 /*
3441 * Write addresses to the MTA, if the attempt fails
25985edc 3442 * then we should just turn on promiscuous mode so
68d480c4
AD		 3443 * that we can at least receive multicast traffic
3444 */
3445 count = igb_write_mc_addr_list(netdev);
3446 if (count < 0) {
3447 rctl |= E1000_RCTL_MPE;
3448 vmolr |= E1000_VMOLR_MPME;
3449 } else if (count) {
3450 vmolr |= E1000_VMOLR_ROMPE;
3451 }
3452 }
3453 /*
3454 * Write addresses to available RAR registers, if there is not
3455 * sufficient space to store all the addresses then enable
25985edc 3456 * unicast promiscuous mode
68d480c4
AD		 3457 */
3458 count = igb_write_uc_addr_list(netdev);
3459 if (count < 0) {
3460 rctl |= E1000_RCTL_UPE;
3461 vmolr |= E1000_VMOLR_ROPE;
3462 }
3463 rctl |= E1000_RCTL_VFE;
28fc06f5 3464 }
68d480c4 3465 wr32(E1000_RCTL, rctl);
28fc06f5 3466
68d480c4
AD		 3467 /*
3468 * In order to support SR-IOV and eventually VMDq it is necessary to set
3469 * the VMOLR to enable the appropriate modes. Without this workaround
3470 * we will have issues with VLAN tag stripping not being done for frames
3471 * that are only arriving because we are the default pool
3472 */
3473 if (hw->mac.type < e1000_82576)
28fc06f5 3474 return;
9d5c8243 3475
68d480c4
AD		 3476 vmolr |= rd32(E1000_VMOLR(vfn)) &
3477 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3478 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3479 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3480}
3481
13800469
GR		 3482static void igb_check_wvbr(struct igb_adapter *adapter)
3483{
3484 struct e1000_hw *hw = &adapter->hw;
3485 u32 wvbr = 0;
3486
3487 switch (hw->mac.type) {
3488 case e1000_82576:
3489 case e1000_i350:
3490 if (!(wvbr = rd32(E1000_WVBR)))
3491 return;
3492 break;
3493 default:
3494 break;
3495 }
3496
3497 adapter->wvbr |= wvbr;
3498}
3499
3500#define IGB_STAGGERED_QUEUE_OFFSET 8
3501
3502static void igb_spoof_check(struct igb_adapter *adapter)
3503{
3504 int j;
3505
3506 if (!adapter->wvbr)
3507 return;
3508
3509 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3510 if (adapter->wvbr & (1 << j) ||
3511 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3512 dev_warn(&adapter->pdev->dev,
3513 "Spoof event(s) detected on VF %d\n", j);
3514 adapter->wvbr &=
3515 ~((1 << j) |
3516 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3517 }
3518 }
3519}
3520
9d5c8243
AK		 3521/* Need to wait a few seconds after link up to get diagnostic information from
3522 * the phy */
3523static void igb_update_phy_info(unsigned long data)
3524{
3525 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3526 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3527}
3528
4d6b725e
AD		 3529/**
3530 * igb_has_link - check shared code for link and determine up/down
3531 * @adapter: pointer to driver private info
3532 **/
3145535a 3533bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3534{
3535 struct e1000_hw *hw = &adapter->hw;
3536 bool link_active = false;
3537 s32 ret_val = 0;
3538
3539 /* get_link_status is set on LSC (link status) interrupt or
3540 * rx sequence error interrupt. get_link_status will stay
3541 * false until the e1000_check_for_link establishes link
3542 * for copper adapters ONLY
3543 */
3544 switch (hw->phy.media_type) {
3545 case e1000_media_type_copper:
3546 if (hw->mac.get_link_status) {
3547 ret_val = hw->mac.ops.check_for_link(hw);
3548 link_active = !hw->mac.get_link_status;
3549 } else {
3550 link_active = true;
3551 }
3552 break;
4d6b725e
AD		 3553 case e1000_media_type_internal_serdes:
3554 ret_val = hw->mac.ops.check_for_link(hw);
3555 link_active = hw->mac.serdes_has_link;
3556 break;
3557 default:
3558 case e1000_media_type_unknown:
3559 break;
3560 }
3561
3562 return link_active;
3563}
3564
563988dc
SA		 3565static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3566{
3567 bool ret = false;
3568 u32 ctrl_ext, thstat;
3569
3570 /* check for thermal sensor event on i350, copper only */
3571 if (hw->mac.type == e1000_i350) {
3572 thstat = rd32(E1000_THSTAT);
3573 ctrl_ext = rd32(E1000_CTRL_EXT);
3574
3575 if ((hw->phy.media_type == e1000_media_type_copper) &&
3576 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3577 ret = !!(thstat & event);
3578 }
3579 }
3580
3581 return ret;
3582}
3583
9d5c8243
AK		 3584/**
3585 * igb_watchdog - Timer Call-back
3586 * @data: pointer to adapter cast into an unsigned long
3587 **/
3588static void igb_watchdog(unsigned long data)
3589{
3590 struct igb_adapter *adapter = (struct igb_adapter *)data;
3591 /* Do the rest outside of interrupt context */
3592 schedule_work(&adapter->watchdog_task);
3593}
3594
3595static void igb_watchdog_task(struct work_struct *work)
3596{
3597 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3598 struct igb_adapter,
3599 watchdog_task);
9d5c8243 3600 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3601 struct net_device *netdev = adapter->netdev;
563988dc 3602 u32 link;
7a6ea550 3603 int i;
9d5c8243 3604
4d6b725e 3605 link = igb_has_link(adapter);
9d5c8243
AK		 3606 if (link) {
3607 if (!netif_carrier_ok(netdev)) {
3608 u32 ctrl;
330a6d6a
AD		 3609 hw->mac.ops.get_speed_and_duplex(hw,
3610 &adapter->link_speed,
3611 &adapter->link_duplex);
9d5c8243
AK		 3612
3613 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3614 /* Links status message must follow this format */
3615 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3616 "Flow Control: %s\n",
559e9c49
AD		 3617 netdev->name,
3618 adapter->link_speed,
3619 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3620 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3621 ((ctrl & E1000_CTRL_TFCE) &&
3622 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3623 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3624 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243 3625
563988dc
SA		 3626 /* check for thermal sensor event */
3627 if (igb_thermal_sensor_event(hw, E1000_THSTAT_LINK_THROTTLE)) {
3628 printk(KERN_INFO "igb: %s The network adapter "
3629 "link speed was downshifted "
3630 "because it overheated.\n",
3631 netdev->name);
7ef5ed1c 3632 }
563988dc 3633
d07f3e37 3634 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3635 adapter->tx_timeout_factor = 1;
3636 switch (adapter->link_speed) {
3637 case SPEED_10:
9d5c8243
AK		 3638 adapter->tx_timeout_factor = 14;
3639 break;
3640 case SPEED_100:
9d5c8243
AK		 3641 /* maybe add some timeout factor ? */
3642 break;
3643 }
3644
3645 netif_carrier_on(netdev);
9d5c8243 3646
4ae196df 3647 igb_ping_all_vfs(adapter);
17dc566c 3648 igb_check_vf_rate_limit(adapter);
4ae196df 3649
4b1a9877 3650 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3651 if (!test_bit(__IGB_DOWN, &adapter->state))
3652 mod_timer(&adapter->phy_info_timer,
3653 round_jiffies(jiffies + 2 * HZ));
3654 }
3655 } else {
3656 if (netif_carrier_ok(netdev)) {
3657 adapter->link_speed = 0;
3658 adapter->link_duplex = 0;
563988dc
SA		 3659
3660 /* check for thermal sensor event */
3661 if (igb_thermal_sensor_event(hw, E1000_THSTAT_PWR_DOWN)) {
3662 printk(KERN_ERR "igb: %s The network adapter "
3663 "was stopped because it "
3664 "overheated.\n",
7ef5ed1c 3665 netdev->name);
7ef5ed1c 3666 }
563988dc 3667
527d47c1
AD		 3668 /* Links status message must follow this format */
3669 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3670 netdev->name);
9d5c8243 3671 netif_carrier_off(netdev);
4b1a9877 3672
4ae196df
AD		 3673 igb_ping_all_vfs(adapter);
3674
4b1a9877 3675 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3676 if (!test_bit(__IGB_DOWN, &adapter->state))
3677 mod_timer(&adapter->phy_info_timer,
3678 round_jiffies(jiffies + 2 * HZ));
3679 }
3680 }
3681
12dcd86b
ED		 3682 spin_lock(&adapter->stats64_lock);
3683 igb_update_stats(adapter, &adapter->stats64);
3684 spin_unlock(&adapter->stats64_lock);
9d5c8243 3685
dbabb065 3686 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3687 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3688 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3689 /* We've lost link, so the controller stops DMA,
3690 * but we've got queued Tx work that's never going
3691 * to get done, so reset controller to flush Tx.
3692 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3693 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3694 adapter->tx_timeout_count++;
3695 schedule_work(&adapter->reset_task);
3696 /* return immediately since reset is imminent */
3697 return;
3698 }
9d5c8243 3699 }
9d5c8243 3700
dbabb065
AD		 3701 /* Force detection of hung controller every watchdog period */
3702 tx_ring->detect_tx_hung = true;
3703 }
f7ba205e 3704
9d5c8243 3705 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3706 if (adapter->msix_entries) {
047e0030
AD		 3707 u32 eics = 0;
3708 for (i = 0; i < adapter->num_q_vectors; i++) {
3709 struct igb_q_vector *q_vector = adapter->q_vector[i];
3710 eics |= q_vector->eims_value;
3711 }
7a6ea550
AD		 3712 wr32(E1000_EICS, eics);
3713 } else {
3714 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3715 }
9d5c8243 3716
13800469
GR		 3717 igb_spoof_check(adapter);
3718
9d5c8243
AK		 3719 /* Reset the timer */
3720 if (!test_bit(__IGB_DOWN, &adapter->state))
3721 mod_timer(&adapter->watchdog_timer,
3722 round_jiffies(jiffies + 2 * HZ));
3723}
3724
3725enum latency_range {
3726 lowest_latency = 0,
3727 low_latency = 1,
3728 bulk_latency = 2,
3729 latency_invalid = 255
3730};
3731
6eb5a7f1
AD		 3732/**
3733 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3734 *
3735 * Stores a new ITR value based on strictly on packet size. This
3736 * algorithm is less sophisticated than that used in igb_update_itr,
3737 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3738 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3739 * were determined based on theoretical maximum wire speed and testing
3740 * data, in order to minimize response time while increasing bulk
3741 * throughput.
3742 * This functionality is controlled by the InterruptThrottleRate module
3743 * parameter (see igb_param.c)
3744 * NOTE: This function is called only when operating in a multiqueue
3745 * receive environment.
047e0030 3746 * @q_vector: pointer to q_vector
6eb5a7f1 3747 **/
047e0030 3748static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3749{
047e0030 3750 int new_val = q_vector->itr_val;
6eb5a7f1 3751 int avg_wire_size = 0;
047e0030 3752 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b
ED		 3753 struct igb_ring *ring;
3754 unsigned int packets;
9d5c8243 3755
6eb5a7f1
AD		 3756 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3757 * ints/sec - ITR timer value of 120 ticks.
3758 */
3759 if (adapter->link_speed != SPEED_1000) {
047e0030 3760 new_val = 976;
6eb5a7f1 3761 goto set_itr_val;
9d5c8243 3762 }
047e0030 3763
12dcd86b
ED		 3764 ring = q_vector->rx_ring;
3765 if (ring) {
3766 packets = ACCESS_ONCE(ring->total_packets);
3767
3768 if (packets)
3769 avg_wire_size = ring->total_bytes / packets;
047e0030
AD		 3770 }
3771
12dcd86b
ED		 3772 ring = q_vector->tx_ring;
3773 if (ring) {
3774 packets = ACCESS_ONCE(ring->total_packets);
3775
3776 if (packets)
3777 avg_wire_size = max_t(u32, avg_wire_size,
3778 ring->total_bytes / packets);
047e0030
AD		 3779 }
3780
3781 /* if avg_wire_size isn't set no work was done */
3782 if (!avg_wire_size)
3783 goto clear_counts;
9d5c8243 3784
6eb5a7f1
AD		 3785 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3786 avg_wire_size += 24;
3787
3788 /* Don't starve jumbo frames */
3789 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3790
6eb5a7f1
AD		 3791 /* Give a little boost to mid-size frames */
3792 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3793 new_val = avg_wire_size / 3;
3794 else
3795 new_val = avg_wire_size / 2;
9d5c8243 3796
abe1c363
NN		 3797 /* when in itr mode 3 do not exceed 20K ints/sec */
3798 if (adapter->rx_itr_setting == 3 && new_val < 196)
3799 new_val = 196;
3800
6eb5a7f1 3801set_itr_val:
047e0030
AD		 3802 if (new_val != q_vector->itr_val) {
3803 q_vector->itr_val = new_val;
3804 q_vector->set_itr = 1;
9d5c8243 3805 }
6eb5a7f1 3806clear_counts:
047e0030
AD		 3807 if (q_vector->rx_ring) {
3808 q_vector->rx_ring->total_bytes = 0;
3809 q_vector->rx_ring->total_packets = 0;
3810 }
3811 if (q_vector->tx_ring) {
3812 q_vector->tx_ring->total_bytes = 0;
3813 q_vector->tx_ring->total_packets = 0;
3814 }
9d5c8243
AK		 3815}
3816
3817/**
3818 * igb_update_itr - update the dynamic ITR value based on statistics
3819 * Stores a new ITR value based on packets and byte
3820 * counts during the last interrupt. The advantage of per interrupt
3821 * computation is faster updates and more accurate ITR for the current
3822 * traffic pattern. Constants in this function were computed
3823 * based on theoretical maximum wire speed and thresholds were set based
3824 * on testing data as well as attempting to minimize response time
3825 * while increasing bulk throughput.
3826 * this functionality is controlled by the InterruptThrottleRate module
3827 * parameter (see igb_param.c)
3828 * NOTE: These calculations are only valid when operating in a single-
3829 * queue environment.
3830 * @adapter: pointer to adapter
047e0030 3831 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3832 * @packets: the number of packets during this measurement interval
3833 * @bytes: the number of bytes during this measurement interval
3834 **/
3835static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3836 int packets, int bytes)
3837{
3838 unsigned int retval = itr_setting;
3839
3840 if (packets == 0)
3841 goto update_itr_done;
3842
3843 switch (itr_setting) {
3844 case lowest_latency:
3845 /* handle TSO and jumbo frames */
3846 if (bytes/packets > 8000)
3847 retval = bulk_latency;
3848 else if ((packets < 5) && (bytes > 512))
3849 retval = low_latency;
3850 break;
3851 case low_latency: /* 50 usec aka 20000 ints/s */
3852 if (bytes > 10000) {
3853 /* this if handles the TSO accounting */
3854 if (bytes/packets > 8000) {
3855 retval = bulk_latency;
3856 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3857 retval = bulk_latency;
3858 } else if ((packets > 35)) {
3859 retval = lowest_latency;
3860 }
3861 } else if (bytes/packets > 2000) {
3862 retval = bulk_latency;
3863 } else if (packets <= 2 && bytes < 512) {
3864 retval = lowest_latency;
3865 }
3866 break;
3867 case bulk_latency: /* 250 usec aka 4000 ints/s */
3868 if (bytes > 25000) {
3869 if (packets > 35)
3870 retval = low_latency;
1e5c3d21 3871 } else if (bytes < 1500) {
9d5c8243
AK		 3872 retval = low_latency;
3873 }
3874 break;
3875 }
3876
3877update_itr_done:
3878 return retval;
3879}
3880
6eb5a7f1 3881static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3882{
047e0030 3883 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3884 u16 current_itr;
047e0030 3885 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3886
3887 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3888 if (adapter->link_speed != SPEED_1000) {
3889 current_itr = 0;
3890 new_itr = 4000;
3891 goto set_itr_now;
3892 }
3893
3894 adapter->rx_itr = igb_update_itr(adapter,
3895 adapter->rx_itr,
3025a446
AD		 3896 q_vector->rx_ring->total_packets,
3897 q_vector->rx_ring->total_bytes);
9d5c8243 3898
047e0030
AD		 3899 adapter->tx_itr = igb_update_itr(adapter,
3900 adapter->tx_itr,
3025a446
AD		 3901 q_vector->tx_ring->total_packets,
3902 q_vector->tx_ring->total_bytes);
047e0030 3903 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3904
6eb5a7f1 3905 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3906 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3907 current_itr = low_latency;
3908
9d5c8243
AK		 3909 switch (current_itr) {
3910 /* counts and packets in update_itr are dependent on these numbers */
3911 case lowest_latency:
78b1f607 3912 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3913 break;
3914 case low_latency:
78b1f607 3915 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3916 break;
3917 case bulk_latency:
78b1f607 3918 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3919 break;
3920 default:
3921 break;
3922 }
3923
3924set_itr_now:
3025a446
AD		 3925 q_vector->rx_ring->total_bytes = 0;
3926 q_vector->rx_ring->total_packets = 0;
3927 q_vector->tx_ring->total_bytes = 0;
3928 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3929
047e0030 3930 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3931 /* this attempts to bias the interrupt rate towards Bulk
3932 * by adding intermediate steps when interrupt rate is
3933 * increasing */
047e0030
AD		 3934 new_itr = new_itr > q_vector->itr_val ?
3935 max((new_itr * q_vector->itr_val) /
3936 (new_itr + (q_vector->itr_val >> 2)),
3937 new_itr) :
9d5c8243
AK		 3938 new_itr;
3939 /* Don't write the value here; it resets the adapter's
3940 * internal timer, and causes us to delay far longer than
3941 * we should between interrupts. Instead, we write the ITR
3942 * value at the beginning of the next interrupt so the timing
3943 * ends up being correct.
3944 */
047e0030
AD		 3945 q_vector->itr_val = new_itr;
3946 q_vector->set_itr = 1;
9d5c8243 3947 }
9d5c8243
AK		 3948}
3949
9d5c8243
AK		 3950#define IGB_TX_FLAGS_CSUM 0x00000001
3951#define IGB_TX_FLAGS_VLAN 0x00000002
3952#define IGB_TX_FLAGS_TSO 0x00000004
3953#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3954#define IGB_TX_FLAGS_TSTAMP 0x00000010
3955#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3956#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3957
cd392f5c
AD		 3958static inline int igb_tso(struct igb_ring *tx_ring,
3959 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
9d5c8243
AK		 3960{
3961 struct e1000_adv_tx_context_desc *context_desc;
3962 unsigned int i;
3963 int err;
3964 struct igb_buffer *buffer_info;
3965 u32 info = 0, tu_cmd = 0;
91d4ee33
NN		 3966 u32 mss_l4len_idx;
3967 u8 l4len;
9d5c8243
AK		 3968
3969 if (skb_header_cloned(skb)) {
3970 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3971 if (err)
3972 return err;
3973 }
3974
3975 l4len = tcp_hdrlen(skb);
3976 *hdr_len += l4len;
3977
3978 if (skb->protocol == htons(ETH_P_IP)) {
3979 struct iphdr *iph = ip_hdr(skb);
3980 iph->tot_len = 0;
3981 iph->check = 0;
3982 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3983 iph->daddr, 0,
3984 IPPROTO_TCP,
3985 0);
8e1e8a47 3986 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3987 ipv6_hdr(skb)->payload_len = 0;
3988 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3989 &ipv6_hdr(skb)->daddr,
3990 0, IPPROTO_TCP, 0);
3991 }
3992
3993 i = tx_ring->next_to_use;
3994
3995 buffer_info = &tx_ring->buffer_info[i];
3996 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3997 /* VLAN MACLEN IPLEN */
3998 if (tx_flags & IGB_TX_FLAGS_VLAN)
3999 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
4000 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
4001 *hdr_len += skb_network_offset(skb);
4002 info |= skb_network_header_len(skb);
4003 *hdr_len += skb_network_header_len(skb);
4004 context_desc->vlan_macip_lens = cpu_to_le32(info);
4005
4006 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4007 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
4008
4009 if (skb->protocol == htons(ETH_P_IP))
4010 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
4011 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4012
4013 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
4014
4015 /* MSS L4LEN IDX */
4016 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
4017 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
4018
73cd78f1 4019 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 4020 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
4021 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4022
4023 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4024 context_desc->seqnum_seed = 0;
4025
4026 buffer_info->time_stamp = jiffies;
0e014cb1 4027 buffer_info->next_to_watch = i;
9d5c8243
AK		 4028 buffer_info->dma = 0;
4029 i++;
4030 if (i == tx_ring->count)
4031 i = 0;
4032
4033 tx_ring->next_to_use = i;
4034
4035 return true;
4036}
4037
cd392f5c
AD		 4038static inline bool igb_tx_csum(struct igb_ring *tx_ring,
4039 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 4040{
4041 struct e1000_adv_tx_context_desc *context_desc;
59d71989 4042 struct device *dev = tx_ring->dev;
9d5c8243
AK		 4043 struct igb_buffer *buffer_info;
4044 u32 info = 0, tu_cmd = 0;
80785298 4045 unsigned int i;
9d5c8243
AK		 4046
4047 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
4048 (tx_flags & IGB_TX_FLAGS_VLAN)) {
4049 i = tx_ring->next_to_use;
4050 buffer_info = &tx_ring->buffer_info[i];
4051 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
4052
4053 if (tx_flags & IGB_TX_FLAGS_VLAN)
4054 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 4055
9d5c8243
AK		 4056 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
4057 if (skb->ip_summed == CHECKSUM_PARTIAL)
4058 info |= skb_network_header_len(skb);
4059
4060 context_desc->vlan_macip_lens = cpu_to_le32(info);
4061
4062 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
4063
4064 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 4065 __be16 protocol;
4066
4067 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
4068 const struct vlan_ethhdr *vhdr =
4069 (const struct vlan_ethhdr*)skb->data;
4070
4071 protocol = vhdr->h_vlan_encapsulated_proto;
4072 } else {
4073 protocol = skb->protocol;
4074 }
4075
4076 switch (protocol) {
09640e63 4077 case cpu_to_be16(ETH_P_IP):
9d5c8243 4078 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 4079 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4080 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 4081 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4082 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 4083 break;
09640e63 4084 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 4085 /* XXX what about other V6 headers?? */
4086 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4087 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 4088 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4089 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 4090 break;
4091 default:
4092 if (unlikely(net_ratelimit()))
59d71989 4093 dev_warn(dev,
44b0cda3
MW		 4094 "partial checksum but proto=%x!\n",
4095 skb->protocol);
4096 break;
4097 }
9d5c8243
AK		 4098 }
4099
4100 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
4101 context_desc->seqnum_seed = 0;
85ad76b2 4102 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 4103 context_desc->mss_l4len_idx =
85ad76b2 4104 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 4105
4106 buffer_info->time_stamp = jiffies;
0e014cb1 4107 buffer_info->next_to_watch = i;
9d5c8243
AK		 4108 buffer_info->dma = 0;
4109
4110 i++;
4111 if (i == tx_ring->count)
4112 i = 0;
4113 tx_ring->next_to_use = i;
4114
4115 return true;
4116 }
9d5c8243
AK		 4117 return false;
4118}
4119
4120#define IGB_MAX_TXD_PWR 16
4121#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
4122
cd392f5c
AD		 4123static inline int igb_tx_map(struct igb_ring *tx_ring, struct sk_buff *skb,
4124 unsigned int first)
9d5c8243
AK		 4125{
4126 struct igb_buffer *buffer_info;
59d71989 4127 struct device *dev = tx_ring->dev;
2873957d 4128 unsigned int hlen = skb_headlen(skb);
9d5c8243
AK		 4129 unsigned int count = 0, i;
4130 unsigned int f;
2873957d 4131 u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
9d5c8243
AK		 4132
4133 i = tx_ring->next_to_use;
4134
4135 buffer_info = &tx_ring->buffer_info[i];
2873957d
NN		 4136 BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
4137 buffer_info->length = hlen;
9d5c8243
AK		 4138 /* set time_stamp *before* dma to help avoid a possible race */
4139 buffer_info->time_stamp = jiffies;
0e014cb1 4140 buffer_info->next_to_watch = i;
2873957d 4141 buffer_info->dma = dma_map_single(dev, skb->data, hlen,
59d71989
AD		 4142 DMA_TO_DEVICE);
4143 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33 4144 goto dma_error;
9d5c8243
AK		 4145
4146 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2873957d
NN		 4147 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
4148 unsigned int len = frag->size;
9d5c8243 4149
8581145f 4150 count++;
65689fef
AD		 4151 i++;
4152 if (i == tx_ring->count)
4153 i = 0;
4154
9d5c8243
AK		 4155 buffer_info = &tx_ring->buffer_info[i];
4156 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
4157 buffer_info->length = len;
4158 buffer_info->time_stamp = jiffies;
0e014cb1 4159 buffer_info->next_to_watch = i;
6366ad33 4160 buffer_info->mapped_as_page = true;
877749bf 4161 buffer_info->dma = skb_frag_dma_map(dev, frag, 0, len,
59d71989
AD		 4162 DMA_TO_DEVICE);
4163 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33
AD		 4164 goto dma_error;
4165
9d5c8243
AK		 4166 }
4167
9d5c8243 4168 tx_ring->buffer_info[i].skb = skb;
2244d07b 4169 tx_ring->buffer_info[i].tx_flags = skb_shinfo(skb)->tx_flags;
2873957d
NN		 4170 /* multiply data chunks by size of headers */
4171 tx_ring->buffer_info[i].bytecount = ((gso_segs - 1) * hlen) + skb->len;
4172 tx_ring->buffer_info[i].gso_segs = gso_segs;
0e014cb1 4173 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 4174
cdfd01fc 4175 return ++count;
6366ad33
AD		 4176
4177dma_error:
59d71989 4178 dev_err(dev, "TX DMA map failed\n");
6366ad33
AD		 4179
4180 /* clear timestamp and dma mappings for failed buffer_info mapping */
4181 buffer_info->dma = 0;
4182 buffer_info->time_stamp = 0;
4183 buffer_info->length = 0;
4184 buffer_info->next_to_watch = 0;
4185 buffer_info->mapped_as_page = false;
6366ad33
AD		 4186
4187 /* clear timestamp and dma mappings for remaining portion of packet */
a77ff709
NN		 4188 while (count--) {
4189 if (i == 0)
4190 i = tx_ring->count;
6366ad33 4191 i--;
6366ad33
AD		 4192 buffer_info = &tx_ring->buffer_info[i];
4193 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
4194 }
4195
4196 return 0;
9d5c8243
AK		 4197}
4198
cd392f5c
AD		 4199static inline void igb_tx_queue(struct igb_ring *tx_ring,
4200 u32 tx_flags, int count, u32 paylen,
4201 u8 hdr_len)
9d5c8243 4202{
cdfd01fc 4203 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 4204 struct igb_buffer *buffer_info;
4205 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 4206 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 4207
4208 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
4209 E1000_ADVTXD_DCMD_DEXT);
4210
4211 if (tx_flags & IGB_TX_FLAGS_VLAN)
4212 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
4213
33af6bcc
PO		 4214 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4215 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
4216
9d5c8243
AK		 4217 if (tx_flags & IGB_TX_FLAGS_TSO) {
4218 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
4219
4220 /* insert tcp checksum */
4221 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4222
4223 /* insert ip checksum */
4224 if (tx_flags & IGB_TX_FLAGS_IPV4)
4225 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4226
4227 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
4228 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4229 }
4230
85ad76b2
AD		 4231 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
4232 (tx_flags & (IGB_TX_FLAGS_CSUM |
4233 IGB_TX_FLAGS_TSO |
7dfc16fa 4234 IGB_TX_FLAGS_VLAN)))
85ad76b2 4235 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4236
4237 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
4238
cdfd01fc 4239 do {
9d5c8243
AK		 4240 buffer_info = &tx_ring->buffer_info[i];
4241 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4242 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
4243 tx_desc->read.cmd_type_len =
4244 cpu_to_le32(cmd_type_len | buffer_info->length);
4245 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 4246 count--;
9d5c8243
AK		 4247 i++;
4248 if (i == tx_ring->count)
4249 i = 0;
cdfd01fc 4250 } while (count > 0);
9d5c8243 4251
85ad76b2 4252 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 4253 /* Force memory writes to complete before letting h/w
4254 * know there are new descriptors to fetch. (Only
4255 * applicable for weak-ordered memory model archs,
4256 * such as IA-64). */
4257 wmb();
4258
4259 tx_ring->next_to_use = i;
fce99e34 4260 writel(i, tx_ring->tail);
9d5c8243
AK		 4261 /* we need this if more than one processor can write to our tail
4262 * at a time, it syncronizes IO on IA64/Altix systems */
4263 mmiowb();
4264}
4265
e694e964 4266static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4267{
e694e964
AD		 4268 struct net_device *netdev = tx_ring->netdev;
4269
661086df 4270 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4271
9d5c8243
AK		 4272 /* Herbert's original patch had:
4273 * smp_mb__after_netif_stop_queue();
4274 * but since that doesn't exist yet, just open code it. */
4275 smp_mb();
4276
4277 /* We need to check again in a case another CPU has just
4278 * made room available. */
c493ea45 4279 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4280 return -EBUSY;
4281
4282 /* A reprieve! */
661086df 4283 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4284
4285 u64_stats_update_begin(&tx_ring->tx_syncp2);
4286 tx_ring->tx_stats.restart_queue2++;
4287 u64_stats_update_end(&tx_ring->tx_syncp2);
4288
9d5c8243
AK		 4289 return 0;
4290}
4291
717ba089 4292static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4293{
c493ea45 4294 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4295 return 0;
e694e964 4296 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4297}
4298
cd392f5c
AD		 4299netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4300 struct igb_ring *tx_ring)
9d5c8243 4301{
cdfd01fc 4302 int tso = 0, count;
91d4ee33
NN		 4303 u32 tx_flags = 0;
4304 u16 first;
4305 u8 hdr_len = 0;
9d5c8243 4306
9d5c8243
AK		 4307 /* need: 1 descriptor per page,
4308 * + 2 desc gap to keep tail from touching head,
4309 * + 1 desc for skb->data,
4310 * + 1 desc for context descriptor,
4311 * otherwise try next time */
e694e964 4312 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4313 /* this is a hard error */
9d5c8243
AK		 4314 return NETDEV_TX_BUSY;
4315 }
33af6bcc 4316
2244d07b
OH		 4317 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4318 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4319 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 4320 }
9d5c8243 4321
eab6d18d 4322 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4323 tx_flags |= IGB_TX_FLAGS_VLAN;
4324 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4325 }
4326
661086df
PWJ		 4327 if (skb->protocol == htons(ETH_P_IP))
4328 tx_flags |= IGB_TX_FLAGS_IPV4;
4329
0e014cb1 4330 first = tx_ring->next_to_use;
85ad76b2 4331 if (skb_is_gso(skb)) {
cd392f5c 4332 tso = igb_tso(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 4333
85ad76b2
AD		 4334 if (tso < 0) {
4335 dev_kfree_skb_any(skb);
4336 return NETDEV_TX_OK;
4337 }
9d5c8243
AK		 4338 }
4339
4340 if (tso)
4341 tx_flags |= IGB_TX_FLAGS_TSO;
cd392f5c 4342 else if (igb_tx_csum(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 4343 (skb->ip_summed == CHECKSUM_PARTIAL))
4344 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 4345
65689fef 4346 /*
cdfd01fc 4347 * count reflects descriptors mapped, if 0 or less then mapping error
25985edc 4348 * has occurred and we need to rewind the descriptor queue
65689fef 4349 */
cd392f5c 4350 count = igb_tx_map(tx_ring, skb, first);
6366ad33 4351 if (!count) {
65689fef
AD		 4352 dev_kfree_skb_any(skb);
4353 tx_ring->buffer_info[first].time_stamp = 0;
4354 tx_ring->next_to_use = first;
85ad76b2 4355 return NETDEV_TX_OK;
65689fef 4356 }
9d5c8243 4357
cd392f5c 4358 igb_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
85ad76b2
AD		 4359
4360 /* Make sure there is space in the ring for the next send. */
e694e964 4361 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4362
9d5c8243
AK		 4363 return NETDEV_TX_OK;
4364}
4365
cd392f5c
AD		 4366static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4367 struct net_device *netdev)
9d5c8243
AK		 4368{
4369 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 4370 struct igb_ring *tx_ring;
661086df 4371 int r_idx = 0;
b1a436c3
AD		 4372
4373 if (test_bit(__IGB_DOWN, &adapter->state)) {
4374 dev_kfree_skb_any(skb);
4375 return NETDEV_TX_OK;
4376 }
4377
4378 if (skb->len <= 0) {
4379 dev_kfree_skb_any(skb);
4380 return NETDEV_TX_OK;
4381 }
4382
1bfaf07b 4383 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 4384 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 4385
4386 /* This goes back to the question of how to logically map a tx queue
4387 * to a flow. Right now, performance is impacted slightly negatively
4388 * if using multiple tx queues. If the stack breaks away from a
4389 * single qdisc implementation, we can look at this again. */
cd392f5c 4390 return igb_xmit_frame_ring(skb, tx_ring);
9d5c8243
AK		 4391}
4392
4393/**
4394 * igb_tx_timeout - Respond to a Tx Hang
4395 * @netdev: network interface device structure
4396 **/
4397static void igb_tx_timeout(struct net_device *netdev)
4398{
4399 struct igb_adapter *adapter = netdev_priv(netdev);
4400 struct e1000_hw *hw = &adapter->hw;
4401
4402 /* Do the reset outside of interrupt context */
4403 adapter->tx_timeout_count++;
f7ba205e 4404
55cac248
AD		 4405 if (hw->mac.type == e1000_82580)
4406 hw->dev_spec._82575.global_device_reset = true;
4407
9d5c8243 4408 schedule_work(&adapter->reset_task);
265de409
AD		 4409 wr32(E1000_EICS,
4410 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4411}
4412
4413static void igb_reset_task(struct work_struct *work)
4414{
4415 struct igb_adapter *adapter;
4416 adapter = container_of(work, struct igb_adapter, reset_task);
4417
c97ec42a
TI		 4418 igb_dump(adapter);
4419 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4420 igb_reinit_locked(adapter);
4421}
4422
4423/**
12dcd86b 4424 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4425 * @netdev: network interface device structure
12dcd86b 4426 * @stats: rtnl_link_stats64 pointer
9d5c8243 4427 *
9d5c8243 4428 **/
12dcd86b
ED		 4429static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4430 struct rtnl_link_stats64 *stats)
9d5c8243 4431{
12dcd86b
ED		 4432 struct igb_adapter *adapter = netdev_priv(netdev);
4433
4434 spin_lock(&adapter->stats64_lock);
4435 igb_update_stats(adapter, &adapter->stats64);
4436 memcpy(stats, &adapter->stats64, sizeof(*stats));
4437 spin_unlock(&adapter->stats64_lock);
4438
4439 return stats;
9d5c8243
AK		 4440}
4441
4442/**
4443 * igb_change_mtu - Change the Maximum Transfer Unit
4444 * @netdev: network interface device structure
4445 * @new_mtu: new value for maximum frame size
4446 *
4447 * Returns 0 on success, negative on failure
4448 **/
4449static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4450{
4451 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4452 struct pci_dev *pdev = adapter->pdev;
153285f9 4453 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4454
c809d227 4455 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4456 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4457 return -EINVAL;
4458 }
4459
153285f9 4460#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4461 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4462 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4463 return -EINVAL;
4464 }
4465
4466 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4467 msleep(1);
73cd78f1 4468
9d5c8243
AK		 4469 /* igb_down has a dependency on max_frame_size */
4470 adapter->max_frame_size = max_frame;
559e9c49 4471
4c844851
AD		 4472 if (netif_running(netdev))
4473 igb_down(adapter);
9d5c8243 4474
090b1795 4475 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4476 netdev->mtu, new_mtu);
4477 netdev->mtu = new_mtu;
4478
4479 if (netif_running(netdev))
4480 igb_up(adapter);
4481 else
4482 igb_reset(adapter);
4483
4484 clear_bit(__IGB_RESETTING, &adapter->state);
4485
4486 return 0;
4487}
4488
4489/**
4490 * igb_update_stats - Update the board statistics counters
4491 * @adapter: board private structure
4492 **/
4493
12dcd86b
ED		 4494void igb_update_stats(struct igb_adapter *adapter,
4495 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4496{
4497 struct e1000_hw *hw = &adapter->hw;
4498 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4499 u32 reg, mpc;
9d5c8243 4500 u16 phy_tmp;
3f9c0164
AD		 4501 int i;
4502 u64 bytes, packets;
12dcd86b
ED		 4503 unsigned int start;
4504 u64 _bytes, _packets;
9d5c8243
AK		 4505
4506#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4507
4508 /*
4509 * Prevent stats update while adapter is being reset, or if the pci
4510 * connection is down.
4511 */
4512 if (adapter->link_speed == 0)
4513 return;
4514 if (pci_channel_offline(pdev))
4515 return;
4516
3f9c0164
AD		 4517 bytes = 0;
4518 packets = 0;
4519 for (i = 0; i < adapter->num_rx_queues; i++) {
4520 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446 4521 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4522
3025a446 4523 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 4524 net_stats->rx_fifo_errors += rqdpc_tmp;
12dcd86b
ED		 4525
4526 do {
4527 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4528 _bytes = ring->rx_stats.bytes;
4529 _packets = ring->rx_stats.packets;
4530 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4531 bytes += _bytes;
4532 packets += _packets;
3f9c0164
AD		 4533 }
4534
128e45eb
AD		 4535 net_stats->rx_bytes = bytes;
4536 net_stats->rx_packets = packets;
3f9c0164
AD		 4537
4538 bytes = 0;
4539 packets = 0;
4540 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4541 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4542 do {
4543 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4544 _bytes = ring->tx_stats.bytes;
4545 _packets = ring->tx_stats.packets;
4546 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4547 bytes += _bytes;
4548 packets += _packets;
3f9c0164 4549 }
128e45eb
AD		 4550 net_stats->tx_bytes = bytes;
4551 net_stats->tx_packets = packets;
3f9c0164
AD		 4552
4553 /* read stats registers */
9d5c8243
AK		 4554 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4555 adapter->stats.gprc += rd32(E1000_GPRC);
4556 adapter->stats.gorc += rd32(E1000_GORCL);
4557 rd32(E1000_GORCH); /* clear GORCL */
4558 adapter->stats.bprc += rd32(E1000_BPRC);
4559 adapter->stats.mprc += rd32(E1000_MPRC);
4560 adapter->stats.roc += rd32(E1000_ROC);
4561
4562 adapter->stats.prc64 += rd32(E1000_PRC64);
4563 adapter->stats.prc127 += rd32(E1000_PRC127);
4564 adapter->stats.prc255 += rd32(E1000_PRC255);
4565 adapter->stats.prc511 += rd32(E1000_PRC511);
4566 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4567 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4568 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4569 adapter->stats.sec += rd32(E1000_SEC);
4570
fa3d9a6d
MW		 4571 mpc = rd32(E1000_MPC);
4572 adapter->stats.mpc += mpc;
4573 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4574 adapter->stats.scc += rd32(E1000_SCC);
4575 adapter->stats.ecol += rd32(E1000_ECOL);
4576 adapter->stats.mcc += rd32(E1000_MCC);
4577 adapter->stats.latecol += rd32(E1000_LATECOL);
4578 adapter->stats.dc += rd32(E1000_DC);
4579 adapter->stats.rlec += rd32(E1000_RLEC);
4580 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4581 adapter->stats.xontxc += rd32(E1000_XONTXC);
4582 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4583 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4584 adapter->stats.fcruc += rd32(E1000_FCRUC);
4585 adapter->stats.gptc += rd32(E1000_GPTC);
4586 adapter->stats.gotc += rd32(E1000_GOTCL);
4587 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4588 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4589 adapter->stats.ruc += rd32(E1000_RUC);
4590 adapter->stats.rfc += rd32(E1000_RFC);
4591 adapter->stats.rjc += rd32(E1000_RJC);
4592 adapter->stats.tor += rd32(E1000_TORH);
4593 adapter->stats.tot += rd32(E1000_TOTH);
4594 adapter->stats.tpr += rd32(E1000_TPR);
4595
4596 adapter->stats.ptc64 += rd32(E1000_PTC64);
4597 adapter->stats.ptc127 += rd32(E1000_PTC127);
4598 adapter->stats.ptc255 += rd32(E1000_PTC255);
4599 adapter->stats.ptc511 += rd32(E1000_PTC511);
4600 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4601 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4602
4603 adapter->stats.mptc += rd32(E1000_MPTC);
4604 adapter->stats.bptc += rd32(E1000_BPTC);
4605
2d0b0f69
NN		 4606 adapter->stats.tpt += rd32(E1000_TPT);
4607 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4608
4609 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4610 /* read internal phy specific stats */
4611 reg = rd32(E1000_CTRL_EXT);
4612 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4613 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4614 adapter->stats.tncrs += rd32(E1000_TNCRS);
4615 }
4616
9d5c8243
AK		 4617 adapter->stats.tsctc += rd32(E1000_TSCTC);
4618 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4619
4620 adapter->stats.iac += rd32(E1000_IAC);
4621 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4622 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4623 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4624 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4625 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4626 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4627 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4628 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4629
4630 /* Fill out the OS statistics structure */
128e45eb
AD		 4631 net_stats->multicast = adapter->stats.mprc;
4632 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4633
4634 /* Rx Errors */
4635
4636 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4637 * our own version based on RUC and ROC */
128e45eb 4638 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4639 adapter->stats.crcerrs + adapter->stats.algnerrc +
4640 adapter->stats.ruc + adapter->stats.roc +
4641 adapter->stats.cexterr;
128e45eb
AD		 4642 net_stats->rx_length_errors = adapter->stats.ruc +
4643 adapter->stats.roc;
4644 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4645 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4646 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4647
4648 /* Tx Errors */
128e45eb
AD		 4649 net_stats->tx_errors = adapter->stats.ecol +
4650 adapter->stats.latecol;
4651 net_stats->tx_aborted_errors = adapter->stats.ecol;
4652 net_stats->tx_window_errors = adapter->stats.latecol;
4653 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4654
4655 /* Tx Dropped needs to be maintained elsewhere */
4656
4657 /* Phy Stats */
4658 if (hw->phy.media_type == e1000_media_type_copper) {
4659 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4660 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4661 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4662 adapter->phy_stats.idle_errors += phy_tmp;
4663 }
4664 }
4665
4666 /* Management Stats */
4667 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4668 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4669 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4670
4671 /* OS2BMC Stats */
4672 reg = rd32(E1000_MANC);
4673 if (reg & E1000_MANC_EN_BMC2OS) {
4674 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4675 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4676 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4677 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4678 }
9d5c8243
AK		 4679}
4680
9d5c8243
AK		 4681static irqreturn_t igb_msix_other(int irq, void *data)
4682{
047e0030 4683 struct igb_adapter *adapter = data;
9d5c8243 4684 struct e1000_hw *hw = &adapter->hw;
844290e5 4685 u32 icr = rd32(E1000_ICR);
844290e5 4686 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4687
7f081d40
AD		 4688 if (icr & E1000_ICR_DRSTA)
4689 schedule_work(&adapter->reset_task);
4690
047e0030 4691 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4692 /* HW is reporting DMA is out of sync */
4693 adapter->stats.doosync++;
13800469
GR		 4694 /* The DMA Out of Sync is also indication of a spoof event
4695 * in IOV mode. Check the Wrong VM Behavior register to
4696 * see if it is really a spoof event. */
4697 igb_check_wvbr(adapter);
dda0e083 4698 }
eebbbdba 4699
4ae196df
AD		 4700 /* Check for a mailbox event */
4701 if (icr & E1000_ICR_VMMB)
4702 igb_msg_task(adapter);
4703
4704 if (icr & E1000_ICR_LSC) {
4705 hw->mac.get_link_status = 1;
4706 /* guard against interrupt when we're going down */
4707 if (!test_bit(__IGB_DOWN, &adapter->state))
4708 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4709 }
4710
25568a53
AD		 4711 if (adapter->vfs_allocated_count)
4712 wr32(E1000_IMS, E1000_IMS_LSC |
4713 E1000_IMS_VMMB |
4714 E1000_IMS_DOUTSYNC);
4715 else
4716 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4717 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4718
4719 return IRQ_HANDLED;
4720}
4721
047e0030 4722static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4723{
26b39276 4724 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4725 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4726
047e0030
AD		 4727 if (!q_vector->set_itr)
4728 return;
73cd78f1 4729
047e0030
AD		 4730 if (!itr_val)
4731 itr_val = 0x4;
661086df 4732
26b39276
AD		 4733 if (adapter->hw.mac.type == e1000_82575)
4734 itr_val |= itr_val << 16;
661086df 4735 else
047e0030 4736 itr_val |= 0x8000000;
661086df 4737
047e0030
AD		 4738 writel(itr_val, q_vector->itr_register);
4739 q_vector->set_itr = 0;
6eb5a7f1
AD		 4740}
4741
047e0030 4742static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4743{
047e0030 4744 struct igb_q_vector *q_vector = data;
9d5c8243 4745
047e0030
AD		 4746 /* Write the ITR value calculated from the previous interrupt. */
4747 igb_write_itr(q_vector);
9d5c8243 4748
047e0030 4749 napi_schedule(&q_vector->napi);
844290e5 4750
047e0030 4751 return IRQ_HANDLED;
fe4506b6
JC		 4752}
4753
421e02f0 4754#ifdef CONFIG_IGB_DCA
047e0030 4755static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4756{
047e0030 4757 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4758 struct e1000_hw *hw = &adapter->hw;
4759 int cpu = get_cpu();
fe4506b6 4760
047e0030
AD		 4761 if (q_vector->cpu == cpu)
4762 goto out_no_update;
4763
4764 if (q_vector->tx_ring) {
4765 int q = q_vector->tx_ring->reg_idx;
4766 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4767 if (hw->mac.type == e1000_82575) {
4768 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4769 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4770 } else {
047e0030
AD		 4771 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4772 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4773 E1000_DCA_TXCTRL_CPUID_SHIFT;
4774 }
4775 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4776 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4777 }
4778 if (q_vector->rx_ring) {
4779 int q = q_vector->rx_ring->reg_idx;
4780 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4781 if (hw->mac.type == e1000_82575) {
2d064c06 4782 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4783 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4784 } else {
4785 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4786 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4787 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4788 }
fe4506b6
JC		 4789 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4790 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4791 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4792 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4793 }
047e0030
AD		 4794 q_vector->cpu = cpu;
4795out_no_update:
fe4506b6
JC		 4796 put_cpu();
4797}
4798
4799static void igb_setup_dca(struct igb_adapter *adapter)
4800{
7e0e99ef 4801 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4802 int i;
4803
7dfc16fa 4804 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4805 return;
4806
7e0e99ef
AD		 4807 /* Always use CB2 mode, difference is masked in the CB driver. */
4808 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4809
047e0030 4810 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4811 adapter->q_vector[i]->cpu = -1;
4812 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4813 }
4814}
4815
4816static int __igb_notify_dca(struct device *dev, void *data)
4817{
4818 struct net_device *netdev = dev_get_drvdata(dev);
4819 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4820 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4821 struct e1000_hw *hw = &adapter->hw;
4822 unsigned long event = *(unsigned long *)data;
4823
4824 switch (event) {
4825 case DCA_PROVIDER_ADD:
4826 /* if already enabled, don't do it again */
7dfc16fa 4827 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4828 break;
fe4506b6 4829 if (dca_add_requester(dev) == 0) {
bbd98fe4 4830 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4831 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4832 igb_setup_dca(adapter);
4833 break;
4834 }
4835 /* Fall Through since DCA is disabled. */
4836 case DCA_PROVIDER_REMOVE:
7dfc16fa 4837 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4838 /* without this a class_device is left
047e0030 4839 * hanging around in the sysfs model */
fe4506b6 4840 dca_remove_requester(dev);
090b1795 4841 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4842 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4843 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4844 }
4845 break;
4846 }
bbd98fe4 4847
fe4506b6 4848 return 0;
9d5c8243
AK		 4849}
4850
fe4506b6
JC		 4851static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4852 void *p)
4853{
4854 int ret_val;
4855
4856 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4857 __igb_notify_dca);
4858
4859 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4860}
421e02f0 4861#endif /* CONFIG_IGB_DCA */
9d5c8243 4862
4ae196df
AD		 4863static void igb_ping_all_vfs(struct igb_adapter *adapter)
4864{
4865 struct e1000_hw *hw = &adapter->hw;
4866 u32 ping;
4867 int i;
4868
4869 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4870 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4871 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4872 ping |= E1000_VT_MSGTYPE_CTS;
4873 igb_write_mbx(hw, &ping, 1, i);
4874 }
4875}
4876
7d5753f0
AD		 4877static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4878{
4879 struct e1000_hw *hw = &adapter->hw;
4880 u32 vmolr = rd32(E1000_VMOLR(vf));
4881 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4882
d85b9004 4883 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 4884 IGB_VF_FLAG_MULTI_PROMISC);
4885 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4886
4887 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4888 vmolr |= E1000_VMOLR_MPME;
d85b9004 4889 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 4890 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4891 } else {
4892 /*
4893 * if we have hashes and we are clearing a multicast promisc
4894 * flag we need to write the hashes to the MTA as this step
4895 * was previously skipped
4896 */
4897 if (vf_data->num_vf_mc_hashes > 30) {
4898 vmolr |= E1000_VMOLR_MPME;
4899 } else if (vf_data->num_vf_mc_hashes) {
4900 int j;
4901 vmolr |= E1000_VMOLR_ROMPE;
4902 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4903 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4904 }
4905 }
4906
4907 wr32(E1000_VMOLR(vf), vmolr);
4908
4909 /* there are flags left unprocessed, likely not supported */
4910 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4911 return -EINVAL;
4912
4913 return 0;
4914
4915}
4916
4ae196df
AD		 4917static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4918 u32 *msgbuf, u32 vf)
4919{
4920 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4921 u16 *hash_list = (u16 *)&msgbuf[1];
4922 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4923 int i;
4924
7d5753f0 4925 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4926 * to this VF for later use to restore when the PF multi cast
4927 * list changes
4928 */
4929 vf_data->num_vf_mc_hashes = n;
4930
7d5753f0
AD		 4931 /* only up to 30 hash values supported */
4932 if (n > 30)
4933 n = 30;
4934
4935 /* store the hashes for later use */
4ae196df 4936 for (i = 0; i < n; i++)
a419aef8 4937 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4938
4939 /* Flush and reset the mta with the new values */
ff41f8dc 4940 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4941
4942 return 0;
4943}
4944
4945static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4946{
4947 struct e1000_hw *hw = &adapter->hw;
4948 struct vf_data_storage *vf_data;
4949 int i, j;
4950
4951 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4952 u32 vmolr = rd32(E1000_VMOLR(i));
4953 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4954
4ae196df 4955 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4956
4957 if ((vf_data->num_vf_mc_hashes > 30) ||
4958 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4959 vmolr |= E1000_VMOLR_MPME;
4960 } else if (vf_data->num_vf_mc_hashes) {
4961 vmolr |= E1000_VMOLR_ROMPE;
4962 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4963 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4964 }
4965 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4966 }
4967}
4968
4969static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4970{
4971 struct e1000_hw *hw = &adapter->hw;
4972 u32 pool_mask, reg, vid;
4973 int i;
4974
4975 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4976
4977 /* Find the vlan filter for this id */
4978 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4979 reg = rd32(E1000_VLVF(i));
4980
4981 /* remove the vf from the pool */
4982 reg &= ~pool_mask;
4983
4984 /* if pool is empty then remove entry from vfta */
4985 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4986 (reg & E1000_VLVF_VLANID_ENABLE)) {
4987 reg = 0;
4988 vid = reg & E1000_VLVF_VLANID_MASK;
4989 igb_vfta_set(hw, vid, false);
4990 }
4991
4992 wr32(E1000_VLVF(i), reg);
4993 }
ae641bdc
AD		 4994
4995 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4996}
4997
4998static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4999{
5000 struct e1000_hw *hw = &adapter->hw;
5001 u32 reg, i;
5002
51466239
AD		 5003 /* The vlvf table only exists on 82576 hardware and newer */
5004 if (hw->mac.type < e1000_82576)
5005 return -1;
5006
5007 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5008 if (!adapter->vfs_allocated_count)
5009 return -1;
5010
5011 /* Find the vlan filter for this id */
5012 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5013 reg = rd32(E1000_VLVF(i));
5014 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5015 vid == (reg & E1000_VLVF_VLANID_MASK))
5016 break;
5017 }
5018
5019 if (add) {
5020 if (i == E1000_VLVF_ARRAY_SIZE) {
5021 /* Did not find a matching VLAN ID entry that was
5022 * enabled. Search for a free filter entry, i.e.
5023 * one without the enable bit set
5024 */
5025 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5026 reg = rd32(E1000_VLVF(i));
5027 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5028 break;
5029 }
5030 }
5031 if (i < E1000_VLVF_ARRAY_SIZE) {
5032 /* Found an enabled/available entry */
5033 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5034
5035 /* if !enabled we need to set this up in vfta */
5036 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5037 /* add VID to filter table */
5038 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5039 reg |= E1000_VLVF_VLANID_ENABLE;
5040 }
cad6d05f
AD		 5041 reg &= ~E1000_VLVF_VLANID_MASK;
5042 reg |= vid;
4ae196df 5043 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5044
5045 /* do not modify RLPML for PF devices */
5046 if (vf >= adapter->vfs_allocated_count)
5047 return 0;
5048
5049 if (!adapter->vf_data[vf].vlans_enabled) {
5050 u32 size;
5051 reg = rd32(E1000_VMOLR(vf));
5052 size = reg & E1000_VMOLR_RLPML_MASK;
5053 size += 4;
5054 reg &= ~E1000_VMOLR_RLPML_MASK;
5055 reg |= size;
5056 wr32(E1000_VMOLR(vf), reg);
5057 }
ae641bdc 5058
51466239 5059 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5060 return 0;
5061 }
5062 } else {
5063 if (i < E1000_VLVF_ARRAY_SIZE) {
5064 /* remove vf from the pool */
5065 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5066 /* if pool is empty then remove entry from vfta */
5067 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5068 reg = 0;
5069 igb_vfta_set(hw, vid, false);
5070 }
5071 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5072
5073 /* do not modify RLPML for PF devices */
5074 if (vf >= adapter->vfs_allocated_count)
5075 return 0;
5076
5077 adapter->vf_data[vf].vlans_enabled--;
5078 if (!adapter->vf_data[vf].vlans_enabled) {
5079 u32 size;
5080 reg = rd32(E1000_VMOLR(vf));
5081 size = reg & E1000_VMOLR_RLPML_MASK;
5082 size -= 4;
5083 reg &= ~E1000_VMOLR_RLPML_MASK;
5084 reg |= size;
5085 wr32(E1000_VMOLR(vf), reg);
5086 }
4ae196df
AD		 5087 }
5088 }
8151d294
WM		 5089 return 0;
5090}
5091
5092static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5093{
5094 struct e1000_hw *hw = &adapter->hw;
5095
5096 if (vid)
5097 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5098 else
5099 wr32(E1000_VMVIR(vf), 0);
5100}
5101
5102static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5103 int vf, u16 vlan, u8 qos)
5104{
5105 int err = 0;
5106 struct igb_adapter *adapter = netdev_priv(netdev);
5107
5108 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5109 return -EINVAL;
5110 if (vlan || qos) {
5111 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5112 if (err)
5113 goto out;
5114 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5115 igb_set_vmolr(adapter, vf, !vlan);
5116 adapter->vf_data[vf].pf_vlan = vlan;
5117 adapter->vf_data[vf].pf_qos = qos;
5118 dev_info(&adapter->pdev->dev,
5119 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5120 if (test_bit(__IGB_DOWN, &adapter->state)) {
5121 dev_warn(&adapter->pdev->dev,
5122 "The VF VLAN has been set,"
5123 " but the PF device is not up.\n");
5124 dev_warn(&adapter->pdev->dev,
5125 "Bring the PF device up before"
5126 " attempting to use the VF device.\n");
5127 }
5128 } else {
5129 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5130 false, vf);
5131 igb_set_vmvir(adapter, vlan, vf);
5132 igb_set_vmolr(adapter, vf, true);
5133 adapter->vf_data[vf].pf_vlan = 0;
5134 adapter->vf_data[vf].pf_qos = 0;
5135 }
5136out:
5137 return err;
4ae196df
AD		 5138}
5139
5140static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5141{
5142 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5143 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5144
5145 return igb_vlvf_set(adapter, vid, add, vf);
5146}
5147
f2ca0dbe 5148static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5149{
8fa7e0f7
GR		 5150 /* clear flags - except flag that indicates PF has set the MAC */
5151 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5152 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5153
5154 /* reset offloads to defaults */
8151d294 5155 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5156
5157 /* reset vlans for device */
5158 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5159 if (adapter->vf_data[vf].pf_vlan)
5160 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5161 adapter->vf_data[vf].pf_vlan,
5162 adapter->vf_data[vf].pf_qos);
5163 else
5164 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5165
5166 /* reset multicast table array for vf */
5167 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5168
5169 /* Flush and reset the mta with the new values */
ff41f8dc 5170 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5171}
5172
f2ca0dbe
AD		 5173static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5174{
5175 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5176
5177 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 5178 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5179 random_ether_addr(vf_mac);
f2ca0dbe
AD		 5180
5181 /* process remaining reset events */
5182 igb_vf_reset(adapter, vf);
5183}
5184
5185static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5186{
5187 struct e1000_hw *hw = &adapter->hw;
5188 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5189 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5190 u32 reg, msgbuf[3];
5191 u8 *addr = (u8 *)(&msgbuf[1]);
5192
5193 /* process all the same items cleared in a function level reset */
f2ca0dbe 5194 igb_vf_reset(adapter, vf);
4ae196df
AD		 5195
5196 /* set vf mac address */
26ad9178 5197 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5198
5199 /* enable transmit and receive for vf */
5200 reg = rd32(E1000_VFTE);
5201 wr32(E1000_VFTE, reg | (1 << vf));
5202 reg = rd32(E1000_VFRE);
5203 wr32(E1000_VFRE, reg | (1 << vf));
5204
8fa7e0f7 5205 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5206
5207 /* reply to reset with ack and vf mac address */
5208 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5209 memcpy(addr, vf_mac, 6);
5210 igb_write_mbx(hw, msgbuf, 3, vf);
5211}
5212
5213static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5214{
de42edde
GR		 5215 /*
5216 * The VF MAC Address is stored in a packed array of bytes
5217 * starting at the second 32 bit word of the msg array
5218 */
f2ca0dbe
AD		 5219 unsigned char *addr = (char *)&msg[1];
5220 int err = -1;
4ae196df 5221
f2ca0dbe
AD		 5222 if (is_valid_ether_addr(addr))
5223 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5224
f2ca0dbe 5225 return err;
4ae196df
AD		 5226}
5227
5228static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5229{
5230 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5231 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5232 u32 msg = E1000_VT_MSGTYPE_NACK;
5233
5234 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5235 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5236 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5237 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5238 vf_data->last_nack = jiffies;
4ae196df
AD		 5239 }
5240}
5241
f2ca0dbe 5242static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5243{
f2ca0dbe
AD		 5244 struct pci_dev *pdev = adapter->pdev;
5245 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5246 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5247 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5248 s32 retval;
5249
f2ca0dbe 5250 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5251
fef45f4c
AD		 5252 if (retval) {
5253 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5254 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5255 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5256 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5257 return;
5258 goto out;
5259 }
4ae196df
AD		 5260
5261 /* this is a message we already processed, do nothing */
5262 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5263 return;
4ae196df
AD		 5264
5265 /*
5266 * until the vf completes a reset it should not be
5267 * allowed to start any configuration.
5268 */
5269
5270 if (msgbuf[0] == E1000_VF_RESET) {
5271 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5272 return;
4ae196df
AD		 5273 }
5274
f2ca0dbe 5275 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5276 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5277 return;
5278 retval = -1;
5279 goto out;
4ae196df
AD		 5280 }
5281
5282 switch ((msgbuf[0] & 0xFFFF)) {
5283 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5284 retval = -EINVAL;
5285 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5286 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5287 else
5288 dev_warn(&pdev->dev,
5289 "VF %d attempted to override administratively "
5290 "set MAC address\nReload the VF driver to "
5291 "resume operations\n", vf);
4ae196df 5292 break;
7d5753f0
AD		 5293 case E1000_VF_SET_PROMISC:
5294 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5295 break;
4ae196df
AD		 5296 case E1000_VF_SET_MULTICAST:
5297 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5298 break;
5299 case E1000_VF_SET_LPE:
5300 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5301 break;
5302 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5303 retval = -1;
5304 if (vf_data->pf_vlan)
5305 dev_warn(&pdev->dev,
5306 "VF %d attempted to override administratively "
5307 "set VLAN tag\nReload the VF driver to "
5308 "resume operations\n", vf);
8151d294
WM		 5309 else
5310 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5311 break;
5312 default:
090b1795 5313 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5314 retval = -1;
5315 break;
5316 }
5317
fef45f4c
AD		 5318 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5319out:
4ae196df
AD		 5320 /* notify the VF of the results of what it sent us */
5321 if (retval)
5322 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5323 else
5324 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5325
4ae196df 5326 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5327}
4ae196df 5328
f2ca0dbe
AD		 5329static void igb_msg_task(struct igb_adapter *adapter)
5330{
5331 struct e1000_hw *hw = &adapter->hw;
5332 u32 vf;
5333
5334 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5335 /* process any reset requests */
5336 if (!igb_check_for_rst(hw, vf))
5337 igb_vf_reset_event(adapter, vf);
5338
5339 /* process any messages pending */
5340 if (!igb_check_for_msg(hw, vf))
5341 igb_rcv_msg_from_vf(adapter, vf);
5342
5343 /* process any acks */
5344 if (!igb_check_for_ack(hw, vf))
5345 igb_rcv_ack_from_vf(adapter, vf);
5346 }
4ae196df
AD		 5347}
5348
68d480c4
AD		 5349/**
5350 * igb_set_uta - Set unicast filter table address
5351 * @adapter: board private structure
5352 *
5353 * The unicast table address is a register array of 32-bit registers.
5354 * The table is meant to be used in a way similar to how the MTA is used
5355 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5356 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5357 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5358 **/
5359static void igb_set_uta(struct igb_adapter *adapter)
5360{
5361 struct e1000_hw *hw = &adapter->hw;
5362 int i;
5363
5364 /* The UTA table only exists on 82576 hardware and newer */
5365 if (hw->mac.type < e1000_82576)
5366 return;
5367
5368 /* we only need to do this if VMDq is enabled */
5369 if (!adapter->vfs_allocated_count)
5370 return;
5371
5372 for (i = 0; i < hw->mac.uta_reg_count; i++)
5373 array_wr32(E1000_UTA, i, ~0);
5374}
5375
9d5c8243
AK		 5376/**
5377 * igb_intr_msi - Interrupt Handler
5378 * @irq: interrupt number
5379 * @data: pointer to a network interface device structure
5380 **/
5381static irqreturn_t igb_intr_msi(int irq, void *data)
5382{
047e0030
AD		 5383 struct igb_adapter *adapter = data;
5384 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5385 struct e1000_hw *hw = &adapter->hw;
5386 /* read ICR disables interrupts using IAM */
5387 u32 icr = rd32(E1000_ICR);
5388
047e0030 5389 igb_write_itr(q_vector);
9d5c8243 5390
7f081d40
AD		 5391 if (icr & E1000_ICR_DRSTA)
5392 schedule_work(&adapter->reset_task);
5393
047e0030 5394 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5395 /* HW is reporting DMA is out of sync */
5396 adapter->stats.doosync++;
5397 }
5398
9d5c8243
AK		 5399 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5400 hw->mac.get_link_status = 1;
5401 if (!test_bit(__IGB_DOWN, &adapter->state))
5402 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5403 }
5404
047e0030 5405 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5406
5407 return IRQ_HANDLED;
5408}
5409
5410/**
4a3c6433 5411 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5412 * @irq: interrupt number
5413 * @data: pointer to a network interface device structure
5414 **/
5415static irqreturn_t igb_intr(int irq, void *data)
5416{
047e0030
AD		 5417 struct igb_adapter *adapter = data;
5418 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5419 struct e1000_hw *hw = &adapter->hw;
5420 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5421 * need for the IMC write */
5422 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5423 if (!icr)
5424 return IRQ_NONE; /* Not our interrupt */
5425
047e0030 5426 igb_write_itr(q_vector);
9d5c8243
AK		 5427
5428 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5429 * not set, then the adapter didn't send an interrupt */
5430 if (!(icr & E1000_ICR_INT_ASSERTED))
5431 return IRQ_NONE;
5432
7f081d40
AD		 5433 if (icr & E1000_ICR_DRSTA)
5434 schedule_work(&adapter->reset_task);
5435
047e0030 5436 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5437 /* HW is reporting DMA is out of sync */
5438 adapter->stats.doosync++;
5439 }
5440
9d5c8243
AK		 5441 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5442 hw->mac.get_link_status = 1;
5443 /* guard against interrupt when we're going down */
5444 if (!test_bit(__IGB_DOWN, &adapter->state))
5445 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5446 }
5447
047e0030 5448 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5449
5450 return IRQ_HANDLED;
5451}
5452
047e0030 5453static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5454{
047e0030 5455 struct igb_adapter *adapter = q_vector->adapter;
46544258 5456 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5457
4fc82adf
AD		 5458 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
5459 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 5460 if (!adapter->msix_entries)
6eb5a7f1 5461 igb_set_itr(adapter);
46544258 5462 else
047e0030 5463 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5464 }
5465
46544258
AD		 5466 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5467 if (adapter->msix_entries)
047e0030 5468 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5469 else
5470 igb_irq_enable(adapter);
5471 }
9d5c8243
AK		 5472}
5473
46544258
AD		 5474/**
5475 * igb_poll - NAPI Rx polling callback
5476 * @napi: napi polling structure
5477 * @budget: count of how many packets we should handle
5478 **/
5479static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5480{
047e0030
AD		 5481 struct igb_q_vector *q_vector = container_of(napi,
5482 struct igb_q_vector,
5483 napi);
16eb8815 5484 bool clean_complete = true;
9d5c8243 5485
421e02f0 5486#ifdef CONFIG_IGB_DCA
047e0030
AD		 5487 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5488 igb_update_dca(q_vector);
fe4506b6 5489#endif
047e0030 5490 if (q_vector->tx_ring)
16eb8815 5491 clean_complete = !!igb_clean_tx_irq(q_vector);
9d5c8243 5492
047e0030 5493 if (q_vector->rx_ring)
cd392f5c 5494 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5495
16eb8815
AD		 5496 /* If all work not completed, return budget and keep polling */
5497 if (!clean_complete)
5498 return budget;
46544258 5499
9d5c8243 5500 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5501 napi_complete(napi);
5502 igb_ring_irq_enable(q_vector);
9d5c8243 5503
16eb8815 5504 return 0;
9d5c8243 5505}
6d8126f9 5506
33af6bcc 5507/**
c5b9bd5e 5508 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 5509 * @adapter: board private structure
c5b9bd5e
AD		 5510 * @shhwtstamps: timestamp structure to update
5511 * @regval: unsigned 64bit system time value.
5512 *
5513 * We need to convert the system time value stored in the RX/TXSTMP registers
5514 * into a hwtstamp which can be used by the upper level timestamping functions
5515 */
5516static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5517 struct skb_shared_hwtstamps *shhwtstamps,
5518 u64 regval)
5519{
5520 u64 ns;
5521
55cac248
AD		 5522 /*
5523 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5524 * 24 to match clock shift we setup earlier.
5525 */
5526 if (adapter->hw.mac.type == e1000_82580)
5527 regval <<= IGB_82580_TSYNC_SHIFT;
5528
c5b9bd5e
AD		 5529 ns = timecounter_cyc2time(&adapter->clock, regval);
5530 timecompare_update(&adapter->compare, ns);
5531 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5532 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5533 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5534}
5535
5536/**
5537 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5538 * @q_vector: pointer to q_vector containing needed info
2873957d 5539 * @buffer: pointer to igb_buffer structure
33af6bcc
PO		 5540 *
5541 * If we were asked to do hardware stamping and such a time stamp is
5542 * available, then it must have been for this skb here because we only
5543 * allow only one such packet into the queue.
5544 */
2873957d 5545static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct igb_buffer *buffer_info)
33af6bcc 5546{
c5b9bd5e 5547 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc 5548 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 5549 struct skb_shared_hwtstamps shhwtstamps;
5550 u64 regval;
33af6bcc 5551
c5b9bd5e 5552 /* if skb does not support hw timestamp or TX stamp not valid exit */
2244d07b 5553 if (likely(!(buffer_info->tx_flags & SKBTX_HW_TSTAMP)) ||
c5b9bd5e
AD		 5554 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5555 return;
5556
5557 regval = rd32(E1000_TXSTMPL);
5558 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5559
5560 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
2873957d 5561 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
33af6bcc
PO		 5562}
5563
9d5c8243
AK		 5564/**
5565 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5566 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 5567 * returns true if ring is completely cleaned
5568 **/
047e0030 5569static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5570{
047e0030
AD		 5571 struct igb_adapter *adapter = q_vector->adapter;
5572 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 5573 struct net_device *netdev = tx_ring->netdev;
0e014cb1 5574 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5575 struct igb_buffer *buffer_info;
0e014cb1 5576 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5577 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 5578 unsigned int i, eop, count = 0;
5579 bool cleaned = false;
9d5c8243 5580
9d5c8243 5581 i = tx_ring->next_to_clean;
0e014cb1
AD		 5582 eop = tx_ring->buffer_info[i].next_to_watch;
5583 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5584
5585 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
5586 (count < tx_ring->count)) {
2d0bb1c1 5587 rmb(); /* read buffer_info after eop_desc status */
0e014cb1
AD		 5588 for (cleaned = false; !cleaned; count++) {
5589 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5590 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5591 cleaned = (i == eop);
9d5c8243 5592
2873957d
NN		 5593 if (buffer_info->skb) {
5594 total_bytes += buffer_info->bytecount;
9d5c8243 5595 /* gso_segs is currently only valid for tcp */
2873957d
NN		 5596 total_packets += buffer_info->gso_segs;
5597 igb_tx_hwtstamp(q_vector, buffer_info);
9d5c8243
AK		 5598 }
5599
80785298 5600 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5601 tx_desc->wb.status = 0;
9d5c8243
AK		 5602
5603 i++;
5604 if (i == tx_ring->count)
5605 i = 0;
9d5c8243 5606 }
0e014cb1
AD		 5607 eop = tx_ring->buffer_info[i].next_to_watch;
5608 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5609 }
5610
9d5c8243
AK		 5611 tx_ring->next_to_clean = i;
5612
fc7d345d 5613 if (unlikely(count &&
9d5c8243 5614 netif_carrier_ok(netdev) &&
c493ea45 5615 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5616 /* Make sure that anybody stopping the queue after this
5617 * sees the new next_to_clean.
5618 */
5619 smp_mb();
661086df
PWJ		 5620 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5621 !(test_bit(__IGB_DOWN, &adapter->state))) {
5622 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 5623
5624 u64_stats_update_begin(&tx_ring->tx_syncp);
04a5fcaa 5625 tx_ring->tx_stats.restart_queue++;
12dcd86b 5626 u64_stats_update_end(&tx_ring->tx_syncp);
661086df 5627 }
9d5c8243
AK		 5628 }
5629
5630 if (tx_ring->detect_tx_hung) {
5631 /* Detect a transmit hang in hardware, this serializes the
5632 * check with the clearing of time_stamp and movement of i */
5633 tx_ring->detect_tx_hung = false;
5634 if (tx_ring->buffer_info[i].time_stamp &&
5635 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5636 (adapter->tx_timeout_factor * HZ)) &&
5637 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5638
9d5c8243 5639 /* detected Tx unit hang */
59d71989 5640 dev_err(tx_ring->dev,
9d5c8243 5641 "Detected Tx Unit Hang\n"
2d064c06 5642 " Tx Queue <%d>\n"
9d5c8243
AK		 5643 " TDH <%x>\n"
5644 " TDT <%x>\n"
5645 " next_to_use <%x>\n"
5646 " next_to_clean <%x>\n"
9d5c8243
AK		 5647 "buffer_info[next_to_clean]\n"
5648 " time_stamp <%lx>\n"
0e014cb1 5649 " next_to_watch <%x>\n"
9d5c8243
AK		 5650 " jiffies <%lx>\n"
5651 " desc.status <%x>\n",
2d064c06 5652 tx_ring->queue_index,
238ac817 5653 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5654 readl(tx_ring->tail),
9d5c8243
AK		 5655 tx_ring->next_to_use,
5656 tx_ring->next_to_clean,
f7ba205e 5657 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5658 eop,
9d5c8243 5659 jiffies,
0e014cb1 5660 eop_desc->wb.status);
661086df 5661 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5662 }
5663 }
5664 tx_ring->total_bytes += total_bytes;
5665 tx_ring->total_packets += total_packets;
12dcd86b 5666 u64_stats_update_begin(&tx_ring->tx_syncp);
e21ed353
AD		 5667 tx_ring->tx_stats.bytes += total_bytes;
5668 tx_ring->tx_stats.packets += total_packets;
12dcd86b 5669 u64_stats_update_end(&tx_ring->tx_syncp);
807540ba 5670 return count < tx_ring->count;
9d5c8243
AK		 5671}
5672
cd392f5c
AD		 5673static inline void igb_rx_checksum(struct igb_ring *ring,
5674 u32 status_err, struct sk_buff *skb)
9d5c8243 5675{
bc8acf2c 5676 skb_checksum_none_assert(skb);
9d5c8243
AK		 5677
5678 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5679 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5680 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5681 return;
85ad76b2 5682
9d5c8243
AK		 5683 /* TCP/UDP checksum error bit is set */
5684 if (status_err &
5685 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5686 /*
5687 * work around errata with sctp packets where the TCPE aka
5688 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5689 * packets, (aka let the stack check the crc32c)
5690 */
85ad76b2 5691 if ((skb->len == 60) &&
12dcd86b
ED		 5692 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) {
5693 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 5694 ring->rx_stats.csum_err++;
12dcd86b
ED		 5695 u64_stats_update_end(&ring->rx_syncp);
5696 }
9d5c8243 5697 /* let the stack verify checksum errors */
9d5c8243
AK		 5698 return;
5699 }
5700 /* It must be a TCP or UDP packet with a valid checksum */
5701 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5702 skb->ip_summed = CHECKSUM_UNNECESSARY;
5703
59d71989 5704 dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5705}
5706
757b77e2 5707static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
c5b9bd5e
AD		 5708 struct sk_buff *skb)
5709{
5710 struct igb_adapter *adapter = q_vector->adapter;
5711 struct e1000_hw *hw = &adapter->hw;
5712 u64 regval;
5713
5714 /*
5715 * If this bit is set, then the RX registers contain the time stamp. No
5716 * other packet will be time stamped until we read these registers, so
5717 * read the registers to make them available again. Because only one
5718 * packet can be time stamped at a time, we know that the register
5719 * values must belong to this one here and therefore we don't need to
5720 * compare any of the additional attributes stored for it.
5721 *
2244d07b 5722 * If nothing went wrong, then it should have a shared tx_flags that we
c5b9bd5e
AD		 5723 * can turn into a skb_shared_hwtstamps.
5724 */
757b77e2
NN		 5725 if (staterr & E1000_RXDADV_STAT_TSIP) {
5726 u32 *stamp = (u32 *)skb->data;
5727 regval = le32_to_cpu(*(stamp + 2));
5728 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5729 skb_pull(skb, IGB_TS_HDR_LEN);
5730 } else {
5731 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5732 return;
c5b9bd5e 5733
757b77e2
NN		 5734 regval = rd32(E1000_RXSTMPL);
5735 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5736 }
c5b9bd5e
AD		 5737
5738 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5739}
44390ca6 5740static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc)
2d94d8ab
AD		 5741{
5742 /* HW will not DMA in data larger than the given buffer, even if it
5743 * parses the (NFS, of course) header to be larger. In that case, it
5744 * fills the header buffer and spills the rest into the page.
5745 */
5746 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5747 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
44390ca6
AD		 5748 if (hlen > IGB_RX_HDR_LEN)
5749 hlen = IGB_RX_HDR_LEN;
2d94d8ab
AD		 5750 return hlen;
5751}
5752
cd392f5c 5753static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)
9d5c8243 5754{
047e0030 5755 struct igb_ring *rx_ring = q_vector->rx_ring;
16eb8815
AD		 5756 union e1000_adv_rx_desc *rx_desc;
5757 const int current_node = numa_node_id();
9d5c8243 5758 unsigned int total_bytes = 0, total_packets = 0;
2d94d8ab 5759 u32 staterr;
16eb8815
AD		 5760 u16 cleaned_count = igb_desc_unused(rx_ring);
5761 u16 i = rx_ring->next_to_clean;
9d5c8243 5762
9d5c8243
AK		 5763 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5764 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5765
5766 while (staterr & E1000_RXD_STAT_DD) {
16eb8815
AD		 5767 struct igb_buffer *buffer_info = &rx_ring->buffer_info[i];
5768 struct sk_buff *skb = buffer_info->skb;
5769 union e1000_adv_rx_desc *next_rxd;
9d5c8243 5770
69d3ca53 5771 buffer_info->skb = NULL;
16eb8815 5772 prefetch(skb->data);
69d3ca53
AD		 5773
5774 i++;
5775 if (i == rx_ring->count)
5776 i = 0;
42d0781a 5777
69d3ca53
AD		 5778 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5779 prefetch(next_rxd);
9d5c8243 5780
16eb8815
AD		 5781 /*
5782 * This memory barrier is needed to keep us from reading
5783 * any other fields out of the rx_desc until we know the
5784 * RXD_STAT_DD bit is set
5785 */
5786 rmb();
9d5c8243 5787
16eb8815
AD		 5788 if (!skb_is_nonlinear(skb)) {
5789 __skb_put(skb, igb_get_hlen(rx_desc));
5790 dma_unmap_single(rx_ring->dev, buffer_info->dma,
44390ca6 5791 IGB_RX_HDR_LEN,
59d71989 5792 DMA_FROM_DEVICE);
91615f76 5793 buffer_info->dma = 0;
bf36c1a0
AD		 5794 }
5795
16eb8815
AD		 5796 if (rx_desc->wb.upper.length) {
5797 u16 length = le16_to_cpu(rx_desc->wb.upper.length);
bf36c1a0 5798
aa913403 5799 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
bf36c1a0
AD		 5800 buffer_info->page,
5801 buffer_info->page_offset,
5802 length);
5803
16eb8815
AD		 5804 skb->len += length;
5805 skb->data_len += length;
5806 skb->truesize += length;
5807
d1eff350
AD		 5808 if ((page_count(buffer_info->page) != 1) ||
5809 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5810 buffer_info->page = NULL;
5811 else
5812 get_page(buffer_info->page);
9d5c8243 5813
16eb8815
AD		 5814 dma_unmap_page(rx_ring->dev, buffer_info->page_dma,
5815 PAGE_SIZE / 2, DMA_FROM_DEVICE);
5816 buffer_info->page_dma = 0;
9d5c8243 5817 }
9d5c8243 5818
bf36c1a0 5819 if (!(staterr & E1000_RXD_STAT_EOP)) {
16eb8815
AD		 5820 struct igb_buffer *next_buffer;
5821 next_buffer = &rx_ring->buffer_info[i];
b2d56536
AD		 5822 buffer_info->skb = next_buffer->skb;
5823 buffer_info->dma = next_buffer->dma;
5824 next_buffer->skb = skb;
5825 next_buffer->dma = 0;
bf36c1a0
AD		 5826 goto next_desc;
5827 }
44390ca6 5828
9d5c8243 5829 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
16eb8815 5830 dev_kfree_skb_any(skb);
9d5c8243
AK		 5831 goto next_desc;
5832 }
9d5c8243 5833
757b77e2
NN		 5834 if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
5835 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5836 total_bytes += skb->len;
5837 total_packets++;
5838
cd392f5c 5839 igb_rx_checksum(rx_ring, staterr, skb);
9d5c8243 5840
16eb8815 5841 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
047e0030 5842
b2cb09b1
JP		 5843 if (staterr & E1000_RXD_STAT_VP) {
5844 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
9d5c8243 5845
b2cb09b1
JP		 5846 __vlan_hwaccel_put_tag(skb, vid);
5847 }
5848 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 5849
16eb8815 5850 budget--;
9d5c8243 5851next_desc:
16eb8815
AD		 5852 if (!budget)
5853 break;
5854
5855 cleaned_count++;
9d5c8243
AK		 5856 /* return some buffers to hardware, one at a time is too slow */
5857 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
cd392f5c 5858 igb_alloc_rx_buffers(rx_ring, cleaned_count);
9d5c8243
AK		 5859 cleaned_count = 0;
5860 }
5861
5862 /* use prefetched values */
5863 rx_desc = next_rxd;
9d5c8243
AK		 5864 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5865 }
bf36c1a0 5866
9d5c8243 5867 rx_ring->next_to_clean = i;
12dcd86b 5868 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 5869 rx_ring->rx_stats.packets += total_packets;
5870 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 5871 u64_stats_update_end(&rx_ring->rx_syncp);
c023cd88
AD		 5872 rx_ring->total_packets += total_packets;
5873 rx_ring->total_bytes += total_bytes;
5874
5875 if (cleaned_count)
cd392f5c 5876 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 5877
16eb8815 5878 return !!budget;
9d5c8243
AK		 5879}
5880
c023cd88
AD		 5881static bool igb_alloc_mapped_skb(struct igb_ring *rx_ring,
5882 struct igb_buffer *bi)
5883{
5884 struct sk_buff *skb = bi->skb;
5885 dma_addr_t dma = bi->dma;
5886
5887 if (dma)
5888 return true;
5889
5890 if (likely(!skb)) {
5891 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5892 IGB_RX_HDR_LEN);
5893 bi->skb = skb;
5894 if (!skb) {
5895 rx_ring->rx_stats.alloc_failed++;
5896 return false;
5897 }
5898
5899 /* initialize skb for ring */
5900 skb_record_rx_queue(skb, rx_ring->queue_index);
5901 }
5902
5903 dma = dma_map_single(rx_ring->dev, skb->data,
5904 IGB_RX_HDR_LEN, DMA_FROM_DEVICE);
5905
5906 if (dma_mapping_error(rx_ring->dev, dma)) {
5907 rx_ring->rx_stats.alloc_failed++;
5908 return false;
5909 }
5910
5911 bi->dma = dma;
5912 return true;
5913}
5914
5915static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
5916 struct igb_buffer *bi)
5917{
5918 struct page *page = bi->page;
5919 dma_addr_t page_dma = bi->page_dma;
5920 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
5921
5922 if (page_dma)
5923 return true;
5924
5925 if (!page) {
5926 page = netdev_alloc_page(rx_ring->netdev);
5927 bi->page = page;
5928 if (unlikely(!page)) {
5929 rx_ring->rx_stats.alloc_failed++;
5930 return false;
5931 }
5932 }
5933
5934 page_dma = dma_map_page(rx_ring->dev, page,
5935 page_offset, PAGE_SIZE / 2,
5936 DMA_FROM_DEVICE);
5937
5938 if (dma_mapping_error(rx_ring->dev, page_dma)) {
5939 rx_ring->rx_stats.alloc_failed++;
5940 return false;
5941 }
5942
5943 bi->page_dma = page_dma;
5944 bi->page_offset = page_offset;
5945 return true;
5946}
5947
9d5c8243 5948/**
cd392f5c 5949 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 5950 * @adapter: address of board private structure
5951 **/
cd392f5c 5952void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 5953{
9d5c8243 5954 union e1000_adv_rx_desc *rx_desc;
c023cd88
AD		 5955 struct igb_buffer *bi;
5956 u16 i = rx_ring->next_to_use;
9d5c8243 5957
c023cd88
AD		 5958 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5959 bi = &rx_ring->buffer_info[i];
5960 i -= rx_ring->count;
9d5c8243
AK		 5961
5962 while (cleaned_count--) {
c023cd88
AD		 5963 if (!igb_alloc_mapped_skb(rx_ring, bi))
5964 break;
9d5c8243 5965
c023cd88
AD		 5966 /* Refresh the desc even if buffer_addrs didn't change
5967 * because each write-back erases this info. */
5968 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9d5c8243 5969
c023cd88
AD		 5970 if (!igb_alloc_mapped_page(rx_ring, bi))
5971 break;
5972
5973 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
9d5c8243 5974
c023cd88
AD		 5975 rx_desc++;
5976 bi++;
9d5c8243 5977 i++;
c023cd88
AD		 5978 if (unlikely(!i)) {
5979 rx_desc = E1000_RX_DESC_ADV(*rx_ring, 0);
5980 bi = rx_ring->buffer_info;
5981 i -= rx_ring->count;
5982 }
5983
5984 /* clear the hdr_addr for the next_to_use descriptor */
5985 rx_desc->read.hdr_addr = 0;
9d5c8243
AK		 5986 }
5987
c023cd88
AD		 5988 i += rx_ring->count;
5989
9d5c8243
AK		 5990 if (rx_ring->next_to_use != i) {
5991 rx_ring->next_to_use = i;
9d5c8243
AK		 5992
5993 /* Force memory writes to complete before letting h/w
5994 * know there are new descriptors to fetch. (Only
5995 * applicable for weak-ordered memory model archs,
5996 * such as IA-64). */
5997 wmb();
fce99e34 5998 writel(i, rx_ring->tail);
9d5c8243
AK		 5999 }
6000}
6001
6002/**
6003 * igb_mii_ioctl -
6004 * @netdev:
6005 * @ifreq:
6006 * @cmd:
6007 **/
6008static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6009{
6010 struct igb_adapter *adapter = netdev_priv(netdev);
6011 struct mii_ioctl_data *data = if_mii(ifr);
6012
6013 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6014 return -EOPNOTSUPP;
6015
6016 switch (cmd) {
6017 case SIOCGMIIPHY:
6018 data->phy_id = adapter->hw.phy.addr;
6019 break;
6020 case SIOCGMIIREG:
f5f4cf08
AD		 6021 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6022 &data->val_out))
9d5c8243
AK		 6023 return -EIO;
6024 break;
6025 case SIOCSMIIREG:
6026 default:
6027 return -EOPNOTSUPP;
6028 }
6029 return 0;
6030}
6031
c6cb090b
PO		 6032/**
6033 * igb_hwtstamp_ioctl - control hardware time stamping
6034 * @netdev:
6035 * @ifreq:
6036 * @cmd:
6037 *
33af6bcc
PO		 6038 * Outgoing time stamping can be enabled and disabled. Play nice and
6039 * disable it when requested, although it shouldn't case any overhead
6040 * when no packet needs it. At most one packet in the queue may be
6041 * marked for time stamping, otherwise it would be impossible to tell
6042 * for sure to which packet the hardware time stamp belongs.
6043 *
6044 * Incoming time stamping has to be configured via the hardware
6045 * filters. Not all combinations are supported, in particular event
6046 * type has to be specified. Matching the kind of event packet is
6047 * not supported, with the exception of "all V2 events regardless of
6048 * level 2 or 4".
6049 *
c6cb090b
PO		 6050 **/
6051static int igb_hwtstamp_ioctl(struct net_device *netdev,
6052 struct ifreq *ifr, int cmd)
6053{
33af6bcc
PO		 6054 struct igb_adapter *adapter = netdev_priv(netdev);
6055 struct e1000_hw *hw = &adapter->hw;
c6cb090b 6056 struct hwtstamp_config config;
c5b9bd5e
AD		 6057 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
6058 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 6059 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 6060 bool is_l4 = false;
6061 bool is_l2 = false;
33af6bcc 6062 u32 regval;
c6cb090b
PO		 6063
6064 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6065 return -EFAULT;
6066
6067 /* reserved for future extensions */
6068 if (config.flags)
6069 return -EINVAL;
6070
33af6bcc
PO		 6071 switch (config.tx_type) {
6072 case HWTSTAMP_TX_OFF:
c5b9bd5e 6073 tsync_tx_ctl = 0;
33af6bcc 6074 case HWTSTAMP_TX_ON:
33af6bcc
PO		 6075 break;
6076 default:
6077 return -ERANGE;
6078 }
6079
6080 switch (config.rx_filter) {
6081 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 6082 tsync_rx_ctl = 0;
33af6bcc
PO		 6083 break;
6084 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6085 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6086 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6087 case HWTSTAMP_FILTER_ALL:
6088 /*
6089 * register TSYNCRXCFG must be set, therefore it is not
6090 * possible to time stamp both Sync and Delay_Req messages
6091 * => fall back to time stamping all packets
6092 */
c5b9bd5e 6093 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 6094 config.rx_filter = HWTSTAMP_FILTER_ALL;
6095 break;
6096 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 6097 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6098 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 6099 is_l4 = true;
33af6bcc
PO		 6100 break;
6101 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 6102 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6103 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 6104 is_l4 = true;
33af6bcc
PO		 6105 break;
6106 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6107 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 6108 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6109 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 6110 is_l2 = true;
6111 is_l4 = true;
33af6bcc
PO		 6112 config.rx_filter = HWTSTAMP_FILTER_SOME;
6113 break;
6114 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6115 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 6116 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6117 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 6118 is_l2 = true;
6119 is_l4 = true;
33af6bcc
PO		 6120 config.rx_filter = HWTSTAMP_FILTER_SOME;
6121 break;
6122 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6123 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6124 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 6125 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 6126 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 6127 is_l2 = true;
33af6bcc
PO		 6128 break;
6129 default:
6130 return -ERANGE;
6131 }
6132
c5b9bd5e
AD		 6133 if (hw->mac.type == e1000_82575) {
6134 if (tsync_rx_ctl | tsync_tx_ctl)
6135 return -EINVAL;
6136 return 0;
6137 }
6138
757b77e2
NN		 6139 /*
6140 * Per-packet timestamping only works if all packets are
6141 * timestamped, so enable timestamping in all packets as
6142 * long as one rx filter was configured.
6143 */
6144 if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
6145 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6146 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6147 }
6148
33af6bcc
PO		 6149 /* enable/disable TX */
6150 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 6151 regval &= ~E1000_TSYNCTXCTL_ENABLED;
6152 regval |= tsync_tx_ctl;
33af6bcc
PO		 6153 wr32(E1000_TSYNCTXCTL, regval);
6154
c5b9bd5e 6155 /* enable/disable RX */
33af6bcc 6156 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 6157 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
6158 regval |= tsync_rx_ctl;
33af6bcc 6159 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 6160
c5b9bd5e
AD		 6161 /* define which PTP packets are time stamped */
6162 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 6163
c5b9bd5e
AD		 6164 /* define ethertype filter for timestamped packets */
6165 if (is_l2)
6166 wr32(E1000_ETQF(3),
6167 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
6168 E1000_ETQF_1588 | /* enable timestamping */
6169 ETH_P_1588)); /* 1588 eth protocol type */
6170 else
6171 wr32(E1000_ETQF(3), 0);
6172
6173#define PTP_PORT 319
6174 /* L4 Queue Filter[3]: filter by destination port and protocol */
6175 if (is_l4) {
6176 u32 ftqf = (IPPROTO_UDP /* UDP */
6177 | E1000_FTQF_VF_BP /* VF not compared */
6178 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
6179 | E1000_FTQF_MASK); /* mask all inputs */
6180 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
6181
6182 wr32(E1000_IMIR(3), htons(PTP_PORT));
6183 wr32(E1000_IMIREXT(3),
6184 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
6185 if (hw->mac.type == e1000_82576) {
6186 /* enable source port check */
6187 wr32(E1000_SPQF(3), htons(PTP_PORT));
6188 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
6189 }
6190 wr32(E1000_FTQF(3), ftqf);
6191 } else {
6192 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
6193 }
33af6bcc
PO		 6194 wrfl();
6195
6196 adapter->hwtstamp_config = config;
6197
6198 /* clear TX/RX time stamp registers, just to be sure */
6199 regval = rd32(E1000_TXSTMPH);
6200 regval = rd32(E1000_RXSTMPH);
c6cb090b 6201
33af6bcc
PO		 6202 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
6203 -EFAULT : 0;
c6cb090b
PO		 6204}
6205
9d5c8243
AK		 6206/**
6207 * igb_ioctl -
6208 * @netdev:
6209 * @ifreq:
6210 * @cmd:
6211 **/
6212static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6213{
6214 switch (cmd) {
6215 case SIOCGMIIPHY:
6216 case SIOCGMIIREG:
6217 case SIOCSMIIREG:
6218 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 6219 case SIOCSHWTSTAMP:
6220 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6221 default:
6222 return -EOPNOTSUPP;
6223 }
6224}
6225
009bc06e
AD		 6226s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6227{
6228 struct igb_adapter *adapter = hw->back;
6229 u16 cap_offset;
6230
bdaae04c 6231 cap_offset = adapter->pdev->pcie_cap;
009bc06e
AD		 6232 if (!cap_offset)
6233 return -E1000_ERR_CONFIG;
6234
6235 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6236
6237 return 0;
6238}
6239
6240s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6241{
6242 struct igb_adapter *adapter = hw->back;
6243 u16 cap_offset;
6244
bdaae04c 6245 cap_offset = adapter->pdev->pcie_cap;
009bc06e
AD		 6246 if (!cap_offset)
6247 return -E1000_ERR_CONFIG;
6248
6249 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6250
6251 return 0;
6252}
6253
b2cb09b1 6254static void igb_vlan_mode(struct net_device *netdev, u32 features)
9d5c8243
AK		 6255{
6256 struct igb_adapter *adapter = netdev_priv(netdev);
6257 struct e1000_hw *hw = &adapter->hw;
6258 u32 ctrl, rctl;
6259
6260 igb_irq_disable(adapter);
9d5c8243 6261
b2cb09b1 6262 if (features & NETIF_F_HW_VLAN_RX) {
9d5c8243
AK		 6263 /* enable VLAN tag insert/strip */
6264 ctrl = rd32(E1000_CTRL);
6265 ctrl |= E1000_CTRL_VME;
6266 wr32(E1000_CTRL, ctrl);
6267
51466239 6268 /* Disable CFI check */
9d5c8243 6269 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6270 rctl &= ~E1000_RCTL_CFIEN;
6271 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6272 } else {
6273 /* disable VLAN tag insert/strip */
6274 ctrl = rd32(E1000_CTRL);
6275 ctrl &= ~E1000_CTRL_VME;
6276 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6277 }
6278
e1739522
AD		 6279 igb_rlpml_set(adapter);
6280
9d5c8243
AK		 6281 if (!test_bit(__IGB_DOWN, &adapter->state))
6282 igb_irq_enable(adapter);
6283}
6284
6285static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6286{
6287 struct igb_adapter *adapter = netdev_priv(netdev);
6288 struct e1000_hw *hw = &adapter->hw;
4ae196df 6289 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6290
51466239
AD		 6291 /* attempt to add filter to vlvf array */
6292 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6293
51466239
AD		 6294 /* add the filter since PF can receive vlans w/o entry in vlvf */
6295 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6296
6297 set_bit(vid, adapter->active_vlans);
9d5c8243
AK		 6298}
6299
6300static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6301{
6302 struct igb_adapter *adapter = netdev_priv(netdev);
6303 struct e1000_hw *hw = &adapter->hw;
4ae196df 6304 int pf_id = adapter->vfs_allocated_count;
51466239 6305 s32 err;
9d5c8243
AK		 6306
6307 igb_irq_disable(adapter);
9d5c8243
AK		 6308
6309 if (!test_bit(__IGB_DOWN, &adapter->state))
6310 igb_irq_enable(adapter);
6311
51466239
AD		 6312 /* remove vlan from VLVF table array */
6313 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6314
51466239
AD		 6315 /* if vid was not present in VLVF just remove it from table */
6316 if (err)
4ae196df 6317 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6318
6319 clear_bit(vid, adapter->active_vlans);
9d5c8243
AK		 6320}
6321
6322static void igb_restore_vlan(struct igb_adapter *adapter)
6323{
b2cb09b1 6324 u16 vid;
9d5c8243 6325
b2cb09b1
JP		 6326 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6327 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6328}
6329
14ad2513 6330int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6331{
090b1795 6332 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6333 struct e1000_mac_info *mac = &adapter->hw.mac;
6334
6335 mac->autoneg = 0;
6336
14ad2513
DD		 6337 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6338 * for the switch() below to work */
6339 if ((spd & 1) || (dplx & ~1))
6340 goto err_inval;
6341
cd2638a8
CW		 6342 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6343 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6344 spd != SPEED_1000 &&
6345 dplx != DUPLEX_FULL)
6346 goto err_inval;
cd2638a8 6347
14ad2513 6348 switch (spd + dplx) {
9d5c8243
AK		 6349 case SPEED_10 + DUPLEX_HALF:
6350 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6351 break;
6352 case SPEED_10 + DUPLEX_FULL:
6353 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6354 break;
6355 case SPEED_100 + DUPLEX_HALF:
6356 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6357 break;
6358 case SPEED_100 + DUPLEX_FULL:
6359 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6360 break;
6361 case SPEED_1000 + DUPLEX_FULL:
6362 mac->autoneg = 1;
6363 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6364 break;
6365 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6366 default:
14ad2513 6367 goto err_inval;
9d5c8243
AK		 6368 }
6369 return 0;
14ad2513
DD		 6370
6371err_inval:
6372 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6373 return -EINVAL;
9d5c8243
AK		 6374}
6375
3fe7c4c9 6376static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 6377{
6378 struct net_device *netdev = pci_get_drvdata(pdev);
6379 struct igb_adapter *adapter = netdev_priv(netdev);
6380 struct e1000_hw *hw = &adapter->hw;
2d064c06 6381 u32 ctrl, rctl, status;
9d5c8243
AK		 6382 u32 wufc = adapter->wol;
6383#ifdef CONFIG_PM
6384 int retval = 0;
6385#endif
6386
6387 netif_device_detach(netdev);
6388
a88f10ec
AD		 6389 if (netif_running(netdev))
6390 igb_close(netdev);
6391
047e0030 6392 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6393
6394#ifdef CONFIG_PM
6395 retval = pci_save_state(pdev);
6396 if (retval)
6397 return retval;
6398#endif
6399
6400 status = rd32(E1000_STATUS);
6401 if (status & E1000_STATUS_LU)
6402 wufc &= ~E1000_WUFC_LNKC;
6403
6404 if (wufc) {
6405 igb_setup_rctl(adapter);
ff41f8dc 6406 igb_set_rx_mode(netdev);
9d5c8243
AK		 6407
6408 /* turn on all-multi mode if wake on multicast is enabled */
6409 if (wufc & E1000_WUFC_MC) {
6410 rctl = rd32(E1000_RCTL);
6411 rctl |= E1000_RCTL_MPE;
6412 wr32(E1000_RCTL, rctl);
6413 }
6414
6415 ctrl = rd32(E1000_CTRL);
6416 /* advertise wake from D3Cold */
6417 #define E1000_CTRL_ADVD3WUC 0x00100000
6418 /* phy power management enable */
6419 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6420 ctrl |= E1000_CTRL_ADVD3WUC;
6421 wr32(E1000_CTRL, ctrl);
6422
9d5c8243 6423 /* Allow time for pending master requests to run */
330a6d6a 6424 igb_disable_pcie_master(hw);
9d5c8243
AK		 6425
6426 wr32(E1000_WUC, E1000_WUC_PME_EN);
6427 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6428 } else {
6429 wr32(E1000_WUC, 0);
6430 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6431 }
6432
3fe7c4c9
RW		 6433 *enable_wake = wufc || adapter->en_mng_pt;
6434 if (!*enable_wake)
88a268c1
NN		 6435 igb_power_down_link(adapter);
6436 else
6437 igb_power_up_link(adapter);
9d5c8243
AK		 6438
6439 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6440 * would have already happened in close and is redundant. */
6441 igb_release_hw_control(adapter);
6442
6443 pci_disable_device(pdev);
6444
9d5c8243
AK		 6445 return 0;
6446}
6447
6448#ifdef CONFIG_PM
3fe7c4c9
RW		 6449static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6450{
6451 int retval;
6452 bool wake;
6453
6454 retval = __igb_shutdown(pdev, &wake);
6455 if (retval)
6456 return retval;
6457
6458 if (wake) {
6459 pci_prepare_to_sleep(pdev);
6460 } else {
6461 pci_wake_from_d3(pdev, false);
6462 pci_set_power_state(pdev, PCI_D3hot);
6463 }
6464
6465 return 0;
6466}
6467
9d5c8243
AK		 6468static int igb_resume(struct pci_dev *pdev)
6469{
6470 struct net_device *netdev = pci_get_drvdata(pdev);
6471 struct igb_adapter *adapter = netdev_priv(netdev);
6472 struct e1000_hw *hw = &adapter->hw;
6473 u32 err;
6474
6475 pci_set_power_state(pdev, PCI_D0);
6476 pci_restore_state(pdev);
b94f2d77 6477 pci_save_state(pdev);
42bfd33a 6478
aed5dec3 6479 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6480 if (err) {
6481 dev_err(&pdev->dev,
6482 "igb: Cannot enable PCI device from suspend\n");
6483 return err;
6484 }
6485 pci_set_master(pdev);
6486
6487 pci_enable_wake(pdev, PCI_D3hot, 0);
6488 pci_enable_wake(pdev, PCI_D3cold, 0);
6489
047e0030 6490 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6491 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6492 return -ENOMEM;
9d5c8243
AK		 6493 }
6494
9d5c8243 6495 igb_reset(adapter);
a8564f03
AD		 6496
6497 /* let the f/w know that the h/w is now under the control of the
6498 * driver. */
6499 igb_get_hw_control(adapter);
6500
9d5c8243
AK		 6501 wr32(E1000_WUS, ~0);
6502
a88f10ec
AD		 6503 if (netif_running(netdev)) {
6504 err = igb_open(netdev);
6505 if (err)
6506 return err;
6507 }
9d5c8243
AK		 6508
6509 netif_device_attach(netdev);
6510
9d5c8243
AK		 6511 return 0;
6512}
6513#endif
6514
6515static void igb_shutdown(struct pci_dev *pdev)
6516{
3fe7c4c9
RW		 6517 bool wake;
6518
6519 __igb_shutdown(pdev, &wake);
6520
6521 if (system_state == SYSTEM_POWER_OFF) {
6522 pci_wake_from_d3(pdev, wake);
6523 pci_set_power_state(pdev, PCI_D3hot);
6524 }
9d5c8243
AK		 6525}
6526
6527#ifdef CONFIG_NET_POLL_CONTROLLER
6528/*
6529 * Polling 'interrupt' - used by things like netconsole to send skbs
6530 * without having to re-enable interrupts. It's not called while
6531 * the interrupt routine is executing.
6532 */
6533static void igb_netpoll(struct net_device *netdev)
6534{
6535 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6536 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6537 int i;
9d5c8243 6538
eebbbdba 6539 if (!adapter->msix_entries) {
047e0030 6540 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 6541 igb_irq_disable(adapter);
047e0030 6542 napi_schedule(&q_vector->napi);
eebbbdba
AD		 6543 return;
6544 }
9d5c8243 6545
047e0030
AD		 6546 for (i = 0; i < adapter->num_q_vectors; i++) {
6547 struct igb_q_vector *q_vector = adapter->q_vector[i];
6548 wr32(E1000_EIMC, q_vector->eims_value);
6549 napi_schedule(&q_vector->napi);
eebbbdba 6550 }
9d5c8243
AK		 6551}
6552#endif /* CONFIG_NET_POLL_CONTROLLER */
6553
6554/**
6555 * igb_io_error_detected - called when PCI error is detected
6556 * @pdev: Pointer to PCI device
6557 * @state: The current pci connection state
6558 *
6559 * This function is called after a PCI bus error affecting
6560 * this device has been detected.
6561 */
6562static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6563 pci_channel_state_t state)
6564{
6565 struct net_device *netdev = pci_get_drvdata(pdev);
6566 struct igb_adapter *adapter = netdev_priv(netdev);
6567
6568 netif_device_detach(netdev);
6569
59ed6eec
AD		 6570 if (state == pci_channel_io_perm_failure)
6571 return PCI_ERS_RESULT_DISCONNECT;
6572
9d5c8243
AK		 6573 if (netif_running(netdev))
6574 igb_down(adapter);
6575 pci_disable_device(pdev);
6576
6577 /* Request a slot slot reset. */
6578 return PCI_ERS_RESULT_NEED_RESET;
6579}
6580
6581/**
6582 * igb_io_slot_reset - called after the pci bus has been reset.
6583 * @pdev: Pointer to PCI device
6584 *
6585 * Restart the card from scratch, as if from a cold-boot. Implementation
6586 * resembles the first-half of the igb_resume routine.
6587 */
6588static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6589{
6590 struct net_device *netdev = pci_get_drvdata(pdev);
6591 struct igb_adapter *adapter = netdev_priv(netdev);
6592 struct e1000_hw *hw = &adapter->hw;
40a914fa 6593 pci_ers_result_t result;
42bfd33a 6594 int err;
9d5c8243 6595
aed5dec3 6596 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6597 dev_err(&pdev->dev,
6598 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6599 result = PCI_ERS_RESULT_DISCONNECT;
6600 } else {
6601 pci_set_master(pdev);
6602 pci_restore_state(pdev);
b94f2d77 6603 pci_save_state(pdev);
9d5c8243 6604
40a914fa
AD		 6605 pci_enable_wake(pdev, PCI_D3hot, 0);
6606 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6607
40a914fa
AD		 6608 igb_reset(adapter);
6609 wr32(E1000_WUS, ~0);
6610 result = PCI_ERS_RESULT_RECOVERED;
6611 }
9d5c8243 6612
ea943d41
JK		 6613 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6614 if (err) {
6615 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6616 "failed 0x%0x\n", err);
6617 /* non-fatal, continue */
6618 }
40a914fa
AD		 6619
6620 return result;
9d5c8243
AK		 6621}
6622
6623/**
6624 * igb_io_resume - called when traffic can start flowing again.
6625 * @pdev: Pointer to PCI device
6626 *
6627 * This callback is called when the error recovery driver tells us that
6628 * its OK to resume normal operation. Implementation resembles the
6629 * second-half of the igb_resume routine.
6630 */
6631static void igb_io_resume(struct pci_dev *pdev)
6632{
6633 struct net_device *netdev = pci_get_drvdata(pdev);
6634 struct igb_adapter *adapter = netdev_priv(netdev);
6635
9d5c8243
AK		 6636 if (netif_running(netdev)) {
6637 if (igb_up(adapter)) {
6638 dev_err(&pdev->dev, "igb_up failed after reset\n");
6639 return;
6640 }
6641 }
6642
6643 netif_device_attach(netdev);
6644
6645 /* let the f/w know that the h/w is now under the control of the
6646 * driver. */
6647 igb_get_hw_control(adapter);
9d5c8243
AK		 6648}
6649
26ad9178
AD		 6650static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6651 u8 qsel)
6652{
6653 u32 rar_low, rar_high;
6654 struct e1000_hw *hw = &adapter->hw;
6655
6656 /* HW expects these in little endian so we reverse the byte order
6657 * from network order (big endian) to little endian
6658 */
6659 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6660 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6661 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6662
6663 /* Indicate to hardware the Address is Valid. */
6664 rar_high |= E1000_RAH_AV;
6665
6666 if (hw->mac.type == e1000_82575)
6667 rar_high |= E1000_RAH_POOL_1 * qsel;
6668 else
6669 rar_high |= E1000_RAH_POOL_1 << qsel;
6670
6671 wr32(E1000_RAL(index), rar_low);
6672 wrfl();
6673 wr32(E1000_RAH(index), rar_high);
6674 wrfl();
6675}
6676
4ae196df
AD		 6677static int igb_set_vf_mac(struct igb_adapter *adapter,
6678 int vf, unsigned char *mac_addr)
6679{
6680 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6681 /* VF MAC addresses start at end of receive addresses and moves
6682 * torwards the first, as a result a collision should not be possible */
6683 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6684
37680117 6685 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6686
26ad9178 6687 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6688
6689 return 0;
6690}
6691
8151d294
WM		 6692static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6693{
6694 struct igb_adapter *adapter = netdev_priv(netdev);
6695 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6696 return -EINVAL;
6697 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6698 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6699 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6700 " change effective.");
6701 if (test_bit(__IGB_DOWN, &adapter->state)) {
6702 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6703 " but the PF device is not up.\n");
6704 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6705 " attempting to use the VF device.\n");
6706 }
6707 return igb_set_vf_mac(adapter, vf, mac);
6708}
6709
17dc566c
LL		 6710static int igb_link_mbps(int internal_link_speed)
6711{
6712 switch (internal_link_speed) {
6713 case SPEED_100:
6714 return 100;
6715 case SPEED_1000:
6716 return 1000;
6717 default:
6718 return 0;
6719 }
6720}
6721
6722static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6723 int link_speed)
6724{
6725 int rf_dec, rf_int;
6726 u32 bcnrc_val;
6727
6728 if (tx_rate != 0) {
6729 /* Calculate the rate factor values to set */
6730 rf_int = link_speed / tx_rate;
6731 rf_dec = (link_speed - (rf_int * tx_rate));
6732 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6733
6734 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6735 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6736 E1000_RTTBCNRC_RF_INT_MASK);
6737 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6738 } else {
6739 bcnrc_val = 0;
6740 }
6741
6742 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
6743 wr32(E1000_RTTBCNRC, bcnrc_val);
6744}
6745
6746static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
6747{
6748 int actual_link_speed, i;
6749 bool reset_rate = false;
6750
6751 /* VF TX rate limit was not set or not supported */
6752 if ((adapter->vf_rate_link_speed == 0) ||
6753 (adapter->hw.mac.type != e1000_82576))
6754 return;
6755
6756 actual_link_speed = igb_link_mbps(adapter->link_speed);
6757 if (actual_link_speed != adapter->vf_rate_link_speed) {
6758 reset_rate = true;
6759 adapter->vf_rate_link_speed = 0;
6760 dev_info(&adapter->pdev->dev,
6761 "Link speed has been changed. VF Transmit "
6762 "rate is disabled\n");
6763 }
6764
6765 for (i = 0; i < adapter->vfs_allocated_count; i++) {
6766 if (reset_rate)
6767 adapter->vf_data[i].tx_rate = 0;
6768
6769 igb_set_vf_rate_limit(&adapter->hw, i,
6770 adapter->vf_data[i].tx_rate,
6771 actual_link_speed);
6772 }
6773}
6774
8151d294
WM		 6775static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6776{
17dc566c
LL		 6777 struct igb_adapter *adapter = netdev_priv(netdev);
6778 struct e1000_hw *hw = &adapter->hw;
6779 int actual_link_speed;
6780
6781 if (hw->mac.type != e1000_82576)
6782 return -EOPNOTSUPP;
6783
6784 actual_link_speed = igb_link_mbps(adapter->link_speed);
6785 if ((vf >= adapter->vfs_allocated_count) ||
6786 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
6787 (tx_rate < 0) || (tx_rate > actual_link_speed))
6788 return -EINVAL;
6789
6790 adapter->vf_rate_link_speed = actual_link_speed;
6791 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
6792 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
6793
6794 return 0;
8151d294
WM		 6795}
6796
6797static int igb_ndo_get_vf_config(struct net_device *netdev,
6798 int vf, struct ifla_vf_info *ivi)
6799{
6800 struct igb_adapter *adapter = netdev_priv(netdev);
6801 if (vf >= adapter->vfs_allocated_count)
6802 return -EINVAL;
6803 ivi->vf = vf;
6804 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 6805 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 6806 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6807 ivi->qos = adapter->vf_data[vf].pf_qos;
6808 return 0;
6809}
6810
4ae196df
AD		 6811static void igb_vmm_control(struct igb_adapter *adapter)
6812{
6813 struct e1000_hw *hw = &adapter->hw;
10d8e907 6814 u32 reg;
4ae196df 6815
52a1dd4d
AD		 6816 switch (hw->mac.type) {
6817 case e1000_82575:
6818 default:
6819 /* replication is not supported for 82575 */
4ae196df 6820 return;
52a1dd4d
AD		 6821 case e1000_82576:
6822 /* notify HW that the MAC is adding vlan tags */
6823 reg = rd32(E1000_DTXCTL);
6824 reg |= E1000_DTXCTL_VLAN_ADDED;
6825 wr32(E1000_DTXCTL, reg);
6826 case e1000_82580:
6827 /* enable replication vlan tag stripping */
6828 reg = rd32(E1000_RPLOLR);
6829 reg |= E1000_RPLOLR_STRVLAN;
6830 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 6831 case e1000_i350:
6832 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 6833 break;
6834 }
10d8e907 6835
d4960307
AD		 6836 if (adapter->vfs_allocated_count) {
6837 igb_vmdq_set_loopback_pf(hw, true);
6838 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 6839 igb_vmdq_set_anti_spoofing_pf(hw, true,
6840 adapter->vfs_allocated_count);
d4960307
AD		 6841 } else {
6842 igb_vmdq_set_loopback_pf(hw, false);
6843 igb_vmdq_set_replication_pf(hw, false);
6844 }
4ae196df
AD		 6845}
6846
9d5c8243 6847/* igb_main.c */
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